1//===- AArch64.cpp --------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "InputFiles.h"
10#include "OutputSections.h"
11#include "RelocScan.h"
12#include "Symbols.h"
13#include "SyntheticSections.h"
14#include "Target.h"
15#include "TargetImpl.h"
16#include "llvm/BinaryFormat/ELF.h"
17#include "llvm/Support/Endian.h"
18
19using namespace llvm;
20using namespace llvm::support::endian;
21using namespace llvm::ELF;
22using namespace lld;
23using namespace lld::elf;
24
25// Page(Expr) is the page address of the expression Expr, defined
26// as (Expr & ~0xFFF). (This applies even if the machine page size
27// supported by the platform has a different value.)
28uint64_t elf::getAArch64Page(uint64_t expr) {
29 return expr & ~static_cast<uint64_t>(0xFFF);
30}
31
32// A BTI landing pad is a valid target for an indirect branch when the Branch
33// Target Identification has been enabled. As linker generated branches are
34// via x16 the BTI landing pads are defined as: BTI C, BTI J, BTI JC, PACIASP,
35// PACIBSP.
36bool elf::isAArch64BTILandingPad(Ctx &ctx, Symbol &s, int64_t a) {
37 // PLT entries accessed indirectly have a BTI c.
38 if (s.isInPlt(ctx))
39 return true;
40 Defined *d = dyn_cast<Defined>(Val: &s);
41 if (!isa_and_nonnull<InputSection>(Val: d->section))
42 // All places that we cannot disassemble are responsible for making
43 // the target a BTI landing pad.
44 return true;
45 InputSection *isec = cast<InputSection>(Val: d->section);
46 uint64_t off = d->value + a;
47 // Likely user error, but protect ourselves against out of bounds
48 // access.
49 if (off >= isec->getSize())
50 return true;
51 const uint8_t *buf = isec->content().begin();
52 // Synthetic sections may have a size but empty data - Assume that they won't
53 // contain a landing pad
54 if (buf == nullptr && isa<SyntheticSection>(Val: isec))
55 return false;
56
57 const uint32_t instr = read32le(P: buf + off);
58 // All BTI instructions are HINT instructions which all have same encoding
59 // apart from bits [11:5]
60 if ((instr & 0xd503201f) == 0xd503201f &&
61 is_contained(Set: {/*PACIASP*/ 0xd503233f, /*PACIBSP*/ 0xd503237f,
62 /*BTI C*/ 0xd503245f, /*BTI J*/ 0xd503249f,
63 /*BTI JC*/ 0xd50324df},
64 Element: instr))
65 return true;
66 return false;
67}
68
69namespace {
70class AArch64 : public TargetInfo {
71public:
72 AArch64(Ctx &);
73 RelExpr getRelExpr(RelType type, const Symbol &s,
74 const uint8_t *loc) const override;
75 RelType getDynRel(RelType type) const override;
76 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
77 void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
78 void writeIgotPlt(uint8_t *buf, const Symbol &s) const override;
79 void writePltHeader(uint8_t *buf) const override;
80 void writePlt(uint8_t *buf, const Symbol &sym,
81 uint64_t pltEntryAddr) const override;
82 template <class ELFT, class RelTy>
83 void scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels,
84 unsigned shard);
85 void scanSection(InputSectionBase &sec, unsigned shard) override {
86 if (ctx.arg.ekind == ELF64BEKind)
87 elf::scanSection1<AArch64, ELF64BE>(target&: *this, sec, shard);
88 else
89 elf::scanSection1<AArch64, ELF64LE>(target&: *this, sec, shard);
90 }
91 bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
92 uint64_t branchAddr, const Symbol &s,
93 int64_t a) const override;
94 uint32_t getThunkSectionSpacing() const override;
95 bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
96 bool usesOnlyLowPageBits(RelType type) const override;
97 void relocate(uint8_t *loc, const Relocation &rel,
98 uint64_t val) const override;
99 void relocateAlloc(InputSection &sec, uint8_t *buf) const override;
100 void applyBranchToBranchOpt() const override;
101
102private:
103 void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
104 void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
105 void relaxTlsIeToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
106};
107
108struct AArch64Relaxer {
109 Ctx &ctx;
110 SmallPtrSet<Symbol *, 32> unsafeToRelaxAdrpLdr;
111
112 AArch64Relaxer(Ctx &ctx, ArrayRef<Relocation> relocs, uint64_t secAddr,
113 uint8_t *buf);
114 bool tryRelaxAdrpAdd(const Relocation &adrpRel, const Relocation &addRel,
115 uint64_t secAddr, uint8_t *buf) const;
116 bool tryRelaxAdrpLdr(const Relocation &adrpRel, const Relocation &ldrRel,
117 uint64_t secAddr, uint8_t *buf) const;
118 bool isLegalAdrpLdrRelaxationCandidate(const Relocation &adrpRel,
119 const Relocation &ldrRel,
120 uint64_t secAddr, uint8_t *buf) const;
121};
122} // namespace
123
124// Return the bits [Start, End] from Val shifted Start bits.
125// For instance, getBits(0xF0, 4, 8) returns 0xF.
126static uint64_t getBits(uint64_t val, int start, int end) {
127 uint64_t mask = ((uint64_t)1 << (end + 1 - start)) - 1;
128 return (val >> start) & mask;
129}
130
131AArch64::AArch64(Ctx &ctx) : TargetInfo(ctx) {
132 copyRel = R_AARCH64_COPY;
133 relativeRel = R_AARCH64_RELATIVE;
134 iRelativeRel = R_AARCH64_IRELATIVE;
135 iRelSymbolicRel = R_AARCH64_FUNCINIT64;
136 gotRel = R_AARCH64_GLOB_DAT;
137 pltRel = R_AARCH64_JUMP_SLOT;
138 symbolicRel = R_AARCH64_ABS64;
139 tlsDescRel = R_AARCH64_TLSDESC;
140 tlsGotRel = R_AARCH64_TLS_TPREL64;
141 pltHeaderSize = 32;
142 pltEntrySize = 16;
143 ipltEntrySize = 16;
144 defaultMaxPageSize = 65536;
145
146 // Align to the 2 MiB page size (known as a superpage or huge page).
147 // FreeBSD automatically promotes 2 MiB-aligned allocations.
148 defaultImageBase = 0x200000;
149
150 needsThunks = true;
151}
152
153// Only needed to support relocations used by relocateNonAlloc and
154// preprocessRelocs.
155RelExpr AArch64::getRelExpr(RelType type, const Symbol &s,
156 const uint8_t *loc) const {
157 switch (type) {
158 case R_AARCH64_ABS32:
159 case R_AARCH64_ABS64:
160 return R_ABS;
161 case R_AARCH64_PREL32:
162 case R_AARCH64_PREL64:
163 return R_PC;
164 case R_AARCH64_TLS_DTPREL64:
165 return R_DTPREL;
166 case R_AARCH64_NONE:
167 return R_NONE;
168 default:
169 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v
170 << ") against symbol " << &s;
171 return R_NONE;
172 }
173}
174
175bool AArch64::usesOnlyLowPageBits(RelType type) const {
176 switch (type) {
177 default:
178 return false;
179 case R_AARCH64_ADD_ABS_LO12_NC:
180 case R_AARCH64_LD64_GOT_LO12_NC:
181 case R_AARCH64_AUTH_LD64_GOT_LO12_NC:
182 case R_AARCH64_AUTH_GOT_ADD_LO12_NC:
183 case R_AARCH64_LDST128_ABS_LO12_NC:
184 case R_AARCH64_LDST16_ABS_LO12_NC:
185 case R_AARCH64_LDST32_ABS_LO12_NC:
186 case R_AARCH64_LDST64_ABS_LO12_NC:
187 case R_AARCH64_LDST8_ABS_LO12_NC:
188 case R_AARCH64_TLSDESC_ADD_LO12:
189 case R_AARCH64_TLSDESC_LD64_LO12:
190 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
191 return true;
192 }
193}
194
195template <class ELFT, class RelTy>
196void AArch64::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels,
197 unsigned shard) {
198 RelocScan rs(ctx, &sec, shard);
199 sec.relocations.reserve(N: rels.size());
200
201 for (auto it = rels.begin(); it != rels.end(); ++it) {
202 const RelTy &rel = *it;
203 uint32_t symIdx = rel.getSymbol(false);
204 Symbol &sym = sec.getFile<ELFT>()->getSymbol(symIdx);
205 uint64_t offset = rel.r_offset;
206 RelType type = rel.getType(false);
207 if (sym.isUndefined() && symIdx != 0 &&
208 rs.maybeReportUndefined(sym&: cast<Undefined>(Val&: sym), offset))
209 continue;
210 int64_t addend = rs.getAddend<ELFT>(rel, type);
211 RelExpr expr;
212 // Relocation types that only need a RelExpr set `expr` and break out of
213 // the switch to reach rs.process(). Types that need special handling
214 // (fast-path helpers, TLS) call a handler and use `continue`.
215 switch (type) {
216 case R_AARCH64_NONE:
217 continue;
218
219 // Absolute relocations:
220 case R_AARCH64_ABS16:
221 case R_AARCH64_ABS32:
222 case R_AARCH64_ABS64:
223 case R_AARCH64_FUNCINIT64:
224 case R_AARCH64_ADD_ABS_LO12_NC:
225 case R_AARCH64_LDST128_ABS_LO12_NC:
226 case R_AARCH64_LDST16_ABS_LO12_NC:
227 case R_AARCH64_LDST32_ABS_LO12_NC:
228 case R_AARCH64_LDST64_ABS_LO12_NC:
229 case R_AARCH64_LDST8_ABS_LO12_NC:
230 case R_AARCH64_MOVW_SABS_G0:
231 case R_AARCH64_MOVW_SABS_G1:
232 case R_AARCH64_MOVW_SABS_G2:
233 case R_AARCH64_MOVW_UABS_G0:
234 case R_AARCH64_MOVW_UABS_G0_NC:
235 case R_AARCH64_MOVW_UABS_G1:
236 case R_AARCH64_MOVW_UABS_G1_NC:
237 case R_AARCH64_MOVW_UABS_G2:
238 case R_AARCH64_MOVW_UABS_G2_NC:
239 case R_AARCH64_MOVW_UABS_G3:
240 expr = R_ABS;
241 break;
242
243 case R_AARCH64_AUTH_ABS64:
244 expr = RE_AARCH64_AUTH;
245 break;
246
247 case R_AARCH64_PATCHINST:
248 if (!isAbsolute(sym))
249 Err(ctx) << getErrorLoc(ctx, loc: sec.content().data() + offset)
250 << "R_AARCH64_PATCHINST relocation against non-absolute "
251 "symbol "
252 << &sym;
253 expr = R_ABS;
254 break;
255
256 // PC-relative relocations:
257 case R_AARCH64_PREL16:
258 case R_AARCH64_PREL32:
259 case R_AARCH64_PREL64:
260 case R_AARCH64_ADR_PREL_LO21:
261 case R_AARCH64_LD_PREL_LO19:
262 case R_AARCH64_MOVW_PREL_G0:
263 case R_AARCH64_MOVW_PREL_G0_NC:
264 case R_AARCH64_MOVW_PREL_G1:
265 case R_AARCH64_MOVW_PREL_G1_NC:
266 case R_AARCH64_MOVW_PREL_G2:
267 case R_AARCH64_MOVW_PREL_G2_NC:
268 case R_AARCH64_MOVW_PREL_G3:
269 rs.processR_PC(type, offset, addend, sym);
270 continue;
271
272 // Page-PC relocations:
273 case R_AARCH64_ADR_PREL_PG_HI21:
274 case R_AARCH64_ADR_PREL_PG_HI21_NC:
275 expr = RE_AARCH64_PAGE_PC;
276 break;
277
278 // PLT-generating relocations:
279 case R_AARCH64_PLT32:
280 sym.thunkAccessed = true;
281 [[fallthrough]];
282 case R_AARCH64_CALL26:
283 case R_AARCH64_CONDBR19:
284 case R_AARCH64_JUMP26:
285 case R_AARCH64_TSTBR14:
286 rs.processR_PLT_PC(type, offset, addend, sym);
287 continue;
288
289 // GOT relocations:
290 case R_AARCH64_ADR_GOT_PAGE:
291 expr = RE_AARCH64_GOT_PAGE_PC;
292 break;
293 case R_AARCH64_LD64_GOT_LO12_NC:
294 expr = R_GOT;
295 break;
296 case R_AARCH64_LD64_GOTPAGE_LO15:
297 expr = RE_AARCH64_GOT_PAGE;
298 break;
299 case R_AARCH64_GOTPCREL32:
300 case R_AARCH64_GOT_LD_PREL19:
301 expr = R_GOT_PC;
302 break;
303
304 // AUTH GOT relocations. Handle flags here, as rs.process assumes R_GOT is a
305 // normal non-AUTH GOT entry.
306 case R_AARCH64_AUTH_LD64_GOT_LO12_NC:
307 case R_AARCH64_AUTH_GOT_ADD_LO12_NC:
308 sym.setFlags(NEEDS_GOT_AUTH);
309 rs.processAux(expr: R_GOT, type, offset, sym, addend);
310 continue;
311 case R_AARCH64_AUTH_GOT_LD_PREL19:
312 case R_AARCH64_AUTH_GOT_ADR_PREL_LO21:
313 sym.setFlags(NEEDS_GOT_AUTH);
314 rs.processAux(expr: R_GOT_PC, type, offset, sym, addend);
315 continue;
316 case R_AARCH64_AUTH_ADR_GOT_PAGE:
317 sym.setFlags(NEEDS_GOT_AUTH);
318 rs.processAux(expr: RE_AARCH64_GOT_PAGE_PC, type, offset, sym, addend);
319 continue;
320
321 // TLS LE relocations:
322 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
323 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
324 case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
325 case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
326 case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
327 case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
328 case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
329 case R_AARCH64_TLSLE_MOVW_TPREL_G0:
330 case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
331 case R_AARCH64_TLSLE_MOVW_TPREL_G1:
332 case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
333 case R_AARCH64_TLSLE_MOVW_TPREL_G2:
334 if (rs.checkTlsLe(offset, sym, type))
335 continue;
336 expr = R_TPREL;
337 break;
338
339 // TLS IE relocations:
340 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
341 rs.handleTlsIe(ieExpr: RE_AARCH64_GOT_PAGE_PC, type, offset, addend, sym);
342 continue;
343 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
344 rs.handleTlsIe(ieExpr: R_GOT, type, offset, addend, sym);
345 continue;
346
347 // TLSDESC relocations:
348 case R_AARCH64_TLSDESC_ADR_PAGE21:
349 rs.handleTlsDesc(sharedExpr: RE_AARCH64_TLSDESC_PAGE, ieExpr: RE_AARCH64_GOT_PAGE_PC, type,
350 offset, addend, sym);
351 continue;
352 case R_AARCH64_TLSDESC_LD64_LO12:
353 case R_AARCH64_TLSDESC_ADD_LO12:
354 rs.handleTlsDesc(sharedExpr: R_TLSDESC, ieExpr: R_GOT, type, offset, addend, sym);
355 continue;
356 case R_AARCH64_TLSDESC_CALL:
357 if (!ctx.arg.shared)
358 sec.addReloc(r: {.expr: R_TPREL, .type: type, .offset: offset, .addend: addend, .sym: &sym});
359 continue;
360
361 // AUTH TLSDESC relocations. Do not optimize to LE/IE because PAUTHELF64
362 // only supports the descriptor based TLS (TLSDESC).
363 // https://github.com/ARM-software/abi-aa/blob/main/pauthabielf64/pauthabielf64.rst#general-restrictions
364 case R_AARCH64_AUTH_TLSDESC_ADR_PAGE21:
365 sym.setFlags(NEEDS_TLSDESC_AUTH);
366 sec.addReloc(r: {.expr: RE_AARCH64_TLSDESC_PAGE, .type: type, .offset: offset, .addend: addend, .sym: &sym});
367 continue;
368 case R_AARCH64_AUTH_TLSDESC_LD64_LO12:
369 case R_AARCH64_AUTH_TLSDESC_ADD_LO12:
370 sym.setFlags(NEEDS_TLSDESC_AUTH);
371 sec.addReloc(r: {.expr: R_TLSDESC, .type: type, .offset: offset, .addend: addend, .sym: &sym});
372 continue;
373
374 default:
375 Err(ctx) << getErrorLoc(ctx, loc: sec.content().data() + offset)
376 << "unknown relocation (" << type.v << ") against symbol "
377 << &sym;
378 continue;
379 }
380 rs.process(expr, type, offset, sym, addend);
381 }
382
383 if (ctx.arg.branchToBranch)
384 llvm::stable_sort(sec.relocs(),
385 [](auto &l, auto &r) { return l.offset < r.offset; });
386}
387
388RelType AArch64::getDynRel(RelType type) const {
389 if (type == R_AARCH64_ABS64 || type == R_AARCH64_AUTH_ABS64 ||
390 type == R_AARCH64_FUNCINIT64)
391 return type;
392 return R_AARCH64_NONE;
393}
394
395int64_t AArch64::getImplicitAddend(const uint8_t *buf, RelType type) const {
396 switch (type) {
397 case R_AARCH64_TLSDESC:
398 return read64(ctx, p: buf + 8);
399 case R_AARCH64_NONE:
400 case R_AARCH64_GLOB_DAT:
401 case R_AARCH64_AUTH_GLOB_DAT:
402 case R_AARCH64_JUMP_SLOT:
403 return 0;
404 case R_AARCH64_ABS16:
405 case R_AARCH64_PREL16:
406 return SignExtend64<16>(x: read16(ctx, p: buf));
407 case R_AARCH64_ABS32:
408 case R_AARCH64_PREL32:
409 return SignExtend64<32>(x: read32(ctx, p: buf));
410 case R_AARCH64_ABS64:
411 case R_AARCH64_PREL64:
412 case R_AARCH64_RELATIVE:
413 case R_AARCH64_IRELATIVE:
414 case R_AARCH64_TLS_TPREL64:
415 return read64(ctx, p: buf);
416
417 // The following relocation types all point at instructions, and
418 // relocate an immediate field in the instruction.
419 //
420 // The general rule, from AAELF64 §5.7.2 "Addends and PC-bias",
421 // says: "If the relocation relocates an instruction the immediate
422 // field of the instruction is extracted, scaled as required by
423 // the instruction field encoding, and sign-extended to 64 bits".
424
425 // The R_AARCH64_MOVW family operates on wide MOV/MOVK/MOVZ
426 // instructions, which have a 16-bit immediate field with its low
427 // bit in bit 5 of the instruction encoding. When the immediate
428 // field is used as an implicit addend for REL-type relocations,
429 // it is treated as added to the low bits of the output value, not
430 // shifted depending on the relocation type.
431 //
432 // This allows REL relocations to express the requirement 'please
433 // add 12345 to this symbol value and give me the four 16-bit
434 // chunks of the result', by putting the same addend 12345 in all
435 // four instructions. Carries between the 16-bit chunks are
436 // handled correctly, because the whole 64-bit addition is done
437 // once per relocation.
438 case R_AARCH64_MOVW_UABS_G0:
439 case R_AARCH64_MOVW_UABS_G0_NC:
440 case R_AARCH64_MOVW_UABS_G1:
441 case R_AARCH64_MOVW_UABS_G1_NC:
442 case R_AARCH64_MOVW_UABS_G2:
443 case R_AARCH64_MOVW_UABS_G2_NC:
444 case R_AARCH64_MOVW_UABS_G3:
445 return SignExtend64<16>(x: getBits(val: read32le(P: buf), start: 5, end: 20));
446
447 // R_AARCH64_TSTBR14 points at a TBZ or TBNZ instruction, which
448 // has a 14-bit offset measured in instructions, i.e. shifted left
449 // by 2.
450 case R_AARCH64_TSTBR14:
451 return SignExtend64<16>(x: getBits(val: read32le(P: buf), start: 5, end: 18) << 2);
452
453 // R_AARCH64_CONDBR19 operates on the ordinary B.cond instruction,
454 // which has a 19-bit offset measured in instructions.
455 //
456 // R_AARCH64_LD_PREL_LO19 operates on the LDR (literal)
457 // instruction, which also has a 19-bit offset, measured in 4-byte
458 // chunks. So the calculation is the same as for
459 // R_AARCH64_CONDBR19.
460 case R_AARCH64_CONDBR19:
461 case R_AARCH64_LD_PREL_LO19:
462 return SignExtend64<21>(x: getBits(val: read32le(P: buf), start: 5, end: 23) << 2);
463
464 // R_AARCH64_ADD_ABS_LO12_NC operates on ADD (immediate). The
465 // immediate can optionally be shifted left by 12 bits, but this
466 // relocation is intended for the case where it is not.
467 case R_AARCH64_ADD_ABS_LO12_NC:
468 return SignExtend64<12>(x: getBits(val: read32le(P: buf), start: 10, end: 21));
469
470 // R_AARCH64_ADR_PREL_LO21 operates on an ADR instruction, whose
471 // 21-bit immediate is split between two bits high up in the word
472 // (in fact the two _lowest_ order bits of the value) and 19 bits
473 // lower down.
474 //
475 // R_AARCH64_ADR_PREL_PG_HI21[_NC] operate on an ADRP instruction,
476 // which encodes the immediate in the same way, but will shift it
477 // left by 12 bits when the instruction executes. For the same
478 // reason as the MOVW family, we don't apply that left shift here.
479 case R_AARCH64_ADR_PREL_LO21:
480 case R_AARCH64_ADR_PREL_PG_HI21:
481 case R_AARCH64_ADR_PREL_PG_HI21_NC:
482 return SignExtend64<21>(x: (getBits(val: read32le(P: buf), start: 5, end: 23) << 2) |
483 getBits(val: read32le(P: buf), start: 29, end: 30));
484
485 // R_AARCH64_{JUMP,CALL}26 operate on B and BL, which have a
486 // 26-bit offset measured in instructions.
487 case R_AARCH64_JUMP26:
488 case R_AARCH64_CALL26:
489 return SignExtend64<28>(x: getBits(val: read32le(P: buf), start: 0, end: 25) << 2);
490
491 default:
492 InternalErr(ctx, buf) << "cannot read addend for relocation " << type;
493 return 0;
494 }
495}
496
497void AArch64::writeGotPlt(uint8_t *buf, const Symbol &) const {
498 write64(ctx, p: buf, v: ctx.in.plt->getVA());
499}
500
501void AArch64::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
502 if (ctx.arg.writeAddends)
503 write64(ctx, p: buf, v: s.getVA(ctx));
504}
505
506void AArch64::writePltHeader(uint8_t *buf) const {
507 const uint8_t pltData[] = {
508 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]!
509 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.got.plt[2]))
510 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.got.plt[2]))]
511 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.got.plt[2]))
512 0x20, 0x02, 0x1f, 0xd6, // br x17
513 0x1f, 0x20, 0x03, 0xd5, // nop
514 0x1f, 0x20, 0x03, 0xd5, // nop
515 0x1f, 0x20, 0x03, 0xd5 // nop
516 };
517 memcpy(dest: buf, src: pltData, n: sizeof(pltData));
518
519 uint64_t got = ctx.in.gotPlt->getVA();
520 uint64_t plt = ctx.in.plt->getVA();
521 relocateNoSym(loc: buf + 4, type: R_AARCH64_ADR_PREL_PG_HI21,
522 val: getAArch64Page(expr: got + 16) - getAArch64Page(expr: plt + 4));
523 relocateNoSym(loc: buf + 8, type: R_AARCH64_LDST64_ABS_LO12_NC, val: got + 16);
524 relocateNoSym(loc: buf + 12, type: R_AARCH64_ADD_ABS_LO12_NC, val: got + 16);
525}
526
527void AArch64::writePlt(uint8_t *buf, const Symbol &sym,
528 uint64_t pltEntryAddr) const {
529 const uint8_t inst[] = {
530 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.got.plt[n]))
531 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.got.plt[n]))]
532 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.got.plt[n]))
533 0x20, 0x02, 0x1f, 0xd6 // br x17
534 };
535 memcpy(dest: buf, src: inst, n: sizeof(inst));
536
537 uint64_t gotPltEntryAddr = sym.getGotPltVA(ctx);
538 relocateNoSym(loc: buf, type: R_AARCH64_ADR_PREL_PG_HI21,
539 val: getAArch64Page(expr: gotPltEntryAddr) - getAArch64Page(expr: pltEntryAddr));
540 relocateNoSym(loc: buf + 4, type: R_AARCH64_LDST64_ABS_LO12_NC, val: gotPltEntryAddr);
541 relocateNoSym(loc: buf + 8, type: R_AARCH64_ADD_ABS_LO12_NC, val: gotPltEntryAddr);
542}
543
544bool AArch64::needsThunk(RelExpr expr, RelType type, const InputFile *file,
545 uint64_t branchAddr, const Symbol &s,
546 int64_t a) const {
547 // If s is an undefined weak symbol and does not have a PLT entry then it will
548 // be resolved as a branch to the next instruction. If it is hidden, its
549 // binding has been converted to local, so we just check isUndefined() here. A
550 // undefined non-weak symbol will have been errored.
551 if (s.isUndefined() && !s.isInPlt(ctx))
552 return false;
553 // ELF for the ARM 64-bit architecture, section Call and Jump relocations
554 // only permits range extension thunks for R_AARCH64_CALL26 and
555 // R_AARCH64_JUMP26 relocation types.
556 if (type != R_AARCH64_CALL26 && type != R_AARCH64_JUMP26 &&
557 type != R_AARCH64_PLT32)
558 return false;
559 uint64_t dst = expr == R_PLT_PC ? s.getPltVA(ctx) : s.getVA(ctx, addend: a);
560 return !inBranchRange(type, src: branchAddr, dst);
561}
562
563uint32_t AArch64::getThunkSectionSpacing() const {
564 // See comment in Arch/ARM.cpp for a more detailed explanation of
565 // getThunkSectionSpacing(). For AArch64 the only branches we are permitted to
566 // Thunk have a range of +/- 128 MiB
567 return (128 * 1024 * 1024) - 0x30000;
568}
569
570bool AArch64::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
571 if (type != R_AARCH64_CALL26 && type != R_AARCH64_JUMP26 &&
572 type != R_AARCH64_PLT32)
573 return true;
574 // The AArch64 call and unconditional branch instructions have a range of
575 // +/- 128 MiB. The PLT32 relocation supports a range up to +/- 2 GiB.
576 uint64_t range =
577 type == R_AARCH64_PLT32 ? (UINT64_C(1) << 31) : (128 * 1024 * 1024);
578 if (dst > src) {
579 // Immediate of branch is signed.
580 range -= 4;
581 return dst - src <= range;
582 }
583 return src - dst <= range;
584}
585
586static void write32AArch64Addr(uint8_t *l, uint64_t imm) {
587 uint32_t immLo = (imm & 0x3) << 29;
588 uint32_t immHi = (imm & 0x1FFFFC) << 3;
589 uint64_t mask = (0x3 << 29) | (0x1FFFFC << 3);
590 write32le(P: l, V: (read32le(P: l) & ~mask) | immLo | immHi);
591}
592
593static void writeMaskedBits32le(uint8_t *p, int32_t v, uint32_t mask) {
594 write32le(P: p, V: (read32le(P: p) & ~mask) | v);
595}
596
597// Update the immediate field in a AARCH64 ldr, str, and add instruction.
598static void write32Imm12(uint8_t *l, uint64_t imm) {
599 writeMaskedBits32le(p: l, v: (imm & 0xFFF) << 10, mask: 0xFFF << 10);
600}
601
602// Update the immediate field in an AArch64 movk, movn or movz instruction
603// for a signed relocation, and update the opcode of a movn or movz instruction
604// to match the sign of the operand.
605static void writeSMovWImm(uint8_t *loc, uint32_t imm) {
606 uint32_t inst = read32le(P: loc);
607 // Opcode field is bits 30, 29, with 10 = movz, 00 = movn and 11 = movk.
608 if (!(inst & (1 << 29))) {
609 // movn or movz.
610 if (imm & 0x10000) {
611 // Change opcode to movn, which takes an inverted operand.
612 imm ^= 0xFFFF;
613 inst &= ~(1 << 30);
614 } else {
615 // Change opcode to movz.
616 inst |= 1 << 30;
617 }
618 }
619 write32le(P: loc, V: inst | ((imm & 0xFFFF) << 5));
620}
621
622void AArch64::relocate(uint8_t *loc, const Relocation &rel,
623 uint64_t val) const {
624 switch (rel.type) {
625 case R_AARCH64_ABS16:
626 checkIntUInt(ctx, loc, v: val, n: 16, rel);
627 write16(ctx, p: loc, v: val);
628 break;
629 case R_AARCH64_PREL16:
630 checkInt(ctx, loc, v: val, n: 16, rel);
631 write16(ctx, p: loc, v: val);
632 break;
633 case R_AARCH64_ABS32:
634 checkIntUInt(ctx, loc, v: val, n: 32, rel);
635 write32(ctx, p: loc, v: val);
636 break;
637 case R_AARCH64_PATCHINST:
638 if (!rel.sym->isUndefined()) {
639 checkUInt(ctx, loc, v: val, n: 32, rel);
640 write32le(P: loc, V: val);
641 }
642 break;
643 case R_AARCH64_PREL32:
644 case R_AARCH64_PLT32:
645 case R_AARCH64_GOTPCREL32:
646 checkInt(ctx, loc, v: val, n: 32, rel);
647 write32(ctx, p: loc, v: val);
648 break;
649 case R_AARCH64_ABS64:
650 write64(ctx, p: loc, v: val);
651 break;
652 case R_AARCH64_PREL64:
653 write64(ctx, p: loc, v: val);
654 break;
655 case R_AARCH64_AUTH_ABS64:
656 // This is used for the addend of a .relr.auth.dyn entry,
657 // which is a 32-bit value; the upper 32 bits are used to
658 // encode the schema.
659 checkInt(ctx, loc, v: val, n: 32, rel);
660 write32(ctx, p: loc, v: val);
661 break;
662 case R_AARCH64_TLS_DTPREL64:
663 write64(ctx, p: loc, v: val);
664 break;
665 case R_AARCH64_ADD_ABS_LO12_NC:
666 case R_AARCH64_AUTH_GOT_ADD_LO12_NC:
667 write32Imm12(l: loc, imm: val);
668 break;
669 case R_AARCH64_ADR_GOT_PAGE:
670 case R_AARCH64_AUTH_ADR_GOT_PAGE:
671 case R_AARCH64_ADR_PREL_PG_HI21:
672 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
673 case R_AARCH64_TLSDESC_ADR_PAGE21:
674 case R_AARCH64_AUTH_TLSDESC_ADR_PAGE21:
675 checkInt(ctx, loc, v: val, n: 33, rel);
676 [[fallthrough]];
677 case R_AARCH64_ADR_PREL_PG_HI21_NC:
678 write32AArch64Addr(l: loc, imm: val >> 12);
679 break;
680 case R_AARCH64_ADR_PREL_LO21:
681 case R_AARCH64_AUTH_GOT_ADR_PREL_LO21:
682 checkInt(ctx, loc, v: val, n: 21, rel);
683 write32AArch64Addr(l: loc, imm: val);
684 break;
685 case R_AARCH64_JUMP26:
686 // Normally we would just write the bits of the immediate field, however
687 // when patching instructions for the cpu errata fix -fix-cortex-a53-843419
688 // we want to replace a non-branch instruction with a branch immediate
689 // instruction. By writing all the bits of the instruction including the
690 // opcode and the immediate (0 001 | 01 imm26) we can do this
691 // transformation by placing a R_AARCH64_JUMP26 relocation at the offset of
692 // the instruction we want to patch.
693 write32le(P: loc, V: 0x14000000);
694 [[fallthrough]];
695 case R_AARCH64_CALL26:
696 checkInt(ctx, loc, v: val, n: 28, rel);
697 writeMaskedBits32le(p: loc, v: (val & 0x0FFFFFFC) >> 2, mask: 0x0FFFFFFC >> 2);
698 break;
699 case R_AARCH64_CONDBR19:
700 case R_AARCH64_LD_PREL_LO19:
701 case R_AARCH64_GOT_LD_PREL19:
702 case R_AARCH64_AUTH_GOT_LD_PREL19:
703 checkAlignment(ctx, loc, v: val, n: 4, rel);
704 checkInt(ctx, loc, v: val, n: 21, rel);
705 writeMaskedBits32le(p: loc, v: (val & 0x1FFFFC) << 3, mask: 0x1FFFFC << 3);
706 break;
707 case R_AARCH64_LDST8_ABS_LO12_NC:
708 case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
709 write32Imm12(l: loc, imm: getBits(val, start: 0, end: 11));
710 break;
711 case R_AARCH64_LDST16_ABS_LO12_NC:
712 case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
713 checkAlignment(ctx, loc, v: val, n: 2, rel);
714 write32Imm12(l: loc, imm: getBits(val, start: 1, end: 11));
715 break;
716 case R_AARCH64_LDST32_ABS_LO12_NC:
717 case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
718 checkAlignment(ctx, loc, v: val, n: 4, rel);
719 write32Imm12(l: loc, imm: getBits(val, start: 2, end: 11));
720 break;
721 case R_AARCH64_LDST64_ABS_LO12_NC:
722 case R_AARCH64_LD64_GOT_LO12_NC:
723 case R_AARCH64_AUTH_LD64_GOT_LO12_NC:
724 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
725 case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
726 case R_AARCH64_TLSDESC_LD64_LO12:
727 case R_AARCH64_AUTH_TLSDESC_LD64_LO12:
728 checkAlignment(ctx, loc, v: val, n: 8, rel);
729 write32Imm12(l: loc, imm: getBits(val, start: 3, end: 11));
730 break;
731 case R_AARCH64_LDST128_ABS_LO12_NC:
732 case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
733 checkAlignment(ctx, loc, v: val, n: 16, rel);
734 write32Imm12(l: loc, imm: getBits(val, start: 4, end: 11));
735 break;
736 case R_AARCH64_LD64_GOTPAGE_LO15:
737 checkAlignment(ctx, loc, v: val, n: 8, rel);
738 write32Imm12(l: loc, imm: getBits(val, start: 3, end: 14));
739 break;
740 case R_AARCH64_MOVW_UABS_G0:
741 checkUInt(ctx, loc, v: val, n: 16, rel);
742 [[fallthrough]];
743 case R_AARCH64_MOVW_UABS_G0_NC:
744 writeMaskedBits32le(p: loc, v: (val & 0xFFFF) << 5, mask: 0xFFFF << 5);
745 break;
746 case R_AARCH64_MOVW_UABS_G1:
747 checkUInt(ctx, loc, v: val, n: 32, rel);
748 [[fallthrough]];
749 case R_AARCH64_MOVW_UABS_G1_NC:
750 writeMaskedBits32le(p: loc, v: (val & 0xFFFF0000) >> 11, mask: 0xFFFF0000 >> 11);
751 break;
752 case R_AARCH64_MOVW_UABS_G2:
753 checkUInt(ctx, loc, v: val, n: 48, rel);
754 [[fallthrough]];
755 case R_AARCH64_MOVW_UABS_G2_NC:
756 writeMaskedBits32le(p: loc, v: (val & 0xFFFF00000000) >> 27,
757 mask: 0xFFFF00000000 >> 27);
758 break;
759 case R_AARCH64_MOVW_UABS_G3:
760 writeMaskedBits32le(p: loc, v: (val & 0xFFFF000000000000) >> 43,
761 mask: 0xFFFF000000000000 >> 43);
762 break;
763 case R_AARCH64_MOVW_PREL_G0:
764 case R_AARCH64_MOVW_SABS_G0:
765 case R_AARCH64_TLSLE_MOVW_TPREL_G0:
766 checkInt(ctx, loc, v: val, n: 17, rel);
767 [[fallthrough]];
768 case R_AARCH64_MOVW_PREL_G0_NC:
769 case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
770 writeSMovWImm(loc, imm: val);
771 break;
772 case R_AARCH64_MOVW_PREL_G1:
773 case R_AARCH64_MOVW_SABS_G1:
774 case R_AARCH64_TLSLE_MOVW_TPREL_G1:
775 checkInt(ctx, loc, v: val, n: 33, rel);
776 [[fallthrough]];
777 case R_AARCH64_MOVW_PREL_G1_NC:
778 case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
779 writeSMovWImm(loc, imm: val >> 16);
780 break;
781 case R_AARCH64_MOVW_PREL_G2:
782 case R_AARCH64_MOVW_SABS_G2:
783 case R_AARCH64_TLSLE_MOVW_TPREL_G2:
784 checkInt(ctx, loc, v: val, n: 49, rel);
785 [[fallthrough]];
786 case R_AARCH64_MOVW_PREL_G2_NC:
787 writeSMovWImm(loc, imm: val >> 32);
788 break;
789 case R_AARCH64_MOVW_PREL_G3:
790 writeSMovWImm(loc, imm: val >> 48);
791 break;
792 case R_AARCH64_TSTBR14:
793 checkInt(ctx, loc, v: val, n: 16, rel);
794 writeMaskedBits32le(p: loc, v: (val & 0xFFFC) << 3, mask: 0xFFFC << 3);
795 break;
796 case R_AARCH64_TLSLE_ADD_TPREL_HI12:
797 checkUInt(ctx, loc, v: val, n: 24, rel);
798 if (ctx.arg.relax && (val >> 12) == 0) {
799 uint32_t inst = read32le(P: loc);
800 // The W-form zero-extends Xd, so only the X-form is a nop.
801 if ((inst & (1u << 31)) && (inst & 0x1f) == ((inst >> 5) & 0x1f)) {
802 write32le(P: loc, V: 0xd503201f); // nop
803 break;
804 }
805 }
806 write32Imm12(l: loc, imm: val >> 12);
807 break;
808 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
809 case R_AARCH64_TLSDESC_ADD_LO12:
810 case R_AARCH64_AUTH_TLSDESC_ADD_LO12:
811 write32Imm12(l: loc, imm: val);
812 break;
813 case R_AARCH64_TLSDESC:
814 // For R_AARCH64_TLSDESC the addend is stored in the second 64-bit word.
815 write64(ctx, p: loc + 8, v: val);
816 break;
817 default:
818 llvm_unreachable("unknown relocation");
819 }
820}
821
822void AArch64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
823 uint64_t val) const {
824 // TLSDESC Global-Dynamic relocation are in the form:
825 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
826 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
827 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
828 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
829 // blr x1
830 // And it can optimized to:
831 // movz x0, #0x0, lsl #16
832 // movk x0, #0x10
833 // nop
834 // nop
835 checkUInt(ctx, loc, v: val, n: 32, rel);
836
837 switch (rel.type) {
838 case R_AARCH64_TLSDESC_ADD_LO12:
839 case R_AARCH64_TLSDESC_CALL:
840 write32le(P: loc, V: 0xd503201f); // nop
841 return;
842 case R_AARCH64_TLSDESC_ADR_PAGE21:
843 write32le(P: loc, V: 0xd2a00000 | (((val >> 16) & 0xffff) << 5)); // movz
844 return;
845 case R_AARCH64_TLSDESC_LD64_LO12:
846 write32le(P: loc, V: 0xf2800000 | ((val & 0xffff) << 5)); // movk
847 return;
848 default:
849 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
850 }
851}
852
853void AArch64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
854 uint64_t val) const {
855 // TLSDESC Global-Dynamic relocation are in the form:
856 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
857 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
858 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
859 // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
860 // blr x1
861 // And it can optimized to:
862 // adrp x0, :gottprel:v
863 // ldr x0, [x0, :gottprel_lo12:v]
864 // nop
865 // nop
866
867 switch (rel.type) {
868 case R_AARCH64_TLSDESC_ADD_LO12:
869 case R_AARCH64_TLSDESC_CALL:
870 write32le(P: loc, V: 0xd503201f); // nop
871 break;
872 case R_AARCH64_TLSDESC_ADR_PAGE21:
873 write32le(P: loc, V: 0x90000000); // adrp
874 relocateNoSym(loc, type: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, val);
875 break;
876 case R_AARCH64_TLSDESC_LD64_LO12:
877 write32le(P: loc, V: 0xf9400000); // ldr
878 relocateNoSym(loc, type: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, val);
879 break;
880 default:
881 llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
882 }
883}
884
885void AArch64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
886 uint64_t val) const {
887 checkUInt(ctx, loc, v: val, n: 32, rel);
888
889 if (rel.type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
890 // Generate MOVZ.
891 uint32_t regNo = read32le(P: loc) & 0x1f;
892 write32le(P: loc, V: (0xd2a00000 | regNo) | (((val >> 16) & 0xffff) << 5));
893 return;
894 }
895 if (rel.type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
896 // Generate MOVK.
897 uint32_t regNo = read32le(P: loc) & 0x1f;
898 write32le(P: loc, V: (0xf2800000 | regNo) | ((val & 0xffff) << 5));
899 return;
900 }
901 llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
902}
903
904AArch64Relaxer::AArch64Relaxer(Ctx &ctx, ArrayRef<Relocation> relocs,
905 uint64_t secAddr, uint8_t *buf)
906 : ctx(ctx) {
907 if (!ctx.arg.relax)
908 return;
909 // For a given symbol R_AARCH64_ADR_GOT_PAGE and R_AARCH64_LD64_GOT_LO12_NC
910 // relaxation is all-or-nothing. We can't relax only some of them, as there
911 // may be a jump destination between the two relocations.
912 size_t i = 0;
913 const size_t size = relocs.size();
914 for (; i != size; ++i) {
915 if (relocs[i].type == R_AARCH64_ADR_GOT_PAGE) {
916 if (i + 1 < size && relocs[i + 1].type == R_AARCH64_LD64_GOT_LO12_NC &&
917 !unsafeToRelaxAdrpLdr.contains(Ptr: relocs[i].sym) &&
918 isLegalAdrpLdrRelaxationCandidate(adrpRel: relocs[i], ldrRel: relocs[i + 1], secAddr,
919 buf)) {
920 ++i;
921 continue;
922 }
923 unsafeToRelaxAdrpLdr.insert(Ptr: relocs[i].sym);
924 } else if (relocs[i].type == R_AARCH64_LD64_GOT_LO12_NC) {
925 unsafeToRelaxAdrpLdr.insert(Ptr: relocs[i].sym);
926 }
927 }
928}
929
930bool AArch64Relaxer::tryRelaxAdrpAdd(const Relocation &adrpRel,
931 const Relocation &addRel, uint64_t secAddr,
932 uint8_t *buf) const {
933 // When the address of sym is within the range of ADR then
934 // we may relax
935 // ADRP xn, sym
936 // ADD xn, xn, :lo12: sym
937 // to
938 // NOP
939 // ADR xn, sym
940 if (!ctx.arg.relax || addRel.type != R_AARCH64_ADD_ABS_LO12_NC)
941 return false;
942 // Check if the relocations apply to consecutive instructions.
943 if (adrpRel.offset + 4 != addRel.offset)
944 return false;
945 if (adrpRel.sym != addRel.sym)
946 return false;
947 if (adrpRel.addend != 0 || addRel.addend != 0)
948 return false;
949
950 uint32_t adrpInstr = read32le(P: buf + adrpRel.offset);
951 uint32_t addInstr = read32le(P: buf + addRel.offset);
952 // Check if the first instruction is ADRP and the second instruction is ADD.
953 if ((adrpInstr & 0x9f000000) != 0x90000000 ||
954 (addInstr & 0xffc00000) != 0x91000000)
955 return false;
956 uint32_t adrpDestReg = adrpInstr & 0x1f;
957 uint32_t addDestReg = addInstr & 0x1f;
958 uint32_t addSrcReg = (addInstr >> 5) & 0x1f;
959 if (adrpDestReg != addDestReg || adrpDestReg != addSrcReg)
960 return false;
961
962 Symbol &sym = *adrpRel.sym;
963 // Check if the address difference is within 1MiB range.
964 int64_t val = sym.getVA(ctx) - (secAddr + addRel.offset);
965 if (val < -1024 * 1024 || val >= 1024 * 1024)
966 return false;
967
968 Relocation adrRel = {.expr: R_ABS, .type: R_AARCH64_ADR_PREL_LO21, .offset: addRel.offset,
969 /*addend=*/0, .sym: &sym};
970 // nop
971 write32le(P: buf + adrpRel.offset, V: 0xd503201f);
972 // adr x_<dest_reg>
973 write32le(P: buf + adrRel.offset, V: 0x10000000 | adrpDestReg);
974 ctx.target->relocate(loc: buf + adrRel.offset, rel: adrRel, val);
975 return true;
976}
977
978bool AArch64Relaxer::isLegalAdrpLdrRelaxationCandidate(
979 const Relocation &adrpRel, const Relocation &ldrRel, uint64_t secAddr,
980 uint8_t *buf) const {
981 // Check if the relocations apply to consecutive instructions.
982 if (adrpRel.offset + 4 != ldrRel.offset)
983 return false;
984 // Check if the relocations reference the same symbol and
985 // skip undefined, preemptible and STT_GNU_IFUNC symbols.
986 if (!adrpRel.sym || adrpRel.sym != ldrRel.sym || !adrpRel.sym->isDefined() ||
987 adrpRel.sym->isPreemptible || adrpRel.sym->isGnuIFunc())
988 return false;
989 // Check if the addends of the both relocations are zero.
990 if (adrpRel.addend != 0 || ldrRel.addend != 0)
991 return false;
992 uint32_t adrpInstr = read32le(P: buf + adrpRel.offset);
993 uint32_t ldrInstr = read32le(P: buf + ldrRel.offset);
994 // Check if the first instruction is ADRP and the second instruction is LDR.
995 if ((adrpInstr & 0x9f000000) != 0x90000000 ||
996 (ldrInstr & 0x3b000000) != 0x39000000)
997 return false;
998 // Check the value of the sf bit.
999 if (!(ldrInstr >> 31))
1000 return false;
1001 uint32_t adrpDestReg = adrpInstr & 0x1f;
1002 uint32_t ldrDestReg = ldrInstr & 0x1f;
1003 uint32_t ldrSrcReg = (ldrInstr >> 5) & 0x1f;
1004 // Check if ADPR and LDR use the same register.
1005 if (adrpDestReg != ldrDestReg || adrpDestReg != ldrSrcReg)
1006 return false;
1007
1008 Symbol &sym = *adrpRel.sym;
1009 // GOT references to absolute symbols can't be relaxed to use ADRP/ADD in
1010 // position-independent code because these instructions produce a relative
1011 // address.
1012 if (ctx.arg.isPic && !cast<Defined>(Val&: sym).section)
1013 return false;
1014 // Check if the address difference is within 4GB range.
1015 int64_t val =
1016 getAArch64Page(expr: sym.getVA(ctx)) - getAArch64Page(expr: secAddr + adrpRel.offset);
1017 if (val != llvm::SignExtend64(X: val, B: 33))
1018 return false;
1019
1020 return true;
1021}
1022
1023bool AArch64Relaxer::tryRelaxAdrpLdr(const Relocation &adrpRel,
1024 const Relocation &ldrRel, uint64_t secAddr,
1025 uint8_t *buf) const {
1026 // When the definition of sym is not preemptible then we may
1027 // be able to relax
1028 // ADRP xn, :got: sym
1029 // LDR xn, [ xn :got_lo12: sym]
1030 // to
1031 // ADRP xn, sym
1032 // ADD xn, xn, :lo_12: sym
1033
1034 if (!ctx.arg.relax || adrpRel.type != R_AARCH64_ADR_GOT_PAGE ||
1035 ldrRel.type != R_AARCH64_LD64_GOT_LO12_NC)
1036 return false;
1037
1038 Symbol *sym = adrpRel.sym;
1039 if (unsafeToRelaxAdrpLdr.contains(Ptr: sym))
1040 return false;
1041
1042 assert(isLegalAdrpLdrRelaxationCandidate(adrpRel, ldrRel, secAddr, buf) &&
1043 "Should have been marked as unsafe");
1044
1045 uint32_t adrpInstr = read32le(P: buf + adrpRel.offset);
1046 uint32_t adrpDestReg = adrpInstr & 0x1f;
1047 Relocation adrpSymRel = {.expr: RE_AARCH64_PAGE_PC, .type: R_AARCH64_ADR_PREL_PG_HI21,
1048 .offset: adrpRel.offset, /*addend=*/0, .sym: sym};
1049 Relocation addRel = {.expr: R_ABS, .type: R_AARCH64_ADD_ABS_LO12_NC, .offset: ldrRel.offset,
1050 /*addend=*/0, .sym: sym};
1051
1052 // adrp x_<dest_reg>
1053 write32le(P: buf + adrpSymRel.offset, V: 0x90000000 | adrpDestReg);
1054 // add x_<dest reg>, x_<dest reg>
1055 write32le(P: buf + addRel.offset, V: 0x91000000 | adrpDestReg | (adrpDestReg << 5));
1056
1057 ctx.target->relocate(
1058 loc: buf + adrpSymRel.offset, rel: adrpSymRel,
1059 val: SignExtend64(X: getAArch64Page(expr: sym->getVA(ctx)) -
1060 getAArch64Page(expr: secAddr + adrpSymRel.offset),
1061 B: 64));
1062 ctx.target->relocate(loc: buf + addRel.offset, rel: addRel,
1063 val: SignExtend64(X: sym->getVA(ctx), B: 64));
1064 tryRelaxAdrpAdd(adrpRel: adrpSymRel, addRel, secAddr, buf);
1065 return true;
1066}
1067
1068// Tagged symbols have upper address bits that are added by the dynamic loader,
1069// and thus need the full 64-bit GOT entry. Do not relax such symbols.
1070static bool needsGotForMemtag(const Relocation &rel) {
1071 return rel.sym->isTagged() && needsGot(expr: rel.expr);
1072}
1073
1074void AArch64::relocateAlloc(InputSection &sec, uint8_t *buf) const {
1075 uint64_t secAddr = sec.getOutputSection()->addr + sec.outSecOff;
1076 const ArrayRef<Relocation> relocs = sec.relocs();
1077 AArch64Relaxer relaxer(ctx, relocs, secAddr, buf);
1078 for (size_t i = 0, size = relocs.size(); i != size; ++i) {
1079 const Relocation &rel = relocs[i];
1080 if (rel.expr == R_NONE) // See finalizeAddressDependentContent()
1081 continue;
1082 uint8_t *loc = buf + rel.offset;
1083 const uint64_t val = sec.getRelocTargetVA(ctx, r: rel, p: secAddr + rel.offset);
1084
1085 if (needsGotForMemtag(rel)) {
1086 relocate(loc, rel, val);
1087 continue;
1088 }
1089
1090 switch (rel.type) {
1091 case R_AARCH64_ADR_GOT_PAGE:
1092 if (i + 1 < size &&
1093 relaxer.tryRelaxAdrpLdr(adrpRel: rel, ldrRel: relocs[i + 1], secAddr, buf)) {
1094 ++i;
1095 continue;
1096 }
1097 break;
1098 case R_AARCH64_ADR_PREL_PG_HI21:
1099 if (i + 1 < size &&
1100 relaxer.tryRelaxAdrpAdd(adrpRel: rel, addRel: relocs[i + 1], secAddr, buf)) {
1101 ++i;
1102 continue;
1103 }
1104 break;
1105
1106 case R_AARCH64_TLSDESC_ADR_PAGE21:
1107 case R_AARCH64_TLSDESC_LD64_LO12:
1108 case R_AARCH64_TLSDESC_ADD_LO12:
1109 case R_AARCH64_TLSDESC_CALL:
1110 if (rel.expr == R_TPREL)
1111 relaxTlsGdToLe(loc, rel, val);
1112 else if (rel.expr == RE_AARCH64_GOT_PAGE_PC || rel.expr == R_GOT)
1113 relaxTlsGdToIe(loc, rel, val);
1114 else
1115 relocate(loc, rel, val);
1116 continue;
1117 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
1118 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
1119 if (rel.expr == R_TPREL)
1120 relaxTlsIeToLe(loc, rel, val);
1121 else
1122 relocate(loc, rel, val);
1123 continue;
1124 default:
1125 break;
1126 }
1127
1128 relocate(loc, rel, val);
1129 }
1130}
1131
1132static std::optional<uint64_t> getControlTransferAddend(InputSection &is,
1133 Relocation &r) {
1134 // Identify a control transfer relocation for the branch-to-branch
1135 // optimization. A "control transfer relocation" means a B or BL
1136 // target but it also includes relative vtable relocations for example.
1137 //
1138 // We require the relocation type to be JUMP26, CALL26 or PLT32. With a
1139 // relocation type of PLT32 the value may be assumed to be used for branching
1140 // directly to the symbol and the addend is only used to produce the relocated
1141 // value (hence the effective addend is always 0). This is because if a PLT is
1142 // needed the addend will be added to the address of the PLT, and it doesn't
1143 // make sense to branch into the middle of a PLT. For example, relative vtable
1144 // relocations use PLT32 and 0 or a positive value as the addend but still are
1145 // used to branch to the symbol.
1146 //
1147 // With JUMP26 or CALL26 the only reasonable interpretation of a non-zero
1148 // addend is that we are branching to symbol+addend so that becomes the
1149 // effective addend.
1150 if (r.type == R_AARCH64_PLT32)
1151 return 0;
1152 if (r.type == R_AARCH64_JUMP26 || r.type == R_AARCH64_CALL26)
1153 return r.addend;
1154 return std::nullopt;
1155}
1156
1157static std::pair<Relocation *, uint64_t>
1158getBranchInfoAtTarget(InputSection &is, uint64_t offset) {
1159 auto *i = llvm::partition_point(
1160 Range&: is.relocations, P: [&](Relocation &r) { return r.offset < offset; });
1161 if (i != is.relocations.end() && i->offset == offset &&
1162 i->type == R_AARCH64_JUMP26) {
1163 return {i, i->addend};
1164 }
1165 return {nullptr, 0};
1166}
1167
1168static void redirectControlTransferRelocations(Relocation &r1,
1169 const Relocation &r2) {
1170 r1.expr = r2.expr;
1171 r1.sym = r2.sym;
1172 // With PLT32 we must respect the original addend as that affects the value's
1173 // interpretation. With the other relocation types the original addend is
1174 // irrelevant because it referred to an offset within the original target
1175 // section so we overwrite it.
1176 if (r1.type == R_AARCH64_PLT32)
1177 r1.addend += r2.addend;
1178 else
1179 r1.addend = r2.addend;
1180}
1181
1182void AArch64::applyBranchToBranchOpt() const {
1183 applyBranchToBranchOptImpl(ctx, getControlTransferAddend,
1184 getBranchInfoAtTarget,
1185 redirectControlTransferRelocations);
1186}
1187
1188// AArch64 may use security features in variant PLT sequences. These are:
1189// Pointer Authentication (PAC), introduced in armv8.3-a and Branch Target
1190// Indicator (BTI) introduced in armv8.5-a. The additional instructions used
1191// in the variant Plt sequences are encoded in the Hint space so they can be
1192// deployed on older architectures, which treat the instructions as a nop.
1193// PAC and BTI can be combined leading to the following combinations:
1194// writePltHeader
1195// writePltHeaderBti (no PAC Header needed)
1196// writePlt
1197// writePltBti (BTI only)
1198// writePltPac (PAC only)
1199// writePltBtiPac (BTI and PAC)
1200//
1201// When PAC is enabled the dynamic loader encrypts the address that it places
1202// in the .got.plt using the pacia1716 instruction which encrypts the value in
1203// x17 using the modifier in x16. The static linker places autia1716 before the
1204// indirect branch to x17 to authenticate the address in x17 with the modifier
1205// in x16. This makes it more difficult for an attacker to modify the value in
1206// the .got.plt.
1207//
1208// When BTI is enabled all indirect branches must land on a bti instruction.
1209// The static linker must place a bti instruction at the start of any PLT entry
1210// that may be the target of an indirect branch. As the PLT entries call the
1211// lazy resolver indirectly this must have a bti instruction at start. In
1212// general a bti instruction is not needed for a PLT entry as indirect calls
1213// are resolved to the function address and not the PLT entry for the function.
1214// There are a small number of cases where the PLT address can escape, such as
1215// taking the address of a function or ifunc via a non got-generating
1216// relocation, and a shared library refers to that symbol.
1217//
1218// We use the bti c variant of the instruction which permits indirect branches
1219// (br) via x16/x17 and indirect function calls (blr) via any register. The ABI
1220// guarantees that all indirect branches from code requiring BTI protection
1221// will go via x16/x17
1222
1223namespace {
1224class AArch64BtiPac final : public AArch64 {
1225public:
1226 AArch64BtiPac(Ctx &);
1227 void writePltHeader(uint8_t *buf) const override;
1228 void writePlt(uint8_t *buf, const Symbol &sym,
1229 uint64_t pltEntryAddr) const override;
1230
1231private:
1232 bool btiHeader; // bti instruction needed in PLT Header and Entry
1233 enum {
1234 PEK_NoAuth,
1235 PEK_AuthHint, // use autia1716 instr for authenticated branch in PLT entry
1236 PEK_Auth, // use braa instr for authenticated branch in PLT entry
1237 } pacEntryKind;
1238};
1239} // namespace
1240
1241AArch64BtiPac::AArch64BtiPac(Ctx &ctx) : AArch64(ctx) {
1242 btiHeader = (ctx.arg.andFeatures & GNU_PROPERTY_AARCH64_FEATURE_1_BTI);
1243 // A BTI (Branch Target Indicator) Plt Entry is only required if the
1244 // address of the PLT entry can be taken by the program, which permits an
1245 // indirect jump to the PLT entry. This can happen when the address
1246 // of the PLT entry for a function is canonicalised due to the address of
1247 // the function in an executable being taken by a shared library, or
1248 // non-preemptible ifunc referenced by non-GOT-generating, non-PLT-generating
1249 // relocations.
1250 // The PAC PLT entries require dynamic loader support and this isn't known
1251 // from properties in the objects, so we use the command line flag.
1252 // By default we only use hint-space instructions, but if we detect the
1253 // PAuthABI, which requires v8.3-A, we can use the non-hint space
1254 // instructions.
1255
1256 if (ctx.arg.zPacPlt) {
1257 if (ctx.aarch64PauthAbiCoreInfo && ctx.aarch64PauthAbiCoreInfo->isValid())
1258 pacEntryKind = PEK_Auth;
1259 else
1260 pacEntryKind = PEK_AuthHint;
1261 } else {
1262 pacEntryKind = PEK_NoAuth;
1263 }
1264
1265 if (btiHeader || (pacEntryKind != PEK_NoAuth)) {
1266 pltEntrySize = 24;
1267 ipltEntrySize = 24;
1268 }
1269}
1270
1271void AArch64BtiPac::writePltHeader(uint8_t *buf) const {
1272 const uint8_t btiData[] = { 0x5f, 0x24, 0x03, 0xd5 }; // bti c
1273 const uint8_t pltData[] = {
1274 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]!
1275 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.got.plt[2]))
1276 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.got.plt[2]))]
1277 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.got.plt[2]))
1278 0x20, 0x02, 0x1f, 0xd6, // br x17
1279 0x1f, 0x20, 0x03, 0xd5, // nop
1280 0x1f, 0x20, 0x03, 0xd5 // nop
1281 };
1282 const uint8_t nopData[] = { 0x1f, 0x20, 0x03, 0xd5 }; // nop
1283
1284 uint64_t got = ctx.in.gotPlt->getVA();
1285 uint64_t plt = ctx.in.plt->getVA();
1286
1287 if (btiHeader) {
1288 // PltHeader is called indirectly by plt[N]. Prefix pltData with a BTI C
1289 // instruction.
1290 memcpy(dest: buf, src: btiData, n: sizeof(btiData));
1291 buf += sizeof(btiData);
1292 plt += sizeof(btiData);
1293 }
1294 memcpy(dest: buf, src: pltData, n: sizeof(pltData));
1295
1296 relocateNoSym(loc: buf + 4, type: R_AARCH64_ADR_PREL_PG_HI21,
1297 val: getAArch64Page(expr: got + 16) - getAArch64Page(expr: plt + 4));
1298 relocateNoSym(loc: buf + 8, type: R_AARCH64_LDST64_ABS_LO12_NC, val: got + 16);
1299 relocateNoSym(loc: buf + 12, type: R_AARCH64_ADD_ABS_LO12_NC, val: got + 16);
1300 if (!btiHeader)
1301 // We didn't add the BTI c instruction so round out size with NOP.
1302 memcpy(dest: buf + sizeof(pltData), src: nopData, n: sizeof(nopData));
1303}
1304
1305void AArch64BtiPac::writePlt(uint8_t *buf, const Symbol &sym,
1306 uint64_t pltEntryAddr) const {
1307 // The PLT entry is of the form:
1308 // [btiData] addrInst (pacBr | stdBr) [nopData]
1309 const uint8_t btiData[] = { 0x5f, 0x24, 0x03, 0xd5 }; // bti c
1310 const uint8_t addrInst[] = {
1311 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.got.plt[n]))
1312 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.got.plt[n]))]
1313 0x10, 0x02, 0x00, 0x91 // add x16, x16, Offset(&(.got.plt[n]))
1314 };
1315 const uint8_t pacHintBr[] = {
1316 0x9f, 0x21, 0x03, 0xd5, // autia1716
1317 0x20, 0x02, 0x1f, 0xd6 // br x17
1318 };
1319 const uint8_t pacBr[] = {
1320 0x30, 0x0a, 0x1f, 0xd7, // braa x17, x16
1321 0x1f, 0x20, 0x03, 0xd5 // nop
1322 };
1323 const uint8_t stdBr[] = {
1324 0x20, 0x02, 0x1f, 0xd6, // br x17
1325 0x1f, 0x20, 0x03, 0xd5 // nop
1326 };
1327 const uint8_t nopData[] = { 0x1f, 0x20, 0x03, 0xd5 }; // nop
1328
1329 // NEEDS_COPY indicates a non-ifunc canonical PLT entry whose address may
1330 // escape to shared objects. isInIplt indicates a non-preemptible ifunc. Its
1331 // address may escape if referenced by a direct relocation. If relative
1332 // vtables are used then if the vtable is in a shared object the offsets will
1333 // be to the PLT entry. The condition is conservative.
1334 bool hasBti = btiHeader &&
1335 (sym.hasFlag(bit: NEEDS_COPY) || sym.isInIplt || sym.thunkAccessed);
1336 if (hasBti) {
1337 memcpy(dest: buf, src: btiData, n: sizeof(btiData));
1338 buf += sizeof(btiData);
1339 pltEntryAddr += sizeof(btiData);
1340 }
1341
1342 uint64_t gotPltEntryAddr = sym.getGotPltVA(ctx);
1343 memcpy(dest: buf, src: addrInst, n: sizeof(addrInst));
1344 relocateNoSym(loc: buf, type: R_AARCH64_ADR_PREL_PG_HI21,
1345 val: getAArch64Page(expr: gotPltEntryAddr) - getAArch64Page(expr: pltEntryAddr));
1346 relocateNoSym(loc: buf + 4, type: R_AARCH64_LDST64_ABS_LO12_NC, val: gotPltEntryAddr);
1347 relocateNoSym(loc: buf + 8, type: R_AARCH64_ADD_ABS_LO12_NC, val: gotPltEntryAddr);
1348
1349 if (pacEntryKind != PEK_NoAuth)
1350 memcpy(dest: buf + sizeof(addrInst),
1351 src: pacEntryKind == PEK_AuthHint ? pacHintBr : pacBr,
1352 n: sizeof(pacEntryKind == PEK_AuthHint ? pacHintBr : pacBr));
1353 else
1354 memcpy(dest: buf + sizeof(addrInst), src: stdBr, n: sizeof(stdBr));
1355 if (!hasBti)
1356 // We didn't add the BTI c instruction so round out size with NOP.
1357 memcpy(dest: buf + sizeof(addrInst) + sizeof(stdBr), src: nopData, n: sizeof(nopData));
1358}
1359
1360template <class ELFT>
1361static void
1362addTaggedSymbolReferences(Ctx &ctx, InputSectionBase &sec,
1363 DenseMap<Symbol *, unsigned> &referenceCount) {
1364 assert(sec.type == SHT_AARCH64_MEMTAG_GLOBALS_STATIC);
1365
1366 const RelsOrRelas<ELFT> rels = sec.relsOrRelas<ELFT>();
1367 if (rels.areRelocsRel())
1368 ErrAlways(ctx)
1369 << "non-RELA relocations are not allowed with memtag globals";
1370
1371 for (const typename ELFT::Rela &rel : rels.relas) {
1372 Symbol &sym = sec.file->getRelocTargetSym(rel);
1373 // Linker-synthesized symbols such as __executable_start may be referenced
1374 // as tagged in input objfiles, and we don't want them to be tagged. A
1375 // cheap way to exclude them is the type check, but their type is
1376 // STT_NOTYPE. In addition, this save us from checking untaggable symbols,
1377 // like functions or TLS symbols.
1378 if (sym.type != STT_OBJECT)
1379 continue;
1380 // STB_LOCAL symbols can't be referenced from outside the object file, and
1381 // thus don't need to be checked for references from other object files.
1382 if (sym.binding == STB_LOCAL) {
1383 sym.setIsTagged(true);
1384 continue;
1385 }
1386 ++referenceCount[&sym];
1387 }
1388 sec.markDead();
1389}
1390
1391// A tagged symbol must be denoted as being tagged by all references and the
1392// chosen definition. For simplicity, here, it must also be denoted as tagged
1393// for all definitions. Otherwise:
1394//
1395// 1. A tagged definition can be used by an untagged declaration, in which case
1396// the untagged access may be PC-relative, causing a tag mismatch at
1397// runtime.
1398// 2. An untagged definition can be used by a tagged declaration, where the
1399// compiler has taken advantage of the increased alignment of the tagged
1400// declaration, but the alignment at runtime is wrong, causing a fault.
1401//
1402// Ideally, this isn't a problem, as any TU that imports or exports tagged
1403// symbols should also be built with tagging. But, to handle these cases, we
1404// demote the symbol to be untagged.
1405void elf::createTaggedSymbols(Ctx &ctx) {
1406 assert(hasMemtag(ctx));
1407
1408 // First, collect all symbols that are marked as tagged, and count how many
1409 // times they're marked as tagged.
1410 DenseMap<Symbol *, unsigned> taggedSymbolReferenceCount;
1411 for (InputFile *file : ctx.objectFiles) {
1412 if (file->kind() != InputFile::ObjKind)
1413 continue;
1414 for (InputSectionBase *section : file->getSections()) {
1415 if (!section || section->type != SHT_AARCH64_MEMTAG_GLOBALS_STATIC ||
1416 section == &InputSection::discarded)
1417 continue;
1418 invokeELFT(addTaggedSymbolReferences, ctx, *section,
1419 taggedSymbolReferenceCount);
1420 }
1421 }
1422
1423 // Now, go through all the symbols. If the number of declarations +
1424 // definitions to a symbol exceeds the amount of times they're marked as
1425 // tagged, it means we have an objfile that uses the untagged variant of the
1426 // symbol.
1427 for (InputFile *file : ctx.objectFiles) {
1428 if (file->kind() != InputFile::BinaryKind &&
1429 file->kind() != InputFile::ObjKind)
1430 continue;
1431
1432 for (Symbol *symbol : file->getSymbols()) {
1433 // See `addTaggedSymbolReferences` for more details.
1434 if (symbol->type != STT_OBJECT ||
1435 symbol->binding == STB_LOCAL)
1436 continue;
1437 auto it = taggedSymbolReferenceCount.find(Val: symbol);
1438 if (it == taggedSymbolReferenceCount.end()) continue;
1439 unsigned &remainingAllowedTaggedRefs = it->second;
1440 if (remainingAllowedTaggedRefs == 0) {
1441 taggedSymbolReferenceCount.erase(I: it);
1442 continue;
1443 }
1444 --remainingAllowedTaggedRefs;
1445 }
1446 }
1447
1448 // `addTaggedSymbolReferences` has already checked that we have RELA
1449 // relocations, the only other way to get written addends is with
1450 // --apply-dynamic-relocs.
1451 if (!taggedSymbolReferenceCount.empty() && ctx.arg.writeAddends)
1452 ErrAlways(ctx) << "--apply-dynamic-relocs cannot be used with MTE globals";
1453
1454 // Now, `taggedSymbolReferenceCount` should only contain symbols that are
1455 // defined as tagged exactly the same amount as it's referenced, meaning all
1456 // uses are tagged.
1457 for (auto &[symbol, remainingTaggedRefs] : taggedSymbolReferenceCount) {
1458 assert(remainingTaggedRefs == 0 &&
1459 "Symbol is defined as tagged more times than it's used");
1460 symbol->setIsTagged(true);
1461 }
1462}
1463
1464void elf::setAArch64TargetInfo(Ctx &ctx) {
1465 if ((ctx.arg.andFeatures & GNU_PROPERTY_AARCH64_FEATURE_1_BTI) ||
1466 ctx.arg.zPacPlt)
1467 ctx.target.reset(p: new AArch64BtiPac(ctx));
1468 else
1469 ctx.target.reset(p: new AArch64(ctx));
1470}
1471