1//===-- Hexagon.cpp -------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "InputFiles.h"
10#include "OutputSections.h"
11#include "RelocScan.h"
12#include "SymbolTable.h"
13#include "Symbols.h"
14#include "SyntheticSections.h"
15#include "Target.h"
16#include "Thunks.h"
17#include "lld/Common/ErrorHandler.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/BinaryFormat/ELF.h"
20#include "llvm/Support/ELFAttributes.h"
21#include "llvm/Support/Endian.h"
22#include "llvm/Support/HexagonAttributeParser.h"
23#include "llvm/Support/HexagonAttributes.h"
24#include "llvm/Support/LEB128.h"
25
26using namespace llvm;
27using namespace llvm::object;
28using namespace llvm::support::endian;
29using namespace llvm::ELF;
30using namespace lld;
31using namespace lld::elf;
32
33namespace {
34class Hexagon final : public TargetInfo {
35public:
36 Hexagon(Ctx &);
37 uint32_t calcEFlags() const override;
38 RelExpr getRelExpr(RelType type, const Symbol &s,
39 const uint8_t *loc) const override;
40 RelType getDynRel(RelType type) const override;
41 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
42 template <class ELFT, class RelTy>
43 void scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels,
44 unsigned shard);
45 void scanSection(InputSectionBase &sec, unsigned shard) override {
46 elf::scanSection1<Hexagon, ELF32LE>(target&: *this, sec, shard);
47 }
48 void finalizeRelocScan() override;
49 bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
50 uint64_t branchAddr, const Symbol &s,
51 int64_t a) const override;
52 uint32_t getThunkSectionSpacing() const override;
53 bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
54 void relocate(uint8_t *loc, const Relocation &rel,
55 uint64_t val) const override;
56 void writePltHeader(uint8_t *buf) const override;
57 void writePlt(uint8_t *buf, const Symbol &sym,
58 uint64_t pltEntryAddr) const override;
59};
60} // namespace
61
62Hexagon::Hexagon(Ctx &ctx) : TargetInfo(ctx) {
63 pltRel = R_HEX_JMP_SLOT;
64 relativeRel = R_HEX_RELATIVE;
65 gotRel = R_HEX_GLOB_DAT;
66 symbolicRel = R_HEX_32;
67
68 gotBaseSymInGotPlt = true;
69 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The
70 // next 3 are reserved for the dynamic loader.
71 gotPltHeaderEntriesNum = 4;
72
73 pltEntrySize = 16;
74 pltHeaderSize = 32;
75
76 // Hexagon Linux uses 64K pages by default.
77 defaultMaxPageSize = 0x10000;
78 tlsGotRel = R_HEX_TPREL_32;
79 tlsModuleIndexRel = R_HEX_DTPMOD_32;
80 tlsOffsetRel = R_HEX_DTPREL_32;
81
82 needsThunks = true;
83}
84
85uint32_t Hexagon::calcEFlags() const {
86 // The architecture revision must always be equal to or greater than
87 // greatest revision in the list of inputs.
88 std::optional<uint32_t> ret;
89 for (InputFile *f : ctx.objectFiles) {
90 uint32_t eflags = cast<ObjFile<ELF32LE>>(Val: f)->getObj().getHeader().e_flags;
91 if (!ret || eflags > *ret)
92 ret = eflags;
93 }
94 return ret.value_or(/* Default Arch Rev: */ u: EF_HEXAGON_MACH_V68);
95}
96
97static uint32_t applyMask(uint32_t mask, uint32_t data) {
98 uint32_t result = 0;
99 size_t off = 0;
100
101 for (size_t bit = 0; bit != 32; ++bit) {
102 uint32_t valBit = (data >> off) & 1;
103 uint32_t maskBit = (mask >> bit) & 1;
104 if (maskBit) {
105 result |= (valBit << bit);
106 ++off;
107 }
108 }
109 return result;
110}
111
112// Only needed to support relocations used by relocateNonAlloc and
113// preprocessRelocs.
114RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
115 const uint8_t *loc) const {
116 switch (type) {
117 case R_HEX_NONE:
118 return R_NONE;
119 case R_HEX_32:
120 return R_ABS;
121 case R_HEX_32_PCREL:
122 return R_PC;
123 default:
124 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v
125 << ") against symbol " << &s;
126 return R_NONE;
127 }
128}
129
130template <class ELFT, class RelTy>
131void Hexagon::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels,
132 unsigned shard) {
133 RelocScan rs(ctx, &sec, shard);
134 sec.relocations.reserve(N: rels.size());
135 for (auto it = rels.begin(); it != rels.end(); ++it) {
136 const RelTy &rel = *it;
137 uint32_t symIdx = rel.getSymbol(false);
138 Symbol &sym = sec.getFile<ELFT>()->getSymbol(symIdx);
139 uint64_t offset = rel.r_offset;
140 RelType type = rel.getType(false);
141 if (sym.isUndefined() && symIdx != 0 &&
142 rs.maybeReportUndefined(sym&: cast<Undefined>(Val&: sym), offset))
143 continue;
144 int64_t addend = rs.getAddend<ELFT>(rel, type);
145 RelExpr expr;
146 // Relocation types that only need a RelExpr set `expr` and break out of
147 // the switch to reach rs.process(). Types that need special handling
148 // (fast-path helpers, TLS) call a handler and use `continue`.
149 switch (type) {
150 case R_HEX_NONE:
151 continue;
152
153 // Absolute relocations:
154 case R_HEX_6_X:
155 case R_HEX_8_X:
156 case R_HEX_9_X:
157 case R_HEX_10_X:
158 case R_HEX_11_X:
159 case R_HEX_12_X:
160 case R_HEX_16_X:
161 case R_HEX_32:
162 case R_HEX_32_6_X:
163 case R_HEX_HI16:
164 case R_HEX_LO16:
165 case R_HEX_DTPREL_32:
166 expr = R_ABS;
167 break;
168
169 // PC-relative relocations:
170 case R_HEX_B9_PCREL:
171 case R_HEX_B13_PCREL:
172 case R_HEX_B15_PCREL:
173 case R_HEX_6_PCREL_X:
174 case R_HEX_32_PCREL:
175 rs.processR_PC(type, offset, addend, sym);
176 continue;
177
178 // PLT-generating relocations:
179 case R_HEX_B9_PCREL_X:
180 case R_HEX_B15_PCREL_X:
181 case R_HEX_B22_PCREL:
182 case R_HEX_PLT_B22_PCREL:
183 case R_HEX_B22_PCREL_X:
184 case R_HEX_B32_PCREL_X:
185 rs.processR_PLT_PC(type, offset, addend, sym);
186 continue;
187 case R_HEX_GD_PLT_B22_PCREL:
188 case R_HEX_GD_PLT_B22_PCREL_X:
189 case R_HEX_GD_PLT_B32_PCREL_X:
190 // GD PLT: call foo@GDPLT becomes call __tls_get_addr.
191 // Record R_PLT_PC on the TLS symbol; finalizeRelocScan (called
192 // single-threaded after scanning) will create __tls_get_addr and
193 // rebind these relocations. We cannot access the symbol table here
194 // because scanSectionImpl runs in parallel.
195 sec.addReloc(r: {.expr: R_PLT_PC, .type: type, .offset: offset, .addend: addend, .sym: &sym});
196 continue;
197
198 // GOT-generating relocations:
199 case R_HEX_GOT_11_X:
200 case R_HEX_GOT_16_X:
201 case R_HEX_GOT_32_6_X:
202 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
203 expr = R_GOTPLT;
204 break;
205
206 // GOTREL relocations:
207 case R_HEX_GOTREL_11_X:
208 case R_HEX_GOTREL_16_X:
209 case R_HEX_GOTREL_32_6_X:
210 case R_HEX_GOTREL_HI16:
211 case R_HEX_GOTREL_LO16:
212 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
213 expr = R_GOTPLTREL;
214 break;
215
216 // TLS relocations:
217 case R_HEX_TPREL_11_X:
218 case R_HEX_TPREL_16:
219 case R_HEX_TPREL_16_X:
220 case R_HEX_TPREL_32_6_X:
221 case R_HEX_TPREL_HI16:
222 case R_HEX_TPREL_LO16:
223 if (rs.checkTlsLe(offset, sym, type))
224 continue;
225 expr = R_TPREL;
226 break;
227 case R_HEX_IE_32_6_X:
228 case R_HEX_IE_16_X:
229 case R_HEX_IE_HI16:
230 case R_HEX_IE_LO16:
231 // There is no IE to LE optimization.
232 rs.handleTlsIe<false>(ieExpr: R_GOT, type, offset, addend, sym);
233 continue;
234 case R_HEX_IE_GOT_11_X:
235 case R_HEX_IE_GOT_16_X:
236 case R_HEX_IE_GOT_32_6_X:
237 case R_HEX_IE_GOT_HI16:
238 case R_HEX_IE_GOT_LO16:
239 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
240 rs.handleTlsIe<false>(ieExpr: R_GOTPLT, type, offset, addend, sym);
241 continue;
242 case R_HEX_GD_GOT_11_X:
243 case R_HEX_GD_GOT_16_X:
244 case R_HEX_GD_GOT_32_6_X:
245 sym.setFlags(NEEDS_TLSGD);
246 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
247 sec.addReloc(r: {.expr: R_TLSGD_GOTPLT, .type: type, .offset: offset, .addend: addend, .sym: &sym});
248 continue;
249
250 default:
251 Err(ctx) << getErrorLoc(ctx, loc: sec.content().data() + offset)
252 << "unknown relocation (" << type.v << ") against symbol "
253 << &sym;
254 continue;
255 }
256 rs.process(expr, type, offset, sym, addend);
257 }
258}
259
260// There are (arguably too) many relocation masks for the DSP's
261// R_HEX_6_X type. The table below is used to select the correct mask
262// for the given instruction.
263struct InstructionMask {
264 uint32_t cmpMask;
265 uint32_t relocMask;
266};
267static const InstructionMask r6[] = {
268 {.cmpMask: 0x38000000, .relocMask: 0x0000201f}, {.cmpMask: 0x39000000, .relocMask: 0x0000201f},
269 {.cmpMask: 0x3e000000, .relocMask: 0x00001f80}, {.cmpMask: 0x3f000000, .relocMask: 0x00001f80},
270 {.cmpMask: 0x40000000, .relocMask: 0x000020f8}, {.cmpMask: 0x41000000, .relocMask: 0x000007e0},
271 {.cmpMask: 0x42000000, .relocMask: 0x000020f8}, {.cmpMask: 0x43000000, .relocMask: 0x000007e0},
272 {.cmpMask: 0x44000000, .relocMask: 0x000020f8}, {.cmpMask: 0x45000000, .relocMask: 0x000007e0},
273 {.cmpMask: 0x46000000, .relocMask: 0x000020f8}, {.cmpMask: 0x47000000, .relocMask: 0x000007e0},
274 {.cmpMask: 0x6a000000, .relocMask: 0x00001f80}, {.cmpMask: 0x7c000000, .relocMask: 0x001f2000},
275 {.cmpMask: 0x9a000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9b000000, .relocMask: 0x00000f60},
276 {.cmpMask: 0x9c000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9d000000, .relocMask: 0x00000f60},
277 {.cmpMask: 0x9f000000, .relocMask: 0x001f0100}, {.cmpMask: 0xab000000, .relocMask: 0x0000003f},
278 {.cmpMask: 0xad000000, .relocMask: 0x0000003f}, {.cmpMask: 0xaf000000, .relocMask: 0x00030078},
279 {.cmpMask: 0xd7000000, .relocMask: 0x006020e0}, {.cmpMask: 0xd8000000, .relocMask: 0x006020e0},
280 {.cmpMask: 0xdb000000, .relocMask: 0x006020e0}, {.cmpMask: 0xdf000000, .relocMask: 0x006020e0}};
281
282constexpr uint32_t instParsePacketEnd = 0x0000c000;
283
284static bool isDuplex(uint32_t insn) {
285 // Duplex forms have a fixed mask and parse bits 15:14 are always
286 // zero. Non-duplex insns will always have at least one bit set in the
287 // parse field.
288 return (instParsePacketEnd & insn) == 0;
289}
290
291static uint32_t findMaskR6(Ctx &ctx, uint32_t insn) {
292 if (isDuplex(insn))
293 return 0x03f00000;
294
295 for (InstructionMask i : r6)
296 if ((0xff000000 & insn) == i.cmpMask)
297 return i.relocMask;
298
299 Err(ctx) << "unrecognized instruction for 6_X relocation: 0x"
300 << utohexstr(X: insn, LowerCase: true);
301 return 0;
302}
303
304static uint32_t findMaskR8(uint32_t insn) {
305 if (isDuplex(insn))
306 return 0x03f00000;
307 if ((0xff000000 & insn) == 0xde000000)
308 return 0x00e020e8;
309 if ((0xff000000 & insn) == 0x3c000000)
310 return 0x0000207f;
311 return 0x00001fe0;
312}
313
314static uint32_t findMaskR11(uint32_t insn) {
315 if (isDuplex(insn))
316 return 0x03f00000;
317 if ((0xff000000 & insn) == 0xa1000000)
318 return 0x060020ff;
319 return 0x06003fe0;
320}
321
322static uint32_t findMaskR16(Ctx &ctx, uint32_t insn) {
323 if (isDuplex(insn))
324 return 0x03f00000;
325
326 // Clear the end-packet-parse bits:
327 insn = insn & ~instParsePacketEnd;
328
329 if ((0xff000000 & insn) == 0x48000000)
330 return 0x061f20ff;
331 if ((0xff000000 & insn) == 0x49000000)
332 return 0x061f3fe0;
333 if ((0xff000000 & insn) == 0x78000000)
334 return 0x00df3fe0;
335 if ((0xff000000 & insn) == 0xb0000000)
336 return 0x0fe03fe0;
337
338 if ((0xff802000 & insn) == 0x74000000)
339 return 0x00001fe0;
340 if ((0xff802000 & insn) == 0x74002000)
341 return 0x00001fe0;
342 if ((0xff802000 & insn) == 0x74800000)
343 return 0x00001fe0;
344 if ((0xff802000 & insn) == 0x74802000)
345 return 0x00001fe0;
346
347 for (InstructionMask i : r6)
348 if ((0xff000000 & insn) == i.cmpMask)
349 return i.relocMask;
350
351 Err(ctx) << "unrecognized instruction for 16_X type: 0x" << utohexstr(X: insn);
352 return 0;
353}
354
355static void or32le(uint8_t *p, int32_t v) { write32le(P: p, V: read32le(P: p) | v); }
356
357bool Hexagon::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
358 int64_t offset = dst - src;
359 switch (type) {
360 case llvm::ELF::R_HEX_B22_PCREL:
361 case llvm::ELF::R_HEX_PLT_B22_PCREL:
362 case llvm::ELF::R_HEX_GD_PLT_B22_PCREL:
363 case llvm::ELF::R_HEX_LD_PLT_B22_PCREL:
364 return llvm::isInt<22>(x: offset >> 2);
365 case llvm::ELF::R_HEX_B15_PCREL:
366 return llvm::isInt<15>(x: offset >> 2);
367 break;
368 case llvm::ELF::R_HEX_B13_PCREL:
369 return llvm::isInt<13>(x: offset >> 2);
370 break;
371 case llvm::ELF::R_HEX_B9_PCREL:
372 return llvm::isInt<9>(x: offset >> 2);
373 default:
374 return true;
375 }
376 llvm_unreachable("unsupported relocation");
377}
378
379bool Hexagon::needsThunk(RelExpr expr, RelType type, const InputFile *file,
380 uint64_t branchAddr, const Symbol &s,
381 int64_t a) const {
382 // Undefined weak symbols without PLT entries resolve to address zero.
383 // Thunks are not needed since the branch target is fixed.
384 if (s.isUndefined() && !s.isInPlt(ctx))
385 return false;
386 switch (type) {
387 case R_HEX_B22_PCREL:
388 case R_HEX_PLT_B22_PCREL:
389 case R_HEX_GD_PLT_B22_PCREL:
390 case R_HEX_LD_PLT_B22_PCREL:
391 case R_HEX_B15_PCREL:
392 case R_HEX_B13_PCREL:
393 case R_HEX_B9_PCREL: {
394 uint64_t dst = expr == R_PLT_PC ? s.getPltVA(ctx) : s.getVA(ctx, addend: a);
395 return !ctx.target->inBranchRange(type, src: branchAddr, dst);
396 }
397 default:
398 return false;
399 }
400}
401
402uint32_t Hexagon::getThunkSectionSpacing() const {
403 // B22_PCREL has a range of +/- 8 MiB (22-bit signed offset * 4).
404 // Pre-create ThunkSections at intervals below this to leave room for
405 // thunk growth.
406 return 0x800000 - 0x30000;
407}
408
409void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
410 uint64_t val) const {
411 switch (rel.type) {
412 case R_HEX_NONE:
413 break;
414 case R_HEX_6_PCREL_X:
415 case R_HEX_6_X:
416 or32le(p: loc, v: applyMask(mask: findMaskR6(ctx, insn: read32le(P: loc)), data: val));
417 break;
418 case R_HEX_8_X:
419 or32le(p: loc, v: applyMask(mask: findMaskR8(insn: read32le(P: loc)), data: val));
420 break;
421 case R_HEX_9_X:
422 or32le(p: loc, v: applyMask(mask: 0x00003fe0, data: val & 0x3f));
423 break;
424 case R_HEX_10_X:
425 or32le(p: loc, v: applyMask(mask: 0x00203fe0, data: val & 0x3f));
426 break;
427 case R_HEX_11_X:
428 case R_HEX_GD_GOT_11_X:
429 case R_HEX_IE_GOT_11_X:
430 case R_HEX_GOT_11_X:
431 case R_HEX_GOTREL_11_X:
432 case R_HEX_TPREL_11_X:
433 or32le(p: loc, v: applyMask(mask: findMaskR11(insn: read32le(P: loc)), data: val & 0x3f));
434 break;
435 case R_HEX_12_X:
436 or32le(p: loc, v: applyMask(mask: 0x000007e0, data: val));
437 break;
438 case R_HEX_16_X: // These relocs only have 6 effective bits.
439 case R_HEX_IE_16_X:
440 case R_HEX_IE_GOT_16_X:
441 case R_HEX_GD_GOT_16_X:
442 case R_HEX_GOT_16_X:
443 case R_HEX_GOTREL_16_X:
444 case R_HEX_TPREL_16_X:
445 or32le(p: loc, v: applyMask(mask: findMaskR16(ctx, insn: read32le(P: loc)), data: val & 0x3f));
446 break;
447 case R_HEX_TPREL_16:
448 or32le(p: loc, v: applyMask(mask: findMaskR16(ctx, insn: read32le(P: loc)), data: val & 0xffff));
449 break;
450 case R_HEX_32:
451 case R_HEX_32_PCREL:
452 case R_HEX_DTPREL_32:
453 or32le(p: loc, v: val);
454 break;
455 case R_HEX_32_6_X:
456 case R_HEX_GD_GOT_32_6_X:
457 case R_HEX_GOT_32_6_X:
458 case R_HEX_GOTREL_32_6_X:
459 case R_HEX_IE_GOT_32_6_X:
460 case R_HEX_IE_32_6_X:
461 case R_HEX_TPREL_32_6_X:
462 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
463 break;
464 case R_HEX_B9_PCREL:
465 checkInt(ctx, loc, v: val, n: 11, rel);
466 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val >> 2));
467 break;
468 case R_HEX_B9_PCREL_X:
469 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val & 0x3f));
470 break;
471 case R_HEX_B13_PCREL:
472 checkInt(ctx, loc, v: val, n: 15, rel);
473 or32le(p: loc, v: applyMask(mask: 0x00202ffe, data: val >> 2));
474 break;
475 case R_HEX_B15_PCREL:
476 checkInt(ctx, loc, v: val, n: 17, rel);
477 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val >> 2));
478 break;
479 case R_HEX_B15_PCREL_X:
480 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val & 0x3f));
481 break;
482 case R_HEX_B22_PCREL:
483 case R_HEX_GD_PLT_B22_PCREL:
484 case R_HEX_PLT_B22_PCREL:
485 checkInt(ctx, loc, v: val, n: 24, rel);
486 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val >> 2));
487 break;
488 case R_HEX_B22_PCREL_X:
489 case R_HEX_GD_PLT_B22_PCREL_X:
490 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val & 0x3f));
491 break;
492 case R_HEX_B32_PCREL_X:
493 case R_HEX_GD_PLT_B32_PCREL_X:
494 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
495 break;
496 case R_HEX_GOTREL_HI16:
497 case R_HEX_HI16:
498 case R_HEX_IE_GOT_HI16:
499 case R_HEX_IE_HI16:
500 case R_HEX_TPREL_HI16:
501 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val >> 16));
502 break;
503 case R_HEX_GOTREL_LO16:
504 case R_HEX_LO16:
505 case R_HEX_IE_GOT_LO16:
506 case R_HEX_IE_LO16:
507 case R_HEX_TPREL_LO16:
508 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val));
509 break;
510 default:
511 llvm_unreachable("unknown relocation");
512 }
513}
514
515void Hexagon::writePltHeader(uint8_t *buf) const {
516 const uint8_t pltData[] = {
517 0x00, 0x40, 0x00, 0x00, // { immext (#0)
518 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0
519 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn
520 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2
521 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1
522 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn
523 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker
524 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
525 };
526 memcpy(dest: buf, src: pltData, n: sizeof(pltData));
527
528 // Offset from PLT0 to the GOT.
529 uint64_t off = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA();
530 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: off);
531 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: off);
532}
533
534void Hexagon::writePlt(uint8_t *buf, const Symbol &sym,
535 uint64_t pltEntryAddr) const {
536 const uint8_t inst[] = {
537 0x00, 0x40, 0x00, 0x00, // { immext (#0)
538 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) }
539 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
540 0x00, 0xc0, 0x9c, 0x52, // jumpr r28
541 };
542 memcpy(dest: buf, src: inst, n: sizeof(inst));
543
544 uint64_t gotPltEntryAddr = sym.getGotPltVA(ctx);
545 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
546 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
547}
548
549RelType Hexagon::getDynRel(RelType type) const {
550 if (type == R_HEX_32)
551 return type;
552 return R_HEX_NONE;
553}
554
555int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
556 switch (type) {
557 case R_HEX_NONE:
558 case R_HEX_GLOB_DAT:
559 case R_HEX_JMP_SLOT:
560 return 0;
561 case R_HEX_32:
562 case R_HEX_RELATIVE:
563 case R_HEX_DTPMOD_32:
564 case R_HEX_DTPREL_32:
565 case R_HEX_TPREL_32:
566 return SignExtend64<32>(x: read32(ctx, p: buf));
567 default:
568 InternalErr(ctx, buf) << "cannot read addend for relocation " << type;
569 return 0;
570 }
571}
572
573namespace {
574class HexagonAttributesSection final : public SyntheticSection {
575public:
576 HexagonAttributesSection(Ctx &ctx)
577 : SyntheticSection(ctx, ".hexagon.attributes", SHT_HEXAGON_ATTRIBUTES, 0,
578 1) {}
579
580 size_t getSize() const override { return size; }
581 void writeTo(uint8_t *buf) override;
582
583 static constexpr StringRef vendor = "hexagon";
584 DenseMap<unsigned, unsigned> intAttr;
585 size_t size = 0;
586};
587} // namespace
588
589static HexagonAttributesSection *
590mergeAttributesSection(Ctx &ctx,
591 const SmallVector<InputSectionBase *, 0> &sections) {
592 ctx.in.hexagonAttributes = std::make_unique<HexagonAttributesSection>(args&: ctx);
593 auto &merged =
594 static_cast<HexagonAttributesSection &>(*ctx.in.hexagonAttributes);
595
596 // Collect all tags values from attributes section.
597 const auto &attributesTags = HexagonAttrs::getHexagonAttributeTags();
598 for (const InputSectionBase *sec : sections) {
599 HexagonAttributeParser parser;
600 if (Error e = parser.parse(section: sec->content(), endian: llvm::endianness::little))
601 Warn(ctx) << sec << ": " << std::move(e);
602 for (const auto &tag : attributesTags) {
603 switch (HexagonAttrs::AttrType(tag.attr)) {
604 case HexagonAttrs::ARCH:
605 case HexagonAttrs::HVXARCH:
606 if (auto i = parser.getAttributeValue(tag: tag.attr)) {
607 auto r = merged.intAttr.try_emplace(Key: tag.attr, Args&: *i);
608 if (!r.second)
609 if (r.first->second < *i)
610 r.first->second = *i;
611 }
612 continue;
613
614 case HexagonAttrs::HVXIEEEFP:
615 case HexagonAttrs::HVXQFLOAT:
616 case HexagonAttrs::ZREG:
617 case HexagonAttrs::AUDIO:
618 case HexagonAttrs::CABAC:
619 if (auto i = parser.getAttributeValue(tag: tag.attr)) {
620 auto r = merged.intAttr.try_emplace(Key: tag.attr, Args&: *i);
621 if (!r.second && r.first->second != *i) {
622 r.first->second |= *i;
623 }
624 }
625 continue;
626 }
627 }
628 }
629
630 // The total size of headers: format-version [ <section-length> "vendor-name"
631 // [ <file-tag> <size>.
632 size_t size = 5 + merged.vendor.size() + 1 + 5;
633 for (auto &attr : merged.intAttr)
634 if (attr.second != 0)
635 size += getULEB128Size(Value: attr.first) + getULEB128Size(Value: attr.second);
636 merged.size = size;
637 return &merged;
638}
639
640void HexagonAttributesSection::writeTo(uint8_t *buf) {
641 const size_t size = getSize();
642 uint8_t *const end = buf + size;
643 *buf = ELFAttrs::Format_Version;
644 write32(ctx, p: buf + 1, v: size - 1);
645 buf += 5;
646
647 memcpy(dest: buf, src: vendor.data(), n: vendor.size());
648 buf += vendor.size() + 1;
649
650 *buf = ELFAttrs::File;
651 write32(ctx, p: buf + 1, v: end - buf);
652 buf += 5;
653
654 for (auto &attr : intAttr) {
655 if (attr.second == 0)
656 continue;
657 buf += encodeULEB128(Value: attr.first, p: buf);
658 buf += encodeULEB128(Value: attr.second, p: buf);
659 }
660}
661
662void elf::mergeHexagonAttributesSections(Ctx &ctx) {
663 // Find the first input SHT_HEXAGON_ATTRIBUTES; return if not found.
664 size_t place =
665 llvm::find_if(Range&: ctx.inputSections,
666 P: [](auto *s) { return s->type == SHT_HEXAGON_ATTRIBUTES; }) -
667 ctx.inputSections.begin();
668 if (place == ctx.inputSections.size())
669 return;
670
671 // Extract all SHT_HEXAGON_ATTRIBUTES sections into `sections`.
672 SmallVector<InputSectionBase *, 0> sections;
673 llvm::erase_if(C&: ctx.inputSections, P: [&](InputSectionBase *s) {
674 if (s->type != SHT_HEXAGON_ATTRIBUTES)
675 return false;
676 sections.push_back(Elt: s);
677 return true;
678 });
679
680 // Add the merged section.
681 ctx.inputSections.insert(I: ctx.inputSections.begin() + place,
682 Elt: mergeAttributesSection(ctx, sections));
683}
684
685static bool isGDPLT(RelType type) {
686 switch (type) {
687 case R_HEX_GD_PLT_B22_PCREL:
688 case R_HEX_GD_PLT_B22_PCREL_X:
689 case R_HEX_GD_PLT_B32_PCREL_X:
690 return true;
691 default:
692 return false;
693 }
694}
695
696void Hexagon::finalizeRelocScan() {
697 Symbol *tga = nullptr;
698
699 // Scan for R_HEX_GD_PLT_* relocations (recorded as R_PLT_PC by
700 // scanSectionImpl) and rebind them to __tls_get_addr.
701 for (ELFFileBase *f : ctx.objectFiles) {
702 for (InputSectionBase *s : f->getSections()) {
703 auto *isec = dyn_cast_or_null<InputSection>(Val: s);
704 if (!isec || !isec->isLive())
705 continue;
706 for (Relocation &rel : isec->relocs()) {
707 if (rel.expr != R_PLT_PC || !isGDPLT(type: rel.type))
708 continue;
709 if (!tga) {
710 tga = ctx.symtab->addSymbol(newSym: Undefined{ctx.internalFile,
711 "__tls_get_addr", STB_GLOBAL,
712 STV_DEFAULT, STT_FUNC});
713 tga->isUsedInRegularObj = true;
714 tga->isPreemptible = true;
715 tga->setFlags(NEEDS_PLT | USED);
716 }
717 rel.sym = tga;
718 }
719 }
720 }
721}
722
723void elf::setHexagonTargetInfo(Ctx &ctx) { ctx.target.reset(p: new Hexagon(ctx)); }
724