1//===-- Hexagon.cpp -------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "InputFiles.h"
10#include "OutputSections.h"
11#include "RelocScan.h"
12#include "Symbols.h"
13#include "SyntheticSections.h"
14#include "Target.h"
15#include "Thunks.h"
16#include "lld/Common/ErrorHandler.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/BinaryFormat/ELF.h"
19#include "llvm/Support/ELFAttributes.h"
20#include "llvm/Support/Endian.h"
21#include "llvm/Support/HexagonAttributeParser.h"
22#include "llvm/Support/HexagonAttributes.h"
23#include "llvm/Support/LEB128.h"
24
25using namespace llvm;
26using namespace llvm::object;
27using namespace llvm::support::endian;
28using namespace llvm::ELF;
29using namespace lld;
30using namespace lld::elf;
31
32namespace {
33class Hexagon final : public TargetInfo {
34public:
35 Hexagon(Ctx &);
36 uint32_t calcEFlags() const override;
37 RelExpr getRelExpr(RelType type, const Symbol &s,
38 const uint8_t *loc) const override;
39 RelType getDynRel(RelType type) const override;
40 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
41 template <class ELFT, class RelTy>
42 void scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels);
43 void scanSection(InputSectionBase &sec) override {
44 elf::scanSection1<Hexagon, ELF32LE>(target&: *this, sec);
45 }
46 bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
47 uint64_t branchAddr, const Symbol &s,
48 int64_t a) const override;
49 bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
50 void relocate(uint8_t *loc, const Relocation &rel,
51 uint64_t val) const override;
52 void writePltHeader(uint8_t *buf) const override;
53 void writePlt(uint8_t *buf, const Symbol &sym,
54 uint64_t pltEntryAddr) const override;
55};
56} // namespace
57
58Hexagon::Hexagon(Ctx &ctx) : TargetInfo(ctx) {
59 pltRel = R_HEX_JMP_SLOT;
60 relativeRel = R_HEX_RELATIVE;
61 gotRel = R_HEX_GLOB_DAT;
62 symbolicRel = R_HEX_32;
63
64 gotBaseSymInGotPlt = true;
65 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The
66 // next 3 are reserved for the dynamic loader.
67 gotPltHeaderEntriesNum = 4;
68
69 pltEntrySize = 16;
70 pltHeaderSize = 32;
71
72 // Hexagon Linux uses 64K pages by default.
73 defaultMaxPageSize = 0x10000;
74 tlsGotRel = R_HEX_TPREL_32;
75 tlsModuleIndexRel = R_HEX_DTPMOD_32;
76 tlsOffsetRel = R_HEX_DTPREL_32;
77
78 needsThunks = true;
79}
80
81uint32_t Hexagon::calcEFlags() const {
82 // The architecture revision must always be equal to or greater than
83 // greatest revision in the list of inputs.
84 std::optional<uint32_t> ret;
85 for (InputFile *f : ctx.objectFiles) {
86 uint32_t eflags = cast<ObjFile<ELF32LE>>(Val: f)->getObj().getHeader().e_flags;
87 if (!ret || eflags > *ret)
88 ret = eflags;
89 }
90 return ret.value_or(/* Default Arch Rev: */ u: EF_HEXAGON_MACH_V68);
91}
92
93static uint32_t applyMask(uint32_t mask, uint32_t data) {
94 uint32_t result = 0;
95 size_t off = 0;
96
97 for (size_t bit = 0; bit != 32; ++bit) {
98 uint32_t valBit = (data >> off) & 1;
99 uint32_t maskBit = (mask >> bit) & 1;
100 if (maskBit) {
101 result |= (valBit << bit);
102 ++off;
103 }
104 }
105 return result;
106}
107
108// Only needed to support relocations used by relocateNonAlloc and
109// preprocessRelocs.
110RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
111 const uint8_t *loc) const {
112 switch (type) {
113 case R_HEX_NONE:
114 return R_NONE;
115 case R_HEX_32:
116 return R_ABS;
117 case R_HEX_32_PCREL:
118 return R_PC;
119 default:
120 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v
121 << ") against symbol " << &s;
122 return R_NONE;
123 }
124}
125
126template <class ELFT, class RelTy>
127void Hexagon::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels) {
128 RelocScan rs(ctx, &sec);
129 sec.relocations.reserve(N: rels.size());
130 for (auto it = rels.begin(); it != rels.end(); ++it) {
131 const RelTy &rel = *it;
132 uint32_t symIdx = rel.getSymbol(false);
133 Symbol &sym = sec.getFile<ELFT>()->getSymbol(symIdx);
134 uint64_t offset = rel.r_offset;
135 RelType type = rel.getType(false);
136 if (sym.isUndefined() && symIdx != 0 &&
137 rs.maybeReportUndefined(sym&: cast<Undefined>(Val&: sym), offset))
138 continue;
139 int64_t addend = rs.getAddend<ELFT>(rel, type);
140 RelExpr expr;
141 // Relocation types that only need a RelExpr set `expr` and break out of
142 // the switch to reach rs.process(). Types that need special handling
143 // (fast-path helpers, TLS) call a handler and use `continue`.
144 switch (type) {
145 case R_HEX_NONE:
146 continue;
147
148 // Absolute relocations:
149 case R_HEX_6_X:
150 case R_HEX_8_X:
151 case R_HEX_9_X:
152 case R_HEX_10_X:
153 case R_HEX_11_X:
154 case R_HEX_12_X:
155 case R_HEX_16_X:
156 case R_HEX_32:
157 case R_HEX_32_6_X:
158 case R_HEX_HI16:
159 case R_HEX_LO16:
160 case R_HEX_DTPREL_32:
161 expr = R_ABS;
162 break;
163
164 // PC-relative relocations:
165 case R_HEX_B9_PCREL:
166 case R_HEX_B13_PCREL:
167 case R_HEX_B15_PCREL:
168 case R_HEX_6_PCREL_X:
169 case R_HEX_32_PCREL:
170 rs.processR_PC(type, offset, addend, sym);
171 continue;
172
173 // PLT-generating relocations:
174 case R_HEX_B9_PCREL_X:
175 case R_HEX_B15_PCREL_X:
176 case R_HEX_B22_PCREL:
177 case R_HEX_PLT_B22_PCREL:
178 case R_HEX_B22_PCREL_X:
179 case R_HEX_B32_PCREL_X:
180 rs.processR_PLT_PC(type, offset, addend, sym);
181 continue;
182 case R_HEX_GD_PLT_B22_PCREL:
183 case R_HEX_GD_PLT_B22_PCREL_X:
184 case R_HEX_GD_PLT_B32_PCREL_X:
185 sym.setFlags(NEEDS_PLT);
186 sec.addReloc(r: {.expr: R_PLT_PC, .type: type, .offset: offset, .addend: addend, .sym: &sym});
187 continue;
188
189 // GOT-generating relocations:
190 case R_HEX_GOT_11_X:
191 case R_HEX_GOT_16_X:
192 case R_HEX_GOT_32_6_X:
193 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
194 expr = R_GOTPLT;
195 break;
196
197 // GOTREL relocations:
198 case R_HEX_GOTREL_11_X:
199 case R_HEX_GOTREL_16_X:
200 case R_HEX_GOTREL_32_6_X:
201 case R_HEX_GOTREL_HI16:
202 case R_HEX_GOTREL_LO16:
203 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
204 expr = R_GOTPLTREL;
205 break;
206
207 // TLS relocations:
208 case R_HEX_TPREL_11_X:
209 case R_HEX_TPREL_16:
210 case R_HEX_TPREL_16_X:
211 case R_HEX_TPREL_32_6_X:
212 case R_HEX_TPREL_HI16:
213 case R_HEX_TPREL_LO16:
214 if (rs.checkTlsLe(offset, sym, type))
215 continue;
216 expr = R_TPREL;
217 break;
218 case R_HEX_IE_32_6_X:
219 case R_HEX_IE_16_X:
220 case R_HEX_IE_HI16:
221 case R_HEX_IE_LO16:
222 // There is no IE to LE optimization.
223 rs.handleTlsIe<false>(ieExpr: R_GOT, type, offset, addend, sym);
224 continue;
225 case R_HEX_IE_GOT_11_X:
226 case R_HEX_IE_GOT_16_X:
227 case R_HEX_IE_GOT_32_6_X:
228 case R_HEX_IE_GOT_HI16:
229 case R_HEX_IE_GOT_LO16:
230 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
231 rs.handleTlsIe<false>(ieExpr: R_GOTPLT, type, offset, addend, sym);
232 continue;
233 case R_HEX_GD_GOT_11_X:
234 case R_HEX_GD_GOT_16_X:
235 case R_HEX_GD_GOT_32_6_X:
236 sym.setFlags(NEEDS_TLSGD);
237 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
238 sec.addReloc(r: {.expr: R_TLSGD_GOTPLT, .type: type, .offset: offset, .addend: addend, .sym: &sym});
239 continue;
240
241 default:
242 Err(ctx) << getErrorLoc(ctx, loc: sec.content().data() + offset)
243 << "unknown relocation (" << type.v << ") against symbol "
244 << &sym;
245 continue;
246 }
247 rs.process(expr, type, offset, sym, addend);
248 }
249}
250
251// There are (arguably too) many relocation masks for the DSP's
252// R_HEX_6_X type. The table below is used to select the correct mask
253// for the given instruction.
254struct InstructionMask {
255 uint32_t cmpMask;
256 uint32_t relocMask;
257};
258static const InstructionMask r6[] = {
259 {.cmpMask: 0x38000000, .relocMask: 0x0000201f}, {.cmpMask: 0x39000000, .relocMask: 0x0000201f},
260 {.cmpMask: 0x3e000000, .relocMask: 0x00001f80}, {.cmpMask: 0x3f000000, .relocMask: 0x00001f80},
261 {.cmpMask: 0x40000000, .relocMask: 0x000020f8}, {.cmpMask: 0x41000000, .relocMask: 0x000007e0},
262 {.cmpMask: 0x42000000, .relocMask: 0x000020f8}, {.cmpMask: 0x43000000, .relocMask: 0x000007e0},
263 {.cmpMask: 0x44000000, .relocMask: 0x000020f8}, {.cmpMask: 0x45000000, .relocMask: 0x000007e0},
264 {.cmpMask: 0x46000000, .relocMask: 0x000020f8}, {.cmpMask: 0x47000000, .relocMask: 0x000007e0},
265 {.cmpMask: 0x6a000000, .relocMask: 0x00001f80}, {.cmpMask: 0x7c000000, .relocMask: 0x001f2000},
266 {.cmpMask: 0x9a000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9b000000, .relocMask: 0x00000f60},
267 {.cmpMask: 0x9c000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9d000000, .relocMask: 0x00000f60},
268 {.cmpMask: 0x9f000000, .relocMask: 0x001f0100}, {.cmpMask: 0xab000000, .relocMask: 0x0000003f},
269 {.cmpMask: 0xad000000, .relocMask: 0x0000003f}, {.cmpMask: 0xaf000000, .relocMask: 0x00030078},
270 {.cmpMask: 0xd7000000, .relocMask: 0x006020e0}, {.cmpMask: 0xd8000000, .relocMask: 0x006020e0},
271 {.cmpMask: 0xdb000000, .relocMask: 0x006020e0}, {.cmpMask: 0xdf000000, .relocMask: 0x006020e0}};
272
273constexpr uint32_t instParsePacketEnd = 0x0000c000;
274
275static bool isDuplex(uint32_t insn) {
276 // Duplex forms have a fixed mask and parse bits 15:14 are always
277 // zero. Non-duplex insns will always have at least one bit set in the
278 // parse field.
279 return (instParsePacketEnd & insn) == 0;
280}
281
282static uint32_t findMaskR6(Ctx &ctx, uint32_t insn) {
283 if (isDuplex(insn))
284 return 0x03f00000;
285
286 for (InstructionMask i : r6)
287 if ((0xff000000 & insn) == i.cmpMask)
288 return i.relocMask;
289
290 Err(ctx) << "unrecognized instruction for 6_X relocation: 0x"
291 << utohexstr(X: insn, LowerCase: true);
292 return 0;
293}
294
295static uint32_t findMaskR8(uint32_t insn) {
296 if (isDuplex(insn))
297 return 0x03f00000;
298 if ((0xff000000 & insn) == 0xde000000)
299 return 0x00e020e8;
300 if ((0xff000000 & insn) == 0x3c000000)
301 return 0x0000207f;
302 return 0x00001fe0;
303}
304
305static uint32_t findMaskR11(uint32_t insn) {
306 if (isDuplex(insn))
307 return 0x03f00000;
308 if ((0xff000000 & insn) == 0xa1000000)
309 return 0x060020ff;
310 return 0x06003fe0;
311}
312
313static uint32_t findMaskR16(Ctx &ctx, uint32_t insn) {
314 if (isDuplex(insn))
315 return 0x03f00000;
316
317 // Clear the end-packet-parse bits:
318 insn = insn & ~instParsePacketEnd;
319
320 if ((0xff000000 & insn) == 0x48000000)
321 return 0x061f20ff;
322 if ((0xff000000 & insn) == 0x49000000)
323 return 0x061f3fe0;
324 if ((0xff000000 & insn) == 0x78000000)
325 return 0x00df3fe0;
326 if ((0xff000000 & insn) == 0xb0000000)
327 return 0x0fe03fe0;
328
329 if ((0xff802000 & insn) == 0x74000000)
330 return 0x00001fe0;
331 if ((0xff802000 & insn) == 0x74002000)
332 return 0x00001fe0;
333 if ((0xff802000 & insn) == 0x74800000)
334 return 0x00001fe0;
335 if ((0xff802000 & insn) == 0x74802000)
336 return 0x00001fe0;
337
338 for (InstructionMask i : r6)
339 if ((0xff000000 & insn) == i.cmpMask)
340 return i.relocMask;
341
342 Err(ctx) << "unrecognized instruction for 16_X type: 0x" << utohexstr(X: insn);
343 return 0;
344}
345
346static void or32le(uint8_t *p, int32_t v) { write32le(P: p, V: read32le(P: p) | v); }
347
348bool Hexagon::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
349 int64_t offset = dst - src;
350 switch (type) {
351 case llvm::ELF::R_HEX_B22_PCREL:
352 case llvm::ELF::R_HEX_PLT_B22_PCREL:
353 case llvm::ELF::R_HEX_GD_PLT_B22_PCREL:
354 case llvm::ELF::R_HEX_LD_PLT_B22_PCREL:
355 return llvm::isInt<22>(x: offset >> 2);
356 case llvm::ELF::R_HEX_B15_PCREL:
357 return llvm::isInt<15>(x: offset >> 2);
358 break;
359 case llvm::ELF::R_HEX_B13_PCREL:
360 return llvm::isInt<13>(x: offset >> 2);
361 break;
362 case llvm::ELF::R_HEX_B9_PCREL:
363 return llvm::isInt<9>(x: offset >> 2);
364 default:
365 return true;
366 }
367 llvm_unreachable("unsupported relocation");
368}
369
370bool Hexagon::needsThunk(RelExpr expr, RelType type, const InputFile *file,
371 uint64_t branchAddr, const Symbol &s,
372 int64_t a) const {
373 // Only check branch range for supported branch relocation types
374 switch (type) {
375 case R_HEX_B22_PCREL:
376 case R_HEX_PLT_B22_PCREL:
377 case R_HEX_GD_PLT_B22_PCREL:
378 case R_HEX_LD_PLT_B22_PCREL:
379 case R_HEX_B15_PCREL:
380 case R_HEX_B13_PCREL:
381 case R_HEX_B9_PCREL:
382 return !ctx.target->inBranchRange(type, src: branchAddr, dst: s.getVA(ctx, addend: a));
383 default:
384 return false;
385 }
386}
387
388void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
389 uint64_t val) const {
390 switch (rel.type) {
391 case R_HEX_NONE:
392 break;
393 case R_HEX_6_PCREL_X:
394 case R_HEX_6_X:
395 or32le(p: loc, v: applyMask(mask: findMaskR6(ctx, insn: read32le(P: loc)), data: val));
396 break;
397 case R_HEX_8_X:
398 or32le(p: loc, v: applyMask(mask: findMaskR8(insn: read32le(P: loc)), data: val));
399 break;
400 case R_HEX_9_X:
401 or32le(p: loc, v: applyMask(mask: 0x00003fe0, data: val & 0x3f));
402 break;
403 case R_HEX_10_X:
404 or32le(p: loc, v: applyMask(mask: 0x00203fe0, data: val & 0x3f));
405 break;
406 case R_HEX_11_X:
407 case R_HEX_GD_GOT_11_X:
408 case R_HEX_IE_GOT_11_X:
409 case R_HEX_GOT_11_X:
410 case R_HEX_GOTREL_11_X:
411 case R_HEX_TPREL_11_X:
412 or32le(p: loc, v: applyMask(mask: findMaskR11(insn: read32le(P: loc)), data: val & 0x3f));
413 break;
414 case R_HEX_12_X:
415 or32le(p: loc, v: applyMask(mask: 0x000007e0, data: val));
416 break;
417 case R_HEX_16_X: // These relocs only have 6 effective bits.
418 case R_HEX_IE_16_X:
419 case R_HEX_IE_GOT_16_X:
420 case R_HEX_GD_GOT_16_X:
421 case R_HEX_GOT_16_X:
422 case R_HEX_GOTREL_16_X:
423 case R_HEX_TPREL_16_X:
424 or32le(p: loc, v: applyMask(mask: findMaskR16(ctx, insn: read32le(P: loc)), data: val & 0x3f));
425 break;
426 case R_HEX_TPREL_16:
427 or32le(p: loc, v: applyMask(mask: findMaskR16(ctx, insn: read32le(P: loc)), data: val & 0xffff));
428 break;
429 case R_HEX_32:
430 case R_HEX_32_PCREL:
431 case R_HEX_DTPREL_32:
432 or32le(p: loc, v: val);
433 break;
434 case R_HEX_32_6_X:
435 case R_HEX_GD_GOT_32_6_X:
436 case R_HEX_GOT_32_6_X:
437 case R_HEX_GOTREL_32_6_X:
438 case R_HEX_IE_GOT_32_6_X:
439 case R_HEX_IE_32_6_X:
440 case R_HEX_TPREL_32_6_X:
441 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
442 break;
443 case R_HEX_B9_PCREL:
444 checkInt(ctx, loc, v: val, n: 11, rel);
445 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val >> 2));
446 break;
447 case R_HEX_B9_PCREL_X:
448 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val & 0x3f));
449 break;
450 case R_HEX_B13_PCREL:
451 checkInt(ctx, loc, v: val, n: 15, rel);
452 or32le(p: loc, v: applyMask(mask: 0x00202ffe, data: val >> 2));
453 break;
454 case R_HEX_B15_PCREL:
455 checkInt(ctx, loc, v: val, n: 17, rel);
456 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val >> 2));
457 break;
458 case R_HEX_B15_PCREL_X:
459 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val & 0x3f));
460 break;
461 case R_HEX_B22_PCREL:
462 case R_HEX_GD_PLT_B22_PCREL:
463 case R_HEX_PLT_B22_PCREL:
464 checkInt(ctx, loc, v: val, n: 24, rel);
465 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val >> 2));
466 break;
467 case R_HEX_B22_PCREL_X:
468 case R_HEX_GD_PLT_B22_PCREL_X:
469 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val & 0x3f));
470 break;
471 case R_HEX_B32_PCREL_X:
472 case R_HEX_GD_PLT_B32_PCREL_X:
473 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
474 break;
475 case R_HEX_GOTREL_HI16:
476 case R_HEX_HI16:
477 case R_HEX_IE_GOT_HI16:
478 case R_HEX_IE_HI16:
479 case R_HEX_TPREL_HI16:
480 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val >> 16));
481 break;
482 case R_HEX_GOTREL_LO16:
483 case R_HEX_LO16:
484 case R_HEX_IE_GOT_LO16:
485 case R_HEX_IE_LO16:
486 case R_HEX_TPREL_LO16:
487 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val));
488 break;
489 default:
490 llvm_unreachable("unknown relocation");
491 }
492}
493
494void Hexagon::writePltHeader(uint8_t *buf) const {
495 const uint8_t pltData[] = {
496 0x00, 0x40, 0x00, 0x00, // { immext (#0)
497 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0
498 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn
499 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2
500 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1
501 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn
502 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker
503 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
504 };
505 memcpy(dest: buf, src: pltData, n: sizeof(pltData));
506
507 // Offset from PLT0 to the GOT.
508 uint64_t off = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA();
509 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: off);
510 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: off);
511}
512
513void Hexagon::writePlt(uint8_t *buf, const Symbol &sym,
514 uint64_t pltEntryAddr) const {
515 const uint8_t inst[] = {
516 0x00, 0x40, 0x00, 0x00, // { immext (#0)
517 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) }
518 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
519 0x00, 0xc0, 0x9c, 0x52, // jumpr r28
520 };
521 memcpy(dest: buf, src: inst, n: sizeof(inst));
522
523 uint64_t gotPltEntryAddr = sym.getGotPltVA(ctx);
524 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
525 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
526}
527
528RelType Hexagon::getDynRel(RelType type) const {
529 if (type == R_HEX_32)
530 return type;
531 return R_HEX_NONE;
532}
533
534int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
535 switch (type) {
536 case R_HEX_NONE:
537 case R_HEX_GLOB_DAT:
538 case R_HEX_JMP_SLOT:
539 return 0;
540 case R_HEX_32:
541 case R_HEX_RELATIVE:
542 case R_HEX_DTPMOD_32:
543 case R_HEX_DTPREL_32:
544 case R_HEX_TPREL_32:
545 return SignExtend64<32>(x: read32(ctx, p: buf));
546 default:
547 InternalErr(ctx, buf) << "cannot read addend for relocation " << type;
548 return 0;
549 }
550}
551
552namespace {
553class HexagonAttributesSection final : public SyntheticSection {
554public:
555 HexagonAttributesSection(Ctx &ctx)
556 : SyntheticSection(ctx, ".hexagon.attributes", SHT_HEXAGON_ATTRIBUTES, 0,
557 1) {}
558
559 size_t getSize() const override { return size; }
560 void writeTo(uint8_t *buf) override;
561
562 static constexpr StringRef vendor = "hexagon";
563 DenseMap<unsigned, unsigned> intAttr;
564 size_t size = 0;
565};
566} // namespace
567
568static HexagonAttributesSection *
569mergeAttributesSection(Ctx &ctx,
570 const SmallVector<InputSectionBase *, 0> &sections) {
571 ctx.in.hexagonAttributes = std::make_unique<HexagonAttributesSection>(args&: ctx);
572 auto &merged =
573 static_cast<HexagonAttributesSection &>(*ctx.in.hexagonAttributes);
574
575 // Collect all tags values from attributes section.
576 const auto &attributesTags = HexagonAttrs::getHexagonAttributeTags();
577 for (const InputSectionBase *sec : sections) {
578 HexagonAttributeParser parser;
579 if (Error e = parser.parse(section: sec->content(), endian: llvm::endianness::little))
580 Warn(ctx) << sec << ": " << std::move(e);
581 for (const auto &tag : attributesTags) {
582 switch (HexagonAttrs::AttrType(tag.attr)) {
583 case HexagonAttrs::ARCH:
584 case HexagonAttrs::HVXARCH:
585 if (auto i = parser.getAttributeValue(tag: tag.attr)) {
586 auto r = merged.intAttr.try_emplace(Key: tag.attr, Args&: *i);
587 if (!r.second)
588 if (r.first->second < *i)
589 r.first->second = *i;
590 }
591 continue;
592
593 case HexagonAttrs::HVXIEEEFP:
594 case HexagonAttrs::HVXQFLOAT:
595 case HexagonAttrs::ZREG:
596 case HexagonAttrs::AUDIO:
597 case HexagonAttrs::CABAC:
598 if (auto i = parser.getAttributeValue(tag: tag.attr)) {
599 auto r = merged.intAttr.try_emplace(Key: tag.attr, Args&: *i);
600 if (!r.second && r.first->second != *i) {
601 r.first->second |= *i;
602 }
603 }
604 continue;
605 }
606 }
607 }
608
609 // The total size of headers: format-version [ <section-length> "vendor-name"
610 // [ <file-tag> <size>.
611 size_t size = 5 + merged.vendor.size() + 1 + 5;
612 for (auto &attr : merged.intAttr)
613 if (attr.second != 0)
614 size += getULEB128Size(Value: attr.first) + getULEB128Size(Value: attr.second);
615 merged.size = size;
616 return &merged;
617}
618
619void HexagonAttributesSection::writeTo(uint8_t *buf) {
620 const size_t size = getSize();
621 uint8_t *const end = buf + size;
622 *buf = ELFAttrs::Format_Version;
623 write32(ctx, p: buf + 1, v: size - 1);
624 buf += 5;
625
626 memcpy(dest: buf, src: vendor.data(), n: vendor.size());
627 buf += vendor.size() + 1;
628
629 *buf = ELFAttrs::File;
630 write32(ctx, p: buf + 1, v: end - buf);
631 buf += 5;
632
633 for (auto &attr : intAttr) {
634 if (attr.second == 0)
635 continue;
636 buf += encodeULEB128(Value: attr.first, p: buf);
637 buf += encodeULEB128(Value: attr.second, p: buf);
638 }
639}
640
641void elf::mergeHexagonAttributesSections(Ctx &ctx) {
642 // Find the first input SHT_HEXAGON_ATTRIBUTES; return if not found.
643 size_t place =
644 llvm::find_if(Range&: ctx.inputSections,
645 P: [](auto *s) { return s->type == SHT_HEXAGON_ATTRIBUTES; }) -
646 ctx.inputSections.begin();
647 if (place == ctx.inputSections.size())
648 return;
649
650 // Extract all SHT_HEXAGON_ATTRIBUTES sections into `sections`.
651 SmallVector<InputSectionBase *, 0> sections;
652 llvm::erase_if(C&: ctx.inputSections, P: [&](InputSectionBase *s) {
653 if (s->type != SHT_HEXAGON_ATTRIBUTES)
654 return false;
655 sections.push_back(Elt: s);
656 return true;
657 });
658
659 // Add the merged section.
660 ctx.inputSections.insert(I: ctx.inputSections.begin() + place,
661 Elt: mergeAttributesSection(ctx, sections));
662}
663
664void elf::setHexagonTargetInfo(Ctx &ctx) { ctx.target.reset(p: new Hexagon(ctx)); }
665