1//===-- Hexagon.cpp -------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "InputFiles.h"
10#include "OutputSections.h"
11#include "RelocScan.h"
12#include "SymbolTable.h"
13#include "Symbols.h"
14#include "SyntheticSections.h"
15#include "Target.h"
16#include "Thunks.h"
17#include "lld/Common/ErrorHandler.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/BinaryFormat/ELF.h"
20#include "llvm/Support/ELFAttributes.h"
21#include "llvm/Support/Endian.h"
22#include "llvm/Support/HexagonAttributeParser.h"
23#include "llvm/Support/HexagonAttributes.h"
24#include "llvm/Support/LEB128.h"
25
26using namespace llvm;
27using namespace llvm::object;
28using namespace llvm::support::endian;
29using namespace llvm::ELF;
30using namespace lld;
31using namespace lld::elf;
32
33namespace {
34class Hexagon final : public TargetInfo {
35public:
36 Hexagon(Ctx &);
37 uint32_t calcEFlags() const override;
38 RelExpr getRelExpr(RelType type, const Symbol &s,
39 const uint8_t *loc) const override;
40 RelType getDynRel(RelType type) const override;
41 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
42 template <class ELFT, class RelTy>
43 void scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels);
44 void scanSection(InputSectionBase &sec) override {
45 elf::scanSection1<Hexagon, ELF32LE>(target&: *this, sec);
46 }
47 void finalizeRelocScan() override;
48 bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
49 uint64_t branchAddr, const Symbol &s,
50 int64_t a) const override;
51 uint32_t getThunkSectionSpacing() const override;
52 bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
53 void relocate(uint8_t *loc, const Relocation &rel,
54 uint64_t val) const override;
55 void writePltHeader(uint8_t *buf) const override;
56 void writePlt(uint8_t *buf, const Symbol &sym,
57 uint64_t pltEntryAddr) const override;
58};
59} // namespace
60
61Hexagon::Hexagon(Ctx &ctx) : TargetInfo(ctx) {
62 pltRel = R_HEX_JMP_SLOT;
63 relativeRel = R_HEX_RELATIVE;
64 gotRel = R_HEX_GLOB_DAT;
65 symbolicRel = R_HEX_32;
66
67 gotBaseSymInGotPlt = true;
68 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The
69 // next 3 are reserved for the dynamic loader.
70 gotPltHeaderEntriesNum = 4;
71
72 pltEntrySize = 16;
73 pltHeaderSize = 32;
74
75 // Hexagon Linux uses 64K pages by default.
76 defaultMaxPageSize = 0x10000;
77 tlsGotRel = R_HEX_TPREL_32;
78 tlsModuleIndexRel = R_HEX_DTPMOD_32;
79 tlsOffsetRel = R_HEX_DTPREL_32;
80
81 needsThunks = true;
82}
83
84uint32_t Hexagon::calcEFlags() const {
85 // The architecture revision must always be equal to or greater than
86 // greatest revision in the list of inputs.
87 std::optional<uint32_t> ret;
88 for (InputFile *f : ctx.objectFiles) {
89 uint32_t eflags = cast<ObjFile<ELF32LE>>(Val: f)->getObj().getHeader().e_flags;
90 if (!ret || eflags > *ret)
91 ret = eflags;
92 }
93 return ret.value_or(/* Default Arch Rev: */ u: EF_HEXAGON_MACH_V68);
94}
95
96static uint32_t applyMask(uint32_t mask, uint32_t data) {
97 uint32_t result = 0;
98 size_t off = 0;
99
100 for (size_t bit = 0; bit != 32; ++bit) {
101 uint32_t valBit = (data >> off) & 1;
102 uint32_t maskBit = (mask >> bit) & 1;
103 if (maskBit) {
104 result |= (valBit << bit);
105 ++off;
106 }
107 }
108 return result;
109}
110
111// Only needed to support relocations used by relocateNonAlloc and
112// preprocessRelocs.
113RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
114 const uint8_t *loc) const {
115 switch (type) {
116 case R_HEX_NONE:
117 return R_NONE;
118 case R_HEX_32:
119 return R_ABS;
120 case R_HEX_32_PCREL:
121 return R_PC;
122 default:
123 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v
124 << ") against symbol " << &s;
125 return R_NONE;
126 }
127}
128
129template <class ELFT, class RelTy>
130void Hexagon::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels) {
131 RelocScan rs(ctx, &sec);
132 sec.relocations.reserve(N: rels.size());
133 for (auto it = rels.begin(); it != rels.end(); ++it) {
134 const RelTy &rel = *it;
135 uint32_t symIdx = rel.getSymbol(false);
136 Symbol &sym = sec.getFile<ELFT>()->getSymbol(symIdx);
137 uint64_t offset = rel.r_offset;
138 RelType type = rel.getType(false);
139 if (sym.isUndefined() && symIdx != 0 &&
140 rs.maybeReportUndefined(sym&: cast<Undefined>(Val&: sym), offset))
141 continue;
142 int64_t addend = rs.getAddend<ELFT>(rel, type);
143 RelExpr expr;
144 // Relocation types that only need a RelExpr set `expr` and break out of
145 // the switch to reach rs.process(). Types that need special handling
146 // (fast-path helpers, TLS) call a handler and use `continue`.
147 switch (type) {
148 case R_HEX_NONE:
149 continue;
150
151 // Absolute relocations:
152 case R_HEX_6_X:
153 case R_HEX_8_X:
154 case R_HEX_9_X:
155 case R_HEX_10_X:
156 case R_HEX_11_X:
157 case R_HEX_12_X:
158 case R_HEX_16_X:
159 case R_HEX_32:
160 case R_HEX_32_6_X:
161 case R_HEX_HI16:
162 case R_HEX_LO16:
163 case R_HEX_DTPREL_32:
164 expr = R_ABS;
165 break;
166
167 // PC-relative relocations:
168 case R_HEX_B9_PCREL:
169 case R_HEX_B13_PCREL:
170 case R_HEX_B15_PCREL:
171 case R_HEX_6_PCREL_X:
172 case R_HEX_32_PCREL:
173 rs.processR_PC(type, offset, addend, sym);
174 continue;
175
176 // PLT-generating relocations:
177 case R_HEX_B9_PCREL_X:
178 case R_HEX_B15_PCREL_X:
179 case R_HEX_B22_PCREL:
180 case R_HEX_PLT_B22_PCREL:
181 case R_HEX_B22_PCREL_X:
182 case R_HEX_B32_PCREL_X:
183 rs.processR_PLT_PC(type, offset, addend, sym);
184 continue;
185 case R_HEX_GD_PLT_B22_PCREL:
186 case R_HEX_GD_PLT_B22_PCREL_X:
187 case R_HEX_GD_PLT_B32_PCREL_X:
188 // GD PLT: call foo@GDPLT becomes call __tls_get_addr.
189 // Record R_PLT_PC on the TLS symbol; finalizeRelocScan (called
190 // single-threaded after scanning) will create __tls_get_addr and
191 // rebind these relocations. We cannot access the symbol table here
192 // because scanSectionImpl runs in parallel.
193 sec.addReloc(r: {.expr: R_PLT_PC, .type: type, .offset: offset, .addend: addend, .sym: &sym});
194 continue;
195
196 // GOT-generating relocations:
197 case R_HEX_GOT_11_X:
198 case R_HEX_GOT_16_X:
199 case R_HEX_GOT_32_6_X:
200 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
201 expr = R_GOTPLT;
202 break;
203
204 // GOTREL relocations:
205 case R_HEX_GOTREL_11_X:
206 case R_HEX_GOTREL_16_X:
207 case R_HEX_GOTREL_32_6_X:
208 case R_HEX_GOTREL_HI16:
209 case R_HEX_GOTREL_LO16:
210 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
211 expr = R_GOTPLTREL;
212 break;
213
214 // TLS relocations:
215 case R_HEX_TPREL_11_X:
216 case R_HEX_TPREL_16:
217 case R_HEX_TPREL_16_X:
218 case R_HEX_TPREL_32_6_X:
219 case R_HEX_TPREL_HI16:
220 case R_HEX_TPREL_LO16:
221 if (rs.checkTlsLe(offset, sym, type))
222 continue;
223 expr = R_TPREL;
224 break;
225 case R_HEX_IE_32_6_X:
226 case R_HEX_IE_16_X:
227 case R_HEX_IE_HI16:
228 case R_HEX_IE_LO16:
229 // There is no IE to LE optimization.
230 rs.handleTlsIe<false>(ieExpr: R_GOT, type, offset, addend, sym);
231 continue;
232 case R_HEX_IE_GOT_11_X:
233 case R_HEX_IE_GOT_16_X:
234 case R_HEX_IE_GOT_32_6_X:
235 case R_HEX_IE_GOT_HI16:
236 case R_HEX_IE_GOT_LO16:
237 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
238 rs.handleTlsIe<false>(ieExpr: R_GOTPLT, type, offset, addend, sym);
239 continue;
240 case R_HEX_GD_GOT_11_X:
241 case R_HEX_GD_GOT_16_X:
242 case R_HEX_GD_GOT_32_6_X:
243 sym.setFlags(NEEDS_TLSGD);
244 ctx.in.gotPlt->hasGotPltOffRel.store(i: true, m: std::memory_order_relaxed);
245 sec.addReloc(r: {.expr: R_TLSGD_GOTPLT, .type: type, .offset: offset, .addend: addend, .sym: &sym});
246 continue;
247
248 default:
249 Err(ctx) << getErrorLoc(ctx, loc: sec.content().data() + offset)
250 << "unknown relocation (" << type.v << ") against symbol "
251 << &sym;
252 continue;
253 }
254 rs.process(expr, type, offset, sym, addend);
255 }
256}
257
258// There are (arguably too) many relocation masks for the DSP's
259// R_HEX_6_X type. The table below is used to select the correct mask
260// for the given instruction.
261struct InstructionMask {
262 uint32_t cmpMask;
263 uint32_t relocMask;
264};
265static const InstructionMask r6[] = {
266 {.cmpMask: 0x38000000, .relocMask: 0x0000201f}, {.cmpMask: 0x39000000, .relocMask: 0x0000201f},
267 {.cmpMask: 0x3e000000, .relocMask: 0x00001f80}, {.cmpMask: 0x3f000000, .relocMask: 0x00001f80},
268 {.cmpMask: 0x40000000, .relocMask: 0x000020f8}, {.cmpMask: 0x41000000, .relocMask: 0x000007e0},
269 {.cmpMask: 0x42000000, .relocMask: 0x000020f8}, {.cmpMask: 0x43000000, .relocMask: 0x000007e0},
270 {.cmpMask: 0x44000000, .relocMask: 0x000020f8}, {.cmpMask: 0x45000000, .relocMask: 0x000007e0},
271 {.cmpMask: 0x46000000, .relocMask: 0x000020f8}, {.cmpMask: 0x47000000, .relocMask: 0x000007e0},
272 {.cmpMask: 0x6a000000, .relocMask: 0x00001f80}, {.cmpMask: 0x7c000000, .relocMask: 0x001f2000},
273 {.cmpMask: 0x9a000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9b000000, .relocMask: 0x00000f60},
274 {.cmpMask: 0x9c000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9d000000, .relocMask: 0x00000f60},
275 {.cmpMask: 0x9f000000, .relocMask: 0x001f0100}, {.cmpMask: 0xab000000, .relocMask: 0x0000003f},
276 {.cmpMask: 0xad000000, .relocMask: 0x0000003f}, {.cmpMask: 0xaf000000, .relocMask: 0x00030078},
277 {.cmpMask: 0xd7000000, .relocMask: 0x006020e0}, {.cmpMask: 0xd8000000, .relocMask: 0x006020e0},
278 {.cmpMask: 0xdb000000, .relocMask: 0x006020e0}, {.cmpMask: 0xdf000000, .relocMask: 0x006020e0}};
279
280constexpr uint32_t instParsePacketEnd = 0x0000c000;
281
282static bool isDuplex(uint32_t insn) {
283 // Duplex forms have a fixed mask and parse bits 15:14 are always
284 // zero. Non-duplex insns will always have at least one bit set in the
285 // parse field.
286 return (instParsePacketEnd & insn) == 0;
287}
288
289static uint32_t findMaskR6(Ctx &ctx, uint32_t insn) {
290 if (isDuplex(insn))
291 return 0x03f00000;
292
293 for (InstructionMask i : r6)
294 if ((0xff000000 & insn) == i.cmpMask)
295 return i.relocMask;
296
297 Err(ctx) << "unrecognized instruction for 6_X relocation: 0x"
298 << utohexstr(X: insn, LowerCase: true);
299 return 0;
300}
301
302static uint32_t findMaskR8(uint32_t insn) {
303 if (isDuplex(insn))
304 return 0x03f00000;
305 if ((0xff000000 & insn) == 0xde000000)
306 return 0x00e020e8;
307 if ((0xff000000 & insn) == 0x3c000000)
308 return 0x0000207f;
309 return 0x00001fe0;
310}
311
312static uint32_t findMaskR11(uint32_t insn) {
313 if (isDuplex(insn))
314 return 0x03f00000;
315 if ((0xff000000 & insn) == 0xa1000000)
316 return 0x060020ff;
317 return 0x06003fe0;
318}
319
320static uint32_t findMaskR16(Ctx &ctx, uint32_t insn) {
321 if (isDuplex(insn))
322 return 0x03f00000;
323
324 // Clear the end-packet-parse bits:
325 insn = insn & ~instParsePacketEnd;
326
327 if ((0xff000000 & insn) == 0x48000000)
328 return 0x061f20ff;
329 if ((0xff000000 & insn) == 0x49000000)
330 return 0x061f3fe0;
331 if ((0xff000000 & insn) == 0x78000000)
332 return 0x00df3fe0;
333 if ((0xff000000 & insn) == 0xb0000000)
334 return 0x0fe03fe0;
335
336 if ((0xff802000 & insn) == 0x74000000)
337 return 0x00001fe0;
338 if ((0xff802000 & insn) == 0x74002000)
339 return 0x00001fe0;
340 if ((0xff802000 & insn) == 0x74800000)
341 return 0x00001fe0;
342 if ((0xff802000 & insn) == 0x74802000)
343 return 0x00001fe0;
344
345 for (InstructionMask i : r6)
346 if ((0xff000000 & insn) == i.cmpMask)
347 return i.relocMask;
348
349 Err(ctx) << "unrecognized instruction for 16_X type: 0x" << utohexstr(X: insn);
350 return 0;
351}
352
353static void or32le(uint8_t *p, int32_t v) { write32le(P: p, V: read32le(P: p) | v); }
354
355bool Hexagon::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
356 int64_t offset = dst - src;
357 switch (type) {
358 case llvm::ELF::R_HEX_B22_PCREL:
359 case llvm::ELF::R_HEX_PLT_B22_PCREL:
360 case llvm::ELF::R_HEX_GD_PLT_B22_PCREL:
361 case llvm::ELF::R_HEX_LD_PLT_B22_PCREL:
362 return llvm::isInt<22>(x: offset >> 2);
363 case llvm::ELF::R_HEX_B15_PCREL:
364 return llvm::isInt<15>(x: offset >> 2);
365 break;
366 case llvm::ELF::R_HEX_B13_PCREL:
367 return llvm::isInt<13>(x: offset >> 2);
368 break;
369 case llvm::ELF::R_HEX_B9_PCREL:
370 return llvm::isInt<9>(x: offset >> 2);
371 default:
372 return true;
373 }
374 llvm_unreachable("unsupported relocation");
375}
376
377bool Hexagon::needsThunk(RelExpr expr, RelType type, const InputFile *file,
378 uint64_t branchAddr, const Symbol &s,
379 int64_t a) const {
380 // Undefined weak symbols without PLT entries resolve to address zero.
381 // Thunks are not needed since the branch target is fixed.
382 if (s.isUndefined() && !s.isInPlt(ctx))
383 return false;
384 switch (type) {
385 case R_HEX_B22_PCREL:
386 case R_HEX_PLT_B22_PCREL:
387 case R_HEX_GD_PLT_B22_PCREL:
388 case R_HEX_LD_PLT_B22_PCREL:
389 case R_HEX_B15_PCREL:
390 case R_HEX_B13_PCREL:
391 case R_HEX_B9_PCREL: {
392 uint64_t dst = expr == R_PLT_PC ? s.getPltVA(ctx) : s.getVA(ctx, addend: a);
393 return !ctx.target->inBranchRange(type, src: branchAddr, dst);
394 }
395 default:
396 return false;
397 }
398}
399
400uint32_t Hexagon::getThunkSectionSpacing() const {
401 // B22_PCREL has a range of +/- 8 MiB (22-bit signed offset * 4).
402 // Pre-create ThunkSections at intervals below this to leave room for
403 // thunk growth.
404 return 0x800000 - 0x30000;
405}
406
407void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
408 uint64_t val) const {
409 switch (rel.type) {
410 case R_HEX_NONE:
411 break;
412 case R_HEX_6_PCREL_X:
413 case R_HEX_6_X:
414 or32le(p: loc, v: applyMask(mask: findMaskR6(ctx, insn: read32le(P: loc)), data: val));
415 break;
416 case R_HEX_8_X:
417 or32le(p: loc, v: applyMask(mask: findMaskR8(insn: read32le(P: loc)), data: val));
418 break;
419 case R_HEX_9_X:
420 or32le(p: loc, v: applyMask(mask: 0x00003fe0, data: val & 0x3f));
421 break;
422 case R_HEX_10_X:
423 or32le(p: loc, v: applyMask(mask: 0x00203fe0, data: val & 0x3f));
424 break;
425 case R_HEX_11_X:
426 case R_HEX_GD_GOT_11_X:
427 case R_HEX_IE_GOT_11_X:
428 case R_HEX_GOT_11_X:
429 case R_HEX_GOTREL_11_X:
430 case R_HEX_TPREL_11_X:
431 or32le(p: loc, v: applyMask(mask: findMaskR11(insn: read32le(P: loc)), data: val & 0x3f));
432 break;
433 case R_HEX_12_X:
434 or32le(p: loc, v: applyMask(mask: 0x000007e0, data: val));
435 break;
436 case R_HEX_16_X: // These relocs only have 6 effective bits.
437 case R_HEX_IE_16_X:
438 case R_HEX_IE_GOT_16_X:
439 case R_HEX_GD_GOT_16_X:
440 case R_HEX_GOT_16_X:
441 case R_HEX_GOTREL_16_X:
442 case R_HEX_TPREL_16_X:
443 or32le(p: loc, v: applyMask(mask: findMaskR16(ctx, insn: read32le(P: loc)), data: val & 0x3f));
444 break;
445 case R_HEX_TPREL_16:
446 or32le(p: loc, v: applyMask(mask: findMaskR16(ctx, insn: read32le(P: loc)), data: val & 0xffff));
447 break;
448 case R_HEX_32:
449 case R_HEX_32_PCREL:
450 case R_HEX_DTPREL_32:
451 or32le(p: loc, v: val);
452 break;
453 case R_HEX_32_6_X:
454 case R_HEX_GD_GOT_32_6_X:
455 case R_HEX_GOT_32_6_X:
456 case R_HEX_GOTREL_32_6_X:
457 case R_HEX_IE_GOT_32_6_X:
458 case R_HEX_IE_32_6_X:
459 case R_HEX_TPREL_32_6_X:
460 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
461 break;
462 case R_HEX_B9_PCREL:
463 checkInt(ctx, loc, v: val, n: 11, rel);
464 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val >> 2));
465 break;
466 case R_HEX_B9_PCREL_X:
467 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val & 0x3f));
468 break;
469 case R_HEX_B13_PCREL:
470 checkInt(ctx, loc, v: val, n: 15, rel);
471 or32le(p: loc, v: applyMask(mask: 0x00202ffe, data: val >> 2));
472 break;
473 case R_HEX_B15_PCREL:
474 checkInt(ctx, loc, v: val, n: 17, rel);
475 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val >> 2));
476 break;
477 case R_HEX_B15_PCREL_X:
478 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val & 0x3f));
479 break;
480 case R_HEX_B22_PCREL:
481 case R_HEX_GD_PLT_B22_PCREL:
482 case R_HEX_PLT_B22_PCREL:
483 checkInt(ctx, loc, v: val, n: 24, rel);
484 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val >> 2));
485 break;
486 case R_HEX_B22_PCREL_X:
487 case R_HEX_GD_PLT_B22_PCREL_X:
488 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val & 0x3f));
489 break;
490 case R_HEX_B32_PCREL_X:
491 case R_HEX_GD_PLT_B32_PCREL_X:
492 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
493 break;
494 case R_HEX_GOTREL_HI16:
495 case R_HEX_HI16:
496 case R_HEX_IE_GOT_HI16:
497 case R_HEX_IE_HI16:
498 case R_HEX_TPREL_HI16:
499 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val >> 16));
500 break;
501 case R_HEX_GOTREL_LO16:
502 case R_HEX_LO16:
503 case R_HEX_IE_GOT_LO16:
504 case R_HEX_IE_LO16:
505 case R_HEX_TPREL_LO16:
506 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val));
507 break;
508 default:
509 llvm_unreachable("unknown relocation");
510 }
511}
512
513void Hexagon::writePltHeader(uint8_t *buf) const {
514 const uint8_t pltData[] = {
515 0x00, 0x40, 0x00, 0x00, // { immext (#0)
516 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0
517 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn
518 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2
519 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1
520 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn
521 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker
522 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
523 };
524 memcpy(dest: buf, src: pltData, n: sizeof(pltData));
525
526 // Offset from PLT0 to the GOT.
527 uint64_t off = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA();
528 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: off);
529 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: off);
530}
531
532void Hexagon::writePlt(uint8_t *buf, const Symbol &sym,
533 uint64_t pltEntryAddr) const {
534 const uint8_t inst[] = {
535 0x00, 0x40, 0x00, 0x00, // { immext (#0)
536 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) }
537 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
538 0x00, 0xc0, 0x9c, 0x52, // jumpr r28
539 };
540 memcpy(dest: buf, src: inst, n: sizeof(inst));
541
542 uint64_t gotPltEntryAddr = sym.getGotPltVA(ctx);
543 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
544 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
545}
546
547RelType Hexagon::getDynRel(RelType type) const {
548 if (type == R_HEX_32)
549 return type;
550 return R_HEX_NONE;
551}
552
553int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
554 switch (type) {
555 case R_HEX_NONE:
556 case R_HEX_GLOB_DAT:
557 case R_HEX_JMP_SLOT:
558 return 0;
559 case R_HEX_32:
560 case R_HEX_RELATIVE:
561 case R_HEX_DTPMOD_32:
562 case R_HEX_DTPREL_32:
563 case R_HEX_TPREL_32:
564 return SignExtend64<32>(x: read32(ctx, p: buf));
565 default:
566 InternalErr(ctx, buf) << "cannot read addend for relocation " << type;
567 return 0;
568 }
569}
570
571namespace {
572class HexagonAttributesSection final : public SyntheticSection {
573public:
574 HexagonAttributesSection(Ctx &ctx)
575 : SyntheticSection(ctx, ".hexagon.attributes", SHT_HEXAGON_ATTRIBUTES, 0,
576 1) {}
577
578 size_t getSize() const override { return size; }
579 void writeTo(uint8_t *buf) override;
580
581 static constexpr StringRef vendor = "hexagon";
582 DenseMap<unsigned, unsigned> intAttr;
583 size_t size = 0;
584};
585} // namespace
586
587static HexagonAttributesSection *
588mergeAttributesSection(Ctx &ctx,
589 const SmallVector<InputSectionBase *, 0> &sections) {
590 ctx.in.hexagonAttributes = std::make_unique<HexagonAttributesSection>(args&: ctx);
591 auto &merged =
592 static_cast<HexagonAttributesSection &>(*ctx.in.hexagonAttributes);
593
594 // Collect all tags values from attributes section.
595 const auto &attributesTags = HexagonAttrs::getHexagonAttributeTags();
596 for (const InputSectionBase *sec : sections) {
597 HexagonAttributeParser parser;
598 if (Error e = parser.parse(section: sec->content(), endian: llvm::endianness::little))
599 Warn(ctx) << sec << ": " << std::move(e);
600 for (const auto &tag : attributesTags) {
601 switch (HexagonAttrs::AttrType(tag.attr)) {
602 case HexagonAttrs::ARCH:
603 case HexagonAttrs::HVXARCH:
604 if (auto i = parser.getAttributeValue(tag: tag.attr)) {
605 auto r = merged.intAttr.try_emplace(Key: tag.attr, Args&: *i);
606 if (!r.second)
607 if (r.first->second < *i)
608 r.first->second = *i;
609 }
610 continue;
611
612 case HexagonAttrs::HVXIEEEFP:
613 case HexagonAttrs::HVXQFLOAT:
614 case HexagonAttrs::ZREG:
615 case HexagonAttrs::AUDIO:
616 case HexagonAttrs::CABAC:
617 if (auto i = parser.getAttributeValue(tag: tag.attr)) {
618 auto r = merged.intAttr.try_emplace(Key: tag.attr, Args&: *i);
619 if (!r.second && r.first->second != *i) {
620 r.first->second |= *i;
621 }
622 }
623 continue;
624 }
625 }
626 }
627
628 // The total size of headers: format-version [ <section-length> "vendor-name"
629 // [ <file-tag> <size>.
630 size_t size = 5 + merged.vendor.size() + 1 + 5;
631 for (auto &attr : merged.intAttr)
632 if (attr.second != 0)
633 size += getULEB128Size(Value: attr.first) + getULEB128Size(Value: attr.second);
634 merged.size = size;
635 return &merged;
636}
637
638void HexagonAttributesSection::writeTo(uint8_t *buf) {
639 const size_t size = getSize();
640 uint8_t *const end = buf + size;
641 *buf = ELFAttrs::Format_Version;
642 write32(ctx, p: buf + 1, v: size - 1);
643 buf += 5;
644
645 memcpy(dest: buf, src: vendor.data(), n: vendor.size());
646 buf += vendor.size() + 1;
647
648 *buf = ELFAttrs::File;
649 write32(ctx, p: buf + 1, v: end - buf);
650 buf += 5;
651
652 for (auto &attr : intAttr) {
653 if (attr.second == 0)
654 continue;
655 buf += encodeULEB128(Value: attr.first, p: buf);
656 buf += encodeULEB128(Value: attr.second, p: buf);
657 }
658}
659
660void elf::mergeHexagonAttributesSections(Ctx &ctx) {
661 // Find the first input SHT_HEXAGON_ATTRIBUTES; return if not found.
662 size_t place =
663 llvm::find_if(Range&: ctx.inputSections,
664 P: [](auto *s) { return s->type == SHT_HEXAGON_ATTRIBUTES; }) -
665 ctx.inputSections.begin();
666 if (place == ctx.inputSections.size())
667 return;
668
669 // Extract all SHT_HEXAGON_ATTRIBUTES sections into `sections`.
670 SmallVector<InputSectionBase *, 0> sections;
671 llvm::erase_if(C&: ctx.inputSections, P: [&](InputSectionBase *s) {
672 if (s->type != SHT_HEXAGON_ATTRIBUTES)
673 return false;
674 sections.push_back(Elt: s);
675 return true;
676 });
677
678 // Add the merged section.
679 ctx.inputSections.insert(I: ctx.inputSections.begin() + place,
680 Elt: mergeAttributesSection(ctx, sections));
681}
682
683static bool isGDPLT(RelType type) {
684 switch (type) {
685 case R_HEX_GD_PLT_B22_PCREL:
686 case R_HEX_GD_PLT_B22_PCREL_X:
687 case R_HEX_GD_PLT_B32_PCREL_X:
688 return true;
689 default:
690 return false;
691 }
692}
693
694void Hexagon::finalizeRelocScan() {
695 Symbol *tga = nullptr;
696
697 // Scan for R_HEX_GD_PLT_* relocations (recorded as R_PLT_PC by
698 // scanSectionImpl) and rebind them to __tls_get_addr.
699 for (ELFFileBase *f : ctx.objectFiles) {
700 for (InputSectionBase *s : f->getSections()) {
701 auto *isec = dyn_cast_or_null<InputSection>(Val: s);
702 if (!isec || !isec->isLive())
703 continue;
704 for (Relocation &rel : isec->relocs()) {
705 if (rel.expr != R_PLT_PC || !isGDPLT(type: rel.type))
706 continue;
707 if (!tga) {
708 tga = ctx.symtab->addSymbol(newSym: Undefined{ctx.internalFile,
709 "__tls_get_addr", STB_GLOBAL,
710 STV_DEFAULT, STT_FUNC});
711 tga->isUsedInRegularObj = true;
712 tga->isPreemptible = true;
713 tga->setFlags(NEEDS_PLT | USED);
714 }
715 rel.sym = tga;
716 }
717 }
718 }
719}
720
721void elf::setHexagonTargetInfo(Ctx &ctx) { ctx.target.reset(p: new Hexagon(ctx)); }
722