1//===- LoongArch.cpp ------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "InputFiles.h"
10#include "OutputSections.h"
11#include "Symbols.h"
12#include "SyntheticSections.h"
13#include "Target.h"
14#include "llvm/BinaryFormat/ELF.h"
15#include "llvm/Support/LEB128.h"
16
17using namespace llvm;
18using namespace llvm::object;
19using namespace llvm::support::endian;
20using namespace llvm::ELF;
21using namespace lld;
22using namespace lld::elf;
23
24namespace {
25class LoongArch final : public TargetInfo {
26public:
27 LoongArch(Ctx &);
28 uint32_t calcEFlags() const override;
29 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
30 void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
31 void writeIgotPlt(uint8_t *buf, const Symbol &s) const override;
32 void writePltHeader(uint8_t *buf) const override;
33 void writePlt(uint8_t *buf, const Symbol &sym,
34 uint64_t pltEntryAddr) const override;
35 RelType getDynRel(RelType type) const override;
36 RelExpr getRelExpr(RelType type, const Symbol &s,
37 const uint8_t *loc) const override;
38 bool usesOnlyLowPageBits(RelType type) const override;
39 void relocate(uint8_t *loc, const Relocation &rel,
40 uint64_t val) const override;
41 bool relaxOnce(int pass) const override;
42 bool synthesizeAlign(uint64_t &dot, InputSection *sec) override;
43 RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override;
44 void relocateAlloc(InputSection &sec, uint8_t *buf) const override;
45 void finalizeRelax(int passes) const override;
46
47private:
48 void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
49 void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
50 bool tryGotToPCRel(uint8_t *loc, const Relocation &rHi20,
51 const Relocation &rLo12, uint64_t secAddr) const;
52 template <class ELFT, class RelTy>
53 bool synthesizeAlignForInput(uint64_t &dot, InputSection *sec,
54 Relocs<RelTy> rels);
55 template <class ELFT, class RelTy>
56 void finalizeSynthesizeAligns(uint64_t &dot, InputSection *sec,
57 Relocs<RelTy> rels);
58 template <class ELFT>
59 bool synthesizeAlignAux(uint64_t &dot, InputSection *sec);
60
61 // The following two variables are used by synthesized ALIGN relocations.
62 InputSection *baseSec = nullptr;
63 // r_offset and r_addend pairs.
64 SmallVector<std::pair<uint64_t, uint64_t>, 0> synthesizedAligns;
65};
66} // end anonymous namespace
67
68namespace {
69enum Op {
70 SUB_W = 0x00110000,
71 SUB_D = 0x00118000,
72 BREAK = 0x002a0000,
73 SRLI_W = 0x00448000,
74 SRLI_D = 0x00450000,
75 ADDI_W = 0x02800000,
76 ADDI_D = 0x02c00000,
77 ANDI = 0x03400000,
78 ORI = 0x03800000,
79 LU12I_W = 0x14000000,
80 PCADDI = 0x18000000,
81 PCADDU12I = 0x1c000000,
82 PCALAU12I = 0x1a000000,
83 LD_W = 0x28800000,
84 LD_D = 0x28c00000,
85 JIRL = 0x4c000000,
86 B = 0x50000000,
87 BL = 0x54000000,
88};
89
90enum Reg {
91 R_ZERO = 0,
92 R_RA = 1,
93 R_TP = 2,
94 R_A0 = 4,
95 R_T0 = 12,
96 R_T1 = 13,
97 R_T2 = 14,
98 R_T3 = 15,
99};
100} // namespace
101
102// Mask out the input's lowest 12 bits for use with `pcalau12i`, in sequences
103// like `pcalau12i + addi.[wd]` or `pcalau12i + {ld,st}.*` where the `pcalau12i`
104// produces a PC-relative intermediate value with the lowest 12 bits zeroed (the
105// "page") for the next instruction to add in the "page offset". (`pcalau12i`
106// stands for something like "PC ALigned Add Upper that starts from the 12th
107// bit, Immediate".)
108//
109// Here a "page" is in fact just another way to refer to the 12-bit range
110// allowed by the immediate field of the addi/ld/st instructions, and not
111// related to the system or the kernel's actual page size. The semantics happen
112// to match the AArch64 `adrp`, so the concept of "page" is borrowed here.
113static uint64_t getLoongArchPage(uint64_t p) {
114 return p & ~static_cast<uint64_t>(0xfff);
115}
116
117static uint32_t lo12(uint32_t val) { return val & 0xfff; }
118
119// Calculate the adjusted page delta between dest and PC.
120uint64_t elf::getLoongArchPageDelta(uint64_t dest, uint64_t pc, RelType type) {
121 // Note that if the sequence being relocated is `pcalau12i + addi.d + lu32i.d
122 // + lu52i.d`, they must be adjacent so that we can infer the PC of
123 // `pcalau12i` when calculating the page delta for the other two instructions
124 // (lu32i.d and lu52i.d). Compensate all the sign-extensions is a bit
125 // complicated. Just use psABI recommended algorithm.
126 uint64_t pcalau12i_pc;
127 switch (type) {
128 case R_LARCH_PCALA64_LO20:
129 case R_LARCH_GOT64_PC_LO20:
130 case R_LARCH_TLS_IE64_PC_LO20:
131 case R_LARCH_TLS_DESC64_PC_LO20:
132 pcalau12i_pc = pc - 8;
133 break;
134 case R_LARCH_PCALA64_HI12:
135 case R_LARCH_GOT64_PC_HI12:
136 case R_LARCH_TLS_IE64_PC_HI12:
137 case R_LARCH_TLS_DESC64_PC_HI12:
138 pcalau12i_pc = pc - 12;
139 break;
140 default:
141 pcalau12i_pc = pc;
142 break;
143 }
144 uint64_t result = getLoongArchPage(p: dest) - getLoongArchPage(p: pcalau12i_pc);
145 if (dest & 0x800)
146 result += 0x1000 - 0x1'0000'0000;
147 if (result & 0x8000'0000)
148 result += 0x1'0000'0000;
149 return result;
150}
151
152static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
153
154static uint32_t insn(uint32_t op, uint32_t d, uint32_t j, uint32_t k) {
155 return op | d | (j << 5) | (k << 10);
156}
157
158// Extract bits v[begin:end], where range is inclusive.
159static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) {
160 return begin == 63 ? v >> end : (v & ((1ULL << (begin + 1)) - 1)) >> end;
161}
162
163static uint32_t getD5(uint64_t v) { return extractBits(v, begin: 4, end: 0); }
164
165static uint32_t getJ5(uint64_t v) { return extractBits(v, begin: 9, end: 5); }
166
167static uint32_t setD5k16(uint32_t insn, uint32_t imm) {
168 uint32_t immLo = extractBits(v: imm, begin: 15, end: 0);
169 uint32_t immHi = extractBits(v: imm, begin: 20, end: 16);
170 return (insn & 0xfc0003e0) | (immLo << 10) | immHi;
171}
172
173static uint32_t setD10k16(uint32_t insn, uint32_t imm) {
174 uint32_t immLo = extractBits(v: imm, begin: 15, end: 0);
175 uint32_t immHi = extractBits(v: imm, begin: 25, end: 16);
176 return (insn & 0xfc000000) | (immLo << 10) | immHi;
177}
178
179static uint32_t setJ20(uint32_t insn, uint32_t imm) {
180 return (insn & 0xfe00001f) | (extractBits(v: imm, begin: 19, end: 0) << 5);
181}
182
183static uint32_t setJ5(uint32_t insn, uint32_t imm) {
184 return (insn & 0xfffffc1f) | (extractBits(v: imm, begin: 4, end: 0) << 5);
185}
186
187static uint32_t setK12(uint32_t insn, uint32_t imm) {
188 return (insn & 0xffc003ff) | (extractBits(v: imm, begin: 11, end: 0) << 10);
189}
190
191static uint32_t setK16(uint32_t insn, uint32_t imm) {
192 return (insn & 0xfc0003ff) | (extractBits(v: imm, begin: 15, end: 0) << 10);
193}
194
195static bool isJirl(uint32_t insn) {
196 return (insn & 0xfc000000) == JIRL;
197}
198
199static void handleUleb128(Ctx &ctx, uint8_t *loc, uint64_t val) {
200 const uint32_t maxcount = 1 + 64 / 7;
201 uint32_t count;
202 const char *error = nullptr;
203 uint64_t orig = decodeULEB128(p: loc, n: &count, end: nullptr, error: &error);
204 if (count > maxcount || (count == maxcount && error))
205 Err(ctx) << getErrorLoc(ctx, loc) << "extra space for uleb128";
206 uint64_t mask = count < maxcount ? (1ULL << 7 * count) - 1 : -1ULL;
207 encodeULEB128(Value: (orig + val) & mask, p: loc, PadTo: count);
208}
209
210LoongArch::LoongArch(Ctx &ctx) : TargetInfo(ctx) {
211 // The LoongArch ISA itself does not have a limit on page sizes. According to
212 // the ISA manual, the PS (page size) field in MTLB entries and CSR.STLBPS is
213 // 6 bits wide, meaning the maximum page size is 2^63 which is equivalent to
214 // "unlimited".
215 // However, practically the maximum usable page size is constrained by the
216 // kernel implementation, and 64KiB is the biggest non-huge page size
217 // supported by Linux as of v6.4. The most widespread page size in use,
218 // though, is 16KiB.
219 defaultCommonPageSize = 16384;
220 defaultMaxPageSize = 65536;
221 write32le(P: trapInstr.data(), V: BREAK); // break 0
222
223 copyRel = R_LARCH_COPY;
224 pltRel = R_LARCH_JUMP_SLOT;
225 relativeRel = R_LARCH_RELATIVE;
226 iRelativeRel = R_LARCH_IRELATIVE;
227
228 if (ctx.arg.is64) {
229 symbolicRel = R_LARCH_64;
230 tlsModuleIndexRel = R_LARCH_TLS_DTPMOD64;
231 tlsOffsetRel = R_LARCH_TLS_DTPREL64;
232 tlsGotRel = R_LARCH_TLS_TPREL64;
233 tlsDescRel = R_LARCH_TLS_DESC64;
234 } else {
235 symbolicRel = R_LARCH_32;
236 tlsModuleIndexRel = R_LARCH_TLS_DTPMOD32;
237 tlsOffsetRel = R_LARCH_TLS_DTPREL32;
238 tlsGotRel = R_LARCH_TLS_TPREL32;
239 tlsDescRel = R_LARCH_TLS_DESC32;
240 }
241
242 gotRel = symbolicRel;
243
244 // .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map
245 gotPltHeaderEntriesNum = 2;
246
247 pltHeaderSize = 32;
248 pltEntrySize = 16;
249 ipltEntrySize = 16;
250}
251
252static uint32_t getEFlags(Ctx &ctx, const InputFile *f) {
253 if (ctx.arg.is64)
254 return cast<ObjFile<ELF64LE>>(Val: f)->getObj().getHeader().e_flags;
255 return cast<ObjFile<ELF32LE>>(Val: f)->getObj().getHeader().e_flags;
256}
257
258static bool inputFileHasCode(const InputFile *f) {
259 for (const auto *sec : f->getSections())
260 if (sec && sec->flags & SHF_EXECINSTR)
261 return true;
262
263 return false;
264}
265
266uint32_t LoongArch::calcEFlags() const {
267 // If there are only binary input files (from -b binary), use a
268 // value of 0 for the ELF header flags.
269 if (ctx.objectFiles.empty())
270 return 0;
271
272 uint32_t target = 0;
273 const InputFile *targetFile;
274 for (const InputFile *f : ctx.objectFiles) {
275 // Do not enforce ABI compatibility if the input file does not contain code.
276 // This is useful for allowing linkage with data-only object files produced
277 // with tools like objcopy, that have zero e_flags.
278 if (!inputFileHasCode(f))
279 continue;
280
281 // Take the first non-zero e_flags as the reference.
282 uint32_t flags = getEFlags(ctx, f);
283 if (target == 0 && flags != 0) {
284 target = flags;
285 targetFile = f;
286 }
287
288 if ((flags & EF_LOONGARCH_ABI_MODIFIER_MASK) !=
289 (target & EF_LOONGARCH_ABI_MODIFIER_MASK))
290 ErrAlways(ctx) << f
291 << ": cannot link object files with different ABI from "
292 << targetFile;
293
294 // We cannot process psABI v1.x / object ABI v0 files (containing stack
295 // relocations), unlike ld.bfd.
296 //
297 // Instead of blindly accepting every v0 object and only failing at
298 // relocation processing time, just disallow interlink altogether. We
299 // don't expect significant usage of object ABI v0 in the wild (the old
300 // world may continue using object ABI v0 for a while, but as it's not
301 // binary-compatible with the upstream i.e. new-world ecosystem, it's not
302 // being considered here).
303 //
304 // There are briefly some new-world systems with object ABI v0 binaries too.
305 // It is because these systems were built before the new ABI was finalized.
306 // These are not supported either due to the extremely small number of them,
307 // and the few impacted users are advised to simply rebuild world or
308 // reinstall a recent system.
309 if ((flags & EF_LOONGARCH_OBJABI_MASK) != EF_LOONGARCH_OBJABI_V1)
310 ErrAlways(ctx) << f << ": unsupported object file ABI version";
311 }
312
313 return target;
314}
315
316int64_t LoongArch::getImplicitAddend(const uint8_t *buf, RelType type) const {
317 switch (type) {
318 default:
319 InternalErr(ctx, buf) << "cannot read addend for relocation " << type;
320 return 0;
321 case R_LARCH_32:
322 case R_LARCH_TLS_DTPMOD32:
323 case R_LARCH_TLS_DTPREL32:
324 case R_LARCH_TLS_TPREL32:
325 return SignExtend64<32>(x: read32le(P: buf));
326 case R_LARCH_64:
327 case R_LARCH_TLS_DTPMOD64:
328 case R_LARCH_TLS_DTPREL64:
329 case R_LARCH_TLS_TPREL64:
330 return read64le(P: buf);
331 case R_LARCH_RELATIVE:
332 case R_LARCH_IRELATIVE:
333 return ctx.arg.is64 ? read64le(P: buf) : read32le(P: buf);
334 case R_LARCH_NONE:
335 case R_LARCH_JUMP_SLOT:
336 // These relocations are defined as not having an implicit addend.
337 return 0;
338 case R_LARCH_TLS_DESC32:
339 return read32le(P: buf + 4);
340 case R_LARCH_TLS_DESC64:
341 return read64le(P: buf + 8);
342 }
343}
344
345void LoongArch::writeGotPlt(uint8_t *buf, const Symbol &s) const {
346 if (ctx.arg.is64)
347 write64le(P: buf, V: ctx.in.plt->getVA());
348 else
349 write32le(P: buf, V: ctx.in.plt->getVA());
350}
351
352void LoongArch::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
353 if (ctx.arg.writeAddends) {
354 if (ctx.arg.is64)
355 write64le(P: buf, V: s.getVA(ctx));
356 else
357 write32le(P: buf, V: s.getVA(ctx));
358 }
359}
360
361void LoongArch::writePltHeader(uint8_t *buf) const {
362 // The LoongArch PLT is currently structured just like that of RISCV.
363 // Annoyingly, this means the PLT is still using `pcaddu12i` to perform
364 // PC-relative addressing (because `pcaddu12i` is the same as RISCV `auipc`),
365 // in contrast to the AArch64-like page-offset scheme with `pcalau12i` that
366 // is used everywhere else involving PC-relative operations in the LoongArch
367 // ELF psABI v2.00.
368 //
369 // The `pcrel_{hi20,lo12}` operators are illustrative only and not really
370 // supported by LoongArch assemblers.
371 //
372 // pcaddu12i $t2, %pcrel_hi20(.got.plt)
373 // sub.[wd] $t1, $t1, $t3
374 // ld.[wd] $t3, $t2, %pcrel_lo12(.got.plt) ; t3 = _dl_runtime_resolve
375 // addi.[wd] $t1, $t1, -pltHeaderSize-12 ; t1 = &.plt[i] - &.plt[0]
376 // addi.[wd] $t0, $t2, %pcrel_lo12(.got.plt)
377 // srli.[wd] $t1, $t1, (is64?1:2) ; t1 = &.got.plt[i] - &.got.plt[0]
378 // ld.[wd] $t0, $t0, Wordsize ; t0 = link_map
379 // jr $t3
380 uint32_t offset = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA();
381 uint32_t sub = ctx.arg.is64 ? SUB_D : SUB_W;
382 uint32_t ld = ctx.arg.is64 ? LD_D : LD_W;
383 uint32_t addi = ctx.arg.is64 ? ADDI_D : ADDI_W;
384 uint32_t srli = ctx.arg.is64 ? SRLI_D : SRLI_W;
385 write32le(P: buf + 0, V: insn(op: PCADDU12I, d: R_T2, j: hi20(val: offset), k: 0));
386 write32le(P: buf + 4, V: insn(op: sub, d: R_T1, j: R_T1, k: R_T3));
387 write32le(P: buf + 8, V: insn(op: ld, d: R_T3, j: R_T2, k: lo12(val: offset)));
388 write32le(P: buf + 12,
389 V: insn(op: addi, d: R_T1, j: R_T1, k: lo12(val: -ctx.target->pltHeaderSize - 12)));
390 write32le(P: buf + 16, V: insn(op: addi, d: R_T0, j: R_T2, k: lo12(val: offset)));
391 write32le(P: buf + 20, V: insn(op: srli, d: R_T1, j: R_T1, k: ctx.arg.is64 ? 1 : 2));
392 write32le(P: buf + 24, V: insn(op: ld, d: R_T0, j: R_T0, k: ctx.arg.wordsize));
393 write32le(P: buf + 28, V: insn(op: JIRL, d: R_ZERO, j: R_T3, k: 0));
394}
395
396void LoongArch::writePlt(uint8_t *buf, const Symbol &sym,
397 uint64_t pltEntryAddr) const {
398 // See the comment in writePltHeader for reason why pcaddu12i is used instead
399 // of the pcalau12i that's more commonly seen in the ELF psABI v2.0 days.
400 //
401 // pcaddu12i $t3, %pcrel_hi20(f@.got.plt)
402 // ld.[wd] $t3, $t3, %pcrel_lo12(f@.got.plt)
403 // jirl $t1, $t3, 0
404 // nop
405 uint32_t offset = sym.getGotPltVA(ctx) - pltEntryAddr;
406 write32le(P: buf + 0, V: insn(op: PCADDU12I, d: R_T3, j: hi20(val: offset), k: 0));
407 write32le(P: buf + 4,
408 V: insn(op: ctx.arg.is64 ? LD_D : LD_W, d: R_T3, j: R_T3, k: lo12(val: offset)));
409 write32le(P: buf + 8, V: insn(op: JIRL, d: R_T1, j: R_T3, k: 0));
410 write32le(P: buf + 12, V: insn(op: ANDI, d: R_ZERO, j: R_ZERO, k: 0));
411}
412
413RelType LoongArch::getDynRel(RelType type) const {
414 return type == ctx.target->symbolicRel ? type
415 : static_cast<RelType>(R_LARCH_NONE);
416}
417
418RelExpr LoongArch::getRelExpr(const RelType type, const Symbol &s,
419 const uint8_t *loc) const {
420 switch (type) {
421 case R_LARCH_NONE:
422 case R_LARCH_MARK_LA:
423 case R_LARCH_MARK_PCREL:
424 return R_NONE;
425 case R_LARCH_32:
426 case R_LARCH_64:
427 case R_LARCH_ABS_HI20:
428 case R_LARCH_ABS_LO12:
429 case R_LARCH_ABS64_LO20:
430 case R_LARCH_ABS64_HI12:
431 return R_ABS;
432 case R_LARCH_PCALA_LO12:
433 // We could just R_ABS, but the JIRL instruction reuses the relocation type
434 // for a different purpose. The questionable usage is part of glibc 2.37
435 // libc_nonshared.a [1], which is linked into user programs, so we have to
436 // work around it for a while, even if a new relocation type may be
437 // introduced in the future [2].
438 //
439 // [1]: https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=9f482b73f41a9a1bbfb173aad0733d1c824c788a
440 // [2]: https://github.com/loongson/la-abi-specs/pull/3
441 return isJirl(insn: read32le(P: loc)) ? R_PLT : R_ABS;
442 case R_LARCH_PCADD_LO12:
443 case R_LARCH_GOT_PCADD_LO12:
444 case R_LARCH_TLS_IE_PCADD_LO12:
445 case R_LARCH_TLS_LD_PCADD_LO12:
446 case R_LARCH_TLS_GD_PCADD_LO12:
447 case R_LARCH_TLS_DESC_PCADD_LO12:
448 return RE_LOONGARCH_PC_INDIRECT;
449 case R_LARCH_TLS_DTPREL32:
450 case R_LARCH_TLS_DTPREL64:
451 return R_DTPREL;
452 case R_LARCH_TLS_TPREL32:
453 case R_LARCH_TLS_TPREL64:
454 case R_LARCH_TLS_LE_HI20:
455 case R_LARCH_TLS_LE_HI20_R:
456 case R_LARCH_TLS_LE_LO12:
457 case R_LARCH_TLS_LE_LO12_R:
458 case R_LARCH_TLS_LE64_LO20:
459 case R_LARCH_TLS_LE64_HI12:
460 return R_TPREL;
461 case R_LARCH_ADD6:
462 case R_LARCH_ADD8:
463 case R_LARCH_ADD16:
464 case R_LARCH_ADD32:
465 case R_LARCH_ADD64:
466 case R_LARCH_ADD_ULEB128:
467 case R_LARCH_SUB6:
468 case R_LARCH_SUB8:
469 case R_LARCH_SUB16:
470 case R_LARCH_SUB32:
471 case R_LARCH_SUB64:
472 case R_LARCH_SUB_ULEB128:
473 // The LoongArch add/sub relocs behave like the RISCV counterparts; reuse
474 // the RelExpr to avoid code duplication.
475 return RE_RISCV_ADD;
476 case R_LARCH_32_PCREL:
477 case R_LARCH_64_PCREL:
478 case R_LARCH_PCREL20_S2:
479 case R_LARCH_PCADD_HI20:
480 return R_PC;
481 case R_LARCH_B16:
482 case R_LARCH_B21:
483 case R_LARCH_B26:
484 case R_LARCH_CALL30:
485 case R_LARCH_CALL36:
486 return R_PLT_PC;
487 case R_LARCH_GOT_PC_HI20:
488 case R_LARCH_GOT64_PC_LO20:
489 case R_LARCH_GOT64_PC_HI12:
490 case R_LARCH_TLS_IE_PC_HI20:
491 case R_LARCH_TLS_IE64_PC_LO20:
492 case R_LARCH_TLS_IE64_PC_HI12:
493 return RE_LOONGARCH_GOT_PAGE_PC;
494 case R_LARCH_GOT_PCADD_HI20:
495 case R_LARCH_TLS_IE_PCADD_HI20:
496 return R_GOT_PC;
497 case R_LARCH_GOT_PC_LO12:
498 case R_LARCH_TLS_IE_PC_LO12:
499 return RE_LOONGARCH_GOT;
500 case R_LARCH_TLS_LD_PC_HI20:
501 case R_LARCH_TLS_GD_PC_HI20:
502 return RE_LOONGARCH_TLSGD_PAGE_PC;
503 case R_LARCH_PCALA_HI20:
504 // Why not RE_LOONGARCH_PAGE_PC, majority of references don't go through
505 // PLT anyway so why waste time checking only to get everything relaxed back
506 // to it?
507 //
508 // This is again due to the R_LARCH_PCALA_LO12 on JIRL case, where we want
509 // both the HI20 and LO12 to potentially refer to the PLT. But in reality
510 // the HI20 reloc appears earlier, and the relocs don't contain enough
511 // information to let us properly resolve semantics per symbol.
512 // Unlike RISCV, our LO12 relocs *do not* point to their corresponding HI20
513 // relocs, hence it is nearly impossible to 100% accurately determine each
514 // HI20's "flavor" without taking big performance hits, in the presence of
515 // edge cases (e.g. HI20 without pairing LO12; paired LO12 placed so far
516 // apart that relationship is not certain anymore), and programmer mistakes
517 // (e.g. as outlined in https://github.com/loongson/la-abi-specs/pull/3).
518 //
519 // Ideally we would scan in an extra pass for all LO12s on JIRL, then mark
520 // every HI20 reloc referring to the same symbol differently; this is not
521 // feasible with the current function signature of getRelExpr that doesn't
522 // allow for such inter-pass state.
523 //
524 // So, unfortunately we have to again workaround this quirk the same way as
525 // BFD: assuming every R_LARCH_PCALA_HI20 is potentially PLT-needing, only
526 // relaxing back to RE_LOONGARCH_PAGE_PC if it's known not so at a later
527 // stage.
528 return RE_LOONGARCH_PLT_PAGE_PC;
529 case R_LARCH_PCALA64_LO20:
530 case R_LARCH_PCALA64_HI12:
531 return RE_LOONGARCH_PAGE_PC;
532 case R_LARCH_GOT_HI20:
533 case R_LARCH_GOT_LO12:
534 case R_LARCH_GOT64_LO20:
535 case R_LARCH_GOT64_HI12:
536 case R_LARCH_TLS_IE_HI20:
537 case R_LARCH_TLS_IE_LO12:
538 case R_LARCH_TLS_IE64_LO20:
539 case R_LARCH_TLS_IE64_HI12:
540 return R_GOT;
541 case R_LARCH_TLS_LD_HI20:
542 return R_TLSLD_GOT;
543 case R_LARCH_TLS_GD_HI20:
544 return R_TLSGD_GOT;
545 case R_LARCH_TLS_LE_ADD_R:
546 case R_LARCH_RELAX:
547 return ctx.arg.relax ? R_RELAX_HINT : R_NONE;
548 case R_LARCH_ALIGN:
549 return R_RELAX_HINT;
550 case R_LARCH_TLS_DESC_PC_HI20:
551 case R_LARCH_TLS_DESC64_PC_LO20:
552 case R_LARCH_TLS_DESC64_PC_HI12:
553 return RE_LOONGARCH_TLSDESC_PAGE_PC;
554 case R_LARCH_TLS_DESC_PC_LO12:
555 case R_LARCH_TLS_DESC_LD:
556 case R_LARCH_TLS_DESC_HI20:
557 case R_LARCH_TLS_DESC_LO12:
558 case R_LARCH_TLS_DESC64_LO20:
559 case R_LARCH_TLS_DESC64_HI12:
560 case R_LARCH_TLS_DESC_PCADD_HI20:
561 return R_TLSDESC;
562 case R_LARCH_TLS_DESC_CALL:
563 return R_TLSDESC_CALL;
564 case R_LARCH_TLS_LD_PCREL20_S2:
565 case R_LARCH_TLS_LD_PCADD_HI20:
566 return R_TLSLD_PC;
567 case R_LARCH_TLS_GD_PCREL20_S2:
568 case R_LARCH_TLS_GD_PCADD_HI20:
569 return R_TLSGD_PC;
570 case R_LARCH_TLS_DESC_PCREL20_S2:
571 return R_TLSDESC_PC;
572
573 // Other known relocs that are explicitly unimplemented:
574 //
575 // - psABI v1 relocs that need a stateful stack machine to work, and not
576 // required when implementing psABI v2;
577 // - relocs that are not used anywhere (R_LARCH_{ADD,SUB}_24 [1], and the
578 // two GNU vtable-related relocs).
579 //
580 // [1]: https://web.archive.org/web/20230709064026/https://github.com/loongson/LoongArch-Documentation/issues/51
581 default:
582 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v
583 << ") against symbol " << &s;
584 return R_NONE;
585 }
586}
587
588bool LoongArch::usesOnlyLowPageBits(RelType type) const {
589 switch (type) {
590 default:
591 return false;
592 case R_LARCH_PCALA_LO12:
593 case R_LARCH_GOT_LO12:
594 case R_LARCH_GOT_PC_LO12:
595 case R_LARCH_TLS_IE_PC_LO12:
596 case R_LARCH_TLS_DESC_LO12:
597 case R_LARCH_TLS_DESC_PC_LO12:
598 return true;
599 }
600}
601
602void LoongArch::relocate(uint8_t *loc, const Relocation &rel,
603 uint64_t val) const {
604 switch (rel.type) {
605 case R_LARCH_32_PCREL:
606 checkInt(ctx, loc, v: val, n: 32, rel);
607 [[fallthrough]];
608 case R_LARCH_32:
609 case R_LARCH_TLS_DTPREL32:
610 write32le(P: loc, V: val);
611 return;
612 case R_LARCH_64:
613 case R_LARCH_TLS_DTPREL64:
614 case R_LARCH_64_PCREL:
615 write64le(P: loc, V: val);
616 return;
617
618 // Relocs intended for `pcaddi`.
619 case R_LARCH_PCREL20_S2:
620 case R_LARCH_TLS_LD_PCREL20_S2:
621 case R_LARCH_TLS_GD_PCREL20_S2:
622 case R_LARCH_TLS_DESC_PCREL20_S2:
623 checkInt(ctx, loc, v: val, n: 22, rel);
624 checkAlignment(ctx, loc, v: val, n: 4, rel);
625 write32le(P: loc, V: setJ20(insn: read32le(P: loc), imm: val >> 2));
626 return;
627
628 case R_LARCH_B16:
629 checkInt(ctx, loc, v: val, n: 18, rel);
630 checkAlignment(ctx, loc, v: val, n: 4, rel);
631 write32le(P: loc, V: setK16(insn: read32le(P: loc), imm: val >> 2));
632 return;
633
634 case R_LARCH_B21:
635 checkInt(ctx, loc, v: val, n: 23, rel);
636 checkAlignment(ctx, loc, v: val, n: 4, rel);
637 write32le(P: loc, V: setD5k16(insn: read32le(P: loc), imm: val >> 2));
638 return;
639
640 case R_LARCH_B26:
641 checkInt(ctx, loc, v: val, n: 28, rel);
642 checkAlignment(ctx, loc, v: val, n: 4, rel);
643 write32le(P: loc, V: setD10k16(insn: read32le(P: loc), imm: val >> 2));
644 return;
645
646 case R_LARCH_CALL30: {
647 // This relocation is designed for adjacent pcaddu12i+jirl pairs that
648 // are patched in one time.
649 // The relocation range is [-2G, +2G) (of course must be 4-byte aligned).
650 checkInt(ctx, loc, v: val, n: 32, rel);
651 checkAlignment(ctx, loc, v: val, n: 4, rel);
652 // Although jirl adds the immediate as a signed value, it is always positive
653 // in this case, so no adjustment is needed, unlike CALL36.
654 uint32_t hi20 = extractBits(v: val, begin: 31, end: 12);
655 // Despite the name, the lower part is actually 12 bits with 4-byte aligned.
656 uint32_t lo10 = extractBits(v: val, begin: 11, end: 2);
657 write32le(P: loc, V: setJ20(insn: read32le(P: loc), imm: hi20));
658 write32le(P: loc + 4, V: setK16(insn: read32le(P: loc + 4), imm: lo10));
659 return;
660 }
661
662 case R_LARCH_CALL36: {
663 // This relocation is designed for adjacent pcaddu18i+jirl pairs that
664 // are patched in one time. Because of sign extension of these insns'
665 // immediate fields, the relocation range is [-128G - 0x20000, +128G -
666 // 0x20000) (of course must be 4-byte aligned).
667 if (((int64_t)val + 0x20000) != llvm::SignExtend64(X: val + 0x20000, B: 38))
668 reportRangeError(ctx, loc, rel, v: Twine(val), min: llvm::minIntN(N: 38) - 0x20000,
669 max: llvm::maxIntN(N: 38) - 0x20000);
670 checkAlignment(ctx, loc, v: val, n: 4, rel);
671 // Since jirl performs sign extension on the offset immediate, adds (1<<17)
672 // to original val to get the correct hi20.
673 uint32_t hi20 = extractBits(v: val + (1 << 17), begin: 37, end: 18);
674 // Despite the name, the lower part is actually 18 bits with 4-byte aligned.
675 uint32_t lo16 = extractBits(v: val, begin: 17, end: 2);
676 write32le(P: loc, V: setJ20(insn: read32le(P: loc), imm: hi20));
677 write32le(P: loc + 4, V: setK16(insn: read32le(P: loc + 4), imm: lo16));
678 return;
679 }
680
681 // Relocs intended for `addi`, `ld` or `st`.
682 case R_LARCH_PCALA_LO12:
683 // We have to again inspect the insn word to handle the R_LARCH_PCALA_LO12
684 // on JIRL case: firstly JIRL wants its immediate's 2 lowest zeroes
685 // removed by us (in contrast to regular R_LARCH_PCALA_LO12), secondly
686 // its immediate slot width is different too (16, not 12).
687 // In this case, process like an R_LARCH_B16, but without overflow checking
688 // and only taking the value's lowest 12 bits.
689 if (isJirl(insn: read32le(P: loc))) {
690 checkAlignment(ctx, loc, v: val, n: 4, rel);
691 val = SignExtend64<12>(x: val);
692 write32le(P: loc, V: setK16(insn: read32le(P: loc), imm: val >> 2));
693 return;
694 }
695 [[fallthrough]];
696 case R_LARCH_ABS_LO12:
697 case R_LARCH_GOT_PC_LO12:
698 case R_LARCH_GOT_LO12:
699 case R_LARCH_TLS_LE_LO12:
700 case R_LARCH_TLS_IE_PC_LO12:
701 case R_LARCH_TLS_IE_LO12:
702 case R_LARCH_TLS_LE_LO12_R:
703 case R_LARCH_TLS_DESC_PC_LO12:
704 case R_LARCH_TLS_DESC_LO12:
705 case R_LARCH_PCADD_LO12:
706 case R_LARCH_GOT_PCADD_LO12:
707 case R_LARCH_TLS_IE_PCADD_LO12:
708 case R_LARCH_TLS_LD_PCADD_LO12:
709 case R_LARCH_TLS_GD_PCADD_LO12:
710 case R_LARCH_TLS_DESC_PCADD_LO12:
711 write32le(P: loc, V: setK12(insn: read32le(P: loc), imm: extractBits(v: val, begin: 11, end: 0)));
712 return;
713
714 // Relocs intended for `lu12i.w` or `pcalau12i`.
715 case R_LARCH_ABS_HI20:
716 case R_LARCH_PCALA_HI20:
717 case R_LARCH_GOT_PC_HI20:
718 case R_LARCH_GOT_HI20:
719 case R_LARCH_TLS_LE_HI20:
720 case R_LARCH_TLS_IE_PC_HI20:
721 case R_LARCH_TLS_IE_HI20:
722 case R_LARCH_TLS_LD_PC_HI20:
723 case R_LARCH_TLS_LD_HI20:
724 case R_LARCH_TLS_GD_PC_HI20:
725 case R_LARCH_TLS_GD_HI20:
726 case R_LARCH_TLS_DESC_PC_HI20:
727 case R_LARCH_TLS_DESC_HI20:
728 write32le(P: loc, V: setJ20(insn: read32le(P: loc), imm: extractBits(v: val, begin: 31, end: 12)));
729 return;
730 case R_LARCH_PCADD_HI20:
731 case R_LARCH_GOT_PCADD_HI20:
732 case R_LARCH_TLS_IE_PCADD_HI20:
733 case R_LARCH_TLS_LD_PCADD_HI20:
734 case R_LARCH_TLS_GD_PCADD_HI20:
735 case R_LARCH_TLS_DESC_PCADD_HI20: {
736 uint64_t hi = val + 0x800;
737 checkInt(ctx, loc, v: val, n: 32, rel);
738 write32le(P: loc, V: setJ20(insn: read32le(P: loc), imm: extractBits(v: hi, begin: 31, end: 12)));
739 return;
740 }
741 case R_LARCH_TLS_LE_HI20_R:
742 write32le(P: loc, V: setJ20(insn: read32le(P: loc), imm: extractBits(v: val + 0x800, begin: 31, end: 12)));
743 return;
744
745 // Relocs intended for `lu32i.d`.
746 case R_LARCH_ABS64_LO20:
747 case R_LARCH_PCALA64_LO20:
748 case R_LARCH_GOT64_PC_LO20:
749 case R_LARCH_GOT64_LO20:
750 case R_LARCH_TLS_LE64_LO20:
751 case R_LARCH_TLS_IE64_PC_LO20:
752 case R_LARCH_TLS_IE64_LO20:
753 case R_LARCH_TLS_DESC64_PC_LO20:
754 case R_LARCH_TLS_DESC64_LO20:
755 write32le(P: loc, V: setJ20(insn: read32le(P: loc), imm: extractBits(v: val, begin: 51, end: 32)));
756 return;
757
758 // Relocs intended for `lu52i.d`.
759 case R_LARCH_ABS64_HI12:
760 case R_LARCH_PCALA64_HI12:
761 case R_LARCH_GOT64_PC_HI12:
762 case R_LARCH_GOT64_HI12:
763 case R_LARCH_TLS_LE64_HI12:
764 case R_LARCH_TLS_IE64_PC_HI12:
765 case R_LARCH_TLS_IE64_HI12:
766 case R_LARCH_TLS_DESC64_PC_HI12:
767 case R_LARCH_TLS_DESC64_HI12:
768 write32le(P: loc, V: setK12(insn: read32le(P: loc), imm: extractBits(v: val, begin: 63, end: 52)));
769 return;
770
771 case R_LARCH_ADD6:
772 *loc = (*loc & 0xc0) | ((*loc + val) & 0x3f);
773 return;
774 case R_LARCH_ADD8:
775 *loc += val;
776 return;
777 case R_LARCH_ADD16:
778 write16le(P: loc, V: read16le(P: loc) + val);
779 return;
780 case R_LARCH_ADD32:
781 write32le(P: loc, V: read32le(P: loc) + val);
782 return;
783 case R_LARCH_ADD64:
784 write64le(P: loc, V: read64le(P: loc) + val);
785 return;
786 case R_LARCH_ADD_ULEB128:
787 handleUleb128(ctx, loc, val);
788 return;
789 case R_LARCH_SUB6:
790 *loc = (*loc & 0xc0) | ((*loc - val) & 0x3f);
791 return;
792 case R_LARCH_SUB8:
793 *loc -= val;
794 return;
795 case R_LARCH_SUB16:
796 write16le(P: loc, V: read16le(P: loc) - val);
797 return;
798 case R_LARCH_SUB32:
799 write32le(P: loc, V: read32le(P: loc) - val);
800 return;
801 case R_LARCH_SUB64:
802 write64le(P: loc, V: read64le(P: loc) - val);
803 return;
804 case R_LARCH_SUB_ULEB128:
805 handleUleb128(ctx, loc, val: -val);
806 return;
807
808 case R_LARCH_MARK_LA:
809 case R_LARCH_MARK_PCREL:
810 // no-op
811 return;
812
813 case R_LARCH_TLS_LE_ADD_R:
814 case R_LARCH_RELAX:
815 return; // Ignored (for now)
816
817 case R_LARCH_TLS_DESC_LD:
818 return; // nothing to do.
819 case R_LARCH_TLS_DESC32:
820 write32le(P: loc + 4, V: val);
821 return;
822 case R_LARCH_TLS_DESC64:
823 write64le(P: loc + 8, V: val);
824 return;
825
826 default:
827 llvm_unreachable("unknown relocation");
828 }
829}
830
831// If the section alignment is > 4, advance `dot` to insert NOPs and synthesize
832// an ALIGN relocation. Otherwise, return false to use default handling.
833template <class ELFT, class RelTy>
834bool LoongArch::synthesizeAlignForInput(uint64_t &dot, InputSection *sec,
835 Relocs<RelTy> rels) {
836 if (!baseSec) {
837 // Record the first input section with RELAX relocations. We will synthesize
838 // ALIGN relocations here.
839 for (auto rel : rels) {
840 if (rel.getType(false) == R_LARCH_RELAX) {
841 baseSec = sec;
842 break;
843 }
844 }
845 } else if (sec->addralign > 4) {
846 // If the alignment is > 4 and the section does not start with an ALIGN
847 // relocation, synthesize one.
848 bool hasAlignRel = llvm::any_of(rels, [](const RelTy &rel) {
849 return rel.r_offset == 0 && rel.getType(false) == R_LARCH_ALIGN;
850 });
851 if (!hasAlignRel) {
852 synthesizedAligns.emplace_back(Args: dot - baseSec->getVA(),
853 Args: sec->addralign - 4);
854 dot += sec->addralign - 4;
855 return true;
856 }
857 }
858 return false;
859}
860
861// Finalize the relocation section by appending synthesized ALIGN relocations
862// after processing all input sections.
863template <class ELFT, class RelTy>
864void LoongArch::finalizeSynthesizeAligns(uint64_t &dot, InputSection *sec,
865 Relocs<RelTy> rels) {
866 auto *f = cast<ObjFile<ELFT>>(baseSec->file);
867 auto shdr = f->template getELFShdrs<ELFT>()[baseSec->relSecIdx];
868 // Create a copy of InputSection.
869 sec = make<InputSection>(*f, shdr, baseSec->name);
870 auto *baseRelSec = cast<InputSection>(f->getSections()[baseSec->relSecIdx]);
871 *sec = *baseRelSec;
872 baseSec = nullptr;
873
874 // Allocate buffer for original and synthesized relocations in RELA format.
875 // If CREL is used, OutputSection::finalizeNonAllocCrel will convert RELA to
876 // CREL.
877 auto newSize = rels.size() + synthesizedAligns.size();
878 auto *relas = makeThreadLocalN<typename ELFT::Rela>(newSize);
879 sec->size = newSize * sizeof(typename ELFT::Rela);
880 sec->content_ = reinterpret_cast<uint8_t *>(relas);
881 sec->type = SHT_RELA;
882 // Copy original relocations to the new buffer, potentially converting CREL to
883 // RELA.
884 for (auto [i, r] : llvm::enumerate(rels)) {
885 relas[i].r_offset = r.r_offset;
886 relas[i].setSymbolAndType(r.getSymbol(0), r.getType(0), false);
887 if constexpr (RelTy::HasAddend)
888 relas[i].r_addend = r.r_addend;
889 }
890 // Append synthesized ALIGN relocations to the buffer.
891 for (auto [i, r] : llvm::enumerate(First&: synthesizedAligns)) {
892 auto &rela = relas[rels.size() + i];
893 rela.r_offset = r.first;
894 rela.setSymbolAndType(0, R_LARCH_ALIGN, false);
895 rela.r_addend = r.second;
896 }
897 synthesizedAligns.clear();
898 // Replace the old relocation section with the new one in the output section.
899 // addOrphanSections ensures that the output relocation section is processed
900 // after osec.
901 for (SectionCommand *cmd : sec->getParent()->commands) {
902 auto *isd = dyn_cast<InputSectionDescription>(Val: cmd);
903 if (!isd)
904 continue;
905 for (auto *&isec : isd->sections)
906 if (isec == baseRelSec)
907 isec = sec;
908 }
909}
910
911template <class ELFT>
912bool LoongArch::synthesizeAlignAux(uint64_t &dot, InputSection *sec) {
913 bool ret = false;
914 if (sec) {
915 invokeOnRelocs(*sec, ret = synthesizeAlignForInput<ELFT>, dot, sec);
916 } else if (baseSec) {
917 invokeOnRelocs(*baseSec, finalizeSynthesizeAligns<ELFT>, dot, sec);
918 }
919 return ret;
920}
921
922// Without linker relaxation enabled for a particular relocatable file or
923// section, the assembler will not generate R_LARCH_ALIGN relocations for
924// alignment directives. This becomes problematic in a two-stage linking
925// process: ld -r a.o b.o -o ab.o; ld ab.o -o ab. This function synthesizes an
926// R_LARCH_ALIGN relocation at section start when needed.
927//
928// When called with an input section (`sec` is not null): If the section
929// alignment is > 4, advance `dot` to insert NOPs and synthesize an ALIGN
930// relocation.
931//
932// When called after all input sections are processed (`sec` is null): The
933// output relocation section is updated with all the newly synthesized ALIGN
934// relocations.
935bool LoongArch::synthesizeAlign(uint64_t &dot, InputSection *sec) {
936 assert(ctx.arg.relocatable);
937 if (ctx.arg.is64)
938 return synthesizeAlignAux<ELF64LE>(dot, sec);
939 return synthesizeAlignAux<ELF32LE>(dot, sec);
940}
941
942static bool relaxable(ArrayRef<Relocation> relocs, size_t i) {
943 return i + 1 < relocs.size() && relocs[i + 1].type == R_LARCH_RELAX;
944}
945
946static bool isPairRelaxable(ArrayRef<Relocation> relocs, size_t i) {
947 return relaxable(relocs, i) && relaxable(relocs, i: i + 2) &&
948 relocs[i].offset + 4 == relocs[i + 2].offset;
949}
950
951// Relax code sequence.
952// From:
953// pcalau12i $a0, %pc_hi20(sym) | %ld_pc_hi20(sym) | %gd_pc_hi20(sym)
954// | %desc_pc_hi20(sym)
955// addi.w/d $a0, $a0, %pc_lo12(sym) | %got_pc_lo12(sym) | %got_pc_lo12(sym)
956// | %desc_pc_lo12(sym)
957// To:
958// pcaddi $a0, %pc_lo12(sym) | %got_pc_lo12(sym) | %got_pc_lo12(sym)
959// | %desc_pcrel_20(sym)
960//
961// From:
962// pcalau12i $a0, %got_pc_hi20(sym_got)
963// ld.w/d $a0, $a0, %got_pc_lo12(sym_got)
964// To:
965// pcaddi $a0, %got_pc_hi20(sym_got)
966static void relaxPCHi20Lo12(Ctx &ctx, const InputSection &sec, size_t i,
967 uint64_t loc, Relocation &rHi20, Relocation &rLo12,
968 uint32_t &remove) {
969 // check if the relocations are relaxable sequences.
970 if (!((rHi20.type == R_LARCH_PCALA_HI20 &&
971 rLo12.type == R_LARCH_PCALA_LO12) ||
972 (rHi20.type == R_LARCH_GOT_PC_HI20 &&
973 rLo12.type == R_LARCH_GOT_PC_LO12) ||
974 (rHi20.type == R_LARCH_TLS_GD_PC_HI20 &&
975 rLo12.type == R_LARCH_GOT_PC_LO12) ||
976 (rHi20.type == R_LARCH_TLS_LD_PC_HI20 &&
977 rLo12.type == R_LARCH_GOT_PC_LO12) ||
978 (rHi20.type == R_LARCH_TLS_DESC_PC_HI20 &&
979 rLo12.type == R_LARCH_TLS_DESC_PC_LO12)))
980 return;
981
982 // GOT references to absolute symbols can't be relaxed to use pcaddi in
983 // position-independent code, because these instructions produce a relative
984 // address.
985 // Meanwhile skip undefined, preemptible and STT_GNU_IFUNC symbols, because
986 // these symbols may be resolve in runtime.
987 // Moreover, relaxation can only occur if the addends of both relocations are
988 // zero for GOT references.
989 if (rHi20.type == R_LARCH_GOT_PC_HI20 &&
990 (!rHi20.sym || rHi20.sym != rLo12.sym || !rHi20.sym->isDefined() ||
991 rHi20.sym->isPreemptible || rHi20.sym->isGnuIFunc() ||
992 (ctx.arg.isPic && !cast<Defined>(Val&: *rHi20.sym).section) ||
993 rHi20.addend != 0 || rLo12.addend != 0))
994 return;
995
996 uint64_t dest = 0;
997 if (rHi20.expr == RE_LOONGARCH_PLT_PAGE_PC)
998 dest = rHi20.sym->getPltVA(ctx);
999 else if (rHi20.expr == RE_LOONGARCH_PAGE_PC ||
1000 rHi20.expr == RE_LOONGARCH_GOT_PAGE_PC)
1001 dest = rHi20.sym->getVA(ctx);
1002 else if (rHi20.expr == RE_LOONGARCH_TLSGD_PAGE_PC)
1003 dest = ctx.in.got->getGlobalDynAddr(b: *rHi20.sym);
1004 else if (rHi20.expr == RE_LOONGARCH_TLSDESC_PAGE_PC)
1005 dest = ctx.in.got->getTlsDescAddr(sym: *rHi20.sym);
1006 else {
1007 Err(ctx) << getErrorLoc(ctx, loc: (const uint8_t *)loc) << "unknown expr ("
1008 << rHi20.expr << ") against symbol " << rHi20.sym
1009 << "in relaxPCHi20Lo12";
1010 return;
1011 }
1012 dest += rHi20.addend;
1013
1014 const int64_t displace = dest - loc;
1015 // Check if the displace aligns 4 bytes or exceeds the range of pcaddi.
1016 if ((displace & 0x3) != 0 || !isInt<22>(x: displace))
1017 return;
1018
1019 // Note: If we can ensure that the .o files generated by LLVM only contain
1020 // relaxable instruction sequences with R_LARCH_RELAX, then we do not need to
1021 // decode instructions. The relaxable instruction sequences imply the
1022 // following constraints:
1023 // * For relocation pairs related to got_pc, the opcodes of instructions
1024 // must be pcalau12i + ld.w/d. In other cases, the opcodes must be pcalau12i +
1025 // addi.w/d.
1026 // * The destination register of pcalau12i is guaranteed to be used only by
1027 // the immediately following instruction.
1028 const uint32_t currInsn = read32le(P: sec.content().data() + rHi20.offset);
1029 const uint32_t nextInsn = read32le(P: sec.content().data() + rLo12.offset);
1030 // Check if use the same register.
1031 if (getD5(v: currInsn) != getJ5(v: nextInsn) || getJ5(v: nextInsn) != getD5(v: nextInsn))
1032 return;
1033
1034 sec.relaxAux->relocTypes[i] = R_LARCH_RELAX;
1035 if (rHi20.type == R_LARCH_TLS_GD_PC_HI20)
1036 sec.relaxAux->relocTypes[i + 2] = R_LARCH_TLS_GD_PCREL20_S2;
1037 else if (rHi20.type == R_LARCH_TLS_LD_PC_HI20)
1038 sec.relaxAux->relocTypes[i + 2] = R_LARCH_TLS_LD_PCREL20_S2;
1039 else if (rHi20.type == R_LARCH_TLS_DESC_PC_HI20)
1040 sec.relaxAux->relocTypes[i + 2] = R_LARCH_TLS_DESC_PCREL20_S2;
1041 else
1042 sec.relaxAux->relocTypes[i + 2] = R_LARCH_PCREL20_S2;
1043 sec.relaxAux->writes.push_back(Elt: insn(op: PCADDI, d: getD5(v: nextInsn), j: 0, k: 0));
1044 remove = 4;
1045}
1046
1047// Relax code sequence.
1048// From:
1049// la32r:
1050// pcaddu12i $ra, %call30(foo)
1051// jirl $ra, $ra, 0
1052// la32s/la64:
1053// pcaddu18i $ra, %call36(foo)
1054// jirl $ra, $ra, 0
1055// To:
1056// b/bl foo
1057static void relaxMediumCall(Ctx &ctx, const InputSection &sec, size_t i,
1058 uint64_t loc, Relocation &r, uint32_t &remove) {
1059 const uint64_t dest =
1060 (r.expr == R_PLT_PC ? r.sym->getPltVA(ctx) : r.sym->getVA(ctx)) +
1061 r.addend;
1062
1063 const int64_t displace = dest - loc;
1064 // Check if the displace aligns 4 bytes or exceeds the range of b[l].
1065 if ((displace & 0x3) != 0 || !isInt<28>(x: displace))
1066 return;
1067
1068 const uint32_t nextInsn = read32le(P: sec.content().data() + r.offset + 4);
1069 if (getD5(v: nextInsn) == R_RA) {
1070 // convert jirl to bl
1071 sec.relaxAux->relocTypes[i] = R_LARCH_B26;
1072 sec.relaxAux->writes.push_back(Elt: insn(op: BL, d: 0, j: 0, k: 0));
1073 remove = 4;
1074 } else if (getD5(v: nextInsn) == R_ZERO) {
1075 // convert jirl to b
1076 sec.relaxAux->relocTypes[i] = R_LARCH_B26;
1077 sec.relaxAux->writes.push_back(Elt: insn(op: B, d: 0, j: 0, k: 0));
1078 remove = 4;
1079 }
1080}
1081
1082// Relax code sequence.
1083// From:
1084// lu12i.w $rd, %le_hi20_r(sym)
1085// add.w/d $rd, $rd, $tp, %le_add_r(sym)
1086// addi/ld/st.w/d $rd, $rd, %le_lo12_r(sym)
1087// To:
1088// addi/ld/st.w/d $rd, $tp, %le_lo12_r(sym)
1089static void relaxTlsLe(Ctx &ctx, const InputSection &sec, size_t i,
1090 uint64_t loc, Relocation &r, uint32_t &remove) {
1091 uint64_t val = r.sym->getVA(ctx, addend: r.addend);
1092 // Check if the val exceeds the range of addi/ld/st.
1093 if (!isInt<12>(x: val))
1094 return;
1095 uint32_t currInsn = read32le(P: sec.content().data() + r.offset);
1096 switch (r.type) {
1097 case R_LARCH_TLS_LE_HI20_R:
1098 case R_LARCH_TLS_LE_ADD_R:
1099 sec.relaxAux->relocTypes[i] = R_LARCH_RELAX;
1100 remove = 4;
1101 break;
1102 case R_LARCH_TLS_LE_LO12_R:
1103 sec.relaxAux->writes.push_back(Elt: setJ5(insn: currInsn, imm: R_TP));
1104 sec.relaxAux->relocTypes[i] = R_LARCH_TLS_LE_LO12_R;
1105 break;
1106 }
1107}
1108
1109static bool relax(Ctx &ctx, InputSection &sec) {
1110 const uint64_t secAddr = sec.getVA();
1111 const MutableArrayRef<Relocation> relocs = sec.relocs();
1112 auto &aux = *sec.relaxAux;
1113 bool changed = false;
1114 ArrayRef<SymbolAnchor> sa = ArrayRef(aux.anchors);
1115 uint64_t delta = 0;
1116
1117 std::fill_n(first: aux.relocTypes.get(), n: relocs.size(), value: R_LARCH_NONE);
1118 aux.writes.clear();
1119 for (auto [i, r] : llvm::enumerate(First: relocs)) {
1120 const uint64_t loc = secAddr + r.offset - delta;
1121 uint32_t &cur = aux.relocDeltas[i], remove = 0;
1122 switch (r.type) {
1123 case R_LARCH_ALIGN: {
1124 const uint64_t addend =
1125 r.sym->isUndefined() ? Log2_64(Value: r.addend) + 1 : r.addend;
1126 const uint64_t allBytes = (1ULL << (addend & 0xff)) - 4;
1127 const uint64_t align = 1ULL << (addend & 0xff);
1128 const uint64_t maxBytes = addend >> 8;
1129 const uint64_t off = loc & (align - 1);
1130 const uint64_t curBytes = off == 0 ? 0 : align - off;
1131 // All bytes beyond the alignment boundary should be removed.
1132 // If emit bytes more than max bytes to emit, remove all.
1133 if (maxBytes != 0 && curBytes > maxBytes)
1134 remove = allBytes;
1135 else
1136 remove = allBytes - curBytes;
1137 // If we can't satisfy this alignment, we've found a bad input.
1138 if (LLVM_UNLIKELY(static_cast<int32_t>(remove) < 0)) {
1139 Err(ctx) << getErrorLoc(ctx, loc: (const uint8_t *)loc)
1140 << "insufficient padding bytes for " << r.type << ": "
1141 << allBytes << " bytes available for "
1142 << "requested alignment of " << align << " bytes";
1143 remove = 0;
1144 }
1145 break;
1146 }
1147 case R_LARCH_PCALA_HI20:
1148 case R_LARCH_GOT_PC_HI20:
1149 case R_LARCH_TLS_GD_PC_HI20:
1150 case R_LARCH_TLS_LD_PC_HI20:
1151 // The overflow check for i+2 will be carried out in isPairRelaxable.
1152 if (isPairRelaxable(relocs, i))
1153 relaxPCHi20Lo12(ctx, sec, i, loc, rHi20&: r, rLo12&: relocs[i + 2], remove);
1154 break;
1155 case R_LARCH_TLS_DESC_PC_HI20:
1156 if (r.expr == RE_LOONGARCH_RELAX_TLS_GD_TO_IE_PAGE_PC ||
1157 r.expr == R_RELAX_TLS_GD_TO_LE) {
1158 if (relaxable(relocs, i))
1159 remove = 4;
1160 } else if (isPairRelaxable(relocs, i))
1161 relaxPCHi20Lo12(ctx, sec, i, loc, rHi20&: r, rLo12&: relocs[i + 2], remove);
1162 break;
1163 case R_LARCH_CALL30:
1164 case R_LARCH_CALL36:
1165 if (relaxable(relocs, i))
1166 relaxMediumCall(ctx, sec, i, loc, r, remove);
1167 break;
1168 case R_LARCH_TLS_LE_HI20_R:
1169 case R_LARCH_TLS_LE_ADD_R:
1170 case R_LARCH_TLS_LE_LO12_R:
1171 if (relaxable(relocs, i))
1172 relaxTlsLe(ctx, sec, i, loc, r, remove);
1173 break;
1174 case R_LARCH_TLS_IE_PC_HI20:
1175 if (relaxable(relocs, i) && r.expr == R_RELAX_TLS_IE_TO_LE &&
1176 isUInt<12>(x: r.sym->getVA(ctx, addend: r.addend)))
1177 remove = 4;
1178 break;
1179 case R_LARCH_TLS_DESC_PC_LO12:
1180 if (relaxable(relocs, i) &&
1181 (r.expr == RE_LOONGARCH_RELAX_TLS_GD_TO_IE_PAGE_PC ||
1182 r.expr == R_RELAX_TLS_GD_TO_LE))
1183 remove = 4;
1184 break;
1185 case R_LARCH_TLS_DESC_LD:
1186 if (relaxable(relocs, i) && r.expr == R_RELAX_TLS_GD_TO_LE &&
1187 isUInt<12>(x: r.sym->getVA(ctx, addend: r.addend)))
1188 remove = 4;
1189 break;
1190 }
1191
1192 // For all anchors whose offsets are <= r.offset, they are preceded by
1193 // the previous relocation whose `relocDeltas` value equals `delta`.
1194 // Decrease their st_value and update their st_size.
1195 for (; sa.size() && sa[0].offset <= r.offset; sa = sa.slice(N: 1)) {
1196 if (sa[0].end)
1197 sa[0].d->size = sa[0].offset - delta - sa[0].d->value;
1198 else
1199 sa[0].d->value = sa[0].offset - delta;
1200 }
1201 delta += remove;
1202 if (delta != cur) {
1203 cur = delta;
1204 changed = true;
1205 }
1206 }
1207
1208 for (const SymbolAnchor &a : sa) {
1209 if (a.end)
1210 a.d->size = a.offset - delta - a.d->value;
1211 else
1212 a.d->value = a.offset - delta;
1213 }
1214 // Inform assignAddresses that the size has changed.
1215 if (!isUInt<32>(x: delta))
1216 Fatal(ctx) << "section size decrease is too large: " << delta;
1217 sec.bytesDropped = delta;
1218 return changed;
1219}
1220
1221// Convert TLS IE to LE in the normal or medium code model.
1222// Original code sequence:
1223// * pcalau12i $a0, %ie_pc_hi20(sym)
1224// * ld.d $a0, $a0, %ie_pc_lo12(sym)
1225//
1226// The code sequence converted is as follows:
1227// * lu12i.w $a0, %le_hi20(sym) # le_hi20 != 0, otherwise NOP
1228// * ori $a0, src, %le_lo12(sym) # le_hi20 != 0, src = $a0,
1229// # otherwise, src = $zero
1230//
1231// When relaxation enables, redundant NOPs can be removed.
1232static void tlsIeToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
1233 assert(isInt<32>(val) &&
1234 "val exceeds the range of medium code model in tlsIeToLe");
1235
1236 bool isUInt12 = isUInt<12>(x: val);
1237 const uint32_t currInsn = read32le(P: loc);
1238 switch (rel.type) {
1239 case R_LARCH_TLS_IE_PC_HI20:
1240 if (isUInt12)
1241 write32le(P: loc, V: insn(op: ANDI, d: R_ZERO, j: R_ZERO, k: 0)); // nop
1242 else
1243 write32le(P: loc, V: insn(op: LU12I_W, d: getD5(v: currInsn), j: extractBits(v: val, begin: 31, end: 12),
1244 k: 0)); // lu12i.w $a0, %le_hi20
1245 break;
1246 case R_LARCH_TLS_IE_PC_LO12:
1247 if (isUInt12)
1248 write32le(P: loc, V: insn(op: ORI, d: getD5(v: currInsn), j: R_ZERO,
1249 k: val)); // ori $a0, $zero, %le_lo12
1250 else
1251 write32le(P: loc, V: insn(op: ORI, d: getD5(v: currInsn), j: getJ5(v: currInsn),
1252 k: lo12(val))); // ori $a0, $a0, %le_lo12
1253 break;
1254 }
1255}
1256
1257// Convert TLSDESC GD/LD to IE.
1258// In normal or medium code model, there are two forms of code sequences:
1259// * pcalau12i $a0, %desc_pc_hi20(sym_desc)
1260// * addi.d $a0, $a0, %desc_pc_lo12(sym_desc)
1261// * ld.d $ra, $a0, %desc_ld(sym_desc)
1262// * jirl $ra, $ra, %desc_call(sym_desc)
1263// ------
1264// * pcaddi $a0, %desc_pcrel_20(a)
1265// * load $ra, $a0, %desc_ld(a)
1266// * jirl $ra, $ra, %desc_call(a)
1267//
1268// The code sequence obtained is as follows:
1269// * pcalau12i $a0, %ie_pc_hi20(sym_ie)
1270// * ld.[wd] $a0, $a0, %ie_pc_lo12(sym_ie)
1271//
1272// Simplicity, whether tlsdescToIe or tlsdescToLe, we always tend to convert the
1273// preceding instructions to NOPs, due to both forms of code sequence
1274// (corresponding to relocation combinations:
1275// R_LARCH_TLS_DESC_PC_HI20+R_LARCH_TLS_DESC_PC_LO12 and
1276// R_LARCH_TLS_DESC_PCREL20_S2) have same process.
1277//
1278// When relaxation enables, redundant NOPs can be removed.
1279void LoongArch::tlsdescToIe(uint8_t *loc, const Relocation &rel,
1280 uint64_t val) const {
1281 switch (rel.type) {
1282 case R_LARCH_TLS_DESC_PC_HI20:
1283 case R_LARCH_TLS_DESC_PC_LO12:
1284 case R_LARCH_TLS_DESC_PCREL20_S2:
1285 write32le(P: loc, V: insn(op: ANDI, d: R_ZERO, j: R_ZERO, k: 0)); // nop
1286 break;
1287 case R_LARCH_TLS_DESC_LD:
1288 write32le(P: loc, V: insn(op: PCALAU12I, d: R_A0, j: 0, k: 0)); // pcalau12i $a0, %ie_pc_hi20
1289 relocateNoSym(loc, type: R_LARCH_TLS_IE_PC_HI20, val);
1290 break;
1291 case R_LARCH_TLS_DESC_CALL:
1292 write32le(P: loc, V: insn(op: ctx.arg.is64 ? LD_D : LD_W, d: R_A0, j: R_A0,
1293 k: 0)); // ld.[wd] $a0, $a0, %ie_pc_lo12
1294 relocateNoSym(loc, type: R_LARCH_TLS_IE_PC_LO12, val);
1295 break;
1296 default:
1297 llvm_unreachable("unsupported relocation for TLSDESC to IE");
1298 }
1299}
1300
1301// Convert TLSDESC GD/LD to LE.
1302// The code sequence obtained in the normal or medium code model is as follows:
1303// * lu12i.w $a0, %le_hi20(sym) # le_hi20 != 0, otherwise NOP
1304// * ori $a0, src, %le_lo12(sym) # le_hi20 != 0, src = $a0,
1305// # otherwise, src = $zero
1306// See the comment in tlsdescToIe for detailed information.
1307void LoongArch::tlsdescToLe(uint8_t *loc, const Relocation &rel,
1308 uint64_t val) const {
1309 assert(isInt<32>(val) &&
1310 "val exceeds the range of medium code model in tlsdescToLe");
1311
1312 bool isUInt12 = isUInt<12>(x: val);
1313 switch (rel.type) {
1314 case R_LARCH_TLS_DESC_PC_HI20:
1315 case R_LARCH_TLS_DESC_PC_LO12:
1316 case R_LARCH_TLS_DESC_PCREL20_S2:
1317 write32le(P: loc, V: insn(op: ANDI, d: R_ZERO, j: R_ZERO, k: 0)); // nop
1318 break;
1319 case R_LARCH_TLS_DESC_LD:
1320 if (isUInt12)
1321 write32le(P: loc, V: insn(op: ANDI, d: R_ZERO, j: R_ZERO, k: 0)); // nop
1322 else
1323 write32le(P: loc, V: insn(op: LU12I_W, d: R_A0, j: extractBits(v: val, begin: 31, end: 12),
1324 k: 0)); // lu12i.w $a0, %le_hi20
1325 break;
1326 case R_LARCH_TLS_DESC_CALL:
1327 if (isUInt12)
1328 write32le(P: loc, V: insn(op: ORI, d: R_A0, j: R_ZERO, k: val)); // ori $a0, $zero, %le_lo12
1329 else
1330 write32le(P: loc,
1331 V: insn(op: ORI, d: R_A0, j: R_A0, k: lo12(val))); // ori $a0, $a0, %le_lo12
1332 break;
1333 default:
1334 llvm_unreachable("unsupported relocation for TLSDESC to LE");
1335 }
1336}
1337
1338// Try GOT indirection to PC relative optimization.
1339// From:
1340// * pcalau12i $a0, %got_pc_hi20(sym_got)
1341// * ld.w/d $a0, $a0, %got_pc_lo12(sym_got)
1342// To:
1343// * pcalau12i $a0, %pc_hi20(sym)
1344// * addi.w/d $a0, $a0, %pc_lo12(sym)
1345//
1346// Note: Althouth the optimization has been performed, the GOT entries still
1347// exists, similarly to AArch64. Eliminating the entries will increase code
1348// complexity.
1349bool LoongArch::tryGotToPCRel(uint8_t *loc, const Relocation &rHi20,
1350 const Relocation &rLo12, uint64_t secAddr) const {
1351 // Check if the relocations apply to consecutive instructions.
1352 if (rHi20.offset + 4 != rLo12.offset)
1353 return false;
1354
1355 // Check if the relocations reference the same symbol and skip undefined,
1356 // preemptible and STT_GNU_IFUNC symbols.
1357 if (!rHi20.sym || rHi20.sym != rLo12.sym || !rHi20.sym->isDefined() ||
1358 rHi20.sym->isPreemptible || rHi20.sym->isGnuIFunc())
1359 return false;
1360
1361 // GOT references to absolute symbols can't be relaxed to use PCALAU12I/ADDI
1362 // in position-independent code because these instructions produce a relative
1363 // address.
1364 if ((ctx.arg.isPic && !cast<Defined>(Val&: *rHi20.sym).section))
1365 return false;
1366
1367 // Check if the addends of the both relocations are zero.
1368 if (rHi20.addend != 0 || rLo12.addend != 0)
1369 return false;
1370
1371 const uint32_t currInsn = read32le(P: loc);
1372 const uint32_t nextInsn = read32le(P: loc + 4);
1373 const uint32_t ldOpcode = ctx.arg.is64 ? LD_D : LD_W;
1374 // Check if the first instruction is PCALAU12I and the second instruction is
1375 // LD.
1376 if ((currInsn & 0xfe000000) != PCALAU12I ||
1377 (nextInsn & 0xffc00000) != ldOpcode)
1378 return false;
1379
1380 // Check if use the same register.
1381 if (getD5(v: currInsn) != getJ5(v: nextInsn) || getJ5(v: nextInsn) != getD5(v: nextInsn))
1382 return false;
1383
1384 Symbol &sym = *rHi20.sym;
1385 uint64_t symLocal = sym.getVA(ctx);
1386 const int64_t displace = symLocal - getLoongArchPage(p: secAddr + rHi20.offset);
1387 // Check if the symbol address is in
1388 // [(PC & ~0xfff) - 2GiB - 0x800, (PC & ~0xfff) + 2GiB - 0x800).
1389 const int64_t underflow = -0x80000000LL - 0x800;
1390 const int64_t overflow = 0x80000000LL - 0x800;
1391 if (!(displace >= underflow && displace < overflow))
1392 return false;
1393
1394 Relocation newRHi20 = {.expr: RE_LOONGARCH_PAGE_PC, .type: R_LARCH_PCALA_HI20, .offset: rHi20.offset,
1395 .addend: rHi20.addend, .sym: &sym};
1396 Relocation newRLo12 = {.expr: R_ABS, .type: R_LARCH_PCALA_LO12, .offset: rLo12.offset, .addend: rLo12.addend,
1397 .sym: &sym};
1398 uint64_t pageDelta =
1399 getLoongArchPageDelta(dest: symLocal, pc: secAddr + rHi20.offset, type: rHi20.type);
1400 // pcalau12i $a0, %pc_hi20
1401 write32le(P: loc, V: insn(op: PCALAU12I, d: getD5(v: currInsn), j: 0, k: 0));
1402 relocate(loc, rel: newRHi20, val: pageDelta);
1403 // addi.w/d $a0, $a0, %pc_lo12
1404 write32le(P: loc + 4, V: insn(op: ctx.arg.is64 ? ADDI_D : ADDI_W, d: getD5(v: nextInsn),
1405 j: getJ5(v: nextInsn), k: 0));
1406 relocate(loc: loc + 4, rel: newRLo12, val: SignExtend64(X: symLocal, B: 64));
1407 return true;
1408}
1409
1410// During TLSDESC GD_TO_IE, the converted code sequence always includes an
1411// instruction related to the Lo12 relocation (ld.[wd]). To obtain correct val
1412// in `getRelocTargetVA`, expr of this instruction should be adjusted to
1413// R_RELAX_TLS_GD_TO_IE_ABS, while expr of other instructions related to the
1414// Hi20 relocation (pcalau12i) should be adjusted to
1415// RE_LOONGARCH_RELAX_TLS_GD_TO_IE_PAGE_PC. Specifically, in the normal or
1416// medium code model, the instruction with relocation R_LARCH_TLS_DESC_CALL is
1417// the candidate of Lo12 relocation.
1418RelExpr LoongArch::adjustTlsExpr(RelType type, RelExpr expr) const {
1419 if (expr == R_RELAX_TLS_GD_TO_IE) {
1420 if (type != R_LARCH_TLS_DESC_CALL)
1421 return RE_LOONGARCH_RELAX_TLS_GD_TO_IE_PAGE_PC;
1422 return R_RELAX_TLS_GD_TO_IE_ABS;
1423 }
1424 return expr;
1425}
1426
1427static bool pairForGotRels(ArrayRef<Relocation> relocs) {
1428 // Check if R_LARCH_GOT_PC_HI20 and R_LARCH_GOT_PC_LO12 always appear in
1429 // pairs.
1430 size_t i = 0;
1431 const size_t size = relocs.size();
1432 for (; i != size; ++i) {
1433 if (relocs[i].type == R_LARCH_GOT_PC_HI20) {
1434 if (i + 1 < size && relocs[i + 1].type == R_LARCH_GOT_PC_LO12) {
1435 ++i;
1436 continue;
1437 }
1438 if (relaxable(relocs, i) && i + 2 < size &&
1439 relocs[i + 2].type == R_LARCH_GOT_PC_LO12) {
1440 i += 2;
1441 continue;
1442 }
1443 break;
1444 } else if (relocs[i].type == R_LARCH_GOT_PC_LO12) {
1445 break;
1446 }
1447 }
1448 return i == size;
1449}
1450
1451void LoongArch::relocateAlloc(InputSection &sec, uint8_t *buf) const {
1452 const unsigned bits = ctx.arg.is64 ? 64 : 32;
1453 uint64_t secAddr = sec.getOutputSection()->addr + sec.outSecOff;
1454 bool isExtreme = false, isRelax = false;
1455 const MutableArrayRef<Relocation> relocs = sec.relocs();
1456 const bool isPairForGotRels = pairForGotRels(relocs);
1457 for (size_t i = 0, size = relocs.size(); i != size; ++i) {
1458 Relocation &rel = relocs[i];
1459 uint8_t *loc = buf + rel.offset;
1460 uint64_t val = SignExtend64(
1461 X: sec.getRelocTargetVA(ctx, r: rel, p: secAddr + rel.offset), B: bits);
1462
1463 switch (rel.expr) {
1464 case R_RELAX_HINT:
1465 continue;
1466 case R_RELAX_TLS_IE_TO_LE:
1467 if (rel.type == R_LARCH_TLS_IE_PC_HI20) {
1468 // LoongArch does not support IE to LE optimization in the extreme code
1469 // model. In this case, the relocs are as follows:
1470 //
1471 // * i -- R_LARCH_TLS_IE_PC_HI20
1472 // * i+1 -- R_LARCH_TLS_IE_PC_LO12
1473 // * i+2 -- R_LARCH_TLS_IE64_PC_LO20
1474 // * i+3 -- R_LARCH_TLS_IE64_PC_HI12
1475 isExtreme =
1476 i + 2 < size && relocs[i + 2].type == R_LARCH_TLS_IE64_PC_LO20;
1477 }
1478 if (isExtreme) {
1479 rel.expr = getRelExpr(type: rel.type, s: *rel.sym, loc);
1480 val = SignExtend64(X: sec.getRelocTargetVA(ctx, r: rel, p: secAddr + rel.offset),
1481 B: bits);
1482 relocateNoSym(loc, type: rel.type, val);
1483 } else {
1484 isRelax = relaxable(relocs, i);
1485 if (isRelax && rel.type == R_LARCH_TLS_IE_PC_HI20 && isUInt<12>(x: val))
1486 continue;
1487 tlsIeToLe(loc, rel, val);
1488 }
1489 continue;
1490 case RE_LOONGARCH_RELAX_TLS_GD_TO_IE_PAGE_PC:
1491 if (rel.type == R_LARCH_TLS_DESC_PC_HI20) {
1492 // LoongArch does not support TLSDESC GD/LD to LE/IE optimization in the
1493 // extreme code model. In these cases, the relocs are as follows:
1494 //
1495 // * i -- R_LARCH_TLS_DESC_PC_HI20
1496 // * i+1 -- R_LARCH_TLS_DESC_PC_LO12
1497 // * i+2 -- R_LARCH_TLS_DESC64_PC_LO20
1498 // * i+3 -- R_LARCH_TLS_DESC64_PC_HI12
1499 isExtreme =
1500 i + 2 < size && relocs[i + 2].type == R_LARCH_TLS_DESC64_PC_LO20;
1501 }
1502 [[fallthrough]];
1503 case R_RELAX_TLS_GD_TO_IE_ABS:
1504 if (isExtreme) {
1505 if (rel.type == R_LARCH_TLS_DESC_CALL)
1506 continue;
1507 rel.expr = getRelExpr(type: rel.type, s: *rel.sym, loc);
1508 val = SignExtend64(X: sec.getRelocTargetVA(ctx, r: rel, p: secAddr + rel.offset),
1509 B: bits);
1510 relocateNoSym(loc, type: rel.type, val);
1511 } else {
1512 isRelax = relaxable(relocs, i);
1513 if (isRelax && (rel.type == R_LARCH_TLS_DESC_PC_HI20 ||
1514 rel.type == R_LARCH_TLS_DESC_PC_LO12))
1515 continue;
1516 tlsdescToIe(loc, rel, val);
1517 }
1518 continue;
1519 case R_RELAX_TLS_GD_TO_LE:
1520 if (rel.type == R_LARCH_TLS_DESC_PC_HI20) {
1521 isExtreme =
1522 i + 2 < size && relocs[i + 2].type == R_LARCH_TLS_DESC64_PC_LO20;
1523 }
1524 if (isExtreme) {
1525 if (rel.type == R_LARCH_TLS_DESC_CALL)
1526 continue;
1527 rel.expr = getRelExpr(type: rel.type, s: *rel.sym, loc);
1528 val = SignExtend64(X: sec.getRelocTargetVA(ctx, r: rel, p: secAddr + rel.offset),
1529 B: bits);
1530 relocateNoSym(loc, type: rel.type, val);
1531 } else {
1532 isRelax = relaxable(relocs, i);
1533 if (isRelax && (rel.type == R_LARCH_TLS_DESC_PC_HI20 ||
1534 rel.type == R_LARCH_TLS_DESC_PC_LO12 ||
1535 (rel.type == R_LARCH_TLS_DESC_LD && isUInt<12>(x: val))))
1536 continue;
1537 tlsdescToLe(loc, rel, val);
1538 }
1539 continue;
1540 case RE_LOONGARCH_GOT_PAGE_PC:
1541 // In LoongArch, we try GOT indirection to PC relative optimization in
1542 // normal or medium code model, whether or not with R_LARCH_RELAX
1543 // relocation. Moreover, if the original code sequence can be relaxed to a
1544 // single instruction `pcaddi`, the first instruction will be removed and
1545 // it will not reach here.
1546 if (isPairForGotRels && rel.type == R_LARCH_GOT_PC_HI20) {
1547 bool isRelax = relaxable(relocs, i);
1548 const Relocation lo12Rel = isRelax ? relocs[i + 2] : relocs[i + 1];
1549 if (lo12Rel.type == R_LARCH_GOT_PC_LO12 &&
1550 tryGotToPCRel(loc, rHi20: rel, rLo12: lo12Rel, secAddr)) {
1551 // isRelax: skip relocations R_LARCH_RELAX, R_LARCH_GOT_PC_LO12
1552 // !isRelax: skip relocation R_LARCH_GOT_PC_LO12
1553 i += isRelax ? 2 : 1;
1554 continue;
1555 }
1556 }
1557 break;
1558 default:
1559 break;
1560 }
1561 relocate(loc, rel, val);
1562 }
1563}
1564
1565// When relaxing just R_LARCH_ALIGN, relocDeltas is usually changed only once in
1566// the absence of a linker script. For call and load/store R_LARCH_RELAX, code
1567// shrinkage may reduce displacement and make more relocations eligible for
1568// relaxation. Code shrinkage may increase displacement to a call/load/store
1569// target at a higher fixed address, invalidating an earlier relaxation. Any
1570// change in section sizes can have cascading effect and require another
1571// relaxation pass.
1572bool LoongArch::relaxOnce(int pass) const {
1573 if (pass == 0)
1574 initSymbolAnchors(ctx);
1575
1576 SmallVector<InputSection *, 0> storage;
1577 bool changed = false;
1578 for (OutputSection *osec : ctx.outputSections) {
1579 if (!(osec->flags & SHF_EXECINSTR))
1580 continue;
1581 for (InputSection *sec : getInputSections(os: *osec, storage))
1582 changed |= relax(ctx, sec&: *sec);
1583 }
1584 return changed;
1585}
1586
1587void LoongArch::finalizeRelax(int passes) const {
1588 Log(ctx) << "relaxation passes: " << passes;
1589 SmallVector<InputSection *, 0> storage;
1590 for (OutputSection *osec : ctx.outputSections) {
1591 if (!(osec->flags & SHF_EXECINSTR))
1592 continue;
1593 for (InputSection *sec : getInputSections(os: *osec, storage)) {
1594 RelaxAux &aux = *sec->relaxAux;
1595 if (!aux.relocDeltas)
1596 continue;
1597
1598 MutableArrayRef<Relocation> rels = sec->relocs();
1599 ArrayRef<uint8_t> old = sec->content();
1600 size_t newSize = old.size() - aux.relocDeltas[rels.size() - 1];
1601 size_t writesIdx = 0;
1602 uint8_t *p = ctx.bAlloc.Allocate<uint8_t>(Num: newSize);
1603 uint64_t offset = 0;
1604 int64_t delta = 0;
1605 sec->content_ = p;
1606 sec->size = newSize;
1607 sec->bytesDropped = 0;
1608
1609 // Update section content: remove NOPs for R_LARCH_ALIGN and rewrite
1610 // instructions for relaxed relocations.
1611 for (size_t i = 0, e = rels.size(); i != e; ++i) {
1612 uint32_t remove = aux.relocDeltas[i] - delta;
1613 delta = aux.relocDeltas[i];
1614 if (remove == 0 && aux.relocTypes[i] == R_LARCH_NONE)
1615 continue;
1616
1617 // Copy from last location to the current relocated location.
1618 Relocation &r = rels[i];
1619 uint64_t size = r.offset - offset;
1620 memcpy(dest: p, src: old.data() + offset, n: size);
1621 p += size;
1622
1623 int64_t skip = 0;
1624 if (RelType newType = aux.relocTypes[i]) {
1625 switch (newType) {
1626 case R_LARCH_RELAX:
1627 break;
1628 case R_LARCH_PCREL20_S2:
1629 skip = 4;
1630 write32le(P: p, V: aux.writes[writesIdx++]);
1631 // RelExpr is needed for relocating.
1632 r.expr = r.sym->hasFlag(bit: NEEDS_PLT) ? R_PLT_PC : R_PC;
1633 break;
1634 case R_LARCH_B26:
1635 case R_LARCH_TLS_LE_LO12_R:
1636 skip = 4;
1637 write32le(P: p, V: aux.writes[writesIdx++]);
1638 break;
1639 case R_LARCH_TLS_GD_PCREL20_S2:
1640 // Note: R_LARCH_TLS_LD_PCREL20_S2 must also use R_TLSGD_PC instead
1641 // of R_TLSLD_PC due to historical reasons. In fact, right now TLSLD
1642 // behaves exactly like TLSGD on LoongArch.
1643 //
1644 // This reason has also been mentioned in mold commit:
1645 // https://github.com/rui314/mold/commit/5dfa1cf07c03bd57cb3d493b652ef22441bcd71c
1646 case R_LARCH_TLS_LD_PCREL20_S2:
1647 skip = 4;
1648 write32le(P: p, V: aux.writes[writesIdx++]);
1649 r.expr = R_TLSGD_PC;
1650 break;
1651 case R_LARCH_TLS_DESC_PCREL20_S2:
1652 skip = 4;
1653 write32le(P: p, V: aux.writes[writesIdx++]);
1654 r.expr = R_TLSDESC_PC;
1655 break;
1656 default:
1657 llvm_unreachable("unsupported type");
1658 }
1659 }
1660
1661 p += skip;
1662 offset = r.offset + skip + remove;
1663 }
1664 memcpy(dest: p, src: old.data() + offset, n: old.size() - offset);
1665
1666 // Subtract the previous relocDeltas value from the relocation offset.
1667 // For a pair of R_LARCH_XXX/R_LARCH_RELAX with the same offset, decrease
1668 // their r_offset by the same delta.
1669 delta = 0;
1670 for (size_t i = 0, e = rels.size(); i != e;) {
1671 uint64_t cur = rels[i].offset;
1672 do {
1673 rels[i].offset -= delta;
1674 if (aux.relocTypes[i] != R_LARCH_NONE)
1675 rels[i].type = aux.relocTypes[i];
1676 } while (++i != e && rels[i].offset == cur);
1677 delta = aux.relocDeltas[i - 1];
1678 }
1679 }
1680 }
1681}
1682
1683void elf::setLoongArchTargetInfo(Ctx &ctx) {
1684 ctx.target.reset(p: new LoongArch(ctx));
1685}
1686