1//===- RISCV.cpp ----------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "InputFiles.h"
10#include "OutputSections.h"
11#include "RelocScan.h"
12#include "Symbols.h"
13#include "SyntheticSections.h"
14#include "Target.h"
15#include "llvm/Support/ELFAttributes.h"
16#include "llvm/Support/LEB128.h"
17#include "llvm/Support/RISCVAttributeParser.h"
18#include "llvm/Support/RISCVAttributes.h"
19#include "llvm/Support/TimeProfiler.h"
20#include "llvm/TargetParser/RISCVISAInfo.h"
21
22using namespace llvm;
23using namespace llvm::object;
24using namespace llvm::support::endian;
25using namespace llvm::ELF;
26using namespace lld;
27using namespace lld::elf;
28
29namespace {
30
31class RISCV final : public TargetInfo {
32public:
33 RISCV(Ctx &);
34 uint32_t calcEFlags() const override;
35 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
36 void writeGotHeader(uint8_t *buf) const override;
37 void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
38 void writeIgotPlt(uint8_t *buf, const Symbol &s) const override;
39 void writePltHeader(uint8_t *buf) const override;
40 void writePlt(uint8_t *buf, const Symbol &sym,
41 uint64_t pltEntryAddr) const override;
42 template <class ELFT, class RelTy>
43 void scanSectionImpl(InputSectionBase &, Relocs<RelTy>, unsigned shard);
44 void scanSection(InputSectionBase &, unsigned shard) override;
45 RelType getDynRel(RelType type) const override;
46 RelExpr getRelExpr(RelType type, const Symbol &s,
47 const uint8_t *loc) const override;
48 void relocate(uint8_t *loc, const Relocation &rel,
49 uint64_t val) const override;
50 void relocateAlloc(InputSection &sec, uint8_t *buf) const override;
51 bool relaxOnce(int pass) const override;
52 template <class ELFT, class RelTy>
53 bool synthesizeAlignForInput(uint64_t &dot, InputSection *sec,
54 Relocs<RelTy> rels);
55 template <class ELFT, class RelTy>
56 void finalizeSynthesizeAligns(uint64_t &dot, InputSection *sec,
57 Relocs<RelTy> rels);
58 template <class ELFT>
59 bool synthesizeAlignAux(uint64_t &dot, InputSection *sec);
60 bool synthesizeAlign(uint64_t &dot, InputSection *sec) override;
61 void finalizeRelax(int passes) const override;
62
63 // The following two variables are used by synthesized ALIGN relocations.
64 InputSection *baseSec = nullptr;
65 // r_offset and r_addend pairs.
66 SmallVector<std::pair<uint64_t, uint64_t>, 0> synthesizedAligns;
67};
68
69} // end anonymous namespace
70
71// These are internal relocation numbers for GP/X0 relaxation. They aren't part
72// of the psABI spec.
73#define INTERNAL_R_RISCV_GPREL_I 256
74#define INTERNAL_R_RISCV_GPREL_S 257
75#define INTERNAL_R_RISCV_X0REL_I 258
76#define INTERNAL_R_RISCV_X0REL_S 259
77
78const uint64_t dtpOffset = 0x800;
79
80namespace {
81enum Op {
82 ADDI = 0x13,
83 AUIPC = 0x17,
84 JALR = 0x67,
85 LD = 0x3003,
86 LUI = 0x37,
87 LW = 0x2003,
88 SRLI = 0x5013,
89 SUB = 0x40000033,
90};
91
92enum Reg {
93 X_X0 = 0,
94 X_RA = 1,
95 X_GP = 3,
96 X_TP = 4,
97 X_T0 = 5,
98 X_T1 = 6,
99 X_T2 = 7,
100 X_A0 = 10,
101 X_T3 = 28,
102};
103} // namespace
104
105static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
106static uint32_t lo12(uint32_t val) { return val & 4095; }
107
108static uint32_t itype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t imm) {
109 return op | (rd << 7) | (rs1 << 15) | (imm << 20);
110}
111static uint32_t rtype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t rs2) {
112 return op | (rd << 7) | (rs1 << 15) | (rs2 << 20);
113}
114static uint32_t utype(uint32_t op, uint32_t rd, uint32_t imm) {
115 return op | (rd << 7) | (imm << 12);
116}
117
118// Extract bits v[begin:end], where range is inclusive, and begin must be < 63.
119static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) {
120 return (v & ((1ULL << (begin + 1)) - 1)) >> end;
121}
122
123static uint32_t setLO12_I(uint32_t insn, uint32_t imm) {
124 return (insn & 0xfffff) | (imm << 20);
125}
126static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
127 return (insn & 0x1fff07f) | (extractBits(v: imm, begin: 11, end: 5) << 25) |
128 (extractBits(v: imm, begin: 4, end: 0) << 7);
129}
130
131RISCV::RISCV(Ctx &ctx) : TargetInfo(ctx) {
132 copyRel = R_RISCV_COPY;
133 pltRel = R_RISCV_JUMP_SLOT;
134 relativeRel = R_RISCV_RELATIVE;
135 iRelativeRel = R_RISCV_IRELATIVE;
136 if (ctx.arg.is64) {
137 symbolicRel = R_RISCV_64;
138 tlsModuleIndexRel = R_RISCV_TLS_DTPMOD64;
139 tlsOffsetRel = R_RISCV_TLS_DTPREL64;
140 tlsGotRel = R_RISCV_TLS_TPREL64;
141 } else {
142 symbolicRel = R_RISCV_32;
143 tlsModuleIndexRel = R_RISCV_TLS_DTPMOD32;
144 tlsOffsetRel = R_RISCV_TLS_DTPREL32;
145 tlsGotRel = R_RISCV_TLS_TPREL32;
146 }
147 gotRel = symbolicRel;
148 tlsDescRel = R_RISCV_TLSDESC;
149
150 // .got[0] = _DYNAMIC
151 gotHeaderEntriesNum = 1;
152
153 // .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map
154 gotPltHeaderEntriesNum = 2;
155
156 pltHeaderSize = 32;
157 pltEntrySize = 16;
158 ipltEntrySize = 16;
159}
160
161static uint32_t getEFlags(Ctx &ctx, InputFile *f) {
162 if (ctx.arg.is64)
163 return cast<ObjFile<ELF64LE>>(Val: f)->getObj().getHeader().e_flags;
164 return cast<ObjFile<ELF32LE>>(Val: f)->getObj().getHeader().e_flags;
165}
166
167uint32_t RISCV::calcEFlags() const {
168 // If there are only binary input files (from -b binary), use a
169 // value of 0 for the ELF header flags.
170 if (ctx.objectFiles.empty())
171 return 0;
172
173 uint32_t target = getEFlags(ctx, f: ctx.objectFiles.front());
174 for (InputFile *f : ctx.objectFiles) {
175 uint32_t eflags = getEFlags(ctx, f);
176 if (eflags & EF_RISCV_RVC)
177 target |= EF_RISCV_RVC;
178
179 if ((eflags & EF_RISCV_FLOAT_ABI) != (target & EF_RISCV_FLOAT_ABI))
180 Err(ctx) << f
181 << ": cannot link object files with different "
182 "floating-point ABI from "
183 << ctx.objectFiles[0];
184
185 if ((eflags & EF_RISCV_RVE) != (target & EF_RISCV_RVE))
186 Err(ctx) << f << ": cannot link object files with different EF_RISCV_RVE";
187 }
188
189 return target;
190}
191
192int64_t RISCV::getImplicitAddend(const uint8_t *buf, RelType type) const {
193 switch (type) {
194 default:
195 InternalErr(ctx, buf) << "cannot read addend for relocation " << type;
196 return 0;
197 case R_RISCV_32:
198 case R_RISCV_TLS_DTPMOD32:
199 case R_RISCV_TLS_DTPREL32:
200 case R_RISCV_TLS_TPREL32:
201 return SignExtend64<32>(x: read32le(P: buf));
202 case R_RISCV_64:
203 case R_RISCV_TLS_DTPMOD64:
204 case R_RISCV_TLS_DTPREL64:
205 case R_RISCV_TLS_TPREL64:
206 return read64le(P: buf);
207 case R_RISCV_RELATIVE:
208 case R_RISCV_IRELATIVE:
209 return ctx.arg.is64 ? read64le(P: buf) : read32le(P: buf);
210 case R_RISCV_NONE:
211 case R_RISCV_JUMP_SLOT:
212 // These relocations are defined as not having an implicit addend.
213 return 0;
214 case R_RISCV_TLSDESC:
215 return ctx.arg.is64 ? read64le(P: buf + 8) : read32le(P: buf + 4);
216 }
217}
218
219void RISCV::writeGotHeader(uint8_t *buf) const {
220 if (ctx.arg.is64)
221 write64le(P: buf, V: ctx.in.dynamic->getVA());
222 else
223 write32le(P: buf, V: ctx.in.dynamic->getVA());
224}
225
226void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const {
227 if (ctx.arg.is64)
228 write64le(P: buf, V: ctx.in.plt->getVA());
229 else
230 write32le(P: buf, V: ctx.in.plt->getVA());
231}
232
233void RISCV::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
234 if (ctx.arg.writeAddends) {
235 if (ctx.arg.is64)
236 write64le(P: buf, V: s.getVA(ctx));
237 else
238 write32le(P: buf, V: s.getVA(ctx));
239 }
240}
241
242void RISCV::writePltHeader(uint8_t *buf) const {
243 // If using lpad (CFI):
244 //
245 // 1: auipc t3, %pcrel_hi(.got.plt)
246 // sub t1, t1, t2
247 // l[w|d] t2, %pcrel_lo(1b)(t3)
248 // addi t1, t1, -(hdr size + 16)
249 // addi t0, t3, %pcrel_lo(1b)
250 // srli t1, t1, log2(16/PTRSIZE)
251 // l[w|d] t0, PTRSIZE(t0)
252 // jr t2
253 //
254 // If not using lpad:
255 //
256 // 1: auipc t2, %pcrel_hi(.got.plt)
257 // sub t1, t1, t3
258 // l[w|d] t3, %pcrel_lo(1b)(t2) ; t3 = _dl_runtime_resolve
259 // addi t1, t1, -pltHeaderSize-12 ; t1 = &.plt[i] - &.plt[0]
260 // addi t0, t2, %pcrel_lo(1b)
261 // srli t1, t1, (rv64?1:2) ; t1 = &.got.plt[i] - &.got.plt[0]
262 // l[w|d] t0, Wordsize(t0) ; t0 = link_map
263 // jr t3
264 bool lpad =
265 ctx.arg.andFeatures & GNU_PROPERTY_RISCV_FEATURE_1_CFI_LP_UNLABELED;
266 uint32_t offset = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA();
267 uint32_t load = ctx.arg.is64 ? LD : LW;
268 uint32_t auipcReg = lpad ? X_T3 : X_T2;
269 uint32_t workReg = lpad ? X_T2 : X_T3;
270
271 write32le(P: buf + 0, V: utype(op: AUIPC, rd: auipcReg, imm: hi20(val: offset)));
272 write32le(P: buf + 4, V: rtype(op: SUB, rd: X_T1, rs1: X_T1, rs2: workReg));
273 write32le(P: buf + 8, V: itype(op: load, rd: workReg, rs1: auipcReg, imm: lo12(val: offset)));
274 write32le(P: buf + 12, V: itype(op: ADDI, rd: X_T1, rs1: X_T1,
275 imm: -ctx.target->pltHeaderSize - (lpad ? 16 : 12)));
276 write32le(P: buf + 16, V: itype(op: ADDI, rd: X_T0, rs1: auipcReg, imm: lo12(val: offset)));
277 write32le(P: buf + 20, V: itype(op: SRLI, rd: X_T1, rs1: X_T1, imm: ctx.arg.is64 ? 1 : 2));
278 write32le(P: buf + 24, V: itype(op: load, rd: X_T0, rs1: X_T0, imm: ctx.arg.wordsize));
279 write32le(P: buf + 28, V: itype(op: JALR, rd: X_X0, rs1: workReg, imm: 0));
280}
281
282void RISCV::writePlt(uint8_t *buf, const Symbol &sym,
283 uint64_t pltEntryAddr) const {
284 // If using lpad:
285 //
286 // lpad 0
287 // 1: auipc t2, %pcrel_hi(function@.got.plt)
288 // l[w|d] t2, %pcrel_lo(1b)(t2)
289 // jalr t1, t2
290 //
291 // If not using lpad:
292 //
293 // 1: auipc t3, %pcrel_hi(f@.got.plt)
294 // l[w|d] t3, %pcrel_lo(1b)(t3)
295 // jalr t1, t3
296 // nop
297 bool lpad =
298 ctx.arg.andFeatures & GNU_PROPERTY_RISCV_FEATURE_1_CFI_LP_UNLABELED;
299 uint32_t auipcOffset = lpad * 4;
300 uint32_t offset = sym.getGotPltVA(ctx) - pltEntryAddr - auipcOffset;
301 uint32_t rd = lpad ? X_T2 : X_T3;
302 if (lpad)
303 write32le(P: buf + 0, V: utype(op: AUIPC, rd: X_X0, imm: 0)); // lpad 0
304 write32le(P: buf + 0 + auipcOffset, V: utype(op: AUIPC, rd, imm: hi20(val: offset)));
305 write32le(P: buf + 4 + auipcOffset,
306 V: itype(op: ctx.arg.is64 ? LD : LW, rd, rs1: rd, imm: lo12(val: offset)));
307 write32le(P: buf + 8 + auipcOffset, V: itype(op: JALR, rd: X_T1, rs1: rd, imm: 0));
308 if (!lpad)
309 write32le(P: buf + 12, V: itype(op: ADDI, rd: X_X0, rs1: X_X0, imm: 0));
310}
311
312RelType RISCV::getDynRel(RelType type) const {
313 return type == ctx.target->symbolicRel ? type
314 : static_cast<RelType>(R_RISCV_NONE);
315}
316
317// Only needed to support relocations used by relocateNonAlloc and
318// preprocessRelocs.
319RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s,
320 const uint8_t *loc) const {
321 switch (type) {
322 case R_RISCV_NONE:
323 return R_NONE;
324 case R_RISCV_32:
325 case R_RISCV_64:
326 return R_ABS;
327 case R_RISCV_ADD8:
328 case R_RISCV_ADD16:
329 case R_RISCV_ADD32:
330 case R_RISCV_ADD64:
331 case R_RISCV_SET6:
332 case R_RISCV_SET8:
333 case R_RISCV_SET16:
334 case R_RISCV_SET32:
335 case R_RISCV_SUB6:
336 case R_RISCV_SUB8:
337 case R_RISCV_SUB16:
338 case R_RISCV_SUB32:
339 case R_RISCV_SUB64:
340 return RE_RISCV_ADD;
341 case R_RISCV_32_PCREL:
342 return R_PC;
343 case R_RISCV_SET_ULEB128:
344 case R_RISCV_SUB_ULEB128:
345 return RE_RISCV_LEB128;
346 default:
347 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v
348 << ") against symbol " << &s;
349 return R_NONE;
350 }
351}
352
353template <class ELFT, class RelTy>
354void RISCV::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels,
355 unsigned shard) {
356 RelocScan rs(ctx, &sec, shard);
357 // Many relocations end up in sec.relocations.
358 sec.relocations.reserve(N: rels.size());
359
360 StringRef vendor;
361 for (auto it = rels.begin(); it != rels.end(); ++it) {
362 RelType type = it->getType(false);
363 uint32_t symIndex = it->getSymbol(false);
364 Symbol &sym = sec.getFile<ELFT>()->getSymbol(symIndex);
365 uint64_t offset = it->r_offset;
366 if (sym.isUndefined() && symIndex != 0 &&
367 rs.maybeReportUndefined(sym&: cast<Undefined>(Val&: sym), offset))
368 continue;
369 int64_t addend = rs.getAddend<ELFT>(*it, type);
370 RelExpr expr;
371 // Relocation types that only need a RelExpr set `expr` and break out of
372 // the switch to reach rs.process(). Types that need special handling
373 // (fast-path helpers, TLS) call a handler and use `continue`.
374 switch (type) {
375 case R_RISCV_NONE:
376 continue;
377
378 // Absolute relocations:
379 case R_RISCV_32:
380 case R_RISCV_64:
381 case R_RISCV_HI20:
382 case R_RISCV_LO12_I:
383 case R_RISCV_LO12_S:
384 expr = R_ABS;
385 break;
386
387 // PC-relative relocations:
388 case R_RISCV_JAL:
389 case R_RISCV_BRANCH:
390 case R_RISCV_PCREL_HI20:
391 case R_RISCV_RVC_BRANCH:
392 case R_RISCV_RVC_JUMP:
393 case R_RISCV_32_PCREL:
394 rs.processR_PC(type, offset, addend, sym);
395 continue;
396 case R_RISCV_PCREL_LO12_I:
397 case R_RISCV_PCREL_LO12_S:
398 expr = RE_RISCV_PC_INDIRECT;
399 break;
400
401 // PLT-generating relocations:
402 case R_RISCV_CALL:
403 case R_RISCV_CALL_PLT:
404 case R_RISCV_PLT32:
405 rs.processR_PLT_PC(type, offset, addend, sym);
406 continue;
407
408 // GOT-generating relocations:
409 case R_RISCV_GOT_HI20:
410 case R_RISCV_GOT32_PCREL:
411 expr = R_GOT_PC;
412 break;
413
414 // TLS relocations:
415 case R_RISCV_TPREL_HI20:
416 case R_RISCV_TPREL_LO12_I:
417 case R_RISCV_TPREL_LO12_S:
418 if (rs.checkTlsLe(offset, sym, type))
419 continue;
420 expr = R_TPREL;
421 break;
422 case R_RISCV_TLS_GOT_HI20:
423 // There is no IE to LE optimization.
424 rs.handleTlsIe<false>(ieExpr: R_GOT_PC, type, offset, addend, sym);
425 continue;
426 case R_RISCV_TLS_GD_HI20:
427 // There is no GD to IE/LE optimization.
428 rs.handleTlsGd(sharedExpr: R_TLSGD_PC, ieExpr: R_NONE, leExpr: R_NONE, type, offset, addend, sym);
429 continue;
430
431 // TLSDESC relocations:
432 case R_RISCV_TLSDESC_HI20:
433 rs.handleTlsDesc(sharedExpr: R_TLSDESC_PC, ieExpr: R_GOT_PC, type, offset, addend, sym);
434 continue;
435 case R_RISCV_TLSDESC_LOAD_LO12:
436 case R_RISCV_TLSDESC_ADD_LO12:
437 // R_RISCV_TLSDESC_{LOAD_LO12,ADD_LO12,CALL} reference a label, not the
438 // TLS symbol, so we cannot use handleTlsDesc (which sets NEEDS_TLSDESC).
439 // For TLSDESC->IE, use R_TPREL as well, but relocateAlloc uses isToLe
440 // (from HI20) to select the correct transform.
441 sec.addReloc(r: {.expr: ctx.arg.shared ? R_TLSDESC_PC : R_TPREL, .type: type, .offset: offset,
442 .addend: addend, .sym: &sym});
443 continue;
444 case R_RISCV_TLSDESC_CALL:
445 if (!ctx.arg.shared)
446 sec.addReloc(r: {.expr: R_TPREL, .type: type, .offset: offset, .addend: addend, .sym: &sym});
447 continue;
448
449 // Relaxation hints:
450 case R_RISCV_ALIGN:
451 sec.addReloc(r: {.expr: R_RELAX_HINT, .type: type, .offset: offset, .addend: addend, .sym: &sym});
452 continue;
453 case R_RISCV_TPREL_ADD:
454 case R_RISCV_RELAX:
455 if (ctx.arg.relax)
456 sec.addReloc(r: {.expr: R_RELAX_HINT, .type: type, .offset: offset, .addend: addend, .sym: &sym});
457 continue;
458
459 // Misc relocations:
460 case R_RISCV_ADD8:
461 case R_RISCV_ADD16:
462 case R_RISCV_ADD32:
463 case R_RISCV_ADD64:
464 case R_RISCV_SET6:
465 case R_RISCV_SET8:
466 case R_RISCV_SET16:
467 case R_RISCV_SET32:
468 case R_RISCV_SUB6:
469 case R_RISCV_SUB8:
470 case R_RISCV_SUB16:
471 case R_RISCV_SUB32:
472 case R_RISCV_SUB64:
473 expr = RE_RISCV_ADD;
474 break;
475 case R_RISCV_SET_ULEB128:
476 case R_RISCV_SUB_ULEB128:
477 expr = RE_RISCV_LEB128;
478 break;
479
480 case R_RISCV_VENDOR: {
481 auto it1 = it;
482 ++it1;
483 if (it1 == rels.end() || it1->getType(false) - 192u > 63u) {
484 Err(ctx) << getErrorLoc(ctx, loc: sec.content().data() + offset)
485 << "R_RISCV_VENDOR is not followed by a relocation of code "
486 "192 to 255";
487 continue;
488 }
489 vendor = sym.getName();
490 }
491 continue;
492 default:
493 auto diag = Err(ctx);
494 diag << getErrorLoc(ctx, loc: sec.content().data() + offset);
495 if (!vendor.empty()) {
496 diag << "unknown vendor-specific relocation (" << type.v
497 << ") in namespace '" << vendor << "' against symbol '" << &sym
498 << "'";
499 vendor = "";
500 } else {
501 diag << "unknown relocation (" << type.v << ") against symbol " << &sym;
502 }
503 continue;
504 }
505 rs.process(expr, type, offset, sym, addend);
506 }
507
508 // Sort relocations by offset for more efficient searching for
509 // R_RISCV_PCREL_HI20.
510 llvm::stable_sort(sec.relocs(),
511 [](const Relocation &lhs, const Relocation &rhs) {
512 return lhs.offset < rhs.offset;
513 });
514}
515
516void RISCV::scanSection(InputSectionBase &sec, unsigned shard) {
517 if (ctx.arg.is64)
518 elf::scanSection1<RISCV, ELF64LE>(target&: *this, sec, shard);
519 else
520 elf::scanSection1<RISCV, ELF32LE>(target&: *this, sec, shard);
521}
522
523void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
524 const unsigned bits = ctx.arg.wordsize * 8;
525
526 switch (rel.type) {
527 case R_RISCV_32:
528 write32le(P: loc, V: val);
529 return;
530 case R_RISCV_64:
531 write64le(P: loc, V: val);
532 return;
533
534 case R_RISCV_RVC_BRANCH: {
535 checkInt(ctx, loc, v: val, n: 9, rel);
536 checkAlignment(ctx, loc, v: val, n: 2, rel);
537 uint16_t insn = read16le(P: loc) & 0xE383;
538 uint16_t imm8 = extractBits(v: val, begin: 8, end: 8) << 12;
539 uint16_t imm4_3 = extractBits(v: val, begin: 4, end: 3) << 10;
540 uint16_t imm7_6 = extractBits(v: val, begin: 7, end: 6) << 5;
541 uint16_t imm2_1 = extractBits(v: val, begin: 2, end: 1) << 3;
542 uint16_t imm5 = extractBits(v: val, begin: 5, end: 5) << 2;
543 insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5;
544
545 write16le(P: loc, V: insn);
546 return;
547 }
548
549 case R_RISCV_RVC_JUMP: {
550 checkInt(ctx, loc, v: val, n: 12, rel);
551 checkAlignment(ctx, loc, v: val, n: 2, rel);
552 uint16_t insn = read16le(P: loc) & 0xE003;
553 uint16_t imm11 = extractBits(v: val, begin: 11, end: 11) << 12;
554 uint16_t imm4 = extractBits(v: val, begin: 4, end: 4) << 11;
555 uint16_t imm9_8 = extractBits(v: val, begin: 9, end: 8) << 9;
556 uint16_t imm10 = extractBits(v: val, begin: 10, end: 10) << 8;
557 uint16_t imm6 = extractBits(v: val, begin: 6, end: 6) << 7;
558 uint16_t imm7 = extractBits(v: val, begin: 7, end: 7) << 6;
559 uint16_t imm3_1 = extractBits(v: val, begin: 3, end: 1) << 3;
560 uint16_t imm5 = extractBits(v: val, begin: 5, end: 5) << 2;
561 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5;
562
563 write16le(P: loc, V: insn);
564 return;
565 }
566
567 case R_RISCV_JAL: {
568 checkInt(ctx, loc, v: val, n: 21, rel);
569 checkAlignment(ctx, loc, v: val, n: 2, rel);
570
571 uint32_t insn = read32le(P: loc) & 0xFFF;
572 uint32_t imm20 = extractBits(v: val, begin: 20, end: 20) << 31;
573 uint32_t imm10_1 = extractBits(v: val, begin: 10, end: 1) << 21;
574 uint32_t imm11 = extractBits(v: val, begin: 11, end: 11) << 20;
575 uint32_t imm19_12 = extractBits(v: val, begin: 19, end: 12) << 12;
576 insn |= imm20 | imm10_1 | imm11 | imm19_12;
577
578 write32le(P: loc, V: insn);
579 return;
580 }
581
582 case R_RISCV_BRANCH: {
583 checkInt(ctx, loc, v: val, n: 13, rel);
584 checkAlignment(ctx, loc, v: val, n: 2, rel);
585
586 uint32_t insn = read32le(P: loc) & 0x1FFF07F;
587 uint32_t imm12 = extractBits(v: val, begin: 12, end: 12) << 31;
588 uint32_t imm10_5 = extractBits(v: val, begin: 10, end: 5) << 25;
589 uint32_t imm4_1 = extractBits(v: val, begin: 4, end: 1) << 8;
590 uint32_t imm11 = extractBits(v: val, begin: 11, end: 11) << 7;
591 insn |= imm12 | imm10_5 | imm4_1 | imm11;
592
593 write32le(P: loc, V: insn);
594 return;
595 }
596
597 // auipc + jalr pair
598 case R_RISCV_CALL:
599 case R_RISCV_CALL_PLT: {
600 int64_t hi = SignExtend64(X: val + 0x800, B: bits) >> 12;
601 checkInt(ctx, loc, v: hi, n: 20, rel);
602 if (isInt<20>(x: hi)) {
603 relocateNoSym(loc, type: R_RISCV_PCREL_HI20, val);
604 relocateNoSym(loc: loc + 4, type: R_RISCV_PCREL_LO12_I, val);
605 }
606 return;
607 }
608
609 case R_RISCV_GOT_HI20:
610 case R_RISCV_PCREL_HI20:
611 case R_RISCV_TLSDESC_HI20:
612 case R_RISCV_TLS_GD_HI20:
613 case R_RISCV_TLS_GOT_HI20:
614 case R_RISCV_TPREL_HI20:
615 case R_RISCV_HI20: {
616 uint64_t hi = val + 0x800;
617 checkInt(ctx, loc, v: SignExtend64(X: hi, B: bits) >> 12, n: 20, rel);
618 write32le(P: loc, V: (read32le(P: loc) & 0xFFF) | (hi & 0xFFFFF000));
619 return;
620 }
621
622 case R_RISCV_PCREL_LO12_I:
623 case R_RISCV_TLSDESC_LOAD_LO12:
624 case R_RISCV_TLSDESC_ADD_LO12:
625 case R_RISCV_TPREL_LO12_I:
626 case R_RISCV_LO12_I: {
627 uint64_t hi = (val + 0x800) >> 12;
628 uint64_t lo = val - (hi << 12);
629 write32le(P: loc, V: setLO12_I(insn: read32le(P: loc), imm: lo & 0xfff));
630 return;
631 }
632
633 case R_RISCV_PCREL_LO12_S:
634 case R_RISCV_TPREL_LO12_S:
635 case R_RISCV_LO12_S: {
636 uint64_t hi = (val + 0x800) >> 12;
637 uint64_t lo = val - (hi << 12);
638 write32le(P: loc, V: setLO12_S(insn: read32le(P: loc), imm: lo));
639 return;
640 }
641
642 case INTERNAL_R_RISCV_X0REL_I:
643 case INTERNAL_R_RISCV_X0REL_S: {
644 checkInt(ctx, loc, v: val, n: 12, rel);
645 uint32_t insn = (read32le(P: loc) & ~(31 << 15)) | (X_X0 << 15);
646 if (rel.type == INTERNAL_R_RISCV_X0REL_I)
647 insn = setLO12_I(insn, imm: val);
648 else
649 insn = setLO12_S(insn, imm: val);
650 write32le(P: loc, V: insn);
651 return;
652 }
653
654 case INTERNAL_R_RISCV_GPREL_I:
655 case INTERNAL_R_RISCV_GPREL_S: {
656 Defined *gp = ctx.sym.riscvGlobalPointer;
657 int64_t displace = SignExtend64(X: val - gp->getVA(ctx), B: bits);
658 checkInt(ctx, loc, v: displace, n: 12, rel);
659 uint32_t insn = (read32le(P: loc) & ~(31 << 15)) | (X_GP << 15);
660 if (rel.type == INTERNAL_R_RISCV_GPREL_I)
661 insn = setLO12_I(insn, imm: displace);
662 else
663 insn = setLO12_S(insn, imm: displace);
664 write32le(P: loc, V: insn);
665 return;
666 }
667
668 case R_RISCV_ADD8:
669 *loc += val;
670 return;
671 case R_RISCV_ADD16:
672 write16le(P: loc, V: read16le(P: loc) + val);
673 return;
674 case R_RISCV_ADD32:
675 write32le(P: loc, V: read32le(P: loc) + val);
676 return;
677 case R_RISCV_ADD64:
678 write64le(P: loc, V: read64le(P: loc) + val);
679 return;
680 case R_RISCV_SUB6:
681 *loc = (*loc & 0xc0) | (((*loc & 0x3f) - val) & 0x3f);
682 return;
683 case R_RISCV_SUB8:
684 *loc -= val;
685 return;
686 case R_RISCV_SUB16:
687 write16le(P: loc, V: read16le(P: loc) - val);
688 return;
689 case R_RISCV_SUB32:
690 write32le(P: loc, V: read32le(P: loc) - val);
691 return;
692 case R_RISCV_SUB64:
693 write64le(P: loc, V: read64le(P: loc) - val);
694 return;
695 case R_RISCV_SET6:
696 *loc = (*loc & 0xc0) | (val & 0x3f);
697 return;
698 case R_RISCV_SET8:
699 *loc = val;
700 return;
701 case R_RISCV_SET16:
702 write16le(P: loc, V: val);
703 return;
704 case R_RISCV_SET32:
705 write32le(P: loc, V: val);
706 return;
707 case R_RISCV_32_PCREL:
708 case R_RISCV_PLT32:
709 case R_RISCV_GOT32_PCREL:
710 checkInt(ctx, loc, v: val, n: 32, rel);
711 write32le(P: loc, V: val);
712 return;
713
714 case R_RISCV_TLS_DTPREL32:
715 write32le(P: loc, V: val - dtpOffset);
716 break;
717 case R_RISCV_TLS_DTPREL64:
718 write64le(P: loc, V: val - dtpOffset);
719 break;
720
721 case R_RISCV_RELAX:
722 return;
723 case R_RISCV_TLSDESC:
724 // The addend is stored in the second word.
725 if (ctx.arg.is64)
726 write64le(P: loc + 8, V: val);
727 else
728 write32le(P: loc + 4, V: val);
729 break;
730 default:
731 llvm_unreachable("unknown relocation");
732 }
733}
734
735static bool relaxable(ArrayRef<Relocation> relocs, size_t i) {
736 return i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX;
737}
738
739static void tlsdescToIe(Ctx &ctx, uint8_t *loc, const Relocation &rel,
740 uint64_t val) {
741 switch (rel.type) {
742 case R_RISCV_TLSDESC_HI20:
743 case R_RISCV_TLSDESC_LOAD_LO12:
744 write32le(P: loc, V: 0x00000013); // nop
745 break;
746 case R_RISCV_TLSDESC_ADD_LO12:
747 write32le(P: loc, V: utype(op: AUIPC, rd: X_A0, imm: hi20(val))); // auipc a0,<hi20>
748 break;
749 case R_RISCV_TLSDESC_CALL:
750 if (ctx.arg.is64)
751 write32le(P: loc, V: itype(op: LD, rd: X_A0, rs1: X_A0, imm: lo12(val))); // ld a0,<lo12>(a0)
752 else
753 write32le(P: loc, V: itype(op: LW, rd: X_A0, rs1: X_A0, imm: lo12(val))); // lw a0,<lo12>(a0)
754 break;
755 default:
756 llvm_unreachable("unsupported relocation for TLSDESC to IE");
757 }
758}
759
760static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
761 switch (rel.type) {
762 case R_RISCV_TLSDESC_HI20:
763 case R_RISCV_TLSDESC_LOAD_LO12:
764 write32le(P: loc, V: 0x00000013); // nop
765 return;
766 case R_RISCV_TLSDESC_ADD_LO12:
767 if (isInt<12>(x: val))
768 write32le(P: loc, V: 0x00000013); // nop
769 else
770 write32le(P: loc, V: utype(op: LUI, rd: X_A0, imm: hi20(val))); // lui a0,<hi20>
771 return;
772 case R_RISCV_TLSDESC_CALL:
773 if (isInt<12>(x: val))
774 write32le(P: loc, V: itype(op: ADDI, rd: X_A0, rs1: 0, imm: val)); // addi a0,zero,<lo12>
775 else
776 write32le(P: loc, V: itype(op: ADDI, rd: X_A0, rs1: X_A0, imm: lo12(val))); // addi a0,a0,<lo12>
777 return;
778 default:
779 llvm_unreachable("unsupported relocation for TLSDESC to LE");
780 }
781}
782
783void RISCV::relocateAlloc(InputSection &sec, uint8_t *buf) const {
784 uint64_t secAddr = sec.getOutputSection()->addr + sec.outSecOff;
785 uint64_t tlsdescVal = 0;
786 bool tlsdescRelax = false, isToLe = false;
787 const ArrayRef<Relocation> relocs = sec.relocs();
788 for (size_t i = 0, size = relocs.size(); i != size; ++i) {
789 const Relocation &rel = relocs[i];
790 uint8_t *loc = buf + rel.offset;
791 uint64_t val = sec.getRelocTargetVA(ctx, r: rel, p: secAddr + rel.offset);
792
793 switch (rel.type) {
794 case R_RISCV_ALIGN:
795 case R_RISCV_RELAX:
796 case R_RISCV_TPREL_ADD:
797 continue;
798 case R_RISCV_TLSDESC_HI20:
799 if (rel.expr == R_TLSDESC_PC) {
800 // Shared object: store &got(sym)-PC for the following L[DW]/ADDI.
801 tlsdescVal = val;
802 break;
803 }
804 // Executable: TLSDESC->LE (R_TPREL) or TLSDESC->IE (R_GOT_PC).
805 isToLe = rel.expr == R_TPREL;
806 if (isToLe) {
807 tlsdescVal = val;
808 } else {
809 // tlsdescVal will be finalized after we see R_RISCV_TLSDESC_ADD_LO12.
810 // The net effect is that tlsdescVal will be smaller than `val` to
811 // take into account of NOP instructions (in the absence of
812 // R_RISCV_RELAX) before AUIPC.
813 tlsdescVal = val + rel.offset;
814 }
815 tlsdescRelax = relaxable(relocs, i);
816 if (!tlsdescRelax) {
817 if (isToLe)
818 tlsdescToLe(loc, rel, val);
819 else
820 tlsdescToIe(ctx, loc, rel, val);
821 }
822 continue;
823 case R_RISCV_TLSDESC_LOAD_LO12:
824 case R_RISCV_TLSDESC_ADD_LO12:
825 case R_RISCV_TLSDESC_CALL:
826 if (rel.expr == R_TLSDESC_PC) {
827 // Shared object: propagate the stored GOT value.
828 val = tlsdescVal;
829 break;
830 }
831 // Executable: IE or LE instruction rewrite.
832 if (!isToLe && rel.type == R_RISCV_TLSDESC_ADD_LO12)
833 tlsdescVal -= rel.offset;
834 val = tlsdescVal;
835 // When NOP conversion is eligible and relaxation applies, don't write a
836 // NOP in case an unrelated instruction follows the current instruction.
837 if (tlsdescRelax &&
838 (rel.type == R_RISCV_TLSDESC_LOAD_LO12 ||
839 (rel.type == R_RISCV_TLSDESC_ADD_LO12 && isToLe && !hi20(val))))
840 continue;
841 if (isToLe)
842 tlsdescToLe(loc, rel, val);
843 else
844 tlsdescToIe(ctx, loc, rel, val);
845 continue;
846 case R_RISCV_SET_ULEB128:
847 if (i + 1 < size) {
848 const Relocation &rel1 = relocs[i + 1];
849 if (rel1.type == R_RISCV_SUB_ULEB128 && rel.offset == rel1.offset) {
850 auto val = rel.sym->getVA(ctx, addend: rel.addend) -
851 rel1.sym->getVA(ctx, addend: rel1.addend);
852 if (overwriteULEB128(bufLoc: loc, val) >= 0x80)
853 Err(ctx) << sec.getLocation(offset: rel.offset) << ": ULEB128 value " << val
854 << " exceeds available space; references '" << rel.sym
855 << "'";
856 ++i;
857 continue;
858 }
859 }
860 Err(ctx) << sec.getLocation(offset: rel.offset)
861 << ": R_RISCV_SET_ULEB128 not paired with R_RISCV_SUB_ULEB128";
862 return;
863 default:
864 break;
865 }
866 relocate(loc, rel, val);
867 }
868}
869
870void elf::initSymbolAnchors(Ctx &ctx) {
871 SmallVector<InputSection *, 0> storage;
872 for (OutputSection *osec : ctx.outputSections) {
873 if (!(osec->flags & SHF_EXECINSTR))
874 continue;
875 for (InputSection *sec : getInputSections(os: *osec, storage)) {
876 if (isa<SyntheticSection>(Val: sec))
877 continue;
878 sec->relaxAux = make<RelaxAux>();
879 if (sec->relocs().size()) {
880 sec->relaxAux->relocDeltas =
881 std::make_unique<uint32_t[]>(num: sec->relocs().size());
882 sec->relaxAux->relocTypes =
883 std::make_unique<RelType[]>(num: sec->relocs().size());
884 }
885 }
886 }
887 // Store symbol anchors for adjusting st_value/st_size during relaxation.
888 // We include symbols where d->file == file for the prevailing copies.
889 //
890 // For a defined symbol foo, we may have `d->file != file` with --wrap=foo.
891 // We should process foo, as the defining object file's symbol table may not
892 // contain foo after redirectSymbols changed the foo entry to __wrap_foo. Use
893 // `d->scriptDefined` to include such symbols.
894 //
895 // `relaxAux->anchors` may contain duplicate symbols, but that is fine.
896 auto addAnchor = [](Defined *d) {
897 if (auto *sec = dyn_cast_or_null<InputSection>(Val: d->section))
898 if (sec->flags & SHF_EXECINSTR && sec->relaxAux) {
899 // If sec is discarded, relaxAux will be nullptr.
900 sec->relaxAux->anchors.push_back(Elt: {.offset: d->value, .d: d, .end: false});
901 sec->relaxAux->anchors.push_back(Elt: {.offset: d->value + d->size, .d: d, .end: true});
902 }
903 };
904 for (InputFile *file : ctx.objectFiles)
905 for (Symbol *sym : file->getSymbols()) {
906 auto *d = dyn_cast<Defined>(Val: sym);
907 if (d && (d->file == file || d->scriptDefined))
908 addAnchor(d);
909 }
910 // Add anchors for IRELATIVE symbols (see `handleNonPreemptibleIfunc`).
911 // Their values must be adjusted so IRELATIVE addends remain correct.
912 for (Defined *d : ctx.irelativeSyms)
913 addAnchor(d);
914 // Sort anchors by offset so that we can find the closest relocation
915 // efficiently. For a zero size symbol, ensure that its start anchor precedes
916 // its end anchor. For two symbols with anchors at the same offset, their
917 // order does not matter.
918 for (OutputSection *osec : ctx.outputSections) {
919 if (!(osec->flags & SHF_EXECINSTR))
920 continue;
921 for (InputSection *sec : getInputSections(os: *osec, storage)) {
922 if (!sec->relaxAux)
923 continue;
924 llvm::sort(C&: sec->relaxAux->anchors, Comp: [](auto &a, auto &b) {
925 return std::make_pair(a.offset, a.end) <
926 std::make_pair(b.offset, b.end);
927 });
928 }
929 }
930}
931
932// Relax R_RISCV_CALL/R_RISCV_CALL_PLT auipc+jalr to c.j, c.jal, or jal.
933static void relaxCall(Ctx &ctx, const InputSection &sec, size_t i, uint64_t loc,
934 Relocation &r, uint32_t &remove) {
935 const bool rvc = getEFlags(ctx, f: sec.file) & EF_RISCV_RVC;
936 const Symbol &sym = *r.sym;
937 const uint64_t insnPair = read64le(P: sec.content().data() + r.offset);
938 const uint32_t rd = extractBits(v: insnPair, begin: 32 + 11, end: 32 + 7);
939 const uint64_t dest =
940 (r.expr == R_PLT_PC ? sym.getPltVA(ctx) : sym.getVA(ctx)) + r.addend;
941 const int64_t displace = dest - loc;
942
943 // When the caller specifies the old value of `remove`, disallow its
944 // increment.
945 if (remove >= 6 && rvc && isInt<12>(x: displace) && rd == X_X0) {
946 sec.relaxAux->relocTypes[i] = R_RISCV_RVC_JUMP;
947 sec.relaxAux->writes.push_back(Elt: 0xa001); // c.j
948 remove = 6;
949 } else if (remove >= 6 && rvc && isInt<12>(x: displace) && rd == X_RA &&
950 !ctx.arg.is64) { // RV32C only
951 sec.relaxAux->relocTypes[i] = R_RISCV_RVC_JUMP;
952 sec.relaxAux->writes.push_back(Elt: 0x2001); // c.jal
953 remove = 6;
954 } else if (remove >= 4 && isInt<21>(x: displace)) {
955 sec.relaxAux->relocTypes[i] = R_RISCV_JAL;
956 sec.relaxAux->writes.push_back(Elt: 0x6f | rd << 7); // jal
957 remove = 4;
958 } else {
959 remove = 0;
960 }
961}
962
963// Relax local-exec TLS when hi20 is zero.
964static void relaxTlsLe(Ctx &ctx, const InputSection &sec, size_t i,
965 uint64_t loc, Relocation &r, uint32_t &remove) {
966 uint64_t val = r.sym->getVA(ctx, addend: r.addend);
967 if (hi20(val) != 0)
968 return;
969 uint32_t insn = read32le(P: sec.content().data() + r.offset);
970 switch (r.type) {
971 case R_RISCV_TPREL_HI20:
972 case R_RISCV_TPREL_ADD:
973 // Remove lui rd, %tprel_hi(x) and add rd, rd, tp, %tprel_add(x).
974 sec.relaxAux->relocTypes[i] = R_RISCV_RELAX;
975 remove = 4;
976 break;
977 case R_RISCV_TPREL_LO12_I:
978 // addi rd, rd, %tprel_lo(x) => addi rd, tp, st_value(x)
979 sec.relaxAux->relocTypes[i] = R_RISCV_32;
980 insn = (insn & ~(31 << 15)) | (X_TP << 15);
981 sec.relaxAux->writes.push_back(Elt: setLO12_I(insn, imm: val));
982 break;
983 case R_RISCV_TPREL_LO12_S:
984 // sw rs, %tprel_lo(x)(rd) => sw rs, st_value(x)(rd)
985 sec.relaxAux->relocTypes[i] = R_RISCV_32;
986 insn = (insn & ~(31 << 15)) | (X_TP << 15);
987 sec.relaxAux->writes.push_back(Elt: setLO12_S(insn, imm: val));
988 break;
989 }
990}
991
992static void relaxHi20Lo12(Ctx &ctx, const InputSection &sec, size_t i,
993 uint64_t loc, Relocation &r, uint32_t &remove) {
994
995 // Fold into use of x0+offset
996 if (isInt<12>(x: r.sym->getVA(ctx, addend: r.addend))) {
997 switch (r.type) {
998 case R_RISCV_HI20:
999 // Remove lui rd, %hi20(x).
1000 sec.relaxAux->relocTypes[i] = R_RISCV_RELAX;
1001 remove = 4;
1002 break;
1003 case R_RISCV_LO12_I:
1004 sec.relaxAux->relocTypes[i] = INTERNAL_R_RISCV_X0REL_I;
1005 break;
1006 case R_RISCV_LO12_S:
1007 sec.relaxAux->relocTypes[i] = INTERNAL_R_RISCV_X0REL_S;
1008 break;
1009 }
1010 return;
1011 }
1012
1013 const Defined *gp = ctx.sym.riscvGlobalPointer;
1014 if (!gp)
1015 return;
1016
1017 if (!isInt<12>(x: r.sym->getVA(ctx, addend: r.addend) - gp->getVA(ctx)))
1018 return;
1019
1020 switch (r.type) {
1021 case R_RISCV_HI20:
1022 // Remove lui rd, %hi20(x).
1023 sec.relaxAux->relocTypes[i] = R_RISCV_RELAX;
1024 remove = 4;
1025 break;
1026 case R_RISCV_LO12_I:
1027 sec.relaxAux->relocTypes[i] = INTERNAL_R_RISCV_GPREL_I;
1028 break;
1029 case R_RISCV_LO12_S:
1030 sec.relaxAux->relocTypes[i] = INTERNAL_R_RISCV_GPREL_S;
1031 break;
1032 }
1033}
1034
1035static bool relax(Ctx &ctx, int pass, InputSection &sec) {
1036 const uint64_t secAddr = sec.getVA();
1037 const MutableArrayRef<Relocation> relocs = sec.relocs();
1038 auto &aux = *sec.relaxAux;
1039 bool changed = false;
1040 ArrayRef<SymbolAnchor> sa = ArrayRef(aux.anchors);
1041 uint64_t delta = 0;
1042 bool tlsdescRelax = false, toLeShortForm = false;
1043
1044 std::fill_n(first: aux.relocTypes.get(), n: relocs.size(), value: R_RISCV_NONE);
1045 aux.writes.clear();
1046 for (auto [i, r] : llvm::enumerate(First: relocs)) {
1047 const uint64_t loc = secAddr + r.offset - delta;
1048 uint32_t &cur = aux.relocDeltas[i], remove = 0;
1049 switch (r.type) {
1050 case R_RISCV_ALIGN: {
1051 const uint64_t nextLoc = loc + r.addend;
1052 const uint64_t align = PowerOf2Ceil(A: r.addend + 2);
1053 // All bytes beyond the alignment boundary should be removed.
1054 remove = nextLoc - ((loc + align - 1) & -align);
1055 // If we can't satisfy this alignment, we've found a bad input.
1056 if (LLVM_UNLIKELY(static_cast<int32_t>(remove) < 0)) {
1057 Err(ctx) << getErrorLoc(ctx, loc: (const uint8_t *)loc)
1058 << "insufficient padding bytes for " << r.type << ": "
1059 << r.addend
1060 << " bytes available "
1061 "for requested alignment of "
1062 << align << " bytes";
1063 remove = 0;
1064 }
1065 break;
1066 }
1067 case R_RISCV_CALL:
1068 case R_RISCV_CALL_PLT:
1069 // Prevent oscillation between states by disallowing the increment of
1070 // `remove` after a few passes. The previous `remove` value is
1071 // `cur-delta`.
1072 if (relaxable(relocs, i)) {
1073 remove = pass < 4 ? 6 : cur - delta;
1074 relaxCall(ctx, sec, i, loc, r, remove);
1075 }
1076 break;
1077 case R_RISCV_TPREL_HI20:
1078 case R_RISCV_TPREL_ADD:
1079 case R_RISCV_TPREL_LO12_I:
1080 case R_RISCV_TPREL_LO12_S:
1081 if (relaxable(relocs, i))
1082 relaxTlsLe(ctx, sec, i, loc, r, remove);
1083 break;
1084 case R_RISCV_HI20:
1085 case R_RISCV_LO12_I:
1086 case R_RISCV_LO12_S:
1087 if (relaxable(relocs, i))
1088 relaxHi20Lo12(ctx, sec, i, loc, r, remove);
1089 break;
1090 case R_RISCV_TLSDESC_HI20:
1091 // For TLSDESC=>LE, we can use the short form if hi20 is zero.
1092 tlsdescRelax = relaxable(relocs, i);
1093 toLeShortForm = tlsdescRelax && r.expr == R_TPREL &&
1094 !hi20(val: r.sym->getVA(ctx, addend: r.addend));
1095 [[fallthrough]];
1096 case R_RISCV_TLSDESC_LOAD_LO12:
1097 // For TLSDESC=>LE/IE, AUIPC and L[DW] are removed if relaxable.
1098 if (tlsdescRelax && r.expr != R_TLSDESC_PC)
1099 remove = 4;
1100 break;
1101 case R_RISCV_TLSDESC_ADD_LO12:
1102 if (toLeShortForm)
1103 remove = 4;
1104 break;
1105 }
1106
1107 // For all anchors whose offsets are <= r.offset, they are preceded by
1108 // the previous relocation whose `relocDeltas` value equals `delta`.
1109 // Decrease their st_value and update their st_size.
1110 for (; sa.size() && sa[0].offset <= r.offset; sa = sa.slice(N: 1)) {
1111 if (sa[0].end)
1112 sa[0].d->size = sa[0].offset - delta - sa[0].d->value;
1113 else
1114 sa[0].d->value = sa[0].offset - delta;
1115 }
1116 delta += remove;
1117 if (delta != cur) {
1118 cur = delta;
1119 changed = true;
1120 }
1121 }
1122
1123 for (const SymbolAnchor &a : sa) {
1124 if (a.end)
1125 a.d->size = a.offset - delta - a.d->value;
1126 else
1127 a.d->value = a.offset - delta;
1128 }
1129 // Inform assignAddresses that the size has changed.
1130 if (!isUInt<32>(x: delta))
1131 Err(ctx) << "section size decrease is too large: " << delta;
1132 sec.bytesDropped = delta;
1133 return changed;
1134}
1135
1136// When relaxing just R_RISCV_ALIGN, relocDeltas is usually changed only once in
1137// the absence of a linker script. For call and load/store R_RISCV_RELAX, code
1138// shrinkage may reduce displacement and make more relocations eligible for
1139// relaxation. Code shrinkage may increase displacement to a call/load/store
1140// target at a higher fixed address, invalidating an earlier relaxation. Any
1141// change in section sizes can have cascading effect and require another
1142// relaxation pass.
1143bool RISCV::relaxOnce(int pass) const {
1144 llvm::TimeTraceScope timeScope("RISC-V relaxOnce");
1145 if (pass == 0)
1146 initSymbolAnchors(ctx);
1147
1148 SmallVector<InputSection *, 0> storage;
1149 bool changed = false;
1150 for (OutputSection *osec : ctx.outputSections) {
1151 if (!(osec->flags & SHF_EXECINSTR))
1152 continue;
1153 for (InputSection *sec : getInputSections(os: *osec, storage))
1154 if (sec->relaxAux)
1155 changed |= relax(ctx, pass, sec&: *sec);
1156 }
1157 return changed;
1158}
1159
1160// If the section alignment is >= 4, advance `dot` to insert NOPs and synthesize
1161// an ALIGN relocation. Otherwise, return false to use default handling.
1162template <class ELFT, class RelTy>
1163bool RISCV::synthesizeAlignForInput(uint64_t &dot, InputSection *sec,
1164 Relocs<RelTy> rels) {
1165 if (!baseSec) {
1166 // Record the first input section with RELAX relocations. We will synthesize
1167 // ALIGN relocations here.
1168 for (auto rel : rels) {
1169 if (rel.getType(false) == R_RISCV_RELAX) {
1170 baseSec = sec;
1171 break;
1172 }
1173 }
1174 } else if (sec->addralign >= 4) {
1175 // If the alignment is > 4, synthesize an ALIGN unless an ALIGN relocation
1176 // at offset 0 already guarantees `addralign`. Note: A weaker ALIGN at
1177 // offset 0 from older assemblers do not suppress synthesis (e.g.
1178 // `.p2align 2; .option norelax; nop; .p2align 3` does not suppress
1179 // synthesized `.p2align 3`).
1180 bool covered = llvm::any_of(rels, [&](const RelTy &rel) {
1181 if (rel.r_offset != 0 || rel.getType(false) != R_RISCV_ALIGN)
1182 return false;
1183 if constexpr (RelTy::HasAddend)
1184 return uint64_t(rel.r_addend) >= sec->addralign - 2;
1185 return false;
1186 });
1187 if (!covered) {
1188 synthesizedAligns.emplace_back(Args: dot - baseSec->getVA(),
1189 Args: sec->addralign - 2);
1190 dot += sec->addralign - 2;
1191 return true;
1192 }
1193 }
1194 return false;
1195}
1196
1197// Finalize the relocation section by appending synthesized ALIGN relocations
1198// after processing all input sections.
1199template <class ELFT, class RelTy>
1200void RISCV::finalizeSynthesizeAligns(uint64_t &dot, InputSection *sec,
1201 Relocs<RelTy> rels) {
1202 auto *f = cast<ObjFile<ELFT>>(baseSec->file);
1203 auto shdr = f->template getELFShdrs<ELFT>()[baseSec->relSecIdx];
1204 // Create a copy of InputSection.
1205 sec = make<InputSection>(*f, shdr, baseSec->name);
1206 auto *baseRelSec = cast<InputSection>(f->getSections()[baseSec->relSecIdx]);
1207 *sec = *baseRelSec;
1208 baseSec = nullptr;
1209
1210 // Allocate buffer for original and synthesized relocations in RELA format.
1211 // If CREL is used, OutputSection::finalizeNonAllocCrel will convert RELA to
1212 // CREL.
1213 auto newSize = rels.size() + synthesizedAligns.size();
1214 auto *relas = makeThreadLocalN<typename ELFT::Rela>(newSize);
1215 sec->size = newSize * sizeof(typename ELFT::Rela);
1216 sec->content_ = reinterpret_cast<uint8_t *>(relas);
1217 sec->type = SHT_RELA;
1218 // Copy original relocations to the new buffer, potentially converting CREL to
1219 // RELA.
1220 for (auto [i, r] : llvm::enumerate(rels)) {
1221 relas[i].r_offset = r.r_offset;
1222 relas[i].setSymbolAndType(r.getSymbol(0), r.getType(0), false);
1223 if constexpr (RelTy::HasAddend)
1224 relas[i].r_addend = r.r_addend;
1225 }
1226 // Append synthesized ALIGN relocations to the buffer.
1227 for (auto [i, r] : llvm::enumerate(First&: synthesizedAligns)) {
1228 auto &rela = relas[rels.size() + i];
1229 rela.r_offset = r.first;
1230 rela.setSymbolAndType(0, R_RISCV_ALIGN, false);
1231 rela.r_addend = r.second;
1232 }
1233 synthesizedAligns.clear();
1234 // Replace the old relocation section with the new one in the output section.
1235 // addOrphanSections ensures that the output relocation section is processed
1236 // after osec.
1237 for (SectionCommand *cmd : sec->getParent()->commands) {
1238 auto *isd = dyn_cast<InputSectionDescription>(Val: cmd);
1239 if (!isd)
1240 continue;
1241 for (auto *&isec : isd->sections)
1242 if (isec == baseRelSec)
1243 isec = sec;
1244 }
1245}
1246
1247template <class ELFT>
1248bool RISCV::synthesizeAlignAux(uint64_t &dot, InputSection *sec) {
1249 bool ret = false;
1250 if (sec) {
1251 invokeOnRelocs(*sec, ret = synthesizeAlignForInput<ELFT>, dot, sec);
1252 } else if (baseSec) {
1253 invokeOnRelocs(*baseSec, finalizeSynthesizeAligns<ELFT>, dot, sec);
1254 }
1255 return ret;
1256}
1257
1258// Without linker relaxation enabled for a particular relocatable file or
1259// section, the assembler will not generate R_RISCV_ALIGN relocations for
1260// alignment directives. This becomes problematic in a two-stage linking
1261// process: ld -r a.o b.o -o ab.o; ld ab.o -o ab. This function synthesizes an
1262// R_RISCV_ALIGN relocation at section start when needed.
1263//
1264// When called with an input section (`sec` is not null): If the section
1265// alignment is >= 4, advance `dot` to insert NOPs and synthesize an ALIGN
1266// relocation.
1267//
1268// When called after all input sections are processed (`sec` is null): The
1269// output relocation section is updated with all the newly synthesized ALIGN
1270// relocations.
1271bool RISCV::synthesizeAlign(uint64_t &dot, InputSection *sec) {
1272 assert(ctx.arg.relocatable);
1273 if (ctx.arg.is64)
1274 return synthesizeAlignAux<ELF64LE>(dot, sec);
1275 return synthesizeAlignAux<ELF32LE>(dot, sec);
1276}
1277
1278void RISCV::finalizeRelax(int passes) const {
1279 llvm::TimeTraceScope timeScope("Finalize RISC-V relaxation");
1280 Log(ctx) << "relaxation passes: " << passes;
1281 SmallVector<InputSection *, 0> storage;
1282 for (OutputSection *osec : ctx.outputSections) {
1283 if (!(osec->flags & SHF_EXECINSTR))
1284 continue;
1285 for (InputSection *sec : getInputSections(os: *osec, storage)) {
1286 if (!sec->relaxAux)
1287 continue;
1288 RelaxAux &aux = *sec->relaxAux;
1289 if (!aux.relocDeltas)
1290 continue;
1291
1292 MutableArrayRef<Relocation> rels = sec->relocs();
1293 ArrayRef<uint8_t> old = sec->content();
1294 size_t newSize = old.size() - aux.relocDeltas[rels.size() - 1];
1295 size_t writesIdx = 0;
1296 uint8_t *p = ctx.bAlloc.Allocate<uint8_t>(Num: newSize);
1297 uint64_t offset = 0;
1298 int64_t delta = 0;
1299 sec->content_ = p;
1300 sec->size = newSize;
1301 sec->bytesDropped = 0;
1302
1303 // Update section content: remove NOPs for R_RISCV_ALIGN and rewrite
1304 // instructions for relaxed relocations.
1305 for (size_t i = 0, e = rels.size(); i != e; ++i) {
1306 uint32_t remove = aux.relocDeltas[i] - delta;
1307 delta = aux.relocDeltas[i];
1308 if (remove == 0 && aux.relocTypes[i] == R_RISCV_NONE)
1309 continue;
1310
1311 // Copy from last location to the current relocated location.
1312 const Relocation &r = rels[i];
1313 uint64_t size = r.offset - offset;
1314 memcpy(dest: p, src: old.data() + offset, n: size);
1315 p += size;
1316
1317 // For R_RISCV_ALIGN, we will place `offset` in a location (among NOPs)
1318 // to satisfy the alignment requirement. If both `remove` and r.addend
1319 // are multiples of 4, it is as if we have skipped some NOPs. Otherwise
1320 // we are in the middle of a 4-byte NOP, and we need to rewrite the NOP
1321 // sequence.
1322 int64_t skip = 0;
1323 if (r.type == R_RISCV_ALIGN) {
1324 if (remove % 4 || r.addend % 4) {
1325 skip = r.addend - remove;
1326 int64_t j = 0;
1327 for (; j + 4 <= skip; j += 4)
1328 write32le(P: p + j, V: 0x00000013); // nop
1329 if (j != skip) {
1330 assert(j + 2 == skip);
1331 write16le(P: p + j, V: 0x0001); // c.nop
1332 }
1333 }
1334 } else if (RelType newType = aux.relocTypes[i]) {
1335 switch (newType) {
1336 case INTERNAL_R_RISCV_GPREL_I:
1337 case INTERNAL_R_RISCV_GPREL_S:
1338 case INTERNAL_R_RISCV_X0REL_I:
1339 case INTERNAL_R_RISCV_X0REL_S:
1340 break;
1341 case R_RISCV_RELAX:
1342 // Used by relaxTlsLe to indicate the relocation is ignored.
1343 break;
1344 case R_RISCV_RVC_JUMP:
1345 skip = 2;
1346 write16le(P: p, V: aux.writes[writesIdx++]);
1347 break;
1348 case R_RISCV_JAL:
1349 skip = 4;
1350 write32le(P: p, V: aux.writes[writesIdx++]);
1351 break;
1352 case R_RISCV_32:
1353 // Used by relaxTlsLe to write a uint32_t then suppress the handling
1354 // in relocateAlloc.
1355 skip = 4;
1356 write32le(P: p, V: aux.writes[writesIdx++]);
1357 aux.relocTypes[i] = R_RISCV_NONE;
1358 break;
1359 default:
1360 llvm_unreachable("unsupported type");
1361 }
1362 }
1363
1364 p += skip;
1365 offset = r.offset + skip + remove;
1366 }
1367 memcpy(dest: p, src: old.data() + offset, n: old.size() - offset);
1368
1369 // Subtract the previous relocDeltas value from the relocation offset.
1370 // For a pair of R_RISCV_CALL/R_RISCV_RELAX with the same offset, decrease
1371 // their r_offset by the same delta.
1372 delta = 0;
1373 for (size_t i = 0, e = rels.size(); i != e;) {
1374 uint64_t cur = rels[i].offset;
1375 do {
1376 rels[i].offset -= delta;
1377 if (aux.relocTypes[i] != R_RISCV_NONE)
1378 rels[i].type = aux.relocTypes[i];
1379 } while (++i != e && rels[i].offset == cur);
1380 delta = aux.relocDeltas[i - 1];
1381 }
1382 }
1383 }
1384}
1385
1386namespace {
1387// Representation of the merged .riscv.attributes input sections. The psABI
1388// specifies merge policy for attributes. E.g. if we link an object without an
1389// extension with an object with the extension, the output Tag_RISCV_arch shall
1390// contain the extension. Some tools like objdump parse .riscv.attributes and
1391// disabling some instructions if the first Tag_RISCV_arch does not contain an
1392// extension.
1393class RISCVAttributesSection final : public SyntheticSection {
1394public:
1395 RISCVAttributesSection(Ctx &ctx)
1396 : SyntheticSection(ctx, ".riscv.attributes", SHT_RISCV_ATTRIBUTES, 0, 1) {
1397 }
1398
1399 size_t getSize() const override { return size; }
1400 void writeTo(uint8_t *buf) override;
1401
1402 static constexpr StringRef vendor = "riscv";
1403 DenseMap<unsigned, unsigned> intAttr;
1404 DenseMap<unsigned, StringRef> strAttr;
1405 size_t size = 0;
1406};
1407} // namespace
1408
1409static void mergeArch(Ctx &ctx, RISCVISAUtils::OrderedExtensionMap &mergedExts,
1410 unsigned &mergedXlen, const InputSectionBase *sec,
1411 StringRef s) {
1412 auto maybeInfo = RISCVISAInfo::parseNormalizedArchString(Arch: s);
1413 if (!maybeInfo) {
1414 Err(ctx) << sec << ": " << s << ": " << maybeInfo.takeError();
1415 return;
1416 }
1417
1418 // Merge extensions.
1419 RISCVISAInfo &info = **maybeInfo;
1420 if (mergedExts.empty()) {
1421 mergedExts = info.getExtensions();
1422 mergedXlen = info.getXLen();
1423 } else {
1424 for (const auto &ext : info.getExtensions()) {
1425 auto p = mergedExts.insert(x: ext);
1426 if (!p.second) {
1427 if (std::tie(args&: p.first->second.Major, args&: p.first->second.Minor) <
1428 std::tie(args: ext.second.Major, args: ext.second.Minor))
1429 p.first->second = ext.second;
1430 }
1431 }
1432 }
1433}
1434
1435static void mergeAtomic(Ctx &ctx, DenseMap<unsigned, unsigned>::iterator it,
1436 const InputSectionBase *oldSection,
1437 const InputSectionBase *newSection,
1438 RISCVAttrs::RISCVAtomicAbiTag oldTag,
1439 RISCVAttrs::RISCVAtomicAbiTag newTag) {
1440 using RISCVAttrs::RISCVAtomicAbiTag;
1441 // Same tags stay the same, and UNKNOWN is compatible with anything
1442 if (oldTag == newTag || newTag == RISCVAtomicAbiTag::UNKNOWN)
1443 return;
1444
1445 auto reportAbiError = [&]() {
1446 Err(ctx) << "atomic abi mismatch for " << oldSection->name << "\n>>> "
1447 << oldSection << ": atomic_abi=" << static_cast<unsigned>(oldTag)
1448 << "\n>>> " << newSection
1449 << ": atomic_abi=" << static_cast<unsigned>(newTag);
1450 };
1451
1452 auto reportUnknownAbiError = [&](const InputSectionBase *section,
1453 RISCVAtomicAbiTag tag) {
1454 switch (tag) {
1455 case RISCVAtomicAbiTag::UNKNOWN:
1456 case RISCVAtomicAbiTag::A6C:
1457 case RISCVAtomicAbiTag::A6S:
1458 case RISCVAtomicAbiTag::A7:
1459 return;
1460 };
1461 Err(ctx) << "unknown atomic abi for " << section->name << "\n>>> "
1462 << section << ": atomic_abi=" << static_cast<unsigned>(tag);
1463 };
1464 switch (oldTag) {
1465 case RISCVAtomicAbiTag::UNKNOWN:
1466 it->getSecond() = static_cast<unsigned>(newTag);
1467 return;
1468 case RISCVAtomicAbiTag::A6C:
1469 switch (newTag) {
1470 case RISCVAtomicAbiTag::A6S:
1471 it->getSecond() = static_cast<unsigned>(RISCVAtomicAbiTag::A6C);
1472 return;
1473 case RISCVAtomicAbiTag::A7:
1474 reportAbiError();
1475 return;
1476 case RISCVAttrs::RISCVAtomicAbiTag::UNKNOWN:
1477 case RISCVAttrs::RISCVAtomicAbiTag::A6C:
1478 return;
1479 };
1480 break;
1481
1482 case RISCVAtomicAbiTag::A6S:
1483 switch (newTag) {
1484 case RISCVAtomicAbiTag::A6C:
1485 it->getSecond() = static_cast<unsigned>(RISCVAtomicAbiTag::A6C);
1486 return;
1487 case RISCVAtomicAbiTag::A7:
1488 it->getSecond() = static_cast<unsigned>(RISCVAtomicAbiTag::A7);
1489 return;
1490 case RISCVAttrs::RISCVAtomicAbiTag::UNKNOWN:
1491 case RISCVAttrs::RISCVAtomicAbiTag::A6S:
1492 return;
1493 };
1494 break;
1495
1496 case RISCVAtomicAbiTag::A7:
1497 switch (newTag) {
1498 case RISCVAtomicAbiTag::A6S:
1499 it->getSecond() = static_cast<unsigned>(RISCVAtomicAbiTag::A7);
1500 return;
1501 case RISCVAtomicAbiTag::A6C:
1502 reportAbiError();
1503 return;
1504 case RISCVAttrs::RISCVAtomicAbiTag::UNKNOWN:
1505 case RISCVAttrs::RISCVAtomicAbiTag::A7:
1506 return;
1507 };
1508 break;
1509 };
1510
1511 // If we get here, then we have an invalid tag, so report it.
1512 // Putting these checks at the end allows us to only do these checks when we
1513 // need to, since this is expected to be a rare occurrence.
1514 reportUnknownAbiError(oldSection, oldTag);
1515 reportUnknownAbiError(newSection, newTag);
1516}
1517
1518static RISCVAttributesSection *
1519mergeAttributesSection(Ctx &ctx,
1520 const SmallVector<InputSectionBase *, 0> &sections) {
1521 using RISCVAttrs::RISCVAtomicAbiTag;
1522 RISCVISAUtils::OrderedExtensionMap exts;
1523 const InputSectionBase *firstStackAlign = nullptr;
1524 const InputSectionBase *firstAtomicAbi = nullptr;
1525 unsigned firstStackAlignValue = 0, xlen = 0;
1526 bool hasArch = false;
1527
1528 ctx.in.riscvAttributes = std::make_unique<RISCVAttributesSection>(args&: ctx);
1529 auto &merged = static_cast<RISCVAttributesSection &>(*ctx.in.riscvAttributes);
1530
1531 // Collect all tags values from attributes section.
1532 const auto &attributesTags = RISCVAttrs::getRISCVAttributeTags();
1533 for (const InputSectionBase *sec : sections) {
1534 RISCVAttributeParser parser;
1535 if (Error e = parser.parse(section: sec->content(), endian: llvm::endianness::little))
1536 Warn(ctx) << sec << ": " << std::move(e);
1537 for (const auto &tag : attributesTags) {
1538 switch (RISCVAttrs::AttrType(tag.attr)) {
1539 // Integer attributes.
1540 case RISCVAttrs::STACK_ALIGN:
1541 if (auto i = parser.getAttributeValue(tag: tag.attr)) {
1542 auto r = merged.intAttr.try_emplace(Key: tag.attr, Args&: *i);
1543 if (r.second) {
1544 firstStackAlign = sec;
1545 firstStackAlignValue = *i;
1546 } else if (r.first->second != *i) {
1547 Err(ctx) << sec << " has stack_align=" << *i << " but "
1548 << firstStackAlign
1549 << " has stack_align=" << firstStackAlignValue;
1550 }
1551 }
1552 continue;
1553 case RISCVAttrs::UNALIGNED_ACCESS:
1554 if (auto i = parser.getAttributeValue(tag: tag.attr))
1555 merged.intAttr[tag.attr] |= *i;
1556 continue;
1557
1558 // String attributes.
1559 case RISCVAttrs::ARCH:
1560 if (auto s = parser.getAttributeString(tag: tag.attr)) {
1561 hasArch = true;
1562 mergeArch(ctx, mergedExts&: exts, mergedXlen&: xlen, sec, s: *s);
1563 }
1564 continue;
1565
1566 // Attributes which use the default handling.
1567 case RISCVAttrs::PRIV_SPEC:
1568 case RISCVAttrs::PRIV_SPEC_MINOR:
1569 case RISCVAttrs::PRIV_SPEC_REVISION:
1570 break;
1571
1572 case RISCVAttrs::AttrType::ATOMIC_ABI:
1573 if (auto i = parser.getAttributeValue(tag: tag.attr)) {
1574 auto r = merged.intAttr.try_emplace(Key: tag.attr, Args&: *i);
1575 if (r.second)
1576 firstAtomicAbi = sec;
1577 else
1578 mergeAtomic(ctx, it: r.first, oldSection: firstAtomicAbi, newSection: sec,
1579 oldTag: static_cast<RISCVAtomicAbiTag>(r.first->getSecond()),
1580 newTag: static_cast<RISCVAtomicAbiTag>(*i));
1581 }
1582 continue;
1583 }
1584
1585 // Fallback for deprecated priv_spec* and other unknown attributes: retain
1586 // the attribute if all input sections agree on the value. GNU ld uses 0
1587 // and empty strings as default values which are not dumped to the output.
1588 // TODO Adjust after resolution to
1589 // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/352
1590 if (tag.attr % 2 == 0) {
1591 if (auto i = parser.getAttributeValue(tag: tag.attr)) {
1592 auto r = merged.intAttr.try_emplace(Key: tag.attr, Args&: *i);
1593 if (!r.second && r.first->second != *i)
1594 r.first->second = 0;
1595 }
1596 } else if (auto s = parser.getAttributeString(tag: tag.attr)) {
1597 auto r = merged.strAttr.try_emplace(Key: tag.attr, Args&: *s);
1598 if (!r.second && r.first->second != *s)
1599 r.first->second = {};
1600 }
1601 }
1602 }
1603
1604 if (hasArch && xlen != 0) {
1605 if (auto result = RISCVISAInfo::createFromExtMap(XLen: xlen, Exts: exts)) {
1606 merged.strAttr.try_emplace(Key: RISCVAttrs::ARCH,
1607 Args: ctx.saver.save(S: (*result)->toString()));
1608 } else {
1609 Err(ctx) << result.takeError();
1610 }
1611 }
1612
1613 // The total size of headers: format-version [ <section-length> "vendor-name"
1614 // [ <file-tag> <size>.
1615 size_t size = 5 + merged.vendor.size() + 1 + 5;
1616 for (auto &attr : merged.intAttr)
1617 if (attr.second != 0)
1618 size += getULEB128Size(Value: attr.first) + getULEB128Size(Value: attr.second);
1619 for (auto &attr : merged.strAttr)
1620 if (!attr.second.empty())
1621 size += getULEB128Size(Value: attr.first) + attr.second.size() + 1;
1622 merged.size = size;
1623 return &merged;
1624}
1625
1626void RISCVAttributesSection::writeTo(uint8_t *buf) {
1627 const size_t size = getSize();
1628 uint8_t *const end = buf + size;
1629 *buf = ELFAttrs::Format_Version;
1630 write32(ctx, p: buf + 1, v: size - 1);
1631 buf += 5;
1632
1633 memcpy(dest: buf, src: vendor.data(), n: vendor.size());
1634 buf += vendor.size() + 1;
1635
1636 *buf = ELFAttrs::File;
1637 write32(ctx, p: buf + 1, v: end - buf);
1638 buf += 5;
1639
1640 for (auto &attr : intAttr) {
1641 if (attr.second == 0)
1642 continue;
1643 buf += encodeULEB128(Value: attr.first, p: buf);
1644 buf += encodeULEB128(Value: attr.second, p: buf);
1645 }
1646 for (auto &attr : strAttr) {
1647 if (attr.second.empty())
1648 continue;
1649 buf += encodeULEB128(Value: attr.first, p: buf);
1650 memcpy(dest: buf, src: attr.second.data(), n: attr.second.size());
1651 buf += attr.second.size() + 1;
1652 }
1653}
1654
1655void elf::mergeRISCVAttributesSections(Ctx &ctx) {
1656 // Find the first input SHT_RISCV_ATTRIBUTES; return if not found.
1657 size_t place =
1658 llvm::find_if(Range&: ctx.inputSections,
1659 P: [](auto *s) { return s->type == SHT_RISCV_ATTRIBUTES; }) -
1660 ctx.inputSections.begin();
1661 if (place == ctx.inputSections.size())
1662 return;
1663
1664 // Extract all SHT_RISCV_ATTRIBUTES sections into `sections`.
1665 SmallVector<InputSectionBase *, 0> sections;
1666 llvm::erase_if(C&: ctx.inputSections, P: [&](InputSectionBase *s) {
1667 if (s->type != SHT_RISCV_ATTRIBUTES)
1668 return false;
1669 sections.push_back(Elt: s);
1670 return true;
1671 });
1672
1673 // Add the merged section.
1674 ctx.inputSections.insert(I: ctx.inputSections.begin() + place,
1675 Elt: mergeAttributesSection(ctx, sections));
1676}
1677
1678void elf::setRISCVTargetInfo(Ctx &ctx) { ctx.target.reset(p: new RISCV(ctx)); }
1679