1//===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the IRTranslator class.
10//===----------------------------------------------------------------------===//
11
12#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
13#include "llvm/ADT/PostOrderIterator.h"
14#include "llvm/ADT/STLExtras.h"
15#include "llvm/ADT/ScopeExit.h"
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/Analysis/AliasAnalysis.h"
18#include "llvm/Analysis/AssumptionCache.h"
19#include "llvm/Analysis/BranchProbabilityInfo.h"
20#include "llvm/Analysis/Loads.h"
21#include "llvm/Analysis/OptimizationRemarkEmitter.h"
22#include "llvm/Analysis/ValueTracking.h"
23#include "llvm/Analysis/VectorUtils.h"
24#include "llvm/CodeGen/Analysis.h"
25#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
26#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
27#include "llvm/CodeGen/GlobalISel/CallLowering.h"
28#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
29#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
30#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
31#include "llvm/CodeGen/LowLevelTypeUtils.h"
32#include "llvm/CodeGen/MachineBasicBlock.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineFunction.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/MachineMemOperand.h"
37#include "llvm/CodeGen/MachineModuleInfo.h"
38#include "llvm/CodeGen/MachineOperand.h"
39#include "llvm/CodeGen/MachineRegisterInfo.h"
40#include "llvm/CodeGen/StackProtector.h"
41#include "llvm/CodeGen/SwitchLoweringUtils.h"
42#include "llvm/CodeGen/TargetFrameLowering.h"
43#include "llvm/CodeGen/TargetInstrInfo.h"
44#include "llvm/CodeGen/TargetLowering.h"
45#include "llvm/CodeGen/TargetOpcodes.h"
46#include "llvm/CodeGen/TargetPassConfig.h"
47#include "llvm/CodeGen/TargetRegisterInfo.h"
48#include "llvm/CodeGen/TargetSubtargetInfo.h"
49#include "llvm/CodeGenTypes/LowLevelType.h"
50#include "llvm/IR/BasicBlock.h"
51#include "llvm/IR/CFG.h"
52#include "llvm/IR/Constant.h"
53#include "llvm/IR/Constants.h"
54#include "llvm/IR/DataLayout.h"
55#include "llvm/IR/DerivedTypes.h"
56#include "llvm/IR/DiagnosticInfo.h"
57#include "llvm/IR/Function.h"
58#include "llvm/IR/GetElementPtrTypeIterator.h"
59#include "llvm/IR/InlineAsm.h"
60#include "llvm/IR/InstrTypes.h"
61#include "llvm/IR/Instructions.h"
62#include "llvm/IR/IntrinsicInst.h"
63#include "llvm/IR/Intrinsics.h"
64#include "llvm/IR/IntrinsicsAMDGPU.h"
65#include "llvm/IR/LLVMContext.h"
66#include "llvm/IR/Metadata.h"
67#include "llvm/IR/PatternMatch.h"
68#include "llvm/IR/Statepoint.h"
69#include "llvm/IR/Type.h"
70#include "llvm/IR/User.h"
71#include "llvm/IR/Value.h"
72#include "llvm/InitializePasses.h"
73#include "llvm/MC/MCContext.h"
74#include "llvm/Pass.h"
75#include "llvm/Support/Casting.h"
76#include "llvm/Support/CodeGen.h"
77#include "llvm/Support/Debug.h"
78#include "llvm/Support/ErrorHandling.h"
79#include "llvm/Support/MathExtras.h"
80#include "llvm/Support/raw_ostream.h"
81#include "llvm/Target/TargetMachine.h"
82#include "llvm/Transforms/Utils/Local.h"
83#include "llvm/Transforms/Utils/MemoryOpRemark.h"
84#include <algorithm>
85#include <cassert>
86#include <cstdint>
87#include <iterator>
88#include <optional>
89#include <string>
90#include <utility>
91#include <vector>
92
93#define DEBUG_TYPE "irtranslator"
94
95using namespace llvm;
96
97static cl::opt<bool>
98 EnableCSEInIRTranslator("enable-cse-in-irtranslator",
99 cl::desc("Should enable CSE in irtranslator"),
100 cl::Optional, cl::init(Val: false));
101char IRTranslator::ID = 0;
102
103INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
104 false, false)
105INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
106INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
107INITIALIZE_PASS_DEPENDENCY(BlockFrequencyInfoWrapperPass)
108INITIALIZE_PASS_DEPENDENCY(StackProtector)
109INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
110INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
111 false, false)
112
113static void reportTranslationError(MachineFunction &MF,
114 OptimizationRemarkEmitter &ORE,
115 OptimizationRemarkMissed &R) {
116 MF.getProperties().setFailedISel();
117 bool IsGlobalISelAbortEnabled =
118 MF.getTarget().Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
119
120 // Print the function name explicitly if we don't have a debug location (which
121 // makes the diagnostic less useful) or if we're going to emit a raw error.
122 if (!R.getLocation().isValid() || IsGlobalISelAbortEnabled)
123 R << (" (in function: " + MF.getName() + ")").str();
124
125 if (IsGlobalISelAbortEnabled)
126 report_fatal_error(reason: Twine(R.getMsg()));
127 else
128 ORE.emit(OptDiag&: R);
129}
130
131IRTranslator::IRTranslator(CodeGenOptLevel optlevel)
132 : MachineFunctionPass(ID), OptLevel(optlevel) {}
133
134#ifndef NDEBUG
135namespace {
136/// Verify that every instruction created has the same DILocation as the
137/// instruction being translated.
138class DILocationVerifier : public GISelChangeObserver {
139 const Instruction *CurrInst = nullptr;
140
141public:
142 DILocationVerifier() = default;
143 ~DILocationVerifier() override = default;
144
145 const Instruction *getCurrentInst() const { return CurrInst; }
146 void setCurrentInst(const Instruction *Inst) { CurrInst = Inst; }
147
148 void erasingInstr(MachineInstr &MI) override {}
149 void changingInstr(MachineInstr &MI) override {}
150 void changedInstr(MachineInstr &MI) override {}
151
152 void createdInstr(MachineInstr &MI) override {
153 assert(getCurrentInst() && "Inserted instruction without a current MI");
154
155 // Only print the check message if we're actually checking it.
156#ifndef NDEBUG
157 LLVM_DEBUG(dbgs() << "Checking DILocation from " << *CurrInst
158 << " was copied to " << MI);
159#endif
160 // We allow insts in the entry block to have no debug loc because
161 // they could have originated from constants, and we don't want a jumpy
162 // debug experience.
163 assert((CurrInst->getDebugLoc() == MI.getDebugLoc() ||
164 (MI.getParent()->isEntryBlock() && !MI.getDebugLoc()) ||
165 (MI.isDebugInstr())) &&
166 "Line info was not transferred to all instructions");
167 }
168};
169} // namespace
170#endif // ifndef NDEBUG
171
172
173void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
174 AU.addRequired<StackProtector>();
175 AU.addRequired<TargetPassConfig>();
176 AU.addRequired<GISelCSEAnalysisWrapperPass>();
177 AU.addRequired<AssumptionCacheTracker>();
178 if (OptLevel != CodeGenOptLevel::None) {
179 AU.addRequired<BranchProbabilityInfoWrapperPass>();
180 AU.addRequired<AAResultsWrapperPass>();
181 }
182 AU.addRequired<TargetLibraryInfoWrapperPass>();
183 AU.addPreserved<TargetLibraryInfoWrapperPass>();
184 AU.addRequired<LibcallLoweringInfoWrapper>();
185
186 getSelectionDAGFallbackAnalysisUsage(AU);
187 MachineFunctionPass::getAnalysisUsage(AU);
188}
189
190IRTranslator::ValueToVRegInfo::VRegListT &
191IRTranslator::allocateVRegs(const Value &Val) {
192 auto VRegsIt = VMap.findVRegs(V: Val);
193 if (VRegsIt != VMap.vregs_end())
194 return *VRegsIt->second;
195 auto *Regs = VMap.getVRegs(V: Val);
196 auto *Offsets = VMap.getOffsets(V: Val);
197 SmallVector<LLT, 4> SplitTys;
198 computeValueLLTs(DL: *DL, Ty&: *Val.getType(), ValueLLTs&: SplitTys,
199 FixedOffsets: Offsets->empty() ? Offsets : nullptr);
200 for (unsigned i = 0; i < SplitTys.size(); ++i)
201 Regs->push_back(Elt: 0);
202 return *Regs;
203}
204
205ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
206 auto VRegsIt = VMap.findVRegs(V: Val);
207 if (VRegsIt != VMap.vregs_end())
208 return *VRegsIt->second;
209
210 if (Val.getType()->isVoidTy())
211 return *VMap.getVRegs(V: Val);
212
213 // Create entry for this type.
214 auto *VRegs = VMap.getVRegs(V: Val);
215 auto *Offsets = VMap.getOffsets(V: Val);
216
217 if (!Val.getType()->isTokenTy())
218 assert(Val.getType()->isSized() &&
219 "Don't know how to create an empty vreg");
220
221 SmallVector<LLT, 4> SplitTys;
222 computeValueLLTs(DL: *DL, Ty&: *Val.getType(), ValueLLTs&: SplitTys,
223 FixedOffsets: Offsets->empty() ? Offsets : nullptr);
224
225 if (!isa<Constant>(Val)) {
226 for (auto Ty : SplitTys)
227 VRegs->push_back(Elt: MRI->createGenericVirtualRegister(Ty));
228 return *VRegs;
229 }
230
231 if (Val.getType()->isAggregateType()) {
232 // UndefValue, ConstantAggregateZero
233 auto &C = cast<Constant>(Val);
234 unsigned Idx = 0;
235 while (auto Elt = C.getAggregateElement(Elt: Idx++)) {
236 auto EltRegs = getOrCreateVRegs(Val: *Elt);
237 llvm::append_range(C&: *VRegs, R&: EltRegs);
238 }
239 } else {
240 assert(SplitTys.size() == 1 && "unexpectedly split LLT");
241 VRegs->push_back(Elt: MRI->createGenericVirtualRegister(Ty: SplitTys[0]));
242 bool Success = translate(C: cast<Constant>(Val), Reg: VRegs->front());
243 if (!Success) {
244 OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
245 MF->getFunction().getSubprogram(),
246 &MF->getFunction().getEntryBlock());
247 R << "unable to translate constant: " << ore::NV("Type", Val.getType());
248 reportTranslationError(MF&: *MF, ORE&: *ORE, R);
249 return *VRegs;
250 }
251 }
252
253 return *VRegs;
254}
255
256int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
257 auto [MapEntry, Inserted] = FrameIndices.try_emplace(Key: &AI);
258 if (!Inserted)
259 return MapEntry->second;
260
261 TypeSize TySize = AI.getAllocationSize(DL: *DL).value_or(u: TypeSize::getZero());
262 uint64_t Size = TySize.getKnownMinValue();
263
264 // Always allocate at least one byte.
265 Size = std::max<uint64_t>(a: Size, b: 1u);
266
267 int &FI = MapEntry->second;
268 FI = MF->getFrameInfo().CreateStackObject(Size, Alignment: AI.getAlign(), isSpillSlot: false, Alloca: &AI);
269
270 // Scalable vectors and structures that contain scalable vectors may
271 // need a special StackID to distinguish them from other (fixed size)
272 // stack objects.
273 if (TySize.isScalable()) {
274 auto StackID =
275 MF->getSubtarget().getFrameLowering()->getStackIDForScalableVectors();
276 MF->getFrameInfo().setStackID(ObjectIdx: FI, ID: StackID);
277 }
278
279 return FI;
280}
281
282Align IRTranslator::getMemOpAlign(const Instruction &I) {
283 if (const StoreInst *SI = dyn_cast<StoreInst>(Val: &I))
284 return SI->getAlign();
285 if (const LoadInst *LI = dyn_cast<LoadInst>(Val: &I))
286 return LI->getAlign();
287 if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(Val: &I))
288 return AI->getAlign();
289 if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(Val: &I))
290 return AI->getAlign();
291
292 OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
293 R << "unable to translate memop: " << ore::NV("Opcode", &I);
294 reportTranslationError(MF&: *MF, ORE&: *ORE, R);
295 return Align(1);
296}
297
298MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
299 MachineBasicBlock *MBB = FuncInfo.getMBB(BB: &BB);
300 assert(MBB && "BasicBlock was not encountered before");
301 return *MBB;
302}
303
304void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
305 assert(NewPred && "new predecessor must be a real MachineBasicBlock");
306 MachinePreds[Edge].push_back(Elt: NewPred);
307}
308
309static bool targetSupportsBF16Type(const MachineFunction *MF) {
310 return MF->getTarget().getTargetTriple().isSPIRV();
311}
312
313static bool containsBF16Type(const User &U) {
314 // BF16 cannot currently be represented by LLT, to avoid miscompiles we
315 // prevent any instructions using them. FIXME: This can be removed once LLT
316 // supports bfloat.
317 return U.getType()->getScalarType()->isBFloatTy() ||
318 any_of(Range: U.operands(), P: [](Value *V) {
319 return V->getType()->getScalarType()->isBFloatTy();
320 });
321}
322
323bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
324 MachineIRBuilder &MIRBuilder) {
325 if (containsBF16Type(U) && !targetSupportsBF16Type(MF))
326 return false;
327
328 // Get or create a virtual register for each value.
329 // Unless the value is a Constant => loadimm cst?
330 // or inline constant each time?
331 // Creation of a virtual register needs to have a size.
332 Register Op0 = getOrCreateVReg(Val: *U.getOperand(i: 0));
333 Register Op1 = getOrCreateVReg(Val: *U.getOperand(i: 1));
334 Register Res = getOrCreateVReg(Val: U);
335 uint32_t Flags = 0;
336 if (isa<Instruction>(Val: U)) {
337 const Instruction &I = cast<Instruction>(Val: U);
338 Flags = MachineInstr::copyFlagsFromInstruction(I);
339 }
340
341 MIRBuilder.buildInstr(Opc: Opcode, DstOps: {Res}, SrcOps: {Op0, Op1}, Flags);
342 return true;
343}
344
345bool IRTranslator::translateUnaryOp(unsigned Opcode, const User &U,
346 MachineIRBuilder &MIRBuilder) {
347 if (containsBF16Type(U) && !targetSupportsBF16Type(MF))
348 return false;
349
350 Register Op0 = getOrCreateVReg(Val: *U.getOperand(i: 0));
351 Register Res = getOrCreateVReg(Val: U);
352 uint32_t Flags = 0;
353 if (isa<Instruction>(Val: U)) {
354 const Instruction &I = cast<Instruction>(Val: U);
355 Flags = MachineInstr::copyFlagsFromInstruction(I);
356 }
357 MIRBuilder.buildInstr(Opc: Opcode, DstOps: {Res}, SrcOps: {Op0}, Flags);
358 return true;
359}
360
361bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
362 return translateUnaryOp(Opcode: TargetOpcode::G_FNEG, U, MIRBuilder);
363}
364
365bool IRTranslator::translateCompare(const User &U,
366 MachineIRBuilder &MIRBuilder) {
367 if (containsBF16Type(U) && !targetSupportsBF16Type(MF))
368 return false;
369
370 auto *CI = cast<CmpInst>(Val: &U);
371 Register Op0 = getOrCreateVReg(Val: *U.getOperand(i: 0));
372 Register Op1 = getOrCreateVReg(Val: *U.getOperand(i: 1));
373 Register Res = getOrCreateVReg(Val: U);
374 CmpInst::Predicate Pred = CI->getPredicate();
375 uint32_t Flags = MachineInstr::copyFlagsFromInstruction(I: *CI);
376 if (CmpInst::isIntPredicate(P: Pred))
377 MIRBuilder.buildICmp(Pred, Res, Op0, Op1, Flags);
378 else if (Pred == CmpInst::FCMP_FALSE)
379 MIRBuilder.buildCopy(
380 Res, Op: getOrCreateVReg(Val: *Constant::getNullValue(Ty: U.getType())));
381 else if (Pred == CmpInst::FCMP_TRUE)
382 MIRBuilder.buildCopy(
383 Res, Op: getOrCreateVReg(Val: *Constant::getAllOnesValue(Ty: U.getType())));
384 else
385 MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, Flags);
386
387 return true;
388}
389
390bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
391 const ReturnInst &RI = cast<ReturnInst>(Val: U);
392 const Value *Ret = RI.getReturnValue();
393 if (Ret && DL->getTypeStoreSize(Ty: Ret->getType()).isZero())
394 Ret = nullptr;
395
396 ArrayRef<Register> VRegs;
397 if (Ret)
398 VRegs = getOrCreateVRegs(Val: *Ret);
399
400 Register SwiftErrorVReg = 0;
401 if (CLI->supportSwiftError() && SwiftError.getFunctionArg()) {
402 SwiftErrorVReg = SwiftError.getOrCreateVRegUseAt(
403 &RI, &MIRBuilder.getMBB(), SwiftError.getFunctionArg());
404 }
405
406 // The target may mess up with the insertion point, but
407 // this is not important as a return is the last instruction
408 // of the block anyway.
409 return CLI->lowerReturn(MIRBuilder, Val: Ret, VRegs, FLI&: FuncInfo, SwiftErrorVReg);
410}
411
412void IRTranslator::emitBranchForMergedCondition(
413 const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
414 MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB,
415 BranchProbability TProb, BranchProbability FProb, bool InvertCond) {
416 // If the leaf of the tree is a comparison, merge the condition into
417 // the caseblock.
418 if (const CmpInst *BOp = dyn_cast<CmpInst>(Val: Cond)) {
419 CmpInst::Predicate Condition;
420 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Val: Cond)) {
421 Condition = InvertCond ? IC->getInversePredicate() : IC->getPredicate();
422 } else {
423 const FCmpInst *FC = cast<FCmpInst>(Val: Cond);
424 Condition = InvertCond ? FC->getInversePredicate() : FC->getPredicate();
425 }
426
427 SwitchCG::CaseBlock CB(Condition, false, BOp->getOperand(i_nocapture: 0),
428 BOp->getOperand(i_nocapture: 1), nullptr, TBB, FBB, CurBB,
429 CurBuilder->getDebugLoc(), TProb, FProb);
430 SL->SwitchCases.push_back(x: CB);
431 return;
432 }
433
434 // Create a CaseBlock record representing this branch.
435 CmpInst::Predicate Pred = InvertCond ? CmpInst::ICMP_NE : CmpInst::ICMP_EQ;
436 SwitchCG::CaseBlock CB(
437 Pred, false, Cond, ConstantInt::getTrue(Context&: MF->getFunction().getContext()),
438 nullptr, TBB, FBB, CurBB, CurBuilder->getDebugLoc(), TProb, FProb);
439 SL->SwitchCases.push_back(x: CB);
440}
441
442static bool isValInBlock(const Value *V, const BasicBlock *BB) {
443 if (const Instruction *I = dyn_cast<Instruction>(Val: V))
444 return I->getParent() == BB;
445 return true;
446}
447
448void IRTranslator::findMergedConditions(
449 const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
450 MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB,
451 Instruction::BinaryOps Opc, BranchProbability TProb,
452 BranchProbability FProb, bool InvertCond) {
453 using namespace PatternMatch;
454 assert((Opc == Instruction::And || Opc == Instruction::Or) &&
455 "Expected Opc to be AND/OR");
456 // Skip over not part of the tree and remember to invert op and operands at
457 // next level.
458 Value *NotCond;
459 if (match(V: Cond, P: m_OneUse(SubPattern: m_Not(V: m_Value(V&: NotCond)))) &&
460 isValInBlock(V: NotCond, BB: CurBB->getBasicBlock())) {
461 findMergedConditions(Cond: NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
462 InvertCond: !InvertCond);
463 return;
464 }
465
466 const Instruction *BOp = dyn_cast<Instruction>(Val: Cond);
467 const Value *BOpOp0, *BOpOp1;
468 // Compute the effective opcode for Cond, taking into account whether it needs
469 // to be inverted, e.g.
470 // and (not (or A, B)), C
471 // gets lowered as
472 // and (and (not A, not B), C)
473 Instruction::BinaryOps BOpc = (Instruction::BinaryOps)0;
474 if (BOp) {
475 BOpc = match(V: BOp, P: m_LogicalAnd(L: m_Value(V&: BOpOp0), R: m_Value(V&: BOpOp1)))
476 ? Instruction::And
477 : (match(V: BOp, P: m_LogicalOr(L: m_Value(V&: BOpOp0), R: m_Value(V&: BOpOp1)))
478 ? Instruction::Or
479 : (Instruction::BinaryOps)0);
480 if (InvertCond) {
481 if (BOpc == Instruction::And)
482 BOpc = Instruction::Or;
483 else if (BOpc == Instruction::Or)
484 BOpc = Instruction::And;
485 }
486 }
487
488 // If this node is not part of the or/and tree, emit it as a branch.
489 // Note that all nodes in the tree should have same opcode.
490 bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->hasOneUse();
491 if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() ||
492 !isValInBlock(V: BOpOp0, BB: CurBB->getBasicBlock()) ||
493 !isValInBlock(V: BOpOp1, BB: CurBB->getBasicBlock())) {
494 emitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB, TProb, FProb,
495 InvertCond);
496 return;
497 }
498
499 // Create TmpBB after CurBB.
500 MachineFunction::iterator BBI(CurBB);
501 MachineBasicBlock *TmpBB =
502 MF->CreateMachineBasicBlock(BB: CurBB->getBasicBlock());
503 CurBB->getParent()->insert(MBBI: ++BBI, MBB: TmpBB);
504
505 if (Opc == Instruction::Or) {
506 // Codegen X | Y as:
507 // BB1:
508 // jmp_if_X TBB
509 // jmp TmpBB
510 // TmpBB:
511 // jmp_if_Y TBB
512 // jmp FBB
513 //
514
515 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
516 // The requirement is that
517 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
518 // = TrueProb for original BB.
519 // Assuming the original probabilities are A and B, one choice is to set
520 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
521 // A/(1+B) and 2B/(1+B). This choice assumes that
522 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
523 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
524 // TmpBB, but the math is more complicated.
525
526 auto NewTrueProb = TProb / 2;
527 auto NewFalseProb = TProb / 2 + FProb;
528 // Emit the LHS condition.
529 findMergedConditions(Cond: BOpOp0, TBB, FBB: TmpBB, CurBB, SwitchBB, Opc, TProb: NewTrueProb,
530 FProb: NewFalseProb, InvertCond);
531
532 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
533 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
534 BranchProbability::normalizeProbabilities(Begin: Probs.begin(), End: Probs.end());
535 // Emit the RHS condition into TmpBB.
536 findMergedConditions(Cond: BOpOp1, TBB, FBB, CurBB: TmpBB, SwitchBB, Opc, TProb: Probs[0],
537 FProb: Probs[1], InvertCond);
538 } else {
539 assert(Opc == Instruction::And && "Unknown merge op!");
540 // Codegen X & Y as:
541 // BB1:
542 // jmp_if_X TmpBB
543 // jmp FBB
544 // TmpBB:
545 // jmp_if_Y TBB
546 // jmp FBB
547 //
548 // This requires creation of TmpBB after CurBB.
549
550 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
551 // The requirement is that
552 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
553 // = FalseProb for original BB.
554 // Assuming the original probabilities are A and B, one choice is to set
555 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
556 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
557 // TrueProb for BB1 * FalseProb for TmpBB.
558
559 auto NewTrueProb = TProb + FProb / 2;
560 auto NewFalseProb = FProb / 2;
561 // Emit the LHS condition.
562 findMergedConditions(Cond: BOpOp0, TBB: TmpBB, FBB, CurBB, SwitchBB, Opc, TProb: NewTrueProb,
563 FProb: NewFalseProb, InvertCond);
564
565 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
566 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
567 BranchProbability::normalizeProbabilities(Begin: Probs.begin(), End: Probs.end());
568 // Emit the RHS condition into TmpBB.
569 findMergedConditions(Cond: BOpOp1, TBB, FBB, CurBB: TmpBB, SwitchBB, Opc, TProb: Probs[0],
570 FProb: Probs[1], InvertCond);
571 }
572}
573
574bool IRTranslator::shouldEmitAsBranches(
575 const std::vector<SwitchCG::CaseBlock> &Cases) {
576 // For multiple cases, it's better to emit as branches.
577 if (Cases.size() != 2)
578 return true;
579
580 // If this is two comparisons of the same values or'd or and'd together, they
581 // will get folded into a single comparison, so don't emit two blocks.
582 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
583 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
584 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
585 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
586 return false;
587 }
588
589 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
590 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
591 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
592 Cases[0].PredInfo.Pred == Cases[1].PredInfo.Pred &&
593 isa<Constant>(Val: Cases[0].CmpRHS) &&
594 cast<Constant>(Val: Cases[0].CmpRHS)->isNullValue()) {
595 if (Cases[0].PredInfo.Pred == CmpInst::ICMP_EQ &&
596 Cases[0].TrueBB == Cases[1].ThisBB)
597 return false;
598 if (Cases[0].PredInfo.Pred == CmpInst::ICMP_NE &&
599 Cases[0].FalseBB == Cases[1].ThisBB)
600 return false;
601 }
602
603 return true;
604}
605
606bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
607 const BranchInst &BrInst = cast<BranchInst>(Val: U);
608 auto &CurMBB = MIRBuilder.getMBB();
609 auto *Succ0MBB = &getMBB(BB: *BrInst.getSuccessor(i: 0));
610
611 if (BrInst.isUnconditional()) {
612 // If the unconditional target is the layout successor, fallthrough.
613 if (OptLevel == CodeGenOptLevel::None ||
614 !CurMBB.isLayoutSuccessor(MBB: Succ0MBB))
615 MIRBuilder.buildBr(Dest&: *Succ0MBB);
616
617 // Link successors.
618 for (const BasicBlock *Succ : successors(I: &BrInst))
619 CurMBB.addSuccessor(Succ: &getMBB(BB: *Succ));
620 return true;
621 }
622
623 // If this condition is one of the special cases we handle, do special stuff
624 // now.
625 const Value *CondVal = BrInst.getCondition();
626 MachineBasicBlock *Succ1MBB = &getMBB(BB: *BrInst.getSuccessor(i: 1));
627
628 // If this is a series of conditions that are or'd or and'd together, emit
629 // this as a sequence of branches instead of setcc's with and/or operations.
630 // As long as jumps are not expensive (exceptions for multi-use logic ops,
631 // unpredictable branches, and vector extracts because those jumps are likely
632 // expensive for any target), this should improve performance.
633 // For example, instead of something like:
634 // cmp A, B
635 // C = seteq
636 // cmp D, E
637 // F = setle
638 // or C, F
639 // jnz foo
640 // Emit:
641 // cmp A, B
642 // je foo
643 // cmp D, E
644 // jle foo
645 using namespace PatternMatch;
646 const Instruction *CondI = dyn_cast<Instruction>(Val: CondVal);
647 if (!TLI->isJumpExpensive() && CondI && CondI->hasOneUse() &&
648 !BrInst.hasMetadata(KindID: LLVMContext::MD_unpredictable)) {
649 Instruction::BinaryOps Opcode = (Instruction::BinaryOps)0;
650 Value *Vec;
651 const Value *BOp0, *BOp1;
652 if (match(V: CondI, P: m_LogicalAnd(L: m_Value(V&: BOp0), R: m_Value(V&: BOp1))))
653 Opcode = Instruction::And;
654 else if (match(V: CondI, P: m_LogicalOr(L: m_Value(V&: BOp0), R: m_Value(V&: BOp1))))
655 Opcode = Instruction::Or;
656
657 if (Opcode && !(match(V: BOp0, P: m_ExtractElt(Val: m_Value(V&: Vec), Idx: m_Value())) &&
658 match(V: BOp1, P: m_ExtractElt(Val: m_Specific(V: Vec), Idx: m_Value())))) {
659 findMergedConditions(Cond: CondI, TBB: Succ0MBB, FBB: Succ1MBB, CurBB: &CurMBB, SwitchBB: &CurMBB, Opc: Opcode,
660 TProb: getEdgeProbability(Src: &CurMBB, Dst: Succ0MBB),
661 FProb: getEdgeProbability(Src: &CurMBB, Dst: Succ1MBB),
662 /*InvertCond=*/false);
663 assert(SL->SwitchCases[0].ThisBB == &CurMBB && "Unexpected lowering!");
664
665 // Allow some cases to be rejected.
666 if (shouldEmitAsBranches(Cases: SL->SwitchCases)) {
667 // Emit the branch for this block.
668 emitSwitchCase(CB&: SL->SwitchCases[0], SwitchBB: &CurMBB, MIB&: *CurBuilder);
669 SL->SwitchCases.erase(position: SL->SwitchCases.begin());
670 return true;
671 }
672
673 // Okay, we decided not to do this, remove any inserted MBB's and clear
674 // SwitchCases.
675 for (unsigned I = 1, E = SL->SwitchCases.size(); I != E; ++I)
676 MF->erase(MBBI: SL->SwitchCases[I].ThisBB);
677
678 SL->SwitchCases.clear();
679 }
680 }
681
682 // Create a CaseBlock record representing this branch.
683 SwitchCG::CaseBlock CB(CmpInst::ICMP_EQ, false, CondVal,
684 ConstantInt::getTrue(Context&: MF->getFunction().getContext()),
685 nullptr, Succ0MBB, Succ1MBB, &CurMBB,
686 CurBuilder->getDebugLoc());
687
688 // Use emitSwitchCase to actually insert the fast branch sequence for this
689 // cond branch.
690 emitSwitchCase(CB, SwitchBB: &CurMBB, MIB&: *CurBuilder);
691 return true;
692}
693
694void IRTranslator::addSuccessorWithProb(MachineBasicBlock *Src,
695 MachineBasicBlock *Dst,
696 BranchProbability Prob) {
697 if (!FuncInfo.BPI) {
698 Src->addSuccessorWithoutProb(Succ: Dst);
699 return;
700 }
701 if (Prob.isUnknown())
702 Prob = getEdgeProbability(Src, Dst);
703 Src->addSuccessor(Succ: Dst, Prob);
704}
705
706BranchProbability
707IRTranslator::getEdgeProbability(const MachineBasicBlock *Src,
708 const MachineBasicBlock *Dst) const {
709 const BasicBlock *SrcBB = Src->getBasicBlock();
710 const BasicBlock *DstBB = Dst->getBasicBlock();
711 if (!FuncInfo.BPI) {
712 // If BPI is not available, set the default probability as 1 / N, where N is
713 // the number of successors.
714 auto SuccSize = std::max<uint32_t>(a: succ_size(BB: SrcBB), b: 1);
715 return BranchProbability(1, SuccSize);
716 }
717 return FuncInfo.BPI->getEdgeProbability(Src: SrcBB, Dst: DstBB);
718}
719
720bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) {
721 using namespace SwitchCG;
722 // Extract cases from the switch.
723 const SwitchInst &SI = cast<SwitchInst>(Val: U);
724 BranchProbabilityInfo *BPI = FuncInfo.BPI;
725 CaseClusterVector Clusters;
726 Clusters.reserve(n: SI.getNumCases());
727 for (const auto &I : SI.cases()) {
728 MachineBasicBlock *Succ = &getMBB(BB: *I.getCaseSuccessor());
729 assert(Succ && "Could not find successor mbb in mapping");
730 const ConstantInt *CaseVal = I.getCaseValue();
731 BranchProbability Prob =
732 BPI ? BPI->getEdgeProbability(Src: SI.getParent(), IndexInSuccessors: I.getSuccessorIndex())
733 : BranchProbability(1, SI.getNumCases() + 1);
734 Clusters.push_back(x: CaseCluster::range(Low: CaseVal, High: CaseVal, MBB: Succ, Prob));
735 }
736
737 MachineBasicBlock *DefaultMBB = &getMBB(BB: *SI.getDefaultDest());
738
739 // Cluster adjacent cases with the same destination. We do this at all
740 // optimization levels because it's cheap to do and will make codegen faster
741 // if there are many clusters.
742 sortAndRangeify(Clusters);
743
744 MachineBasicBlock *SwitchMBB = &getMBB(BB: *SI.getParent());
745
746 // If there is only the default destination, jump there directly.
747 if (Clusters.empty()) {
748 SwitchMBB->addSuccessor(Succ: DefaultMBB);
749 if (DefaultMBB != SwitchMBB->getNextNode())
750 MIB.buildBr(Dest&: *DefaultMBB);
751 return true;
752 }
753
754 SL->findJumpTables(Clusters, SI: &SI, SL: std::nullopt, DefaultMBB, PSI: nullptr, BFI: nullptr);
755 SL->findBitTestClusters(Clusters, SI: &SI);
756
757 LLVM_DEBUG({
758 dbgs() << "Case clusters: ";
759 for (const CaseCluster &C : Clusters) {
760 if (C.Kind == CC_JumpTable)
761 dbgs() << "JT:";
762 if (C.Kind == CC_BitTests)
763 dbgs() << "BT:";
764
765 C.Low->getValue().print(dbgs(), true);
766 if (C.Low != C.High) {
767 dbgs() << '-';
768 C.High->getValue().print(dbgs(), true);
769 }
770 dbgs() << ' ';
771 }
772 dbgs() << '\n';
773 });
774
775 assert(!Clusters.empty());
776 SwitchWorkList WorkList;
777 CaseClusterIt First = Clusters.begin();
778 CaseClusterIt Last = Clusters.end() - 1;
779 auto DefaultProb = getEdgeProbability(Src: SwitchMBB, Dst: DefaultMBB);
780 WorkList.push_back(Elt: {.MBB: SwitchMBB, .FirstCluster: First, .LastCluster: Last, .GE: nullptr, .LT: nullptr, .DefaultProb: DefaultProb});
781
782 while (!WorkList.empty()) {
783 SwitchWorkListItem W = WorkList.pop_back_val();
784
785 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
786 // For optimized builds, lower large range as a balanced binary tree.
787 if (NumClusters > 3 &&
788 MF->getTarget().getOptLevel() != CodeGenOptLevel::None &&
789 !DefaultMBB->getParent()->getFunction().hasMinSize()) {
790 splitWorkItem(WorkList, W, Cond: SI.getCondition(), SwitchMBB, MIB);
791 continue;
792 }
793
794 if (!lowerSwitchWorkItem(W, Cond: SI.getCondition(), SwitchMBB, DefaultMBB, MIB))
795 return false;
796 }
797 return true;
798}
799
800void IRTranslator::splitWorkItem(SwitchCG::SwitchWorkList &WorkList,
801 const SwitchCG::SwitchWorkListItem &W,
802 Value *Cond, MachineBasicBlock *SwitchMBB,
803 MachineIRBuilder &MIB) {
804 using namespace SwitchCG;
805 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
806 "Clusters not sorted?");
807 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
808
809 auto [LastLeft, FirstRight, LeftProb, RightProb] =
810 SL->computeSplitWorkItemInfo(W);
811
812 // Use the first element on the right as pivot since we will make less-than
813 // comparisons against it.
814 CaseClusterIt PivotCluster = FirstRight;
815 assert(PivotCluster > W.FirstCluster);
816 assert(PivotCluster <= W.LastCluster);
817
818 CaseClusterIt FirstLeft = W.FirstCluster;
819 CaseClusterIt LastRight = W.LastCluster;
820
821 const ConstantInt *Pivot = PivotCluster->Low;
822
823 // New blocks will be inserted immediately after the current one.
824 MachineFunction::iterator BBI(W.MBB);
825 ++BBI;
826
827 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
828 // we can branch to its destination directly if it's squeezed exactly in
829 // between the known lower bound and Pivot - 1.
830 MachineBasicBlock *LeftMBB;
831 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
832 FirstLeft->Low == W.GE &&
833 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
834 LeftMBB = FirstLeft->MBB;
835 } else {
836 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(BB: W.MBB->getBasicBlock());
837 FuncInfo.MF->insert(MBBI: BBI, MBB: LeftMBB);
838 WorkList.push_back(
839 Elt: {.MBB: LeftMBB, .FirstCluster: FirstLeft, .LastCluster: LastLeft, .GE: W.GE, .LT: Pivot, .DefaultProb: W.DefaultProb / 2});
840 }
841
842 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
843 // single cluster, RHS.Low == Pivot, and we can branch to its destination
844 // directly if RHS.High equals the current upper bound.
845 MachineBasicBlock *RightMBB;
846 if (FirstRight == LastRight && FirstRight->Kind == CC_Range && W.LT &&
847 (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
848 RightMBB = FirstRight->MBB;
849 } else {
850 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(BB: W.MBB->getBasicBlock());
851 FuncInfo.MF->insert(MBBI: BBI, MBB: RightMBB);
852 WorkList.push_back(
853 Elt: {.MBB: RightMBB, .FirstCluster: FirstRight, .LastCluster: LastRight, .GE: Pivot, .LT: W.LT, .DefaultProb: W.DefaultProb / 2});
854 }
855
856 // Create the CaseBlock record that will be used to lower the branch.
857 CaseBlock CB(ICmpInst::Predicate::ICMP_SLT, false, Cond, Pivot, nullptr,
858 LeftMBB, RightMBB, W.MBB, MIB.getDebugLoc(), LeftProb,
859 RightProb);
860
861 if (W.MBB == SwitchMBB)
862 emitSwitchCase(CB, SwitchBB: SwitchMBB, MIB);
863 else
864 SL->SwitchCases.push_back(x: CB);
865}
866
867void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
868 MachineBasicBlock *MBB) {
869 // Emit the code for the jump table
870 assert(JT.Reg && "Should lower JT Header first!");
871 MachineIRBuilder MIB(*MBB->getParent());
872 MIB.setMBB(*MBB);
873 MIB.setDebugLoc(CurBuilder->getDebugLoc());
874
875 Type *PtrIRTy = PointerType::getUnqual(C&: MF->getFunction().getContext());
876 const LLT PtrTy = getLLTForType(Ty&: *PtrIRTy, DL: *DL);
877
878 auto Table = MIB.buildJumpTable(PtrTy, JTI: JT.JTI);
879 MIB.buildBrJT(TablePtr: Table.getReg(Idx: 0), JTI: JT.JTI, IndexReg: JT.Reg);
880}
881
882bool IRTranslator::emitJumpTableHeader(SwitchCG::JumpTable &JT,
883 SwitchCG::JumpTableHeader &JTH,
884 MachineBasicBlock *HeaderBB) {
885 MachineIRBuilder MIB(*HeaderBB->getParent());
886 MIB.setMBB(*HeaderBB);
887 MIB.setDebugLoc(CurBuilder->getDebugLoc());
888
889 const Value &SValue = *JTH.SValue;
890 // Subtract the lowest switch case value from the value being switched on.
891 const LLT SwitchTy = getLLTForType(Ty&: *SValue.getType(), DL: *DL);
892 Register SwitchOpReg = getOrCreateVReg(Val: SValue);
893 auto FirstCst = MIB.buildConstant(Res: SwitchTy, Val: JTH.First);
894 auto Sub = MIB.buildSub(Dst: {SwitchTy}, Src0: SwitchOpReg, Src1: FirstCst);
895
896 // This value may be smaller or larger than the target's pointer type, and
897 // therefore require extension or truncating.
898 auto *PtrIRTy = PointerType::getUnqual(C&: SValue.getContext());
899 const LLT PtrScalarTy = LLT::scalar(SizeInBits: DL->getTypeSizeInBits(Ty: PtrIRTy));
900 Sub = MIB.buildZExtOrTrunc(Res: PtrScalarTy, Op: Sub);
901
902 JT.Reg = Sub.getReg(Idx: 0);
903
904 if (JTH.FallthroughUnreachable) {
905 if (JT.MBB != HeaderBB->getNextNode())
906 MIB.buildBr(Dest&: *JT.MBB);
907 return true;
908 }
909
910 // Emit the range check for the jump table, and branch to the default block
911 // for the switch statement if the value being switched on exceeds the
912 // largest case in the switch.
913 auto Cst = getOrCreateVReg(
914 Val: *ConstantInt::get(Ty: SValue.getType(), V: JTH.Last - JTH.First));
915 Cst = MIB.buildZExtOrTrunc(Res: PtrScalarTy, Op: Cst).getReg(Idx: 0);
916 auto Cmp = MIB.buildICmp(Pred: CmpInst::ICMP_UGT, Res: LLT::scalar(SizeInBits: 1), Op0: Sub, Op1: Cst);
917
918 auto BrCond = MIB.buildBrCond(Tst: Cmp.getReg(Idx: 0), Dest&: *JT.Default);
919
920 // Avoid emitting unnecessary branches to the next block.
921 if (JT.MBB != HeaderBB->getNextNode())
922 BrCond = MIB.buildBr(Dest&: *JT.MBB);
923 return true;
924}
925
926void IRTranslator::emitSwitchCase(SwitchCG::CaseBlock &CB,
927 MachineBasicBlock *SwitchBB,
928 MachineIRBuilder &MIB) {
929 Register CondLHS = getOrCreateVReg(Val: *CB.CmpLHS);
930 Register Cond;
931 DebugLoc OldDbgLoc = MIB.getDebugLoc();
932 MIB.setDebugLoc(CB.DbgLoc);
933 MIB.setMBB(*CB.ThisBB);
934
935 if (CB.PredInfo.NoCmp) {
936 // Branch or fall through to TrueBB.
937 addSuccessorWithProb(Src: CB.ThisBB, Dst: CB.TrueBB, Prob: CB.TrueProb);
938 addMachineCFGPred(Edge: {SwitchBB->getBasicBlock(), CB.TrueBB->getBasicBlock()},
939 NewPred: CB.ThisBB);
940 CB.ThisBB->normalizeSuccProbs();
941 if (CB.TrueBB != CB.ThisBB->getNextNode())
942 MIB.buildBr(Dest&: *CB.TrueBB);
943 MIB.setDebugLoc(OldDbgLoc);
944 return;
945 }
946
947 const LLT i1Ty = LLT::scalar(SizeInBits: 1);
948 // Build the compare.
949 if (!CB.CmpMHS) {
950 const auto *CI = dyn_cast<ConstantInt>(Val: CB.CmpRHS);
951 // For conditional branch lowering, we might try to do something silly like
952 // emit an G_ICMP to compare an existing G_ICMP i1 result with true. If so,
953 // just re-use the existing condition vreg.
954 if (MRI->getType(Reg: CondLHS).getSizeInBits() == 1 && CI && CI->isOne() &&
955 CB.PredInfo.Pred == CmpInst::ICMP_EQ) {
956 Cond = CondLHS;
957 } else {
958 Register CondRHS = getOrCreateVReg(Val: *CB.CmpRHS);
959 if (CmpInst::isFPPredicate(P: CB.PredInfo.Pred))
960 Cond =
961 MIB.buildFCmp(Pred: CB.PredInfo.Pred, Res: i1Ty, Op0: CondLHS, Op1: CondRHS).getReg(Idx: 0);
962 else
963 Cond =
964 MIB.buildICmp(Pred: CB.PredInfo.Pred, Res: i1Ty, Op0: CondLHS, Op1: CondRHS).getReg(Idx: 0);
965 }
966 } else {
967 assert(CB.PredInfo.Pred == CmpInst::ICMP_SLE &&
968 "Can only handle SLE ranges");
969
970 const APInt& Low = cast<ConstantInt>(Val: CB.CmpLHS)->getValue();
971 const APInt& High = cast<ConstantInt>(Val: CB.CmpRHS)->getValue();
972
973 Register CmpOpReg = getOrCreateVReg(Val: *CB.CmpMHS);
974 if (cast<ConstantInt>(Val: CB.CmpLHS)->isMinValue(IsSigned: true)) {
975 Register CondRHS = getOrCreateVReg(Val: *CB.CmpRHS);
976 Cond =
977 MIB.buildICmp(Pred: CmpInst::ICMP_SLE, Res: i1Ty, Op0: CmpOpReg, Op1: CondRHS).getReg(Idx: 0);
978 } else {
979 const LLT CmpTy = MRI->getType(Reg: CmpOpReg);
980 auto Sub = MIB.buildSub(Dst: {CmpTy}, Src0: CmpOpReg, Src1: CondLHS);
981 auto Diff = MIB.buildConstant(Res: CmpTy, Val: High - Low);
982 Cond = MIB.buildICmp(Pred: CmpInst::ICMP_ULE, Res: i1Ty, Op0: Sub, Op1: Diff).getReg(Idx: 0);
983 }
984 }
985
986 // Update successor info
987 addSuccessorWithProb(Src: CB.ThisBB, Dst: CB.TrueBB, Prob: CB.TrueProb);
988
989 addMachineCFGPred(Edge: {SwitchBB->getBasicBlock(), CB.TrueBB->getBasicBlock()},
990 NewPred: CB.ThisBB);
991
992 // TrueBB and FalseBB are always different unless the incoming IR is
993 // degenerate. This only happens when running llc on weird IR.
994 if (CB.TrueBB != CB.FalseBB)
995 addSuccessorWithProb(Src: CB.ThisBB, Dst: CB.FalseBB, Prob: CB.FalseProb);
996 CB.ThisBB->normalizeSuccProbs();
997
998 addMachineCFGPred(Edge: {SwitchBB->getBasicBlock(), CB.FalseBB->getBasicBlock()},
999 NewPred: CB.ThisBB);
1000
1001 MIB.buildBrCond(Tst: Cond, Dest&: *CB.TrueBB);
1002 MIB.buildBr(Dest&: *CB.FalseBB);
1003 MIB.setDebugLoc(OldDbgLoc);
1004}
1005
1006bool IRTranslator::lowerJumpTableWorkItem(SwitchCG::SwitchWorkListItem W,
1007 MachineBasicBlock *SwitchMBB,
1008 MachineBasicBlock *CurMBB,
1009 MachineBasicBlock *DefaultMBB,
1010 MachineIRBuilder &MIB,
1011 MachineFunction::iterator BBI,
1012 BranchProbability UnhandledProbs,
1013 SwitchCG::CaseClusterIt I,
1014 MachineBasicBlock *Fallthrough,
1015 bool FallthroughUnreachable) {
1016 using namespace SwitchCG;
1017 MachineFunction *CurMF = SwitchMBB->getParent();
1018 // FIXME: Optimize away range check based on pivot comparisons.
1019 JumpTableHeader *JTH = &SL->JTCases[I->JTCasesIndex].first;
1020 SwitchCG::JumpTable *JT = &SL->JTCases[I->JTCasesIndex].second;
1021 BranchProbability DefaultProb = W.DefaultProb;
1022
1023 // The jump block hasn't been inserted yet; insert it here.
1024 MachineBasicBlock *JumpMBB = JT->MBB;
1025 CurMF->insert(MBBI: BBI, MBB: JumpMBB);
1026
1027 // Since the jump table block is separate from the switch block, we need
1028 // to keep track of it as a machine predecessor to the default block,
1029 // otherwise we lose the phi edges.
1030 addMachineCFGPred(Edge: {SwitchMBB->getBasicBlock(), DefaultMBB->getBasicBlock()},
1031 NewPred: CurMBB);
1032 addMachineCFGPred(Edge: {SwitchMBB->getBasicBlock(), DefaultMBB->getBasicBlock()},
1033 NewPred: JumpMBB);
1034
1035 auto JumpProb = I->Prob;
1036 auto FallthroughProb = UnhandledProbs;
1037
1038 // If the default statement is a target of the jump table, we evenly
1039 // distribute the default probability to successors of CurMBB. Also
1040 // update the probability on the edge from JumpMBB to Fallthrough.
1041 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
1042 SE = JumpMBB->succ_end();
1043 SI != SE; ++SI) {
1044 if (*SI == DefaultMBB) {
1045 JumpProb += DefaultProb / 2;
1046 FallthroughProb -= DefaultProb / 2;
1047 JumpMBB->setSuccProbability(I: SI, Prob: DefaultProb / 2);
1048 JumpMBB->normalizeSuccProbs();
1049 } else {
1050 // Also record edges from the jump table block to it's successors.
1051 addMachineCFGPred(Edge: {SwitchMBB->getBasicBlock(), (*SI)->getBasicBlock()},
1052 NewPred: JumpMBB);
1053 }
1054 }
1055
1056 if (FallthroughUnreachable)
1057 JTH->FallthroughUnreachable = true;
1058
1059 if (!JTH->FallthroughUnreachable)
1060 addSuccessorWithProb(Src: CurMBB, Dst: Fallthrough, Prob: FallthroughProb);
1061 addSuccessorWithProb(Src: CurMBB, Dst: JumpMBB, Prob: JumpProb);
1062 CurMBB->normalizeSuccProbs();
1063
1064 // The jump table header will be inserted in our current block, do the
1065 // range check, and fall through to our fallthrough block.
1066 JTH->HeaderBB = CurMBB;
1067 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
1068
1069 // If we're in the right place, emit the jump table header right now.
1070 if (CurMBB == SwitchMBB) {
1071 if (!emitJumpTableHeader(JT&: *JT, JTH&: *JTH, HeaderBB: CurMBB))
1072 return false;
1073 JTH->Emitted = true;
1074 }
1075 return true;
1076}
1077bool IRTranslator::lowerSwitchRangeWorkItem(SwitchCG::CaseClusterIt I,
1078 Value *Cond,
1079 MachineBasicBlock *Fallthrough,
1080 bool FallthroughUnreachable,
1081 BranchProbability UnhandledProbs,
1082 MachineBasicBlock *CurMBB,
1083 MachineIRBuilder &MIB,
1084 MachineBasicBlock *SwitchMBB) {
1085 using namespace SwitchCG;
1086 const Value *RHS, *LHS, *MHS;
1087 CmpInst::Predicate Pred;
1088 if (I->Low == I->High) {
1089 // Check Cond == I->Low.
1090 Pred = CmpInst::ICMP_EQ;
1091 LHS = Cond;
1092 RHS = I->Low;
1093 MHS = nullptr;
1094 } else {
1095 // Check I->Low <= Cond <= I->High.
1096 Pred = CmpInst::ICMP_SLE;
1097 LHS = I->Low;
1098 MHS = Cond;
1099 RHS = I->High;
1100 }
1101
1102 // If Fallthrough is unreachable, fold away the comparison.
1103 // The false probability is the sum of all unhandled cases.
1104 CaseBlock CB(Pred, FallthroughUnreachable, LHS, RHS, MHS, I->MBB, Fallthrough,
1105 CurMBB, MIB.getDebugLoc(), I->Prob, UnhandledProbs);
1106
1107 emitSwitchCase(CB, SwitchBB: SwitchMBB, MIB);
1108 return true;
1109}
1110
1111void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
1112 MachineBasicBlock *SwitchBB) {
1113 MachineIRBuilder &MIB = *CurBuilder;
1114 MIB.setMBB(*SwitchBB);
1115
1116 // Subtract the minimum value.
1117 Register SwitchOpReg = getOrCreateVReg(Val: *B.SValue);
1118
1119 LLT SwitchOpTy = MRI->getType(Reg: SwitchOpReg);
1120 Register MinValReg = MIB.buildConstant(Res: SwitchOpTy, Val: B.First).getReg(Idx: 0);
1121 auto RangeSub = MIB.buildSub(Dst: SwitchOpTy, Src0: SwitchOpReg, Src1: MinValReg);
1122
1123 Type *PtrIRTy = PointerType::getUnqual(C&: MF->getFunction().getContext());
1124 const LLT PtrTy = getLLTForType(Ty&: *PtrIRTy, DL: *DL);
1125
1126 LLT MaskTy = SwitchOpTy;
1127 if (MaskTy.getSizeInBits() > PtrTy.getSizeInBits() ||
1128 !llvm::has_single_bit<uint32_t>(Value: MaskTy.getSizeInBits()))
1129 MaskTy = LLT::scalar(SizeInBits: PtrTy.getSizeInBits());
1130 else {
1131 // Ensure that the type will fit the mask value.
1132 for (const SwitchCG::BitTestCase &Case : B.Cases) {
1133 if (!isUIntN(N: SwitchOpTy.getSizeInBits(), x: Case.Mask)) {
1134 // Switch table case range are encoded into series of masks.
1135 // Just use pointer type, it's guaranteed to fit.
1136 MaskTy = LLT::scalar(SizeInBits: PtrTy.getSizeInBits());
1137 break;
1138 }
1139 }
1140 }
1141 Register SubReg = RangeSub.getReg(Idx: 0);
1142 if (SwitchOpTy != MaskTy)
1143 SubReg = MIB.buildZExtOrTrunc(Res: MaskTy, Op: SubReg).getReg(Idx: 0);
1144
1145 B.RegVT = getMVTForLLT(Ty: MaskTy);
1146 B.Reg = SubReg;
1147
1148 MachineBasicBlock *MBB = B.Cases[0].ThisBB;
1149
1150 if (!B.FallthroughUnreachable)
1151 addSuccessorWithProb(Src: SwitchBB, Dst: B.Default, Prob: B.DefaultProb);
1152 addSuccessorWithProb(Src: SwitchBB, Dst: MBB, Prob: B.Prob);
1153
1154 SwitchBB->normalizeSuccProbs();
1155
1156 if (!B.FallthroughUnreachable) {
1157 // Conditional branch to the default block.
1158 auto RangeCst = MIB.buildConstant(Res: SwitchOpTy, Val: B.Range);
1159 auto RangeCmp = MIB.buildICmp(Pred: CmpInst::Predicate::ICMP_UGT, Res: LLT::scalar(SizeInBits: 1),
1160 Op0: RangeSub, Op1: RangeCst);
1161 MIB.buildBrCond(Tst: RangeCmp, Dest&: *B.Default);
1162 }
1163
1164 // Avoid emitting unnecessary branches to the next block.
1165 if (MBB != SwitchBB->getNextNode())
1166 MIB.buildBr(Dest&: *MBB);
1167}
1168
1169void IRTranslator::emitBitTestCase(SwitchCG::BitTestBlock &BB,
1170 MachineBasicBlock *NextMBB,
1171 BranchProbability BranchProbToNext,
1172 Register Reg, SwitchCG::BitTestCase &B,
1173 MachineBasicBlock *SwitchBB) {
1174 MachineIRBuilder &MIB = *CurBuilder;
1175 MIB.setMBB(*SwitchBB);
1176
1177 LLT SwitchTy = getLLTForMVT(Ty: BB.RegVT);
1178 Register Cmp;
1179 unsigned PopCount = llvm::popcount(Value: B.Mask);
1180 if (PopCount == 1) {
1181 // Testing for a single bit; just compare the shift count with what it
1182 // would need to be to shift a 1 bit in that position.
1183 auto MaskTrailingZeros =
1184 MIB.buildConstant(Res: SwitchTy, Val: llvm::countr_zero(Val: B.Mask));
1185 Cmp =
1186 MIB.buildICmp(Pred: ICmpInst::ICMP_EQ, Res: LLT::scalar(SizeInBits: 1), Op0: Reg, Op1: MaskTrailingZeros)
1187 .getReg(Idx: 0);
1188 } else if (PopCount == BB.Range) {
1189 // There is only one zero bit in the range, test for it directly.
1190 auto MaskTrailingOnes =
1191 MIB.buildConstant(Res: SwitchTy, Val: llvm::countr_one(Value: B.Mask));
1192 Cmp = MIB.buildICmp(Pred: CmpInst::ICMP_NE, Res: LLT::scalar(SizeInBits: 1), Op0: Reg, Op1: MaskTrailingOnes)
1193 .getReg(Idx: 0);
1194 } else {
1195 // Make desired shift.
1196 auto CstOne = MIB.buildConstant(Res: SwitchTy, Val: 1);
1197 auto SwitchVal = MIB.buildShl(Dst: SwitchTy, Src0: CstOne, Src1: Reg);
1198
1199 // Emit bit tests and jumps.
1200 auto CstMask = MIB.buildConstant(Res: SwitchTy, Val: B.Mask);
1201 auto AndOp = MIB.buildAnd(Dst: SwitchTy, Src0: SwitchVal, Src1: CstMask);
1202 auto CstZero = MIB.buildConstant(Res: SwitchTy, Val: 0);
1203 Cmp = MIB.buildICmp(Pred: CmpInst::ICMP_NE, Res: LLT::scalar(SizeInBits: 1), Op0: AndOp, Op1: CstZero)
1204 .getReg(Idx: 0);
1205 }
1206
1207 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
1208 addSuccessorWithProb(Src: SwitchBB, Dst: B.TargetBB, Prob: B.ExtraProb);
1209 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
1210 addSuccessorWithProb(Src: SwitchBB, Dst: NextMBB, Prob: BranchProbToNext);
1211 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
1212 // one as they are relative probabilities (and thus work more like weights),
1213 // and hence we need to normalize them to let the sum of them become one.
1214 SwitchBB->normalizeSuccProbs();
1215
1216 // Record the fact that the IR edge from the header to the bit test target
1217 // will go through our new block. Neeeded for PHIs to have nodes added.
1218 addMachineCFGPred(Edge: {BB.Parent->getBasicBlock(), B.TargetBB->getBasicBlock()},
1219 NewPred: SwitchBB);
1220
1221 MIB.buildBrCond(Tst: Cmp, Dest&: *B.TargetBB);
1222
1223 // Avoid emitting unnecessary branches to the next block.
1224 if (NextMBB != SwitchBB->getNextNode())
1225 MIB.buildBr(Dest&: *NextMBB);
1226}
1227
1228bool IRTranslator::lowerBitTestWorkItem(
1229 SwitchCG::SwitchWorkListItem W, MachineBasicBlock *SwitchMBB,
1230 MachineBasicBlock *CurMBB, MachineBasicBlock *DefaultMBB,
1231 MachineIRBuilder &MIB, MachineFunction::iterator BBI,
1232 BranchProbability DefaultProb, BranchProbability UnhandledProbs,
1233 SwitchCG::CaseClusterIt I, MachineBasicBlock *Fallthrough,
1234 bool FallthroughUnreachable) {
1235 using namespace SwitchCG;
1236 MachineFunction *CurMF = SwitchMBB->getParent();
1237 // FIXME: Optimize away range check based on pivot comparisons.
1238 BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex];
1239 // The bit test blocks haven't been inserted yet; insert them here.
1240 for (BitTestCase &BTC : BTB->Cases)
1241 CurMF->insert(MBBI: BBI, MBB: BTC.ThisBB);
1242
1243 // Fill in fields of the BitTestBlock.
1244 BTB->Parent = CurMBB;
1245 BTB->Default = Fallthrough;
1246
1247 BTB->DefaultProb = UnhandledProbs;
1248 // If the cases in bit test don't form a contiguous range, we evenly
1249 // distribute the probability on the edge to Fallthrough to two
1250 // successors of CurMBB.
1251 if (!BTB->ContiguousRange) {
1252 BTB->Prob += DefaultProb / 2;
1253 BTB->DefaultProb -= DefaultProb / 2;
1254 }
1255
1256 if (FallthroughUnreachable)
1257 BTB->FallthroughUnreachable = true;
1258
1259 // If we're in the right place, emit the bit test header right now.
1260 if (CurMBB == SwitchMBB) {
1261 emitBitTestHeader(B&: *BTB, SwitchBB: SwitchMBB);
1262 BTB->Emitted = true;
1263 }
1264 return true;
1265}
1266
1267bool IRTranslator::lowerSwitchWorkItem(SwitchCG::SwitchWorkListItem W,
1268 Value *Cond,
1269 MachineBasicBlock *SwitchMBB,
1270 MachineBasicBlock *DefaultMBB,
1271 MachineIRBuilder &MIB) {
1272 using namespace SwitchCG;
1273 MachineFunction *CurMF = FuncInfo.MF;
1274 MachineBasicBlock *NextMBB = nullptr;
1275 MachineFunction::iterator BBI(W.MBB);
1276 if (++BBI != FuncInfo.MF->end())
1277 NextMBB = &*BBI;
1278
1279 if (EnableOpts) {
1280 // Here, we order cases by probability so the most likely case will be
1281 // checked first. However, two clusters can have the same probability in
1282 // which case their relative ordering is non-deterministic. So we use Low
1283 // as a tie-breaker as clusters are guaranteed to never overlap.
1284 llvm::sort(Start: W.FirstCluster, End: W.LastCluster + 1,
1285 Comp: [](const CaseCluster &a, const CaseCluster &b) {
1286 return a.Prob != b.Prob
1287 ? a.Prob > b.Prob
1288 : a.Low->getValue().slt(RHS: b.Low->getValue());
1289 });
1290
1291 // Rearrange the case blocks so that the last one falls through if possible
1292 // without changing the order of probabilities.
1293 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster;) {
1294 --I;
1295 if (I->Prob > W.LastCluster->Prob)
1296 break;
1297 if (I->Kind == CC_Range && I->MBB == NextMBB) {
1298 std::swap(a&: *I, b&: *W.LastCluster);
1299 break;
1300 }
1301 }
1302 }
1303
1304 // Compute total probability.
1305 BranchProbability DefaultProb = W.DefaultProb;
1306 BranchProbability UnhandledProbs = DefaultProb;
1307 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
1308 UnhandledProbs += I->Prob;
1309
1310 MachineBasicBlock *CurMBB = W.MBB;
1311 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
1312 bool FallthroughUnreachable = false;
1313 MachineBasicBlock *Fallthrough;
1314 if (I == W.LastCluster) {
1315 // For the last cluster, fall through to the default destination.
1316 Fallthrough = DefaultMBB;
1317 FallthroughUnreachable = isa<UnreachableInst>(
1318 Val: DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
1319 } else {
1320 Fallthrough = CurMF->CreateMachineBasicBlock(BB: CurMBB->getBasicBlock());
1321 CurMF->insert(MBBI: BBI, MBB: Fallthrough);
1322 }
1323 UnhandledProbs -= I->Prob;
1324
1325 switch (I->Kind) {
1326 case CC_BitTests: {
1327 if (!lowerBitTestWorkItem(W, SwitchMBB, CurMBB, DefaultMBB, MIB, BBI,
1328 DefaultProb, UnhandledProbs, I, Fallthrough,
1329 FallthroughUnreachable)) {
1330 LLVM_DEBUG(dbgs() << "Failed to lower bit test for switch");
1331 return false;
1332 }
1333 break;
1334 }
1335
1336 case CC_JumpTable: {
1337 if (!lowerJumpTableWorkItem(W, SwitchMBB, CurMBB, DefaultMBB, MIB, BBI,
1338 UnhandledProbs, I, Fallthrough,
1339 FallthroughUnreachable)) {
1340 LLVM_DEBUG(dbgs() << "Failed to lower jump table");
1341 return false;
1342 }
1343 break;
1344 }
1345 case CC_Range: {
1346 if (!lowerSwitchRangeWorkItem(I, Cond, Fallthrough,
1347 FallthroughUnreachable, UnhandledProbs,
1348 CurMBB, MIB, SwitchMBB)) {
1349 LLVM_DEBUG(dbgs() << "Failed to lower switch range");
1350 return false;
1351 }
1352 break;
1353 }
1354 }
1355 CurMBB = Fallthrough;
1356 }
1357
1358 return true;
1359}
1360
1361bool IRTranslator::translateIndirectBr(const User &U,
1362 MachineIRBuilder &MIRBuilder) {
1363 const IndirectBrInst &BrInst = cast<IndirectBrInst>(Val: U);
1364
1365 const Register Tgt = getOrCreateVReg(Val: *BrInst.getAddress());
1366 MIRBuilder.buildBrIndirect(Tgt);
1367
1368 // Link successors.
1369 SmallPtrSet<const BasicBlock *, 32> AddedSuccessors;
1370 MachineBasicBlock &CurBB = MIRBuilder.getMBB();
1371 for (const BasicBlock *Succ : successors(I: &BrInst)) {
1372 // It's legal for indirectbr instructions to have duplicate blocks in the
1373 // destination list. We don't allow this in MIR. Skip anything that's
1374 // already a successor.
1375 if (!AddedSuccessors.insert(Ptr: Succ).second)
1376 continue;
1377 CurBB.addSuccessor(Succ: &getMBB(BB: *Succ));
1378 }
1379
1380 return true;
1381}
1382
1383static bool isSwiftError(const Value *V) {
1384 if (auto Arg = dyn_cast<Argument>(Val: V))
1385 return Arg->hasSwiftErrorAttr();
1386 if (auto AI = dyn_cast<AllocaInst>(Val: V))
1387 return AI->isSwiftError();
1388 return false;
1389}
1390
1391bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
1392 const LoadInst &LI = cast<LoadInst>(Val: U);
1393 TypeSize StoreSize = DL->getTypeStoreSize(Ty: LI.getType());
1394 if (StoreSize.isZero())
1395 return true;
1396
1397 ArrayRef<Register> Regs = getOrCreateVRegs(Val: LI);
1398 ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V: LI);
1399 Register Base = getOrCreateVReg(Val: *LI.getPointerOperand());
1400 AAMDNodes AAInfo = LI.getAAMetadata();
1401
1402 const Value *Ptr = LI.getPointerOperand();
1403 Type *OffsetIRTy = DL->getIndexType(PtrTy: Ptr->getType());
1404 LLT OffsetTy = getLLTForType(Ty&: *OffsetIRTy, DL: *DL);
1405
1406 if (CLI->supportSwiftError() && isSwiftError(V: Ptr)) {
1407 assert(Regs.size() == 1 && "swifterror should be single pointer");
1408 Register VReg =
1409 SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(), Ptr);
1410 MIRBuilder.buildCopy(Res: Regs[0], Op: VReg);
1411 return true;
1412 }
1413
1414 MachineMemOperand::Flags Flags =
1415 TLI->getLoadMemOperandFlags(LI, DL: *DL, AC, LibInfo);
1416 if (AA && !(Flags & MachineMemOperand::MOInvariant)) {
1417 if (AA->pointsToConstantMemory(
1418 Loc: MemoryLocation(Ptr, LocationSize::precise(Value: StoreSize), AAInfo))) {
1419 Flags |= MachineMemOperand::MOInvariant;
1420 }
1421 }
1422
1423 const MDNode *Ranges =
1424 Regs.size() == 1 ? LI.getMetadata(KindID: LLVMContext::MD_range) : nullptr;
1425 for (unsigned i = 0; i < Regs.size(); ++i) {
1426 Register Addr;
1427 MIRBuilder.materializeObjectPtrOffset(Res&: Addr, Op0: Base, ValueTy: OffsetTy, Value: Offsets[i]);
1428
1429 MachinePointerInfo Ptr(LI.getPointerOperand(), Offsets[i]);
1430 Align BaseAlign = getMemOpAlign(I: LI);
1431 auto MMO =
1432 MF->getMachineMemOperand(PtrInfo: Ptr, f: Flags, MemTy: MRI->getType(Reg: Regs[i]),
1433 base_alignment: commonAlignment(A: BaseAlign, Offset: Offsets[i]), AAInfo,
1434 Ranges, SSID: LI.getSyncScopeID(), Ordering: LI.getOrdering());
1435 MIRBuilder.buildLoad(Res: Regs[i], Addr, MMO&: *MMO);
1436 }
1437
1438 return true;
1439}
1440
1441bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
1442 const StoreInst &SI = cast<StoreInst>(Val: U);
1443 if (DL->getTypeStoreSize(Ty: SI.getValueOperand()->getType()).isZero())
1444 return true;
1445
1446 ArrayRef<Register> Vals = getOrCreateVRegs(Val: *SI.getValueOperand());
1447 ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V: *SI.getValueOperand());
1448 Register Base = getOrCreateVReg(Val: *SI.getPointerOperand());
1449
1450 Type *OffsetIRTy = DL->getIndexType(PtrTy: SI.getPointerOperandType());
1451 LLT OffsetTy = getLLTForType(Ty&: *OffsetIRTy, DL: *DL);
1452
1453 if (CLI->supportSwiftError() && isSwiftError(V: SI.getPointerOperand())) {
1454 assert(Vals.size() == 1 && "swifterror should be single pointer");
1455
1456 Register VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
1457 SI.getPointerOperand());
1458 MIRBuilder.buildCopy(Res: VReg, Op: Vals[0]);
1459 return true;
1460 }
1461
1462 MachineMemOperand::Flags Flags = TLI->getStoreMemOperandFlags(SI, DL: *DL);
1463
1464 for (unsigned i = 0; i < Vals.size(); ++i) {
1465 Register Addr;
1466 MIRBuilder.materializeObjectPtrOffset(Res&: Addr, Op0: Base, ValueTy: OffsetTy, Value: Offsets[i]);
1467
1468 MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i]);
1469 Align BaseAlign = getMemOpAlign(I: SI);
1470 auto MMO = MF->getMachineMemOperand(PtrInfo: Ptr, f: Flags, MemTy: MRI->getType(Reg: Vals[i]),
1471 base_alignment: commonAlignment(A: BaseAlign, Offset: Offsets[i]),
1472 AAInfo: SI.getAAMetadata(), Ranges: nullptr,
1473 SSID: SI.getSyncScopeID(), Ordering: SI.getOrdering());
1474 MIRBuilder.buildStore(Val: Vals[i], Addr, MMO&: *MMO);
1475 }
1476 return true;
1477}
1478
1479static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
1480 const Value *Src = U.getOperand(i: 0);
1481 Type *Int32Ty = Type::getInt32Ty(C&: U.getContext());
1482
1483 // getIndexedOffsetInType is designed for GEPs, so the first index is the
1484 // usual array element rather than looking into the actual aggregate.
1485 SmallVector<Value *, 1> Indices;
1486 Indices.push_back(Elt: ConstantInt::get(Ty: Int32Ty, V: 0));
1487
1488 if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(Val: &U)) {
1489 for (auto Idx : EVI->indices())
1490 Indices.push_back(Elt: ConstantInt::get(Ty: Int32Ty, V: Idx));
1491 } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(Val: &U)) {
1492 for (auto Idx : IVI->indices())
1493 Indices.push_back(Elt: ConstantInt::get(Ty: Int32Ty, V: Idx));
1494 } else {
1495 llvm::append_range(C&: Indices, R: drop_begin(RangeOrContainer: U.operands()));
1496 }
1497
1498 return static_cast<uint64_t>(
1499 DL.getIndexedOffsetInType(ElemTy: Src->getType(), Indices));
1500}
1501
1502bool IRTranslator::translateExtractValue(const User &U,
1503 MachineIRBuilder &MIRBuilder) {
1504 const Value *Src = U.getOperand(i: 0);
1505 uint64_t Offset = getOffsetFromIndices(U, DL: *DL);
1506 ArrayRef<Register> SrcRegs = getOrCreateVRegs(Val: *Src);
1507 ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V: *Src);
1508 unsigned Idx = llvm::lower_bound(Range&: Offsets, Value&: Offset) - Offsets.begin();
1509 auto &DstRegs = allocateVRegs(Val: U);
1510
1511 for (unsigned i = 0; i < DstRegs.size(); ++i)
1512 DstRegs[i] = SrcRegs[Idx++];
1513
1514 return true;
1515}
1516
1517bool IRTranslator::translateInsertValue(const User &U,
1518 MachineIRBuilder &MIRBuilder) {
1519 const Value *Src = U.getOperand(i: 0);
1520 uint64_t Offset = getOffsetFromIndices(U, DL: *DL);
1521 auto &DstRegs = allocateVRegs(Val: U);
1522 ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(V: U);
1523 ArrayRef<Register> SrcRegs = getOrCreateVRegs(Val: *Src);
1524 ArrayRef<Register> InsertedRegs = getOrCreateVRegs(Val: *U.getOperand(i: 1));
1525 auto *InsertedIt = InsertedRegs.begin();
1526
1527 for (unsigned i = 0; i < DstRegs.size(); ++i) {
1528 if (DstOffsets[i] >= Offset && InsertedIt != InsertedRegs.end())
1529 DstRegs[i] = *InsertedIt++;
1530 else
1531 DstRegs[i] = SrcRegs[i];
1532 }
1533
1534 return true;
1535}
1536
1537bool IRTranslator::translateSelect(const User &U,
1538 MachineIRBuilder &MIRBuilder) {
1539 Register Tst = getOrCreateVReg(Val: *U.getOperand(i: 0));
1540 ArrayRef<Register> ResRegs = getOrCreateVRegs(Val: U);
1541 ArrayRef<Register> Op0Regs = getOrCreateVRegs(Val: *U.getOperand(i: 1));
1542 ArrayRef<Register> Op1Regs = getOrCreateVRegs(Val: *U.getOperand(i: 2));
1543
1544 uint32_t Flags = 0;
1545 if (const SelectInst *SI = dyn_cast<SelectInst>(Val: &U))
1546 Flags = MachineInstr::copyFlagsFromInstruction(I: *SI);
1547
1548 for (unsigned i = 0; i < ResRegs.size(); ++i) {
1549 MIRBuilder.buildSelect(Res: ResRegs[i], Tst, Op0: Op0Regs[i], Op1: Op1Regs[i], Flags);
1550 }
1551
1552 return true;
1553}
1554
1555bool IRTranslator::translateCopy(const User &U, const Value &V,
1556 MachineIRBuilder &MIRBuilder) {
1557 Register Src = getOrCreateVReg(Val: V);
1558 auto &Regs = *VMap.getVRegs(V: U);
1559 if (Regs.empty()) {
1560 Regs.push_back(Elt: Src);
1561 VMap.getOffsets(V: U)->push_back(Elt: 0);
1562 } else {
1563 // If we already assigned a vreg for this instruction, we can't change that.
1564 // Emit a copy to satisfy the users we already emitted.
1565 MIRBuilder.buildCopy(Res: Regs[0], Op: Src);
1566 }
1567 return true;
1568}
1569
1570bool IRTranslator::translateBitCast(const User &U,
1571 MachineIRBuilder &MIRBuilder) {
1572 // If we're bitcasting to the source type, we can reuse the source vreg.
1573 if (getLLTForType(Ty&: *U.getOperand(i: 0)->getType(), DL: *DL) ==
1574 getLLTForType(Ty&: *U.getType(), DL: *DL)) {
1575 // If the source is a ConstantInt then it was probably created by
1576 // ConstantHoisting and we should leave it alone.
1577 if (isa<ConstantInt>(Val: U.getOperand(i: 0)))
1578 return translateCast(Opcode: TargetOpcode::G_CONSTANT_FOLD_BARRIER, U,
1579 MIRBuilder);
1580 return translateCopy(U, V: *U.getOperand(i: 0), MIRBuilder);
1581 }
1582
1583 return translateCast(Opcode: TargetOpcode::G_BITCAST, U, MIRBuilder);
1584}
1585
1586bool IRTranslator::translateCast(unsigned Opcode, const User &U,
1587 MachineIRBuilder &MIRBuilder) {
1588 if (containsBF16Type(U) && !targetSupportsBF16Type(MF))
1589 return false;
1590
1591 uint32_t Flags = 0;
1592 if (const Instruction *I = dyn_cast<Instruction>(Val: &U))
1593 Flags = MachineInstr::copyFlagsFromInstruction(I: *I);
1594
1595 Register Op = getOrCreateVReg(Val: *U.getOperand(i: 0));
1596 Register Res = getOrCreateVReg(Val: U);
1597 MIRBuilder.buildInstr(Opc: Opcode, DstOps: {Res}, SrcOps: {Op}, Flags);
1598 return true;
1599}
1600
1601bool IRTranslator::translateGetElementPtr(const User &U,
1602 MachineIRBuilder &MIRBuilder) {
1603 Value &Op0 = *U.getOperand(i: 0);
1604 Register BaseReg = getOrCreateVReg(Val: Op0);
1605 Type *PtrIRTy = Op0.getType();
1606 LLT PtrTy = getLLTForType(Ty&: *PtrIRTy, DL: *DL);
1607 Type *OffsetIRTy = DL->getIndexType(PtrTy: PtrIRTy);
1608 LLT OffsetTy = getLLTForType(Ty&: *OffsetIRTy, DL: *DL);
1609
1610 uint32_t PtrAddFlags = 0;
1611 // Each PtrAdd generated to implement the GEP inherits its nuw, nusw, inbounds
1612 // flags.
1613 if (const Instruction *I = dyn_cast<Instruction>(Val: &U))
1614 PtrAddFlags = MachineInstr::copyFlagsFromInstruction(I: *I);
1615
1616 auto PtrAddFlagsWithConst = [&](int64_t Offset) {
1617 // For nusw/inbounds GEP with an offset that is nonnegative when interpreted
1618 // as signed, assume there is no unsigned overflow.
1619 if (Offset >= 0 && (PtrAddFlags & MachineInstr::MIFlag::NoUSWrap))
1620 return PtrAddFlags | MachineInstr::MIFlag::NoUWrap;
1621 return PtrAddFlags;
1622 };
1623
1624 // Normalize Vector GEP - all scalar operands should be converted to the
1625 // splat vector.
1626 unsigned VectorWidth = 0;
1627
1628 // True if we should use a splat vector; using VectorWidth alone is not
1629 // sufficient.
1630 bool WantSplatVector = false;
1631 if (auto *VT = dyn_cast<VectorType>(Val: U.getType())) {
1632 VectorWidth = cast<FixedVectorType>(Val: VT)->getNumElements();
1633 // We don't produce 1 x N vectors; those are treated as scalars.
1634 WantSplatVector = VectorWidth > 1;
1635 }
1636
1637 // We might need to splat the base pointer into a vector if the offsets
1638 // are vectors.
1639 if (WantSplatVector && !PtrTy.isVector()) {
1640 BaseReg = MIRBuilder
1641 .buildSplatBuildVector(Res: LLT::fixed_vector(NumElements: VectorWidth, ScalarTy: PtrTy),
1642 Src: BaseReg)
1643 .getReg(Idx: 0);
1644 PtrIRTy = FixedVectorType::get(ElementType: PtrIRTy, NumElts: VectorWidth);
1645 PtrTy = getLLTForType(Ty&: *PtrIRTy, DL: *DL);
1646 OffsetIRTy = DL->getIndexType(PtrTy: PtrIRTy);
1647 OffsetTy = getLLTForType(Ty&: *OffsetIRTy, DL: *DL);
1648 }
1649
1650 int64_t Offset = 0;
1651 for (gep_type_iterator GTI = gep_type_begin(GEP: &U), E = gep_type_end(GEP: &U);
1652 GTI != E; ++GTI) {
1653 const Value *Idx = GTI.getOperand();
1654 if (StructType *StTy = GTI.getStructTypeOrNull()) {
1655 unsigned Field = cast<Constant>(Val: Idx)->getUniqueInteger().getZExtValue();
1656 Offset += DL->getStructLayout(Ty: StTy)->getElementOffset(Idx: Field);
1657 continue;
1658 } else {
1659 uint64_t ElementSize = GTI.getSequentialElementStride(DL: *DL);
1660
1661 // If this is a scalar constant or a splat vector of constants,
1662 // handle it quickly.
1663 if (const auto *CI = dyn_cast<ConstantInt>(Val: Idx)) {
1664 if (std::optional<int64_t> Val = CI->getValue().trySExtValue()) {
1665 Offset += ElementSize * *Val;
1666 continue;
1667 }
1668 }
1669
1670 if (Offset != 0) {
1671 auto OffsetMIB = MIRBuilder.buildConstant(Res: {OffsetTy}, Val: Offset);
1672 BaseReg = MIRBuilder
1673 .buildPtrAdd(Res: PtrTy, Op0: BaseReg, Op1: OffsetMIB.getReg(Idx: 0),
1674 Flags: PtrAddFlagsWithConst(Offset))
1675 .getReg(Idx: 0);
1676 Offset = 0;
1677 }
1678
1679 Register IdxReg = getOrCreateVReg(Val: *Idx);
1680 LLT IdxTy = MRI->getType(Reg: IdxReg);
1681 if (IdxTy != OffsetTy) {
1682 if (!IdxTy.isVector() && WantSplatVector) {
1683 IdxReg = MIRBuilder
1684 .buildSplatBuildVector(Res: OffsetTy.changeElementType(NewEltTy: IdxTy),
1685 Src: IdxReg)
1686 .getReg(Idx: 0);
1687 }
1688
1689 IdxReg = MIRBuilder.buildSExtOrTrunc(Res: OffsetTy, Op: IdxReg).getReg(Idx: 0);
1690 }
1691
1692 // N = N + Idx * ElementSize;
1693 // Avoid doing it for ElementSize of 1.
1694 Register GepOffsetReg;
1695 if (ElementSize != 1) {
1696 auto ElementSizeMIB = MIRBuilder.buildConstant(
1697 Res: getLLTForType(Ty&: *OffsetIRTy, DL: *DL), Val: ElementSize);
1698
1699 // The multiplication is NUW if the GEP is NUW and NSW if the GEP is
1700 // NUSW.
1701 uint32_t ScaleFlags = PtrAddFlags & MachineInstr::MIFlag::NoUWrap;
1702 if (PtrAddFlags & MachineInstr::MIFlag::NoUSWrap)
1703 ScaleFlags |= MachineInstr::MIFlag::NoSWrap;
1704
1705 GepOffsetReg =
1706 MIRBuilder.buildMul(Dst: OffsetTy, Src0: IdxReg, Src1: ElementSizeMIB, Flags: ScaleFlags)
1707 .getReg(Idx: 0);
1708 } else {
1709 GepOffsetReg = IdxReg;
1710 }
1711
1712 BaseReg =
1713 MIRBuilder.buildPtrAdd(Res: PtrTy, Op0: BaseReg, Op1: GepOffsetReg, Flags: PtrAddFlags)
1714 .getReg(Idx: 0);
1715 }
1716 }
1717
1718 if (Offset != 0) {
1719 auto OffsetMIB =
1720 MIRBuilder.buildConstant(Res: OffsetTy, Val: Offset);
1721
1722 MIRBuilder.buildPtrAdd(Res: getOrCreateVReg(Val: U), Op0: BaseReg, Op1: OffsetMIB.getReg(Idx: 0),
1723 Flags: PtrAddFlagsWithConst(Offset));
1724 return true;
1725 }
1726
1727 MIRBuilder.buildCopy(Res: getOrCreateVReg(Val: U), Op: BaseReg);
1728 return true;
1729}
1730
1731bool IRTranslator::translateMemFunc(const CallInst &CI,
1732 MachineIRBuilder &MIRBuilder,
1733 unsigned Opcode) {
1734 const Value *SrcPtr = CI.getArgOperand(i: 1);
1735 // If the source is undef, then just emit a nop.
1736 if (isa<UndefValue>(Val: SrcPtr))
1737 return true;
1738
1739 SmallVector<Register, 3> SrcRegs;
1740
1741 unsigned MinPtrSize = UINT_MAX;
1742 for (auto AI = CI.arg_begin(), AE = CI.arg_end(); std::next(x: AI) != AE; ++AI) {
1743 Register SrcReg = getOrCreateVReg(Val: **AI);
1744 LLT SrcTy = MRI->getType(Reg: SrcReg);
1745 if (SrcTy.isPointer())
1746 MinPtrSize = std::min<unsigned>(a: SrcTy.getSizeInBits(), b: MinPtrSize);
1747 SrcRegs.push_back(Elt: SrcReg);
1748 }
1749
1750 LLT SizeTy = LLT::scalar(SizeInBits: MinPtrSize);
1751
1752 // The size operand should be the minimum of the pointer sizes.
1753 Register &SizeOpReg = SrcRegs[SrcRegs.size() - 1];
1754 if (MRI->getType(Reg: SizeOpReg) != SizeTy)
1755 SizeOpReg = MIRBuilder.buildZExtOrTrunc(Res: SizeTy, Op: SizeOpReg).getReg(Idx: 0);
1756
1757 auto ICall = MIRBuilder.buildInstr(Opcode);
1758 for (Register SrcReg : SrcRegs)
1759 ICall.addUse(RegNo: SrcReg);
1760
1761 Align DstAlign;
1762 Align SrcAlign;
1763 unsigned IsVol =
1764 cast<ConstantInt>(Val: CI.getArgOperand(i: CI.arg_size() - 1))->getZExtValue();
1765
1766 ConstantInt *CopySize = nullptr;
1767
1768 if (auto *MCI = dyn_cast<MemCpyInst>(Val: &CI)) {
1769 DstAlign = MCI->getDestAlign().valueOrOne();
1770 SrcAlign = MCI->getSourceAlign().valueOrOne();
1771 CopySize = dyn_cast<ConstantInt>(Val: MCI->getArgOperand(i: 2));
1772 } else if (auto *MMI = dyn_cast<MemMoveInst>(Val: &CI)) {
1773 DstAlign = MMI->getDestAlign().valueOrOne();
1774 SrcAlign = MMI->getSourceAlign().valueOrOne();
1775 CopySize = dyn_cast<ConstantInt>(Val: MMI->getArgOperand(i: 2));
1776 } else {
1777 auto *MSI = cast<MemSetInst>(Val: &CI);
1778 DstAlign = MSI->getDestAlign().valueOrOne();
1779 }
1780
1781 if (Opcode != TargetOpcode::G_MEMCPY_INLINE) {
1782 // We need to propagate the tail call flag from the IR inst as an argument.
1783 // Otherwise, we have to pessimize and assume later that we cannot tail call
1784 // any memory intrinsics.
1785 ICall.addImm(Val: CI.isTailCall() ? 1 : 0);
1786 }
1787
1788 // Create mem operands to store the alignment and volatile info.
1789 MachineMemOperand::Flags LoadFlags = MachineMemOperand::MOLoad;
1790 MachineMemOperand::Flags StoreFlags = MachineMemOperand::MOStore;
1791 if (IsVol) {
1792 LoadFlags |= MachineMemOperand::MOVolatile;
1793 StoreFlags |= MachineMemOperand::MOVolatile;
1794 }
1795
1796 AAMDNodes AAInfo = CI.getAAMetadata();
1797 if (AA && CopySize &&
1798 AA->pointsToConstantMemory(Loc: MemoryLocation(
1799 SrcPtr, LocationSize::precise(Value: CopySize->getZExtValue()), AAInfo))) {
1800 LoadFlags |= MachineMemOperand::MOInvariant;
1801
1802 // FIXME: pointsToConstantMemory probably does not imply dereferenceable,
1803 // but the previous usage implied it did. Probably should check
1804 // isDereferenceableAndAlignedPointer.
1805 LoadFlags |= MachineMemOperand::MODereferenceable;
1806 }
1807
1808 ICall.addMemOperand(
1809 MMO: MF->getMachineMemOperand(PtrInfo: MachinePointerInfo(CI.getArgOperand(i: 0)),
1810 F: StoreFlags, Size: 1, BaseAlignment: DstAlign, AAInfo));
1811 if (Opcode != TargetOpcode::G_MEMSET)
1812 ICall.addMemOperand(MMO: MF->getMachineMemOperand(
1813 PtrInfo: MachinePointerInfo(SrcPtr), F: LoadFlags, Size: 1, BaseAlignment: SrcAlign, AAInfo));
1814
1815 return true;
1816}
1817
1818bool IRTranslator::translateTrap(const CallInst &CI,
1819 MachineIRBuilder &MIRBuilder,
1820 unsigned Opcode) {
1821 StringRef TrapFuncName =
1822 CI.getAttributes().getFnAttr(Kind: "trap-func-name").getValueAsString();
1823 if (TrapFuncName.empty()) {
1824 if (Opcode == TargetOpcode::G_UBSANTRAP) {
1825 uint64_t Code = cast<ConstantInt>(Val: CI.getOperand(i_nocapture: 0))->getZExtValue();
1826 MIRBuilder.buildInstr(Opc: Opcode, DstOps: {}, SrcOps: ArrayRef<llvm::SrcOp>{Code});
1827 } else {
1828 MIRBuilder.buildInstr(Opcode);
1829 }
1830 return true;
1831 }
1832
1833 CallLowering::CallLoweringInfo Info;
1834 if (Opcode == TargetOpcode::G_UBSANTRAP)
1835 Info.OrigArgs.push_back(Elt: {getOrCreateVRegs(Val: *CI.getArgOperand(i: 0)),
1836 CI.getArgOperand(i: 0)->getType(), 0});
1837
1838 Info.Callee = MachineOperand::CreateES(SymName: TrapFuncName.data());
1839 Info.CB = &CI;
1840 Info.OrigRet = {Register(), Type::getVoidTy(C&: CI.getContext()), 0};
1841 return CLI->lowerCall(MIRBuilder, Info);
1842}
1843
1844bool IRTranslator::translateVectorInterleave2Intrinsic(
1845 const CallInst &CI, MachineIRBuilder &MIRBuilder) {
1846 assert(CI.getIntrinsicID() == Intrinsic::vector_interleave2 &&
1847 "This function can only be called on the interleave2 intrinsic!");
1848 // Canonicalize interleave2 to G_SHUFFLE_VECTOR (similar to SelectionDAG).
1849 Register Op0 = getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 0));
1850 Register Op1 = getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 1));
1851 Register Res = getOrCreateVReg(Val: CI);
1852
1853 LLT OpTy = MRI->getType(Reg: Op0);
1854 MIRBuilder.buildShuffleVector(Res, Src1: Op0, Src2: Op1,
1855 Mask: createInterleaveMask(VF: OpTy.getNumElements(), NumVecs: 2));
1856
1857 return true;
1858}
1859
1860bool IRTranslator::translateVectorDeinterleave2Intrinsic(
1861 const CallInst &CI, MachineIRBuilder &MIRBuilder) {
1862 assert(CI.getIntrinsicID() == Intrinsic::vector_deinterleave2 &&
1863 "This function can only be called on the deinterleave2 intrinsic!");
1864 // Canonicalize deinterleave2 to shuffles that extract sub-vectors (similar to
1865 // SelectionDAG).
1866 Register Op = getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 0));
1867 auto Undef = MIRBuilder.buildUndef(Res: MRI->getType(Reg: Op));
1868 ArrayRef<Register> Res = getOrCreateVRegs(Val: CI);
1869
1870 LLT ResTy = MRI->getType(Reg: Res[0]);
1871 MIRBuilder.buildShuffleVector(Res: Res[0], Src1: Op, Src2: Undef,
1872 Mask: createStrideMask(Start: 0, Stride: 2, VF: ResTy.getNumElements()));
1873 MIRBuilder.buildShuffleVector(Res: Res[1], Src1: Op, Src2: Undef,
1874 Mask: createStrideMask(Start: 1, Stride: 2, VF: ResTy.getNumElements()));
1875
1876 return true;
1877}
1878
1879void IRTranslator::getStackGuard(Register DstReg,
1880 MachineIRBuilder &MIRBuilder) {
1881 Value *Global =
1882 TLI->getSDagStackGuard(M: *MF->getFunction().getParent(), Libcalls: *Libcalls);
1883 if (!Global) {
1884 LLVMContext &Ctx = MIRBuilder.getContext();
1885 Ctx.diagnose(DI: DiagnosticInfoGeneric("unable to lower stackguard"));
1886 MIRBuilder.buildUndef(Res: DstReg);
1887 return;
1888 }
1889
1890 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1891 MRI->setRegClass(Reg: DstReg, RC: TRI->getPointerRegClass());
1892 auto MIB =
1893 MIRBuilder.buildInstr(Opc: TargetOpcode::LOAD_STACK_GUARD, DstOps: {DstReg}, SrcOps: {});
1894
1895 unsigned AddrSpace = Global->getType()->getPointerAddressSpace();
1896 LLT PtrTy = LLT::pointer(AddressSpace: AddrSpace, SizeInBits: DL->getPointerSizeInBits(AS: AddrSpace));
1897
1898 MachinePointerInfo MPInfo(Global);
1899 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
1900 MachineMemOperand::MODereferenceable;
1901 MachineMemOperand *MemRef = MF->getMachineMemOperand(
1902 PtrInfo: MPInfo, f: Flags, MemTy: PtrTy, base_alignment: DL->getPointerABIAlignment(AS: AddrSpace));
1903 MIB.setMemRefs({MemRef});
1904}
1905
1906bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
1907 MachineIRBuilder &MIRBuilder) {
1908 ArrayRef<Register> ResRegs = getOrCreateVRegs(Val: CI);
1909 MIRBuilder.buildInstr(
1910 Opc: Op, DstOps: {ResRegs[0], ResRegs[1]},
1911 SrcOps: {getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 0)), getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 1))});
1912
1913 return true;
1914}
1915
1916bool IRTranslator::translateFixedPointIntrinsic(unsigned Op, const CallInst &CI,
1917 MachineIRBuilder &MIRBuilder) {
1918 Register Dst = getOrCreateVReg(Val: CI);
1919 Register Src0 = getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 0));
1920 Register Src1 = getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 1));
1921 uint64_t Scale = cast<ConstantInt>(Val: CI.getOperand(i_nocapture: 2))->getZExtValue();
1922 MIRBuilder.buildInstr(Opc: Op, DstOps: {Dst}, SrcOps: { Src0, Src1, Scale });
1923 return true;
1924}
1925
1926unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
1927 switch (ID) {
1928 default:
1929 break;
1930 case Intrinsic::acos:
1931 return TargetOpcode::G_FACOS;
1932 case Intrinsic::asin:
1933 return TargetOpcode::G_FASIN;
1934 case Intrinsic::atan:
1935 return TargetOpcode::G_FATAN;
1936 case Intrinsic::atan2:
1937 return TargetOpcode::G_FATAN2;
1938 case Intrinsic::bswap:
1939 return TargetOpcode::G_BSWAP;
1940 case Intrinsic::bitreverse:
1941 return TargetOpcode::G_BITREVERSE;
1942 case Intrinsic::fshl:
1943 return TargetOpcode::G_FSHL;
1944 case Intrinsic::fshr:
1945 return TargetOpcode::G_FSHR;
1946 case Intrinsic::ceil:
1947 return TargetOpcode::G_FCEIL;
1948 case Intrinsic::cos:
1949 return TargetOpcode::G_FCOS;
1950 case Intrinsic::cosh:
1951 return TargetOpcode::G_FCOSH;
1952 case Intrinsic::ctpop:
1953 return TargetOpcode::G_CTPOP;
1954 case Intrinsic::exp:
1955 return TargetOpcode::G_FEXP;
1956 case Intrinsic::exp2:
1957 return TargetOpcode::G_FEXP2;
1958 case Intrinsic::exp10:
1959 return TargetOpcode::G_FEXP10;
1960 case Intrinsic::fabs:
1961 return TargetOpcode::G_FABS;
1962 case Intrinsic::copysign:
1963 return TargetOpcode::G_FCOPYSIGN;
1964 case Intrinsic::minnum:
1965 return TargetOpcode::G_FMINNUM;
1966 case Intrinsic::maxnum:
1967 return TargetOpcode::G_FMAXNUM;
1968 case Intrinsic::minimum:
1969 return TargetOpcode::G_FMINIMUM;
1970 case Intrinsic::maximum:
1971 return TargetOpcode::G_FMAXIMUM;
1972 case Intrinsic::minimumnum:
1973 return TargetOpcode::G_FMINIMUMNUM;
1974 case Intrinsic::maximumnum:
1975 return TargetOpcode::G_FMAXIMUMNUM;
1976 case Intrinsic::canonicalize:
1977 return TargetOpcode::G_FCANONICALIZE;
1978 case Intrinsic::floor:
1979 return TargetOpcode::G_FFLOOR;
1980 case Intrinsic::fma:
1981 return TargetOpcode::G_FMA;
1982 case Intrinsic::log:
1983 return TargetOpcode::G_FLOG;
1984 case Intrinsic::log2:
1985 return TargetOpcode::G_FLOG2;
1986 case Intrinsic::log10:
1987 return TargetOpcode::G_FLOG10;
1988 case Intrinsic::ldexp:
1989 return TargetOpcode::G_FLDEXP;
1990 case Intrinsic::nearbyint:
1991 return TargetOpcode::G_FNEARBYINT;
1992 case Intrinsic::pow:
1993 return TargetOpcode::G_FPOW;
1994 case Intrinsic::powi:
1995 return TargetOpcode::G_FPOWI;
1996 case Intrinsic::rint:
1997 return TargetOpcode::G_FRINT;
1998 case Intrinsic::round:
1999 return TargetOpcode::G_INTRINSIC_ROUND;
2000 case Intrinsic::roundeven:
2001 return TargetOpcode::G_INTRINSIC_ROUNDEVEN;
2002 case Intrinsic::sin:
2003 return TargetOpcode::G_FSIN;
2004 case Intrinsic::sinh:
2005 return TargetOpcode::G_FSINH;
2006 case Intrinsic::sqrt:
2007 return TargetOpcode::G_FSQRT;
2008 case Intrinsic::tan:
2009 return TargetOpcode::G_FTAN;
2010 case Intrinsic::tanh:
2011 return TargetOpcode::G_FTANH;
2012 case Intrinsic::trunc:
2013 return TargetOpcode::G_INTRINSIC_TRUNC;
2014 case Intrinsic::readcyclecounter:
2015 return TargetOpcode::G_READCYCLECOUNTER;
2016 case Intrinsic::readsteadycounter:
2017 return TargetOpcode::G_READSTEADYCOUNTER;
2018 case Intrinsic::ptrmask:
2019 return TargetOpcode::G_PTRMASK;
2020 case Intrinsic::lrint:
2021 return TargetOpcode::G_INTRINSIC_LRINT;
2022 case Intrinsic::llrint:
2023 return TargetOpcode::G_INTRINSIC_LLRINT;
2024 // FADD/FMUL require checking the FMF, so are handled elsewhere.
2025 case Intrinsic::vector_reduce_fmin:
2026 return TargetOpcode::G_VECREDUCE_FMIN;
2027 case Intrinsic::vector_reduce_fmax:
2028 return TargetOpcode::G_VECREDUCE_FMAX;
2029 case Intrinsic::vector_reduce_fminimum:
2030 return TargetOpcode::G_VECREDUCE_FMINIMUM;
2031 case Intrinsic::vector_reduce_fmaximum:
2032 return TargetOpcode::G_VECREDUCE_FMAXIMUM;
2033 case Intrinsic::vector_reduce_add:
2034 return TargetOpcode::G_VECREDUCE_ADD;
2035 case Intrinsic::vector_reduce_mul:
2036 return TargetOpcode::G_VECREDUCE_MUL;
2037 case Intrinsic::vector_reduce_and:
2038 return TargetOpcode::G_VECREDUCE_AND;
2039 case Intrinsic::vector_reduce_or:
2040 return TargetOpcode::G_VECREDUCE_OR;
2041 case Intrinsic::vector_reduce_xor:
2042 return TargetOpcode::G_VECREDUCE_XOR;
2043 case Intrinsic::vector_reduce_smax:
2044 return TargetOpcode::G_VECREDUCE_SMAX;
2045 case Intrinsic::vector_reduce_smin:
2046 return TargetOpcode::G_VECREDUCE_SMIN;
2047 case Intrinsic::vector_reduce_umax:
2048 return TargetOpcode::G_VECREDUCE_UMAX;
2049 case Intrinsic::vector_reduce_umin:
2050 return TargetOpcode::G_VECREDUCE_UMIN;
2051 case Intrinsic::experimental_vector_compress:
2052 return TargetOpcode::G_VECTOR_COMPRESS;
2053 case Intrinsic::lround:
2054 return TargetOpcode::G_LROUND;
2055 case Intrinsic::llround:
2056 return TargetOpcode::G_LLROUND;
2057 case Intrinsic::get_fpenv:
2058 return TargetOpcode::G_GET_FPENV;
2059 case Intrinsic::get_fpmode:
2060 return TargetOpcode::G_GET_FPMODE;
2061 }
2062 return Intrinsic::not_intrinsic;
2063}
2064
2065bool IRTranslator::translateSimpleIntrinsic(const CallInst &CI,
2066 Intrinsic::ID ID,
2067 MachineIRBuilder &MIRBuilder) {
2068
2069 unsigned Op = getSimpleIntrinsicOpcode(ID);
2070
2071 // Is this a simple intrinsic?
2072 if (Op == Intrinsic::not_intrinsic)
2073 return false;
2074
2075 // Yes. Let's translate it.
2076 SmallVector<llvm::SrcOp, 4> VRegs;
2077 for (const auto &Arg : CI.args())
2078 VRegs.push_back(Elt: getOrCreateVReg(Val: *Arg));
2079
2080 MIRBuilder.buildInstr(Opc: Op, DstOps: {getOrCreateVReg(Val: CI)}, SrcOps: VRegs,
2081 Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2082 return true;
2083}
2084
2085// TODO: Include ConstainedOps.def when all strict instructions are defined.
2086static unsigned getConstrainedOpcode(Intrinsic::ID ID) {
2087 switch (ID) {
2088 case Intrinsic::experimental_constrained_fadd:
2089 return TargetOpcode::G_STRICT_FADD;
2090 case Intrinsic::experimental_constrained_fsub:
2091 return TargetOpcode::G_STRICT_FSUB;
2092 case Intrinsic::experimental_constrained_fmul:
2093 return TargetOpcode::G_STRICT_FMUL;
2094 case Intrinsic::experimental_constrained_fdiv:
2095 return TargetOpcode::G_STRICT_FDIV;
2096 case Intrinsic::experimental_constrained_frem:
2097 return TargetOpcode::G_STRICT_FREM;
2098 case Intrinsic::experimental_constrained_fma:
2099 return TargetOpcode::G_STRICT_FMA;
2100 case Intrinsic::experimental_constrained_sqrt:
2101 return TargetOpcode::G_STRICT_FSQRT;
2102 case Intrinsic::experimental_constrained_ldexp:
2103 return TargetOpcode::G_STRICT_FLDEXP;
2104 default:
2105 return 0;
2106 }
2107}
2108
2109bool IRTranslator::translateConstrainedFPIntrinsic(
2110 const ConstrainedFPIntrinsic &FPI, MachineIRBuilder &MIRBuilder) {
2111 fp::ExceptionBehavior EB = *FPI.getExceptionBehavior();
2112
2113 unsigned Opcode = getConstrainedOpcode(ID: FPI.getIntrinsicID());
2114 if (!Opcode)
2115 return false;
2116
2117 uint32_t Flags = MachineInstr::copyFlagsFromInstruction(I: FPI);
2118 if (EB == fp::ExceptionBehavior::ebIgnore)
2119 Flags |= MachineInstr::NoFPExcept;
2120
2121 SmallVector<llvm::SrcOp, 4> VRegs;
2122 for (unsigned I = 0, E = FPI.getNonMetadataArgCount(); I != E; ++I)
2123 VRegs.push_back(Elt: getOrCreateVReg(Val: *FPI.getArgOperand(i: I)));
2124
2125 MIRBuilder.buildInstr(Opc: Opcode, DstOps: {getOrCreateVReg(Val: FPI)}, SrcOps: VRegs, Flags);
2126 return true;
2127}
2128
2129std::optional<MCRegister> IRTranslator::getArgPhysReg(Argument &Arg) {
2130 auto VRegs = getOrCreateVRegs(Val: Arg);
2131 if (VRegs.size() != 1)
2132 return std::nullopt;
2133
2134 // Arguments are lowered as a copy of a livein physical register.
2135 auto *VRegDef = MF->getRegInfo().getVRegDef(Reg: VRegs[0]);
2136 if (!VRegDef || !VRegDef->isCopy())
2137 return std::nullopt;
2138 return VRegDef->getOperand(i: 1).getReg().asMCReg();
2139}
2140
2141bool IRTranslator::translateIfEntryValueArgument(bool isDeclare, Value *Val,
2142 const DILocalVariable *Var,
2143 const DIExpression *Expr,
2144 const DebugLoc &DL,
2145 MachineIRBuilder &MIRBuilder) {
2146 auto *Arg = dyn_cast<Argument>(Val);
2147 if (!Arg)
2148 return false;
2149
2150 if (!Expr->isEntryValue())
2151 return false;
2152
2153 std::optional<MCRegister> PhysReg = getArgPhysReg(Arg&: *Arg);
2154 if (!PhysReg) {
2155 LLVM_DEBUG(dbgs() << "Dropping dbg." << (isDeclare ? "declare" : "value")
2156 << ": expression is entry_value but "
2157 << "couldn't find a physical register\n");
2158 LLVM_DEBUG(dbgs() << *Var << "\n");
2159 return true;
2160 }
2161
2162 if (isDeclare) {
2163 // Append an op deref to account for the fact that this is a dbg_declare.
2164 Expr = DIExpression::append(Expr, Ops: dwarf::DW_OP_deref);
2165 MF->setVariableDbgInfo(Var, Expr, Reg: *PhysReg, Loc: DL);
2166 } else {
2167 MIRBuilder.buildDirectDbgValue(Reg: *PhysReg, Variable: Var, Expr);
2168 }
2169
2170 return true;
2171}
2172
2173static unsigned getConvOpcode(Intrinsic::ID ID) {
2174 switch (ID) {
2175 default:
2176 llvm_unreachable("Unexpected intrinsic");
2177 case Intrinsic::experimental_convergence_anchor:
2178 return TargetOpcode::CONVERGENCECTRL_ANCHOR;
2179 case Intrinsic::experimental_convergence_entry:
2180 return TargetOpcode::CONVERGENCECTRL_ENTRY;
2181 case Intrinsic::experimental_convergence_loop:
2182 return TargetOpcode::CONVERGENCECTRL_LOOP;
2183 }
2184}
2185
2186bool IRTranslator::translateConvergenceControlIntrinsic(
2187 const CallInst &CI, Intrinsic::ID ID, MachineIRBuilder &MIRBuilder) {
2188 MachineInstrBuilder MIB = MIRBuilder.buildInstr(Opcode: getConvOpcode(ID));
2189 Register OutputReg = getOrCreateConvergenceTokenVReg(Token: CI);
2190 MIB.addDef(RegNo: OutputReg);
2191
2192 if (ID == Intrinsic::experimental_convergence_loop) {
2193 auto Bundle = CI.getOperandBundle(ID: LLVMContext::OB_convergencectrl);
2194 assert(Bundle && "Expected a convergence control token.");
2195 Register InputReg =
2196 getOrCreateConvergenceTokenVReg(Token: *Bundle->Inputs[0].get());
2197 MIB.addUse(RegNo: InputReg);
2198 }
2199
2200 return true;
2201}
2202
2203bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
2204 MachineIRBuilder &MIRBuilder) {
2205 if (auto *MI = dyn_cast<AnyMemIntrinsic>(Val: &CI)) {
2206 if (ORE->enabled()) {
2207 if (MemoryOpRemark::canHandle(I: MI, TLI: *LibInfo)) {
2208 MemoryOpRemark R(*ORE, "gisel-irtranslator-memsize", *DL, *LibInfo);
2209 R.visit(I: MI);
2210 }
2211 }
2212 }
2213
2214 // If this is a simple intrinsic (that is, we just need to add a def of
2215 // a vreg, and uses for each arg operand, then translate it.
2216 if (translateSimpleIntrinsic(CI, ID, MIRBuilder))
2217 return true;
2218
2219 switch (ID) {
2220 default:
2221 break;
2222 case Intrinsic::lifetime_start:
2223 case Intrinsic::lifetime_end: {
2224 // No stack colouring in O0, discard region information.
2225 if (MF->getTarget().getOptLevel() == CodeGenOptLevel::None ||
2226 MF->getFunction().hasOptNone())
2227 return true;
2228
2229 unsigned Op = ID == Intrinsic::lifetime_start ? TargetOpcode::LIFETIME_START
2230 : TargetOpcode::LIFETIME_END;
2231
2232 const AllocaInst *AI = dyn_cast<AllocaInst>(Val: CI.getArgOperand(i: 0));
2233 if (!AI || !AI->isStaticAlloca())
2234 return true;
2235
2236 MIRBuilder.buildInstr(Opcode: Op).addFrameIndex(Idx: getOrCreateFrameIndex(AI: *AI));
2237 return true;
2238 }
2239 case Intrinsic::fake_use: {
2240 SmallVector<llvm::SrcOp, 4> VRegs;
2241 for (const auto &Arg : CI.args())
2242 llvm::append_range(C&: VRegs, R: getOrCreateVRegs(Val: *Arg));
2243 MIRBuilder.buildInstr(Opc: TargetOpcode::FAKE_USE, DstOps: {}, SrcOps: VRegs);
2244 MF->setHasFakeUses(true);
2245 return true;
2246 }
2247 case Intrinsic::dbg_declare: {
2248 const DbgDeclareInst &DI = cast<DbgDeclareInst>(Val: CI);
2249 assert(DI.getVariable() && "Missing variable");
2250 translateDbgDeclareRecord(Address: DI.getAddress(), HasArgList: DI.hasArgList(), Variable: DI.getVariable(),
2251 Expression: DI.getExpression(), DL: DI.getDebugLoc(), MIRBuilder);
2252 return true;
2253 }
2254 case Intrinsic::dbg_label: {
2255 const DbgLabelInst &DI = cast<DbgLabelInst>(Val: CI);
2256 assert(DI.getLabel() && "Missing label");
2257
2258 assert(DI.getLabel()->isValidLocationForIntrinsic(
2259 MIRBuilder.getDebugLoc()) &&
2260 "Expected inlined-at fields to agree");
2261
2262 MIRBuilder.buildDbgLabel(Label: DI.getLabel());
2263 return true;
2264 }
2265 case Intrinsic::vaend:
2266 // No target I know of cares about va_end. Certainly no in-tree target
2267 // does. Simplest intrinsic ever!
2268 return true;
2269 case Intrinsic::vastart: {
2270 Value *Ptr = CI.getArgOperand(i: 0);
2271 unsigned ListSize = TLI->getVaListSizeInBits(DL: *DL) / 8;
2272 Align Alignment = getKnownAlignment(V: Ptr, DL: *DL);
2273
2274 MIRBuilder.buildInstr(Opc: TargetOpcode::G_VASTART, DstOps: {}, SrcOps: {getOrCreateVReg(Val: *Ptr)})
2275 .addMemOperand(MMO: MF->getMachineMemOperand(PtrInfo: MachinePointerInfo(Ptr),
2276 F: MachineMemOperand::MOStore,
2277 Size: ListSize, BaseAlignment: Alignment));
2278 return true;
2279 }
2280 case Intrinsic::dbg_assign:
2281 // A dbg.assign is a dbg.value with more information about stack locations,
2282 // typically produced during optimisation of variables with leaked
2283 // addresses. We can treat it like a normal dbg_value intrinsic here; to
2284 // benefit from the full analysis of stack/SSA locations, GlobalISel would
2285 // need to register for and use the AssignmentTrackingAnalysis pass.
2286 [[fallthrough]];
2287 case Intrinsic::dbg_value: {
2288 // This form of DBG_VALUE is target-independent.
2289 const DbgValueInst &DI = cast<DbgValueInst>(Val: CI);
2290 translateDbgValueRecord(V: DI.getValue(), HasArgList: DI.hasArgList(), Variable: DI.getVariable(),
2291 Expression: DI.getExpression(), DL: DI.getDebugLoc(), MIRBuilder);
2292 return true;
2293 }
2294 case Intrinsic::uadd_with_overflow:
2295 return translateOverflowIntrinsic(CI, Op: TargetOpcode::G_UADDO, MIRBuilder);
2296 case Intrinsic::sadd_with_overflow:
2297 return translateOverflowIntrinsic(CI, Op: TargetOpcode::G_SADDO, MIRBuilder);
2298 case Intrinsic::usub_with_overflow:
2299 return translateOverflowIntrinsic(CI, Op: TargetOpcode::G_USUBO, MIRBuilder);
2300 case Intrinsic::ssub_with_overflow:
2301 return translateOverflowIntrinsic(CI, Op: TargetOpcode::G_SSUBO, MIRBuilder);
2302 case Intrinsic::umul_with_overflow:
2303 return translateOverflowIntrinsic(CI, Op: TargetOpcode::G_UMULO, MIRBuilder);
2304 case Intrinsic::smul_with_overflow:
2305 return translateOverflowIntrinsic(CI, Op: TargetOpcode::G_SMULO, MIRBuilder);
2306 case Intrinsic::uadd_sat:
2307 return translateBinaryOp(Opcode: TargetOpcode::G_UADDSAT, U: CI, MIRBuilder);
2308 case Intrinsic::sadd_sat:
2309 return translateBinaryOp(Opcode: TargetOpcode::G_SADDSAT, U: CI, MIRBuilder);
2310 case Intrinsic::usub_sat:
2311 return translateBinaryOp(Opcode: TargetOpcode::G_USUBSAT, U: CI, MIRBuilder);
2312 case Intrinsic::ssub_sat:
2313 return translateBinaryOp(Opcode: TargetOpcode::G_SSUBSAT, U: CI, MIRBuilder);
2314 case Intrinsic::ushl_sat:
2315 return translateBinaryOp(Opcode: TargetOpcode::G_USHLSAT, U: CI, MIRBuilder);
2316 case Intrinsic::sshl_sat:
2317 return translateBinaryOp(Opcode: TargetOpcode::G_SSHLSAT, U: CI, MIRBuilder);
2318 case Intrinsic::umin:
2319 return translateBinaryOp(Opcode: TargetOpcode::G_UMIN, U: CI, MIRBuilder);
2320 case Intrinsic::umax:
2321 return translateBinaryOp(Opcode: TargetOpcode::G_UMAX, U: CI, MIRBuilder);
2322 case Intrinsic::smin:
2323 return translateBinaryOp(Opcode: TargetOpcode::G_SMIN, U: CI, MIRBuilder);
2324 case Intrinsic::smax:
2325 return translateBinaryOp(Opcode: TargetOpcode::G_SMAX, U: CI, MIRBuilder);
2326 case Intrinsic::abs:
2327 // TODO: Preserve "int min is poison" arg in GMIR?
2328 return translateUnaryOp(Opcode: TargetOpcode::G_ABS, U: CI, MIRBuilder);
2329 case Intrinsic::smul_fix:
2330 return translateFixedPointIntrinsic(Op: TargetOpcode::G_SMULFIX, CI, MIRBuilder);
2331 case Intrinsic::umul_fix:
2332 return translateFixedPointIntrinsic(Op: TargetOpcode::G_UMULFIX, CI, MIRBuilder);
2333 case Intrinsic::smul_fix_sat:
2334 return translateFixedPointIntrinsic(Op: TargetOpcode::G_SMULFIXSAT, CI, MIRBuilder);
2335 case Intrinsic::umul_fix_sat:
2336 return translateFixedPointIntrinsic(Op: TargetOpcode::G_UMULFIXSAT, CI, MIRBuilder);
2337 case Intrinsic::sdiv_fix:
2338 return translateFixedPointIntrinsic(Op: TargetOpcode::G_SDIVFIX, CI, MIRBuilder);
2339 case Intrinsic::udiv_fix:
2340 return translateFixedPointIntrinsic(Op: TargetOpcode::G_UDIVFIX, CI, MIRBuilder);
2341 case Intrinsic::sdiv_fix_sat:
2342 return translateFixedPointIntrinsic(Op: TargetOpcode::G_SDIVFIXSAT, CI, MIRBuilder);
2343 case Intrinsic::udiv_fix_sat:
2344 return translateFixedPointIntrinsic(Op: TargetOpcode::G_UDIVFIXSAT, CI, MIRBuilder);
2345 case Intrinsic::fmuladd: {
2346 const TargetMachine &TM = MF->getTarget();
2347 Register Dst = getOrCreateVReg(Val: CI);
2348 Register Op0 = getOrCreateVReg(Val: *CI.getArgOperand(i: 0));
2349 Register Op1 = getOrCreateVReg(Val: *CI.getArgOperand(i: 1));
2350 Register Op2 = getOrCreateVReg(Val: *CI.getArgOperand(i: 2));
2351 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
2352 TLI->isFMAFasterThanFMulAndFAdd(MF: *MF,
2353 TLI->getValueType(DL: *DL, Ty: CI.getType()))) {
2354 // TODO: Revisit this to see if we should move this part of the
2355 // lowering to the combiner.
2356 MIRBuilder.buildFMA(Dst, Src0: Op0, Src1: Op1, Src2: Op2,
2357 Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2358 } else {
2359 LLT Ty = getLLTForType(Ty&: *CI.getType(), DL: *DL);
2360 auto FMul = MIRBuilder.buildFMul(
2361 Dst: Ty, Src0: Op0, Src1: Op1, Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2362 MIRBuilder.buildFAdd(Dst, Src0: FMul, Src1: Op2,
2363 Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2364 }
2365 return true;
2366 }
2367 case Intrinsic::frexp: {
2368 ArrayRef<Register> VRegs = getOrCreateVRegs(Val: CI);
2369 MIRBuilder.buildFFrexp(Fract: VRegs[0], Exp: VRegs[1],
2370 Src: getOrCreateVReg(Val: *CI.getArgOperand(i: 0)),
2371 Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2372 return true;
2373 }
2374 case Intrinsic::modf: {
2375 ArrayRef<Register> VRegs = getOrCreateVRegs(Val: CI);
2376 MIRBuilder.buildModf(Fract: VRegs[0], Int: VRegs[1],
2377 Src: getOrCreateVReg(Val: *CI.getArgOperand(i: 0)),
2378 Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2379 return true;
2380 }
2381 case Intrinsic::sincos: {
2382 ArrayRef<Register> VRegs = getOrCreateVRegs(Val: CI);
2383 MIRBuilder.buildFSincos(Sin: VRegs[0], Cos: VRegs[1],
2384 Src: getOrCreateVReg(Val: *CI.getArgOperand(i: 0)),
2385 Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2386 return true;
2387 }
2388 case Intrinsic::fptosi_sat:
2389 MIRBuilder.buildFPTOSI_SAT(Dst: getOrCreateVReg(Val: CI),
2390 Src0: getOrCreateVReg(Val: *CI.getArgOperand(i: 0)));
2391 return true;
2392 case Intrinsic::fptoui_sat:
2393 MIRBuilder.buildFPTOUI_SAT(Dst: getOrCreateVReg(Val: CI),
2394 Src0: getOrCreateVReg(Val: *CI.getArgOperand(i: 0)));
2395 return true;
2396 case Intrinsic::memcpy_inline:
2397 return translateMemFunc(CI, MIRBuilder, Opcode: TargetOpcode::G_MEMCPY_INLINE);
2398 case Intrinsic::memcpy:
2399 return translateMemFunc(CI, MIRBuilder, Opcode: TargetOpcode::G_MEMCPY);
2400 case Intrinsic::memmove:
2401 return translateMemFunc(CI, MIRBuilder, Opcode: TargetOpcode::G_MEMMOVE);
2402 case Intrinsic::memset:
2403 return translateMemFunc(CI, MIRBuilder, Opcode: TargetOpcode::G_MEMSET);
2404 case Intrinsic::eh_typeid_for: {
2405 GlobalValue *GV = ExtractTypeInfo(V: CI.getArgOperand(i: 0));
2406 Register Reg = getOrCreateVReg(Val: CI);
2407 unsigned TypeID = MF->getTypeIDFor(TI: GV);
2408 MIRBuilder.buildConstant(Res: Reg, Val: TypeID);
2409 return true;
2410 }
2411 case Intrinsic::objectsize:
2412 llvm_unreachable("llvm.objectsize.* should have been lowered already");
2413
2414 case Intrinsic::is_constant:
2415 llvm_unreachable("llvm.is.constant.* should have been lowered already");
2416
2417 case Intrinsic::stackguard:
2418 getStackGuard(DstReg: getOrCreateVReg(Val: CI), MIRBuilder);
2419 return true;
2420 case Intrinsic::stackprotector: {
2421 LLT PtrTy = getLLTForType(Ty&: *CI.getArgOperand(i: 0)->getType(), DL: *DL);
2422 Register GuardVal;
2423 if (TLI->useLoadStackGuardNode(M: *CI.getModule())) {
2424 GuardVal = MRI->createGenericVirtualRegister(Ty: PtrTy);
2425 getStackGuard(DstReg: GuardVal, MIRBuilder);
2426 } else
2427 GuardVal = getOrCreateVReg(Val: *CI.getArgOperand(i: 0)); // The guard's value.
2428
2429 AllocaInst *Slot = cast<AllocaInst>(Val: CI.getArgOperand(i: 1));
2430 int FI = getOrCreateFrameIndex(AI: *Slot);
2431 MF->getFrameInfo().setStackProtectorIndex(FI);
2432
2433 MIRBuilder.buildStore(
2434 Val: GuardVal, Addr: getOrCreateVReg(Val: *Slot),
2435 MMO&: *MF->getMachineMemOperand(PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI),
2436 f: MachineMemOperand::MOStore |
2437 MachineMemOperand::MOVolatile,
2438 MemTy: PtrTy, base_alignment: Align(8)));
2439 return true;
2440 }
2441 case Intrinsic::stacksave: {
2442 MIRBuilder.buildInstr(Opc: TargetOpcode::G_STACKSAVE, DstOps: {getOrCreateVReg(Val: CI)}, SrcOps: {});
2443 return true;
2444 }
2445 case Intrinsic::stackrestore: {
2446 MIRBuilder.buildInstr(Opc: TargetOpcode::G_STACKRESTORE, DstOps: {},
2447 SrcOps: {getOrCreateVReg(Val: *CI.getArgOperand(i: 0))});
2448 return true;
2449 }
2450 case Intrinsic::cttz:
2451 case Intrinsic::ctlz: {
2452 ConstantInt *Cst = cast<ConstantInt>(Val: CI.getArgOperand(i: 1));
2453 bool isTrailing = ID == Intrinsic::cttz;
2454 unsigned Opcode = isTrailing
2455 ? Cst->isZero() ? TargetOpcode::G_CTTZ
2456 : TargetOpcode::G_CTTZ_ZERO_UNDEF
2457 : Cst->isZero() ? TargetOpcode::G_CTLZ
2458 : TargetOpcode::G_CTLZ_ZERO_UNDEF;
2459 MIRBuilder.buildInstr(Opc: Opcode, DstOps: {getOrCreateVReg(Val: CI)},
2460 SrcOps: {getOrCreateVReg(Val: *CI.getArgOperand(i: 0))});
2461 return true;
2462 }
2463 case Intrinsic::invariant_start: {
2464 MIRBuilder.buildUndef(Res: getOrCreateVReg(Val: CI));
2465 return true;
2466 }
2467 case Intrinsic::invariant_end:
2468 return true;
2469 case Intrinsic::expect:
2470 case Intrinsic::expect_with_probability:
2471 case Intrinsic::annotation:
2472 case Intrinsic::ptr_annotation:
2473 case Intrinsic::launder_invariant_group:
2474 case Intrinsic::strip_invariant_group: {
2475 // Drop the intrinsic, but forward the value.
2476 MIRBuilder.buildCopy(Res: getOrCreateVReg(Val: CI),
2477 Op: getOrCreateVReg(Val: *CI.getArgOperand(i: 0)));
2478 return true;
2479 }
2480 case Intrinsic::assume:
2481 case Intrinsic::experimental_noalias_scope_decl:
2482 case Intrinsic::var_annotation:
2483 case Intrinsic::sideeffect:
2484 // Discard annotate attributes, assumptions, and artificial side-effects.
2485 return true;
2486 case Intrinsic::read_volatile_register:
2487 case Intrinsic::read_register: {
2488 Value *Arg = CI.getArgOperand(i: 0);
2489 MIRBuilder
2490 .buildInstr(Opc: TargetOpcode::G_READ_REGISTER, DstOps: {getOrCreateVReg(Val: CI)}, SrcOps: {})
2491 .addMetadata(MD: cast<MDNode>(Val: cast<MetadataAsValue>(Val: Arg)->getMetadata()));
2492 return true;
2493 }
2494 case Intrinsic::write_register: {
2495 Value *Arg = CI.getArgOperand(i: 0);
2496 MIRBuilder.buildInstr(Opcode: TargetOpcode::G_WRITE_REGISTER)
2497 .addMetadata(MD: cast<MDNode>(Val: cast<MetadataAsValue>(Val: Arg)->getMetadata()))
2498 .addUse(RegNo: getOrCreateVReg(Val: *CI.getArgOperand(i: 1)));
2499 return true;
2500 }
2501 case Intrinsic::localescape: {
2502 MachineBasicBlock &EntryMBB = MF->front();
2503 StringRef EscapedName = GlobalValue::dropLLVMManglingEscape(Name: MF->getName());
2504
2505 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
2506 // is the same on all targets.
2507 for (unsigned Idx = 0, E = CI.arg_size(); Idx < E; ++Idx) {
2508 Value *Arg = CI.getArgOperand(i: Idx)->stripPointerCasts();
2509 if (isa<ConstantPointerNull>(Val: Arg))
2510 continue; // Skip null pointers. They represent a hole in index space.
2511
2512 int FI = getOrCreateFrameIndex(AI: *cast<AllocaInst>(Val: Arg));
2513 MCSymbol *FrameAllocSym =
2514 MF->getContext().getOrCreateFrameAllocSymbol(FuncName: EscapedName, Idx);
2515
2516 // This should be inserted at the start of the entry block.
2517 auto LocalEscape =
2518 MIRBuilder.buildInstrNoInsert(Opcode: TargetOpcode::LOCAL_ESCAPE)
2519 .addSym(Sym: FrameAllocSym)
2520 .addFrameIndex(Idx: FI);
2521
2522 EntryMBB.insert(I: EntryMBB.begin(), MI: LocalEscape);
2523 }
2524
2525 return true;
2526 }
2527 case Intrinsic::vector_reduce_fadd:
2528 case Intrinsic::vector_reduce_fmul: {
2529 // Need to check for the reassoc flag to decide whether we want a
2530 // sequential reduction opcode or not.
2531 Register Dst = getOrCreateVReg(Val: CI);
2532 Register ScalarSrc = getOrCreateVReg(Val: *CI.getArgOperand(i: 0));
2533 Register VecSrc = getOrCreateVReg(Val: *CI.getArgOperand(i: 1));
2534 unsigned Opc = 0;
2535 if (!CI.hasAllowReassoc()) {
2536 // The sequential ordering case.
2537 Opc = ID == Intrinsic::vector_reduce_fadd
2538 ? TargetOpcode::G_VECREDUCE_SEQ_FADD
2539 : TargetOpcode::G_VECREDUCE_SEQ_FMUL;
2540 if (!MRI->getType(Reg: VecSrc).isVector())
2541 Opc = ID == Intrinsic::vector_reduce_fadd ? TargetOpcode::G_FADD
2542 : TargetOpcode::G_FMUL;
2543 MIRBuilder.buildInstr(Opc, DstOps: {Dst}, SrcOps: {ScalarSrc, VecSrc},
2544 Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2545 return true;
2546 }
2547 // We split the operation into a separate G_FADD/G_FMUL + the reduce,
2548 // since the associativity doesn't matter.
2549 unsigned ScalarOpc;
2550 if (ID == Intrinsic::vector_reduce_fadd) {
2551 Opc = TargetOpcode::G_VECREDUCE_FADD;
2552 ScalarOpc = TargetOpcode::G_FADD;
2553 } else {
2554 Opc = TargetOpcode::G_VECREDUCE_FMUL;
2555 ScalarOpc = TargetOpcode::G_FMUL;
2556 }
2557 LLT DstTy = MRI->getType(Reg: Dst);
2558 auto Rdx = MIRBuilder.buildInstr(
2559 Opc, DstOps: {DstTy}, SrcOps: {VecSrc}, Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2560 MIRBuilder.buildInstr(Opc: ScalarOpc, DstOps: {Dst}, SrcOps: {ScalarSrc, Rdx},
2561 Flags: MachineInstr::copyFlagsFromInstruction(I: CI));
2562
2563 return true;
2564 }
2565 case Intrinsic::trap:
2566 return translateTrap(CI, MIRBuilder, Opcode: TargetOpcode::G_TRAP);
2567 case Intrinsic::debugtrap:
2568 return translateTrap(CI, MIRBuilder, Opcode: TargetOpcode::G_DEBUGTRAP);
2569 case Intrinsic::ubsantrap:
2570 return translateTrap(CI, MIRBuilder, Opcode: TargetOpcode::G_UBSANTRAP);
2571 case Intrinsic::allow_runtime_check:
2572 case Intrinsic::allow_ubsan_check:
2573 MIRBuilder.buildCopy(Res: getOrCreateVReg(Val: CI),
2574 Op: getOrCreateVReg(Val: *ConstantInt::getTrue(Ty: CI.getType())));
2575 return true;
2576 case Intrinsic::amdgcn_cs_chain:
2577 case Intrinsic::amdgcn_call_whole_wave:
2578 return translateCallBase(CB: CI, MIRBuilder);
2579 case Intrinsic::fptrunc_round: {
2580 uint32_t Flags = MachineInstr::copyFlagsFromInstruction(I: CI);
2581
2582 // Convert the metadata argument to a constant integer
2583 Metadata *MD = cast<MetadataAsValue>(Val: CI.getArgOperand(i: 1))->getMetadata();
2584 std::optional<RoundingMode> RoundMode =
2585 convertStrToRoundingMode(cast<MDString>(Val: MD)->getString());
2586
2587 // Add the Rounding mode as an integer
2588 MIRBuilder
2589 .buildInstr(Opc: TargetOpcode::G_INTRINSIC_FPTRUNC_ROUND,
2590 DstOps: {getOrCreateVReg(Val: CI)},
2591 SrcOps: {getOrCreateVReg(Val: *CI.getArgOperand(i: 0))}, Flags)
2592 .addImm(Val: (int)*RoundMode);
2593
2594 return true;
2595 }
2596 case Intrinsic::is_fpclass: {
2597 Value *FpValue = CI.getOperand(i_nocapture: 0);
2598 ConstantInt *TestMaskValue = cast<ConstantInt>(Val: CI.getOperand(i_nocapture: 1));
2599
2600 MIRBuilder
2601 .buildInstr(Opc: TargetOpcode::G_IS_FPCLASS, DstOps: {getOrCreateVReg(Val: CI)},
2602 SrcOps: {getOrCreateVReg(Val: *FpValue)})
2603 .addImm(Val: TestMaskValue->getZExtValue());
2604
2605 return true;
2606 }
2607 case Intrinsic::set_fpenv: {
2608 Value *FPEnv = CI.getOperand(i_nocapture: 0);
2609 MIRBuilder.buildSetFPEnv(Src: getOrCreateVReg(Val: *FPEnv));
2610 return true;
2611 }
2612 case Intrinsic::reset_fpenv:
2613 MIRBuilder.buildResetFPEnv();
2614 return true;
2615 case Intrinsic::set_fpmode: {
2616 Value *FPState = CI.getOperand(i_nocapture: 0);
2617 MIRBuilder.buildSetFPMode(Src: getOrCreateVReg(Val: *FPState));
2618 return true;
2619 }
2620 case Intrinsic::reset_fpmode:
2621 MIRBuilder.buildResetFPMode();
2622 return true;
2623 case Intrinsic::get_rounding:
2624 MIRBuilder.buildGetRounding(Dst: getOrCreateVReg(Val: CI));
2625 return true;
2626 case Intrinsic::set_rounding:
2627 MIRBuilder.buildSetRounding(Src: getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 0)));
2628 return true;
2629 case Intrinsic::vscale: {
2630 MIRBuilder.buildVScale(Res: getOrCreateVReg(Val: CI), MinElts: 1);
2631 return true;
2632 }
2633 case Intrinsic::scmp:
2634 MIRBuilder.buildSCmp(Res: getOrCreateVReg(Val: CI),
2635 Op0: getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 0)),
2636 Op1: getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 1)));
2637 return true;
2638 case Intrinsic::ucmp:
2639 MIRBuilder.buildUCmp(Res: getOrCreateVReg(Val: CI),
2640 Op0: getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 0)),
2641 Op1: getOrCreateVReg(Val: *CI.getOperand(i_nocapture: 1)));
2642 return true;
2643 case Intrinsic::vector_extract:
2644 return translateExtractVector(U: CI, MIRBuilder);
2645 case Intrinsic::vector_insert:
2646 return translateInsertVector(U: CI, MIRBuilder);
2647 case Intrinsic::stepvector: {
2648 MIRBuilder.buildStepVector(Res: getOrCreateVReg(Val: CI), Step: 1);
2649 return true;
2650 }
2651 case Intrinsic::prefetch: {
2652 Value *Addr = CI.getOperand(i_nocapture: 0);
2653 unsigned RW = cast<ConstantInt>(Val: CI.getOperand(i_nocapture: 1))->getZExtValue();
2654 unsigned Locality = cast<ConstantInt>(Val: CI.getOperand(i_nocapture: 2))->getZExtValue();
2655 unsigned CacheType = cast<ConstantInt>(Val: CI.getOperand(i_nocapture: 3))->getZExtValue();
2656
2657 auto Flags = RW ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;
2658 auto &MMO = *MF->getMachineMemOperand(PtrInfo: MachinePointerInfo(Addr), f: Flags,
2659 MemTy: LLT(), base_alignment: Align());
2660
2661 MIRBuilder.buildPrefetch(Addr: getOrCreateVReg(Val: *Addr), RW, Locality, CacheType,
2662 MMO);
2663
2664 return true;
2665 }
2666
2667 case Intrinsic::vector_interleave2:
2668 case Intrinsic::vector_deinterleave2: {
2669 // Both intrinsics have at least one operand.
2670 Value *Op0 = CI.getOperand(i_nocapture: 0);
2671 LLT ResTy = getLLTForType(Ty&: *Op0->getType(), DL: MIRBuilder.getDataLayout());
2672 if (!ResTy.isFixedVector())
2673 return false;
2674
2675 if (CI.getIntrinsicID() == Intrinsic::vector_interleave2)
2676 return translateVectorInterleave2Intrinsic(CI, MIRBuilder);
2677
2678 return translateVectorDeinterleave2Intrinsic(CI, MIRBuilder);
2679 }
2680
2681#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
2682 case Intrinsic::INTRINSIC:
2683#include "llvm/IR/ConstrainedOps.def"
2684 return translateConstrainedFPIntrinsic(FPI: cast<ConstrainedFPIntrinsic>(Val: CI),
2685 MIRBuilder);
2686 case Intrinsic::experimental_convergence_anchor:
2687 case Intrinsic::experimental_convergence_entry:
2688 case Intrinsic::experimental_convergence_loop:
2689 return translateConvergenceControlIntrinsic(CI, ID, MIRBuilder);
2690 case Intrinsic::reloc_none: {
2691 Metadata *MD = cast<MetadataAsValue>(Val: CI.getArgOperand(i: 0))->getMetadata();
2692 StringRef SymbolName = cast<MDString>(Val: MD)->getString();
2693 MIRBuilder.buildInstr(Opcode: TargetOpcode::RELOC_NONE)
2694 .addExternalSymbol(FnName: SymbolName.data());
2695 return true;
2696 }
2697 }
2698 return false;
2699}
2700
2701bool IRTranslator::translateInlineAsm(const CallBase &CB,
2702 MachineIRBuilder &MIRBuilder) {
2703 if (containsBF16Type(U: CB) && !targetSupportsBF16Type(MF))
2704 return false;
2705
2706 const InlineAsmLowering *ALI = MF->getSubtarget().getInlineAsmLowering();
2707
2708 if (!ALI) {
2709 LLVM_DEBUG(
2710 dbgs() << "Inline asm lowering is not supported for this target yet\n");
2711 return false;
2712 }
2713
2714 return ALI->lowerInlineAsm(
2715 MIRBuilder, CB, GetOrCreateVRegs: [&](const Value &Val) { return getOrCreateVRegs(Val); });
2716}
2717
2718bool IRTranslator::translateCallBase(const CallBase &CB,
2719 MachineIRBuilder &MIRBuilder) {
2720 ArrayRef<Register> Res = getOrCreateVRegs(Val: CB);
2721
2722 SmallVector<ArrayRef<Register>, 8> Args;
2723 Register SwiftInVReg = 0;
2724 Register SwiftErrorVReg = 0;
2725 for (const auto &Arg : CB.args()) {
2726 if (CLI->supportSwiftError() && isSwiftError(V: Arg)) {
2727 assert(SwiftInVReg == 0 && "Expected only one swift error argument");
2728 LLT Ty = getLLTForType(Ty&: *Arg->getType(), DL: *DL);
2729 SwiftInVReg = MRI->createGenericVirtualRegister(Ty);
2730 MIRBuilder.buildCopy(Res: SwiftInVReg, Op: SwiftError.getOrCreateVRegUseAt(
2731 &CB, &MIRBuilder.getMBB(), Arg));
2732 Args.emplace_back(Args: ArrayRef(SwiftInVReg));
2733 SwiftErrorVReg =
2734 SwiftError.getOrCreateVRegDefAt(&CB, &MIRBuilder.getMBB(), Arg);
2735 continue;
2736 }
2737 Args.push_back(Elt: getOrCreateVRegs(Val: *Arg));
2738 }
2739
2740 if (auto *CI = dyn_cast<CallInst>(Val: &CB)) {
2741 if (ORE->enabled()) {
2742 if (MemoryOpRemark::canHandle(I: CI, TLI: *LibInfo)) {
2743 MemoryOpRemark R(*ORE, "gisel-irtranslator-memsize", *DL, *LibInfo);
2744 R.visit(I: CI);
2745 }
2746 }
2747 }
2748
2749 std::optional<CallLowering::PtrAuthInfo> PAI;
2750 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_ptrauth)) {
2751 // Functions should never be ptrauth-called directly.
2752 assert(!CB.getCalledFunction() && "invalid direct ptrauth call");
2753
2754 const Value *Key = Bundle->Inputs[0];
2755 const Value *Discriminator = Bundle->Inputs[1];
2756
2757 // Look through ptrauth constants to try to eliminate the matching bundle
2758 // and turn this into a direct call with no ptrauth.
2759 // CallLowering will use the raw pointer if it doesn't find the PAI.
2760 const auto *CalleeCPA = dyn_cast<ConstantPtrAuth>(Val: CB.getCalledOperand());
2761 if (!CalleeCPA || !isa<Function>(Val: CalleeCPA->getPointer()) ||
2762 !CalleeCPA->isKnownCompatibleWith(Key, Discriminator, DL: *DL)) {
2763 // If we can't make it direct, package the bundle into PAI.
2764 Register DiscReg = getOrCreateVReg(Val: *Discriminator);
2765 PAI = CallLowering::PtrAuthInfo{.Key: cast<ConstantInt>(Val: Key)->getZExtValue(),
2766 .Discriminator: DiscReg};
2767 }
2768 }
2769
2770 Register ConvergenceCtrlToken = 0;
2771 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_convergencectrl)) {
2772 const auto &Token = *Bundle->Inputs[0].get();
2773 ConvergenceCtrlToken = getOrCreateConvergenceTokenVReg(Token);
2774 }
2775
2776 // We don't set HasCalls on MFI here yet because call lowering may decide to
2777 // optimize into tail calls. Instead, we defer that to selection where a final
2778 // scan is done to check if any instructions are calls.
2779 bool Success = CLI->lowerCall(
2780 MIRBuilder, Call: CB, ResRegs: Res, ArgRegs: Args, SwiftErrorVReg, PAI, ConvergenceCtrlToken,
2781 GetCalleeReg: [&]() { return getOrCreateVReg(Val: *CB.getCalledOperand()); });
2782
2783 // Check if we just inserted a tail call.
2784 if (Success) {
2785 assert(!HasTailCall && "Can't tail call return twice from block?");
2786 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
2787 HasTailCall = TII->isTailCall(Inst: *std::prev(x: MIRBuilder.getInsertPt()));
2788 }
2789
2790 return Success;
2791}
2792
2793bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
2794 if (containsBF16Type(U) && !targetSupportsBF16Type(MF))
2795 return false;
2796
2797 const CallInst &CI = cast<CallInst>(Val: U);
2798 const Function *F = CI.getCalledFunction();
2799
2800 // FIXME: support Windows dllimport function calls and calls through
2801 // weak symbols.
2802 if (F && (F->hasDLLImportStorageClass() ||
2803 (MF->getTarget().getTargetTriple().isOSWindows() &&
2804 F->hasExternalWeakLinkage())))
2805 return false;
2806
2807 // FIXME: support control flow guard targets.
2808 if (CI.countOperandBundlesOfType(ID: LLVMContext::OB_cfguardtarget))
2809 return false;
2810
2811 // FIXME: support statepoints and related.
2812 if (isa<GCStatepointInst, GCRelocateInst, GCResultInst>(Val: U))
2813 return false;
2814
2815 if (CI.isInlineAsm())
2816 return translateInlineAsm(CB: CI, MIRBuilder);
2817
2818 Intrinsic::ID ID = F ? F->getIntrinsicID() : Intrinsic::not_intrinsic;
2819 if (!F || ID == Intrinsic::not_intrinsic) {
2820 if (translateCallBase(CB: CI, MIRBuilder)) {
2821 diagnoseDontCall(CI);
2822 return true;
2823 }
2824 return false;
2825 }
2826
2827 assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
2828
2829 if (translateKnownIntrinsic(CI, ID, MIRBuilder))
2830 return true;
2831
2832 SmallVector<TargetLowering::IntrinsicInfo> Infos;
2833 TLI->getTgtMemIntrinsic(Infos, I: CI, MF&: *MF, Intrinsic: ID);
2834
2835 return translateIntrinsic(CB: CI, ID, MIRBuilder, TgtMemIntrinsicInfos: Infos);
2836}
2837
2838/// Translate a call or callbr to an intrinsic.
2839bool IRTranslator::translateIntrinsic(
2840 const CallBase &CB, Intrinsic::ID ID, MachineIRBuilder &MIRBuilder,
2841 ArrayRef<TargetLowering::IntrinsicInfo> TgtMemIntrinsicInfos) {
2842 ArrayRef<Register> ResultRegs;
2843 if (!CB.getType()->isVoidTy())
2844 ResultRegs = getOrCreateVRegs(Val: CB);
2845
2846 // Ignore the callsite attributes. Backend code is most likely not expecting
2847 // an intrinsic to sometimes have side effects and sometimes not.
2848 MachineInstrBuilder MIB = MIRBuilder.buildIntrinsic(ID, Res: ResultRegs);
2849 if (isa<FPMathOperator>(Val: CB))
2850 MIB->copyIRFlags(I: CB);
2851
2852 for (const auto &Arg : enumerate(First: CB.args())) {
2853 // If this is required to be an immediate, don't materialize it in a
2854 // register.
2855 if (CB.paramHasAttr(ArgNo: Arg.index(), Kind: Attribute::ImmArg)) {
2856 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val: Arg.value())) {
2857 // imm arguments are more convenient than cimm (and realistically
2858 // probably sufficient), so use them.
2859 assert(CI->getBitWidth() <= 64 &&
2860 "large intrinsic immediates not handled");
2861 MIB.addImm(Val: CI->getSExtValue());
2862 } else {
2863 MIB.addFPImm(Val: cast<ConstantFP>(Val: Arg.value()));
2864 }
2865 } else if (auto *MDVal = dyn_cast<MetadataAsValue>(Val: Arg.value())) {
2866 auto *MD = MDVal->getMetadata();
2867 auto *MDN = dyn_cast<MDNode>(Val: MD);
2868 if (!MDN) {
2869 if (auto *ConstMD = dyn_cast<ConstantAsMetadata>(Val: MD))
2870 MDN = MDNode::get(Context&: MF->getFunction().getContext(), MDs: ConstMD);
2871 else // This was probably an MDString.
2872 return false;
2873 }
2874 MIB.addMetadata(MD: MDN);
2875 } else {
2876 ArrayRef<Register> VRegs = getOrCreateVRegs(Val: *Arg.value());
2877 if (VRegs.size() > 1)
2878 return false;
2879 MIB.addUse(RegNo: VRegs[0]);
2880 }
2881 }
2882
2883 // Add MachineMemOperands for each memory access described by the target.
2884 for (const auto &Info : TgtMemIntrinsicInfos) {
2885 Align Alignment = Info.align.value_or(
2886 u: DL->getABITypeAlign(Ty: Info.memVT.getTypeForEVT(Context&: CB.getContext())));
2887 LLT MemTy = Info.memVT.isSimple()
2888 ? getLLTForMVT(Ty: Info.memVT.getSimpleVT())
2889 : LLT::scalar(SizeInBits: Info.memVT.getStoreSizeInBits());
2890
2891 // TODO: We currently just fallback to address space 0 if
2892 // getTgtMemIntrinsic didn't yield anything useful.
2893 MachinePointerInfo MPI;
2894 if (Info.ptrVal) {
2895 MPI = MachinePointerInfo(Info.ptrVal, Info.offset);
2896 } else if (Info.fallbackAddressSpace) {
2897 MPI = MachinePointerInfo(*Info.fallbackAddressSpace);
2898 }
2899 MIB.addMemOperand(MMO: MF->getMachineMemOperand(
2900 PtrInfo: MPI, f: Info.flags, MemTy, base_alignment: Alignment, AAInfo: CB.getAAMetadata(),
2901 /*Ranges=*/nullptr, SSID: Info.ssid, Ordering: Info.order, FailureOrdering: Info.failureOrder));
2902 }
2903
2904 if (CB.isConvergent()) {
2905 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_convergencectrl)) {
2906 auto *Token = Bundle->Inputs[0].get();
2907 Register TokenReg = getOrCreateVReg(Val: *Token);
2908 MIB.addUse(RegNo: TokenReg, Flags: RegState::Implicit);
2909 }
2910 }
2911
2912 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_deactivation_symbol))
2913 MIB->setDeactivationSymbol(MF&: *MF, DS: Bundle->Inputs[0].get());
2914
2915 return true;
2916}
2917
2918bool IRTranslator::findUnwindDestinations(
2919 const BasicBlock *EHPadBB,
2920 BranchProbability Prob,
2921 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
2922 &UnwindDests) {
2923 EHPersonality Personality = classifyEHPersonality(
2924 Pers: EHPadBB->getParent()->getFunction().getPersonalityFn());
2925 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
2926 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
2927 bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
2928 bool IsSEH = isAsynchronousEHPersonality(Pers: Personality);
2929
2930 if (IsWasmCXX) {
2931 // Ignore this for now.
2932 return false;
2933 }
2934
2935 while (EHPadBB) {
2936 BasicBlock::const_iterator Pad = EHPadBB->getFirstNonPHIIt();
2937 BasicBlock *NewEHPadBB = nullptr;
2938 if (isa<LandingPadInst>(Val: Pad)) {
2939 // Stop on landingpads. They are not funclets.
2940 UnwindDests.emplace_back(Args: &getMBB(BB: *EHPadBB), Args&: Prob);
2941 break;
2942 }
2943 if (isa<CleanupPadInst>(Val: Pad)) {
2944 // Stop on cleanup pads. Cleanups are always funclet entries for all known
2945 // personalities.
2946 UnwindDests.emplace_back(Args: &getMBB(BB: *EHPadBB), Args&: Prob);
2947 UnwindDests.back().first->setIsEHScopeEntry();
2948 UnwindDests.back().first->setIsEHFuncletEntry();
2949 break;
2950 }
2951 if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Val&: Pad)) {
2952 // Add the catchpad handlers to the possible destinations.
2953 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2954 UnwindDests.emplace_back(Args: &getMBB(BB: *CatchPadBB), Args&: Prob);
2955 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
2956 if (IsMSVCCXX || IsCoreCLR)
2957 UnwindDests.back().first->setIsEHFuncletEntry();
2958 if (!IsSEH)
2959 UnwindDests.back().first->setIsEHScopeEntry();
2960 }
2961 NewEHPadBB = CatchSwitch->getUnwindDest();
2962 } else {
2963 continue;
2964 }
2965
2966 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2967 if (BPI && NewEHPadBB)
2968 Prob *= BPI->getEdgeProbability(Src: EHPadBB, Dst: NewEHPadBB);
2969 EHPadBB = NewEHPadBB;
2970 }
2971 return true;
2972}
2973
2974bool IRTranslator::translateInvoke(const User &U,
2975 MachineIRBuilder &MIRBuilder) {
2976 const InvokeInst &I = cast<InvokeInst>(Val: U);
2977 MCContext &Context = MF->getContext();
2978
2979 const BasicBlock *ReturnBB = I.getSuccessor(i: 0);
2980 const BasicBlock *EHPadBB = I.getSuccessor(i: 1);
2981
2982 const Function *Fn = I.getCalledFunction();
2983
2984 // FIXME: support invoking patchpoint and statepoint intrinsics.
2985 if (Fn && Fn->isIntrinsic())
2986 return false;
2987
2988 // FIXME: support whatever these are.
2989 if (I.hasDeoptState())
2990 return false;
2991
2992 // FIXME: support control flow guard targets.
2993 if (I.countOperandBundlesOfType(ID: LLVMContext::OB_cfguardtarget))
2994 return false;
2995
2996 // FIXME: support Windows exception handling.
2997 if (!isa<LandingPadInst>(Val: EHPadBB->getFirstNonPHIIt()))
2998 return false;
2999
3000 // FIXME: support Windows dllimport function calls and calls through
3001 // weak symbols.
3002 if (Fn && (Fn->hasDLLImportStorageClass() ||
3003 (MF->getTarget().getTargetTriple().isOSWindows() &&
3004 Fn->hasExternalWeakLinkage())))
3005 return false;
3006
3007 bool LowerInlineAsm = I.isInlineAsm();
3008 bool NeedEHLabel = true;
3009
3010 // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
3011 // the region covered by the try.
3012 MCSymbol *BeginSymbol = nullptr;
3013 if (NeedEHLabel) {
3014 MIRBuilder.buildInstr(Opcode: TargetOpcode::G_INVOKE_REGION_START);
3015 BeginSymbol = Context.createTempSymbol();
3016 MIRBuilder.buildInstr(Opcode: TargetOpcode::EH_LABEL).addSym(Sym: BeginSymbol);
3017 }
3018
3019 if (LowerInlineAsm) {
3020 if (!translateInlineAsm(CB: I, MIRBuilder))
3021 return false;
3022 } else if (!translateCallBase(CB: I, MIRBuilder))
3023 return false;
3024
3025 MCSymbol *EndSymbol = nullptr;
3026 if (NeedEHLabel) {
3027 EndSymbol = Context.createTempSymbol();
3028 MIRBuilder.buildInstr(Opcode: TargetOpcode::EH_LABEL).addSym(Sym: EndSymbol);
3029 }
3030
3031 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
3032 BranchProbabilityInfo *BPI = FuncInfo.BPI;
3033 MachineBasicBlock *InvokeMBB = &MIRBuilder.getMBB();
3034 BranchProbability EHPadBBProb =
3035 BPI ? BPI->getEdgeProbability(Src: InvokeMBB->getBasicBlock(), Dst: EHPadBB)
3036 : BranchProbability::getZero();
3037
3038 if (!findUnwindDestinations(EHPadBB, Prob: EHPadBBProb, UnwindDests))
3039 return false;
3040
3041 MachineBasicBlock &EHPadMBB = getMBB(BB: *EHPadBB),
3042 &ReturnMBB = getMBB(BB: *ReturnBB);
3043 // Update successor info.
3044 addSuccessorWithProb(Src: InvokeMBB, Dst: &ReturnMBB);
3045 for (auto &UnwindDest : UnwindDests) {
3046 UnwindDest.first->setIsEHPad();
3047 addSuccessorWithProb(Src: InvokeMBB, Dst: UnwindDest.first, Prob: UnwindDest.second);
3048 }
3049 InvokeMBB->normalizeSuccProbs();
3050
3051 if (NeedEHLabel) {
3052 assert(BeginSymbol && "Expected a begin symbol!");
3053 assert(EndSymbol && "Expected an end symbol!");
3054 MF->addInvoke(LandingPad: &EHPadMBB, BeginLabel: BeginSymbol, EndLabel: EndSymbol);
3055 }
3056
3057 MIRBuilder.buildBr(Dest&: ReturnMBB);
3058 return true;
3059}
3060
3061/// The intrinsics currently supported by callbr are implicit control flow
3062/// intrinsics such as amdgcn.kill.
3063bool IRTranslator::translateCallBr(const User &U,
3064 MachineIRBuilder &MIRBuilder) {
3065 if (containsBF16Type(U))
3066 return false; // see translateCall
3067
3068 const CallBrInst &I = cast<CallBrInst>(Val: U);
3069 MachineBasicBlock *CallBrMBB = &MIRBuilder.getMBB();
3070
3071 Intrinsic::ID IID = I.getIntrinsicID();
3072 if (I.isInlineAsm()) {
3073 // FIXME: inline asm is not yet supported for callbr in GlobalISel. As soon
3074 // as we add support, we need to handle the indirect asm targets, see
3075 // SelectionDAGBuilder::visitCallBr().
3076 return false;
3077 }
3078 if (!translateIntrinsic(CB: I, ID: IID, MIRBuilder))
3079 return false;
3080
3081 // Retrieve successors.
3082 SmallPtrSet<BasicBlock *, 8> Dests = {I.getDefaultDest()};
3083 MachineBasicBlock *Return = &getMBB(BB: *I.getDefaultDest());
3084
3085 // Update successor info.
3086 addSuccessorWithProb(Src: CallBrMBB, Dst: Return, Prob: BranchProbability::getOne());
3087
3088 // Add indirect targets as successors. For intrinsic callbr, these represent
3089 // implicit control flow (e.g., the "kill" path for amdgcn.kill). We mark them
3090 // with setIsInlineAsmBrIndirectTarget so the machine verifier accepts them as
3091 // valid successors, even though they're not from inline asm.
3092 for (BasicBlock *Dest : I.getIndirectDests()) {
3093 MachineBasicBlock &Target = getMBB(BB: *Dest);
3094 Target.setIsInlineAsmBrIndirectTarget();
3095 Target.setLabelMustBeEmitted();
3096 // Don't add duplicate machine successors.
3097 if (Dests.insert(Ptr: Dest).second)
3098 addSuccessorWithProb(Src: CallBrMBB, Dst: &Target, Prob: BranchProbability::getZero());
3099 }
3100
3101 CallBrMBB->normalizeSuccProbs();
3102
3103 // Drop into default successor.
3104 MIRBuilder.buildBr(Dest&: *Return);
3105
3106 return true;
3107}
3108
3109bool IRTranslator::translateLandingPad(const User &U,
3110 MachineIRBuilder &MIRBuilder) {
3111 const LandingPadInst &LP = cast<LandingPadInst>(Val: U);
3112
3113 MachineBasicBlock &MBB = MIRBuilder.getMBB();
3114
3115 MBB.setIsEHPad();
3116
3117 // If there aren't registers to copy the values into (e.g., during SjLj
3118 // exceptions), then don't bother.
3119 const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
3120 if (TLI->getExceptionPointerRegister(PersonalityFn) == 0 &&
3121 TLI->getExceptionSelectorRegister(PersonalityFn) == 0)
3122 return true;
3123
3124 // If landingpad's return type is token type, we don't create DAG nodes
3125 // for its exception pointer and selector value. The extraction of exception
3126 // pointer or selector value from token type landingpads is not currently
3127 // supported.
3128 if (LP.getType()->isTokenTy())
3129 return true;
3130
3131 // Add a label to mark the beginning of the landing pad. Deletion of the
3132 // landing pad can thus be detected via the MachineModuleInfo.
3133 MIRBuilder.buildInstr(Opcode: TargetOpcode::EH_LABEL)
3134 .addSym(Sym: MF->addLandingPad(LandingPad: &MBB));
3135
3136 // If the unwinder does not preserve all registers, ensure that the
3137 // function marks the clobbered registers as used.
3138 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
3139 if (auto *RegMask = TRI.getCustomEHPadPreservedMask(MF: *MF))
3140 MF->getRegInfo().addPhysRegsUsedFromRegMask(RegMask);
3141
3142 LLT Ty = getLLTForType(Ty&: *LP.getType(), DL: *DL);
3143 Register Undef = MRI->createGenericVirtualRegister(Ty);
3144 MIRBuilder.buildUndef(Res: Undef);
3145
3146 SmallVector<LLT, 2> Tys;
3147 for (Type *Ty : cast<StructType>(Val: LP.getType())->elements())
3148 Tys.push_back(Elt: getLLTForType(Ty&: *Ty, DL: *DL));
3149 assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
3150
3151 // Mark exception register as live in.
3152 Register ExceptionReg = TLI->getExceptionPointerRegister(PersonalityFn);
3153 if (!ExceptionReg)
3154 return false;
3155
3156 MBB.addLiveIn(PhysReg: ExceptionReg);
3157 ArrayRef<Register> ResRegs = getOrCreateVRegs(Val: LP);
3158 MIRBuilder.buildCopy(Res: ResRegs[0], Op: ExceptionReg);
3159
3160 Register SelectorReg = TLI->getExceptionSelectorRegister(PersonalityFn);
3161 if (!SelectorReg)
3162 return false;
3163
3164 MBB.addLiveIn(PhysReg: SelectorReg);
3165 Register PtrVReg = MRI->createGenericVirtualRegister(Ty: Tys[0]);
3166 MIRBuilder.buildCopy(Res: PtrVReg, Op: SelectorReg);
3167 MIRBuilder.buildCast(Dst: ResRegs[1], Src: PtrVReg);
3168
3169 return true;
3170}
3171
3172bool IRTranslator::translateAlloca(const User &U,
3173 MachineIRBuilder &MIRBuilder) {
3174 auto &AI = cast<AllocaInst>(Val: U);
3175
3176 if (AI.isSwiftError())
3177 return true;
3178
3179 if (AI.isStaticAlloca()) {
3180 Register Res = getOrCreateVReg(Val: AI);
3181 int FI = getOrCreateFrameIndex(AI);
3182 MIRBuilder.buildFrameIndex(Res, Idx: FI);
3183 return true;
3184 }
3185
3186 // FIXME: support stack probing for Windows.
3187 if (MF->getTarget().getTargetTriple().isOSWindows())
3188 return false;
3189
3190 // Now we're in the harder dynamic case.
3191 Register NumElts = getOrCreateVReg(Val: *AI.getArraySize());
3192 Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
3193 LLT IntPtrTy = getLLTForType(Ty&: *IntPtrIRTy, DL: *DL);
3194 if (MRI->getType(Reg: NumElts) != IntPtrTy) {
3195 Register ExtElts = MRI->createGenericVirtualRegister(Ty: IntPtrTy);
3196 MIRBuilder.buildZExtOrTrunc(Res: ExtElts, Op: NumElts);
3197 NumElts = ExtElts;
3198 }
3199
3200 Type *Ty = AI.getAllocatedType();
3201 TypeSize TySize = DL->getTypeAllocSize(Ty);
3202
3203 Register AllocSize = MRI->createGenericVirtualRegister(Ty: IntPtrTy);
3204 Register TySizeReg;
3205 if (TySize.isScalable()) {
3206 // For scalable types, use vscale * min_value
3207 TySizeReg = MRI->createGenericVirtualRegister(Ty: IntPtrTy);
3208 MIRBuilder.buildVScale(Res: TySizeReg, MinElts: TySize.getKnownMinValue());
3209 } else {
3210 // For fixed types, use a constant
3211 TySizeReg =
3212 getOrCreateVReg(Val: *ConstantInt::get(Ty: IntPtrIRTy, V: TySize.getFixedValue()));
3213 }
3214 MIRBuilder.buildMul(Dst: AllocSize, Src0: NumElts, Src1: TySizeReg);
3215
3216 // Round the size of the allocation up to the stack alignment size
3217 // by add SA-1 to the size. This doesn't overflow because we're computing
3218 // an address inside an alloca.
3219 Align StackAlign = MF->getSubtarget().getFrameLowering()->getStackAlign();
3220 auto SAMinusOne = MIRBuilder.buildConstant(Res: IntPtrTy, Val: StackAlign.value() - 1);
3221 auto AllocAdd = MIRBuilder.buildAdd(Dst: IntPtrTy, Src0: AllocSize, Src1: SAMinusOne,
3222 Flags: MachineInstr::NoUWrap);
3223 auto AlignCst =
3224 MIRBuilder.buildConstant(Res: IntPtrTy, Val: ~(uint64_t)(StackAlign.value() - 1));
3225 auto AlignedAlloc = MIRBuilder.buildAnd(Dst: IntPtrTy, Src0: AllocAdd, Src1: AlignCst);
3226
3227 Align Alignment = AI.getAlign();
3228 if (Alignment <= StackAlign)
3229 Alignment = Align(1);
3230 MIRBuilder.buildDynStackAlloc(Res: getOrCreateVReg(Val: AI), Size: AlignedAlloc, Alignment);
3231
3232 MF->getFrameInfo().CreateVariableSizedObject(Alignment, Alloca: &AI);
3233 assert(MF->getFrameInfo().hasVarSizedObjects());
3234 return true;
3235}
3236
3237bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
3238 // FIXME: We may need more info about the type. Because of how LLT works,
3239 // we're completely discarding the i64/double distinction here (amongst
3240 // others). Fortunately the ABIs I know of where that matters don't use va_arg
3241 // anyway but that's not guaranteed.
3242 MIRBuilder.buildInstr(Opc: TargetOpcode::G_VAARG, DstOps: {getOrCreateVReg(Val: U)},
3243 SrcOps: {getOrCreateVReg(Val: *U.getOperand(i: 0)),
3244 DL->getABITypeAlign(Ty: U.getType()).value()});
3245 return true;
3246}
3247
3248bool IRTranslator::translateUnreachable(const User &U,
3249 MachineIRBuilder &MIRBuilder) {
3250 auto &UI = cast<UnreachableInst>(Val: U);
3251 if (!UI.shouldLowerToTrap(TrapUnreachable: MF->getTarget().Options.TrapUnreachable,
3252 NoTrapAfterNoreturn: MF->getTarget().Options.NoTrapAfterNoreturn))
3253 return true;
3254
3255 MIRBuilder.buildTrap();
3256 return true;
3257}
3258
3259bool IRTranslator::translateInsertElement(const User &U,
3260 MachineIRBuilder &MIRBuilder) {
3261 // If it is a <1 x Ty> vector, use the scalar as it is
3262 // not a legal vector type in LLT.
3263 if (auto *FVT = dyn_cast<FixedVectorType>(Val: U.getType());
3264 FVT && FVT->getNumElements() == 1)
3265 return translateCopy(U, V: *U.getOperand(i: 1), MIRBuilder);
3266
3267 Register Res = getOrCreateVReg(Val: U);
3268 Register Val = getOrCreateVReg(Val: *U.getOperand(i: 0));
3269 Register Elt = getOrCreateVReg(Val: *U.getOperand(i: 1));
3270 unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(DL: *DL);
3271 Register Idx;
3272 if (auto *CI = dyn_cast<ConstantInt>(Val: U.getOperand(i: 2))) {
3273 if (CI->getBitWidth() != PreferredVecIdxWidth) {
3274 APInt NewIdx = CI->getValue().zextOrTrunc(width: PreferredVecIdxWidth);
3275 auto *NewIdxCI = ConstantInt::get(Context&: CI->getContext(), V: NewIdx);
3276 Idx = getOrCreateVReg(Val: *NewIdxCI);
3277 }
3278 }
3279 if (!Idx)
3280 Idx = getOrCreateVReg(Val: *U.getOperand(i: 2));
3281 if (MRI->getType(Reg: Idx).getSizeInBits() != PreferredVecIdxWidth) {
3282 const LLT VecIdxTy = LLT::scalar(SizeInBits: PreferredVecIdxWidth);
3283 Idx = MIRBuilder.buildZExtOrTrunc(Res: VecIdxTy, Op: Idx).getReg(Idx: 0);
3284 }
3285 MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
3286 return true;
3287}
3288
3289bool IRTranslator::translateInsertVector(const User &U,
3290 MachineIRBuilder &MIRBuilder) {
3291 Register Dst = getOrCreateVReg(Val: U);
3292 Register Vec = getOrCreateVReg(Val: *U.getOperand(i: 0));
3293 Register Elt = getOrCreateVReg(Val: *U.getOperand(i: 1));
3294
3295 ConstantInt *CI = cast<ConstantInt>(Val: U.getOperand(i: 2));
3296 unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(DL: *DL);
3297
3298 // Resize Index to preferred index width.
3299 if (CI->getBitWidth() != PreferredVecIdxWidth) {
3300 APInt NewIdx = CI->getValue().zextOrTrunc(width: PreferredVecIdxWidth);
3301 CI = ConstantInt::get(Context&: CI->getContext(), V: NewIdx);
3302 }
3303
3304 // If it is a <1 x Ty> vector, we have to use other means.
3305 if (auto *ResultType = dyn_cast<FixedVectorType>(Val: U.getOperand(i: 1)->getType());
3306 ResultType && ResultType->getNumElements() == 1) {
3307 if (auto *InputType = dyn_cast<FixedVectorType>(Val: U.getOperand(i: 0)->getType());
3308 InputType && InputType->getNumElements() == 1) {
3309 // We are inserting an illegal fixed vector into an illegal
3310 // fixed vector, use the scalar as it is not a legal vector type
3311 // in LLT.
3312 return translateCopy(U, V: *U.getOperand(i: 0), MIRBuilder);
3313 }
3314 if (isa<FixedVectorType>(Val: U.getOperand(i: 0)->getType())) {
3315 // We are inserting an illegal fixed vector into a legal fixed
3316 // vector, use the scalar as it is not a legal vector type in
3317 // LLT.
3318 Register Idx = getOrCreateVReg(Val: *CI);
3319 MIRBuilder.buildInsertVectorElement(Res: Dst, Val: Vec, Elt, Idx);
3320 return true;
3321 }
3322 if (isa<ScalableVectorType>(Val: U.getOperand(i: 0)->getType())) {
3323 // We are inserting an illegal fixed vector into a scalable
3324 // vector, use a scalar element insert.
3325 LLT VecIdxTy = LLT::scalar(SizeInBits: PreferredVecIdxWidth);
3326 Register Idx = getOrCreateVReg(Val: *CI);
3327 auto ScaledIndex = MIRBuilder.buildMul(
3328 Dst: VecIdxTy, Src0: MIRBuilder.buildVScale(Res: VecIdxTy, MinElts: 1), Src1: Idx);
3329 MIRBuilder.buildInsertVectorElement(Res: Dst, Val: Vec, Elt, Idx: ScaledIndex);
3330 return true;
3331 }
3332 }
3333
3334 MIRBuilder.buildInsertSubvector(
3335 Res: getOrCreateVReg(Val: U), Src0: getOrCreateVReg(Val: *U.getOperand(i: 0)),
3336 Src1: getOrCreateVReg(Val: *U.getOperand(i: 1)), Index: CI->getZExtValue());
3337 return true;
3338}
3339
3340bool IRTranslator::translateExtractElement(const User &U,
3341 MachineIRBuilder &MIRBuilder) {
3342 // If it is a <1 x Ty> vector, use the scalar as it is
3343 // not a legal vector type in LLT.
3344 if (const FixedVectorType *FVT =
3345 dyn_cast<FixedVectorType>(Val: U.getOperand(i: 0)->getType()))
3346 if (FVT->getNumElements() == 1)
3347 return translateCopy(U, V: *U.getOperand(i: 0), MIRBuilder);
3348
3349 Register Res = getOrCreateVReg(Val: U);
3350 Register Val = getOrCreateVReg(Val: *U.getOperand(i: 0));
3351 unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(DL: *DL);
3352 Register Idx;
3353 if (auto *CI = dyn_cast<ConstantInt>(Val: U.getOperand(i: 1))) {
3354 if (CI->getBitWidth() != PreferredVecIdxWidth) {
3355 APInt NewIdx = CI->getValue().zextOrTrunc(width: PreferredVecIdxWidth);
3356 auto *NewIdxCI = ConstantInt::get(Context&: CI->getContext(), V: NewIdx);
3357 Idx = getOrCreateVReg(Val: *NewIdxCI);
3358 }
3359 }
3360 if (!Idx)
3361 Idx = getOrCreateVReg(Val: *U.getOperand(i: 1));
3362 if (MRI->getType(Reg: Idx).getSizeInBits() != PreferredVecIdxWidth) {
3363 const LLT VecIdxTy = LLT::scalar(SizeInBits: PreferredVecIdxWidth);
3364 Idx = MIRBuilder.buildZExtOrTrunc(Res: VecIdxTy, Op: Idx).getReg(Idx: 0);
3365 }
3366 MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
3367 return true;
3368}
3369
3370bool IRTranslator::translateExtractVector(const User &U,
3371 MachineIRBuilder &MIRBuilder) {
3372 Register Res = getOrCreateVReg(Val: U);
3373 Register Vec = getOrCreateVReg(Val: *U.getOperand(i: 0));
3374 ConstantInt *CI = cast<ConstantInt>(Val: U.getOperand(i: 1));
3375 unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(DL: *DL);
3376
3377 // Resize Index to preferred index width.
3378 if (CI->getBitWidth() != PreferredVecIdxWidth) {
3379 APInt NewIdx = CI->getValue().zextOrTrunc(width: PreferredVecIdxWidth);
3380 CI = ConstantInt::get(Context&: CI->getContext(), V: NewIdx);
3381 }
3382
3383 // If it is a <1 x Ty> vector, we have to use other means.
3384 if (auto *ResultType = dyn_cast<FixedVectorType>(Val: U.getType());
3385 ResultType && ResultType->getNumElements() == 1) {
3386 if (auto *InputType = dyn_cast<FixedVectorType>(Val: U.getOperand(i: 0)->getType());
3387 InputType && InputType->getNumElements() == 1) {
3388 // We are extracting an illegal fixed vector from an illegal fixed vector,
3389 // use the scalar as it is not a legal vector type in LLT.
3390 return translateCopy(U, V: *U.getOperand(i: 0), MIRBuilder);
3391 }
3392 if (isa<FixedVectorType>(Val: U.getOperand(i: 0)->getType())) {
3393 // We are extracting an illegal fixed vector from a legal fixed
3394 // vector, use the scalar as it is not a legal vector type in
3395 // LLT.
3396 Register Idx = getOrCreateVReg(Val: *CI);
3397 MIRBuilder.buildExtractVectorElement(Res, Val: Vec, Idx);
3398 return true;
3399 }
3400 if (isa<ScalableVectorType>(Val: U.getOperand(i: 0)->getType())) {
3401 // We are extracting an illegal fixed vector from a scalable
3402 // vector, use a scalar element extract.
3403 LLT VecIdxTy = LLT::scalar(SizeInBits: PreferredVecIdxWidth);
3404 Register Idx = getOrCreateVReg(Val: *CI);
3405 auto ScaledIndex = MIRBuilder.buildMul(
3406 Dst: VecIdxTy, Src0: MIRBuilder.buildVScale(Res: VecIdxTy, MinElts: 1), Src1: Idx);
3407 MIRBuilder.buildExtractVectorElement(Res, Val: Vec, Idx: ScaledIndex);
3408 return true;
3409 }
3410 }
3411
3412 MIRBuilder.buildExtractSubvector(Res: getOrCreateVReg(Val: U),
3413 Src: getOrCreateVReg(Val: *U.getOperand(i: 0)),
3414 Index: CI->getZExtValue());
3415 return true;
3416}
3417
3418bool IRTranslator::translateShuffleVector(const User &U,
3419 MachineIRBuilder &MIRBuilder) {
3420 // A ShuffleVector that operates on scalable vectors is a splat vector where
3421 // the value of the splat vector is the 0th element of the first operand,
3422 // since the index mask operand is the zeroinitializer (undef and
3423 // poison are treated as zeroinitializer here).
3424 if (U.getOperand(i: 0)->getType()->isScalableTy()) {
3425 Register Val = getOrCreateVReg(Val: *U.getOperand(i: 0));
3426 auto SplatVal = MIRBuilder.buildExtractVectorElementConstant(
3427 Res: MRI->getType(Reg: Val).getElementType(), Val, Idx: 0);
3428 MIRBuilder.buildSplatVector(Res: getOrCreateVReg(Val: U), Val: SplatVal);
3429 return true;
3430 }
3431
3432 ArrayRef<int> Mask;
3433 if (auto *SVI = dyn_cast<ShuffleVectorInst>(Val: &U))
3434 Mask = SVI->getShuffleMask();
3435 else
3436 Mask = cast<ConstantExpr>(Val: U).getShuffleMask();
3437
3438 // As GISel does not represent <1 x > vectors as a separate type from scalars,
3439 // we transform shuffle_vector with a scalar output to an
3440 // ExtractVectorElement. If the input type is also scalar it becomes a Copy.
3441 unsigned DstElts = cast<FixedVectorType>(Val: U.getType())->getNumElements();
3442 unsigned SrcElts =
3443 cast<FixedVectorType>(Val: U.getOperand(i: 0)->getType())->getNumElements();
3444 if (DstElts == 1) {
3445 unsigned M = Mask[0];
3446 if (SrcElts == 1) {
3447 if (M == 0 || M == 1)
3448 return translateCopy(U, V: *U.getOperand(i: M), MIRBuilder);
3449 MIRBuilder.buildUndef(Res: getOrCreateVReg(Val: U));
3450 } else {
3451 Register Dst = getOrCreateVReg(Val: U);
3452 if (M < SrcElts) {
3453 MIRBuilder.buildExtractVectorElementConstant(
3454 Res: Dst, Val: getOrCreateVReg(Val: *U.getOperand(i: 0)), Idx: M);
3455 } else if (M < SrcElts * 2) {
3456 MIRBuilder.buildExtractVectorElementConstant(
3457 Res: Dst, Val: getOrCreateVReg(Val: *U.getOperand(i: 1)), Idx: M - SrcElts);
3458 } else {
3459 MIRBuilder.buildUndef(Res: Dst);
3460 }
3461 }
3462 return true;
3463 }
3464
3465 // A single element src is transformed to a build_vector.
3466 if (SrcElts == 1) {
3467 SmallVector<Register> Ops;
3468 Register Undef;
3469 for (int M : Mask) {
3470 LLT SrcTy = getLLTForType(Ty&: *U.getOperand(i: 0)->getType(), DL: *DL);
3471 if (M == 0 || M == 1) {
3472 Ops.push_back(Elt: getOrCreateVReg(Val: *U.getOperand(i: M)));
3473 } else {
3474 if (!Undef.isValid()) {
3475 Undef = MRI->createGenericVirtualRegister(Ty: SrcTy);
3476 MIRBuilder.buildUndef(Res: Undef);
3477 }
3478 Ops.push_back(Elt: Undef);
3479 }
3480 }
3481 MIRBuilder.buildBuildVector(Res: getOrCreateVReg(Val: U), Ops);
3482 return true;
3483 }
3484
3485 ArrayRef<int> MaskAlloc = MF->allocateShuffleMask(Mask);
3486 MIRBuilder
3487 .buildInstr(Opc: TargetOpcode::G_SHUFFLE_VECTOR, DstOps: {getOrCreateVReg(Val: U)},
3488 SrcOps: {getOrCreateVReg(Val: *U.getOperand(i: 0)),
3489 getOrCreateVReg(Val: *U.getOperand(i: 1))})
3490 .addShuffleMask(Val: MaskAlloc);
3491 return true;
3492}
3493
3494bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
3495 const PHINode &PI = cast<PHINode>(Val: U);
3496
3497 SmallVector<MachineInstr *, 4> Insts;
3498 for (auto Reg : getOrCreateVRegs(Val: PI)) {
3499 auto MIB = MIRBuilder.buildInstr(Opc: TargetOpcode::G_PHI, DstOps: {Reg}, SrcOps: {});
3500 Insts.push_back(Elt: MIB.getInstr());
3501 }
3502
3503 PendingPHIs.emplace_back(Args: &PI, Args: std::move(Insts));
3504 return true;
3505}
3506
3507bool IRTranslator::translateAtomicCmpXchg(const User &U,
3508 MachineIRBuilder &MIRBuilder) {
3509 const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(Val: U);
3510
3511 auto Flags = TLI->getAtomicMemOperandFlags(AI: I, DL: *DL);
3512
3513 auto Res = getOrCreateVRegs(Val: I);
3514 Register OldValRes = Res[0];
3515 Register SuccessRes = Res[1];
3516 Register Addr = getOrCreateVReg(Val: *I.getPointerOperand());
3517 Register Cmp = getOrCreateVReg(Val: *I.getCompareOperand());
3518 Register NewVal = getOrCreateVReg(Val: *I.getNewValOperand());
3519
3520 MIRBuilder.buildAtomicCmpXchgWithSuccess(
3521 OldValRes, SuccessRes, Addr, CmpVal: Cmp, NewVal,
3522 MMO&: *MF->getMachineMemOperand(
3523 PtrInfo: MachinePointerInfo(I.getPointerOperand()), f: Flags, MemTy: MRI->getType(Reg: Cmp),
3524 base_alignment: getMemOpAlign(I), AAInfo: I.getAAMetadata(), Ranges: nullptr, SSID: I.getSyncScopeID(),
3525 Ordering: I.getSuccessOrdering(), FailureOrdering: I.getFailureOrdering()));
3526 return true;
3527}
3528
3529bool IRTranslator::translateAtomicRMW(const User &U,
3530 MachineIRBuilder &MIRBuilder) {
3531 if (containsBF16Type(U) && !targetSupportsBF16Type(MF))
3532 return false;
3533
3534 const AtomicRMWInst &I = cast<AtomicRMWInst>(Val: U);
3535 auto Flags = TLI->getAtomicMemOperandFlags(AI: I, DL: *DL);
3536
3537 Register Res = getOrCreateVReg(Val: I);
3538 Register Addr = getOrCreateVReg(Val: *I.getPointerOperand());
3539 Register Val = getOrCreateVReg(Val: *I.getValOperand());
3540
3541 unsigned Opcode = 0;
3542 switch (I.getOperation()) {
3543 default:
3544 return false;
3545 case AtomicRMWInst::Xchg:
3546 Opcode = TargetOpcode::G_ATOMICRMW_XCHG;
3547 break;
3548 case AtomicRMWInst::Add:
3549 Opcode = TargetOpcode::G_ATOMICRMW_ADD;
3550 break;
3551 case AtomicRMWInst::Sub:
3552 Opcode = TargetOpcode::G_ATOMICRMW_SUB;
3553 break;
3554 case AtomicRMWInst::And:
3555 Opcode = TargetOpcode::G_ATOMICRMW_AND;
3556 break;
3557 case AtomicRMWInst::Nand:
3558 Opcode = TargetOpcode::G_ATOMICRMW_NAND;
3559 break;
3560 case AtomicRMWInst::Or:
3561 Opcode = TargetOpcode::G_ATOMICRMW_OR;
3562 break;
3563 case AtomicRMWInst::Xor:
3564 Opcode = TargetOpcode::G_ATOMICRMW_XOR;
3565 break;
3566 case AtomicRMWInst::Max:
3567 Opcode = TargetOpcode::G_ATOMICRMW_MAX;
3568 break;
3569 case AtomicRMWInst::Min:
3570 Opcode = TargetOpcode::G_ATOMICRMW_MIN;
3571 break;
3572 case AtomicRMWInst::UMax:
3573 Opcode = TargetOpcode::G_ATOMICRMW_UMAX;
3574 break;
3575 case AtomicRMWInst::UMin:
3576 Opcode = TargetOpcode::G_ATOMICRMW_UMIN;
3577 break;
3578 case AtomicRMWInst::FAdd:
3579 Opcode = TargetOpcode::G_ATOMICRMW_FADD;
3580 break;
3581 case AtomicRMWInst::FSub:
3582 Opcode = TargetOpcode::G_ATOMICRMW_FSUB;
3583 break;
3584 case AtomicRMWInst::FMax:
3585 Opcode = TargetOpcode::G_ATOMICRMW_FMAX;
3586 break;
3587 case AtomicRMWInst::FMin:
3588 Opcode = TargetOpcode::G_ATOMICRMW_FMIN;
3589 break;
3590 case AtomicRMWInst::FMaximum:
3591 Opcode = TargetOpcode::G_ATOMICRMW_FMAXIMUM;
3592 break;
3593 case AtomicRMWInst::FMinimum:
3594 Opcode = TargetOpcode::G_ATOMICRMW_FMINIMUM;
3595 break;
3596 case AtomicRMWInst::UIncWrap:
3597 Opcode = TargetOpcode::G_ATOMICRMW_UINC_WRAP;
3598 break;
3599 case AtomicRMWInst::UDecWrap:
3600 Opcode = TargetOpcode::G_ATOMICRMW_UDEC_WRAP;
3601 break;
3602 case AtomicRMWInst::USubCond:
3603 Opcode = TargetOpcode::G_ATOMICRMW_USUB_COND;
3604 break;
3605 case AtomicRMWInst::USubSat:
3606 Opcode = TargetOpcode::G_ATOMICRMW_USUB_SAT;
3607 break;
3608 }
3609
3610 MIRBuilder.buildAtomicRMW(
3611 Opcode, OldValRes: Res, Addr, Val,
3612 MMO&: *MF->getMachineMemOperand(PtrInfo: MachinePointerInfo(I.getPointerOperand()),
3613 f: Flags, MemTy: MRI->getType(Reg: Val), base_alignment: getMemOpAlign(I),
3614 AAInfo: I.getAAMetadata(), Ranges: nullptr, SSID: I.getSyncScopeID(),
3615 Ordering: I.getOrdering()));
3616 return true;
3617}
3618
3619bool IRTranslator::translateFence(const User &U,
3620 MachineIRBuilder &MIRBuilder) {
3621 const FenceInst &Fence = cast<FenceInst>(Val: U);
3622 MIRBuilder.buildFence(Ordering: static_cast<unsigned>(Fence.getOrdering()),
3623 Scope: Fence.getSyncScopeID());
3624 return true;
3625}
3626
3627bool IRTranslator::translateFreeze(const User &U,
3628 MachineIRBuilder &MIRBuilder) {
3629 const ArrayRef<Register> DstRegs = getOrCreateVRegs(Val: U);
3630 const ArrayRef<Register> SrcRegs = getOrCreateVRegs(Val: *U.getOperand(i: 0));
3631
3632 assert(DstRegs.size() == SrcRegs.size() &&
3633 "Freeze with different source and destination type?");
3634
3635 for (unsigned I = 0; I < DstRegs.size(); ++I) {
3636 MIRBuilder.buildFreeze(Dst: DstRegs[I], Src: SrcRegs[I]);
3637 }
3638
3639 return true;
3640}
3641
3642void IRTranslator::finishPendingPhis() {
3643#ifndef NDEBUG
3644 DILocationVerifier Verifier;
3645 GISelObserverWrapper WrapperObserver(&Verifier);
3646 RAIIMFObsDelInstaller ObsInstall(*MF, WrapperObserver);
3647#endif // ifndef NDEBUG
3648 for (auto &Phi : PendingPHIs) {
3649 const PHINode *PI = Phi.first;
3650 if (PI->getType()->isEmptyTy())
3651 continue;
3652 ArrayRef<MachineInstr *> ComponentPHIs = Phi.second;
3653 MachineBasicBlock *PhiMBB = ComponentPHIs[0]->getParent();
3654 EntryBuilder->setDebugLoc(PI->getDebugLoc());
3655#ifndef NDEBUG
3656 Verifier.setCurrentInst(PI);
3657#endif // ifndef NDEBUG
3658
3659 SmallPtrSet<const MachineBasicBlock *, 16> SeenPreds;
3660 for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
3661 auto IRPred = PI->getIncomingBlock(i);
3662 ArrayRef<Register> ValRegs = getOrCreateVRegs(Val: *PI->getIncomingValue(i));
3663 for (auto *Pred : getMachinePredBBs(Edge: {IRPred, PI->getParent()})) {
3664 if (SeenPreds.count(Ptr: Pred) || !PhiMBB->isPredecessor(MBB: Pred))
3665 continue;
3666 SeenPreds.insert(Ptr: Pred);
3667 for (unsigned j = 0; j < ValRegs.size(); ++j) {
3668 MachineInstrBuilder MIB(*MF, ComponentPHIs[j]);
3669 MIB.addUse(RegNo: ValRegs[j]);
3670 MIB.addMBB(MBB: Pred);
3671 }
3672 }
3673 }
3674 }
3675}
3676
3677void IRTranslator::translateDbgValueRecord(Value *V, bool HasArgList,
3678 const DILocalVariable *Variable,
3679 const DIExpression *Expression,
3680 const DebugLoc &DL,
3681 MachineIRBuilder &MIRBuilder) {
3682 assert(Variable->isValidLocationForIntrinsic(DL) &&
3683 "Expected inlined-at fields to agree");
3684 // Act as if we're handling a debug intrinsic.
3685 MIRBuilder.setDebugLoc(DL);
3686
3687 if (!V || HasArgList) {
3688 // DI cannot produce a valid DBG_VALUE, so produce an undef DBG_VALUE to
3689 // terminate any prior location.
3690 MIRBuilder.buildIndirectDbgValue(Reg: 0, Variable, Expr: Expression);
3691 return;
3692 }
3693
3694 if (const auto *CI = dyn_cast<Constant>(Val: V)) {
3695 MIRBuilder.buildConstDbgValue(C: *CI, Variable, Expr: Expression);
3696 return;
3697 }
3698
3699 if (auto *AI = dyn_cast<AllocaInst>(Val: V);
3700 AI && AI->isStaticAlloca() && Expression->startsWithDeref()) {
3701 // If the value is an alloca and the expression starts with a
3702 // dereference, track a stack slot instead of a register, as registers
3703 // may be clobbered.
3704 auto ExprOperands = Expression->getElements();
3705 auto *ExprDerefRemoved =
3706 DIExpression::get(Context&: AI->getContext(), Elements: ExprOperands.drop_front());
3707 MIRBuilder.buildFIDbgValue(FI: getOrCreateFrameIndex(AI: *AI), Variable,
3708 Expr: ExprDerefRemoved);
3709 return;
3710 }
3711 if (translateIfEntryValueArgument(isDeclare: false, Val: V, Var: Variable, Expr: Expression, DL,
3712 MIRBuilder))
3713 return;
3714 for (Register Reg : getOrCreateVRegs(Val: *V)) {
3715 // FIXME: This does not handle register-indirect values at offset 0. The
3716 // direct/indirect thing shouldn't really be handled by something as
3717 // implicit as reg+noreg vs reg+imm in the first place, but it seems
3718 // pretty baked in right now.
3719 MIRBuilder.buildDirectDbgValue(Reg, Variable, Expr: Expression);
3720 }
3721}
3722
3723void IRTranslator::translateDbgDeclareRecord(Value *Address, bool HasArgList,
3724 const DILocalVariable *Variable,
3725 const DIExpression *Expression,
3726 const DebugLoc &DL,
3727 MachineIRBuilder &MIRBuilder) {
3728 if (!Address || isa<UndefValue>(Val: Address)) {
3729 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *Variable << "\n");
3730 return;
3731 }
3732
3733 assert(Variable->isValidLocationForIntrinsic(DL) &&
3734 "Expected inlined-at fields to agree");
3735 auto AI = dyn_cast<AllocaInst>(Val: Address);
3736 if (AI && AI->isStaticAlloca()) {
3737 // Static allocas are tracked at the MF level, no need for DBG_VALUE
3738 // instructions (in fact, they get ignored if they *do* exist).
3739 MF->setVariableDbgInfo(Var: Variable, Expr: Expression,
3740 Slot: getOrCreateFrameIndex(AI: *AI), Loc: DL);
3741 return;
3742 }
3743
3744 if (translateIfEntryValueArgument(isDeclare: true, Val: Address, Var: Variable,
3745 Expr: Expression, DL,
3746 MIRBuilder))
3747 return;
3748
3749 // A dbg.declare describes the address of a source variable, so lower it
3750 // into an indirect DBG_VALUE.
3751 MIRBuilder.setDebugLoc(DL);
3752 MIRBuilder.buildIndirectDbgValue(Reg: getOrCreateVReg(Val: *Address), Variable,
3753 Expr: Expression);
3754}
3755
3756void IRTranslator::translateDbgInfo(const Instruction &Inst,
3757 MachineIRBuilder &MIRBuilder) {
3758 for (DbgRecord &DR : Inst.getDbgRecordRange()) {
3759 if (DbgLabelRecord *DLR = dyn_cast<DbgLabelRecord>(Val: &DR)) {
3760 MIRBuilder.setDebugLoc(DLR->getDebugLoc());
3761 assert(DLR->getLabel() && "Missing label");
3762 assert(DLR->getLabel()->isValidLocationForIntrinsic(
3763 MIRBuilder.getDebugLoc()) &&
3764 "Expected inlined-at fields to agree");
3765 MIRBuilder.buildDbgLabel(Label: DLR->getLabel());
3766 continue;
3767 }
3768 DbgVariableRecord &DVR = cast<DbgVariableRecord>(Val&: DR);
3769 const DILocalVariable *Variable = DVR.getVariable();
3770 const DIExpression *Expression = DVR.getExpression();
3771 Value *V = DVR.getVariableLocationOp(OpIdx: 0);
3772 if (DVR.isDbgDeclare())
3773 translateDbgDeclareRecord(Address: V, HasArgList: DVR.hasArgList(), Variable, Expression,
3774 DL: DVR.getDebugLoc(), MIRBuilder);
3775 else
3776 translateDbgValueRecord(V, HasArgList: DVR.hasArgList(), Variable, Expression,
3777 DL: DVR.getDebugLoc(), MIRBuilder);
3778 }
3779}
3780
3781bool IRTranslator::translate(const Instruction &Inst) {
3782 CurBuilder->setDebugLoc(Inst.getDebugLoc());
3783 CurBuilder->setPCSections(Inst.getMetadata(KindID: LLVMContext::MD_pcsections));
3784 CurBuilder->setMMRAMetadata(Inst.getMetadata(KindID: LLVMContext::MD_mmra));
3785
3786 if (TLI->fallBackToDAGISel(Inst))
3787 return false;
3788
3789 switch (Inst.getOpcode()) {
3790#define HANDLE_INST(NUM, OPCODE, CLASS) \
3791 case Instruction::OPCODE: \
3792 return translate##OPCODE(Inst, *CurBuilder.get());
3793#include "llvm/IR/Instruction.def"
3794 default:
3795 return false;
3796 }
3797}
3798
3799bool IRTranslator::translate(const Constant &C, Register Reg) {
3800 // We only emit constants into the entry block from here. To prevent jumpy
3801 // debug behaviour remove debug line.
3802 if (auto CurrInstDL = CurBuilder->getDL())
3803 EntryBuilder->setDebugLoc(DebugLoc());
3804
3805 if (auto CI = dyn_cast<ConstantInt>(Val: &C)) {
3806 // buildConstant expects a to-be-splatted scalar ConstantInt.
3807 if (isa<VectorType>(Val: CI->getType()))
3808 CI = ConstantInt::get(Context&: CI->getContext(), V: CI->getValue());
3809 EntryBuilder->buildConstant(Res: Reg, Val: *CI);
3810 } else if (auto CF = dyn_cast<ConstantFP>(Val: &C)) {
3811 // buildFConstant expects a to-be-splatted scalar ConstantFP.
3812 if (isa<VectorType>(Val: CF->getType()))
3813 CF = ConstantFP::get(Context&: CF->getContext(), V: CF->getValue());
3814 EntryBuilder->buildFConstant(Res: Reg, Val: *CF);
3815 } else if (isa<UndefValue>(Val: C))
3816 EntryBuilder->buildUndef(Res: Reg);
3817 else if (isa<ConstantPointerNull>(Val: C))
3818 EntryBuilder->buildConstant(Res: Reg, Val: 0);
3819 else if (auto GV = dyn_cast<GlobalValue>(Val: &C))
3820 EntryBuilder->buildGlobalValue(Res: Reg, GV);
3821 else if (auto CPA = dyn_cast<ConstantPtrAuth>(Val: &C)) {
3822 Register Addr = getOrCreateVReg(Val: *CPA->getPointer());
3823 Register AddrDisc = getOrCreateVReg(Val: *CPA->getAddrDiscriminator());
3824 EntryBuilder->buildConstantPtrAuth(Res: Reg, CPA, Addr, AddrDisc);
3825 } else if (auto CAZ = dyn_cast<ConstantAggregateZero>(Val: &C)) {
3826 Constant &Elt = *CAZ->getElementValue(Idx: 0u);
3827 if (isa<ScalableVectorType>(Val: CAZ->getType())) {
3828 EntryBuilder->buildSplatVector(Res: Reg, Val: getOrCreateVReg(Val: Elt));
3829 return true;
3830 }
3831 // Return the scalar if it is a <1 x Ty> vector.
3832 unsigned NumElts = CAZ->getElementCount().getFixedValue();
3833 if (NumElts == 1)
3834 return translateCopy(U: C, V: Elt, MIRBuilder&: *EntryBuilder);
3835 // All elements are zero so we can just use the first one.
3836 EntryBuilder->buildSplatBuildVector(Res: Reg, Src: getOrCreateVReg(Val: Elt));
3837 } else if (auto CV = dyn_cast<ConstantDataVector>(Val: &C)) {
3838 // Return the scalar if it is a <1 x Ty> vector.
3839 if (CV->getNumElements() == 1)
3840 return translateCopy(U: C, V: *CV->getElementAsConstant(i: 0), MIRBuilder&: *EntryBuilder);
3841 SmallVector<Register, 4> Ops;
3842 for (unsigned i = 0; i < CV->getNumElements(); ++i) {
3843 Constant &Elt = *CV->getElementAsConstant(i);
3844 Ops.push_back(Elt: getOrCreateVReg(Val: Elt));
3845 }
3846 EntryBuilder->buildBuildVector(Res: Reg, Ops);
3847 } else if (auto CE = dyn_cast<ConstantExpr>(Val: &C)) {
3848 switch(CE->getOpcode()) {
3849#define HANDLE_INST(NUM, OPCODE, CLASS) \
3850 case Instruction::OPCODE: \
3851 return translate##OPCODE(*CE, *EntryBuilder.get());
3852#include "llvm/IR/Instruction.def"
3853 default:
3854 return false;
3855 }
3856 } else if (auto CV = dyn_cast<ConstantVector>(Val: &C)) {
3857 if (CV->getNumOperands() == 1)
3858 return translateCopy(U: C, V: *CV->getOperand(i_nocapture: 0), MIRBuilder&: *EntryBuilder);
3859 SmallVector<Register, 4> Ops;
3860 for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
3861 Ops.push_back(Elt: getOrCreateVReg(Val: *CV->getOperand(i_nocapture: i)));
3862 }
3863 EntryBuilder->buildBuildVector(Res: Reg, Ops);
3864 } else if (auto *BA = dyn_cast<BlockAddress>(Val: &C)) {
3865 EntryBuilder->buildBlockAddress(Res: Reg, BA);
3866 } else
3867 return false;
3868
3869 return true;
3870}
3871
3872bool IRTranslator::finalizeBasicBlock(const BasicBlock &BB,
3873 MachineBasicBlock &MBB) {
3874 for (auto &BTB : SL->BitTestCases) {
3875 // Emit header first, if it wasn't already emitted.
3876 if (!BTB.Emitted)
3877 emitBitTestHeader(B&: BTB, SwitchBB: BTB.Parent);
3878
3879 BranchProbability UnhandledProb = BTB.Prob;
3880 for (unsigned j = 0, ej = BTB.Cases.size(); j != ej; ++j) {
3881 UnhandledProb -= BTB.Cases[j].ExtraProb;
3882 // Set the current basic block to the mbb we wish to insert the code into
3883 MachineBasicBlock *MBB = BTB.Cases[j].ThisBB;
3884 // If all cases cover a contiguous range, it is not necessary to jump to
3885 // the default block after the last bit test fails. This is because the
3886 // range check during bit test header creation has guaranteed that every
3887 // case here doesn't go outside the range. In this case, there is no need
3888 // to perform the last bit test, as it will always be true. Instead, make
3889 // the second-to-last bit-test fall through to the target of the last bit
3890 // test, and delete the last bit test.
3891
3892 MachineBasicBlock *NextMBB;
3893 if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) && j + 2 == ej) {
3894 // Second-to-last bit-test with contiguous range: fall through to the
3895 // target of the final bit test.
3896 NextMBB = BTB.Cases[j + 1].TargetBB;
3897 } else if (j + 1 == ej) {
3898 // For the last bit test, fall through to Default.
3899 NextMBB = BTB.Default;
3900 } else {
3901 // Otherwise, fall through to the next bit test.
3902 NextMBB = BTB.Cases[j + 1].ThisBB;
3903 }
3904
3905 emitBitTestCase(BB&: BTB, NextMBB, BranchProbToNext: UnhandledProb, Reg: BTB.Reg, B&: BTB.Cases[j], SwitchBB: MBB);
3906
3907 if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) && j + 2 == ej) {
3908 // We need to record the replacement phi edge here that normally
3909 // happens in emitBitTestCase before we delete the case, otherwise the
3910 // phi edge will be lost.
3911 addMachineCFGPred(Edge: {BTB.Parent->getBasicBlock(),
3912 BTB.Cases[ej - 1].TargetBB->getBasicBlock()},
3913 NewPred: MBB);
3914 // Since we're not going to use the final bit test, remove it.
3915 BTB.Cases.pop_back();
3916 break;
3917 }
3918 }
3919 // This is "default" BB. We have two jumps to it. From "header" BB and from
3920 // last "case" BB, unless the latter was skipped.
3921 CFGEdge HeaderToDefaultEdge = {BTB.Parent->getBasicBlock(),
3922 BTB.Default->getBasicBlock()};
3923 addMachineCFGPred(Edge: HeaderToDefaultEdge, NewPred: BTB.Parent);
3924 if (!BTB.ContiguousRange) {
3925 addMachineCFGPred(Edge: HeaderToDefaultEdge, NewPred: BTB.Cases.back().ThisBB);
3926 }
3927 }
3928 SL->BitTestCases.clear();
3929
3930 for (auto &JTCase : SL->JTCases) {
3931 // Emit header first, if it wasn't already emitted.
3932 if (!JTCase.first.Emitted)
3933 emitJumpTableHeader(JT&: JTCase.second, JTH&: JTCase.first, HeaderBB: JTCase.first.HeaderBB);
3934
3935 emitJumpTable(JT&: JTCase.second, MBB: JTCase.second.MBB);
3936 }
3937 SL->JTCases.clear();
3938
3939 for (auto &SwCase : SL->SwitchCases)
3940 emitSwitchCase(CB&: SwCase, SwitchBB: &CurBuilder->getMBB(), MIB&: *CurBuilder);
3941 SL->SwitchCases.clear();
3942
3943 // Check if we need to generate stack-protector guard checks.
3944 StackProtector &SP = getAnalysis<StackProtector>();
3945 if (SP.shouldEmitSDCheck(BB)) {
3946 bool FunctionBasedInstrumentation =
3947 TLI->getSSPStackGuardCheck(M: *MF->getFunction().getParent(), Libcalls: *Libcalls);
3948 SPDescriptor.initialize(BB: &BB, MBB: &MBB, FunctionBasedInstrumentation);
3949 }
3950 // Handle stack protector.
3951 if (SPDescriptor.shouldEmitFunctionBasedCheckStackProtector()) {
3952 LLVM_DEBUG(dbgs() << "Unimplemented stack protector case\n");
3953 return false;
3954 } else if (SPDescriptor.shouldEmitStackProtector()) {
3955 MachineBasicBlock *ParentMBB = SPDescriptor.getParentMBB();
3956 MachineBasicBlock *SuccessMBB = SPDescriptor.getSuccessMBB();
3957
3958 // Find the split point to split the parent mbb. At the same time copy all
3959 // physical registers used in the tail of parent mbb into virtual registers
3960 // before the split point and back into physical registers after the split
3961 // point. This prevents us needing to deal with Live-ins and many other
3962 // register allocation issues caused by us splitting the parent mbb. The
3963 // register allocator will clean up said virtual copies later on.
3964 MachineBasicBlock::iterator SplitPoint = findSplitPointForStackProtector(
3965 BB: ParentMBB, TII: *MF->getSubtarget().getInstrInfo());
3966
3967 // Splice the terminator of ParentMBB into SuccessMBB.
3968 SuccessMBB->splice(Where: SuccessMBB->end(), Other: ParentMBB, From: SplitPoint,
3969 To: ParentMBB->end());
3970
3971 // Add compare/jump on neq/jump to the parent BB.
3972 if (!emitSPDescriptorParent(SPD&: SPDescriptor, ParentBB: ParentMBB))
3973 return false;
3974
3975 // CodeGen Failure MBB if we have not codegened it yet.
3976 MachineBasicBlock *FailureMBB = SPDescriptor.getFailureMBB();
3977 if (FailureMBB->empty()) {
3978 if (!emitSPDescriptorFailure(SPD&: SPDescriptor, FailureBB: FailureMBB))
3979 return false;
3980 }
3981
3982 // Clear the Per-BB State.
3983 SPDescriptor.resetPerBBState();
3984 }
3985 return true;
3986}
3987
3988bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
3989 MachineBasicBlock *ParentBB) {
3990 CurBuilder->setInsertPt(MBB&: *ParentBB, II: ParentBB->end());
3991 // First create the loads to the guard/stack slot for the comparison.
3992 Type *PtrIRTy = PointerType::getUnqual(C&: MF->getFunction().getContext());
3993 const LLT PtrTy = getLLTForType(Ty&: *PtrIRTy, DL: *DL);
3994 LLT PtrMemTy = getLLTForMVT(Ty: TLI->getPointerMemTy(DL: *DL));
3995
3996 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
3997 int FI = MFI.getStackProtectorIndex();
3998
3999 Register Guard;
4000 Register StackSlotPtr = CurBuilder->buildFrameIndex(Res: PtrTy, Idx: FI).getReg(Idx: 0);
4001 const Module &M = *ParentBB->getParent()->getFunction().getParent();
4002 Align Align = DL->getPrefTypeAlign(Ty: PointerType::getUnqual(C&: M.getContext()));
4003
4004 // Generate code to load the content of the guard slot.
4005 Register GuardVal =
4006 CurBuilder
4007 ->buildLoad(Res: PtrMemTy, Addr: StackSlotPtr,
4008 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), Alignment: Align,
4009 MMOFlags: MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile)
4010 .getReg(Idx: 0);
4011
4012 if (TLI->useStackGuardXorFP()) {
4013 LLVM_DEBUG(dbgs() << "Stack protector xor'ing with FP not yet implemented");
4014 return false;
4015 }
4016
4017 // Retrieve guard check function, nullptr if instrumentation is inlined.
4018 if (const Function *GuardCheckFn = TLI->getSSPStackGuardCheck(M, Libcalls: *Libcalls)) {
4019 // This path is currently untestable on GlobalISel, since the only platform
4020 // that needs this seems to be Windows, and we fall back on that currently.
4021 // The code still lives here in case that changes.
4022 // Silence warning about unused variable until the code below that uses
4023 // 'GuardCheckFn' is enabled.
4024 (void)GuardCheckFn;
4025 return false;
4026#if 0
4027 // The target provides a guard check function to validate the guard value.
4028 // Generate a call to that function with the content of the guard slot as
4029 // argument.
4030 FunctionType *FnTy = GuardCheckFn->getFunctionType();
4031 assert(FnTy->getNumParams() == 1 && "Invalid function signature");
4032 ISD::ArgFlagsTy Flags;
4033 if (GuardCheckFn->hasAttribute(1, Attribute::AttrKind::InReg))
4034 Flags.setInReg();
4035 CallLowering::ArgInfo GuardArgInfo(
4036 {GuardVal, FnTy->getParamType(0), {Flags}});
4037
4038 CallLowering::CallLoweringInfo Info;
4039 Info.OrigArgs.push_back(GuardArgInfo);
4040 Info.CallConv = GuardCheckFn->getCallingConv();
4041 Info.Callee = MachineOperand::CreateGA(GuardCheckFn, 0);
4042 Info.OrigRet = {Register(), FnTy->getReturnType()};
4043 if (!CLI->lowerCall(MIRBuilder, Info)) {
4044 LLVM_DEBUG(dbgs() << "Failed to lower call to stack protector check\n");
4045 return false;
4046 }
4047 return true;
4048#endif
4049 }
4050
4051 // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
4052 // Otherwise, emit a volatile load to retrieve the stack guard value.
4053 if (TLI->useLoadStackGuardNode(M: *ParentBB->getBasicBlock()->getModule())) {
4054 Guard =
4055 MRI->createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: PtrTy.getSizeInBits()));
4056 getStackGuard(DstReg: Guard, MIRBuilder&: *CurBuilder);
4057 } else {
4058 // TODO: test using android subtarget when we support @llvm.thread.pointer.
4059 const Value *IRGuard = TLI->getSDagStackGuard(M, Libcalls: *Libcalls);
4060 Register GuardPtr = getOrCreateVReg(Val: *IRGuard);
4061
4062 Guard = CurBuilder
4063 ->buildLoad(Res: PtrMemTy, Addr: GuardPtr,
4064 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), Alignment: Align,
4065 MMOFlags: MachineMemOperand::MOLoad |
4066 MachineMemOperand::MOVolatile)
4067 .getReg(Idx: 0);
4068 }
4069
4070 // Perform the comparison.
4071 auto Cmp =
4072 CurBuilder->buildICmp(Pred: CmpInst::ICMP_NE, Res: LLT::scalar(SizeInBits: 1), Op0: Guard, Op1: GuardVal);
4073 // If the guard/stackslot do not equal, branch to failure MBB.
4074 CurBuilder->buildBrCond(Tst: Cmp, Dest&: *SPD.getFailureMBB());
4075 // Otherwise branch to success MBB.
4076 CurBuilder->buildBr(Dest&: *SPD.getSuccessMBB());
4077 return true;
4078}
4079
4080bool IRTranslator::emitSPDescriptorFailure(StackProtectorDescriptor &SPD,
4081 MachineBasicBlock *FailureBB) {
4082 const RTLIB::LibcallImpl LibcallImpl =
4083 Libcalls->getLibcallImpl(Call: RTLIB::STACKPROTECTOR_CHECK_FAIL);
4084 if (LibcallImpl == RTLIB::Unsupported)
4085 return false;
4086
4087 CurBuilder->setInsertPt(MBB&: *FailureBB, II: FailureBB->end());
4088
4089 CallLowering::CallLoweringInfo Info;
4090 Info.CallConv = Libcalls->getLibcallImplCallingConv(Call: LibcallImpl);
4091
4092 StringRef LibcallName =
4093 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: LibcallImpl);
4094 Info.Callee = MachineOperand::CreateES(SymName: LibcallName.data());
4095 Info.OrigRet = {Register(), Type::getVoidTy(C&: MF->getFunction().getContext()),
4096 0};
4097 if (!CLI->lowerCall(MIRBuilder&: *CurBuilder, Info)) {
4098 LLVM_DEBUG(dbgs() << "Failed to lower call to stack protector fail\n");
4099 return false;
4100 }
4101
4102 // Emit a trap instruction if we are required to do so.
4103 const TargetOptions &TargetOpts = TLI->getTargetMachine().Options;
4104 if (TargetOpts.TrapUnreachable && !TargetOpts.NoTrapAfterNoreturn)
4105 CurBuilder->buildInstr(Opcode: TargetOpcode::G_TRAP);
4106
4107 return true;
4108}
4109
4110void IRTranslator::finalizeFunction() {
4111 // Release the memory used by the different maps we
4112 // needed during the translation.
4113 PendingPHIs.clear();
4114 VMap.reset();
4115 FrameIndices.clear();
4116 MachinePreds.clear();
4117 // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
4118 // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
4119 // destroying it twice (in ~IRTranslator() and ~LLVMContext())
4120 EntryBuilder.reset();
4121 CurBuilder.reset();
4122 FuncInfo.clear();
4123 SPDescriptor.resetPerFunctionState();
4124}
4125
4126/// Returns true if a BasicBlock \p BB within a variadic function contains a
4127/// variadic musttail call.
4128static bool checkForMustTailInVarArgFn(bool IsVarArg, const BasicBlock &BB) {
4129 if (!IsVarArg)
4130 return false;
4131
4132 // Walk the block backwards, because tail calls usually only appear at the end
4133 // of a block.
4134 return llvm::any_of(Range: llvm::reverse(C: BB), P: [](const Instruction &I) {
4135 const auto *CI = dyn_cast<CallInst>(Val: &I);
4136 return CI && CI->isMustTailCall();
4137 });
4138}
4139
4140bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
4141 MF = &CurMF;
4142 const Function &F = MF->getFunction();
4143 ORE = std::make_unique<OptimizationRemarkEmitter>(args: &F);
4144 CLI = MF->getSubtarget().getCallLowering();
4145
4146 if (CLI->fallBackToDAGISel(MF: *MF)) {
4147 OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
4148 F.getSubprogram(), &F.getEntryBlock());
4149 R << "unable to lower function: "
4150 << ore::NV("Prototype", F.getFunctionType());
4151
4152 reportTranslationError(MF&: *MF, ORE&: *ORE, R);
4153 return false;
4154 }
4155
4156 GISelCSEAnalysisWrapper &Wrapper =
4157 getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
4158 // Set the CSEConfig and run the analysis.
4159 GISelCSEInfo *CSEInfo = nullptr;
4160 TPC = &getAnalysis<TargetPassConfig>();
4161
4162 bool EnableCSE = EnableCSEInIRTranslator.getNumOccurrences()
4163 ? EnableCSEInIRTranslator
4164 : TPC->isGISelCSEEnabled();
4165
4166 const TargetSubtargetInfo &Subtarget = MF->getSubtarget();
4167 TLI = Subtarget.getTargetLowering();
4168
4169 if (EnableCSE) {
4170 EntryBuilder = std::make_unique<CSEMIRBuilder>(args&: CurMF);
4171 CSEInfo = &Wrapper.get(CSEOpt: TPC->getCSEConfig());
4172 EntryBuilder->setCSEInfo(CSEInfo);
4173 CurBuilder = std::make_unique<CSEMIRBuilder>(args&: CurMF);
4174 CurBuilder->setCSEInfo(CSEInfo);
4175 } else {
4176 EntryBuilder = std::make_unique<MachineIRBuilder>();
4177 CurBuilder = std::make_unique<MachineIRBuilder>();
4178 }
4179 CLI = Subtarget.getCallLowering();
4180 CurBuilder->setMF(*MF);
4181 EntryBuilder->setMF(*MF);
4182 MRI = &MF->getRegInfo();
4183 DL = &F.getDataLayout();
4184 const TargetMachine &TM = MF->getTarget();
4185 TM.resetTargetOptions(F);
4186 EnableOpts = OptLevel != CodeGenOptLevel::None && !skipFunction(F);
4187 FuncInfo.MF = MF;
4188 if (EnableOpts) {
4189 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
4190 FuncInfo.BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
4191 } else {
4192 AA = nullptr;
4193 FuncInfo.BPI = nullptr;
4194 }
4195
4196 AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(
4197 F&: MF->getFunction());
4198 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
4199 Libcalls = &getAnalysis<LibcallLoweringInfoWrapper>().getLibcallLowering(
4200 M: *F.getParent(), Subtarget);
4201
4202 FuncInfo.CanLowerReturn = CLI->checkReturnTypeForCallConv(MF&: *MF);
4203
4204 SL = std::make_unique<GISelSwitchLowering>(args: this, args&: FuncInfo);
4205 SL->init(tli: *TLI, tm: TM, dl: *DL);
4206
4207 assert(PendingPHIs.empty() && "stale PHIs");
4208
4209 // Targets which want to use big endian can enable it using
4210 // enableBigEndian()
4211 if (!DL->isLittleEndian() && !CLI->enableBigEndian()) {
4212 // Currently we don't properly handle big endian code.
4213 OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
4214 F.getSubprogram(), &F.getEntryBlock());
4215 R << "unable to translate in big endian mode";
4216 reportTranslationError(MF&: *MF, ORE&: *ORE, R);
4217 return false;
4218 }
4219
4220 // Release the per-function state when we return, whether we succeeded or not.
4221 llvm::scope_exit FinalizeOnReturn([this]() { finalizeFunction(); });
4222
4223 // Setup a separate basic-block for the arguments and constants
4224 MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
4225 MF->push_back(MBB: EntryBB);
4226 EntryBuilder->setMBB(*EntryBB);
4227
4228 DebugLoc DbgLoc = F.getEntryBlock().getFirstNonPHIIt()->getDebugLoc();
4229 SwiftError.setFunction(CurMF);
4230 SwiftError.createEntriesInEntryBlock(DbgLoc);
4231
4232 bool IsVarArg = F.isVarArg();
4233 bool HasMustTailInVarArgFn = false;
4234
4235 // Create all blocks, in IR order, to preserve the layout.
4236 FuncInfo.MBBMap.resize(N: F.getMaxBlockNumber());
4237 for (const BasicBlock &BB: F) {
4238 auto *&MBB = FuncInfo.MBBMap[BB.getNumber()];
4239
4240 MBB = MF->CreateMachineBasicBlock(BB: &BB);
4241 MF->push_back(MBB);
4242
4243 // Only mark the block if the BlockAddress actually has users. The
4244 // hasAddressTaken flag may be stale if the BlockAddress was optimized away
4245 // but the constant still exists in the uniquing table.
4246 if (BB.hasAddressTaken()) {
4247 if (BlockAddress *BA = BlockAddress::lookup(BB: &BB))
4248 if (!BA->hasZeroLiveUses())
4249 MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB));
4250 }
4251
4252 if (!HasMustTailInVarArgFn)
4253 HasMustTailInVarArgFn = checkForMustTailInVarArgFn(IsVarArg, BB);
4254 }
4255
4256 MF->getFrameInfo().setHasMustTailInVarArgFunc(HasMustTailInVarArgFn);
4257
4258 // Make our arguments/constants entry block fallthrough to the IR entry block.
4259 EntryBB->addSuccessor(Succ: &getMBB(BB: F.front()));
4260
4261 // Lower the actual args into this basic block.
4262 SmallVector<ArrayRef<Register>, 8> VRegArgs;
4263 for (const Argument &Arg: F.args()) {
4264 if (DL->getTypeStoreSize(Ty: Arg.getType()).isZero())
4265 continue; // Don't handle zero sized types.
4266 ArrayRef<Register> VRegs = getOrCreateVRegs(Val: Arg);
4267 VRegArgs.push_back(Elt: VRegs);
4268
4269 if (Arg.hasSwiftErrorAttr()) {
4270 assert(VRegs.size() == 1 && "Too many vregs for Swift error");
4271 SwiftError.setCurrentVReg(MBB: EntryBB, SwiftError.getFunctionArg(), VRegs[0]);
4272 }
4273 }
4274
4275 if (!CLI->lowerFormalArguments(MIRBuilder&: *EntryBuilder, F, VRegs: VRegArgs, FLI&: FuncInfo)) {
4276 OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
4277 F.getSubprogram(), &F.getEntryBlock());
4278 R << "unable to lower arguments: "
4279 << ore::NV("Prototype", F.getFunctionType());
4280 reportTranslationError(MF&: *MF, ORE&: *ORE, R);
4281 return false;
4282 }
4283
4284 // Need to visit defs before uses when translating instructions.
4285 GISelObserverWrapper WrapperObserver;
4286 if (EnableCSE && CSEInfo)
4287 WrapperObserver.addObserver(O: CSEInfo);
4288 {
4289 ReversePostOrderTraversal<const Function *> RPOT(&F);
4290#ifndef NDEBUG
4291 DILocationVerifier Verifier;
4292 WrapperObserver.addObserver(&Verifier);
4293#endif // ifndef NDEBUG
4294 RAIIMFObsDelInstaller ObsInstall(*MF, WrapperObserver);
4295 for (const BasicBlock *BB : RPOT) {
4296 MachineBasicBlock &MBB = getMBB(BB: *BB);
4297 // Set the insertion point of all the following translations to
4298 // the end of this basic block.
4299 CurBuilder->setMBB(MBB);
4300 HasTailCall = false;
4301 for (const Instruction &Inst : *BB) {
4302 // If we translated a tail call in the last step, then we know
4303 // everything after the call is either a return, or something that is
4304 // handled by the call itself. (E.g. a lifetime marker or assume
4305 // intrinsic.) In this case, we should stop translating the block and
4306 // move on.
4307 if (HasTailCall)
4308 break;
4309#ifndef NDEBUG
4310 Verifier.setCurrentInst(&Inst);
4311#endif // ifndef NDEBUG
4312
4313 // Translate any debug-info attached to the instruction.
4314 translateDbgInfo(Inst, MIRBuilder&: *CurBuilder);
4315
4316 if (translate(Inst))
4317 continue;
4318
4319 OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
4320 Inst.getDebugLoc(), BB);
4321 R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
4322
4323 if (ORE->allowExtraAnalysis(PassName: "gisel-irtranslator")) {
4324 std::string InstStrStorage;
4325 raw_string_ostream InstStr(InstStrStorage);
4326 InstStr << Inst;
4327
4328 R << ": '" << InstStrStorage << "'";
4329 }
4330
4331 reportTranslationError(MF&: *MF, ORE&: *ORE, R);
4332 return false;
4333 }
4334
4335 if (!finalizeBasicBlock(BB: *BB, MBB)) {
4336 OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
4337 BB->getTerminator()->getDebugLoc(), BB);
4338 R << "unable to translate basic block";
4339 reportTranslationError(MF&: *MF, ORE&: *ORE, R);
4340 return false;
4341 }
4342 }
4343#ifndef NDEBUG
4344 WrapperObserver.removeObserver(&Verifier);
4345#endif
4346 }
4347
4348 finishPendingPhis();
4349
4350 SwiftError.propagateVRegs();
4351
4352 // Merge the argument lowering and constants block with its single
4353 // successor, the LLVM-IR entry block. We want the basic block to
4354 // be maximal.
4355 assert(EntryBB->succ_size() == 1 &&
4356 "Custom BB used for lowering should have only one successor");
4357 // Get the successor of the current entry block.
4358 MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
4359 assert(NewEntryBB.pred_size() == 1 &&
4360 "LLVM-IR entry block has a predecessor!?");
4361 // Move all the instruction from the current entry block to the
4362 // new entry block.
4363 NewEntryBB.splice(Where: NewEntryBB.begin(), Other: EntryBB, From: EntryBB->begin(),
4364 To: EntryBB->end());
4365
4366 // Update the live-in information for the new entry block.
4367 for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
4368 NewEntryBB.addLiveIn(RegMaskPair: LiveIn);
4369 NewEntryBB.sortUniqueLiveIns();
4370
4371 // Get rid of the now empty basic block.
4372 EntryBB->removeSuccessor(Succ: &NewEntryBB);
4373 MF->remove(MBBI: EntryBB);
4374 MF->deleteMachineBasicBlock(MBB: EntryBB);
4375
4376 assert(&MF->front() == &NewEntryBB &&
4377 "New entry wasn't next in the list of basic block!");
4378
4379 // Initialize stack protector information.
4380 StackProtector &SP = getAnalysis<StackProtector>();
4381 SP.copyToMachineFrameInfo(MFI&: MF->getFrameInfo());
4382
4383 return false;
4384}
4385