1//===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the InstructionSelect class.
10//===----------------------------------------------------------------------===//
11
12#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
13#include "llvm/ADT/PostOrderIterator.h"
14#include "llvm/ADT/ScopeExit.h"
15#include "llvm/ADT/SetVector.h"
16#include "llvm/Analysis/LazyBlockFrequencyInfo.h"
17#include "llvm/Analysis/ProfileSummaryInfo.h"
18#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
19#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
20#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
21#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
22#include "llvm/CodeGen/GlobalISel/Utils.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/TargetLowering.h"
27#include "llvm/CodeGen/TargetOpcodes.h"
28#include "llvm/CodeGen/TargetPassConfig.h"
29#include "llvm/CodeGen/TargetSubtargetInfo.h"
30#include "llvm/Config/config.h"
31#include "llvm/IR/Function.h"
32#include "llvm/MC/TargetRegistry.h"
33#include "llvm/Support/CodeGenCoverage.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/DebugCounter.h"
36#include "llvm/Target/TargetMachine.h"
37
38#define DEBUG_TYPE "instruction-select"
39
40using namespace llvm;
41
42DEBUG_COUNTER(GlobalISelCounter, "globalisel",
43 "Controls whether to select function with GlobalISel");
44
45#ifdef LLVM_GISEL_COV_PREFIX
46static cl::opt<std::string>
47 CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
48 cl::desc("Record GlobalISel rule coverage files of this "
49 "prefix if instrumentation was generated"));
50#else
51static const std::string CoveragePrefix;
52#endif
53
54char InstructionSelect::ID = 0;
55INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
56 "Select target instructions out of generic instructions",
57 false, false)
58INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
59INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
60INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
61INITIALIZE_PASS_DEPENDENCY(LazyBlockFrequencyInfoPass)
62INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
63 "Select target instructions out of generic instructions",
64 false, false)
65
66InstructionSelect::InstructionSelect(CodeGenOptLevel OL, char &PassID)
67 : MachineFunctionPass(PassID), OptLevel(OL) {}
68
69/// This class observes instruction insertions/removals.
70/// InstructionSelect stores an iterator of the instruction prior to the one
71/// that is currently being selected to determine which instruction to select
72/// next. Previously this meant that selecting multiple instructions at once was
73/// illegal behavior due to potential invalidation of this iterator. This is
74/// a non-obvious limitation for selector implementers. Therefore, to allow
75/// deletion of arbitrary instructions, we detect this case and continue
76/// selection with the predecessor of the deleted instruction.
77class InstructionSelect::MIIteratorMaintainer : public GISelChangeObserver {
78#ifndef NDEBUG
79 SmallSetVector<const MachineInstr *, 32> CreatedInstrs;
80#endif
81public:
82 MachineBasicBlock::reverse_iterator MII;
83
84 void changingInstr(MachineInstr &MI) override {
85 llvm_unreachable("InstructionSelect does not track changed instructions!");
86 }
87 void changedInstr(MachineInstr &MI) override {
88 llvm_unreachable("InstructionSelect does not track changed instructions!");
89 }
90
91 void createdInstr(MachineInstr &MI) override {
92 LLVM_DEBUG(dbgs() << "Creating: " << MI; CreatedInstrs.insert(&MI));
93 }
94
95 void erasingInstr(MachineInstr &MI) override {
96 LLVM_DEBUG(dbgs() << "Erasing: " << MI; CreatedInstrs.remove(&MI));
97 if (MII.getInstrIterator().getNodePtr() == &MI) {
98 // If the iterator points to the MI that will be erased (i.e. the MI prior
99 // to the MI that is currently being selected), the iterator would be
100 // invalidated. Continue selection with its predecessor.
101 ++MII;
102 LLVM_DEBUG(dbgs() << "Instruction removal updated iterator.\n");
103 }
104 }
105
106 void reportFullyCreatedInstrs() {
107 LLVM_DEBUG({
108 if (CreatedInstrs.empty()) {
109 dbgs() << "Created no instructions.\n";
110 } else {
111 dbgs() << "Created:\n";
112 for (const auto *MI : CreatedInstrs) {
113 dbgs() << " " << *MI;
114 }
115 CreatedInstrs.clear();
116 }
117 });
118 }
119};
120
121void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
122 AU.addRequired<TargetPassConfig>();
123 AU.addRequired<GISelValueTrackingAnalysisLegacy>();
124 AU.addPreserved<GISelValueTrackingAnalysisLegacy>();
125
126 if (OptLevel != CodeGenOptLevel::None) {
127 AU.addRequired<ProfileSummaryInfoWrapperPass>();
128 LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
129 }
130 getSelectionDAGFallbackAnalysisUsage(AU);
131 MachineFunctionPass::getAnalysisUsage(AU);
132}
133
134bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
135 // If the ISel pipeline failed, do not bother running that pass.
136 if (MF.getProperties().hasFailedISel())
137 return false;
138
139 ISel = MF.getSubtarget().getInstructionSelector();
140
141 // FIXME: Properly override OptLevel in TargetMachine. See OptLevelChanger
142 CodeGenOptLevel OldOptLevel = OptLevel;
143 llvm::scope_exit RestoreOptLevel([=]() { OptLevel = OldOptLevel; });
144 OptLevel = MF.getFunction().hasOptNone() ? CodeGenOptLevel::None
145 : MF.getTarget().getOptLevel();
146
147 VT = &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
148 if (OptLevel != CodeGenOptLevel::None) {
149 PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
150 if (PSI && PSI->hasProfileSummary())
151 BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
152 }
153
154 return selectMachineFunction(MF);
155}
156
157bool InstructionSelect::selectMachineFunction(MachineFunction &MF) {
158 LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
159 assert(ISel && "Cannot work without InstructionSelector");
160
161 CodeGenCoverage CoverageInfo;
162 ISel->setupMF(mf&: MF, vt: VT, covinfo: &CoverageInfo, psi: PSI, bfi: BFI);
163
164 // An optimization remark emitter. Used to report failures.
165 MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
166 ISel->MORE = &MORE;
167
168 // FIXME: There are many other MF/MFI fields we need to initialize.
169
170 MachineRegisterInfo &MRI = MF.getRegInfo();
171#ifndef NDEBUG
172 // Check that our input is fully legal: we require the function to have the
173 // Legalized property, so it should be.
174 // FIXME: This should be in the MachineVerifier, as the RegBankSelected
175 // property check already is.
176 if (!DisableGISelLegalityCheck)
177 if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
178 reportGISelFailure(MF, MORE, "gisel-select", "instruction is not legal",
179 *MI);
180 return false;
181 }
182 // FIXME: We could introduce new blocks and will need to fix the outer loop.
183 // Until then, keep track of the number of blocks to assert that we don't.
184 const size_t NumBlocks = MF.size();
185#endif
186 // Keep track of selected blocks, so we can delete unreachable ones later.
187 DenseSet<MachineBasicBlock *> SelectedBlocks;
188
189 {
190 // Observe IR insertions and removals during selection.
191 // We only install a MachineFunction::Delegate instead of a
192 // GISelChangeObserver, because we do not want notifications about changed
193 // instructions. This prevents significant compile-time regressions from
194 // e.g. constrainOperandRegClass().
195 GISelObserverWrapper AllObservers;
196 MIIteratorMaintainer MIIMaintainer;
197 AllObservers.addObserver(O: &MIIMaintainer);
198 RAIIDelegateInstaller DelInstaller(MF, &AllObservers);
199 ISel->AllObservers = &AllObservers;
200
201 for (MachineBasicBlock *MBB : post_order(G: &MF)) {
202 ISel->CurMBB = MBB;
203 SelectedBlocks.insert(V: MBB);
204
205 // Select instructions in reverse block order.
206 MIIMaintainer.MII = MBB->rbegin();
207 for (auto End = MBB->rend(); MIIMaintainer.MII != End;) {
208 MachineInstr &MI = *MIIMaintainer.MII;
209 // Increment early to skip instructions inserted by select().
210 ++MIIMaintainer.MII;
211
212 LLVM_DEBUG(dbgs() << "\nSelect: " << MI);
213 if (!selectInstr(MI)) {
214 LLVM_DEBUG(dbgs() << "Selection failed!\n";
215 MIIMaintainer.reportFullyCreatedInstrs());
216 reportGISelFailure(MF, MORE, PassName: "gisel-select", Msg: "cannot select", MI);
217 return false;
218 }
219 LLVM_DEBUG(MIIMaintainer.reportFullyCreatedInstrs());
220 }
221 }
222 }
223
224 for (MachineBasicBlock &MBB : MF) {
225 if (MBB.empty())
226 continue;
227
228 if (!SelectedBlocks.contains(V: &MBB)) {
229 // This is an unreachable block and therefore hasn't been selected, since
230 // the main selection loop above uses a postorder block traversal.
231 // We delete all the instructions in this block since it's unreachable.
232 MBB.clear();
233 // Don't delete the block in case the block has it's address taken or is
234 // still being referenced by a phi somewhere.
235 continue;
236 }
237 // Try to find redundant copies b/w vregs of the same register class.
238 for (auto MII = MBB.rbegin(), End = MBB.rend(); MII != End;) {
239 MachineInstr &MI = *MII;
240 ++MII;
241
242 if (MI.getOpcode() != TargetOpcode::COPY)
243 continue;
244 Register SrcReg = MI.getOperand(i: 1).getReg();
245 Register DstReg = MI.getOperand(i: 0).getReg();
246 if (SrcReg.isVirtual() && DstReg.isVirtual()) {
247 auto SrcRC = MRI.getRegClass(Reg: SrcReg);
248 auto DstRC = MRI.getRegClass(Reg: DstReg);
249 if (SrcRC == DstRC) {
250 MRI.replaceRegWith(FromReg: DstReg, ToReg: SrcReg);
251 MI.eraseFromParent();
252 }
253 }
254 }
255 }
256
257#ifndef NDEBUG
258 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
259 // Now that selection is complete, there are no more generic vregs. Verify
260 // that the size of the now-constrained vreg is unchanged and that it has a
261 // register class.
262 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
263 Register VReg = Register::index2VirtReg(I);
264
265 MachineInstr *MI = nullptr;
266 if (!MRI.def_empty(VReg))
267 MI = &*MRI.def_instr_begin(VReg);
268 else if (!MRI.use_empty(VReg)) {
269 MI = &*MRI.use_instr_begin(VReg);
270 // Debug value instruction is permitted to use undefined vregs.
271 if (MI->isDebugValue())
272 continue;
273 }
274 if (!MI)
275 continue;
276
277 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
278 if (!RC) {
279 reportGISelFailure(MF, MORE, "gisel-select",
280 "VReg has no regclass after selection", *MI);
281 return false;
282 }
283
284 const LLT Ty = MRI.getType(VReg);
285 if (Ty.isValid() &&
286 TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {
287 reportGISelFailure(
288 MF, MORE, "gisel-select",
289 "VReg's low-level type and register class have different sizes", *MI);
290 return false;
291 }
292 }
293
294 if (MF.size() != NumBlocks) {
295 MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
296 MF.getFunction().getSubprogram(),
297 /*MBB=*/nullptr);
298 R << "inserting blocks is not supported yet";
299 reportGISelFailure(MF, MORE, R);
300 return false;
301 }
302#endif
303
304 if (!DebugCounter::shouldExecute(Counter&: GlobalISelCounter)) {
305 dbgs() << "Falling back for function " << MF.getName() << "\n";
306 MF.getProperties().setFailedISel();
307 return false;
308 }
309
310 // Determine if there are any calls in this machine function. Ported from
311 // SelectionDAG.
312 MachineFrameInfo &MFI = MF.getFrameInfo();
313 for (const auto &MBB : MF) {
314 if (MFI.hasCalls() && MF.hasInlineAsm())
315 break;
316
317 for (const auto &MI : MBB) {
318 if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
319 MFI.setHasCalls(true);
320 if (MI.isInlineAsm())
321 MF.setHasInlineAsm(true);
322 }
323 }
324
325 // FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
326 auto &TLI = *MF.getSubtarget().getTargetLowering();
327 TLI.finalizeLowering(MF);
328
329 LLVM_DEBUG({
330 dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
331 for (auto RuleID : CoverageInfo.covered())
332 dbgs() << " id" << RuleID;
333 dbgs() << "\n\n";
334 });
335 CoverageInfo.emit(FilePrefix: CoveragePrefix,
336 BackendName: TLI.getTargetMachine().getTarget().getBackendName());
337
338 // If we successfully selected the function nothing is going to use the vreg
339 // types after us (otherwise MIRPrinter would need them). Make sure the types
340 // disappear.
341 MRI.clearVirtRegTypes();
342
343 // FIXME: Should we accurately track changes?
344 return true;
345}
346
347bool InstructionSelect::selectInstr(MachineInstr &MI) {
348 MachineRegisterInfo &MRI = ISel->MF->getRegInfo();
349
350 // We could have folded this instruction away already, making it dead.
351 // If so, erase it.
352 if (isTriviallyDead(MI, MRI)) {
353 LLVM_DEBUG(dbgs() << "Is dead.\n");
354 salvageDebugInfo(MRI, MI);
355 MI.eraseFromParent();
356 return true;
357 }
358
359 // Eliminate hints or G_CONSTANT_FOLD_BARRIER.
360 if (isPreISelGenericOptimizationHint(Opcode: MI.getOpcode()) ||
361 MI.getOpcode() == TargetOpcode::G_CONSTANT_FOLD_BARRIER) {
362 auto [DstReg, SrcReg] = MI.getFirst2Regs();
363
364 // At this point, the destination register class of the op may have
365 // been decided.
366 //
367 // Propagate that through to the source register.
368 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(Reg: DstReg);
369 const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(Reg: SrcReg);
370 if (DstRC && SrcRC)
371 MRI.constrainRegClass(Reg: SrcReg, RC: DstRC);
372 else if (DstRC)
373 MRI.setRegClass(Reg: SrcReg, RC: DstRC);
374 MI.eraseFromParent();
375 MRI.replaceRegWith(FromReg: DstReg, ToReg: SrcReg);
376 return true;
377 }
378
379 if (MI.getOpcode() == TargetOpcode::G_INVOKE_REGION_START) {
380 MI.eraseFromParent();
381 return true;
382 }
383
384 return ISel->select(I&: MI);
385}
386