1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/Hashing.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallBitVector.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/Analysis/AliasAnalysis.h"
20#include "llvm/Analysis/MemoryLocation.h"
21#include "llvm/CodeGen/LiveRegUnits.h"
22#include "llvm/CodeGen/MachineBasicBlock.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineInstrBundle.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/Register.h"
33#include "llvm/CodeGen/StackMaps.h"
34#include "llvm/CodeGen/TargetInstrInfo.h"
35#include "llvm/CodeGen/TargetRegisterInfo.h"
36#include "llvm/CodeGen/TargetSubtargetInfo.h"
37#include "llvm/CodeGenTypes/LowLevelType.h"
38#include "llvm/IR/Constants.h"
39#include "llvm/IR/DebugInfoMetadata.h"
40#include "llvm/IR/DebugLoc.h"
41#include "llvm/IR/Function.h"
42#include "llvm/IR/InlineAsm.h"
43#include "llvm/IR/Instructions.h"
44#include "llvm/IR/LLVMContext.h"
45#include "llvm/IR/Metadata.h"
46#include "llvm/IR/Module.h"
47#include "llvm/IR/ModuleSlotTracker.h"
48#include "llvm/IR/Operator.h"
49#include "llvm/MC/MCInstrDesc.h"
50#include "llvm/MC/MCRegisterInfo.h"
51#include "llvm/Support/Casting.h"
52#include "llvm/Support/Compiler.h"
53#include "llvm/Support/Debug.h"
54#include "llvm/Support/ErrorHandling.h"
55#include "llvm/Support/FormattedStream.h"
56#include "llvm/Support/raw_ostream.h"
57#include "llvm/Target/TargetMachine.h"
58#include <algorithm>
59#include <cassert>
60#include <cstdint>
61#include <cstring>
62#include <utility>
63
64using namespace llvm;
65
66static cl::opt<bool>
67 PrintMIAddrs("print-mi-addrs", cl::Hidden,
68 cl::desc("Print addresses of MachineInstrs when dumping"));
69
70static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
71 if (const MachineBasicBlock *MBB = MI.getParent())
72 if (const MachineFunction *MF = MBB->getParent())
73 return MF;
74 return nullptr;
75}
76
77// Try to crawl up to the machine function and get TRI/MRI/TII from it.
78static void tryToGetTargetInfo(const MachineInstr &MI,
79 const TargetRegisterInfo *&TRI,
80 const MachineRegisterInfo *&MRI,
81 const TargetInstrInfo *&TII) {
82
83 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
84 TRI = MF->getSubtarget().getRegisterInfo();
85 MRI = &MF->getRegInfo();
86 TII = MF->getSubtarget().getInstrInfo();
87 }
88}
89
90void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
91 for (MCPhysReg ImpDef : MCID->implicit_defs())
92 addOperand(MF, Op: MachineOperand::CreateReg(Reg: ImpDef, isDef: true, isImp: true));
93 for (MCPhysReg ImpUse : MCID->implicit_uses())
94 addOperand(MF, Op: MachineOperand::CreateReg(Reg: ImpUse, isDef: false, isImp: true));
95}
96
97/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
98/// implicit operands. It reserves space for the number of operands specified by
99/// the MCInstrDesc.
100MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
101 DebugLoc DL, bool NoImp)
102 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
103 Opcode(TID.Opcode), DebugInstrNum(0), DbgLoc(std::move(DL)) {
104 // Reserve space for the expected number of operands.
105 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() +
106 MCID->implicit_uses().size()) {
107 CapOperands = OperandCapacity::get(N: NumOps);
108 Operands = MF.allocateOperandArray(Cap: CapOperands);
109 }
110
111 if (!NoImp)
112 addImplicitDefUseOperands(MF);
113}
114
115/// MachineInstr ctor - Copies MachineInstr arg exactly.
116/// Does not copy the number from debug instruction numbering, to preserve
117/// uniqueness.
118MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
119 : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0),
120 Opcode(MI.getOpcode()), DebugInstrNum(0), Info(MI.Info),
121 DbgLoc(MI.getDebugLoc()) {
122 CapOperands = OperandCapacity::get(N: MI.getNumOperands());
123 Operands = MF.allocateOperandArray(Cap: CapOperands);
124
125 // Copy operands.
126 for (const MachineOperand &MO : MI.operands())
127 addOperand(MF, Op: MO);
128
129 // Replicate ties between the operands, which addOperand was not
130 // able to do reliably.
131 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
132 MachineOperand &NewMO = getOperand(i);
133 const MachineOperand &OrigMO = MI.getOperand(i);
134 NewMO.TiedTo = OrigMO.TiedTo;
135 }
136
137 // Copy all the sensible flags.
138 setFlags(MI.Flags);
139}
140
141void MachineInstr::setDesc(const MCInstrDesc &TID) {
142 if (getParent())
143 getMF()->handleChangeDesc(MI&: *this, TID);
144 MCID = &TID;
145 Opcode = TID.Opcode;
146}
147
148void MachineInstr::moveBefore(MachineInstr *MovePos) {
149 MovePos->getParent()->splice(Where: MovePos, Other: getParent(), From: getIterator());
150}
151
152/// getRegInfo - If this instruction is embedded into a MachineFunction,
153/// return the MachineRegisterInfo object for the current function, otherwise
154/// return null.
155MachineRegisterInfo *MachineInstr::getRegInfo() {
156 if (MachineBasicBlock *MBB = getParent())
157 return &MBB->getParent()->getRegInfo();
158 return nullptr;
159}
160
161const MachineRegisterInfo *MachineInstr::getRegInfo() const {
162 if (const MachineBasicBlock *MBB = getParent())
163 return &MBB->getParent()->getRegInfo();
164 return nullptr;
165}
166
167void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
168 for (MachineOperand &MO : operands())
169 if (MO.isReg())
170 MRI.removeRegOperandFromUseList(MO: &MO);
171}
172
173void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
174 for (MachineOperand &MO : operands())
175 if (MO.isReg())
176 MRI.addRegOperandToUseList(MO: &MO);
177}
178
179void MachineInstr::addOperand(const MachineOperand &Op) {
180 MachineBasicBlock *MBB = getParent();
181 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
182 MachineFunction *MF = MBB->getParent();
183 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
184 addOperand(MF&: *MF, Op);
185}
186
187/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
188/// ranges. If MRI is non-null also update use-def chains.
189static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
190 unsigned NumOps, MachineRegisterInfo *MRI) {
191 if (MRI)
192 return MRI->moveOperands(Dst, Src, NumOps);
193 // MachineOperand is a trivially copyable type so we can just use memmove.
194 assert(Dst && Src && "Unknown operands");
195 std::memmove(dest: Dst, src: Src, n: NumOps * sizeof(MachineOperand));
196}
197
198/// addOperand - Add the specified operand to the instruction. If it is an
199/// implicit operand, it is added to the end of the operand list. If it is
200/// an explicit operand it is added at the end of the explicit operand list
201/// (before the first implicit operand).
202void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
203 assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&
204 "Cannot add more operands.");
205 assert(MCID && "Cannot add operands before providing an instr descriptor");
206
207 // Check if we're adding one of our existing operands.
208 if (&Op >= Operands && &Op < Operands + NumOperands) {
209 // This is unusual: MI->addOperand(MI->getOperand(i)).
210 // If adding Op requires reallocating or moving existing operands around,
211 // the Op reference could go stale. Support it by copying Op.
212 MachineOperand CopyOp(Op);
213 return addOperand(MF, Op: CopyOp);
214 }
215
216 // Find the insert location for the new operand. Implicit registers go at
217 // the end, everything else goes before the implicit regs.
218 //
219 // FIXME: Allow mixed explicit and implicit operands on inline asm.
220 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
221 // implicit-defs, but they must not be moved around. See the FIXME in
222 // InstrEmitter.cpp.
223 unsigned OpNo = getNumOperands();
224 bool isImpReg = Op.isReg() && Op.isImplicit();
225 if (!isImpReg && !isInlineAsm()) {
226 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
227 --OpNo;
228 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
229 }
230 }
231
232 // OpNo now points as the desired insertion point. Unless this is a variadic
233 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
234 // RegMask operands go between the explicit and implicit operands.
235 MachineRegisterInfo *MRI = getRegInfo();
236
237 // Determine if the Operands array needs to be reallocated.
238 // Save the old capacity and operand array.
239 OperandCapacity OldCap = CapOperands;
240 MachineOperand *OldOperands = Operands;
241 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
242 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(N: 1);
243 Operands = MF.allocateOperandArray(Cap: CapOperands);
244 // Move the operands before the insertion point.
245 if (OpNo)
246 moveOperands(Dst: Operands, Src: OldOperands, NumOps: OpNo, MRI);
247 }
248
249 // Move the operands following the insertion point.
250 if (OpNo != NumOperands)
251 moveOperands(Dst: Operands + OpNo + 1, Src: OldOperands + OpNo, NumOps: NumOperands - OpNo,
252 MRI);
253 ++NumOperands;
254
255 // Deallocate the old operand array.
256 if (OldOperands != Operands && OldOperands)
257 MF.deallocateOperandArray(Cap: OldCap, Array: OldOperands);
258
259 // Copy Op into place. It still needs to be inserted into the MRI use lists.
260 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
261 NewMO->ParentMI = this;
262
263 // When adding a register operand, tell MRI about it.
264 if (NewMO->isReg()) {
265 // Ensure isOnRegUseList() returns false, regardless of Op's status.
266 NewMO->Contents.Reg.Prev = nullptr;
267 // Ignore existing ties. This is not a property that can be copied.
268 NewMO->TiedTo = 0;
269 // Add the new operand to MRI, but only for instructions in an MBB.
270 if (MRI)
271 MRI->addRegOperandToUseList(MO: NewMO);
272 // The MCID operand information isn't accurate until we start adding
273 // explicit operands. The implicit operands are added first, then the
274 // explicits are inserted before them.
275 if (!isImpReg) {
276 // Tie uses to defs as indicated in MCInstrDesc.
277 if (NewMO->isUse()) {
278 int DefIdx = MCID->getOperandConstraint(OpNum: OpNo, Constraint: MCOI::TIED_TO);
279 if (DefIdx != -1)
280 tieOperands(DefIdx, UseIdx: OpNo);
281 }
282 // If the register operand is flagged as early, mark the operand as such.
283 if (MCID->getOperandConstraint(OpNum: OpNo, Constraint: MCOI::EARLY_CLOBBER) != -1)
284 NewMO->setIsEarlyClobber(true);
285 }
286 // Ensure debug instructions set debug flag on register uses.
287 if (NewMO->isUse() && isDebugInstr())
288 NewMO->setIsDebug();
289 }
290}
291
292void MachineInstr::removeOperand(unsigned OpNo) {
293 assert(OpNo < getNumOperands() && "Invalid operand number");
294 untieRegOperand(OpIdx: OpNo);
295
296#ifndef NDEBUG
297 // Moving tied operands would break the ties.
298 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
299 if (Operands[i].isReg())
300 assert(!Operands[i].isTied() && "Cannot move tied operands");
301#endif
302
303 MachineRegisterInfo *MRI = getRegInfo();
304 if (MRI && Operands[OpNo].isReg())
305 MRI->removeRegOperandFromUseList(MO: Operands + OpNo);
306
307 // Don't call the MachineOperand destructor. A lot of this code depends on
308 // MachineOperand having a trivial destructor anyway, and adding a call here
309 // wouldn't make it 'destructor-correct'.
310
311 if (unsigned N = NumOperands - 1 - OpNo)
312 moveOperands(Dst: Operands + OpNo, Src: Operands + OpNo + 1, NumOps: N, MRI);
313 --NumOperands;
314}
315
316void MachineInstr::setExtraInfo(MachineFunction &MF,
317 ArrayRef<MachineMemOperand *> MMOs,
318 MCSymbol *PreInstrSymbol,
319 MCSymbol *PostInstrSymbol,
320 MDNode *HeapAllocMarker, MDNode *PCSections,
321 uint32_t CFIType, MDNode *MMRAs, Value *DS) {
322 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
323 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
324 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
325 bool HasPCSections = PCSections != nullptr;
326 bool HasCFIType = CFIType != 0;
327 bool HasMMRAs = MMRAs != nullptr;
328 bool HasDS = DS != nullptr;
329 int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +
330 HasHeapAllocMarker + HasPCSections + HasCFIType + HasMMRAs +
331 HasDS;
332
333 // Drop all extra info if there is none.
334 if (NumPointers <= 0) {
335 Info.clear();
336 return;
337 }
338
339 // If more than one pointer, then store out of line. Store heap alloc markers
340 // out of line because PointerSumType cannot hold more than 4 tag types with
341 // 32-bit pointers.
342 // FIXME: Maybe we should make the symbols in the extra info mutable?
343 else if (NumPointers > 1 || HasMMRAs || HasHeapAllocMarker || HasPCSections ||
344 HasCFIType || HasDS) {
345 Info.set<EIIK_OutOfLine>(
346 MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol,
347 HeapAllocMarker, PCSections, CFIType, MMRAs, DS));
348 return;
349 }
350
351 // Otherwise store the single pointer inline.
352 if (HasPreInstrSymbol)
353 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
354 else if (HasPostInstrSymbol)
355 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
356 else
357 Info.set<EIIK_MMO>(MMOs[0]);
358}
359
360void MachineInstr::dropMemRefs(MachineFunction &MF) {
361 if (memoperands_empty())
362 return;
363
364 setExtraInfo(MF, MMOs: {}, PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
365 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
366 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
367}
368
369void MachineInstr::setMemRefs(MachineFunction &MF,
370 ArrayRef<MachineMemOperand *> MMOs) {
371 if (MMOs.empty()) {
372 dropMemRefs(MF);
373 return;
374 }
375
376 setExtraInfo(MF, MMOs, PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
377 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
378 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
379}
380
381void MachineInstr::addMemOperand(MachineFunction &MF,
382 MachineMemOperand *MO) {
383 if (memoperands_empty()) {
384 setMemRefs(MF, MMOs: {MO});
385 return;
386 }
387
388 SmallVector<MachineMemOperand *, 2> MMOs;
389 MMOs.append(in_start: memoperands_begin(), in_end: memoperands_end());
390 MMOs.push_back(Elt: MO);
391 setMemRefs(MF, MMOs);
392}
393
394void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
395 if (this == &MI)
396 // Nothing to do for a self-clone!
397 return;
398
399 assert(&MF == MI.getMF() &&
400 "Invalid machine functions when cloning memory refrences!");
401 // See if we can just steal the extra info already allocated for the
402 // instruction. We can do this whenever the pre- and post-instruction symbols
403 // are the same (including null).
404 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
405 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
406 getHeapAllocMarker() == MI.getHeapAllocMarker() &&
407 getPCSections() == MI.getPCSections() && getMMRAMetadata() &&
408 MI.getMMRAMetadata()) {
409 Info = MI.Info;
410 return;
411 }
412
413 // Otherwise, fall back on a copy-based clone.
414 setMemRefs(MF, MMOs: MI.memoperands());
415}
416
417/// Check to see if the MMOs pointed to by the two MemRefs arrays are
418/// identical.
419static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
420 ArrayRef<MachineMemOperand *> RHS) {
421 if (LHS.size() != RHS.size())
422 return false;
423
424 auto LHSPointees = make_pointee_range(Range&: LHS);
425 auto RHSPointees = make_pointee_range(Range&: RHS);
426 return std::equal(first1: LHSPointees.begin(), last1: LHSPointees.end(),
427 first2: RHSPointees.begin());
428}
429
430void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
431 ArrayRef<const MachineInstr *> MIs) {
432 // Try handling easy numbers of MIs with simpler mechanisms.
433 if (MIs.empty()) {
434 dropMemRefs(MF);
435 return;
436 }
437 if (MIs.size() == 1) {
438 cloneMemRefs(MF, MI: *MIs[0]);
439 return;
440 }
441 // Because an empty memoperands list provides *no* information and must be
442 // handled conservatively (assuming the instruction can do anything), the only
443 // way to merge with it is to drop all other memoperands.
444 if (MIs[0]->memoperands_empty()) {
445 dropMemRefs(MF);
446 return;
447 }
448
449 // Handle the general case.
450 SmallVector<MachineMemOperand *, 2> MergedMMOs;
451 // Start with the first instruction.
452 assert(&MF == MIs[0]->getMF() &&
453 "Invalid machine functions when cloning memory references!");
454 MergedMMOs.append(in_start: MIs[0]->memoperands_begin(), in_end: MIs[0]->memoperands_end());
455 // Now walk all the other instructions and accumulate any different MMOs.
456 for (const MachineInstr &MI : make_pointee_range(Range: MIs.slice(N: 1))) {
457 assert(&MF == MI.getMF() &&
458 "Invalid machine functions when cloning memory references!");
459
460 // Skip MIs with identical operands to the first. This is a somewhat
461 // arbitrary hack but will catch common cases without being quadratic.
462 // TODO: We could fully implement merge semantics here if needed.
463 if (hasIdenticalMMOs(LHS: MIs[0]->memoperands(), RHS: MI.memoperands()))
464 continue;
465
466 // Because an empty memoperands list provides *no* information and must be
467 // handled conservatively (assuming the instruction can do anything), the
468 // only way to merge with it is to drop all other memoperands.
469 if (MI.memoperands_empty()) {
470 dropMemRefs(MF);
471 return;
472 }
473
474 // Otherwise accumulate these into our temporary buffer of the merged state.
475 MergedMMOs.append(in_start: MI.memoperands_begin(), in_end: MI.memoperands_end());
476 }
477
478 setMemRefs(MF, MMOs: MergedMMOs);
479}
480
481void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
482 // Do nothing if old and new symbols are the same.
483 if (Symbol == getPreInstrSymbol())
484 return;
485
486 // If there was only one symbol and we're removing it, just clear info.
487 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
488 Info.clear();
489 return;
490 }
491
492 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: Symbol, PostInstrSymbol: getPostInstrSymbol(),
493 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
494 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
495}
496
497void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
498 // Do nothing if old and new symbols are the same.
499 if (Symbol == getPostInstrSymbol())
500 return;
501
502 // If there was only one symbol and we're removing it, just clear info.
503 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
504 Info.clear();
505 return;
506 }
507
508 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: Symbol,
509 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
510 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
511}
512
513void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
514 // Do nothing if old and new symbols are the same.
515 if (Marker == getHeapAllocMarker())
516 return;
517
518 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
519 HeapAllocMarker: Marker, PCSections: getPCSections(), CFIType: getCFIType(), MMRAs: getMMRAMetadata(),
520 DS: getDeactivationSymbol());
521}
522
523void MachineInstr::setPCSections(MachineFunction &MF, MDNode *PCSections) {
524 // Do nothing if old and new symbols are the same.
525 if (PCSections == getPCSections())
526 return;
527
528 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
529 HeapAllocMarker: getHeapAllocMarker(), PCSections, CFIType: getCFIType(),
530 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
531}
532
533void MachineInstr::setCFIType(MachineFunction &MF, uint32_t Type) {
534 // Do nothing if old and new types are the same.
535 if (Type == getCFIType())
536 return;
537
538 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
539 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: Type, MMRAs: getMMRAMetadata(),
540 DS: getDeactivationSymbol());
541}
542
543void MachineInstr::setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs) {
544 // Do nothing if old and new symbols are the same.
545 if (MMRAs == getMMRAMetadata())
546 return;
547
548 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
549 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(), MMRAs,
550 DS: getDeactivationSymbol());
551}
552
553void MachineInstr::setDeactivationSymbol(MachineFunction &MF, Value *DS) {
554 // Do nothing if old and new symbols are the same.
555 if (DS == getDeactivationSymbol())
556 return;
557
558 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
559 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
560 MMRAs: getMMRAMetadata(), DS);
561}
562
563void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
564 const MachineInstr &MI) {
565 if (this == &MI)
566 // Nothing to do for a self-clone!
567 return;
568
569 assert(&MF == MI.getMF() &&
570 "Invalid machine functions when cloning instruction symbols!");
571
572 setPreInstrSymbol(MF, Symbol: MI.getPreInstrSymbol());
573 setPostInstrSymbol(MF, Symbol: MI.getPostInstrSymbol());
574 setHeapAllocMarker(MF, Marker: MI.getHeapAllocMarker());
575 setPCSections(MF, PCSections: MI.getPCSections());
576 setMMRAMetadata(MF, MMRAs: MI.getMMRAMetadata());
577}
578
579uint32_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
580 // For now, the just return the union of the flags. If the flags get more
581 // complicated over time, we might need more logic here.
582 return getFlags() | Other.getFlags();
583}
584
585uint32_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
586 uint32_t MIFlags = 0;
587 // Copy the wrapping flags.
588 if (const OverflowingBinaryOperator *OB =
589 dyn_cast<OverflowingBinaryOperator>(Val: &I)) {
590 if (OB->hasNoSignedWrap())
591 MIFlags |= MachineInstr::MIFlag::NoSWrap;
592 if (OB->hasNoUnsignedWrap())
593 MIFlags |= MachineInstr::MIFlag::NoUWrap;
594 } else if (const TruncInst *TI = dyn_cast<TruncInst>(Val: &I)) {
595 if (TI->hasNoSignedWrap())
596 MIFlags |= MachineInstr::MIFlag::NoSWrap;
597 if (TI->hasNoUnsignedWrap())
598 MIFlags |= MachineInstr::MIFlag::NoUWrap;
599 } else if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Val: &I)) {
600 if (GEP->hasNoUnsignedSignedWrap())
601 MIFlags |= MachineInstr::MIFlag::NoUSWrap;
602 if (GEP->hasNoUnsignedWrap())
603 MIFlags |= MachineInstr::MIFlag::NoUWrap;
604 if (GEP->isInBounds())
605 MIFlags |= MachineInstr::MIFlag::InBounds;
606 }
607
608 // Copy the nonneg flag.
609 if (const PossiblyNonNegInst *PNI = dyn_cast<PossiblyNonNegInst>(Val: &I)) {
610 if (PNI->hasNonNeg())
611 MIFlags |= MachineInstr::MIFlag::NonNeg;
612 // Copy the disjoint flag.
613 } else if (const PossiblyDisjointInst *PD =
614 dyn_cast<PossiblyDisjointInst>(Val: &I)) {
615 if (PD->isDisjoint())
616 MIFlags |= MachineInstr::MIFlag::Disjoint;
617 }
618
619 // Copy the samesign flag.
620 if (const ICmpInst *ICmp = dyn_cast<ICmpInst>(Val: &I))
621 if (ICmp->hasSameSign())
622 MIFlags |= MachineInstr::MIFlag::SameSign;
623
624 // Copy the nonnull flag.
625 if (const auto *ASC = dyn_cast<AddrSpaceCastInst>(Val: &I))
626 if (ASC->hasNonNull())
627 MIFlags |= MachineInstr::MIFlag::NonNull;
628
629 // Copy the exact flag.
630 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(Val: &I))
631 if (PE->isExact())
632 MIFlags |= MachineInstr::MIFlag::IsExact;
633
634 // Copy the fast-math flags.
635 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(Val: &I)) {
636 const FastMathFlags Flags = FP->getFastMathFlags();
637 if (Flags.noNaNs())
638 MIFlags |= MachineInstr::MIFlag::FmNoNans;
639 if (Flags.noInfs())
640 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
641 if (Flags.noSignedZeros())
642 MIFlags |= MachineInstr::MIFlag::FmNsz;
643 if (Flags.allowReciprocal())
644 MIFlags |= MachineInstr::MIFlag::FmArcp;
645 if (Flags.allowContract())
646 MIFlags |= MachineInstr::MIFlag::FmContract;
647 if (Flags.approxFunc())
648 MIFlags |= MachineInstr::MIFlag::FmAfn;
649 if (Flags.allowReassoc())
650 MIFlags |= MachineInstr::MIFlag::FmReassoc;
651 }
652
653 if (I.getMetadata(KindID: LLVMContext::MD_unpredictable))
654 MIFlags |= MachineInstr::MIFlag::Unpredictable;
655
656 return MIFlags;
657}
658
659void MachineInstr::copyIRFlags(const Instruction &I) {
660 Flags = copyFlagsFromInstruction(I);
661}
662
663bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
664 assert(!isBundledWithPred() && "Must be called on bundle header");
665 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
666 if (MII->getDesc().getFlags() & Mask) {
667 if (Type == AnyInBundle)
668 return true;
669 } else {
670 if (Type == AllInBundle && !MII->isBundle())
671 return false;
672 }
673 // This was the last instruction in the bundle.
674 if (!MII->isBundledWithSucc())
675 return Type == AllInBundle;
676 }
677}
678
679bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
680 MICheckType Check) const {
681 // If opcodes or number of operands are not the same then the two
682 // instructions are obviously not identical.
683 if (Other.getOpcode() != getOpcode() ||
684 Other.getNumOperands() != getNumOperands())
685 return false;
686
687 if (isBundle()) {
688 // We have passed the test above that both instructions have the same
689 // opcode, so we know that both instructions are bundles here. Let's compare
690 // MIs inside the bundle.
691 assert(Other.isBundle() && "Expected that both instructions are bundles.");
692 MachineBasicBlock::const_instr_iterator I1 = getIterator();
693 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
694 // Loop until we analysed the last intruction inside at least one of the
695 // bundles.
696 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
697 ++I1;
698 ++I2;
699 if (!I1->isIdenticalTo(Other: *I2, Check))
700 return false;
701 }
702 // If we've reached the end of just one of the two bundles, but not both,
703 // the instructions are not identical.
704 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
705 return false;
706 }
707
708 // Check operands to make sure they match.
709 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
710 const MachineOperand &MO = getOperand(i);
711 const MachineOperand &OMO = Other.getOperand(i);
712 if (!MO.isReg()) {
713 if (!MO.isIdenticalTo(Other: OMO))
714 return false;
715 continue;
716 }
717
718 // Clients may or may not want to ignore defs when testing for equality.
719 // For example, machine CSE pass only cares about finding common
720 // subexpressions, so it's safe to ignore virtual register defs.
721 if (MO.isDef()) {
722 if (Check == IgnoreDefs)
723 continue;
724 else if (Check == IgnoreVRegDefs) {
725 if (!MO.getReg().isVirtual() || !OMO.getReg().isVirtual())
726 if (!MO.isIdenticalTo(Other: OMO))
727 return false;
728 } else {
729 if (!MO.isIdenticalTo(Other: OMO))
730 return false;
731 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
732 return false;
733 }
734 } else {
735 if (!MO.isIdenticalTo(Other: OMO))
736 return false;
737 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
738 return false;
739 }
740 }
741 // If DebugLoc does not match then two debug instructions are not identical.
742 if (isDebugInstr())
743 if (getDebugLoc() && Other.getDebugLoc() &&
744 getDebugLoc() != Other.getDebugLoc())
745 return false;
746 // If pre- or post-instruction symbols do not match then the two instructions
747 // are not identical.
748 if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
749 getPostInstrSymbol() != Other.getPostInstrSymbol())
750 return false;
751 if (isCall()) {
752 // Call instructions with different CFI types are not identical.
753 if (getCFIType() != Other.getCFIType())
754 return false;
755 // Even if the call instructions have the same ops, they are not identical
756 // if they are for different globals (this may happen with indirect calls).
757 if (isCandidateForAdditionalCallInfo()) {
758 MachineFunction::CalledGlobalInfo ThisCGI =
759 getParent()->getParent()->tryGetCalledGlobal(MI: this);
760 MachineFunction::CalledGlobalInfo OtherCGI =
761 Other.getParent()->getParent()->tryGetCalledGlobal(MI: &Other);
762 if (ThisCGI.Callee != OtherCGI.Callee ||
763 ThisCGI.TargetFlags != OtherCGI.TargetFlags)
764 return false;
765 }
766 }
767 if (getDeactivationSymbol() != Other.getDeactivationSymbol())
768 return false;
769
770 return true;
771}
772
773bool MachineInstr::isEquivalentDbgInstr(const MachineInstr &Other) const {
774 if (!isDebugValueLike() || !Other.isDebugValueLike())
775 return false;
776 if (getDebugLoc() != Other.getDebugLoc())
777 return false;
778 if (getDebugVariable() != Other.getDebugVariable())
779 return false;
780 if (getNumDebugOperands() != Other.getNumDebugOperands())
781 return false;
782 for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx)
783 if (!getDebugOperand(Index: OpIdx).isIdenticalTo(Other: Other.getDebugOperand(Index: OpIdx)))
784 return false;
785 if (!DIExpression::isEqualExpression(
786 FirstExpr: getDebugExpression(), FirstIndirect: isIndirectDebugValue(),
787 SecondExpr: Other.getDebugExpression(), SecondIndirect: Other.isIndirectDebugValue()))
788 return false;
789 return true;
790}
791
792const MachineFunction *MachineInstr::getMF() const {
793 return getParent()->getParent();
794}
795
796MachineInstr *MachineInstr::removeFromParent() {
797 assert(getParent() && "Not embedded in a basic block!");
798 return getParent()->remove(I: this);
799}
800
801MachineInstr *MachineInstr::removeFromBundle() {
802 assert(getParent() && "Not embedded in a basic block!");
803 return getParent()->remove_instr(I: this);
804}
805
806MachineBasicBlock::iterator MachineInstr::eraseFromParent() {
807 assert(getParent() && "Not embedded in a basic block!");
808 return getParent()->erase(I: this);
809}
810
811void MachineInstr::eraseFromBundle() {
812 assert(getParent() && "Not embedded in a basic block!");
813 getParent()->erase_instr(I: this);
814}
815
816bool MachineInstr::isCandidateForAdditionalCallInfo(QueryType Type) const {
817 if (!isCall(Type))
818 return false;
819 switch (getOpcode()) {
820 case TargetOpcode::PATCHPOINT:
821 case TargetOpcode::STACKMAP:
822 case TargetOpcode::STATEPOINT:
823 case TargetOpcode::FENTRY_CALL:
824 return false;
825 }
826 return true;
827}
828
829bool MachineInstr::shouldUpdateAdditionalCallInfo() const {
830 if (isBundle())
831 return isCandidateForAdditionalCallInfo(Type: MachineInstr::AnyInBundle);
832 return isCandidateForAdditionalCallInfo();
833}
834
835template <typename Operand, typename Instruction>
836static iterator_range<
837 filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
838getDebugOperandsForRegHelper(Instruction *MI, Register Reg) {
839 std::function<bool(Operand & Op)> OpUsesReg(
840 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
841 return make_filter_range(MI->debug_operands(), OpUsesReg);
842}
843
844iterator_range<filter_iterator<const MachineOperand *,
845 std::function<bool(const MachineOperand &Op)>>>
846MachineInstr::getDebugOperandsForReg(Register Reg) const {
847 return getDebugOperandsForRegHelper<const MachineOperand, const MachineInstr>(
848 MI: this, Reg);
849}
850
851iterator_range<
852 filter_iterator<MachineOperand *, std::function<bool(MachineOperand &Op)>>>
853MachineInstr::getDebugOperandsForReg(Register Reg) {
854 return getDebugOperandsForRegHelper<MachineOperand, MachineInstr>(MI: this, Reg);
855}
856
857unsigned MachineInstr::getNumExplicitOperands() const {
858 unsigned NumOperands = MCID->getNumOperands();
859 if (!MCID->isVariadic())
860 return NumOperands;
861
862 for (const MachineOperand &MO : operands_impl().drop_front(N: NumOperands)) {
863 // The operands must always be in the following order:
864 // - explicit reg defs,
865 // - other explicit operands (reg uses, immediates, etc.),
866 // - implicit reg defs
867 // - implicit reg uses
868 if (MO.isReg() && MO.isImplicit())
869 break;
870 ++NumOperands;
871 }
872 return NumOperands;
873}
874
875unsigned MachineInstr::getNumExplicitDefs() const {
876 unsigned NumDefs = MCID->getNumDefs();
877 if (!MCID->isVariadic())
878 return NumDefs;
879
880 for (const MachineOperand &MO : operands_impl().drop_front(N: NumDefs)) {
881 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
882 break;
883 ++NumDefs;
884 }
885 return NumDefs;
886}
887
888void MachineInstr::bundleWithPred() {
889 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
890 setFlag(BundledPred);
891 MachineBasicBlock::instr_iterator Pred = getIterator();
892 --Pred;
893 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
894 Pred->setFlag(BundledSucc);
895}
896
897void MachineInstr::bundleWithSucc() {
898 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
899 setFlag(BundledSucc);
900 MachineBasicBlock::instr_iterator Succ = getIterator();
901 ++Succ;
902 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
903 Succ->setFlag(BundledPred);
904}
905
906void MachineInstr::unbundleFromPred() {
907 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
908 clearFlag(Flag: BundledPred);
909 MachineBasicBlock::instr_iterator Pred = getIterator();
910 --Pred;
911 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
912 Pred->clearFlag(Flag: BundledSucc);
913}
914
915void MachineInstr::unbundleFromSucc() {
916 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
917 clearFlag(Flag: BundledSucc);
918 MachineBasicBlock::instr_iterator Succ = getIterator();
919 ++Succ;
920 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
921 Succ->clearFlag(Flag: BundledPred);
922}
923
924bool MachineInstr::isStackAligningInlineAsm() const {
925 if (isInlineAsm()) {
926 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
927 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
928 return true;
929 }
930 return false;
931}
932
933InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
934 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
935 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
936 return InlineAsm::getDialect(ExtraInfo);
937}
938
939int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
940 unsigned *GroupNo) const {
941 assert(isInlineAsm() && "Expected an inline asm instruction");
942 assert(OpIdx < getNumOperands() && "OpIdx out of range");
943
944 // Ignore queries about the initial operands.
945 if (OpIdx < InlineAsm::MIOp_FirstOperand)
946 return -1;
947
948 unsigned Group = 0;
949 unsigned NumOps;
950 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
951 i += NumOps) {
952 const MachineOperand &FlagMO = getOperand(i);
953 // If we reach the implicit register operands, stop looking.
954 if (!FlagMO.isImm())
955 return -1;
956 const InlineAsm::Flag F(FlagMO.getImm());
957 NumOps = 1 + F.getNumOperandRegisters();
958 if (i + NumOps > OpIdx) {
959 if (GroupNo)
960 *GroupNo = Group;
961 return i;
962 }
963 ++Group;
964 }
965 return -1;
966}
967
968const DILabel *MachineInstr::getDebugLabel() const {
969 assert(isDebugLabel() && "not a DBG_LABEL");
970 return cast<DILabel>(Val: getOperand(i: 0).getMetadata());
971}
972
973const MachineOperand &MachineInstr::getDebugVariableOp() const {
974 assert((isDebugValueLike()) && "not a DBG_VALUE*");
975 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
976 return getOperand(i: VariableOp);
977}
978
979MachineOperand &MachineInstr::getDebugVariableOp() {
980 assert((isDebugValueLike()) && "not a DBG_VALUE*");
981 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
982 return getOperand(i: VariableOp);
983}
984
985const DILocalVariable *MachineInstr::getDebugVariable() const {
986 return cast<DILocalVariable>(Val: getDebugVariableOp().getMetadata());
987}
988
989const MachineOperand &MachineInstr::getDebugExpressionOp() const {
990 assert((isDebugValueLike()) && "not a DBG_VALUE*");
991 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
992 return getOperand(i: ExpressionOp);
993}
994
995MachineOperand &MachineInstr::getDebugExpressionOp() {
996 assert((isDebugValueLike()) && "not a DBG_VALUE*");
997 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
998 return getOperand(i: ExpressionOp);
999}
1000
1001const DIExpression *MachineInstr::getDebugExpression() const {
1002 return cast<DIExpression>(Val: getDebugExpressionOp().getMetadata());
1003}
1004
1005bool MachineInstr::isDebugEntryValue() const {
1006 return isDebugValue() && getDebugExpression()->isEntryValue();
1007}
1008
1009const TargetRegisterClass*
1010MachineInstr::getRegClassConstraint(unsigned OpIdx,
1011 const TargetInstrInfo *TII,
1012 const TargetRegisterInfo *TRI) const {
1013 assert(getParent() && "Can't have an MBB reference here!");
1014 assert(getMF() && "Can't have an MF reference here!");
1015 // Most opcodes have fixed constraints in their MCInstrDesc.
1016 if (!isInlineAsm())
1017 return TII->getRegClass(MCID: getDesc(), OpNum: OpIdx);
1018
1019 if (!getOperand(i: OpIdx).isReg())
1020 return nullptr;
1021
1022 // For tied uses on inline asm, get the constraint from the def.
1023 unsigned DefIdx;
1024 if (getOperand(i: OpIdx).isUse() && isRegTiedToDefOperand(UseOpIdx: OpIdx, DefOpIdx: &DefIdx))
1025 OpIdx = DefIdx;
1026
1027 // Inline asm stores register class constraints in the flag word.
1028 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1029 if (FlagIdx < 0)
1030 return nullptr;
1031
1032 const InlineAsm::Flag F(getOperand(i: FlagIdx).getImm());
1033 unsigned RCID;
1034 if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) &&
1035 F.hasRegClassConstraint(RC&: RCID))
1036 return TRI->getRegClass(i: RCID);
1037
1038 // Assume that all registers in a memory operand are pointers.
1039 if (F.isMemKind())
1040 return TII->getInlineAsmMemoryOperandRegClass(C: F.getMemoryConstraintID());
1041
1042 return nullptr;
1043}
1044
1045const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
1046 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
1047 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
1048 // Check every operands inside the bundle if we have
1049 // been asked to.
1050 if (ExploreBundle)
1051 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
1052 ++OpndIt)
1053 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1054 OpIdx: OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
1055 else
1056 // Otherwise, just check the current operands.
1057 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1058 CurRC = getRegClassConstraintEffectForVRegImpl(OpIdx: i, Reg, CurRC, TII, TRI);
1059 return CurRC;
1060}
1061
1062const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1063 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1064 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1065 assert(CurRC && "Invalid initial register class");
1066 // Check if Reg is constrained by some of its use/def from MI.
1067 const MachineOperand &MO = getOperand(i: OpIdx);
1068 if (!MO.isReg() || MO.getReg() != Reg)
1069 return CurRC;
1070 // If yes, accumulate the constraints through the operand.
1071 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1072}
1073
1074const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
1075 unsigned OpIdx, const TargetRegisterClass *CurRC,
1076 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1077 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1078 const MachineOperand &MO = getOperand(i: OpIdx);
1079 assert(MO.isReg() &&
1080 "Cannot get register constraints for non-register operand");
1081 assert(CurRC && "Invalid initial register class");
1082 if (unsigned SubIdx = MO.getSubReg()) {
1083 if (OpRC)
1084 CurRC = TRI->getMatchingSuperRegClass(A: CurRC, B: OpRC, Idx: SubIdx);
1085 else
1086 CurRC = TRI->getSubClassWithSubReg(RC: CurRC, Idx: SubIdx);
1087 } else if (OpRC)
1088 CurRC = TRI->getCommonSubClass(A: CurRC, B: OpRC);
1089 return CurRC;
1090}
1091
1092/// Return the number of instructions inside the MI bundle, not counting the
1093/// header instruction.
1094unsigned MachineInstr::getBundleSize() const {
1095 MachineBasicBlock::const_instr_iterator I = getIterator();
1096 unsigned Size = 0;
1097 while (I->isBundledWithSucc()) {
1098 ++Size;
1099 ++I;
1100 }
1101 return Size;
1102}
1103
1104/// Returns true if the MachineInstr has an implicit-use operand of exactly
1105/// the given register (not considering sub/super-registers).
1106bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
1107 for (const MachineOperand &MO : implicit_operands()) {
1108 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
1109 return true;
1110 }
1111 return false;
1112}
1113
1114/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1115/// the specific register or -1 if it is not found. It further tightens
1116/// the search criteria to a use that kills the register if isKill is true.
1117int MachineInstr::findRegisterUseOperandIdx(Register Reg,
1118 const TargetRegisterInfo *TRI,
1119 bool isKill) const {
1120 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1121 const MachineOperand &MO = getOperand(i);
1122 if (!MO.isReg() || !MO.isUse())
1123 continue;
1124 Register MOReg = MO.getReg();
1125 if (!MOReg)
1126 continue;
1127 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(RegA: MOReg, RegB: Reg)))
1128 if (!isKill || MO.isKill())
1129 return i;
1130 }
1131 return -1;
1132}
1133
1134bool MachineInstr::hasTiedAndOtherReadOf(Register Reg, unsigned SubReg) const {
1135 bool Tied = false;
1136 unsigned Reads = 0;
1137 for (const MachineOperand &MO : all_uses()) {
1138 if (MO.getReg() != Reg || MO.getSubReg() != SubReg)
1139 continue;
1140 ++Reads;
1141 // A tie its def already satisfies is not rewritten.
1142 Tied |= MO.isTied() &&
1143 getOperand(i: findTiedOperandIdx(OpIdx: getOperandNo(I: &MO))).getReg() != Reg;
1144 }
1145 return Tied && Reads > 1;
1146}
1147
1148/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1149/// indicating if this instruction reads or writes Reg. This also considers
1150/// partial defines.
1151std::pair<bool,bool>
1152MachineInstr::readsWritesVirtualRegister(Register Reg,
1153 SmallVectorImpl<unsigned> *Ops) const {
1154 bool PartDef = false; // Partial redefine.
1155 bool FullDef = false; // Full define.
1156 bool Use = false;
1157
1158 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1159 const MachineOperand &MO = getOperand(i);
1160 if (!MO.isReg() || MO.getReg() != Reg)
1161 continue;
1162 if (Ops)
1163 Ops->push_back(Elt: i);
1164 if (MO.isUse())
1165 Use |= !MO.isUndef();
1166 else if (MO.getSubReg() && !MO.isUndef())
1167 // A partial def undef doesn't count as reading the register.
1168 PartDef = true;
1169 else
1170 FullDef = true;
1171 }
1172 // A partial redefine uses Reg unless there is also a full define.
1173 return std::make_pair(x: Use || (PartDef && !FullDef), y: PartDef || FullDef);
1174}
1175
1176/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1177/// the specified register or -1 if it is not found. If isDead is true, defs
1178/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1179/// also checks if there is a def of a super-register.
1180int MachineInstr::findRegisterDefOperandIdx(Register Reg,
1181 const TargetRegisterInfo *TRI,
1182 bool isDead, bool Overlap) const {
1183 bool isPhys = Reg.isPhysical();
1184 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1185 const MachineOperand &MO = getOperand(i);
1186 // Accept regmask operands when Overlap is set.
1187 // Ignore them when looking for a specific def operand (Overlap == false).
1188 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(PhysReg: Reg))
1189 return i;
1190 if (!MO.isReg() || !MO.isDef())
1191 continue;
1192 Register MOReg = MO.getReg();
1193 bool Found = (MOReg == Reg);
1194 if (!Found && TRI && isPhys && MOReg.isPhysical()) {
1195 if (Overlap)
1196 Found = TRI->regsOverlap(RegA: MOReg, RegB: Reg);
1197 else
1198 Found = TRI->isSubRegister(RegA: MOReg, RegB: Reg);
1199 }
1200 if (Found && (!isDead || MO.isDead()))
1201 return i;
1202 }
1203 return -1;
1204}
1205
1206/// findFirstPredOperandIdx() - Find the index of the first operand in the
1207/// operand list that is used to represent the predicate. It returns -1 if
1208/// none is found.
1209int MachineInstr::findFirstPredOperandIdx() const {
1210 // Don't call MCID.findFirstPredOperandIdx() because this variant
1211 // is sometimes called on an instruction that's not yet complete, and
1212 // so the number of operands is less than the MCID indicates. In
1213 // particular, the PTX target does this.
1214 const MCInstrDesc &MCID = getDesc();
1215 if (MCID.isPredicable()) {
1216 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1217 if (MCID.operands()[i].isPredicate())
1218 return i;
1219 }
1220
1221 return -1;
1222}
1223
1224// MachineOperand::TiedTo is 4 bits wide.
1225const unsigned TiedMax = 15;
1226
1227/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1228///
1229/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1230/// field. TiedTo can have these values:
1231///
1232/// 0: Operand is not tied to anything.
1233/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1234/// TiedMax: Tied to an operand >= TiedMax-1.
1235///
1236/// The tied def must be one of the first TiedMax operands on a normal
1237/// instruction. INLINEASM instructions allow more tied defs.
1238///
1239void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1240 MachineOperand &DefMO = getOperand(i: DefIdx);
1241 MachineOperand &UseMO = getOperand(i: UseIdx);
1242 assert(DefMO.isDef() && "DefIdx must be a def operand");
1243 assert(UseMO.isUse() && "UseIdx must be a use operand");
1244 assert(!DefMO.isTied() && "Def is already tied to another use");
1245 assert(!UseMO.isTied() && "Use is already tied to another def");
1246
1247 if (DefIdx < TiedMax) {
1248 UseMO.TiedTo = DefIdx + 1;
1249 } else {
1250 // Inline asm can use the group descriptors to find tied operands,
1251 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1252 // but on normal instruction, the tied def must be within the first TiedMax
1253 // operands.
1254 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1255 "DefIdx out of range");
1256 UseMO.TiedTo = TiedMax;
1257 }
1258
1259 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1260 DefMO.TiedTo = std::min(a: UseIdx + 1, b: TiedMax);
1261}
1262
1263/// Given the index of a tied register operand, find the operand it is tied to.
1264/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1265/// which must exist.
1266unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1267 const MachineOperand &MO = getOperand(i: OpIdx);
1268 assert(MO.isTied() && "Operand isn't tied");
1269
1270 // Normally TiedTo is in range.
1271 if (MO.TiedTo < TiedMax)
1272 return MO.TiedTo - 1;
1273
1274 // Uses on normal instructions can be out of range.
1275 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1276 // Normal tied defs must be in the 0..TiedMax-1 range.
1277 if (MO.isUse())
1278 return TiedMax - 1;
1279 // MO is a def. Search for the tied use.
1280 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1281 const MachineOperand &UseMO = getOperand(i);
1282 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1283 return i;
1284 }
1285 llvm_unreachable("Can't find tied use");
1286 }
1287
1288 if (getOpcode() == TargetOpcode::STATEPOINT) {
1289 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1290 // on registers.
1291 StatepointOpers SO(this);
1292 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1293 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1294 unsigned NumDefs = getNumDefs();
1295 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1296 while (!getOperand(i: CurUseIdx).isReg())
1297 CurUseIdx = StackMaps::getNextMetaArgIdx(MI: this, CurIdx: CurUseIdx);
1298 if (OpIdx == CurDefIdx)
1299 return CurUseIdx;
1300 if (OpIdx == CurUseIdx)
1301 return CurDefIdx;
1302 CurUseIdx = StackMaps::getNextMetaArgIdx(MI: this, CurIdx: CurUseIdx);
1303 }
1304 llvm_unreachable("Can't find tied use");
1305 }
1306
1307 // Now deal with inline asm by parsing the operand group descriptor flags.
1308 // Find the beginning of each operand group.
1309 SmallVector<unsigned, 8> GroupIdx;
1310 unsigned OpIdxGroup = ~0u;
1311 unsigned NumOps;
1312 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1313 i += NumOps) {
1314 const MachineOperand &FlagMO = getOperand(i);
1315 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1316 unsigned CurGroup = GroupIdx.size();
1317 GroupIdx.push_back(Elt: i);
1318 const InlineAsm::Flag F(FlagMO.getImm());
1319 NumOps = 1 + F.getNumOperandRegisters();
1320 // OpIdx belongs to this operand group.
1321 if (OpIdx > i && OpIdx < i + NumOps)
1322 OpIdxGroup = CurGroup;
1323 unsigned TiedGroup;
1324 if (!F.isUseOperandTiedToDef(Idx&: TiedGroup))
1325 continue;
1326 // Operands in this group are tied to operands in TiedGroup which must be
1327 // earlier. Find the number of operands between the two groups.
1328 unsigned Delta = i - GroupIdx[TiedGroup];
1329
1330 // OpIdx is a use tied to TiedGroup.
1331 if (OpIdxGroup == CurGroup)
1332 return OpIdx - Delta;
1333
1334 // OpIdx is a def tied to this use group.
1335 if (OpIdxGroup == TiedGroup)
1336 return OpIdx + Delta;
1337 }
1338 llvm_unreachable("Invalid tied operand on inline asm");
1339}
1340
1341/// clearKillInfo - Clears kill flags on all operands.
1342///
1343void MachineInstr::clearKillInfo() {
1344 for (MachineOperand &MO : operands()) {
1345 if (MO.isReg() && MO.isUse())
1346 MO.setIsKill(false);
1347 }
1348}
1349
1350void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1351 unsigned SubIdx,
1352 const TargetRegisterInfo &RegInfo) {
1353 if (ToReg.isPhysical()) {
1354 if (SubIdx)
1355 ToReg = RegInfo.getSubReg(Reg: ToReg, Idx: SubIdx);
1356 for (MachineOperand &MO : operands()) {
1357 if (!MO.isReg() || MO.getReg() != FromReg)
1358 continue;
1359 MO.substPhysReg(Reg: ToReg, RegInfo);
1360 }
1361 } else {
1362 for (MachineOperand &MO : operands()) {
1363 if (!MO.isReg() || MO.getReg() != FromReg)
1364 continue;
1365 MO.substVirtReg(Reg: ToReg, SubIdx, RegInfo);
1366 }
1367 }
1368}
1369
1370/// isSafeToMove - Return true if it is safe to move this instruction. If
1371/// SawStore is set to true, it means that there is a store (or call) between
1372/// the instruction's location and its intended destination.
1373bool MachineInstr::isSafeToMove(bool &SawStore) const {
1374 // Ignore stuff that we obviously can't move.
1375 //
1376 // Treat volatile loads as stores. This is not strictly necessary for
1377 // volatiles, but it is required for atomic loads. It is not allowed to move
1378 // a load across an atomic load with Ordering > Monotonic.
1379 if (mayStore() || isCall() || isPHI() || hasOrderedMemoryRef()) {
1380 SawStore = true;
1381 return false;
1382 }
1383
1384 // Don't touch instructions that have non-trivial invariants. For example,
1385 // terminators have to be at the end of a basic block.
1386 if (isPosition() || isDebugInstr() || isTerminator() ||
1387 isJumpTableDebugInfo() || isLifetimeMarker())
1388 return false;
1389
1390 // Don't touch instructions which can have non-load/store effects.
1391 //
1392 // Inline asm has a "sideeffect" marker to indicate whether the asm has
1393 // intentional side-effects. Even if an inline asm is not "sideeffect",
1394 // though, it still can't be speculatively executed: the operation might
1395 // not be valid on the current target, or for some combinations of operands.
1396 // (Some transforms that move an instruction don't speculatively execute it;
1397 // we currently don't try to handle that distinction here.)
1398 //
1399 // Other instructions handled here include those that can raise FP
1400 // exceptions, x86 "DIV" instructions which trap on divide by zero, and
1401 // stack adjustments.
1402 if (mayRaiseFPException() || hasProperty(MCFlag: MCID::UnmodeledSideEffects) ||
1403 isInlineAsm())
1404 return false;
1405
1406 // See if this instruction does a load. If so, we have to guarantee that the
1407 // loaded value doesn't change between the load and the its intended
1408 // destination. The check for isInvariantLoad gives the target the chance to
1409 // classify the load as always returning a constant, e.g. a constant pool
1410 // load.
1411 if (mayLoad() && !isDereferenceableInvariantLoad())
1412 // Otherwise, this is a real load. If there is a store between the load and
1413 // end of block, we can't move it.
1414 return !SawStore;
1415
1416 return true;
1417}
1418
1419bool MachineInstr::wouldBeTriviallyDead() const {
1420 // Don't delete frame allocation labels.
1421 // FIXME: Why is LOCAL_ESCAPE not considered in MachineInstr::isLabel?
1422 if (getOpcode() == TargetOpcode::LOCAL_ESCAPE)
1423 return false;
1424
1425 // Don't delete FAKE_USE.
1426 // FIXME: Why is FAKE_USE not considered in MachineInstr::isPosition?
1427 if (isFakeUse())
1428 return false;
1429
1430 // If we can move an instruction, we can remove it. Otherwise, it has
1431 // a side-effect of some sort.
1432 bool SawStore = false;
1433 return isPHI() || isSafeToMove(SawStore);
1434}
1435
1436bool MachineInstr::isDead(const MachineRegisterInfo &MRI,
1437 LiveRegUnits *LivePhysRegs) const {
1438 // Instructions without side-effects are dead iff they only define dead regs.
1439 // This function is hot and this loop returns early in the common case,
1440 // so only perform additional checks before this if absolutely necessary.
1441 for (const MachineOperand &MO : all_defs()) {
1442 Register Reg = MO.getReg();
1443 if (Reg.isPhysical()) {
1444 // Don't delete live physreg defs, or any reserved register defs.
1445 if (!LivePhysRegs || !LivePhysRegs->available(Reg) || MRI.isReserved(PhysReg: Reg))
1446 return false;
1447 } else {
1448 if (MO.isDead())
1449 continue;
1450 for (const MachineInstr &Use : MRI.use_nodbg_instructions(Reg)) {
1451 if (&Use != this)
1452 // This def has a non-debug use. Don't delete the instruction!
1453 return false;
1454 }
1455 }
1456 }
1457
1458 // Technically speaking inline asm without side effects and no defs can still
1459 // be deleted. But there is so much bad inline asm code out there, we should
1460 // let them be.
1461 if (isInlineAsm())
1462 return false;
1463
1464 // FIXME: See issue #105950 for why LIFETIME markers are considered dead here.
1465 if (isLifetimeMarker())
1466 return true;
1467
1468 // If there are no defs with uses, then we call the instruction dead so long
1469 // as we do not suspect it may have sideeffects.
1470 return wouldBeTriviallyDead();
1471}
1472
1473static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI,
1474 BatchAAResults *AA, bool UseTBAA,
1475 const MachineMemOperand *MMOa,
1476 const MachineMemOperand *MMOb) {
1477 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1478 // operates with MachineMemOperand offset with some important assumptions:
1479 // - LLVM fundamentally assumes flat address spaces.
1480 // - MachineOperand offset can *only* result from legalization and cannot
1481 // affect queries other than the trivial case of overlap checking.
1482 // - These offsets never wrap and never step outside of allocated objects.
1483 // - There should never be any negative offsets here.
1484 //
1485 // FIXME: Modify API to hide this math from "user"
1486 // Even before we go to AA we can reason locally about some memory objects. It
1487 // can save compile time, and possibly catch some corner cases not currently
1488 // covered.
1489
1490 int64_t OffsetA = MMOa->getOffset();
1491 int64_t OffsetB = MMOb->getOffset();
1492 int64_t MinOffset = std::min(a: OffsetA, b: OffsetB);
1493
1494 LocationSize WidthA = MMOa->getSize();
1495 LocationSize WidthB = MMOb->getSize();
1496 bool KnownWidthA = WidthA.hasValue();
1497 bool KnownWidthB = WidthB.hasValue();
1498 bool BothMMONonScalable = !WidthA.isScalable() && !WidthB.isScalable();
1499
1500 const Value *ValA = MMOa->getValue();
1501 const Value *ValB = MMOb->getValue();
1502 bool SameVal = (ValA && ValB && (ValA == ValB));
1503 if (!SameVal) {
1504 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1505 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1506 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1507 return false;
1508 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1509 return false;
1510 if (PSVa && PSVb && (PSVa == PSVb))
1511 SameVal = true;
1512 }
1513
1514 if (SameVal && BothMMONonScalable) {
1515 if (!KnownWidthA || !KnownWidthB)
1516 return true;
1517 int64_t MaxOffset = std::max(a: OffsetA, b: OffsetB);
1518 int64_t LowWidth = (MinOffset == OffsetA)
1519 ? WidthA.getValue().getKnownMinValue()
1520 : WidthB.getValue().getKnownMinValue();
1521 return (MinOffset + LowWidth > MaxOffset);
1522 }
1523
1524 if (!AA)
1525 return true;
1526
1527 if (!ValA || !ValB)
1528 return true;
1529
1530 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1531 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1532
1533 // If Scalable Location Size has non-zero offset, Width + Offset does not work
1534 // at the moment
1535 if ((WidthA.isScalable() && OffsetA > 0) ||
1536 (WidthB.isScalable() && OffsetB > 0))
1537 return true;
1538
1539 int64_t OverlapA =
1540 KnownWidthA ? WidthA.getValue().getKnownMinValue() + OffsetA - MinOffset
1541 : MemoryLocation::UnknownSize;
1542 int64_t OverlapB =
1543 KnownWidthB ? WidthB.getValue().getKnownMinValue() + OffsetB - MinOffset
1544 : MemoryLocation::UnknownSize;
1545
1546 LocationSize LocA = (WidthA.isScalable() || !KnownWidthA)
1547 ? WidthA
1548 : LocationSize::precise(Value: OverlapA);
1549 LocationSize LocB = (WidthB.isScalable() || !KnownWidthB)
1550 ? WidthB
1551 : LocationSize::precise(Value: OverlapB);
1552
1553 return !AA->isNoAlias(
1554 LocA: MemoryLocation(ValA, LocA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1555 LocB: MemoryLocation(ValB, LocB, UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1556}
1557
1558bool MachineInstr::mayAlias(BatchAAResults *AA, const MachineInstr &Other,
1559 bool UseTBAA) const {
1560 const MachineFunction *MF = getMF();
1561 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1562 const MachineFrameInfo &MFI = MF->getFrameInfo();
1563
1564 // Exclude call instruction which may alter the memory but can not be handled
1565 // by this function.
1566 if (isCall() || Other.isCall())
1567 return true;
1568
1569 // If neither instruction stores to memory, they can't alias in any
1570 // meaningful way, even if they read from the same address.
1571 if (!mayStore() && !Other.mayStore())
1572 return false;
1573
1574 // Both instructions must be memory operations to be able to alias.
1575 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1576 return false;
1577
1578 // Let the target decide if memory accesses cannot possibly overlap.
1579 if (TII->areMemAccessesTriviallyDisjoint(MIa: *this, MIb: Other))
1580 return false;
1581
1582 // Memory operations without memory operands may access anything. Be
1583 // conservative and assume `MayAlias`.
1584 if (memoperands_empty() || Other.memoperands_empty())
1585 return true;
1586
1587 // Skip if there are too many memory operands.
1588 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1589 if (NumChecks > TII->getMemOperandAACheckLimit())
1590 return true;
1591
1592 // Check each pair of memory operands from both instructions, which can't
1593 // alias only if all pairs won't alias.
1594 for (auto *MMOa : memoperands()) {
1595 for (auto *MMOb : Other.memoperands()) {
1596 if (!MMOa->isStore() && !MMOb->isStore())
1597 continue;
1598 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1599 return true;
1600 }
1601 }
1602
1603 return false;
1604}
1605
1606bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1607 bool UseTBAA) const {
1608 if (AA) {
1609 BatchAAResults BAA(*AA);
1610 return mayAlias(AA: &BAA, Other, UseTBAA);
1611 }
1612 return mayAlias(AA: static_cast<BatchAAResults *>(nullptr), Other, UseTBAA);
1613}
1614
1615/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1616/// or volatile memory reference, or if the information describing the memory
1617/// reference is not available. Return false if it is known to have no ordered
1618/// memory references.
1619bool MachineInstr::hasOrderedMemoryRef() const {
1620 // An instruction known never to access memory won't have a volatile access.
1621 if (!mayStore() &&
1622 !mayLoad() &&
1623 !isCall() &&
1624 !hasUnmodeledSideEffects())
1625 return false;
1626
1627 // Otherwise, if the instruction has no memory reference information,
1628 // conservatively assume it wasn't preserved.
1629 if (memoperands_empty())
1630 return true;
1631
1632 // Check if any of our memory operands are ordered.
1633 return llvm::any_of(Range: memoperands(), P: [](const MachineMemOperand *MMO) {
1634 return !MMO->isUnordered();
1635 });
1636}
1637
1638/// isDereferenceableInvariantLoad - Return true if this instruction will never
1639/// trap and is loading from a location whose value is invariant across a run of
1640/// this function.
1641bool MachineInstr::isDereferenceableInvariantLoad() const {
1642 // If the instruction doesn't load at all, it isn't an invariant load.
1643 if (!mayLoad())
1644 return false;
1645
1646 // If the instruction has lost its memoperands, conservatively assume that
1647 // it may not be an invariant load.
1648 if (memoperands_empty())
1649 return false;
1650
1651 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1652
1653 for (MachineMemOperand *MMO : memoperands()) {
1654 if (!MMO->isUnordered())
1655 // If the memory operand has ordering side effects, we can't move the
1656 // instruction. Such an instruction is technically an invariant load,
1657 // but the caller code would need updated to expect that.
1658 return false;
1659 if (MMO->isStore()) return false;
1660 if (MMO->isInvariant() && MMO->isDereferenceable())
1661 continue;
1662
1663 // A load from a constant PseudoSourceValue is invariant.
1664 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
1665 if (PSV->isConstant(&MFI))
1666 continue;
1667 }
1668
1669 // Otherwise assume conservatively.
1670 return false;
1671 }
1672
1673 // Everything checks out.
1674 return true;
1675}
1676
1677Register MachineInstr::isConstantValuePHI() const {
1678 if (!isPHI())
1679 return {};
1680 assert(getNumOperands() >= 3 &&
1681 "It's illegal to have a PHI without source operands");
1682
1683 Register Reg = getOperand(i: 1).getReg();
1684 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1685 if (getOperand(i).getReg() != Reg)
1686 return {};
1687 return Reg;
1688}
1689
1690bool MachineInstr::hasUnmodeledSideEffects() const {
1691 if (hasProperty(MCFlag: MCID::UnmodeledSideEffects))
1692 return true;
1693 if (isInlineAsm()) {
1694 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1695 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1696 return true;
1697 }
1698
1699 return false;
1700}
1701
1702bool MachineInstr::isLoadFoldBarrier() const {
1703 return mayStore() || isCall() ||
1704 (hasUnmodeledSideEffects() && !isPseudoProbe());
1705}
1706
1707/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1708///
1709bool MachineInstr::allDefsAreDead() const {
1710 for (const MachineOperand &MO : operands()) {
1711 if (!MO.isReg() || MO.isUse())
1712 continue;
1713 if (!MO.isDead())
1714 return false;
1715 }
1716 return true;
1717}
1718
1719bool MachineInstr::allImplicitDefsAreDead() const {
1720 for (const MachineOperand &MO : implicit_operands()) {
1721 if (!MO.isReg() || MO.isUse())
1722 continue;
1723 if (!MO.isDead())
1724 return false;
1725 }
1726 return true;
1727}
1728
1729/// copyImplicitOps - Copy implicit register operands from specified
1730/// instruction to this instruction.
1731void MachineInstr::copyImplicitOps(MachineFunction &MF,
1732 const MachineInstr &MI) {
1733 for (const MachineOperand &MO :
1734 llvm::drop_begin(RangeOrContainer: MI.operands(), N: MI.getDesc().getNumOperands()))
1735 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1736 addOperand(MF, Op: MO);
1737}
1738
1739bool MachineInstr::hasComplexRegisterTies() const {
1740 const MCInstrDesc &MCID = getDesc();
1741 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1742 return true;
1743 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1744 const auto &Operand = getOperand(i: I);
1745 if (!Operand.isReg() || Operand.isDef())
1746 // Ignore the defined registers as MCID marks only the uses as tied.
1747 continue;
1748 int ExpectedTiedIdx = MCID.getOperandConstraint(OpNum: I, Constraint: MCOI::TIED_TO);
1749 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(OpIdx: I)) : -1;
1750 if (ExpectedTiedIdx != TiedIdx)
1751 return true;
1752 }
1753 return false;
1754}
1755
1756LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1757 const MachineRegisterInfo &MRI) const {
1758 const MachineOperand &Op = getOperand(i: OpIdx);
1759 if (!Op.isReg())
1760 return LLT{};
1761
1762 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1763 return MRI.getType(Reg: Op.getReg());
1764
1765 auto &OpInfo = getDesc().operands()[OpIdx];
1766 if (!OpInfo.isGenericType())
1767 return MRI.getType(Reg: Op.getReg());
1768
1769 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1770 return LLT{};
1771
1772 LLT TypeToPrint = MRI.getType(Reg: Op.getReg());
1773 // Don't mark the type index printed if it wasn't actually printed: maybe
1774 // another operand with the same type index has an actual type attached:
1775 if (TypeToPrint.isValid())
1776 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1777 return TypeToPrint;
1778}
1779
1780#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1781LLVM_DUMP_METHOD void MachineInstr::dump() const {
1782 dbgs() << " ";
1783 print(dbgs());
1784}
1785
1786LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1787 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1788 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1789 if (Depth >= MaxDepth)
1790 return;
1791 if (!AlreadySeenInstrs.insert(this).second)
1792 return;
1793 // PadToColumn always inserts at least one space.
1794 // Don't mess up the alignment if we don't want any space.
1795 if (Depth)
1796 fdbgs().PadToColumn(Depth * 2);
1797 print(fdbgs());
1798 for (const MachineOperand &MO : operands()) {
1799 if (!MO.isReg() || MO.isDef())
1800 continue;
1801 Register Reg = MO.getReg();
1802 if (Reg.isPhysical())
1803 continue;
1804 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1805 if (NewMI == nullptr)
1806 continue;
1807 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1808 }
1809}
1810
1811LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1812 unsigned MaxDepth) const {
1813 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1814 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1815}
1816#endif
1817
1818void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1819 bool SkipDebugLoc, bool AddNewLine,
1820 const TargetInstrInfo *TII) const {
1821 const Module *M = nullptr;
1822 const Function *F = nullptr;
1823 if (const MachineFunction *MF = getMFIfAvailable(MI: *this)) {
1824 F = &MF->getFunction();
1825 M = F->getParent();
1826 if (!TII)
1827 TII = MF->getSubtarget().getInstrInfo();
1828 }
1829
1830 ModuleSlotTracker MST(M);
1831 if (F)
1832 MST.incorporateFunction(F: *F);
1833 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1834}
1835
1836void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1837 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1838 bool AddNewLine, const TargetInstrInfo *TII) const {
1839 // We can be a bit tidier if we know the MachineFunction.
1840 const TargetRegisterInfo *TRI = nullptr;
1841 const MachineRegisterInfo *MRI = nullptr;
1842 tryToGetTargetInfo(MI: *this, TRI, MRI, TII);
1843
1844 if (isCFIInstruction())
1845 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1846
1847 SmallBitVector PrintedTypes(8);
1848 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1849 auto GetTiedOperandIdx = [&](unsigned OpIdx) {
1850 if (!ShouldPrintRegisterTies)
1851 return 0U;
1852 const MachineOperand &MO = getOperand(i: OpIdx);
1853 if (MO.isReg() && MO.isTied() && !MO.isDef())
1854 return findTiedOperandIdx(OpIdx);
1855 return 0U;
1856 };
1857 unsigned StartOp = 0;
1858 unsigned e = getNumOperands();
1859
1860 // Print explicitly defined operands on the left of an assignment syntax.
1861 while (StartOp < e) {
1862 const MachineOperand &MO = getOperand(i: StartOp);
1863 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1864 break;
1865
1866 if (StartOp != 0)
1867 OS << ", ";
1868
1869 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: StartOp, PrintedTypes, MRI: *MRI) : LLT{};
1870 // tied operands are not printed for defs.
1871 MO.print(os&: OS, MST, TypeToPrint, OpIdx: StartOp, /*PrintDef=*/false, IsStandalone,
1872 /*ShouldPrintRegisterTies=*/false, /*TiedOperandIdx=*/0, TRI);
1873 ++StartOp;
1874 }
1875
1876 if (StartOp != 0)
1877 OS << " = ";
1878
1879 if (getFlag(Flag: MachineInstr::FrameSetup))
1880 OS << "frame-setup ";
1881 if (getFlag(Flag: MachineInstr::FrameDestroy))
1882 OS << "frame-destroy ";
1883 if (getFlag(Flag: MachineInstr::FmNoNans))
1884 OS << "nnan ";
1885 if (getFlag(Flag: MachineInstr::FmNoInfs))
1886 OS << "ninf ";
1887 if (getFlag(Flag: MachineInstr::FmNsz))
1888 OS << "nsz ";
1889 if (getFlag(Flag: MachineInstr::FmArcp))
1890 OS << "arcp ";
1891 if (getFlag(Flag: MachineInstr::FmContract))
1892 OS << "contract ";
1893 if (getFlag(Flag: MachineInstr::FmAfn))
1894 OS << "afn ";
1895 if (getFlag(Flag: MachineInstr::FmReassoc))
1896 OS << "reassoc ";
1897 if (getFlag(Flag: MachineInstr::NoUWrap))
1898 OS << "nuw ";
1899 if (getFlag(Flag: MachineInstr::NoSWrap))
1900 OS << "nsw ";
1901 if (getFlag(Flag: MachineInstr::IsExact))
1902 OS << "exact ";
1903 if (getFlag(Flag: MachineInstr::NoFPExcept))
1904 OS << "nofpexcept ";
1905 if (getFlag(Flag: MachineInstr::NoMerge))
1906 OS << "nomerge ";
1907 if (getFlag(Flag: MachineInstr::NoConvergent))
1908 OS << "noconvergent ";
1909 if (getFlag(Flag: MachineInstr::NonNeg))
1910 OS << "nneg ";
1911 if (getFlag(Flag: MachineInstr::Disjoint))
1912 OS << "disjoint ";
1913 if (getFlag(Flag: MachineInstr::NoUSWrap))
1914 OS << "nusw ";
1915 if (getFlag(Flag: MachineInstr::SameSign))
1916 OS << "samesign ";
1917 if (getFlag(Flag: MachineInstr::InBounds))
1918 OS << "inbounds ";
1919 if (getFlag(Flag: MachineInstr::LRSplit))
1920 OS << "lr-split ";
1921 if (getFlag(Flag: MachineInstr::NonNull))
1922 OS << "nonnull ";
1923
1924 // Print the opcode name.
1925 if (TII)
1926 OS << TII->getName(Opcode: getOpcode());
1927 else
1928 OS << "UNKNOWN";
1929
1930 if (SkipOpers)
1931 return;
1932
1933 // Print the rest of the operands.
1934 bool FirstOp = true;
1935 unsigned AsmDescOp = ~0u;
1936 unsigned AsmOpCount = 0;
1937
1938 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1939 // Print asm string.
1940 OS << " ";
1941 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1942 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, MRI: *MRI) : LLT{};
1943 unsigned TiedOperandIdx = GetTiedOperandIdx(OpIdx);
1944 getOperand(i: OpIdx).print(os&: OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true,
1945 IsStandalone, ShouldPrintRegisterTies,
1946 TiedOperandIdx, TRI);
1947
1948 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1949 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1950 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1951 OS << " [sideeffect]";
1952 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1953 OS << " [mayload]";
1954 if (ExtraInfo & InlineAsm::Extra_MayStore)
1955 OS << " [maystore]";
1956 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1957 OS << " [isconvergent]";
1958 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1959 OS << " [alignstack]";
1960 if (ExtraInfo & InlineAsm::Extra_MayUnwind)
1961 OS << " [unwind]";
1962 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1963 OS << " [attdialect]";
1964 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1965 OS << " [inteldialect]";
1966
1967 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1968 FirstOp = false;
1969 }
1970
1971 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1972 const MachineOperand &MO = getOperand(i);
1973
1974 if (FirstOp) FirstOp = false; else OS << ",";
1975 OS << " ";
1976
1977 if (isDebugValueLike() && MO.isMetadata()) {
1978 // Pretty print DBG_VALUE* instructions.
1979 auto *DIV = dyn_cast<DILocalVariable>(Val: MO.getMetadata());
1980 if (DIV && !DIV->getName().empty())
1981 OS << "!\"" << DIV->getName() << '\"';
1982 else {
1983 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{};
1984 unsigned TiedOperandIdx = GetTiedOperandIdx(i);
1985 MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone,
1986 ShouldPrintRegisterTies, TiedOperandIdx, TRI);
1987 }
1988 } else if (isDebugLabel() && MO.isMetadata()) {
1989 // Pretty print DBG_LABEL instructions.
1990 auto *DIL = dyn_cast<DILabel>(Val: MO.getMetadata());
1991 if (DIL && !DIL->getName().empty())
1992 OS << "\"" << DIL->getName() << '\"';
1993 else {
1994 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{};
1995 unsigned TiedOperandIdx = GetTiedOperandIdx(i);
1996 MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone,
1997 ShouldPrintRegisterTies, TiedOperandIdx, TRI);
1998 }
1999 } else if (i == AsmDescOp && MO.isImm()) {
2000 // Pretty print the inline asm operand descriptor.
2001 OS << '$' << AsmOpCount++;
2002 unsigned Flag = MO.getImm();
2003 const InlineAsm::Flag F(Flag);
2004 OS << ":[";
2005 OS << F.getKindName();
2006
2007 unsigned RCID;
2008 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RC&: RCID)) {
2009 if (TRI) {
2010 OS << ':' << TRI->getRegClassName(Class: TRI->getRegClass(i: RCID));
2011 } else
2012 OS << ":RC" << RCID;
2013 }
2014
2015 if (F.isMemKind()) {
2016 const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
2017 OS << ":" << InlineAsm::getMemConstraintName(C: MCID);
2018 }
2019
2020 unsigned TiedTo;
2021 if (F.isUseOperandTiedToDef(Idx&: TiedTo))
2022 OS << " tiedto:$" << TiedTo;
2023
2024 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||
2025 F.isRegUseKind()) &&
2026 F.getRegMayBeFolded()) {
2027 OS << " foldable";
2028 }
2029
2030 OS << ']';
2031
2032 // Compute the index of the next operand descriptor.
2033 AsmDescOp += 1 + F.getNumOperandRegisters();
2034 } else if (MO.isImm() && isOperandSubregIdx(OpIdx: i)) {
2035 MachineOperand::printSubRegIdx(OS, Index: MO.getImm(), TRI);
2036 } else {
2037 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{};
2038 unsigned TiedOperandIdx = GetTiedOperandIdx(i);
2039 MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone,
2040 ShouldPrintRegisterTies, TiedOperandIdx, TRI);
2041 }
2042 }
2043
2044 // Print any optional symbols attached to this instruction as-if they were
2045 // operands.
2046 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
2047 if (!FirstOp) {
2048 OS << ',';
2049 }
2050 OS << " pre-instr-symbol ";
2051 MachineOperand::printSymbol(OS, Sym&: *PreInstrSymbol);
2052 }
2053 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
2054 if (!FirstOp) {
2055 OS << ',';
2056 }
2057 OS << " post-instr-symbol ";
2058 MachineOperand::printSymbol(OS, Sym&: *PostInstrSymbol);
2059 }
2060 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
2061 if (!FirstOp) {
2062 OS << ',';
2063 }
2064 OS << " heap-alloc-marker ";
2065 HeapAllocMarker->printAsOperand(OS, MST);
2066 }
2067 if (MDNode *PCSections = getPCSections()) {
2068 if (!FirstOp) {
2069 OS << ',';
2070 }
2071 OS << " pcsections ";
2072 PCSections->printAsOperand(OS, MST);
2073 }
2074 if (MDNode *MMRA = getMMRAMetadata()) {
2075 if (!FirstOp) {
2076 OS << ',';
2077 }
2078 OS << " mmra ";
2079 MMRA->printAsOperand(OS, MST);
2080 }
2081 if (uint32_t CFIType = getCFIType()) {
2082 if (!FirstOp)
2083 OS << ',';
2084 OS << " cfi-type " << CFIType;
2085 }
2086 if (getDeactivationSymbol())
2087 OS << ", deactivation-symbol " << getDeactivationSymbol()->getName();
2088
2089 if (DebugInstrNum) {
2090 if (!FirstOp)
2091 OS << ",";
2092 OS << " debug-instr-number " << DebugInstrNum;
2093 }
2094
2095 if (!SkipDebugLoc) {
2096 if (const DebugLoc &DL = getDebugLoc()) {
2097 if (!FirstOp)
2098 OS << ',';
2099 OS << " debug-location ";
2100 DL->printAsOperand(OS, MST);
2101 }
2102 }
2103
2104 if (!memoperands_empty()) {
2105 SmallVector<StringRef, 0> SSNs;
2106 const LLVMContext *Context = nullptr;
2107 std::unique_ptr<LLVMContext> CtxPtr;
2108 const MachineFrameInfo *MFI = nullptr;
2109 if (const MachineFunction *MF = getMFIfAvailable(MI: *this)) {
2110 MFI = &MF->getFrameInfo();
2111 Context = &MF->getFunction().getContext();
2112 } else {
2113 CtxPtr = std::make_unique<LLVMContext>();
2114 Context = CtxPtr.get();
2115 }
2116
2117 OS << " :: ";
2118 bool NeedComma = false;
2119 for (const MachineMemOperand *Op : memoperands()) {
2120 if (NeedComma)
2121 OS << ", ";
2122 Op->print(OS, MST, SSNs, Context: *Context, MFI, TII);
2123 NeedComma = true;
2124 }
2125 }
2126
2127 if (SkipDebugLoc)
2128 return;
2129
2130 bool HaveSemi = false;
2131
2132 // Print debug location information.
2133 if (const DebugLoc &DL = getDebugLoc()) {
2134 if (!HaveSemi) {
2135 OS << ';';
2136 HaveSemi = true;
2137 }
2138 OS << ' ';
2139 DL.print(OS);
2140 }
2141
2142 // Print extra comments for DEBUG_VALUE and friends if they are well-formed.
2143 if ((isNonListDebugValue() && getNumOperands() >= 4) ||
2144 (isDebugValueList() && getNumOperands() >= 2) ||
2145 (isDebugRef() && getNumOperands() >= 3)) {
2146 if (getDebugVariableOp().isMetadata()) {
2147 if (!HaveSemi) {
2148 OS << ";";
2149 HaveSemi = true;
2150 }
2151 auto *DV = getDebugVariable();
2152 OS << " line no:" << DV->getLine();
2153 if (isIndirectDebugValue())
2154 OS << " indirect";
2155 }
2156 }
2157 // TODO: DBG_LABEL
2158
2159 if (PrintMIAddrs)
2160 OS << " ; " << this;
2161
2162 if (AddNewLine)
2163 OS << '\n';
2164}
2165
2166bool MachineInstr::addRegisterKilled(Register IncomingReg,
2167 const TargetRegisterInfo *RegInfo,
2168 bool AddIfNotFound) {
2169 bool isPhysReg = IncomingReg.isPhysical();
2170 bool hasAliases = isPhysReg &&
2171 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
2172 bool Found = false;
2173 SmallVector<unsigned,4> DeadOps;
2174 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2175 MachineOperand &MO = getOperand(i);
2176 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
2177 continue;
2178
2179 // DEBUG_VALUE nodes do not contribute to code generation and should
2180 // always be ignored. Failure to do so may result in trying to modify
2181 // KILL flags on DEBUG_VALUE nodes.
2182 if (MO.isDebug())
2183 continue;
2184
2185 Register Reg = MO.getReg();
2186 if (!Reg)
2187 continue;
2188
2189 if (Reg == IncomingReg) {
2190 if (!Found) {
2191 if (MO.isKill())
2192 // The register is already marked kill.
2193 return true;
2194 if (isPhysReg && isRegTiedToDefOperand(UseOpIdx: i))
2195 // Two-address uses of physregs must not be marked kill.
2196 return true;
2197 MO.setIsKill();
2198 Found = true;
2199 }
2200 } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {
2201 // A super-register kill already exists.
2202 if (RegInfo->isSuperRegister(RegA: IncomingReg, RegB: Reg))
2203 return true;
2204 if (RegInfo->isSubRegister(RegA: IncomingReg, RegB: Reg))
2205 DeadOps.push_back(Elt: i);
2206 }
2207 }
2208
2209 // Trim unneeded kill operands.
2210 while (!DeadOps.empty()) {
2211 unsigned OpIdx = DeadOps.back();
2212 if (getOperand(i: OpIdx).isImplicit() &&
2213 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2214 removeOperand(OpNo: OpIdx);
2215 else
2216 getOperand(i: OpIdx).setIsKill(false);
2217 DeadOps.pop_back();
2218 }
2219
2220 // If not found, this means an alias of one of the operands is killed. Add a
2221 // new implicit operand if required.
2222 if (!Found && AddIfNotFound) {
2223 addOperand(Op: MachineOperand::CreateReg(Reg: IncomingReg,
2224 isDef: false /*IsDef*/,
2225 isImp: true /*IsImp*/,
2226 isKill: true /*IsKill*/));
2227 return true;
2228 }
2229 return Found;
2230}
2231
2232void MachineInstr::clearRegisterKills(Register Reg,
2233 const TargetRegisterInfo *RegInfo) {
2234 if (!Reg.isPhysical())
2235 RegInfo = nullptr;
2236 for (MachineOperand &MO : operands()) {
2237 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2238 continue;
2239 Register OpReg = MO.getReg();
2240 if ((RegInfo && RegInfo->regsOverlap(RegA: Reg, RegB: OpReg)) || Reg == OpReg)
2241 MO.setIsKill(false);
2242 }
2243}
2244
2245bool MachineInstr::addRegisterDead(Register Reg,
2246 const TargetRegisterInfo *RegInfo,
2247 bool AddIfNotFound) {
2248 bool isPhysReg = Reg.isPhysical();
2249 bool hasAliases = isPhysReg &&
2250 MCRegAliasIterator(Reg, RegInfo, false).isValid();
2251 bool Found = false;
2252 SmallVector<unsigned,4> DeadOps;
2253 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2254 MachineOperand &MO = getOperand(i);
2255 if (!MO.isReg() || !MO.isDef())
2256 continue;
2257 Register MOReg = MO.getReg();
2258 if (!MOReg)
2259 continue;
2260
2261 if (MOReg == Reg) {
2262 MO.setIsDead();
2263 Found = true;
2264 } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {
2265 // There exists a super-register that's marked dead.
2266 if (RegInfo->isSuperRegister(RegA: Reg, RegB: MOReg))
2267 return true;
2268 if (RegInfo->isSubRegister(RegA: Reg, RegB: MOReg))
2269 DeadOps.push_back(Elt: i);
2270 }
2271 }
2272
2273 // Trim unneeded dead operands.
2274 while (!DeadOps.empty()) {
2275 unsigned OpIdx = DeadOps.back();
2276 if (getOperand(i: OpIdx).isImplicit() &&
2277 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2278 removeOperand(OpNo: OpIdx);
2279 else
2280 getOperand(i: OpIdx).setIsDead(false);
2281 DeadOps.pop_back();
2282 }
2283
2284 // If not found, this means an alias of one of the operands is dead. Add a
2285 // new implicit operand if required.
2286 if (Found || !AddIfNotFound)
2287 return Found;
2288
2289 addOperand(Op: MachineOperand::CreateReg(Reg,
2290 isDef: true /*IsDef*/,
2291 isImp: true /*IsImp*/,
2292 isKill: false /*IsKill*/,
2293 isDead: true /*IsDead*/));
2294 return true;
2295}
2296
2297void MachineInstr::clearRegisterDeads(Register Reg) {
2298 for (MachineOperand &MO : all_defs())
2299 if (MO.getReg() == Reg)
2300 MO.setIsDead(false);
2301}
2302
2303void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2304 for (MachineOperand &MO : all_defs())
2305 if (MO.getReg() == Reg && MO.getSubReg() != 0)
2306 MO.setIsUndef(IsUndef);
2307}
2308
2309void MachineInstr::addRegisterDefined(Register Reg,
2310 const TargetRegisterInfo *RegInfo) {
2311 if (Reg.isPhysical()) {
2312 MachineOperand *MO = findRegisterDefOperand(Reg, TRI: RegInfo, isDead: false, Overlap: false);
2313 if (MO)
2314 return;
2315 } else {
2316 for (const MachineOperand &MO : all_defs()) {
2317 if (MO.getReg() == Reg && MO.getSubReg() == 0)
2318 return;
2319 }
2320 }
2321 addOperand(Op: MachineOperand::CreateReg(Reg,
2322 isDef: true /*IsDef*/,
2323 isImp: true /*IsImp*/));
2324}
2325
2326void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2327 const TargetRegisterInfo &TRI) {
2328 bool HasRegMask = false;
2329 for (MachineOperand &MO : operands()) {
2330 if (MO.isRegMask()) {
2331 HasRegMask = true;
2332 continue;
2333 }
2334 if (!MO.isReg() || !MO.isDef()) continue;
2335 Register Reg = MO.getReg();
2336 if (!Reg.isPhysical())
2337 continue;
2338 // If there are no uses, including partial uses, the def is dead.
2339 if (llvm::none_of(Range&: UsedRegs,
2340 P: [&](MCRegister Use) { return TRI.regsOverlap(RegA: Use, RegB: Reg); }))
2341 MO.setIsDead();
2342 }
2343
2344 // This is a call with a register mask operand.
2345 // Mask clobbers are always dead, so add defs for the non-dead defines.
2346 if (HasRegMask)
2347 for (const Register &UsedReg : UsedRegs)
2348 addRegisterDefined(Reg: UsedReg, RegInfo: &TRI);
2349}
2350
2351unsigned
2352MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2353 // Build up a buffer of hash code components.
2354 SmallVector<size_t, 16> HashComponents;
2355 HashComponents.reserve(N: MI->getNumOperands() + 1);
2356 HashComponents.push_back(Elt: MI->getOpcode());
2357 for (const MachineOperand &MO : MI->operands()) {
2358 if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
2359 continue; // Skip virtual register defs.
2360
2361 HashComponents.push_back(Elt: hash_value(MO));
2362 }
2363 return hash_combine_range(R&: HashComponents);
2364}
2365
2366const MDNode *MachineInstr::getLocCookieMD() const {
2367 // Find the source location cookie.
2368 const MDNode *LocMD = nullptr;
2369 for (unsigned i = getNumOperands(); i != 0; --i) {
2370 if (getOperand(i: i-1).isMetadata() &&
2371 (LocMD = getOperand(i: i-1).getMetadata()) &&
2372 LocMD->getNumOperands() != 0) {
2373 if (mdconst::hasa<ConstantInt>(MD: LocMD->getOperand(I: 0)))
2374 return LocMD;
2375 }
2376 }
2377
2378 return nullptr;
2379}
2380
2381void MachineInstr::emitInlineAsmError(const Twine &Msg) const {
2382 assert(isInlineAsm());
2383 const MDNode *LocMD = getLocCookieMD();
2384 uint64_t LocCookie =
2385 LocMD
2386 ? mdconst::extract<ConstantInt>(MD: LocMD->getOperand(I: 0))->getZExtValue()
2387 : 0;
2388 LLVMContext &Ctx = getMF()->getFunction().getContext();
2389 Ctx.diagnose(DI: DiagnosticInfoInlineAsm(LocCookie, Msg));
2390}
2391
2392void MachineInstr::emitGenericError(const Twine &Msg) const {
2393 const Function &Fn = getMF()->getFunction();
2394 Fn.getContext().diagnose(
2395 DI: DiagnosticInfoGenericWithLoc(Msg, Fn, getDebugLoc()));
2396}
2397
2398MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2399 const MCInstrDesc &MCID, bool IsIndirect,
2400 Register Reg, const MDNode *Variable,
2401 const MDNode *Expr) {
2402 assert(isa<DILocalVariable>(Variable) && "not a variable");
2403 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2404 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2405 "Expected inlined-at fields to agree");
2406 auto MIB = BuildMI(MF, MIMD: DL, MCID).addReg(RegNo: Reg);
2407 if (IsIndirect)
2408 MIB.addImm(Val: 0U);
2409 else
2410 MIB.addReg(RegNo: 0U);
2411 return MIB.addMetadata(MD: Variable).addMetadata(MD: Expr);
2412}
2413
2414MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2415 const MCInstrDesc &MCID, bool IsIndirect,
2416 ArrayRef<MachineOperand> DebugOps,
2417 const MDNode *Variable, const MDNode *Expr) {
2418 assert(isa<DILocalVariable>(Variable) && "not a variable");
2419 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2420 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2421 "Expected inlined-at fields to agree");
2422 if (MCID.Opcode == TargetOpcode::DBG_VALUE) {
2423 assert(DebugOps.size() == 1 &&
2424 "DBG_VALUE must contain exactly one debug operand");
2425 MachineOperand DebugOp = DebugOps[0];
2426 if (DebugOp.isReg())
2427 return BuildMI(MF, DL, MCID, IsIndirect, Reg: DebugOp.getReg(), Variable,
2428 Expr);
2429
2430 auto MIB = BuildMI(MF, MIMD: DL, MCID).add(MO: DebugOp);
2431 if (IsIndirect)
2432 MIB.addImm(Val: 0U);
2433 else
2434 MIB.addReg(RegNo: 0U);
2435 return MIB.addMetadata(MD: Variable).addMetadata(MD: Expr);
2436 }
2437
2438 auto MIB = BuildMI(MF, MIMD: DL, MCID);
2439 MIB.addMetadata(MD: Variable).addMetadata(MD: Expr);
2440 for (const MachineOperand &DebugOp : DebugOps)
2441 if (DebugOp.isReg())
2442 MIB.addReg(RegNo: DebugOp.getReg());
2443 else
2444 MIB.add(MO: DebugOp);
2445 return MIB;
2446}
2447
2448MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2449 MachineBasicBlock::iterator I,
2450 const DebugLoc &DL, const MCInstrDesc &MCID,
2451 bool IsIndirect, Register Reg,
2452 const MDNode *Variable, const MDNode *Expr) {
2453 MachineFunction &MF = *BB.getParent();
2454 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2455 BB.insert(I, MI);
2456 return MachineInstrBuilder(MF, MI);
2457}
2458
2459MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2460 MachineBasicBlock::iterator I,
2461 const DebugLoc &DL, const MCInstrDesc &MCID,
2462 bool IsIndirect,
2463 ArrayRef<MachineOperand> DebugOps,
2464 const MDNode *Variable, const MDNode *Expr) {
2465 MachineFunction &MF = *BB.getParent();
2466 MachineInstr *MI =
2467 BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2468 BB.insert(I, MI);
2469 return MachineInstrBuilder(MF, *MI);
2470}
2471
2472/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2473/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2474static const DIExpression *computeExprForSpill(
2475 const MachineInstr &MI,
2476 const SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2477 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2478 "Expected inlined-at fields to agree");
2479
2480 const DIExpression *Expr = MI.getDebugExpression();
2481 if (MI.isIndirectDebugValue()) {
2482 assert(MI.getDebugOffset().getImm() == 0 &&
2483 "DBG_VALUE with nonzero offset");
2484 Expr = DIExpression::prepend(Expr, Flags: DIExpression::DerefBefore);
2485 } else if (MI.isDebugValueList()) {
2486 // We will replace the spilled register with a frame index, so
2487 // immediately deref all references to the spilled register.
2488 std::array<uint64_t, 1> Ops{._M_elems: {dwarf::DW_OP_deref}};
2489 for (const MachineOperand *Op : SpilledOperands) {
2490 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2491 Expr = DIExpression::appendOpsToArg(Expr, Ops, ArgNo: OpIdx);
2492 }
2493 }
2494 return Expr;
2495}
2496static const DIExpression *computeExprForSpill(const MachineInstr &MI,
2497 Register SpillReg) {
2498 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2499 SmallVector<const MachineOperand *> SpillOperands(
2500 llvm::make_pointer_range(Range: MI.getDebugOperandsForReg(Reg: SpillReg)));
2501 return computeExprForSpill(MI, SpilledOperands: SpillOperands);
2502}
2503
2504MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2505 MachineBasicBlock::iterator I,
2506 const MachineInstr &Orig,
2507 int FrameIndex, Register SpillReg) {
2508 assert(!Orig.isDebugRef() &&
2509 "DBG_INSTR_REF should not reference a virtual register.");
2510 const DIExpression *Expr = computeExprForSpill(MI: Orig, SpillReg);
2511 MachineInstrBuilder NewMI =
2512 BuildMI(BB, I, MIMD: Orig.getDebugLoc(), MCID: Orig.getDesc());
2513 // Non-Variadic Operands: Location, Offset, Variable, Expression
2514 // Variadic Operands: Variable, Expression, Locations...
2515 if (Orig.isNonListDebugValue())
2516 NewMI.addFrameIndex(Idx: FrameIndex).addImm(Val: 0U);
2517 NewMI.addMetadata(MD: Orig.getDebugVariable()).addMetadata(MD: Expr);
2518 if (Orig.isDebugValueList()) {
2519 for (const MachineOperand &Op : Orig.debug_operands())
2520 if (Op.isReg() && Op.getReg() == SpillReg)
2521 NewMI.addFrameIndex(Idx: FrameIndex);
2522 else
2523 NewMI.add(MO: MachineOperand(Op));
2524 }
2525 return NewMI;
2526}
2527MachineInstr *llvm::buildDbgValueForSpill(
2528 MachineBasicBlock &BB, MachineBasicBlock::iterator I,
2529 const MachineInstr &Orig, int FrameIndex,
2530 const SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2531 const DIExpression *Expr = computeExprForSpill(MI: Orig, SpilledOperands);
2532 MachineInstrBuilder NewMI =
2533 BuildMI(BB, I, MIMD: Orig.getDebugLoc(), MCID: Orig.getDesc());
2534 // Non-Variadic Operands: Location, Offset, Variable, Expression
2535 // Variadic Operands: Variable, Expression, Locations...
2536 if (Orig.isNonListDebugValue())
2537 NewMI.addFrameIndex(Idx: FrameIndex).addImm(Val: 0U);
2538 NewMI.addMetadata(MD: Orig.getDebugVariable()).addMetadata(MD: Expr);
2539 if (Orig.isDebugValueList()) {
2540 for (const MachineOperand &Op : Orig.debug_operands())
2541 if (is_contained(Range: SpilledOperands, Element: &Op))
2542 NewMI.addFrameIndex(Idx: FrameIndex);
2543 else
2544 NewMI.add(MO: MachineOperand(Op));
2545 }
2546 return NewMI;
2547}
2548
2549void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex,
2550 Register Reg) {
2551 const DIExpression *Expr = computeExprForSpill(MI: Orig, SpillReg: Reg);
2552 if (Orig.isNonListDebugValue())
2553 Orig.getDebugOffset().ChangeToImmediate(ImmVal: 0U);
2554 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2555 Op.ChangeToFrameIndex(Idx: FrameIndex);
2556 Orig.getDebugExpressionOp().setMetadata(Expr);
2557}
2558
2559void MachineInstr::collectDebugValues(
2560 SmallVectorImpl<MachineInstr *> &DbgValues) {
2561 MachineInstr &MI = *this;
2562 if (!MI.getOperand(i: 0).isReg())
2563 return;
2564
2565 MachineBasicBlock::iterator DI = MI; ++DI;
2566 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2567 DI != DE; ++DI) {
2568 if (!DI->isDebugValue())
2569 return;
2570 if (DI->hasDebugOperandForReg(Reg: MI.getOperand(i: 0).getReg()))
2571 DbgValues.push_back(Elt: &*DI);
2572 }
2573}
2574
2575void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2576 // Collect matching debug values.
2577 SmallVector<MachineInstr *, 2> DbgValues;
2578
2579 if (!getOperand(i: 0).isReg())
2580 return;
2581
2582 Register DefReg = getOperand(i: 0).getReg();
2583 auto *MRI = getRegInfo();
2584 for (MachineInstr &DI : MRI->use_instructions(Reg: DefReg)) {
2585 if (!DI.isDebugValue())
2586 continue;
2587 if (DI.hasDebugOperandForReg(Reg: DefReg)) {
2588 DbgValues.push_back(Elt: &DI);
2589 }
2590 }
2591
2592 // Propagate Reg to debug value instructions.
2593 for (auto *DBI : DbgValues)
2594 for (MachineOperand &Op : DBI->getDebugOperandsForReg(Reg: DefReg))
2595 Op.setReg(Reg);
2596}
2597
2598using MMOList = SmallVector<const MachineMemOperand *, 2>;
2599
2600static LocationSize getSpillSlotSize(const MMOList &Accesses,
2601 const MachineFrameInfo &MFI) {
2602 std::optional<TypeSize> Size;
2603 for (const auto *A : Accesses) {
2604 if (MFI.isSpillSlotObjectIndex(
2605 ObjectIdx: cast<FixedStackPseudoSourceValue>(Val: A->getPseudoValue())
2606 ->getFrameIndex())) {
2607 LocationSize S = A->getSize();
2608 if (!S.hasValue())
2609 return LocationSize::beforeOrAfterPointer();
2610 if (!Size)
2611 Size = S.getValue();
2612 else
2613 Size = *Size + S.getValue();
2614 }
2615 }
2616 if (!Size)
2617 return LocationSize::precise(Value: 0);
2618 return LocationSize::precise(Value: *Size);
2619}
2620
2621std::optional<LocationSize>
2622MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2623 int FI;
2624 if (TII->isStoreToStackSlotPostFE(MI: *this, FrameIndex&: FI)) {
2625 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2626 if (MFI.isSpillSlotObjectIndex(ObjectIdx: FI))
2627 return (*memoperands_begin())->getSize();
2628 }
2629 return std::nullopt;
2630}
2631
2632std::optional<LocationSize>
2633MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2634 if (!mayStore())
2635 return std::nullopt;
2636
2637 MMOList Accesses;
2638 if (TII->hasStoreToStackSlot(MI: *this, Accesses))
2639 return getSpillSlotSize(Accesses, MFI: getMF()->getFrameInfo());
2640 return std::nullopt;
2641}
2642
2643std::optional<LocationSize>
2644MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2645 int FI;
2646 if (TII->isLoadFromStackSlotPostFE(MI: *this, FrameIndex&: FI)) {
2647 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2648 if (MFI.isSpillSlotObjectIndex(ObjectIdx: FI))
2649 return (*memoperands_begin())->getSize();
2650 }
2651 return std::nullopt;
2652}
2653
2654std::optional<LocationSize>
2655MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2656 MMOList Accesses;
2657 if (TII->hasLoadFromStackSlot(MI: *this, Accesses))
2658 return getSpillSlotSize(Accesses, MFI: getMF()->getFrameInfo());
2659 return std::nullopt;
2660}
2661
2662unsigned MachineInstr::getDebugInstrNum() {
2663 if (DebugInstrNum == 0)
2664 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2665 return DebugInstrNum;
2666}
2667
2668unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {
2669 if (DebugInstrNum == 0)
2670 DebugInstrNum = MF.getNewDebugInstrNum();
2671 return DebugInstrNum;
2672}
2673
2674std::tuple<LLT, LLT> MachineInstr::getFirst2LLTs() const {
2675 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2676 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()));
2677}
2678
2679std::tuple<LLT, LLT, LLT> MachineInstr::getFirst3LLTs() const {
2680 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2681 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()),
2682 getRegInfo()->getType(Reg: getOperand(i: 2).getReg()));
2683}
2684
2685std::tuple<LLT, LLT, LLT, LLT> MachineInstr::getFirst4LLTs() const {
2686 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2687 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()),
2688 getRegInfo()->getType(Reg: getOperand(i: 2).getReg()),
2689 getRegInfo()->getType(Reg: getOperand(i: 3).getReg()));
2690}
2691
2692std::tuple<LLT, LLT, LLT, LLT, LLT> MachineInstr::getFirst5LLTs() const {
2693 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2694 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()),
2695 getRegInfo()->getType(Reg: getOperand(i: 2).getReg()),
2696 getRegInfo()->getType(Reg: getOperand(i: 3).getReg()),
2697 getRegInfo()->getType(Reg: getOperand(i: 4).getReg()));
2698}
2699
2700std::tuple<Register, LLT, Register, LLT>
2701MachineInstr::getFirst2RegLLTs() const {
2702 Register Reg0 = getOperand(i: 0).getReg();
2703 Register Reg1 = getOperand(i: 1).getReg();
2704 return std::tuple(Reg0, getRegInfo()->getType(Reg: Reg0), Reg1,
2705 getRegInfo()->getType(Reg: Reg1));
2706}
2707
2708std::tuple<Register, LLT, Register, LLT, Register, LLT>
2709MachineInstr::getFirst3RegLLTs() const {
2710 Register Reg0 = getOperand(i: 0).getReg();
2711 Register Reg1 = getOperand(i: 1).getReg();
2712 Register Reg2 = getOperand(i: 2).getReg();
2713 return std::tuple(Reg0, getRegInfo()->getType(Reg: Reg0), Reg1,
2714 getRegInfo()->getType(Reg: Reg1), Reg2,
2715 getRegInfo()->getType(Reg: Reg2));
2716}
2717
2718std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2719MachineInstr::getFirst4RegLLTs() const {
2720 Register Reg0 = getOperand(i: 0).getReg();
2721 Register Reg1 = getOperand(i: 1).getReg();
2722 Register Reg2 = getOperand(i: 2).getReg();
2723 Register Reg3 = getOperand(i: 3).getReg();
2724 return std::tuple(
2725 Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, getRegInfo()->getType(Reg: Reg1),
2726 Reg2, getRegInfo()->getType(Reg: Reg2), Reg3, getRegInfo()->getType(Reg: Reg3));
2727}
2728
2729std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register,
2730 LLT>
2731MachineInstr::getFirst5RegLLTs() const {
2732 Register Reg0 = getOperand(i: 0).getReg();
2733 Register Reg1 = getOperand(i: 1).getReg();
2734 Register Reg2 = getOperand(i: 2).getReg();
2735 Register Reg3 = getOperand(i: 3).getReg();
2736 Register Reg4 = getOperand(i: 4).getReg();
2737 return std::tuple(
2738 Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, getRegInfo()->getType(Reg: Reg1),
2739 Reg2, getRegInfo()->getType(Reg: Reg2), Reg3, getRegInfo()->getType(Reg: Reg3),
2740 Reg4, getRegInfo()->getType(Reg: Reg4));
2741}
2742
2743void MachineInstr::insert(mop_iterator InsertBefore,
2744 ArrayRef<MachineOperand> Ops) {
2745 assert(InsertBefore != nullptr && "invalid iterator");
2746 assert(InsertBefore->getParent() == this &&
2747 "iterator points to operand of other inst");
2748 if (Ops.empty())
2749 return;
2750
2751 // Do one pass to untie operands.
2752 SmallDenseMap<unsigned, unsigned> TiedOpIndices;
2753 for (const MachineOperand &MO : operands()) {
2754 if (MO.isReg() && MO.isTied()) {
2755 unsigned OpNo = getOperandNo(I: &MO);
2756 unsigned TiedTo = findTiedOperandIdx(OpIdx: OpNo);
2757 TiedOpIndices[OpNo] = TiedTo;
2758 untieRegOperand(OpIdx: OpNo);
2759 }
2760 }
2761
2762 unsigned OpIdx = getOperandNo(I: InsertBefore);
2763 SmallVector<MachineOperand> MovingOps(InsertBefore, operands_end());
2764
2765 for (unsigned I = getNumOperands(); I > OpIdx; --I)
2766 removeOperand(OpNo: I - 1);
2767 for (const MachineOperand &MO : Ops)
2768 addOperand(Op: MO);
2769 for (const MachineOperand &OpMoved : MovingOps)
2770 addOperand(Op: OpMoved);
2771
2772 // Re-tie operands.
2773 for (auto [Tie1, Tie2] : TiedOpIndices) {
2774 if (Tie1 >= OpIdx)
2775 Tie1 += Ops.size();
2776 if (Tie2 >= OpIdx)
2777 Tie2 += Ops.size();
2778 tieOperands(DefIdx: Tie1, UseIdx: Tie2);
2779 }
2780}
2781
2782bool MachineInstr::mayFoldInlineAsmRegOp(unsigned OpId) const {
2783 assert(OpId && "expected non-zero operand id");
2784 assert(isInlineAsm() && "should only be used on inline asm");
2785
2786 if (!getOperand(i: OpId).isReg())
2787 return false;
2788
2789 const MachineOperand &MD = getOperand(i: OpId - 1);
2790 if (!MD.isImm())
2791 return false;
2792
2793 InlineAsm::Flag F(MD.getImm());
2794 if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind())
2795 return F.getRegMayBeFolded();
2796 return false;
2797}
2798
2799unsigned MachineInstr::removePHIIncomingValueFor(const MachineBasicBlock &MBB) {
2800 assert(isPHI());
2801
2802 // Phi might have multiple entries for MBB. Need to remove them all.
2803 unsigned RemovedCount = 0;
2804 for (unsigned N = getNumOperands(); N > 2; N -= 2) {
2805 if (getOperand(i: N - 1).getMBB() == &MBB) {
2806 removeOperand(OpNo: N - 1);
2807 removeOperand(OpNo: N - 2);
2808 RemovedCount += 2;
2809 }
2810 }
2811 return RemovedCount;
2812}
2813