1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/Hashing.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallBitVector.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/Analysis/AliasAnalysis.h"
20#include "llvm/Analysis/MemoryLocation.h"
21#include "llvm/CodeGen/LiveRegUnits.h"
22#include "llvm/CodeGen/MachineBasicBlock.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineInstrBundle.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/Register.h"
33#include "llvm/CodeGen/StackMaps.h"
34#include "llvm/CodeGen/TargetInstrInfo.h"
35#include "llvm/CodeGen/TargetRegisterInfo.h"
36#include "llvm/CodeGen/TargetSubtargetInfo.h"
37#include "llvm/CodeGenTypes/LowLevelType.h"
38#include "llvm/IR/Constants.h"
39#include "llvm/IR/DebugInfoMetadata.h"
40#include "llvm/IR/DebugLoc.h"
41#include "llvm/IR/Function.h"
42#include "llvm/IR/InlineAsm.h"
43#include "llvm/IR/Instructions.h"
44#include "llvm/IR/LLVMContext.h"
45#include "llvm/IR/Metadata.h"
46#include "llvm/IR/Module.h"
47#include "llvm/IR/ModuleSlotTracker.h"
48#include "llvm/IR/Operator.h"
49#include "llvm/MC/MCInstrDesc.h"
50#include "llvm/MC/MCRegisterInfo.h"
51#include "llvm/Support/Casting.h"
52#include "llvm/Support/Compiler.h"
53#include "llvm/Support/Debug.h"
54#include "llvm/Support/ErrorHandling.h"
55#include "llvm/Support/FormattedStream.h"
56#include "llvm/Support/raw_ostream.h"
57#include "llvm/Target/TargetMachine.h"
58#include <algorithm>
59#include <cassert>
60#include <cstdint>
61#include <cstring>
62#include <utility>
63
64using namespace llvm;
65
66static cl::opt<bool>
67 PrintMIAddrs("print-mi-addrs", cl::Hidden,
68 cl::desc("Print addresses of MachineInstrs when dumping"));
69
70static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
71 if (const MachineBasicBlock *MBB = MI.getParent())
72 if (const MachineFunction *MF = MBB->getParent())
73 return MF;
74 return nullptr;
75}
76
77// Try to crawl up to the machine function and get TRI/MRI/TII from it.
78static void tryToGetTargetInfo(const MachineInstr &MI,
79 const TargetRegisterInfo *&TRI,
80 const MachineRegisterInfo *&MRI,
81 const TargetInstrInfo *&TII) {
82
83 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
84 TRI = MF->getSubtarget().getRegisterInfo();
85 MRI = &MF->getRegInfo();
86 TII = MF->getSubtarget().getInstrInfo();
87 }
88}
89
90void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
91 for (MCPhysReg ImpDef : MCID->implicit_defs())
92 addOperand(MF, Op: MachineOperand::CreateReg(Reg: ImpDef, isDef: true, isImp: true));
93 for (MCPhysReg ImpUse : MCID->implicit_uses())
94 addOperand(MF, Op: MachineOperand::CreateReg(Reg: ImpUse, isDef: false, isImp: true));
95}
96
97/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
98/// implicit operands. It reserves space for the number of operands specified by
99/// the MCInstrDesc.
100MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
101 DebugLoc DL, bool NoImp)
102 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
103 Opcode(TID.Opcode), DebugInstrNum(0), DbgLoc(std::move(DL)) {
104 // Reserve space for the expected number of operands.
105 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() +
106 MCID->implicit_uses().size()) {
107 CapOperands = OperandCapacity::get(N: NumOps);
108 Operands = MF.allocateOperandArray(Cap: CapOperands);
109 }
110
111 if (!NoImp)
112 addImplicitDefUseOperands(MF);
113}
114
115/// MachineInstr ctor - Copies MachineInstr arg exactly.
116/// Does not copy the number from debug instruction numbering, to preserve
117/// uniqueness.
118MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
119 : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0),
120 Opcode(MI.getOpcode()), DebugInstrNum(0), Info(MI.Info),
121 DbgLoc(MI.getDebugLoc()) {
122 CapOperands = OperandCapacity::get(N: MI.getNumOperands());
123 Operands = MF.allocateOperandArray(Cap: CapOperands);
124
125 // Copy operands.
126 for (const MachineOperand &MO : MI.operands())
127 addOperand(MF, Op: MO);
128
129 // Replicate ties between the operands, which addOperand was not
130 // able to do reliably.
131 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
132 MachineOperand &NewMO = getOperand(i);
133 const MachineOperand &OrigMO = MI.getOperand(i);
134 NewMO.TiedTo = OrigMO.TiedTo;
135 }
136
137 // Copy all the sensible flags.
138 setFlags(MI.Flags);
139}
140
141void MachineInstr::setDesc(const MCInstrDesc &TID) {
142 if (getParent())
143 getMF()->handleChangeDesc(MI&: *this, TID);
144 MCID = &TID;
145 Opcode = TID.Opcode;
146}
147
148void MachineInstr::moveBefore(MachineInstr *MovePos) {
149 MovePos->getParent()->splice(Where: MovePos, Other: getParent(), From: getIterator());
150}
151
152/// getRegInfo - If this instruction is embedded into a MachineFunction,
153/// return the MachineRegisterInfo object for the current function, otherwise
154/// return null.
155MachineRegisterInfo *MachineInstr::getRegInfo() {
156 if (MachineBasicBlock *MBB = getParent())
157 return &MBB->getParent()->getRegInfo();
158 return nullptr;
159}
160
161const MachineRegisterInfo *MachineInstr::getRegInfo() const {
162 if (const MachineBasicBlock *MBB = getParent())
163 return &MBB->getParent()->getRegInfo();
164 return nullptr;
165}
166
167void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
168 for (MachineOperand &MO : operands())
169 if (MO.isReg())
170 MRI.removeRegOperandFromUseList(MO: &MO);
171}
172
173void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
174 for (MachineOperand &MO : operands())
175 if (MO.isReg())
176 MRI.addRegOperandToUseList(MO: &MO);
177}
178
179void MachineInstr::addOperand(const MachineOperand &Op) {
180 MachineBasicBlock *MBB = getParent();
181 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
182 MachineFunction *MF = MBB->getParent();
183 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
184 addOperand(MF&: *MF, Op);
185}
186
187/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
188/// ranges. If MRI is non-null also update use-def chains.
189static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
190 unsigned NumOps, MachineRegisterInfo *MRI) {
191 if (MRI)
192 return MRI->moveOperands(Dst, Src, NumOps);
193 // MachineOperand is a trivially copyable type so we can just use memmove.
194 assert(Dst && Src && "Unknown operands");
195 std::memmove(dest: Dst, src: Src, n: NumOps * sizeof(MachineOperand));
196}
197
198/// addOperand - Add the specified operand to the instruction. If it is an
199/// implicit operand, it is added to the end of the operand list. If it is
200/// an explicit operand it is added at the end of the explicit operand list
201/// (before the first implicit operand).
202void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
203 assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&
204 "Cannot add more operands.");
205 assert(MCID && "Cannot add operands before providing an instr descriptor");
206
207 // Check if we're adding one of our existing operands.
208 if (&Op >= Operands && &Op < Operands + NumOperands) {
209 // This is unusual: MI->addOperand(MI->getOperand(i)).
210 // If adding Op requires reallocating or moving existing operands around,
211 // the Op reference could go stale. Support it by copying Op.
212 MachineOperand CopyOp(Op);
213 return addOperand(MF, Op: CopyOp);
214 }
215
216 // Find the insert location for the new operand. Implicit registers go at
217 // the end, everything else goes before the implicit regs.
218 //
219 // FIXME: Allow mixed explicit and implicit operands on inline asm.
220 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
221 // implicit-defs, but they must not be moved around. See the FIXME in
222 // InstrEmitter.cpp.
223 unsigned OpNo = getNumOperands();
224 bool isImpReg = Op.isReg() && Op.isImplicit();
225 if (!isImpReg && !isInlineAsm()) {
226 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
227 --OpNo;
228 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
229 }
230 }
231
232 // OpNo now points as the desired insertion point. Unless this is a variadic
233 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
234 // RegMask operands go between the explicit and implicit operands.
235 MachineRegisterInfo *MRI = getRegInfo();
236
237 // Determine if the Operands array needs to be reallocated.
238 // Save the old capacity and operand array.
239 OperandCapacity OldCap = CapOperands;
240 MachineOperand *OldOperands = Operands;
241 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
242 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(N: 1);
243 Operands = MF.allocateOperandArray(Cap: CapOperands);
244 // Move the operands before the insertion point.
245 if (OpNo)
246 moveOperands(Dst: Operands, Src: OldOperands, NumOps: OpNo, MRI);
247 }
248
249 // Move the operands following the insertion point.
250 if (OpNo != NumOperands)
251 moveOperands(Dst: Operands + OpNo + 1, Src: OldOperands + OpNo, NumOps: NumOperands - OpNo,
252 MRI);
253 ++NumOperands;
254
255 // Deallocate the old operand array.
256 if (OldOperands != Operands && OldOperands)
257 MF.deallocateOperandArray(Cap: OldCap, Array: OldOperands);
258
259 // Copy Op into place. It still needs to be inserted into the MRI use lists.
260 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
261 NewMO->ParentMI = this;
262
263 // When adding a register operand, tell MRI about it.
264 if (NewMO->isReg()) {
265 // Ensure isOnRegUseList() returns false, regardless of Op's status.
266 NewMO->Contents.Reg.Prev = nullptr;
267 // Ignore existing ties. This is not a property that can be copied.
268 NewMO->TiedTo = 0;
269 // Add the new operand to MRI, but only for instructions in an MBB.
270 if (MRI)
271 MRI->addRegOperandToUseList(MO: NewMO);
272 // The MCID operand information isn't accurate until we start adding
273 // explicit operands. The implicit operands are added first, then the
274 // explicits are inserted before them.
275 if (!isImpReg) {
276 // Tie uses to defs as indicated in MCInstrDesc.
277 if (NewMO->isUse()) {
278 int DefIdx = MCID->getOperandConstraint(OpNum: OpNo, Constraint: MCOI::TIED_TO);
279 if (DefIdx != -1)
280 tieOperands(DefIdx, UseIdx: OpNo);
281 }
282 // If the register operand is flagged as early, mark the operand as such.
283 if (MCID->getOperandConstraint(OpNum: OpNo, Constraint: MCOI::EARLY_CLOBBER) != -1)
284 NewMO->setIsEarlyClobber(true);
285 }
286 // Ensure debug instructions set debug flag on register uses.
287 if (NewMO->isUse() && isDebugInstr())
288 NewMO->setIsDebug();
289 }
290}
291
292void MachineInstr::removeOperand(unsigned OpNo) {
293 assert(OpNo < getNumOperands() && "Invalid operand number");
294 untieRegOperand(OpIdx: OpNo);
295
296#ifndef NDEBUG
297 // Moving tied operands would break the ties.
298 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
299 if (Operands[i].isReg())
300 assert(!Operands[i].isTied() && "Cannot move tied operands");
301#endif
302
303 MachineRegisterInfo *MRI = getRegInfo();
304 if (MRI && Operands[OpNo].isReg())
305 MRI->removeRegOperandFromUseList(MO: Operands + OpNo);
306
307 // Don't call the MachineOperand destructor. A lot of this code depends on
308 // MachineOperand having a trivial destructor anyway, and adding a call here
309 // wouldn't make it 'destructor-correct'.
310
311 if (unsigned N = NumOperands - 1 - OpNo)
312 moveOperands(Dst: Operands + OpNo, Src: Operands + OpNo + 1, NumOps: N, MRI);
313 --NumOperands;
314}
315
316void MachineInstr::setExtraInfo(MachineFunction &MF,
317 ArrayRef<MachineMemOperand *> MMOs,
318 MCSymbol *PreInstrSymbol,
319 MCSymbol *PostInstrSymbol,
320 MDNode *HeapAllocMarker, MDNode *PCSections,
321 uint32_t CFIType, MDNode *MMRAs, Value *DS) {
322 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
323 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
324 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
325 bool HasPCSections = PCSections != nullptr;
326 bool HasCFIType = CFIType != 0;
327 bool HasMMRAs = MMRAs != nullptr;
328 bool HasDS = DS != nullptr;
329 int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +
330 HasHeapAllocMarker + HasPCSections + HasCFIType + HasMMRAs +
331 HasDS;
332
333 // Drop all extra info if there is none.
334 if (NumPointers <= 0) {
335 Info.clear();
336 return;
337 }
338
339 // If more than one pointer, then store out of line. Store heap alloc markers
340 // out of line because PointerSumType cannot hold more than 4 tag types with
341 // 32-bit pointers.
342 // FIXME: Maybe we should make the symbols in the extra info mutable?
343 else if (NumPointers > 1 || HasMMRAs || HasHeapAllocMarker || HasPCSections ||
344 HasCFIType || HasDS) {
345 Info.set<EIIK_OutOfLine>(
346 MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol,
347 HeapAllocMarker, PCSections, CFIType, MMRAs, DS));
348 return;
349 }
350
351 // Otherwise store the single pointer inline.
352 if (HasPreInstrSymbol)
353 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
354 else if (HasPostInstrSymbol)
355 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
356 else
357 Info.set<EIIK_MMO>(MMOs[0]);
358}
359
360void MachineInstr::dropMemRefs(MachineFunction &MF) {
361 if (memoperands_empty())
362 return;
363
364 setExtraInfo(MF, MMOs: {}, PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
365 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
366 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
367}
368
369void MachineInstr::setMemRefs(MachineFunction &MF,
370 ArrayRef<MachineMemOperand *> MMOs) {
371 if (MMOs.empty()) {
372 dropMemRefs(MF);
373 return;
374 }
375
376 setExtraInfo(MF, MMOs, PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
377 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
378 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
379}
380
381void MachineInstr::addMemOperand(MachineFunction &MF,
382 MachineMemOperand *MO) {
383 SmallVector<MachineMemOperand *, 2> MMOs;
384 MMOs.append(in_start: memoperands_begin(), in_end: memoperands_end());
385 MMOs.push_back(Elt: MO);
386 setMemRefs(MF, MMOs);
387}
388
389void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
390 if (this == &MI)
391 // Nothing to do for a self-clone!
392 return;
393
394 assert(&MF == MI.getMF() &&
395 "Invalid machine functions when cloning memory refrences!");
396 // See if we can just steal the extra info already allocated for the
397 // instruction. We can do this whenever the pre- and post-instruction symbols
398 // are the same (including null).
399 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
400 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
401 getHeapAllocMarker() == MI.getHeapAllocMarker() &&
402 getPCSections() == MI.getPCSections() && getMMRAMetadata() &&
403 MI.getMMRAMetadata()) {
404 Info = MI.Info;
405 return;
406 }
407
408 // Otherwise, fall back on a copy-based clone.
409 setMemRefs(MF, MMOs: MI.memoperands());
410}
411
412/// Check to see if the MMOs pointed to by the two MemRefs arrays are
413/// identical.
414static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
415 ArrayRef<MachineMemOperand *> RHS) {
416 if (LHS.size() != RHS.size())
417 return false;
418
419 auto LHSPointees = make_pointee_range(Range&: LHS);
420 auto RHSPointees = make_pointee_range(Range&: RHS);
421 return std::equal(first1: LHSPointees.begin(), last1: LHSPointees.end(),
422 first2: RHSPointees.begin());
423}
424
425void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
426 ArrayRef<const MachineInstr *> MIs) {
427 // Try handling easy numbers of MIs with simpler mechanisms.
428 if (MIs.empty()) {
429 dropMemRefs(MF);
430 return;
431 }
432 if (MIs.size() == 1) {
433 cloneMemRefs(MF, MI: *MIs[0]);
434 return;
435 }
436 // Because an empty memoperands list provides *no* information and must be
437 // handled conservatively (assuming the instruction can do anything), the only
438 // way to merge with it is to drop all other memoperands.
439 if (MIs[0]->memoperands_empty()) {
440 dropMemRefs(MF);
441 return;
442 }
443
444 // Handle the general case.
445 SmallVector<MachineMemOperand *, 2> MergedMMOs;
446 // Start with the first instruction.
447 assert(&MF == MIs[0]->getMF() &&
448 "Invalid machine functions when cloning memory references!");
449 MergedMMOs.append(in_start: MIs[0]->memoperands_begin(), in_end: MIs[0]->memoperands_end());
450 // Now walk all the other instructions and accumulate any different MMOs.
451 for (const MachineInstr &MI : make_pointee_range(Range: MIs.slice(N: 1))) {
452 assert(&MF == MI.getMF() &&
453 "Invalid machine functions when cloning memory references!");
454
455 // Skip MIs with identical operands to the first. This is a somewhat
456 // arbitrary hack but will catch common cases without being quadratic.
457 // TODO: We could fully implement merge semantics here if needed.
458 if (hasIdenticalMMOs(LHS: MIs[0]->memoperands(), RHS: MI.memoperands()))
459 continue;
460
461 // Because an empty memoperands list provides *no* information and must be
462 // handled conservatively (assuming the instruction can do anything), the
463 // only way to merge with it is to drop all other memoperands.
464 if (MI.memoperands_empty()) {
465 dropMemRefs(MF);
466 return;
467 }
468
469 // Otherwise accumulate these into our temporary buffer of the merged state.
470 MergedMMOs.append(in_start: MI.memoperands_begin(), in_end: MI.memoperands_end());
471 }
472
473 setMemRefs(MF, MMOs: MergedMMOs);
474}
475
476void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
477 // Do nothing if old and new symbols are the same.
478 if (Symbol == getPreInstrSymbol())
479 return;
480
481 // If there was only one symbol and we're removing it, just clear info.
482 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
483 Info.clear();
484 return;
485 }
486
487 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: Symbol, PostInstrSymbol: getPostInstrSymbol(),
488 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
489 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
490}
491
492void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
493 // Do nothing if old and new symbols are the same.
494 if (Symbol == getPostInstrSymbol())
495 return;
496
497 // If there was only one symbol and we're removing it, just clear info.
498 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
499 Info.clear();
500 return;
501 }
502
503 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: Symbol,
504 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
505 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
506}
507
508void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
509 // Do nothing if old and new symbols are the same.
510 if (Marker == getHeapAllocMarker())
511 return;
512
513 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
514 HeapAllocMarker: Marker, PCSections: getPCSections(), CFIType: getCFIType(), MMRAs: getMMRAMetadata(),
515 DS: getDeactivationSymbol());
516}
517
518void MachineInstr::setPCSections(MachineFunction &MF, MDNode *PCSections) {
519 // Do nothing if old and new symbols are the same.
520 if (PCSections == getPCSections())
521 return;
522
523 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
524 HeapAllocMarker: getHeapAllocMarker(), PCSections, CFIType: getCFIType(),
525 MMRAs: getMMRAMetadata(), DS: getDeactivationSymbol());
526}
527
528void MachineInstr::setCFIType(MachineFunction &MF, uint32_t Type) {
529 // Do nothing if old and new types are the same.
530 if (Type == getCFIType())
531 return;
532
533 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
534 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: Type, MMRAs: getMMRAMetadata(),
535 DS: getDeactivationSymbol());
536}
537
538void MachineInstr::setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs) {
539 // Do nothing if old and new symbols are the same.
540 if (MMRAs == getMMRAMetadata())
541 return;
542
543 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
544 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(), MMRAs,
545 DS: getDeactivationSymbol());
546}
547
548void MachineInstr::setDeactivationSymbol(MachineFunction &MF, Value *DS) {
549 // Do nothing if old and new symbols are the same.
550 if (DS == getDeactivationSymbol())
551 return;
552
553 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
554 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
555 MMRAs: getMMRAMetadata(), DS);
556}
557
558void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
559 const MachineInstr &MI) {
560 if (this == &MI)
561 // Nothing to do for a self-clone!
562 return;
563
564 assert(&MF == MI.getMF() &&
565 "Invalid machine functions when cloning instruction symbols!");
566
567 setPreInstrSymbol(MF, Symbol: MI.getPreInstrSymbol());
568 setPostInstrSymbol(MF, Symbol: MI.getPostInstrSymbol());
569 setHeapAllocMarker(MF, Marker: MI.getHeapAllocMarker());
570 setPCSections(MF, PCSections: MI.getPCSections());
571 setMMRAMetadata(MF, MMRAs: MI.getMMRAMetadata());
572}
573
574uint32_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
575 // For now, the just return the union of the flags. If the flags get more
576 // complicated over time, we might need more logic here.
577 return getFlags() | Other.getFlags();
578}
579
580uint32_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
581 uint32_t MIFlags = 0;
582 // Copy the wrapping flags.
583 if (const OverflowingBinaryOperator *OB =
584 dyn_cast<OverflowingBinaryOperator>(Val: &I)) {
585 if (OB->hasNoSignedWrap())
586 MIFlags |= MachineInstr::MIFlag::NoSWrap;
587 if (OB->hasNoUnsignedWrap())
588 MIFlags |= MachineInstr::MIFlag::NoUWrap;
589 } else if (const TruncInst *TI = dyn_cast<TruncInst>(Val: &I)) {
590 if (TI->hasNoSignedWrap())
591 MIFlags |= MachineInstr::MIFlag::NoSWrap;
592 if (TI->hasNoUnsignedWrap())
593 MIFlags |= MachineInstr::MIFlag::NoUWrap;
594 } else if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Val: &I)) {
595 if (GEP->hasNoUnsignedSignedWrap())
596 MIFlags |= MachineInstr::MIFlag::NoUSWrap;
597 if (GEP->hasNoUnsignedWrap())
598 MIFlags |= MachineInstr::MIFlag::NoUWrap;
599 if (GEP->isInBounds())
600 MIFlags |= MachineInstr::MIFlag::InBounds;
601 }
602
603 // Copy the nonneg flag.
604 if (const PossiblyNonNegInst *PNI = dyn_cast<PossiblyNonNegInst>(Val: &I)) {
605 if (PNI->hasNonNeg())
606 MIFlags |= MachineInstr::MIFlag::NonNeg;
607 // Copy the disjoint flag.
608 } else if (const PossiblyDisjointInst *PD =
609 dyn_cast<PossiblyDisjointInst>(Val: &I)) {
610 if (PD->isDisjoint())
611 MIFlags |= MachineInstr::MIFlag::Disjoint;
612 }
613
614 // Copy the samesign flag.
615 if (const ICmpInst *ICmp = dyn_cast<ICmpInst>(Val: &I))
616 if (ICmp->hasSameSign())
617 MIFlags |= MachineInstr::MIFlag::SameSign;
618
619 // Copy the exact flag.
620 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(Val: &I))
621 if (PE->isExact())
622 MIFlags |= MachineInstr::MIFlag::IsExact;
623
624 // Copy the fast-math flags.
625 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(Val: &I)) {
626 const FastMathFlags Flags = FP->getFastMathFlags();
627 if (Flags.noNaNs())
628 MIFlags |= MachineInstr::MIFlag::FmNoNans;
629 if (Flags.noInfs())
630 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
631 if (Flags.noSignedZeros())
632 MIFlags |= MachineInstr::MIFlag::FmNsz;
633 if (Flags.allowReciprocal())
634 MIFlags |= MachineInstr::MIFlag::FmArcp;
635 if (Flags.allowContract())
636 MIFlags |= MachineInstr::MIFlag::FmContract;
637 if (Flags.approxFunc())
638 MIFlags |= MachineInstr::MIFlag::FmAfn;
639 if (Flags.allowReassoc())
640 MIFlags |= MachineInstr::MIFlag::FmReassoc;
641 }
642
643 if (I.getMetadata(KindID: LLVMContext::MD_unpredictable))
644 MIFlags |= MachineInstr::MIFlag::Unpredictable;
645
646 return MIFlags;
647}
648
649void MachineInstr::copyIRFlags(const Instruction &I) {
650 Flags = copyFlagsFromInstruction(I);
651}
652
653bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
654 assert(!isBundledWithPred() && "Must be called on bundle header");
655 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
656 if (MII->getDesc().getFlags() & Mask) {
657 if (Type == AnyInBundle)
658 return true;
659 } else {
660 if (Type == AllInBundle && !MII->isBundle())
661 return false;
662 }
663 // This was the last instruction in the bundle.
664 if (!MII->isBundledWithSucc())
665 return Type == AllInBundle;
666 }
667}
668
669bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
670 MICheckType Check) const {
671 // If opcodes or number of operands are not the same then the two
672 // instructions are obviously not identical.
673 if (Other.getOpcode() != getOpcode() ||
674 Other.getNumOperands() != getNumOperands())
675 return false;
676
677 if (isBundle()) {
678 // We have passed the test above that both instructions have the same
679 // opcode, so we know that both instructions are bundles here. Let's compare
680 // MIs inside the bundle.
681 assert(Other.isBundle() && "Expected that both instructions are bundles.");
682 MachineBasicBlock::const_instr_iterator I1 = getIterator();
683 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
684 // Loop until we analysed the last intruction inside at least one of the
685 // bundles.
686 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
687 ++I1;
688 ++I2;
689 if (!I1->isIdenticalTo(Other: *I2, Check))
690 return false;
691 }
692 // If we've reached the end of just one of the two bundles, but not both,
693 // the instructions are not identical.
694 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
695 return false;
696 }
697
698 // Check operands to make sure they match.
699 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
700 const MachineOperand &MO = getOperand(i);
701 const MachineOperand &OMO = Other.getOperand(i);
702 if (!MO.isReg()) {
703 if (!MO.isIdenticalTo(Other: OMO))
704 return false;
705 continue;
706 }
707
708 // Clients may or may not want to ignore defs when testing for equality.
709 // For example, machine CSE pass only cares about finding common
710 // subexpressions, so it's safe to ignore virtual register defs.
711 if (MO.isDef()) {
712 if (Check == IgnoreDefs)
713 continue;
714 else if (Check == IgnoreVRegDefs) {
715 if (!MO.getReg().isVirtual() || !OMO.getReg().isVirtual())
716 if (!MO.isIdenticalTo(Other: OMO))
717 return false;
718 } else {
719 if (!MO.isIdenticalTo(Other: OMO))
720 return false;
721 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
722 return false;
723 }
724 } else {
725 if (!MO.isIdenticalTo(Other: OMO))
726 return false;
727 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
728 return false;
729 }
730 }
731 // If DebugLoc does not match then two debug instructions are not identical.
732 if (isDebugInstr())
733 if (getDebugLoc() && Other.getDebugLoc() &&
734 getDebugLoc() != Other.getDebugLoc())
735 return false;
736 // If pre- or post-instruction symbols do not match then the two instructions
737 // are not identical.
738 if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
739 getPostInstrSymbol() != Other.getPostInstrSymbol())
740 return false;
741 if (isCall()) {
742 // Call instructions with different CFI types are not identical.
743 if (getCFIType() != Other.getCFIType())
744 return false;
745 // Even if the call instructions have the same ops, they are not identical
746 // if they are for different globals (this may happen with indirect calls).
747 if (isCandidateForAdditionalCallInfo()) {
748 MachineFunction::CalledGlobalInfo ThisCGI =
749 getParent()->getParent()->tryGetCalledGlobal(MI: this);
750 MachineFunction::CalledGlobalInfo OtherCGI =
751 Other.getParent()->getParent()->tryGetCalledGlobal(MI: &Other);
752 if (ThisCGI.Callee != OtherCGI.Callee ||
753 ThisCGI.TargetFlags != OtherCGI.TargetFlags)
754 return false;
755 }
756 }
757 if (getDeactivationSymbol() != Other.getDeactivationSymbol())
758 return false;
759
760 return true;
761}
762
763bool MachineInstr::isEquivalentDbgInstr(const MachineInstr &Other) const {
764 if (!isDebugValueLike() || !Other.isDebugValueLike())
765 return false;
766 if (getDebugLoc() != Other.getDebugLoc())
767 return false;
768 if (getDebugVariable() != Other.getDebugVariable())
769 return false;
770 if (getNumDebugOperands() != Other.getNumDebugOperands())
771 return false;
772 for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx)
773 if (!getDebugOperand(Index: OpIdx).isIdenticalTo(Other: Other.getDebugOperand(Index: OpIdx)))
774 return false;
775 if (!DIExpression::isEqualExpression(
776 FirstExpr: getDebugExpression(), FirstIndirect: isIndirectDebugValue(),
777 SecondExpr: Other.getDebugExpression(), SecondIndirect: Other.isIndirectDebugValue()))
778 return false;
779 return true;
780}
781
782const MachineFunction *MachineInstr::getMF() const {
783 return getParent()->getParent();
784}
785
786MachineInstr *MachineInstr::removeFromParent() {
787 assert(getParent() && "Not embedded in a basic block!");
788 return getParent()->remove(I: this);
789}
790
791MachineInstr *MachineInstr::removeFromBundle() {
792 assert(getParent() && "Not embedded in a basic block!");
793 return getParent()->remove_instr(I: this);
794}
795
796MachineBasicBlock::iterator MachineInstr::eraseFromParent() {
797 assert(getParent() && "Not embedded in a basic block!");
798 return getParent()->erase(I: this);
799}
800
801void MachineInstr::eraseFromBundle() {
802 assert(getParent() && "Not embedded in a basic block!");
803 getParent()->erase_instr(I: this);
804}
805
806bool MachineInstr::isCandidateForAdditionalCallInfo(QueryType Type) const {
807 if (!isCall(Type))
808 return false;
809 switch (getOpcode()) {
810 case TargetOpcode::PATCHPOINT:
811 case TargetOpcode::STACKMAP:
812 case TargetOpcode::STATEPOINT:
813 case TargetOpcode::FENTRY_CALL:
814 return false;
815 }
816 return true;
817}
818
819bool MachineInstr::shouldUpdateAdditionalCallInfo() const {
820 if (isBundle())
821 return isCandidateForAdditionalCallInfo(Type: MachineInstr::AnyInBundle);
822 return isCandidateForAdditionalCallInfo();
823}
824
825template <typename Operand, typename Instruction>
826static iterator_range<
827 filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
828getDebugOperandsForRegHelper(Instruction *MI, Register Reg) {
829 std::function<bool(Operand & Op)> OpUsesReg(
830 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
831 return make_filter_range(MI->debug_operands(), OpUsesReg);
832}
833
834iterator_range<filter_iterator<const MachineOperand *,
835 std::function<bool(const MachineOperand &Op)>>>
836MachineInstr::getDebugOperandsForReg(Register Reg) const {
837 return getDebugOperandsForRegHelper<const MachineOperand, const MachineInstr>(
838 MI: this, Reg);
839}
840
841iterator_range<
842 filter_iterator<MachineOperand *, std::function<bool(MachineOperand &Op)>>>
843MachineInstr::getDebugOperandsForReg(Register Reg) {
844 return getDebugOperandsForRegHelper<MachineOperand, MachineInstr>(MI: this, Reg);
845}
846
847unsigned MachineInstr::getNumExplicitOperands() const {
848 unsigned NumOperands = MCID->getNumOperands();
849 if (!MCID->isVariadic())
850 return NumOperands;
851
852 for (const MachineOperand &MO : operands_impl().drop_front(N: NumOperands)) {
853 // The operands must always be in the following order:
854 // - explicit reg defs,
855 // - other explicit operands (reg uses, immediates, etc.),
856 // - implicit reg defs
857 // - implicit reg uses
858 if (MO.isReg() && MO.isImplicit())
859 break;
860 ++NumOperands;
861 }
862 return NumOperands;
863}
864
865unsigned MachineInstr::getNumExplicitDefs() const {
866 unsigned NumDefs = MCID->getNumDefs();
867 if (!MCID->isVariadic())
868 return NumDefs;
869
870 for (const MachineOperand &MO : operands_impl().drop_front(N: NumDefs)) {
871 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
872 break;
873 ++NumDefs;
874 }
875 return NumDefs;
876}
877
878void MachineInstr::bundleWithPred() {
879 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
880 setFlag(BundledPred);
881 MachineBasicBlock::instr_iterator Pred = getIterator();
882 --Pred;
883 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
884 Pred->setFlag(BundledSucc);
885}
886
887void MachineInstr::bundleWithSucc() {
888 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
889 setFlag(BundledSucc);
890 MachineBasicBlock::instr_iterator Succ = getIterator();
891 ++Succ;
892 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
893 Succ->setFlag(BundledPred);
894}
895
896void MachineInstr::unbundleFromPred() {
897 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
898 clearFlag(Flag: BundledPred);
899 MachineBasicBlock::instr_iterator Pred = getIterator();
900 --Pred;
901 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
902 Pred->clearFlag(Flag: BundledSucc);
903}
904
905void MachineInstr::unbundleFromSucc() {
906 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
907 clearFlag(Flag: BundledSucc);
908 MachineBasicBlock::instr_iterator Succ = getIterator();
909 ++Succ;
910 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
911 Succ->clearFlag(Flag: BundledPred);
912}
913
914bool MachineInstr::isStackAligningInlineAsm() const {
915 if (isInlineAsm()) {
916 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
917 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
918 return true;
919 }
920 return false;
921}
922
923InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
924 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
925 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
926 return InlineAsm::getDialect(ExtraInfo);
927}
928
929int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
930 unsigned *GroupNo) const {
931 assert(isInlineAsm() && "Expected an inline asm instruction");
932 assert(OpIdx < getNumOperands() && "OpIdx out of range");
933
934 // Ignore queries about the initial operands.
935 if (OpIdx < InlineAsm::MIOp_FirstOperand)
936 return -1;
937
938 unsigned Group = 0;
939 unsigned NumOps;
940 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
941 i += NumOps) {
942 const MachineOperand &FlagMO = getOperand(i);
943 // If we reach the implicit register operands, stop looking.
944 if (!FlagMO.isImm())
945 return -1;
946 const InlineAsm::Flag F(FlagMO.getImm());
947 NumOps = 1 + F.getNumOperandRegisters();
948 if (i + NumOps > OpIdx) {
949 if (GroupNo)
950 *GroupNo = Group;
951 return i;
952 }
953 ++Group;
954 }
955 return -1;
956}
957
958const DILabel *MachineInstr::getDebugLabel() const {
959 assert(isDebugLabel() && "not a DBG_LABEL");
960 return cast<DILabel>(Val: getOperand(i: 0).getMetadata());
961}
962
963const MachineOperand &MachineInstr::getDebugVariableOp() const {
964 assert((isDebugValueLike()) && "not a DBG_VALUE*");
965 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
966 return getOperand(i: VariableOp);
967}
968
969MachineOperand &MachineInstr::getDebugVariableOp() {
970 assert((isDebugValueLike()) && "not a DBG_VALUE*");
971 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
972 return getOperand(i: VariableOp);
973}
974
975const DILocalVariable *MachineInstr::getDebugVariable() const {
976 return cast<DILocalVariable>(Val: getDebugVariableOp().getMetadata());
977}
978
979const MachineOperand &MachineInstr::getDebugExpressionOp() const {
980 assert((isDebugValueLike()) && "not a DBG_VALUE*");
981 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
982 return getOperand(i: ExpressionOp);
983}
984
985MachineOperand &MachineInstr::getDebugExpressionOp() {
986 assert((isDebugValueLike()) && "not a DBG_VALUE*");
987 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
988 return getOperand(i: ExpressionOp);
989}
990
991const DIExpression *MachineInstr::getDebugExpression() const {
992 return cast<DIExpression>(Val: getDebugExpressionOp().getMetadata());
993}
994
995bool MachineInstr::isDebugEntryValue() const {
996 return isDebugValue() && getDebugExpression()->isEntryValue();
997}
998
999const TargetRegisterClass*
1000MachineInstr::getRegClassConstraint(unsigned OpIdx,
1001 const TargetInstrInfo *TII,
1002 const TargetRegisterInfo *TRI) const {
1003 assert(getParent() && "Can't have an MBB reference here!");
1004 assert(getMF() && "Can't have an MF reference here!");
1005 // Most opcodes have fixed constraints in their MCInstrDesc.
1006 if (!isInlineAsm())
1007 return TII->getRegClass(MCID: getDesc(), OpNum: OpIdx);
1008
1009 if (!getOperand(i: OpIdx).isReg())
1010 return nullptr;
1011
1012 // For tied uses on inline asm, get the constraint from the def.
1013 unsigned DefIdx;
1014 if (getOperand(i: OpIdx).isUse() && isRegTiedToDefOperand(UseOpIdx: OpIdx, DefOpIdx: &DefIdx))
1015 OpIdx = DefIdx;
1016
1017 // Inline asm stores register class constraints in the flag word.
1018 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1019 if (FlagIdx < 0)
1020 return nullptr;
1021
1022 const InlineAsm::Flag F(getOperand(i: FlagIdx).getImm());
1023 unsigned RCID;
1024 if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) &&
1025 F.hasRegClassConstraint(RC&: RCID))
1026 return TRI->getRegClass(i: RCID);
1027
1028 // Assume that all registers in a memory operand are pointers.
1029 if (F.isMemKind())
1030 return TRI->getPointerRegClass();
1031
1032 return nullptr;
1033}
1034
1035const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
1036 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
1037 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
1038 // Check every operands inside the bundle if we have
1039 // been asked to.
1040 if (ExploreBundle)
1041 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
1042 ++OpndIt)
1043 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1044 OpIdx: OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
1045 else
1046 // Otherwise, just check the current operands.
1047 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1048 CurRC = getRegClassConstraintEffectForVRegImpl(OpIdx: i, Reg, CurRC, TII, TRI);
1049 return CurRC;
1050}
1051
1052const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1053 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1054 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1055 assert(CurRC && "Invalid initial register class");
1056 // Check if Reg is constrained by some of its use/def from MI.
1057 const MachineOperand &MO = getOperand(i: OpIdx);
1058 if (!MO.isReg() || MO.getReg() != Reg)
1059 return CurRC;
1060 // If yes, accumulate the constraints through the operand.
1061 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1062}
1063
1064const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
1065 unsigned OpIdx, const TargetRegisterClass *CurRC,
1066 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1067 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1068 const MachineOperand &MO = getOperand(i: OpIdx);
1069 assert(MO.isReg() &&
1070 "Cannot get register constraints for non-register operand");
1071 assert(CurRC && "Invalid initial register class");
1072 if (unsigned SubIdx = MO.getSubReg()) {
1073 if (OpRC)
1074 CurRC = TRI->getMatchingSuperRegClass(A: CurRC, B: OpRC, Idx: SubIdx);
1075 else
1076 CurRC = TRI->getSubClassWithSubReg(RC: CurRC, Idx: SubIdx);
1077 } else if (OpRC)
1078 CurRC = TRI->getCommonSubClass(A: CurRC, B: OpRC);
1079 return CurRC;
1080}
1081
1082/// Return the number of instructions inside the MI bundle, not counting the
1083/// header instruction.
1084unsigned MachineInstr::getBundleSize() const {
1085 MachineBasicBlock::const_instr_iterator I = getIterator();
1086 unsigned Size = 0;
1087 while (I->isBundledWithSucc()) {
1088 ++Size;
1089 ++I;
1090 }
1091 return Size;
1092}
1093
1094/// Returns true if the MachineInstr has an implicit-use operand of exactly
1095/// the given register (not considering sub/super-registers).
1096bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
1097 for (const MachineOperand &MO : implicit_operands()) {
1098 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
1099 return true;
1100 }
1101 return false;
1102}
1103
1104/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1105/// the specific register or -1 if it is not found. It further tightens
1106/// the search criteria to a use that kills the register if isKill is true.
1107int MachineInstr::findRegisterUseOperandIdx(Register Reg,
1108 const TargetRegisterInfo *TRI,
1109 bool isKill) const {
1110 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1111 const MachineOperand &MO = getOperand(i);
1112 if (!MO.isReg() || !MO.isUse())
1113 continue;
1114 Register MOReg = MO.getReg();
1115 if (!MOReg)
1116 continue;
1117 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(RegA: MOReg, RegB: Reg)))
1118 if (!isKill || MO.isKill())
1119 return i;
1120 }
1121 return -1;
1122}
1123
1124/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1125/// indicating if this instruction reads or writes Reg. This also considers
1126/// partial defines.
1127std::pair<bool,bool>
1128MachineInstr::readsWritesVirtualRegister(Register Reg,
1129 SmallVectorImpl<unsigned> *Ops) const {
1130 bool PartDef = false; // Partial redefine.
1131 bool FullDef = false; // Full define.
1132 bool Use = false;
1133
1134 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1135 const MachineOperand &MO = getOperand(i);
1136 if (!MO.isReg() || MO.getReg() != Reg)
1137 continue;
1138 if (Ops)
1139 Ops->push_back(Elt: i);
1140 if (MO.isUse())
1141 Use |= !MO.isUndef();
1142 else if (MO.getSubReg() && !MO.isUndef())
1143 // A partial def undef doesn't count as reading the register.
1144 PartDef = true;
1145 else
1146 FullDef = true;
1147 }
1148 // A partial redefine uses Reg unless there is also a full define.
1149 return std::make_pair(x: Use || (PartDef && !FullDef), y: PartDef || FullDef);
1150}
1151
1152/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1153/// the specified register or -1 if it is not found. If isDead is true, defs
1154/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1155/// also checks if there is a def of a super-register.
1156int MachineInstr::findRegisterDefOperandIdx(Register Reg,
1157 const TargetRegisterInfo *TRI,
1158 bool isDead, bool Overlap) const {
1159 bool isPhys = Reg.isPhysical();
1160 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1161 const MachineOperand &MO = getOperand(i);
1162 // Accept regmask operands when Overlap is set.
1163 // Ignore them when looking for a specific def operand (Overlap == false).
1164 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(PhysReg: Reg))
1165 return i;
1166 if (!MO.isReg() || !MO.isDef())
1167 continue;
1168 Register MOReg = MO.getReg();
1169 bool Found = (MOReg == Reg);
1170 if (!Found && TRI && isPhys && MOReg.isPhysical()) {
1171 if (Overlap)
1172 Found = TRI->regsOverlap(RegA: MOReg, RegB: Reg);
1173 else
1174 Found = TRI->isSubRegister(RegA: MOReg, RegB: Reg);
1175 }
1176 if (Found && (!isDead || MO.isDead()))
1177 return i;
1178 }
1179 return -1;
1180}
1181
1182/// findFirstPredOperandIdx() - Find the index of the first operand in the
1183/// operand list that is used to represent the predicate. It returns -1 if
1184/// none is found.
1185int MachineInstr::findFirstPredOperandIdx() const {
1186 // Don't call MCID.findFirstPredOperandIdx() because this variant
1187 // is sometimes called on an instruction that's not yet complete, and
1188 // so the number of operands is less than the MCID indicates. In
1189 // particular, the PTX target does this.
1190 const MCInstrDesc &MCID = getDesc();
1191 if (MCID.isPredicable()) {
1192 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1193 if (MCID.operands()[i].isPredicate())
1194 return i;
1195 }
1196
1197 return -1;
1198}
1199
1200// MachineOperand::TiedTo is 4 bits wide.
1201const unsigned TiedMax = 15;
1202
1203/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1204///
1205/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1206/// field. TiedTo can have these values:
1207///
1208/// 0: Operand is not tied to anything.
1209/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1210/// TiedMax: Tied to an operand >= TiedMax-1.
1211///
1212/// The tied def must be one of the first TiedMax operands on a normal
1213/// instruction. INLINEASM instructions allow more tied defs.
1214///
1215void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1216 MachineOperand &DefMO = getOperand(i: DefIdx);
1217 MachineOperand &UseMO = getOperand(i: UseIdx);
1218 assert(DefMO.isDef() && "DefIdx must be a def operand");
1219 assert(UseMO.isUse() && "UseIdx must be a use operand");
1220 assert(!DefMO.isTied() && "Def is already tied to another use");
1221 assert(!UseMO.isTied() && "Use is already tied to another def");
1222
1223 if (DefIdx < TiedMax) {
1224 UseMO.TiedTo = DefIdx + 1;
1225 } else {
1226 // Inline asm can use the group descriptors to find tied operands,
1227 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1228 // but on normal instruction, the tied def must be within the first TiedMax
1229 // operands.
1230 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1231 "DefIdx out of range");
1232 UseMO.TiedTo = TiedMax;
1233 }
1234
1235 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1236 DefMO.TiedTo = std::min(a: UseIdx + 1, b: TiedMax);
1237}
1238
1239/// Given the index of a tied register operand, find the operand it is tied to.
1240/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1241/// which must exist.
1242unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1243 const MachineOperand &MO = getOperand(i: OpIdx);
1244 assert(MO.isTied() && "Operand isn't tied");
1245
1246 // Normally TiedTo is in range.
1247 if (MO.TiedTo < TiedMax)
1248 return MO.TiedTo - 1;
1249
1250 // Uses on normal instructions can be out of range.
1251 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1252 // Normal tied defs must be in the 0..TiedMax-1 range.
1253 if (MO.isUse())
1254 return TiedMax - 1;
1255 // MO is a def. Search for the tied use.
1256 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1257 const MachineOperand &UseMO = getOperand(i);
1258 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1259 return i;
1260 }
1261 llvm_unreachable("Can't find tied use");
1262 }
1263
1264 if (getOpcode() == TargetOpcode::STATEPOINT) {
1265 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1266 // on registers.
1267 StatepointOpers SO(this);
1268 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1269 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1270 unsigned NumDefs = getNumDefs();
1271 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1272 while (!getOperand(i: CurUseIdx).isReg())
1273 CurUseIdx = StackMaps::getNextMetaArgIdx(MI: this, CurIdx: CurUseIdx);
1274 if (OpIdx == CurDefIdx)
1275 return CurUseIdx;
1276 if (OpIdx == CurUseIdx)
1277 return CurDefIdx;
1278 CurUseIdx = StackMaps::getNextMetaArgIdx(MI: this, CurIdx: CurUseIdx);
1279 }
1280 llvm_unreachable("Can't find tied use");
1281 }
1282
1283 // Now deal with inline asm by parsing the operand group descriptor flags.
1284 // Find the beginning of each operand group.
1285 SmallVector<unsigned, 8> GroupIdx;
1286 unsigned OpIdxGroup = ~0u;
1287 unsigned NumOps;
1288 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1289 i += NumOps) {
1290 const MachineOperand &FlagMO = getOperand(i);
1291 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1292 unsigned CurGroup = GroupIdx.size();
1293 GroupIdx.push_back(Elt: i);
1294 const InlineAsm::Flag F(FlagMO.getImm());
1295 NumOps = 1 + F.getNumOperandRegisters();
1296 // OpIdx belongs to this operand group.
1297 if (OpIdx > i && OpIdx < i + NumOps)
1298 OpIdxGroup = CurGroup;
1299 unsigned TiedGroup;
1300 if (!F.isUseOperandTiedToDef(Idx&: TiedGroup))
1301 continue;
1302 // Operands in this group are tied to operands in TiedGroup which must be
1303 // earlier. Find the number of operands between the two groups.
1304 unsigned Delta = i - GroupIdx[TiedGroup];
1305
1306 // OpIdx is a use tied to TiedGroup.
1307 if (OpIdxGroup == CurGroup)
1308 return OpIdx - Delta;
1309
1310 // OpIdx is a def tied to this use group.
1311 if (OpIdxGroup == TiedGroup)
1312 return OpIdx + Delta;
1313 }
1314 llvm_unreachable("Invalid tied operand on inline asm");
1315}
1316
1317/// clearKillInfo - Clears kill flags on all operands.
1318///
1319void MachineInstr::clearKillInfo() {
1320 for (MachineOperand &MO : operands()) {
1321 if (MO.isReg() && MO.isUse())
1322 MO.setIsKill(false);
1323 }
1324}
1325
1326void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1327 unsigned SubIdx,
1328 const TargetRegisterInfo &RegInfo) {
1329 if (ToReg.isPhysical()) {
1330 if (SubIdx)
1331 ToReg = RegInfo.getSubReg(Reg: ToReg, Idx: SubIdx);
1332 for (MachineOperand &MO : operands()) {
1333 if (!MO.isReg() || MO.getReg() != FromReg)
1334 continue;
1335 MO.substPhysReg(Reg: ToReg, RegInfo);
1336 }
1337 } else {
1338 for (MachineOperand &MO : operands()) {
1339 if (!MO.isReg() || MO.getReg() != FromReg)
1340 continue;
1341 MO.substVirtReg(Reg: ToReg, SubIdx, RegInfo);
1342 }
1343 }
1344}
1345
1346/// isSafeToMove - Return true if it is safe to move this instruction. If
1347/// SawStore is set to true, it means that there is a store (or call) between
1348/// the instruction's location and its intended destination.
1349bool MachineInstr::isSafeToMove(bool &SawStore) const {
1350 // Ignore stuff that we obviously can't move.
1351 //
1352 // Treat volatile loads as stores. This is not strictly necessary for
1353 // volatiles, but it is required for atomic loads. It is not allowed to move
1354 // a load across an atomic load with Ordering > Monotonic.
1355 if (mayStore() || isCall() || isPHI() || hasOrderedMemoryRef()) {
1356 SawStore = true;
1357 return false;
1358 }
1359
1360 // Don't touch instructions that have non-trivial invariants. For example,
1361 // terminators have to be at the end of a basic block.
1362 if (isPosition() || isDebugInstr() || isTerminator() ||
1363 isJumpTableDebugInfo())
1364 return false;
1365
1366 // Don't touch instructions which can have non-load/store effects.
1367 //
1368 // Inline asm has a "sideeffect" marker to indicate whether the asm has
1369 // intentional side-effects. Even if an inline asm is not "sideeffect",
1370 // though, it still can't be speculatively executed: the operation might
1371 // not be valid on the current target, or for some combinations of operands.
1372 // (Some transforms that move an instruction don't speculatively execute it;
1373 // we currently don't try to handle that distinction here.)
1374 //
1375 // Other instructions handled here include those that can raise FP
1376 // exceptions, x86 "DIV" instructions which trap on divide by zero, and
1377 // stack adjustments.
1378 if (mayRaiseFPException() || hasProperty(MCFlag: MCID::UnmodeledSideEffects) ||
1379 isInlineAsm())
1380 return false;
1381
1382 // See if this instruction does a load. If so, we have to guarantee that the
1383 // loaded value doesn't change between the load and the its intended
1384 // destination. The check for isInvariantLoad gives the target the chance to
1385 // classify the load as always returning a constant, e.g. a constant pool
1386 // load.
1387 if (mayLoad() && !isDereferenceableInvariantLoad())
1388 // Otherwise, this is a real load. If there is a store between the load and
1389 // end of block, we can't move it.
1390 return !SawStore;
1391
1392 return true;
1393}
1394
1395bool MachineInstr::wouldBeTriviallyDead() const {
1396 // Don't delete frame allocation labels.
1397 // FIXME: Why is LOCAL_ESCAPE not considered in MachineInstr::isLabel?
1398 if (getOpcode() == TargetOpcode::LOCAL_ESCAPE)
1399 return false;
1400
1401 // Don't delete FAKE_USE.
1402 // FIXME: Why is FAKE_USE not considered in MachineInstr::isPosition?
1403 if (isFakeUse())
1404 return false;
1405
1406 // LIFETIME markers should be preserved.
1407 // FIXME: Why are LIFETIME markers not considered in MachineInstr::isPosition?
1408 if (isLifetimeMarker())
1409 return false;
1410
1411 // If we can move an instruction, we can remove it. Otherwise, it has
1412 // a side-effect of some sort.
1413 bool SawStore = false;
1414 return isPHI() || isSafeToMove(SawStore);
1415}
1416
1417bool MachineInstr::isDead(const MachineRegisterInfo &MRI,
1418 LiveRegUnits *LivePhysRegs) const {
1419 // Instructions without side-effects are dead iff they only define dead regs.
1420 // This function is hot and this loop returns early in the common case,
1421 // so only perform additional checks before this if absolutely necessary.
1422 for (const MachineOperand &MO : all_defs()) {
1423 Register Reg = MO.getReg();
1424 if (Reg.isPhysical()) {
1425 // Don't delete live physreg defs, or any reserved register defs.
1426 if (!LivePhysRegs || !LivePhysRegs->available(Reg) || MRI.isReserved(PhysReg: Reg))
1427 return false;
1428 } else {
1429 if (MO.isDead())
1430 continue;
1431 for (const MachineInstr &Use : MRI.use_nodbg_instructions(Reg)) {
1432 if (&Use != this)
1433 // This def has a non-debug use. Don't delete the instruction!
1434 return false;
1435 }
1436 }
1437 }
1438
1439 // Technically speaking inline asm without side effects and no defs can still
1440 // be deleted. But there is so much bad inline asm code out there, we should
1441 // let them be.
1442 if (isInlineAsm())
1443 return false;
1444
1445 // FIXME: See issue #105950 for why LIFETIME markers are considered dead here.
1446 if (isLifetimeMarker())
1447 return true;
1448
1449 // If there are no defs with uses, then we call the instruction dead so long
1450 // as we do not suspect it may have sideeffects.
1451 return wouldBeTriviallyDead();
1452}
1453
1454static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI,
1455 BatchAAResults *AA, bool UseTBAA,
1456 const MachineMemOperand *MMOa,
1457 const MachineMemOperand *MMOb) {
1458 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1459 // operates with MachineMemOperand offset with some important assumptions:
1460 // - LLVM fundamentally assumes flat address spaces.
1461 // - MachineOperand offset can *only* result from legalization and cannot
1462 // affect queries other than the trivial case of overlap checking.
1463 // - These offsets never wrap and never step outside of allocated objects.
1464 // - There should never be any negative offsets here.
1465 //
1466 // FIXME: Modify API to hide this math from "user"
1467 // Even before we go to AA we can reason locally about some memory objects. It
1468 // can save compile time, and possibly catch some corner cases not currently
1469 // covered.
1470
1471 int64_t OffsetA = MMOa->getOffset();
1472 int64_t OffsetB = MMOb->getOffset();
1473 int64_t MinOffset = std::min(a: OffsetA, b: OffsetB);
1474
1475 LocationSize WidthA = MMOa->getSize();
1476 LocationSize WidthB = MMOb->getSize();
1477 bool KnownWidthA = WidthA.hasValue();
1478 bool KnownWidthB = WidthB.hasValue();
1479 bool BothMMONonScalable = !WidthA.isScalable() && !WidthB.isScalable();
1480
1481 const Value *ValA = MMOa->getValue();
1482 const Value *ValB = MMOb->getValue();
1483 bool SameVal = (ValA && ValB && (ValA == ValB));
1484 if (!SameVal) {
1485 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1486 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1487 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1488 return false;
1489 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1490 return false;
1491 if (PSVa && PSVb && (PSVa == PSVb))
1492 SameVal = true;
1493 }
1494
1495 if (SameVal && BothMMONonScalable) {
1496 if (!KnownWidthA || !KnownWidthB)
1497 return true;
1498 int64_t MaxOffset = std::max(a: OffsetA, b: OffsetB);
1499 int64_t LowWidth = (MinOffset == OffsetA)
1500 ? WidthA.getValue().getKnownMinValue()
1501 : WidthB.getValue().getKnownMinValue();
1502 return (MinOffset + LowWidth > MaxOffset);
1503 }
1504
1505 if (!AA)
1506 return true;
1507
1508 if (!ValA || !ValB)
1509 return true;
1510
1511 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1512 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1513
1514 // If Scalable Location Size has non-zero offset, Width + Offset does not work
1515 // at the moment
1516 if ((WidthA.isScalable() && OffsetA > 0) ||
1517 (WidthB.isScalable() && OffsetB > 0))
1518 return true;
1519
1520 int64_t OverlapA =
1521 KnownWidthA ? WidthA.getValue().getKnownMinValue() + OffsetA - MinOffset
1522 : MemoryLocation::UnknownSize;
1523 int64_t OverlapB =
1524 KnownWidthB ? WidthB.getValue().getKnownMinValue() + OffsetB - MinOffset
1525 : MemoryLocation::UnknownSize;
1526
1527 LocationSize LocA = (WidthA.isScalable() || !KnownWidthA)
1528 ? WidthA
1529 : LocationSize::precise(Value: OverlapA);
1530 LocationSize LocB = (WidthB.isScalable() || !KnownWidthB)
1531 ? WidthB
1532 : LocationSize::precise(Value: OverlapB);
1533
1534 return !AA->isNoAlias(
1535 LocA: MemoryLocation(ValA, LocA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1536 LocB: MemoryLocation(ValB, LocB, UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1537}
1538
1539bool MachineInstr::mayAlias(BatchAAResults *AA, const MachineInstr &Other,
1540 bool UseTBAA) const {
1541 const MachineFunction *MF = getMF();
1542 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1543 const MachineFrameInfo &MFI = MF->getFrameInfo();
1544
1545 // Exclude call instruction which may alter the memory but can not be handled
1546 // by this function.
1547 if (isCall() || Other.isCall())
1548 return true;
1549
1550 // If neither instruction stores to memory, they can't alias in any
1551 // meaningful way, even if they read from the same address.
1552 if (!mayStore() && !Other.mayStore())
1553 return false;
1554
1555 // Both instructions must be memory operations to be able to alias.
1556 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1557 return false;
1558
1559 // Let the target decide if memory accesses cannot possibly overlap.
1560 if (TII->areMemAccessesTriviallyDisjoint(MIa: *this, MIb: Other))
1561 return false;
1562
1563 // Memory operations without memory operands may access anything. Be
1564 // conservative and assume `MayAlias`.
1565 if (memoperands_empty() || Other.memoperands_empty())
1566 return true;
1567
1568 // Skip if there are too many memory operands.
1569 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1570 if (NumChecks > TII->getMemOperandAACheckLimit())
1571 return true;
1572
1573 // Check each pair of memory operands from both instructions, which can't
1574 // alias only if all pairs won't alias.
1575 for (auto *MMOa : memoperands()) {
1576 for (auto *MMOb : Other.memoperands()) {
1577 if (!MMOa->isStore() && !MMOb->isStore())
1578 continue;
1579 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1580 return true;
1581 }
1582 }
1583
1584 return false;
1585}
1586
1587bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1588 bool UseTBAA) const {
1589 if (AA) {
1590 BatchAAResults BAA(*AA);
1591 return mayAlias(AA: &BAA, Other, UseTBAA);
1592 }
1593 return mayAlias(AA: static_cast<BatchAAResults *>(nullptr), Other, UseTBAA);
1594}
1595
1596/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1597/// or volatile memory reference, or if the information describing the memory
1598/// reference is not available. Return false if it is known to have no ordered
1599/// memory references.
1600bool MachineInstr::hasOrderedMemoryRef() const {
1601 // An instruction known never to access memory won't have a volatile access.
1602 if (!mayStore() &&
1603 !mayLoad() &&
1604 !isCall() &&
1605 !hasUnmodeledSideEffects())
1606 return false;
1607
1608 // Otherwise, if the instruction has no memory reference information,
1609 // conservatively assume it wasn't preserved.
1610 if (memoperands_empty())
1611 return true;
1612
1613 // Check if any of our memory operands are ordered.
1614 return llvm::any_of(Range: memoperands(), P: [](const MachineMemOperand *MMO) {
1615 return !MMO->isUnordered();
1616 });
1617}
1618
1619/// isDereferenceableInvariantLoad - Return true if this instruction will never
1620/// trap and is loading from a location whose value is invariant across a run of
1621/// this function.
1622bool MachineInstr::isDereferenceableInvariantLoad() const {
1623 // If the instruction doesn't load at all, it isn't an invariant load.
1624 if (!mayLoad())
1625 return false;
1626
1627 // If the instruction has lost its memoperands, conservatively assume that
1628 // it may not be an invariant load.
1629 if (memoperands_empty())
1630 return false;
1631
1632 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1633
1634 for (MachineMemOperand *MMO : memoperands()) {
1635 if (!MMO->isUnordered())
1636 // If the memory operand has ordering side effects, we can't move the
1637 // instruction. Such an instruction is technically an invariant load,
1638 // but the caller code would need updated to expect that.
1639 return false;
1640 if (MMO->isStore()) return false;
1641 if (MMO->isInvariant() && MMO->isDereferenceable())
1642 continue;
1643
1644 // A load from a constant PseudoSourceValue is invariant.
1645 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
1646 if (PSV->isConstant(&MFI))
1647 continue;
1648 }
1649
1650 // Otherwise assume conservatively.
1651 return false;
1652 }
1653
1654 // Everything checks out.
1655 return true;
1656}
1657
1658Register MachineInstr::isConstantValuePHI() const {
1659 if (!isPHI())
1660 return {};
1661 assert(getNumOperands() >= 3 &&
1662 "It's illegal to have a PHI without source operands");
1663
1664 Register Reg = getOperand(i: 1).getReg();
1665 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1666 if (getOperand(i).getReg() != Reg)
1667 return {};
1668 return Reg;
1669}
1670
1671bool MachineInstr::hasUnmodeledSideEffects() const {
1672 if (hasProperty(MCFlag: MCID::UnmodeledSideEffects))
1673 return true;
1674 if (isInlineAsm()) {
1675 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1676 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1677 return true;
1678 }
1679
1680 return false;
1681}
1682
1683bool MachineInstr::isLoadFoldBarrier() const {
1684 return mayStore() || isCall() ||
1685 (hasUnmodeledSideEffects() && !isPseudoProbe());
1686}
1687
1688/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1689///
1690bool MachineInstr::allDefsAreDead() const {
1691 for (const MachineOperand &MO : operands()) {
1692 if (!MO.isReg() || MO.isUse())
1693 continue;
1694 if (!MO.isDead())
1695 return false;
1696 }
1697 return true;
1698}
1699
1700bool MachineInstr::allImplicitDefsAreDead() const {
1701 for (const MachineOperand &MO : implicit_operands()) {
1702 if (!MO.isReg() || MO.isUse())
1703 continue;
1704 if (!MO.isDead())
1705 return false;
1706 }
1707 return true;
1708}
1709
1710/// copyImplicitOps - Copy implicit register operands from specified
1711/// instruction to this instruction.
1712void MachineInstr::copyImplicitOps(MachineFunction &MF,
1713 const MachineInstr &MI) {
1714 for (const MachineOperand &MO :
1715 llvm::drop_begin(RangeOrContainer: MI.operands(), N: MI.getDesc().getNumOperands()))
1716 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1717 addOperand(MF, Op: MO);
1718}
1719
1720bool MachineInstr::hasComplexRegisterTies() const {
1721 const MCInstrDesc &MCID = getDesc();
1722 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1723 return true;
1724 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1725 const auto &Operand = getOperand(i: I);
1726 if (!Operand.isReg() || Operand.isDef())
1727 // Ignore the defined registers as MCID marks only the uses as tied.
1728 continue;
1729 int ExpectedTiedIdx = MCID.getOperandConstraint(OpNum: I, Constraint: MCOI::TIED_TO);
1730 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(OpIdx: I)) : -1;
1731 if (ExpectedTiedIdx != TiedIdx)
1732 return true;
1733 }
1734 return false;
1735}
1736
1737LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1738 const MachineRegisterInfo &MRI) const {
1739 const MachineOperand &Op = getOperand(i: OpIdx);
1740 if (!Op.isReg())
1741 return LLT{};
1742
1743 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1744 return MRI.getType(Reg: Op.getReg());
1745
1746 auto &OpInfo = getDesc().operands()[OpIdx];
1747 if (!OpInfo.isGenericType())
1748 return MRI.getType(Reg: Op.getReg());
1749
1750 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1751 return LLT{};
1752
1753 LLT TypeToPrint = MRI.getType(Reg: Op.getReg());
1754 // Don't mark the type index printed if it wasn't actually printed: maybe
1755 // another operand with the same type index has an actual type attached:
1756 if (TypeToPrint.isValid())
1757 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1758 return TypeToPrint;
1759}
1760
1761#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1762LLVM_DUMP_METHOD void MachineInstr::dump() const {
1763 dbgs() << " ";
1764 print(dbgs());
1765}
1766
1767LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1768 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1769 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1770 if (Depth >= MaxDepth)
1771 return;
1772 if (!AlreadySeenInstrs.insert(this).second)
1773 return;
1774 // PadToColumn always inserts at least one space.
1775 // Don't mess up the alignment if we don't want any space.
1776 if (Depth)
1777 fdbgs().PadToColumn(Depth * 2);
1778 print(fdbgs());
1779 for (const MachineOperand &MO : operands()) {
1780 if (!MO.isReg() || MO.isDef())
1781 continue;
1782 Register Reg = MO.getReg();
1783 if (Reg.isPhysical())
1784 continue;
1785 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1786 if (NewMI == nullptr)
1787 continue;
1788 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1789 }
1790}
1791
1792LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1793 unsigned MaxDepth) const {
1794 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1795 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1796}
1797#endif
1798
1799void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1800 bool SkipDebugLoc, bool AddNewLine,
1801 const TargetInstrInfo *TII) const {
1802 const Module *M = nullptr;
1803 const Function *F = nullptr;
1804 if (const MachineFunction *MF = getMFIfAvailable(MI: *this)) {
1805 F = &MF->getFunction();
1806 M = F->getParent();
1807 if (!TII)
1808 TII = MF->getSubtarget().getInstrInfo();
1809 }
1810
1811 ModuleSlotTracker MST(M);
1812 if (F)
1813 MST.incorporateFunction(F: *F);
1814 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1815}
1816
1817void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1818 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1819 bool AddNewLine, const TargetInstrInfo *TII) const {
1820 // We can be a bit tidier if we know the MachineFunction.
1821 const TargetRegisterInfo *TRI = nullptr;
1822 const MachineRegisterInfo *MRI = nullptr;
1823 tryToGetTargetInfo(MI: *this, TRI, MRI, TII);
1824
1825 if (isCFIInstruction())
1826 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1827
1828 SmallBitVector PrintedTypes(8);
1829 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1830 auto GetTiedOperandIdx = [&](unsigned OpIdx) {
1831 if (!ShouldPrintRegisterTies)
1832 return 0U;
1833 const MachineOperand &MO = getOperand(i: OpIdx);
1834 if (MO.isReg() && MO.isTied() && !MO.isDef())
1835 return findTiedOperandIdx(OpIdx);
1836 return 0U;
1837 };
1838 unsigned StartOp = 0;
1839 unsigned e = getNumOperands();
1840
1841 // Print explicitly defined operands on the left of an assignment syntax.
1842 while (StartOp < e) {
1843 const MachineOperand &MO = getOperand(i: StartOp);
1844 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1845 break;
1846
1847 if (StartOp != 0)
1848 OS << ", ";
1849
1850 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: StartOp, PrintedTypes, MRI: *MRI) : LLT{};
1851 // tied operands are not printed for defs.
1852 MO.print(os&: OS, MST, TypeToPrint, OpIdx: StartOp, /*PrintDef=*/false, IsStandalone,
1853 /*ShouldPrintRegisterTies=*/false, /*TiedOperandIdx=*/0, TRI);
1854 ++StartOp;
1855 }
1856
1857 if (StartOp != 0)
1858 OS << " = ";
1859
1860 if (getFlag(Flag: MachineInstr::FrameSetup))
1861 OS << "frame-setup ";
1862 if (getFlag(Flag: MachineInstr::FrameDestroy))
1863 OS << "frame-destroy ";
1864 if (getFlag(Flag: MachineInstr::FmNoNans))
1865 OS << "nnan ";
1866 if (getFlag(Flag: MachineInstr::FmNoInfs))
1867 OS << "ninf ";
1868 if (getFlag(Flag: MachineInstr::FmNsz))
1869 OS << "nsz ";
1870 if (getFlag(Flag: MachineInstr::FmArcp))
1871 OS << "arcp ";
1872 if (getFlag(Flag: MachineInstr::FmContract))
1873 OS << "contract ";
1874 if (getFlag(Flag: MachineInstr::FmAfn))
1875 OS << "afn ";
1876 if (getFlag(Flag: MachineInstr::FmReassoc))
1877 OS << "reassoc ";
1878 if (getFlag(Flag: MachineInstr::NoUWrap))
1879 OS << "nuw ";
1880 if (getFlag(Flag: MachineInstr::NoSWrap))
1881 OS << "nsw ";
1882 if (getFlag(Flag: MachineInstr::IsExact))
1883 OS << "exact ";
1884 if (getFlag(Flag: MachineInstr::NoFPExcept))
1885 OS << "nofpexcept ";
1886 if (getFlag(Flag: MachineInstr::NoMerge))
1887 OS << "nomerge ";
1888 if (getFlag(Flag: MachineInstr::NoConvergent))
1889 OS << "noconvergent ";
1890 if (getFlag(Flag: MachineInstr::NonNeg))
1891 OS << "nneg ";
1892 if (getFlag(Flag: MachineInstr::Disjoint))
1893 OS << "disjoint ";
1894 if (getFlag(Flag: MachineInstr::NoUSWrap))
1895 OS << "nusw ";
1896 if (getFlag(Flag: MachineInstr::SameSign))
1897 OS << "samesign ";
1898 if (getFlag(Flag: MachineInstr::InBounds))
1899 OS << "inbounds ";
1900
1901 // Print the opcode name.
1902 if (TII)
1903 OS << TII->getName(Opcode: getOpcode());
1904 else
1905 OS << "UNKNOWN";
1906
1907 if (SkipOpers)
1908 return;
1909
1910 // Print the rest of the operands.
1911 bool FirstOp = true;
1912 unsigned AsmDescOp = ~0u;
1913 unsigned AsmOpCount = 0;
1914
1915 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1916 // Print asm string.
1917 OS << " ";
1918 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1919 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, MRI: *MRI) : LLT{};
1920 unsigned TiedOperandIdx = GetTiedOperandIdx(OpIdx);
1921 getOperand(i: OpIdx).print(os&: OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true,
1922 IsStandalone, ShouldPrintRegisterTies,
1923 TiedOperandIdx, TRI);
1924
1925 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1926 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1927 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1928 OS << " [sideeffect]";
1929 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1930 OS << " [mayload]";
1931 if (ExtraInfo & InlineAsm::Extra_MayStore)
1932 OS << " [maystore]";
1933 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1934 OS << " [isconvergent]";
1935 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1936 OS << " [alignstack]";
1937 if (ExtraInfo & InlineAsm::Extra_MayUnwind)
1938 OS << " [unwind]";
1939 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1940 OS << " [attdialect]";
1941 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1942 OS << " [inteldialect]";
1943
1944 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1945 FirstOp = false;
1946 }
1947
1948 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1949 const MachineOperand &MO = getOperand(i);
1950
1951 if (FirstOp) FirstOp = false; else OS << ",";
1952 OS << " ";
1953
1954 if (isDebugValueLike() && MO.isMetadata()) {
1955 // Pretty print DBG_VALUE* instructions.
1956 auto *DIV = dyn_cast<DILocalVariable>(Val: MO.getMetadata());
1957 if (DIV && !DIV->getName().empty())
1958 OS << "!\"" << DIV->getName() << '\"';
1959 else {
1960 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{};
1961 unsigned TiedOperandIdx = GetTiedOperandIdx(i);
1962 MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone,
1963 ShouldPrintRegisterTies, TiedOperandIdx, TRI);
1964 }
1965 } else if (isDebugLabel() && MO.isMetadata()) {
1966 // Pretty print DBG_LABEL instructions.
1967 auto *DIL = dyn_cast<DILabel>(Val: MO.getMetadata());
1968 if (DIL && !DIL->getName().empty())
1969 OS << "\"" << DIL->getName() << '\"';
1970 else {
1971 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{};
1972 unsigned TiedOperandIdx = GetTiedOperandIdx(i);
1973 MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone,
1974 ShouldPrintRegisterTies, TiedOperandIdx, TRI);
1975 }
1976 } else if (i == AsmDescOp && MO.isImm()) {
1977 // Pretty print the inline asm operand descriptor.
1978 OS << '$' << AsmOpCount++;
1979 unsigned Flag = MO.getImm();
1980 const InlineAsm::Flag F(Flag);
1981 OS << ":[";
1982 OS << F.getKindName();
1983
1984 unsigned RCID;
1985 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RC&: RCID)) {
1986 if (TRI) {
1987 OS << ':' << TRI->getRegClassName(Class: TRI->getRegClass(i: RCID));
1988 } else
1989 OS << ":RC" << RCID;
1990 }
1991
1992 if (F.isMemKind()) {
1993 const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
1994 OS << ":" << InlineAsm::getMemConstraintName(C: MCID);
1995 }
1996
1997 unsigned TiedTo;
1998 if (F.isUseOperandTiedToDef(Idx&: TiedTo))
1999 OS << " tiedto:$" << TiedTo;
2000
2001 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||
2002 F.isRegUseKind()) &&
2003 F.getRegMayBeFolded()) {
2004 OS << " foldable";
2005 }
2006
2007 OS << ']';
2008
2009 // Compute the index of the next operand descriptor.
2010 AsmDescOp += 1 + F.getNumOperandRegisters();
2011 } else if (MO.isImm() && isOperandSubregIdx(OpIdx: i)) {
2012 MachineOperand::printSubRegIdx(OS, Index: MO.getImm(), TRI);
2013 } else {
2014 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{};
2015 unsigned TiedOperandIdx = GetTiedOperandIdx(i);
2016 MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone,
2017 ShouldPrintRegisterTies, TiedOperandIdx, TRI);
2018 }
2019 }
2020
2021 // Print any optional symbols attached to this instruction as-if they were
2022 // operands.
2023 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
2024 if (!FirstOp) {
2025 OS << ',';
2026 }
2027 OS << " pre-instr-symbol ";
2028 MachineOperand::printSymbol(OS, Sym&: *PreInstrSymbol);
2029 }
2030 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
2031 if (!FirstOp) {
2032 OS << ',';
2033 }
2034 OS << " post-instr-symbol ";
2035 MachineOperand::printSymbol(OS, Sym&: *PostInstrSymbol);
2036 }
2037 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
2038 if (!FirstOp) {
2039 OS << ',';
2040 }
2041 OS << " heap-alloc-marker ";
2042 HeapAllocMarker->printAsOperand(OS, MST);
2043 }
2044 if (MDNode *PCSections = getPCSections()) {
2045 if (!FirstOp) {
2046 OS << ',';
2047 }
2048 OS << " pcsections ";
2049 PCSections->printAsOperand(OS, MST);
2050 }
2051 if (MDNode *MMRA = getMMRAMetadata()) {
2052 if (!FirstOp) {
2053 OS << ',';
2054 }
2055 OS << " mmra ";
2056 MMRA->printAsOperand(OS, MST);
2057 }
2058 if (uint32_t CFIType = getCFIType()) {
2059 if (!FirstOp)
2060 OS << ',';
2061 OS << " cfi-type " << CFIType;
2062 }
2063 if (getDeactivationSymbol())
2064 OS << ", deactivation-symbol " << getDeactivationSymbol()->getName();
2065
2066 if (DebugInstrNum) {
2067 if (!FirstOp)
2068 OS << ",";
2069 OS << " debug-instr-number " << DebugInstrNum;
2070 }
2071
2072 if (!SkipDebugLoc) {
2073 if (const DebugLoc &DL = getDebugLoc()) {
2074 if (!FirstOp)
2075 OS << ',';
2076 OS << " debug-location ";
2077 DL->printAsOperand(OS, MST);
2078 }
2079 }
2080
2081 if (!memoperands_empty()) {
2082 SmallVector<StringRef, 0> SSNs;
2083 const LLVMContext *Context = nullptr;
2084 std::unique_ptr<LLVMContext> CtxPtr;
2085 const MachineFrameInfo *MFI = nullptr;
2086 if (const MachineFunction *MF = getMFIfAvailable(MI: *this)) {
2087 MFI = &MF->getFrameInfo();
2088 Context = &MF->getFunction().getContext();
2089 } else {
2090 CtxPtr = std::make_unique<LLVMContext>();
2091 Context = CtxPtr.get();
2092 }
2093
2094 OS << " :: ";
2095 bool NeedComma = false;
2096 for (const MachineMemOperand *Op : memoperands()) {
2097 if (NeedComma)
2098 OS << ", ";
2099 Op->print(OS, MST, SSNs, Context: *Context, MFI, TII);
2100 NeedComma = true;
2101 }
2102 }
2103
2104 if (SkipDebugLoc)
2105 return;
2106
2107 bool HaveSemi = false;
2108
2109 // Print debug location information.
2110 if (const DebugLoc &DL = getDebugLoc()) {
2111 if (!HaveSemi) {
2112 OS << ';';
2113 HaveSemi = true;
2114 }
2115 OS << ' ';
2116 DL.print(OS);
2117 }
2118
2119 // Print extra comments for DEBUG_VALUE and friends if they are well-formed.
2120 if ((isNonListDebugValue() && getNumOperands() >= 4) ||
2121 (isDebugValueList() && getNumOperands() >= 2) ||
2122 (isDebugRef() && getNumOperands() >= 3)) {
2123 if (getDebugVariableOp().isMetadata()) {
2124 if (!HaveSemi) {
2125 OS << ";";
2126 HaveSemi = true;
2127 }
2128 auto *DV = getDebugVariable();
2129 OS << " line no:" << DV->getLine();
2130 if (isIndirectDebugValue())
2131 OS << " indirect";
2132 }
2133 }
2134 // TODO: DBG_LABEL
2135
2136 if (PrintMIAddrs)
2137 OS << " ; " << this;
2138
2139 if (AddNewLine)
2140 OS << '\n';
2141}
2142
2143bool MachineInstr::addRegisterKilled(Register IncomingReg,
2144 const TargetRegisterInfo *RegInfo,
2145 bool AddIfNotFound) {
2146 bool isPhysReg = IncomingReg.isPhysical();
2147 bool hasAliases = isPhysReg &&
2148 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
2149 bool Found = false;
2150 SmallVector<unsigned,4> DeadOps;
2151 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2152 MachineOperand &MO = getOperand(i);
2153 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
2154 continue;
2155
2156 // DEBUG_VALUE nodes do not contribute to code generation and should
2157 // always be ignored. Failure to do so may result in trying to modify
2158 // KILL flags on DEBUG_VALUE nodes.
2159 if (MO.isDebug())
2160 continue;
2161
2162 Register Reg = MO.getReg();
2163 if (!Reg)
2164 continue;
2165
2166 if (Reg == IncomingReg) {
2167 if (!Found) {
2168 if (MO.isKill())
2169 // The register is already marked kill.
2170 return true;
2171 if (isPhysReg && isRegTiedToDefOperand(UseOpIdx: i))
2172 // Two-address uses of physregs must not be marked kill.
2173 return true;
2174 MO.setIsKill();
2175 Found = true;
2176 }
2177 } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {
2178 // A super-register kill already exists.
2179 if (RegInfo->isSuperRegister(RegA: IncomingReg, RegB: Reg))
2180 return true;
2181 if (RegInfo->isSubRegister(RegA: IncomingReg, RegB: Reg))
2182 DeadOps.push_back(Elt: i);
2183 }
2184 }
2185
2186 // Trim unneeded kill operands.
2187 while (!DeadOps.empty()) {
2188 unsigned OpIdx = DeadOps.back();
2189 if (getOperand(i: OpIdx).isImplicit() &&
2190 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2191 removeOperand(OpNo: OpIdx);
2192 else
2193 getOperand(i: OpIdx).setIsKill(false);
2194 DeadOps.pop_back();
2195 }
2196
2197 // If not found, this means an alias of one of the operands is killed. Add a
2198 // new implicit operand if required.
2199 if (!Found && AddIfNotFound) {
2200 addOperand(Op: MachineOperand::CreateReg(Reg: IncomingReg,
2201 isDef: false /*IsDef*/,
2202 isImp: true /*IsImp*/,
2203 isKill: true /*IsKill*/));
2204 return true;
2205 }
2206 return Found;
2207}
2208
2209void MachineInstr::clearRegisterKills(Register Reg,
2210 const TargetRegisterInfo *RegInfo) {
2211 if (!Reg.isPhysical())
2212 RegInfo = nullptr;
2213 for (MachineOperand &MO : operands()) {
2214 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2215 continue;
2216 Register OpReg = MO.getReg();
2217 if ((RegInfo && RegInfo->regsOverlap(RegA: Reg, RegB: OpReg)) || Reg == OpReg)
2218 MO.setIsKill(false);
2219 }
2220}
2221
2222bool MachineInstr::addRegisterDead(Register Reg,
2223 const TargetRegisterInfo *RegInfo,
2224 bool AddIfNotFound) {
2225 bool isPhysReg = Reg.isPhysical();
2226 bool hasAliases = isPhysReg &&
2227 MCRegAliasIterator(Reg, RegInfo, false).isValid();
2228 bool Found = false;
2229 SmallVector<unsigned,4> DeadOps;
2230 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2231 MachineOperand &MO = getOperand(i);
2232 if (!MO.isReg() || !MO.isDef())
2233 continue;
2234 Register MOReg = MO.getReg();
2235 if (!MOReg)
2236 continue;
2237
2238 if (MOReg == Reg) {
2239 MO.setIsDead();
2240 Found = true;
2241 } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {
2242 // There exists a super-register that's marked dead.
2243 if (RegInfo->isSuperRegister(RegA: Reg, RegB: MOReg))
2244 return true;
2245 if (RegInfo->isSubRegister(RegA: Reg, RegB: MOReg))
2246 DeadOps.push_back(Elt: i);
2247 }
2248 }
2249
2250 // Trim unneeded dead operands.
2251 while (!DeadOps.empty()) {
2252 unsigned OpIdx = DeadOps.back();
2253 if (getOperand(i: OpIdx).isImplicit() &&
2254 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2255 removeOperand(OpNo: OpIdx);
2256 else
2257 getOperand(i: OpIdx).setIsDead(false);
2258 DeadOps.pop_back();
2259 }
2260
2261 // If not found, this means an alias of one of the operands is dead. Add a
2262 // new implicit operand if required.
2263 if (Found || !AddIfNotFound)
2264 return Found;
2265
2266 addOperand(Op: MachineOperand::CreateReg(Reg,
2267 isDef: true /*IsDef*/,
2268 isImp: true /*IsImp*/,
2269 isKill: false /*IsKill*/,
2270 isDead: true /*IsDead*/));
2271 return true;
2272}
2273
2274void MachineInstr::clearRegisterDeads(Register Reg) {
2275 for (MachineOperand &MO : all_defs())
2276 if (MO.getReg() == Reg)
2277 MO.setIsDead(false);
2278}
2279
2280void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2281 for (MachineOperand &MO : all_defs())
2282 if (MO.getReg() == Reg && MO.getSubReg() != 0)
2283 MO.setIsUndef(IsUndef);
2284}
2285
2286void MachineInstr::addRegisterDefined(Register Reg,
2287 const TargetRegisterInfo *RegInfo) {
2288 if (Reg.isPhysical()) {
2289 MachineOperand *MO = findRegisterDefOperand(Reg, TRI: RegInfo, isDead: false, Overlap: false);
2290 if (MO)
2291 return;
2292 } else {
2293 for (const MachineOperand &MO : all_defs()) {
2294 if (MO.getReg() == Reg && MO.getSubReg() == 0)
2295 return;
2296 }
2297 }
2298 addOperand(Op: MachineOperand::CreateReg(Reg,
2299 isDef: true /*IsDef*/,
2300 isImp: true /*IsImp*/));
2301}
2302
2303void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2304 const TargetRegisterInfo &TRI) {
2305 bool HasRegMask = false;
2306 for (MachineOperand &MO : operands()) {
2307 if (MO.isRegMask()) {
2308 HasRegMask = true;
2309 continue;
2310 }
2311 if (!MO.isReg() || !MO.isDef()) continue;
2312 Register Reg = MO.getReg();
2313 if (!Reg.isPhysical())
2314 continue;
2315 // If there are no uses, including partial uses, the def is dead.
2316 if (llvm::none_of(Range&: UsedRegs,
2317 P: [&](MCRegister Use) { return TRI.regsOverlap(RegA: Use, RegB: Reg); }))
2318 MO.setIsDead();
2319 }
2320
2321 // This is a call with a register mask operand.
2322 // Mask clobbers are always dead, so add defs for the non-dead defines.
2323 if (HasRegMask)
2324 for (const Register &UsedReg : UsedRegs)
2325 addRegisterDefined(Reg: UsedReg, RegInfo: &TRI);
2326}
2327
2328unsigned
2329MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2330 // Build up a buffer of hash code components.
2331 SmallVector<size_t, 16> HashComponents;
2332 HashComponents.reserve(N: MI->getNumOperands() + 1);
2333 HashComponents.push_back(Elt: MI->getOpcode());
2334 for (const MachineOperand &MO : MI->operands()) {
2335 if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
2336 continue; // Skip virtual register defs.
2337
2338 HashComponents.push_back(Elt: hash_value(MO));
2339 }
2340 return hash_combine_range(R&: HashComponents);
2341}
2342
2343const MDNode *MachineInstr::getLocCookieMD() const {
2344 // Find the source location cookie.
2345 const MDNode *LocMD = nullptr;
2346 for (unsigned i = getNumOperands(); i != 0; --i) {
2347 if (getOperand(i: i-1).isMetadata() &&
2348 (LocMD = getOperand(i: i-1).getMetadata()) &&
2349 LocMD->getNumOperands() != 0) {
2350 if (mdconst::hasa<ConstantInt>(MD: LocMD->getOperand(I: 0)))
2351 return LocMD;
2352 }
2353 }
2354
2355 return nullptr;
2356}
2357
2358void MachineInstr::emitInlineAsmError(const Twine &Msg) const {
2359 assert(isInlineAsm());
2360 const MDNode *LocMD = getLocCookieMD();
2361 uint64_t LocCookie =
2362 LocMD
2363 ? mdconst::extract<ConstantInt>(MD: LocMD->getOperand(I: 0))->getZExtValue()
2364 : 0;
2365 LLVMContext &Ctx = getMF()->getFunction().getContext();
2366 Ctx.diagnose(DI: DiagnosticInfoInlineAsm(LocCookie, Msg));
2367}
2368
2369void MachineInstr::emitGenericError(const Twine &Msg) const {
2370 const Function &Fn = getMF()->getFunction();
2371 Fn.getContext().diagnose(
2372 DI: DiagnosticInfoGenericWithLoc(Msg, Fn, getDebugLoc()));
2373}
2374
2375MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2376 const MCInstrDesc &MCID, bool IsIndirect,
2377 Register Reg, const MDNode *Variable,
2378 const MDNode *Expr) {
2379 assert(isa<DILocalVariable>(Variable) && "not a variable");
2380 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2381 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2382 "Expected inlined-at fields to agree");
2383 auto MIB = BuildMI(MF, MIMD: DL, MCID).addReg(RegNo: Reg);
2384 if (IsIndirect)
2385 MIB.addImm(Val: 0U);
2386 else
2387 MIB.addReg(RegNo: 0U);
2388 return MIB.addMetadata(MD: Variable).addMetadata(MD: Expr);
2389}
2390
2391MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2392 const MCInstrDesc &MCID, bool IsIndirect,
2393 ArrayRef<MachineOperand> DebugOps,
2394 const MDNode *Variable, const MDNode *Expr) {
2395 assert(isa<DILocalVariable>(Variable) && "not a variable");
2396 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2397 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2398 "Expected inlined-at fields to agree");
2399 if (MCID.Opcode == TargetOpcode::DBG_VALUE) {
2400 assert(DebugOps.size() == 1 &&
2401 "DBG_VALUE must contain exactly one debug operand");
2402 MachineOperand DebugOp = DebugOps[0];
2403 if (DebugOp.isReg())
2404 return BuildMI(MF, DL, MCID, IsIndirect, Reg: DebugOp.getReg(), Variable,
2405 Expr);
2406
2407 auto MIB = BuildMI(MF, MIMD: DL, MCID).add(MO: DebugOp);
2408 if (IsIndirect)
2409 MIB.addImm(Val: 0U);
2410 else
2411 MIB.addReg(RegNo: 0U);
2412 return MIB.addMetadata(MD: Variable).addMetadata(MD: Expr);
2413 }
2414
2415 auto MIB = BuildMI(MF, MIMD: DL, MCID);
2416 MIB.addMetadata(MD: Variable).addMetadata(MD: Expr);
2417 for (const MachineOperand &DebugOp : DebugOps)
2418 if (DebugOp.isReg())
2419 MIB.addReg(RegNo: DebugOp.getReg());
2420 else
2421 MIB.add(MO: DebugOp);
2422 return MIB;
2423}
2424
2425MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2426 MachineBasicBlock::iterator I,
2427 const DebugLoc &DL, const MCInstrDesc &MCID,
2428 bool IsIndirect, Register Reg,
2429 const MDNode *Variable, const MDNode *Expr) {
2430 MachineFunction &MF = *BB.getParent();
2431 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2432 BB.insert(I, MI);
2433 return MachineInstrBuilder(MF, MI);
2434}
2435
2436MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2437 MachineBasicBlock::iterator I,
2438 const DebugLoc &DL, const MCInstrDesc &MCID,
2439 bool IsIndirect,
2440 ArrayRef<MachineOperand> DebugOps,
2441 const MDNode *Variable, const MDNode *Expr) {
2442 MachineFunction &MF = *BB.getParent();
2443 MachineInstr *MI =
2444 BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2445 BB.insert(I, MI);
2446 return MachineInstrBuilder(MF, *MI);
2447}
2448
2449/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2450/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2451static const DIExpression *computeExprForSpill(
2452 const MachineInstr &MI,
2453 const SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2454 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2455 "Expected inlined-at fields to agree");
2456
2457 const DIExpression *Expr = MI.getDebugExpression();
2458 if (MI.isIndirectDebugValue()) {
2459 assert(MI.getDebugOffset().getImm() == 0 &&
2460 "DBG_VALUE with nonzero offset");
2461 Expr = DIExpression::prepend(Expr, Flags: DIExpression::DerefBefore);
2462 } else if (MI.isDebugValueList()) {
2463 // We will replace the spilled register with a frame index, so
2464 // immediately deref all references to the spilled register.
2465 std::array<uint64_t, 1> Ops{._M_elems: {dwarf::DW_OP_deref}};
2466 for (const MachineOperand *Op : SpilledOperands) {
2467 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2468 Expr = DIExpression::appendOpsToArg(Expr, Ops, ArgNo: OpIdx);
2469 }
2470 }
2471 return Expr;
2472}
2473static const DIExpression *computeExprForSpill(const MachineInstr &MI,
2474 Register SpillReg) {
2475 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2476 SmallVector<const MachineOperand *> SpillOperands(
2477 llvm::make_pointer_range(Range: MI.getDebugOperandsForReg(Reg: SpillReg)));
2478 return computeExprForSpill(MI, SpilledOperands: SpillOperands);
2479}
2480
2481MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2482 MachineBasicBlock::iterator I,
2483 const MachineInstr &Orig,
2484 int FrameIndex, Register SpillReg) {
2485 assert(!Orig.isDebugRef() &&
2486 "DBG_INSTR_REF should not reference a virtual register.");
2487 const DIExpression *Expr = computeExprForSpill(MI: Orig, SpillReg);
2488 MachineInstrBuilder NewMI =
2489 BuildMI(BB, I, MIMD: Orig.getDebugLoc(), MCID: Orig.getDesc());
2490 // Non-Variadic Operands: Location, Offset, Variable, Expression
2491 // Variadic Operands: Variable, Expression, Locations...
2492 if (Orig.isNonListDebugValue())
2493 NewMI.addFrameIndex(Idx: FrameIndex).addImm(Val: 0U);
2494 NewMI.addMetadata(MD: Orig.getDebugVariable()).addMetadata(MD: Expr);
2495 if (Orig.isDebugValueList()) {
2496 for (const MachineOperand &Op : Orig.debug_operands())
2497 if (Op.isReg() && Op.getReg() == SpillReg)
2498 NewMI.addFrameIndex(Idx: FrameIndex);
2499 else
2500 NewMI.add(MO: MachineOperand(Op));
2501 }
2502 return NewMI;
2503}
2504MachineInstr *llvm::buildDbgValueForSpill(
2505 MachineBasicBlock &BB, MachineBasicBlock::iterator I,
2506 const MachineInstr &Orig, int FrameIndex,
2507 const SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2508 const DIExpression *Expr = computeExprForSpill(MI: Orig, SpilledOperands);
2509 MachineInstrBuilder NewMI =
2510 BuildMI(BB, I, MIMD: Orig.getDebugLoc(), MCID: Orig.getDesc());
2511 // Non-Variadic Operands: Location, Offset, Variable, Expression
2512 // Variadic Operands: Variable, Expression, Locations...
2513 if (Orig.isNonListDebugValue())
2514 NewMI.addFrameIndex(Idx: FrameIndex).addImm(Val: 0U);
2515 NewMI.addMetadata(MD: Orig.getDebugVariable()).addMetadata(MD: Expr);
2516 if (Orig.isDebugValueList()) {
2517 for (const MachineOperand &Op : Orig.debug_operands())
2518 if (is_contained(Range: SpilledOperands, Element: &Op))
2519 NewMI.addFrameIndex(Idx: FrameIndex);
2520 else
2521 NewMI.add(MO: MachineOperand(Op));
2522 }
2523 return NewMI;
2524}
2525
2526void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex,
2527 Register Reg) {
2528 const DIExpression *Expr = computeExprForSpill(MI: Orig, SpillReg: Reg);
2529 if (Orig.isNonListDebugValue())
2530 Orig.getDebugOffset().ChangeToImmediate(ImmVal: 0U);
2531 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2532 Op.ChangeToFrameIndex(Idx: FrameIndex);
2533 Orig.getDebugExpressionOp().setMetadata(Expr);
2534}
2535
2536void MachineInstr::collectDebugValues(
2537 SmallVectorImpl<MachineInstr *> &DbgValues) {
2538 MachineInstr &MI = *this;
2539 if (!MI.getOperand(i: 0).isReg())
2540 return;
2541
2542 MachineBasicBlock::iterator DI = MI; ++DI;
2543 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2544 DI != DE; ++DI) {
2545 if (!DI->isDebugValue())
2546 return;
2547 if (DI->hasDebugOperandForReg(Reg: MI.getOperand(i: 0).getReg()))
2548 DbgValues.push_back(Elt: &*DI);
2549 }
2550}
2551
2552void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2553 // Collect matching debug values.
2554 SmallVector<MachineInstr *, 2> DbgValues;
2555
2556 if (!getOperand(i: 0).isReg())
2557 return;
2558
2559 Register DefReg = getOperand(i: 0).getReg();
2560 auto *MRI = getRegInfo();
2561 for (auto &MO : MRI->use_operands(Reg: DefReg)) {
2562 auto *DI = MO.getParent();
2563 if (!DI->isDebugValue())
2564 continue;
2565 if (DI->hasDebugOperandForReg(Reg: DefReg)) {
2566 DbgValues.push_back(Elt: DI);
2567 }
2568 }
2569
2570 // Propagate Reg to debug value instructions.
2571 for (auto *DBI : DbgValues)
2572 for (MachineOperand &Op : DBI->getDebugOperandsForReg(Reg: DefReg))
2573 Op.setReg(Reg);
2574}
2575
2576using MMOList = SmallVector<const MachineMemOperand *, 2>;
2577
2578static LocationSize getSpillSlotSize(const MMOList &Accesses,
2579 const MachineFrameInfo &MFI) {
2580 std::optional<TypeSize> Size;
2581 for (const auto *A : Accesses) {
2582 if (MFI.isSpillSlotObjectIndex(
2583 ObjectIdx: cast<FixedStackPseudoSourceValue>(Val: A->getPseudoValue())
2584 ->getFrameIndex())) {
2585 LocationSize S = A->getSize();
2586 if (!S.hasValue())
2587 return LocationSize::beforeOrAfterPointer();
2588 if (!Size)
2589 Size = S.getValue();
2590 else
2591 Size = *Size + S.getValue();
2592 }
2593 }
2594 if (!Size)
2595 return LocationSize::precise(Value: 0);
2596 return LocationSize::precise(Value: *Size);
2597}
2598
2599std::optional<LocationSize>
2600MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2601 int FI;
2602 if (TII->isStoreToStackSlotPostFE(MI: *this, FrameIndex&: FI)) {
2603 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2604 if (MFI.isSpillSlotObjectIndex(ObjectIdx: FI))
2605 return (*memoperands_begin())->getSize();
2606 }
2607 return std::nullopt;
2608}
2609
2610std::optional<LocationSize>
2611MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2612 if (!mayStore())
2613 return std::nullopt;
2614
2615 MMOList Accesses;
2616 if (TII->hasStoreToStackSlot(MI: *this, Accesses))
2617 return getSpillSlotSize(Accesses, MFI: getMF()->getFrameInfo());
2618 return std::nullopt;
2619}
2620
2621std::optional<LocationSize>
2622MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2623 int FI;
2624 if (TII->isLoadFromStackSlotPostFE(MI: *this, FrameIndex&: FI)) {
2625 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2626 if (MFI.isSpillSlotObjectIndex(ObjectIdx: FI))
2627 return (*memoperands_begin())->getSize();
2628 }
2629 return std::nullopt;
2630}
2631
2632std::optional<LocationSize>
2633MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2634 MMOList Accesses;
2635 if (TII->hasLoadFromStackSlot(MI: *this, Accesses))
2636 return getSpillSlotSize(Accesses, MFI: getMF()->getFrameInfo());
2637 return std::nullopt;
2638}
2639
2640unsigned MachineInstr::getDebugInstrNum() {
2641 if (DebugInstrNum == 0)
2642 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2643 return DebugInstrNum;
2644}
2645
2646unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {
2647 if (DebugInstrNum == 0)
2648 DebugInstrNum = MF.getNewDebugInstrNum();
2649 return DebugInstrNum;
2650}
2651
2652std::tuple<LLT, LLT> MachineInstr::getFirst2LLTs() const {
2653 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2654 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()));
2655}
2656
2657std::tuple<LLT, LLT, LLT> MachineInstr::getFirst3LLTs() const {
2658 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2659 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()),
2660 getRegInfo()->getType(Reg: getOperand(i: 2).getReg()));
2661}
2662
2663std::tuple<LLT, LLT, LLT, LLT> MachineInstr::getFirst4LLTs() const {
2664 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2665 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()),
2666 getRegInfo()->getType(Reg: getOperand(i: 2).getReg()),
2667 getRegInfo()->getType(Reg: getOperand(i: 3).getReg()));
2668}
2669
2670std::tuple<LLT, LLT, LLT, LLT, LLT> MachineInstr::getFirst5LLTs() const {
2671 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2672 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()),
2673 getRegInfo()->getType(Reg: getOperand(i: 2).getReg()),
2674 getRegInfo()->getType(Reg: getOperand(i: 3).getReg()),
2675 getRegInfo()->getType(Reg: getOperand(i: 4).getReg()));
2676}
2677
2678std::tuple<Register, LLT, Register, LLT>
2679MachineInstr::getFirst2RegLLTs() const {
2680 Register Reg0 = getOperand(i: 0).getReg();
2681 Register Reg1 = getOperand(i: 1).getReg();
2682 return std::tuple(Reg0, getRegInfo()->getType(Reg: Reg0), Reg1,
2683 getRegInfo()->getType(Reg: Reg1));
2684}
2685
2686std::tuple<Register, LLT, Register, LLT, Register, LLT>
2687MachineInstr::getFirst3RegLLTs() const {
2688 Register Reg0 = getOperand(i: 0).getReg();
2689 Register Reg1 = getOperand(i: 1).getReg();
2690 Register Reg2 = getOperand(i: 2).getReg();
2691 return std::tuple(Reg0, getRegInfo()->getType(Reg: Reg0), Reg1,
2692 getRegInfo()->getType(Reg: Reg1), Reg2,
2693 getRegInfo()->getType(Reg: Reg2));
2694}
2695
2696std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2697MachineInstr::getFirst4RegLLTs() const {
2698 Register Reg0 = getOperand(i: 0).getReg();
2699 Register Reg1 = getOperand(i: 1).getReg();
2700 Register Reg2 = getOperand(i: 2).getReg();
2701 Register Reg3 = getOperand(i: 3).getReg();
2702 return std::tuple(
2703 Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, getRegInfo()->getType(Reg: Reg1),
2704 Reg2, getRegInfo()->getType(Reg: Reg2), Reg3, getRegInfo()->getType(Reg: Reg3));
2705}
2706
2707std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register,
2708 LLT>
2709MachineInstr::getFirst5RegLLTs() const {
2710 Register Reg0 = getOperand(i: 0).getReg();
2711 Register Reg1 = getOperand(i: 1).getReg();
2712 Register Reg2 = getOperand(i: 2).getReg();
2713 Register Reg3 = getOperand(i: 3).getReg();
2714 Register Reg4 = getOperand(i: 4).getReg();
2715 return std::tuple(
2716 Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, getRegInfo()->getType(Reg: Reg1),
2717 Reg2, getRegInfo()->getType(Reg: Reg2), Reg3, getRegInfo()->getType(Reg: Reg3),
2718 Reg4, getRegInfo()->getType(Reg: Reg4));
2719}
2720
2721void MachineInstr::insert(mop_iterator InsertBefore,
2722 ArrayRef<MachineOperand> Ops) {
2723 assert(InsertBefore != nullptr && "invalid iterator");
2724 assert(InsertBefore->getParent() == this &&
2725 "iterator points to operand of other inst");
2726 if (Ops.empty())
2727 return;
2728
2729 // Do one pass to untie operands.
2730 SmallDenseMap<unsigned, unsigned> TiedOpIndices;
2731 for (const MachineOperand &MO : operands()) {
2732 if (MO.isReg() && MO.isTied()) {
2733 unsigned OpNo = getOperandNo(I: &MO);
2734 unsigned TiedTo = findTiedOperandIdx(OpIdx: OpNo);
2735 TiedOpIndices[OpNo] = TiedTo;
2736 untieRegOperand(OpIdx: OpNo);
2737 }
2738 }
2739
2740 unsigned OpIdx = getOperandNo(I: InsertBefore);
2741 unsigned NumOperands = getNumOperands();
2742 unsigned OpsToMove = NumOperands - OpIdx;
2743
2744 SmallVector<MachineOperand> MovingOps;
2745 MovingOps.reserve(N: OpsToMove);
2746
2747 for (unsigned I = 0; I < OpsToMove; ++I) {
2748 MovingOps.emplace_back(Args&: getOperand(i: OpIdx));
2749 removeOperand(OpNo: OpIdx);
2750 }
2751 for (const MachineOperand &MO : Ops)
2752 addOperand(Op: MO);
2753 for (const MachineOperand &OpMoved : MovingOps)
2754 addOperand(Op: OpMoved);
2755
2756 // Re-tie operands.
2757 for (auto [Tie1, Tie2] : TiedOpIndices) {
2758 if (Tie1 >= OpIdx)
2759 Tie1 += Ops.size();
2760 if (Tie2 >= OpIdx)
2761 Tie2 += Ops.size();
2762 tieOperands(DefIdx: Tie1, UseIdx: Tie2);
2763 }
2764}
2765
2766bool MachineInstr::mayFoldInlineAsmRegOp(unsigned OpId) const {
2767 assert(OpId && "expected non-zero operand id");
2768 assert(isInlineAsm() && "should only be used on inline asm");
2769
2770 if (!getOperand(i: OpId).isReg())
2771 return false;
2772
2773 const MachineOperand &MD = getOperand(i: OpId - 1);
2774 if (!MD.isImm())
2775 return false;
2776
2777 InlineAsm::Flag F(MD.getImm());
2778 if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind())
2779 return F.getRegMayBeFolded();
2780 return false;
2781}
2782
2783unsigned MachineInstr::removePHIIncomingValueFor(const MachineBasicBlock &MBB) {
2784 assert(isPHI());
2785
2786 // Phi might have multiple entries for MBB. Need to remove them all.
2787 unsigned RemovedCount = 0;
2788 for (unsigned N = getNumOperands(); N > 2; N -= 2) {
2789 if (getOperand(i: N - 1).getMBB() == &MBB) {
2790 removeOperand(OpNo: N - 1);
2791 removeOperand(OpNo: N - 2);
2792 RemovedCount += 2;
2793 }
2794 }
2795 return RemovedCount;
2796}
2797