1//===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating from LLVM IR into SelectionDAG IR.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SelectionDAGBuilder.h"
14#include "SDNodeDbgValue.h"
15#include "llvm/ADT/APFloat.h"
16#include "llvm/ADT/APInt.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallPtrSet.h"
20#include "llvm/ADT/StringExtras.h"
21#include "llvm/ADT/StringRef.h"
22#include "llvm/ADT/Twine.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/Analysis/BranchProbabilityInfo.h"
25#include "llvm/Analysis/ConstantFolding.h"
26#include "llvm/Analysis/Loads.h"
27#include "llvm/Analysis/MemoryLocation.h"
28#include "llvm/Analysis/TargetLibraryInfo.h"
29#include "llvm/Analysis/TargetTransformInfo.h"
30#include "llvm/Analysis/ValueTracking.h"
31#include "llvm/Analysis/VectorUtils.h"
32#include "llvm/CodeGen/Analysis.h"
33#include "llvm/CodeGen/AssignmentTrackingAnalysis.h"
34#include "llvm/CodeGen/CodeGenCommonISel.h"
35#include "llvm/CodeGen/FunctionLoweringInfo.h"
36#include "llvm/CodeGen/GCMetadata.h"
37#include "llvm/CodeGen/ISDOpcodes.h"
38#include "llvm/CodeGen/MachineBasicBlock.h"
39#include "llvm/CodeGen/MachineFrameInfo.h"
40#include "llvm/CodeGen/MachineFunction.h"
41#include "llvm/CodeGen/MachineInstrBuilder.h"
42#include "llvm/CodeGen/MachineInstrBundleIterator.h"
43#include "llvm/CodeGen/MachineMemOperand.h"
44#include "llvm/CodeGen/MachineModuleInfo.h"
45#include "llvm/CodeGen/MachineOperand.h"
46#include "llvm/CodeGen/MachineRegisterInfo.h"
47#include "llvm/CodeGen/SelectionDAG.h"
48#include "llvm/CodeGen/SelectionDAGNodes.h"
49#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
50#include "llvm/CodeGen/StackMaps.h"
51#include "llvm/CodeGen/SwiftErrorValueTracking.h"
52#include "llvm/CodeGen/TargetFrameLowering.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetOpcodes.h"
55#include "llvm/CodeGen/TargetRegisterInfo.h"
56#include "llvm/CodeGen/TargetSubtargetInfo.h"
57#include "llvm/CodeGen/WinEHFuncInfo.h"
58#include "llvm/IR/Argument.h"
59#include "llvm/IR/Attributes.h"
60#include "llvm/IR/BasicBlock.h"
61#include "llvm/IR/CFG.h"
62#include "llvm/IR/CallingConv.h"
63#include "llvm/IR/Constant.h"
64#include "llvm/IR/ConstantRange.h"
65#include "llvm/IR/Constants.h"
66#include "llvm/IR/DataLayout.h"
67#include "llvm/IR/DebugInfo.h"
68#include "llvm/IR/DebugInfoMetadata.h"
69#include "llvm/IR/DerivedTypes.h"
70#include "llvm/IR/DiagnosticInfo.h"
71#include "llvm/IR/EHPersonalities.h"
72#include "llvm/IR/Function.h"
73#include "llvm/IR/GetElementPtrTypeIterator.h"
74#include "llvm/IR/InlineAsm.h"
75#include "llvm/IR/InstrTypes.h"
76#include "llvm/IR/Instructions.h"
77#include "llvm/IR/IntrinsicInst.h"
78#include "llvm/IR/Intrinsics.h"
79#include "llvm/IR/IntrinsicsAArch64.h"
80#include "llvm/IR/IntrinsicsAMDGPU.h"
81#include "llvm/IR/IntrinsicsWebAssembly.h"
82#include "llvm/IR/LLVMContext.h"
83#include "llvm/IR/MemoryModelRelaxationAnnotations.h"
84#include "llvm/IR/Metadata.h"
85#include "llvm/IR/Module.h"
86#include "llvm/IR/Operator.h"
87#include "llvm/IR/PatternMatch.h"
88#include "llvm/IR/Statepoint.h"
89#include "llvm/IR/Type.h"
90#include "llvm/IR/User.h"
91#include "llvm/IR/Value.h"
92#include "llvm/MC/MCContext.h"
93#include "llvm/Support/AtomicOrdering.h"
94#include "llvm/Support/Casting.h"
95#include "llvm/Support/CommandLine.h"
96#include "llvm/Support/Compiler.h"
97#include "llvm/Support/Debug.h"
98#include "llvm/Support/InstructionCost.h"
99#include "llvm/Support/MathExtras.h"
100#include "llvm/Support/raw_ostream.h"
101#include "llvm/Target/TargetMachine.h"
102#include "llvm/Target/TargetOptions.h"
103#include "llvm/TargetParser/Triple.h"
104#include "llvm/Transforms/Utils/Local.h"
105#include <cstddef>
106#include <limits>
107#include <optional>
108#include <tuple>
109
110using namespace llvm;
111using namespace PatternMatch;
112using namespace SwitchCG;
113
114#define DEBUG_TYPE "isel"
115
116/// LimitFloatPrecision - Generate low-precision inline sequences for
117/// some float libcalls (6, 8 or 12 bits).
118static unsigned LimitFloatPrecision;
119
120static cl::opt<bool>
121 InsertAssertAlign("insert-assert-align", cl::init(Val: true),
122 cl::desc("Insert the experimental `assertalign` node."),
123 cl::ReallyHidden);
124
125static cl::opt<unsigned, true>
126 LimitFPPrecision("limit-float-precision",
127 cl::desc("Generate low-precision inline sequences "
128 "for some float libcalls"),
129 cl::location(L&: LimitFloatPrecision), cl::Hidden,
130 cl::init(Val: 0));
131
132static cl::opt<unsigned> SwitchPeelThreshold(
133 "switch-peel-threshold", cl::Hidden, cl::init(Val: 66),
134 cl::desc("Set the case probability threshold for peeling the case from a "
135 "switch statement. A value greater than 100 will void this "
136 "optimization"));
137
138// Limit the width of DAG chains. This is important in general to prevent
139// DAG-based analysis from blowing up. For example, alias analysis and
140// load clustering may not complete in reasonable time. It is difficult to
141// recognize and avoid this situation within each individual analysis, and
142// future analyses are likely to have the same behavior. Limiting DAG width is
143// the safe approach and will be especially important with global DAGs.
144//
145// MaxParallelChains default is arbitrarily high to avoid affecting
146// optimization, but could be lowered to improve compile time. Any ld-ld-st-st
147// sequence over this should have been converted to llvm.memcpy by the
148// frontend. It is easy to induce this behavior with .ll code such as:
149// %buffer = alloca [4096 x i8]
150// %data = load [4096 x i8]* %argPtr
151// store [4096 x i8] %data, [4096 x i8]* %buffer
152static const unsigned MaxParallelChains = 64;
153
154static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
155 const SDValue *Parts, unsigned NumParts,
156 MVT PartVT, EVT ValueVT, const Value *V,
157 SDValue InChain,
158 std::optional<CallingConv::ID> CC);
159
160/// getCopyFromParts - Create a value that contains the specified legal parts
161/// combined into the value they represent. If the parts combine to a type
162/// larger than ValueVT then AssertOp can be used to specify whether the extra
163/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
164/// (ISD::AssertSext).
165static SDValue
166getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
167 unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V,
168 SDValue InChain,
169 std::optional<CallingConv::ID> CC = std::nullopt,
170 std::optional<ISD::NodeType> AssertOp = std::nullopt) {
171 // Let the target assemble the parts if it wants to
172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
173 if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts,
174 PartVT, ValueVT, CC))
175 return Val;
176
177 if (ValueVT.isVector())
178 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
179 InChain, CC);
180
181 assert(NumParts > 0 && "No parts to assemble!");
182 SDValue Val = Parts[0];
183
184 if (NumParts > 1) {
185 // Assemble the value from multiple parts.
186 if (ValueVT.isInteger()) {
187 unsigned PartBits = PartVT.getSizeInBits();
188 unsigned ValueBits = ValueVT.getSizeInBits();
189
190 // Assemble the power of 2 part.
191 unsigned RoundParts = llvm::bit_floor(Value: NumParts);
192 unsigned RoundBits = PartBits * RoundParts;
193 EVT RoundVT = RoundBits == ValueBits ?
194 ValueVT : EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RoundBits);
195 SDValue Lo, Hi;
196
197 EVT HalfVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RoundBits/2);
198
199 if (RoundParts > 2) {
200 Lo = getCopyFromParts(DAG, DL, Parts, NumParts: RoundParts / 2, PartVT, ValueVT: HalfVT, V,
201 InChain);
202 Hi = getCopyFromParts(DAG, DL, Parts: Parts + RoundParts / 2, NumParts: RoundParts / 2,
203 PartVT, ValueVT: HalfVT, V, InChain);
204 } else {
205 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: HalfVT, Operand: Parts[0]);
206 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: HalfVT, Operand: Parts[1]);
207 }
208
209 if (DAG.getDataLayout().isBigEndian())
210 std::swap(a&: Lo, b&: Hi);
211
212 Val = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL, VT: RoundVT, N1: Lo, N2: Hi);
213
214 if (RoundParts < NumParts) {
215 // Assemble the trailing non-power-of-2 part.
216 unsigned OddParts = NumParts - RoundParts;
217 EVT OddVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: OddParts * PartBits);
218 Hi = getCopyFromParts(DAG, DL, Parts: Parts + RoundParts, NumParts: OddParts, PartVT,
219 ValueVT: OddVT, V, InChain, CC);
220
221 // Combine the round and odd parts.
222 Lo = Val;
223 if (DAG.getDataLayout().isBigEndian())
224 std::swap(a&: Lo, b&: Hi);
225 EVT TotalVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumParts * PartBits);
226 Hi = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: TotalVT, Operand: Hi);
227 Hi = DAG.getNode(
228 Opcode: ISD::SHL, DL, VT: TotalVT, N1: Hi,
229 N2: DAG.getShiftAmountConstant(Val: Lo.getValueSizeInBits(), VT: TotalVT, DL));
230 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: TotalVT, Operand: Lo);
231 Val = DAG.getNode(Opcode: ISD::OR, DL, VT: TotalVT, N1: Lo, N2: Hi);
232 }
233 } else if (PartVT.isFloatingPoint()) {
234 // FP split into multiple FP parts (for ppcf128)
235 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
236 "Unexpected split");
237 SDValue Lo, Hi;
238 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: EVT(MVT::f64), Operand: Parts[0]);
239 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: EVT(MVT::f64), Operand: Parts[1]);
240 if (TLI.hasBigEndianPartOrdering(VT: ValueVT, DL: DAG.getDataLayout()))
241 std::swap(a&: Lo, b&: Hi);
242 Val = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL, VT: ValueVT, N1: Lo, N2: Hi);
243 } else {
244 // FP split into integer parts (soft fp)
245 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
246 !PartVT.isVector() && "Unexpected split");
247 EVT IntVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueVT.getSizeInBits());
248 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, ValueVT: IntVT, V,
249 InChain, CC);
250 }
251 }
252
253 // There is now one part, held in Val. Correct it to match ValueVT.
254 // PartEVT is the type of the register class that holds the value.
255 // ValueVT is the type of the inline asm operation.
256 EVT PartEVT = Val.getValueType();
257
258 if (PartEVT == ValueVT)
259 return Val;
260
261 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
262 ValueVT.bitsLT(VT: PartEVT)) {
263 // For an FP value in an integer part, we need to truncate to the right
264 // width first.
265 PartEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueVT.getSizeInBits());
266 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: PartEVT, Operand: Val);
267 }
268
269 // Handle types that have the same size.
270 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
271 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
272
273 // Handle types with different sizes.
274 if (PartEVT.isInteger() && ValueVT.isInteger()) {
275 if (ValueVT.bitsLT(VT: PartEVT)) {
276 // For a truncate, see if we have any information to
277 // indicate whether the truncated bits will always be
278 // zero or sign-extension.
279 if (AssertOp)
280 Val = DAG.getNode(Opcode: *AssertOp, DL, VT: PartEVT, N1: Val,
281 N2: DAG.getValueType(ValueVT));
282 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValueVT, Operand: Val);
283 }
284 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValueVT, Operand: Val);
285 }
286
287 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
288 // FP_ROUND's are always exact here.
289 if (ValueVT.bitsLT(VT: Val.getValueType())) {
290
291 SDValue NoChange =
292 DAG.getTargetConstant(Val: 1, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
293
294 if (DAG.getMachineFunction().getFunction().getAttributes().hasFnAttr(
295 Kind: llvm::Attribute::StrictFP)) {
296 return DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL,
297 VTList: DAG.getVTList(VT1: ValueVT, VT2: MVT::Other), N1: InChain, N2: Val,
298 N3: NoChange);
299 }
300
301 return DAG.getNode(Opcode: ISD::FP_ROUND, DL, VT: ValueVT, N1: Val, N2: NoChange);
302 }
303
304 return DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: ValueVT, Operand: Val);
305 }
306
307 // Handle MMX to a narrower integer type by bitcasting MMX to integer and
308 // then truncating.
309 if (PartEVT == MVT::x86mmx && ValueVT.isInteger() &&
310 ValueVT.bitsLT(VT: PartEVT)) {
311 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::i64, Operand: Val);
312 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValueVT, Operand: Val);
313 }
314
315 report_fatal_error(reason: "Unknown mismatch in getCopyFromParts!");
316}
317
318static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
319 const Twine &ErrMsg) {
320 const Instruction *I = dyn_cast_or_null<Instruction>(Val: V);
321 if (!I)
322 return Ctx.emitError(ErrorStr: ErrMsg);
323
324 if (const CallInst *CI = dyn_cast<CallInst>(Val: I))
325 if (CI->isInlineAsm()) {
326 return Ctx.diagnose(DI: DiagnosticInfoInlineAsm(
327 *CI, ErrMsg + ", possible invalid constraint for vector type"));
328 }
329
330 return Ctx.emitError(I, ErrorStr: ErrMsg);
331}
332
333/// getCopyFromPartsVector - Create a value that contains the specified legal
334/// parts combined into the value they represent. If the parts combine to a
335/// type larger than ValueVT then AssertOp can be used to specify whether the
336/// extra bits are known to be zero (ISD::AssertZext) or sign extended from
337/// ValueVT (ISD::AssertSext).
338static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
339 const SDValue *Parts, unsigned NumParts,
340 MVT PartVT, EVT ValueVT, const Value *V,
341 SDValue InChain,
342 std::optional<CallingConv::ID> CallConv) {
343 assert(ValueVT.isVector() && "Not a vector value");
344 assert(NumParts > 0 && "No parts to assemble!");
345 const bool IsABIRegCopy = CallConv.has_value();
346
347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
348 SDValue Val = Parts[0];
349
350 // Handle a multi-element vector.
351 if (NumParts > 1) {
352 EVT IntermediateVT;
353 MVT RegisterVT;
354 unsigned NumIntermediates;
355 unsigned NumRegs;
356
357 if (IsABIRegCopy) {
358 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
359 Context&: *DAG.getContext(), CC: *CallConv, VT: ValueVT, IntermediateVT,
360 NumIntermediates, RegisterVT);
361 } else {
362 NumRegs =
363 TLI.getVectorTypeBreakdown(Context&: *DAG.getContext(), VT: ValueVT, IntermediateVT,
364 NumIntermediates, RegisterVT);
365 }
366
367 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
368 NumParts = NumRegs; // Silence a compiler warning.
369 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
370 assert(RegisterVT.getSizeInBits() ==
371 Parts[0].getSimpleValueType().getSizeInBits() &&
372 "Part type sizes don't match!");
373
374 // Assemble the parts into intermediate operands.
375 SmallVector<SDValue, 8> Ops(NumIntermediates);
376 if (NumIntermediates == NumParts) {
377 // If the register was not expanded, truncate or copy the value,
378 // as appropriate.
379 for (unsigned i = 0; i != NumParts; ++i)
380 Ops[i] = getCopyFromParts(DAG, DL, Parts: &Parts[i], NumParts: 1, PartVT, ValueVT: IntermediateVT,
381 V, InChain, CC: CallConv);
382 } else if (NumParts > 0) {
383 // If the intermediate type was expanded, build the intermediate
384 // operands from the parts.
385 assert(NumParts % NumIntermediates == 0 &&
386 "Must expand into a divisible number of parts!");
387 unsigned Factor = NumParts / NumIntermediates;
388 for (unsigned i = 0; i != NumIntermediates; ++i)
389 Ops[i] = getCopyFromParts(DAG, DL, Parts: &Parts[i * Factor], NumParts: Factor, PartVT,
390 ValueVT: IntermediateVT, V, InChain, CC: CallConv);
391 }
392
393 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
394 // intermediate operands.
395 EVT BuiltVectorTy =
396 IntermediateVT.isVector()
397 ? EVT::getVectorVT(
398 Context&: *DAG.getContext(), VT: IntermediateVT.getScalarType(),
399 EC: IntermediateVT.getVectorElementCount() * NumParts)
400 : EVT::getVectorVT(Context&: *DAG.getContext(),
401 VT: IntermediateVT.getScalarType(),
402 NumElements: NumIntermediates);
403 Val = DAG.getNode(Opcode: IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
404 : ISD::BUILD_VECTOR,
405 DL, VT: BuiltVectorTy, Ops);
406 }
407
408 // There is now one part, held in Val. Correct it to match ValueVT.
409 EVT PartEVT = Val.getValueType();
410
411 if (PartEVT == ValueVT)
412 return Val;
413
414 if (PartEVT.isVector()) {
415 // Vector/Vector bitcast.
416 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
417 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
418
419 // If the parts vector has more elements than the value vector, then we
420 // have a vector widening case (e.g. <2 x float> -> <4 x float>).
421 // Extract the elements we want.
422 if (PartEVT.getVectorElementCount() != ValueVT.getVectorElementCount()) {
423 assert((PartEVT.getVectorElementCount().getKnownMinValue() >
424 ValueVT.getVectorElementCount().getKnownMinValue()) &&
425 (PartEVT.getVectorElementCount().isScalable() ==
426 ValueVT.getVectorElementCount().isScalable()) &&
427 "Cannot narrow, it would be a lossy transformation");
428 PartEVT =
429 EVT::getVectorVT(Context&: *DAG.getContext(), VT: PartEVT.getVectorElementType(),
430 EC: ValueVT.getVectorElementCount());
431 Val = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT: PartEVT, N1: Val,
432 N2: DAG.getVectorIdxConstant(Val: 0, DL));
433 if (PartEVT == ValueVT)
434 return Val;
435 if (PartEVT.isInteger() && ValueVT.isFloatingPoint())
436 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
437
438 // Vector/Vector bitcast (e.g. <2 x bfloat> -> <2 x half>).
439 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
440 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
441 }
442
443 // Promoted vector extract
444 return DAG.getAnyExtOrTrunc(Op: Val, DL, VT: ValueVT);
445 }
446
447 // Trivial bitcast if the types are the same size and the destination
448 // vector type is legal.
449 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
450 TLI.isTypeLegal(VT: ValueVT))
451 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
452
453 if (ValueVT.getVectorNumElements() != 1) {
454 // Certain ABIs require that vectors are passed as integers. For vectors
455 // are the same size, this is an obvious bitcast.
456 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) {
457 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
458 } else if (ValueVT.bitsLT(VT: PartEVT)) {
459 const uint64_t ValueSize = ValueVT.getFixedSizeInBits();
460 EVT IntermediateType = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueSize);
461 // Drop the extra bits.
462 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: IntermediateType, Operand: Val);
463 return DAG.getBitcast(VT: ValueVT, V: Val);
464 }
465
466 diagnosePossiblyInvalidConstraint(
467 Ctx&: *DAG.getContext(), V, ErrMsg: "non-trivial scalar-to-vector conversion");
468 return DAG.getUNDEF(VT: ValueVT);
469 }
470
471 // Handle cases such as i8 -> <1 x i1>
472 EVT ValueSVT = ValueVT.getVectorElementType();
473 if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) {
474 unsigned ValueSize = ValueSVT.getSizeInBits();
475 if (ValueSize == PartEVT.getSizeInBits()) {
476 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueSVT, Operand: Val);
477 } else if (ValueSVT.isFloatingPoint() && PartEVT.isInteger()) {
478 // It's possible a scalar floating point type gets softened to integer and
479 // then promoted to a larger integer. If PartEVT is the larger integer
480 // we need to truncate it and then bitcast to the FP type.
481 assert(ValueSVT.bitsLT(PartEVT) && "Unexpected types");
482 EVT IntermediateType = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueSize);
483 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: IntermediateType, Operand: Val);
484 Val = DAG.getBitcast(VT: ValueSVT, V: Val);
485 } else {
486 Val = ValueVT.isFloatingPoint()
487 ? DAG.getFPExtendOrRound(Op: Val, DL, VT: ValueSVT)
488 : DAG.getAnyExtOrTrunc(Op: Val, DL, VT: ValueSVT);
489 }
490 }
491
492 return DAG.getBuildVector(VT: ValueVT, DL, Ops: Val);
493}
494
495static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
496 SDValue Val, SDValue *Parts, unsigned NumParts,
497 MVT PartVT, const Value *V,
498 std::optional<CallingConv::ID> CallConv);
499
500/// getCopyToParts - Create a series of nodes that contain the specified value
501/// split into legal parts. If the parts contain more bits than Val, then, for
502/// integers, ExtendKind can be used to specify how to generate the extra bits.
503static void
504getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
505 unsigned NumParts, MVT PartVT, const Value *V,
506 std::optional<CallingConv::ID> CallConv = std::nullopt,
507 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
508 // Let the target split the parts if it wants to
509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
510 if (TLI.splitValueIntoRegisterParts(DAG, DL, Val, Parts, NumParts, PartVT,
511 CC: CallConv))
512 return;
513 EVT ValueVT = Val.getValueType();
514
515 // Handle the vector case separately.
516 if (ValueVT.isVector())
517 return getCopyToPartsVector(DAG, dl: DL, Val, Parts, NumParts, PartVT, V,
518 CallConv);
519
520 unsigned OrigNumParts = NumParts;
521 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
522 "Copying to an illegal type!");
523
524 if (NumParts == 0)
525 return;
526
527 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
528 EVT PartEVT = PartVT;
529 if (PartEVT == ValueVT) {
530 assert(NumParts == 1 && "No-op copy with multiple parts!");
531 Parts[0] = Val;
532 return;
533 }
534
535 unsigned PartBits = PartVT.getSizeInBits();
536 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
537 // If the parts cover more bits than the value has, promote the value.
538 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
539 assert(NumParts == 1 && "Do not know what to promote to!");
540 Val = DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: PartVT, Operand: Val);
541 } else {
542 if (ValueVT.isFloatingPoint()) {
543 // FP values need to be bitcast, then extended if they are being put
544 // into a larger container.
545 ValueVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueVT.getSizeInBits());
546 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
547 }
548 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
549 ValueVT.isInteger() &&
550 "Unknown mismatch!");
551 ValueVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumParts * PartBits);
552 Val = DAG.getNode(Opcode: ExtendKind, DL, VT: ValueVT, Operand: Val);
553 if (PartVT == MVT::x86mmx)
554 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
555 }
556 } else if (PartBits == ValueVT.getSizeInBits()) {
557 // Different types of the same size.
558 assert(NumParts == 1 && PartEVT != ValueVT);
559 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
560 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
561 // If the parts cover less bits than value has, truncate the value.
562 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
563 ValueVT.isInteger() &&
564 "Unknown mismatch!");
565 ValueVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumParts * PartBits);
566 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValueVT, Operand: Val);
567 if (PartVT == MVT::x86mmx)
568 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
569 }
570
571 // The value may have changed - recompute ValueVT.
572 ValueVT = Val.getValueType();
573 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
574 "Failed to tile the value with PartVT!");
575
576 if (NumParts == 1) {
577 if (PartEVT != ValueVT) {
578 diagnosePossiblyInvalidConstraint(Ctx&: *DAG.getContext(), V,
579 ErrMsg: "scalar-to-vector conversion failed");
580 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
581 }
582
583 Parts[0] = Val;
584 return;
585 }
586
587 // Expand the value into multiple parts.
588 if (NumParts & (NumParts - 1)) {
589 // The number of parts is not a power of 2. Split off and copy the tail.
590 assert(PartVT.isInteger() && ValueVT.isInteger() &&
591 "Do not know what to expand to!");
592 unsigned RoundParts = llvm::bit_floor(Value: NumParts);
593 unsigned RoundBits = RoundParts * PartBits;
594 unsigned OddParts = NumParts - RoundParts;
595 SDValue OddVal = DAG.getNode(Opcode: ISD::SRL, DL, VT: ValueVT, N1: Val,
596 N2: DAG.getShiftAmountConstant(Val: RoundBits, VT: ValueVT, DL));
597
598 getCopyToParts(DAG, DL, Val: OddVal, Parts: Parts + RoundParts, NumParts: OddParts, PartVT, V,
599 CallConv);
600
601 if (DAG.getDataLayout().isBigEndian())
602 // The odd parts were reversed by getCopyToParts - unreverse them.
603 std::reverse(first: Parts + RoundParts, last: Parts + NumParts);
604
605 NumParts = RoundParts;
606 ValueVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumParts * PartBits);
607 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValueVT, Operand: Val);
608 }
609
610 // The number of parts is a power of 2. Repeatedly bisect the value using
611 // EXTRACT_ELEMENT.
612 Parts[0] = DAG.getNode(Opcode: ISD::BITCAST, DL,
613 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
614 BitWidth: ValueVT.getSizeInBits()),
615 Operand: Val);
616
617 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
618 for (unsigned i = 0; i < NumParts; i += StepSize) {
619 unsigned ThisBits = StepSize * PartBits / 2;
620 EVT ThisVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ThisBits);
621 SDValue &Part0 = Parts[i];
622 SDValue &Part1 = Parts[i+StepSize/2];
623
624 Part1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL,
625 VT: ThisVT, N1: Part0, N2: DAG.getIntPtrConstant(Val: 1, DL));
626 Part0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL,
627 VT: ThisVT, N1: Part0, N2: DAG.getIntPtrConstant(Val: 0, DL));
628
629 if (ThisBits == PartBits && ThisVT != PartVT) {
630 Part0 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Part0);
631 Part1 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Part1);
632 }
633 }
634 }
635
636 if (DAG.getDataLayout().isBigEndian())
637 std::reverse(first: Parts, last: Parts + OrigNumParts);
638}
639
640static SDValue widenVectorToPartType(SelectionDAG &DAG, SDValue Val,
641 const SDLoc &DL, EVT PartVT) {
642 if (!PartVT.isVector())
643 return SDValue();
644
645 EVT ValueVT = Val.getValueType();
646 EVT PartEVT = PartVT.getVectorElementType();
647 EVT ValueEVT = ValueVT.getVectorElementType();
648 ElementCount PartNumElts = PartVT.getVectorElementCount();
649 ElementCount ValueNumElts = ValueVT.getVectorElementCount();
650
651 // We only support widening vectors with equivalent element types and
652 // fixed/scalable properties. If a target needs to widen a fixed-length type
653 // to a scalable one, it should be possible to use INSERT_SUBVECTOR below.
654 if (ElementCount::isKnownLE(LHS: PartNumElts, RHS: ValueNumElts) ||
655 PartNumElts.isScalable() != ValueNumElts.isScalable())
656 return SDValue();
657
658 // Have a try for bf16 because some targets share its ABI with fp16.
659 if (ValueEVT == MVT::bf16 && PartEVT == MVT::f16) {
660 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
661 "Cannot widen to illegal type");
662 Val = DAG.getNode(
663 Opcode: ISD::BITCAST, DL,
664 VT: ValueVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MVT::f16), Operand: Val);
665 } else if (PartEVT != ValueEVT) {
666 return SDValue();
667 }
668
669 // Widening a scalable vector to another scalable vector is done by inserting
670 // the vector into a larger undef one.
671 if (PartNumElts.isScalable())
672 return DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL, VT: PartVT, N1: DAG.getUNDEF(VT: PartVT),
673 N2: Val, N3: DAG.getVectorIdxConstant(Val: 0, DL));
674
675 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
676 // undef elements.
677 SmallVector<SDValue, 16> Ops;
678 DAG.ExtractVectorElements(Op: Val, Args&: Ops);
679 SDValue EltUndef = DAG.getUNDEF(VT: PartEVT);
680 Ops.append(NumInputs: (PartNumElts - ValueNumElts).getFixedValue(), Elt: EltUndef);
681
682 // FIXME: Use CONCAT for 2x -> 4x.
683 return DAG.getBuildVector(VT: PartVT, DL, Ops);
684}
685
686/// getCopyToPartsVector - Create a series of nodes that contain the specified
687/// value split into legal parts.
688static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
689 SDValue Val, SDValue *Parts, unsigned NumParts,
690 MVT PartVT, const Value *V,
691 std::optional<CallingConv::ID> CallConv) {
692 EVT ValueVT = Val.getValueType();
693 assert(ValueVT.isVector() && "Not a vector");
694 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
695 const bool IsABIRegCopy = CallConv.has_value();
696
697 if (NumParts == 1) {
698 EVT PartEVT = PartVT;
699 if (PartEVT == ValueVT) {
700 // Nothing to do.
701 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
702 // Bitconvert vector->vector case.
703 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
704 } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) {
705 Val = Widened;
706 } else if (PartVT.isVector() &&
707 PartEVT.getVectorElementType().bitsGE(
708 VT: ValueVT.getVectorElementType()) &&
709 PartEVT.getVectorElementCount() ==
710 ValueVT.getVectorElementCount()) {
711
712 // Promoted vector extract
713 Val = DAG.getAnyExtOrTrunc(Op: Val, DL, VT: PartVT);
714 } else if (PartEVT.isVector() &&
715 PartEVT.getVectorElementType() !=
716 ValueVT.getVectorElementType() &&
717 TLI.getTypeAction(Context&: *DAG.getContext(), VT: ValueVT) ==
718 TargetLowering::TypeWidenVector) {
719 // Combination of widening and promotion.
720 EVT WidenVT =
721 EVT::getVectorVT(Context&: *DAG.getContext(), VT: ValueVT.getVectorElementType(),
722 EC: PartVT.getVectorElementCount());
723 SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT: WidenVT);
724 Val = DAG.getAnyExtOrTrunc(Op: Widened, DL, VT: PartVT);
725 } else {
726 // Don't extract an integer from a float vector. This can happen if the
727 // FP type gets softened to integer and then promoted. The promotion
728 // prevents it from being picked up by the earlier bitcast case.
729 if (ValueVT.getVectorElementCount().isScalar() &&
730 (!ValueVT.isFloatingPoint() || !PartVT.isInteger())) {
731 // If we reach this condition and PartVT is FP, this means that
732 // ValueVT is also FP and both have a different size, otherwise we
733 // would have bitcasted them. Producing an EXTRACT_VECTOR_ELT here
734 // would be invalid since that would mean the smaller FP type has to
735 // be extended to the larger one.
736 if (PartVT.isFloatingPoint()) {
737 Val = DAG.getBitcast(VT: ValueVT.getScalarType(), V: Val);
738 Val = DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: PartVT, Operand: Val);
739 } else
740 Val = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: PartVT, N1: Val,
741 N2: DAG.getVectorIdxConstant(Val: 0, DL));
742 } else {
743 uint64_t ValueSize = ValueVT.getFixedSizeInBits();
744 assert(PartVT.getFixedSizeInBits() > ValueSize &&
745 "lossy conversion of vector to scalar type");
746 EVT IntermediateType = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueSize);
747 Val = DAG.getBitcast(VT: IntermediateType, V: Val);
748 Val = DAG.getAnyExtOrTrunc(Op: Val, DL, VT: PartVT);
749 }
750 }
751
752 assert(Val.getValueType() == PartVT && "Unexpected vector part value type");
753 Parts[0] = Val;
754 return;
755 }
756
757 // Handle a multi-element vector.
758 EVT IntermediateVT;
759 MVT RegisterVT;
760 unsigned NumIntermediates;
761 unsigned NumRegs;
762 if (IsABIRegCopy) {
763 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
764 Context&: *DAG.getContext(), CC: *CallConv, VT: ValueVT, IntermediateVT, NumIntermediates,
765 RegisterVT);
766 } else {
767 NumRegs =
768 TLI.getVectorTypeBreakdown(Context&: *DAG.getContext(), VT: ValueVT, IntermediateVT,
769 NumIntermediates, RegisterVT);
770 }
771
772 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
773 NumParts = NumRegs; // Silence a compiler warning.
774 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
775
776 assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() &&
777 "Mixing scalable and fixed vectors when copying in parts");
778
779 std::optional<ElementCount> DestEltCnt;
780
781 if (IntermediateVT.isVector())
782 DestEltCnt = IntermediateVT.getVectorElementCount() * NumIntermediates;
783 else
784 DestEltCnt = ElementCount::getFixed(MinVal: NumIntermediates);
785
786 EVT BuiltVectorTy = EVT::getVectorVT(
787 Context&: *DAG.getContext(), VT: IntermediateVT.getScalarType(), EC: *DestEltCnt);
788
789 if (ValueVT == BuiltVectorTy) {
790 // Nothing to do.
791 } else if (ValueVT.getSizeInBits() == BuiltVectorTy.getSizeInBits()) {
792 // Bitconvert vector->vector case.
793 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: BuiltVectorTy, Operand: Val);
794 } else {
795 if (BuiltVectorTy.getVectorElementType().bitsGT(
796 VT: ValueVT.getVectorElementType())) {
797 // Integer promotion.
798 ValueVT = EVT::getVectorVT(Context&: *DAG.getContext(),
799 VT: BuiltVectorTy.getVectorElementType(),
800 EC: ValueVT.getVectorElementCount());
801 Val = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValueVT, Operand: Val);
802 }
803
804 if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT: BuiltVectorTy)) {
805 Val = Widened;
806 }
807 }
808
809 assert(Val.getValueType() == BuiltVectorTy && "Unexpected vector value type");
810
811 // Split the vector into intermediate operands.
812 SmallVector<SDValue, 8> Ops(NumIntermediates);
813 for (unsigned i = 0; i != NumIntermediates; ++i) {
814 if (IntermediateVT.isVector()) {
815 // This does something sensible for scalable vectors - see the
816 // definition of EXTRACT_SUBVECTOR for further details.
817 unsigned IntermediateNumElts = IntermediateVT.getVectorMinNumElements();
818 Ops[i] =
819 DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT: IntermediateVT, N1: Val,
820 N2: DAG.getVectorIdxConstant(Val: i * IntermediateNumElts, DL));
821 } else {
822 Ops[i] = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: IntermediateVT, N1: Val,
823 N2: DAG.getVectorIdxConstant(Val: i, DL));
824 }
825 }
826
827 // Split the intermediate operands into legal parts.
828 if (NumParts == NumIntermediates) {
829 // If the register was not expanded, promote or copy the value,
830 // as appropriate.
831 for (unsigned i = 0; i != NumParts; ++i)
832 getCopyToParts(DAG, DL, Val: Ops[i], Parts: &Parts[i], NumParts: 1, PartVT, V, CallConv);
833 } else if (NumParts > 0) {
834 // If the intermediate type was expanded, split each the value into
835 // legal parts.
836 assert(NumIntermediates != 0 && "division by zero");
837 assert(NumParts % NumIntermediates == 0 &&
838 "Must expand into a divisible number of parts!");
839 unsigned Factor = NumParts / NumIntermediates;
840 for (unsigned i = 0; i != NumIntermediates; ++i)
841 getCopyToParts(DAG, DL, Val: Ops[i], Parts: &Parts[i * Factor], NumParts: Factor, PartVT, V,
842 CallConv);
843 }
844}
845
846static void failForInvalidBundles(const CallBase &I, StringRef Name,
847 ArrayRef<uint32_t> AllowedBundles) {
848 if (I.hasOperandBundlesOtherThan(IDs: AllowedBundles)) {
849 ListSeparator LS;
850 std::string Error;
851 raw_string_ostream OS(Error);
852 for (unsigned i = 0, e = I.getNumOperandBundles(); i != e; ++i) {
853 OperandBundleUse U = I.getOperandBundleAt(Index: i);
854 if (!is_contained(Range&: AllowedBundles, Element: U.getTagID()))
855 OS << LS << U.getTagName();
856 }
857 reportFatalUsageError(
858 reason: Twine("cannot lower ", Name)
859 .concat(Suffix: Twine(" with arbitrary operand bundles: ", Error)));
860 }
861}
862
863RegsForValue::RegsForValue(const SmallVector<Register, 4> &regs, MVT regvt,
864 EVT valuevt, std::optional<CallingConv::ID> CC)
865 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
866 RegCount(1, regs.size()), CallConv(CC) {}
867
868RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
869 const DataLayout &DL, Register Reg, Type *Ty,
870 std::optional<CallingConv::ID> CC) {
871 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
872
873 CallConv = CC;
874
875 for (EVT ValueVT : ValueVTs) {
876 unsigned NumRegs =
877 isABIMangled()
878 ? TLI.getNumRegistersForCallingConv(Context, CC: *CC, VT: ValueVT)
879 : TLI.getNumRegisters(Context, VT: ValueVT);
880 MVT RegisterVT =
881 isABIMangled()
882 ? TLI.getRegisterTypeForCallingConv(Context, CC: *CC, VT: ValueVT)
883 : TLI.getRegisterType(Context, VT: ValueVT);
884 for (unsigned i = 0; i != NumRegs; ++i)
885 Regs.push_back(Elt: Reg + i);
886 RegVTs.push_back(Elt: RegisterVT);
887 RegCount.push_back(Elt: NumRegs);
888 Reg = Reg.id() + NumRegs;
889 }
890}
891
892SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
893 FunctionLoweringInfo &FuncInfo,
894 const SDLoc &dl, SDValue &Chain,
895 SDValue *Glue, const Value *V) const {
896 // A Value with type {} or [0 x %t] needs no registers.
897 if (ValueVTs.empty())
898 return SDValue();
899
900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
901
902 // Assemble the legal parts into the final values.
903 SmallVector<SDValue, 4> Values(ValueVTs.size());
904 SmallVector<SDValue, 8> Parts;
905 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
906 // Copy the legal parts from the registers.
907 EVT ValueVT = ValueVTs[Value];
908 unsigned NumRegs = RegCount[Value];
909 MVT RegisterVT = isABIMangled()
910 ? TLI.getRegisterTypeForCallingConv(
911 Context&: *DAG.getContext(), CC: *CallConv, VT: RegVTs[Value])
912 : RegVTs[Value];
913
914 Parts.resize(N: NumRegs);
915 for (unsigned i = 0; i != NumRegs; ++i) {
916 SDValue P;
917 if (!Glue) {
918 P = DAG.getCopyFromReg(Chain, dl, Reg: Regs[Part+i], VT: RegisterVT);
919 } else {
920 P = DAG.getCopyFromReg(Chain, dl, Reg: Regs[Part+i], VT: RegisterVT, Glue: *Glue);
921 *Glue = P.getValue(R: 2);
922 }
923
924 Chain = P.getValue(R: 1);
925 Parts[i] = P;
926
927 // If the source register was virtual and if we know something about it,
928 // add an assert node.
929 if (!Regs[Part + i].isVirtual() || !RegisterVT.isInteger())
930 continue;
931
932 const FunctionLoweringInfo::LiveOutInfo *LOI =
933 FuncInfo.GetLiveOutRegInfo(Reg: Regs[Part+i]);
934 if (!LOI)
935 continue;
936
937 unsigned RegSize = RegisterVT.getScalarSizeInBits();
938 unsigned NumSignBits = LOI->NumSignBits;
939 unsigned NumZeroBits = LOI->Known.countMinLeadingZeros();
940
941 if (NumZeroBits == RegSize) {
942 // The current value is a zero.
943 // Explicitly express that as it would be easier for
944 // optimizations to kick in.
945 Parts[i] = DAG.getConstant(Val: 0, DL: dl, VT: RegisterVT);
946 continue;
947 }
948
949 // FIXME: We capture more information than the dag can represent. For
950 // now, just use the tightest assertzext/assertsext possible.
951 bool isSExt;
952 EVT FromVT(MVT::Other);
953 if (NumZeroBits) {
954 FromVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RegSize - NumZeroBits);
955 isSExt = false;
956 } else if (NumSignBits > 1) {
957 FromVT =
958 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RegSize - NumSignBits + 1);
959 isSExt = true;
960 } else {
961 continue;
962 }
963 // Add an assertion node.
964 assert(FromVT != MVT::Other);
965 Parts[i] = DAG.getNode(Opcode: isSExt ? ISD::AssertSext : ISD::AssertZext, DL: dl,
966 VT: RegisterVT, N1: P, N2: DAG.getValueType(FromVT));
967 }
968
969 Values[Value] = getCopyFromParts(DAG, DL: dl, Parts: Parts.begin(), NumParts: NumRegs,
970 PartVT: RegisterVT, ValueVT, V, InChain: Chain, CC: CallConv);
971 Part += NumRegs;
972 Parts.clear();
973 }
974
975 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: dl, VTList: DAG.getVTList(VTs: ValueVTs), Ops: Values);
976}
977
978void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
979 const SDLoc &dl, SDValue &Chain, SDValue *Glue,
980 const Value *V,
981 ISD::NodeType PreferredExtendType) const {
982 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
983 ISD::NodeType ExtendKind = PreferredExtendType;
984
985 // Get the list of the values's legal parts.
986 unsigned NumRegs = Regs.size();
987 SmallVector<SDValue, 8> Parts(NumRegs);
988 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
989 unsigned NumParts = RegCount[Value];
990
991 MVT RegisterVT = isABIMangled()
992 ? TLI.getRegisterTypeForCallingConv(
993 Context&: *DAG.getContext(), CC: *CallConv, VT: RegVTs[Value])
994 : RegVTs[Value];
995
996 if (ExtendKind == ISD::ANY_EXTEND)
997 if (TLI.isZExtFree(Val: peekThroughFreeze(V: Val), VT2: RegisterVT))
998 ExtendKind = ISD::ZERO_EXTEND;
999
1000 getCopyToParts(DAG, DL: dl, Val: Val.getValue(R: Val.getResNo() + Value), Parts: &Parts[Part],
1001 NumParts, PartVT: RegisterVT, V, CallConv, ExtendKind);
1002 Part += NumParts;
1003 }
1004
1005 // Copy the parts into the registers.
1006 SmallVector<SDValue, 8> Chains(NumRegs);
1007 for (unsigned i = 0; i != NumRegs; ++i) {
1008 SDValue Part;
1009 if (!Glue) {
1010 Part = DAG.getCopyToReg(Chain, dl, Reg: Regs[i], N: Parts[i]);
1011 } else {
1012 Part = DAG.getCopyToReg(Chain, dl, Reg: Regs[i], N: Parts[i], Glue: *Glue);
1013 *Glue = Part.getValue(R: 1);
1014 }
1015
1016 Chains[i] = Part.getValue(R: 0);
1017 }
1018
1019 if (NumRegs == 1 || Glue)
1020 // If NumRegs > 1 && Glue is used then the use of the last CopyToReg is
1021 // flagged to it. That is the CopyToReg nodes and the user are considered
1022 // a single scheduling unit. If we create a TokenFactor and return it as
1023 // chain, then the TokenFactor is both a predecessor (operand) of the
1024 // user as well as a successor (the TF operands are flagged to the user).
1025 // c1, f1 = CopyToReg
1026 // c2, f2 = CopyToReg
1027 // c3 = TokenFactor c1, c2
1028 // ...
1029 // = op c3, ..., f2
1030 Chain = Chains[NumRegs-1];
1031 else
1032 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: Chains);
1033}
1034
1035void RegsForValue::AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
1036 unsigned MatchingIdx, const SDLoc &dl,
1037 SelectionDAG &DAG,
1038 std::vector<SDValue> &Ops) const {
1039 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1040
1041 InlineAsm::Flag Flag(Code, Regs.size());
1042 if (HasMatching)
1043 Flag.setMatchingOp(MatchingIdx);
1044 else if (!Regs.empty() && Regs.front().isVirtual()) {
1045 // Put the register class of the virtual registers in the flag word. That
1046 // way, later passes can recompute register class constraints for inline
1047 // assembly as well as normal instructions.
1048 // Don't do this for tied operands that can use the regclass information
1049 // from the def.
1050 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1051 const TargetRegisterClass *RC = MRI.getRegClass(Reg: Regs.front());
1052 Flag.setRegClass(RC->getID());
1053 }
1054
1055 SDValue Res = DAG.getTargetConstant(Val: Flag, DL: dl, VT: MVT::i32);
1056 Ops.push_back(x: Res);
1057
1058 if (Code == InlineAsm::Kind::Clobber) {
1059 // Clobbers should always have a 1:1 mapping with registers, and may
1060 // reference registers that have illegal (e.g. vector) types. Hence, we
1061 // shouldn't try to apply any sort of splitting logic to them.
1062 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&
1063 "No 1:1 mapping from clobbers to regs?");
1064 Register SP = TLI.getStackPointerRegisterToSaveRestore();
1065 (void)SP;
1066 for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) {
1067 Ops.push_back(x: DAG.getRegister(Reg: Regs[I], VT: RegVTs[I]));
1068 assert(
1069 (Regs[I] != SP ||
1070 DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) &&
1071 "If we clobbered the stack pointer, MFI should know about it.");
1072 }
1073 return;
1074 }
1075
1076 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
1077 MVT RegisterVT = RegVTs[Value];
1078 unsigned NumRegs = TLI.getNumRegisters(Context&: *DAG.getContext(), VT: ValueVTs[Value],
1079 RegisterVT);
1080 for (unsigned i = 0; i != NumRegs; ++i) {
1081 assert(Reg < Regs.size() && "Mismatch in # registers expected");
1082 Register TheReg = Regs[Reg++];
1083 Ops.push_back(x: DAG.getRegister(Reg: TheReg, VT: RegisterVT));
1084 }
1085 }
1086}
1087
1088SmallVector<std::pair<Register, TypeSize>, 4>
1089RegsForValue::getRegsAndSizes() const {
1090 SmallVector<std::pair<Register, TypeSize>, 4> OutVec;
1091 unsigned I = 0;
1092 for (auto CountAndVT : zip_first(t: RegCount, u: RegVTs)) {
1093 unsigned RegCount = std::get<0>(t&: CountAndVT);
1094 MVT RegisterVT = std::get<1>(t&: CountAndVT);
1095 TypeSize RegisterSize = RegisterVT.getSizeInBits();
1096 for (unsigned E = I + RegCount; I != E; ++I)
1097 OutVec.push_back(Elt: std::make_pair(x: Regs[I], y&: RegisterSize));
1098 }
1099 return OutVec;
1100}
1101
1102void SelectionDAGBuilder::init(GCFunctionInfo *gfi, BatchAAResults *aa,
1103 AssumptionCache *ac, const TargetLibraryInfo *li,
1104 const TargetTransformInfo &TTI) {
1105 BatchAA = aa;
1106 AC = ac;
1107 GFI = gfi;
1108 LibInfo = li;
1109 Context = DAG.getContext();
1110 LPadToCallSiteMap.clear();
1111 this->TTI = &TTI;
1112 SL->init(tli: DAG.getTargetLoweringInfo(), tm: TM, dl: DAG.getDataLayout());
1113 AssignmentTrackingEnabled = isAssignmentTrackingEnabled(
1114 M: *DAG.getMachineFunction().getFunction().getParent());
1115}
1116
1117void SelectionDAGBuilder::clear() {
1118 NodeMap.clear();
1119 UnusedArgNodeMap.clear();
1120 PendingLoads.clear();
1121 PendingExports.clear();
1122 PendingConstrainedFP.clear();
1123 PendingConstrainedFPStrict.clear();
1124 CurInst = nullptr;
1125 HasTailCall = false;
1126 SDNodeOrder = LowestSDNodeOrder;
1127 StatepointLowering.clear();
1128}
1129
1130void SelectionDAGBuilder::clearDanglingDebugInfo() {
1131 DanglingDebugInfoMap.clear();
1132}
1133
1134// Update DAG root to include dependencies on Pending chains.
1135SDValue SelectionDAGBuilder::updateRoot(SmallVectorImpl<SDValue> &Pending) {
1136 SDValue Root = DAG.getRoot();
1137
1138 if (Pending.empty())
1139 return Root;
1140
1141 // Add current root to PendingChains, unless we already indirectly
1142 // depend on it.
1143 if (Root.getOpcode() != ISD::EntryToken) {
1144 unsigned i = 0, e = Pending.size();
1145 for (; i != e; ++i) {
1146 assert(Pending[i].getNode()->getNumOperands() > 1);
1147 if (Pending[i].getNode()->getOperand(Num: 0) == Root)
1148 break; // Don't add the root if we already indirectly depend on it.
1149 }
1150
1151 if (i == e)
1152 Pending.push_back(Elt: Root);
1153 }
1154
1155 if (Pending.size() == 1)
1156 Root = Pending[0];
1157 else
1158 Root = DAG.getTokenFactor(DL: getCurSDLoc(), Vals&: Pending);
1159
1160 DAG.setRoot(Root);
1161 Pending.clear();
1162 return Root;
1163}
1164
1165SDValue SelectionDAGBuilder::getMemoryRoot() {
1166 return updateRoot(Pending&: PendingLoads);
1167}
1168
1169SDValue SelectionDAGBuilder::getFPOperationRoot(fp::ExceptionBehavior EB) {
1170 // If the new exception behavior differs from that of the pending
1171 // ones, chain up them and update the root.
1172 switch (EB) {
1173 case fp::ExceptionBehavior::ebMayTrap:
1174 case fp::ExceptionBehavior::ebIgnore:
1175 // Floating-point exceptions produced by such operations are not intended
1176 // to be observed, so the sequence of these operations does not need to be
1177 // preserved.
1178 //
1179 // They however must not be mixed with the instructions that have strict
1180 // exception behavior. Placing an operation with 'ebIgnore' behavior between
1181 // 'ebStrict' operations could distort the observed exception behavior.
1182 if (!PendingConstrainedFPStrict.empty()) {
1183 assert(PendingConstrainedFP.empty());
1184 updateRoot(Pending&: PendingConstrainedFPStrict);
1185 }
1186 break;
1187 case fp::ExceptionBehavior::ebStrict:
1188 // Floating-point exception produced by these operations may be observed, so
1189 // they must be correctly chained. If trapping on FP exceptions is
1190 // disabled, the exceptions can be observed only by functions that read
1191 // exception flags, like 'llvm.get_fpenv' or 'fetestexcept'. It means that
1192 // the order of operations is not significant between barriers.
1193 //
1194 // If trapping is enabled, each operation becomes an implicit observation
1195 // point, so the operations must be sequenced according their original
1196 // source order.
1197 if (!PendingConstrainedFP.empty()) {
1198 assert(PendingConstrainedFPStrict.empty());
1199 updateRoot(Pending&: PendingConstrainedFP);
1200 }
1201 // TODO: Add support for trapping-enabled scenarios.
1202 }
1203 return DAG.getRoot();
1204}
1205
1206SDValue SelectionDAGBuilder::getRoot() {
1207 // Chain up all pending constrained intrinsics together with all
1208 // pending loads, by simply appending them to PendingLoads and
1209 // then calling getMemoryRoot().
1210 PendingLoads.reserve(N: PendingLoads.size() +
1211 PendingConstrainedFP.size() +
1212 PendingConstrainedFPStrict.size());
1213 PendingLoads.append(in_start: PendingConstrainedFP.begin(),
1214 in_end: PendingConstrainedFP.end());
1215 PendingLoads.append(in_start: PendingConstrainedFPStrict.begin(),
1216 in_end: PendingConstrainedFPStrict.end());
1217 PendingConstrainedFP.clear();
1218 PendingConstrainedFPStrict.clear();
1219 return getMemoryRoot();
1220}
1221
1222SDValue SelectionDAGBuilder::getControlRoot() {
1223 // We need to emit pending fpexcept.strict constrained intrinsics,
1224 // so append them to the PendingExports list.
1225 PendingExports.append(in_start: PendingConstrainedFPStrict.begin(),
1226 in_end: PendingConstrainedFPStrict.end());
1227 PendingConstrainedFPStrict.clear();
1228 return updateRoot(Pending&: PendingExports);
1229}
1230
1231void SelectionDAGBuilder::handleDebugDeclare(Value *Address,
1232 DILocalVariable *Variable,
1233 DIExpression *Expression,
1234 DebugLoc DL) {
1235 assert(Variable && "Missing variable");
1236
1237 // Check if address has undef value.
1238 if (!Address || isa<UndefValue>(Val: Address) ||
1239 (Address->use_empty() && !isa<Argument>(Val: Address))) {
1240 LLVM_DEBUG(
1241 dbgs()
1242 << "dbg_declare: Dropping debug info (bad/undef/unused-arg address)\n");
1243 return;
1244 }
1245
1246 bool IsParameter = Variable->isParameter() || isa<Argument>(Val: Address);
1247
1248 SDValue &N = NodeMap[Address];
1249 if (!N.getNode() && isa<Argument>(Val: Address))
1250 // Check unused arguments map.
1251 N = UnusedArgNodeMap[Address];
1252 SDDbgValue *SDV;
1253 if (N.getNode()) {
1254 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Val: Address))
1255 Address = BCI->getOperand(i_nocapture: 0);
1256 // Parameters are handled specially.
1257 auto *FINode = dyn_cast<FrameIndexSDNode>(Val: N.getNode());
1258 if (IsParameter && FINode) {
1259 // Byval parameter. We have a frame index at this point.
1260 SDV = DAG.getFrameIndexDbgValue(Var: Variable, Expr: Expression, FI: FINode->getIndex(),
1261 /*IsIndirect*/ true, DL, O: SDNodeOrder);
1262 } else if (isa<Argument>(Val: Address)) {
1263 // Address is an argument, so try to emit its dbg value using
1264 // virtual register info from the FuncInfo.ValueMap.
1265 EmitFuncArgumentDbgValue(V: Address, Variable, Expr: Expression, DL,
1266 Kind: FuncArgumentDbgValueKind::Declare, N);
1267 return;
1268 } else {
1269 SDV = DAG.getDbgValue(Var: Variable, Expr: Expression, N: N.getNode(), R: N.getResNo(),
1270 IsIndirect: true, DL, O: SDNodeOrder);
1271 }
1272 DAG.AddDbgValue(DB: SDV, isParameter: IsParameter);
1273 } else {
1274 // If Address is an argument then try to emit its dbg value using
1275 // virtual register info from the FuncInfo.ValueMap.
1276 if (!EmitFuncArgumentDbgValue(V: Address, Variable, Expr: Expression, DL,
1277 Kind: FuncArgumentDbgValueKind::Declare, N)) {
1278 LLVM_DEBUG(dbgs() << "dbg_declare: Dropping debug info"
1279 << " (could not emit func-arg dbg_value)\n");
1280 }
1281 }
1282}
1283
1284void SelectionDAGBuilder::visitDbgInfo(const Instruction &I) {
1285 // Add SDDbgValue nodes for any var locs here. Do so before updating
1286 // SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}.
1287 if (FunctionVarLocs const *FnVarLocs = DAG.getFunctionVarLocs()) {
1288 // Add SDDbgValue nodes for any var locs here. Do so before updating
1289 // SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}.
1290 for (auto It = FnVarLocs->locs_begin(Before: &I), End = FnVarLocs->locs_end(Before: &I);
1291 It != End; ++It) {
1292 auto *Var = FnVarLocs->getDILocalVariable(ID: It->VariableID);
1293 dropDanglingDebugInfo(Variable: Var, Expr: It->Expr);
1294 if (It->Values.isKillLocation(Expression: It->Expr)) {
1295 handleKillDebugValue(Var, Expr: It->Expr, DbgLoc: It->DL, Order: SDNodeOrder);
1296 continue;
1297 }
1298 SmallVector<Value *> Values(It->Values.location_ops());
1299 if (!handleDebugValue(Values, Var, Expr: It->Expr, DbgLoc: It->DL, Order: SDNodeOrder,
1300 IsVariadic: It->Values.hasArgList())) {
1301 SmallVector<Value *, 4> Vals(It->Values.location_ops());
1302 addDanglingDebugInfo(Values&: Vals,
1303 Var: FnVarLocs->getDILocalVariable(ID: It->VariableID),
1304 Expr: It->Expr, IsVariadic: Vals.size() > 1, DL: It->DL, Order: SDNodeOrder);
1305 }
1306 }
1307 }
1308
1309 // We must skip DbgVariableRecords if they've already been processed above as
1310 // we have just emitted the debug values resulting from assignment tracking
1311 // analysis, making any existing DbgVariableRecords redundant (and probably
1312 // less correct). We still need to process DbgLabelRecords. This does sink
1313 // DbgLabelRecords to the bottom of the group of debug records. That sholdn't
1314 // be important as it does so deterministcally and ordering between
1315 // DbgLabelRecords and DbgVariableRecords is immaterial (other than for MIR/IR
1316 // printing).
1317 bool SkipDbgVariableRecords = DAG.getFunctionVarLocs();
1318 // Is there is any debug-info attached to this instruction, in the form of
1319 // DbgRecord non-instruction debug-info records.
1320 for (DbgRecord &DR : I.getDbgRecordRange()) {
1321 if (DbgLabelRecord *DLR = dyn_cast<DbgLabelRecord>(Val: &DR)) {
1322 assert(DLR->getLabel() && "Missing label");
1323 SDDbgLabel *SDV =
1324 DAG.getDbgLabel(Label: DLR->getLabel(), DL: DLR->getDebugLoc(), O: SDNodeOrder);
1325 DAG.AddDbgLabel(DB: SDV);
1326 continue;
1327 }
1328
1329 if (SkipDbgVariableRecords)
1330 continue;
1331 DbgVariableRecord &DVR = cast<DbgVariableRecord>(Val&: DR);
1332 DILocalVariable *Variable = DVR.getVariable();
1333 DIExpression *Expression = DVR.getExpression();
1334 dropDanglingDebugInfo(Variable, Expr: Expression);
1335
1336 if (DVR.getType() == DbgVariableRecord::LocationType::Declare) {
1337 if (FuncInfo.PreprocessedDVRDeclares.contains(Ptr: &DVR))
1338 continue;
1339 LLVM_DEBUG(dbgs() << "SelectionDAG visiting dbg_declare: " << DVR
1340 << "\n");
1341 handleDebugDeclare(Address: DVR.getVariableLocationOp(OpIdx: 0), Variable, Expression,
1342 DL: DVR.getDebugLoc());
1343 continue;
1344 }
1345
1346 // A DbgVariableRecord with no locations is a kill location.
1347 SmallVector<Value *, 4> Values(DVR.location_ops());
1348 if (Values.empty()) {
1349 handleKillDebugValue(Var: Variable, Expr: Expression, DbgLoc: DVR.getDebugLoc(),
1350 Order: SDNodeOrder);
1351 continue;
1352 }
1353
1354 // A DbgVariableRecord with an undef or absent location is also a kill
1355 // location.
1356 if (llvm::any_of(Range&: Values,
1357 P: [](Value *V) { return !V || isa<UndefValue>(Val: V); })) {
1358 handleKillDebugValue(Var: Variable, Expr: Expression, DbgLoc: DVR.getDebugLoc(),
1359 Order: SDNodeOrder);
1360 continue;
1361 }
1362
1363 bool IsVariadic = DVR.hasArgList();
1364 if (!handleDebugValue(Values, Var: Variable, Expr: Expression, DbgLoc: DVR.getDebugLoc(),
1365 Order: SDNodeOrder, IsVariadic)) {
1366 addDanglingDebugInfo(Values, Var: Variable, Expr: Expression, IsVariadic,
1367 DL: DVR.getDebugLoc(), Order: SDNodeOrder);
1368 }
1369 }
1370}
1371
1372void SelectionDAGBuilder::visit(const Instruction &I) {
1373 visitDbgInfo(I);
1374
1375 // Set up outgoing PHI node register values before emitting the terminator.
1376 if (I.isTerminator()) {
1377 HandlePHINodesInSuccessorBlocks(LLVMBB: I.getParent());
1378 }
1379
1380 ++SDNodeOrder;
1381 CurInst = &I;
1382
1383 // Set inserted listener only if required.
1384 bool NodeInserted = false;
1385 std::unique_ptr<SelectionDAG::DAGNodeInsertedListener> InsertedListener;
1386 MDNode *PCSectionsMD = I.getMetadata(KindID: LLVMContext::MD_pcsections);
1387 MDNode *MMRA = I.getMetadata(KindID: LLVMContext::MD_mmra);
1388 if (PCSectionsMD || MMRA) {
1389 InsertedListener = std::make_unique<SelectionDAG::DAGNodeInsertedListener>(
1390 args&: DAG, args: [&](SDNode *) { NodeInserted = true; });
1391 }
1392
1393 visit(Opcode: I.getOpcode(), I);
1394
1395 if (!I.isTerminator() && !HasTailCall &&
1396 !isa<GCStatepointInst>(Val: I)) // statepoints handle their exports internally
1397 CopyToExportRegsIfNeeded(V: &I);
1398
1399 // Handle metadata.
1400 if (PCSectionsMD || MMRA) {
1401 auto It = NodeMap.find(Val: &I);
1402 if (It != NodeMap.end()) {
1403 if (PCSectionsMD)
1404 DAG.addPCSections(Node: It->second.getNode(), MD: PCSectionsMD);
1405 if (MMRA)
1406 DAG.addMMRAMetadata(Node: It->second.getNode(), MMRA);
1407 } else if (NodeInserted) {
1408 // This should not happen; if it does, don't let it go unnoticed so we can
1409 // fix it. Relevant visit*() function is probably missing a setValue().
1410 errs() << "warning: loosing !pcsections and/or !mmra metadata ["
1411 << I.getModule()->getName() << "]\n";
1412 LLVM_DEBUG(I.dump());
1413 assert(false);
1414 }
1415 }
1416
1417 CurInst = nullptr;
1418}
1419
1420void SelectionDAGBuilder::visitPHI(const PHINode &) {
1421 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
1422}
1423
1424void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
1425 // Note: this doesn't use InstVisitor, because it has to work with
1426 // ConstantExpr's in addition to instructions.
1427 switch (Opcode) {
1428 default: llvm_unreachable("Unknown instruction type encountered!");
1429 // Build the switch statement using the Instruction.def file.
1430#define HANDLE_INST(NUM, OPCODE, CLASS) \
1431 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1432#include "llvm/IR/Instruction.def"
1433 }
1434}
1435
1436static bool handleDanglingVariadicDebugInfo(SelectionDAG &DAG,
1437 DILocalVariable *Variable,
1438 DebugLoc DL, unsigned Order,
1439 SmallVectorImpl<Value *> &Values,
1440 DIExpression *Expression) {
1441 // For variadic dbg_values we will now insert poison.
1442 // FIXME: We can potentially recover these!
1443 SmallVector<SDDbgOperand, 2> Locs;
1444 for (const Value *V : Values) {
1445 auto *Poison = PoisonValue::get(T: V->getType());
1446 Locs.push_back(Elt: SDDbgOperand::fromConst(Const: Poison));
1447 }
1448 SDDbgValue *SDV = DAG.getDbgValueList(Var: Variable, Expr: Expression, Locs, Dependencies: {},
1449 /*IsIndirect=*/false, DL, O: Order,
1450 /*IsVariadic=*/true);
1451 DAG.AddDbgValue(DB: SDV, /*isParameter=*/false);
1452 return true;
1453}
1454
1455void SelectionDAGBuilder::addDanglingDebugInfo(SmallVectorImpl<Value *> &Values,
1456 DILocalVariable *Var,
1457 DIExpression *Expr,
1458 bool IsVariadic, DebugLoc DL,
1459 unsigned Order) {
1460 if (IsVariadic) {
1461 handleDanglingVariadicDebugInfo(DAG, Variable: Var, DL, Order, Values, Expression: Expr);
1462 return;
1463 }
1464 // TODO: Dangling debug info will eventually either be resolved or produce
1465 // a poison DBG_VALUE. However in the resolution case, a gap may appear
1466 // between the original dbg.value location and its resolved DBG_VALUE,
1467 // which we should ideally fill with an extra poison DBG_VALUE.
1468 assert(Values.size() == 1);
1469 DanglingDebugInfoMap[Values[0]].emplace_back(args&: Var, args&: Expr, args&: DL, args&: Order);
1470}
1471
1472void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable,
1473 const DIExpression *Expr) {
1474 auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1475 DIVariable *DanglingVariable = DDI.getVariable();
1476 DIExpression *DanglingExpr = DDI.getExpression();
1477 if (DanglingVariable == Variable && Expr->fragmentsOverlap(Other: DanglingExpr)) {
1478 LLVM_DEBUG(dbgs() << "Dropping dangling debug info for "
1479 << printDDI(nullptr, DDI) << "\n");
1480 return true;
1481 }
1482 return false;
1483 };
1484
1485 for (auto &DDIMI : DanglingDebugInfoMap) {
1486 DanglingDebugInfoVector &DDIV = DDIMI.second;
1487
1488 // If debug info is to be dropped, run it through final checks to see
1489 // whether it can be salvaged.
1490 for (auto &DDI : DDIV)
1491 if (isMatchingDbgValue(DDI))
1492 salvageUnresolvedDbgValue(V: DDIMI.first, DDI);
1493
1494 erase_if(C&: DDIV, P: isMatchingDbgValue);
1495 }
1496}
1497
1498// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
1499// generate the debug data structures now that we've seen its definition.
1500void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
1501 SDValue Val) {
1502 auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(Key: V);
1503 if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1504 return;
1505
1506 DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1507 for (auto &DDI : DDIV) {
1508 DebugLoc DL = DDI.getDebugLoc();
1509 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1510 DILocalVariable *Variable = DDI.getVariable();
1511 DIExpression *Expr = DDI.getExpression();
1512 assert(Variable->isValidLocationForIntrinsic(DL) &&
1513 "Expected inlined-at fields to agree");
1514 SDDbgValue *SDV;
1515 if (Val.getNode()) {
1516 // FIXME: I doubt that it is correct to resolve a dangling DbgValue as a
1517 // FuncArgumentDbgValue (it would be hoisted to the function entry, and if
1518 // we couldn't resolve it directly when examining the DbgValue intrinsic
1519 // in the first place we should not be more successful here). Unless we
1520 // have some test case that prove this to be correct we should avoid
1521 // calling EmitFuncArgumentDbgValue here.
1522 unsigned ValSDNodeOrder = Val.getNode()->getIROrder();
1523 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, DL,
1524 Kind: FuncArgumentDbgValueKind::Value, N: Val)) {
1525 LLVM_DEBUG(dbgs() << "Resolve dangling debug info for "
1526 << printDDI(V, DDI) << "\n");
1527 LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump());
1528 // Increase the SDNodeOrder for the DbgValue here to make sure it is
1529 // inserted after the definition of Val when emitting the instructions
1530 // after ISel. An alternative could be to teach
1531 // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly.
1532 LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs()
1533 << "changing SDNodeOrder from " << DbgSDNodeOrder << " to "
1534 << ValSDNodeOrder << "\n");
1535 SDV = getDbgValue(N: Val, Variable, Expr, dl: DL,
1536 DbgSDNodeOrder: std::max(a: DbgSDNodeOrder, b: ValSDNodeOrder));
1537 DAG.AddDbgValue(DB: SDV, isParameter: false);
1538 } else
1539 LLVM_DEBUG(dbgs() << "Resolved dangling debug info for "
1540 << printDDI(V, DDI)
1541 << " in EmitFuncArgumentDbgValue\n");
1542 } else {
1543 LLVM_DEBUG(dbgs() << "Dropping debug info for " << printDDI(V, DDI)
1544 << "\n");
1545 auto Poison = PoisonValue::get(T: V->getType());
1546 auto SDV =
1547 DAG.getConstantDbgValue(Var: Variable, Expr, C: Poison, DL, O: DbgSDNodeOrder);
1548 DAG.AddDbgValue(DB: SDV, isParameter: false);
1549 }
1550 }
1551 DDIV.clear();
1552}
1553
1554void SelectionDAGBuilder::salvageUnresolvedDbgValue(const Value *V,
1555 DanglingDebugInfo &DDI) {
1556 // TODO: For the variadic implementation, instead of only checking the fail
1557 // state of `handleDebugValue`, we need know specifically which values were
1558 // invalid, so that we attempt to salvage only those values when processing
1559 // a DIArgList.
1560 const Value *OrigV = V;
1561 DILocalVariable *Var = DDI.getVariable();
1562 DIExpression *Expr = DDI.getExpression();
1563 DebugLoc DL = DDI.getDebugLoc();
1564 unsigned SDOrder = DDI.getSDNodeOrder();
1565
1566 // Currently we consider only dbg.value intrinsics -- we tell the salvager
1567 // that DW_OP_stack_value is desired.
1568 bool StackValue = true;
1569
1570 // Can this Value can be encoded without any further work?
1571 if (handleDebugValue(Values: V, Var, Expr, DbgLoc: DL, Order: SDOrder, /*IsVariadic=*/false))
1572 return;
1573
1574 // Attempt to salvage back through as many instructions as possible. Bail if
1575 // a non-instruction is seen, such as a constant expression or global
1576 // variable. FIXME: Further work could recover those too.
1577 while (isa<Instruction>(Val: V)) {
1578 const Instruction &VAsInst = *cast<const Instruction>(Val: V);
1579 // Temporary "0", awaiting real implementation.
1580 SmallVector<uint64_t, 16> Ops;
1581 SmallVector<Value *, 4> AdditionalValues;
1582 V = salvageDebugInfoImpl(I&: const_cast<Instruction &>(VAsInst),
1583 CurrentLocOps: Expr->getNumLocationOperands(), Ops,
1584 AdditionalValues);
1585 // If we cannot salvage any further, and haven't yet found a suitable debug
1586 // expression, bail out.
1587 if (!V)
1588 break;
1589
1590 // TODO: If AdditionalValues isn't empty, then the salvage can only be
1591 // represented with a DBG_VALUE_LIST, so we give up. When we have support
1592 // here for variadic dbg_values, remove that condition.
1593 if (!AdditionalValues.empty())
1594 break;
1595
1596 // New value and expr now represent this debuginfo.
1597 Expr = DIExpression::appendOpsToArg(Expr, Ops, ArgNo: 0, StackValue);
1598
1599 // Some kind of simplification occurred: check whether the operand of the
1600 // salvaged debug expression can be encoded in this DAG.
1601 if (handleDebugValue(Values: V, Var, Expr, DbgLoc: DL, Order: SDOrder, /*IsVariadic=*/false)) {
1602 LLVM_DEBUG(
1603 dbgs() << "Salvaged debug location info for:\n " << *Var << "\n"
1604 << *OrigV << "\nBy stripping back to:\n " << *V << "\n");
1605 return;
1606 }
1607 }
1608
1609 // This was the final opportunity to salvage this debug information, and it
1610 // couldn't be done. Place a poison DBG_VALUE at this location to terminate
1611 // any earlier variable location.
1612 assert(OrigV && "V shouldn't be null");
1613 auto *Poison = PoisonValue::get(T: OrigV->getType());
1614 auto *SDV = DAG.getConstantDbgValue(Var, Expr, C: Poison, DL, O: SDNodeOrder);
1615 DAG.AddDbgValue(DB: SDV, isParameter: false);
1616 LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n "
1617 << printDDI(OrigV, DDI) << "\n");
1618}
1619
1620void SelectionDAGBuilder::handleKillDebugValue(DILocalVariable *Var,
1621 DIExpression *Expr,
1622 DebugLoc DbgLoc,
1623 unsigned Order) {
1624 Value *Poison = PoisonValue::get(T: Type::getInt1Ty(C&: *Context));
1625 DIExpression *NewExpr =
1626 const_cast<DIExpression *>(DIExpression::convertToUndefExpression(Expr));
1627 handleDebugValue(Values: Poison, Var, Expr: NewExpr, DbgLoc, Order,
1628 /*IsVariadic*/ false);
1629}
1630
1631bool SelectionDAGBuilder::handleDebugValue(ArrayRef<const Value *> Values,
1632 DILocalVariable *Var,
1633 DIExpression *Expr, DebugLoc DbgLoc,
1634 unsigned Order, bool IsVariadic) {
1635 if (Values.empty())
1636 return true;
1637
1638 // Filter EntryValue locations out early.
1639 if (visitEntryValueDbgValue(Values, Variable: Var, Expr, DbgLoc))
1640 return true;
1641
1642 SmallVector<SDDbgOperand> LocationOps;
1643 SmallVector<SDNode *> Dependencies;
1644 for (const Value *V : Values) {
1645 // Constant value.
1646 if (isa<ConstantInt>(Val: V) || isa<ConstantFP>(Val: V) || isa<UndefValue>(Val: V) ||
1647 isa<ConstantPointerNull>(Val: V)) {
1648 LocationOps.emplace_back(Args: SDDbgOperand::fromConst(Const: V));
1649 continue;
1650 }
1651
1652 // Look through IntToPtr constants.
1653 if (auto *CE = dyn_cast<ConstantExpr>(Val: V))
1654 if (CE->getOpcode() == Instruction::IntToPtr) {
1655 LocationOps.emplace_back(Args: SDDbgOperand::fromConst(Const: CE->getOperand(i_nocapture: 0)));
1656 continue;
1657 }
1658
1659 // If the Value is a frame index, we can create a FrameIndex debug value
1660 // without relying on the DAG at all.
1661 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Val: V)) {
1662 auto SI = FuncInfo.StaticAllocaMap.find(Val: AI);
1663 if (SI != FuncInfo.StaticAllocaMap.end()) {
1664 LocationOps.emplace_back(Args: SDDbgOperand::fromFrameIdx(FrameIdx: SI->second));
1665 continue;
1666 }
1667 }
1668
1669 // Do not use getValue() in here; we don't want to generate code at
1670 // this point if it hasn't been done yet.
1671 SDValue N = NodeMap[V];
1672 if (!N.getNode() && isa<Argument>(Val: V)) // Check unused arguments map.
1673 N = UnusedArgNodeMap[V];
1674
1675 if (N.getNode()) {
1676 // Only emit func arg dbg value for non-variadic dbg.values for now.
1677 if (!IsVariadic &&
1678 EmitFuncArgumentDbgValue(V, Variable: Var, Expr, DL: DbgLoc,
1679 Kind: FuncArgumentDbgValueKind::Value, N))
1680 return true;
1681 if (auto *FISDN = dyn_cast<FrameIndexSDNode>(Val: N.getNode())) {
1682 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can
1683 // describe stack slot locations.
1684 //
1685 // Consider "int x = 0; int *px = &x;". There are two kinds of
1686 // interesting debug values here after optimization:
1687 //
1688 // dbg.value(i32* %px, !"int *px", !DIExpression()), and
1689 // dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref))
1690 //
1691 // Both describe the direct values of their associated variables.
1692 Dependencies.push_back(Elt: N.getNode());
1693 LocationOps.emplace_back(Args: SDDbgOperand::fromFrameIdx(FrameIdx: FISDN->getIndex()));
1694 continue;
1695 }
1696 LocationOps.emplace_back(
1697 Args: SDDbgOperand::fromNode(Node: N.getNode(), ResNo: N.getResNo()));
1698 continue;
1699 }
1700
1701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1702 // Special rules apply for the first dbg.values of parameter variables in a
1703 // function. Identify them by the fact they reference Argument Values, that
1704 // they're parameters, and they are parameters of the current function. We
1705 // need to let them dangle until they get an SDNode.
1706 bool IsParamOfFunc =
1707 isa<Argument>(Val: V) && Var->isParameter() && !DbgLoc.getInlinedAt();
1708 if (IsParamOfFunc)
1709 return false;
1710
1711 // The value is not used in this block yet (or it would have an SDNode).
1712 // We still want the value to appear for the user if possible -- if it has
1713 // an associated VReg, we can refer to that instead.
1714 auto VMI = FuncInfo.ValueMap.find(Val: V);
1715 if (VMI != FuncInfo.ValueMap.end()) {
1716 Register Reg = VMI->second;
1717 // If this is a PHI node, it may be split up into several MI PHI nodes
1718 // (in FunctionLoweringInfo::set).
1719 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
1720 V->getType(), std::nullopt);
1721 if (RFV.occupiesMultipleRegs()) {
1722 // FIXME: We could potentially support variadic dbg_values here.
1723 if (IsVariadic)
1724 return false;
1725 unsigned Offset = 0;
1726 unsigned BitsToDescribe = 0;
1727 if (auto VarSize = Var->getSizeInBits())
1728 BitsToDescribe = *VarSize;
1729 if (auto Fragment = Expr->getFragmentInfo())
1730 BitsToDescribe = Fragment->SizeInBits;
1731 for (const auto &RegAndSize : RFV.getRegsAndSizes()) {
1732 // Bail out if all bits are described already.
1733 if (Offset >= BitsToDescribe)
1734 break;
1735 // TODO: handle scalable vectors.
1736 unsigned RegisterSize = RegAndSize.second;
1737 unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
1738 ? BitsToDescribe - Offset
1739 : RegisterSize;
1740 auto FragmentExpr = DIExpression::createFragmentExpression(
1741 Expr, OffsetInBits: Offset, SizeInBits: FragmentSize);
1742 if (!FragmentExpr)
1743 continue;
1744 SDDbgValue *SDV = DAG.getVRegDbgValue(
1745 Var, Expr: *FragmentExpr, VReg: RegAndSize.first, IsIndirect: false, DL: DbgLoc, O: Order);
1746 DAG.AddDbgValue(DB: SDV, isParameter: false);
1747 Offset += RegisterSize;
1748 }
1749 return true;
1750 }
1751 // We can use simple vreg locations for variadic dbg_values as well.
1752 LocationOps.emplace_back(Args: SDDbgOperand::fromVReg(VReg: Reg));
1753 continue;
1754 }
1755 // We failed to create a SDDbgOperand for V.
1756 return false;
1757 }
1758
1759 // We have created a SDDbgOperand for each Value in Values.
1760 assert(!LocationOps.empty());
1761 SDDbgValue *SDV =
1762 DAG.getDbgValueList(Var, Expr, Locs: LocationOps, Dependencies,
1763 /*IsIndirect=*/false, DL: DbgLoc, O: Order, IsVariadic);
1764 DAG.AddDbgValue(DB: SDV, /*isParameter=*/false);
1765 return true;
1766}
1767
1768void SelectionDAGBuilder::resolveOrClearDbgInfo() {
1769 // Try to fixup any remaining dangling debug info -- and drop it if we can't.
1770 for (auto &Pair : DanglingDebugInfoMap)
1771 for (auto &DDI : Pair.second)
1772 salvageUnresolvedDbgValue(V: const_cast<Value *>(Pair.first), DDI);
1773 clearDanglingDebugInfo();
1774}
1775
1776/// getCopyFromRegs - If there was virtual register allocated for the value V
1777/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1778SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1779 auto It = FuncInfo.ValueMap.find(Val: V);
1780 SDValue Result;
1781
1782 if (It != FuncInfo.ValueMap.end()) {
1783 Register InReg = It->second;
1784
1785 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1786 DAG.getDataLayout(), InReg, Ty,
1787 std::nullopt); // This is not an ABI copy.
1788 SDValue Chain = DAG.getEntryNode();
1789 Result = RFV.getCopyFromRegs(DAG, FuncInfo, dl: getCurSDLoc(), Chain, Glue: nullptr,
1790 V);
1791 resolveDanglingDebugInfo(V, Val: Result);
1792 }
1793
1794 return Result;
1795}
1796
1797/// getValue - Return an SDValue for the given Value.
1798SDValue SelectionDAGBuilder::getValue(const Value *V) {
1799 // If we already have an SDValue for this value, use it. It's important
1800 // to do this first, so that we don't create a CopyFromReg if we already
1801 // have a regular SDValue.
1802 SDValue &N = NodeMap[V];
1803 if (N.getNode()) return N;
1804
1805 // If there's a virtual register allocated and initialized for this
1806 // value, use it.
1807 if (SDValue copyFromReg = getCopyFromRegs(V, Ty: V->getType()))
1808 return copyFromReg;
1809
1810 // Otherwise create a new SDValue and remember it.
1811 SDValue Val = getValueImpl(V);
1812 NodeMap[V] = Val;
1813 resolveDanglingDebugInfo(V, Val);
1814 return Val;
1815}
1816
1817void SelectionDAGBuilder::setValueToPoison(const Value *V, const SDLoc &dl) {
1818 if (V->getType()->isVoidTy())
1819 return;
1820
1821 SmallVector<EVT, 4> ValueVTs;
1822 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(),
1823 Ty: V->getType(), ValueVTs);
1824 setValue(V, NewN: DAG.getErrorMergeValues(ResultTypes: ValueVTs, Chain: SDValue(), dl));
1825}
1826
1827/// getNonRegisterValue - Return an SDValue for the given Value, but
1828/// don't look in FuncInfo.ValueMap for a virtual register.
1829SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1830 // If we already have an SDValue for this value, use it.
1831 SDValue &N = NodeMap[V];
1832 if (N.getNode()) {
1833 if (isIntOrFPConstant(V: N)) {
1834 // Remove the debug location from the node as the node is about to be used
1835 // in a location which may differ from the original debug location. This
1836 // is relevant to Constant and ConstantFP nodes because they can appear
1837 // as constant expressions inside PHI nodes.
1838 N->setDebugLoc(DebugLoc());
1839 }
1840 return N;
1841 }
1842
1843 // Otherwise create a new SDValue and remember it.
1844 SDValue Val = getValueImpl(V);
1845 NodeMap[V] = Val;
1846 resolveDanglingDebugInfo(V, Val);
1847 return Val;
1848}
1849
1850/// getValueImpl - Helper function for getValue and getNonRegisterValue.
1851/// Create an SDValue for the given value.
1852SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1854
1855 if (const Constant *C = dyn_cast<Constant>(Val: V)) {
1856 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: V->getType(), AllowUnknown: true);
1857
1858 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: C)) {
1859 SDLoc DL = getCurSDLoc();
1860
1861 // DAG.getConstant() may attempt to legalise the vector constant which can
1862 // significantly change the combines applied to the DAG. To reduce the
1863 // divergence when enabling ConstantInt based vectors we try to construct
1864 // the DAG in the same way as shufflevector based splats. TODO: The
1865 // divergence sometimes leads to better optimisations. Ideally we should
1866 // prevent DAG.getConstant() from legalising too early but there are some
1867 // degradations preventing this.
1868 if (VT.isScalableVector())
1869 return DAG.getNode(
1870 Opcode: ISD::SPLAT_VECTOR, DL, VT,
1871 Operand: DAG.getConstant(Val: CI->getValue(), DL, VT: VT.getVectorElementType()));
1872 if (VT.isFixedLengthVector())
1873 return DAG.getSplatBuildVector(
1874 VT, DL,
1875 Op: DAG.getConstant(Val: CI->getValue(), DL, VT: VT.getVectorElementType()));
1876 return DAG.getConstant(Val: *CI, DL, VT);
1877 }
1878
1879 if (const ConstantByte *CB = dyn_cast<ConstantByte>(Val: C))
1880 return DAG.getConstant(Val: CB->getValue(), DL: getCurSDLoc(), VT);
1881
1882 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: C))
1883 return DAG.getGlobalAddress(GV, DL: getCurSDLoc(), VT);
1884
1885 if (const ConstantPtrAuth *CPA = dyn_cast<ConstantPtrAuth>(Val: C)) {
1886 return DAG.getNode(Opcode: ISD::PtrAuthGlobalAddress, DL: getCurSDLoc(), VT,
1887 N1: getValue(V: CPA->getPointer()), N2: getValue(V: CPA->getKey()),
1888 N3: getValue(V: CPA->getAddrDiscriminator()),
1889 N4: getValue(V: CPA->getDiscriminator()));
1890 }
1891
1892 if (isa<ConstantPointerNull>(Val: C))
1893 return DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT);
1894
1895 if (match(V: C, P: m_VScale()))
1896 return DAG.getVScale(DL: getCurSDLoc(), VT, MulImm: APInt(VT.getSizeInBits(), 1));
1897
1898 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Val: C))
1899 return DAG.getConstantFP(V: *CFP, DL: getCurSDLoc(), VT);
1900
1901 if (isa<UndefValue>(Val: C) && !V->getType()->isAggregateType())
1902 return isa<PoisonValue>(Val: C) ? DAG.getPOISON(VT) : DAG.getUNDEF(VT);
1903
1904 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(Val: C)) {
1905 visit(Opcode: CE->getOpcode(), I: *CE);
1906 SDValue N1 = NodeMap[V];
1907 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1908 return N1;
1909 }
1910
1911 if (isa<ConstantStruct>(Val: C) || isa<ConstantArray>(Val: C)) {
1912 SmallVector<SDValue, 4> Constants;
1913 for (const Use &U : C->operands()) {
1914 SDNode *Val = getValue(V: U).getNode();
1915 // If the operand is an empty aggregate, there are no values.
1916 if (!Val) continue;
1917 // Add each leaf value from the operand to the Constants list
1918 // to form a flattened list of all the values.
1919 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1920 Constants.push_back(Elt: SDValue(Val, i));
1921 }
1922
1923 return DAG.getMergeValues(Ops: Constants, dl: getCurSDLoc());
1924 }
1925
1926 if (const ConstantDataSequential *CDS =
1927 dyn_cast<ConstantDataSequential>(Val: C)) {
1928 SmallVector<SDValue, 4> Ops;
1929 for (uint64_t i = 0, e = CDS->getNumElements(); i != e; ++i) {
1930 SDNode *Val = getValue(V: CDS->getElementAsConstant(i)).getNode();
1931 // Add each leaf value from the operand to the Constants list
1932 // to form a flattened list of all the values.
1933 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1934 Ops.push_back(Elt: SDValue(Val, i));
1935 }
1936
1937 if (isa<ArrayType>(Val: CDS->getType()))
1938 return DAG.getMergeValues(Ops, dl: getCurSDLoc());
1939 return DAG.getBuildVector(VT, DL: getCurSDLoc(), Ops);
1940 }
1941
1942 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1943 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1944 "Unknown struct or array constant!");
1945
1946 SmallVector<EVT, 4> ValueVTs;
1947 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: C->getType(), ValueVTs);
1948 unsigned NumElts = ValueVTs.size();
1949 if (NumElts == 0)
1950 return SDValue(); // empty struct
1951 SmallVector<SDValue, 4> Constants(NumElts);
1952 for (unsigned i = 0; i != NumElts; ++i) {
1953 EVT EltVT = ValueVTs[i];
1954 if (isa<UndefValue>(Val: C))
1955 Constants[i] = DAG.getUNDEF(VT: EltVT);
1956 else if (EltVT.isFloatingPoint())
1957 Constants[i] = DAG.getConstantFP(Val: 0, DL: getCurSDLoc(), VT: EltVT);
1958 else
1959 Constants[i] = DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: EltVT);
1960 }
1961
1962 return DAG.getMergeValues(Ops: Constants, dl: getCurSDLoc());
1963 }
1964
1965 if (const BlockAddress *BA = dyn_cast<BlockAddress>(Val: C))
1966 return DAG.getBlockAddress(BA, VT);
1967
1968 if (const auto *Equiv = dyn_cast<DSOLocalEquivalent>(Val: C))
1969 return getValue(V: Equiv->getGlobalValue());
1970
1971 if (const auto *NC = dyn_cast<NoCFIValue>(Val: C))
1972 return getValue(V: NC->getGlobalValue());
1973
1974 if (VT == MVT::aarch64svcount) {
1975 assert(C->isNullValue() && "Can only zero this target type!");
1976 return DAG.getNode(Opcode: ISD::BITCAST, DL: getCurSDLoc(), VT,
1977 Operand: DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: MVT::nxv16i1));
1978 }
1979
1980 if (VT.isRISCVVectorTuple()) {
1981 assert(C->isNullValue() && "Can only zero this target type!");
1982 return DAG.getNode(
1983 Opcode: ISD::BITCAST, DL: getCurSDLoc(), VT,
1984 Operand: DAG.getNode(
1985 Opcode: ISD::SPLAT_VECTOR, DL: getCurSDLoc(),
1986 VT: EVT::getVectorVT(Context&: *DAG.getContext(), VT: MVT::i8,
1987 NumElements: VT.getSizeInBits().getKnownMinValue() / 8, IsScalable: true),
1988 Operand: DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: MVT::getIntegerVT(BitWidth: 8))));
1989 }
1990
1991 if (VT == MVT::externref || VT == MVT::funcref) {
1992 assert(C->isNullValue() && "Can only zero this target type!");
1993 // The zero value of a WebAssembly reference type is the null reference,
1994 // materialized with ref.null.
1995 Intrinsic::ID IID = VT == MVT::externref ? Intrinsic::wasm_ref_null_extern
1996 : Intrinsic::wasm_ref_null_func;
1997 return DAG.getNode(Opcode: ISD::INTRINSIC_WO_CHAIN, DL: getCurSDLoc(), VT,
1998 Operand: DAG.getTargetConstant(Val: IID, DL: getCurSDLoc(), VT: MVT::i32));
1999 }
2000
2001 VectorType *VecTy = cast<VectorType>(Val: V->getType());
2002
2003 // Now that we know the number and type of the elements, get that number of
2004 // elements into the Ops array based on what kind of constant it is.
2005 if (const ConstantVector *CV = dyn_cast<ConstantVector>(Val: C)) {
2006 SmallVector<SDValue, 16> Ops;
2007 unsigned NumElements = cast<FixedVectorType>(Val: VecTy)->getNumElements();
2008 for (unsigned i = 0; i != NumElements; ++i)
2009 Ops.push_back(Elt: getValue(V: CV->getOperand(i_nocapture: i)));
2010
2011 return DAG.getBuildVector(VT, DL: getCurSDLoc(), Ops);
2012 }
2013
2014 if (isa<ConstantAggregateZero>(Val: C)) {
2015 EVT EltVT =
2016 TLI.getValueType(DL: DAG.getDataLayout(), Ty: VecTy->getElementType());
2017
2018 SDValue Op;
2019 if (EltVT.isFloatingPoint())
2020 Op = DAG.getConstantFP(Val: 0, DL: getCurSDLoc(), VT: EltVT);
2021 else
2022 Op = DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: EltVT);
2023
2024 return DAG.getSplat(VT, DL: getCurSDLoc(), Op);
2025 }
2026
2027 llvm_unreachable("Unknown vector constant");
2028 }
2029
2030 // If this is a static alloca, generate it as the frameindex instead of
2031 // computation.
2032 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Val: V)) {
2033 auto SI = FuncInfo.StaticAllocaMap.find(Val: AI);
2034 if (SI != FuncInfo.StaticAllocaMap.end())
2035 return DAG.getFrameIndex(
2036 FI: SI->second, VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: AI->getType()));
2037 }
2038
2039 // If this is an instruction which fast-isel has deferred, select it now.
2040 if (const Instruction *Inst = dyn_cast<Instruction>(Val: V)) {
2041 Register InReg = FuncInfo.InitializeRegForValue(V: Inst);
2042 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
2043 Inst->getType(), std::nullopt);
2044 SDValue Chain = DAG.getEntryNode();
2045 return RFV.getCopyFromRegs(DAG, FuncInfo, dl: getCurSDLoc(), Chain, Glue: nullptr, V);
2046 }
2047
2048 if (const MetadataAsValue *MD = dyn_cast<MetadataAsValue>(Val: V))
2049 return DAG.getMDNode(MD: cast<MDNode>(Val: MD->getMetadata()));
2050
2051 if (const auto *BB = dyn_cast<BasicBlock>(Val: V))
2052 return DAG.getBasicBlock(MBB: FuncInfo.getMBB(BB));
2053
2054 llvm_unreachable("Can't get register for value!");
2055}
2056
2057void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
2058 auto Pers = classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
2059 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
2060 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
2061 bool IsSEH = isAsynchronousEHPersonality(Pers);
2062 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
2063 if (IsSEH) {
2064 // For SEH, EHCont Guard needs to know that this catchpad is a target.
2065 CatchPadMBB->setIsEHContTarget(true);
2066 DAG.getMachineFunction().setHasEHContTarget(true);
2067 } else
2068 CatchPadMBB->setIsEHScopeEntry();
2069 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
2070 if (IsMSVCCXX || IsCoreCLR)
2071 CatchPadMBB->setIsEHFuncletEntry();
2072}
2073
2074void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
2075 // Update machine-CFG edge.
2076 MachineBasicBlock *TargetMBB = FuncInfo.getMBB(BB: I.getSuccessor());
2077 FuncInfo.MBB->addSuccessor(Succ: TargetMBB);
2078
2079 auto Pers = classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
2080 bool IsSEH = isAsynchronousEHPersonality(Pers);
2081 if (IsSEH) {
2082 // If this is not a fall-through branch or optimizations are switched off,
2083 // emit the branch.
2084 if (TargetMBB != NextBlock(MBB: FuncInfo.MBB) ||
2085 TM.getOptLevel() == CodeGenOptLevel::None)
2086 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(), VT: MVT::Other,
2087 N1: getControlRoot(), N2: DAG.getBasicBlock(MBB: TargetMBB)));
2088 return;
2089 }
2090
2091 // For non-SEH, EHCont Guard needs to know that this catchret is a target.
2092 TargetMBB->setIsEHContTarget(true);
2093 DAG.getMachineFunction().setHasEHContTarget(true);
2094
2095 // Figure out the funclet membership for the catchret's successor.
2096 // This will be used by the FuncletLayout pass to determine how to order the
2097 // BB's.
2098 // A 'catchret' returns to the outer scope's color.
2099 Value *ParentPad = I.getCatchSwitchParentPad();
2100 const BasicBlock *SuccessorColor;
2101 if (isa<ConstantTokenNone>(Val: ParentPad))
2102 SuccessorColor = &FuncInfo.Fn->getEntryBlock();
2103 else
2104 SuccessorColor = cast<Instruction>(Val: ParentPad)->getParent();
2105 assert(SuccessorColor && "No parent funclet for catchret!");
2106 MachineBasicBlock *SuccessorColorMBB = FuncInfo.getMBB(BB: SuccessorColor);
2107 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
2108
2109 // Create the terminator node.
2110 SDValue Ret = DAG.getNode(Opcode: ISD::CATCHRET, DL: getCurSDLoc(), VT: MVT::Other,
2111 N1: getControlRoot(), N2: DAG.getBasicBlock(MBB: TargetMBB),
2112 N3: DAG.getBasicBlock(MBB: SuccessorColorMBB));
2113 DAG.setRoot(Ret);
2114}
2115
2116void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
2117 // Don't emit any special code for the cleanuppad instruction. It just marks
2118 // the start of an EH scope/funclet.
2119 FuncInfo.MBB->setIsEHScopeEntry();
2120 auto Pers = classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
2121 if (Pers != EHPersonality::Wasm_CXX) {
2122 FuncInfo.MBB->setIsEHFuncletEntry();
2123 FuncInfo.MBB->setIsCleanupFuncletEntry();
2124 }
2125}
2126
2127/// When an invoke or a cleanupret unwinds to the next EH pad, there are
2128/// many places it could ultimately go. In the IR, we have a single unwind
2129/// destination, but in the machine CFG, we enumerate all the possible blocks.
2130/// This function skips over imaginary basic blocks that hold catchswitch
2131/// instructions, and finds all the "real" machine
2132/// basic block destinations. As those destinations may not be successors of
2133/// EHPadBB, here we also calculate the edge probability to those destinations.
2134/// The passed-in Prob is the edge probability to EHPadBB.
2135static void findUnwindDestinations(
2136 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
2137 BranchProbability Prob,
2138 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
2139 &UnwindDests) {
2140 EHPersonality Personality =
2141 classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
2142 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
2143 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
2144 bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
2145 bool IsSEH = isAsynchronousEHPersonality(Pers: Personality);
2146
2147 while (EHPadBB) {
2148 BasicBlock::const_iterator Pad = EHPadBB->getFirstNonPHIIt();
2149 BasicBlock *NewEHPadBB = nullptr;
2150 if (isa<LandingPadInst>(Val: Pad)) {
2151 // Stop on landingpads. They are not funclets.
2152 UnwindDests.emplace_back(Args: FuncInfo.getMBB(BB: EHPadBB), Args&: Prob);
2153 break;
2154 } else if (isa<CleanupPadInst>(Val: Pad)) {
2155 // Stop on cleanup pads. Cleanups are always funclet entries for all known
2156 // personalities except Wasm. And in Wasm this becomes a catch_all(_ref),
2157 // which always catches an exception.
2158 UnwindDests.emplace_back(Args: FuncInfo.getMBB(BB: EHPadBB), Args&: Prob);
2159 UnwindDests.back().first->setIsEHScopeEntry();
2160 // In Wasm, EH scopes are not funclets
2161 if (!IsWasmCXX)
2162 UnwindDests.back().first->setIsEHFuncletEntry();
2163 break;
2164 } else if (const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Val&: Pad)) {
2165 // Add the catchpad handlers to the possible destinations.
2166 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2167 UnwindDests.emplace_back(Args: FuncInfo.getMBB(BB: CatchPadBB), Args&: Prob);
2168 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
2169 if (IsMSVCCXX || IsCoreCLR)
2170 UnwindDests.back().first->setIsEHFuncletEntry();
2171 if (!IsSEH)
2172 UnwindDests.back().first->setIsEHScopeEntry();
2173 }
2174 NewEHPadBB = CatchSwitch->getUnwindDest();
2175 } else {
2176 continue;
2177 }
2178
2179 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2180 if (BPI && NewEHPadBB)
2181 Prob *= BPI->getEdgeProbability(Src: EHPadBB, Dst: NewEHPadBB);
2182 EHPadBB = NewEHPadBB;
2183 }
2184}
2185
2186void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
2187 // Update successor info.
2188 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2189 auto UnwindDest = I.getUnwindDest();
2190 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2191 BranchProbability UnwindDestProb =
2192 (BPI && UnwindDest)
2193 ? BPI->getEdgeProbability(Src: FuncInfo.MBB->getBasicBlock(), Dst: UnwindDest)
2194 : BranchProbability::getZero();
2195 findUnwindDestinations(FuncInfo, EHPadBB: UnwindDest, Prob: UnwindDestProb, UnwindDests);
2196 for (auto &UnwindDest : UnwindDests) {
2197 UnwindDest.first->setIsEHPad();
2198 addSuccessorWithProb(Src: FuncInfo.MBB, Dst: UnwindDest.first, Prob: UnwindDest.second);
2199 }
2200 FuncInfo.MBB->normalizeSuccProbs();
2201
2202 // Create the terminator node.
2203 MachineBasicBlock *CleanupPadMBB =
2204 FuncInfo.getMBB(BB: I.getCleanupPad()->getParent());
2205 SDValue Ret = DAG.getNode(Opcode: ISD::CLEANUPRET, DL: getCurSDLoc(), VT: MVT::Other,
2206 N1: getControlRoot(), N2: DAG.getBasicBlock(MBB: CleanupPadMBB));
2207 DAG.setRoot(Ret);
2208}
2209
2210void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
2211 report_fatal_error(reason: "visitCatchSwitch not yet implemented!");
2212}
2213
2214void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
2215 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2216 auto &DL = DAG.getDataLayout();
2217 SDValue Chain = getControlRoot();
2218 SmallVector<ISD::OutputArg, 8> Outs;
2219 SmallVector<SDValue, 8> OutVals;
2220
2221 // Calls to @llvm.experimental.deoptimize don't generate a return value, so
2222 // lower
2223 //
2224 // %val = call <ty> @llvm.experimental.deoptimize()
2225 // ret <ty> %val
2226 //
2227 // differently.
2228 if (I.getParent()->getTerminatingDeoptimizeCall()) {
2229 LowerDeoptimizingReturn();
2230 return;
2231 }
2232
2233 if (!FuncInfo.CanLowerReturn) {
2234 Register DemoteReg = FuncInfo.DemoteRegister;
2235
2236 // Emit a store of the return value through the virtual register.
2237 // Leave Outs empty so that LowerReturn won't try to load return
2238 // registers the usual way.
2239 MVT PtrValueVT = TLI.getPointerTy(DL, AS: DL.getAllocaAddrSpace());
2240 SDValue RetPtr =
2241 DAG.getCopyFromReg(Chain, dl: getCurSDLoc(), Reg: DemoteReg, VT: PtrValueVT);
2242 Type *RetTy = I.getOperand(i_nocapture: 0)->getType();
2243 Align BaseAlign = DL.getPrefTypeAlign(Ty: RetTy);
2244 RetPtr =
2245 TLI.annotateStackObjectPointer(Ptr: RetPtr, DAG, DL: getCurSDLoc(), Alignment: BaseAlign);
2246 SDValue RetOp = getValue(V: I.getOperand(i_nocapture: 0));
2247
2248 SmallVector<EVT, 4> ValueVTs, MemVTs;
2249 SmallVector<uint64_t, 4> Offsets;
2250 ComputeValueVTs(TLI, DL, Ty: RetTy, ValueVTs, MemVTs: &MemVTs, FixedOffsets: &Offsets, StartingOffset: 0);
2251 unsigned NumValues = ValueVTs.size();
2252
2253 SmallVector<SDValue, 4> Chains(NumValues);
2254 for (unsigned i = 0; i != NumValues; ++i) {
2255 // An aggregate return value cannot wrap around the address space, so
2256 // offsets to its parts don't wrap either.
2257 SDValue Ptr = DAG.getObjectPtrOffset(SL: getCurSDLoc(), Ptr: RetPtr,
2258 Offset: TypeSize::getFixed(ExactSize: Offsets[i]));
2259
2260 SDValue Val = RetOp.getValue(R: RetOp.getResNo() + i);
2261 if (MemVTs[i] != ValueVTs[i])
2262 Val = DAG.getPtrExtOrTrunc(Op: Val, DL: getCurSDLoc(), VT: MemVTs[i]);
2263 Chains[i] = DAG.getStore(
2264 Chain, dl: getCurSDLoc(), Val,
2265 // FIXME: better loc info would be nice.
2266 Ptr, PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
2267 Alignment: commonAlignment(A: BaseAlign, Offset: Offsets[i]));
2268 }
2269
2270 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: getCurSDLoc(),
2271 VT: MVT::Other, Ops: Chains);
2272 } else if (I.getNumOperands() != 0) {
2273 SmallVector<Type *, 4> Types;
2274 ComputeValueTypes(DL, Ty: I.getOperand(i_nocapture: 0)->getType(), Types);
2275 unsigned NumValues = Types.size();
2276 if (NumValues) {
2277 SDValue RetOp = getValue(V: I.getOperand(i_nocapture: 0));
2278
2279 const Function *F = I.getParent()->getParent();
2280
2281 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
2282 Ty: I.getOperand(i_nocapture: 0)->getType(), CallConv: F->getCallingConv(),
2283 /*IsVarArg*/ isVarArg: false, DL);
2284
2285 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
2286 if (F->getAttributes().hasRetAttr(Kind: Attribute::SExt))
2287 ExtendKind = ISD::SIGN_EXTEND;
2288 else if (F->getAttributes().hasRetAttr(Kind: Attribute::ZExt))
2289 ExtendKind = ISD::ZERO_EXTEND;
2290
2291 LLVMContext &Context = F->getContext();
2292 bool RetInReg = F->getAttributes().hasRetAttr(Kind: Attribute::InReg);
2293
2294 for (unsigned j = 0; j != NumValues; ++j) {
2295 EVT VT = TLI.getValueType(DL, Ty: Types[j]);
2296
2297 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
2298 VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
2299
2300 CallingConv::ID CC = F->getCallingConv();
2301
2302 unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT);
2303 MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT);
2304 SmallVector<SDValue, 4> Parts(NumParts);
2305 getCopyToParts(DAG, DL: getCurSDLoc(),
2306 Val: SDValue(RetOp.getNode(), RetOp.getResNo() + j),
2307 Parts: &Parts[0], NumParts, PartVT, V: &I, CallConv: CC, ExtendKind);
2308
2309 // 'inreg' on function refers to return value
2310 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
2311 if (RetInReg)
2312 Flags.setInReg();
2313
2314 if (I.getOperand(i_nocapture: 0)->getType()->isPointerTy()) {
2315 Flags.setPointer();
2316 Flags.setPointerAddrSpace(
2317 cast<PointerType>(Val: I.getOperand(i_nocapture: 0)->getType())->getAddressSpace());
2318 }
2319
2320 if (NeedsRegBlock) {
2321 Flags.setInConsecutiveRegs();
2322 if (j == NumValues - 1)
2323 Flags.setInConsecutiveRegsLast();
2324 }
2325
2326 // Propagate extension type if any
2327 if (ExtendKind == ISD::SIGN_EXTEND)
2328 Flags.setSExt();
2329 else if (ExtendKind == ISD::ZERO_EXTEND)
2330 Flags.setZExt();
2331 else if (F->getAttributes().hasRetAttr(Kind: Attribute::NoExt))
2332 Flags.setNoExt();
2333
2334 for (unsigned i = 0; i < NumParts; ++i) {
2335 Outs.push_back(Elt: ISD::OutputArg(Flags,
2336 Parts[i].getValueType().getSimpleVT(),
2337 VT, Types[j], 0, 0));
2338 OutVals.push_back(Elt: Parts[i]);
2339 }
2340 }
2341 }
2342 }
2343
2344 // Push in swifterror virtual register as the last element of Outs. This makes
2345 // sure swifterror virtual register will be returned in the swifterror
2346 // physical register.
2347 const Function *F = I.getParent()->getParent();
2348 if (TLI.supportSwiftError() &&
2349 F->getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError)) {
2350 assert(SwiftError.getFunctionArg() && "Need a swift error argument");
2351 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
2352 Flags.setSwiftError();
2353 Outs.push_back(Elt: ISD::OutputArg(Flags, /*vt=*/TLI.getPointerTy(DL),
2354 /*argvt=*/EVT(TLI.getPointerTy(DL)),
2355 PointerType::getUnqual(C&: *DAG.getContext()),
2356 /*origidx=*/1, /*partOffs=*/0));
2357 // Create SDNode for the swifterror virtual register.
2358 OutVals.push_back(
2359 Elt: DAG.getRegister(Reg: SwiftError.getOrCreateVRegUseAt(
2360 &I, FuncInfo.MBB, SwiftError.getFunctionArg()),
2361 VT: EVT(TLI.getPointerTy(DL))));
2362 }
2363
2364 bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg();
2365 CallingConv::ID CallConv =
2366 DAG.getMachineFunction().getFunction().getCallingConv();
2367 Chain = DAG.getTargetLoweringInfo().LowerReturn(
2368 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
2369
2370 // Verify that the target's LowerReturn behaved as expected.
2371 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
2372 "LowerReturn didn't return a valid chain!");
2373
2374 // Update the DAG with the new chain value resulting from return lowering.
2375 DAG.setRoot(Chain);
2376}
2377
2378/// CopyToExportRegsIfNeeded - If the given value has virtual registers
2379/// created for it, emit nodes to copy the value into the virtual
2380/// registers.
2381void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
2382 // Skip empty types
2383 if (V->getType()->isEmptyTy())
2384 return;
2385
2386 auto VMI = FuncInfo.ValueMap.find(Val: V);
2387 if (VMI != FuncInfo.ValueMap.end()) {
2388 assert((!V->use_empty() || isa<CallBrInst>(V)) &&
2389 "Unused value assigned virtual registers!");
2390 CopyValueToVirtualRegister(V, Reg: VMI->second);
2391 }
2392}
2393
2394/// ExportFromCurrentBlock - If this condition isn't known to be exported from
2395/// the current basic block, add it to ValueMap now so that we'll get a
2396/// CopyTo/FromReg.
2397void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
2398 // No need to export constants.
2399 if (!isa<Instruction>(Val: V) && !isa<Argument>(Val: V)) return;
2400
2401 // Already exported?
2402 if (FuncInfo.isExportedInst(V)) return;
2403
2404 Register Reg = FuncInfo.InitializeRegForValue(V);
2405 CopyValueToVirtualRegister(V, Reg);
2406}
2407
2408bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
2409 const BasicBlock *FromBB) {
2410 // The operands of the setcc have to be in this block. We don't know
2411 // how to export them from some other block.
2412 if (const Instruction *VI = dyn_cast<Instruction>(Val: V)) {
2413 // Can export from current BB.
2414 if (VI->getParent() == FromBB)
2415 return true;
2416
2417 // Is already exported, noop.
2418 return FuncInfo.isExportedInst(V);
2419 }
2420
2421 // If this is an argument, we can export it if the BB is the entry block or
2422 // if it is already exported.
2423 if (isa<Argument>(Val: V)) {
2424 if (FromBB->isEntryBlock())
2425 return true;
2426
2427 // Otherwise, can only export this if it is already exported.
2428 return FuncInfo.isExportedInst(V);
2429 }
2430
2431 // Otherwise, constants can always be exported.
2432 return true;
2433}
2434
2435/// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
2436BranchProbability
2437SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
2438 const MachineBasicBlock *Dst) const {
2439 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2440 const BasicBlock *SrcBB = Src->getBasicBlock();
2441 const BasicBlock *DstBB = Dst->getBasicBlock();
2442 if (!BPI) {
2443 // If BPI is not available, set the default probability as 1 / N, where N is
2444 // the number of successors.
2445 auto SuccSize = std::max<uint32_t>(a: succ_size(BB: SrcBB), b: 1);
2446 return BranchProbability(1, SuccSize);
2447 }
2448 return BPI->getEdgeProbability(Src: SrcBB, Dst: DstBB);
2449}
2450
2451void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
2452 MachineBasicBlock *Dst,
2453 BranchProbability Prob) {
2454 if (!FuncInfo.BPI)
2455 Src->addSuccessorWithoutProb(Succ: Dst);
2456 else {
2457 if (Prob.isUnknown())
2458 Prob = getEdgeProbability(Src, Dst);
2459 Src->addSuccessor(Succ: Dst, Prob);
2460 }
2461}
2462
2463static bool InBlock(const Value *V, const BasicBlock *BB) {
2464 if (const Instruction *I = dyn_cast<Instruction>(Val: V))
2465 return I->getParent() == BB;
2466 return true;
2467}
2468
2469/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
2470/// This function emits a branch and is used at the leaves of an OR or an
2471/// AND operator tree.
2472void
2473SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
2474 MachineBasicBlock *TBB,
2475 MachineBasicBlock *FBB,
2476 MachineBasicBlock *CurBB,
2477 MachineBasicBlock *SwitchBB,
2478 BranchProbability TProb,
2479 BranchProbability FProb,
2480 bool InvertCond) {
2481 const BasicBlock *BB = CurBB->getBasicBlock();
2482
2483 // If the leaf of the tree is a comparison, merge the condition into
2484 // the caseblock.
2485 if (const CmpInst *BOp = dyn_cast<CmpInst>(Val: Cond)) {
2486 // The operands of the cmp have to be in this block. We don't know
2487 // how to export them from some other block. If this is the first block
2488 // of the sequence, no exporting is needed.
2489 if (CurBB == SwitchBB ||
2490 (isExportableFromCurrentBlock(V: BOp->getOperand(i_nocapture: 0), FromBB: BB) &&
2491 isExportableFromCurrentBlock(V: BOp->getOperand(i_nocapture: 1), FromBB: BB))) {
2492 ISD::CondCode Condition;
2493 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Val: Cond)) {
2494 ICmpInst::Predicate Pred =
2495 InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2496 Condition = getICmpCondCode(Pred);
2497 } else {
2498 const FCmpInst *FC = cast<FCmpInst>(Val: Cond);
2499 FCmpInst::Predicate Pred =
2500 InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2501 Condition = getFCmpCondCode(Pred);
2502 if (FC->hasNoNaNs() ||
2503 (isKnownNeverNaN(V: FC->getOperand(i_nocapture: 0),
2504 SQ: SimplifyQuery(DAG.getDataLayout(), FC)) &&
2505 isKnownNeverNaN(V: FC->getOperand(i_nocapture: 1),
2506 SQ: SimplifyQuery(DAG.getDataLayout(), FC))))
2507 Condition = getFCmpCodeWithoutNaN(CC: Condition);
2508 }
2509
2510 CaseBlock CB(Condition, BOp->getOperand(i_nocapture: 0), BOp->getOperand(i_nocapture: 1), nullptr,
2511 TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2512 SL->SwitchCases.push_back(x: CB);
2513 return;
2514 }
2515 }
2516
2517 // Create a CaseBlock record representing this branch.
2518 ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
2519 CaseBlock CB(Opc, Cond, ConstantInt::getTrue(Context&: *DAG.getContext()),
2520 nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2521 SL->SwitchCases.push_back(x: CB);
2522}
2523
2524// Collect dependencies on V recursively. This is used for the cost analysis in
2525// `shouldKeepJumpConditionsTogether`.
2526static bool collectInstructionDeps(
2527 SmallMapVector<const Instruction *, bool, 8> *Deps, const Value *V,
2528 SmallMapVector<const Instruction *, bool, 8> *Necessary = nullptr,
2529 unsigned Depth = 0) {
2530 // Return false if we have an incomplete count.
2531 if (Depth >= SelectionDAG::MaxRecursionDepth)
2532 return false;
2533
2534 auto *I = dyn_cast<Instruction>(Val: V);
2535 if (I == nullptr)
2536 return true;
2537
2538 if (Necessary != nullptr) {
2539 // This instruction is necessary for the other side of the condition so
2540 // don't count it.
2541 if (Necessary->contains(Key: I))
2542 return true;
2543 }
2544
2545 // Already added this dep.
2546 if (!Deps->try_emplace(Key: I, Args: false).second)
2547 return true;
2548
2549 for (unsigned OpIdx = 0, E = I->getNumOperands(); OpIdx < E; ++OpIdx)
2550 if (!collectInstructionDeps(Deps, V: I->getOperand(i: OpIdx), Necessary,
2551 Depth: Depth + 1))
2552 return false;
2553 return true;
2554}
2555
2556bool SelectionDAGBuilder::shouldKeepJumpConditionsTogether(
2557 const FunctionLoweringInfo &FuncInfo, const CondBrInst &I,
2558 Instruction::BinaryOps Opc, const Value *Lhs, const Value *Rhs,
2559 TargetLoweringBase::CondMergingParams Params) const {
2560 if (Params.BaseCost < 0)
2561 return false;
2562
2563 // Baseline cost.
2564 InstructionCost CostThresh = Params.BaseCost;
2565
2566 BranchProbabilityInfo *BPI = nullptr;
2567 if (Params.LikelyBias || Params.UnlikelyBias)
2568 BPI = FuncInfo.BPI;
2569 if (BPI != nullptr) {
2570 // See if we are either likely to get an early out or compute both lhs/rhs
2571 // of the condition.
2572 BasicBlock *IfFalse = I.getSuccessor(i: 0);
2573 BasicBlock *IfTrue = I.getSuccessor(i: 1);
2574
2575 std::optional<bool> Likely;
2576 if (BPI->isEdgeHot(Src: I.getParent(), Dst: IfTrue))
2577 Likely = true;
2578 else if (BPI->isEdgeHot(Src: I.getParent(), Dst: IfFalse))
2579 Likely = false;
2580
2581 if (Likely) {
2582 if (Opc == (*Likely ? Instruction::And : Instruction::Or))
2583 // Its likely we will have to compute both lhs and rhs of condition
2584 CostThresh += Params.LikelyBias;
2585 else {
2586 if (Params.UnlikelyBias < 0)
2587 return false;
2588 // Its likely we will get an early out.
2589 CostThresh -= Params.UnlikelyBias;
2590 }
2591 }
2592 }
2593
2594 if (CostThresh <= 0)
2595 return false;
2596
2597 // Collect "all" instructions that lhs condition is dependent on.
2598 // Use map for stable iteration (to avoid non-determanism of iteration of
2599 // SmallPtrSet). The `bool` value is just a dummy.
2600 SmallMapVector<const Instruction *, bool, 8> LhsDeps, RhsDeps;
2601 collectInstructionDeps(Deps: &LhsDeps, V: Lhs);
2602 // Collect "all" instructions that rhs condition is dependent on AND are
2603 // dependencies of lhs. This gives us an estimate on which instructions we
2604 // stand to save by splitting the condition.
2605 if (!collectInstructionDeps(Deps: &RhsDeps, V: Rhs, Necessary: &LhsDeps))
2606 return false;
2607 // Add the compare instruction itself unless its a dependency on the LHS.
2608 if (const auto *RhsI = dyn_cast<Instruction>(Val: Rhs))
2609 if (!LhsDeps.contains(Key: RhsI))
2610 RhsDeps.try_emplace(Key: RhsI, Args: false);
2611
2612 InstructionCost CostOfIncluding = 0;
2613 // See if this instruction will need to computed independently of whether RHS
2614 // is.
2615 Value *BrCond = I.getCondition();
2616 auto ShouldCountInsn = [&RhsDeps, &BrCond](const Instruction *Ins) {
2617 for (const auto *U : Ins->users()) {
2618 // If user is independent of RHS calculation we don't need to count it.
2619 if (auto *UIns = dyn_cast<Instruction>(Val: U))
2620 if (UIns != BrCond && !RhsDeps.contains(Key: UIns))
2621 return false;
2622 }
2623 return true;
2624 };
2625
2626 // Prune instructions from RHS Deps that are dependencies of unrelated
2627 // instructions. The value (SelectionDAG::MaxRecursionDepth) is fairly
2628 // arbitrary and just meant to cap the how much time we spend in the pruning
2629 // loop. Its highly unlikely to come into affect.
2630 const unsigned MaxPruneIters = SelectionDAG::MaxRecursionDepth;
2631 // Stop after a certain point. No incorrectness from including too many
2632 // instructions.
2633 for (unsigned PruneIters = 0; PruneIters < MaxPruneIters; ++PruneIters) {
2634 const Instruction *ToDrop = nullptr;
2635 for (const auto &InsPair : RhsDeps) {
2636 if (!ShouldCountInsn(InsPair.first)) {
2637 ToDrop = InsPair.first;
2638 break;
2639 }
2640 }
2641 if (ToDrop == nullptr)
2642 break;
2643 RhsDeps.erase(Key: ToDrop);
2644 }
2645
2646 for (const auto &InsPair : RhsDeps) {
2647 // Finally accumulate latency that we can only attribute to computing the
2648 // RHS condition. Use latency because we are essentially trying to calculate
2649 // the cost of the dependency chain.
2650 // Possible TODO: We could try to estimate ILP and make this more precise.
2651 CostOfIncluding += TTI->getInstructionCost(
2652 U: InsPair.first, CostKind: TargetTransformInfo::TCK_Latency);
2653
2654 if (CostOfIncluding > CostThresh)
2655 return false;
2656 }
2657 return true;
2658}
2659
2660void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
2661 MachineBasicBlock *TBB,
2662 MachineBasicBlock *FBB,
2663 MachineBasicBlock *CurBB,
2664 MachineBasicBlock *SwitchBB,
2665 Instruction::BinaryOps Opc,
2666 BranchProbability TProb,
2667 BranchProbability FProb,
2668 bool InvertCond) {
2669 // Skip over not part of the tree and remember to invert op and operands at
2670 // next level.
2671 Value *NotCond;
2672 if (match(V: Cond, P: m_OneUse(SubPattern: m_Not(V: m_Value(V&: NotCond)))) &&
2673 InBlock(V: NotCond, BB: CurBB->getBasicBlock())) {
2674 FindMergedConditions(Cond: NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
2675 InvertCond: !InvertCond);
2676 return;
2677 }
2678
2679 const Instruction *BOp = dyn_cast<Instruction>(Val: Cond);
2680 const Value *BOpOp0, *BOpOp1;
2681 // Compute the effective opcode for Cond, taking into account whether it needs
2682 // to be inverted, e.g.
2683 // and (not (or A, B)), C
2684 // gets lowered as
2685 // and (and (not A, not B), C)
2686 Instruction::BinaryOps BOpc = (Instruction::BinaryOps)0;
2687 if (BOp) {
2688 BOpc = match(V: BOp, P: m_LogicalAnd(L: m_Value(V&: BOpOp0), R: m_Value(V&: BOpOp1)))
2689 ? Instruction::And
2690 : (match(V: BOp, P: m_LogicalOr(L: m_Value(V&: BOpOp0), R: m_Value(V&: BOpOp1)))
2691 ? Instruction::Or
2692 : (Instruction::BinaryOps)0);
2693 if (InvertCond) {
2694 if (BOpc == Instruction::And)
2695 BOpc = Instruction::Or;
2696 else if (BOpc == Instruction::Or)
2697 BOpc = Instruction::And;
2698 }
2699 }
2700
2701 // If this node is not part of the or/and tree, emit it as a branch.
2702 // Note that all nodes in the tree should have same opcode.
2703 bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->hasOneUse();
2704 if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() ||
2705 !InBlock(V: BOpOp0, BB: CurBB->getBasicBlock()) ||
2706 !InBlock(V: BOpOp1, BB: CurBB->getBasicBlock())) {
2707 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
2708 TProb, FProb, InvertCond);
2709 return;
2710 }
2711
2712 // Create TmpBB after CurBB.
2713 MachineFunction::iterator BBI(CurBB);
2714 MachineFunction &MF = DAG.getMachineFunction();
2715 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(BB: CurBB->getBasicBlock());
2716 CurBB->getParent()->insert(MBBI: ++BBI, MBB: TmpBB);
2717
2718 if (Opc == Instruction::Or) {
2719 // Codegen X | Y as:
2720 // BB1:
2721 // jmp_if_X TBB
2722 // jmp TmpBB
2723 // TmpBB:
2724 // jmp_if_Y TBB
2725 // jmp FBB
2726 //
2727
2728 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2729 // The requirement is that
2730 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
2731 // = TrueProb for original BB.
2732 // Assuming the original probabilities are A and B, one choice is to set
2733 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
2734 // A/(1+B) and 2B/(1+B). This choice assumes that
2735 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
2736 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
2737 // TmpBB, but the math is more complicated.
2738
2739 auto NewTrueProb = TProb / 2;
2740 auto NewFalseProb = TProb / 2 + FProb;
2741 // Emit the LHS condition.
2742 FindMergedConditions(Cond: BOpOp0, TBB, FBB: TmpBB, CurBB, SwitchBB, Opc, TProb: NewTrueProb,
2743 FProb: NewFalseProb, InvertCond);
2744
2745 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
2746 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
2747 BranchProbability::normalizeProbabilities(Begin: Probs.begin(), End: Probs.end());
2748 // Emit the RHS condition into TmpBB.
2749 FindMergedConditions(Cond: BOpOp1, TBB, FBB, CurBB: TmpBB, SwitchBB, Opc, TProb: Probs[0],
2750 FProb: Probs[1], InvertCond);
2751 } else {
2752 assert(Opc == Instruction::And && "Unknown merge op!");
2753 // Codegen X & Y as:
2754 // BB1:
2755 // jmp_if_X TmpBB
2756 // jmp FBB
2757 // TmpBB:
2758 // jmp_if_Y TBB
2759 // jmp FBB
2760 //
2761 // This requires creation of TmpBB after CurBB.
2762
2763 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2764 // The requirement is that
2765 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
2766 // = FalseProb for original BB.
2767 // Assuming the original probabilities are A and B, one choice is to set
2768 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
2769 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
2770 // TrueProb for BB1 * FalseProb for TmpBB.
2771
2772 auto NewTrueProb = TProb + FProb / 2;
2773 auto NewFalseProb = FProb / 2;
2774 // Emit the LHS condition.
2775 FindMergedConditions(Cond: BOpOp0, TBB: TmpBB, FBB, CurBB, SwitchBB, Opc, TProb: NewTrueProb,
2776 FProb: NewFalseProb, InvertCond);
2777
2778 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
2779 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
2780 BranchProbability::normalizeProbabilities(Begin: Probs.begin(), End: Probs.end());
2781 // Emit the RHS condition into TmpBB.
2782 FindMergedConditions(Cond: BOpOp1, TBB, FBB, CurBB: TmpBB, SwitchBB, Opc, TProb: Probs[0],
2783 FProb: Probs[1], InvertCond);
2784 }
2785}
2786
2787/// If the set of cases should be emitted as a series of branches, return true.
2788/// If we should emit this as a bunch of and/or'd together conditions, return
2789/// false.
2790bool
2791SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
2792 if (Cases.size() != 2) return true;
2793
2794 // If this is two comparisons of the same values or'd or and'd together, they
2795 // will get folded into a single comparison, so don't emit two blocks.
2796 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2797 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2798 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2799 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2800 return false;
2801 }
2802
2803 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
2804 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
2805 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2806 Cases[0].CC == Cases[1].CC &&
2807 isa<Constant>(Val: Cases[0].CmpRHS) &&
2808 cast<Constant>(Val: Cases[0].CmpRHS)->isNullValue()) {
2809 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2810 return false;
2811 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2812 return false;
2813 }
2814
2815 return true;
2816}
2817
2818void SelectionDAGBuilder::visitUncondBr(const UncondBrInst &I) {
2819 MachineBasicBlock *BrMBB = FuncInfo.MBB;
2820
2821 MachineBasicBlock *Succ0MBB = FuncInfo.getMBB(BB: I.getSuccessor(i: 0));
2822
2823 // Update machine-CFG edges.
2824 BrMBB->addSuccessor(Succ: Succ0MBB);
2825
2826 // If this is not a fall-through branch or optimizations are switched off,
2827 // emit the branch.
2828 if (Succ0MBB != NextBlock(MBB: BrMBB) ||
2829 TM.getOptLevel() == CodeGenOptLevel::None) {
2830 auto Br = DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(), VT: MVT::Other, N1: getControlRoot(),
2831 N2: DAG.getBasicBlock(MBB: Succ0MBB));
2832 setValue(V: &I, NewN: Br);
2833 DAG.setRoot(Br);
2834 }
2835}
2836
2837void SelectionDAGBuilder::visitCondBr(const CondBrInst &I) {
2838 MachineBasicBlock *BrMBB = FuncInfo.MBB;
2839
2840 MachineBasicBlock *Succ0MBB = FuncInfo.getMBB(BB: I.getSuccessor(i: 0));
2841
2842 // If this condition is one of the special cases we handle, do special stuff
2843 // now.
2844 const Value *CondVal = I.getCondition();
2845 MachineBasicBlock *Succ1MBB = FuncInfo.getMBB(BB: I.getSuccessor(i: 1));
2846
2847 // If this is a series of conditions that are or'd or and'd together, emit
2848 // this as a sequence of branches instead of setcc's with and/or operations.
2849 // As long as jumps are not expensive (exceptions for multi-use logic ops,
2850 // unpredictable branches, and vector extracts because those jumps are likely
2851 // expensive for any target), this should improve performance.
2852 // For example, instead of something like:
2853 // cmp A, B
2854 // C = seteq
2855 // cmp D, E
2856 // F = setle
2857 // or C, F
2858 // jnz foo
2859 // Emit:
2860 // cmp A, B
2861 // je foo
2862 // cmp D, E
2863 // jle foo
2864 bool IsUnpredictable = I.hasMetadata(KindID: LLVMContext::MD_unpredictable);
2865 const Instruction *BOp = dyn_cast<Instruction>(Val: CondVal);
2866 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp &&
2867 BOp->hasOneUse() && !IsUnpredictable) {
2868 Value *Vec;
2869 const Value *BOp0, *BOp1;
2870 Instruction::BinaryOps Opcode = (Instruction::BinaryOps)0;
2871 if (match(V: BOp, P: m_LogicalAnd(L: m_Value(V&: BOp0), R: m_Value(V&: BOp1))))
2872 Opcode = Instruction::And;
2873 else if (match(V: BOp, P: m_LogicalOr(L: m_Value(V&: BOp0), R: m_Value(V&: BOp1))))
2874 Opcode = Instruction::Or;
2875
2876 if (Opcode &&
2877 !(match(V: BOp0, P: m_ExtractElt(Val: m_Value(V&: Vec), Idx: m_Value())) &&
2878 match(V: BOp1, P: m_ExtractElt(Val: m_Specific(V: Vec), Idx: m_Value()))) &&
2879 !shouldKeepJumpConditionsTogether(
2880 FuncInfo, I, Opc: Opcode, Lhs: BOp0, Rhs: BOp1,
2881 Params: DAG.getTargetLoweringInfo().getJumpConditionMergingParams(
2882 Opcode, BOp0, BOp1, FuncInfo.Fn))) {
2883 FindMergedConditions(Cond: BOp, TBB: Succ0MBB, FBB: Succ1MBB, CurBB: BrMBB, SwitchBB: BrMBB, Opc: Opcode,
2884 TProb: getEdgeProbability(Src: BrMBB, Dst: Succ0MBB),
2885 FProb: getEdgeProbability(Src: BrMBB, Dst: Succ1MBB),
2886 /*InvertCond=*/false);
2887 // If the compares in later blocks need to use values not currently
2888 // exported from this block, export them now. This block should always
2889 // be the first entry.
2890 assert(SL->SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
2891
2892 // Allow some cases to be rejected.
2893 if (ShouldEmitAsBranches(Cases: SL->SwitchCases)) {
2894 for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) {
2895 ExportFromCurrentBlock(V: SL->SwitchCases[i].CmpLHS);
2896 ExportFromCurrentBlock(V: SL->SwitchCases[i].CmpRHS);
2897 }
2898
2899 // Emit the branch for this block.
2900 visitSwitchCase(CB&: SL->SwitchCases[0], SwitchBB: BrMBB);
2901 SL->SwitchCases.erase(position: SL->SwitchCases.begin());
2902 return;
2903 }
2904
2905 // Okay, we decided not to do this, remove any inserted MBB's and clear
2906 // SwitchCases.
2907 for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i)
2908 FuncInfo.MF->erase(MBBI: SL->SwitchCases[i].ThisBB);
2909
2910 SL->SwitchCases.clear();
2911 }
2912 }
2913
2914 // Create a CaseBlock record representing this branch.
2915 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(Context&: *DAG.getContext()),
2916 nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc(),
2917 BranchProbability::getUnknown(), BranchProbability::getUnknown(),
2918 IsUnpredictable);
2919
2920 // Use visitSwitchCase to actually insert the fast branch sequence for this
2921 // cond branch.
2922 visitSwitchCase(CB, SwitchBB: BrMBB);
2923}
2924
2925/// visitSwitchCase - Emits the necessary code to represent a single node in
2926/// the binary search tree resulting from lowering a switch instruction.
2927void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
2928 MachineBasicBlock *SwitchBB) {
2929 SDValue Cond;
2930 SDValue CondLHS = getValue(V: CB.CmpLHS);
2931 SDLoc dl = CB.DL;
2932
2933 if (CB.CC == ISD::SETTRUE) {
2934 // Branch or fall through to TrueBB.
2935 addSuccessorWithProb(Src: SwitchBB, Dst: CB.TrueBB, Prob: CB.TrueProb);
2936 SwitchBB->normalizeSuccProbs();
2937 if (CB.TrueBB != NextBlock(MBB: SwitchBB)) {
2938 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: getControlRoot(),
2939 N2: DAG.getBasicBlock(MBB: CB.TrueBB)));
2940 }
2941 return;
2942 }
2943
2944 auto &TLI = DAG.getTargetLoweringInfo();
2945 EVT MemVT = TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: CB.CmpLHS->getType());
2946
2947 // Build the setcc now.
2948 if (!CB.CmpMHS) {
2949 // Fold "(X == true)" to X and "(X == false)" to !X to
2950 // handle common cases produced by branch lowering.
2951 if (CB.CmpRHS == ConstantInt::getTrue(Context&: *DAG.getContext()) &&
2952 CB.CC == ISD::SETEQ)
2953 Cond = CondLHS;
2954 else if (CB.CmpRHS == ConstantInt::getFalse(Context&: *DAG.getContext()) &&
2955 CB.CC == ISD::SETEQ) {
2956 SDValue True = DAG.getConstant(Val: 1, DL: dl, VT: CondLHS.getValueType());
2957 Cond = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: CondLHS.getValueType(), N1: CondLHS, N2: True);
2958 } else {
2959 SDValue CondRHS = getValue(V: CB.CmpRHS);
2960
2961 // If a pointer's DAG type is larger than its memory type then the DAG
2962 // values are zero-extended. This breaks signed comparisons so truncate
2963 // back to the underlying type before doing the compare.
2964 if (CondLHS.getValueType() != MemVT) {
2965 CondLHS = DAG.getPtrExtOrTrunc(Op: CondLHS, DL: getCurSDLoc(), VT: MemVT);
2966 CondRHS = DAG.getPtrExtOrTrunc(Op: CondRHS, DL: getCurSDLoc(), VT: MemVT);
2967 }
2968 Cond = DAG.getSetCC(DL: dl, VT: MVT::i1, LHS: CondLHS, RHS: CondRHS, Cond: CB.CC);
2969 }
2970 } else {
2971 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
2972
2973 const APInt& Low = cast<ConstantInt>(Val: CB.CmpLHS)->getValue();
2974 const APInt& High = cast<ConstantInt>(Val: CB.CmpRHS)->getValue();
2975
2976 SDValue CmpOp = getValue(V: CB.CmpMHS);
2977 EVT VT = CmpOp.getValueType();
2978
2979 if (cast<ConstantInt>(Val: CB.CmpLHS)->isMinValue(IsSigned: true)) {
2980 Cond = DAG.getSetCC(DL: dl, VT: MVT::i1, LHS: CmpOp, RHS: DAG.getConstant(Val: High, DL: dl, VT),
2981 Cond: ISD::SETLE);
2982 } else {
2983 SDValue SUB = DAG.getNode(Opcode: ISD::SUB, DL: dl,
2984 VT, N1: CmpOp, N2: DAG.getConstant(Val: Low, DL: dl, VT));
2985 Cond = DAG.getSetCC(DL: dl, VT: MVT::i1, LHS: SUB,
2986 RHS: DAG.getConstant(Val: High-Low, DL: dl, VT), Cond: ISD::SETULE);
2987 }
2988 }
2989
2990 // Update successor info
2991 addSuccessorWithProb(Src: SwitchBB, Dst: CB.TrueBB, Prob: CB.TrueProb);
2992 // TrueBB and FalseBB are always different unless the incoming IR is
2993 // degenerate. This only happens when running llc on weird IR.
2994 if (CB.TrueBB != CB.FalseBB)
2995 addSuccessorWithProb(Src: SwitchBB, Dst: CB.FalseBB, Prob: CB.FalseProb);
2996 SwitchBB->normalizeSuccProbs();
2997
2998 // If the lhs block is the next block, invert the condition so that we can
2999 // fall through to the lhs instead of the rhs block.
3000 if (CB.TrueBB == NextBlock(MBB: SwitchBB)) {
3001 std::swap(a&: CB.TrueBB, b&: CB.FalseBB);
3002 SDValue True = DAG.getConstant(Val: 1, DL: dl, VT: Cond.getValueType());
3003 Cond = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: Cond.getValueType(), N1: Cond, N2: True);
3004 }
3005
3006 SDNodeFlags Flags;
3007 Flags.setUnpredictable(CB.IsUnpredictable);
3008 SDValue BrCond = DAG.getNode(Opcode: ISD::BRCOND, DL: dl, VT: MVT::Other, N1: getControlRoot(),
3009 N2: Cond, N3: DAG.getBasicBlock(MBB: CB.TrueBB), Flags);
3010
3011 setValue(V: CurInst, NewN: BrCond);
3012
3013 // Insert the false branch. Do this even if it's a fall through branch,
3014 // this makes it easier to do DAG optimizations which require inverting
3015 // the branch condition.
3016 BrCond = DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: BrCond,
3017 N2: DAG.getBasicBlock(MBB: CB.FalseBB));
3018
3019 DAG.setRoot(BrCond);
3020}
3021
3022/// visitJumpTable - Emit JumpTable node in the current MBB
3023void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) {
3024 // Emit the code for the jump table
3025 assert(JT.SL && "Should set SDLoc for SelectionDAG!");
3026 assert(JT.Reg && "Should lower JT Header first!");
3027 EVT PTy = DAG.getTargetLoweringInfo().getJumpTableRegTy(DL: DAG.getDataLayout());
3028 SDValue Index = DAG.getCopyFromReg(Chain: getControlRoot(), dl: *JT.SL, Reg: JT.Reg, VT: PTy);
3029 SDValue Table = DAG.getJumpTable(JTI: JT.JTI, VT: PTy);
3030 SDValue BrJumpTable = DAG.getNode(Opcode: ISD::BR_JT, DL: *JT.SL, VT: MVT::Other,
3031 N1: Index.getValue(R: 1), N2: Table, N3: Index);
3032 DAG.setRoot(BrJumpTable);
3033}
3034
3035/// visitJumpTableHeader - This function emits necessary code to produce index
3036/// in the JumpTable from switch case.
3037void SelectionDAGBuilder::visitJumpTableHeader(SwitchCG::JumpTable &JT,
3038 JumpTableHeader &JTH,
3039 MachineBasicBlock *SwitchBB) {
3040 assert(JT.SL && "Should set SDLoc for SelectionDAG!");
3041 const SDLoc &dl = *JT.SL;
3042
3043 // Subtract the lowest switch case value from the value being switched on.
3044 SDValue SwitchOp = getValue(V: JTH.SValue);
3045 EVT VT = SwitchOp.getValueType();
3046 SDValue Sub = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: SwitchOp,
3047 N2: DAG.getConstant(Val: JTH.First, DL: dl, VT));
3048
3049 // The SDNode we just created, which holds the value being switched on minus
3050 // the smallest case value, needs to be copied to a virtual register so it
3051 // can be used as an index into the jump table in a subsequent basic block.
3052 // This value may be smaller or larger than the target's pointer type, and
3053 // therefore require extension or truncating.
3054 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3055 SwitchOp =
3056 DAG.getZExtOrTrunc(Op: Sub, DL: dl, VT: TLI.getJumpTableRegTy(DL: DAG.getDataLayout()));
3057
3058 Register JumpTableReg =
3059 FuncInfo.CreateReg(VT: TLI.getJumpTableRegTy(DL: DAG.getDataLayout()));
3060 SDValue CopyTo =
3061 DAG.getCopyToReg(Chain: getControlRoot(), dl, Reg: JumpTableReg, N: SwitchOp);
3062 JT.Reg = JumpTableReg;
3063
3064 if (!JTH.FallthroughUnreachable) {
3065 // Emit the range check for the jump table, and branch to the default block
3066 // for the switch statement if the value being switched on exceeds the
3067 // largest case in the switch.
3068 SDValue CMP = DAG.getSetCC(
3069 DL: dl, VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(),
3070 VT: Sub.getValueType()),
3071 LHS: Sub, RHS: DAG.getConstant(Val: JTH.Last - JTH.First, DL: dl, VT), Cond: ISD::SETUGT);
3072
3073 SDValue BrCond = DAG.getNode(Opcode: ISD::BRCOND, DL: dl,
3074 VT: MVT::Other, N1: CopyTo, N2: CMP,
3075 N3: DAG.getBasicBlock(MBB: JT.Default));
3076
3077 // Avoid emitting unnecessary branches to the next block.
3078 if (JT.MBB != NextBlock(MBB: SwitchBB))
3079 BrCond = DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: BrCond,
3080 N2: DAG.getBasicBlock(MBB: JT.MBB));
3081
3082 DAG.setRoot(BrCond);
3083 } else {
3084 // Avoid emitting unnecessary branches to the next block.
3085 if (JT.MBB != NextBlock(MBB: SwitchBB))
3086 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: CopyTo,
3087 N2: DAG.getBasicBlock(MBB: JT.MBB)));
3088 else
3089 DAG.setRoot(CopyTo);
3090 }
3091}
3092
3093/// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
3094/// variable if there exists one.
3095static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL,
3096 SDValue &Chain) {
3097 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3098 EVT PtrTy = TLI.getPointerTy(DL: DAG.getDataLayout());
3099 EVT PtrMemTy = TLI.getPointerMemTy(DL: DAG.getDataLayout());
3100 MachineFunction &MF = DAG.getMachineFunction();
3101 Value *Global =
3102 TLI.getSDagStackGuard(M: *MF.getFunction().getParent(), Libcalls: DAG.getLibcalls());
3103 MachineSDNode *Node =
3104 DAG.getMachineNode(Opcode: TargetOpcode::LOAD_STACK_GUARD, dl: DL, VT: PtrTy, Op1: Chain);
3105 if (Global) {
3106 MachinePointerInfo MPInfo(Global);
3107 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
3108 MachineMemOperand::MODereferenceable;
3109 MachineMemOperand *MemRef = MF.getMachineMemOperand(
3110 PtrInfo: MPInfo, F: Flags, Size: PtrTy.getSizeInBits() / 8, BaseAlignment: DAG.getEVTAlign(MemoryVT: PtrTy));
3111 DAG.setNodeMemRefs(N: Node, NewMemRefs: {MemRef});
3112 }
3113 if (PtrTy != PtrMemTy)
3114 return DAG.getPtrExtOrTrunc(Op: SDValue(Node, 0), DL, VT: PtrMemTy);
3115 return SDValue(Node, 0);
3116}
3117
3118/// Codegen a new tail for a stack protector check ParentMBB which has had its
3119/// tail spliced into a stack protector check success bb.
3120///
3121/// For a high level explanation of how this fits into the stack protector
3122/// generation see the comment on the declaration of class
3123/// StackProtectorDescriptor.
3124void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
3125 MachineBasicBlock *ParentBB) {
3126
3127 // First create the loads to the guard/stack slot for the comparison.
3128 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3129 auto &DL = DAG.getDataLayout();
3130 EVT PtrTy = TLI.getFrameIndexTy(DL);
3131 EVT PtrMemTy = TLI.getPointerMemTy(DL, AS: DL.getAllocaAddrSpace());
3132
3133 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
3134 int FI = MFI.getStackProtectorIndex();
3135
3136 SDValue Guard;
3137 SDLoc dl = getCurSDLoc();
3138 SDValue StackSlotPtr = DAG.getFrameIndex(FI, VT: PtrTy);
3139 const Module &M = *ParentBB->getParent()->getFunction().getParent();
3140 Align Align = DL.getPrefTypeAlign(
3141 Ty: PointerType::get(C&: M.getContext(), AddressSpace: DL.getAllocaAddrSpace()));
3142
3143 // Generate code to load the content of the guard slot.
3144 SDValue GuardVal = DAG.getLoad(
3145 VT: PtrMemTy, dl, Chain: DAG.getEntryNode(), Ptr: StackSlotPtr,
3146 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI), Alignment: Align,
3147 MMOFlags: MachineMemOperand::MOVolatile);
3148
3149 // If cookie mixing is enabled, unmix the stored GuardVal to get back the
3150 // original cookie for comparison. The prologue stored (FP - Cookie) or
3151 // (FP XOR Cookie), so we apply the same operation again to unmix:
3152 // FP - (FP - Cookie) = Cookie, or (FP XOR Cookie) XOR FP = Cookie.
3153 if (TLI.useStackGuardMixFP())
3154 GuardVal = TLI.emitStackGuardMixFP(DAG, Val: GuardVal, DL: dl);
3155
3156 // If we're using function-based instrumentation, call the guard check
3157 // function
3158 if (SPD.shouldEmitFunctionBasedCheckStackProtector()) {
3159 // Get the guard check function from the target and verify it exists since
3160 // we're using function-based instrumentation
3161 const Function *GuardCheckFn =
3162 TLI.getSSPStackGuardCheck(M, Libcalls: DAG.getLibcalls());
3163 assert(GuardCheckFn && "Guard check function is null");
3164
3165 // The target provides a guard check function to validate the guard value.
3166 // Generate a call to that function with the content of the guard slot as
3167 // argument.
3168 FunctionType *FnTy = GuardCheckFn->getFunctionType();
3169 assert(FnTy->getNumParams() == 1 && "Invalid function signature");
3170
3171 TargetLowering::ArgListTy Args;
3172 TargetLowering::ArgListEntry Entry(GuardVal, FnTy->getParamType(i: 0));
3173 if (GuardCheckFn->hasParamAttribute(ArgNo: 0, Kind: Attribute::AttrKind::InReg))
3174 Entry.IsInReg = true;
3175 Args.push_back(x: Entry);
3176
3177 TargetLowering::CallLoweringInfo CLI(DAG);
3178 CLI.setDebugLoc(getCurSDLoc())
3179 .setChain(DAG.getEntryNode())
3180 .setCallee(CC: GuardCheckFn->getCallingConv(), ResultType: FnTy->getReturnType(),
3181 Target: getValue(V: GuardCheckFn), ArgsList: std::move(Args));
3182
3183 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
3184 DAG.setRoot(Result.second);
3185 return;
3186 }
3187
3188 // Load the fresh guard value for comparison.
3189 // For targets that mix the cookie in LOAD_STACK_GUARD expansion, we need to
3190 // load directly without using LOAD_STACK_GUARD to avoid unwanted mixing.
3191 SDValue Chain = DAG.getEntryNode();
3192 if (TLI.useStackGuardMixFP()) {
3193 // Mixing targets: load cookie directly to avoid mixing in LOAD_STACK_GUARD
3194 if (const Value *IRGuard = TLI.getSDagStackGuard(M, Libcalls: DAG.getLibcalls())) {
3195 SDValue GuardPtr = getValue(V: IRGuard);
3196 Guard = DAG.getLoad(VT: PtrMemTy, dl, Chain, Ptr: GuardPtr,
3197 PtrInfo: MachinePointerInfo(IRGuard, 0), Alignment: Align,
3198 MMOFlags: MachineMemOperand::MOVolatile);
3199 } else {
3200 LLVMContext &Ctx = *DAG.getContext();
3201 Ctx.diagnose(DI: DiagnosticInfoGeneric("unable to lower stackguard"));
3202 Guard = DAG.getPOISON(VT: PtrMemTy);
3203 }
3204 } else {
3205 // Non-mixing targets: use LOAD_STACK_GUARD or direct load as usual
3206 if (TLI.useLoadStackGuardNode(M)) {
3207 Guard = getLoadStackGuard(DAG, DL: dl, Chain);
3208 } else {
3209 if (const Value *IRGuard = TLI.getSDagStackGuard(M, Libcalls: DAG.getLibcalls())) {
3210 SDValue GuardPtr = getValue(V: IRGuard);
3211 Guard = DAG.getLoad(VT: PtrMemTy, dl, Chain, Ptr: GuardPtr,
3212 PtrInfo: MachinePointerInfo(IRGuard, 0), Alignment: Align,
3213 MMOFlags: MachineMemOperand::MOVolatile);
3214 } else {
3215 LLVMContext &Ctx = *DAG.getContext();
3216 Ctx.diagnose(DI: DiagnosticInfoGeneric("unable to lower stackguard"));
3217 Guard = DAG.getPOISON(VT: PtrMemTy);
3218 }
3219 }
3220 }
3221
3222 // Now both Guard (fresh cookie) and GuardVal (unmixed from stored value)
3223 // contain unmixed cookie values that can be compared directly.
3224
3225 // Perform the comparison via a getsetcc.
3226 SDValue Cmp = DAG.getSetCC(
3227 DL: dl, VT: TLI.getSetCCResultType(DL, Context&: *DAG.getContext(), VT: Guard.getValueType()),
3228 LHS: Guard, RHS: GuardVal, Cond: ISD::SETNE);
3229
3230 // If the guard/stackslot do not equal, branch to failure MBB.
3231 SDValue BrCond = DAG.getNode(Opcode: ISD::BRCOND, DL: dl, VT: MVT::Other, N1: getControlRoot(),
3232 N2: Cmp, N3: DAG.getBasicBlock(MBB: SPD.getFailureMBB()));
3233 // Otherwise branch to success MBB.
3234 SDValue Br = DAG.getNode(Opcode: ISD::BR, DL: dl,
3235 VT: MVT::Other, N1: BrCond,
3236 N2: DAG.getBasicBlock(MBB: SPD.getSuccessMBB()));
3237
3238 DAG.setRoot(Br);
3239}
3240
3241/// Codegen the failure basic block for a stack protector check.
3242///
3243/// A failure stack protector machine basic block consists simply of a call to
3244/// __stack_chk_fail().
3245///
3246/// For a high level explanation of how this fits into the stack protector
3247/// generation see the comment on the declaration of class
3248/// StackProtectorDescriptor.
3249void SelectionDAGBuilder::visitSPDescriptorFailure(
3250 StackProtectorDescriptor &SPD) {
3251
3252 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3253 MachineBasicBlock *ParentBB = SPD.getParentMBB();
3254 const Module &M = *ParentBB->getParent()->getFunction().getParent();
3255 SDValue Chain;
3256
3257 // For -Oz builds with a guard check function, we use function-based
3258 // instrumentation. Otherwise, if we have a guard check function, we call it
3259 // in the failure block.
3260 auto *GuardCheckFn = TLI.getSSPStackGuardCheck(M, Libcalls: DAG.getLibcalls());
3261 if (GuardCheckFn && !SPD.shouldEmitFunctionBasedCheckStackProtector()) {
3262 // First create the loads to the guard/stack slot for the comparison.
3263 auto &DL = DAG.getDataLayout();
3264 EVT PtrTy = TLI.getFrameIndexTy(DL);
3265 EVT PtrMemTy = TLI.getPointerMemTy(DL, AS: DL.getAllocaAddrSpace());
3266
3267 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
3268 int FI = MFI.getStackProtectorIndex();
3269
3270 SDLoc dl = getCurSDLoc();
3271 SDValue StackSlotPtr = DAG.getFrameIndex(FI, VT: PtrTy);
3272 Align Align = DL.getPrefTypeAlign(
3273 Ty: PointerType::get(C&: M.getContext(), AddressSpace: DL.getAllocaAddrSpace()));
3274
3275 // Generate code to load the content of the guard slot.
3276 SDValue GuardVal = DAG.getLoad(
3277 VT: PtrMemTy, dl, Chain: DAG.getEntryNode(), Ptr: StackSlotPtr,
3278 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI), Alignment: Align,
3279 MMOFlags: MachineMemOperand::MOVolatile);
3280
3281 if (TLI.useStackGuardMixFP())
3282 GuardVal = TLI.emitStackGuardMixFP(DAG, Val: GuardVal, DL: dl);
3283
3284 // The target provides a guard check function to validate the guard value.
3285 // Generate a call to that function with the content of the guard slot as
3286 // argument.
3287 FunctionType *FnTy = GuardCheckFn->getFunctionType();
3288 assert(FnTy->getNumParams() == 1 && "Invalid function signature");
3289
3290 TargetLowering::ArgListTy Args;
3291 TargetLowering::ArgListEntry Entry(GuardVal, FnTy->getParamType(i: 0));
3292 if (GuardCheckFn->hasParamAttribute(ArgNo: 0, Kind: Attribute::AttrKind::InReg))
3293 Entry.IsInReg = true;
3294 Args.push_back(x: Entry);
3295
3296 TargetLowering::CallLoweringInfo CLI(DAG);
3297 CLI.setDebugLoc(getCurSDLoc())
3298 .setChain(DAG.getEntryNode())
3299 .setCallee(CC: GuardCheckFn->getCallingConv(), ResultType: FnTy->getReturnType(),
3300 Target: getValue(V: GuardCheckFn), ArgsList: std::move(Args));
3301
3302 Chain = TLI.LowerCallTo(CLI).second;
3303 } else {
3304 TargetLowering::MakeLibCallOptions CallOptions;
3305 CallOptions.setDiscardResult(true);
3306 Chain = TLI.makeLibCall(DAG, LC: RTLIB::STACKPROTECTOR_CHECK_FAIL, RetVT: MVT::isVoid,
3307 Ops: {}, CallOptions, dl: getCurSDLoc())
3308 .second;
3309 }
3310
3311 // Emit a trap instruction if we are required to do so.
3312 const TargetOptions &TargetOpts = DAG.getTarget().Options;
3313 if (TargetOpts.TrapUnreachable && !TargetOpts.NoTrapAfterNoreturn)
3314 Chain = DAG.getNode(Opcode: ISD::TRAP, DL: getCurSDLoc(), VT: MVT::Other, Operand: Chain);
3315
3316 DAG.setRoot(Chain);
3317}
3318
3319/// visitBitTestHeader - This function emits necessary code to produce value
3320/// suitable for "bit tests"
3321void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
3322 MachineBasicBlock *SwitchBB) {
3323 SDLoc dl = getCurSDLoc();
3324
3325 // Subtract the minimum value.
3326 SDValue SwitchOp = getValue(V: B.SValue);
3327 EVT VT = SwitchOp.getValueType();
3328 SDValue RangeSub =
3329 DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: SwitchOp, N2: DAG.getConstant(Val: B.First, DL: dl, VT));
3330
3331 // Determine the type of the test operands.
3332 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3333 bool UsePtrType = false;
3334 if (!TLI.isTypeLegal(VT)) {
3335 UsePtrType = true;
3336 } else {
3337 for (const BitTestCase &Case : B.Cases)
3338 if (!isUIntN(N: VT.getSizeInBits(), x: Case.Mask)) {
3339 // Switch table case range are encoded into series of masks.
3340 // Just use pointer type, it's guaranteed to fit.
3341 UsePtrType = true;
3342 break;
3343 }
3344 }
3345 SDValue Sub = RangeSub;
3346 if (UsePtrType) {
3347 VT = TLI.getPointerTy(DL: DAG.getDataLayout());
3348 Sub = DAG.getZExtOrTrunc(Op: Sub, DL: dl, VT);
3349 }
3350
3351 B.RegVT = VT.getSimpleVT();
3352 B.Reg = FuncInfo.CreateReg(VT: B.RegVT);
3353 SDValue CopyTo = DAG.getCopyToReg(Chain: getControlRoot(), dl, Reg: B.Reg, N: Sub);
3354
3355 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
3356
3357 if (!B.FallthroughUnreachable)
3358 addSuccessorWithProb(Src: SwitchBB, Dst: B.Default, Prob: B.DefaultProb);
3359 addSuccessorWithProb(Src: SwitchBB, Dst: MBB, Prob: B.Prob);
3360 SwitchBB->normalizeSuccProbs();
3361
3362 SDValue Root = CopyTo;
3363 if (!B.FallthroughUnreachable) {
3364 // Conditional branch to the default block.
3365 SDValue RangeCmp = DAG.getSetCC(DL: dl,
3366 VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(),
3367 VT: RangeSub.getValueType()),
3368 LHS: RangeSub, RHS: DAG.getConstant(Val: B.Range, DL: dl, VT: RangeSub.getValueType()),
3369 Cond: ISD::SETUGT);
3370
3371 Root = DAG.getNode(Opcode: ISD::BRCOND, DL: dl, VT: MVT::Other, N1: Root, N2: RangeCmp,
3372 N3: DAG.getBasicBlock(MBB: B.Default));
3373 }
3374
3375 // Avoid emitting unnecessary branches to the next block.
3376 if (MBB != NextBlock(MBB: SwitchBB))
3377 Root = DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: Root, N2: DAG.getBasicBlock(MBB));
3378
3379 DAG.setRoot(Root);
3380}
3381
3382/// visitBitTestCase - this function produces one "bit test"
3383void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
3384 MachineBasicBlock *NextMBB,
3385 BranchProbability BranchProbToNext,
3386 Register Reg, BitTestCase &B,
3387 MachineBasicBlock *SwitchBB) {
3388 SDLoc dl = getCurSDLoc();
3389 MVT VT = BB.RegVT;
3390 SDValue ShiftOp = DAG.getCopyFromReg(Chain: getControlRoot(), dl, Reg, VT);
3391 SDValue Cmp;
3392 unsigned PopCount = llvm::popcount(Value: B.Mask);
3393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3394 if (PopCount == 1) {
3395 // Testing for a single bit; just compare the shift count with what it
3396 // would need to be to shift a 1 bit in that position.
3397 Cmp = DAG.getSetCC(
3398 DL: dl, VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT),
3399 LHS: ShiftOp, RHS: DAG.getConstant(Val: llvm::countr_zero(Val: B.Mask), DL: dl, VT),
3400 Cond: ISD::SETEQ);
3401 } else if (PopCount == BB.Range) {
3402 // There is only one zero bit in the range, test for it directly.
3403 Cmp = DAG.getSetCC(
3404 DL: dl, VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT),
3405 LHS: ShiftOp, RHS: DAG.getConstant(Val: llvm::countr_one(Value: B.Mask), DL: dl, VT), Cond: ISD::SETNE);
3406 } else {
3407 // Make desired shift
3408 SDValue SwitchVal = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT,
3409 N1: DAG.getConstant(Val: 1, DL: dl, VT), N2: ShiftOp);
3410
3411 // Emit bit tests and jumps
3412 SDValue AndOp = DAG.getNode(Opcode: ISD::AND, DL: dl,
3413 VT, N1: SwitchVal, N2: DAG.getConstant(Val: B.Mask, DL: dl, VT));
3414 Cmp = DAG.getSetCC(
3415 DL: dl, VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT),
3416 LHS: AndOp, RHS: DAG.getConstant(Val: 0, DL: dl, VT), Cond: ISD::SETNE);
3417 }
3418
3419 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
3420 addSuccessorWithProb(Src: SwitchBB, Dst: B.TargetBB, Prob: B.ExtraProb);
3421 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
3422 addSuccessorWithProb(Src: SwitchBB, Dst: NextMBB, Prob: BranchProbToNext);
3423 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
3424 // one as they are relative probabilities (and thus work more like weights),
3425 // and hence we need to normalize them to let the sum of them become one.
3426 SwitchBB->normalizeSuccProbs();
3427
3428 SDValue BrAnd = DAG.getNode(Opcode: ISD::BRCOND, DL: dl,
3429 VT: MVT::Other, N1: getControlRoot(),
3430 N2: Cmp, N3: DAG.getBasicBlock(MBB: B.TargetBB));
3431
3432 // Avoid emitting unnecessary branches to the next block.
3433 if (NextMBB != NextBlock(MBB: SwitchBB))
3434 BrAnd = DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: BrAnd,
3435 N2: DAG.getBasicBlock(MBB: NextMBB));
3436
3437 DAG.setRoot(BrAnd);
3438}
3439
3440void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
3441 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
3442
3443 // Retrieve successors. Look through artificial IR level blocks like
3444 // catchswitch for successors.
3445 MachineBasicBlock *Return = FuncInfo.getMBB(BB: I.getSuccessor(i: 0));
3446 const BasicBlock *EHPadBB = I.getSuccessor(i: 1);
3447 MachineBasicBlock *EHPadMBB = FuncInfo.getMBB(BB: EHPadBB);
3448
3449 // Deopt and ptrauth bundles are lowered in helper functions, and we don't
3450 // have to do anything here to lower funclet bundles.
3451 failForInvalidBundles(I, Name: "invokes",
3452 AllowedBundles: {LLVMContext::OB_deopt, LLVMContext::OB_gc_transition,
3453 LLVMContext::OB_gc_live, LLVMContext::OB_funclet,
3454 LLVMContext::OB_cfguardtarget, LLVMContext::OB_ptrauth,
3455 LLVMContext::OB_clang_arc_attachedcall,
3456 LLVMContext::OB_kcfi});
3457
3458 const Value *Callee(I.getCalledOperand());
3459 const Function *Fn = dyn_cast<Function>(Val: Callee);
3460 if (isa<InlineAsm>(Val: Callee))
3461 visitInlineAsm(Call: I, EHPadBB);
3462 else if (Fn && Fn->isIntrinsic()) {
3463 switch (Fn->getIntrinsicID()) {
3464 default:
3465 llvm_unreachable("Cannot invoke this intrinsic");
3466 case Intrinsic::donothing:
3467 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
3468 case Intrinsic::seh_try_begin:
3469 case Intrinsic::seh_scope_begin:
3470 case Intrinsic::seh_try_end:
3471 case Intrinsic::seh_scope_end:
3472 if (EHPadMBB)
3473 // a block referenced by EH table
3474 // so dtor-funclet not removed by opts
3475 EHPadMBB->setMachineBlockAddressTaken();
3476 break;
3477 case Intrinsic::experimental_patchpoint_void:
3478 case Intrinsic::experimental_patchpoint:
3479 visitPatchpoint(CB: I, EHPadBB);
3480 break;
3481 case Intrinsic::experimental_gc_statepoint:
3482 LowerStatepoint(I: cast<GCStatepointInst>(Val: I), EHPadBB);
3483 break;
3484 // wasm_throw, wasm_rethrow: This is usually done in visitTargetIntrinsic,
3485 // but these intrinsics are special because they can be invoked, so we
3486 // manually lower it to a DAG node here.
3487 case Intrinsic::wasm_throw: {
3488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3489 std::array<SDValue, 4> Ops = {
3490 getControlRoot(), // inchain for the terminator node
3491 DAG.getTargetConstant(Val: Intrinsic::wasm_throw, DL: getCurSDLoc(),
3492 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
3493 getValue(V: I.getArgOperand(i: 0)), // tag
3494 getValue(V: I.getArgOperand(i: 1)) // thrown value
3495 };
3496 SDVTList VTs = DAG.getVTList(VTs: ArrayRef<EVT>({MVT::Other})); // outchain
3497 DAG.setRoot(DAG.getNode(Opcode: ISD::INTRINSIC_VOID, DL: getCurSDLoc(), VTList: VTs, Ops));
3498 break;
3499 }
3500 case Intrinsic::wasm_rethrow: {
3501 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3502 std::array<SDValue, 2> Ops = {
3503 getControlRoot(), // inchain for the terminator node
3504 DAG.getTargetConstant(Val: Intrinsic::wasm_rethrow, DL: getCurSDLoc(),
3505 VT: TLI.getPointerTy(DL: DAG.getDataLayout()))};
3506 SDVTList VTs = DAG.getVTList(VTs: ArrayRef<EVT>({MVT::Other})); // outchain
3507 DAG.setRoot(DAG.getNode(Opcode: ISD::INTRINSIC_VOID, DL: getCurSDLoc(), VTList: VTs, Ops));
3508 break;
3509 }
3510 }
3511 } else if (I.hasDeoptState()) {
3512 // Currently we do not lower any intrinsic calls with deopt operand bundles.
3513 // Eventually we will support lowering the @llvm.experimental.deoptimize
3514 // intrinsic, and right now there are no plans to support other intrinsics
3515 // with deopt state.
3516 LowerCallSiteWithDeoptBundle(Call: &I, Callee: getValue(V: Callee), EHPadBB);
3517 } else if (I.countOperandBundlesOfType(ID: LLVMContext::OB_ptrauth)) {
3518 LowerCallSiteWithPtrAuthBundle(CB: cast<CallBase>(Val: I), EHPadBB);
3519 } else {
3520 LowerCallTo(CB: I, Callee: getValue(V: Callee), IsTailCall: false, IsMustTailCall: false, EHPadBB);
3521 }
3522
3523 // If the value of the invoke is used outside of its defining block, make it
3524 // available as a virtual register.
3525 // We already took care of the exported value for the statepoint instruction
3526 // during call to the LowerStatepoint.
3527 if (!isa<GCStatepointInst>(Val: I)) {
3528 CopyToExportRegsIfNeeded(V: &I);
3529 }
3530
3531 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
3532 BranchProbabilityInfo *BPI = FuncInfo.BPI;
3533 BranchProbability EHPadBBProb =
3534 BPI ? BPI->getEdgeProbability(Src: InvokeMBB->getBasicBlock(), Dst: EHPadBB)
3535 : BranchProbability::getZero();
3536 findUnwindDestinations(FuncInfo, EHPadBB, Prob: EHPadBBProb, UnwindDests);
3537
3538 // Update successor info.
3539 addSuccessorWithProb(Src: InvokeMBB, Dst: Return);
3540 for (auto &UnwindDest : UnwindDests) {
3541 UnwindDest.first->setIsEHPad();
3542 addSuccessorWithProb(Src: InvokeMBB, Dst: UnwindDest.first, Prob: UnwindDest.second);
3543 }
3544 InvokeMBB->normalizeSuccProbs();
3545
3546 // Drop into normal successor.
3547 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(), VT: MVT::Other, N1: getControlRoot(),
3548 N2: DAG.getBasicBlock(MBB: Return)));
3549}
3550
3551/// The intrinsics currently supported by callbr are implicit control flow
3552/// intrinsics such as amdgcn.kill.
3553/// - they should be called (no "dontcall-" attributes)
3554/// - they do not touch memory on the target (= !TLI.getTgtMemIntrinsic())
3555/// - they do not need custom argument handling (no
3556/// TLI.CollectTargetIntrinsicOperands())
3557void SelectionDAGBuilder::visitCallBrIntrinsic(const CallBrInst &I) {
3558#ifndef NDEBUG
3559 SmallVector<TargetLowering::IntrinsicInfo, 2> Infos;
3560 DAG.getTargetLoweringInfo().getTgtMemIntrinsic(
3561 Infos, I, DAG.getMachineFunction(), I.getIntrinsicID());
3562 assert(Infos.empty() && "Intrinsic touches memory");
3563#endif
3564
3565 auto [HasChain, OnlyLoad] = getTargetIntrinsicCallProperties(I);
3566
3567 SmallVector<SDValue, 8> Ops =
3568 getTargetIntrinsicOperands(I, HasChain, OnlyLoad);
3569 SDVTList VTs = getTargetIntrinsicVTList(I, HasChain);
3570
3571 // Create the node.
3572 SDValue Result =
3573 getTargetNonMemIntrinsicNode(IntrinsicVT: *I.getType(), HasChain, Ops, VTs);
3574 Result = handleTargetIntrinsicRet(I, HasChain, OnlyLoad, Result);
3575
3576 setValue(V: &I, NewN: Result);
3577}
3578
3579void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) {
3580 MachineBasicBlock *CallBrMBB = FuncInfo.MBB;
3581
3582 if (I.isInlineAsm()) {
3583 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
3584 // have to do anything here to lower funclet bundles.
3585 failForInvalidBundles(I, Name: "callbrs",
3586 AllowedBundles: {LLVMContext::OB_deopt, LLVMContext::OB_funclet});
3587 visitInlineAsm(Call: I);
3588 } else {
3589 assert(!I.hasOperandBundles() &&
3590 "Can't have operand bundles for intrinsics");
3591 visitCallBrIntrinsic(I);
3592 }
3593 CopyToExportRegsIfNeeded(V: &I);
3594
3595 // Retrieve successors.
3596 SmallPtrSet<BasicBlock *, 8> Dests;
3597 Dests.insert(Ptr: I.getDefaultDest());
3598 MachineBasicBlock *Return = FuncInfo.getMBB(BB: I.getDefaultDest());
3599
3600 // Update successor info.
3601 addSuccessorWithProb(Src: CallBrMBB, Dst: Return, Prob: BranchProbability::getOne());
3602 // TODO: For most of the cases where there is an intrinsic callbr, we're
3603 // having exactly one indirect target, which will be unreachable. As soon as
3604 // this changes, we might need to enhance
3605 // Target->setIsInlineAsmBrIndirectTarget or add something similar for
3606 // intrinsic indirect branches.
3607 if (I.isInlineAsm()) {
3608 for (BasicBlock *Dest : I.getIndirectDests()) {
3609 MachineBasicBlock *Target = FuncInfo.getMBB(BB: Dest);
3610 Target->setIsInlineAsmBrIndirectTarget();
3611 // If we introduce a type of asm goto statement that is permitted to use
3612 // an indirect call instruction to jump to its labels, then we should add
3613 // a call to Target->setMachineBlockAddressTaken() here, to mark the
3614 // target block as requiring a BTI.
3615
3616 Target->setLabelMustBeEmitted();
3617 // Don't add duplicate machine successors.
3618 if (Dests.insert(Ptr: Dest).second)
3619 addSuccessorWithProb(Src: CallBrMBB, Dst: Target, Prob: BranchProbability::getZero());
3620 }
3621 }
3622 CallBrMBB->normalizeSuccProbs();
3623
3624 // Drop into default successor.
3625 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(),
3626 VT: MVT::Other, N1: getControlRoot(),
3627 N2: DAG.getBasicBlock(MBB: Return)));
3628}
3629
3630void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
3631 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
3632}
3633
3634void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
3635 assert(FuncInfo.MBB->isEHPad() &&
3636 "Call to landingpad not in landing pad!");
3637
3638 // If there aren't registers to copy the values into (e.g., during SjLj
3639 // exceptions), then don't bother to create these DAG nodes.
3640 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3641 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
3642 if (TLI.getExceptionPointerRegister(
3643 EH: TLI.getTargetMachine().getExceptionModel(), PersonalityFn) == 0 &&
3644 TLI.getExceptionSelectorRegister(
3645 EH: TLI.getTargetMachine().getExceptionModel(), PersonalityFn) == 0)
3646 return;
3647
3648 // If landingpad's return type is token type, we don't create DAG nodes
3649 // for its exception pointer and selector value. The extraction of exception
3650 // pointer or selector value from token type landingpads is not currently
3651 // supported.
3652 if (LP.getType()->isTokenTy())
3653 return;
3654
3655 SmallVector<EVT, 2> ValueVTs;
3656 SDLoc dl = getCurSDLoc();
3657 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: LP.getType(), ValueVTs);
3658 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
3659
3660 // Get the two live-in registers as SDValues. The physregs have already been
3661 // copied into virtual registers.
3662 SDValue Ops[2];
3663 if (FuncInfo.ExceptionPointerVirtReg) {
3664 Ops[0] = DAG.getZExtOrTrunc(
3665 Op: DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl,
3666 Reg: FuncInfo.ExceptionPointerVirtReg,
3667 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
3668 DL: dl, VT: ValueVTs[0]);
3669 } else {
3670 Ops[0] = DAG.getConstant(Val: 0, DL: dl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
3671 }
3672 Ops[1] = DAG.getZExtOrTrunc(
3673 Op: DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl,
3674 Reg: FuncInfo.ExceptionSelectorVirtReg,
3675 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
3676 DL: dl, VT: ValueVTs[1]);
3677
3678 // Merge into one.
3679 SDValue Res = DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: dl,
3680 VTList: DAG.getVTList(VTs: ValueVTs), Ops);
3681 setValue(V: &LP, NewN: Res);
3682}
3683
3684void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
3685 MachineBasicBlock *Last) {
3686 // Update JTCases.
3687 for (JumpTableBlock &JTB : SL->JTCases)
3688 if (JTB.first.HeaderBB == First)
3689 JTB.first.HeaderBB = Last;
3690
3691 // Update BitTestCases.
3692 for (BitTestBlock &BTB : SL->BitTestCases)
3693 if (BTB.Parent == First)
3694 BTB.Parent = Last;
3695}
3696
3697void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
3698 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
3699
3700 // Update machine-CFG edges with unique successors.
3701 SmallPtrSet<BasicBlock *, 32> Done;
3702 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
3703 BasicBlock *BB = I.getSuccessor(i);
3704 bool Inserted = Done.insert(Ptr: BB).second;
3705 if (!Inserted)
3706 continue;
3707
3708 MachineBasicBlock *Succ = FuncInfo.getMBB(BB);
3709 addSuccessorWithProb(Src: IndirectBrMBB, Dst: Succ);
3710 }
3711 IndirectBrMBB->normalizeSuccProbs();
3712
3713 DAG.setRoot(DAG.getNode(Opcode: ISD::BRIND, DL: getCurSDLoc(),
3714 VT: MVT::Other, N1: getControlRoot(),
3715 N2: getValue(V: I.getAddress())));
3716}
3717
3718void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
3719 if (!I.shouldLowerToTrap(TrapUnreachable: DAG.getTarget().Options.TrapUnreachable,
3720 NoTrapAfterNoreturn: DAG.getTarget().Options.NoTrapAfterNoreturn))
3721 return;
3722
3723 DAG.setRoot(DAG.getNode(Opcode: ISD::TRAP, DL: getCurSDLoc(), VT: MVT::Other, Operand: DAG.getRoot()));
3724}
3725
3726void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) {
3727 SDNodeFlags Flags;
3728 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
3729 Flags.copyFMF(FPMO: *FPOp);
3730
3731 SDValue Op = getValue(V: I.getOperand(i: 0));
3732 SDValue UnNodeValue = DAG.getNode(Opcode, DL: getCurSDLoc(), VT: Op.getValueType(),
3733 Operand: Op, Flags);
3734 setValue(V: &I, NewN: UnNodeValue);
3735}
3736
3737void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) {
3738 SDNodeFlags Flags;
3739 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(Val: &I)) {
3740 Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
3741 Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
3742 }
3743 if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(Val: &I))
3744 Flags.setExact(ExactOp->isExact());
3745 if (auto *DisjointOp = dyn_cast<PossiblyDisjointInst>(Val: &I))
3746 Flags.setDisjoint(DisjointOp->isDisjoint());
3747 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
3748 Flags.copyFMF(FPMO: *FPOp);
3749
3750 SDValue Op1 = getValue(V: I.getOperand(i: 0));
3751 SDValue Op2 = getValue(V: I.getOperand(i: 1));
3752 SDValue BinNodeValue = DAG.getNode(Opcode, DL: getCurSDLoc(), VT: Op1.getValueType(),
3753 N1: Op1, N2: Op2, Flags);
3754 setValue(V: &I, NewN: BinNodeValue);
3755}
3756
3757void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
3758 SDValue Op1 = getValue(V: I.getOperand(i: 0));
3759 SDValue Op2 = getValue(V: I.getOperand(i: 1));
3760
3761 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
3762 LHSTy: Op1.getValueType(), DL: DAG.getDataLayout());
3763
3764 // Coerce the shift amount to the right type if we can. This exposes the
3765 // truncate or zext to optimization early.
3766 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
3767 assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) &&
3768 "Unexpected shift type");
3769 Op2 = DAG.getZExtOrTrunc(Op: Op2, DL: getCurSDLoc(), VT: ShiftTy);
3770 }
3771
3772 bool nuw = false;
3773 bool nsw = false;
3774 bool exact = false;
3775
3776 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
3777
3778 if (const OverflowingBinaryOperator *OFBinOp =
3779 dyn_cast<const OverflowingBinaryOperator>(Val: &I)) {
3780 nuw = OFBinOp->hasNoUnsignedWrap();
3781 nsw = OFBinOp->hasNoSignedWrap();
3782 }
3783 if (const PossiblyExactOperator *ExactOp =
3784 dyn_cast<const PossiblyExactOperator>(Val: &I))
3785 exact = ExactOp->isExact();
3786 }
3787 SDNodeFlags Flags;
3788 Flags.setExact(exact);
3789 Flags.setNoSignedWrap(nsw);
3790 Flags.setNoUnsignedWrap(nuw);
3791 SDValue Res = DAG.getNode(Opcode, DL: getCurSDLoc(), VT: Op1.getValueType(), N1: Op1, N2: Op2,
3792 Flags);
3793 setValue(V: &I, NewN: Res);
3794}
3795
3796void SelectionDAGBuilder::visitSDiv(const User &I) {
3797 SDValue Op1 = getValue(V: I.getOperand(i: 0));
3798 SDValue Op2 = getValue(V: I.getOperand(i: 1));
3799
3800 SDNodeFlags Flags;
3801 Flags.setExact(isa<PossiblyExactOperator>(Val: &I) &&
3802 cast<PossiblyExactOperator>(Val: &I)->isExact());
3803 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SDIV, DL: getCurSDLoc(), VT: Op1.getValueType(), N1: Op1,
3804 N2: Op2, Flags));
3805}
3806
3807void SelectionDAGBuilder::visitICmp(const ICmpInst &I) {
3808 ICmpInst::Predicate predicate = I.getPredicate();
3809 SDValue Op1 = getValue(V: I.getOperand(i_nocapture: 0));
3810 SDValue Op2 = getValue(V: I.getOperand(i_nocapture: 1));
3811 ISD::CondCode Opcode = getICmpCondCode(Pred: predicate);
3812
3813 auto &TLI = DAG.getTargetLoweringInfo();
3814 EVT MemVT =
3815 TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getOperand(i_nocapture: 0)->getType());
3816
3817 // If a pointer's DAG type is larger than its memory type then the DAG values
3818 // are zero-extended. This breaks signed comparisons so truncate back to the
3819 // underlying type before doing the compare.
3820 if (Op1.getValueType() != MemVT) {
3821 Op1 = DAG.getPtrExtOrTrunc(Op: Op1, DL: getCurSDLoc(), VT: MemVT);
3822 Op2 = DAG.getPtrExtOrTrunc(Op: Op2, DL: getCurSDLoc(), VT: MemVT);
3823 }
3824
3825 SDNodeFlags Flags;
3826 Flags.setSameSign(I.hasSameSign());
3827
3828 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
3829 Ty: I.getType());
3830 setValue(V: &I, NewN: DAG.getSetCC(DL: getCurSDLoc(), VT: DestVT, LHS: Op1, RHS: Op2, Cond: Opcode,
3831 /*Chain=*/{}, /*IsSignaling=*/false, Flags));
3832}
3833
3834void SelectionDAGBuilder::visitFCmp(const FCmpInst &I) {
3835 FCmpInst::Predicate predicate = I.getPredicate();
3836 SDValue Op1 = getValue(V: I.getOperand(i_nocapture: 0));
3837 SDValue Op2 = getValue(V: I.getOperand(i_nocapture: 1));
3838
3839 ISD::CondCode Condition = getFCmpCondCode(Pred: predicate);
3840 auto *FPMO = cast<FPMathOperator>(Val: &I);
3841 if (FPMO->hasNoNaNs() ||
3842 (DAG.isKnownNeverNaN(Op: Op1) && DAG.isKnownNeverNaN(Op: Op2)))
3843 Condition = getFCmpCodeWithoutNaN(CC: Condition);
3844
3845 SDNodeFlags Flags;
3846 Flags.copyFMF(FPMO: *FPMO);
3847
3848 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
3849 Ty: I.getType());
3850 setValue(V: &I, NewN: DAG.getSetCC(DL: getCurSDLoc(), VT: DestVT, LHS: Op1, RHS: Op2, Cond: Condition,
3851 /*Chain=*/{}, /*IsSignaling=*/false, Flags));
3852}
3853
3854// Check if the condition of the select has one use or two users that are both
3855// selects with the same condition.
3856static bool hasOnlySelectUsers(const Value *Cond) {
3857 return llvm::all_of(Range: Cond->users(), P: [](const Value *V) {
3858 return isa<SelectInst>(Val: V);
3859 });
3860}
3861
3862void SelectionDAGBuilder::visitSelect(const User &I) {
3863 SmallVector<EVT, 4> ValueVTs;
3864 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(), Ty: I.getType(),
3865 ValueVTs);
3866 unsigned NumValues = ValueVTs.size();
3867 if (NumValues == 0) return;
3868
3869 SmallVector<SDValue, 4> Values(NumValues);
3870 SDValue Cond = getValue(V: I.getOperand(i: 0));
3871 SDValue LHSVal = getValue(V: I.getOperand(i: 1));
3872 SDValue RHSVal = getValue(V: I.getOperand(i: 2));
3873 SmallVector<SDValue, 1> BaseOps(1, Cond);
3874 ISD::NodeType OpCode =
3875 Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
3876
3877 bool IsUnaryAbs = false;
3878 bool Negate = false;
3879
3880 SDNodeFlags Flags;
3881 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
3882 Flags.copyFMF(FPMO: *FPOp);
3883
3884 Flags.setUnpredictable(
3885 cast<SelectInst>(Val: I).getMetadata(KindID: LLVMContext::MD_unpredictable));
3886
3887 // Min/max matching is only viable if all output VTs are the same.
3888 if (all_equal(Range&: ValueVTs)) {
3889 EVT VT = ValueVTs[0];
3890 LLVMContext &Ctx = *DAG.getContext();
3891 auto &TLI = DAG.getTargetLoweringInfo();
3892
3893 // We care about the legality of the operation after it has been type
3894 // legalized.
3895 while (TLI.getTypeAction(Context&: Ctx, VT) != TargetLoweringBase::TypeLegal)
3896 VT = TLI.getTypeToTransformTo(Context&: Ctx, VT);
3897
3898 // If the vselect is legal, assume we want to leave this as a vector setcc +
3899 // vselect. Otherwise, if this is going to be scalarized, we want to see if
3900 // min/max is legal on the scalar type.
3901 bool UseScalarMinMax = VT.isVector() &&
3902 !TLI.isOperationLegalOrCustom(Op: ISD::VSELECT, VT);
3903
3904 // ValueTracking's select pattern matching does not account for -0.0,
3905 // so we can't lower to FMINIMUM/FMAXIMUM because those nodes specify that
3906 // -0.0 is less than +0.0.
3907 const Value *LHS, *RHS;
3908 auto SPR = matchSelectPattern(V: &I, LHS, RHS);
3909 ISD::NodeType Opc = ISD::DELETED_NODE;
3910 switch (SPR.Flavor) {
3911 case SPF_UMAX: Opc = ISD::UMAX; break;
3912 case SPF_UMIN: Opc = ISD::UMIN; break;
3913 case SPF_SMAX: Opc = ISD::SMAX; break;
3914 case SPF_SMIN: Opc = ISD::SMIN; break;
3915 case SPF_FMINNUM:
3916 if (!TLI.isProfitableToCombineMinNumMaxNum(VT))
3917 break;
3918
3919 switch (SPR.NaNBehavior) {
3920 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3921 case SPNB_RETURNS_ANY:
3922 case SPNB_RETURNS_NAN:
3923 break;
3924 case SPNB_RETURNS_OTHER:
3925 Opc = ISD::FMINIMUMNUM;
3926 Flags.setNoSignedZeros(true);
3927 break;
3928 }
3929 break;
3930 case SPF_FMAXNUM:
3931 if (!TLI.isProfitableToCombineMinNumMaxNum(VT))
3932 break;
3933
3934 switch (SPR.NaNBehavior) {
3935 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3936 case SPNB_RETURNS_NAN:
3937 case SPNB_RETURNS_ANY:
3938 break;
3939 case SPNB_RETURNS_OTHER:
3940 Opc = ISD::FMAXIMUMNUM;
3941 Flags.setNoSignedZeros(true);
3942 break;
3943 }
3944 break;
3945 case SPF_NABS:
3946 Negate = true;
3947 [[fallthrough]];
3948 case SPF_ABS:
3949 IsUnaryAbs = true;
3950 Opc = ISD::ABS;
3951 break;
3952 default: break;
3953 }
3954
3955 if (!IsUnaryAbs && Opc != ISD::DELETED_NODE &&
3956 (TLI.isOperationLegalOrCustom(Op: Opc, VT) ||
3957 (UseScalarMinMax &&
3958 TLI.isOperationLegalOrCustom(Op: Opc, VT: VT.getScalarType()))) &&
3959 // If the underlying comparison instruction is used by any other
3960 // instruction, the consumed instructions won't be destroyed, so it is
3961 // not profitable to convert to a min/max.
3962 hasOnlySelectUsers(Cond: cast<SelectInst>(Val: I).getCondition())) {
3963 OpCode = Opc;
3964 LHSVal = getValue(V: LHS);
3965 RHSVal = getValue(V: RHS);
3966 BaseOps.clear();
3967 }
3968
3969 if (IsUnaryAbs) {
3970 OpCode = Opc;
3971 LHSVal = getValue(V: LHS);
3972 BaseOps.clear();
3973 }
3974 }
3975
3976 if (IsUnaryAbs) {
3977 for (unsigned i = 0; i != NumValues; ++i) {
3978 SDLoc dl = getCurSDLoc();
3979 EVT VT = LHSVal.getNode()->getValueType(ResNo: LHSVal.getResNo() + i);
3980 Values[i] =
3981 DAG.getNode(Opcode: OpCode, DL: dl, VT, Operand: LHSVal.getValue(R: LHSVal.getResNo() + i));
3982 if (Negate)
3983 Values[i] = DAG.getNegative(Val: Values[i], DL: dl, VT);
3984 }
3985 } else {
3986 for (unsigned i = 0; i != NumValues; ++i) {
3987 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
3988 Ops.push_back(Elt: SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3989 Ops.push_back(Elt: SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
3990 Values[i] = DAG.getNode(
3991 Opcode: OpCode, DL: getCurSDLoc(),
3992 VT: LHSVal.getNode()->getValueType(ResNo: LHSVal.getResNo() + i), Ops, Flags);
3993 }
3994 }
3995
3996 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
3997 VTList: DAG.getVTList(VTs: ValueVTs), Ops: Values));
3998}
3999
4000void SelectionDAGBuilder::visitTrunc(const User &I) {
4001 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
4002 SDValue N = getValue(V: I.getOperand(i: 0));
4003 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4004 Ty: I.getType());
4005 SDNodeFlags Flags;
4006 if (auto *Trunc = dyn_cast<TruncInst>(Val: &I)) {
4007 Flags.setNoSignedWrap(Trunc->hasNoSignedWrap());
4008 Flags.setNoUnsignedWrap(Trunc->hasNoUnsignedWrap());
4009 }
4010
4011 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::TRUNCATE, DL: getCurSDLoc(), VT: DestVT, Operand: N, Flags));
4012}
4013
4014void SelectionDAGBuilder::visitZExt(const User &I) {
4015 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
4016 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
4017 SDValue N = getValue(V: I.getOperand(i: 0));
4018 auto &TLI = DAG.getTargetLoweringInfo();
4019 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4020
4021 SDNodeFlags Flags;
4022 if (auto *PNI = dyn_cast<PossiblyNonNegInst>(Val: &I))
4023 Flags.setNonNeg(PNI->hasNonNeg());
4024
4025 // Eagerly use nonneg information to canonicalize towards sign_extend if
4026 // that is the target's preference.
4027 // TODO: Let the target do this later.
4028 if (Flags.hasNonNeg() &&
4029 TLI.isSExtCheaperThanZExt(FromTy: N.getValueType(), ToTy: DestVT)) {
4030 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: getCurSDLoc(), VT: DestVT, Operand: N));
4031 return;
4032 }
4033
4034 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: getCurSDLoc(), VT: DestVT, Operand: N, Flags));
4035}
4036
4037void SelectionDAGBuilder::visitSExt(const User &I) {
4038 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
4039 // SExt also can't be a cast to bool for same reason. So, nothing much to do
4040 SDValue N = getValue(V: I.getOperand(i: 0));
4041 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4042 Ty: I.getType());
4043 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: getCurSDLoc(), VT: DestVT, Operand: N));
4044}
4045
4046void SelectionDAGBuilder::visitFPTrunc(const User &I) {
4047 // FPTrunc is never a no-op cast, no need to check
4048 SDValue N = getValue(V: I.getOperand(i: 0));
4049 SDLoc dl = getCurSDLoc();
4050 SDNodeFlags Flags;
4051 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
4052 Flags.copyFMF(FPMO: *FPOp);
4053 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4054 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4055 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: DestVT, N1: N,
4056 N2: DAG.getTargetConstant(
4057 Val: 0, DL: dl, VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
4058 Flags));
4059}
4060
4061void SelectionDAGBuilder::visitFPExt(const User &I) {
4062 // FPExt is never a no-op cast, no need to check
4063 SDValue N = getValue(V: I.getOperand(i: 0));
4064 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4065 Ty: I.getType());
4066 SDNodeFlags Flags;
4067 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
4068 Flags.copyFMF(FPMO: *FPOp);
4069 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_EXTEND, DL: getCurSDLoc(), VT: DestVT, Operand: N, Flags));
4070}
4071
4072void SelectionDAGBuilder::visitFPToUI(const User &I) {
4073 // FPToUI is never a no-op cast, no need to check
4074 SDValue N = getValue(V: I.getOperand(i: 0));
4075 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4076 Ty: I.getType());
4077 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_TO_UINT, DL: getCurSDLoc(), VT: DestVT, Operand: N));
4078}
4079
4080void SelectionDAGBuilder::visitFPToSI(const User &I) {
4081 // FPToSI is never a no-op cast, no need to check
4082 SDValue N = getValue(V: I.getOperand(i: 0));
4083 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4084 Ty: I.getType());
4085 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_TO_SINT, DL: getCurSDLoc(), VT: DestVT, Operand: N));
4086}
4087
4088void SelectionDAGBuilder::visitUIToFP(const User &I) {
4089 // UIToFP is never a no-op cast, no need to check
4090 SDValue N = getValue(V: I.getOperand(i: 0));
4091 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4092 Ty: I.getType());
4093 SDNodeFlags Flags;
4094 Flags.setNonNeg(cast<PossiblyNonNegInst>(Val: &I)->hasNonNeg());
4095 Flags.copyFMF(FPMO: *cast<FPMathOperator>(Val: &I));
4096
4097 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UINT_TO_FP, DL: getCurSDLoc(), VT: DestVT, Operand: N, Flags));
4098}
4099
4100void SelectionDAGBuilder::visitSIToFP(const User &I) {
4101 // SIToFP is never a no-op cast, no need to check
4102 SDValue N = getValue(V: I.getOperand(i: 0));
4103 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4104 Ty: I.getType());
4105 SDNodeFlags Flags;
4106 Flags.copyFMF(FPMO: *cast<FPMathOperator>(Val: &I));
4107
4108 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: getCurSDLoc(), VT: DestVT, Operand: N, Flags));
4109}
4110
4111void SelectionDAGBuilder::visitPtrToAddr(const User &I) {
4112 SDValue N = getValue(V: I.getOperand(i: 0));
4113 // By definition the type of the ptrtoaddr must be equal to the address type.
4114 const auto &TLI = DAG.getTargetLoweringInfo();
4115 EVT AddrVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4116 // The address width must be smaller or equal to the pointer representation
4117 // width, so we lower ptrtoaddr as a truncate (possibly folded to a no-op).
4118 N = DAG.getNode(Opcode: ISD::TRUNCATE, DL: getCurSDLoc(), VT: AddrVT, Operand: N);
4119 setValue(V: &I, NewN: N);
4120}
4121
4122void SelectionDAGBuilder::visitPtrToInt(const User &I) {
4123 // What to do depends on the size of the integer and the size of the pointer.
4124 // We can either truncate, zero extend, or no-op, accordingly.
4125 SDValue N = getValue(V: I.getOperand(i: 0));
4126 auto &TLI = DAG.getTargetLoweringInfo();
4127 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4128 Ty: I.getType());
4129 EVT PtrMemVT =
4130 TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getOperand(i: 0)->getType());
4131 N = DAG.getPtrExtOrTrunc(Op: N, DL: getCurSDLoc(), VT: PtrMemVT);
4132 N = DAG.getZExtOrTrunc(Op: N, DL: getCurSDLoc(), VT: DestVT);
4133 setValue(V: &I, NewN: N);
4134}
4135
4136void SelectionDAGBuilder::visitIntToPtr(const User &I) {
4137 // What to do depends on the size of the integer and the size of the pointer.
4138 // We can either truncate, zero extend, or no-op, accordingly.
4139 SDValue N = getValue(V: I.getOperand(i: 0));
4140 auto &TLI = DAG.getTargetLoweringInfo();
4141 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4142 EVT PtrMemVT = TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4143 N = DAG.getZExtOrTrunc(Op: N, DL: getCurSDLoc(), VT: PtrMemVT);
4144 N = DAG.getPtrExtOrTrunc(Op: N, DL: getCurSDLoc(), VT: DestVT);
4145 setValue(V: &I, NewN: N);
4146}
4147
4148void SelectionDAGBuilder::visitBitCast(const User &I) {
4149 SDValue N = getValue(V: I.getOperand(i: 0));
4150 SDLoc dl = getCurSDLoc();
4151 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4152 Ty: I.getType());
4153
4154 // BitCast assures us that source and destination are the same size so this is
4155 // either a BITCAST or a no-op.
4156 if (DestVT != N.getValueType())
4157 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::BITCAST, DL: dl,
4158 VT: DestVT, Operand: N)); // convert types.
4159 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
4160 // might fold any kind of constant expression to an integer constant and that
4161 // is not what we are looking for. Only recognize a bitcast of a genuine
4162 // constant integer as an opaque constant.
4163 else if(ConstantInt *C = dyn_cast<ConstantInt>(Val: I.getOperand(i: 0)))
4164 setValue(V: &I, NewN: DAG.getConstant(Val: C->getValue(), DL: dl, VT: DestVT, /*isTarget=*/false,
4165 /*isOpaque*/true));
4166 else
4167 setValue(V: &I, NewN: N); // noop cast.
4168}
4169
4170void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
4171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4172 const Value *SV = I.getOperand(i: 0);
4173 SDValue N = getValue(V: SV);
4174 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4175
4176 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
4177 unsigned DestAS = I.getType()->getPointerAddressSpace();
4178
4179 if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS))
4180 N = DAG.getAddrSpaceCast(dl: getCurSDLoc(), VT: DestVT, Ptr: N, SrcAS, DestAS);
4181
4182 setValue(V: &I, NewN: N);
4183}
4184
4185void SelectionDAGBuilder::visitInsertElement(const User &I) {
4186 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4187 SDValue InVec = getValue(V: I.getOperand(i: 0));
4188 SDValue InVal = getValue(V: I.getOperand(i: 1));
4189 SDValue InIdx = DAG.getZExtOrTrunc(Op: getValue(V: I.getOperand(i: 2)), DL: getCurSDLoc(),
4190 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
4191 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: getCurSDLoc(),
4192 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
4193 N1: InVec, N2: InVal, N3: InIdx));
4194}
4195
4196void SelectionDAGBuilder::visitExtractElement(const User &I) {
4197 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4198 SDValue InVec = getValue(V: I.getOperand(i: 0));
4199 SDValue InIdx = DAG.getZExtOrTrunc(Op: getValue(V: I.getOperand(i: 1)), DL: getCurSDLoc(),
4200 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
4201 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: getCurSDLoc(),
4202 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
4203 N1: InVec, N2: InIdx));
4204}
4205
4206void SelectionDAGBuilder::visitShuffleVector(const User &I) {
4207 SDValue Src1 = getValue(V: I.getOperand(i: 0));
4208 SDValue Src2 = getValue(V: I.getOperand(i: 1));
4209 ArrayRef<int> Mask;
4210 if (auto *SVI = dyn_cast<ShuffleVectorInst>(Val: &I))
4211 Mask = SVI->getShuffleMask();
4212 else
4213 Mask = cast<ConstantExpr>(Val: I).getShuffleMask();
4214 SDLoc DL = getCurSDLoc();
4215 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4216 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4217 EVT SrcVT = Src1.getValueType();
4218
4219 if (all_of(Range&: Mask, P: equal_to(Arg: 0)) && VT.isScalableVector()) {
4220 // Canonical splat form of first element of first input vector.
4221 SDValue FirstElt =
4222 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: SrcVT.getScalarType(), N1: Src1,
4223 N2: DAG.getVectorIdxConstant(Val: 0, DL));
4224 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SPLAT_VECTOR, DL, VT, Operand: FirstElt));
4225 return;
4226 }
4227
4228 // For now, we only handle splats for scalable vectors.
4229 // The DAGCombiner will perform a BUILD_VECTOR -> SPLAT_VECTOR transformation
4230 // for targets that support a SPLAT_VECTOR for non-scalable vector types.
4231 assert(!VT.isScalableVector() && "Unsupported scalable vector shuffle");
4232
4233 unsigned SrcNumElts = SrcVT.getVectorNumElements();
4234 unsigned MaskNumElts = Mask.size();
4235
4236 if (SrcNumElts == MaskNumElts) {
4237 setValue(V: &I, NewN: DAG.getVectorShuffle(VT, dl: DL, N1: Src1, N2: Src2, Mask));
4238 return;
4239 }
4240
4241 // Normalize the shuffle vector since mask and vector length don't match.
4242 if (SrcNumElts < MaskNumElts) {
4243 // Mask is longer than the source vectors. We can use concatenate vector to
4244 // make the mask and vectors lengths match.
4245
4246 if (MaskNumElts % SrcNumElts == 0) {
4247 // Mask length is a multiple of the source vector length.
4248 // Check if the shuffle is some kind of concatenation of the input
4249 // vectors.
4250 unsigned NumConcat = MaskNumElts / SrcNumElts;
4251 bool IsConcat = true;
4252 SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
4253 for (unsigned i = 0; i != MaskNumElts; ++i) {
4254 int Idx = Mask[i];
4255 if (Idx < 0)
4256 continue;
4257 // Ensure the indices in each SrcVT sized piece are sequential and that
4258 // the same source is used for the whole piece.
4259 if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
4260 (ConcatSrcs[i / SrcNumElts] >= 0 &&
4261 ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
4262 IsConcat = false;
4263 break;
4264 }
4265 // Remember which source this index came from.
4266 ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
4267 }
4268
4269 // The shuffle is concatenating multiple vectors together. Just emit
4270 // a CONCAT_VECTORS operation.
4271 if (IsConcat) {
4272 SmallVector<SDValue, 8> ConcatOps;
4273 for (auto Src : ConcatSrcs) {
4274 if (Src < 0)
4275 ConcatOps.push_back(Elt: DAG.getUNDEF(VT: SrcVT));
4276 else if (Src == 0)
4277 ConcatOps.push_back(Elt: Src1);
4278 else
4279 ConcatOps.push_back(Elt: Src2);
4280 }
4281 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT, Ops: ConcatOps));
4282 return;
4283 }
4284 }
4285
4286 unsigned PaddedMaskNumElts = alignTo(Value: MaskNumElts, Align: SrcNumElts);
4287 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
4288 EVT PaddedVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: VT.getScalarType(),
4289 NumElements: PaddedMaskNumElts);
4290
4291 // Pad both vectors with undefs to make them the same length as the mask.
4292 SDValue UndefVal = DAG.getUNDEF(VT: SrcVT);
4293
4294 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
4295 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
4296 MOps1[0] = Src1;
4297 MOps2[0] = Src2;
4298
4299 Src1 = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: PaddedVT, Ops: MOps1);
4300 Src2 = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: PaddedVT, Ops: MOps2);
4301
4302 // Readjust mask for new input vector length.
4303 SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
4304 for (unsigned i = 0; i != MaskNumElts; ++i) {
4305 int Idx = Mask[i];
4306 if (Idx >= (int)SrcNumElts)
4307 Idx -= SrcNumElts - PaddedMaskNumElts;
4308 MappedOps[i] = Idx;
4309 }
4310
4311 SDValue Result = DAG.getVectorShuffle(VT: PaddedVT, dl: DL, N1: Src1, N2: Src2, Mask: MappedOps);
4312
4313 // If the concatenated vector was padded, extract a subvector with the
4314 // correct number of elements.
4315 if (MaskNumElts != PaddedMaskNumElts)
4316 Result = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT, N1: Result,
4317 N2: DAG.getVectorIdxConstant(Val: 0, DL));
4318
4319 setValue(V: &I, NewN: Result);
4320 return;
4321 }
4322
4323 assert(SrcNumElts > MaskNumElts);
4324
4325 // Analyze the access pattern of the vector to see if we can extract
4326 // two subvectors and do the shuffle.
4327 int StartIdx[2] = {-1, -1}; // StartIdx to extract from
4328 bool CanExtract = true;
4329 for (int Idx : Mask) {
4330 unsigned Input = 0;
4331 if (Idx < 0)
4332 continue;
4333
4334 if (Idx >= (int)SrcNumElts) {
4335 Input = 1;
4336 Idx -= SrcNumElts;
4337 }
4338
4339 // If all the indices come from the same MaskNumElts sized portion of
4340 // the sources we can use extract. Also make sure the extract wouldn't
4341 // extract past the end of the source.
4342 int NewStartIdx = alignDown(Value: Idx, Align: MaskNumElts);
4343 if (NewStartIdx + MaskNumElts > SrcNumElts ||
4344 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
4345 CanExtract = false;
4346 // Make sure we always update StartIdx as we use it to track if all
4347 // elements are undef.
4348 StartIdx[Input] = NewStartIdx;
4349 }
4350
4351 if (StartIdx[0] < 0 && StartIdx[1] < 0) {
4352 setValue(V: &I, NewN: DAG.getUNDEF(VT)); // Vectors are not used.
4353 return;
4354 }
4355 if (CanExtract) {
4356 // Extract appropriate subvector and generate a vector shuffle
4357 for (unsigned Input = 0; Input < 2; ++Input) {
4358 SDValue &Src = Input == 0 ? Src1 : Src2;
4359 if (StartIdx[Input] < 0)
4360 Src = DAG.getUNDEF(VT);
4361 else {
4362 Src = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT, N1: Src,
4363 N2: DAG.getVectorIdxConstant(Val: StartIdx[Input], DL));
4364 }
4365 }
4366
4367 // Calculate new mask.
4368 SmallVector<int, 8> MappedOps(Mask);
4369 for (int &Idx : MappedOps) {
4370 if (Idx >= (int)SrcNumElts)
4371 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
4372 else if (Idx >= 0)
4373 Idx -= StartIdx[0];
4374 }
4375
4376 setValue(V: &I, NewN: DAG.getVectorShuffle(VT, dl: DL, N1: Src1, N2: Src2, Mask: MappedOps));
4377 return;
4378 }
4379
4380 // We can't use either concat vectors or extract subvectors so fall back to
4381 // replacing the shuffle with extract and build vector.
4382 // to insert and build vector.
4383 EVT EltVT = VT.getVectorElementType();
4384 SmallVector<SDValue,8> Ops;
4385 for (int Idx : Mask) {
4386 SDValue Res;
4387
4388 if (Idx < 0) {
4389 Res = DAG.getUNDEF(VT: EltVT);
4390 } else {
4391 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
4392 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
4393
4394 Res = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: EltVT, N1: Src,
4395 N2: DAG.getVectorIdxConstant(Val: Idx, DL));
4396 }
4397
4398 Ops.push_back(Elt: Res);
4399 }
4400
4401 setValue(V: &I, NewN: DAG.getBuildVector(VT, DL, Ops));
4402}
4403
4404void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
4405 ArrayRef<unsigned> Indices = I.getIndices();
4406 const Value *Op0 = I.getOperand(i_nocapture: 0);
4407 const Value *Op1 = I.getOperand(i_nocapture: 1);
4408 Type *AggTy = I.getType();
4409 Type *ValTy = Op1->getType();
4410 bool IntoUndef = isa<UndefValue>(Val: Op0);
4411 bool FromUndef = isa<UndefValue>(Val: Op1);
4412
4413 unsigned LinearIndex = ComputeLinearIndex(Ty: AggTy, Indices);
4414
4415 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4416 SmallVector<EVT, 4> AggValueVTs;
4417 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: AggTy, ValueVTs&: AggValueVTs);
4418 SmallVector<EVT, 4> ValValueVTs;
4419 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: ValTy, ValueVTs&: ValValueVTs);
4420
4421 unsigned NumAggValues = AggValueVTs.size();
4422 unsigned NumValValues = ValValueVTs.size();
4423 SmallVector<SDValue, 4> Values(NumAggValues);
4424
4425 // Ignore an insertvalue that produces an empty object
4426 if (!NumAggValues) {
4427 setValue(V: &I, NewN: DAG.getUNDEF(VT: MVT(MVT::Other)));
4428 return;
4429 }
4430
4431 SDValue Agg = getValue(V: Op0);
4432 unsigned i = 0;
4433 // Copy the beginning value(s) from the original aggregate.
4434 for (; i != LinearIndex; ++i)
4435 Values[i] = IntoUndef ? DAG.getUNDEF(VT: AggValueVTs[i]) :
4436 SDValue(Agg.getNode(), Agg.getResNo() + i);
4437 // Copy values from the inserted value(s).
4438 if (NumValValues) {
4439 SDValue Val = getValue(V: Op1);
4440 for (; i != LinearIndex + NumValValues; ++i)
4441 Values[i] = FromUndef ? DAG.getUNDEF(VT: AggValueVTs[i]) :
4442 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
4443 }
4444 // Copy remaining value(s) from the original aggregate.
4445 for (; i != NumAggValues; ++i)
4446 Values[i] = IntoUndef ? DAG.getUNDEF(VT: AggValueVTs[i]) :
4447 SDValue(Agg.getNode(), Agg.getResNo() + i);
4448
4449 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
4450 VTList: DAG.getVTList(VTs: AggValueVTs), Ops: Values));
4451}
4452
4453void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
4454 ArrayRef<unsigned> Indices = I.getIndices();
4455 const Value *Op0 = I.getOperand(i_nocapture: 0);
4456 Type *AggTy = Op0->getType();
4457 Type *ValTy = I.getType();
4458 bool OutOfUndef = isa<UndefValue>(Val: Op0);
4459
4460 unsigned LinearIndex = ComputeLinearIndex(Ty: AggTy, Indices);
4461
4462 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4463 SmallVector<EVT, 4> ValValueVTs;
4464 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: ValTy, ValueVTs&: ValValueVTs);
4465
4466 unsigned NumValValues = ValValueVTs.size();
4467
4468 // Ignore a extractvalue that produces an empty object
4469 if (!NumValValues) {
4470 setValue(V: &I, NewN: DAG.getUNDEF(VT: MVT(MVT::Other)));
4471 return;
4472 }
4473
4474 SmallVector<SDValue, 4> Values(NumValValues);
4475
4476 SDValue Agg = getValue(V: Op0);
4477 // Copy out the selected value(s).
4478 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
4479 Values[i - LinearIndex] =
4480 OutOfUndef ?
4481 DAG.getUNDEF(VT: Agg.getNode()->getValueType(ResNo: Agg.getResNo() + i)) :
4482 SDValue(Agg.getNode(), Agg.getResNo() + i);
4483
4484 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
4485 VTList: DAG.getVTList(VTs: ValValueVTs), Ops: Values));
4486}
4487
4488void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
4489 Value *Op0 = I.getOperand(i: 0);
4490 // Note that the pointer operand may be a vector of pointers. Take the scalar
4491 // element which holds a pointer.
4492 unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
4493 SDValue N = getValue(V: Op0);
4494 SDLoc dl = getCurSDLoc();
4495 auto &TLI = DAG.getTargetLoweringInfo();
4496 GEPNoWrapFlags NW = cast<GEPOperator>(Val: I).getNoWrapFlags();
4497
4498 // For a vector GEP, keep the prefix scalar as long as possible, then
4499 // convert any scalars encountered after the first vector operand to vectors.
4500 bool IsVectorGEP = I.getType()->isVectorTy();
4501 ElementCount VectorElementCount =
4502 IsVectorGEP ? cast<VectorType>(Val: I.getType())->getElementCount()
4503 : ElementCount::getFixed(MinVal: 0);
4504
4505 for (gep_type_iterator GTI = gep_type_begin(GEP: &I), E = gep_type_end(GEP: &I);
4506 GTI != E; ++GTI) {
4507 const Value *Idx = GTI.getOperand();
4508 if (StructType *StTy = GTI.getStructTypeOrNull()) {
4509 unsigned Field = cast<Constant>(Val: Idx)->getUniqueInteger().getZExtValue();
4510 if (Field) {
4511 // N = N + Offset
4512 uint64_t Offset =
4513 DAG.getDataLayout().getStructLayout(Ty: StTy)->getElementOffset(Idx: Field);
4514
4515 // In an inbounds GEP with an offset that is nonnegative even when
4516 // interpreted as signed, assume there is no unsigned overflow.
4517 SDNodeFlags Flags;
4518 if (NW.hasNoUnsignedWrap() ||
4519 (int64_t(Offset) >= 0 && NW.hasNoUnsignedSignedWrap()))
4520 Flags |= SDNodeFlags::NoUnsignedWrap;
4521 Flags.setInBounds(NW.isInBounds());
4522
4523 N = DAG.getMemBasePlusOffset(
4524 Base: N, Offset: DAG.getConstant(Val: Offset, DL: dl, VT: N.getValueType()), DL: dl, Flags);
4525 }
4526 } else {
4527 // IdxSize is the width of the arithmetic according to IR semantics.
4528 // In SelectionDAG, we may prefer to do arithmetic in a wider bitwidth
4529 // (and fix up the result later).
4530 unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS);
4531 MVT IdxTy = MVT::getIntegerVT(BitWidth: IdxSize);
4532 TypeSize ElementSize =
4533 GTI.getSequentialElementStride(DL: DAG.getDataLayout());
4534 // We intentionally mask away the high bits here; ElementSize may not
4535 // fit in IdxTy.
4536 APInt ElementMul(IdxSize, ElementSize.getKnownMinValue(),
4537 /*isSigned=*/false, /*implicitTrunc=*/true);
4538 bool ElementScalable = ElementSize.isScalable();
4539
4540 // If this is a scalar constant or a splat vector of constants,
4541 // handle it quickly.
4542 const auto *C = dyn_cast<Constant>(Val: Idx);
4543 if (C && isa<VectorType>(Val: C->getType()))
4544 C = C->getSplatValue();
4545
4546 const auto *CI = dyn_cast_or_null<ConstantInt>(Val: C);
4547 if (CI && CI->isZero())
4548 continue;
4549 if (CI && !ElementScalable) {
4550 APInt Offs = ElementMul * CI->getValue().sextOrTrunc(width: IdxSize);
4551 LLVMContext &Context = *DAG.getContext();
4552 SDValue OffsVal;
4553 if (N.getValueType().isVector())
4554 OffsVal = DAG.getConstant(
4555 Val: Offs, DL: dl, VT: EVT::getVectorVT(Context, VT: IdxTy, EC: VectorElementCount));
4556 else
4557 OffsVal = DAG.getConstant(Val: Offs, DL: dl, VT: IdxTy);
4558
4559 // In an inbounds GEP with an offset that is nonnegative even when
4560 // interpreted as signed, assume there is no unsigned overflow.
4561 SDNodeFlags Flags;
4562 if (NW.hasNoUnsignedWrap() ||
4563 (Offs.isNonNegative() && NW.hasNoUnsignedSignedWrap()))
4564 Flags.setNoUnsignedWrap(true);
4565 Flags.setInBounds(NW.isInBounds());
4566
4567 OffsVal = DAG.getSExtOrTrunc(Op: OffsVal, DL: dl, VT: N.getValueType());
4568
4569 N = DAG.getMemBasePlusOffset(Base: N, Offset: OffsVal, DL: dl, Flags);
4570 continue;
4571 }
4572
4573 // N = N + Idx * ElementMul;
4574 SDValue IdxN = getValue(V: Idx);
4575
4576 if (IdxN.getValueType().isVector() != N.getValueType().isVector()) {
4577 if (N.getValueType().isVector()) {
4578 EVT VT = EVT::getVectorVT(Context&: *Context, VT: IdxN.getValueType(),
4579 EC: VectorElementCount);
4580 IdxN = DAG.getSplat(VT, DL: dl, Op: IdxN);
4581 } else {
4582 EVT VT =
4583 EVT::getVectorVT(Context&: *Context, VT: N.getValueType(), EC: VectorElementCount);
4584 N = DAG.getSplat(VT, DL: dl, Op: N);
4585 }
4586 }
4587
4588 // If the index is smaller or larger than intptr_t, truncate or extend
4589 // it.
4590 IdxN = DAG.getSExtOrTrunc(Op: IdxN, DL: dl, VT: N.getValueType());
4591
4592 SDNodeFlags ScaleFlags;
4593 // The multiplication of an index by the type size does not wrap the
4594 // pointer index type in a signed sense (mul nsw).
4595 ScaleFlags.setNoSignedWrap(NW.hasNoUnsignedSignedWrap());
4596
4597 // The multiplication of an index by the type size does not wrap the
4598 // pointer index type in an unsigned sense (mul nuw).
4599 ScaleFlags.setNoUnsignedWrap(NW.hasNoUnsignedWrap());
4600
4601 if (ElementScalable) {
4602 EVT VScaleTy = N.getValueType().getScalarType();
4603 SDValue VScale = DAG.getNode(
4604 Opcode: ISD::VSCALE, DL: dl, VT: VScaleTy,
4605 Operand: DAG.getConstant(Val: ElementMul.getZExtValue(), DL: dl, VT: VScaleTy));
4606 if (N.getValueType().isVector())
4607 VScale = DAG.getSplatVector(VT: N.getValueType(), DL: dl, Op: VScale);
4608 IdxN = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: N.getValueType(), N1: IdxN, N2: VScale,
4609 Flags: ScaleFlags);
4610 } else {
4611 // If this is a multiply by a power of two, turn it into a shl
4612 // immediately. This is a very common case.
4613 if (ElementMul != 1) {
4614 if (ElementMul.isPowerOf2()) {
4615 unsigned Amt = ElementMul.logBase2();
4616 IdxN = DAG.getNode(
4617 Opcode: ISD::SHL, DL: dl, VT: N.getValueType(), N1: IdxN,
4618 N2: DAG.getShiftAmountConstant(Val: Amt, VT: N.getValueType(), DL: dl),
4619 Flags: ScaleFlags);
4620 } else {
4621 SDValue Scale = DAG.getConstant(Val: ElementMul.getZExtValue(), DL: dl,
4622 VT: IdxN.getValueType());
4623 IdxN = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: N.getValueType(), N1: IdxN, N2: Scale,
4624 Flags: ScaleFlags);
4625 }
4626 }
4627 }
4628
4629 // The successive addition of the current address, truncated to the
4630 // pointer index type and interpreted as an unsigned number, and each
4631 // offset, also interpreted as an unsigned number, does not wrap the
4632 // pointer index type (add nuw).
4633 SDNodeFlags AddFlags;
4634 AddFlags.setNoUnsignedWrap(NW.hasNoUnsignedWrap());
4635 AddFlags.setInBounds(NW.isInBounds());
4636
4637 N = DAG.getMemBasePlusOffset(Base: N, Offset: IdxN, DL: dl, Flags: AddFlags);
4638 }
4639 }
4640
4641 if (IsVectorGEP && !N.getValueType().isVector()) {
4642 EVT VT = EVT::getVectorVT(Context&: *Context, VT: N.getValueType(), EC: VectorElementCount);
4643 N = DAG.getSplat(VT, DL: dl, Op: N);
4644 }
4645
4646 MVT PtrTy = TLI.getPointerTy(DL: DAG.getDataLayout(), AS);
4647 MVT PtrMemTy = TLI.getPointerMemTy(DL: DAG.getDataLayout(), AS);
4648 if (IsVectorGEP) {
4649 PtrTy = MVT::getVectorVT(VT: PtrTy, EC: VectorElementCount);
4650 PtrMemTy = MVT::getVectorVT(VT: PtrMemTy, EC: VectorElementCount);
4651 }
4652
4653 if (PtrMemTy != PtrTy && !cast<GEPOperator>(Val: I).isInBounds())
4654 N = DAG.getPtrExtendInReg(Op: N, DL: dl, VT: PtrMemTy);
4655
4656 setValue(V: &I, NewN: N);
4657}
4658
4659void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
4660 // If this is a fixed sized alloca in the entry block of the function,
4661 // allocate it statically on the stack.
4662 if (FuncInfo.StaticAllocaMap.count(Val: &I))
4663 return; // getValue will auto-populate this.
4664
4665 SDLoc dl = getCurSDLoc();
4666 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4667 auto &DL = DAG.getDataLayout();
4668 TypeSize TySize = I.getAllocationBaseSize(DL);
4669 MaybeAlign Alignment = I.getAlign();
4670
4671 SDValue AllocSize = getValue(V: I.getArraySize());
4672
4673 EVT IntPtr = TLI.getPointerTy(DL, AS: I.getAddressSpace());
4674 if (AllocSize.getValueType() != IntPtr)
4675 AllocSize = DAG.getZExtOrTrunc(Op: AllocSize, DL: dl, VT: IntPtr);
4676
4677 AllocSize = DAG.getNode(
4678 Opcode: ISD::MUL, DL: dl, VT: IntPtr, N1: AllocSize,
4679 N2: DAG.getZExtOrTrunc(Op: DAG.getTypeSize(DL: dl, VT: MVT::i64, TS: TySize), DL: dl, VT: IntPtr));
4680
4681 // Handle alignment. If the requested alignment is less than or equal to
4682 // the stack alignment, ignore it. If the size is greater than or equal to
4683 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
4684 Align StackAlign = DAG.getSubtarget().getFrameLowering()->getStackAlign();
4685 if (*Alignment <= StackAlign)
4686 Alignment = std::nullopt;
4687
4688 const uint64_t StackAlignMask = StackAlign.value() - 1U;
4689 // Round the size of the allocation up to the stack alignment size
4690 // by add SA-1 to the size. This doesn't overflow because we're computing
4691 // an address inside an alloca.
4692 AllocSize = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: AllocSize.getValueType(), N1: AllocSize,
4693 N2: DAG.getConstant(Val: StackAlignMask, DL: dl, VT: IntPtr),
4694 Flags: SDNodeFlags::NoUnsignedWrap);
4695
4696 // Mask out the low bits for alignment purposes.
4697 AllocSize = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AllocSize.getValueType(), N1: AllocSize,
4698 N2: DAG.getSignedConstant(Val: ~StackAlignMask, DL: dl, VT: IntPtr));
4699
4700 SDValue Ops[] = {
4701 getRoot(), AllocSize,
4702 DAG.getConstant(Val: Alignment ? Alignment->value() : 0, DL: dl, VT: IntPtr)};
4703 SDVTList VTs = DAG.getVTList(VT1: AllocSize.getValueType(), VT2: MVT::Other);
4704 SDValue DSA = DAG.getNode(Opcode: ISD::DYNAMIC_STACKALLOC, DL: dl, VTList: VTs, Ops);
4705 setValue(V: &I, NewN: DSA);
4706 DAG.setRoot(DSA.getValue(R: 1));
4707
4708 assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects());
4709}
4710
4711static const MDNode *getRangeMetadata(const Instruction &I) {
4712 return I.getMetadata(KindID: LLVMContext::MD_range);
4713}
4714
4715static std::optional<ConstantRange> getRange(const Instruction &I) {
4716 if (const auto *CB = dyn_cast<CallBase>(Val: &I))
4717 if (std::optional<ConstantRange> CR = CB->getRange())
4718 return CR;
4719 if (const MDNode *Range = getRangeMetadata(I))
4720 return getConstantRangeFromMetadata(RangeMD: *Range);
4721 return std::nullopt;
4722}
4723
4724static FPClassTest getNoFPClass(const Instruction &I) {
4725 if (const auto *CB = dyn_cast<CallBase>(Val: &I))
4726 return CB->getRetNoFPClass();
4727 return fcNone;
4728}
4729
4730void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
4731 if (I.isAtomic())
4732 return visitAtomicLoad(I);
4733
4734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4735 const Value *SV = I.getOperand(i_nocapture: 0);
4736 if (TLI.supportSwiftError()) {
4737 // Swifterror values can come from either a function parameter with
4738 // swifterror attribute or an alloca with swifterror attribute.
4739 if (const Argument *Arg = dyn_cast<Argument>(Val: SV)) {
4740 if (Arg->hasSwiftErrorAttr())
4741 return visitLoadFromSwiftError(I);
4742 }
4743
4744 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: SV)) {
4745 if (Alloca->isSwiftError())
4746 return visitLoadFromSwiftError(I);
4747 }
4748 }
4749
4750 SDValue Ptr = getValue(V: SV);
4751
4752 Type *Ty = I.getType();
4753 SmallVector<EVT, 4> ValueVTs, MemVTs;
4754 SmallVector<TypeSize, 4> Offsets;
4755 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty, ValueVTs, MemVTs: &MemVTs, Offsets: &Offsets);
4756 unsigned NumValues = ValueVTs.size();
4757 if (NumValues == 0)
4758 return;
4759
4760 Align Alignment = I.getAlign();
4761 AAMDNodes AAInfo = I.getAAMetadata();
4762 const MDNode *Ranges = getRangeMetadata(I);
4763 const MDNode *MemCacheHint = getMemCacheHintMetadata(I);
4764 bool isVolatile = I.isVolatile();
4765 MachineMemOperand::Flags MMOFlags =
4766 TLI.getLoadMemOperandFlags(LI: I, DL: DAG.getDataLayout(), AC, LibInfo);
4767
4768 SDValue Root;
4769 bool ConstantMemory = false;
4770 if (isVolatile)
4771 // Serialize volatile loads with other side effects.
4772 Root = getRoot();
4773 else if (NumValues > MaxParallelChains)
4774 Root = getMemoryRoot();
4775 else if (BatchAA &&
4776 BatchAA->pointsToConstantMemory(Loc: MemoryLocation(
4777 SV,
4778 LocationSize::precise(Value: DAG.getDataLayout().getTypeStoreSize(Ty)),
4779 AAInfo))) {
4780 // Do not serialize (non-volatile) loads of constant memory with anything.
4781 Root = DAG.getEntryNode();
4782 ConstantMemory = true;
4783 MMOFlags |= MachineMemOperand::MOInvariant;
4784 } else {
4785 // Do not serialize non-volatile loads against each other.
4786 Root = DAG.getRoot();
4787 }
4788
4789 SDLoc dl = getCurSDLoc();
4790
4791 if (isVolatile)
4792 Root = TLI.prepareVolatileOrAtomicLoad(Chain: Root, DL: dl, DAG);
4793
4794 SmallVector<SDValue, 4> Values(NumValues);
4795 SmallVector<SDValue, 4> Chains(std::min(a: MaxParallelChains, b: NumValues));
4796
4797 unsigned ChainI = 0;
4798 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4799 // Serializing loads here may result in excessive register pressure, and
4800 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
4801 // could recover a bit by hoisting nodes upward in the chain by recognizing
4802 // they are side-effect free or do not alias. The optimizer should really
4803 // avoid this case by converting large object/array copies to llvm.memcpy
4804 // (MaxParallelChains should always remain as failsafe).
4805 if (ChainI == MaxParallelChains) {
4806 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
4807 SDValue Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other,
4808 Ops: ArrayRef(Chains.data(), ChainI));
4809 Root = Chain;
4810 ChainI = 0;
4811 }
4812
4813 // TODO: MachinePointerInfo only supports a fixed length offset.
4814 MachinePointerInfo PtrInfo =
4815 !Offsets[i].isScalable() || Offsets[i].isZero()
4816 ? MachinePointerInfo(SV, Offsets[i].getKnownMinValue())
4817 : MachinePointerInfo();
4818
4819 SDValue A = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: Offsets[i]);
4820 SDValue L =
4821 DAG.getLoad(VT: MemVTs[i], dl, Chain: Root, Ptr: A, PtrInfo, Alignment, MMOFlags,
4822 Metadata: MMOMetadata(AAInfo, Ranges, MemCacheHint));
4823 Chains[ChainI] = L.getValue(R: 1);
4824
4825 if (MemVTs[i] != ValueVTs[i])
4826 L = DAG.getPtrExtOrTrunc(Op: L, DL: dl, VT: ValueVTs[i]);
4827
4828 if (MDNode *NoFPClassMD = I.getMetadata(KindID: LLVMContext::MD_nofpclass)) {
4829 uint64_t FPTestInt =
4830 cast<ConstantInt>(
4831 Val: cast<ConstantAsMetadata>(Val: NoFPClassMD->getOperand(I: 0))->getValue())
4832 ->getZExtValue();
4833 if (FPTestInt != fcNone) {
4834 SDValue FPTestConst =
4835 DAG.getTargetConstant(Val: FPTestInt, DL: SDLoc(), VT: MVT::i32);
4836 L = DAG.getNode(Opcode: ISD::AssertNoFPClass, DL: dl, VT: L.getValueType(), N1: L,
4837 N2: FPTestConst);
4838 }
4839 }
4840 Values[i] = L;
4841 }
4842
4843 if (!ConstantMemory) {
4844 SDValue Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other,
4845 Ops: ArrayRef(Chains.data(), ChainI));
4846 if (isVolatile)
4847 DAG.setRoot(Chain);
4848 else
4849 PendingLoads.push_back(Elt: Chain);
4850 }
4851
4852 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: dl,
4853 VTList: DAG.getVTList(VTs: ValueVTs), Ops: Values));
4854}
4855
4856void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
4857 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&
4858 "call visitStoreToSwiftError when backend supports swifterror");
4859
4860 SmallVector<EVT, 4> ValueVTs;
4861 SmallVector<uint64_t, 4> Offsets;
4862 const Value *SrcV = I.getOperand(i_nocapture: 0);
4863 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(),
4864 Ty: SrcV->getType(), ValueVTs, /*MemVTs=*/nullptr, FixedOffsets: &Offsets, StartingOffset: 0);
4865 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4866 "expect a single EVT for swifterror");
4867
4868 SDValue Src = getValue(V: SrcV);
4869 // Create a virtual register, then update the virtual register.
4870 Register VReg =
4871 SwiftError.getOrCreateVRegDefAt(&I, FuncInfo.MBB, I.getPointerOperand());
4872 // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
4873 // Chain can be getRoot or getControlRoot.
4874 SDValue CopyNode = DAG.getCopyToReg(Chain: getRoot(), dl: getCurSDLoc(), Reg: VReg,
4875 N: SDValue(Src.getNode(), Src.getResNo()));
4876 DAG.setRoot(CopyNode);
4877}
4878
4879void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
4880 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&
4881 "call visitLoadFromSwiftError when backend supports swifterror");
4882
4883 assert(!I.isVolatile() &&
4884 !I.hasMetadata(LLVMContext::MD_nontemporal) &&
4885 !I.hasMetadata(LLVMContext::MD_invariant_load) &&
4886 "Support volatile, non temporal, invariant for load_from_swift_error");
4887
4888 const Value *SV = I.getOperand(i_nocapture: 0);
4889 Type *Ty = I.getType();
4890 assert(
4891 (!BatchAA ||
4892 !BatchAA->pointsToConstantMemory(MemoryLocation(
4893 SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),
4894 I.getAAMetadata()))) &&
4895 "load_from_swift_error should not be constant memory");
4896
4897 SmallVector<EVT, 4> ValueVTs;
4898 SmallVector<uint64_t, 4> Offsets;
4899 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(), Ty,
4900 ValueVTs, /*MemVTs=*/nullptr, FixedOffsets: &Offsets, StartingOffset: 0);
4901 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4902 "expect a single EVT for swifterror");
4903
4904 // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
4905 SDValue L = DAG.getCopyFromReg(
4906 Chain: getRoot(), dl: getCurSDLoc(),
4907 Reg: SwiftError.getOrCreateVRegUseAt(&I, FuncInfo.MBB, SV), VT: ValueVTs[0]);
4908
4909 setValue(V: &I, NewN: L);
4910}
4911
4912void SelectionDAGBuilder::visitStore(const StoreInst &I) {
4913 if (I.isAtomic())
4914 return visitAtomicStore(I);
4915
4916 const Value *SrcV = I.getOperand(i_nocapture: 0);
4917 const Value *PtrV = I.getOperand(i_nocapture: 1);
4918
4919 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4920 if (TLI.supportSwiftError()) {
4921 // Swifterror values can come from either a function parameter with
4922 // swifterror attribute or an alloca with swifterror attribute.
4923 if (const Argument *Arg = dyn_cast<Argument>(Val: PtrV)) {
4924 if (Arg->hasSwiftErrorAttr())
4925 return visitStoreToSwiftError(I);
4926 }
4927
4928 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: PtrV)) {
4929 if (Alloca->isSwiftError())
4930 return visitStoreToSwiftError(I);
4931 }
4932 }
4933
4934 SmallVector<EVT, 4> ValueVTs, MemVTs;
4935 SmallVector<TypeSize, 4> Offsets;
4936 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(),
4937 Ty: SrcV->getType(), ValueVTs, MemVTs: &MemVTs, Offsets: &Offsets);
4938 unsigned NumValues = ValueVTs.size();
4939 if (NumValues == 0)
4940 return;
4941
4942 // Get the lowered operands. Note that we do this after
4943 // checking if NumResults is zero, because with zero results
4944 // the operands won't have values in the map.
4945 SDValue Src = getValue(V: SrcV);
4946 SDValue Ptr = getValue(V: PtrV);
4947
4948 SDValue Root = I.isVolatile() ? getRoot() : getMemoryRoot();
4949 SmallVector<SDValue, 4> Chains(std::min(a: MaxParallelChains, b: NumValues));
4950 SDLoc dl = getCurSDLoc();
4951 Align Alignment = I.getAlign();
4952 AAMDNodes AAInfo = I.getAAMetadata();
4953 const MDNode *MemCacheHint =
4954 getMemCacheHintMetadata(I, OperandNo: I.getPointerOperandIndex());
4955
4956 auto MMOFlags = TLI.getStoreMemOperandFlags(SI: I, DL: DAG.getDataLayout());
4957
4958 unsigned ChainI = 0;
4959 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4960 // See visitLoad comments.
4961 if (ChainI == MaxParallelChains) {
4962 SDValue Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other,
4963 Ops: ArrayRef(Chains.data(), ChainI));
4964 Root = Chain;
4965 ChainI = 0;
4966 }
4967
4968 // TODO: MachinePointerInfo only supports a fixed length offset.
4969 MachinePointerInfo PtrInfo =
4970 !Offsets[i].isScalable() || Offsets[i].isZero()
4971 ? MachinePointerInfo(PtrV, Offsets[i].getKnownMinValue())
4972 : MachinePointerInfo();
4973
4974 SDValue Add = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: Offsets[i]);
4975 SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
4976 if (MemVTs[i] != ValueVTs[i])
4977 Val = DAG.getPtrExtOrTrunc(Op: Val, DL: dl, VT: MemVTs[i]);
4978 SDValue St =
4979 DAG.getStore(Chain: Root, dl, Val, Ptr: Add, PtrInfo, Alignment, MMOFlags,
4980 Metadata: MMOMetadata(AAInfo, /*Ranges=*/nullptr, MemCacheHint));
4981 Chains[ChainI] = St;
4982 }
4983
4984 SDValue StoreNode = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other,
4985 Ops: ArrayRef(Chains.data(), ChainI));
4986 setValue(V: &I, NewN: StoreNode);
4987 DAG.setRoot(StoreNode);
4988}
4989
4990void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
4991 bool IsCompressing) {
4992 SDLoc sdl = getCurSDLoc();
4993
4994 Value *Src0Operand = I.getArgOperand(i: 0);
4995 Value *PtrOperand = I.getArgOperand(i: 1);
4996 Value *MaskOperand = I.getArgOperand(i: 2);
4997 Align Alignment = I.getParamAlign(ArgNo: 1).valueOrOne();
4998
4999 SDValue Ptr = getValue(V: PtrOperand);
5000 SDValue Src0 = getValue(V: Src0Operand);
5001 SDValue Mask = getValue(V: MaskOperand);
5002 SDValue Offset = DAG.getPOISON(VT: Ptr.getValueType());
5003
5004 EVT VT = Src0.getValueType();
5005
5006 const auto &TLI = DAG.getTargetLoweringInfo();
5007
5008 auto MMOFlags = MachineMemOperand::MOStore;
5009 MMOFlags |= TLI.getTargetMMOFlags(I);
5010 if (I.hasMetadata(KindID: LLVMContext::MD_nontemporal))
5011 MMOFlags |= MachineMemOperand::MONonTemporal;
5012
5013 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
5014 PtrInfo: MachinePointerInfo(PtrOperand), F: MMOFlags,
5015 Size: LocationSize::upperBound(Value: VT.getStoreSize()), BaseAlignment: Alignment,
5016 Metadata: I.getAAMetadata());
5017
5018 SDValue StoreNode =
5019 !IsCompressing && TTI->hasConditionalLoadStoreForType(
5020 Ty: I.getArgOperand(i: 0)->getType(), /*IsStore=*/true)
5021 ? TLI.visitMaskedStore(DAG, DL: sdl, Chain: getMemoryRoot(), MMO, Ptr, Val: Src0,
5022 Mask)
5023 : DAG.getMaskedStore(Chain: getMemoryRoot(), dl: sdl, Val: Src0, Base: Ptr, Offset, Mask,
5024 MemVT: VT, MMO, AM: ISD::UNINDEXED, /*Truncating=*/IsTruncating: false,
5025 IsCompressing);
5026 DAG.setRoot(StoreNode);
5027 setValue(V: &I, NewN: StoreNode);
5028}
5029
5030// Get a uniform base for the Gather/Scatter intrinsic.
5031// The first argument of the Gather/Scatter intrinsic is a vector of pointers.
5032// We try to represent it as a base pointer + vector of indices.
5033// Usually, the vector of pointers comes from a 'getelementptr' instruction.
5034// The first operand of the GEP may be a single pointer or a vector of pointers
5035// Example:
5036// %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
5037// or
5038// %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
5039// %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
5040//
5041// When the first GEP operand is a single pointer - it is the uniform base we
5042// are looking for. If first operand of the GEP is a splat vector - we
5043// extract the splat value and use it as a uniform base.
5044// In all other cases the function returns 'false'.
5045static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index,
5046 SDValue &Scale, SelectionDAGBuilder *SDB,
5047 const BasicBlock *CurBB, uint64_t ElemSize) {
5048 SelectionDAG& DAG = SDB->DAG;
5049 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5050 const DataLayout &DL = DAG.getDataLayout();
5051
5052 assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type");
5053
5054 // Handle splat constant pointer.
5055 if (auto *C = dyn_cast<Constant>(Val: Ptr)) {
5056 C = C->getSplatValue();
5057 if (!C)
5058 return false;
5059
5060 Base = SDB->getValue(V: C);
5061
5062 ElementCount NumElts = cast<VectorType>(Val: Ptr->getType())->getElementCount();
5063 EVT VT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: TLI.getPointerTy(DL), EC: NumElts);
5064 Index = DAG.getConstant(Val: 0, DL: SDB->getCurSDLoc(), VT);
5065 Scale = DAG.getTargetConstant(Val: 1, DL: SDB->getCurSDLoc(), VT: TLI.getPointerTy(DL));
5066 return true;
5067 }
5068
5069 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Val: Ptr);
5070 if (!GEP || GEP->getParent() != CurBB)
5071 return false;
5072
5073 if (GEP->getNumOperands() != 2)
5074 return false;
5075
5076 const Value *BasePtr = GEP->getPointerOperand();
5077 const Value *IndexVal = GEP->getOperand(i_nocapture: GEP->getNumOperands() - 1);
5078
5079 // Make sure the base is scalar and the index is a vector.
5080 if (BasePtr->getType()->isVectorTy() || !IndexVal->getType()->isVectorTy())
5081 return false;
5082
5083 TypeSize ScaleVal = DL.getTypeAllocSize(Ty: GEP->getResultElementType());
5084 if (ScaleVal.isScalable())
5085 return false;
5086
5087 // Target may not support the required addressing mode.
5088 if (ScaleVal != 1 &&
5089 !TLI.isLegalScaleForGatherScatter(Scale: ScaleVal.getFixedValue(), ElemSize))
5090 return false;
5091
5092 Base = SDB->getValue(V: BasePtr);
5093 Index = SDB->getValue(V: IndexVal);
5094
5095 Scale =
5096 DAG.getTargetConstant(Val: ScaleVal, DL: SDB->getCurSDLoc(), VT: TLI.getPointerTy(DL));
5097 return true;
5098}
5099
5100void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
5101 SDLoc sdl = getCurSDLoc();
5102
5103 // llvm.masked.scatter.*(Src0, Ptrs, Mask)
5104 const Value *Ptr = I.getArgOperand(i: 1);
5105 SDValue Src0 = getValue(V: I.getArgOperand(i: 0));
5106 SDValue Mask = getValue(V: I.getArgOperand(i: 2));
5107 EVT VT = Src0.getValueType();
5108 Align Alignment = I.getParamAlign(ArgNo: 1).valueOrOne();
5109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5110
5111 SDValue Base;
5112 SDValue Index;
5113 SDValue Scale;
5114 bool UniformBase = getUniformBase(Ptr, Base, Index, Scale, SDB: this,
5115 CurBB: I.getParent(), ElemSize: VT.getScalarStoreSize());
5116
5117 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
5118 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
5119 PtrInfo: MachinePointerInfo(AS), F: MachineMemOperand::MOStore,
5120 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: Alignment, Metadata: I.getAAMetadata());
5121 if (!UniformBase) {
5122 Base = DAG.getConstant(Val: 0, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
5123 Index = getValue(V: Ptr);
5124 Scale =
5125 DAG.getTargetConstant(Val: 1, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
5126 }
5127
5128 EVT IdxVT = Index.getValueType();
5129 EVT EltTy = IdxVT.getVectorElementType();
5130 if (TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
5131 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
5132 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: sdl, VT: NewIdxVT, Operand: Index);
5133 }
5134
5135 SDValue Ops[] = { getMemoryRoot(), Src0, Mask, Base, Index, Scale };
5136 SDValue Scatter = DAG.getMaskedScatter(VTs: DAG.getVTList(VT: MVT::Other), MemVT: VT, dl: sdl,
5137 Ops, MMO, IndexType: ISD::SIGNED_SCALED, IsTruncating: false);
5138 DAG.setRoot(Scatter);
5139 setValue(V: &I, NewN: Scatter);
5140}
5141
5142void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
5143 SDLoc sdl = getCurSDLoc();
5144
5145 Value *PtrOperand = I.getArgOperand(i: 0);
5146 Value *MaskOperand = I.getArgOperand(i: 1);
5147 Value *Src0Operand = I.getArgOperand(i: 2);
5148 Align Alignment = I.getParamAlign(ArgNo: 0).valueOrOne();
5149
5150 SDValue Ptr = getValue(V: PtrOperand);
5151 SDValue Src0 = getValue(V: Src0Operand);
5152 SDValue Mask = getValue(V: MaskOperand);
5153 SDValue Offset = DAG.getPOISON(VT: Ptr.getValueType());
5154
5155 EVT VT = Src0.getValueType();
5156 AAMDNodes AAInfo = I.getAAMetadata();
5157 const MDNode *Ranges = getRangeMetadata(I);
5158
5159 // Do not serialize masked loads of constant memory with anything.
5160 MemoryLocation ML = MemoryLocation::getAfter(Ptr: PtrOperand, AATags: AAInfo);
5161 bool AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(Loc: ML);
5162
5163 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
5164
5165 const auto &TLI = DAG.getTargetLoweringInfo();
5166
5167 auto MMOFlags = MachineMemOperand::MOLoad;
5168 MMOFlags |= TLI.getTargetMMOFlags(I);
5169 if (I.hasMetadata(KindID: LLVMContext::MD_nontemporal))
5170 MMOFlags |= MachineMemOperand::MONonTemporal;
5171 if (I.hasMetadata(KindID: LLVMContext::MD_invariant_load))
5172 MMOFlags |= MachineMemOperand::MOInvariant;
5173
5174 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
5175 PtrInfo: MachinePointerInfo(PtrOperand), F: MMOFlags,
5176 Size: LocationSize::upperBound(Value: VT.getStoreSize()), BaseAlignment: Alignment,
5177 Metadata: MMOMetadata(AAInfo, Ranges));
5178
5179 // The Load/Res may point to different values and both of them are output
5180 // variables.
5181 SDValue Load;
5182 SDValue Res;
5183 if (!IsExpanding &&
5184 TTI->hasConditionalLoadStoreForType(Ty: Src0Operand->getType(),
5185 /*IsStore=*/false))
5186 Res = TLI.visitMaskedLoad(DAG, DL: sdl, Chain: InChain, MMO, NewLoad&: Load, Ptr, PassThru: Src0, Mask);
5187 else
5188 Res = Load =
5189 DAG.getMaskedLoad(VT, dl: sdl, Chain: InChain, Base: Ptr, Offset, Mask, Src0, MemVT: VT, MMO,
5190 AM: ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding);
5191 if (AddToChain)
5192 PendingLoads.push_back(Elt: Load.getValue(R: 1));
5193 setValue(V: &I, NewN: Res);
5194}
5195
5196void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
5197 SDLoc sdl = getCurSDLoc();
5198
5199 // @llvm.masked.gather.*(Ptrs, Mask, Src0)
5200 const Value *Ptr = I.getArgOperand(i: 0);
5201 SDValue Src0 = getValue(V: I.getArgOperand(i: 2));
5202 SDValue Mask = getValue(V: I.getArgOperand(i: 1));
5203
5204 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5205 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
5206 Align Alignment = I.getParamAlign(ArgNo: 0).valueOrOne();
5207
5208 const MDNode *Ranges = getRangeMetadata(I);
5209
5210 SDValue Root = DAG.getRoot();
5211 SDValue Base;
5212 SDValue Index;
5213 SDValue Scale;
5214 bool UniformBase = getUniformBase(Ptr, Base, Index, Scale, SDB: this,
5215 CurBB: I.getParent(), ElemSize: VT.getScalarStoreSize());
5216 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
5217 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
5218 PtrInfo: MachinePointerInfo(AS), F: MachineMemOperand::MOLoad,
5219 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: Alignment,
5220 Metadata: MMOMetadata(I.getAAMetadata(), Ranges));
5221
5222 if (!UniformBase) {
5223 Base = DAG.getConstant(Val: 0, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
5224 Index = getValue(V: Ptr);
5225 Scale =
5226 DAG.getTargetConstant(Val: 1, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
5227 }
5228
5229 EVT IdxVT = Index.getValueType();
5230 EVT EltTy = IdxVT.getVectorElementType();
5231 if (TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
5232 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
5233 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: sdl, VT: NewIdxVT, Operand: Index);
5234 }
5235
5236 SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale };
5237 SDValue Gather =
5238 DAG.getMaskedGather(VTs: DAG.getVTList(VT1: VT, VT2: MVT::Other), MemVT: VT, dl: sdl, Ops, MMO,
5239 IndexType: ISD::SIGNED_SCALED, ExtTy: ISD::NON_EXTLOAD);
5240
5241 PendingLoads.push_back(Elt: Gather.getValue(R: 1));
5242 setValue(V: &I, NewN: Gather);
5243}
5244
5245void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
5246 SDLoc dl = getCurSDLoc();
5247 AtomicOrdering SuccessOrdering = I.getSuccessOrdering();
5248 AtomicOrdering FailureOrdering = I.getFailureOrdering();
5249 SyncScope::ID SSID = I.getSyncScopeID();
5250
5251 SDValue InChain = getRoot();
5252
5253 MVT MemVT = getValue(V: I.getCompareOperand()).getSimpleValueType();
5254 SDVTList VTs = DAG.getVTList(VT1: MemVT, VT2: MVT::i1, VT3: MVT::Other);
5255
5256 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5257 auto Flags = TLI.getAtomicMemOperandFlags(AI: I, DL: DAG.getDataLayout());
5258
5259 MachineFunction &MF = DAG.getMachineFunction();
5260 MachineMemOperand *MMO = MF.getMachineMemOperand(
5261 PtrInfo: MachinePointerInfo(I.getPointerOperand()), F: Flags, Size: MemVT.getStoreSize(),
5262 BaseAlignment: I.getAlign(), Metadata: MMOMetadata(), SSID, Ordering: SuccessOrdering, FailureOrdering);
5263
5264 SDValue L = DAG.getAtomicCmpSwap(Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
5265 dl, MemVT, VTs, Chain: InChain,
5266 Ptr: getValue(V: I.getPointerOperand()),
5267 Cmp: getValue(V: I.getCompareOperand()),
5268 Swp: getValue(V: I.getNewValOperand()), MMO);
5269
5270 SDValue OutChain = L.getValue(R: 2);
5271
5272 setValue(V: &I, NewN: L);
5273 DAG.setRoot(OutChain);
5274}
5275
5276void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
5277 SDLoc dl = getCurSDLoc();
5278 ISD::NodeType NT;
5279 switch (I.getOperation()) {
5280 default: llvm_unreachable("Unknown atomicrmw operation");
5281 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
5282 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
5283 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
5284 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
5285 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
5286 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
5287 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
5288 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
5289 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
5290 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
5291 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
5292 case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break;
5293 case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break;
5294 case AtomicRMWInst::FMax: NT = ISD::ATOMIC_LOAD_FMAX; break;
5295 case AtomicRMWInst::FMin: NT = ISD::ATOMIC_LOAD_FMIN; break;
5296 case AtomicRMWInst::FMaximum:
5297 NT = ISD::ATOMIC_LOAD_FMAXIMUM;
5298 break;
5299 case AtomicRMWInst::FMinimum:
5300 NT = ISD::ATOMIC_LOAD_FMINIMUM;
5301 break;
5302 case AtomicRMWInst::FMaximumNum:
5303 NT = ISD::ATOMIC_LOAD_FMAXIMUMNUM;
5304 break;
5305 case AtomicRMWInst::FMinimumNum:
5306 NT = ISD::ATOMIC_LOAD_FMINIMUMNUM;
5307 break;
5308 case AtomicRMWInst::UIncWrap:
5309 NT = ISD::ATOMIC_LOAD_UINC_WRAP;
5310 break;
5311 case AtomicRMWInst::UDecWrap:
5312 NT = ISD::ATOMIC_LOAD_UDEC_WRAP;
5313 break;
5314 case AtomicRMWInst::USubCond:
5315 NT = ISD::ATOMIC_LOAD_USUB_COND;
5316 break;
5317 case AtomicRMWInst::USubSat:
5318 NT = ISD::ATOMIC_LOAD_USUB_SAT;
5319 break;
5320 }
5321 AtomicOrdering Ordering = I.getOrdering();
5322 SyncScope::ID SSID = I.getSyncScopeID();
5323
5324 SDValue InChain = getRoot();
5325
5326 auto MemVT = getValue(V: I.getValOperand()).getSimpleValueType();
5327 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5328 auto Flags = TLI.getAtomicMemOperandFlags(AI: I, DL: DAG.getDataLayout());
5329
5330 MachineFunction &MF = DAG.getMachineFunction();
5331 MachineMemOperand *MMO = MF.getMachineMemOperand(
5332 PtrInfo: MachinePointerInfo(I.getPointerOperand()), F: Flags, Size: MemVT.getStoreSize(),
5333 BaseAlignment: I.getAlign(), Metadata: MMOMetadata(), SSID, Ordering);
5334
5335 SDValue L =
5336 DAG.getAtomic(Opcode: NT, dl, MemVT, Chain: InChain,
5337 Ptr: getValue(V: I.getPointerOperand()), Val: getValue(V: I.getValOperand()),
5338 MMO);
5339
5340 SDValue OutChain = L.getValue(R: 1);
5341
5342 setValue(V: &I, NewN: L);
5343 DAG.setRoot(OutChain);
5344}
5345
5346void SelectionDAGBuilder::visitFence(const FenceInst &I) {
5347 SDLoc dl = getCurSDLoc();
5348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5349 SDValue Ops[3];
5350 Ops[0] = getRoot();
5351 Ops[1] = DAG.getTargetConstant(Val: (unsigned)I.getOrdering(), DL: dl,
5352 VT: TLI.getFenceOperandTy(DL: DAG.getDataLayout()));
5353 Ops[2] = DAG.getTargetConstant(Val: I.getSyncScopeID(), DL: dl,
5354 VT: TLI.getFenceOperandTy(DL: DAG.getDataLayout()));
5355 SDValue N = DAG.getNode(Opcode: ISD::ATOMIC_FENCE, DL: dl, VT: MVT::Other, Ops);
5356 setValue(V: &I, NewN: N);
5357 DAG.setRoot(N);
5358}
5359
5360void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
5361 SDLoc dl = getCurSDLoc();
5362 AtomicOrdering Order = I.getOrdering();
5363 SyncScope::ID SSID = I.getSyncScopeID();
5364
5365 SDValue InChain = getRoot();
5366
5367 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5368 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
5369 EVT MemVT = TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getType());
5370
5371 if (!TLI.supportsUnalignedAtomics() &&
5372 I.getAlign().value() < MemVT.getSizeInBits() / 8)
5373 report_fatal_error(reason: "Cannot generate unaligned atomic load");
5374
5375 auto Flags = TLI.getLoadMemOperandFlags(LI: I, DL: DAG.getDataLayout(), AC, LibInfo);
5376
5377 const MDNode *Ranges = getRangeMetadata(I);
5378 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
5379 PtrInfo: MachinePointerInfo(I.getPointerOperand()), F: Flags, Size: MemVT.getStoreSize(),
5380 BaseAlignment: I.getAlign(), Metadata: MMOMetadata(AAMDNodes(), Ranges), SSID, Ordering: Order);
5381
5382 InChain = TLI.prepareVolatileOrAtomicLoad(Chain: InChain, DL: dl, DAG);
5383
5384 SDValue Ptr = getValue(V: I.getPointerOperand());
5385 SDValue L =
5386 DAG.getAtomicLoad(ExtType: ISD::NON_EXTLOAD, dl, MemVT, VT: MemVT, Chain: InChain, Ptr, MMO);
5387
5388 SDValue OutChain = L.getValue(R: 1);
5389 if (MemVT != VT)
5390 L = DAG.getPtrExtOrTrunc(Op: L, DL: dl, VT);
5391
5392 setValue(V: &I, NewN: L);
5393 DAG.setRoot(OutChain);
5394}
5395
5396void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
5397 SDLoc dl = getCurSDLoc();
5398
5399 AtomicOrdering Ordering = I.getOrdering();
5400 SyncScope::ID SSID = I.getSyncScopeID();
5401
5402 SDValue InChain = getRoot();
5403
5404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5405 EVT MemVT =
5406 TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getValueOperand()->getType());
5407
5408 if (!TLI.supportsUnalignedAtomics() &&
5409 I.getAlign().value() < MemVT.getSizeInBits() / 8)
5410 report_fatal_error(reason: "Cannot generate unaligned atomic store");
5411
5412 auto Flags = TLI.getStoreMemOperandFlags(SI: I, DL: DAG.getDataLayout());
5413
5414 MachineFunction &MF = DAG.getMachineFunction();
5415 MachineMemOperand *MMO = MF.getMachineMemOperand(
5416 PtrInfo: MachinePointerInfo(I.getPointerOperand()), F: Flags, Size: MemVT.getStoreSize(),
5417 BaseAlignment: I.getAlign(), Metadata: MMOMetadata(), SSID, Ordering);
5418
5419 SDValue Val = getValue(V: I.getValueOperand());
5420 if (Val.getValueType() != MemVT)
5421 Val = DAG.getPtrExtOrTrunc(Op: Val, DL: dl, VT: MemVT);
5422 SDValue Ptr = getValue(V: I.getPointerOperand());
5423
5424 SDValue OutChain =
5425 DAG.getAtomic(Opcode: ISD::ATOMIC_STORE, dl, MemVT, Chain: InChain, Ptr: Val, Val: Ptr, MMO);
5426
5427 setValue(V: &I, NewN: OutChain);
5428 DAG.setRoot(OutChain);
5429}
5430
5431/// Check if this intrinsic call depends on the chain (1st return value)
5432/// and if it only *loads* memory.
5433/// Ignore the callsite's attributes. A specific call site may be marked with
5434/// readnone, but the lowering code will expect the chain based on the
5435/// definition.
5436std::pair<bool, bool>
5437SelectionDAGBuilder::getTargetIntrinsicCallProperties(const CallBase &I) {
5438 const Function *F = I.getCalledFunction();
5439 bool HasChain = !F->doesNotAccessMemory();
5440 bool OnlyLoad =
5441 HasChain && F->onlyReadsMemory() && F->willReturn() && F->doesNotThrow();
5442
5443 return {HasChain, OnlyLoad};
5444}
5445
5446SmallVector<SDValue, 8> SelectionDAGBuilder::getTargetIntrinsicOperands(
5447 const CallBase &I, bool HasChain, bool OnlyLoad,
5448 TargetLowering::IntrinsicInfo *TgtMemIntrinsicInfo) {
5449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5450
5451 // Build the operand list.
5452 SmallVector<SDValue, 8> Ops;
5453 if (HasChain) { // If this intrinsic has side-effects, chainify it.
5454 if (OnlyLoad) {
5455 // We don't need to serialize loads against other loads.
5456 Ops.push_back(Elt: DAG.getRoot());
5457 } else {
5458 Ops.push_back(Elt: getRoot());
5459 }
5460 }
5461
5462 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
5463 if (!TgtMemIntrinsicInfo || TgtMemIntrinsicInfo->opc == ISD::INTRINSIC_VOID ||
5464 TgtMemIntrinsicInfo->opc == ISD::INTRINSIC_W_CHAIN)
5465 Ops.push_back(Elt: DAG.getTargetConstant(Val: I.getIntrinsicID(), DL: getCurSDLoc(),
5466 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
5467
5468 // Add all operands of the call to the operand list.
5469 for (unsigned i = 0, e = I.arg_size(); i != e; ++i) {
5470 const Value *Arg = I.getArgOperand(i);
5471 if (!I.paramHasAttr(ArgNo: i, Kind: Attribute::ImmArg)) {
5472 Ops.push_back(Elt: getValue(V: Arg));
5473 continue;
5474 }
5475
5476 // Use TargetConstant instead of a regular constant for immarg.
5477 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: Arg->getType(), AllowUnknown: true);
5478 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: Arg)) {
5479 assert(CI->getBitWidth() <= 64 &&
5480 "large intrinsic immediates not handled");
5481 Ops.push_back(Elt: DAG.getTargetConstant(Val: *CI, DL: SDLoc(), VT));
5482 } else {
5483 Ops.push_back(
5484 Elt: DAG.getTargetConstantFP(Val: *cast<ConstantFP>(Val: Arg), DL: SDLoc(), VT));
5485 }
5486 }
5487
5488 if (std::optional<OperandBundleUse> Bundle =
5489 I.getOperandBundle(ID: LLVMContext::OB_deactivation_symbol)) {
5490 auto *Sym = Bundle->Inputs[0].get();
5491 SDValue SDSym = getValue(V: Sym);
5492 SDSym = DAG.getDeactivationSymbol(GV: cast<GlobalValue>(Val: Sym));
5493 Ops.push_back(Elt: SDSym);
5494 }
5495
5496 if (std::optional<OperandBundleUse> Bundle =
5497 I.getOperandBundle(ID: LLVMContext::OB_convergencectrl)) {
5498 Value *Token = Bundle->Inputs[0].get();
5499 SDValue ConvControlToken = getValue(V: Token);
5500 assert(Ops.back().getValueType() != MVT::Glue &&
5501 "Did not expect another glue node here.");
5502 ConvControlToken =
5503 DAG.getNode(Opcode: ISD::CONVERGENCECTRL_GLUE, DL: {}, VT: MVT::Glue, Operand: ConvControlToken);
5504 Ops.push_back(Elt: ConvControlToken);
5505 }
5506
5507 return Ops;
5508}
5509
5510SDVTList SelectionDAGBuilder::getTargetIntrinsicVTList(const CallBase &I,
5511 bool HasChain) {
5512 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5513
5514 SmallVector<EVT, 4> ValueVTs;
5515 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: I.getType(), ValueVTs);
5516
5517 if (HasChain)
5518 ValueVTs.push_back(Elt: MVT::Other);
5519
5520 return DAG.getVTList(VTs: ValueVTs);
5521}
5522
5523/// Get an INTRINSIC node for a target intrinsic which does not touch memory.
5524SDValue SelectionDAGBuilder::getTargetNonMemIntrinsicNode(
5525 const Type &IntrinsicVT, bool HasChain, ArrayRef<SDValue> Ops,
5526 const SDVTList &VTs) {
5527 if (!HasChain)
5528 return DAG.getNode(Opcode: ISD::INTRINSIC_WO_CHAIN, DL: getCurSDLoc(), VTList: VTs, Ops);
5529 if (!IntrinsicVT.isVoidTy())
5530 return DAG.getNode(Opcode: ISD::INTRINSIC_W_CHAIN, DL: getCurSDLoc(), VTList: VTs, Ops);
5531 return DAG.getNode(Opcode: ISD::INTRINSIC_VOID, DL: getCurSDLoc(), VTList: VTs, Ops);
5532}
5533
5534/// Set root, convert return type if necessary and check alignment.
5535SDValue SelectionDAGBuilder::handleTargetIntrinsicRet(const CallBase &I,
5536 bool HasChain,
5537 bool OnlyLoad,
5538 SDValue Result) {
5539 if (HasChain) {
5540 SDValue Chain = Result.getValue(R: Result.getNode()->getNumValues() - 1);
5541 if (OnlyLoad)
5542 PendingLoads.push_back(Elt: Chain);
5543 else
5544 DAG.setRoot(Chain);
5545 }
5546
5547 if (I.getType()->isVoidTy())
5548 return Result;
5549
5550 if (MaybeAlign Alignment = I.getRetAlign(); InsertAssertAlign && Alignment) {
5551 // Insert `assertalign` node if there's an alignment.
5552 Result = DAG.getAssertAlign(DL: getCurSDLoc(), V: Result, A: Alignment.valueOrOne());
5553 } else if (!isa<VectorType>(Val: I.getType())) {
5554 Result = lowerRangeToAssertZExt(DAG, I, Op: Result);
5555 }
5556
5557 return Result;
5558}
5559
5560/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
5561/// node.
5562void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
5563 unsigned Intrinsic) {
5564 auto [HasChain, OnlyLoad] = getTargetIntrinsicCallProperties(I);
5565 Intrinsic::ID IntrinsicID = static_cast<Intrinsic::ID>(Intrinsic);
5566
5567 if (!DAG.getMachineFunction().getSubtarget().isIntrinsicSupported(
5568 IntrinsicID: Intrinsic)) {
5569 SDLoc DL = getCurSDLoc();
5570 DAG.getContext()->diagnose(DI: DiagnosticInfoUnsupportedTargetIntrinsic(
5571 *I.getFunction(), IntrinsicID, DL.getDebugLoc()));
5572
5573 // The intrinsic is not available on this subtarget. Preserve the chain for
5574 // side-effecting intrinsics and lower any result to poison so that
5575 // compilation can continue and collect further diagnostics.
5576 if (HasChain && !OnlyLoad)
5577 DAG.setRoot(getRoot());
5578
5579 setValueToPoison(V: &I, dl: DL);
5580 return;
5581 }
5582
5583 // Infos is set by getTgtMemIntrinsic.
5584 SmallVector<TargetLowering::IntrinsicInfo> Infos;
5585 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5586 TLI.getTgtMemIntrinsic(Infos, I, MF&: DAG.getMachineFunction(), Intrinsic);
5587 // Use the first (primary) info determines the node opcode.
5588 TargetLowering::IntrinsicInfo *Info = !Infos.empty() ? &Infos[0] : nullptr;
5589
5590 SmallVector<SDValue, 8> Ops =
5591 getTargetIntrinsicOperands(I, HasChain, OnlyLoad, TgtMemIntrinsicInfo: Info);
5592 SDVTList VTs = getTargetIntrinsicVTList(I, HasChain);
5593
5594 // Propagate fast-math-flags from IR to node(s).
5595 SDNodeFlags Flags;
5596 if (auto *FPMO = dyn_cast<FPMathOperator>(Val: &I))
5597 Flags.copyFMF(FPMO: *FPMO);
5598 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
5599
5600 // Create the node.
5601 SDValue Result;
5602
5603 // In some cases, custom collection of operands from CallInst I may be needed.
5604 TLI.CollectTargetIntrinsicOperands(I, Ops, DAG);
5605 if (!Infos.empty()) {
5606 // This is target intrinsic that touches memory
5607 // Create MachineMemOperands for each memory access described by the target.
5608 MachineFunction &MF = DAG.getMachineFunction();
5609 SmallVector<MachineMemOperand *> MMOs;
5610 for (const auto &Info : Infos) {
5611 // TODO: We currently just fallback to address space 0 if
5612 // getTgtMemIntrinsic didn't yield anything useful.
5613 MachinePointerInfo MPI;
5614 if (Info.ptrVal)
5615 MPI = MachinePointerInfo(Info.ptrVal, Info.offset);
5616 else if (Info.fallbackAddressSpace)
5617 MPI = MachinePointerInfo(*Info.fallbackAddressSpace);
5618 EVT MemVT = Info.memVT;
5619 LocationSize Size = LocationSize::precise(Value: Info.size);
5620 if (Size.hasValue() && !Size.getValue())
5621 Size = LocationSize::precise(Value: MemVT.getStoreSize());
5622 Align Alignment = Info.align.value_or(u: DAG.getEVTAlign(MemoryVT: MemVT));
5623 MachineMemOperand *MMO = MF.getMachineMemOperand(
5624 PtrInfo: MPI, F: Info.flags, Size, BaseAlignment: Alignment, Metadata: I.getAAMetadata(), SSID: Info.ssid,
5625 Ordering: Info.order, FailureOrdering: Info.failureOrder);
5626 MMOs.push_back(Elt: MMO);
5627 }
5628
5629 Result = DAG.getMemIntrinsicNode(Opcode: Info->opc, dl: getCurSDLoc(), VTList: VTs, Ops,
5630 MemVT: Info->memVT, MMOs);
5631 } else {
5632 Result = getTargetNonMemIntrinsicNode(IntrinsicVT: *I.getType(), HasChain, Ops, VTs);
5633 }
5634
5635 Result = handleTargetIntrinsicRet(I, HasChain, OnlyLoad, Result);
5636
5637 setValue(V: &I, NewN: Result);
5638}
5639
5640/// GetSignificand - Get the significand and build it into a floating-point
5641/// number with exponent of 1:
5642///
5643/// Op = (Op & 0x007fffff) | 0x3f800000;
5644///
5645/// where Op is the hexadecimal representation of floating point value.
5646static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) {
5647 SDValue t1 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: MVT::i32, N1: Op,
5648 N2: DAG.getConstant(Val: 0x007fffff, DL: dl, VT: MVT::i32));
5649 SDValue t2 = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: MVT::i32, N1: t1,
5650 N2: DAG.getConstant(Val: 0x3f800000, DL: dl, VT: MVT::i32));
5651 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32, Operand: t2);
5652}
5653
5654/// GetExponent - Get the exponent:
5655///
5656/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
5657///
5658/// where Op is the hexadecimal representation of floating point value.
5659static SDValue GetExponent(SelectionDAG &DAG, SDValue Op,
5660 const TargetLowering &TLI, const SDLoc &dl) {
5661 SDValue t0 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: MVT::i32, N1: Op,
5662 N2: DAG.getConstant(Val: 0x7f800000, DL: dl, VT: MVT::i32));
5663 SDValue t1 = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: MVT::i32, N1: t0,
5664 N2: DAG.getShiftAmountConstant(Val: 23, VT: MVT::i32, DL: dl));
5665 SDValue t2 = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: MVT::i32, N1: t1,
5666 N2: DAG.getConstant(Val: 127, DL: dl, VT: MVT::i32));
5667 return DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: MVT::f32, Operand: t2);
5668}
5669
5670/// getF32Constant - Get 32-bit floating point constant.
5671static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
5672 const SDLoc &dl) {
5673 return DAG.getConstantFP(Val: APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), DL: dl,
5674 VT: MVT::f32);
5675}
5676
5677static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl,
5678 SelectionDAG &DAG) {
5679 // TODO: What fast-math-flags should be set on the floating-point nodes?
5680
5681 // IntegerPartOfX = ((int32_t)(t0);
5682 SDValue IntegerPartOfX = DAG.getNode(Opcode: ISD::FP_TO_SINT, DL: dl, VT: MVT::i32, Operand: t0);
5683
5684 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
5685 SDValue t1 = DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: MVT::f32, Operand: IntegerPartOfX);
5686 SDValue X = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t0, N2: t1);
5687
5688 // IntegerPartOfX <<= 23;
5689 IntegerPartOfX = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: MVT::i32, N1: IntegerPartOfX,
5690 N2: DAG.getShiftAmountConstant(Val: 23, VT: MVT::i32, DL: dl));
5691
5692 SDValue TwoToFractionalPartOfX;
5693 if (LimitFloatPrecision <= 6) {
5694 // For floating-point precision of 6:
5695 //
5696 // TwoToFractionalPartOfX =
5697 // 0.997535578f +
5698 // (0.735607626f + 0.252464424f * x) * x;
5699 //
5700 // error 0.0144103317, which is 6 bits
5701 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5702 N2: getF32Constant(DAG, Flt: 0x3e814304, dl));
5703 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
5704 N2: getF32Constant(DAG, Flt: 0x3f3c50c8, dl));
5705 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5706 TwoToFractionalPartOfX = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5707 N2: getF32Constant(DAG, Flt: 0x3f7f5e7e, dl));
5708 } else if (LimitFloatPrecision <= 12) {
5709 // For floating-point precision of 12:
5710 //
5711 // TwoToFractionalPartOfX =
5712 // 0.999892986f +
5713 // (0.696457318f +
5714 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
5715 //
5716 // error 0.000107046256, which is 13 to 14 bits
5717 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5718 N2: getF32Constant(DAG, Flt: 0x3da235e3, dl));
5719 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
5720 N2: getF32Constant(DAG, Flt: 0x3e65b8f3, dl));
5721 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5722 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5723 N2: getF32Constant(DAG, Flt: 0x3f324b07, dl));
5724 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5725 TwoToFractionalPartOfX = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t6,
5726 N2: getF32Constant(DAG, Flt: 0x3f7ff8fd, dl));
5727 } else { // LimitFloatPrecision <= 18
5728 // For floating-point precision of 18:
5729 //
5730 // TwoToFractionalPartOfX =
5731 // 0.999999982f +
5732 // (0.693148872f +
5733 // (0.240227044f +
5734 // (0.554906021e-1f +
5735 // (0.961591928e-2f +
5736 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
5737 // error 2.47208000*10^(-7), which is better than 18 bits
5738 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5739 N2: getF32Constant(DAG, Flt: 0x3924b03e, dl));
5740 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
5741 N2: getF32Constant(DAG, Flt: 0x3ab24b87, dl));
5742 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5743 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5744 N2: getF32Constant(DAG, Flt: 0x3c1d8c17, dl));
5745 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5746 SDValue t7 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t6,
5747 N2: getF32Constant(DAG, Flt: 0x3d634a1d, dl));
5748 SDValue t8 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t7, N2: X);
5749 SDValue t9 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t8,
5750 N2: getF32Constant(DAG, Flt: 0x3e75fe14, dl));
5751 SDValue t10 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t9, N2: X);
5752 SDValue t11 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t10,
5753 N2: getF32Constant(DAG, Flt: 0x3f317234, dl));
5754 SDValue t12 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t11, N2: X);
5755 TwoToFractionalPartOfX = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t12,
5756 N2: getF32Constant(DAG, Flt: 0x3f800000, dl));
5757 }
5758
5759 // Add the exponent into the result in integer domain.
5760 SDValue t13 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: TwoToFractionalPartOfX);
5761 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32,
5762 Operand: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: t13, N2: IntegerPartOfX));
5763}
5764
5765/// expandExp - Lower an exp intrinsic. Handles the special sequences for
5766/// limited-precision mode.
5767static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5768 const TargetLowering &TLI, SDNodeFlags Flags) {
5769 if (Op.getValueType() == MVT::f32 &&
5770 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5771
5772 // Put the exponent in the right bit position for later addition to the
5773 // final result:
5774 //
5775 // t0 = Op * log2(e)
5776
5777 // TODO: What fast-math-flags should be set here?
5778 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: Op,
5779 N2: DAG.getConstantFP(Val: numbers::log2ef, DL: dl, VT: MVT::f32));
5780 return getLimitedPrecisionExp2(t0, dl, DAG);
5781 }
5782
5783 // No special expansion.
5784 return DAG.getNode(Opcode: ISD::FEXP, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
5785}
5786
5787/// expandLog - Lower a log intrinsic. Handles the special sequences for
5788/// limited-precision mode.
5789static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5790 const TargetLowering &TLI, SDNodeFlags Flags) {
5791 // TODO: What fast-math-flags should be set on the floating-point nodes?
5792
5793 if (Op.getValueType() == MVT::f32 &&
5794 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5795 SDValue Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Op);
5796
5797 // Scale the exponent by log(2).
5798 SDValue Exp = GetExponent(DAG, Op: Op1, TLI, dl);
5799 SDValue LogOfExponent =
5800 DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: Exp,
5801 N2: DAG.getConstantFP(Val: numbers::ln2f, DL: dl, VT: MVT::f32));
5802
5803 // Get the significand and build it into a floating-point number with
5804 // exponent of 1.
5805 SDValue X = GetSignificand(DAG, Op: Op1, dl);
5806
5807 SDValue LogOfMantissa;
5808 if (LimitFloatPrecision <= 6) {
5809 // For floating-point precision of 6:
5810 //
5811 // LogofMantissa =
5812 // -1.1609546f +
5813 // (1.4034025f - 0.23903021f * x) * x;
5814 //
5815 // error 0.0034276066, which is better than 8 bits
5816 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5817 N2: getF32Constant(DAG, Flt: 0xbe74c456, dl));
5818 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5819 N2: getF32Constant(DAG, Flt: 0x3fb3a2b1, dl));
5820 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5821 LogOfMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5822 N2: getF32Constant(DAG, Flt: 0x3f949a29, dl));
5823 } else if (LimitFloatPrecision <= 12) {
5824 // For floating-point precision of 12:
5825 //
5826 // LogOfMantissa =
5827 // -1.7417939f +
5828 // (2.8212026f +
5829 // (-1.4699568f +
5830 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
5831 //
5832 // error 0.000061011436, which is 14 bits
5833 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5834 N2: getF32Constant(DAG, Flt: 0xbd67b6d6, dl));
5835 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5836 N2: getF32Constant(DAG, Flt: 0x3ee4f4b8, dl));
5837 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5838 SDValue t3 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5839 N2: getF32Constant(DAG, Flt: 0x3fbc278b, dl));
5840 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5841 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5842 N2: getF32Constant(DAG, Flt: 0x40348e95, dl));
5843 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5844 LogOfMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t6,
5845 N2: getF32Constant(DAG, Flt: 0x3fdef31a, dl));
5846 } else { // LimitFloatPrecision <= 18
5847 // For floating-point precision of 18:
5848 //
5849 // LogOfMantissa =
5850 // -2.1072184f +
5851 // (4.2372794f +
5852 // (-3.7029485f +
5853 // (2.2781945f +
5854 // (-0.87823314f +
5855 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
5856 //
5857 // error 0.0000023660568, which is better than 18 bits
5858 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5859 N2: getF32Constant(DAG, Flt: 0xbc91e5ac, dl));
5860 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5861 N2: getF32Constant(DAG, Flt: 0x3e4350aa, dl));
5862 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5863 SDValue t3 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5864 N2: getF32Constant(DAG, Flt: 0x3f60d3e3, dl));
5865 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5866 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5867 N2: getF32Constant(DAG, Flt: 0x4011cdf0, dl));
5868 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5869 SDValue t7 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t6,
5870 N2: getF32Constant(DAG, Flt: 0x406cfd1c, dl));
5871 SDValue t8 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t7, N2: X);
5872 SDValue t9 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t8,
5873 N2: getF32Constant(DAG, Flt: 0x408797cb, dl));
5874 SDValue t10 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t9, N2: X);
5875 LogOfMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t10,
5876 N2: getF32Constant(DAG, Flt: 0x4006dcab, dl));
5877 }
5878
5879 return DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: LogOfExponent, N2: LogOfMantissa);
5880 }
5881
5882 // No special expansion.
5883 return DAG.getNode(Opcode: ISD::FLOG, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
5884}
5885
5886/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
5887/// limited-precision mode.
5888static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5889 const TargetLowering &TLI, SDNodeFlags Flags) {
5890 // TODO: What fast-math-flags should be set on the floating-point nodes?
5891
5892 if (Op.getValueType() == MVT::f32 &&
5893 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5894 SDValue Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Op);
5895
5896 // Get the exponent.
5897 SDValue LogOfExponent = GetExponent(DAG, Op: Op1, TLI, dl);
5898
5899 // Get the significand and build it into a floating-point number with
5900 // exponent of 1.
5901 SDValue X = GetSignificand(DAG, Op: Op1, dl);
5902
5903 // Different possible minimax approximations of significand in
5904 // floating-point for various degrees of accuracy over [1,2].
5905 SDValue Log2ofMantissa;
5906 if (LimitFloatPrecision <= 6) {
5907 // For floating-point precision of 6:
5908 //
5909 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
5910 //
5911 // error 0.0049451742, which is more than 7 bits
5912 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5913 N2: getF32Constant(DAG, Flt: 0xbeb08fe0, dl));
5914 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5915 N2: getF32Constant(DAG, Flt: 0x40019463, dl));
5916 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5917 Log2ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5918 N2: getF32Constant(DAG, Flt: 0x3fd6633d, dl));
5919 } else if (LimitFloatPrecision <= 12) {
5920 // For floating-point precision of 12:
5921 //
5922 // Log2ofMantissa =
5923 // -2.51285454f +
5924 // (4.07009056f +
5925 // (-2.12067489f +
5926 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
5927 //
5928 // error 0.0000876136000, which is better than 13 bits
5929 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5930 N2: getF32Constant(DAG, Flt: 0xbda7262e, dl));
5931 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5932 N2: getF32Constant(DAG, Flt: 0x3f25280b, dl));
5933 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5934 SDValue t3 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5935 N2: getF32Constant(DAG, Flt: 0x4007b923, dl));
5936 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5937 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5938 N2: getF32Constant(DAG, Flt: 0x40823e2f, dl));
5939 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5940 Log2ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t6,
5941 N2: getF32Constant(DAG, Flt: 0x4020d29c, dl));
5942 } else { // LimitFloatPrecision <= 18
5943 // For floating-point precision of 18:
5944 //
5945 // Log2ofMantissa =
5946 // -3.0400495f +
5947 // (6.1129976f +
5948 // (-5.3420409f +
5949 // (3.2865683f +
5950 // (-1.2669343f +
5951 // (0.27515199f -
5952 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
5953 //
5954 // error 0.0000018516, which is better than 18 bits
5955 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5956 N2: getF32Constant(DAG, Flt: 0xbcd2769e, dl));
5957 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5958 N2: getF32Constant(DAG, Flt: 0x3e8ce0b9, dl));
5959 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5960 SDValue t3 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5961 N2: getF32Constant(DAG, Flt: 0x3fa22ae7, dl));
5962 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5963 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5964 N2: getF32Constant(DAG, Flt: 0x40525723, dl));
5965 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5966 SDValue t7 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t6,
5967 N2: getF32Constant(DAG, Flt: 0x40aaf200, dl));
5968 SDValue t8 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t7, N2: X);
5969 SDValue t9 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t8,
5970 N2: getF32Constant(DAG, Flt: 0x40c39dad, dl));
5971 SDValue t10 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t9, N2: X);
5972 Log2ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t10,
5973 N2: getF32Constant(DAG, Flt: 0x4042902c, dl));
5974 }
5975
5976 return DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: LogOfExponent, N2: Log2ofMantissa);
5977 }
5978
5979 // No special expansion.
5980 return DAG.getNode(Opcode: ISD::FLOG2, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
5981}
5982
5983/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
5984/// limited-precision mode.
5985static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5986 const TargetLowering &TLI, SDNodeFlags Flags) {
5987 // TODO: What fast-math-flags should be set on the floating-point nodes?
5988
5989 if (Op.getValueType() == MVT::f32 &&
5990 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5991 SDValue Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Op);
5992
5993 // Scale the exponent by log10(2) [0.30102999f].
5994 SDValue Exp = GetExponent(DAG, Op: Op1, TLI, dl);
5995 SDValue LogOfExponent = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: Exp,
5996 N2: getF32Constant(DAG, Flt: 0x3e9a209a, dl));
5997
5998 // Get the significand and build it into a floating-point number with
5999 // exponent of 1.
6000 SDValue X = GetSignificand(DAG, Op: Op1, dl);
6001
6002 SDValue Log10ofMantissa;
6003 if (LimitFloatPrecision <= 6) {
6004 // For floating-point precision of 6:
6005 //
6006 // Log10ofMantissa =
6007 // -0.50419619f +
6008 // (0.60948995f - 0.10380950f * x) * x;
6009 //
6010 // error 0.0014886165, which is 6 bits
6011 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
6012 N2: getF32Constant(DAG, Flt: 0xbdd49a13, dl));
6013 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
6014 N2: getF32Constant(DAG, Flt: 0x3f1c0789, dl));
6015 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
6016 Log10ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
6017 N2: getF32Constant(DAG, Flt: 0x3f011300, dl));
6018 } else if (LimitFloatPrecision <= 12) {
6019 // For floating-point precision of 12:
6020 //
6021 // Log10ofMantissa =
6022 // -0.64831180f +
6023 // (0.91751397f +
6024 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
6025 //
6026 // error 0.00019228036, which is better than 12 bits
6027 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
6028 N2: getF32Constant(DAG, Flt: 0x3d431f31, dl));
6029 SDValue t1 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t0,
6030 N2: getF32Constant(DAG, Flt: 0x3ea21fb2, dl));
6031 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
6032 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
6033 N2: getF32Constant(DAG, Flt: 0x3f6ae232, dl));
6034 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
6035 Log10ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t4,
6036 N2: getF32Constant(DAG, Flt: 0x3f25f7c3, dl));
6037 } else { // LimitFloatPrecision <= 18
6038 // For floating-point precision of 18:
6039 //
6040 // Log10ofMantissa =
6041 // -0.84299375f +
6042 // (1.5327582f +
6043 // (-1.0688956f +
6044 // (0.49102474f +
6045 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
6046 //
6047 // error 0.0000037995730, which is better than 18 bits
6048 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
6049 N2: getF32Constant(DAG, Flt: 0x3c5d51ce, dl));
6050 SDValue t1 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t0,
6051 N2: getF32Constant(DAG, Flt: 0x3e00685a, dl));
6052 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
6053 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
6054 N2: getF32Constant(DAG, Flt: 0x3efb6798, dl));
6055 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
6056 SDValue t5 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t4,
6057 N2: getF32Constant(DAG, Flt: 0x3f88d192, dl));
6058 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
6059 SDValue t7 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t6,
6060 N2: getF32Constant(DAG, Flt: 0x3fc4316c, dl));
6061 SDValue t8 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t7, N2: X);
6062 Log10ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t8,
6063 N2: getF32Constant(DAG, Flt: 0x3f57ce70, dl));
6064 }
6065
6066 return DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: LogOfExponent, N2: Log10ofMantissa);
6067 }
6068
6069 // No special expansion.
6070 return DAG.getNode(Opcode: ISD::FLOG10, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
6071}
6072
6073/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
6074/// limited-precision mode.
6075static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
6076 const TargetLowering &TLI, SDNodeFlags Flags) {
6077 if (Op.getValueType() == MVT::f32 &&
6078 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
6079 return getLimitedPrecisionExp2(t0: Op, dl, DAG);
6080
6081 // No special expansion.
6082 return DAG.getNode(Opcode: ISD::FEXP2, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
6083}
6084
6085/// visitPow - Lower a pow intrinsic. Handles the special sequences for
6086/// limited-precision mode with x == 10.0f.
6087static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS,
6088 SelectionDAG &DAG, const TargetLowering &TLI,
6089 SDNodeFlags Flags) {
6090 bool IsExp10 = false;
6091 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
6092 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
6093 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(Val&: LHS)) {
6094 APFloat Ten(10.0f);
6095 IsExp10 = LHSC->isExactlyValue(V: Ten);
6096 }
6097 }
6098
6099 // TODO: What fast-math-flags should be set on the FMUL node?
6100 if (IsExp10) {
6101 // Put the exponent in the right bit position for later addition to the
6102 // final result:
6103 //
6104 // #define LOG2OF10 3.3219281f
6105 // t0 = Op * LOG2OF10;
6106 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: RHS,
6107 N2: getF32Constant(DAG, Flt: 0x40549a78, dl));
6108 return getLimitedPrecisionExp2(t0, dl, DAG);
6109 }
6110
6111 // No special expansion.
6112 return DAG.getNode(Opcode: ISD::FPOW, DL: dl, VT: LHS.getValueType(), N1: LHS, N2: RHS, Flags);
6113}
6114
6115/// ExpandPowI - Expand a llvm.powi intrinsic.
6116static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
6117 SelectionDAG &DAG) {
6118 // If RHS is a constant, we can expand this out to a multiplication tree if
6119 // it's beneficial on the target, otherwise we end up lowering to a call to
6120 // __powidf2 (for example).
6121 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Val&: RHS)) {
6122 unsigned Val = RHSC->getSExtValue();
6123
6124 // powi(x, 0) -> 1.0
6125 if (Val == 0)
6126 return DAG.getConstantFP(Val: 1.0, DL, VT: LHS.getValueType());
6127
6128 if (DAG.getTargetLoweringInfo().isBeneficialToExpandPowI(
6129 Exponent: Val, OptForSize: DAG.shouldOptForSize())) {
6130 // Get the exponent as a positive value.
6131 if ((int)Val < 0)
6132 Val = -Val;
6133 // We use the simple binary decomposition method to generate the multiply
6134 // sequence. There are more optimal ways to do this (for example,
6135 // powi(x,15) generates one more multiply than it should), but this has
6136 // the benefit of being both really simple and much better than a libcall.
6137 SDValue Res; // Logically starts equal to 1.0
6138 SDValue CurSquare = LHS;
6139 // TODO: Intrinsics should have fast-math-flags that propagate to these
6140 // nodes.
6141 while (Val) {
6142 if (Val & 1) {
6143 if (Res.getNode())
6144 Res =
6145 DAG.getNode(Opcode: ISD::FMUL, DL, VT: Res.getValueType(), N1: Res, N2: CurSquare);
6146 else
6147 Res = CurSquare; // 1.0*CurSquare.
6148 }
6149
6150 CurSquare = DAG.getNode(Opcode: ISD::FMUL, DL, VT: CurSquare.getValueType(),
6151 N1: CurSquare, N2: CurSquare);
6152 Val >>= 1;
6153 }
6154
6155 // If the original was negative, invert the result, producing 1/(x*x*x).
6156 if (RHSC->getSExtValue() < 0)
6157 Res = DAG.getNode(Opcode: ISD::FDIV, DL, VT: LHS.getValueType(),
6158 N1: DAG.getConstantFP(Val: 1.0, DL, VT: LHS.getValueType()), N2: Res);
6159 return Res;
6160 }
6161 }
6162
6163 // Otherwise, expand to a libcall.
6164 return DAG.getNode(Opcode: ISD::FPOWI, DL, VT: LHS.getValueType(), N1: LHS, N2: RHS);
6165}
6166
6167static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL,
6168 SDValue LHS, SDValue RHS, SDValue Scale,
6169 SelectionDAG &DAG, const TargetLowering &TLI) {
6170 EVT VT = LHS.getValueType();
6171 bool Signed = Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT;
6172 bool Saturating = Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIXSAT;
6173 LLVMContext &Ctx = *DAG.getContext();
6174
6175 // If the type is legal but the operation isn't, this node might survive all
6176 // the way to operation legalization. If we end up there and we do not have
6177 // the ability to widen the type (if VT*2 is not legal), we cannot expand the
6178 // node.
6179
6180 // Coax the legalizer into expanding the node during type legalization instead
6181 // by bumping the size by one bit. This will force it to Promote, enabling the
6182 // early expansion and avoiding the need to expand later.
6183
6184 // We don't have to do this if Scale is 0; that can always be expanded, unless
6185 // it's a saturating signed operation. Those can experience true integer
6186 // division overflow, a case which we must avoid.
6187
6188 // FIXME: We wouldn't have to do this (or any of the early
6189 // expansion/promotion) if it was possible to expand a libcall of an
6190 // illegal type during operation legalization. But it's not, so things
6191 // get a bit hacky.
6192 unsigned ScaleInt = Scale->getAsZExtVal();
6193 if ((ScaleInt > 0 || (Saturating && Signed)) &&
6194 (TLI.isTypeLegal(VT) ||
6195 (VT.isVector() && TLI.isTypeLegal(VT: VT.getVectorElementType())))) {
6196 TargetLowering::LegalizeAction Action = TLI.getFixedPointOperationAction(
6197 Op: Opcode, VT, Scale: ScaleInt);
6198 if (Action != TargetLowering::Legal && Action != TargetLowering::Custom) {
6199 EVT PromVT;
6200 if (VT.isScalarInteger())
6201 PromVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: VT.getSizeInBits() + 1);
6202 else if (VT.isVector()) {
6203 PromVT = VT.getVectorElementType();
6204 PromVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: PromVT.getSizeInBits() + 1);
6205 PromVT = EVT::getVectorVT(Context&: Ctx, VT: PromVT, EC: VT.getVectorElementCount());
6206 } else
6207 llvm_unreachable("Wrong VT for DIVFIX?");
6208 LHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: LHS, DL, VT: PromVT);
6209 RHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: RHS, DL, VT: PromVT);
6210 EVT ShiftTy = TLI.getShiftAmountTy(LHSTy: PromVT, DL: DAG.getDataLayout());
6211 // For saturating operations, we need to shift up the LHS to get the
6212 // proper saturation width, and then shift down again afterwards.
6213 if (Saturating)
6214 LHS = DAG.getNode(Opcode: ISD::SHL, DL, VT: PromVT, N1: LHS,
6215 N2: DAG.getConstant(Val: 1, DL, VT: ShiftTy));
6216 SDValue Res = DAG.getNode(Opcode, DL, VT: PromVT, N1: LHS, N2: RHS, N3: Scale);
6217 if (Saturating)
6218 Res = DAG.getNode(Opcode: Signed ? ISD::SRA : ISD::SRL, DL, VT: PromVT, N1: Res,
6219 N2: DAG.getConstant(Val: 1, DL, VT: ShiftTy));
6220 return DAG.getZExtOrTrunc(Op: Res, DL, VT);
6221 }
6222 }
6223
6224 return DAG.getNode(Opcode, DL, VT, N1: LHS, N2: RHS, N3: Scale);
6225}
6226
6227// getUnderlyingArgRegs - Find underlying registers used for a truncated,
6228// bitcasted, or split argument. Returns a list of <Register, size in bits>
6229static void
6230getUnderlyingArgRegs(SmallVectorImpl<std::pair<Register, TypeSize>> &Regs,
6231 const SDValue &N) {
6232 switch (N.getOpcode()) {
6233 case ISD::CopyFromReg: {
6234 SDValue Op = N.getOperand(i: 1);
6235 Regs.emplace_back(Args: cast<RegisterSDNode>(Val&: Op)->getReg(),
6236 Args: Op.getValueType().getSizeInBits());
6237 return;
6238 }
6239 case ISD::BITCAST:
6240 case ISD::AssertZext:
6241 case ISD::AssertSext:
6242 case ISD::TRUNCATE:
6243 getUnderlyingArgRegs(Regs, N: N.getOperand(i: 0));
6244 return;
6245 case ISD::BUILD_PAIR:
6246 case ISD::BUILD_VECTOR:
6247 case ISD::CONCAT_VECTORS:
6248 for (SDValue Op : N->op_values())
6249 getUnderlyingArgRegs(Regs, N: Op);
6250 return;
6251 default:
6252 return;
6253 }
6254}
6255
6256/// If the DbgValueInst is a dbg_value of a function argument, create the
6257/// corresponding DBG_VALUE machine instruction for it now. At the end of
6258/// instruction selection, they will be inserted to the entry BB.
6259/// We don't currently support this for variadic dbg_values, as they shouldn't
6260/// appear for function arguments or in the prologue.
6261bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
6262 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
6263 DILocation *DL, FuncArgumentDbgValueKind Kind, const SDValue &N) {
6264 const Argument *Arg = dyn_cast<Argument>(Val: V);
6265 if (!Arg)
6266 return false;
6267
6268 MachineFunction &MF = DAG.getMachineFunction();
6269 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
6270
6271 // Helper to create DBG_INSTR_REFs or DBG_VALUEs, depending on what kind
6272 // we've been asked to pursue.
6273 auto MakeVRegDbgValue = [&](Register Reg, DIExpression *FragExpr,
6274 bool Indirect) {
6275 if (Reg.isVirtual() && MF.useDebugInstrRef()) {
6276 // For VRegs, in instruction referencing mode, create a DBG_INSTR_REF
6277 // pointing at the VReg, which will be patched up later.
6278 auto &Inst = TII->get(Opcode: TargetOpcode::DBG_INSTR_REF);
6279 SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg(
6280 /* Reg */ Reg, /* isDef */ false, /* isImp */ false,
6281 /* isKill */ false, /* isDead */ false,
6282 /* isUndef */ false, /* isEarlyClobber */ false,
6283 /* SubReg */ 0, /* isDebug */ true)});
6284
6285 auto *NewDIExpr = FragExpr;
6286 // We don't have an "Indirect" field in DBG_INSTR_REF, fold that into
6287 // the DIExpression.
6288 if (Indirect)
6289 NewDIExpr = DIExpression::prepend(Expr: FragExpr, Flags: DIExpression::DerefBefore);
6290 SmallVector<uint64_t, 2> Ops({dwarf::DW_OP_LLVM_arg, 0});
6291 NewDIExpr = DIExpression::prependOpcodes(Expr: NewDIExpr, Ops);
6292 return BuildMI(MF, DL, MCID: Inst, IsIndirect: false, MOs, Variable, Expr: NewDIExpr);
6293 } else {
6294 // Create a completely standard DBG_VALUE.
6295 auto &Inst = TII->get(Opcode: TargetOpcode::DBG_VALUE);
6296 return BuildMI(MF, DL, MCID: Inst, IsIndirect: Indirect, Reg, Variable, Expr: FragExpr);
6297 }
6298 };
6299
6300 if (Kind == FuncArgumentDbgValueKind::Value) {
6301 // ArgDbgValues are hoisted to the beginning of the entry block. So we
6302 // should only emit as ArgDbgValue if the dbg.value intrinsic is found in
6303 // the entry block.
6304 bool IsInEntryBlock = FuncInfo.MBB == &FuncInfo.MF->front();
6305 if (!IsInEntryBlock)
6306 return false;
6307
6308 // ArgDbgValues are hoisted to the beginning of the entry block. So we
6309 // should only emit as ArgDbgValue if the dbg.value intrinsic describes a
6310 // variable that also is a param.
6311 //
6312 // Although, if we are at the top of the entry block already, we can still
6313 // emit using ArgDbgValue. This might catch some situations when the
6314 // dbg.value refers to an argument that isn't used in the entry block, so
6315 // any CopyToReg node would be optimized out and the only way to express
6316 // this DBG_VALUE is by using the physical reg (or FI) as done in this
6317 // method. ArgDbgValues are hoisted to the beginning of the entry block. So
6318 // we should only emit as ArgDbgValue if the Variable is an argument to the
6319 // current function, and the dbg.value intrinsic is found in the entry
6320 // block.
6321 bool VariableIsFunctionInputArg = Variable->isParameter() &&
6322 !DL->getInlinedAt();
6323 bool IsInPrologue = SDNodeOrder == LowestSDNodeOrder;
6324 if (!IsInPrologue && !VariableIsFunctionInputArg)
6325 return false;
6326
6327 // Here we assume that a function argument on IR level only can be used to
6328 // describe one input parameter on source level. If we for example have
6329 // source code like this
6330 //
6331 // struct A { long x, y; };
6332 // void foo(struct A a, long b) {
6333 // ...
6334 // b = a.x;
6335 // ...
6336 // }
6337 //
6338 // and IR like this
6339 //
6340 // define void @foo(i32 %a1, i32 %a2, i32 %b) {
6341 // entry:
6342 // call void @llvm.dbg.value(metadata i32 %a1, "a", DW_OP_LLVM_fragment
6343 // call void @llvm.dbg.value(metadata i32 %a2, "a", DW_OP_LLVM_fragment
6344 // call void @llvm.dbg.value(metadata i32 %b, "b",
6345 // ...
6346 // call void @llvm.dbg.value(metadata i32 %a1, "b"
6347 // ...
6348 //
6349 // then the last dbg.value is describing a parameter "b" using a value that
6350 // is an argument. But since we already has used %a1 to describe a parameter
6351 // we should not handle that last dbg.value here (that would result in an
6352 // incorrect hoisting of the DBG_VALUE to the function entry).
6353 // Notice that we allow one dbg.value per IR level argument, to accommodate
6354 // for the situation with fragments above.
6355 // If there is no node for the value being handled, we return true to skip
6356 // the normal generation of debug info, as it would kill existing debug
6357 // info for the parameter in case of duplicates.
6358 if (VariableIsFunctionInputArg) {
6359 unsigned ArgNo = Arg->getArgNo();
6360 if (ArgNo >= FuncInfo.DescribedArgs.size())
6361 FuncInfo.DescribedArgs.resize(N: ArgNo + 1, t: false);
6362 else if (!IsInPrologue && FuncInfo.DescribedArgs.test(Idx: ArgNo))
6363 return !NodeMap[V].getNode();
6364 FuncInfo.DescribedArgs.set(ArgNo);
6365 }
6366 }
6367
6368 bool IsIndirect = false;
6369 std::optional<MachineOperand> Op;
6370 // Some arguments' frame index is recorded during argument lowering.
6371 int FI = FuncInfo.getArgumentFrameIndex(A: Arg);
6372 if (FI != std::numeric_limits<int>::max())
6373 Op = MachineOperand::CreateFI(Idx: FI);
6374
6375 SmallVector<std::pair<Register, TypeSize>, 8> ArgRegsAndSizes;
6376 if (!Op && N.getNode()) {
6377 getUnderlyingArgRegs(Regs&: ArgRegsAndSizes, N);
6378 Register Reg;
6379 if (ArgRegsAndSizes.size() == 1)
6380 Reg = ArgRegsAndSizes.front().first;
6381
6382 if (Reg && Reg.isVirtual()) {
6383 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6384 Register PR = RegInfo.getLiveInPhysReg(VReg: Reg);
6385 if (PR)
6386 Reg = PR;
6387 }
6388 if (Reg) {
6389 Op = MachineOperand::CreateReg(Reg, isDef: false);
6390 IsIndirect = Kind != FuncArgumentDbgValueKind::Value;
6391 }
6392 }
6393
6394 if (!Op && N.getNode()) {
6395 // Check if frame index is available.
6396 SDValue LCandidate = peekThroughBitcasts(V: N);
6397 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(Val: LCandidate.getNode()))
6398 if (FrameIndexSDNode *FINode =
6399 dyn_cast<FrameIndexSDNode>(Val: LNode->getBasePtr().getNode()))
6400 Op = MachineOperand::CreateFI(Idx: FINode->getIndex());
6401 }
6402
6403 if (!Op) {
6404 // Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg
6405 auto splitMultiRegDbgValue =
6406 [&](ArrayRef<std::pair<Register, TypeSize>> SplitRegs) -> bool {
6407 unsigned Offset = 0;
6408 for (const auto &[Reg, RegSizeInBits] : SplitRegs) {
6409 // FIXME: Scalable sizes are not supported in fragment expressions.
6410 if (RegSizeInBits.isScalable())
6411 return false;
6412
6413 // If the expression is already a fragment, the current register
6414 // offset+size might extend beyond the fragment. In this case, only
6415 // the register bits that are inside the fragment are relevant.
6416 int RegFragmentSizeInBits = RegSizeInBits.getFixedValue();
6417 if (auto ExprFragmentInfo = Expr->getFragmentInfo()) {
6418 uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits;
6419 // The register is entirely outside the expression fragment,
6420 // so is irrelevant for debug info.
6421 if (Offset >= ExprFragmentSizeInBits)
6422 break;
6423 // The register is partially outside the expression fragment, only
6424 // the low bits within the fragment are relevant for debug info.
6425 if (Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) {
6426 RegFragmentSizeInBits = ExprFragmentSizeInBits - Offset;
6427 }
6428 }
6429
6430 auto FragmentExpr = DIExpression::createFragmentExpression(
6431 Expr, OffsetInBits: Offset, SizeInBits: RegFragmentSizeInBits);
6432 Offset += RegSizeInBits.getFixedValue();
6433 // If a valid fragment expression cannot be created, the variable's
6434 // correct value cannot be determined and so it is set as poison.
6435 if (!FragmentExpr) {
6436 SDDbgValue *SDV = DAG.getConstantDbgValue(
6437 Var: Variable, Expr, C: PoisonValue::get(T: V->getType()), DL, O: SDNodeOrder);
6438 DAG.AddDbgValue(DB: SDV, isParameter: false);
6439 continue;
6440 }
6441 MachineInstr *NewMI = MakeVRegDbgValue(
6442 Reg, *FragmentExpr, Kind != FuncArgumentDbgValueKind::Value);
6443 FuncInfo.ArgDbgValues.push_back(Elt: NewMI);
6444 }
6445
6446 return true;
6447 };
6448
6449 // Check if ValueMap has reg number.
6450 DenseMap<const Value *, Register>::const_iterator
6451 VMI = FuncInfo.ValueMap.find(Val: V);
6452 if (VMI != FuncInfo.ValueMap.end()) {
6453 const auto &TLI = DAG.getTargetLoweringInfo();
6454 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second,
6455 V->getType(), std::nullopt);
6456 if (RFV.occupiesMultipleRegs())
6457 return splitMultiRegDbgValue(RFV.getRegsAndSizes());
6458
6459 Op = MachineOperand::CreateReg(Reg: VMI->second, isDef: false);
6460 IsIndirect = Kind != FuncArgumentDbgValueKind::Value;
6461 } else if (ArgRegsAndSizes.size() > 1) {
6462 // This was split due to the calling convention, and no virtual register
6463 // mapping exists for the value.
6464 return splitMultiRegDbgValue(ArgRegsAndSizes);
6465 }
6466 }
6467
6468 if (!Op)
6469 return false;
6470
6471 assert(Variable->isValidLocationForIntrinsic(DL) &&
6472 "Expected inlined-at fields to agree");
6473 MachineInstr *NewMI = nullptr;
6474
6475 if (Op->isReg())
6476 NewMI = MakeVRegDbgValue(Op->getReg(), Expr, IsIndirect);
6477 else
6478 NewMI = BuildMI(MF, DL, MCID: TII->get(Opcode: TargetOpcode::DBG_VALUE), IsIndirect: true, MOs: *Op,
6479 Variable, Expr);
6480
6481 // Otherwise, use ArgDbgValues.
6482 FuncInfo.ArgDbgValues.push_back(Elt: NewMI);
6483 return true;
6484}
6485
6486/// Return the appropriate SDDbgValue based on N.
6487SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N,
6488 DILocalVariable *Variable,
6489 DIExpression *Expr,
6490 const DebugLoc &dl,
6491 unsigned DbgSDNodeOrder) {
6492 if (auto *FISDN = dyn_cast<FrameIndexSDNode>(Val: N.getNode())) {
6493 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe
6494 // stack slot locations.
6495 //
6496 // Consider "int x = 0; int *px = &x;". There are two kinds of interesting
6497 // debug values here after optimization:
6498 //
6499 // dbg.value(i32* %px, !"int *px", !DIExpression()), and
6500 // dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref))
6501 //
6502 // Both describe the direct values of their associated variables.
6503 return DAG.getFrameIndexDbgValue(Var: Variable, Expr, FI: FISDN->getIndex(),
6504 /*IsIndirect*/ false, DL: dl, O: DbgSDNodeOrder);
6505 }
6506 return DAG.getDbgValue(Var: Variable, Expr, N: N.getNode(), R: N.getResNo(),
6507 /*IsIndirect*/ false, DL: dl, O: DbgSDNodeOrder);
6508}
6509
6510static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic) {
6511 switch (Intrinsic) {
6512 case Intrinsic::smul_fix:
6513 return ISD::SMULFIX;
6514 case Intrinsic::umul_fix:
6515 return ISD::UMULFIX;
6516 case Intrinsic::smul_fix_sat:
6517 return ISD::SMULFIXSAT;
6518 case Intrinsic::umul_fix_sat:
6519 return ISD::UMULFIXSAT;
6520 case Intrinsic::sdiv_fix:
6521 return ISD::SDIVFIX;
6522 case Intrinsic::udiv_fix:
6523 return ISD::UDIVFIX;
6524 case Intrinsic::sdiv_fix_sat:
6525 return ISD::SDIVFIXSAT;
6526 case Intrinsic::udiv_fix_sat:
6527 return ISD::UDIVFIXSAT;
6528 default:
6529 llvm_unreachable("Unhandled fixed point intrinsic");
6530 }
6531}
6532
6533/// Given a @llvm.call.preallocated.setup, return the corresponding
6534/// preallocated call.
6535static const CallBase *FindPreallocatedCall(const Value *PreallocatedSetup) {
6536 assert(cast<CallBase>(PreallocatedSetup)
6537 ->getCalledFunction()
6538 ->getIntrinsicID() == Intrinsic::call_preallocated_setup &&
6539 "expected call_preallocated_setup Value");
6540 for (const auto *U : PreallocatedSetup->users()) {
6541 auto *UseCall = cast<CallBase>(Val: U);
6542 const Function *Fn = UseCall->getCalledFunction();
6543 if (!Fn || Fn->getIntrinsicID() != Intrinsic::call_preallocated_arg) {
6544 return UseCall;
6545 }
6546 }
6547 llvm_unreachable("expected corresponding call to preallocated setup/arg");
6548}
6549
6550/// If DI is a debug value with an EntryValue expression, lower it using the
6551/// corresponding physical register of the associated Argument value
6552/// (guaranteed to exist by the verifier).
6553bool SelectionDAGBuilder::visitEntryValueDbgValue(
6554 ArrayRef<const Value *> Values, DILocalVariable *Variable,
6555 DIExpression *Expr, DebugLoc DbgLoc) {
6556 if (!Expr->isEntryValue() || !hasSingleElement(C&: Values))
6557 return false;
6558
6559 // These properties are guaranteed by the verifier.
6560 const Argument *Arg = cast<Argument>(Val: Values[0]);
6561 assert(Arg->hasAttribute(Attribute::AttrKind::SwiftAsync));
6562
6563 auto ArgIt = FuncInfo.ValueMap.find(Val: Arg);
6564 if (ArgIt == FuncInfo.ValueMap.end()) {
6565 LLVM_DEBUG(
6566 dbgs() << "Dropping dbg.value: expression is entry_value but "
6567 "couldn't find an associated register for the Argument\n");
6568 return true;
6569 }
6570 Register ArgVReg = ArgIt->getSecond();
6571
6572 for (auto [PhysReg, VirtReg] : FuncInfo.RegInfo->liveins())
6573 if (ArgVReg == VirtReg || ArgVReg == PhysReg) {
6574 SDDbgValue *SDV = DAG.getVRegDbgValue(
6575 Var: Variable, Expr, VReg: PhysReg, IsIndirect: false /*IsIndidrect*/, DL: DbgLoc, O: SDNodeOrder);
6576 DAG.AddDbgValue(DB: SDV, isParameter: false /*treat as dbg.declare byval parameter*/);
6577 return true;
6578 }
6579 LLVM_DEBUG(dbgs() << "Dropping dbg.value: expression is entry_value but "
6580 "couldn't find a physical register\n");
6581 return true;
6582}
6583
6584/// Lower the call to the specified intrinsic function.
6585void SelectionDAGBuilder::visitConvergenceControl(const CallInst &I,
6586 unsigned Intrinsic) {
6587 SDLoc sdl = getCurSDLoc();
6588 switch (Intrinsic) {
6589 case Intrinsic::experimental_convergence_anchor:
6590 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONVERGENCECTRL_ANCHOR, DL: sdl, VT: MVT::Untyped));
6591 break;
6592 case Intrinsic::experimental_convergence_entry:
6593 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONVERGENCECTRL_ENTRY, DL: sdl, VT: MVT::Untyped));
6594 break;
6595 case Intrinsic::experimental_convergence_loop: {
6596 auto Bundle = I.getOperandBundle(ID: LLVMContext::OB_convergencectrl);
6597 auto *Token = Bundle->Inputs[0].get();
6598 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONVERGENCECTRL_LOOP, DL: sdl, VT: MVT::Untyped,
6599 Operand: getValue(V: Token)));
6600 break;
6601 }
6602 }
6603}
6604
6605void SelectionDAGBuilder::visitVectorHistogram(const CallInst &I,
6606 unsigned IntrinsicID) {
6607 // For now, we're only lowering an 'add' histogram.
6608 // We can add others later, e.g. saturating adds, min/max.
6609 assert(IntrinsicID == Intrinsic::experimental_vector_histogram_add &&
6610 "Tried to lower unsupported histogram type");
6611 SDLoc sdl = getCurSDLoc();
6612 Value *Ptr = I.getOperand(i_nocapture: 0);
6613 SDValue Inc = getValue(V: I.getOperand(i_nocapture: 1));
6614 SDValue Mask = getValue(V: I.getOperand(i_nocapture: 2));
6615
6616 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6617 DataLayout TargetDL = DAG.getDataLayout();
6618 EVT VT = Inc.getValueType();
6619 Align Alignment = DAG.getEVTAlign(MemoryVT: VT);
6620
6621 const MDNode *Ranges = getRangeMetadata(I);
6622
6623 SDValue Root = DAG.getRoot();
6624 SDValue Base;
6625 SDValue Index;
6626 SDValue Scale;
6627 bool UniformBase = getUniformBase(Ptr, Base, Index, Scale, SDB: this,
6628 CurBB: I.getParent(), ElemSize: VT.getScalarStoreSize());
6629
6630 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
6631
6632 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
6633 PtrInfo: MachinePointerInfo(AS),
6634 F: MachineMemOperand::MOLoad | MachineMemOperand::MOStore,
6635 Size: MemoryLocation::UnknownSize, BaseAlignment: Alignment,
6636 Metadata: MMOMetadata(I.getAAMetadata(), Ranges));
6637
6638 if (!UniformBase) {
6639 Base = DAG.getConstant(Val: 0, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
6640 Index = getValue(V: Ptr);
6641 Scale =
6642 DAG.getTargetConstant(Val: 1, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
6643 }
6644
6645 EVT IdxVT = Index.getValueType();
6646
6647 // Avoid using e.g. i32 as index type when the increment must be performed
6648 // on i64's.
6649 bool MustExtendIndex = VT.getScalarSizeInBits() > IdxVT.getScalarSizeInBits();
6650 EVT EltTy = MustExtendIndex ? VT : IdxVT.getVectorElementType();
6651 if (MustExtendIndex || TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
6652 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
6653 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: sdl, VT: NewIdxVT, Operand: Index);
6654 }
6655
6656 SDValue ID = DAG.getTargetConstant(Val: IntrinsicID, DL: sdl, VT: MVT::i32);
6657
6658 SDValue Ops[] = {Root, Inc, Mask, Base, Index, Scale, ID};
6659 SDValue Histogram = DAG.getMaskedHistogram(VTs: DAG.getVTList(VT: MVT::Other), MemVT: VT, dl: sdl,
6660 Ops, MMO, IndexType: ISD::SIGNED_SCALED);
6661
6662 setValue(V: &I, NewN: Histogram);
6663 DAG.setRoot(Histogram);
6664}
6665
6666void SelectionDAGBuilder::visitVectorExtractLastActive(const CallInst &I,
6667 unsigned Intrinsic) {
6668 assert(Intrinsic == Intrinsic::experimental_vector_extract_last_active &&
6669 "Tried lowering invalid vector extract last");
6670 SDLoc sdl = getCurSDLoc();
6671 const DataLayout &Layout = DAG.getDataLayout();
6672 SDValue Data = getValue(V: I.getOperand(i_nocapture: 0));
6673 SDValue Mask = getValue(V: I.getOperand(i_nocapture: 1));
6674
6675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6676 EVT ResVT = TLI.getValueType(DL: Layout, Ty: I.getType());
6677
6678 EVT ExtVT = TLI.getVectorIdxTy(DL: Layout);
6679 SDValue Idx = DAG.getNode(Opcode: ISD::VECTOR_FIND_LAST_ACTIVE, DL: sdl, VT: ExtVT, Operand: Mask);
6680 SDValue Result = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: sdl, VT: ResVT, N1: Data, N2: Idx);
6681
6682 Value *Default = I.getOperand(i_nocapture: 2);
6683 if (!isa<PoisonValue>(Val: Default) && !isa<UndefValue>(Val: Default)) {
6684 SDValue PassThru = getValue(V: Default);
6685 EVT BoolVT = Mask.getValueType().getScalarType();
6686 SDValue AnyActive = DAG.getNode(Opcode: ISD::VECREDUCE_OR, DL: sdl, VT: BoolVT, Operand: Mask);
6687 Result = DAG.getSelect(DL: sdl, VT: ResVT, Cond: AnyActive, LHS: Result, RHS: PassThru);
6688 }
6689
6690 setValue(V: &I, NewN: Result);
6691}
6692
6693/// Lower the call to the specified intrinsic function.
6694void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
6695 unsigned Intrinsic) {
6696 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6697 SDLoc sdl = getCurSDLoc();
6698 DebugLoc dl = getCurDebugLoc();
6699 SDValue Res;
6700
6701 SDNodeFlags Flags;
6702 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
6703 Flags.copyFMF(FPMO: *FPOp);
6704
6705 switch (Intrinsic) {
6706 default:
6707 // By default, turn this into a target intrinsic node.
6708 visitTargetIntrinsic(I, Intrinsic);
6709 return;
6710 case Intrinsic::vscale: {
6711 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
6712 setValue(V: &I, NewN: DAG.getVScale(DL: sdl, VT, MulImm: APInt(VT.getSizeInBits(), 1)));
6713 return;
6714 }
6715 case Intrinsic::vastart: visitVAStart(I); return;
6716 case Intrinsic::vaend: visitVAEnd(I); return;
6717 case Intrinsic::vacopy: visitVACopy(I); return;
6718 case Intrinsic::returnaddress:
6719 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::RETURNADDR, DL: sdl,
6720 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
6721 Operand: getValue(V: I.getArgOperand(i: 0))));
6722 return;
6723 case Intrinsic::addressofreturnaddress:
6724 setValue(V: &I,
6725 NewN: DAG.getNode(Opcode: ISD::ADDROFRETURNADDR, DL: sdl,
6726 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType())));
6727 return;
6728 case Intrinsic::sponentry:
6729 setValue(V: &I,
6730 NewN: DAG.getNode(Opcode: ISD::SPONENTRY, DL: sdl,
6731 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType())));
6732 return;
6733 case Intrinsic::frameaddress:
6734 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FRAMEADDR, DL: sdl,
6735 VT: TLI.getFrameIndexTy(DL: DAG.getDataLayout()),
6736 Operand: getValue(V: I.getArgOperand(i: 0))));
6737 return;
6738 case Intrinsic::read_volatile_register:
6739 case Intrinsic::read_register: {
6740 Value *Reg = I.getArgOperand(i: 0);
6741 SDValue Chain = getRoot();
6742 SDValue RegName =
6743 DAG.getMDNode(MD: cast<MDNode>(Val: cast<MetadataAsValue>(Val: Reg)->getMetadata()));
6744 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
6745 Res = DAG.getNode(Opcode: ISD::READ_REGISTER, DL: sdl,
6746 VTList: DAG.getVTList(VT1: VT, VT2: MVT::Other), N1: Chain, N2: RegName);
6747 setValue(V: &I, NewN: Res);
6748 DAG.setRoot(Res.getValue(R: 1));
6749 return;
6750 }
6751 case Intrinsic::write_register: {
6752 Value *Reg = I.getArgOperand(i: 0);
6753 Value *RegValue = I.getArgOperand(i: 1);
6754 SDValue Chain = getRoot();
6755 SDValue RegName =
6756 DAG.getMDNode(MD: cast<MDNode>(Val: cast<MetadataAsValue>(Val: Reg)->getMetadata()));
6757 DAG.setRoot(DAG.getNode(Opcode: ISD::WRITE_REGISTER, DL: sdl, VT: MVT::Other, N1: Chain,
6758 N2: RegName, N3: getValue(V: RegValue)));
6759 return;
6760 }
6761 case Intrinsic::write_volatile_register: {
6762 Value *Reg = I.getArgOperand(i: 0);
6763 Value *RegValue = I.getArgOperand(i: 1);
6764 SDValue Chain = getRoot();
6765 const MDNode *MD = cast<MDNode>(Val: cast<MetadataAsValue>(Val: Reg)->getMetadata());
6766 SDValue RegName = DAG.getMDNode(MD);
6767 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: RegValue->getType());
6768 SDValue WriteChain = DAG.getNode(Opcode: ISD::WRITE_REGISTER, DL: sdl, VT: MVT::Other,
6769 N1: Chain, N2: RegName, N3: getValue(V: RegValue));
6770 // FAKE_USE of the physical register marks it live after the WRITE_REGISTER,
6771 // preventing the backend from dead-eliminating the write. This is
6772 // preferred over READ_REGISTER, which would emit extra register copies
6773 // (e.g. fmov xN, dN for FP/SIMD registers).
6774 const MDString *RegStr = cast<MDString>(Val: MD->getOperand(I: 0));
6775 LLT Ty = VT.isSimple() ? getLLTForMVT(Ty: VT.getSimpleVT()) : LLT();
6776 const MachineFunction &MF = DAG.getMachineFunction();
6777 Register PhysReg =
6778 TLI.getRegisterByName(RegName: RegStr->getString().data(), Ty, MF);
6779 if (PhysReg.isValid()) {
6780 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
6781 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg: PhysReg);
6782 MVT RegVT = *TRI->legalclasstypes_begin(RC: *RC);
6783 DAG.setRoot(DAG.getNode(Opcode: ISD::FAKE_USE, DL: sdl, VT: MVT::Other,
6784 Ops: {WriteChain, DAG.getRegister(Reg: PhysReg, VT: RegVT)}));
6785 } else {
6786 DAG.setRoot(WriteChain);
6787 }
6788 return;
6789 }
6790 case Intrinsic::memcpy:
6791 case Intrinsic::memcpy_inline: {
6792 const auto &MCI = cast<MemCpyInst>(Val: I);
6793 SDValue Dst = getValue(V: I.getArgOperand(i: 0));
6794 SDValue Src = getValue(V: I.getArgOperand(i: 1));
6795 SDValue Size = getValue(V: I.getArgOperand(i: 2));
6796 assert((!MCI.isForceInlined() || isa<ConstantSDNode>(Size)) &&
6797 "memcpy_inline needs constant size");
6798 // @llvm.memcpy.inline defines 0 and 1 to both mean no alignment.
6799 Align DstAlign = MCI.getDestAlign().valueOrOne();
6800 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6801 bool isVol = MCI.isVolatile();
6802 SDValue Root = isVol ? getRoot() : getMemoryRoot();
6803 SDValue MC = DAG.getMemcpy(Chain: Root, dl: sdl, Dst, Src, Size, DstAlign, SrcAlign,
6804 isVol, AlwaysInline: MCI.isForceInlined(), CI: &I, OverrideTailCall: std::nullopt,
6805 DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
6806 SrcPtrInfo: MachinePointerInfo(I.getArgOperand(i: 1)),
6807 AAInfo: I.getAAMetadata(), BatchAA);
6808 updateDAGForMaybeTailCall(MaybeTC: MC);
6809 return;
6810 }
6811 case Intrinsic::memset:
6812 case Intrinsic::memset_inline: {
6813 const auto &MSII = cast<MemSetInst>(Val: I);
6814 SDValue Dst = getValue(V: I.getArgOperand(i: 0));
6815 SDValue Value = getValue(V: I.getArgOperand(i: 1));
6816 SDValue Size = getValue(V: I.getArgOperand(i: 2));
6817 assert((!MSII.isForceInlined() || isa<ConstantSDNode>(Size)) &&
6818 "memset_inline needs constant size");
6819 // @llvm.memset defines 0 and 1 to both mean no alignment.
6820 Align DstAlign = MSII.getDestAlign().valueOrOne();
6821 bool isVol = MSII.isVolatile();
6822 SDValue Root = isVol ? getRoot() : getMemoryRoot();
6823 SDValue MC = DAG.getMemset(
6824 Chain: Root, dl: sdl, Dst, Src: Value, Size, Alignment: DstAlign, isVol, AlwaysInline: MSII.isForceInlined(),
6825 CI: &I, DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)), AAInfo: I.getAAMetadata());
6826 updateDAGForMaybeTailCall(MaybeTC: MC);
6827 return;
6828 }
6829 case Intrinsic::memmove: {
6830 const auto &MMI = cast<MemMoveInst>(Val: I);
6831 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
6832 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
6833 SDValue Op3 = getValue(V: I.getArgOperand(i: 2));
6834 // @llvm.memmove defines 0 and 1 to both mean no alignment.
6835 Align DstAlign = MMI.getDestAlign().valueOrOne();
6836 Align SrcAlign = MMI.getSourceAlign().valueOrOne();
6837 bool isVol = MMI.isVolatile();
6838 SDValue Root = isVol ? getRoot() : getMemoryRoot();
6839 SDValue MM = DAG.getMemmove(
6840 Chain: Root, dl: sdl, Dst: Op1, Src: Op2, Size: Op3, DstAlign, SrcAlign, isVol, CI: &I,
6841 /* OverrideTailCall */ std::nullopt,
6842 DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
6843 SrcPtrInfo: MachinePointerInfo(I.getArgOperand(i: 1)), AAInfo: I.getAAMetadata(), BatchAA);
6844 updateDAGForMaybeTailCall(MaybeTC: MM);
6845 return;
6846 }
6847 case Intrinsic::memcpy_element_unordered_atomic: {
6848 auto &MI = cast<AnyMemCpyInst>(Val: I);
6849 SDValue Dst = getValue(V: MI.getRawDest());
6850 SDValue Src = getValue(V: MI.getRawSource());
6851 SDValue Length = getValue(V: MI.getLength());
6852
6853 Type *LengthTy = MI.getLength()->getType();
6854 unsigned ElemSz = MI.getElementSizeInBytes();
6855 bool isTC = I.isTailCall() && isInTailCallPosition(Call: I, TM: DAG.getTarget());
6856 SDValue MC =
6857 DAG.getAtomicMemcpy(Chain: getRoot(), dl: sdl, Dst, Src, Size: Length, SizeTy: LengthTy, ElemSz,
6858 isTailCall: isTC, DstPtrInfo: MachinePointerInfo(MI.getRawDest()),
6859 SrcPtrInfo: MachinePointerInfo(MI.getRawSource()));
6860 updateDAGForMaybeTailCall(MaybeTC: MC);
6861 return;
6862 }
6863 case Intrinsic::memmove_element_unordered_atomic: {
6864 auto &MI = cast<AnyMemMoveInst>(Val: I);
6865 SDValue Dst = getValue(V: MI.getRawDest());
6866 SDValue Src = getValue(V: MI.getRawSource());
6867 SDValue Length = getValue(V: MI.getLength());
6868
6869 Type *LengthTy = MI.getLength()->getType();
6870 unsigned ElemSz = MI.getElementSizeInBytes();
6871 bool isTC = I.isTailCall() && isInTailCallPosition(Call: I, TM: DAG.getTarget());
6872 SDValue MC =
6873 DAG.getAtomicMemmove(Chain: getRoot(), dl: sdl, Dst, Src, Size: Length, SizeTy: LengthTy, ElemSz,
6874 isTailCall: isTC, DstPtrInfo: MachinePointerInfo(MI.getRawDest()),
6875 SrcPtrInfo: MachinePointerInfo(MI.getRawSource()));
6876 updateDAGForMaybeTailCall(MaybeTC: MC);
6877 return;
6878 }
6879 case Intrinsic::memset_element_unordered_atomic: {
6880 auto &MI = cast<AnyMemSetInst>(Val: I);
6881 SDValue Dst = getValue(V: MI.getRawDest());
6882 SDValue Val = getValue(V: MI.getValue());
6883 SDValue Length = getValue(V: MI.getLength());
6884
6885 Type *LengthTy = MI.getLength()->getType();
6886 unsigned ElemSz = MI.getElementSizeInBytes();
6887 bool isTC = I.isTailCall() && isInTailCallPosition(Call: I, TM: DAG.getTarget());
6888 SDValue MC =
6889 DAG.getAtomicMemset(Chain: getRoot(), dl: sdl, Dst, Value: Val, Size: Length, SizeTy: LengthTy, ElemSz,
6890 isTailCall: isTC, DstPtrInfo: MachinePointerInfo(MI.getRawDest()));
6891 updateDAGForMaybeTailCall(MaybeTC: MC);
6892 return;
6893 }
6894 case Intrinsic::call_preallocated_setup: {
6895 const CallBase *PreallocatedCall = FindPreallocatedCall(PreallocatedSetup: &I);
6896 SDValue SrcValue = DAG.getSrcValue(v: PreallocatedCall);
6897 SDValue Res = DAG.getNode(Opcode: ISD::PREALLOCATED_SETUP, DL: sdl, VT: MVT::Other,
6898 N1: getRoot(), N2: SrcValue);
6899 setValue(V: &I, NewN: Res);
6900 DAG.setRoot(Res);
6901 return;
6902 }
6903 case Intrinsic::call_preallocated_arg: {
6904 const CallBase *PreallocatedCall = FindPreallocatedCall(PreallocatedSetup: I.getOperand(i_nocapture: 0));
6905 SDValue SrcValue = DAG.getSrcValue(v: PreallocatedCall);
6906 SDValue Ops[3];
6907 Ops[0] = getRoot();
6908 Ops[1] = SrcValue;
6909 Ops[2] = DAG.getTargetConstant(Val: *cast<ConstantInt>(Val: I.getArgOperand(i: 1)), DL: sdl,
6910 VT: MVT::i32); // arg index
6911 SDValue Res = DAG.getNode(
6912 Opcode: ISD::PREALLOCATED_ARG, DL: sdl,
6913 VTList: DAG.getVTList(VT1: TLI.getPointerTy(DL: DAG.getDataLayout()), VT2: MVT::Other), Ops);
6914 setValue(V: &I, NewN: Res);
6915 DAG.setRoot(Res.getValue(R: 1));
6916 return;
6917 }
6918
6919 case Intrinsic::eh_typeid_for: {
6920 // Find the type id for the given typeinfo.
6921 GlobalValue *GV = ExtractTypeInfo(V: I.getArgOperand(i: 0));
6922 unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(TI: GV);
6923 Res = DAG.getConstant(Val: TypeID, DL: sdl, VT: MVT::i32);
6924 setValue(V: &I, NewN: Res);
6925 return;
6926 }
6927
6928 case Intrinsic::eh_return_i32:
6929 case Intrinsic::eh_return_i64:
6930 DAG.getMachineFunction().setCallsEHReturn(true);
6931 DAG.setRoot(DAG.getNode(Opcode: ISD::EH_RETURN, DL: sdl,
6932 VT: MVT::Other,
6933 N1: getControlRoot(),
6934 N2: getValue(V: I.getArgOperand(i: 0)),
6935 N3: getValue(V: I.getArgOperand(i: 1))));
6936 return;
6937 case Intrinsic::eh_unwind_init:
6938 DAG.getMachineFunction().setCallsUnwindInit(true);
6939 return;
6940 case Intrinsic::eh_dwarf_cfa:
6941 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::EH_DWARF_CFA, DL: sdl,
6942 VT: TLI.getPointerTy(DL: DAG.getDataLayout()),
6943 Operand: getValue(V: I.getArgOperand(i: 0))));
6944 return;
6945 case Intrinsic::eh_sjlj_callsite: {
6946 ConstantInt *CI = cast<ConstantInt>(Val: I.getArgOperand(i: 0));
6947 assert(FuncInfo.getCurrentCallSite() == 0 && "Overlapping call sites!");
6948
6949 FuncInfo.setCurrentCallSite(CI->getZExtValue());
6950 return;
6951 }
6952 case Intrinsic::eh_sjlj_functioncontext: {
6953 // Get and store the index of the function context.
6954 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
6955 AllocaInst *FnCtx =
6956 cast<AllocaInst>(Val: I.getArgOperand(i: 0)->stripPointerCasts());
6957 int FI = FuncInfo.StaticAllocaMap[FnCtx];
6958 MFI.setFunctionContextIndex(FI);
6959 return;
6960 }
6961 case Intrinsic::eh_sjlj_setjmp: {
6962 SDValue Ops[2];
6963 Ops[0] = getRoot();
6964 Ops[1] = getValue(V: I.getArgOperand(i: 0));
6965 SDValue Op = DAG.getNode(Opcode: ISD::EH_SJLJ_SETJMP, DL: sdl,
6966 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::Other), Ops);
6967 setValue(V: &I, NewN: Op.getValue(R: 0));
6968 DAG.setRoot(Op.getValue(R: 1));
6969 return;
6970 }
6971 case Intrinsic::eh_sjlj_longjmp:
6972 DAG.setRoot(DAG.getNode(Opcode: ISD::EH_SJLJ_LONGJMP, DL: sdl, VT: MVT::Other,
6973 N1: getRoot(), N2: getValue(V: I.getArgOperand(i: 0))));
6974 return;
6975 case Intrinsic::eh_sjlj_setup_dispatch:
6976 DAG.setRoot(DAG.getNode(Opcode: ISD::EH_SJLJ_SETUP_DISPATCH, DL: sdl, VT: MVT::Other,
6977 Operand: getRoot()));
6978 return;
6979 case Intrinsic::masked_gather:
6980 visitMaskedGather(I);
6981 return;
6982 case Intrinsic::masked_load:
6983 visitMaskedLoad(I);
6984 return;
6985 case Intrinsic::masked_scatter:
6986 visitMaskedScatter(I);
6987 return;
6988 case Intrinsic::masked_store:
6989 visitMaskedStore(I);
6990 return;
6991 case Intrinsic::masked_expandload:
6992 visitMaskedLoad(I, IsExpanding: true /* IsExpanding */);
6993 return;
6994 case Intrinsic::masked_compressstore:
6995 visitMaskedStore(I, IsCompressing: true /* IsCompressing */);
6996 return;
6997 case Intrinsic::powi:
6998 setValue(V: &I, NewN: ExpandPowI(DL: sdl, LHS: getValue(V: I.getArgOperand(i: 0)),
6999 RHS: getValue(V: I.getArgOperand(i: 1)), DAG));
7000 return;
7001 case Intrinsic::log:
7002 setValue(V: &I, NewN: expandLog(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
7003 return;
7004 case Intrinsic::log2:
7005 setValue(V: &I,
7006 NewN: expandLog2(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
7007 return;
7008 case Intrinsic::log10:
7009 setValue(V: &I,
7010 NewN: expandLog10(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
7011 return;
7012 case Intrinsic::exp:
7013 setValue(V: &I, NewN: expandExp(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
7014 return;
7015 case Intrinsic::exp2:
7016 setValue(V: &I,
7017 NewN: expandExp2(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
7018 return;
7019 case Intrinsic::pow:
7020 setValue(V: &I, NewN: expandPow(dl: sdl, LHS: getValue(V: I.getArgOperand(i: 0)),
7021 RHS: getValue(V: I.getArgOperand(i: 1)), DAG, TLI, Flags));
7022 return;
7023 case Intrinsic::sqrt:
7024 case Intrinsic::fabs:
7025 case Intrinsic::sin:
7026 case Intrinsic::cos:
7027 case Intrinsic::tan:
7028 case Intrinsic::asin:
7029 case Intrinsic::acos:
7030 case Intrinsic::atan:
7031 case Intrinsic::sinh:
7032 case Intrinsic::cosh:
7033 case Intrinsic::tanh:
7034 case Intrinsic::exp10:
7035 case Intrinsic::floor:
7036 case Intrinsic::ceil:
7037 case Intrinsic::trunc:
7038 case Intrinsic::rint:
7039 case Intrinsic::nearbyint:
7040 case Intrinsic::round:
7041 case Intrinsic::roundeven:
7042 case Intrinsic::canonicalize: {
7043 unsigned Opcode;
7044 // clang-format off
7045 switch (Intrinsic) {
7046 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7047 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
7048 case Intrinsic::fabs: Opcode = ISD::FABS; break;
7049 case Intrinsic::sin: Opcode = ISD::FSIN; break;
7050 case Intrinsic::cos: Opcode = ISD::FCOS; break;
7051 case Intrinsic::tan: Opcode = ISD::FTAN; break;
7052 case Intrinsic::asin: Opcode = ISD::FASIN; break;
7053 case Intrinsic::acos: Opcode = ISD::FACOS; break;
7054 case Intrinsic::atan: Opcode = ISD::FATAN; break;
7055 case Intrinsic::sinh: Opcode = ISD::FSINH; break;
7056 case Intrinsic::cosh: Opcode = ISD::FCOSH; break;
7057 case Intrinsic::tanh: Opcode = ISD::FTANH; break;
7058 case Intrinsic::exp10: Opcode = ISD::FEXP10; break;
7059 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
7060 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
7061 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
7062 case Intrinsic::rint: Opcode = ISD::FRINT; break;
7063 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
7064 case Intrinsic::round: Opcode = ISD::FROUND; break;
7065 case Intrinsic::roundeven: Opcode = ISD::FROUNDEVEN; break;
7066 case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break;
7067 }
7068 // clang-format on
7069
7070 setValue(V: &I, NewN: DAG.getNode(Opcode, DL: sdl,
7071 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7072 Operand: getValue(V: I.getArgOperand(i: 0)), Flags));
7073 return;
7074 }
7075 case Intrinsic::atan2:
7076 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FATAN2, DL: sdl,
7077 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7078 N1: getValue(V: I.getArgOperand(i: 0)),
7079 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7080 return;
7081 case Intrinsic::lround:
7082 case Intrinsic::llround:
7083 case Intrinsic::lrint:
7084 case Intrinsic::llrint: {
7085 unsigned Opcode;
7086 // clang-format off
7087 switch (Intrinsic) {
7088 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7089 case Intrinsic::lround: Opcode = ISD::LROUND; break;
7090 case Intrinsic::llround: Opcode = ISD::LLROUND; break;
7091 case Intrinsic::lrint: Opcode = ISD::LRINT; break;
7092 case Intrinsic::llrint: Opcode = ISD::LLRINT; break;
7093 }
7094 // clang-format on
7095
7096 EVT RetVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7097 setValue(V: &I, NewN: DAG.getNode(Opcode, DL: sdl, VT: RetVT,
7098 Operand: getValue(V: I.getArgOperand(i: 0))));
7099 return;
7100 }
7101 case Intrinsic::minnum:
7102 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMINNUM, DL: sdl,
7103 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7104 N1: getValue(V: I.getArgOperand(i: 0)),
7105 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7106 return;
7107 case Intrinsic::maxnum:
7108 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMAXNUM, DL: sdl,
7109 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7110 N1: getValue(V: I.getArgOperand(i: 0)),
7111 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7112 return;
7113 case Intrinsic::minimum:
7114 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMINIMUM, DL: sdl,
7115 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7116 N1: getValue(V: I.getArgOperand(i: 0)),
7117 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7118 return;
7119 case Intrinsic::maximum:
7120 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMAXIMUM, DL: sdl,
7121 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7122 N1: getValue(V: I.getArgOperand(i: 0)),
7123 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7124 return;
7125 case Intrinsic::minimumnum:
7126 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMINIMUMNUM, DL: sdl,
7127 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7128 N1: getValue(V: I.getArgOperand(i: 0)),
7129 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7130 return;
7131 case Intrinsic::maximumnum:
7132 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMAXIMUMNUM, DL: sdl,
7133 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7134 N1: getValue(V: I.getArgOperand(i: 0)),
7135 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7136 return;
7137 case Intrinsic::copysign:
7138 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FCOPYSIGN, DL: sdl,
7139 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7140 N1: getValue(V: I.getArgOperand(i: 0)),
7141 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7142 return;
7143 case Intrinsic::ldexp:
7144 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FLDEXP, DL: sdl,
7145 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7146 N1: getValue(V: I.getArgOperand(i: 0)),
7147 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7148 return;
7149 case Intrinsic::modf:
7150 case Intrinsic::sincos:
7151 case Intrinsic::sincospi:
7152 case Intrinsic::frexp: {
7153 unsigned Opcode;
7154 switch (Intrinsic) {
7155 default:
7156 llvm_unreachable("unexpected intrinsic");
7157 case Intrinsic::sincos:
7158 Opcode = ISD::FSINCOS;
7159 break;
7160 case Intrinsic::sincospi:
7161 Opcode = ISD::FSINCOSPI;
7162 break;
7163 case Intrinsic::modf:
7164 Opcode = ISD::FMODF;
7165 break;
7166 case Intrinsic::frexp:
7167 Opcode = ISD::FFREXP;
7168 break;
7169 }
7170 SmallVector<EVT, 2> ValueVTs;
7171 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: I.getType(), ValueVTs);
7172 SDVTList VTs = DAG.getVTList(VTs: ValueVTs);
7173 setValue(
7174 V: &I, NewN: DAG.getNode(Opcode, DL: sdl, VTList: VTs, Ops: getValue(V: I.getArgOperand(i: 0)), Flags));
7175 return;
7176 }
7177 case Intrinsic::arithmetic_fence: {
7178 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::ARITH_FENCE, DL: sdl,
7179 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7180 Operand: getValue(V: I.getArgOperand(i: 0)), Flags));
7181 return;
7182 }
7183 case Intrinsic::fma:
7184 setValue(V: &I, NewN: DAG.getNode(
7185 Opcode: ISD::FMA, DL: sdl, VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7186 N1: getValue(V: I.getArgOperand(i: 0)), N2: getValue(V: I.getArgOperand(i: 1)),
7187 N3: getValue(V: I.getArgOperand(i: 2)), Flags));
7188 return;
7189#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
7190 case Intrinsic::INTRINSIC:
7191#include "llvm/IR/ConstrainedOps.def"
7192 visitConstrainedFPIntrinsic(FPI: cast<ConstrainedFPIntrinsic>(Val: I));
7193 return;
7194#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
7195#include "llvm/IR/VPIntrinsics.def"
7196 visitVectorPredicationIntrinsic(VPIntrin: cast<VPIntrinsic>(Val: I));
7197 return;
7198 case Intrinsic::fptrunc_round: {
7199 // Get the last argument, the metadata and convert it to an integer in the
7200 // call
7201 Metadata *MD = cast<MetadataAsValue>(Val: I.getArgOperand(i: 1))->getMetadata();
7202 std::optional<RoundingMode> RoundMode =
7203 convertStrToRoundingMode(cast<MDString>(Val: MD)->getString());
7204
7205 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7206
7207 // Propagate fast-math-flags from IR to node(s).
7208 SDNodeFlags Flags;
7209 Flags.copyFMF(FPMO: *cast<FPMathOperator>(Val: &I));
7210 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
7211
7212 SDValue Result;
7213 Result = DAG.getNode(
7214 Opcode: ISD::FPTRUNC_ROUND, DL: sdl, VT, N1: getValue(V: I.getArgOperand(i: 0)),
7215 N2: DAG.getTargetConstant(Val: (int)*RoundMode, DL: sdl, VT: MVT::i32));
7216 setValue(V: &I, NewN: Result);
7217
7218 return;
7219 }
7220 case Intrinsic::fmuladd: {
7221 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7222 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
7223 TLI.isFMAFasterThanFMulAndFAdd(MF: DAG.getMachineFunction(), VT)) {
7224 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMA, DL: sdl,
7225 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7226 N1: getValue(V: I.getArgOperand(i: 0)),
7227 N2: getValue(V: I.getArgOperand(i: 1)),
7228 N3: getValue(V: I.getArgOperand(i: 2)), Flags));
7229 } else if (TLI.isOperationLegalOrCustom(Op: ISD::FMULADD, VT)) {
7230 // TODO: Support splitting the vector.
7231 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMULADD, DL: sdl,
7232 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7233 N1: getValue(V: I.getArgOperand(i: 0)),
7234 N2: getValue(V: I.getArgOperand(i: 1)),
7235 N3: getValue(V: I.getArgOperand(i: 2)), Flags));
7236 } else {
7237 // TODO: Intrinsic calls should have fast-math-flags.
7238 SDValue Mul = DAG.getNode(
7239 Opcode: ISD::FMUL, DL: sdl, VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7240 N1: getValue(V: I.getArgOperand(i: 0)), N2: getValue(V: I.getArgOperand(i: 1)), Flags);
7241 SDValue Add = DAG.getNode(Opcode: ISD::FADD, DL: sdl,
7242 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7243 N1: Mul, N2: getValue(V: I.getArgOperand(i: 2)), Flags);
7244 setValue(V: &I, NewN: Add);
7245 }
7246 return;
7247 }
7248 case Intrinsic::fptosi_sat: {
7249 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7250 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_TO_SINT_SAT, DL: sdl, VT,
7251 N1: getValue(V: I.getArgOperand(i: 0)),
7252 N2: DAG.getValueType(VT.getScalarType())));
7253 return;
7254 }
7255 case Intrinsic::fptoui_sat: {
7256 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7257 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_TO_UINT_SAT, DL: sdl, VT,
7258 N1: getValue(V: I.getArgOperand(i: 0)),
7259 N2: DAG.getValueType(VT.getScalarType())));
7260 return;
7261 }
7262 case Intrinsic::convert_from_arbitrary_fp: {
7263 // Extract format metadata and convert to semantics enum.
7264 EVT DstVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7265 Metadata *MD = cast<MetadataAsValue>(Val: I.getArgOperand(i: 1))->getMetadata();
7266 StringRef FormatStr = cast<MDString>(Val: MD)->getString();
7267 const fltSemantics *SrcSem =
7268 APFloatBase::getArbitraryFPSemantics(Format: FormatStr);
7269 if (!SrcSem) {
7270 DAG.getContext()->emitError(
7271 ErrorStr: "convert_from_arbitrary_fp: not implemented format '" + FormatStr +
7272 "'");
7273 setValue(V: &I, NewN: DAG.getPOISON(VT: DstVT));
7274 return;
7275 }
7276 APFloatBase::Semantics SemEnum = APFloatBase::SemanticsToEnum(Sem: *SrcSem);
7277
7278 SDValue IntVal = getValue(V: I.getArgOperand(i: 0));
7279
7280 // Emit ISD::CONVERT_FROM_ARBITRARY_FP node.
7281 SDValue SemConst =
7282 DAG.getTargetConstant(Val: static_cast<int>(SemEnum), DL: sdl, VT: MVT::i32);
7283 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONVERT_FROM_ARBITRARY_FP, DL: sdl, VT: DstVT, N1: IntVal,
7284 N2: SemConst));
7285 return;
7286 }
7287 case Intrinsic::convert_to_arbitrary_fp: {
7288 // Extract format metadata and convert to semantics enum.
7289 EVT DstVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7290 Metadata *MD = cast<MetadataAsValue>(Val: I.getArgOperand(i: 1))->getMetadata();
7291 StringRef FormatStr = cast<MDString>(Val: MD)->getString();
7292 const fltSemantics *DstSem =
7293 APFloatBase::getArbitraryFPSemantics(Format: FormatStr);
7294 if (!DstSem) {
7295 DAG.getContext()->emitError(
7296 ErrorStr: "convert_to_arbitrary_fp: not implemented format '" + FormatStr +
7297 "'");
7298 setValue(V: &I, NewN: DAG.getPOISON(VT: DstVT));
7299 return;
7300 }
7301 APFloatBase::Semantics SemEnum = APFloatBase::SemanticsToEnum(Sem: *DstSem);
7302
7303 Metadata *RoundMD =
7304 cast<MetadataAsValue>(Val: I.getArgOperand(i: 2))->getMetadata();
7305 StringRef RoundStr = cast<MDString>(Val: RoundMD)->getString();
7306 std::optional<RoundingMode> RoundMode = convertStrToRoundingMode(RoundStr);
7307 assert(RoundMode && *RoundMode != RoundingMode::Dynamic &&
7308 "Dynamic rounding mode should have been rejected by the verifier");
7309
7310 uint64_t Saturate =
7311 cast<ConstantInt>(Val: I.getArgOperand(i: 3))->getZExtValue() ? 1 : 0;
7312
7313 SDValue FloatVal = getValue(V: I.getArgOperand(i: 0));
7314
7315 SDValue SemConst =
7316 DAG.getTargetConstant(Val: static_cast<int>(SemEnum), DL: sdl, VT: MVT::i32);
7317 SDValue RoundConst =
7318 DAG.getTargetConstant(Val: static_cast<int>(*RoundMode), DL: sdl, VT: MVT::i32);
7319 SDValue SatConst = DAG.getTargetConstant(Val: Saturate, DL: sdl, VT: MVT::i32);
7320 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONVERT_TO_ARBITRARY_FP, DL: sdl, VT: DstVT, N1: FloatVal,
7321 N2: SemConst, N3: RoundConst, N4: SatConst));
7322 return;
7323 }
7324 case Intrinsic::set_rounding:
7325 Res = DAG.getNode(Opcode: ISD::SET_ROUNDING, DL: sdl, VT: MVT::Other,
7326 Ops: {getRoot(), getValue(V: I.getArgOperand(i: 0))});
7327 setValue(V: &I, NewN: Res);
7328 DAG.setRoot(Res.getValue(R: 0));
7329 return;
7330 case Intrinsic::is_fpclass: {
7331 const DataLayout DLayout = DAG.getDataLayout();
7332 EVT DestVT = TLI.getValueType(DL: DLayout, Ty: I.getType());
7333 EVT ArgVT = TLI.getValueType(DL: DLayout, Ty: I.getArgOperand(i: 0)->getType());
7334 FPClassTest Test = static_cast<FPClassTest>(
7335 cast<ConstantInt>(Val: I.getArgOperand(i: 1))->getZExtValue());
7336 MachineFunction &MF = DAG.getMachineFunction();
7337 const Function &F = MF.getFunction();
7338 SDValue Op = getValue(V: I.getArgOperand(i: 0));
7339 SDNodeFlags Flags;
7340 Flags.setNoFPExcept(
7341 !F.getAttributes().hasFnAttr(Kind: llvm::Attribute::StrictFP));
7342 // If ISD::IS_FPCLASS should be expanded, do it right now, because the
7343 // expansion can use illegal types. Making expansion early allows
7344 // legalizing these types prior to selection.
7345 if (!TLI.isOperationLegal(Op: ISD::IS_FPCLASS, VT: ArgVT) &&
7346 !TLI.isOperationCustom(Op: ISD::IS_FPCLASS, VT: ArgVT)) {
7347 SDValue Result = TLI.expandIS_FPCLASS(ResultVT: DestVT, Op, Test, Flags, DL: sdl, DAG);
7348 setValue(V: &I, NewN: Result);
7349 return;
7350 }
7351
7352 SDValue Check = DAG.getTargetConstant(Val: Test, DL: sdl, VT: MVT::i32);
7353 SDValue V = DAG.getNode(Opcode: ISD::IS_FPCLASS, DL: sdl, VT: DestVT, Ops: {Op, Check}, Flags);
7354 setValue(V: &I, NewN: V);
7355 return;
7356 }
7357 case Intrinsic::get_fpenv: {
7358 const DataLayout DLayout = DAG.getDataLayout();
7359 EVT EnvVT = TLI.getValueType(DL: DLayout, Ty: I.getType());
7360 Align TempAlign = DAG.getEVTAlign(MemoryVT: EnvVT);
7361 SDValue Chain = getRoot();
7362 // Use GET_FPENV if it is legal or custom. Otherwise use memory-based node
7363 // and temporary storage in stack.
7364 if (TLI.isOperationLegalOrCustom(Op: ISD::GET_FPENV, VT: EnvVT)) {
7365 Res = DAG.getNode(
7366 Opcode: ISD::GET_FPENV, DL: sdl,
7367 VTList: DAG.getVTList(VT1: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
7368 VT2: MVT::Other),
7369 N: Chain);
7370 } else {
7371 SDValue Temp = DAG.CreateStackTemporary(VT: EnvVT, minAlign: TempAlign.value());
7372 int SPFI = cast<FrameIndexSDNode>(Val: Temp.getNode())->getIndex();
7373 auto MPI =
7374 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI);
7375 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7376 PtrInfo: MPI, F: MachineMemOperand::MOStore, Size: LocationSize::beforeOrAfterPointer(),
7377 BaseAlignment: TempAlign);
7378 Chain = DAG.getGetFPEnv(Chain, dl: sdl, Ptr: Temp, MemVT: EnvVT, MMO);
7379 Res = DAG.getLoad(VT: EnvVT, dl: sdl, Chain, Ptr: Temp, PtrInfo: MPI);
7380 }
7381 setValue(V: &I, NewN: Res);
7382 DAG.setRoot(Res.getValue(R: 1));
7383 return;
7384 }
7385 case Intrinsic::set_fpenv: {
7386 const DataLayout DLayout = DAG.getDataLayout();
7387 SDValue Env = getValue(V: I.getArgOperand(i: 0));
7388 EVT EnvVT = Env.getValueType();
7389 Align TempAlign = DAG.getEVTAlign(MemoryVT: EnvVT);
7390 SDValue Chain = getRoot();
7391 // If SET_FPENV is custom or legal, use it. Otherwise use loading
7392 // environment from memory.
7393 if (TLI.isOperationLegalOrCustom(Op: ISD::SET_FPENV, VT: EnvVT)) {
7394 Chain = DAG.getNode(Opcode: ISD::SET_FPENV, DL: sdl, VT: MVT::Other, N1: Chain, N2: Env);
7395 } else {
7396 // Allocate space in stack, copy environment bits into it and use this
7397 // memory in SET_FPENV_MEM.
7398 SDValue Temp = DAG.CreateStackTemporary(VT: EnvVT, minAlign: TempAlign.value());
7399 int SPFI = cast<FrameIndexSDNode>(Val: Temp.getNode())->getIndex();
7400 auto MPI =
7401 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI);
7402 Chain = DAG.getStore(Chain, dl: sdl, Val: Env, Ptr: Temp, PtrInfo: MPI, Alignment: TempAlign,
7403 MMOFlags: MachineMemOperand::MOStore);
7404 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7405 PtrInfo: MPI, F: MachineMemOperand::MOLoad, Size: LocationSize::beforeOrAfterPointer(),
7406 BaseAlignment: TempAlign);
7407 Chain = DAG.getSetFPEnv(Chain, dl: sdl, Ptr: Temp, MemVT: EnvVT, MMO);
7408 }
7409 DAG.setRoot(Chain);
7410 return;
7411 }
7412 case Intrinsic::reset_fpenv:
7413 DAG.setRoot(DAG.getNode(Opcode: ISD::RESET_FPENV, DL: sdl, VT: MVT::Other, Operand: getRoot()));
7414 return;
7415 case Intrinsic::get_fpmode:
7416 Res = DAG.getNode(
7417 Opcode: ISD::GET_FPMODE, DL: sdl,
7418 VTList: DAG.getVTList(VT1: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
7419 VT2: MVT::Other),
7420 N: DAG.getRoot());
7421 setValue(V: &I, NewN: Res);
7422 DAG.setRoot(Res.getValue(R: 1));
7423 return;
7424 case Intrinsic::set_fpmode:
7425 Res = DAG.getNode(Opcode: ISD::SET_FPMODE, DL: sdl, VT: MVT::Other, N1: {DAG.getRoot()},
7426 N2: getValue(V: I.getArgOperand(i: 0)));
7427 DAG.setRoot(Res);
7428 return;
7429 case Intrinsic::reset_fpmode: {
7430 Res = DAG.getNode(Opcode: ISD::RESET_FPMODE, DL: sdl, VT: MVT::Other, Operand: getRoot());
7431 DAG.setRoot(Res);
7432 return;
7433 }
7434 case Intrinsic::pcmarker: {
7435 SDValue Tmp = getValue(V: I.getArgOperand(i: 0));
7436 DAG.setRoot(DAG.getNode(Opcode: ISD::PCMARKER, DL: sdl, VT: MVT::Other, N1: getRoot(), N2: Tmp));
7437 return;
7438 }
7439 case Intrinsic::readcyclecounter: {
7440 SDValue Op = getRoot();
7441 Res = DAG.getNode(Opcode: ISD::READCYCLECOUNTER, DL: sdl,
7442 VTList: DAG.getVTList(VT1: MVT::i64, VT2: MVT::Other), N: Op);
7443 setValue(V: &I, NewN: Res);
7444 DAG.setRoot(Res.getValue(R: 1));
7445 return;
7446 }
7447 case Intrinsic::readsteadycounter: {
7448 SDValue Op = getRoot();
7449 Res = DAG.getNode(Opcode: ISD::READSTEADYCOUNTER, DL: sdl,
7450 VTList: DAG.getVTList(VT1: MVT::i64, VT2: MVT::Other), N: Op);
7451 setValue(V: &I, NewN: Res);
7452 DAG.setRoot(Res.getValue(R: 1));
7453 return;
7454 }
7455 case Intrinsic::bitreverse:
7456 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::BITREVERSE, DL: sdl,
7457 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7458 Operand: getValue(V: I.getArgOperand(i: 0))));
7459 return;
7460 case Intrinsic::bswap:
7461 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::BSWAP, DL: sdl,
7462 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7463 Operand: getValue(V: I.getArgOperand(i: 0))));
7464 return;
7465 case Intrinsic::cttz: {
7466 SDValue Arg = getValue(V: I.getArgOperand(i: 0));
7467 ConstantInt *CI = cast<ConstantInt>(Val: I.getArgOperand(i: 1));
7468 EVT Ty = Arg.getValueType();
7469 setValue(V: &I, NewN: DAG.getNode(Opcode: CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_POISON,
7470 DL: sdl, VT: Ty, Operand: Arg));
7471 return;
7472 }
7473 case Intrinsic::ctlz: {
7474 SDValue Arg = getValue(V: I.getArgOperand(i: 0));
7475 ConstantInt *CI = cast<ConstantInt>(Val: I.getArgOperand(i: 1));
7476 EVT Ty = Arg.getValueType();
7477 setValue(V: &I, NewN: DAG.getNode(Opcode: CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_POISON,
7478 DL: sdl, VT: Ty, Operand: Arg));
7479 return;
7480 }
7481 case Intrinsic::ctpop: {
7482 SDValue Arg = getValue(V: I.getArgOperand(i: 0));
7483 EVT Ty = Arg.getValueType();
7484 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CTPOP, DL: sdl, VT: Ty, Operand: Arg));
7485 return;
7486 }
7487 case Intrinsic::fshl:
7488 case Intrinsic::fshr: {
7489 bool IsFSHL = Intrinsic == Intrinsic::fshl;
7490 SDValue X = getValue(V: I.getArgOperand(i: 0));
7491 SDValue Y = getValue(V: I.getArgOperand(i: 1));
7492 SDValue Z = getValue(V: I.getArgOperand(i: 2));
7493 EVT VT = X.getValueType();
7494
7495 if (X == Y) {
7496 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
7497 setValue(V: &I, NewN: DAG.getNode(Opcode: RotateOpcode, DL: sdl, VT, N1: X, N2: Z));
7498 } else {
7499 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;
7500 setValue(V: &I, NewN: DAG.getNode(Opcode: FunnelOpcode, DL: sdl, VT, N1: X, N2: Y, N3: Z));
7501 }
7502 return;
7503 }
7504 case Intrinsic::clmul: {
7505 SDValue X = getValue(V: I.getArgOperand(i: 0));
7506 SDValue Y = getValue(V: I.getArgOperand(i: 1));
7507 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CLMUL, DL: sdl, VT: X.getValueType(), N1: X, N2: Y));
7508 return;
7509 }
7510 case Intrinsic::pext: {
7511 SDValue X = getValue(V: I.getArgOperand(i: 0));
7512 SDValue Y = getValue(V: I.getArgOperand(i: 1));
7513 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::PEXT, DL: sdl, VT: X.getValueType(), N1: X, N2: Y));
7514 return;
7515 }
7516 case Intrinsic::pdep: {
7517 SDValue X = getValue(V: I.getArgOperand(i: 0));
7518 SDValue Y = getValue(V: I.getArgOperand(i: 1));
7519 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::PDEP, DL: sdl, VT: X.getValueType(), N1: X, N2: Y));
7520 return;
7521 }
7522 case Intrinsic::sadd_sat: {
7523 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7524 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7525 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SADDSAT, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7526 return;
7527 }
7528 case Intrinsic::uadd_sat: {
7529 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7530 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7531 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UADDSAT, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7532 return;
7533 }
7534 case Intrinsic::ssub_sat: {
7535 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7536 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7537 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SSUBSAT, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7538 return;
7539 }
7540 case Intrinsic::usub_sat: {
7541 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7542 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7543 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::USUBSAT, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7544 return;
7545 }
7546 case Intrinsic::sshl_sat:
7547 case Intrinsic::ushl_sat: {
7548 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7549 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7550
7551 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
7552 LHSTy: Op1.getValueType(), DL: DAG.getDataLayout());
7553
7554 // Coerce the shift amount to the right type if we can. This exposes the
7555 // truncate or zext to optimization early.
7556 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
7557 assert(ShiftTy.getSizeInBits() >=
7558 Log2_32_Ceil(Op1.getValueSizeInBits()) &&
7559 "Unexpected shift type");
7560 Op2 = DAG.getZExtOrTrunc(Op: Op2, DL: getCurSDLoc(), VT: ShiftTy);
7561 }
7562
7563 unsigned Opc =
7564 Intrinsic == Intrinsic::sshl_sat ? ISD::SSHLSAT : ISD::USHLSAT;
7565 setValue(V: &I, NewN: DAG.getNode(Opcode: Opc, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7566 return;
7567 }
7568 case Intrinsic::smul_fix:
7569 case Intrinsic::umul_fix:
7570 case Intrinsic::smul_fix_sat:
7571 case Intrinsic::umul_fix_sat: {
7572 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7573 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7574 SDValue Op3 = getValue(V: I.getArgOperand(i: 2));
7575 setValue(V: &I, NewN: DAG.getNode(Opcode: FixedPointIntrinsicToOpcode(Intrinsic), DL: sdl,
7576 VT: Op1.getValueType(), N1: Op1, N2: Op2, N3: Op3));
7577 return;
7578 }
7579 case Intrinsic::sdiv_fix:
7580 case Intrinsic::udiv_fix:
7581 case Intrinsic::sdiv_fix_sat:
7582 case Intrinsic::udiv_fix_sat: {
7583 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7584 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7585 SDValue Op3 = getValue(V: I.getArgOperand(i: 2));
7586 setValue(V: &I, NewN: expandDivFix(Opcode: FixedPointIntrinsicToOpcode(Intrinsic), DL: sdl,
7587 LHS: Op1, RHS: Op2, Scale: Op3, DAG, TLI));
7588 return;
7589 }
7590 case Intrinsic::smax: {
7591 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7592 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7593 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SMAX, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7594 return;
7595 }
7596 case Intrinsic::smin: {
7597 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7598 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7599 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SMIN, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7600 return;
7601 }
7602 case Intrinsic::umax: {
7603 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7604 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7605 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UMAX, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7606 return;
7607 }
7608 case Intrinsic::umin: {
7609 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7610 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7611 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UMIN, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7612 return;
7613 }
7614 case Intrinsic::abs: {
7615 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7616 bool IntMinIsPoison = cast<ConstantInt>(Val: I.getArgOperand(i: 1))->isOne();
7617 unsigned Opc = IntMinIsPoison ? ISD::ABS_MIN_POISON : ISD::ABS;
7618 setValue(V: &I, NewN: DAG.getNode(Opcode: Opc, DL: sdl, VT: Op1.getValueType(), Operand: Op1));
7619 return;
7620 }
7621 case Intrinsic::scmp: {
7622 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7623 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7624 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7625 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SCMP, DL: sdl, VT: DestVT, N1: Op1, N2: Op2));
7626 break;
7627 }
7628 case Intrinsic::ucmp: {
7629 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7630 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7631 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7632 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UCMP, DL: sdl, VT: DestVT, N1: Op1, N2: Op2));
7633 break;
7634 }
7635 case Intrinsic::stackaddress:
7636 case Intrinsic::stacksave: {
7637 unsigned SDOpcode = Intrinsic == Intrinsic::stackaddress ? ISD::STACKADDRESS
7638 : ISD::STACKSAVE;
7639 SDValue Op = getRoot();
7640 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7641 Res = DAG.getNode(Opcode: SDOpcode, DL: sdl, VTList: DAG.getVTList(VT1: VT, VT2: MVT::Other), N: Op);
7642 setValue(V: &I, NewN: Res);
7643 DAG.setRoot(Res.getValue(R: 1));
7644 return;
7645 }
7646 case Intrinsic::stackrestore:
7647 Res = getValue(V: I.getArgOperand(i: 0));
7648 DAG.setRoot(DAG.getNode(Opcode: ISD::STACKRESTORE, DL: sdl, VT: MVT::Other, N1: getRoot(), N2: Res));
7649 return;
7650 case Intrinsic::get_dynamic_area_offset: {
7651 SDValue Op = getRoot();
7652 EVT ResTy = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7653 Res = DAG.getNode(Opcode: ISD::GET_DYNAMIC_AREA_OFFSET, DL: sdl, VTList: DAG.getVTList(VT: ResTy),
7654 N: Op);
7655 DAG.setRoot(Op);
7656 setValue(V: &I, NewN: Res);
7657 return;
7658 }
7659 case Intrinsic::stackguard: {
7660 MachineFunction &MF = DAG.getMachineFunction();
7661 const Module &M = *MF.getFunction().getParent();
7662 EVT PtrTy = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7663 SDValue Chain = getRoot();
7664 if (TLI.useLoadStackGuardNode(M)) {
7665 Res = getLoadStackGuard(DAG, DL: sdl, Chain);
7666 Res = DAG.getPtrExtOrTrunc(Op: Res, DL: sdl, VT: PtrTy);
7667 } else {
7668 const Value *Global = TLI.getSDagStackGuard(M, Libcalls: DAG.getLibcalls());
7669 if (!Global) {
7670 LLVMContext &Ctx = *DAG.getContext();
7671 Ctx.diagnose(DI: DiagnosticInfoGeneric("unable to lower stackguard"));
7672 setValue(V: &I, NewN: DAG.getPOISON(VT: PtrTy));
7673 return;
7674 }
7675
7676 Align Align = DAG.getDataLayout().getPrefTypeAlign(Ty: Global->getType());
7677 Res = DAG.getLoad(VT: PtrTy, dl: sdl, Chain, Ptr: getValue(V: Global),
7678 PtrInfo: MachinePointerInfo(Global, 0), Alignment: Align,
7679 MMOFlags: MachineMemOperand::MOVolatile);
7680 }
7681 // Mix the cookie with FP if enabled. Skip if using LOAD_STACK_GUARD
7682 // with post-RA mixing (AArch64 MSVCRT), as the mixing will be done during
7683 // post-RA expansion of LOAD_STACK_GUARD.
7684 if (TLI.useStackGuardMixFP() && !TLI.useLoadStackGuardNode(M))
7685 Res = TLI.emitStackGuardMixFP(DAG, Val: Res, DL: sdl);
7686 DAG.setRoot(Chain);
7687 setValue(V: &I, NewN: Res);
7688 return;
7689 }
7690 case Intrinsic::stackprotector: {
7691 // Emit code into the DAG to store the stack guard onto the stack.
7692 MachineFunction &MF = DAG.getMachineFunction();
7693 MachineFrameInfo &MFI = MF.getFrameInfo();
7694 const Module &M = *MF.getFunction().getParent();
7695 SDValue Src, Chain = getRoot();
7696
7697 if (TLI.useLoadStackGuardNode(M))
7698 Src = getLoadStackGuard(DAG, DL: sdl, Chain);
7699 else
7700 Src = getValue(V: I.getArgOperand(i: 0)); // The guard's value.
7701
7702 AllocaInst *Slot = cast<AllocaInst>(Val: I.getArgOperand(i: 1));
7703
7704 int FI = FuncInfo.StaticAllocaMap[Slot];
7705 MFI.setStackProtectorIndex(FI);
7706 EVT PtrTy = TLI.getFrameIndexTy(DL: DAG.getDataLayout());
7707
7708 SDValue FIN = DAG.getFrameIndex(FI, VT: PtrTy);
7709
7710 // Store the stack protector onto the stack.
7711 Res = DAG.getStore(
7712 Chain, dl: sdl, Val: Src, Ptr: FIN,
7713 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI),
7714 Alignment: MaybeAlign(), MMOFlags: MachineMemOperand::MOVolatile);
7715 setValue(V: &I, NewN: Res);
7716 DAG.setRoot(Res);
7717 return;
7718 }
7719 case Intrinsic::objectsize:
7720 llvm_unreachable("llvm.objectsize.* should have been lowered already");
7721
7722 case Intrinsic::is_constant:
7723 llvm_unreachable("llvm.is.constant.* should have been lowered already");
7724
7725 case Intrinsic::annotation:
7726 case Intrinsic::ptr_annotation:
7727 case Intrinsic::launder_invariant_group:
7728 case Intrinsic::strip_invariant_group:
7729 // Drop the intrinsic, but forward the value
7730 setValue(V: &I, NewN: getValue(V: I.getOperand(i_nocapture: 0)));
7731 return;
7732
7733 case Intrinsic::type_test:
7734 case Intrinsic::public_type_test:
7735 case Intrinsic::type_checked_load:
7736 case Intrinsic::type_checked_load_relative: {
7737 // These intrinsics are expected to be lowered by the LowerTypeTests pass
7738 // before code generation. Surviving until here usually indicates a
7739 // misconfiguration, for instance when devirtualization is enabled but LTO
7740 // does not actually run.
7741 DAG.getContext()->diagnose(DI: DiagnosticInfoUnsupported(
7742 *I.getFunction(),
7743 Intrinsic::getBaseName(id: Intrinsic) +
7744 " intrinsic must be lowered by the LowerTypeTests pass "
7745 "before code generation",
7746 sdl.getDebugLoc()));
7747
7748 // Lower the result to poison so that compilation can continue and collect
7749 // any further diagnostics.
7750 setValueToPoison(V: &I, dl: sdl);
7751 return;
7752 }
7753
7754 case Intrinsic::assume:
7755 case Intrinsic::experimental_noalias_scope_decl:
7756 case Intrinsic::var_annotation:
7757 case Intrinsic::sideeffect:
7758 // Discard annotate attributes, noalias scope declarations, assumptions, and
7759 // artificial side-effects.
7760 return;
7761
7762 case Intrinsic::codeview_annotation: {
7763 // Emit a label associated with this metadata.
7764 MachineFunction &MF = DAG.getMachineFunction();
7765 MCSymbol *Label = MF.getContext().createTempSymbol(Name: "annotation", AlwaysAddSuffix: true);
7766 Metadata *MD = cast<MetadataAsValue>(Val: I.getArgOperand(i: 0))->getMetadata();
7767 MF.addCodeViewAnnotation(Label, MD: cast<MDNode>(Val: MD));
7768 Res = DAG.getLabelNode(Opcode: ISD::ANNOTATION_LABEL, dl: sdl, Root: getRoot(), Label);
7769 DAG.setRoot(Res);
7770 return;
7771 }
7772
7773 case Intrinsic::init_trampoline: {
7774 const Function *F = cast<Function>(Val: I.getArgOperand(i: 1)->stripPointerCasts());
7775
7776 SDValue Ops[6];
7777 Ops[0] = getRoot();
7778 Ops[1] = getValue(V: I.getArgOperand(i: 0));
7779 Ops[2] = getValue(V: I.getArgOperand(i: 1));
7780 Ops[3] = getValue(V: I.getArgOperand(i: 2));
7781 Ops[4] = DAG.getSrcValue(v: I.getArgOperand(i: 0));
7782 Ops[5] = DAG.getSrcValue(v: F);
7783
7784 Res = DAG.getNode(Opcode: ISD::INIT_TRAMPOLINE, DL: sdl, VT: MVT::Other, Ops);
7785
7786 DAG.setRoot(Res);
7787 return;
7788 }
7789 case Intrinsic::adjust_trampoline:
7790 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::ADJUST_TRAMPOLINE, DL: sdl,
7791 VT: TLI.getPointerTy(DL: DAG.getDataLayout()),
7792 Operand: getValue(V: I.getArgOperand(i: 0))));
7793 return;
7794 case Intrinsic::gcroot: {
7795 assert(DAG.getMachineFunction().getFunction().hasGC() &&
7796 "only valid in functions with gc specified, enforced by Verifier");
7797 assert(GFI && "implied by previous");
7798 const Value *Alloca = I.getArgOperand(i: 0)->stripPointerCasts();
7799 const Constant *TypeMap = cast<Constant>(Val: I.getArgOperand(i: 1));
7800
7801 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Val: getValue(V: Alloca).getNode());
7802 GFI->addStackRoot(Num: FI->getIndex(), Metadata: TypeMap);
7803 return;
7804 }
7805 case Intrinsic::gcread:
7806 case Intrinsic::gcwrite:
7807 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
7808 case Intrinsic::get_rounding:
7809 Res = DAG.getNode(Opcode: ISD::GET_ROUNDING, DL: sdl, ResultTys: {MVT::i32, MVT::Other}, Ops: getRoot());
7810 setValue(V: &I, NewN: Res);
7811 DAG.setRoot(Res.getValue(R: 1));
7812 return;
7813
7814 case Intrinsic::expect:
7815 case Intrinsic::expect_with_probability:
7816 // Just replace __builtin_expect(exp, c) and
7817 // __builtin_expect_with_probability(exp, c, p) with EXP.
7818 setValue(V: &I, NewN: getValue(V: I.getArgOperand(i: 0)));
7819 return;
7820
7821 case Intrinsic::ubsantrap:
7822 case Intrinsic::debugtrap:
7823 case Intrinsic::trap: {
7824 StringRef TrapFuncName =
7825 I.getAttributes().getFnAttr(Kind: "trap-func-name").getValueAsString();
7826 if (TrapFuncName.empty()) {
7827 switch (Intrinsic) {
7828 case Intrinsic::trap:
7829 DAG.setRoot(DAG.getNode(Opcode: ISD::TRAP, DL: sdl, VT: MVT::Other, Operand: getRoot()));
7830 break;
7831 case Intrinsic::debugtrap:
7832 DAG.setRoot(DAG.getNode(Opcode: ISD::DEBUGTRAP, DL: sdl, VT: MVT::Other, Operand: getRoot()));
7833 break;
7834 case Intrinsic::ubsantrap:
7835 DAG.setRoot(DAG.getNode(
7836 Opcode: ISD::UBSANTRAP, DL: sdl, VT: MVT::Other, N1: getRoot(),
7837 N2: DAG.getTargetConstant(
7838 Val: cast<ConstantInt>(Val: I.getArgOperand(i: 0))->getZExtValue(), DL: sdl,
7839 VT: MVT::i32)));
7840 break;
7841 default: llvm_unreachable("unknown trap intrinsic");
7842 }
7843 DAG.addNoMergeSiteInfo(Node: DAG.getRoot().getNode(),
7844 NoMerge: I.hasFnAttr(Kind: Attribute::NoMerge));
7845 return;
7846 }
7847 TargetLowering::ArgListTy Args;
7848 if (Intrinsic == Intrinsic::ubsantrap) {
7849 Value *Arg = I.getArgOperand(i: 0);
7850 Args.emplace_back(args&: Arg, args: getValue(V: Arg));
7851 }
7852
7853 TargetLowering::CallLoweringInfo CLI(DAG);
7854 CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee(
7855 CC: CallingConv::C, ResultType: I.getType(),
7856 Target: DAG.getExternalSymbol(Sym: TrapFuncName.data(),
7857 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
7858 ArgsList: std::move(Args));
7859 CLI.NoMerge = I.hasFnAttr(Kind: Attribute::NoMerge);
7860 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
7861 DAG.setRoot(Result.second);
7862 return;
7863 }
7864
7865 case Intrinsic::allow_runtime_check:
7866 case Intrinsic::allow_ubsan_check:
7867 setValue(V: &I, NewN: getValue(V: ConstantInt::getTrue(Ty: I.getType())));
7868 return;
7869
7870 case Intrinsic::uadd_with_overflow:
7871 case Intrinsic::sadd_with_overflow:
7872 case Intrinsic::usub_with_overflow:
7873 case Intrinsic::ssub_with_overflow:
7874 case Intrinsic::umul_with_overflow:
7875 case Intrinsic::smul_with_overflow: {
7876 ISD::NodeType Op;
7877 switch (Intrinsic) {
7878 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7879 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
7880 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
7881 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
7882 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
7883 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
7884 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
7885 }
7886 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7887 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7888
7889 EVT ResultVT = Op1.getValueType();
7890 EVT OverflowVT = ResultVT.changeElementType(Context&: *Context, EltVT: MVT::i1);
7891
7892 SDVTList VTs = DAG.getVTList(VT1: ResultVT, VT2: OverflowVT);
7893 setValue(V: &I, NewN: DAG.getNode(Opcode: Op, DL: sdl, VTList: VTs, N1: Op1, N2: Op2));
7894 return;
7895 }
7896 case Intrinsic::prefetch: {
7897 SDValue Ops[5];
7898 unsigned rw = cast<ConstantInt>(Val: I.getArgOperand(i: 1))->getZExtValue();
7899 auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore;
7900 Ops[0] = DAG.getRoot();
7901 Ops[1] = getValue(V: I.getArgOperand(i: 0));
7902 Ops[2] = DAG.getTargetConstant(Val: *cast<ConstantInt>(Val: I.getArgOperand(i: 1)), DL: sdl,
7903 VT: MVT::i32);
7904 Ops[3] = DAG.getTargetConstant(Val: *cast<ConstantInt>(Val: I.getArgOperand(i: 2)), DL: sdl,
7905 VT: MVT::i32);
7906 Ops[4] = DAG.getTargetConstant(Val: *cast<ConstantInt>(Val: I.getArgOperand(i: 3)), DL: sdl,
7907 VT: MVT::i32);
7908 SDValue Result = DAG.getMemIntrinsicNode(
7909 Opcode: ISD::PREFETCH, dl: sdl, VTList: DAG.getVTList(VT: MVT::Other), Ops,
7910 MemVT: EVT::getIntegerVT(Context&: *Context, BitWidth: 8), PtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
7911 /* align */ Alignment: std::nullopt, Flags);
7912
7913 // Chain the prefetch in parallel with any pending loads, to stay out of
7914 // the way of later optimizations.
7915 PendingLoads.push_back(Elt: Result);
7916 Result = getRoot();
7917 DAG.setRoot(Result);
7918 return;
7919 }
7920 case Intrinsic::lifetime_start:
7921 case Intrinsic::lifetime_end: {
7922 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
7923 // Stack coloring is not enabled in O0, discard region information.
7924 if (TM.getOptLevel() == CodeGenOptLevel::None)
7925 return;
7926
7927 const AllocaInst *LifetimeObject = dyn_cast<AllocaInst>(Val: I.getArgOperand(i: 0));
7928 if (!LifetimeObject)
7929 return;
7930
7931 // First check that the Alloca is static, otherwise it won't have a
7932 // valid frame index.
7933 auto SI = FuncInfo.StaticAllocaMap.find(Val: LifetimeObject);
7934 if (SI == FuncInfo.StaticAllocaMap.end())
7935 return;
7936
7937 const int FrameIndex = SI->second;
7938 Res = DAG.getLifetimeNode(IsStart, dl: sdl, Chain: getRoot(), FrameIndex);
7939 DAG.setRoot(Res);
7940 return;
7941 }
7942 case Intrinsic::pseudoprobe: {
7943 auto Guid = cast<ConstantInt>(Val: I.getArgOperand(i: 0))->getZExtValue();
7944 auto Index = cast<ConstantInt>(Val: I.getArgOperand(i: 1))->getZExtValue();
7945 auto Attr = cast<ConstantInt>(Val: I.getArgOperand(i: 2))->getZExtValue();
7946 Res = DAG.getPseudoProbeNode(Dl: sdl, Chain: getRoot(), Guid, Index, Attr);
7947 DAG.setRoot(Res);
7948 return;
7949 }
7950 case Intrinsic::invariant_start:
7951 // Discard region information.
7952 setValue(V: &I,
7953 NewN: DAG.getUNDEF(VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType())));
7954 return;
7955 case Intrinsic::invariant_end:
7956 // Discard region information.
7957 return;
7958 case Intrinsic::clear_cache: {
7959 SDValue InputChain = DAG.getRoot();
7960 SDValue StartVal = getValue(V: I.getArgOperand(i: 0));
7961 SDValue EndVal = getValue(V: I.getArgOperand(i: 1));
7962 Res = DAG.getNode(Opcode: ISD::CLEAR_CACHE, DL: sdl, VTList: DAG.getVTList(VT: MVT::Other),
7963 Ops: {InputChain, StartVal, EndVal});
7964 setValue(V: &I, NewN: Res);
7965 DAG.setRoot(Res);
7966 return;
7967 }
7968 case Intrinsic::donothing:
7969 case Intrinsic::seh_try_begin:
7970 case Intrinsic::seh_scope_begin:
7971 case Intrinsic::seh_try_end:
7972 case Intrinsic::seh_scope_end:
7973 // ignore
7974 return;
7975 case Intrinsic::experimental_stackmap:
7976 visitStackmap(I);
7977 return;
7978 case Intrinsic::experimental_patchpoint_void:
7979 case Intrinsic::experimental_patchpoint:
7980 visitPatchpoint(CB: I);
7981 return;
7982 case Intrinsic::experimental_gc_statepoint:
7983 LowerStatepoint(I: cast<GCStatepointInst>(Val: I));
7984 return;
7985 case Intrinsic::experimental_gc_result:
7986 visitGCResult(I: cast<GCResultInst>(Val: I));
7987 return;
7988 case Intrinsic::experimental_gc_relocate:
7989 visitGCRelocate(Relocate: cast<GCRelocateInst>(Val: I));
7990 return;
7991 case Intrinsic::instrprof_cover:
7992 llvm_unreachable("instrprof failed to lower a cover");
7993 case Intrinsic::instrprof_increment:
7994 llvm_unreachable("instrprof failed to lower an increment");
7995 case Intrinsic::instrprof_timestamp:
7996 llvm_unreachable("instrprof failed to lower a timestamp");
7997 case Intrinsic::instrprof_value_profile:
7998 llvm_unreachable("instrprof failed to lower a value profiling call");
7999 case Intrinsic::instrprof_mcdc_parameters:
8000 llvm_unreachable("instrprof failed to lower mcdc parameters");
8001 case Intrinsic::instrprof_mcdc_tvbitmap_update:
8002 llvm_unreachable("instrprof failed to lower an mcdc tvbitmap update");
8003 case Intrinsic::localescape: {
8004 MachineFunction &MF = DAG.getMachineFunction();
8005 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
8006
8007 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
8008 // is the same on all targets.
8009 for (unsigned Idx = 0, E = I.arg_size(); Idx < E; ++Idx) {
8010 Value *Arg = I.getArgOperand(i: Idx)->stripPointerCasts();
8011 if (isa<ConstantPointerNull>(Val: Arg))
8012 continue; // Skip null pointers. They represent a hole in index space.
8013 AllocaInst *Slot = cast<AllocaInst>(Val: Arg);
8014 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
8015 "can only escape static allocas");
8016 int FI = FuncInfo.StaticAllocaMap[Slot];
8017 MCSymbol *FrameAllocSym = MF.getContext().getOrCreateFrameAllocSymbol(
8018 FuncName: GlobalValue::dropLLVMManglingEscape(Name: MF.getName()), Idx);
8019 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD: dl,
8020 MCID: TII->get(Opcode: TargetOpcode::LOCAL_ESCAPE))
8021 .addSym(Sym: FrameAllocSym)
8022 .addFrameIndex(Idx: FI);
8023 }
8024
8025 return;
8026 }
8027
8028 case Intrinsic::localrecover: {
8029 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
8030 MachineFunction &MF = DAG.getMachineFunction();
8031
8032 // Get the symbol that defines the frame offset.
8033 auto *Fn = cast<Function>(Val: I.getArgOperand(i: 0)->stripPointerCasts());
8034 auto *Idx = cast<ConstantInt>(Val: I.getArgOperand(i: 2));
8035 unsigned IdxVal =
8036 unsigned(Idx->getLimitedValue(Limit: std::numeric_limits<int>::max()));
8037 MCSymbol *FrameAllocSym = MF.getContext().getOrCreateFrameAllocSymbol(
8038 FuncName: GlobalValue::dropLLVMManglingEscape(Name: Fn->getName()), Idx: IdxVal);
8039
8040 Value *FP = I.getArgOperand(i: 1);
8041 SDValue FPVal = getValue(V: FP);
8042 EVT PtrVT = FPVal.getValueType();
8043
8044 // Create a MCSymbol for the label to avoid any target lowering
8045 // that would make this PC relative.
8046 SDValue OffsetSym = DAG.getMCSymbol(Sym: FrameAllocSym, VT: PtrVT);
8047 SDValue OffsetVal =
8048 DAG.getNode(Opcode: ISD::LOCAL_RECOVER, DL: sdl, VT: PtrVT, Operand: OffsetSym);
8049
8050 // Add the offset to the FP.
8051 SDValue Add = DAG.getMemBasePlusOffset(Base: FPVal, Offset: OffsetVal, DL: sdl);
8052 setValue(V: &I, NewN: Add);
8053
8054 return;
8055 }
8056
8057 case Intrinsic::fake_use: {
8058 Value *V = I.getArgOperand(i: 0);
8059 SDValue Ops[2];
8060 // For Values not declared or previously used in this basic block, the
8061 // NodeMap will not have an entry, and `getValue` will assert if V has no
8062 // valid register value.
8063 auto FakeUseValue = [&]() -> SDValue {
8064 SDValue &N = NodeMap[V];
8065 if (N.getNode())
8066 return N;
8067
8068 // If there's a virtual register allocated and initialized for this
8069 // value, use it.
8070 if (SDValue copyFromReg = getCopyFromRegs(V, Ty: V->getType()))
8071 return copyFromReg;
8072 // FIXME: Do we want to preserve constants? It seems pointless.
8073 if (isa<Constant>(Val: V))
8074 return getValue(V);
8075 return SDValue();
8076 }();
8077 if (!FakeUseValue || FakeUseValue.isUndef())
8078 return;
8079 Ops[0] = getRoot();
8080 Ops[1] = FakeUseValue;
8081 // Also, do not translate a fake use with an undef operand, or any other
8082 // empty SDValues.
8083 if (!Ops[1] || Ops[1].isUndef())
8084 return;
8085 DAG.setRoot(DAG.getNode(Opcode: ISD::FAKE_USE, DL: sdl, VT: MVT::Other, Ops));
8086 return;
8087 }
8088
8089 case Intrinsic::reloc_none: {
8090 Metadata *MD = cast<MetadataAsValue>(Val: I.getArgOperand(i: 0))->getMetadata();
8091 StringRef SymbolName = cast<MDString>(Val: MD)->getString();
8092 SDValue Ops[2] = {
8093 getRoot(),
8094 DAG.getTargetExternalSymbol(
8095 Sym: SymbolName.data(), VT: TLI.getProgramPointerTy(DL: DAG.getDataLayout()))};
8096 DAG.setRoot(DAG.getNode(Opcode: ISD::RELOC_NONE, DL: sdl, VT: MVT::Other, Ops));
8097 return;
8098 }
8099
8100 case Intrinsic::cond_loop: {
8101 SDValue InputChain = DAG.getRoot();
8102 SDValue P = getValue(V: I.getArgOperand(i: 0));
8103 Res = DAG.getNode(Opcode: ISD::COND_LOOP, DL: sdl, VTList: DAG.getVTList(VT: MVT::Other),
8104 Ops: {InputChain, P});
8105 setValue(V: &I, NewN: Res);
8106 DAG.setRoot(Res);
8107 return;
8108 }
8109
8110 case Intrinsic::eh_exceptionpointer:
8111 case Intrinsic::eh_exceptioncode: {
8112 // Get the exception pointer vreg, copy from it, and resize it to fit.
8113 const auto *CPI = cast<CatchPadInst>(Val: I.getArgOperand(i: 0));
8114 MVT PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
8115 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(VT: PtrVT);
8116 Register VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, RC: PtrRC);
8117 SDValue N = DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl: sdl, Reg: VReg, VT: PtrVT);
8118 if (Intrinsic == Intrinsic::eh_exceptioncode)
8119 N = DAG.getZExtOrTrunc(Op: N, DL: sdl, VT: MVT::i32);
8120 setValue(V: &I, NewN: N);
8121 return;
8122 }
8123 case Intrinsic::xray_customevent: {
8124 // Here we want to make sure that the intrinsic behaves as if it has a
8125 // specific calling convention.
8126 const auto &Triple = DAG.getTarget().getTargetTriple();
8127 if (!Triple.isAArch64(PointerWidth: 64) && Triple.getArch() != Triple::x86_64 &&
8128 Triple.getArch() != Triple::hexagon)
8129 return;
8130
8131 SmallVector<SDValue, 8> Ops;
8132
8133 // We want to say that we always want the arguments in registers.
8134 SDValue LogEntryVal = getValue(V: I.getArgOperand(i: 0));
8135 SDValue StrSizeVal = getValue(V: I.getArgOperand(i: 1));
8136 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
8137 SDValue Chain = getRoot();
8138 Ops.push_back(Elt: LogEntryVal);
8139 Ops.push_back(Elt: StrSizeVal);
8140 Ops.push_back(Elt: Chain);
8141
8142 // We need to enforce the calling convention for the callsite, so that
8143 // argument ordering is enforced correctly, and that register allocation can
8144 // see that some registers may be assumed clobbered and have to preserve
8145 // them across calls to the intrinsic.
8146 MachineSDNode *MN = DAG.getMachineNode(Opcode: TargetOpcode::PATCHABLE_EVENT_CALL,
8147 dl: sdl, VTs: NodeTys, Ops);
8148 SDValue patchableNode = SDValue(MN, 0);
8149 DAG.setRoot(patchableNode);
8150 setValue(V: &I, NewN: patchableNode);
8151 return;
8152 }
8153 case Intrinsic::xray_typedevent: {
8154 // Here we want to make sure that the intrinsic behaves as if it has a
8155 // specific calling convention.
8156 const auto &Triple = DAG.getTarget().getTargetTriple();
8157 if (!Triple.isAArch64(PointerWidth: 64) && Triple.getArch() != Triple::x86_64 &&
8158 Triple.getArch() != Triple::hexagon)
8159 return;
8160
8161 SmallVector<SDValue, 8> Ops;
8162
8163 // We want to say that we always want the arguments in registers.
8164 // It's unclear to me how manipulating the selection DAG here forces callers
8165 // to provide arguments in registers instead of on the stack.
8166 SDValue LogTypeId = getValue(V: I.getArgOperand(i: 0));
8167 SDValue LogEntryVal = getValue(V: I.getArgOperand(i: 1));
8168 SDValue StrSizeVal = getValue(V: I.getArgOperand(i: 2));
8169 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
8170 SDValue Chain = getRoot();
8171 Ops.push_back(Elt: LogTypeId);
8172 Ops.push_back(Elt: LogEntryVal);
8173 Ops.push_back(Elt: StrSizeVal);
8174 Ops.push_back(Elt: Chain);
8175
8176 // We need to enforce the calling convention for the callsite, so that
8177 // argument ordering is enforced correctly, and that register allocation can
8178 // see that some registers may be assumed clobbered and have to preserve
8179 // them across calls to the intrinsic.
8180 MachineSDNode *MN = DAG.getMachineNode(
8181 Opcode: TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, dl: sdl, VTs: NodeTys, Ops);
8182 SDValue patchableNode = SDValue(MN, 0);
8183 DAG.setRoot(patchableNode);
8184 setValue(V: &I, NewN: patchableNode);
8185 return;
8186 }
8187 case Intrinsic::experimental_deoptimize:
8188 LowerDeoptimizeCall(CI: &I);
8189 return;
8190 case Intrinsic::stepvector:
8191 visitStepVector(I);
8192 return;
8193 case Intrinsic::vector_reduce_fadd:
8194 case Intrinsic::vector_reduce_fmul:
8195 case Intrinsic::vector_reduce_add:
8196 case Intrinsic::vector_reduce_mul:
8197 case Intrinsic::vector_reduce_and:
8198 case Intrinsic::vector_reduce_or:
8199 case Intrinsic::vector_reduce_xor:
8200 case Intrinsic::vector_reduce_smax:
8201 case Intrinsic::vector_reduce_smin:
8202 case Intrinsic::vector_reduce_umax:
8203 case Intrinsic::vector_reduce_umin:
8204 case Intrinsic::vector_reduce_fmax:
8205 case Intrinsic::vector_reduce_fmin:
8206 case Intrinsic::vector_reduce_fmaximum:
8207 case Intrinsic::vector_reduce_fminimum:
8208 case Intrinsic::vector_reduce_fmaximumnum:
8209 case Intrinsic::vector_reduce_fminimumnum:
8210 visitVectorReduce(I, Intrinsic);
8211 return;
8212
8213 case Intrinsic::icall_branch_funnel: {
8214 SmallVector<SDValue, 16> Ops;
8215 Ops.push_back(Elt: getValue(V: I.getArgOperand(i: 0)));
8216
8217 int64_t Offset;
8218 auto *Base = dyn_cast<GlobalObject>(Val: GetPointerBaseWithConstantOffset(
8219 Ptr: I.getArgOperand(i: 1), Offset, DL: DAG.getDataLayout()));
8220 if (!Base)
8221 report_fatal_error(
8222 reason: "llvm.icall.branch.funnel operand must be a GlobalValue");
8223 Ops.push_back(Elt: DAG.getTargetGlobalAddress(GV: Base, DL: sdl, VT: MVT::i64, offset: 0));
8224
8225 struct BranchFunnelTarget {
8226 int64_t Offset;
8227 SDValue Target;
8228 };
8229 SmallVector<BranchFunnelTarget, 8> Targets;
8230
8231 for (unsigned Op = 1, N = I.arg_size(); Op != N; Op += 2) {
8232 auto *ElemBase = dyn_cast<GlobalObject>(Val: GetPointerBaseWithConstantOffset(
8233 Ptr: I.getArgOperand(i: Op), Offset, DL: DAG.getDataLayout()));
8234 if (ElemBase != Base)
8235 report_fatal_error(reason: "all llvm.icall.branch.funnel operands must refer "
8236 "to the same GlobalValue");
8237
8238 SDValue Val = getValue(V: I.getArgOperand(i: Op + 1));
8239 auto *GA = dyn_cast<GlobalAddressSDNode>(Val);
8240 if (!GA)
8241 report_fatal_error(
8242 reason: "llvm.icall.branch.funnel operand must be a GlobalValue");
8243 Targets.push_back(Elt: {.Offset: Offset, .Target: DAG.getTargetGlobalAddress(
8244 GV: GA->getGlobal(), DL: sdl, VT: Val.getValueType(),
8245 offset: GA->getOffset())});
8246 }
8247 llvm::sort(C&: Targets,
8248 Comp: [](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) {
8249 return T1.Offset < T2.Offset;
8250 });
8251
8252 for (auto &T : Targets) {
8253 Ops.push_back(Elt: DAG.getTargetConstant(Val: T.Offset, DL: sdl, VT: MVT::i32));
8254 Ops.push_back(Elt: T.Target);
8255 }
8256
8257 Ops.push_back(Elt: DAG.getRoot()); // Chain
8258 SDValue N(DAG.getMachineNode(Opcode: TargetOpcode::ICALL_BRANCH_FUNNEL, dl: sdl,
8259 VT: MVT::Other, Ops),
8260 0);
8261 DAG.setRoot(N);
8262 setValue(V: &I, NewN: N);
8263 HasTailCall = true;
8264 return;
8265 }
8266
8267 case Intrinsic::wasm_landingpad_index:
8268 // Information this intrinsic contained has been transferred to
8269 // MachineFunction in SelectionDAGISel::PrepareEHLandingPad. We can safely
8270 // delete it now.
8271 return;
8272
8273 case Intrinsic::aarch64_settag:
8274 case Intrinsic::aarch64_settag_zero: {
8275 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
8276 bool ZeroMemory = Intrinsic == Intrinsic::aarch64_settag_zero;
8277 SDValue Val = TSI.EmitTargetCodeForSetTag(
8278 DAG, dl: sdl, Chain: getRoot(), Addr: getValue(V: I.getArgOperand(i: 0)),
8279 Size: getValue(V: I.getArgOperand(i: 1)), DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
8280 ZeroData: ZeroMemory);
8281 DAG.setRoot(Val);
8282 setValue(V: &I, NewN: Val);
8283 return;
8284 }
8285 case Intrinsic::amdgcn_cs_chain: {
8286 // At this point we don't care if it's amdgpu_cs_chain or
8287 // amdgpu_cs_chain_preserve.
8288 CallingConv::ID CC = CallingConv::AMDGPU_CS_Chain;
8289
8290 Type *RetTy = I.getType();
8291 assert(RetTy->isVoidTy() && "Should not return");
8292
8293 SDValue Callee = getValue(V: I.getOperand(i_nocapture: 0));
8294
8295 // We only have 2 actual args: one for the SGPRs and one for the VGPRs.
8296 // We'll also tack the value of the EXEC mask at the end.
8297 TargetLowering::ArgListTy Args;
8298 Args.reserve(n: 3);
8299
8300 for (unsigned Idx : {2, 3, 1}) {
8301 TargetLowering::ArgListEntry Arg(getValue(V: I.getOperand(i_nocapture: Idx)),
8302 I.getOperand(i_nocapture: Idx)->getType());
8303 Arg.setAttributes(Call: &I, ArgIdx: Idx);
8304 Args.push_back(x: Arg);
8305 }
8306
8307 assert(Args[0].IsInReg && "SGPR args should be marked inreg");
8308 assert(!Args[1].IsInReg && "VGPR args should not be marked inreg");
8309 Args[2].IsInReg = true; // EXEC should be inreg
8310
8311 // Forward the flags and any additional arguments.
8312 for (unsigned Idx = 4; Idx < I.arg_size(); ++Idx) {
8313 TargetLowering::ArgListEntry Arg(getValue(V: I.getOperand(i_nocapture: Idx)),
8314 I.getOperand(i_nocapture: Idx)->getType());
8315 Arg.setAttributes(Call: &I, ArgIdx: Idx);
8316 Args.push_back(x: Arg);
8317 }
8318
8319 TargetLowering::CallLoweringInfo CLI(DAG);
8320 CLI.setDebugLoc(getCurSDLoc())
8321 .setChain(getRoot())
8322 .setCallee(CC, ResultType: RetTy, Target: Callee, ArgsList: std::move(Args))
8323 .setNoReturn(true)
8324 .setTailCall(true)
8325 .setConvergent(I.isConvergent());
8326 CLI.CB = &I;
8327 std::pair<SDValue, SDValue> Result =
8328 lowerInvokable(CLI, /*EHPadBB*/ nullptr);
8329 (void)Result;
8330 assert(!Result.first.getNode() && !Result.second.getNode() &&
8331 "Should've lowered as tail call");
8332
8333 HasTailCall = true;
8334 return;
8335 }
8336 case Intrinsic::amdgcn_call_whole_wave: {
8337 TargetLowering::ArgListTy Args;
8338 bool isTailCall = I.isTailCall();
8339
8340 // The first argument is the callee. Skip it when assembling the call args.
8341 for (unsigned Idx = 1; Idx < I.arg_size(); ++Idx) {
8342 TargetLowering::ArgListEntry Arg(getValue(V: I.getArgOperand(i: Idx)),
8343 I.getArgOperand(i: Idx)->getType());
8344 Arg.setAttributes(Call: &I, ArgIdx: Idx);
8345
8346 // If we have an explicit sret argument that is an Instruction, (i.e., it
8347 // might point to function-local memory), we can't meaningfully tail-call.
8348 if (Arg.IsSRet && isa<Instruction>(Val: I.getArgOperand(i: Idx)))
8349 isTailCall = false;
8350
8351 Args.push_back(x: Arg);
8352 }
8353
8354 SDValue ConvControlToken;
8355 if (auto Bundle = I.getOperandBundle(ID: LLVMContext::OB_convergencectrl)) {
8356 auto *Token = Bundle->Inputs[0].get();
8357 ConvControlToken = getValue(V: Token);
8358 }
8359
8360 TargetLowering::CallLoweringInfo CLI(DAG);
8361 CLI.setDebugLoc(getCurSDLoc())
8362 .setChain(getRoot())
8363 .setCallee(CC: CallingConv::AMDGPU_Gfx_WholeWave, ResultType: I.getType(),
8364 Target: getValue(V: I.getArgOperand(i: 0)), ArgsList: std::move(Args))
8365 .setTailCall(isTailCall && canTailCall(CB: I))
8366 .setIsPreallocated(
8367 I.countOperandBundlesOfType(ID: LLVMContext::OB_preallocated) != 0)
8368 .setConvergent(I.isConvergent())
8369 .setConvergenceControlToken(ConvControlToken);
8370 CLI.CB = &I;
8371
8372 std::pair<SDValue, SDValue> Result =
8373 lowerInvokable(CLI, /*EHPadBB=*/nullptr);
8374
8375 if (Result.first.getNode())
8376 setValue(V: &I, NewN: Result.first);
8377 return;
8378 }
8379 case Intrinsic::ptrmask: {
8380 SDValue Ptr = getValue(V: I.getOperand(i_nocapture: 0));
8381 SDValue Mask = getValue(V: I.getOperand(i_nocapture: 1));
8382
8383 // On arm64_32, pointers are 32 bits when stored in memory, but
8384 // zero-extended to 64 bits when in registers. Thus the mask is 32 bits to
8385 // match the index type, but the pointer is 64 bits, so the mask must be
8386 // zero-extended up to 64 bits to match the pointer.
8387 EVT PtrVT =
8388 TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getOperand(i_nocapture: 0)->getType());
8389 EVT MemVT =
8390 TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getOperand(i_nocapture: 0)->getType());
8391 assert(PtrVT == Ptr.getValueType());
8392 if (Mask.getValueType().getFixedSizeInBits() < MemVT.getFixedSizeInBits()) {
8393 // For AMDGPU buffer descriptors the mask is 48 bits, but the pointer is
8394 // 128-bit, so we have to pad the mask with ones for unused bits.
8395 auto HighOnes = DAG.getNode(
8396 Opcode: ISD::SHL, DL: sdl, VT: PtrVT, N1: DAG.getAllOnesConstant(DL: sdl, VT: PtrVT),
8397 N2: DAG.getShiftAmountConstant(Val: Mask.getValueType().getFixedSizeInBits(),
8398 VT: PtrVT, DL: sdl));
8399 Mask = DAG.getNode(Opcode: ISD::OR, DL: sdl, VT: PtrVT,
8400 N1: DAG.getZExtOrTrunc(Op: Mask, DL: sdl, VT: PtrVT), N2: HighOnes);
8401 } else if (Mask.getValueType() != PtrVT)
8402 Mask = DAG.getPtrExtOrTrunc(Op: Mask, DL: sdl, VT: PtrVT);
8403
8404 assert(Mask.getValueType() == PtrVT);
8405 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::AND, DL: sdl, VT: PtrVT, N1: Ptr, N2: Mask));
8406 return;
8407 }
8408 case Intrinsic::threadlocal_address: {
8409 setValue(V: &I, NewN: getValue(V: I.getOperand(i_nocapture: 0)));
8410 return;
8411 }
8412 case Intrinsic::get_active_lane_mask: {
8413 EVT CCVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8414 SDValue Index = getValue(V: I.getOperand(i_nocapture: 0));
8415 SDValue TripCount = getValue(V: I.getOperand(i_nocapture: 1));
8416 EVT ElementVT = Index.getValueType();
8417
8418 if (!TLI.shouldExpandGetActiveLaneMask(VT: CCVT, OpVT: ElementVT)) {
8419 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::GET_ACTIVE_LANE_MASK, DL: sdl, VT: CCVT, N1: Index,
8420 N2: TripCount));
8421 return;
8422 }
8423
8424 EVT VecTy = EVT::getVectorVT(Context&: *DAG.getContext(), VT: ElementVT,
8425 EC: CCVT.getVectorElementCount());
8426
8427 SDValue VectorIndex = DAG.getSplat(VT: VecTy, DL: sdl, Op: Index);
8428 SDValue VectorTripCount = DAG.getSplat(VT: VecTy, DL: sdl, Op: TripCount);
8429 SDValue VectorStep = DAG.getStepVector(DL: sdl, ResVT: VecTy);
8430 SDValue VectorInduction = DAG.getNode(
8431 Opcode: ISD::UADDSAT, DL: sdl, VT: VecTy, N1: VectorIndex, N2: VectorStep);
8432 SDValue SetCC = DAG.getSetCC(DL: sdl, VT: CCVT, LHS: VectorInduction,
8433 RHS: VectorTripCount, Cond: ISD::CondCode::SETULT);
8434 setValue(V: &I, NewN: SetCC);
8435 return;
8436 }
8437 case Intrinsic::experimental_get_vector_length: {
8438 assert(cast<ConstantInt>(I.getOperand(1))->getSExtValue() > 0 &&
8439 "Expected positive VF");
8440 unsigned VF = cast<ConstantInt>(Val: I.getOperand(i_nocapture: 1))->getZExtValue();
8441 bool IsScalable = cast<ConstantInt>(Val: I.getOperand(i_nocapture: 2))->isOne();
8442
8443 SDValue Count = getValue(V: I.getOperand(i_nocapture: 0));
8444 EVT CountVT = Count.getValueType();
8445
8446 if (!TLI.shouldExpandGetVectorLength(CountVT, VF, IsScalable)) {
8447 visitTargetIntrinsic(I, Intrinsic);
8448 return;
8449 }
8450
8451 // Expand to a umin between the trip count and the maximum elements the type
8452 // can hold.
8453 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8454
8455 // Extend the trip count to at least the result VT.
8456 if (CountVT.bitsLT(VT)) {
8457 Count = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: sdl, VT, Operand: Count);
8458 CountVT = VT;
8459 }
8460
8461 SDValue MaxEVL = DAG.getElementCount(DL: sdl, VT: CountVT,
8462 EC: ElementCount::get(MinVal: VF, Scalable: IsScalable));
8463
8464 SDValue UMin = DAG.getNode(Opcode: ISD::UMIN, DL: sdl, VT: CountVT, N1: Count, N2: MaxEVL);
8465 // Clip to the result type if needed.
8466 SDValue Trunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: sdl, VT, Operand: UMin);
8467
8468 setValue(V: &I, NewN: Trunc);
8469 return;
8470 }
8471 case Intrinsic::vector_partial_reduce_add: {
8472 SDValue Acc = getValue(V: I.getOperand(i_nocapture: 0));
8473 SDValue Input = getValue(V: I.getOperand(i_nocapture: 1));
8474 setValue(V: &I,
8475 NewN: DAG.getNode(Opcode: ISD::PARTIAL_REDUCE_UMLA, DL: sdl, VT: Acc.getValueType(), N1: Acc,
8476 N2: Input, N3: DAG.getConstant(Val: 1, DL: sdl, VT: Input.getValueType())));
8477 return;
8478 }
8479 case Intrinsic::vector_partial_reduce_fadd: {
8480 SDValue Acc = getValue(V: I.getOperand(i_nocapture: 0));
8481 SDValue Input = getValue(V: I.getOperand(i_nocapture: 1));
8482 setValue(V: &I, NewN: DAG.getNode(
8483 Opcode: ISD::PARTIAL_REDUCE_FMLA, DL: sdl, VT: Acc.getValueType(), N1: Acc,
8484 N2: Input, N3: DAG.getConstantFP(Val: 1.0, DL: sdl, VT: Input.getValueType())));
8485 return;
8486 }
8487 case Intrinsic::experimental_cttz_elts: {
8488 SDValue Op = getValue(V: I.getOperand(i_nocapture: 0));
8489 EVT OpVT = Op.getValueType();
8490 EVT RetTy = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8491 bool ZeroIsPoison =
8492 !cast<ConstantSDNode>(Val: getValue(V: I.getOperand(i_nocapture: 1)))->isZero();
8493 if (OpVT.getVectorElementType() != MVT::i1) {
8494 // Compare the input vector elements to zero & use to count trailing
8495 // zeros.
8496 SDValue AllZero = DAG.getConstant(Val: 0, DL: sdl, VT: OpVT);
8497 EVT I1OpVT = OpVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MVT::i1);
8498 Op = DAG.getSetCC(DL: sdl, VT: I1OpVT, LHS: Op, RHS: AllZero, Cond: ISD::SETNE);
8499 }
8500 setValue(V: &I, NewN: DAG.getNode(Opcode: ZeroIsPoison ? ISD::CTTZ_ELTS_ZERO_POISON
8501 : ISD::CTTZ_ELTS,
8502 DL: sdl, VT: RetTy, Operand: Op));
8503 return;
8504 }
8505 case Intrinsic::vector_insert: {
8506 SDValue Vec = getValue(V: I.getOperand(i_nocapture: 0));
8507 SDValue SubVec = getValue(V: I.getOperand(i_nocapture: 1));
8508 SDValue Index = getValue(V: I.getOperand(i_nocapture: 2));
8509
8510 // The intrinsic's index type is i64, but the SDNode requires an index type
8511 // suitable for the target. Convert the index as required.
8512 MVT VectorIdxTy = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
8513 if (Index.getValueType() != VectorIdxTy)
8514 Index = DAG.getVectorIdxConstant(Val: Index->getAsZExtVal(), DL: sdl);
8515
8516 EVT ResultVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8517 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: sdl, VT: ResultVT, N1: Vec, N2: SubVec,
8518 N3: Index));
8519 return;
8520 }
8521 case Intrinsic::vector_extract: {
8522 SDValue Vec = getValue(V: I.getOperand(i_nocapture: 0));
8523 SDValue Index = getValue(V: I.getOperand(i_nocapture: 1));
8524 EVT ResultVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8525
8526 // The intrinsic's index type is i64, but the SDNode requires an index type
8527 // suitable for the target. Convert the index as required.
8528 MVT VectorIdxTy = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
8529 if (Index.getValueType() != VectorIdxTy)
8530 Index = DAG.getVectorIdxConstant(Val: Index->getAsZExtVal(), DL: sdl);
8531
8532 setValue(V: &I,
8533 NewN: DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: sdl, VT: ResultVT, N1: Vec, N2: Index));
8534 return;
8535 }
8536 case Intrinsic::experimental_vector_match: {
8537 SDValue Op1 = getValue(V: I.getOperand(i_nocapture: 0));
8538 SDValue Op2 = getValue(V: I.getOperand(i_nocapture: 1));
8539 SDValue Mask = getValue(V: I.getOperand(i_nocapture: 2));
8540 EVT ResVT = Mask.getValueType();
8541 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::VECTOR_MATCH, DL: sdl, VT: ResVT, N1: Op1, N2: Op2, N3: Mask));
8542 return;
8543 }
8544 case Intrinsic::vector_reverse:
8545 visitVectorReverse(I);
8546 return;
8547 case Intrinsic::vector_splice_left:
8548 case Intrinsic::vector_splice_right:
8549 visitVectorSplice(I);
8550 return;
8551 case Intrinsic::callbr_landingpad:
8552 visitCallBrLandingPad(I);
8553 return;
8554 case Intrinsic::vector_interleave2:
8555 visitVectorInterleave(I, Factor: 2);
8556 return;
8557 case Intrinsic::vector_interleave3:
8558 visitVectorInterleave(I, Factor: 3);
8559 return;
8560 case Intrinsic::vector_interleave4:
8561 visitVectorInterleave(I, Factor: 4);
8562 return;
8563 case Intrinsic::vector_interleave5:
8564 visitVectorInterleave(I, Factor: 5);
8565 return;
8566 case Intrinsic::vector_interleave6:
8567 visitVectorInterleave(I, Factor: 6);
8568 return;
8569 case Intrinsic::vector_interleave7:
8570 visitVectorInterleave(I, Factor: 7);
8571 return;
8572 case Intrinsic::vector_interleave8:
8573 visitVectorInterleave(I, Factor: 8);
8574 return;
8575 case Intrinsic::vector_deinterleave2:
8576 visitVectorDeinterleave(I, Factor: 2);
8577 return;
8578 case Intrinsic::vector_deinterleave3:
8579 visitVectorDeinterleave(I, Factor: 3);
8580 return;
8581 case Intrinsic::vector_deinterleave4:
8582 visitVectorDeinterleave(I, Factor: 4);
8583 return;
8584 case Intrinsic::vector_deinterleave5:
8585 visitVectorDeinterleave(I, Factor: 5);
8586 return;
8587 case Intrinsic::vector_deinterleave6:
8588 visitVectorDeinterleave(I, Factor: 6);
8589 return;
8590 case Intrinsic::vector_deinterleave7:
8591 visitVectorDeinterleave(I, Factor: 7);
8592 return;
8593 case Intrinsic::vector_deinterleave8:
8594 visitVectorDeinterleave(I, Factor: 8);
8595 return;
8596 case Intrinsic::experimental_vector_compress:
8597 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: sdl,
8598 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
8599 N1: getValue(V: I.getArgOperand(i: 0)),
8600 N2: getValue(V: I.getArgOperand(i: 1)),
8601 N3: getValue(V: I.getArgOperand(i: 2)), Flags));
8602 return;
8603 case Intrinsic::experimental_convergence_anchor:
8604 case Intrinsic::experimental_convergence_entry:
8605 case Intrinsic::experimental_convergence_loop:
8606 visitConvergenceControl(I, Intrinsic);
8607 return;
8608 case Intrinsic::experimental_vector_histogram_add: {
8609 visitVectorHistogram(I, IntrinsicID: Intrinsic);
8610 return;
8611 }
8612 case Intrinsic::experimental_vector_extract_last_active: {
8613 visitVectorExtractLastActive(I, Intrinsic);
8614 return;
8615 }
8616 case Intrinsic::loop_dependence_war_mask:
8617 setValue(V: &I,
8618 NewN: DAG.getNode(Opcode: ISD::LOOP_DEPENDENCE_WAR_MASK, DL: sdl,
8619 VT: EVT::getEVT(Ty: I.getType()), N1: getValue(V: I.getOperand(i_nocapture: 0)),
8620 N2: getValue(V: I.getOperand(i_nocapture: 1)), N3: getValue(V: I.getOperand(i_nocapture: 2)),
8621 N4: DAG.getConstant(Val: 0, DL: sdl, VT: MVT::i64)));
8622 return;
8623 case Intrinsic::loop_dependence_raw_mask:
8624 setValue(V: &I,
8625 NewN: DAG.getNode(Opcode: ISD::LOOP_DEPENDENCE_RAW_MASK, DL: sdl,
8626 VT: EVT::getEVT(Ty: I.getType()), N1: getValue(V: I.getOperand(i_nocapture: 0)),
8627 N2: getValue(V: I.getOperand(i_nocapture: 1)), N3: getValue(V: I.getOperand(i_nocapture: 2)),
8628 N4: DAG.getConstant(Val: 0, DL: sdl, VT: MVT::i64)));
8629 return;
8630 case Intrinsic::masked_udiv:
8631 setValue(V: &I,
8632 NewN: DAG.getNode(Opcode: ISD::MASKED_UDIV, DL: sdl, VT: EVT::getEVT(Ty: I.getType()),
8633 N1: getValue(V: I.getOperand(i_nocapture: 0)), N2: getValue(V: I.getOperand(i_nocapture: 1)),
8634 N3: getValue(V: I.getOperand(i_nocapture: 2))));
8635 return;
8636 case Intrinsic::masked_sdiv:
8637 setValue(V: &I,
8638 NewN: DAG.getNode(Opcode: ISD::MASKED_SDIV, DL: sdl, VT: EVT::getEVT(Ty: I.getType()),
8639 N1: getValue(V: I.getOperand(i_nocapture: 0)), N2: getValue(V: I.getOperand(i_nocapture: 1)),
8640 N3: getValue(V: I.getOperand(i_nocapture: 2))));
8641 return;
8642 case Intrinsic::masked_urem:
8643 setValue(V: &I,
8644 NewN: DAG.getNode(Opcode: ISD::MASKED_UREM, DL: sdl, VT: EVT::getEVT(Ty: I.getType()),
8645 N1: getValue(V: I.getOperand(i_nocapture: 0)), N2: getValue(V: I.getOperand(i_nocapture: 1)),
8646 N3: getValue(V: I.getOperand(i_nocapture: 2))));
8647 return;
8648 case Intrinsic::masked_srem:
8649 setValue(V: &I,
8650 NewN: DAG.getNode(Opcode: ISD::MASKED_SREM, DL: sdl, VT: EVT::getEVT(Ty: I.getType()),
8651 N1: getValue(V: I.getOperand(i_nocapture: 0)), N2: getValue(V: I.getOperand(i_nocapture: 1)),
8652 N3: getValue(V: I.getOperand(i_nocapture: 2))));
8653 return;
8654 }
8655}
8656
8657void SelectionDAGBuilder::pushFPOpOutChain(SDValue Result,
8658 fp::ExceptionBehavior EB) {
8659 assert(Result.getNode()->getNumValues() == 2);
8660 SDValue OutChain = Result.getValue(R: 1);
8661 assert(OutChain.getValueType() == MVT::Other);
8662
8663 // Instead of updating the root immediately, push the produced chain to the
8664 // appropriate list, deferring the update until the root is requested. In this
8665 // case, the nodes from the lists are chained using TokenFactor, indicating
8666 // that the operations are independent.
8667 //
8668 // In particular, the root is updated before any call that might access the
8669 // floating-point environment, except for constrained intrinsics.
8670 switch (EB) {
8671 case fp::ExceptionBehavior::ebMayTrap:
8672 case fp::ExceptionBehavior::ebIgnore:
8673 PendingConstrainedFP.push_back(Elt: OutChain);
8674 break;
8675 case fp::ExceptionBehavior::ebStrict:
8676 PendingConstrainedFPStrict.push_back(Elt: OutChain);
8677 break;
8678 }
8679}
8680
8681void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
8682 const ConstrainedFPIntrinsic &FPI) {
8683 SDLoc sdl = getCurSDLoc();
8684
8685 // We do not need to serialize constrained FP intrinsics against
8686 // each other or against (nonvolatile) loads, so they can be
8687 // chained like loads.
8688 fp::ExceptionBehavior EB = *FPI.getExceptionBehavior();
8689 SDValue Chain = getFPOperationRoot(EB);
8690 SmallVector<SDValue, 4> Opers;
8691 Opers.push_back(Elt: Chain);
8692 for (unsigned I = 0, E = FPI.getNonMetadataArgCount(); I != E; ++I)
8693 Opers.push_back(Elt: getValue(V: FPI.getArgOperand(i: I)));
8694
8695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8696 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: FPI.getType());
8697 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::Other);
8698
8699 SDNodeFlags Flags;
8700 if (EB == fp::ExceptionBehavior::ebIgnore)
8701 Flags.setNoFPExcept(true);
8702
8703 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &FPI))
8704 Flags.copyFMF(FPMO: *FPOp);
8705
8706 unsigned Opcode;
8707 switch (FPI.getIntrinsicID()) {
8708 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
8709#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
8710 case Intrinsic::INTRINSIC: \
8711 Opcode = ISD::STRICT_##DAGN; \
8712 break;
8713#include "llvm/IR/ConstrainedOps.def"
8714 case Intrinsic::experimental_constrained_fmuladd: {
8715 Opcode = ISD::STRICT_FMA;
8716 // Break fmuladd into fmul and fadd.
8717 if (TM.Options.AllowFPOpFusion == FPOpFusion::Strict ||
8718 !TLI.isFMAFasterThanFMulAndFAdd(MF: DAG.getMachineFunction(), VT)) {
8719 Opers.pop_back();
8720 SDValue Mul = DAG.getNode(Opcode: ISD::STRICT_FMUL, DL: sdl, VTList: VTs, Ops: Opers, Flags);
8721 pushFPOpOutChain(Result: Mul, EB);
8722 Opcode = ISD::STRICT_FADD;
8723 Opers.clear();
8724 Opers.push_back(Elt: Mul.getValue(R: 1));
8725 Opers.push_back(Elt: Mul.getValue(R: 0));
8726 Opers.push_back(Elt: getValue(V: FPI.getArgOperand(i: 2)));
8727 }
8728 break;
8729 }
8730 }
8731
8732 // A few strict DAG nodes carry additional operands that are not
8733 // set up by the default code above.
8734 switch (Opcode) {
8735 default: break;
8736 case ISD::STRICT_FP_ROUND:
8737 Opers.push_back(
8738 Elt: DAG.getTargetConstant(Val: 0, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
8739 break;
8740 case ISD::STRICT_FSETCC:
8741 case ISD::STRICT_FSETCCS: {
8742 auto *FPCmp = dyn_cast<ConstrainedFPCmpIntrinsic>(Val: &FPI);
8743 ISD::CondCode Condition = getFCmpCondCode(Pred: FPCmp->getPredicate());
8744 if (DAG.isKnownNeverNaN(Op: Opers[1]) && DAG.isKnownNeverNaN(Op: Opers[2]))
8745 Condition = getFCmpCodeWithoutNaN(CC: Condition);
8746 Opers.push_back(Elt: DAG.getCondCode(Cond: Condition));
8747 break;
8748 }
8749 }
8750
8751 SDValue Result = DAG.getNode(Opcode, DL: sdl, VTList: VTs, Ops: Opers, Flags);
8752 pushFPOpOutChain(Result, EB);
8753
8754 SDValue FPResult = Result.getValue(R: 0);
8755 setValue(V: &FPI, NewN: FPResult);
8756}
8757
8758static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) {
8759 std::optional<unsigned> ResOPC;
8760 switch (VPIntrin.getIntrinsicID()) {
8761 case Intrinsic::vp_cttz_elts: {
8762 bool IsZeroPoison = cast<ConstantInt>(Val: VPIntrin.getArgOperand(i: 1))->isOne();
8763 ResOPC = IsZeroPoison ? ISD::VP_CTTZ_ELTS_ZERO_POISON : ISD::VP_CTTZ_ELTS;
8764 break;
8765 }
8766#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
8767 case Intrinsic::VPID: \
8768 ResOPC = ISD::VPSD; \
8769 break;
8770#include "llvm/IR/VPIntrinsics.def"
8771 }
8772
8773 if (!ResOPC)
8774 llvm_unreachable(
8775 "Inconsistency: no SDNode available for this VPIntrinsic!");
8776
8777 if (*ResOPC == ISD::VP_REDUCE_SEQ_FADD ||
8778 *ResOPC == ISD::VP_REDUCE_SEQ_FMUL) {
8779 if (VPIntrin.getFastMathFlags().allowReassoc())
8780 return *ResOPC == ISD::VP_REDUCE_SEQ_FADD ? ISD::VP_REDUCE_FADD
8781 : ISD::VP_REDUCE_FMUL;
8782 }
8783
8784 return *ResOPC;
8785}
8786
8787void SelectionDAGBuilder::visitVPLoad(
8788 const VPIntrinsic &VPIntrin, EVT VT,
8789 const SmallVectorImpl<SDValue> &OpValues) {
8790 SDLoc DL = getCurSDLoc();
8791 Value *PtrOperand = VPIntrin.getArgOperand(i: 0);
8792 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8793 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8794 const MDNode *Ranges = getRangeMetadata(I: VPIntrin);
8795 SDValue LD;
8796 // Do not serialize variable-length loads of constant memory with
8797 // anything.
8798 if (!Alignment)
8799 Alignment = DAG.getEVTAlign(MemoryVT: VT);
8800 MemoryLocation ML = MemoryLocation::getAfter(Ptr: PtrOperand, AATags: AAInfo);
8801 bool AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(Loc: ML);
8802 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
8803 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8804 MachineMemOperand::Flags MMOFlags =
8805 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8806 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8807 PtrInfo: MachinePointerInfo(PtrOperand), F: MMOFlags,
8808 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: *Alignment,
8809 Metadata: MMOMetadata(AAInfo, Ranges));
8810 LD = DAG.getLoadVP(VT, dl: DL, Chain: InChain, Ptr: OpValues[0], Mask: OpValues[1], EVL: OpValues[2],
8811 MMO, IsExpanding: false /*IsExpanding */);
8812 if (AddToChain)
8813 PendingLoads.push_back(Elt: LD.getValue(R: 1));
8814 setValue(V: &VPIntrin, NewN: LD);
8815}
8816
8817void SelectionDAGBuilder::visitVPLoadFF(
8818 const VPIntrinsic &VPIntrin, EVT VT, EVT EVLVT,
8819 const SmallVectorImpl<SDValue> &OpValues) {
8820 assert(OpValues.size() == 3 && "Unexpected number of operands");
8821 SDLoc DL = getCurSDLoc();
8822 Value *PtrOperand = VPIntrin.getArgOperand(i: 0);
8823 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8824 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8825 const MDNode *Ranges = VPIntrin.getMetadata(KindID: LLVMContext::MD_range);
8826 SDValue LD;
8827 // Do not serialize variable-length loads of constant memory with
8828 // anything.
8829 if (!Alignment)
8830 Alignment = DAG.getEVTAlign(MemoryVT: VT);
8831 MemoryLocation ML = MemoryLocation::getAfter(Ptr: PtrOperand, AATags: AAInfo);
8832 bool AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(Loc: ML);
8833 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
8834 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8835 PtrInfo: MachinePointerInfo(PtrOperand), F: MachineMemOperand::MOLoad,
8836 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: *Alignment,
8837 Metadata: MMOMetadata(AAInfo, Ranges));
8838 LD = DAG.getLoadFFVP(VT, DL, Chain: InChain, Ptr: OpValues[0], Mask: OpValues[1], EVL: OpValues[2],
8839 MMO);
8840 SDValue Trunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: EVLVT, Operand: LD.getValue(R: 1));
8841 if (AddToChain)
8842 PendingLoads.push_back(Elt: LD.getValue(R: 2));
8843 setValue(V: &VPIntrin, NewN: DAG.getMergeValues(Ops: {LD.getValue(R: 0), Trunc}, dl: DL));
8844}
8845
8846void SelectionDAGBuilder::visitVPGather(
8847 const VPIntrinsic &VPIntrin, EVT VT,
8848 const SmallVectorImpl<SDValue> &OpValues) {
8849 SDLoc DL = getCurSDLoc();
8850 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8851 Value *PtrOperand = VPIntrin.getArgOperand(i: 0);
8852 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8853 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8854 const MDNode *Ranges = getRangeMetadata(I: VPIntrin);
8855 SDValue LD;
8856 if (!Alignment)
8857 Alignment = DAG.getEVTAlign(MemoryVT: VT.getScalarType());
8858 unsigned AS =
8859 PtrOperand->getType()->getScalarType()->getPointerAddressSpace();
8860 MachineMemOperand::Flags MMOFlags =
8861 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8862 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8863 PtrInfo: MachinePointerInfo(AS), F: MMOFlags, Size: LocationSize::beforeOrAfterPointer(),
8864 BaseAlignment: *Alignment, Metadata: MMOMetadata(AAInfo, Ranges));
8865 SDValue Base, Index, Scale;
8866 bool UniformBase =
8867 getUniformBase(Ptr: PtrOperand, Base, Index, Scale, SDB: this, CurBB: VPIntrin.getParent(),
8868 ElemSize: VT.getScalarStoreSize());
8869 if (!UniformBase) {
8870 Base = DAG.getConstant(Val: 0, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
8871 Index = getValue(V: PtrOperand);
8872 Scale = DAG.getTargetConstant(Val: 1, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
8873 }
8874 EVT IdxVT = Index.getValueType();
8875 EVT EltTy = IdxVT.getVectorElementType();
8876 if (TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
8877 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
8878 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: NewIdxVT, Operand: Index);
8879 }
8880 LD = DAG.getGatherVP(
8881 VTs: DAG.getVTList(VT1: VT, VT2: MVT::Other), VT, dl: DL,
8882 Ops: {DAG.getRoot(), Base, Index, Scale, OpValues[1], OpValues[2]}, MMO,
8883 IndexType: ISD::SIGNED_SCALED);
8884 PendingLoads.push_back(Elt: LD.getValue(R: 1));
8885 setValue(V: &VPIntrin, NewN: LD);
8886}
8887
8888void SelectionDAGBuilder::visitVPStore(
8889 const VPIntrinsic &VPIntrin, const SmallVectorImpl<SDValue> &OpValues) {
8890 SDLoc DL = getCurSDLoc();
8891 Value *PtrOperand = VPIntrin.getArgOperand(i: 1);
8892 EVT VT = OpValues[0].getValueType();
8893 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8894 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8895 SDValue ST;
8896 if (!Alignment)
8897 Alignment = DAG.getEVTAlign(MemoryVT: VT);
8898 SDValue Ptr = OpValues[1];
8899 SDValue Offset = DAG.getPOISON(VT: Ptr.getValueType());
8900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8901 MachineMemOperand::Flags MMOFlags =
8902 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8903 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8904 PtrInfo: MachinePointerInfo(PtrOperand), F: MMOFlags,
8905 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: *Alignment, Metadata: AAInfo);
8906 ST = DAG.getStoreVP(Chain: getMemoryRoot(), dl: DL, Val: OpValues[0], Ptr, Offset,
8907 Mask: OpValues[2], EVL: OpValues[3], MemVT: VT, MMO, AM: ISD::UNINDEXED,
8908 /* IsTruncating */ false, /*IsCompressing*/ false);
8909 DAG.setRoot(ST);
8910 setValue(V: &VPIntrin, NewN: ST);
8911}
8912
8913void SelectionDAGBuilder::visitVPScatter(
8914 const VPIntrinsic &VPIntrin, const SmallVectorImpl<SDValue> &OpValues) {
8915 SDLoc DL = getCurSDLoc();
8916 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8917 Value *PtrOperand = VPIntrin.getArgOperand(i: 1);
8918 EVT VT = OpValues[0].getValueType();
8919 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8920 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8921 SDValue ST;
8922 if (!Alignment)
8923 Alignment = DAG.getEVTAlign(MemoryVT: VT.getScalarType());
8924 unsigned AS =
8925 PtrOperand->getType()->getScalarType()->getPointerAddressSpace();
8926 MachineMemOperand::Flags MMOFlags =
8927 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8928 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8929 PtrInfo: MachinePointerInfo(AS), F: MMOFlags, Size: LocationSize::beforeOrAfterPointer(),
8930 BaseAlignment: *Alignment, Metadata: AAInfo);
8931 SDValue Base, Index, Scale;
8932 bool UniformBase =
8933 getUniformBase(Ptr: PtrOperand, Base, Index, Scale, SDB: this, CurBB: VPIntrin.getParent(),
8934 ElemSize: VT.getScalarStoreSize());
8935 if (!UniformBase) {
8936 Base = DAG.getConstant(Val: 0, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
8937 Index = getValue(V: PtrOperand);
8938 Scale = DAG.getTargetConstant(Val: 1, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
8939 }
8940 EVT IdxVT = Index.getValueType();
8941 EVT EltTy = IdxVT.getVectorElementType();
8942 if (TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
8943 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
8944 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: NewIdxVT, Operand: Index);
8945 }
8946 ST = DAG.getScatterVP(VTs: DAG.getVTList(VT: MVT::Other), VT, dl: DL,
8947 Ops: {getMemoryRoot(), OpValues[0], Base, Index, Scale,
8948 OpValues[2], OpValues[3]},
8949 MMO, IndexType: ISD::SIGNED_SCALED);
8950 DAG.setRoot(ST);
8951 setValue(V: &VPIntrin, NewN: ST);
8952}
8953
8954void SelectionDAGBuilder::visitVPStridedLoad(
8955 const VPIntrinsic &VPIntrin, EVT VT,
8956 const SmallVectorImpl<SDValue> &OpValues) {
8957 SDLoc DL = getCurSDLoc();
8958 Value *PtrOperand = VPIntrin.getArgOperand(i: 0);
8959 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8960 if (!Alignment)
8961 Alignment = DAG.getEVTAlign(MemoryVT: VT.getScalarType());
8962 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8963 const MDNode *Ranges = getRangeMetadata(I: VPIntrin);
8964 MemoryLocation ML = MemoryLocation::getAfter(Ptr: PtrOperand, AATags: AAInfo);
8965 bool AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(Loc: ML);
8966 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
8967 unsigned AS = PtrOperand->getType()->getPointerAddressSpace();
8968 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8969 MachineMemOperand::Flags MMOFlags =
8970 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8971 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8972 PtrInfo: MachinePointerInfo(AS), F: MMOFlags, Size: LocationSize::beforeOrAfterPointer(),
8973 BaseAlignment: *Alignment, Metadata: MMOMetadata(AAInfo, Ranges));
8974
8975 SDValue LD = DAG.getStridedLoadVP(VT, DL, Chain: InChain, Ptr: OpValues[0], Stride: OpValues[1],
8976 Mask: OpValues[2], EVL: OpValues[3], MMO,
8977 IsExpanding: false /*IsExpanding*/);
8978
8979 if (AddToChain)
8980 PendingLoads.push_back(Elt: LD.getValue(R: 1));
8981 setValue(V: &VPIntrin, NewN: LD);
8982}
8983
8984void SelectionDAGBuilder::visitVPStridedStore(
8985 const VPIntrinsic &VPIntrin, const SmallVectorImpl<SDValue> &OpValues) {
8986 SDLoc DL = getCurSDLoc();
8987 Value *PtrOperand = VPIntrin.getArgOperand(i: 1);
8988 EVT VT = OpValues[0].getValueType();
8989 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8990 if (!Alignment)
8991 Alignment = DAG.getEVTAlign(MemoryVT: VT.getScalarType());
8992 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8993 unsigned AS = PtrOperand->getType()->getPointerAddressSpace();
8994 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8995 MachineMemOperand::Flags MMOFlags =
8996 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8997 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8998 PtrInfo: MachinePointerInfo(AS), F: MMOFlags, Size: LocationSize::beforeOrAfterPointer(),
8999 BaseAlignment: *Alignment, Metadata: AAInfo);
9000
9001 SDValue ST = DAG.getStridedStoreVP(
9002 Chain: getMemoryRoot(), DL, Val: OpValues[0], Ptr: OpValues[1],
9003 Offset: DAG.getPOISON(VT: OpValues[1].getValueType()), Stride: OpValues[2], Mask: OpValues[3],
9004 EVL: OpValues[4], MemVT: VT, MMO, AM: ISD::UNINDEXED, /*IsTruncating*/ false,
9005 /*IsCompressing*/ false);
9006
9007 DAG.setRoot(ST);
9008 setValue(V: &VPIntrin, NewN: ST);
9009}
9010
9011void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
9012 const VPIntrinsic &VPIntrin) {
9013 SDLoc DL = getCurSDLoc();
9014 unsigned Opcode = getISDForVPIntrinsic(VPIntrin);
9015
9016 auto IID = VPIntrin.getIntrinsicID();
9017
9018 SmallVector<EVT, 4> ValueVTs;
9019 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9020 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: VPIntrin.getType(), ValueVTs);
9021 SDVTList VTs = DAG.getVTList(VTs: ValueVTs);
9022
9023 auto EVLParamPos = VPIntrinsic::getVectorLengthParamPos(IntrinsicID: IID);
9024
9025 MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy();
9026 assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) &&
9027 "Unexpected target EVL type");
9028
9029 // Request operands.
9030 SmallVector<SDValue, 7> OpValues;
9031 for (unsigned I = 0; I < VPIntrin.arg_size(); ++I) {
9032 auto Op = getValue(V: VPIntrin.getArgOperand(i: I));
9033 if (I == EVLParamPos)
9034 Op = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: EVLParamVT, Operand: Op);
9035 OpValues.push_back(Elt: Op);
9036 }
9037
9038 switch (Opcode) {
9039 default: {
9040 SDNodeFlags SDFlags;
9041 if (auto *FPMO = dyn_cast<FPMathOperator>(Val: &VPIntrin))
9042 SDFlags.copyFMF(FPMO: *FPMO);
9043 SDValue Result = DAG.getNode(Opcode, DL, VTList: VTs, Ops: OpValues, Flags: SDFlags);
9044 setValue(V: &VPIntrin, NewN: Result);
9045 break;
9046 }
9047 case ISD::VP_LOAD:
9048 visitVPLoad(VPIntrin, VT: ValueVTs[0], OpValues);
9049 break;
9050 case ISD::VP_LOAD_FF:
9051 visitVPLoadFF(VPIntrin, VT: ValueVTs[0], EVLVT: ValueVTs[1], OpValues);
9052 break;
9053 case ISD::VP_GATHER:
9054 visitVPGather(VPIntrin, VT: ValueVTs[0], OpValues);
9055 break;
9056 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
9057 visitVPStridedLoad(VPIntrin, VT: ValueVTs[0], OpValues);
9058 break;
9059 case ISD::VP_STORE:
9060 visitVPStore(VPIntrin, OpValues);
9061 break;
9062 case ISD::VP_SCATTER:
9063 visitVPScatter(VPIntrin, OpValues);
9064 break;
9065 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
9066 visitVPStridedStore(VPIntrin, OpValues);
9067 break;
9068 case ISD::VP_CTTZ_ELTS_ZERO_POISON:
9069 case ISD::VP_CTTZ_ELTS: {
9070 SDValue Result =
9071 DAG.getNode(Opcode, DL, VTList: VTs, Ops: {OpValues[0], OpValues[2], OpValues[3]});
9072 setValue(V: &VPIntrin, NewN: Result);
9073 break;
9074 }
9075 }
9076}
9077
9078SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain,
9079 const BasicBlock *EHPadBB,
9080 MCSymbol *&BeginLabel) {
9081 MachineFunction &MF = DAG.getMachineFunction();
9082
9083 // Insert a label before the invoke call to mark the try range. This can be
9084 // used to detect deletion of the invoke via the MachineModuleInfo.
9085 BeginLabel = MF.getContext().createTempSymbol();
9086
9087 // For SjLj, keep track of which landing pads go with which invokes
9088 // so as to maintain the ordering of pads in the LSDA.
9089 unsigned CallSiteIndex = FuncInfo.getCurrentCallSite();
9090 if (CallSiteIndex) {
9091 MF.setCallSiteBeginLabel(BeginLabel, Site: CallSiteIndex);
9092 LPadToCallSiteMap[FuncInfo.getMBB(BB: EHPadBB)].push_back(Elt: CallSiteIndex);
9093
9094 // Now that the call site is handled, stop tracking it.
9095 FuncInfo.setCurrentCallSite(0);
9096 }
9097
9098 return DAG.getEHLabel(dl: getCurSDLoc(), Root: Chain, Label: BeginLabel);
9099}
9100
9101SDValue SelectionDAGBuilder::lowerEndEH(SDValue Chain, const InvokeInst *II,
9102 const BasicBlock *EHPadBB,
9103 MCSymbol *BeginLabel) {
9104 assert(BeginLabel && "BeginLabel should've been set");
9105
9106 MachineFunction &MF = DAG.getMachineFunction();
9107
9108 // Insert a label at the end of the invoke call to mark the try range. This
9109 // can be used to detect deletion of the invoke via the MachineModuleInfo.
9110 MCSymbol *EndLabel = MF.getContext().createTempSymbol();
9111 Chain = DAG.getEHLabel(dl: getCurSDLoc(), Root: Chain, Label: EndLabel);
9112
9113 // Inform MachineModuleInfo of range.
9114 auto Pers = classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
9115 // There is a platform (e.g. wasm) that uses funclet style IR but does not
9116 // actually use outlined funclets and their LSDA info style.
9117 if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) {
9118 assert(II && "II should've been set");
9119 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
9120 EHInfo->addIPToStateRange(II, InvokeBegin: BeginLabel, InvokeEnd: EndLabel);
9121 } else if (!isScopedEHPersonality(Pers)) {
9122 assert(EHPadBB);
9123 MF.addInvoke(LandingPad: FuncInfo.getMBB(BB: EHPadBB), BeginLabel, EndLabel);
9124 }
9125
9126 return Chain;
9127}
9128
9129std::pair<SDValue, SDValue>
9130SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
9131 const BasicBlock *EHPadBB) {
9132 MCSymbol *BeginLabel = nullptr;
9133
9134 if (EHPadBB) {
9135 // Both PendingLoads and PendingExports must be flushed here;
9136 // this call might not return.
9137 (void)getRoot();
9138 DAG.setRoot(lowerStartEH(Chain: getControlRoot(), EHPadBB, BeginLabel));
9139 CLI.setChain(getRoot());
9140 }
9141
9142 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9143 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
9144
9145 assert((CLI.IsTailCall || Result.second.getNode()) &&
9146 "Non-null chain expected with non-tail call!");
9147 assert((Result.second.getNode() || !Result.first.getNode()) &&
9148 "Null value expected with tail call!");
9149
9150 if (!Result.second.getNode()) {
9151 // As a special case, a null chain means that a tail call has been emitted
9152 // and the DAG root is already updated.
9153 HasTailCall = true;
9154
9155 // Since there's no actual continuation from this block, nothing can be
9156 // relying on us setting vregs for them.
9157 PendingExports.clear();
9158 } else {
9159 DAG.setRoot(Result.second);
9160 }
9161
9162 if (EHPadBB) {
9163 DAG.setRoot(lowerEndEH(Chain: getRoot(), II: cast_or_null<InvokeInst>(Val: CLI.CB), EHPadBB,
9164 BeginLabel));
9165 Result.second = getRoot();
9166 }
9167
9168 return Result;
9169}
9170
9171bool SelectionDAGBuilder::canTailCall(const CallBase &CB) const {
9172 bool isMustTailCall = CB.isMustTailCall();
9173
9174 // Avoid emitting tail calls in functions with the disable-tail-calls
9175 // attribute.
9176 const Function *Caller = CB.getParent()->getParent();
9177 if (!isMustTailCall &&
9178 Caller->getFnAttribute(Kind: "disable-tail-calls").getValueAsBool())
9179 return false;
9180
9181 // We can't tail call inside a function with a swifterror argument. Lowering
9182 // does not support this yet. It would have to move into the swifterror
9183 // register before the call.
9184 if (DAG.hasSwiftErrorArg())
9185 return false;
9186
9187 // Check if target-independent constraints permit a tail call here.
9188 // Target-dependent constraints are checked within TLI->LowerCallTo.
9189 return isInTailCallPosition(Call: CB, TM: DAG.getTarget());
9190}
9191
9192void SelectionDAGBuilder::LowerCallTo(const CallBase &CB, SDValue Callee,
9193 bool isTailCall, bool isMustTailCall,
9194 const BasicBlock *EHPadBB,
9195 const TargetLowering::PtrAuthInfo *PAI) {
9196 auto &DL = DAG.getDataLayout();
9197 FunctionType *FTy = CB.getFunctionType();
9198 Type *RetTy = CB.getType();
9199
9200 TargetLowering::ArgListTy Args;
9201 Args.reserve(n: CB.arg_size());
9202
9203 const Value *SwiftErrorVal = nullptr;
9204 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9205
9206 if (isTailCall)
9207 isTailCall = canTailCall(CB);
9208
9209 for (auto I = CB.arg_begin(), E = CB.arg_end(); I != E; ++I) {
9210 const Value *V = *I;
9211
9212 // Skip empty types
9213 if (V->getType()->isEmptyTy())
9214 continue;
9215
9216 SDValue ArgNode = getValue(V);
9217 TargetLowering::ArgListEntry Entry(ArgNode, V->getType());
9218 Entry.setAttributes(Call: &CB, ArgIdx: I - CB.arg_begin());
9219
9220 // Use swifterror virtual register as input to the call.
9221 if (Entry.IsSwiftError && TLI.supportSwiftError()) {
9222 SwiftErrorVal = V;
9223 // We find the virtual register for the actual swifterror argument.
9224 // Instead of using the Value, we use the virtual register instead.
9225 Entry.Node =
9226 DAG.getRegister(Reg: SwiftError.getOrCreateVRegUseAt(&CB, FuncInfo.MBB, V),
9227 VT: EVT(TLI.getPointerTy(DL)));
9228 }
9229
9230 Args.push_back(x: Entry);
9231
9232 // If we have an explicit sret argument that is an Instruction, (i.e., it
9233 // might point to function-local memory), we can't meaningfully tail-call.
9234 if (Entry.IsSRet && isa<Instruction>(Val: V))
9235 isTailCall = false;
9236 }
9237
9238 // If call site has a cfguardtarget operand bundle, create and add an
9239 // additional ArgListEntry.
9240 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_cfguardtarget)) {
9241 Value *V = Bundle->Inputs[0];
9242 TargetLowering::ArgListEntry Entry(V, getValue(V));
9243 Entry.IsCFGuardTarget = true;
9244 Args.push_back(x: Entry);
9245 }
9246
9247 // Disable tail calls if there is an swifterror argument. Targets have not
9248 // been updated to support tail calls.
9249 if (TLI.supportSwiftError() && SwiftErrorVal)
9250 isTailCall = false;
9251
9252 ConstantInt *CFIType = nullptr;
9253 if (CB.isIndirectCall()) {
9254 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_kcfi)) {
9255 if (!TLI.supportKCFIBundles())
9256 report_fatal_error(
9257 reason: "Target doesn't support calls with kcfi operand bundles.");
9258 CFIType = cast<ConstantInt>(Val: Bundle->Inputs[0]);
9259 assert(CFIType->getType()->isIntegerTy(32) && "Invalid CFI type");
9260 }
9261 }
9262
9263 SDValue ConvControlToken;
9264 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_convergencectrl)) {
9265 auto *Token = Bundle->Inputs[0].get();
9266 ConvControlToken = getValue(V: Token);
9267 }
9268
9269 GlobalValue *DeactivationSymbol = nullptr;
9270 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_deactivation_symbol)) {
9271 DeactivationSymbol = cast<GlobalValue>(Val: Bundle->Inputs[0].get());
9272 }
9273
9274 TargetLowering::CallLoweringInfo CLI(DAG);
9275 CLI.setDebugLoc(getCurSDLoc())
9276 .setChain(getRoot())
9277 .setCallee(ResultType: RetTy, FTy, Target: Callee, ArgsList: std::move(Args), Call: CB)
9278 .setTailCall(isTailCall)
9279 .setConvergent(CB.isConvergent())
9280 .setIsPreallocated(
9281 CB.countOperandBundlesOfType(ID: LLVMContext::OB_preallocated) != 0)
9282 .setCFIType(CFIType)
9283 .setConvergenceControlToken(ConvControlToken)
9284 .setDeactivationSymbol(DeactivationSymbol);
9285
9286 // Set the pointer authentication info if we have it.
9287 if (PAI) {
9288 if (!TLI.supportPtrAuthBundles())
9289 report_fatal_error(
9290 reason: "This target doesn't support calls with ptrauth operand bundles.");
9291 CLI.setPtrAuth(*PAI);
9292 }
9293
9294 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
9295
9296 if (Result.first.getNode()) {
9297 Result.first = lowerRangeToAssertZExt(DAG, I: CB, Op: Result.first);
9298 Result.first = lowerNoFPClassToAssertNoFPClass(DAG, I: CB, Op: Result.first);
9299 setValue(V: &CB, NewN: Result.first);
9300 }
9301
9302 // The last element of CLI.InVals has the SDValue for swifterror return.
9303 // Here we copy it to a virtual register and update SwiftErrorMap for
9304 // book-keeping.
9305 if (SwiftErrorVal && TLI.supportSwiftError()) {
9306 // Get the last element of InVals.
9307 SDValue Src = CLI.InVals.back();
9308 Register VReg =
9309 SwiftError.getOrCreateVRegDefAt(&CB, FuncInfo.MBB, SwiftErrorVal);
9310 SDValue CopyNode = CLI.DAG.getCopyToReg(Chain: Result.second, dl: CLI.DL, Reg: VReg, N: Src);
9311 DAG.setRoot(CopyNode);
9312 }
9313}
9314
9315static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
9316 SelectionDAGBuilder &Builder) {
9317 // Check to see if this load can be trivially constant folded, e.g. if the
9318 // input is from a string literal.
9319 if (const Constant *LoadInput = dyn_cast<Constant>(Val: PtrVal)) {
9320 // Cast pointer to the type we really want to load.
9321 Type *LoadTy =
9322 Type::getIntNTy(C&: PtrVal->getContext(), N: LoadVT.getScalarSizeInBits());
9323 if (LoadVT.isVector())
9324 LoadTy = FixedVectorType::get(ElementType: LoadTy, NumElts: LoadVT.getVectorNumElements());
9325 if (const Constant *LoadCst =
9326 ConstantFoldLoadFromConstPtr(C: const_cast<Constant *>(LoadInput),
9327 Ty: LoadTy, DL: Builder.DAG.getDataLayout()))
9328 return Builder.getValue(V: LoadCst);
9329 }
9330
9331 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
9332 // still constant memory, the input chain can be the entry node.
9333 SDValue Root;
9334 bool ConstantMemory = false;
9335
9336 // Do not serialize (non-volatile) loads of constant memory with anything.
9337 if (Builder.BatchAA && Builder.BatchAA->pointsToConstantMemory(P: PtrVal)) {
9338 Root = Builder.DAG.getEntryNode();
9339 ConstantMemory = true;
9340 } else {
9341 // Do not serialize non-volatile loads against each other.
9342 Root = Builder.DAG.getRoot();
9343 }
9344
9345 SDValue Ptr = Builder.getValue(V: PtrVal);
9346 SDValue LoadVal =
9347 Builder.DAG.getLoad(VT: LoadVT, dl: Builder.getCurSDLoc(), Chain: Root, Ptr,
9348 PtrInfo: MachinePointerInfo(PtrVal), Alignment: Align(1));
9349
9350 if (!ConstantMemory)
9351 Builder.PendingLoads.push_back(Elt: LoadVal.getValue(R: 1));
9352 return LoadVal;
9353}
9354
9355/// Record the value for an instruction that produces an integer result,
9356/// converting the type where necessary.
9357void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
9358 SDValue Value,
9359 bool IsSigned) {
9360 EVT VT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
9361 Ty: I.getType(), AllowUnknown: true);
9362 Value = DAG.getExtOrTrunc(IsSigned, Op: Value, DL: getCurSDLoc(), VT);
9363 setValue(V: &I, NewN: Value);
9364}
9365
9366/// See if we can lower a memcmp/bcmp call into an optimized form. If so, return
9367/// true and lower it. Otherwise return false, and it will be lowered like a
9368/// normal call.
9369/// The caller already checked that \p I calls the appropriate LibFunc with a
9370/// correct prototype.
9371bool SelectionDAGBuilder::visitMemCmpBCmpCall(const CallInst &I) {
9372 const Value *LHS = I.getArgOperand(i: 0), *RHS = I.getArgOperand(i: 1);
9373 const Value *Size = I.getArgOperand(i: 2);
9374 const ConstantSDNode *CSize = dyn_cast<ConstantSDNode>(Val: getValue(V: Size));
9375 if (CSize && CSize->getZExtValue() == 0) {
9376 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
9377 Ty: I.getType(), AllowUnknown: true);
9378 setValue(V: &I, NewN: DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: CallVT));
9379 return true;
9380 }
9381
9382 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9383 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemcmp(
9384 DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(), Op1: getValue(V: LHS), Op2: getValue(V: RHS),
9385 Op3: getValue(V: Size), CI: &I);
9386 if (Res.first.getNode()) {
9387 processIntegerCallValue(I, Value: Res.first, IsSigned: true);
9388 PendingLoads.push_back(Elt: Res.second);
9389 return true;
9390 }
9391
9392 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
9393 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
9394 if (!CSize || !isOnlyUsedInZeroEqualityComparison(CxtI: &I))
9395 return false;
9396
9397 // If the target has a fast compare for the given size, it will return a
9398 // preferred load type for that size. Require that the load VT is legal and
9399 // that the target supports unaligned loads of that type. Otherwise, return
9400 // INVALID.
9401 auto hasFastLoadsAndCompare = [&](unsigned NumBits) {
9402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9403 MVT LVT = TLI.hasFastEqualityCompare(NumBits);
9404 if (LVT != MVT::INVALID_SIMPLE_VALUE_TYPE) {
9405 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
9406 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
9407 // TODO: Check alignment of src and dest ptrs.
9408 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
9409 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
9410 if (!TLI.isTypeLegal(VT: LVT) ||
9411 !TLI.allowsMisalignedMemoryAccesses(LVT, AddrSpace: SrcAS) ||
9412 !TLI.allowsMisalignedMemoryAccesses(LVT, AddrSpace: DstAS))
9413 LVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
9414 }
9415
9416 return LVT;
9417 };
9418
9419 // This turns into unaligned loads. We only do this if the target natively
9420 // supports the MVT we'll be loading or if it is small enough (<= 4) that
9421 // we'll only produce a small number of byte loads.
9422 MVT LoadVT;
9423 unsigned NumBitsToCompare = CSize->getZExtValue() * 8;
9424 switch (NumBitsToCompare) {
9425 default:
9426 return false;
9427 case 16:
9428 LoadVT = MVT::i16;
9429 break;
9430 case 32:
9431 LoadVT = MVT::i32;
9432 break;
9433 case 64:
9434 case 128:
9435 case 256:
9436 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare);
9437 break;
9438 }
9439
9440 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE)
9441 return false;
9442
9443 SDValue LoadL = getMemCmpLoad(PtrVal: LHS, LoadVT, Builder&: *this);
9444 SDValue LoadR = getMemCmpLoad(PtrVal: RHS, LoadVT, Builder&: *this);
9445
9446 // Bitcast to a wide integer type if the loads are vectors.
9447 if (LoadVT.isVector()) {
9448 EVT CmpVT = EVT::getIntegerVT(Context&: LHS->getContext(), BitWidth: LoadVT.getSizeInBits());
9449 LoadL = DAG.getBitcast(VT: CmpVT, V: LoadL);
9450 LoadR = DAG.getBitcast(VT: CmpVT, V: LoadR);
9451 }
9452
9453 SDValue Cmp = DAG.getSetCC(DL: getCurSDLoc(), VT: MVT::i1, LHS: LoadL, RHS: LoadR, Cond: ISD::SETNE);
9454 processIntegerCallValue(I, Value: Cmp, IsSigned: false);
9455 return true;
9456}
9457
9458/// See if we can lower a memchr call into an optimized form. If so, return
9459/// true and lower it. Otherwise return false, and it will be lowered like a
9460/// normal call.
9461/// The caller already checked that \p I calls the appropriate LibFunc with a
9462/// correct prototype.
9463bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
9464 const Value *Src = I.getArgOperand(i: 0);
9465 const Value *Char = I.getArgOperand(i: 1);
9466 const Value *Length = I.getArgOperand(i: 2);
9467
9468 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9469 std::pair<SDValue, SDValue> Res =
9470 TSI.EmitTargetCodeForMemchr(DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(),
9471 Src: getValue(V: Src), Char: getValue(V: Char), Length: getValue(V: Length),
9472 SrcPtrInfo: MachinePointerInfo(Src));
9473 if (Res.first.getNode()) {
9474 setValue(V: &I, NewN: Res.first);
9475 PendingLoads.push_back(Elt: Res.second);
9476 return true;
9477 }
9478
9479 return false;
9480}
9481
9482/// See if we can lower a memccpy call into an optimized form. If so, return
9483/// true and lower it, otherwise return false and it will be lowered like a
9484/// normal call.
9485/// The caller already checked that \p I calls the appropriate LibFunc with a
9486/// correct prototype.
9487bool SelectionDAGBuilder::visitMemCCpyCall(const CallInst &I) {
9488 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9489 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemccpy(
9490 DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(), Dst: getValue(V: I.getArgOperand(i: 0)),
9491 Src: getValue(V: I.getArgOperand(i: 1)), C: getValue(V: I.getArgOperand(i: 2)),
9492 Size: getValue(V: I.getArgOperand(i: 3)), CI: &I);
9493
9494 if (Res.first) {
9495 processIntegerCallValue(I, Value: Res.first, IsSigned: true);
9496 PendingLoads.push_back(Elt: Res.second);
9497 return true;
9498 }
9499 return false;
9500}
9501
9502/// See if we can lower a mempcpy call into an optimized form. If so, return
9503/// true and lower it. Otherwise return false, and it will be lowered like a
9504/// normal call.
9505/// The caller already checked that \p I calls the appropriate LibFunc with a
9506/// correct prototype.
9507bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) {
9508 SDValue Dst = getValue(V: I.getArgOperand(i: 0));
9509 SDValue Src = getValue(V: I.getArgOperand(i: 1));
9510 SDValue Size = getValue(V: I.getArgOperand(i: 2));
9511
9512 Align DstAlign = DAG.InferPtrAlign(Ptr: Dst).valueOrOne();
9513 Align SrcAlign = DAG.InferPtrAlign(Ptr: Src).valueOrOne();
9514
9515 SDLoc sdl = getCurSDLoc();
9516
9517 // In the mempcpy context we need to pass in a false value for isTailCall
9518 // because the return pointer needs to be adjusted by the size of
9519 // the copied memory.
9520 SDValue Root = getMemoryRoot();
9521 SDValue MC = DAG.getMemcpy(
9522 Chain: Root, dl: sdl, Dst, Src, Size, DstAlign, SrcAlign, isVol: false, AlwaysInline: false,
9523 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
9524 SrcPtrInfo: MachinePointerInfo(I.getArgOperand(i: 1)), AAInfo: I.getAAMetadata());
9525 assert(MC.getNode() != nullptr &&
9526 "** memcpy should not be lowered as TailCall in mempcpy context **");
9527 DAG.setRoot(MC);
9528
9529 // Check if Size needs to be truncated or extended.
9530 Size = DAG.getSExtOrTrunc(Op: Size, DL: sdl, VT: Dst.getValueType());
9531
9532 // Adjust return pointer to point just past the last dst byte.
9533 SDValue DstPlusSize = DAG.getMemBasePlusOffset(Base: Dst, Offset: Size, DL: sdl);
9534 setValue(V: &I, NewN: DstPlusSize);
9535 return true;
9536}
9537
9538/// See if we can lower a strcpy call into an optimized form. If so, return
9539/// true and lower it, otherwise return false and it will be lowered like a
9540/// normal call.
9541/// The caller already checked that \p I calls the appropriate LibFunc with a
9542/// correct prototype.
9543bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
9544 const Value *Arg0 = I.getArgOperand(i: 0), *Arg1 = I.getArgOperand(i: 1);
9545
9546 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9547 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForStrcpy(
9548 DAG, DL: getCurSDLoc(), Chain: getRoot(), Dest: getValue(V: Arg0), Src: getValue(V: Arg1),
9549 DestPtrInfo: MachinePointerInfo(Arg0), SrcPtrInfo: MachinePointerInfo(Arg1), isStpcpy, CI: &I);
9550 if (Res.first.getNode()) {
9551 setValue(V: &I, NewN: Res.first);
9552 DAG.setRoot(Res.second);
9553 return true;
9554 }
9555
9556 return false;
9557}
9558
9559/// See if we can lower a strcmp call into an optimized form. If so, return
9560/// true and lower it, otherwise return false and it will be lowered like a
9561/// normal call.
9562/// The caller already checked that \p I calls the appropriate LibFunc with a
9563/// correct prototype.
9564bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
9565 const Value *Arg0 = I.getArgOperand(i: 0), *Arg1 = I.getArgOperand(i: 1);
9566
9567 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9568 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForStrcmp(
9569 DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(), Op1: getValue(V: Arg0), Op2: getValue(V: Arg1),
9570 Op1PtrInfo: MachinePointerInfo(Arg0), Op2PtrInfo: MachinePointerInfo(Arg1), CI: &I);
9571 if (Res.first.getNode()) {
9572 processIntegerCallValue(I, Value: Res.first, IsSigned: true);
9573 PendingLoads.push_back(Elt: Res.second);
9574 return true;
9575 }
9576
9577 return false;
9578}
9579
9580/// See if we can lower a strlen call into an optimized form. If so, return
9581/// true and lower it, otherwise return false and it will be lowered like a
9582/// normal call.
9583/// The caller already checked that \p I calls the appropriate LibFunc with a
9584/// correct prototype.
9585bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
9586 const Value *Arg0 = I.getArgOperand(i: 0);
9587
9588 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9589 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForStrlen(
9590 DAG, DL: getCurSDLoc(), Chain: DAG.getRoot(), Src: getValue(V: Arg0), CI: &I);
9591 if (Res.first.getNode()) {
9592 processIntegerCallValue(I, Value: Res.first, IsSigned: false);
9593 PendingLoads.push_back(Elt: Res.second);
9594 return true;
9595 }
9596
9597 return false;
9598}
9599
9600/// See if we can lower a strnlen call into an optimized form. If so, return
9601/// true and lower it, otherwise return false and it will be lowered like a
9602/// normal call.
9603/// The caller already checked that \p I calls the appropriate LibFunc with a
9604/// correct prototype.
9605bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
9606 const Value *Arg0 = I.getArgOperand(i: 0), *Arg1 = I.getArgOperand(i: 1);
9607
9608 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9609 std::pair<SDValue, SDValue> Res =
9610 TSI.EmitTargetCodeForStrnlen(DAG, DL: getCurSDLoc(), Chain: DAG.getRoot(),
9611 Src: getValue(V: Arg0), MaxLength: getValue(V: Arg1),
9612 SrcPtrInfo: MachinePointerInfo(Arg0));
9613 if (Res.first.getNode()) {
9614 processIntegerCallValue(I, Value: Res.first, IsSigned: false);
9615 PendingLoads.push_back(Elt: Res.second);
9616 return true;
9617 }
9618
9619 return false;
9620}
9621
9622/// See if we can lower a Strstr call into an optimized form. If so, return
9623/// true and lower it, otherwise return false and it will be lowered like a
9624/// normal call.
9625/// The caller already checked that \p I calls the appropriate LibFunc with a
9626/// correct prototype.
9627bool SelectionDAGBuilder::visitStrstrCall(const CallInst &I) {
9628 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9629 const Value *Arg0 = I.getArgOperand(i: 0), *Arg1 = I.getArgOperand(i: 1);
9630 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForStrstr(
9631 DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(), Op1: getValue(V: Arg0), Op2: getValue(V: Arg1), CI: &I);
9632 if (Res.first) {
9633 processIntegerCallValue(I, Value: Res.first, IsSigned: false);
9634 PendingLoads.push_back(Elt: Res.second);
9635 return true;
9636 }
9637 return false;
9638}
9639
9640/// See if we can lower a unary floating-point operation into an SDNode with
9641/// the specified Opcode. If so, return true and lower it, otherwise return
9642/// false and it will be lowered like a normal call.
9643/// The caller already checked that \p I calls the appropriate LibFunc with a
9644/// correct prototype.
9645bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
9646 unsigned Opcode) {
9647 // We already checked this call's prototype; verify it doesn't modify errno.
9648 // Do not perform optimizations for call sites that require strict
9649 // floating-point semantics.
9650 if (!I.onlyReadsMemory() || I.isStrictFP())
9651 return false;
9652
9653 SDNodeFlags Flags;
9654 Flags.copyFMF(FPMO: cast<FPMathOperator>(Val: I));
9655
9656 SDValue Tmp = getValue(V: I.getArgOperand(i: 0));
9657 setValue(V: &I,
9658 NewN: DAG.getNode(Opcode, DL: getCurSDLoc(), VT: Tmp.getValueType(), Operand: Tmp, Flags));
9659 return true;
9660}
9661
9662/// See if we can lower a binary floating-point operation into an SDNode with
9663/// the specified Opcode. If so, return true and lower it. Otherwise return
9664/// false, and it will be lowered like a normal call.
9665/// The caller already checked that \p I calls the appropriate LibFunc with a
9666/// correct prototype.
9667bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
9668 unsigned Opcode) {
9669 // We already checked this call's prototype; verify it doesn't modify errno.
9670 // Do not perform optimizations for call sites that require strict
9671 // floating-point semantics.
9672 if (!I.onlyReadsMemory() || I.isStrictFP())
9673 return false;
9674
9675 SDNodeFlags Flags;
9676 Flags.copyFMF(FPMO: cast<FPMathOperator>(Val: I));
9677
9678 SDValue Tmp0 = getValue(V: I.getArgOperand(i: 0));
9679 SDValue Tmp1 = getValue(V: I.getArgOperand(i: 1));
9680 EVT VT = Tmp0.getValueType();
9681 setValue(V: &I, NewN: DAG.getNode(Opcode, DL: getCurSDLoc(), VT, N1: Tmp0, N2: Tmp1, Flags));
9682 return true;
9683}
9684
9685void SelectionDAGBuilder::visitCall(const CallInst &I) {
9686 // Handle inline assembly differently.
9687 if (I.isInlineAsm()) {
9688 visitInlineAsm(Call: I);
9689 return;
9690 }
9691
9692 diagnoseDontCall(CI: I);
9693
9694 if (Function *F = I.getCalledFunction()) {
9695 if (F->isDeclaration()) {
9696 // Is this an LLVM intrinsic?
9697 if (unsigned IID = F->getIntrinsicID()) {
9698 visitIntrinsicCall(I, Intrinsic: IID);
9699 return;
9700 }
9701 }
9702
9703 // Check for well-known libc/libm calls. If the function is internal, it
9704 // can't be a library call. Don't do the check if marked as nobuiltin for
9705 // some reason.
9706 // This code should not handle libcalls that are already canonicalized to
9707 // intrinsics by the middle-end.
9708 LibFunc Func = !I.isNoBuiltin() && !F->hasLocalLinkage() && F->hasName()
9709 ? LibInfo->getLibFunc(FDecl: *F)
9710 : NotLibFunc;
9711 if (LibInfo->hasOptimizedCodeGen(F: Func)) {
9712 switch (Func) {
9713 default: break;
9714 case LibFunc_bcmp:
9715 if (visitMemCmpBCmpCall(I))
9716 return;
9717 break;
9718 case LibFunc_copysign:
9719 case LibFunc_copysignf:
9720 case LibFunc_copysignl:
9721 // We already checked this call's prototype; verify it doesn't modify
9722 // errno.
9723 if (I.onlyReadsMemory()) {
9724 SDValue LHS = getValue(V: I.getArgOperand(i: 0));
9725 SDValue RHS = getValue(V: I.getArgOperand(i: 1));
9726 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FCOPYSIGN, DL: getCurSDLoc(),
9727 VT: LHS.getValueType(), N1: LHS, N2: RHS));
9728 return;
9729 }
9730 break;
9731 case LibFunc_sin:
9732 case LibFunc_sinf:
9733 case LibFunc_sinl:
9734 if (visitUnaryFloatCall(I, Opcode: ISD::FSIN))
9735 return;
9736 break;
9737 case LibFunc_cos:
9738 case LibFunc_cosf:
9739 case LibFunc_cosl:
9740 if (visitUnaryFloatCall(I, Opcode: ISD::FCOS))
9741 return;
9742 break;
9743 case LibFunc_tan:
9744 case LibFunc_tanf:
9745 case LibFunc_tanl:
9746 if (visitUnaryFloatCall(I, Opcode: ISD::FTAN))
9747 return;
9748 break;
9749 case LibFunc_asin:
9750 case LibFunc_asinf:
9751 case LibFunc_asinl:
9752 if (visitUnaryFloatCall(I, Opcode: ISD::FASIN))
9753 return;
9754 break;
9755 case LibFunc_acos:
9756 case LibFunc_acosf:
9757 case LibFunc_acosl:
9758 if (visitUnaryFloatCall(I, Opcode: ISD::FACOS))
9759 return;
9760 break;
9761 case LibFunc_atan:
9762 case LibFunc_atanf:
9763 case LibFunc_atanl:
9764 if (visitUnaryFloatCall(I, Opcode: ISD::FATAN))
9765 return;
9766 break;
9767 case LibFunc_atan2:
9768 case LibFunc_atan2f:
9769 case LibFunc_atan2l:
9770 if (visitBinaryFloatCall(I, Opcode: ISD::FATAN2))
9771 return;
9772 break;
9773 case LibFunc_sinh:
9774 case LibFunc_sinhf:
9775 case LibFunc_sinhl:
9776 if (visitUnaryFloatCall(I, Opcode: ISD::FSINH))
9777 return;
9778 break;
9779 case LibFunc_cosh:
9780 case LibFunc_coshf:
9781 case LibFunc_coshl:
9782 if (visitUnaryFloatCall(I, Opcode: ISD::FCOSH))
9783 return;
9784 break;
9785 case LibFunc_tanh:
9786 case LibFunc_tanhf:
9787 case LibFunc_tanhl:
9788 if (visitUnaryFloatCall(I, Opcode: ISD::FTANH))
9789 return;
9790 break;
9791 case LibFunc_sqrt:
9792 case LibFunc_sqrtf:
9793 case LibFunc_sqrtl:
9794 case LibFunc_sqrt_finite:
9795 case LibFunc_sqrtf_finite:
9796 case LibFunc_sqrtl_finite:
9797 if (visitUnaryFloatCall(I, Opcode: ISD::FSQRT))
9798 return;
9799 break;
9800 case LibFunc_log2:
9801 case LibFunc_log2f:
9802 case LibFunc_log2l:
9803 if (visitUnaryFloatCall(I, Opcode: ISD::FLOG2))
9804 return;
9805 break;
9806 case LibFunc_exp2:
9807 case LibFunc_exp2f:
9808 case LibFunc_exp2l:
9809 if (visitUnaryFloatCall(I, Opcode: ISD::FEXP2))
9810 return;
9811 break;
9812 case LibFunc_exp10:
9813 case LibFunc_exp10f:
9814 case LibFunc_exp10l:
9815 if (visitUnaryFloatCall(I, Opcode: ISD::FEXP10))
9816 return;
9817 break;
9818 case LibFunc_ldexp:
9819 case LibFunc_ldexpf:
9820 case LibFunc_ldexpl:
9821 if (visitBinaryFloatCall(I, Opcode: ISD::FLDEXP))
9822 return;
9823 break;
9824 case LibFunc_strstr:
9825 if (visitStrstrCall(I))
9826 return;
9827 break;
9828 case LibFunc_memcmp:
9829 if (visitMemCmpBCmpCall(I))
9830 return;
9831 break;
9832 case LibFunc_memccpy:
9833 if (visitMemCCpyCall(I))
9834 return;
9835 break;
9836 case LibFunc_mempcpy:
9837 if (visitMemPCpyCall(I))
9838 return;
9839 break;
9840 case LibFunc_memchr:
9841 if (visitMemChrCall(I))
9842 return;
9843 break;
9844 case LibFunc_strcpy:
9845 if (visitStrCpyCall(I, isStpcpy: false))
9846 return;
9847 break;
9848 case LibFunc_stpcpy:
9849 if (visitStrCpyCall(I, isStpcpy: true))
9850 return;
9851 break;
9852 case LibFunc_strcmp:
9853 if (visitStrCmpCall(I))
9854 return;
9855 break;
9856 case LibFunc_strlen:
9857 if (visitStrLenCall(I))
9858 return;
9859 break;
9860 case LibFunc_strnlen:
9861 if (visitStrNLenCall(I))
9862 return;
9863 break;
9864 }
9865 }
9866 }
9867
9868 if (I.countOperandBundlesOfType(ID: LLVMContext::OB_ptrauth)) {
9869 LowerCallSiteWithPtrAuthBundle(CB: cast<CallBase>(Val: I), /*EHPadBB=*/nullptr);
9870 return;
9871 }
9872
9873 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
9874 // have to do anything here to lower funclet bundles.
9875 // CFGuardTarget bundles are lowered in LowerCallTo.
9876 failForInvalidBundles(
9877 I, Name: "calls",
9878 AllowedBundles: {LLVMContext::OB_deopt, LLVMContext::OB_funclet,
9879 LLVMContext::OB_cfguardtarget, LLVMContext::OB_preallocated,
9880 LLVMContext::OB_clang_arc_attachedcall, LLVMContext::OB_kcfi,
9881 LLVMContext::OB_convergencectrl, LLVMContext::OB_deactivation_symbol});
9882
9883 SDValue Callee = getValue(V: I.getCalledOperand());
9884
9885 if (I.hasDeoptState())
9886 LowerCallSiteWithDeoptBundle(Call: &I, Callee, EHPadBB: nullptr);
9887 else
9888 // Check if we can potentially perform a tail call. More detailed checking
9889 // is be done within LowerCallTo, after more information about the call is
9890 // known.
9891 LowerCallTo(CB: I, Callee, isTailCall: I.isTailCall(), isMustTailCall: I.isMustTailCall());
9892}
9893
9894void SelectionDAGBuilder::LowerCallSiteWithPtrAuthBundle(
9895 const CallBase &CB, const BasicBlock *EHPadBB) {
9896 auto PAB = CB.getOperandBundle(Name: "ptrauth");
9897 const Value *CalleeV = CB.getCalledOperand();
9898
9899 // Gather the call ptrauth data from the operand bundle:
9900 // [ i32 <key>, i64 <discriminator> ]
9901 const auto *Key = cast<ConstantInt>(Val: PAB->Inputs[0]);
9902 const Value *Discriminator = PAB->Inputs[1];
9903
9904 assert(Key->getType()->isIntegerTy(32) && "Invalid ptrauth key");
9905 assert(Discriminator->getType()->isIntegerTy(64) &&
9906 "Invalid ptrauth discriminator");
9907
9908 // Look through ptrauth constants to find the raw callee.
9909 // Do a direct unauthenticated call if we found it and everything matches.
9910 if (const auto *CalleeCPA = dyn_cast<ConstantPtrAuth>(Val: CalleeV))
9911 if (CalleeCPA->isKnownCompatibleWith(Key, Discriminator,
9912 DL: DAG.getDataLayout()))
9913 return LowerCallTo(CB, Callee: getValue(V: CalleeCPA->getPointer()), isTailCall: CB.isTailCall(),
9914 isMustTailCall: CB.isMustTailCall(), EHPadBB);
9915
9916 // Functions should never be ptrauth-called directly.
9917 assert(!isa<Function>(CalleeV) && "invalid direct ptrauth call");
9918
9919 // Otherwise, do an authenticated indirect call.
9920 TargetLowering::PtrAuthInfo PAI = {.Key: Key->getZExtValue(),
9921 .Discriminator: getValue(V: Discriminator)};
9922
9923 LowerCallTo(CB, Callee: getValue(V: CalleeV), isTailCall: CB.isTailCall(), isMustTailCall: CB.isMustTailCall(),
9924 EHPadBB, PAI: &PAI);
9925}
9926
9927namespace {
9928
9929/// AsmOperandInfo - This contains information for each constraint that we are
9930/// lowering.
9931class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
9932public:
9933 /// CallOperand - If this is the result output operand or a clobber
9934 /// this is null, otherwise it is the incoming operand to the CallInst.
9935 /// This gets modified as the asm is processed.
9936 SDValue CallOperand;
9937
9938 /// AssignedRegs - If this is a register or register class operand, this
9939 /// contains the set of register corresponding to the operand.
9940 RegsForValue AssignedRegs;
9941
9942 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
9943 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr, 0) {
9944 }
9945
9946 /// Whether or not this operand accesses memory
9947 bool hasMemory(const TargetLowering &TLI) const {
9948 // Indirect operand accesses access memory.
9949 if (isIndirect)
9950 return true;
9951
9952 for (const auto &Code : Codes)
9953 if (TLI.getConstraintType(Constraint: Code) == TargetLowering::C_Memory)
9954 return true;
9955
9956 return false;
9957 }
9958};
9959
9960
9961} // end anonymous namespace
9962
9963/// Make sure that the output operand \p OpInfo and its corresponding input
9964/// operand \p MatchingOpInfo have compatible constraint types (otherwise error
9965/// out).
9966static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo,
9967 SDISelAsmOperandInfo &MatchingOpInfo,
9968 SelectionDAG &DAG) {
9969 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
9970 return;
9971
9972 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
9973 const auto &TLI = DAG.getTargetLoweringInfo();
9974
9975 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
9976 TLI.getRegForInlineAsmConstraint(TRI, Constraint: OpInfo.ConstraintCode,
9977 VT: OpInfo.ConstraintVT);
9978 std::pair<unsigned, const TargetRegisterClass *> InputRC =
9979 TLI.getRegForInlineAsmConstraint(TRI, Constraint: MatchingOpInfo.ConstraintCode,
9980 VT: MatchingOpInfo.ConstraintVT);
9981 const bool OutOpIsIntOrFP =
9982 OpInfo.ConstraintVT.isInteger() || OpInfo.ConstraintVT.isFloatingPoint();
9983 const bool InOpIsIntOrFP = MatchingOpInfo.ConstraintVT.isInteger() ||
9984 MatchingOpInfo.ConstraintVT.isFloatingPoint();
9985 if ((OutOpIsIntOrFP != InOpIsIntOrFP) || (MatchRC.second != InputRC.second)) {
9986 // FIXME: error out in a more elegant fashion
9987 report_fatal_error(reason: "Unsupported asm: input constraint"
9988 " with a matching output constraint of"
9989 " incompatible type!");
9990 }
9991 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
9992}
9993
9994/// Get a direct memory input to behave well as an indirect operand.
9995/// This may introduce stores, hence the need for a \p Chain.
9996/// \return The (possibly updated) chain.
9997static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
9998 SDISelAsmOperandInfo &OpInfo,
9999 SelectionDAG &DAG) {
10000 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10001
10002 // If we don't have an indirect input, put it in the constpool if we can,
10003 // otherwise spill it to a stack slot.
10004 // TODO: This isn't quite right. We need to handle these according to
10005 // the addressing mode that the constraint wants. Also, this may take
10006 // an additional register for the computation and we don't want that
10007 // either.
10008
10009 // If the operand is a float, integer, or vector constant, spill to a
10010 // constant pool entry to get its address.
10011 const Value *OpVal = OpInfo.CallOperandVal;
10012 if (isa<ConstantFP>(Val: OpVal) || isa<ConstantInt>(Val: OpVal) ||
10013 isa<ConstantVector>(Val: OpVal) || isa<ConstantDataVector>(Val: OpVal)) {
10014 OpInfo.CallOperand = DAG.getConstantPool(
10015 C: cast<Constant>(Val: OpVal), VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
10016 return Chain;
10017 }
10018
10019 // Otherwise, create a stack slot and emit a store to it before the asm.
10020 Type *Ty = OpVal->getType();
10021 auto &DL = DAG.getDataLayout();
10022 TypeSize TySize = DL.getTypeAllocSize(Ty);
10023 MachineFunction &MF = DAG.getMachineFunction();
10024 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
10025 int StackID = 0;
10026 if (TySize.isScalable())
10027 StackID = TFI->getStackIDForScalableVectors();
10028 int SSFI = MF.getFrameInfo().CreateStackObject(Size: TySize.getKnownMinValue(),
10029 Alignment: DL.getPrefTypeAlign(Ty), isSpillSlot: false,
10030 Alloca: nullptr, ID: StackID);
10031 SDValue StackSlot = DAG.getFrameIndex(FI: SSFI, VT: TLI.getFrameIndexTy(DL));
10032 Chain = DAG.getTruncStore(Chain, dl: Location, Val: OpInfo.CallOperand, Ptr: StackSlot,
10033 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: SSFI),
10034 SVT: TLI.getMemValueType(DL, Ty));
10035 OpInfo.CallOperand = StackSlot;
10036
10037 return Chain;
10038}
10039
10040/// GetRegistersForValue - Assign registers (virtual or physical) for the
10041/// specified operand. We prefer to assign virtual registers, to allow the
10042/// register allocator to handle the assignment process. However, if the asm
10043/// uses features that we can't model on machineinstrs, we have SDISel do the
10044/// allocation. This produces generally horrible, but correct, code.
10045///
10046/// OpInfo describes the operand
10047/// RefOpInfo describes the matching operand if any, the operand otherwise
10048static std::optional<unsigned>
10049getRegistersForValue(SelectionDAG &DAG, const SDLoc &DL,
10050 SDISelAsmOperandInfo &OpInfo,
10051 SDISelAsmOperandInfo &RefOpInfo) {
10052 LLVMContext &Context = *DAG.getContext();
10053 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10054
10055 MachineFunction &MF = DAG.getMachineFunction();
10056 SmallVector<Register, 4> Regs;
10057 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
10058
10059 // No work to do for memory/address operands.
10060 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
10061 OpInfo.ConstraintType == TargetLowering::C_Address)
10062 return std::nullopt;
10063
10064 // If this is a constraint for a single physreg, or a constraint for a
10065 // register class, find it.
10066 unsigned AssignedReg;
10067 const TargetRegisterClass *RC;
10068 std::tie(args&: AssignedReg, args&: RC) = TLI.getRegForInlineAsmConstraint(
10069 TRI: &TRI, Constraint: RefOpInfo.ConstraintCode, VT: RefOpInfo.ConstraintVT);
10070 // RC is unset only on failure. Return immediately.
10071 if (!RC)
10072 return std::nullopt;
10073
10074 // Get the actual register value type. This is important, because the user
10075 // may have asked for (e.g.) the AX register in i32 type. We need to
10076 // remember that AX is actually i16 to get the right extension.
10077 const MVT RegVT = *TRI.legalclasstypes_begin(RC: *RC);
10078
10079 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) {
10080 // If this is an FP operand in an integer register (or visa versa), or more
10081 // generally if the operand value disagrees with the register class we plan
10082 // to stick it in, fix the operand type.
10083 //
10084 // If this is an input value, the bitcast to the new type is done now.
10085 // Bitcast for output value is done at the end of visitInlineAsm().
10086 if ((OpInfo.Type == InlineAsm::isOutput ||
10087 OpInfo.Type == InlineAsm::isInput) &&
10088 !TRI.isTypeLegalForClass(RC: *RC, T: OpInfo.ConstraintVT)) {
10089 // Try to convert to the first EVT that the reg class contains. If the
10090 // types are identical size, use a bitcast to convert (e.g. two differing
10091 // vector types). Note: output bitcast is done at the end of
10092 // visitInlineAsm().
10093 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
10094 // Exclude indirect inputs while they are unsupported because the code
10095 // to perform the load is missing and thus OpInfo.CallOperand still
10096 // refers to the input address rather than the pointed-to value.
10097 if (OpInfo.Type == InlineAsm::isInput && !OpInfo.isIndirect)
10098 OpInfo.CallOperand =
10099 DAG.getNode(Opcode: ISD::BITCAST, DL, VT: RegVT, Operand: OpInfo.CallOperand);
10100 OpInfo.ConstraintVT = RegVT;
10101 // If the operand is an FP value and we want it in integer registers,
10102 // use the corresponding integer type. This turns an f64 value into
10103 // i64, which can be passed with two i32 values on a 32-bit machine.
10104 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
10105 MVT VT = MVT::getIntegerVT(BitWidth: OpInfo.ConstraintVT.getSizeInBits());
10106 if (OpInfo.Type == InlineAsm::isInput)
10107 OpInfo.CallOperand =
10108 DAG.getNode(Opcode: ISD::BITCAST, DL, VT, Operand: OpInfo.CallOperand);
10109 OpInfo.ConstraintVT = VT;
10110 }
10111 }
10112 }
10113
10114 // No need to allocate a matching input constraint since the constraint it's
10115 // matching to has already been allocated.
10116 if (OpInfo.isMatchingInputConstraint())
10117 return std::nullopt;
10118
10119 EVT ValueVT = OpInfo.ConstraintVT;
10120 if (OpInfo.ConstraintVT == MVT::Other)
10121 ValueVT = RegVT;
10122
10123 // Initialize NumRegs.
10124 unsigned NumRegs = 1;
10125 if (OpInfo.ConstraintVT != MVT::Other)
10126 NumRegs = TLI.getNumRegisters(Context, VT: OpInfo.ConstraintVT, RegisterVT: RegVT);
10127
10128 // If this is a constraint for a specific physical register, like {r17},
10129 // assign it now.
10130
10131 // If this associated to a specific register, initialize iterator to correct
10132 // place. If virtual, make sure we have enough registers
10133
10134 // Initialize iterator if necessary
10135 TargetRegisterClass::iterator I = RC->begin();
10136 MachineRegisterInfo &RegInfo = MF.getRegInfo();
10137
10138 // Do not check for single registers.
10139 if (AssignedReg) {
10140 I = std::find(first: I, last: RC->end(), val: AssignedReg);
10141 if (I == RC->end()) {
10142 // RC does not contain the selected register, which indicates a
10143 // mismatch between the register and the required type/bitwidth.
10144 return {AssignedReg};
10145 }
10146 }
10147
10148 for (; NumRegs; --NumRegs, ++I) {
10149 assert(I != RC->end() && "Ran out of registers to allocate!");
10150 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RegClass: RC);
10151 Regs.push_back(Elt: R);
10152 }
10153
10154 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
10155 return std::nullopt;
10156}
10157
10158static unsigned
10159findMatchingInlineAsmOperand(unsigned OperandNo,
10160 const std::vector<SDValue> &AsmNodeOperands) {
10161 // Scan until we find the definition we already emitted of this operand.
10162 unsigned CurOp = InlineAsm::Op_FirstOperand;
10163 for (; OperandNo; --OperandNo) {
10164 // Advance to the next operand.
10165 unsigned OpFlag = AsmNodeOperands[CurOp]->getAsZExtVal();
10166 const InlineAsm::Flag F(OpFlag);
10167 assert(
10168 (F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isMemKind()) &&
10169 "Skipped past definitions?");
10170 CurOp += F.getNumOperandRegisters() + 1;
10171 }
10172 return CurOp;
10173}
10174
10175namespace {
10176
10177class ExtraFlags {
10178 unsigned Flags = 0;
10179
10180public:
10181 explicit ExtraFlags(const CallBase &Call) {
10182 const InlineAsm *IA = cast<InlineAsm>(Val: Call.getCalledOperand());
10183 if (IA->hasSideEffects())
10184 Flags |= InlineAsm::Extra_HasSideEffects;
10185 if (IA->isAlignStack())
10186 Flags |= InlineAsm::Extra_IsAlignStack;
10187 if (IA->canThrow())
10188 Flags |= InlineAsm::Extra_MayUnwind;
10189 if (Call.isConvergent())
10190 Flags |= InlineAsm::Extra_IsConvergent;
10191 Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
10192 }
10193
10194 void update(const TargetLowering::AsmOperandInfo &OpInfo) {
10195 // Ideally, we would only check against memory constraints. However, the
10196 // meaning of an Other constraint can be target-specific and we can't easily
10197 // reason about it. Therefore, be conservative and set MayLoad/MayStore
10198 // for Other constraints as well.
10199 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
10200 OpInfo.ConstraintType == TargetLowering::C_Other) {
10201 if (OpInfo.Type == InlineAsm::isInput)
10202 Flags |= InlineAsm::Extra_MayLoad;
10203 else if (OpInfo.Type == InlineAsm::isOutput)
10204 Flags |= InlineAsm::Extra_MayStore;
10205 else if (OpInfo.Type == InlineAsm::isClobber)
10206 Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
10207 }
10208 }
10209
10210 unsigned get() const { return Flags; }
10211};
10212
10213} // end anonymous namespace
10214
10215static bool isFunction(SDValue Op) {
10216 if (Op && Op.getOpcode() == ISD::GlobalAddress) {
10217 if (auto *GA = dyn_cast<GlobalAddressSDNode>(Val&: Op)) {
10218 auto Fn = dyn_cast_or_null<Function>(Val: GA->getGlobal());
10219
10220 // In normal "call dllimport func" instruction (non-inlineasm) it force
10221 // indirect access by specifing call opcode. And usually specially print
10222 // asm with indirect symbol (i.g: "*") according to opcode. Inline asm can
10223 // not do in this way now. (In fact, this is similar with "Data Access"
10224 // action). So here we ignore dllimport function.
10225 if (Fn && !Fn->hasDLLImportStorageClass())
10226 return true;
10227 }
10228 }
10229 return false;
10230}
10231
10232namespace {
10233
10234struct ConstraintDecisionInfo {
10235 SmallVector<SDISelAsmOperandInfo, 16> ConstraintOperands;
10236 std::vector<SDValue> AsmNodeOperands;
10237 SDValue Glue, Chain;
10238 bool HasSideEffect = false;
10239 MCSymbol *BeginLabel = nullptr;
10240
10241 SmallVector<char> Buffer;
10242 raw_svector_ostream ErrorMsg;
10243
10244 ConstraintDecisionInfo() : ErrorMsg(Buffer) {}
10245};
10246
10247} // end anonymous namespace
10248
10249/// Construct operand info objects.
10250static bool
10251constructOperandInfo(ConstraintDecisionInfo &Info,
10252 TargetLowering::AsmOperandInfoVector &TargetConstraints,
10253 SelectionDAGBuilder &Builder, const TargetLowering &TLI,
10254 ExtraFlags &ExtraInfo) {
10255 for (auto &T : TargetConstraints) {
10256 Info.ConstraintOperands.push_back(Elt: SDISelAsmOperandInfo(T));
10257 SDISelAsmOperandInfo &OpInfo = Info.ConstraintOperands.back();
10258
10259 if (OpInfo.CallOperandVal)
10260 OpInfo.CallOperand = Builder.getValue(V: OpInfo.CallOperandVal);
10261
10262 if (!Info.HasSideEffect)
10263 Info.HasSideEffect = OpInfo.hasMemory(TLI);
10264
10265 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
10266 // FIXME: Could we compute this on OpInfo rather than T?
10267
10268 // Compute the constraint code and ConstraintType to use.
10269 TLI.ComputeConstraintToUse(OpInfo&: T, Op: SDValue());
10270
10271 if (T.ConstraintType == TargetLowering::C_Immediate && OpInfo.CallOperand &&
10272 !isa<ConstantSDNode>(Val: OpInfo.CallOperand)) {
10273 // We've delayed emitting a diagnostic like the "n" constraint because
10274 // inlining could cause an integer showing up.
10275 Info.ErrorMsg << "constraint '" << T.ConstraintCode
10276 << "' expects an integer constant expression";
10277 return true;
10278 }
10279
10280 ExtraInfo.update(OpInfo: T);
10281 }
10282
10283 return false;
10284}
10285
10286/// Compute which constraint option to use for each operand.
10287static void
10288computeConstraintToUse(ConstraintDecisionInfo &Info, const CallBase &Call,
10289 TargetLowering::AsmOperandInfoVector &TargetConstraints,
10290 SelectionDAGBuilder &Builder, const TargetLowering &TLI,
10291 const TargetMachine &TM, SelectionDAG &DAG) {
10292 const auto *IA = cast<InlineAsm>(Val: Call.getCalledOperand());
10293 SmallVector<StringRef, 4> AsmStrs;
10294 IA->collectAsmStrs(AsmStrs);
10295
10296 int OpNo = -1;
10297 for (SDISelAsmOperandInfo &OpInfo : Info.ConstraintOperands) {
10298 if (OpInfo.hasArg() || OpInfo.Type == InlineAsm::isOutput)
10299 OpNo++;
10300
10301 // If this is an output operand with a matching input operand, look up the
10302 // matching input. If their types mismatch, e.g. one is an integer, the
10303 // other is floating point, or their sizes are different, flag it as an
10304 // error.
10305 if (OpInfo.hasMatchingInput()) {
10306 SDISelAsmOperandInfo &Input =
10307 Info.ConstraintOperands[OpInfo.MatchingInput];
10308 patchMatchingInput(OpInfo, MatchingOpInfo&: Input, DAG);
10309 }
10310
10311 // Compute the constraint code and ConstraintType to use.
10312 TLI.ComputeConstraintToUse(OpInfo, Op: OpInfo.CallOperand, DAG: &DAG);
10313
10314 if ((OpInfo.ConstraintType == TargetLowering::C_Memory &&
10315 OpInfo.Type == InlineAsm::isClobber) ||
10316 OpInfo.ConstraintType == TargetLowering::C_Address)
10317 continue;
10318
10319 // In Linux PIC model, there are 4 cases about value/label addressing:
10320 //
10321 // 1: Function call or Label jmp inside the module.
10322 // 2: Data access (such as global variable, static variable) inside module.
10323 // 3: Function call or Label jmp outside the module.
10324 // 4: Data access (such as global variable) outside the module.
10325 //
10326 // Due to current llvm inline asm architecture designed to not "recognize"
10327 // the asm code, there are quite troubles for us to treat mem addressing
10328 // differently for same value/adress used in different instuctions.
10329 // For example, in pic model, call a func may in plt way or direclty
10330 // pc-related, but lea/mov a function adress may use got.
10331 //
10332 // Here we try to "recognize" function call for the case 1 and case 3 in
10333 // inline asm. And try to adjust the constraint for them.
10334 //
10335 // TODO: Due to current inline asm didn't encourage to jmp to the outsider
10336 // label, so here we don't handle jmp function label now, but we need to
10337 // enhance it (especilly in PIC model) if we meet meaningful requirements.
10338 if (OpInfo.isIndirect && isFunction(Op: OpInfo.CallOperand) &&
10339 TLI.isInlineAsmTargetBranch(AsmStrs, OpNo) &&
10340 TM.getCodeModel() != CodeModel::Large) {
10341 OpInfo.isIndirect = false;
10342 OpInfo.ConstraintType = TargetLowering::C_Address;
10343 }
10344
10345 // If this is a memory input, and if the operand is not indirect, do what we
10346 // need to provide an address for the memory input.
10347 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
10348 !OpInfo.isIndirect) {
10349 assert((OpInfo.isMultipleAlternative ||
10350 (OpInfo.Type == InlineAsm::isInput)) &&
10351 "Can only indirectify direct input operands!");
10352
10353 // Memory operands really want the address of the value.
10354 Info.Chain = getAddressForMemoryInput(Chain: Info.Chain, Location: Builder.getCurSDLoc(),
10355 OpInfo, DAG);
10356
10357 // There is no longer a Value* corresponding to this operand.
10358 OpInfo.CallOperandVal = nullptr;
10359
10360 // It is now an indirect operand.
10361 OpInfo.isIndirect = true;
10362 }
10363 }
10364}
10365
10366/// Prepare DAG-level operands. As part of this, assign virtual and physical
10367/// registers for inputs and output.
10368static bool prepareDAGLevelOperands(ConstraintDecisionInfo &Info,
10369 const CallBase &Call,
10370 SelectionDAGBuilder &Builder,
10371 const TargetLowering &TLI,
10372 SelectionDAG &DAG) {
10373 SDLoc DL = Builder.getCurSDLoc();
10374 for (SDISelAsmOperandInfo &OpInfo : Info.ConstraintOperands) {
10375 // Assign Registers.
10376 SDISelAsmOperandInfo &RefOpInfo =
10377 OpInfo.isMatchingInputConstraint()
10378 ? Info.ConstraintOperands[OpInfo.getMatchedOperand()]
10379 : OpInfo;
10380 const auto RegError = getRegistersForValue(DAG, DL, OpInfo, RefOpInfo);
10381 if (RegError) {
10382 const MachineFunction &MF = DAG.getMachineFunction();
10383 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
10384 const char *RegName = TRI.getName(RegNo: *RegError);
10385 Info.ErrorMsg << "register '" << RegName << "' allocated for constraint '"
10386 << OpInfo.ConstraintCode
10387 << "' does not match required type";
10388 return true;
10389 }
10390
10391 auto DetectWriteToReservedRegister = [&]() {
10392 const MachineFunction &MF = DAG.getMachineFunction();
10393 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
10394
10395 for (Register Reg : OpInfo.AssignedRegs.Regs) {
10396 if (Reg.isPhysical() && TRI.isInlineAsmReadOnlyReg(MF, PhysReg: Reg)) {
10397 Info.ErrorMsg << "write to reserved register '"
10398 << TRI.getRegAsmName(Reg) << "'";
10399 return true;
10400 }
10401 }
10402
10403 return false;
10404 };
10405 assert((OpInfo.ConstraintType != TargetLowering::C_Address ||
10406 (OpInfo.Type == InlineAsm::isInput &&
10407 !OpInfo.isMatchingInputConstraint())) &&
10408 "Only address as input operand is allowed.");
10409
10410 switch (OpInfo.Type) {
10411 case InlineAsm::isOutput:
10412 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
10413 const InlineAsm::ConstraintCode ConstraintID =
10414 TLI.getInlineAsmMemConstraint(ConstraintCode: OpInfo.ConstraintCode);
10415 assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
10416 "Failed to convert memory constraint code to constraint id.");
10417
10418 // Add information to the INLINEASM node to know about this output.
10419 InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
10420 OpFlags.setMemConstraint(ConstraintID);
10421 Info.AsmNodeOperands.push_back(
10422 x: DAG.getTargetConstant(Val: OpFlags, DL, VT: MVT::i32));
10423 Info.AsmNodeOperands.push_back(x: OpInfo.CallOperand);
10424 } else {
10425 // Otherwise, this outputs to a register (directly for C_Register /
10426 // C_RegisterClass, and a target-defined fashion for
10427 // C_Immediate/C_Other). Find a register that we can use.
10428 if (OpInfo.AssignedRegs.Regs.empty()) {
10429 Info.ErrorMsg << "could not allocate output register for "
10430 << "constraint '" << OpInfo.ConstraintCode << "'";
10431 return true;
10432 }
10433
10434 if (DetectWriteToReservedRegister())
10435 return true;
10436
10437 // Add information to the INLINEASM node to know that this register is
10438 // set.
10439 OpInfo.AssignedRegs.AddInlineAsmOperands(
10440 Code: OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
10441 : InlineAsm::Kind::RegDef,
10442 HasMatching: false, MatchingIdx: 0, dl: DL, DAG, Ops&: Info.AsmNodeOperands);
10443 }
10444 break;
10445
10446 case InlineAsm::isInput:
10447 case InlineAsm::isLabel: {
10448 SDValue InOperandVal = OpInfo.CallOperand;
10449
10450 if (OpInfo.isMatchingInputConstraint()) {
10451 // If this is required to match an output register we have already set,
10452 // just use its register.
10453 auto CurOp = findMatchingInlineAsmOperand(OperandNo: OpInfo.getMatchedOperand(),
10454 AsmNodeOperands: Info.AsmNodeOperands);
10455 InlineAsm::Flag Flag(Info.AsmNodeOperands[CurOp]->getAsZExtVal());
10456 if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) {
10457 if (OpInfo.isIndirect) {
10458 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
10459 Info.ErrorMsg << "inline asm not supported yet: cannot handle "
10460 << "tied indirect register inputs";
10461 return true;
10462 }
10463
10464 SmallVector<Register, 4> Regs;
10465 MachineFunction &MF = DAG.getMachineFunction();
10466 MachineRegisterInfo &MRI = MF.getRegInfo();
10467 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
10468 auto *R = cast<RegisterSDNode>(Val&: Info.AsmNodeOperands[CurOp + 1]);
10469 Register TiedReg = R->getReg();
10470 MVT RegVT = R->getSimpleValueType(ResNo: 0);
10471 const TargetRegisterClass *RC =
10472 TiedReg.isVirtual() ? MRI.getRegClass(Reg: TiedReg)
10473 : RegVT != MVT::Untyped ? TLI.getRegClassFor(VT: RegVT)
10474 : TRI.getMinimalPhysRegClass(Reg: TiedReg);
10475 for (unsigned I = 0, E = Flag.getNumOperandRegisters(); I != E; ++I)
10476 Regs.push_back(Elt: MRI.createVirtualRegister(RegClass: RC));
10477
10478 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
10479
10480 // Use the produced MatchedRegs object to
10481 MatchedRegs.getCopyToRegs(Val: InOperandVal, DAG, dl: DL, Chain&: Info.Chain,
10482 Glue: &Info.Glue, V: &Call);
10483 MatchedRegs.AddInlineAsmOperands(Code: InlineAsm::Kind::RegUse, HasMatching: true,
10484 MatchingIdx: OpInfo.getMatchedOperand(), dl: DL, DAG,
10485 Ops&: Info.AsmNodeOperands);
10486 break;
10487 }
10488
10489 assert(Flag.isMemKind() && "Unknown matching constraint!");
10490 assert(Flag.getNumOperandRegisters() == 1 &&
10491 "Unexpected number of operands");
10492
10493 // Add information to the INLINEASM node to know about this input.
10494 // See InlineAsm.h isUseOperandTiedToDef.
10495 Flag.clearMemConstraint();
10496 Flag.setMatchingOp(OpInfo.getMatchedOperand());
10497 Info.AsmNodeOperands.push_back(x: DAG.getTargetConstant(
10498 Val: Flag, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
10499 Info.AsmNodeOperands.push_back(x: Info.AsmNodeOperands[CurOp + 1]);
10500 break;
10501 }
10502
10503 // Treat indirect 'X' constraint as memory.
10504 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
10505 OpInfo.isIndirect)
10506 OpInfo.ConstraintType = TargetLowering::C_Memory;
10507
10508 if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
10509 OpInfo.ConstraintType == TargetLowering::C_Other) {
10510 std::vector<SDValue> Ops;
10511 TLI.LowerAsmOperandForConstraint(Op: InOperandVal, Constraint: OpInfo.ConstraintCode,
10512 Ops, DAG);
10513 if (Ops.empty()) {
10514 if (OpInfo.ConstraintType == TargetLowering::C_Immediate)
10515 if (isa<ConstantSDNode>(Val: InOperandVal)) {
10516 Info.ErrorMsg << "value out of range for constraint '"
10517 << OpInfo.ConstraintCode << "'";
10518 return true;
10519 }
10520
10521 Info.ErrorMsg << "invalid operand for inline asm constraint '"
10522 << OpInfo.ConstraintCode << "'";
10523 return true;
10524 }
10525
10526 // Add information to the INLINEASM node to know about this input.
10527 InlineAsm::Flag ResOpType(InlineAsm::Kind::Imm, Ops.size());
10528 Info.AsmNodeOperands.push_back(x: DAG.getTargetConstant(
10529 Val: ResOpType, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
10530 llvm::append_range(C&: Info.AsmNodeOperands, R&: Ops);
10531 break;
10532 }
10533
10534 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
10535 assert((OpInfo.isIndirect ||
10536 OpInfo.ConstraintType != TargetLowering::C_Memory) &&
10537 "Operand must be indirect to be a mem!");
10538 assert(InOperandVal.getValueType() ==
10539 TLI.getPointerTy(DAG.getDataLayout()) &&
10540 "Memory operands expect pointer values");
10541
10542 const InlineAsm::ConstraintCode ConstraintID =
10543 TLI.getInlineAsmMemConstraint(ConstraintCode: OpInfo.ConstraintCode);
10544 assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
10545 "Failed to convert memory constraint code to constraint id.");
10546
10547 // Add information to the INLINEASM node to know about this input.
10548 InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
10549 ResOpType.setMemConstraint(ConstraintID);
10550 Info.AsmNodeOperands.push_back(
10551 x: DAG.getTargetConstant(Val: ResOpType, DL, VT: MVT::i32));
10552 Info.AsmNodeOperands.push_back(x: InOperandVal);
10553 break;
10554 }
10555
10556 if (OpInfo.ConstraintType == TargetLowering::C_Address) {
10557 const InlineAsm::ConstraintCode ConstraintID =
10558 TLI.getInlineAsmMemConstraint(ConstraintCode: OpInfo.ConstraintCode);
10559 assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
10560 "Failed to convert memory constraint code to constraint id.");
10561
10562 InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
10563
10564 SDValue AsmOp = InOperandVal;
10565 if (isFunction(Op: InOperandVal)) {
10566 auto *GA = cast<GlobalAddressSDNode>(Val&: InOperandVal);
10567 ResOpType = InlineAsm::Flag(InlineAsm::Kind::Func, 1);
10568 AsmOp = DAG.getTargetGlobalAddress(GV: GA->getGlobal(), DL,
10569 VT: InOperandVal.getValueType(),
10570 offset: GA->getOffset());
10571 }
10572
10573 // Add information to the INLINEASM node to know about this input.
10574 ResOpType.setMemConstraint(ConstraintID);
10575
10576 Info.AsmNodeOperands.push_back(
10577 x: DAG.getTargetConstant(Val: ResOpType, DL, VT: MVT::i32));
10578 Info.AsmNodeOperands.push_back(x: AsmOp);
10579 break;
10580 }
10581
10582 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
10583 OpInfo.ConstraintType != TargetLowering::C_Register) {
10584 Info.ErrorMsg << "unknown asm constraint '" << OpInfo.ConstraintCode
10585 << "'";
10586 return true;
10587 }
10588
10589 // TODO: Support this.
10590 if (OpInfo.isIndirect) {
10591 Info.ErrorMsg << "cannot handle indirect register inputs yet for "
10592 << "constraint '" << OpInfo.ConstraintCode << "'";
10593 return true;
10594 }
10595
10596 // Copy the input into the appropriate registers.
10597 if (OpInfo.AssignedRegs.Regs.empty()) {
10598 Info.ErrorMsg << "could not allocate input reg for constraint '"
10599 << OpInfo.ConstraintCode << "'";
10600 return true;
10601 }
10602
10603 if (DetectWriteToReservedRegister())
10604 return true;
10605
10606 OpInfo.AssignedRegs.getCopyToRegs(Val: InOperandVal, DAG, dl: DL, Chain&: Info.Chain,
10607 Glue: &Info.Glue, V: &Call);
10608 OpInfo.AssignedRegs.AddInlineAsmOperands(
10609 Code: InlineAsm::Kind::RegUse, HasMatching: false, MatchingIdx: 0, dl: DL, DAG, Ops&: Info.AsmNodeOperands);
10610 break;
10611 }
10612
10613 case InlineAsm::isClobber:
10614 // Add the clobbered value to the operand list, so that the register
10615 // allocator is aware that the physreg got clobbered.
10616 if (!OpInfo.AssignedRegs.Regs.empty())
10617 OpInfo.AssignedRegs.AddInlineAsmOperands(
10618 Code: InlineAsm::Kind::Clobber, HasMatching: false, MatchingIdx: 0, dl: DL, DAG, Ops&: Info.AsmNodeOperands);
10619 break;
10620 }
10621 }
10622
10623 return false;
10624}
10625
10626/// DetermineConstraints - Find the constraints to use for inline asm operands.
10627static bool
10628determineConstraints(ConstraintDecisionInfo &Info,
10629 TargetLowering::AsmOperandInfoVector &TargetConstraints,
10630 const CallBase &Call, SelectionDAGBuilder &Builder,
10631 const TargetLowering &TLI, const TargetMachine &TM,
10632 SelectionDAG &DAG, const BasicBlock *EHPadBB) {
10633 const auto *IA = cast<InlineAsm>(Val: Call.getCalledOperand());
10634 ExtraFlags ExtraInfo(Call);
10635
10636 // First pass: Construct operand info objects.
10637 Info.HasSideEffect = IA->hasSideEffects();
10638 if (constructOperandInfo(Info, TargetConstraints, Builder, TLI, ExtraInfo))
10639 return true;
10640
10641 // We won't need to flush pending loads if this asm doesn't touch
10642 // memory and is nonvolatile.
10643 Info.Chain = Info.HasSideEffect ? Builder.getRoot() : DAG.getRoot();
10644
10645 bool IsCallBr = isa<CallBrInst>(Val: Call);
10646 bool EmitEHLabels = isa<InvokeInst>(Val: Call);
10647 if (IsCallBr || EmitEHLabels)
10648 // If this is a callbr or invoke we need to flush pending exports since
10649 // inlineasm_br and invoke are terminators.
10650 // We need to do this before nodes are glued to the inlineasm_br node.
10651 Info.Chain = Builder.getControlRoot();
10652
10653 if (EmitEHLabels)
10654 Info.Chain = Builder.lowerStartEH(Chain: Info.Chain, EHPadBB, BeginLabel&: Info.BeginLabel);
10655
10656 // Second pass: Compute which constraint option to use.
10657 computeConstraintToUse(Info, Call, TargetConstraints, Builder, TLI, TM, DAG);
10658
10659 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
10660 Info.AsmNodeOperands.push_back(x: SDValue()); // reserve space for input chain
10661 Info.AsmNodeOperands.push_back(x: DAG.getTargetExternalSymbol(
10662 Sym: IA->getAsmString().data(), VT: TLI.getProgramPointerTy(DL: DAG.getDataLayout())));
10663
10664 // If we have a !srcloc metadata node associated with it, we want to attach
10665 // this to the ultimately generated inline asm machineinstr. To do this, we
10666 // pass in the third operand as this (potentially null) inline asm MDNode.
10667 const MDNode *SrcLoc = Call.getMetadata(Kind: "srcloc");
10668 Info.AsmNodeOperands.push_back(x: DAG.getMDNode(MD: SrcLoc));
10669
10670 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
10671 // bits as operand 3.
10672 Info.AsmNodeOperands.push_back(
10673 x: DAG.getTargetConstant(Val: ExtraInfo.get(), DL: Builder.getCurSDLoc(),
10674 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
10675
10676 // Third pass: Prepare DAG-level operands
10677 return prepareDAGLevelOperands(Info, Call, Builder, TLI, DAG);
10678}
10679
10680/// visitInlineAsm - Handle a call to an InlineAsm object.
10681void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
10682 const BasicBlock *EHPadBB) {
10683 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10684 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
10685 DL: DAG.getDataLayout(), TRI: DAG.getSubtarget().getRegisterInfo(), Call);
10686
10687 assert((!isa<InvokeInst>(Call) || EHPadBB) &&
10688 "InvokeInst must have an EHPadBB");
10689
10690 ConstraintDecisionInfo Info;
10691 if (determineConstraints(Info, TargetConstraints, Call, Builder&: *this, TLI, TM, DAG,
10692 EHPadBB))
10693 return emitInlineAsmError(Call, Message: Info.ErrorMsg.str());
10694
10695 SDValue Glue = Info.Glue;
10696 SDValue Chain = Info.Chain;
10697
10698 // Finish up input operands. Set the input chain and add the flag last.
10699 Info.AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
10700 if (Glue.getNode())
10701 Info.AsmNodeOperands.push_back(x: Glue);
10702
10703 bool IsCallBr = isa<CallBrInst>(Val: Call);
10704 unsigned ISDOpc = IsCallBr ? ISD::INLINEASM_BR : ISD::INLINEASM;
10705 Chain =
10706 DAG.getNode(Opcode: ISDOpc, DL: getCurSDLoc(), VTList: DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue),
10707 Ops: Info.AsmNodeOperands);
10708 Glue = Chain.getValue(R: 1);
10709
10710 // Do additional work to generate outputs.
10711
10712 SmallVector<EVT, 1> ResultVTs;
10713 SmallVector<SDValue, 1> ResultValues;
10714 SmallVector<SDValue, 8> OutChains;
10715
10716 llvm::Type *CallResultType = Call.getType();
10717 ArrayRef<Type *> ResultTypes;
10718 if (StructType *StructResult = dyn_cast<StructType>(Val: CallResultType))
10719 ResultTypes = StructResult->elements();
10720 else if (!CallResultType->isVoidTy())
10721 ResultTypes = ArrayRef(CallResultType);
10722
10723 auto CurResultType = ResultTypes.begin();
10724 auto handleRegAssign = [&](SDValue V) {
10725 assert(CurResultType != ResultTypes.end() && "Unexpected value");
10726 assert((*CurResultType)->isSized() && "Unexpected unsized type");
10727 EVT ResultVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: *CurResultType);
10728 ++CurResultType;
10729 // If the type of the inline asm call site return value is different but has
10730 // same size as the type of the asm output bitcast it. One example of this
10731 // is for vectors with different width / number of elements. This can
10732 // happen for register classes that can contain multiple different value
10733 // types. The preg or vreg allocated may not have the same VT as was
10734 // expected.
10735 //
10736 // This can also happen for a return value that disagrees with the register
10737 // class it is put in, eg. a double in a general-purpose register on a
10738 // 32-bit machine.
10739 if (ResultVT != V.getValueType() &&
10740 ResultVT.getSizeInBits() == V.getValueSizeInBits())
10741 V = DAG.getNode(Opcode: ISD::BITCAST, DL: getCurSDLoc(), VT: ResultVT, Operand: V);
10742 else if (ResultVT != V.getValueType() && ResultVT.isInteger() &&
10743 V.getValueType().isInteger()) {
10744 // If a result value was tied to an input value, the computed result
10745 // may have a wider width than the expected result. Extract the
10746 // relevant portion.
10747 V = DAG.getNode(Opcode: ISD::TRUNCATE, DL: getCurSDLoc(), VT: ResultVT, Operand: V);
10748 }
10749 assert(ResultVT == V.getValueType() && "Asm result value mismatch!");
10750 ResultVTs.push_back(Elt: ResultVT);
10751 ResultValues.push_back(Elt: V);
10752 };
10753
10754 // Deal with output operands.
10755 for (SDISelAsmOperandInfo &OpInfo : Info.ConstraintOperands) {
10756 if (OpInfo.Type == InlineAsm::isOutput) {
10757 SDValue Val;
10758 // Skip trivial output operands.
10759 if (OpInfo.AssignedRegs.Regs.empty())
10760 continue;
10761
10762 switch (OpInfo.ConstraintType) {
10763 case TargetLowering::C_Register:
10764 case TargetLowering::C_RegisterClass:
10765 Val = OpInfo.AssignedRegs.getCopyFromRegs(DAG, FuncInfo, dl: getCurSDLoc(),
10766 Chain, Glue: &Glue, V: &Call);
10767 break;
10768 case TargetLowering::C_Immediate:
10769 case TargetLowering::C_Other:
10770 Val = TLI.LowerAsmOutputForConstraint(Chain, Glue, DL: getCurSDLoc(),
10771 OpInfo, DAG);
10772 break;
10773 case TargetLowering::C_Memory:
10774 break; // Already handled.
10775 case TargetLowering::C_Address:
10776 break; // Silence warning.
10777 case TargetLowering::C_Unknown:
10778 assert(false && "Unexpected unknown constraint");
10779 }
10780
10781 // Indirect output manifest as stores. Record output chains.
10782 if (OpInfo.isIndirect) {
10783 const Value *Ptr = OpInfo.CallOperandVal;
10784 assert(Ptr && "Expected value CallOperandVal for indirect asm operand");
10785 SDValue Store = DAG.getStore(Chain, dl: getCurSDLoc(), Val, Ptr: getValue(V: Ptr),
10786 PtrInfo: MachinePointerInfo(Ptr));
10787 OutChains.push_back(Elt: Store);
10788 } else {
10789 // generate CopyFromRegs to associated registers.
10790 assert(!Call.getType()->isVoidTy() && "Bad inline asm!");
10791 if (Val.getOpcode() == ISD::MERGE_VALUES) {
10792 for (const SDValue &V : Val->op_values())
10793 handleRegAssign(V);
10794 } else
10795 handleRegAssign(Val);
10796 }
10797 }
10798 }
10799
10800 // Set results.
10801 if (!ResultValues.empty()) {
10802 assert(CurResultType == ResultTypes.end() &&
10803 "Mismatch in number of ResultTypes");
10804 assert(ResultValues.size() == ResultTypes.size() &&
10805 "Mismatch in number of output operands in asm result");
10806
10807 SDValue V = DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
10808 VTList: DAG.getVTList(VTs: ResultVTs), Ops: ResultValues);
10809 setValue(V: &Call, NewN: V);
10810 }
10811
10812 // Collect store chains.
10813 if (!OutChains.empty())
10814 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: getCurSDLoc(), VT: MVT::Other, Ops: OutChains);
10815
10816 if (const auto *II = dyn_cast<InvokeInst>(Val: &Call))
10817 Chain = lowerEndEH(Chain, II, EHPadBB, BeginLabel: Info.BeginLabel);
10818
10819 // Only Update Root if inline assembly has a memory effect.
10820 if (ResultValues.empty() || Info.HasSideEffect || !OutChains.empty() ||
10821 IsCallBr || isa<InvokeInst>(Val: Call))
10822 DAG.setRoot(Chain);
10823}
10824
10825void SelectionDAGBuilder::emitInlineAsmError(const CallBase &Call,
10826 const Twine &Message) {
10827 LLVMContext &Ctx = *DAG.getContext();
10828 Ctx.diagnose(DI: DiagnosticInfoInlineAsm(Call, Message));
10829
10830 // Make sure we leave the DAG in a valid state
10831 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10832 SmallVector<EVT, 1> ValueVTs;
10833 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: Call.getType(), ValueVTs);
10834
10835 if (ValueVTs.empty())
10836 return;
10837
10838 SmallVector<SDValue, 1> Ops;
10839 for (const EVT &VT : ValueVTs)
10840 Ops.push_back(Elt: DAG.getUNDEF(VT));
10841
10842 setValue(V: &Call, NewN: DAG.getMergeValues(Ops, dl: getCurSDLoc()));
10843}
10844
10845void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
10846 DAG.setRoot(DAG.getNode(Opcode: ISD::VASTART, DL: getCurSDLoc(),
10847 VT: MVT::Other, N1: getRoot(),
10848 N2: getValue(V: I.getArgOperand(i: 0)),
10849 N3: DAG.getSrcValue(v: I.getArgOperand(i: 0))));
10850}
10851
10852void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
10853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10854 const DataLayout &DL = DAG.getDataLayout();
10855 SDValue V = DAG.getVAArg(
10856 VT: TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getType()), dl: getCurSDLoc(),
10857 Chain: getRoot(), Ptr: getValue(V: I.getOperand(i_nocapture: 0)), SV: DAG.getSrcValue(v: I.getOperand(i_nocapture: 0)),
10858 Align: DL.getABITypeAlign(Ty: I.getType()).value());
10859 DAG.setRoot(V.getValue(R: 1));
10860
10861 if (I.getType()->isPointerTy())
10862 V = DAG.getPtrExtOrTrunc(
10863 Op: V, DL: getCurSDLoc(), VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()));
10864 setValue(V: &I, NewN: V);
10865}
10866
10867void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
10868 DAG.setRoot(DAG.getNode(Opcode: ISD::VAEND, DL: getCurSDLoc(),
10869 VT: MVT::Other, N1: getRoot(),
10870 N2: getValue(V: I.getArgOperand(i: 0)),
10871 N3: DAG.getSrcValue(v: I.getArgOperand(i: 0))));
10872}
10873
10874void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
10875 DAG.setRoot(DAG.getNode(Opcode: ISD::VACOPY, DL: getCurSDLoc(),
10876 VT: MVT::Other, N1: getRoot(),
10877 N2: getValue(V: I.getArgOperand(i: 0)),
10878 N3: getValue(V: I.getArgOperand(i: 1)),
10879 N4: DAG.getSrcValue(v: I.getArgOperand(i: 0)),
10880 N5: DAG.getSrcValue(v: I.getArgOperand(i: 1))));
10881}
10882
10883SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
10884 const Instruction &I,
10885 SDValue Op) {
10886 std::optional<ConstantRange> CR = getRange(I);
10887
10888 if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
10889 return Op;
10890
10891 APInt Hi = CR->getUnsignedMax();
10892 unsigned Bits = std::max(a: Hi.getActiveBits(),
10893 b: static_cast<unsigned>(IntegerType::MIN_INT_BITS));
10894
10895 EVT SmallVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: Bits);
10896
10897 SDLoc SL = getCurSDLoc();
10898
10899 SDValue ZExt = DAG.getNode(Opcode: ISD::AssertZext, DL: SL, VT: Op.getValueType(), N1: Op,
10900 N2: DAG.getValueType(SmallVT));
10901 unsigned NumVals = Op.getNode()->getNumValues();
10902 if (NumVals == 1)
10903 return ZExt;
10904
10905 SmallVector<SDValue, 4> Ops;
10906
10907 Ops.push_back(Elt: ZExt);
10908 for (unsigned I = 1; I != NumVals; ++I)
10909 Ops.push_back(Elt: Op.getValue(R: I));
10910
10911 return DAG.getMergeValues(Ops, dl: SL);
10912}
10913
10914SDValue SelectionDAGBuilder::lowerNoFPClassToAssertNoFPClass(
10915 SelectionDAG &DAG, const Instruction &I, SDValue Op) {
10916 FPClassTest Classes = getNoFPClass(I);
10917 if (Classes == fcNone)
10918 return Op;
10919
10920 SDLoc SL = getCurSDLoc();
10921 SDValue TestConst = DAG.getTargetConstant(Val: Classes, DL: SDLoc(), VT: MVT::i32);
10922
10923 if (Op.getOpcode() != ISD::MERGE_VALUES) {
10924 return DAG.getNode(Opcode: ISD::AssertNoFPClass, DL: SL, VT: Op.getValueType(), N1: Op,
10925 N2: TestConst);
10926 }
10927
10928 SmallVector<SDValue, 8> Ops(Op.getNumOperands());
10929 for (unsigned I = 0, E = Ops.size(); I != E; ++I) {
10930 SDValue MergeOp = Op.getOperand(i: I);
10931 Ops[I] = DAG.getNode(Opcode: ISD::AssertNoFPClass, DL: SL, VT: MergeOp.getValueType(),
10932 N1: MergeOp, N2: TestConst);
10933 }
10934
10935 return DAG.getMergeValues(Ops, dl: SL);
10936}
10937
10938/// Populate a CallLowerinInfo (into \p CLI) based on the properties of
10939/// the call being lowered.
10940///
10941/// This is a helper for lowering intrinsics that follow a target calling
10942/// convention or require stack pointer adjustment. Only a subset of the
10943/// intrinsic's operands need to participate in the calling convention.
10944void SelectionDAGBuilder::populateCallLoweringInfo(
10945 TargetLowering::CallLoweringInfo &CLI, const CallBase *Call,
10946 unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy,
10947 AttributeSet RetAttrs, bool IsPatchPoint) {
10948 TargetLowering::ArgListTy Args;
10949 Args.reserve(n: NumArgs);
10950
10951 // Populate the argument list.
10952 // Attributes for args start at offset 1, after the return attribute.
10953 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs;
10954 ArgI != ArgE; ++ArgI) {
10955 const Value *V = Call->getOperand(i_nocapture: ArgI);
10956
10957 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
10958
10959 TargetLowering::ArgListEntry Entry(getValue(V), V->getType());
10960 Entry.setAttributes(Call, ArgIdx: ArgI);
10961 Args.push_back(x: Entry);
10962 }
10963
10964 CLI.setDebugLoc(getCurSDLoc())
10965 .setChain(getRoot())
10966 .setCallee(CC: Call->getCallingConv(), ResultType: ReturnTy, Target: Callee, ArgsList: std::move(Args),
10967 ResultAttrs: RetAttrs)
10968 .setDiscardResult(Call->use_empty())
10969 .setIsPatchPoint(IsPatchPoint)
10970 .setIsPreallocated(
10971 Call->countOperandBundlesOfType(ID: LLVMContext::OB_preallocated) != 0);
10972}
10973
10974/// Add a stack map intrinsic call's live variable operands to a stackmap
10975/// or patchpoint target node's operand list.
10976///
10977/// Constants are converted to TargetConstants purely as an optimization to
10978/// avoid constant materialization and register allocation.
10979///
10980/// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
10981/// generate addess computation nodes, and so FinalizeISel can convert the
10982/// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
10983/// address materialization and register allocation, but may also be required
10984/// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
10985/// alloca in the entry block, then the runtime may assume that the alloca's
10986/// StackMap location can be read immediately after compilation and that the
10987/// location is valid at any point during execution (this is similar to the
10988/// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
10989/// only available in a register, then the runtime would need to trap when
10990/// execution reaches the StackMap in order to read the alloca's location.
10991static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx,
10992 const SDLoc &DL, SmallVectorImpl<SDValue> &Ops,
10993 SelectionDAGBuilder &Builder) {
10994 SelectionDAG &DAG = Builder.DAG;
10995 for (unsigned I = StartIdx; I < Call.arg_size(); I++) {
10996 SDValue Op = Builder.getValue(V: Call.getArgOperand(i: I));
10997
10998 // Things on the stack are pointer-typed, meaning that they are already
10999 // legal and can be emitted directly to target nodes.
11000 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Val&: Op)) {
11001 Ops.push_back(Elt: DAG.getTargetFrameIndex(FI: FI->getIndex(), VT: Op.getValueType()));
11002 } else {
11003 // Otherwise emit a target independent node to be legalised.
11004 Ops.push_back(Elt: Builder.getValue(V: Call.getArgOperand(i: I)));
11005 }
11006 }
11007}
11008
11009/// Lower llvm.experimental.stackmap.
11010void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
11011 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
11012 // [live variables...])
11013
11014 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
11015
11016 SDValue Chain, InGlue, Callee;
11017 SmallVector<SDValue, 32> Ops;
11018
11019 SDLoc DL = getCurSDLoc();
11020 Callee = getValue(V: CI.getCalledOperand());
11021
11022 // The stackmap intrinsic only records the live variables (the arguments
11023 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
11024 // intrinsic, this won't be lowered to a function call. This means we don't
11025 // have to worry about calling conventions and target specific lowering code.
11026 // Instead we perform the call lowering right here.
11027 //
11028 // chain, flag = CALLSEQ_START(chain, 0, 0)
11029 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
11030 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
11031 //
11032 Chain = DAG.getCALLSEQ_START(Chain: getRoot(), InSize: 0, OutSize: 0, DL);
11033 InGlue = Chain.getValue(R: 1);
11034
11035 // Add the STACKMAP operands, starting with DAG house-keeping.
11036 Ops.push_back(Elt: Chain);
11037 Ops.push_back(Elt: InGlue);
11038
11039 // Add the <id>, <numShadowBytes> operands.
11040 //
11041 // These do not require legalisation, and can be emitted directly to target
11042 // constant nodes.
11043 SDValue ID = getValue(V: CI.getArgOperand(i: 0));
11044 assert(ID.getValueType() == MVT::i64);
11045 SDValue IDConst =
11046 DAG.getTargetConstant(Val: ID->getAsZExtVal(), DL, VT: ID.getValueType());
11047 Ops.push_back(Elt: IDConst);
11048
11049 SDValue Shad = getValue(V: CI.getArgOperand(i: 1));
11050 assert(Shad.getValueType() == MVT::i32);
11051 SDValue ShadConst =
11052 DAG.getTargetConstant(Val: Shad->getAsZExtVal(), DL, VT: Shad.getValueType());
11053 Ops.push_back(Elt: ShadConst);
11054
11055 // Add the live variables.
11056 addStackMapLiveVars(Call: CI, StartIdx: 2, DL, Ops, Builder&: *this);
11057
11058 // Create the STACKMAP node.
11059 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
11060 Chain = DAG.getNode(Opcode: ISD::STACKMAP, DL, VTList: NodeTys, Ops);
11061 InGlue = Chain.getValue(R: 1);
11062
11063 Chain = DAG.getCALLSEQ_END(Chain, Size1: 0, Size2: 0, Glue: InGlue, DL);
11064
11065 // Stackmaps don't generate values, so nothing goes into the NodeMap.
11066
11067 // Set the root to the target-lowered call chain.
11068 DAG.setRoot(Chain);
11069
11070 // Inform the Frame Information that we have a stackmap in this function.
11071 FuncInfo.MF->getFrameInfo().setHasStackMap();
11072}
11073
11074/// Lower llvm.experimental.patchpoint directly to its target opcode.
11075void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB,
11076 const BasicBlock *EHPadBB) {
11077 // <ty> @llvm.experimental.patchpoint.<ty>(i64 <id>,
11078 // i32 <numBytes>,
11079 // i8* <target>,
11080 // i32 <numArgs>,
11081 // [Args...],
11082 // [live variables...])
11083
11084 CallingConv::ID CC = CB.getCallingConv();
11085 bool IsAnyRegCC = CC == CallingConv::AnyReg;
11086 bool HasDef = !CB.getType()->isVoidTy();
11087 SDLoc dl = getCurSDLoc();
11088 SDValue Callee = getValue(V: CB.getArgOperand(i: PatchPointOpers::TargetPos));
11089
11090 // Handle immediate and symbolic callees.
11091 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Val&: Callee))
11092 Callee = DAG.getIntPtrConstant(Val: ConstCallee->getZExtValue(), DL: dl,
11093 /*isTarget=*/true);
11094 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
11095 Callee = DAG.getTargetGlobalAddress(GV: SymbolicCallee->getGlobal(),
11096 DL: SDLoc(SymbolicCallee),
11097 VT: SymbolicCallee->getValueType(ResNo: 0));
11098
11099 // Get the real number of arguments participating in the call <numArgs>
11100 SDValue NArgVal = getValue(V: CB.getArgOperand(i: PatchPointOpers::NArgPos));
11101 unsigned NumArgs = NArgVal->getAsZExtVal();
11102
11103 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
11104 // Intrinsics include all meta-operands up to but not including CC.
11105 unsigned NumMetaOpers = PatchPointOpers::CCPos;
11106 assert(CB.arg_size() >= NumMetaOpers + NumArgs &&
11107 "Not enough arguments provided to the patchpoint intrinsic");
11108
11109 // For AnyRegCC the arguments are lowered later on manually.
11110 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
11111 Type *ReturnTy =
11112 IsAnyRegCC ? Type::getVoidTy(C&: *DAG.getContext()) : CB.getType();
11113
11114 TargetLowering::CallLoweringInfo CLI(DAG);
11115 populateCallLoweringInfo(CLI, Call: &CB, ArgIdx: NumMetaOpers, NumArgs: NumCallArgs, Callee,
11116 ReturnTy, RetAttrs: CB.getAttributes().getRetAttrs(), IsPatchPoint: true);
11117 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
11118
11119 SDNode *CallEnd = Result.second.getNode();
11120 if (CallEnd->getOpcode() == ISD::EH_LABEL)
11121 CallEnd = CallEnd->getOperand(Num: 0).getNode();
11122 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
11123 CallEnd = CallEnd->getOperand(Num: 0).getNode();
11124
11125 /// Get a call instruction from the call sequence chain.
11126 /// Tail calls are not allowed.
11127 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
11128 "Expected a callseq node.");
11129 SDNode *Call = CallEnd->getOperand(Num: 0).getNode();
11130 bool HasGlue = Call->getGluedNode();
11131
11132 // Replace the target specific call node with the patchable intrinsic.
11133 SmallVector<SDValue, 8> Ops;
11134
11135 // Push the chain.
11136 Ops.push_back(Elt: *(Call->op_begin()));
11137
11138 // Optionally, push the glue (if any).
11139 if (HasGlue)
11140 Ops.push_back(Elt: *(Call->op_end() - 1));
11141
11142 // Push the register mask info.
11143 if (HasGlue)
11144 Ops.push_back(Elt: *(Call->op_end() - 2));
11145 else
11146 Ops.push_back(Elt: *(Call->op_end() - 1));
11147
11148 // Add the <id> and <numBytes> constants.
11149 SDValue IDVal = getValue(V: CB.getArgOperand(i: PatchPointOpers::IDPos));
11150 Ops.push_back(Elt: DAG.getTargetConstant(Val: IDVal->getAsZExtVal(), DL: dl, VT: MVT::i64));
11151 SDValue NBytesVal = getValue(V: CB.getArgOperand(i: PatchPointOpers::NBytesPos));
11152 Ops.push_back(Elt: DAG.getTargetConstant(Val: NBytesVal->getAsZExtVal(), DL: dl, VT: MVT::i32));
11153
11154 // Add the callee.
11155 Ops.push_back(Elt: Callee);
11156
11157 // Adjust <numArgs> to account for any arguments that have been passed on the
11158 // stack instead.
11159 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
11160 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
11161 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
11162 Ops.push_back(Elt: DAG.getTargetConstant(Val: NumCallRegArgs, DL: dl, VT: MVT::i32));
11163
11164 // Add the calling convention
11165 Ops.push_back(Elt: DAG.getTargetConstant(Val: (unsigned)CC, DL: dl, VT: MVT::i32));
11166
11167 // Add the arguments we omitted previously. The register allocator should
11168 // place these in any free register.
11169 if (IsAnyRegCC)
11170 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
11171 Ops.push_back(Elt: getValue(V: CB.getArgOperand(i)));
11172
11173 // Push the arguments from the call instruction.
11174 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
11175 Ops.append(in_start: Call->op_begin() + 2, in_end: e);
11176
11177 // Push live variables for the stack map.
11178 addStackMapLiveVars(Call: CB, StartIdx: NumMetaOpers + NumArgs, DL: dl, Ops, Builder&: *this);
11179
11180 SDVTList NodeTys;
11181 if (IsAnyRegCC && HasDef) {
11182 // Create the return types based on the intrinsic definition
11183 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11184 SmallVector<EVT, 3> ValueVTs;
11185 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: CB.getType(), ValueVTs);
11186 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
11187
11188 // There is always a chain and a glue type at the end
11189 ValueVTs.push_back(Elt: MVT::Other);
11190 ValueVTs.push_back(Elt: MVT::Glue);
11191 NodeTys = DAG.getVTList(VTs: ValueVTs);
11192 } else
11193 NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
11194
11195 // Replace the target specific call node with a PATCHPOINT node.
11196 SDValue PPV = DAG.getNode(Opcode: ISD::PATCHPOINT, DL: dl, VTList: NodeTys, Ops);
11197
11198 // Update the NodeMap.
11199 if (HasDef) {
11200 if (IsAnyRegCC)
11201 setValue(V: &CB, NewN: SDValue(PPV.getNode(), 0));
11202 else
11203 setValue(V: &CB, NewN: Result.first);
11204 }
11205
11206 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
11207 // call sequence. Furthermore the location of the chain and glue can change
11208 // when the AnyReg calling convention is used and the intrinsic returns a
11209 // value.
11210 if (IsAnyRegCC && HasDef) {
11211 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
11212 SDValue To[] = {PPV.getValue(R: 1), PPV.getValue(R: 2)};
11213 DAG.ReplaceAllUsesOfValuesWith(From, To, Num: 2);
11214 } else
11215 DAG.ReplaceAllUsesWith(From: Call, To: PPV.getNode());
11216 DAG.DeleteNode(N: Call);
11217
11218 // Inform the Frame Information that we have a patchpoint in this function.
11219 FuncInfo.MF->getFrameInfo().setHasPatchPoint();
11220}
11221
11222void SelectionDAGBuilder::visitVectorReduce(const CallInst &I,
11223 unsigned Intrinsic) {
11224 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11225 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
11226 SDValue Op2;
11227 if (I.arg_size() > 1)
11228 Op2 = getValue(V: I.getArgOperand(i: 1));
11229 SDLoc dl = getCurSDLoc();
11230 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
11231 SDValue Res;
11232 SDNodeFlags SDFlags;
11233 if (auto *FPMO = dyn_cast<FPMathOperator>(Val: &I))
11234 SDFlags.copyFMF(FPMO: *FPMO);
11235
11236 switch (Intrinsic) {
11237 case Intrinsic::vector_reduce_fadd:
11238 if (SDFlags.hasAllowReassociation())
11239 Res = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT, N1: Op1,
11240 N2: DAG.getNode(Opcode: ISD::VECREDUCE_FADD, DL: dl, VT, Operand: Op2, Flags: SDFlags),
11241 Flags: SDFlags);
11242 else
11243 Res = DAG.getNode(Opcode: ISD::VECREDUCE_SEQ_FADD, DL: dl, VT, N1: Op1, N2: Op2, Flags: SDFlags);
11244 break;
11245 case Intrinsic::vector_reduce_fmul:
11246 if (SDFlags.hasAllowReassociation())
11247 Res = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: Op1,
11248 N2: DAG.getNode(Opcode: ISD::VECREDUCE_FMUL, DL: dl, VT, Operand: Op2, Flags: SDFlags),
11249 Flags: SDFlags);
11250 else
11251 Res = DAG.getNode(Opcode: ISD::VECREDUCE_SEQ_FMUL, DL: dl, VT, N1: Op1, N2: Op2, Flags: SDFlags);
11252 break;
11253 case Intrinsic::vector_reduce_add:
11254 Res = DAG.getNode(Opcode: ISD::VECREDUCE_ADD, DL: dl, VT, Operand: Op1);
11255 break;
11256 case Intrinsic::vector_reduce_mul:
11257 Res = DAG.getNode(Opcode: ISD::VECREDUCE_MUL, DL: dl, VT, Operand: Op1);
11258 break;
11259 case Intrinsic::vector_reduce_and:
11260 Res = DAG.getNode(Opcode: ISD::VECREDUCE_AND, DL: dl, VT, Operand: Op1);
11261 break;
11262 case Intrinsic::vector_reduce_or:
11263 Res = DAG.getNode(Opcode: ISD::VECREDUCE_OR, DL: dl, VT, Operand: Op1);
11264 break;
11265 case Intrinsic::vector_reduce_xor:
11266 Res = DAG.getNode(Opcode: ISD::VECREDUCE_XOR, DL: dl, VT, Operand: Op1);
11267 break;
11268 case Intrinsic::vector_reduce_smax:
11269 Res = DAG.getNode(Opcode: ISD::VECREDUCE_SMAX, DL: dl, VT, Operand: Op1);
11270 break;
11271 case Intrinsic::vector_reduce_smin:
11272 Res = DAG.getNode(Opcode: ISD::VECREDUCE_SMIN, DL: dl, VT, Operand: Op1);
11273 break;
11274 case Intrinsic::vector_reduce_umax:
11275 Res = DAG.getNode(Opcode: ISD::VECREDUCE_UMAX, DL: dl, VT, Operand: Op1);
11276 break;
11277 case Intrinsic::vector_reduce_umin:
11278 Res = DAG.getNode(Opcode: ISD::VECREDUCE_UMIN, DL: dl, VT, Operand: Op1);
11279 break;
11280 case Intrinsic::vector_reduce_fmax:
11281 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMAX, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11282 break;
11283 case Intrinsic::vector_reduce_fmin:
11284 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMIN, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11285 break;
11286 case Intrinsic::vector_reduce_fmaximum:
11287 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMAXIMUM, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11288 break;
11289 case Intrinsic::vector_reduce_fminimum:
11290 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMINIMUM, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11291 break;
11292 case Intrinsic::vector_reduce_fmaximumnum:
11293 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMAXIMUMNUM, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11294 break;
11295 case Intrinsic::vector_reduce_fminimumnum:
11296 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMINIMUMNUM, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11297 break;
11298 default:
11299 llvm_unreachable("Unhandled vector reduce intrinsic");
11300 }
11301 setValue(V: &I, NewN: Res);
11302}
11303
11304/// Returns an AttributeList representing the attributes applied to the return
11305/// value of the given call.
11306static AttributeList getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
11307 SmallVector<Attribute::AttrKind, 2> Attrs;
11308 if (CLI.RetSExt)
11309 Attrs.push_back(Elt: Attribute::SExt);
11310 if (CLI.RetZExt)
11311 Attrs.push_back(Elt: Attribute::ZExt);
11312 if (CLI.IsInReg)
11313 Attrs.push_back(Elt: Attribute::InReg);
11314
11315 return AttributeList::get(C&: CLI.RetTy->getContext(), Index: AttributeList::ReturnIndex,
11316 Kinds: Attrs);
11317}
11318
11319/// TargetLowering::LowerCallTo - This is the default LowerCallTo
11320/// implementation, which just calls LowerCall.
11321/// FIXME: When all targets are
11322/// migrated to using LowerCall, this hook should be integrated into SDISel.
11323std::pair<SDValue, SDValue>
11324TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
11325 LLVMContext &Context = CLI.RetTy->getContext();
11326
11327 // Handle the incoming return values from the call.
11328 CLI.Ins.clear();
11329 SmallVector<Type *, 4> RetOrigTys;
11330 SmallVector<TypeSize, 4> Offsets;
11331 auto &DL = CLI.DAG.getDataLayout();
11332 ComputeValueTypes(DL, Ty: CLI.OrigRetTy, Types&: RetOrigTys, Offsets: &Offsets);
11333
11334 SmallVector<EVT, 4> RetVTs;
11335 if (CLI.RetTy != CLI.OrigRetTy) {
11336 assert(RetOrigTys.size() == 1 &&
11337 "Only supported for non-aggregate returns");
11338 RetVTs.push_back(Elt: getValueType(DL, Ty: CLI.RetTy));
11339 } else {
11340 for (Type *Ty : RetOrigTys)
11341 RetVTs.push_back(Elt: getValueType(DL, Ty));
11342 }
11343
11344 if (CLI.IsPostTypeLegalization) {
11345 // If we are lowering a libcall after legalization, split the return type.
11346 SmallVector<Type *, 4> OldRetOrigTys;
11347 SmallVector<EVT, 4> OldRetVTs;
11348 SmallVector<TypeSize, 4> OldOffsets;
11349 RetOrigTys.swap(RHS&: OldRetOrigTys);
11350 RetVTs.swap(RHS&: OldRetVTs);
11351 Offsets.swap(RHS&: OldOffsets);
11352
11353 for (size_t i = 0, e = OldRetVTs.size(); i != e; ++i) {
11354 EVT RetVT = OldRetVTs[i];
11355 uint64_t Offset = OldOffsets[i];
11356 MVT RegisterVT = getRegisterType(Context, VT: RetVT);
11357 unsigned NumRegs = getNumRegisters(Context, VT: RetVT);
11358 unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8;
11359 RetOrigTys.append(NumInputs: NumRegs, Elt: OldRetOrigTys[i]);
11360 RetVTs.append(NumInputs: NumRegs, Elt: RegisterVT);
11361 for (unsigned j = 0; j != NumRegs; ++j)
11362 Offsets.push_back(Elt: TypeSize::getFixed(ExactSize: Offset + j * RegisterVTByteSZ));
11363 }
11364 }
11365
11366 SmallVector<ISD::OutputArg, 4> Outs;
11367 GetReturnInfo(CC: CLI.CallConv, ReturnType: CLI.RetTy, attr: getReturnAttrs(CLI), Outs, TLI: *this, DL);
11368
11369 bool CanLowerReturn =
11370 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
11371 CLI.IsVarArg, Outs, Context, RetTy: CLI.RetTy);
11372
11373 SDValue DemoteStackSlot;
11374 int DemoteStackIdx = -100;
11375 if (!CanLowerReturn) {
11376 // FIXME: equivalent assert?
11377 // assert(!CS.hasInAllocaArgument() &&
11378 // "sret demotion is incompatible with inalloca");
11379 uint64_t TySize = DL.getTypeAllocSize(Ty: CLI.RetTy);
11380 Align Alignment = DL.getPrefTypeAlign(Ty: CLI.RetTy);
11381 MachineFunction &MF = CLI.DAG.getMachineFunction();
11382 DemoteStackIdx =
11383 MF.getFrameInfo().CreateStackObject(Size: TySize, Alignment, isSpillSlot: false);
11384 Type *StackSlotPtrType = PointerType::get(C&: Context, AddressSpace: DL.getAllocaAddrSpace());
11385
11386 DemoteStackSlot = CLI.DAG.getFrameIndex(FI: DemoteStackIdx, VT: getFrameIndexTy(DL));
11387 ArgListEntry Entry(DemoteStackSlot, StackSlotPtrType);
11388 Entry.IsSRet = true;
11389 Entry.Alignment = Alignment;
11390 CLI.getArgs().insert(position: CLI.getArgs().begin(), x: Entry);
11391 CLI.NumFixedArgs += 1;
11392 CLI.getArgs()[0].IndirectType = CLI.RetTy;
11393 CLI.RetTy = CLI.OrigRetTy = Type::getVoidTy(C&: Context);
11394
11395 // sret demotion isn't compatible with tail-calls, since the sret argument
11396 // points into the callers stack frame.
11397 CLI.IsTailCall = false;
11398 } else {
11399 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
11400 Ty: CLI.RetTy, CallConv: CLI.CallConv, isVarArg: CLI.IsVarArg, DL);
11401 for (unsigned I = 0, E = RetVTs.size(); I != E; ++I) {
11402 ISD::ArgFlagsTy Flags;
11403 if (NeedsRegBlock) {
11404 Flags.setInConsecutiveRegs();
11405 if (I == RetVTs.size() - 1)
11406 Flags.setInConsecutiveRegsLast();
11407 }
11408 EVT VT = RetVTs[I];
11409 MVT RegisterVT = getRegisterTypeForCallingConv(Context, CC: CLI.CallConv, VT);
11410 unsigned NumRegs =
11411 getNumRegistersForCallingConv(Context, CC: CLI.CallConv, VT);
11412 for (unsigned i = 0; i != NumRegs; ++i) {
11413 ISD::InputArg Ret(Flags, RegisterVT, VT, RetOrigTys[I],
11414 CLI.IsReturnValueUsed, ISD::InputArg::NoArgIndex, 0);
11415 if (CLI.RetTy->isPointerTy()) {
11416 Ret.Flags.setPointer();
11417 Ret.Flags.setPointerAddrSpace(
11418 cast<PointerType>(Val: CLI.RetTy)->getAddressSpace());
11419 }
11420 if (CLI.RetSExt)
11421 Ret.Flags.setSExt();
11422 if (CLI.RetZExt)
11423 Ret.Flags.setZExt();
11424 if (CLI.IsInReg)
11425 Ret.Flags.setInReg();
11426 CLI.Ins.push_back(Elt: Ret);
11427 }
11428 }
11429 }
11430
11431 // We push in swifterror return as the last element of CLI.Ins.
11432 ArgListTy &Args = CLI.getArgs();
11433 if (supportSwiftError()) {
11434 for (const ArgListEntry &Arg : Args) {
11435 if (Arg.IsSwiftError) {
11436 ISD::ArgFlagsTy Flags;
11437 Flags.setSwiftError();
11438 ISD::InputArg Ret(Flags, getPointerTy(DL), EVT(getPointerTy(DL)),
11439 PointerType::getUnqual(C&: Context),
11440 /*Used=*/true, ISD::InputArg::NoArgIndex, 0);
11441 CLI.Ins.push_back(Elt: Ret);
11442 }
11443 }
11444 }
11445
11446 // Handle all of the outgoing arguments.
11447 CLI.Outs.clear();
11448 CLI.OutVals.clear();
11449 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
11450 SmallVector<Type *, 4> OrigArgTys;
11451 ComputeValueTypes(DL, Ty: Args[i].OrigTy, Types&: OrigArgTys);
11452 // FIXME: Split arguments if CLI.IsPostTypeLegalization
11453 Type *FinalType = Args[i].Ty;
11454 if (Args[i].IsByVal)
11455 FinalType = Args[i].IndirectType;
11456 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
11457 Ty: FinalType, CallConv: CLI.CallConv, isVarArg: CLI.IsVarArg, DL);
11458 for (unsigned Value = 0, NumValues = OrigArgTys.size(); Value != NumValues;
11459 ++Value) {
11460 Type *OrigArgTy = OrigArgTys[Value];
11461 Type *ArgTy = OrigArgTy;
11462 if (Args[i].Ty != Args[i].OrigTy) {
11463 assert(Value == 0 && "Only supported for non-aggregate arguments");
11464 ArgTy = Args[i].Ty;
11465 }
11466
11467 EVT VT = getValueType(DL, Ty: ArgTy);
11468 SDValue Op = SDValue(Args[i].Node.getNode(),
11469 Args[i].Node.getResNo() + Value);
11470 ISD::ArgFlagsTy Flags;
11471
11472 // Certain targets (such as MIPS), may have a different ABI alignment
11473 // for a type depending on the context. Give the target a chance to
11474 // specify the alignment it wants.
11475 const Align OriginalAlignment(getABIAlignmentForCallingConv(ArgTy, DL));
11476 Flags.setOrigAlign(OriginalAlignment);
11477
11478 if (i >= CLI.NumFixedArgs)
11479 Flags.setVarArg();
11480 if (ArgTy->isPointerTy()) {
11481 Flags.setPointer();
11482 Flags.setPointerAddrSpace(cast<PointerType>(Val: ArgTy)->getAddressSpace());
11483 }
11484 if (Args[i].IsZExt)
11485 Flags.setZExt();
11486 if (Args[i].IsSExt)
11487 Flags.setSExt();
11488 if (Args[i].IsNoExt)
11489 Flags.setNoExt();
11490 if (Args[i].IsInReg) {
11491 // If we are using vectorcall calling convention, a structure that is
11492 // passed InReg - is surely an HVA
11493 if (CLI.CallConv == CallingConv::X86_VectorCall &&
11494 isa<StructType>(Val: FinalType)) {
11495 // The first value of a structure is marked
11496 if (0 == Value)
11497 Flags.setHvaStart();
11498 Flags.setHva();
11499 }
11500 // Set InReg Flag
11501 Flags.setInReg();
11502 }
11503 if (Args[i].IsSRet)
11504 Flags.setSRet();
11505 if (Args[i].IsSwiftSelf)
11506 Flags.setSwiftSelf();
11507 if (Args[i].IsSwiftAsync)
11508 Flags.setSwiftAsync();
11509 if (Args[i].IsSwiftError)
11510 Flags.setSwiftError();
11511 if (Args[i].IsCFGuardTarget)
11512 Flags.setCFGuardTarget();
11513 if (Args[i].IsByVal)
11514 Flags.setByVal();
11515 if (Args[i].IsByRef)
11516 Flags.setByRef();
11517 if (Args[i].IsPreallocated) {
11518 Flags.setPreallocated();
11519 // Set the byval flag for CCAssignFn callbacks that don't know about
11520 // preallocated. This way we can know how many bytes we should've
11521 // allocated and how many bytes a callee cleanup function will pop. If
11522 // we port preallocated to more targets, we'll have to add custom
11523 // preallocated handling in the various CC lowering callbacks.
11524 Flags.setByVal();
11525 }
11526 if (Args[i].IsInAlloca) {
11527 Flags.setInAlloca();
11528 // Set the byval flag for CCAssignFn callbacks that don't know about
11529 // inalloca. This way we can know how many bytes we should've allocated
11530 // and how many bytes a callee cleanup function will pop. If we port
11531 // inalloca to more targets, we'll have to add custom inalloca handling
11532 // in the various CC lowering callbacks.
11533 Flags.setByVal();
11534 }
11535 Align MemAlign;
11536 if (Args[i].IsByVal || Args[i].IsInAlloca || Args[i].IsPreallocated) {
11537 unsigned FrameSize = DL.getTypeAllocSize(Ty: Args[i].IndirectType);
11538 Flags.setByValSize(FrameSize);
11539
11540 // info is not there but there are cases it cannot get right.
11541 if (auto MA = Args[i].Alignment)
11542 MemAlign = *MA;
11543 else
11544 MemAlign = getByValTypeAlignment(Ty: Args[i].IndirectType, DL);
11545 } else if (auto MA = Args[i].Alignment) {
11546 MemAlign = *MA;
11547 } else {
11548 MemAlign = OriginalAlignment;
11549 }
11550 Flags.setMemAlign(MemAlign);
11551 if (Args[i].IsNest)
11552 Flags.setNest();
11553 if (NeedsRegBlock)
11554 Flags.setInConsecutiveRegs();
11555
11556 MVT PartVT = getRegisterTypeForCallingConv(Context, CC: CLI.CallConv, VT);
11557 unsigned NumParts =
11558 getNumRegistersForCallingConv(Context, CC: CLI.CallConv, VT);
11559 SmallVector<SDValue, 4> Parts(NumParts);
11560 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
11561
11562 if (Args[i].IsSExt)
11563 ExtendKind = ISD::SIGN_EXTEND;
11564 else if (Args[i].IsZExt)
11565 ExtendKind = ISD::ZERO_EXTEND;
11566
11567 // Conservatively only handle 'returned' on non-vectors that can be lowered,
11568 // for now.
11569 if (Args[i].IsReturned && !Op.getValueType().isVector() &&
11570 CanLowerReturn) {
11571 assert((CLI.RetTy == Args[i].Ty ||
11572 (CLI.RetTy->isPointerTy() && Args[i].Ty->isPointerTy() &&
11573 CLI.RetTy->getPointerAddressSpace() ==
11574 Args[i].Ty->getPointerAddressSpace())) &&
11575 RetVTs.size() == NumValues && "unexpected use of 'returned'");
11576 // Before passing 'returned' to the target lowering code, ensure that
11577 // either the register MVT and the actual EVT are the same size or that
11578 // the return value and argument are extended in the same way; in these
11579 // cases it's safe to pass the argument register value unchanged as the
11580 // return register value (although it's at the target's option whether
11581 // to do so)
11582 // TODO: allow code generation to take advantage of partially preserved
11583 // registers rather than clobbering the entire register when the
11584 // parameter extension method is not compatible with the return
11585 // extension method
11586 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
11587 (ExtendKind != ISD::ANY_EXTEND && CLI.RetSExt == Args[i].IsSExt &&
11588 CLI.RetZExt == Args[i].IsZExt))
11589 Flags.setReturned();
11590 }
11591
11592 getCopyToParts(DAG&: CLI.DAG, DL: CLI.DL, Val: Op, Parts: &Parts[0], NumParts, PartVT, V: CLI.CB,
11593 CallConv: CLI.CallConv, ExtendKind);
11594
11595 for (unsigned j = 0; j != NumParts; ++j) {
11596 // if it isn't first piece, alignment must be 1
11597 // For scalable vectors the scalable part is currently handled
11598 // by individual targets, so we just use the known minimum size here.
11599 ISD::OutputArg MyFlags(
11600 Flags, Parts[j].getValueType().getSimpleVT(), VT, OrigArgTy, i,
11601 j * Parts[j].getValueType().getStoreSize().getKnownMinValue());
11602 if (NumParts > 1 && j == 0)
11603 MyFlags.Flags.setSplit();
11604 else if (j != 0) {
11605 MyFlags.Flags.setOrigAlign(Align(1));
11606 if (j == NumParts - 1)
11607 MyFlags.Flags.setSplitEnd();
11608 }
11609
11610 CLI.Outs.push_back(Elt: MyFlags);
11611 CLI.OutVals.push_back(Elt: Parts[j]);
11612 }
11613
11614 if (NeedsRegBlock && Value == NumValues - 1)
11615 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
11616 }
11617 }
11618
11619 SmallVector<SDValue, 4> InVals;
11620 CLI.Chain = LowerCall(CLI, InVals);
11621
11622 // Update CLI.InVals to use outside of this function.
11623 CLI.InVals = InVals;
11624
11625 // Verify that the target's LowerCall behaved as expected.
11626 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
11627 "LowerCall didn't return a valid chain!");
11628 assert((!CLI.IsTailCall || InVals.empty()) &&
11629 "LowerCall emitted a return value for a tail call!");
11630 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
11631 "LowerCall didn't emit the correct number of values!");
11632
11633 // For a tail call, the return value is merely live-out and there aren't
11634 // any nodes in the DAG representing it. Return a special value to
11635 // indicate that a tail call has been emitted and no more Instructions
11636 // should be processed in the current block.
11637 if (CLI.IsTailCall) {
11638 CLI.DAG.setRoot(CLI.Chain);
11639 return std::make_pair(x: SDValue(), y: SDValue());
11640 }
11641
11642#ifndef NDEBUG
11643 for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
11644 assert(InVals[i].getNode() && "LowerCall emitted a null value!");
11645 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
11646 "LowerCall emitted a value with the wrong type!");
11647 }
11648#endif
11649
11650 SmallVector<SDValue, 4> ReturnValues;
11651 if (!CanLowerReturn) {
11652 // The instruction result is the result of loading from the
11653 // hidden sret parameter.
11654 MVT PtrVT = getPointerTy(DL, AS: DL.getAllocaAddrSpace());
11655
11656 unsigned NumValues = RetVTs.size();
11657 ReturnValues.resize(N: NumValues);
11658 SmallVector<SDValue, 4> Chains(NumValues);
11659
11660 // An aggregate return value cannot wrap around the address space, so
11661 // offsets to its parts don't wrap either.
11662 MachineFunction &MF = CLI.DAG.getMachineFunction();
11663 Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(ObjectIdx: DemoteStackIdx);
11664 for (unsigned i = 0; i < NumValues; ++i) {
11665 SDValue Add = CLI.DAG.getMemBasePlusOffset(
11666 Base: DemoteStackSlot, Offset: CLI.DAG.getConstant(Val: Offsets[i], DL: CLI.DL, VT: PtrVT),
11667 DL: CLI.DL, Flags: SDNodeFlags::NoUnsignedWrap);
11668 SDValue L = CLI.DAG.getLoad(
11669 VT: RetVTs[i], dl: CLI.DL, Chain: CLI.Chain, Ptr: Add,
11670 PtrInfo: MachinePointerInfo::getFixedStack(MF&: CLI.DAG.getMachineFunction(),
11671 FI: DemoteStackIdx, Offset: Offsets[i]),
11672 Alignment: HiddenSRetAlign);
11673 ReturnValues[i] = L;
11674 Chains[i] = L.getValue(R: 1);
11675 }
11676
11677 CLI.Chain = CLI.DAG.getNode(Opcode: ISD::TokenFactor, DL: CLI.DL, VT: MVT::Other, Ops: Chains);
11678 } else {
11679 // Collect the legal value parts into potentially illegal values
11680 // that correspond to the original function's return values.
11681 std::optional<ISD::NodeType> AssertOp;
11682 if (CLI.RetSExt)
11683 AssertOp = ISD::AssertSext;
11684 else if (CLI.RetZExt)
11685 AssertOp = ISD::AssertZext;
11686 unsigned CurReg = 0;
11687 for (EVT VT : RetVTs) {
11688 MVT RegisterVT = getRegisterTypeForCallingConv(Context, CC: CLI.CallConv, VT);
11689 unsigned NumRegs =
11690 getNumRegistersForCallingConv(Context, CC: CLI.CallConv, VT);
11691
11692 ReturnValues.push_back(Elt: getCopyFromParts(
11693 DAG&: CLI.DAG, DL: CLI.DL, Parts: &InVals[CurReg], NumParts: NumRegs, PartVT: RegisterVT, ValueVT: VT, V: nullptr,
11694 InChain: CLI.Chain, CC: CLI.CallConv, AssertOp));
11695 CurReg += NumRegs;
11696 }
11697
11698 // For a function returning void, there is no return value. We can't create
11699 // such a node, so we just return a null return value in that case. In
11700 // that case, nothing will actually look at the value.
11701 if (ReturnValues.empty())
11702 return std::make_pair(x: SDValue(), y&: CLI.Chain);
11703 }
11704
11705 SDValue Res = CLI.DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: CLI.DL,
11706 VTList: CLI.DAG.getVTList(VTs: RetVTs), Ops: ReturnValues);
11707 return std::make_pair(x&: Res, y&: CLI.Chain);
11708}
11709
11710/// Places new result values for the node in Results (their number
11711/// and types must exactly match those of the original return values of
11712/// the node), or leaves Results empty, which indicates that the node is not
11713/// to be custom lowered after all.
11714void TargetLowering::LowerOperationWrapper(SDNode *N,
11715 SmallVectorImpl<SDValue> &Results,
11716 SelectionDAG &DAG) const {
11717 SDValue Res = LowerOperation(Op: SDValue(N, 0), DAG);
11718
11719 if (!Res.getNode())
11720 return;
11721
11722 // If the original node has one result, take the return value from
11723 // LowerOperation as is. It might not be result number 0.
11724 if (N->getNumValues() == 1) {
11725 Results.push_back(Elt: Res);
11726 return;
11727 }
11728
11729 // If the original node has multiple results, then the return node should
11730 // have the same number of results.
11731 assert((N->getNumValues() == Res->getNumValues()) &&
11732 "Lowering returned the wrong number of results!");
11733
11734 // Places new result values base on N result number.
11735 for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
11736 Results.push_back(Elt: Res.getValue(R: I));
11737}
11738
11739SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
11740 llvm_unreachable("LowerOperation not implemented for this target!");
11741}
11742
11743void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V,
11744 Register Reg,
11745 ISD::NodeType ExtendType) {
11746 SDValue Op = getNonRegisterValue(V);
11747 assert((Op.getOpcode() != ISD::CopyFromReg ||
11748 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
11749 "Copy from a reg to the same reg!");
11750 assert(!Reg.isPhysical() && "Is a physreg");
11751
11752 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11753 // If this is an InlineAsm we have to match the registers required, not the
11754 // notional registers required by the type.
11755
11756 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, V->getType(),
11757 std::nullopt); // This is not an ABI copy.
11758 SDValue Chain = DAG.getEntryNode();
11759
11760 if (ExtendType == ISD::ANY_EXTEND) {
11761 auto PreferredExtendIt = FuncInfo.PreferredExtendType.find(Val: V);
11762 if (PreferredExtendIt != FuncInfo.PreferredExtendType.end())
11763 ExtendType = PreferredExtendIt->second;
11764 }
11765 RFV.getCopyToRegs(Val: Op, DAG, dl: getCurSDLoc(), Chain, Glue: nullptr, V, PreferredExtendType: ExtendType);
11766 PendingExports.push_back(Elt: Chain);
11767}
11768
11769#include "llvm/CodeGen/SelectionDAGISel.h"
11770
11771/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
11772/// entry block, return true. This includes arguments used by switches, since
11773/// the switch may expand into multiple basic blocks.
11774static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
11775 // With FastISel active, we may be splitting blocks, so force creation
11776 // of virtual registers for all non-dead arguments.
11777 if (FastISel)
11778 return A->use_empty();
11779
11780 const BasicBlock &Entry = A->getParent()->front();
11781 for (const User *U : A->users())
11782 if (cast<Instruction>(Val: U)->getParent() != &Entry || isa<SwitchInst>(Val: U))
11783 return false; // Use not in entry block.
11784
11785 return true;
11786}
11787
11788using ArgCopyElisionMapTy =
11789 DenseMap<const Argument *,
11790 std::pair<const AllocaInst *, const StoreInst *>>;
11791
11792/// Scan the entry block of the function in FuncInfo for arguments that look
11793/// like copies into a local alloca. Record any copied arguments in
11794/// ArgCopyElisionCandidates.
11795static void
11796findArgumentCopyElisionCandidates(const DataLayout &DL,
11797 FunctionLoweringInfo *FuncInfo,
11798 ArgCopyElisionMapTy &ArgCopyElisionCandidates) {
11799 // Record the state of every static alloca used in the entry block. Argument
11800 // allocas are all used in the entry block, so we need approximately as many
11801 // entries as we have arguments.
11802 enum StaticAllocaInfo { Unknown, Clobbered, Elidable };
11803 SmallDenseMap<const AllocaInst *, StaticAllocaInfo, 8> StaticAllocas;
11804 unsigned NumArgs = FuncInfo->Fn->arg_size();
11805 StaticAllocas.reserve(NumEntries: NumArgs * 2);
11806
11807 auto GetInfoIfStaticAlloca = [&](const Value *V) -> StaticAllocaInfo * {
11808 if (!V)
11809 return nullptr;
11810 V = V->stripPointerCasts();
11811 const auto *AI = dyn_cast<AllocaInst>(Val: V);
11812 if (!AI || !AI->isStaticAlloca() || !FuncInfo->StaticAllocaMap.count(Val: AI))
11813 return nullptr;
11814 auto Iter = StaticAllocas.insert(KV: {AI, Unknown});
11815 return &Iter.first->second;
11816 };
11817
11818 // Look for stores of arguments to static allocas. Look through bitcasts and
11819 // GEPs to handle type coercions, as long as the alloca is fully initialized
11820 // by the store. Any non-store use of an alloca escapes it and any subsequent
11821 // unanalyzed store might write it.
11822 // FIXME: Handle structs initialized with multiple stores.
11823 for (const Instruction &I : FuncInfo->Fn->getEntryBlock()) {
11824 // Look for stores, and handle non-store uses conservatively.
11825 const auto *SI = dyn_cast<StoreInst>(Val: &I);
11826 if (!SI) {
11827 // We will look through cast uses, so ignore them completely.
11828 if (I.isCast())
11829 continue;
11830 // Ignore debug info and pseudo op intrinsics, they don't escape or store
11831 // to allocas.
11832 if (I.isDebugOrPseudoInst())
11833 continue;
11834 // This is an unknown instruction. Assume it escapes or writes to all
11835 // static alloca operands.
11836 for (const Use &U : I.operands()) {
11837 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(U))
11838 *Info = StaticAllocaInfo::Clobbered;
11839 }
11840 continue;
11841 }
11842
11843 // If the stored value is a static alloca, mark it as escaped.
11844 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(SI->getValueOperand()))
11845 *Info = StaticAllocaInfo::Clobbered;
11846
11847 // Check if the destination is a static alloca.
11848 const Value *Dst = SI->getPointerOperand()->stripPointerCasts();
11849 StaticAllocaInfo *Info = GetInfoIfStaticAlloca(Dst);
11850 if (!Info)
11851 continue;
11852 const AllocaInst *AI = cast<AllocaInst>(Val: Dst);
11853
11854 // Skip allocas that have been initialized or clobbered.
11855 if (*Info != StaticAllocaInfo::Unknown)
11856 continue;
11857
11858 // Check if the stored value is an argument, and that this store fully
11859 // initializes the alloca.
11860 // If the argument type has padding bits we can't directly forward a pointer
11861 // as the upper bits may contain garbage.
11862 // Don't elide copies from the same argument twice.
11863 const Value *Val = SI->getValueOperand()->stripPointerCasts();
11864 const auto *Arg = dyn_cast<Argument>(Val);
11865 std::optional<TypeSize> AllocaSize = AI->getAllocationSize(DL);
11866 if (!Arg || Arg->hasPassPointeeByValueCopyAttr() ||
11867 Arg->getType()->isEmptyTy() || !AllocaSize ||
11868 DL.getTypeStoreSize(Ty: Arg->getType()) != *AllocaSize ||
11869 !DL.typeSizeEqualsStoreSize(Ty: Arg->getType()) ||
11870 ArgCopyElisionCandidates.count(Val: Arg)) {
11871 *Info = StaticAllocaInfo::Clobbered;
11872 continue;
11873 }
11874
11875 LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AI
11876 << '\n');
11877
11878 // Mark this alloca and store for argument copy elision.
11879 *Info = StaticAllocaInfo::Elidable;
11880 ArgCopyElisionCandidates.insert(KV: {Arg, {AI, SI}});
11881
11882 // Stop scanning if we've seen all arguments. This will happen early in -O0
11883 // builds, which is useful, because -O0 builds have large entry blocks and
11884 // many allocas.
11885 if (ArgCopyElisionCandidates.size() == NumArgs)
11886 break;
11887 }
11888}
11889
11890/// Try to elide argument copies from memory into a local alloca. Succeeds if
11891/// ArgVal is a load from a suitable fixed stack object.
11892static void tryToElideArgumentCopy(
11893 FunctionLoweringInfo &FuncInfo, SmallVectorImpl<SDValue> &Chains,
11894 DenseMap<int, int> &ArgCopyElisionFrameIndexMap,
11895 SmallPtrSetImpl<const Instruction *> &ElidedArgCopyInstrs,
11896 ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg,
11897 ArrayRef<SDValue> ArgVals, bool &ArgHasUses) {
11898 // Check if this is a load from a fixed stack object.
11899 auto *LNode = dyn_cast<LoadSDNode>(Val: ArgVals[0]);
11900 if (!LNode)
11901 return;
11902 auto *FINode = dyn_cast<FrameIndexSDNode>(Val: LNode->getBasePtr().getNode());
11903 if (!FINode)
11904 return;
11905
11906 // Check that the fixed stack object is the right size and alignment.
11907 // Look at the alignment that the user wrote on the alloca instead of looking
11908 // at the stack object.
11909 auto ArgCopyIter = ArgCopyElisionCandidates.find(Val: &Arg);
11910 assert(ArgCopyIter != ArgCopyElisionCandidates.end());
11911 const AllocaInst *AI = ArgCopyIter->second.first;
11912 int FixedIndex = FINode->getIndex();
11913 int &AllocaIndex = FuncInfo.StaticAllocaMap[AI];
11914 int OldIndex = AllocaIndex;
11915 MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
11916 if (MFI.getObjectSize(ObjectIdx: FixedIndex) != MFI.getObjectSize(ObjectIdx: OldIndex)) {
11917 LLVM_DEBUG(
11918 dbgs() << " argument copy elision failed due to bad fixed stack "
11919 "object size\n");
11920 return;
11921 }
11922 Align RequiredAlignment = AI->getAlign();
11923 if (MFI.getObjectAlign(ObjectIdx: FixedIndex) < RequiredAlignment) {
11924 LLVM_DEBUG(dbgs() << " argument copy elision failed: alignment of alloca "
11925 "greater than stack argument alignment ("
11926 << DebugStr(RequiredAlignment) << " vs "
11927 << DebugStr(MFI.getObjectAlign(FixedIndex)) << ")\n");
11928 return;
11929 }
11930
11931 // Perform the elision. Delete the old stack object and replace its only use
11932 // in the variable info map. Mark the stack object as mutable and aliased.
11933 LLVM_DEBUG({
11934 dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n'
11935 << " Replacing frame index " << OldIndex << " with " << FixedIndex
11936 << '\n';
11937 });
11938 MFI.RemoveStackObject(ObjectIdx: OldIndex);
11939 MFI.setIsImmutableObjectIndex(ObjectIdx: FixedIndex, IsImmutable: false);
11940 MFI.setIsAliasedObjectIndex(ObjectIdx: FixedIndex, IsAliased: true);
11941 AllocaIndex = FixedIndex;
11942 ArgCopyElisionFrameIndexMap.insert(KV: {OldIndex, FixedIndex});
11943 for (SDValue ArgVal : ArgVals)
11944 Chains.push_back(Elt: ArgVal.getValue(R: 1));
11945
11946 // Avoid emitting code for the store implementing the copy.
11947 const StoreInst *SI = ArgCopyIter->second.second;
11948 ElidedArgCopyInstrs.insert(Ptr: SI);
11949
11950 // Check for uses of the argument again so that we can avoid exporting ArgVal
11951 // if it is't used by anything other than the store.
11952 for (const Value *U : Arg.users()) {
11953 if (U != SI) {
11954 ArgHasUses = true;
11955 break;
11956 }
11957 }
11958}
11959
11960void SelectionDAGISel::LowerArguments(const Function &F) {
11961 SelectionDAG &DAG = SDB->DAG;
11962 SDLoc dl = SDB->getCurSDLoc();
11963 const DataLayout &DL = DAG.getDataLayout();
11964 SmallVector<ISD::InputArg, 16> Ins;
11965
11966 // In Naked functions we aren't going to save any registers.
11967 if (F.hasFnAttribute(Kind: Attribute::Naked))
11968 return;
11969
11970 if (!FuncInfo->CanLowerReturn) {
11971 // Put in an sret pointer parameter before all the other parameters.
11972 MVT ValueVT = TLI->getPointerTy(DL, AS: DL.getAllocaAddrSpace());
11973
11974 ISD::ArgFlagsTy Flags;
11975 Flags.setSRet();
11976 MVT RegisterVT = TLI->getRegisterType(Context&: *DAG.getContext(), VT: ValueVT);
11977 ISD::InputArg RetArg(Flags, RegisterVT, ValueVT, F.getReturnType(), true,
11978 ISD::InputArg::NoArgIndex, 0);
11979 Ins.push_back(Elt: RetArg);
11980 }
11981
11982 // Look for stores of arguments to static allocas. Mark such arguments with a
11983 // flag to ask the target to give us the memory location of that argument if
11984 // available.
11985 ArgCopyElisionMapTy ArgCopyElisionCandidates;
11986 findArgumentCopyElisionCandidates(DL, FuncInfo: FuncInfo.get(),
11987 ArgCopyElisionCandidates);
11988
11989 // Set up the incoming argument description vector.
11990 for (const Argument &Arg : F.args()) {
11991 unsigned ArgNo = Arg.getArgNo();
11992 SmallVector<Type *, 4> Types;
11993 ComputeValueTypes(DL: DAG.getDataLayout(), Ty: Arg.getType(), Types);
11994 bool isArgValueUsed = !Arg.use_empty();
11995 Type *FinalType = Arg.getType();
11996 if (Arg.hasAttribute(Kind: Attribute::ByVal))
11997 FinalType = Arg.getParamByValType();
11998 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
11999 Ty: FinalType, CallConv: F.getCallingConv(), isVarArg: F.isVarArg(), DL);
12000 for (unsigned Value = 0, NumValues = Types.size(); Value != NumValues;
12001 ++Value) {
12002 Type *ArgTy = Types[Value];
12003 EVT VT = TLI->getValueType(DL, Ty: ArgTy);
12004 ISD::ArgFlagsTy Flags;
12005
12006 if (ArgTy->isPointerTy()) {
12007 Flags.setPointer();
12008 Flags.setPointerAddrSpace(cast<PointerType>(Val: ArgTy)->getAddressSpace());
12009 }
12010 if (Arg.hasAttribute(Kind: Attribute::ZExt))
12011 Flags.setZExt();
12012 if (Arg.hasAttribute(Kind: Attribute::SExt))
12013 Flags.setSExt();
12014 if (Arg.hasAttribute(Kind: Attribute::InReg)) {
12015 // If we are using vectorcall calling convention, a structure that is
12016 // passed InReg - is surely an HVA
12017 if (F.getCallingConv() == CallingConv::X86_VectorCall &&
12018 isa<StructType>(Val: Arg.getType())) {
12019 // The first value of a structure is marked
12020 if (0 == Value)
12021 Flags.setHvaStart();
12022 Flags.setHva();
12023 }
12024 // Set InReg Flag
12025 Flags.setInReg();
12026 }
12027 if (Arg.hasAttribute(Kind: Attribute::StructRet))
12028 Flags.setSRet();
12029 if (Arg.hasAttribute(Kind: Attribute::SwiftSelf))
12030 Flags.setSwiftSelf();
12031 if (Arg.hasAttribute(Kind: Attribute::SwiftAsync))
12032 Flags.setSwiftAsync();
12033 if (Arg.hasAttribute(Kind: Attribute::SwiftError))
12034 Flags.setSwiftError();
12035 if (Arg.hasAttribute(Kind: Attribute::ByVal))
12036 Flags.setByVal();
12037 if (Arg.hasAttribute(Kind: Attribute::ByRef))
12038 Flags.setByRef();
12039 if (Arg.hasAttribute(Kind: Attribute::InAlloca)) {
12040 Flags.setInAlloca();
12041 // Set the byval flag for CCAssignFn callbacks that don't know about
12042 // inalloca. This way we can know how many bytes we should've allocated
12043 // and how many bytes a callee cleanup function will pop. If we port
12044 // inalloca to more targets, we'll have to add custom inalloca handling
12045 // in the various CC lowering callbacks.
12046 Flags.setByVal();
12047 }
12048 if (Arg.hasAttribute(Kind: Attribute::Preallocated)) {
12049 Flags.setPreallocated();
12050 // Set the byval flag for CCAssignFn callbacks that don't know about
12051 // preallocated. This way we can know how many bytes we should've
12052 // allocated and how many bytes a callee cleanup function will pop. If
12053 // we port preallocated to more targets, we'll have to add custom
12054 // preallocated handling in the various CC lowering callbacks.
12055 Flags.setByVal();
12056 }
12057
12058 // Certain targets (such as MIPS), may have a different ABI alignment
12059 // for a type depending on the context. Give the target a chance to
12060 // specify the alignment it wants.
12061 const Align OriginalAlignment(
12062 TLI->getABIAlignmentForCallingConv(ArgTy, DL));
12063 Flags.setOrigAlign(OriginalAlignment);
12064
12065 Align MemAlign;
12066 Type *ArgMemTy = nullptr;
12067 if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated() ||
12068 Flags.isByRef()) {
12069 if (!ArgMemTy)
12070 ArgMemTy = Arg.getPointeeInMemoryValueType();
12071
12072 uint64_t MemSize = DL.getTypeAllocSize(Ty: ArgMemTy);
12073
12074 // For in-memory arguments, size and alignment should be passed from FE.
12075 // BE will guess if this info is not there but there are cases it cannot
12076 // get right.
12077 if (auto ParamAlign = Arg.getParamStackAlign())
12078 MemAlign = *ParamAlign;
12079 else if ((ParamAlign = Arg.getParamAlign()))
12080 MemAlign = *ParamAlign;
12081 else
12082 MemAlign = TLI->getByValTypeAlignment(Ty: ArgMemTy, DL);
12083 if (Flags.isByRef())
12084 Flags.setByRefSize(MemSize);
12085 else
12086 Flags.setByValSize(MemSize);
12087 } else if (auto ParamAlign = Arg.getParamStackAlign()) {
12088 MemAlign = *ParamAlign;
12089 } else {
12090 MemAlign = OriginalAlignment;
12091 }
12092 Flags.setMemAlign(MemAlign);
12093
12094 if (Arg.hasAttribute(Kind: Attribute::Nest))
12095 Flags.setNest();
12096 if (NeedsRegBlock)
12097 Flags.setInConsecutiveRegs();
12098 if (ArgCopyElisionCandidates.count(Val: &Arg))
12099 Flags.setCopyElisionCandidate();
12100 if (Arg.hasAttribute(Kind: Attribute::Returned))
12101 Flags.setReturned();
12102
12103 MVT RegisterVT = TLI->getRegisterTypeForCallingConv(
12104 Context&: *CurDAG->getContext(), CC: F.getCallingConv(), VT);
12105 unsigned NumRegs = TLI->getNumRegistersForCallingConv(
12106 Context&: *CurDAG->getContext(), CC: F.getCallingConv(), VT);
12107 for (unsigned i = 0; i != NumRegs; ++i) {
12108 // For scalable vectors, use the minimum size; individual targets
12109 // are responsible for handling scalable vector arguments and
12110 // return values.
12111 ISD::InputArg MyFlags(
12112 Flags, RegisterVT, VT, ArgTy, isArgValueUsed, ArgNo,
12113 i * RegisterVT.getStoreSize().getKnownMinValue());
12114 if (NumRegs > 1 && i == 0)
12115 MyFlags.Flags.setSplit();
12116 // if it isn't first piece, alignment must be 1
12117 else if (i > 0) {
12118 MyFlags.Flags.setOrigAlign(Align(1));
12119 if (i == NumRegs - 1)
12120 MyFlags.Flags.setSplitEnd();
12121 }
12122 Ins.push_back(Elt: MyFlags);
12123 }
12124 if (NeedsRegBlock && Value == NumValues - 1)
12125 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
12126 }
12127 }
12128
12129 // Call the target to set up the argument values.
12130 SmallVector<SDValue, 8> InVals;
12131 SDValue NewRoot = TLI->LowerFormalArguments(
12132 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
12133
12134 // Verify that the target's LowerFormalArguments behaved as expected.
12135 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
12136 "LowerFormalArguments didn't return a valid chain!");
12137 assert(InVals.size() == Ins.size() &&
12138 "LowerFormalArguments didn't emit the correct number of values!");
12139 assert(all_of(InVals, [](SDValue InVal) { return InVal.getNode(); }) &&
12140 "LowerFormalArguments emitted a null value!");
12141
12142 // Update the DAG with the new chain value resulting from argument lowering.
12143 DAG.setRoot(NewRoot);
12144
12145 // Set up the argument values.
12146 unsigned i = 0;
12147 if (!FuncInfo->CanLowerReturn) {
12148 // Create a virtual register for the sret pointer, and put in a copy
12149 // from the sret argument into it.
12150 MVT VT = TLI->getPointerTy(DL, AS: DL.getAllocaAddrSpace());
12151 MVT RegVT = TLI->getRegisterType(Context&: *CurDAG->getContext(), VT);
12152 std::optional<ISD::NodeType> AssertOp;
12153 SDValue ArgValue =
12154 getCopyFromParts(DAG, DL: dl, Parts: &InVals[0], NumParts: 1, PartVT: RegVT, ValueVT: VT, V: nullptr, InChain: NewRoot,
12155 CC: F.getCallingConv(), AssertOp);
12156
12157 MachineFunction& MF = SDB->DAG.getMachineFunction();
12158 MachineRegisterInfo& RegInfo = MF.getRegInfo();
12159 Register SRetReg =
12160 RegInfo.createVirtualRegister(RegClass: TLI->getRegClassFor(VT: RegVT));
12161 FuncInfo->DemoteRegister = SRetReg;
12162 NewRoot =
12163 SDB->DAG.getCopyToReg(Chain: NewRoot, dl: SDB->getCurSDLoc(), Reg: SRetReg, N: ArgValue);
12164 DAG.setRoot(NewRoot);
12165
12166 // i indexes lowered arguments. Bump it past the hidden sret argument.
12167 ++i;
12168 }
12169
12170 SmallVector<SDValue, 4> Chains;
12171 DenseMap<int, int> ArgCopyElisionFrameIndexMap;
12172 for (const Argument &Arg : F.args()) {
12173 SmallVector<SDValue, 4> ArgValues;
12174 SmallVector<EVT, 4> ValueVTs;
12175 ComputeValueVTs(TLI: *TLI, DL: DAG.getDataLayout(), Ty: Arg.getType(), ValueVTs);
12176 unsigned NumValues = ValueVTs.size();
12177 if (NumValues == 0)
12178 continue;
12179
12180 bool ArgHasUses = !Arg.use_empty();
12181
12182 // Elide the copying store if the target loaded this argument from a
12183 // suitable fixed stack object.
12184 if (Ins[i].Flags.isCopyElisionCandidate()) {
12185 unsigned NumParts = 0;
12186 for (EVT VT : ValueVTs)
12187 NumParts += TLI->getNumRegistersForCallingConv(Context&: *CurDAG->getContext(),
12188 CC: F.getCallingConv(), VT);
12189
12190 tryToElideArgumentCopy(FuncInfo&: *FuncInfo, Chains, ArgCopyElisionFrameIndexMap,
12191 ElidedArgCopyInstrs, ArgCopyElisionCandidates, Arg,
12192 ArgVals: ArrayRef(&InVals[i], NumParts), ArgHasUses);
12193 }
12194
12195 // If this argument is unused then remember its value. It is used to generate
12196 // debugging information.
12197 bool isSwiftErrorArg =
12198 TLI->supportSwiftError() &&
12199 Arg.hasAttribute(Kind: Attribute::SwiftError);
12200 if (!ArgHasUses && !isSwiftErrorArg) {
12201 SDB->setUnusedArgValue(V: &Arg, NewN: InVals[i]);
12202
12203 // Also remember any frame index for use in FastISel.
12204 if (FrameIndexSDNode *FI =
12205 dyn_cast<FrameIndexSDNode>(Val: InVals[i].getNode()))
12206 FuncInfo->setArgumentFrameIndex(A: &Arg, FI: FI->getIndex());
12207 }
12208
12209 for (unsigned Val = 0; Val != NumValues; ++Val) {
12210 EVT VT = ValueVTs[Val];
12211 MVT PartVT = TLI->getRegisterTypeForCallingConv(Context&: *CurDAG->getContext(),
12212 CC: F.getCallingConv(), VT);
12213 unsigned NumParts = TLI->getNumRegistersForCallingConv(
12214 Context&: *CurDAG->getContext(), CC: F.getCallingConv(), VT);
12215
12216 // Even an apparent 'unused' swifterror argument needs to be returned. So
12217 // we do generate a copy for it that can be used on return from the
12218 // function.
12219 if (ArgHasUses || isSwiftErrorArg) {
12220 std::optional<ISD::NodeType> AssertOp;
12221 if (Arg.hasAttribute(Kind: Attribute::SExt))
12222 AssertOp = ISD::AssertSext;
12223 else if (Arg.hasAttribute(Kind: Attribute::ZExt))
12224 AssertOp = ISD::AssertZext;
12225
12226 SDValue OutVal =
12227 getCopyFromParts(DAG, DL: dl, Parts: &InVals[i], NumParts, PartVT, ValueVT: VT, V: nullptr,
12228 InChain: NewRoot, CC: F.getCallingConv(), AssertOp);
12229
12230 FPClassTest NoFPClass = Arg.getNoFPClass();
12231 if (NoFPClass != fcNone) {
12232 SDValue SDNoFPClass = DAG.getTargetConstant(
12233 Val: static_cast<uint64_t>(NoFPClass), DL: dl, VT: MVT::i32);
12234 OutVal = DAG.getNode(Opcode: ISD::AssertNoFPClass, DL: dl, VT: OutVal.getValueType(),
12235 N1: OutVal, N2: SDNoFPClass);
12236 }
12237 ArgValues.push_back(Elt: OutVal);
12238 }
12239
12240 i += NumParts;
12241 }
12242
12243 // We don't need to do anything else for unused arguments.
12244 if (ArgValues.empty())
12245 continue;
12246
12247 // Note down frame index.
12248 if (FrameIndexSDNode *FI =
12249 dyn_cast<FrameIndexSDNode>(Val: ArgValues[0].getNode()))
12250 FuncInfo->setArgumentFrameIndex(A: &Arg, FI: FI->getIndex());
12251
12252 SDValue Res = DAG.getMergeValues(Ops: ArrayRef(ArgValues.data(), NumValues),
12253 dl: SDB->getCurSDLoc());
12254
12255 SDB->setValue(V: &Arg, NewN: Res);
12256 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
12257 // We want to associate the argument with the frame index, among
12258 // involved operands, that correspond to the lowest address. The
12259 // getCopyFromParts function, called earlier, is swapping the order of
12260 // the operands to BUILD_PAIR depending on endianness. The result of
12261 // that swapping is that the least significant bits of the argument will
12262 // be in the first operand of the BUILD_PAIR node, and the most
12263 // significant bits will be in the second operand.
12264 unsigned LowAddressOp = DAG.getDataLayout().isBigEndian() ? 1 : 0;
12265 if (LoadSDNode *LNode =
12266 dyn_cast<LoadSDNode>(Val: Res.getOperand(i: LowAddressOp).getNode()))
12267 if (FrameIndexSDNode *FI =
12268 dyn_cast<FrameIndexSDNode>(Val: LNode->getBasePtr().getNode()))
12269 FuncInfo->setArgumentFrameIndex(A: &Arg, FI: FI->getIndex());
12270 }
12271
12272 // Analyses past this point are naive and don't expect an assertion.
12273 if (Res.getOpcode() == ISD::AssertZext)
12274 Res = Res.getOperand(i: 0);
12275
12276 // Update the SwiftErrorVRegDefMap.
12277 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) {
12278 Register Reg = cast<RegisterSDNode>(Val: Res.getOperand(i: 1))->getReg();
12279 if (Reg.isVirtual())
12280 SwiftError->setCurrentVReg(MBB: FuncInfo->MBB, SwiftError->getFunctionArg(),
12281 Reg);
12282 }
12283
12284 // If this argument is live outside of the entry block, insert a copy from
12285 // wherever we got it to the vreg that other BB's will reference it as.
12286 if (Res.getOpcode() == ISD::CopyFromReg) {
12287 // If we can, though, try to skip creating an unnecessary vreg.
12288 // FIXME: This isn't very clean... it would be nice to make this more
12289 // general.
12290 Register Reg = cast<RegisterSDNode>(Val: Res.getOperand(i: 1))->getReg();
12291 if (Reg.isVirtual()) {
12292 FuncInfo->ValueMap[&Arg] = Reg;
12293 continue;
12294 }
12295 }
12296 if (!isOnlyUsedInEntryBlock(A: &Arg, FastISel: TM.Options.EnableFastISel)) {
12297 FuncInfo->InitializeRegForValue(V: &Arg);
12298 SDB->CopyToExportRegsIfNeeded(V: &Arg);
12299 }
12300 }
12301
12302 if (!Chains.empty()) {
12303 Chains.push_back(Elt: NewRoot);
12304 NewRoot = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: Chains);
12305 }
12306
12307 DAG.setRoot(NewRoot);
12308
12309 assert(i == InVals.size() && "Argument register count mismatch!");
12310
12311 // If any argument copy elisions occurred and we have debug info, update the
12312 // stale frame indices used in the dbg.declare variable info table.
12313 if (!ArgCopyElisionFrameIndexMap.empty()) {
12314 for (MachineFunction::VariableDbgInfo &VI :
12315 MF->getInStackSlotVariableDbgInfo()) {
12316 auto I = ArgCopyElisionFrameIndexMap.find(Val: VI.getStackSlot());
12317 if (I != ArgCopyElisionFrameIndexMap.end())
12318 VI.updateStackSlot(NewSlot: I->second);
12319 }
12320 }
12321
12322 // Finally, if the target has anything special to do, allow it to do so.
12323 emitFunctionEntryCode();
12324}
12325
12326/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
12327/// ensure constants are generated when needed. Remember the virtual registers
12328/// that need to be added to the Machine PHI nodes as input. We cannot just
12329/// directly add them, because expansion might result in multiple MBB's for one
12330/// BB. As such, the start of the BB might correspond to a different MBB than
12331/// the end.
12332void
12333SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
12334 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12335
12336 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
12337
12338 // Check PHI nodes in successors that expect a value to be available from this
12339 // block.
12340 for (const BasicBlock *SuccBB : successors(I: LLVMBB->getTerminator())) {
12341 if (!isa<PHINode>(Val: SuccBB->begin())) continue;
12342 MachineBasicBlock *SuccMBB = FuncInfo.getMBB(BB: SuccBB);
12343
12344 // If this terminator has multiple identical successors (common for
12345 // switches), only handle each succ once.
12346 if (!SuccsHandled.insert(Ptr: SuccMBB).second)
12347 continue;
12348
12349 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
12350
12351 // At this point we know that there is a 1-1 correspondence between LLVM PHI
12352 // nodes and Machine PHI nodes, but the incoming operands have not been
12353 // emitted yet.
12354 for (const PHINode &PN : SuccBB->phis()) {
12355 // Ignore dead phi's.
12356 if (PN.use_empty())
12357 continue;
12358
12359 // Skip empty types
12360 if (PN.getType()->isEmptyTy())
12361 continue;
12362
12363 Register Reg;
12364 const Value *PHIOp = PN.getIncomingValueForBlock(BB: LLVMBB);
12365
12366 if (const auto *C = dyn_cast<Constant>(Val: PHIOp)) {
12367 Register &RegOut = ConstantsOut[C];
12368 if (!RegOut) {
12369 RegOut = FuncInfo.CreateRegs(V: &PN);
12370 // We need to zero/sign extend ConstantInt phi operands to match
12371 // assumptions in FunctionLoweringInfo::ComputePHILiveOutRegInfo.
12372 ISD::NodeType ExtendType = ISD::ANY_EXTEND;
12373 if (auto *CI = dyn_cast<ConstantInt>(Val: C))
12374 ExtendType = TLI.signExtendConstant(C: CI) ? ISD::SIGN_EXTEND
12375 : ISD::ZERO_EXTEND;
12376 CopyValueToVirtualRegister(V: C, Reg: RegOut, ExtendType);
12377 }
12378 Reg = RegOut;
12379 } else {
12380 auto I = FuncInfo.ValueMap.find(Val: PHIOp);
12381 if (I != FuncInfo.ValueMap.end())
12382 Reg = I->second;
12383 else {
12384 assert(isa<AllocaInst>(PHIOp) &&
12385 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
12386 "Didn't codegen value into a register!??");
12387 Reg = FuncInfo.CreateRegs(V: &PN);
12388 CopyValueToVirtualRegister(V: PHIOp, Reg);
12389 }
12390 }
12391
12392 // Remember that this register needs to added to the machine PHI node as
12393 // the input for this MBB.
12394 SmallVector<EVT, 4> ValueVTs;
12395 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: PN.getType(), ValueVTs);
12396 for (EVT VT : ValueVTs) {
12397 const unsigned NumRegisters = TLI.getNumRegisters(Context&: *DAG.getContext(), VT);
12398 for (unsigned i = 0; i != NumRegisters; ++i)
12399 FuncInfo.PHINodesToUpdate.emplace_back(args: &*MBBI++, args: Reg + i);
12400 Reg += NumRegisters;
12401 }
12402 }
12403 }
12404
12405 ConstantsOut.clear();
12406}
12407
12408MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
12409 MachineFunction::iterator I(MBB);
12410 if (++I == FuncInfo.MF->end())
12411 return nullptr;
12412 return &*I;
12413}
12414
12415/// During lowering new call nodes can be created (such as memset, etc.).
12416/// Those will become new roots of the current DAG, but complications arise
12417/// when they are tail calls. In such cases, the call lowering will update
12418/// the root, but the builder still needs to know that a tail call has been
12419/// lowered in order to avoid generating an additional return.
12420void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
12421 // If the node is null, we do have a tail call.
12422 if (MaybeTC.getNode() != nullptr)
12423 DAG.setRoot(MaybeTC);
12424 else
12425 HasTailCall = true;
12426}
12427
12428void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
12429 MachineBasicBlock *SwitchMBB,
12430 MachineBasicBlock *DefaultMBB) {
12431 MachineFunction *CurMF = FuncInfo.MF;
12432 MachineBasicBlock *NextMBB = nullptr;
12433 MachineFunction::iterator BBI(W.MBB);
12434 if (++BBI != FuncInfo.MF->end())
12435 NextMBB = &*BBI;
12436
12437 unsigned Size = W.LastCluster - W.FirstCluster + 1;
12438
12439 BranchProbabilityInfo *BPI = FuncInfo.BPI;
12440
12441 if (Size == 2 && W.MBB == SwitchMBB) {
12442 // If any two of the cases has the same destination, and if one value
12443 // is the same as the other, but has one bit unset that the other has set,
12444 // use bit manipulation to do two compares at once. For example:
12445 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
12446 // TODO: This could be extended to merge any 2 cases in switches with 3
12447 // cases.
12448 // TODO: Handle cases where W.CaseBB != SwitchBB.
12449 CaseCluster &Small = *W.FirstCluster;
12450 CaseCluster &Big = *W.LastCluster;
12451
12452 if (Small.Low == Small.High && Big.Low == Big.High &&
12453 Small.MBB == Big.MBB) {
12454 const APInt &SmallValue = Small.Low->getValue();
12455 const APInt &BigValue = Big.Low->getValue();
12456
12457 // Check that there is only one bit different.
12458 APInt CommonBit = BigValue ^ SmallValue;
12459 if (CommonBit.isPowerOf2()) {
12460 SDValue CondLHS = getValue(V: Cond);
12461 EVT VT = CondLHS.getValueType();
12462 SDLoc DL = getCurSDLoc();
12463
12464 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: CondLHS,
12465 N2: DAG.getConstant(Val: CommonBit, DL, VT));
12466 SDValue Cond = DAG.getSetCC(
12467 DL, VT: MVT::i1, LHS: Or, RHS: DAG.getConstant(Val: BigValue | SmallValue, DL, VT),
12468 Cond: ISD::SETEQ);
12469
12470 // Update successor info.
12471 // Both Small and Big will jump to Small.BB, so we sum up the
12472 // probabilities.
12473 addSuccessorWithProb(Src: SwitchMBB, Dst: Small.MBB, Prob: Small.Prob + Big.Prob);
12474 if (BPI)
12475 addSuccessorWithProb(
12476 Src: SwitchMBB, Dst: DefaultMBB,
12477 // The default destination is the first successor in IR.
12478 Prob: BPI->getEdgeProbability(Src: SwitchMBB->getBasicBlock(), IndexInSuccessors: (unsigned)0));
12479 else
12480 addSuccessorWithProb(Src: SwitchMBB, Dst: DefaultMBB);
12481
12482 // Insert the true branch.
12483 SDValue BrCond =
12484 DAG.getNode(Opcode: ISD::BRCOND, DL, VT: MVT::Other, N1: getControlRoot(), N2: Cond,
12485 N3: DAG.getBasicBlock(MBB: Small.MBB));
12486 // Insert the false branch.
12487 BrCond = DAG.getNode(Opcode: ISD::BR, DL, VT: MVT::Other, N1: BrCond,
12488 N2: DAG.getBasicBlock(MBB: DefaultMBB));
12489
12490 DAG.setRoot(BrCond);
12491 return;
12492 }
12493 }
12494 }
12495
12496 if (TM.getOptLevel() != CodeGenOptLevel::None) {
12497 // Here, we order cases by probability so the most likely case will be
12498 // checked first. However, two clusters can have the same probability in
12499 // which case their relative ordering is non-deterministic. So we use Low
12500 // as a tie-breaker as clusters are guaranteed to never overlap.
12501 llvm::sort(Start: W.FirstCluster, End: W.LastCluster + 1,
12502 Comp: [](const CaseCluster &a, const CaseCluster &b) {
12503 return a.Prob != b.Prob ?
12504 a.Prob > b.Prob :
12505 a.Low->getValue().slt(RHS: b.Low->getValue());
12506 });
12507
12508 // Rearrange the case blocks so that the last one falls through if possible
12509 // without changing the order of probabilities.
12510 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
12511 --I;
12512 if (I->Prob > W.LastCluster->Prob)
12513 break;
12514 if (I->Kind == CC_Range && I->MBB == NextMBB) {
12515 std::swap(a&: *I, b&: *W.LastCluster);
12516 break;
12517 }
12518 }
12519 }
12520
12521 // Compute total probability.
12522 BranchProbability DefaultProb = W.DefaultProb;
12523 BranchProbability UnhandledProbs = DefaultProb;
12524 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
12525 UnhandledProbs += I->Prob;
12526
12527 MachineBasicBlock *CurMBB = W.MBB;
12528 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
12529 bool FallthroughUnreachable = false;
12530 MachineBasicBlock *Fallthrough;
12531 if (I == W.LastCluster) {
12532 // For the last cluster, fall through to the default destination.
12533 Fallthrough = DefaultMBB;
12534 FallthroughUnreachable = isa<UnreachableInst>(
12535 Val: DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
12536 } else {
12537 Fallthrough = CurMF->CreateMachineBasicBlock(BB: CurMBB->getBasicBlock());
12538 CurMF->insert(MBBI: BBI, MBB: Fallthrough);
12539 // Put Cond in a virtual register to make it available from the new blocks.
12540 ExportFromCurrentBlock(V: Cond);
12541 }
12542 UnhandledProbs -= I->Prob;
12543
12544 switch (I->Kind) {
12545 case CC_JumpTable: {
12546 // FIXME: Optimize away range check based on pivot comparisons.
12547 JumpTableHeader *JTH = &SL->JTCases[I->JTCasesIndex].first;
12548 SwitchCG::JumpTable *JT = &SL->JTCases[I->JTCasesIndex].second;
12549
12550 // The jump block hasn't been inserted yet; insert it here.
12551 MachineBasicBlock *JumpMBB = JT->MBB;
12552 CurMF->insert(MBBI: BBI, MBB: JumpMBB);
12553
12554 auto JumpProb = I->Prob;
12555 auto FallthroughProb = UnhandledProbs;
12556
12557 // If the default statement is a target of the jump table, we evenly
12558 // distribute the default probability to successors of CurMBB. Also
12559 // update the probability on the edge from JumpMBB to Fallthrough.
12560 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
12561 SE = JumpMBB->succ_end();
12562 SI != SE; ++SI) {
12563 if (*SI == DefaultMBB) {
12564 JumpProb += DefaultProb / 2;
12565 FallthroughProb -= DefaultProb / 2;
12566 JumpMBB->setSuccProbability(I: SI, Prob: DefaultProb / 2);
12567 JumpMBB->normalizeSuccProbs();
12568 break;
12569 }
12570 }
12571
12572 // If the default clause is unreachable, propagate that knowledge into
12573 // JTH->FallthroughUnreachable which will use it to suppress the range
12574 // check.
12575 //
12576 // However, don't do this if we're doing branch target enforcement,
12577 // because a table branch _without_ a range check can be a tempting JOP
12578 // gadget - out-of-bounds inputs that are impossible in correct
12579 // execution become possible again if an attacker can influence the
12580 // control flow. So if an attacker doesn't already have a BTI bypass
12581 // available, we don't want them to be able to get one out of this
12582 // table branch.
12583 if (FallthroughUnreachable) {
12584 Function &CurFunc = CurMF->getFunction();
12585 if (!CurFunc.hasFnAttribute(Kind: "branch-target-enforcement"))
12586 JTH->FallthroughUnreachable = true;
12587 }
12588
12589 if (!JTH->FallthroughUnreachable)
12590 addSuccessorWithProb(Src: CurMBB, Dst: Fallthrough, Prob: FallthroughProb);
12591 addSuccessorWithProb(Src: CurMBB, Dst: JumpMBB, Prob: JumpProb);
12592 CurMBB->normalizeSuccProbs();
12593
12594 // The jump table header will be inserted in our current block, do the
12595 // range check, and fall through to our fallthrough block.
12596 JTH->HeaderBB = CurMBB;
12597 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
12598
12599 // If we're in the right place, emit the jump table header right now.
12600 if (CurMBB == SwitchMBB) {
12601 visitJumpTableHeader(JT&: *JT, JTH&: *JTH, SwitchBB: SwitchMBB);
12602 JTH->Emitted = true;
12603 }
12604 break;
12605 }
12606 case CC_BitTests: {
12607 // FIXME: Optimize away range check based on pivot comparisons.
12608 BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex];
12609
12610 // The bit test blocks haven't been inserted yet; insert them here.
12611 for (BitTestCase &BTC : BTB->Cases)
12612 CurMF->insert(MBBI: BBI, MBB: BTC.ThisBB);
12613
12614 // Fill in fields of the BitTestBlock.
12615 BTB->Parent = CurMBB;
12616 BTB->Default = Fallthrough;
12617
12618 BTB->DefaultProb = UnhandledProbs;
12619 // If the cases in bit test don't form a contiguous range, we evenly
12620 // distribute the probability on the edge to Fallthrough to two
12621 // successors of CurMBB.
12622 if (!BTB->ContiguousRange) {
12623 BTB->Prob += DefaultProb / 2;
12624 BTB->DefaultProb -= DefaultProb / 2;
12625 }
12626
12627 if (FallthroughUnreachable)
12628 BTB->FallthroughUnreachable = true;
12629
12630 // If we're in the right place, emit the bit test header right now.
12631 if (CurMBB == SwitchMBB) {
12632 visitBitTestHeader(B&: *BTB, SwitchBB: SwitchMBB);
12633 BTB->Emitted = true;
12634 }
12635 break;
12636 }
12637 case CC_Range: {
12638 const Value *RHS, *LHS, *MHS;
12639 ISD::CondCode CC;
12640 if (I->Low == I->High) {
12641 // Check Cond == I->Low.
12642 CC = ISD::SETEQ;
12643 LHS = Cond;
12644 RHS=I->Low;
12645 MHS = nullptr;
12646 } else {
12647 // Check I->Low <= Cond <= I->High.
12648 CC = ISD::SETLE;
12649 LHS = I->Low;
12650 MHS = Cond;
12651 RHS = I->High;
12652 }
12653
12654 // If Fallthrough is unreachable, fold away the comparison.
12655 if (FallthroughUnreachable)
12656 CC = ISD::SETTRUE;
12657
12658 // The false probability is the sum of all unhandled cases.
12659 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB,
12660 getCurSDLoc(), I->Prob, UnhandledProbs);
12661
12662 if (CurMBB == SwitchMBB)
12663 visitSwitchCase(CB, SwitchBB: SwitchMBB);
12664 else
12665 SL->SwitchCases.push_back(x: CB);
12666
12667 break;
12668 }
12669 }
12670 CurMBB = Fallthrough;
12671 }
12672}
12673
12674void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
12675 const SwitchWorkListItem &W,
12676 Value *Cond,
12677 MachineBasicBlock *SwitchMBB) {
12678 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
12679 "Clusters not sorted?");
12680 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
12681
12682 auto [LastLeft, FirstRight, LeftProb, RightProb] =
12683 SL->computeSplitWorkItemInfo(W);
12684
12685 // Use the first element on the right as pivot since we will make less-than
12686 // comparisons against it.
12687 CaseClusterIt PivotCluster = FirstRight;
12688 assert(PivotCluster > W.FirstCluster);
12689 assert(PivotCluster <= W.LastCluster);
12690
12691 CaseClusterIt FirstLeft = W.FirstCluster;
12692 CaseClusterIt LastRight = W.LastCluster;
12693
12694 const ConstantInt *Pivot = PivotCluster->Low;
12695
12696 // New blocks will be inserted immediately after the current one.
12697 MachineFunction::iterator BBI(W.MBB);
12698 ++BBI;
12699
12700 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
12701 // we can branch to its destination directly if it's squeezed exactly in
12702 // between the known lower bound and Pivot - 1.
12703 MachineBasicBlock *LeftMBB;
12704 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
12705 FirstLeft->Low == W.GE &&
12706 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
12707 LeftMBB = FirstLeft->MBB;
12708 } else {
12709 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(BB: W.MBB->getBasicBlock());
12710 FuncInfo.MF->insert(MBBI: BBI, MBB: LeftMBB);
12711 WorkList.push_back(
12712 Elt: {.MBB: LeftMBB, .FirstCluster: FirstLeft, .LastCluster: LastLeft, .GE: W.GE, .LT: Pivot, .DefaultProb: W.DefaultProb / 2});
12713 // Put Cond in a virtual register to make it available from the new blocks.
12714 ExportFromCurrentBlock(V: Cond);
12715 }
12716
12717 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
12718 // single cluster, RHS.Low == Pivot, and we can branch to its destination
12719 // directly if RHS.High equals the current upper bound.
12720 MachineBasicBlock *RightMBB;
12721 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
12722 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
12723 RightMBB = FirstRight->MBB;
12724 } else {
12725 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(BB: W.MBB->getBasicBlock());
12726 FuncInfo.MF->insert(MBBI: BBI, MBB: RightMBB);
12727 WorkList.push_back(
12728 Elt: {.MBB: RightMBB, .FirstCluster: FirstRight, .LastCluster: LastRight, .GE: Pivot, .LT: W.LT, .DefaultProb: W.DefaultProb / 2});
12729 // Put Cond in a virtual register to make it available from the new blocks.
12730 ExportFromCurrentBlock(V: Cond);
12731 }
12732
12733 // Create the CaseBlock record that will be used to lower the branch.
12734 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
12735 getCurSDLoc(), LeftProb, RightProb);
12736
12737 if (W.MBB == SwitchMBB)
12738 visitSwitchCase(CB, SwitchBB: SwitchMBB);
12739 else
12740 SL->SwitchCases.push_back(x: CB);
12741}
12742
12743// Scale CaseProb after peeling a case with the probablity of PeeledCaseProb
12744// from the swith statement.
12745static BranchProbability scaleCaseProbality(BranchProbability CaseProb,
12746 BranchProbability PeeledCaseProb) {
12747 if (PeeledCaseProb == BranchProbability::getOne())
12748 return BranchProbability::getZero();
12749 BranchProbability SwitchProb = PeeledCaseProb.getCompl();
12750
12751 uint32_t Numerator = CaseProb.getNumerator();
12752 uint32_t Denominator = SwitchProb.scale(Num: CaseProb.getDenominator());
12753 return BranchProbability(Numerator, std::max(a: Numerator, b: Denominator));
12754}
12755
12756// Try to peel the top probability case if it exceeds the threshold.
12757// Return current MachineBasicBlock for the switch statement if the peeling
12758// does not occur.
12759// If the peeling is performed, return the newly created MachineBasicBlock
12760// for the peeled switch statement. Also update Clusters to remove the peeled
12761// case. PeeledCaseProb is the BranchProbability for the peeled case.
12762MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster(
12763 const SwitchInst &SI, CaseClusterVector &Clusters,
12764 BranchProbability &PeeledCaseProb) {
12765 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
12766 // Don't perform if there is only one cluster or optimizing for size.
12767 if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 ||
12768 TM.getOptLevel() == CodeGenOptLevel::None ||
12769 SwitchMBB->getParent()->getFunction().hasMinSize())
12770 return SwitchMBB;
12771
12772 BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100);
12773 unsigned PeeledCaseIndex = 0;
12774 bool SwitchPeeled = false;
12775 for (unsigned Index = 0; Index < Clusters.size(); ++Index) {
12776 CaseCluster &CC = Clusters[Index];
12777 if (CC.Prob < TopCaseProb)
12778 continue;
12779 TopCaseProb = CC.Prob;
12780 PeeledCaseIndex = Index;
12781 SwitchPeeled = true;
12782 }
12783 if (!SwitchPeeled)
12784 return SwitchMBB;
12785
12786 LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: "
12787 << TopCaseProb << "\n");
12788
12789 // Record the MBB for the peeled switch statement.
12790 MachineFunction::iterator BBI(SwitchMBB);
12791 ++BBI;
12792 MachineBasicBlock *PeeledSwitchMBB =
12793 FuncInfo.MF->CreateMachineBasicBlock(BB: SwitchMBB->getBasicBlock());
12794 FuncInfo.MF->insert(MBBI: BBI, MBB: PeeledSwitchMBB);
12795
12796 ExportFromCurrentBlock(V: SI.getCondition());
12797 auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
12798 SwitchWorkListItem W = {.MBB: SwitchMBB, .FirstCluster: PeeledCaseIt, .LastCluster: PeeledCaseIt,
12799 .GE: nullptr, .LT: nullptr, .DefaultProb: TopCaseProb.getCompl()};
12800 lowerWorkItem(W, Cond: SI.getCondition(), SwitchMBB, DefaultMBB: PeeledSwitchMBB);
12801
12802 Clusters.erase(position: PeeledCaseIt);
12803 for (CaseCluster &CC : Clusters) {
12804 LLVM_DEBUG(
12805 dbgs() << "Scale the probablity for one cluster, before scaling: "
12806 << CC.Prob << "\n");
12807 CC.Prob = scaleCaseProbality(CaseProb: CC.Prob, PeeledCaseProb: TopCaseProb);
12808 LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n");
12809 }
12810 PeeledCaseProb = TopCaseProb;
12811 return PeeledSwitchMBB;
12812}
12813
12814void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
12815 // Extract cases from the switch.
12816 BranchProbabilityInfo *BPI = FuncInfo.BPI;
12817 CaseClusterVector Clusters;
12818 Clusters.reserve(n: SI.getNumCases());
12819 for (auto I : SI.cases()) {
12820 MachineBasicBlock *Succ = FuncInfo.getMBB(BB: I.getCaseSuccessor());
12821 const ConstantInt *CaseVal = I.getCaseValue();
12822 BranchProbability Prob =
12823 BPI ? BPI->getEdgeProbability(Src: SI.getParent(), IndexInSuccessors: I.getSuccessorIndex())
12824 : BranchProbability(1, SI.getNumCases() + 1);
12825 Clusters.push_back(x: CaseCluster::range(Low: CaseVal, High: CaseVal, MBB: Succ, Prob));
12826 }
12827
12828 MachineBasicBlock *DefaultMBB = FuncInfo.getMBB(BB: SI.getDefaultDest());
12829
12830 // Cluster adjacent cases with the same destination. We do this at all
12831 // optimization levels because it's cheap to do and will make codegen faster
12832 // if there are many clusters.
12833 sortAndRangeify(Clusters);
12834
12835 // The branch probablity of the peeled case.
12836 BranchProbability PeeledCaseProb = BranchProbability::getZero();
12837 MachineBasicBlock *PeeledSwitchMBB =
12838 peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);
12839
12840 // If there is only the default destination, jump there directly.
12841 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
12842 if (Clusters.empty()) {
12843 assert(PeeledSwitchMBB == SwitchMBB);
12844 SwitchMBB->addSuccessor(Succ: DefaultMBB);
12845 if (DefaultMBB != NextBlock(MBB: SwitchMBB)) {
12846 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(), VT: MVT::Other,
12847 N1: getControlRoot(), N2: DAG.getBasicBlock(MBB: DefaultMBB)));
12848 }
12849 return;
12850 }
12851
12852 SL->findJumpTables(Clusters, SI: &SI, SL: getCurSDLoc(), DefaultMBB, PSI: DAG.getPSI(),
12853 BFI: DAG.getBFI());
12854 SL->findBitTestClusters(Clusters, SI: &SI);
12855
12856 LLVM_DEBUG({
12857 dbgs() << "Case clusters: ";
12858 for (const CaseCluster &C : Clusters) {
12859 if (C.Kind == CC_JumpTable)
12860 dbgs() << "JT:";
12861 if (C.Kind == CC_BitTests)
12862 dbgs() << "BT:";
12863
12864 C.Low->getValue().print(dbgs(), true);
12865 if (C.Low != C.High) {
12866 dbgs() << '-';
12867 C.High->getValue().print(dbgs(), true);
12868 }
12869 dbgs() << ' ';
12870 }
12871 dbgs() << '\n';
12872 });
12873
12874 assert(!Clusters.empty());
12875 SwitchWorkList WorkList;
12876 CaseClusterIt First = Clusters.begin();
12877 CaseClusterIt Last = Clusters.end() - 1;
12878 auto DefaultProb = getEdgeProbability(Src: PeeledSwitchMBB, Dst: DefaultMBB);
12879 // Scale the branchprobability for DefaultMBB if the peel occurs and
12880 // DefaultMBB is not replaced.
12881 if (PeeledCaseProb != BranchProbability::getZero() &&
12882 DefaultMBB == FuncInfo.getMBB(BB: SI.getDefaultDest()))
12883 DefaultProb = scaleCaseProbality(CaseProb: DefaultProb, PeeledCaseProb);
12884 WorkList.push_back(
12885 Elt: {.MBB: PeeledSwitchMBB, .FirstCluster: First, .LastCluster: Last, .GE: nullptr, .LT: nullptr, .DefaultProb: DefaultProb});
12886
12887 while (!WorkList.empty()) {
12888 SwitchWorkListItem W = WorkList.pop_back_val();
12889 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
12890
12891 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOptLevel::None &&
12892 !DefaultMBB->getParent()->getFunction().hasMinSize()) {
12893 // For optimized builds, lower large range as a balanced binary tree.
12894 splitWorkItem(WorkList, W, Cond: SI.getCondition(), SwitchMBB);
12895 continue;
12896 }
12897
12898 lowerWorkItem(W, Cond: SI.getCondition(), SwitchMBB, DefaultMBB);
12899 }
12900}
12901
12902void SelectionDAGBuilder::visitStepVector(const CallInst &I) {
12903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12904 auto DL = getCurSDLoc();
12905 EVT ResultVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
12906 setValue(V: &I, NewN: DAG.getStepVector(DL, ResVT: ResultVT));
12907}
12908
12909void SelectionDAGBuilder::visitVectorReverse(const CallInst &I) {
12910 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12911 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
12912
12913 SDLoc DL = getCurSDLoc();
12914 SDValue V = getValue(V: I.getOperand(i_nocapture: 0));
12915 assert(VT == V.getValueType() && "Malformed vector.reverse!");
12916
12917 if (VT.isScalableVector()) {
12918 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::VECTOR_REVERSE, DL, VT, Operand: V));
12919 return;
12920 }
12921
12922 // Use VECTOR_SHUFFLE for the fixed-length vector
12923 // to maintain existing behavior.
12924 SmallVector<int, 8> Mask;
12925 unsigned NumElts = VT.getVectorMinNumElements();
12926 for (unsigned i = 0; i != NumElts; ++i)
12927 Mask.push_back(Elt: NumElts - 1 - i);
12928
12929 setValue(V: &I, NewN: DAG.getVectorShuffle(VT, dl: DL, N1: V, N2: DAG.getUNDEF(VT), Mask));
12930}
12931
12932void SelectionDAGBuilder::visitVectorDeinterleave(const CallInst &I,
12933 unsigned Factor) {
12934 auto DL = getCurSDLoc();
12935 SDValue InVec = getValue(V: I.getOperand(i_nocapture: 0));
12936
12937 SmallVector<EVT, 4> ValueVTs;
12938 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(), Ty: I.getType(),
12939 ValueVTs);
12940
12941 EVT OutVT = ValueVTs[0];
12942 unsigned OutNumElts = OutVT.getVectorMinNumElements();
12943
12944 SmallVector<SDValue, 4> SubVecs(Factor);
12945 for (unsigned i = 0; i != Factor; ++i) {
12946 assert(ValueVTs[i] == OutVT && "Expected VTs to be the same");
12947 SubVecs[i] = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT: OutVT, N1: InVec,
12948 N2: DAG.getVectorIdxConstant(Val: OutNumElts * i, DL));
12949 }
12950
12951 // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
12952 // from existing legalisation and combines.
12953 if (OutVT.isFixedLengthVector() && Factor == 2) {
12954 SDValue Even = DAG.getVectorShuffle(VT: OutVT, dl: DL, N1: SubVecs[0], N2: SubVecs[1],
12955 Mask: createStrideMask(Start: 0, Stride: 2, VF: OutNumElts));
12956 SDValue Odd = DAG.getVectorShuffle(VT: OutVT, dl: DL, N1: SubVecs[0], N2: SubVecs[1],
12957 Mask: createStrideMask(Start: 1, Stride: 2, VF: OutNumElts));
12958 SDValue Res = DAG.getMergeValues(Ops: {Even, Odd}, dl: getCurSDLoc());
12959 setValue(V: &I, NewN: Res);
12960 return;
12961 }
12962
12963 SDValue Res = DAG.getNode(Opcode: ISD::VECTOR_DEINTERLEAVE, DL,
12964 VTList: DAG.getVTList(VTs: ValueVTs), Ops: SubVecs);
12965 setValue(V: &I, NewN: Res);
12966}
12967
12968void SelectionDAGBuilder::visitVectorInterleave(const CallInst &I,
12969 unsigned Factor) {
12970 auto DL = getCurSDLoc();
12971 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12972 EVT InVT = getValue(V: I.getOperand(i_nocapture: 0)).getValueType();
12973 EVT OutVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
12974
12975 SmallVector<SDValue, 8> InVecs(Factor);
12976 for (unsigned i = 0; i < Factor; ++i) {
12977 InVecs[i] = getValue(V: I.getOperand(i_nocapture: i));
12978 assert(InVecs[i].getValueType() == InVecs[0].getValueType() &&
12979 "Expected VTs to be the same");
12980 }
12981
12982 // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
12983 // from existing legalisation and combines.
12984 if (OutVT.isFixedLengthVector() && Factor == 2) {
12985 unsigned NumElts = InVT.getVectorMinNumElements();
12986 SDValue V = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: OutVT, Ops: InVecs);
12987 setValue(V: &I, NewN: DAG.getVectorShuffle(VT: OutVT, dl: DL, N1: V, N2: DAG.getUNDEF(VT: OutVT),
12988 Mask: createInterleaveMask(VF: NumElts, NumVecs: 2)));
12989 return;
12990 }
12991
12992 SmallVector<EVT, 8> ValueVTs(Factor, InVT);
12993 SDValue Res =
12994 DAG.getNode(Opcode: ISD::VECTOR_INTERLEAVE, DL, VTList: DAG.getVTList(VTs: ValueVTs), Ops: InVecs);
12995
12996 SmallVector<SDValue, 8> Results(Factor);
12997 for (unsigned i = 0; i < Factor; ++i)
12998 Results[i] = Res.getValue(R: i);
12999
13000 Res = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: OutVT, Ops: Results);
13001 setValue(V: &I, NewN: Res);
13002}
13003
13004void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) {
13005 SmallVector<EVT, 4> ValueVTs;
13006 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(), Ty: I.getType(),
13007 ValueVTs);
13008 unsigned NumValues = ValueVTs.size();
13009 if (NumValues == 0) return;
13010
13011 SmallVector<SDValue, 4> Values(NumValues);
13012 SDValue Op = getValue(V: I.getOperand(i_nocapture: 0));
13013
13014 for (unsigned i = 0; i != NumValues; ++i)
13015 Values[i] = DAG.getNode(Opcode: ISD::FREEZE, DL: getCurSDLoc(), VT: ValueVTs[i],
13016 Operand: SDValue(Op.getNode(), Op.getResNo() + i));
13017
13018 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
13019 VTList: DAG.getVTList(VTs: ValueVTs), Ops: Values));
13020}
13021
13022void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) {
13023 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13024 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
13025
13026 SDLoc DL = getCurSDLoc();
13027 SDValue V1 = getValue(V: I.getOperand(i_nocapture: 0));
13028 SDValue V2 = getValue(V: I.getOperand(i_nocapture: 1));
13029 const bool IsLeft = I.getIntrinsicID() == Intrinsic::vector_splice_left;
13030
13031 // VECTOR_SHUFFLE doesn't support a scalable or non-constant mask.
13032 if (VT.isScalableVector() || !isa<ConstantInt>(Val: I.getOperand(i_nocapture: 2))) {
13033 SDValue Offset = DAG.getZExtOrTrunc(
13034 Op: getValue(V: I.getOperand(i_nocapture: 2)), DL, VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
13035 setValue(V: &I, NewN: DAG.getNode(Opcode: IsLeft ? ISD::VECTOR_SPLICE_LEFT
13036 : ISD::VECTOR_SPLICE_RIGHT,
13037 DL, VT, N1: V1, N2: V2, N3: Offset));
13038 return;
13039 }
13040 uint64_t Imm = cast<ConstantInt>(Val: I.getOperand(i_nocapture: 2))->getZExtValue();
13041
13042 unsigned NumElts = VT.getVectorNumElements();
13043
13044 uint64_t Idx = IsLeft ? Imm : NumElts - Imm;
13045
13046 // Use VECTOR_SHUFFLE to maintain original behaviour for fixed-length vectors.
13047 SmallVector<int, 8> Mask;
13048 for (unsigned i = 0; i < NumElts; ++i)
13049 Mask.push_back(Elt: Idx + i);
13050 setValue(V: &I, NewN: DAG.getVectorShuffle(VT, dl: DL, N1: V1, N2: V2, Mask));
13051}
13052
13053// Consider the following MIR after SelectionDAG, which produces output in
13054// phyregs in the first case or virtregs in the second case.
13055//
13056// INLINEASM_BR ..., implicit-def $ebx, ..., implicit-def $edx
13057// %5:gr32 = COPY $ebx
13058// %6:gr32 = COPY $edx
13059// %1:gr32 = COPY %6:gr32
13060// %0:gr32 = COPY %5:gr32
13061//
13062// INLINEASM_BR ..., def %5:gr32, ..., def %6:gr32
13063// %1:gr32 = COPY %6:gr32
13064// %0:gr32 = COPY %5:gr32
13065//
13066// Given %0, we'd like to return $ebx in the first case and %5 in the second.
13067// Given %1, we'd like to return $edx in the first case and %6 in the second.
13068//
13069// If a callbr has outputs, it will have a single mapping in FuncInfo.ValueMap
13070// to a single virtreg (such as %0). The remaining outputs monotonically
13071// increase in virtreg number from there. If a callbr has no outputs, then it
13072// should not have a corresponding callbr landingpad; in fact, the callbr
13073// landingpad would not even be able to refer to such a callbr.
13074static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg) {
13075 MachineInstr *MI = MRI.def_begin(RegNo: Reg)->getParent();
13076 // There is definitely at least one copy.
13077 assert(MI->getOpcode() == TargetOpcode::COPY &&
13078 "start of copy chain MUST be COPY");
13079 Reg = MI->getOperand(i: 1).getReg();
13080
13081 // If the copied register in the first copy must be virtual.
13082 assert(Reg.isVirtual() && "expected COPY of virtual register");
13083 MI = MRI.def_begin(RegNo: Reg)->getParent();
13084
13085 // There may be an optional second copy.
13086 if (MI->getOpcode() == TargetOpcode::COPY) {
13087 assert(Reg.isVirtual() && "expected COPY of virtual register");
13088 Reg = MI->getOperand(i: 1).getReg();
13089 assert(Reg.isPhysical() && "expected COPY of physical register");
13090 } else {
13091 // The start of the chain must be an INLINEASM_BR.
13092 assert(MI->getOpcode() == TargetOpcode::INLINEASM_BR &&
13093 "end of copy chain MUST be INLINEASM_BR");
13094 }
13095
13096 return Reg;
13097}
13098
13099// We must do this walk rather than the simpler
13100// setValue(&I, getCopyFromRegs(CBR, CBR->getType()));
13101// otherwise we will end up with copies of virtregs only valid along direct
13102// edges.
13103void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) {
13104 SmallVector<EVT, 8> ResultVTs;
13105 SmallVector<SDValue, 8> ResultValues;
13106 const auto *CBR =
13107 cast<CallBrInst>(Val: I.getParent()->getUniquePredecessor()->getTerminator());
13108
13109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13110 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
13111 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
13112
13113 Register InitialDef = FuncInfo.ValueMap[CBR];
13114 SDValue Chain = DAG.getRoot();
13115
13116 // Re-parse the asm constraints string.
13117 TargetLowering::AsmOperandInfoVector TargetConstraints =
13118 TLI.ParseConstraints(DL: DAG.getDataLayout(), TRI, Call: *CBR);
13119 for (auto &T : TargetConstraints) {
13120 SDISelAsmOperandInfo OpInfo(T);
13121 if (OpInfo.Type != InlineAsm::isOutput)
13122 continue;
13123
13124 // Pencil in OpInfo.ConstraintType and OpInfo.ConstraintVT based on the
13125 // individual constraint.
13126 TLI.ComputeConstraintToUse(OpInfo, Op: OpInfo.CallOperand, DAG: &DAG);
13127
13128 switch (OpInfo.ConstraintType) {
13129 case TargetLowering::C_Register:
13130 case TargetLowering::C_RegisterClass: {
13131 // Fill in OpInfo.AssignedRegs.Regs.
13132 getRegistersForValue(DAG, DL: getCurSDLoc(), OpInfo, RefOpInfo&: OpInfo);
13133
13134 // getRegistersForValue may produce 1 to many registers based on whether
13135 // the OpInfo.ConstraintVT is legal on the target or not.
13136 for (Register &Reg : OpInfo.AssignedRegs.Regs) {
13137 Register OriginalDef = FollowCopyChain(MRI, Reg: InitialDef++);
13138 if (OriginalDef.isPhysical())
13139 FuncInfo.MBB->addLiveIn(PhysReg: OriginalDef);
13140 // Update the assigned registers to use the original defs.
13141 Reg = OriginalDef;
13142 }
13143
13144 SDValue V = OpInfo.AssignedRegs.getCopyFromRegs(
13145 DAG, FuncInfo, dl: getCurSDLoc(), Chain, Glue: nullptr, V: CBR);
13146 ResultValues.push_back(Elt: V);
13147 ResultVTs.push_back(Elt: OpInfo.ConstraintVT);
13148 break;
13149 }
13150 case TargetLowering::C_Other: {
13151 SDValue Flag;
13152 SDValue V = TLI.LowerAsmOutputForConstraint(Chain, Glue&: Flag, DL: getCurSDLoc(),
13153 OpInfo, DAG);
13154 ++InitialDef;
13155 ResultValues.push_back(Elt: V);
13156 ResultVTs.push_back(Elt: OpInfo.ConstraintVT);
13157 break;
13158 }
13159 default:
13160 break;
13161 }
13162 }
13163 SDValue V = DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
13164 VTList: DAG.getVTList(VTs: ResultVTs), Ops: ResultValues);
13165 setValue(V: &I, NewN: V);
13166}
13167