1//===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating from LLVM IR into SelectionDAG IR.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SelectionDAGBuilder.h"
14#include "SDNodeDbgValue.h"
15#include "llvm/ADT/APFloat.h"
16#include "llvm/ADT/APInt.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallPtrSet.h"
20#include "llvm/ADT/StringExtras.h"
21#include "llvm/ADT/StringRef.h"
22#include "llvm/ADT/Twine.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/Analysis/BranchProbabilityInfo.h"
25#include "llvm/Analysis/ConstantFolding.h"
26#include "llvm/Analysis/Loads.h"
27#include "llvm/Analysis/MemoryLocation.h"
28#include "llvm/Analysis/TargetLibraryInfo.h"
29#include "llvm/Analysis/TargetTransformInfo.h"
30#include "llvm/Analysis/ValueTracking.h"
31#include "llvm/Analysis/VectorUtils.h"
32#include "llvm/CodeGen/Analysis.h"
33#include "llvm/CodeGen/AssignmentTrackingAnalysis.h"
34#include "llvm/CodeGen/CodeGenCommonISel.h"
35#include "llvm/CodeGen/FunctionLoweringInfo.h"
36#include "llvm/CodeGen/GCMetadata.h"
37#include "llvm/CodeGen/ISDOpcodes.h"
38#include "llvm/CodeGen/MachineBasicBlock.h"
39#include "llvm/CodeGen/MachineFrameInfo.h"
40#include "llvm/CodeGen/MachineFunction.h"
41#include "llvm/CodeGen/MachineInstrBuilder.h"
42#include "llvm/CodeGen/MachineInstrBundleIterator.h"
43#include "llvm/CodeGen/MachineMemOperand.h"
44#include "llvm/CodeGen/MachineModuleInfo.h"
45#include "llvm/CodeGen/MachineOperand.h"
46#include "llvm/CodeGen/MachineRegisterInfo.h"
47#include "llvm/CodeGen/SelectionDAG.h"
48#include "llvm/CodeGen/SelectionDAGNodes.h"
49#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
50#include "llvm/CodeGen/StackMaps.h"
51#include "llvm/CodeGen/SwiftErrorValueTracking.h"
52#include "llvm/CodeGen/TargetFrameLowering.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetOpcodes.h"
55#include "llvm/CodeGen/TargetRegisterInfo.h"
56#include "llvm/CodeGen/TargetSubtargetInfo.h"
57#include "llvm/CodeGen/WinEHFuncInfo.h"
58#include "llvm/IR/Argument.h"
59#include "llvm/IR/Attributes.h"
60#include "llvm/IR/BasicBlock.h"
61#include "llvm/IR/CFG.h"
62#include "llvm/IR/CallingConv.h"
63#include "llvm/IR/Constant.h"
64#include "llvm/IR/ConstantRange.h"
65#include "llvm/IR/Constants.h"
66#include "llvm/IR/DataLayout.h"
67#include "llvm/IR/DebugInfo.h"
68#include "llvm/IR/DebugInfoMetadata.h"
69#include "llvm/IR/DerivedTypes.h"
70#include "llvm/IR/DiagnosticInfo.h"
71#include "llvm/IR/EHPersonalities.h"
72#include "llvm/IR/Function.h"
73#include "llvm/IR/GetElementPtrTypeIterator.h"
74#include "llvm/IR/InlineAsm.h"
75#include "llvm/IR/InstrTypes.h"
76#include "llvm/IR/Instructions.h"
77#include "llvm/IR/IntrinsicInst.h"
78#include "llvm/IR/Intrinsics.h"
79#include "llvm/IR/IntrinsicsAArch64.h"
80#include "llvm/IR/IntrinsicsAMDGPU.h"
81#include "llvm/IR/IntrinsicsWebAssembly.h"
82#include "llvm/IR/LLVMContext.h"
83#include "llvm/IR/MemoryModelRelaxationAnnotations.h"
84#include "llvm/IR/Metadata.h"
85#include "llvm/IR/Module.h"
86#include "llvm/IR/Operator.h"
87#include "llvm/IR/PatternMatch.h"
88#include "llvm/IR/Statepoint.h"
89#include "llvm/IR/Type.h"
90#include "llvm/IR/User.h"
91#include "llvm/IR/Value.h"
92#include "llvm/MC/MCContext.h"
93#include "llvm/Support/AtomicOrdering.h"
94#include "llvm/Support/Casting.h"
95#include "llvm/Support/CommandLine.h"
96#include "llvm/Support/Compiler.h"
97#include "llvm/Support/Debug.h"
98#include "llvm/Support/InstructionCost.h"
99#include "llvm/Support/MathExtras.h"
100#include "llvm/Support/raw_ostream.h"
101#include "llvm/Target/TargetMachine.h"
102#include "llvm/Target/TargetOptions.h"
103#include "llvm/TargetParser/Triple.h"
104#include "llvm/Transforms/Utils/Local.h"
105#include <cstddef>
106#include <limits>
107#include <optional>
108#include <tuple>
109
110using namespace llvm;
111using namespace PatternMatch;
112using namespace SwitchCG;
113
114#define DEBUG_TYPE "isel"
115
116/// LimitFloatPrecision - Generate low-precision inline sequences for
117/// some float libcalls (6, 8 or 12 bits).
118static unsigned LimitFloatPrecision;
119
120static cl::opt<bool>
121 InsertAssertAlign("insert-assert-align", cl::init(Val: true),
122 cl::desc("Insert the experimental `assertalign` node."),
123 cl::ReallyHidden);
124
125static cl::opt<unsigned, true>
126 LimitFPPrecision("limit-float-precision",
127 cl::desc("Generate low-precision inline sequences "
128 "for some float libcalls"),
129 cl::location(L&: LimitFloatPrecision), cl::Hidden,
130 cl::init(Val: 0));
131
132static cl::opt<unsigned> SwitchPeelThreshold(
133 "switch-peel-threshold", cl::Hidden, cl::init(Val: 66),
134 cl::desc("Set the case probability threshold for peeling the case from a "
135 "switch statement. A value greater than 100 will void this "
136 "optimization"));
137
138// Limit the width of DAG chains. This is important in general to prevent
139// DAG-based analysis from blowing up. For example, alias analysis and
140// load clustering may not complete in reasonable time. It is difficult to
141// recognize and avoid this situation within each individual analysis, and
142// future analyses are likely to have the same behavior. Limiting DAG width is
143// the safe approach and will be especially important with global DAGs.
144//
145// MaxParallelChains default is arbitrarily high to avoid affecting
146// optimization, but could be lowered to improve compile time. Any ld-ld-st-st
147// sequence over this should have been converted to llvm.memcpy by the
148// frontend. It is easy to induce this behavior with .ll code such as:
149// %buffer = alloca [4096 x i8]
150// %data = load [4096 x i8]* %argPtr
151// store [4096 x i8] %data, [4096 x i8]* %buffer
152static const unsigned MaxParallelChains = 64;
153
154static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
155 const SDValue *Parts, unsigned NumParts,
156 MVT PartVT, EVT ValueVT, const Value *V,
157 SDValue InChain,
158 std::optional<CallingConv::ID> CC);
159
160/// getCopyFromParts - Create a value that contains the specified legal parts
161/// combined into the value they represent. If the parts combine to a type
162/// larger than ValueVT then AssertOp can be used to specify whether the extra
163/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
164/// (ISD::AssertSext).
165static SDValue
166getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
167 unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V,
168 SDValue InChain,
169 std::optional<CallingConv::ID> CC = std::nullopt,
170 std::optional<ISD::NodeType> AssertOp = std::nullopt) {
171 // Let the target assemble the parts if it wants to
172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
173 if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts,
174 PartVT, ValueVT, CC))
175 return Val;
176
177 if (ValueVT.isVector())
178 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
179 InChain, CC);
180
181 assert(NumParts > 0 && "No parts to assemble!");
182 SDValue Val = Parts[0];
183
184 if (NumParts > 1) {
185 // Assemble the value from multiple parts.
186 if (ValueVT.isInteger()) {
187 unsigned PartBits = PartVT.getSizeInBits();
188 unsigned ValueBits = ValueVT.getSizeInBits();
189
190 // Assemble the power of 2 part.
191 unsigned RoundParts = llvm::bit_floor(Value: NumParts);
192 unsigned RoundBits = PartBits * RoundParts;
193 EVT RoundVT = RoundBits == ValueBits ?
194 ValueVT : EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RoundBits);
195 SDValue Lo, Hi;
196
197 EVT HalfVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RoundBits/2);
198
199 if (RoundParts > 2) {
200 Lo = getCopyFromParts(DAG, DL, Parts, NumParts: RoundParts / 2, PartVT, ValueVT: HalfVT, V,
201 InChain);
202 Hi = getCopyFromParts(DAG, DL, Parts: Parts + RoundParts / 2, NumParts: RoundParts / 2,
203 PartVT, ValueVT: HalfVT, V, InChain);
204 } else {
205 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: HalfVT, Operand: Parts[0]);
206 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: HalfVT, Operand: Parts[1]);
207 }
208
209 if (DAG.getDataLayout().isBigEndian())
210 std::swap(a&: Lo, b&: Hi);
211
212 Val = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL, VT: RoundVT, N1: Lo, N2: Hi);
213
214 if (RoundParts < NumParts) {
215 // Assemble the trailing non-power-of-2 part.
216 unsigned OddParts = NumParts - RoundParts;
217 EVT OddVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: OddParts * PartBits);
218 Hi = getCopyFromParts(DAG, DL, Parts: Parts + RoundParts, NumParts: OddParts, PartVT,
219 ValueVT: OddVT, V, InChain, CC);
220
221 // Combine the round and odd parts.
222 Lo = Val;
223 if (DAG.getDataLayout().isBigEndian())
224 std::swap(a&: Lo, b&: Hi);
225 EVT TotalVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumParts * PartBits);
226 Hi = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: TotalVT, Operand: Hi);
227 Hi = DAG.getNode(
228 Opcode: ISD::SHL, DL, VT: TotalVT, N1: Hi,
229 N2: DAG.getShiftAmountConstant(Val: Lo.getValueSizeInBits(), VT: TotalVT, DL));
230 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: TotalVT, Operand: Lo);
231 Val = DAG.getNode(Opcode: ISD::OR, DL, VT: TotalVT, N1: Lo, N2: Hi);
232 }
233 } else if (PartVT.isFloatingPoint()) {
234 // FP split into multiple FP parts (for ppcf128)
235 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
236 "Unexpected split");
237 SDValue Lo, Hi;
238 Lo = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: EVT(MVT::f64), Operand: Parts[0]);
239 Hi = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: EVT(MVT::f64), Operand: Parts[1]);
240 if (TLI.hasBigEndianPartOrdering(VT: ValueVT, DL: DAG.getDataLayout()))
241 std::swap(a&: Lo, b&: Hi);
242 Val = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL, VT: ValueVT, N1: Lo, N2: Hi);
243 } else {
244 // FP split into integer parts (soft fp)
245 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
246 !PartVT.isVector() && "Unexpected split");
247 EVT IntVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueVT.getSizeInBits());
248 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, ValueVT: IntVT, V,
249 InChain, CC);
250 }
251 }
252
253 // There is now one part, held in Val. Correct it to match ValueVT.
254 // PartEVT is the type of the register class that holds the value.
255 // ValueVT is the type of the inline asm operation.
256 EVT PartEVT = Val.getValueType();
257
258 if (PartEVT == ValueVT)
259 return Val;
260
261 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
262 ValueVT.bitsLT(VT: PartEVT)) {
263 // For an FP value in an integer part, we need to truncate to the right
264 // width first.
265 PartEVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueVT.getSizeInBits());
266 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: PartEVT, Operand: Val);
267 }
268
269 // Handle types that have the same size.
270 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
271 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
272
273 // Handle types with different sizes.
274 if (PartEVT.isInteger() && ValueVT.isInteger()) {
275 if (ValueVT.bitsLT(VT: PartEVT)) {
276 // For a truncate, see if we have any information to
277 // indicate whether the truncated bits will always be
278 // zero or sign-extension.
279 if (AssertOp)
280 Val = DAG.getNode(Opcode: *AssertOp, DL, VT: PartEVT, N1: Val,
281 N2: DAG.getValueType(ValueVT));
282 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValueVT, Operand: Val);
283 }
284 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValueVT, Operand: Val);
285 }
286
287 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
288 // FP_ROUND's are always exact here.
289 if (ValueVT.bitsLT(VT: Val.getValueType())) {
290
291 SDValue NoChange =
292 DAG.getTargetConstant(Val: 1, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
293
294 if (DAG.getMachineFunction().getFunction().getAttributes().hasFnAttr(
295 Kind: llvm::Attribute::StrictFP)) {
296 return DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL,
297 VTList: DAG.getVTList(VT1: ValueVT, VT2: MVT::Other), N1: InChain, N2: Val,
298 N3: NoChange);
299 }
300
301 return DAG.getNode(Opcode: ISD::FP_ROUND, DL, VT: ValueVT, N1: Val, N2: NoChange);
302 }
303
304 return DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: ValueVT, Operand: Val);
305 }
306
307 // Handle MMX to a narrower integer type by bitcasting MMX to integer and
308 // then truncating.
309 if (PartEVT == MVT::x86mmx && ValueVT.isInteger() &&
310 ValueVT.bitsLT(VT: PartEVT)) {
311 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::i64, Operand: Val);
312 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValueVT, Operand: Val);
313 }
314
315 report_fatal_error(reason: "Unknown mismatch in getCopyFromParts!");
316}
317
318static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
319 const Twine &ErrMsg) {
320 const Instruction *I = dyn_cast_or_null<Instruction>(Val: V);
321 if (!I)
322 return Ctx.emitError(ErrorStr: ErrMsg);
323
324 if (const CallInst *CI = dyn_cast<CallInst>(Val: I))
325 if (CI->isInlineAsm()) {
326 return Ctx.diagnose(DI: DiagnosticInfoInlineAsm(
327 *CI, ErrMsg + ", possible invalid constraint for vector type"));
328 }
329
330 return Ctx.emitError(I, ErrorStr: ErrMsg);
331}
332
333/// getCopyFromPartsVector - Create a value that contains the specified legal
334/// parts combined into the value they represent. If the parts combine to a
335/// type larger than ValueVT then AssertOp can be used to specify whether the
336/// extra bits are known to be zero (ISD::AssertZext) or sign extended from
337/// ValueVT (ISD::AssertSext).
338static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
339 const SDValue *Parts, unsigned NumParts,
340 MVT PartVT, EVT ValueVT, const Value *V,
341 SDValue InChain,
342 std::optional<CallingConv::ID> CallConv) {
343 assert(ValueVT.isVector() && "Not a vector value");
344 assert(NumParts > 0 && "No parts to assemble!");
345 const bool IsABIRegCopy = CallConv.has_value();
346
347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
348 SDValue Val = Parts[0];
349
350 // Handle a multi-element vector.
351 if (NumParts > 1) {
352 EVT IntermediateVT;
353 MVT RegisterVT;
354 unsigned NumIntermediates;
355 unsigned NumRegs;
356
357 if (IsABIRegCopy) {
358 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
359 Context&: *DAG.getContext(), CC: *CallConv, VT: ValueVT, IntermediateVT,
360 NumIntermediates, RegisterVT);
361 } else {
362 NumRegs =
363 TLI.getVectorTypeBreakdown(Context&: *DAG.getContext(), VT: ValueVT, IntermediateVT,
364 NumIntermediates, RegisterVT);
365 }
366
367 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
368 NumParts = NumRegs; // Silence a compiler warning.
369 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
370 assert(RegisterVT.getSizeInBits() ==
371 Parts[0].getSimpleValueType().getSizeInBits() &&
372 "Part type sizes don't match!");
373
374 // Assemble the parts into intermediate operands.
375 SmallVector<SDValue, 8> Ops(NumIntermediates);
376 if (NumIntermediates == NumParts) {
377 // If the register was not expanded, truncate or copy the value,
378 // as appropriate.
379 for (unsigned i = 0; i != NumParts; ++i)
380 Ops[i] = getCopyFromParts(DAG, DL, Parts: &Parts[i], NumParts: 1, PartVT, ValueVT: IntermediateVT,
381 V, InChain, CC: CallConv);
382 } else if (NumParts > 0) {
383 // If the intermediate type was expanded, build the intermediate
384 // operands from the parts.
385 assert(NumParts % NumIntermediates == 0 &&
386 "Must expand into a divisible number of parts!");
387 unsigned Factor = NumParts / NumIntermediates;
388 for (unsigned i = 0; i != NumIntermediates; ++i)
389 Ops[i] = getCopyFromParts(DAG, DL, Parts: &Parts[i * Factor], NumParts: Factor, PartVT,
390 ValueVT: IntermediateVT, V, InChain, CC: CallConv);
391 }
392
393 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
394 // intermediate operands.
395 EVT BuiltVectorTy =
396 IntermediateVT.isVector()
397 ? EVT::getVectorVT(
398 Context&: *DAG.getContext(), VT: IntermediateVT.getScalarType(),
399 EC: IntermediateVT.getVectorElementCount() * NumParts)
400 : EVT::getVectorVT(Context&: *DAG.getContext(),
401 VT: IntermediateVT.getScalarType(),
402 NumElements: NumIntermediates);
403 Val = DAG.getNode(Opcode: IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
404 : ISD::BUILD_VECTOR,
405 DL, VT: BuiltVectorTy, Ops);
406 }
407
408 // There is now one part, held in Val. Correct it to match ValueVT.
409 EVT PartEVT = Val.getValueType();
410
411 if (PartEVT == ValueVT)
412 return Val;
413
414 if (PartEVT.isVector()) {
415 // Vector/Vector bitcast.
416 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
417 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
418
419 // If the parts vector has more elements than the value vector, then we
420 // have a vector widening case (e.g. <2 x float> -> <4 x float>).
421 // Extract the elements we want.
422 if (PartEVT.getVectorElementCount() != ValueVT.getVectorElementCount()) {
423 assert((PartEVT.getVectorElementCount().getKnownMinValue() >
424 ValueVT.getVectorElementCount().getKnownMinValue()) &&
425 (PartEVT.getVectorElementCount().isScalable() ==
426 ValueVT.getVectorElementCount().isScalable()) &&
427 "Cannot narrow, it would be a lossy transformation");
428 PartEVT =
429 EVT::getVectorVT(Context&: *DAG.getContext(), VT: PartEVT.getVectorElementType(),
430 EC: ValueVT.getVectorElementCount());
431 Val = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT: PartEVT, N1: Val,
432 N2: DAG.getVectorIdxConstant(Val: 0, DL));
433 if (PartEVT == ValueVT)
434 return Val;
435 if (PartEVT.isInteger() && ValueVT.isFloatingPoint())
436 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
437
438 // Vector/Vector bitcast (e.g. <2 x bfloat> -> <2 x half>).
439 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
440 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
441 }
442
443 // Promoted vector extract
444 return DAG.getAnyExtOrTrunc(Op: Val, DL, VT: ValueVT);
445 }
446
447 // Trivial bitcast if the types are the same size and the destination
448 // vector type is legal.
449 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
450 TLI.isTypeLegal(VT: ValueVT))
451 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
452
453 if (ValueVT.getVectorNumElements() != 1) {
454 // Certain ABIs require that vectors are passed as integers. For vectors
455 // are the same size, this is an obvious bitcast.
456 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) {
457 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
458 } else if (ValueVT.bitsLT(VT: PartEVT)) {
459 const uint64_t ValueSize = ValueVT.getFixedSizeInBits();
460 EVT IntermediateType = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueSize);
461 // Drop the extra bits.
462 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: IntermediateType, Operand: Val);
463 return DAG.getBitcast(VT: ValueVT, V: Val);
464 }
465
466 diagnosePossiblyInvalidConstraint(
467 Ctx&: *DAG.getContext(), V, ErrMsg: "non-trivial scalar-to-vector conversion");
468 return DAG.getUNDEF(VT: ValueVT);
469 }
470
471 // Handle cases such as i8 -> <1 x i1>
472 EVT ValueSVT = ValueVT.getVectorElementType();
473 if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) {
474 unsigned ValueSize = ValueSVT.getSizeInBits();
475 if (ValueSize == PartEVT.getSizeInBits()) {
476 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueSVT, Operand: Val);
477 } else if (ValueSVT.isFloatingPoint() && PartEVT.isInteger()) {
478 // It's possible a scalar floating point type gets softened to integer and
479 // then promoted to a larger integer. If PartEVT is the larger integer
480 // we need to truncate it and then bitcast to the FP type.
481 assert(ValueSVT.bitsLT(PartEVT) && "Unexpected types");
482 EVT IntermediateType = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueSize);
483 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: IntermediateType, Operand: Val);
484 Val = DAG.getBitcast(VT: ValueSVT, V: Val);
485 } else {
486 Val = ValueVT.isFloatingPoint()
487 ? DAG.getFPExtendOrRound(Op: Val, DL, VT: ValueSVT)
488 : DAG.getAnyExtOrTrunc(Op: Val, DL, VT: ValueSVT);
489 }
490 }
491
492 return DAG.getBuildVector(VT: ValueVT, DL, Ops: Val);
493}
494
495static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
496 SDValue Val, SDValue *Parts, unsigned NumParts,
497 MVT PartVT, const Value *V,
498 std::optional<CallingConv::ID> CallConv);
499
500/// getCopyToParts - Create a series of nodes that contain the specified value
501/// split into legal parts. If the parts contain more bits than Val, then, for
502/// integers, ExtendKind can be used to specify how to generate the extra bits.
503static void
504getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
505 unsigned NumParts, MVT PartVT, const Value *V,
506 std::optional<CallingConv::ID> CallConv = std::nullopt,
507 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
508 // Let the target split the parts if it wants to
509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
510 if (TLI.splitValueIntoRegisterParts(DAG, DL, Val, Parts, NumParts, PartVT,
511 CC: CallConv))
512 return;
513 EVT ValueVT = Val.getValueType();
514
515 // Handle the vector case separately.
516 if (ValueVT.isVector())
517 return getCopyToPartsVector(DAG, dl: DL, Val, Parts, NumParts, PartVT, V,
518 CallConv);
519
520 unsigned OrigNumParts = NumParts;
521 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
522 "Copying to an illegal type!");
523
524 if (NumParts == 0)
525 return;
526
527 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
528 EVT PartEVT = PartVT;
529 if (PartEVT == ValueVT) {
530 assert(NumParts == 1 && "No-op copy with multiple parts!");
531 Parts[0] = Val;
532 return;
533 }
534
535 unsigned PartBits = PartVT.getSizeInBits();
536 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
537 // If the parts cover more bits than the value has, promote the value.
538 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
539 assert(NumParts == 1 && "Do not know what to promote to!");
540 Val = DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: PartVT, Operand: Val);
541 } else {
542 if (ValueVT.isFloatingPoint()) {
543 // FP values need to be bitcast, then extended if they are being put
544 // into a larger container.
545 ValueVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueVT.getSizeInBits());
546 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ValueVT, Operand: Val);
547 }
548 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
549 ValueVT.isInteger() &&
550 "Unknown mismatch!");
551 ValueVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumParts * PartBits);
552 Val = DAG.getNode(Opcode: ExtendKind, DL, VT: ValueVT, Operand: Val);
553 if (PartVT == MVT::x86mmx)
554 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
555 }
556 } else if (PartBits == ValueVT.getSizeInBits()) {
557 // Different types of the same size.
558 assert(NumParts == 1 && PartEVT != ValueVT);
559 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
560 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
561 // If the parts cover less bits than value has, truncate the value.
562 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
563 ValueVT.isInteger() &&
564 "Unknown mismatch!");
565 ValueVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumParts * PartBits);
566 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValueVT, Operand: Val);
567 if (PartVT == MVT::x86mmx)
568 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
569 }
570
571 // The value may have changed - recompute ValueVT.
572 ValueVT = Val.getValueType();
573 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
574 "Failed to tile the value with PartVT!");
575
576 if (NumParts == 1) {
577 if (PartEVT != ValueVT) {
578 diagnosePossiblyInvalidConstraint(Ctx&: *DAG.getContext(), V,
579 ErrMsg: "scalar-to-vector conversion failed");
580 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
581 }
582
583 Parts[0] = Val;
584 return;
585 }
586
587 // Expand the value into multiple parts.
588 if (NumParts & (NumParts - 1)) {
589 // The number of parts is not a power of 2. Split off and copy the tail.
590 assert(PartVT.isInteger() && ValueVT.isInteger() &&
591 "Do not know what to expand to!");
592 unsigned RoundParts = llvm::bit_floor(Value: NumParts);
593 unsigned RoundBits = RoundParts * PartBits;
594 unsigned OddParts = NumParts - RoundParts;
595 SDValue OddVal = DAG.getNode(Opcode: ISD::SRL, DL, VT: ValueVT, N1: Val,
596 N2: DAG.getShiftAmountConstant(Val: RoundBits, VT: ValueVT, DL));
597
598 getCopyToParts(DAG, DL, Val: OddVal, Parts: Parts + RoundParts, NumParts: OddParts, PartVT, V,
599 CallConv);
600
601 if (DAG.getDataLayout().isBigEndian())
602 // The odd parts were reversed by getCopyToParts - unreverse them.
603 std::reverse(first: Parts + RoundParts, last: Parts + NumParts);
604
605 NumParts = RoundParts;
606 ValueVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumParts * PartBits);
607 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ValueVT, Operand: Val);
608 }
609
610 // The number of parts is a power of 2. Repeatedly bisect the value using
611 // EXTRACT_ELEMENT.
612 Parts[0] = DAG.getNode(Opcode: ISD::BITCAST, DL,
613 VT: EVT::getIntegerVT(Context&: *DAG.getContext(),
614 BitWidth: ValueVT.getSizeInBits()),
615 Operand: Val);
616
617 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
618 for (unsigned i = 0; i < NumParts; i += StepSize) {
619 unsigned ThisBits = StepSize * PartBits / 2;
620 EVT ThisVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ThisBits);
621 SDValue &Part0 = Parts[i];
622 SDValue &Part1 = Parts[i+StepSize/2];
623
624 Part1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL,
625 VT: ThisVT, N1: Part0, N2: DAG.getIntPtrConstant(Val: 1, DL));
626 Part0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL,
627 VT: ThisVT, N1: Part0, N2: DAG.getIntPtrConstant(Val: 0, DL));
628
629 if (ThisBits == PartBits && ThisVT != PartVT) {
630 Part0 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Part0);
631 Part1 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Part1);
632 }
633 }
634 }
635
636 if (DAG.getDataLayout().isBigEndian())
637 std::reverse(first: Parts, last: Parts + OrigNumParts);
638}
639
640static SDValue widenVectorToPartType(SelectionDAG &DAG, SDValue Val,
641 const SDLoc &DL, EVT PartVT) {
642 if (!PartVT.isVector())
643 return SDValue();
644
645 EVT ValueVT = Val.getValueType();
646 EVT PartEVT = PartVT.getVectorElementType();
647 EVT ValueEVT = ValueVT.getVectorElementType();
648 ElementCount PartNumElts = PartVT.getVectorElementCount();
649 ElementCount ValueNumElts = ValueVT.getVectorElementCount();
650
651 // We only support widening vectors with equivalent element types and
652 // fixed/scalable properties. If a target needs to widen a fixed-length type
653 // to a scalable one, it should be possible to use INSERT_SUBVECTOR below.
654 if (ElementCount::isKnownLE(LHS: PartNumElts, RHS: ValueNumElts) ||
655 PartNumElts.isScalable() != ValueNumElts.isScalable())
656 return SDValue();
657
658 // Have a try for bf16 because some targets share its ABI with fp16.
659 if (ValueEVT == MVT::bf16 && PartEVT == MVT::f16) {
660 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
661 "Cannot widen to illegal type");
662 Val = DAG.getNode(
663 Opcode: ISD::BITCAST, DL,
664 VT: ValueVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MVT::f16), Operand: Val);
665 } else if (PartEVT != ValueEVT) {
666 return SDValue();
667 }
668
669 // Widening a scalable vector to another scalable vector is done by inserting
670 // the vector into a larger undef one.
671 if (PartNumElts.isScalable())
672 return DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL, VT: PartVT, N1: DAG.getUNDEF(VT: PartVT),
673 N2: Val, N3: DAG.getVectorIdxConstant(Val: 0, DL));
674
675 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
676 // undef elements.
677 SmallVector<SDValue, 16> Ops;
678 DAG.ExtractVectorElements(Op: Val, Args&: Ops);
679 SDValue EltUndef = DAG.getUNDEF(VT: PartEVT);
680 Ops.append(NumInputs: (PartNumElts - ValueNumElts).getFixedValue(), Elt: EltUndef);
681
682 // FIXME: Use CONCAT for 2x -> 4x.
683 return DAG.getBuildVector(VT: PartVT, DL, Ops);
684}
685
686/// getCopyToPartsVector - Create a series of nodes that contain the specified
687/// value split into legal parts.
688static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
689 SDValue Val, SDValue *Parts, unsigned NumParts,
690 MVT PartVT, const Value *V,
691 std::optional<CallingConv::ID> CallConv) {
692 EVT ValueVT = Val.getValueType();
693 assert(ValueVT.isVector() && "Not a vector");
694 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
695 const bool IsABIRegCopy = CallConv.has_value();
696
697 if (NumParts == 1) {
698 EVT PartEVT = PartVT;
699 if (PartEVT == ValueVT) {
700 // Nothing to do.
701 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
702 // Bitconvert vector->vector case.
703 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: PartVT, Operand: Val);
704 } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) {
705 Val = Widened;
706 } else if (PartVT.isVector() &&
707 PartEVT.getVectorElementType().bitsGE(
708 VT: ValueVT.getVectorElementType()) &&
709 PartEVT.getVectorElementCount() ==
710 ValueVT.getVectorElementCount()) {
711
712 // Promoted vector extract
713 Val = DAG.getAnyExtOrTrunc(Op: Val, DL, VT: PartVT);
714 } else if (PartEVT.isVector() &&
715 PartEVT.getVectorElementType() !=
716 ValueVT.getVectorElementType() &&
717 TLI.getTypeAction(Context&: *DAG.getContext(), VT: ValueVT) ==
718 TargetLowering::TypeWidenVector) {
719 // Combination of widening and promotion.
720 EVT WidenVT =
721 EVT::getVectorVT(Context&: *DAG.getContext(), VT: ValueVT.getVectorElementType(),
722 EC: PartVT.getVectorElementCount());
723 SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT: WidenVT);
724 Val = DAG.getAnyExtOrTrunc(Op: Widened, DL, VT: PartVT);
725 } else {
726 // Don't extract an integer from a float vector. This can happen if the
727 // FP type gets softened to integer and then promoted. The promotion
728 // prevents it from being picked up by the earlier bitcast case.
729 if (ValueVT.getVectorElementCount().isScalar() &&
730 (!ValueVT.isFloatingPoint() || !PartVT.isInteger())) {
731 // If we reach this condition and PartVT is FP, this means that
732 // ValueVT is also FP and both have a different size, otherwise we
733 // would have bitcasted them. Producing an EXTRACT_VECTOR_ELT here
734 // would be invalid since that would mean the smaller FP type has to
735 // be extended to the larger one.
736 if (PartVT.isFloatingPoint()) {
737 Val = DAG.getBitcast(VT: ValueVT.getScalarType(), V: Val);
738 Val = DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: PartVT, Operand: Val);
739 } else
740 Val = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: PartVT, N1: Val,
741 N2: DAG.getVectorIdxConstant(Val: 0, DL));
742 } else {
743 uint64_t ValueSize = ValueVT.getFixedSizeInBits();
744 assert(PartVT.getFixedSizeInBits() > ValueSize &&
745 "lossy conversion of vector to scalar type");
746 EVT IntermediateType = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ValueSize);
747 Val = DAG.getBitcast(VT: IntermediateType, V: Val);
748 Val = DAG.getAnyExtOrTrunc(Op: Val, DL, VT: PartVT);
749 }
750 }
751
752 assert(Val.getValueType() == PartVT && "Unexpected vector part value type");
753 Parts[0] = Val;
754 return;
755 }
756
757 // Handle a multi-element vector.
758 EVT IntermediateVT;
759 MVT RegisterVT;
760 unsigned NumIntermediates;
761 unsigned NumRegs;
762 if (IsABIRegCopy) {
763 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
764 Context&: *DAG.getContext(), CC: *CallConv, VT: ValueVT, IntermediateVT, NumIntermediates,
765 RegisterVT);
766 } else {
767 NumRegs =
768 TLI.getVectorTypeBreakdown(Context&: *DAG.getContext(), VT: ValueVT, IntermediateVT,
769 NumIntermediates, RegisterVT);
770 }
771
772 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
773 NumParts = NumRegs; // Silence a compiler warning.
774 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
775
776 assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() &&
777 "Mixing scalable and fixed vectors when copying in parts");
778
779 std::optional<ElementCount> DestEltCnt;
780
781 if (IntermediateVT.isVector())
782 DestEltCnt = IntermediateVT.getVectorElementCount() * NumIntermediates;
783 else
784 DestEltCnt = ElementCount::getFixed(MinVal: NumIntermediates);
785
786 EVT BuiltVectorTy = EVT::getVectorVT(
787 Context&: *DAG.getContext(), VT: IntermediateVT.getScalarType(), EC: *DestEltCnt);
788
789 if (ValueVT == BuiltVectorTy) {
790 // Nothing to do.
791 } else if (ValueVT.getSizeInBits() == BuiltVectorTy.getSizeInBits()) {
792 // Bitconvert vector->vector case.
793 Val = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: BuiltVectorTy, Operand: Val);
794 } else {
795 if (BuiltVectorTy.getVectorElementType().bitsGT(
796 VT: ValueVT.getVectorElementType())) {
797 // Integer promotion.
798 ValueVT = EVT::getVectorVT(Context&: *DAG.getContext(),
799 VT: BuiltVectorTy.getVectorElementType(),
800 EC: ValueVT.getVectorElementCount());
801 Val = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValueVT, Operand: Val);
802 }
803
804 if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT: BuiltVectorTy)) {
805 Val = Widened;
806 }
807 }
808
809 assert(Val.getValueType() == BuiltVectorTy && "Unexpected vector value type");
810
811 // Split the vector into intermediate operands.
812 SmallVector<SDValue, 8> Ops(NumIntermediates);
813 for (unsigned i = 0; i != NumIntermediates; ++i) {
814 if (IntermediateVT.isVector()) {
815 // This does something sensible for scalable vectors - see the
816 // definition of EXTRACT_SUBVECTOR for further details.
817 unsigned IntermediateNumElts = IntermediateVT.getVectorMinNumElements();
818 Ops[i] =
819 DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT: IntermediateVT, N1: Val,
820 N2: DAG.getVectorIdxConstant(Val: i * IntermediateNumElts, DL));
821 } else {
822 Ops[i] = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: IntermediateVT, N1: Val,
823 N2: DAG.getVectorIdxConstant(Val: i, DL));
824 }
825 }
826
827 // Split the intermediate operands into legal parts.
828 if (NumParts == NumIntermediates) {
829 // If the register was not expanded, promote or copy the value,
830 // as appropriate.
831 for (unsigned i = 0; i != NumParts; ++i)
832 getCopyToParts(DAG, DL, Val: Ops[i], Parts: &Parts[i], NumParts: 1, PartVT, V, CallConv);
833 } else if (NumParts > 0) {
834 // If the intermediate type was expanded, split each the value into
835 // legal parts.
836 assert(NumIntermediates != 0 && "division by zero");
837 assert(NumParts % NumIntermediates == 0 &&
838 "Must expand into a divisible number of parts!");
839 unsigned Factor = NumParts / NumIntermediates;
840 for (unsigned i = 0; i != NumIntermediates; ++i)
841 getCopyToParts(DAG, DL, Val: Ops[i], Parts: &Parts[i * Factor], NumParts: Factor, PartVT, V,
842 CallConv);
843 }
844}
845
846static void failForInvalidBundles(const CallBase &I, StringRef Name,
847 ArrayRef<uint32_t> AllowedBundles) {
848 if (I.hasOperandBundlesOtherThan(IDs: AllowedBundles)) {
849 ListSeparator LS;
850 std::string Error;
851 raw_string_ostream OS(Error);
852 for (unsigned i = 0, e = I.getNumOperandBundles(); i != e; ++i) {
853 OperandBundleUse U = I.getOperandBundleAt(Index: i);
854 if (!is_contained(Range&: AllowedBundles, Element: U.getTagID()))
855 OS << LS << U.getTagName();
856 }
857 reportFatalUsageError(
858 reason: Twine("cannot lower ", Name)
859 .concat(Suffix: Twine(" with arbitrary operand bundles: ", Error)));
860 }
861}
862
863RegsForValue::RegsForValue(const SmallVector<Register, 4> &regs, MVT regvt,
864 EVT valuevt, std::optional<CallingConv::ID> CC)
865 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
866 RegCount(1, regs.size()), CallConv(CC) {}
867
868RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
869 const DataLayout &DL, Register Reg, Type *Ty,
870 std::optional<CallingConv::ID> CC) {
871 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
872
873 CallConv = CC;
874
875 for (EVT ValueVT : ValueVTs) {
876 unsigned NumRegs =
877 isABIMangled()
878 ? TLI.getNumRegistersForCallingConv(Context, CC: *CC, VT: ValueVT)
879 : TLI.getNumRegisters(Context, VT: ValueVT);
880 MVT RegisterVT =
881 isABIMangled()
882 ? TLI.getRegisterTypeForCallingConv(Context, CC: *CC, VT: ValueVT)
883 : TLI.getRegisterType(Context, VT: ValueVT);
884 for (unsigned i = 0; i != NumRegs; ++i)
885 Regs.push_back(Elt: Reg + i);
886 RegVTs.push_back(Elt: RegisterVT);
887 RegCount.push_back(Elt: NumRegs);
888 Reg = Reg.id() + NumRegs;
889 }
890}
891
892SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
893 FunctionLoweringInfo &FuncInfo,
894 const SDLoc &dl, SDValue &Chain,
895 SDValue *Glue, const Value *V) const {
896 // A Value with type {} or [0 x %t] needs no registers.
897 if (ValueVTs.empty())
898 return SDValue();
899
900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
901
902 // Assemble the legal parts into the final values.
903 SmallVector<SDValue, 4> Values(ValueVTs.size());
904 SmallVector<SDValue, 8> Parts;
905 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
906 // Copy the legal parts from the registers.
907 EVT ValueVT = ValueVTs[Value];
908 unsigned NumRegs = RegCount[Value];
909 MVT RegisterVT = isABIMangled()
910 ? TLI.getRegisterTypeForCallingConv(
911 Context&: *DAG.getContext(), CC: *CallConv, VT: RegVTs[Value])
912 : RegVTs[Value];
913
914 Parts.resize(N: NumRegs);
915 for (unsigned i = 0; i != NumRegs; ++i) {
916 SDValue P;
917 if (!Glue) {
918 P = DAG.getCopyFromReg(Chain, dl, Reg: Regs[Part+i], VT: RegisterVT);
919 } else {
920 P = DAG.getCopyFromReg(Chain, dl, Reg: Regs[Part+i], VT: RegisterVT, Glue: *Glue);
921 *Glue = P.getValue(R: 2);
922 }
923
924 Chain = P.getValue(R: 1);
925 Parts[i] = P;
926
927 // If the source register was virtual and if we know something about it,
928 // add an assert node.
929 if (!Regs[Part + i].isVirtual() || !RegisterVT.isInteger())
930 continue;
931
932 const FunctionLoweringInfo::LiveOutInfo *LOI =
933 FuncInfo.GetLiveOutRegInfo(Reg: Regs[Part+i]);
934 if (!LOI)
935 continue;
936
937 unsigned RegSize = RegisterVT.getScalarSizeInBits();
938 unsigned NumSignBits = LOI->NumSignBits;
939 unsigned NumZeroBits = LOI->Known.countMinLeadingZeros();
940
941 if (NumZeroBits == RegSize) {
942 // The current value is a zero.
943 // Explicitly express that as it would be easier for
944 // optimizations to kick in.
945 Parts[i] = DAG.getConstant(Val: 0, DL: dl, VT: RegisterVT);
946 continue;
947 }
948
949 // FIXME: We capture more information than the dag can represent. For
950 // now, just use the tightest assertzext/assertsext possible.
951 bool isSExt;
952 EVT FromVT(MVT::Other);
953 if (NumZeroBits) {
954 FromVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RegSize - NumZeroBits);
955 isSExt = false;
956 } else if (NumSignBits > 1) {
957 FromVT =
958 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RegSize - NumSignBits + 1);
959 isSExt = true;
960 } else {
961 continue;
962 }
963 // Add an assertion node.
964 assert(FromVT != MVT::Other);
965 Parts[i] = DAG.getNode(Opcode: isSExt ? ISD::AssertSext : ISD::AssertZext, DL: dl,
966 VT: RegisterVT, N1: P, N2: DAG.getValueType(FromVT));
967 }
968
969 Values[Value] = getCopyFromParts(DAG, DL: dl, Parts: Parts.begin(), NumParts: NumRegs,
970 PartVT: RegisterVT, ValueVT, V, InChain: Chain, CC: CallConv);
971 Part += NumRegs;
972 Parts.clear();
973 }
974
975 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: dl, VTList: DAG.getVTList(VTs: ValueVTs), Ops: Values);
976}
977
978void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
979 const SDLoc &dl, SDValue &Chain, SDValue *Glue,
980 const Value *V,
981 ISD::NodeType PreferredExtendType) const {
982 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
983 ISD::NodeType ExtendKind = PreferredExtendType;
984
985 // Get the list of the values's legal parts.
986 unsigned NumRegs = Regs.size();
987 SmallVector<SDValue, 8> Parts(NumRegs);
988 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
989 unsigned NumParts = RegCount[Value];
990
991 MVT RegisterVT = isABIMangled()
992 ? TLI.getRegisterTypeForCallingConv(
993 Context&: *DAG.getContext(), CC: *CallConv, VT: RegVTs[Value])
994 : RegVTs[Value];
995
996 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, VT2: RegisterVT))
997 ExtendKind = ISD::ZERO_EXTEND;
998
999 getCopyToParts(DAG, DL: dl, Val: Val.getValue(R: Val.getResNo() + Value), Parts: &Parts[Part],
1000 NumParts, PartVT: RegisterVT, V, CallConv, ExtendKind);
1001 Part += NumParts;
1002 }
1003
1004 // Copy the parts into the registers.
1005 SmallVector<SDValue, 8> Chains(NumRegs);
1006 for (unsigned i = 0; i != NumRegs; ++i) {
1007 SDValue Part;
1008 if (!Glue) {
1009 Part = DAG.getCopyToReg(Chain, dl, Reg: Regs[i], N: Parts[i]);
1010 } else {
1011 Part = DAG.getCopyToReg(Chain, dl, Reg: Regs[i], N: Parts[i], Glue: *Glue);
1012 *Glue = Part.getValue(R: 1);
1013 }
1014
1015 Chains[i] = Part.getValue(R: 0);
1016 }
1017
1018 if (NumRegs == 1 || Glue)
1019 // If NumRegs > 1 && Glue is used then the use of the last CopyToReg is
1020 // flagged to it. That is the CopyToReg nodes and the user are considered
1021 // a single scheduling unit. If we create a TokenFactor and return it as
1022 // chain, then the TokenFactor is both a predecessor (operand) of the
1023 // user as well as a successor (the TF operands are flagged to the user).
1024 // c1, f1 = CopyToReg
1025 // c2, f2 = CopyToReg
1026 // c3 = TokenFactor c1, c2
1027 // ...
1028 // = op c3, ..., f2
1029 Chain = Chains[NumRegs-1];
1030 else
1031 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: Chains);
1032}
1033
1034void RegsForValue::AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
1035 unsigned MatchingIdx, const SDLoc &dl,
1036 SelectionDAG &DAG,
1037 std::vector<SDValue> &Ops) const {
1038 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1039
1040 InlineAsm::Flag Flag(Code, Regs.size());
1041 if (HasMatching)
1042 Flag.setMatchingOp(MatchingIdx);
1043 else if (!Regs.empty() && Regs.front().isVirtual()) {
1044 // Put the register class of the virtual registers in the flag word. That
1045 // way, later passes can recompute register class constraints for inline
1046 // assembly as well as normal instructions.
1047 // Don't do this for tied operands that can use the regclass information
1048 // from the def.
1049 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1050 const TargetRegisterClass *RC = MRI.getRegClass(Reg: Regs.front());
1051 Flag.setRegClass(RC->getID());
1052 }
1053
1054 SDValue Res = DAG.getTargetConstant(Val: Flag, DL: dl, VT: MVT::i32);
1055 Ops.push_back(x: Res);
1056
1057 if (Code == InlineAsm::Kind::Clobber) {
1058 // Clobbers should always have a 1:1 mapping with registers, and may
1059 // reference registers that have illegal (e.g. vector) types. Hence, we
1060 // shouldn't try to apply any sort of splitting logic to them.
1061 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&
1062 "No 1:1 mapping from clobbers to regs?");
1063 Register SP = TLI.getStackPointerRegisterToSaveRestore();
1064 (void)SP;
1065 for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) {
1066 Ops.push_back(x: DAG.getRegister(Reg: Regs[I], VT: RegVTs[I]));
1067 assert(
1068 (Regs[I] != SP ||
1069 DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) &&
1070 "If we clobbered the stack pointer, MFI should know about it.");
1071 }
1072 return;
1073 }
1074
1075 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
1076 MVT RegisterVT = RegVTs[Value];
1077 unsigned NumRegs = TLI.getNumRegisters(Context&: *DAG.getContext(), VT: ValueVTs[Value],
1078 RegisterVT);
1079 for (unsigned i = 0; i != NumRegs; ++i) {
1080 assert(Reg < Regs.size() && "Mismatch in # registers expected");
1081 Register TheReg = Regs[Reg++];
1082 Ops.push_back(x: DAG.getRegister(Reg: TheReg, VT: RegisterVT));
1083 }
1084 }
1085}
1086
1087SmallVector<std::pair<Register, TypeSize>, 4>
1088RegsForValue::getRegsAndSizes() const {
1089 SmallVector<std::pair<Register, TypeSize>, 4> OutVec;
1090 unsigned I = 0;
1091 for (auto CountAndVT : zip_first(t: RegCount, u: RegVTs)) {
1092 unsigned RegCount = std::get<0>(t&: CountAndVT);
1093 MVT RegisterVT = std::get<1>(t&: CountAndVT);
1094 TypeSize RegisterSize = RegisterVT.getSizeInBits();
1095 for (unsigned E = I + RegCount; I != E; ++I)
1096 OutVec.push_back(Elt: std::make_pair(x: Regs[I], y&: RegisterSize));
1097 }
1098 return OutVec;
1099}
1100
1101void SelectionDAGBuilder::init(GCFunctionInfo *gfi, BatchAAResults *aa,
1102 AssumptionCache *ac, const TargetLibraryInfo *li,
1103 const TargetTransformInfo &TTI) {
1104 BatchAA = aa;
1105 AC = ac;
1106 GFI = gfi;
1107 LibInfo = li;
1108 Context = DAG.getContext();
1109 LPadToCallSiteMap.clear();
1110 this->TTI = &TTI;
1111 SL->init(tli: DAG.getTargetLoweringInfo(), tm: TM, dl: DAG.getDataLayout());
1112 AssignmentTrackingEnabled = isAssignmentTrackingEnabled(
1113 M: *DAG.getMachineFunction().getFunction().getParent());
1114}
1115
1116void SelectionDAGBuilder::clear() {
1117 NodeMap.clear();
1118 UnusedArgNodeMap.clear();
1119 PendingLoads.clear();
1120 PendingExports.clear();
1121 PendingConstrainedFP.clear();
1122 PendingConstrainedFPStrict.clear();
1123 CurInst = nullptr;
1124 HasTailCall = false;
1125 SDNodeOrder = LowestSDNodeOrder;
1126 StatepointLowering.clear();
1127}
1128
1129void SelectionDAGBuilder::clearDanglingDebugInfo() {
1130 DanglingDebugInfoMap.clear();
1131}
1132
1133// Update DAG root to include dependencies on Pending chains.
1134SDValue SelectionDAGBuilder::updateRoot(SmallVectorImpl<SDValue> &Pending) {
1135 SDValue Root = DAG.getRoot();
1136
1137 if (Pending.empty())
1138 return Root;
1139
1140 // Add current root to PendingChains, unless we already indirectly
1141 // depend on it.
1142 if (Root.getOpcode() != ISD::EntryToken) {
1143 unsigned i = 0, e = Pending.size();
1144 for (; i != e; ++i) {
1145 assert(Pending[i].getNode()->getNumOperands() > 1);
1146 if (Pending[i].getNode()->getOperand(Num: 0) == Root)
1147 break; // Don't add the root if we already indirectly depend on it.
1148 }
1149
1150 if (i == e)
1151 Pending.push_back(Elt: Root);
1152 }
1153
1154 if (Pending.size() == 1)
1155 Root = Pending[0];
1156 else
1157 Root = DAG.getTokenFactor(DL: getCurSDLoc(), Vals&: Pending);
1158
1159 DAG.setRoot(Root);
1160 Pending.clear();
1161 return Root;
1162}
1163
1164SDValue SelectionDAGBuilder::getMemoryRoot() {
1165 return updateRoot(Pending&: PendingLoads);
1166}
1167
1168SDValue SelectionDAGBuilder::getFPOperationRoot(fp::ExceptionBehavior EB) {
1169 // If the new exception behavior differs from that of the pending
1170 // ones, chain up them and update the root.
1171 switch (EB) {
1172 case fp::ExceptionBehavior::ebMayTrap:
1173 case fp::ExceptionBehavior::ebIgnore:
1174 // Floating-point exceptions produced by such operations are not intended
1175 // to be observed, so the sequence of these operations does not need to be
1176 // preserved.
1177 //
1178 // They however must not be mixed with the instructions that have strict
1179 // exception behavior. Placing an operation with 'ebIgnore' behavior between
1180 // 'ebStrict' operations could distort the observed exception behavior.
1181 if (!PendingConstrainedFPStrict.empty()) {
1182 assert(PendingConstrainedFP.empty());
1183 updateRoot(Pending&: PendingConstrainedFPStrict);
1184 }
1185 break;
1186 case fp::ExceptionBehavior::ebStrict:
1187 // Floating-point exception produced by these operations may be observed, so
1188 // they must be correctly chained. If trapping on FP exceptions is
1189 // disabled, the exceptions can be observed only by functions that read
1190 // exception flags, like 'llvm.get_fpenv' or 'fetestexcept'. It means that
1191 // the order of operations is not significant between barriers.
1192 //
1193 // If trapping is enabled, each operation becomes an implicit observation
1194 // point, so the operations must be sequenced according their original
1195 // source order.
1196 if (!PendingConstrainedFP.empty()) {
1197 assert(PendingConstrainedFPStrict.empty());
1198 updateRoot(Pending&: PendingConstrainedFP);
1199 }
1200 // TODO: Add support for trapping-enabled scenarios.
1201 }
1202 return DAG.getRoot();
1203}
1204
1205SDValue SelectionDAGBuilder::getRoot() {
1206 // Chain up all pending constrained intrinsics together with all
1207 // pending loads, by simply appending them to PendingLoads and
1208 // then calling getMemoryRoot().
1209 PendingLoads.reserve(N: PendingLoads.size() +
1210 PendingConstrainedFP.size() +
1211 PendingConstrainedFPStrict.size());
1212 PendingLoads.append(in_start: PendingConstrainedFP.begin(),
1213 in_end: PendingConstrainedFP.end());
1214 PendingLoads.append(in_start: PendingConstrainedFPStrict.begin(),
1215 in_end: PendingConstrainedFPStrict.end());
1216 PendingConstrainedFP.clear();
1217 PendingConstrainedFPStrict.clear();
1218 return getMemoryRoot();
1219}
1220
1221SDValue SelectionDAGBuilder::getControlRoot() {
1222 // We need to emit pending fpexcept.strict constrained intrinsics,
1223 // so append them to the PendingExports list.
1224 PendingExports.append(in_start: PendingConstrainedFPStrict.begin(),
1225 in_end: PendingConstrainedFPStrict.end());
1226 PendingConstrainedFPStrict.clear();
1227 return updateRoot(Pending&: PendingExports);
1228}
1229
1230void SelectionDAGBuilder::handleDebugDeclare(Value *Address,
1231 DILocalVariable *Variable,
1232 DIExpression *Expression,
1233 DebugLoc DL) {
1234 assert(Variable && "Missing variable");
1235
1236 // Check if address has undef value.
1237 if (!Address || isa<UndefValue>(Val: Address) ||
1238 (Address->use_empty() && !isa<Argument>(Val: Address))) {
1239 LLVM_DEBUG(
1240 dbgs()
1241 << "dbg_declare: Dropping debug info (bad/undef/unused-arg address)\n");
1242 return;
1243 }
1244
1245 bool IsParameter = Variable->isParameter() || isa<Argument>(Val: Address);
1246
1247 SDValue &N = NodeMap[Address];
1248 if (!N.getNode() && isa<Argument>(Val: Address))
1249 // Check unused arguments map.
1250 N = UnusedArgNodeMap[Address];
1251 SDDbgValue *SDV;
1252 if (N.getNode()) {
1253 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Val: Address))
1254 Address = BCI->getOperand(i_nocapture: 0);
1255 // Parameters are handled specially.
1256 auto *FINode = dyn_cast<FrameIndexSDNode>(Val: N.getNode());
1257 if (IsParameter && FINode) {
1258 // Byval parameter. We have a frame index at this point.
1259 SDV = DAG.getFrameIndexDbgValue(Var: Variable, Expr: Expression, FI: FINode->getIndex(),
1260 /*IsIndirect*/ true, DL, O: SDNodeOrder);
1261 } else if (isa<Argument>(Val: Address)) {
1262 // Address is an argument, so try to emit its dbg value using
1263 // virtual register info from the FuncInfo.ValueMap.
1264 EmitFuncArgumentDbgValue(V: Address, Variable, Expr: Expression, DL,
1265 Kind: FuncArgumentDbgValueKind::Declare, N);
1266 return;
1267 } else {
1268 SDV = DAG.getDbgValue(Var: Variable, Expr: Expression, N: N.getNode(), R: N.getResNo(),
1269 IsIndirect: true, DL, O: SDNodeOrder);
1270 }
1271 DAG.AddDbgValue(DB: SDV, isParameter: IsParameter);
1272 } else {
1273 // If Address is an argument then try to emit its dbg value using
1274 // virtual register info from the FuncInfo.ValueMap.
1275 if (!EmitFuncArgumentDbgValue(V: Address, Variable, Expr: Expression, DL,
1276 Kind: FuncArgumentDbgValueKind::Declare, N)) {
1277 LLVM_DEBUG(dbgs() << "dbg_declare: Dropping debug info"
1278 << " (could not emit func-arg dbg_value)\n");
1279 }
1280 }
1281}
1282
1283void SelectionDAGBuilder::visitDbgInfo(const Instruction &I) {
1284 // Add SDDbgValue nodes for any var locs here. Do so before updating
1285 // SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}.
1286 if (FunctionVarLocs const *FnVarLocs = DAG.getFunctionVarLocs()) {
1287 // Add SDDbgValue nodes for any var locs here. Do so before updating
1288 // SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}.
1289 for (auto It = FnVarLocs->locs_begin(Before: &I), End = FnVarLocs->locs_end(Before: &I);
1290 It != End; ++It) {
1291 auto *Var = FnVarLocs->getDILocalVariable(ID: It->VariableID);
1292 dropDanglingDebugInfo(Variable: Var, Expr: It->Expr);
1293 if (It->Values.isKillLocation(Expression: It->Expr)) {
1294 handleKillDebugValue(Var, Expr: It->Expr, DbgLoc: It->DL, Order: SDNodeOrder);
1295 continue;
1296 }
1297 SmallVector<Value *> Values(It->Values.location_ops());
1298 if (!handleDebugValue(Values, Var, Expr: It->Expr, DbgLoc: It->DL, Order: SDNodeOrder,
1299 IsVariadic: It->Values.hasArgList())) {
1300 SmallVector<Value *, 4> Vals(It->Values.location_ops());
1301 addDanglingDebugInfo(Values&: Vals,
1302 Var: FnVarLocs->getDILocalVariable(ID: It->VariableID),
1303 Expr: It->Expr, IsVariadic: Vals.size() > 1, DL: It->DL, Order: SDNodeOrder);
1304 }
1305 }
1306 }
1307
1308 // We must skip DbgVariableRecords if they've already been processed above as
1309 // we have just emitted the debug values resulting from assignment tracking
1310 // analysis, making any existing DbgVariableRecords redundant (and probably
1311 // less correct). We still need to process DbgLabelRecords. This does sink
1312 // DbgLabelRecords to the bottom of the group of debug records. That sholdn't
1313 // be important as it does so deterministcally and ordering between
1314 // DbgLabelRecords and DbgVariableRecords is immaterial (other than for MIR/IR
1315 // printing).
1316 bool SkipDbgVariableRecords = DAG.getFunctionVarLocs();
1317 // Is there is any debug-info attached to this instruction, in the form of
1318 // DbgRecord non-instruction debug-info records.
1319 for (DbgRecord &DR : I.getDbgRecordRange()) {
1320 if (DbgLabelRecord *DLR = dyn_cast<DbgLabelRecord>(Val: &DR)) {
1321 assert(DLR->getLabel() && "Missing label");
1322 SDDbgLabel *SDV =
1323 DAG.getDbgLabel(Label: DLR->getLabel(), DL: DLR->getDebugLoc(), O: SDNodeOrder);
1324 DAG.AddDbgLabel(DB: SDV);
1325 continue;
1326 }
1327
1328 if (SkipDbgVariableRecords)
1329 continue;
1330 DbgVariableRecord &DVR = cast<DbgVariableRecord>(Val&: DR);
1331 DILocalVariable *Variable = DVR.getVariable();
1332 DIExpression *Expression = DVR.getExpression();
1333 dropDanglingDebugInfo(Variable, Expr: Expression);
1334
1335 if (DVR.getType() == DbgVariableRecord::LocationType::Declare) {
1336 if (FuncInfo.PreprocessedDVRDeclares.contains(Ptr: &DVR))
1337 continue;
1338 LLVM_DEBUG(dbgs() << "SelectionDAG visiting dbg_declare: " << DVR
1339 << "\n");
1340 handleDebugDeclare(Address: DVR.getVariableLocationOp(OpIdx: 0), Variable, Expression,
1341 DL: DVR.getDebugLoc());
1342 continue;
1343 }
1344
1345 // A DbgVariableRecord with no locations is a kill location.
1346 SmallVector<Value *, 4> Values(DVR.location_ops());
1347 if (Values.empty()) {
1348 handleKillDebugValue(Var: Variable, Expr: Expression, DbgLoc: DVR.getDebugLoc(),
1349 Order: SDNodeOrder);
1350 continue;
1351 }
1352
1353 // A DbgVariableRecord with an undef or absent location is also a kill
1354 // location.
1355 if (llvm::any_of(Range&: Values,
1356 P: [](Value *V) { return !V || isa<UndefValue>(Val: V); })) {
1357 handleKillDebugValue(Var: Variable, Expr: Expression, DbgLoc: DVR.getDebugLoc(),
1358 Order: SDNodeOrder);
1359 continue;
1360 }
1361
1362 bool IsVariadic = DVR.hasArgList();
1363 if (!handleDebugValue(Values, Var: Variable, Expr: Expression, DbgLoc: DVR.getDebugLoc(),
1364 Order: SDNodeOrder, IsVariadic)) {
1365 addDanglingDebugInfo(Values, Var: Variable, Expr: Expression, IsVariadic,
1366 DL: DVR.getDebugLoc(), Order: SDNodeOrder);
1367 }
1368 }
1369}
1370
1371void SelectionDAGBuilder::visit(const Instruction &I) {
1372 visitDbgInfo(I);
1373
1374 // Set up outgoing PHI node register values before emitting the terminator.
1375 if (I.isTerminator()) {
1376 HandlePHINodesInSuccessorBlocks(LLVMBB: I.getParent());
1377 }
1378
1379 ++SDNodeOrder;
1380 CurInst = &I;
1381
1382 // Set inserted listener only if required.
1383 bool NodeInserted = false;
1384 std::unique_ptr<SelectionDAG::DAGNodeInsertedListener> InsertedListener;
1385 MDNode *PCSectionsMD = I.getMetadata(KindID: LLVMContext::MD_pcsections);
1386 MDNode *MMRA = I.getMetadata(KindID: LLVMContext::MD_mmra);
1387 if (PCSectionsMD || MMRA) {
1388 InsertedListener = std::make_unique<SelectionDAG::DAGNodeInsertedListener>(
1389 args&: DAG, args: [&](SDNode *) { NodeInserted = true; });
1390 }
1391
1392 visit(Opcode: I.getOpcode(), I);
1393
1394 if (!I.isTerminator() && !HasTailCall &&
1395 !isa<GCStatepointInst>(Val: I)) // statepoints handle their exports internally
1396 CopyToExportRegsIfNeeded(V: &I);
1397
1398 // Handle metadata.
1399 if (PCSectionsMD || MMRA) {
1400 auto It = NodeMap.find(Val: &I);
1401 if (It != NodeMap.end()) {
1402 if (PCSectionsMD)
1403 DAG.addPCSections(Node: It->second.getNode(), MD: PCSectionsMD);
1404 if (MMRA)
1405 DAG.addMMRAMetadata(Node: It->second.getNode(), MMRA);
1406 } else if (NodeInserted) {
1407 // This should not happen; if it does, don't let it go unnoticed so we can
1408 // fix it. Relevant visit*() function is probably missing a setValue().
1409 errs() << "warning: loosing !pcsections and/or !mmra metadata ["
1410 << I.getModule()->getName() << "]\n";
1411 LLVM_DEBUG(I.dump());
1412 assert(false);
1413 }
1414 }
1415
1416 CurInst = nullptr;
1417}
1418
1419void SelectionDAGBuilder::visitPHI(const PHINode &) {
1420 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
1421}
1422
1423void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
1424 // Note: this doesn't use InstVisitor, because it has to work with
1425 // ConstantExpr's in addition to instructions.
1426 switch (Opcode) {
1427 default: llvm_unreachable("Unknown instruction type encountered!");
1428 // Build the switch statement using the Instruction.def file.
1429#define HANDLE_INST(NUM, OPCODE, CLASS) \
1430 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1431#include "llvm/IR/Instruction.def"
1432 }
1433}
1434
1435static bool handleDanglingVariadicDebugInfo(SelectionDAG &DAG,
1436 DILocalVariable *Variable,
1437 DebugLoc DL, unsigned Order,
1438 SmallVectorImpl<Value *> &Values,
1439 DIExpression *Expression) {
1440 // For variadic dbg_values we will now insert poison.
1441 // FIXME: We can potentially recover these!
1442 SmallVector<SDDbgOperand, 2> Locs;
1443 for (const Value *V : Values) {
1444 auto *Poison = PoisonValue::get(T: V->getType());
1445 Locs.push_back(Elt: SDDbgOperand::fromConst(Const: Poison));
1446 }
1447 SDDbgValue *SDV = DAG.getDbgValueList(Var: Variable, Expr: Expression, Locs, Dependencies: {},
1448 /*IsIndirect=*/false, DL, O: Order,
1449 /*IsVariadic=*/true);
1450 DAG.AddDbgValue(DB: SDV, /*isParameter=*/false);
1451 return true;
1452}
1453
1454void SelectionDAGBuilder::addDanglingDebugInfo(SmallVectorImpl<Value *> &Values,
1455 DILocalVariable *Var,
1456 DIExpression *Expr,
1457 bool IsVariadic, DebugLoc DL,
1458 unsigned Order) {
1459 if (IsVariadic) {
1460 handleDanglingVariadicDebugInfo(DAG, Variable: Var, DL, Order, Values, Expression: Expr);
1461 return;
1462 }
1463 // TODO: Dangling debug info will eventually either be resolved or produce
1464 // a poison DBG_VALUE. However in the resolution case, a gap may appear
1465 // between the original dbg.value location and its resolved DBG_VALUE,
1466 // which we should ideally fill with an extra poison DBG_VALUE.
1467 assert(Values.size() == 1);
1468 DanglingDebugInfoMap[Values[0]].emplace_back(args&: Var, args&: Expr, args&: DL, args&: Order);
1469}
1470
1471void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable,
1472 const DIExpression *Expr) {
1473 auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1474 DIVariable *DanglingVariable = DDI.getVariable();
1475 DIExpression *DanglingExpr = DDI.getExpression();
1476 if (DanglingVariable == Variable && Expr->fragmentsOverlap(Other: DanglingExpr)) {
1477 LLVM_DEBUG(dbgs() << "Dropping dangling debug info for "
1478 << printDDI(nullptr, DDI) << "\n");
1479 return true;
1480 }
1481 return false;
1482 };
1483
1484 for (auto &DDIMI : DanglingDebugInfoMap) {
1485 DanglingDebugInfoVector &DDIV = DDIMI.second;
1486
1487 // If debug info is to be dropped, run it through final checks to see
1488 // whether it can be salvaged.
1489 for (auto &DDI : DDIV)
1490 if (isMatchingDbgValue(DDI))
1491 salvageUnresolvedDbgValue(V: DDIMI.first, DDI);
1492
1493 erase_if(C&: DDIV, P: isMatchingDbgValue);
1494 }
1495}
1496
1497// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
1498// generate the debug data structures now that we've seen its definition.
1499void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
1500 SDValue Val) {
1501 auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(Key: V);
1502 if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1503 return;
1504
1505 DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1506 for (auto &DDI : DDIV) {
1507 DebugLoc DL = DDI.getDebugLoc();
1508 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1509 DILocalVariable *Variable = DDI.getVariable();
1510 DIExpression *Expr = DDI.getExpression();
1511 assert(Variable->isValidLocationForIntrinsic(DL) &&
1512 "Expected inlined-at fields to agree");
1513 SDDbgValue *SDV;
1514 if (Val.getNode()) {
1515 // FIXME: I doubt that it is correct to resolve a dangling DbgValue as a
1516 // FuncArgumentDbgValue (it would be hoisted to the function entry, and if
1517 // we couldn't resolve it directly when examining the DbgValue intrinsic
1518 // in the first place we should not be more successful here). Unless we
1519 // have some test case that prove this to be correct we should avoid
1520 // calling EmitFuncArgumentDbgValue here.
1521 unsigned ValSDNodeOrder = Val.getNode()->getIROrder();
1522 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, DL,
1523 Kind: FuncArgumentDbgValueKind::Value, N: Val)) {
1524 LLVM_DEBUG(dbgs() << "Resolve dangling debug info for "
1525 << printDDI(V, DDI) << "\n");
1526 LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump());
1527 // Increase the SDNodeOrder for the DbgValue here to make sure it is
1528 // inserted after the definition of Val when emitting the instructions
1529 // after ISel. An alternative could be to teach
1530 // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly.
1531 LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs()
1532 << "changing SDNodeOrder from " << DbgSDNodeOrder << " to "
1533 << ValSDNodeOrder << "\n");
1534 SDV = getDbgValue(N: Val, Variable, Expr, dl: DL,
1535 DbgSDNodeOrder: std::max(a: DbgSDNodeOrder, b: ValSDNodeOrder));
1536 DAG.AddDbgValue(DB: SDV, isParameter: false);
1537 } else
1538 LLVM_DEBUG(dbgs() << "Resolved dangling debug info for "
1539 << printDDI(V, DDI)
1540 << " in EmitFuncArgumentDbgValue\n");
1541 } else {
1542 LLVM_DEBUG(dbgs() << "Dropping debug info for " << printDDI(V, DDI)
1543 << "\n");
1544 auto Poison = PoisonValue::get(T: V->getType());
1545 auto SDV =
1546 DAG.getConstantDbgValue(Var: Variable, Expr, C: Poison, DL, O: DbgSDNodeOrder);
1547 DAG.AddDbgValue(DB: SDV, isParameter: false);
1548 }
1549 }
1550 DDIV.clear();
1551}
1552
1553void SelectionDAGBuilder::salvageUnresolvedDbgValue(const Value *V,
1554 DanglingDebugInfo &DDI) {
1555 // TODO: For the variadic implementation, instead of only checking the fail
1556 // state of `handleDebugValue`, we need know specifically which values were
1557 // invalid, so that we attempt to salvage only those values when processing
1558 // a DIArgList.
1559 const Value *OrigV = V;
1560 DILocalVariable *Var = DDI.getVariable();
1561 DIExpression *Expr = DDI.getExpression();
1562 DebugLoc DL = DDI.getDebugLoc();
1563 unsigned SDOrder = DDI.getSDNodeOrder();
1564
1565 // Currently we consider only dbg.value intrinsics -- we tell the salvager
1566 // that DW_OP_stack_value is desired.
1567 bool StackValue = true;
1568
1569 // Can this Value can be encoded without any further work?
1570 if (handleDebugValue(Values: V, Var, Expr, DbgLoc: DL, Order: SDOrder, /*IsVariadic=*/false))
1571 return;
1572
1573 // Attempt to salvage back through as many instructions as possible. Bail if
1574 // a non-instruction is seen, such as a constant expression or global
1575 // variable. FIXME: Further work could recover those too.
1576 while (isa<Instruction>(Val: V)) {
1577 const Instruction &VAsInst = *cast<const Instruction>(Val: V);
1578 // Temporary "0", awaiting real implementation.
1579 SmallVector<uint64_t, 16> Ops;
1580 SmallVector<Value *, 4> AdditionalValues;
1581 V = salvageDebugInfoImpl(I&: const_cast<Instruction &>(VAsInst),
1582 CurrentLocOps: Expr->getNumLocationOperands(), Ops,
1583 AdditionalValues);
1584 // If we cannot salvage any further, and haven't yet found a suitable debug
1585 // expression, bail out.
1586 if (!V)
1587 break;
1588
1589 // TODO: If AdditionalValues isn't empty, then the salvage can only be
1590 // represented with a DBG_VALUE_LIST, so we give up. When we have support
1591 // here for variadic dbg_values, remove that condition.
1592 if (!AdditionalValues.empty())
1593 break;
1594
1595 // New value and expr now represent this debuginfo.
1596 Expr = DIExpression::appendOpsToArg(Expr, Ops, ArgNo: 0, StackValue);
1597
1598 // Some kind of simplification occurred: check whether the operand of the
1599 // salvaged debug expression can be encoded in this DAG.
1600 if (handleDebugValue(Values: V, Var, Expr, DbgLoc: DL, Order: SDOrder, /*IsVariadic=*/false)) {
1601 LLVM_DEBUG(
1602 dbgs() << "Salvaged debug location info for:\n " << *Var << "\n"
1603 << *OrigV << "\nBy stripping back to:\n " << *V << "\n");
1604 return;
1605 }
1606 }
1607
1608 // This was the final opportunity to salvage this debug information, and it
1609 // couldn't be done. Place a poison DBG_VALUE at this location to terminate
1610 // any earlier variable location.
1611 assert(OrigV && "V shouldn't be null");
1612 auto *Poison = PoisonValue::get(T: OrigV->getType());
1613 auto *SDV = DAG.getConstantDbgValue(Var, Expr, C: Poison, DL, O: SDNodeOrder);
1614 DAG.AddDbgValue(DB: SDV, isParameter: false);
1615 LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n "
1616 << printDDI(OrigV, DDI) << "\n");
1617}
1618
1619void SelectionDAGBuilder::handleKillDebugValue(DILocalVariable *Var,
1620 DIExpression *Expr,
1621 DebugLoc DbgLoc,
1622 unsigned Order) {
1623 Value *Poison = PoisonValue::get(T: Type::getInt1Ty(C&: *Context));
1624 DIExpression *NewExpr =
1625 const_cast<DIExpression *>(DIExpression::convertToUndefExpression(Expr));
1626 handleDebugValue(Values: Poison, Var, Expr: NewExpr, DbgLoc, Order,
1627 /*IsVariadic*/ false);
1628}
1629
1630bool SelectionDAGBuilder::handleDebugValue(ArrayRef<const Value *> Values,
1631 DILocalVariable *Var,
1632 DIExpression *Expr, DebugLoc DbgLoc,
1633 unsigned Order, bool IsVariadic) {
1634 if (Values.empty())
1635 return true;
1636
1637 // Filter EntryValue locations out early.
1638 if (visitEntryValueDbgValue(Values, Variable: Var, Expr, DbgLoc))
1639 return true;
1640
1641 SmallVector<SDDbgOperand> LocationOps;
1642 SmallVector<SDNode *> Dependencies;
1643 for (const Value *V : Values) {
1644 // Constant value.
1645 if (isa<ConstantInt>(Val: V) || isa<ConstantFP>(Val: V) || isa<UndefValue>(Val: V) ||
1646 isa<ConstantPointerNull>(Val: V)) {
1647 LocationOps.emplace_back(Args: SDDbgOperand::fromConst(Const: V));
1648 continue;
1649 }
1650
1651 // Look through IntToPtr constants.
1652 if (auto *CE = dyn_cast<ConstantExpr>(Val: V))
1653 if (CE->getOpcode() == Instruction::IntToPtr) {
1654 LocationOps.emplace_back(Args: SDDbgOperand::fromConst(Const: CE->getOperand(i_nocapture: 0)));
1655 continue;
1656 }
1657
1658 // If the Value is a frame index, we can create a FrameIndex debug value
1659 // without relying on the DAG at all.
1660 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Val: V)) {
1661 auto SI = FuncInfo.StaticAllocaMap.find(Val: AI);
1662 if (SI != FuncInfo.StaticAllocaMap.end()) {
1663 LocationOps.emplace_back(Args: SDDbgOperand::fromFrameIdx(FrameIdx: SI->second));
1664 continue;
1665 }
1666 }
1667
1668 // Do not use getValue() in here; we don't want to generate code at
1669 // this point if it hasn't been done yet.
1670 SDValue N = NodeMap[V];
1671 if (!N.getNode() && isa<Argument>(Val: V)) // Check unused arguments map.
1672 N = UnusedArgNodeMap[V];
1673
1674 if (N.getNode()) {
1675 // Only emit func arg dbg value for non-variadic dbg.values for now.
1676 if (!IsVariadic &&
1677 EmitFuncArgumentDbgValue(V, Variable: Var, Expr, DL: DbgLoc,
1678 Kind: FuncArgumentDbgValueKind::Value, N))
1679 return true;
1680 if (auto *FISDN = dyn_cast<FrameIndexSDNode>(Val: N.getNode())) {
1681 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can
1682 // describe stack slot locations.
1683 //
1684 // Consider "int x = 0; int *px = &x;". There are two kinds of
1685 // interesting debug values here after optimization:
1686 //
1687 // dbg.value(i32* %px, !"int *px", !DIExpression()), and
1688 // dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref))
1689 //
1690 // Both describe the direct values of their associated variables.
1691 Dependencies.push_back(Elt: N.getNode());
1692 LocationOps.emplace_back(Args: SDDbgOperand::fromFrameIdx(FrameIdx: FISDN->getIndex()));
1693 continue;
1694 }
1695 LocationOps.emplace_back(
1696 Args: SDDbgOperand::fromNode(Node: N.getNode(), ResNo: N.getResNo()));
1697 continue;
1698 }
1699
1700 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1701 // Special rules apply for the first dbg.values of parameter variables in a
1702 // function. Identify them by the fact they reference Argument Values, that
1703 // they're parameters, and they are parameters of the current function. We
1704 // need to let them dangle until they get an SDNode.
1705 bool IsParamOfFunc =
1706 isa<Argument>(Val: V) && Var->isParameter() && !DbgLoc.getInlinedAt();
1707 if (IsParamOfFunc)
1708 return false;
1709
1710 // The value is not used in this block yet (or it would have an SDNode).
1711 // We still want the value to appear for the user if possible -- if it has
1712 // an associated VReg, we can refer to that instead.
1713 auto VMI = FuncInfo.ValueMap.find(Val: V);
1714 if (VMI != FuncInfo.ValueMap.end()) {
1715 Register Reg = VMI->second;
1716 // If this is a PHI node, it may be split up into several MI PHI nodes
1717 // (in FunctionLoweringInfo::set).
1718 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
1719 V->getType(), std::nullopt);
1720 if (RFV.occupiesMultipleRegs()) {
1721 // FIXME: We could potentially support variadic dbg_values here.
1722 if (IsVariadic)
1723 return false;
1724 unsigned Offset = 0;
1725 unsigned BitsToDescribe = 0;
1726 if (auto VarSize = Var->getSizeInBits())
1727 BitsToDescribe = *VarSize;
1728 if (auto Fragment = Expr->getFragmentInfo())
1729 BitsToDescribe = Fragment->SizeInBits;
1730 for (const auto &RegAndSize : RFV.getRegsAndSizes()) {
1731 // Bail out if all bits are described already.
1732 if (Offset >= BitsToDescribe)
1733 break;
1734 // TODO: handle scalable vectors.
1735 unsigned RegisterSize = RegAndSize.second;
1736 unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
1737 ? BitsToDescribe - Offset
1738 : RegisterSize;
1739 auto FragmentExpr = DIExpression::createFragmentExpression(
1740 Expr, OffsetInBits: Offset, SizeInBits: FragmentSize);
1741 if (!FragmentExpr)
1742 continue;
1743 SDDbgValue *SDV = DAG.getVRegDbgValue(
1744 Var, Expr: *FragmentExpr, VReg: RegAndSize.first, IsIndirect: false, DL: DbgLoc, O: Order);
1745 DAG.AddDbgValue(DB: SDV, isParameter: false);
1746 Offset += RegisterSize;
1747 }
1748 return true;
1749 }
1750 // We can use simple vreg locations for variadic dbg_values as well.
1751 LocationOps.emplace_back(Args: SDDbgOperand::fromVReg(VReg: Reg));
1752 continue;
1753 }
1754 // We failed to create a SDDbgOperand for V.
1755 return false;
1756 }
1757
1758 // We have created a SDDbgOperand for each Value in Values.
1759 assert(!LocationOps.empty());
1760 SDDbgValue *SDV =
1761 DAG.getDbgValueList(Var, Expr, Locs: LocationOps, Dependencies,
1762 /*IsIndirect=*/false, DL: DbgLoc, O: Order, IsVariadic);
1763 DAG.AddDbgValue(DB: SDV, /*isParameter=*/false);
1764 return true;
1765}
1766
1767void SelectionDAGBuilder::resolveOrClearDbgInfo() {
1768 // Try to fixup any remaining dangling debug info -- and drop it if we can't.
1769 for (auto &Pair : DanglingDebugInfoMap)
1770 for (auto &DDI : Pair.second)
1771 salvageUnresolvedDbgValue(V: const_cast<Value *>(Pair.first), DDI);
1772 clearDanglingDebugInfo();
1773}
1774
1775/// getCopyFromRegs - If there was virtual register allocated for the value V
1776/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1777SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1778 DenseMap<const Value *, Register>::iterator It = FuncInfo.ValueMap.find(Val: V);
1779 SDValue Result;
1780
1781 if (It != FuncInfo.ValueMap.end()) {
1782 Register InReg = It->second;
1783
1784 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1785 DAG.getDataLayout(), InReg, Ty,
1786 std::nullopt); // This is not an ABI copy.
1787 SDValue Chain = DAG.getEntryNode();
1788 Result = RFV.getCopyFromRegs(DAG, FuncInfo, dl: getCurSDLoc(), Chain, Glue: nullptr,
1789 V);
1790 resolveDanglingDebugInfo(V, Val: Result);
1791 }
1792
1793 return Result;
1794}
1795
1796/// getValue - Return an SDValue for the given Value.
1797SDValue SelectionDAGBuilder::getValue(const Value *V) {
1798 // If we already have an SDValue for this value, use it. It's important
1799 // to do this first, so that we don't create a CopyFromReg if we already
1800 // have a regular SDValue.
1801 SDValue &N = NodeMap[V];
1802 if (N.getNode()) return N;
1803
1804 // If there's a virtual register allocated and initialized for this
1805 // value, use it.
1806 if (SDValue copyFromReg = getCopyFromRegs(V, Ty: V->getType()))
1807 return copyFromReg;
1808
1809 // Otherwise create a new SDValue and remember it.
1810 SDValue Val = getValueImpl(V);
1811 NodeMap[V] = Val;
1812 resolveDanglingDebugInfo(V, Val);
1813 return Val;
1814}
1815
1816/// getNonRegisterValue - Return an SDValue for the given Value, but
1817/// don't look in FuncInfo.ValueMap for a virtual register.
1818SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1819 // If we already have an SDValue for this value, use it.
1820 SDValue &N = NodeMap[V];
1821 if (N.getNode()) {
1822 if (isIntOrFPConstant(V: N)) {
1823 // Remove the debug location from the node as the node is about to be used
1824 // in a location which may differ from the original debug location. This
1825 // is relevant to Constant and ConstantFP nodes because they can appear
1826 // as constant expressions inside PHI nodes.
1827 N->setDebugLoc(DebugLoc());
1828 }
1829 return N;
1830 }
1831
1832 // Otherwise create a new SDValue and remember it.
1833 SDValue Val = getValueImpl(V);
1834 NodeMap[V] = Val;
1835 resolveDanglingDebugInfo(V, Val);
1836 return Val;
1837}
1838
1839/// getValueImpl - Helper function for getValue and getNonRegisterValue.
1840/// Create an SDValue for the given value.
1841SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1842 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1843
1844 if (const Constant *C = dyn_cast<Constant>(Val: V)) {
1845 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: V->getType(), AllowUnknown: true);
1846
1847 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: C)) {
1848 SDLoc DL = getCurSDLoc();
1849
1850 // DAG.getConstant() may attempt to legalise the vector constant which can
1851 // significantly change the combines applied to the DAG. To reduce the
1852 // divergence when enabling ConstantInt based vectors we try to construct
1853 // the DAG in the same way as shufflevector based splats. TODO: The
1854 // divergence sometimes leads to better optimisations. Ideally we should
1855 // prevent DAG.getConstant() from legalising too early but there are some
1856 // degradations preventing this.
1857 if (VT.isScalableVector())
1858 return DAG.getNode(
1859 Opcode: ISD::SPLAT_VECTOR, DL, VT,
1860 Operand: DAG.getConstant(Val: CI->getValue(), DL, VT: VT.getVectorElementType()));
1861 if (VT.isFixedLengthVector())
1862 return DAG.getSplatBuildVector(
1863 VT, DL,
1864 Op: DAG.getConstant(Val: CI->getValue(), DL, VT: VT.getVectorElementType()));
1865 return DAG.getConstant(Val: *CI, DL, VT);
1866 }
1867
1868 if (const ConstantByte *CB = dyn_cast<ConstantByte>(Val: C))
1869 return DAG.getConstant(Val: CB->getValue(), DL: getCurSDLoc(), VT);
1870
1871 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: C))
1872 return DAG.getGlobalAddress(GV, DL: getCurSDLoc(), VT);
1873
1874 if (const ConstantPtrAuth *CPA = dyn_cast<ConstantPtrAuth>(Val: C)) {
1875 return DAG.getNode(Opcode: ISD::PtrAuthGlobalAddress, DL: getCurSDLoc(), VT,
1876 N1: getValue(V: CPA->getPointer()), N2: getValue(V: CPA->getKey()),
1877 N3: getValue(V: CPA->getAddrDiscriminator()),
1878 N4: getValue(V: CPA->getDiscriminator()));
1879 }
1880
1881 if (isa<ConstantPointerNull>(Val: C))
1882 return DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT);
1883
1884 if (match(V: C, P: m_VScale()))
1885 return DAG.getVScale(DL: getCurSDLoc(), VT, MulImm: APInt(VT.getSizeInBits(), 1));
1886
1887 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Val: C))
1888 return DAG.getConstantFP(V: *CFP, DL: getCurSDLoc(), VT);
1889
1890 if (isa<UndefValue>(Val: C) && !V->getType()->isAggregateType())
1891 return isa<PoisonValue>(Val: C) ? DAG.getPOISON(VT) : DAG.getUNDEF(VT);
1892
1893 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(Val: C)) {
1894 visit(Opcode: CE->getOpcode(), I: *CE);
1895 SDValue N1 = NodeMap[V];
1896 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1897 return N1;
1898 }
1899
1900 if (isa<ConstantStruct>(Val: C) || isa<ConstantArray>(Val: C)) {
1901 SmallVector<SDValue, 4> Constants;
1902 for (const Use &U : C->operands()) {
1903 SDNode *Val = getValue(V: U).getNode();
1904 // If the operand is an empty aggregate, there are no values.
1905 if (!Val) continue;
1906 // Add each leaf value from the operand to the Constants list
1907 // to form a flattened list of all the values.
1908 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1909 Constants.push_back(Elt: SDValue(Val, i));
1910 }
1911
1912 return DAG.getMergeValues(Ops: Constants, dl: getCurSDLoc());
1913 }
1914
1915 if (const ConstantDataSequential *CDS =
1916 dyn_cast<ConstantDataSequential>(Val: C)) {
1917 SmallVector<SDValue, 4> Ops;
1918 for (uint64_t i = 0, e = CDS->getNumElements(); i != e; ++i) {
1919 SDNode *Val = getValue(V: CDS->getElementAsConstant(i)).getNode();
1920 // Add each leaf value from the operand to the Constants list
1921 // to form a flattened list of all the values.
1922 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1923 Ops.push_back(Elt: SDValue(Val, i));
1924 }
1925
1926 if (isa<ArrayType>(Val: CDS->getType()))
1927 return DAG.getMergeValues(Ops, dl: getCurSDLoc());
1928 return DAG.getBuildVector(VT, DL: getCurSDLoc(), Ops);
1929 }
1930
1931 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1932 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1933 "Unknown struct or array constant!");
1934
1935 SmallVector<EVT, 4> ValueVTs;
1936 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: C->getType(), ValueVTs);
1937 unsigned NumElts = ValueVTs.size();
1938 if (NumElts == 0)
1939 return SDValue(); // empty struct
1940 SmallVector<SDValue, 4> Constants(NumElts);
1941 for (unsigned i = 0; i != NumElts; ++i) {
1942 EVT EltVT = ValueVTs[i];
1943 if (isa<UndefValue>(Val: C))
1944 Constants[i] = DAG.getUNDEF(VT: EltVT);
1945 else if (EltVT.isFloatingPoint())
1946 Constants[i] = DAG.getConstantFP(Val: 0, DL: getCurSDLoc(), VT: EltVT);
1947 else
1948 Constants[i] = DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: EltVT);
1949 }
1950
1951 return DAG.getMergeValues(Ops: Constants, dl: getCurSDLoc());
1952 }
1953
1954 if (const BlockAddress *BA = dyn_cast<BlockAddress>(Val: C))
1955 return DAG.getBlockAddress(BA, VT);
1956
1957 if (const auto *Equiv = dyn_cast<DSOLocalEquivalent>(Val: C))
1958 return getValue(V: Equiv->getGlobalValue());
1959
1960 if (const auto *NC = dyn_cast<NoCFIValue>(Val: C))
1961 return getValue(V: NC->getGlobalValue());
1962
1963 if (VT == MVT::aarch64svcount) {
1964 assert(C->isNullValue() && "Can only zero this target type!");
1965 return DAG.getNode(Opcode: ISD::BITCAST, DL: getCurSDLoc(), VT,
1966 Operand: DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: MVT::nxv16i1));
1967 }
1968
1969 if (VT.isRISCVVectorTuple()) {
1970 assert(C->isNullValue() && "Can only zero this target type!");
1971 return DAG.getNode(
1972 Opcode: ISD::BITCAST, DL: getCurSDLoc(), VT,
1973 Operand: DAG.getNode(
1974 Opcode: ISD::SPLAT_VECTOR, DL: getCurSDLoc(),
1975 VT: EVT::getVectorVT(Context&: *DAG.getContext(), VT: MVT::i8,
1976 NumElements: VT.getSizeInBits().getKnownMinValue() / 8, IsScalable: true),
1977 Operand: DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: MVT::getIntegerVT(BitWidth: 8))));
1978 }
1979
1980 VectorType *VecTy = cast<VectorType>(Val: V->getType());
1981
1982 // Now that we know the number and type of the elements, get that number of
1983 // elements into the Ops array based on what kind of constant it is.
1984 if (const ConstantVector *CV = dyn_cast<ConstantVector>(Val: C)) {
1985 SmallVector<SDValue, 16> Ops;
1986 unsigned NumElements = cast<FixedVectorType>(Val: VecTy)->getNumElements();
1987 for (unsigned i = 0; i != NumElements; ++i)
1988 Ops.push_back(Elt: getValue(V: CV->getOperand(i_nocapture: i)));
1989
1990 return DAG.getBuildVector(VT, DL: getCurSDLoc(), Ops);
1991 }
1992
1993 if (isa<ConstantAggregateZero>(Val: C)) {
1994 EVT EltVT =
1995 TLI.getValueType(DL: DAG.getDataLayout(), Ty: VecTy->getElementType());
1996
1997 SDValue Op;
1998 if (EltVT.isFloatingPoint())
1999 Op = DAG.getConstantFP(Val: 0, DL: getCurSDLoc(), VT: EltVT);
2000 else
2001 Op = DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: EltVT);
2002
2003 return DAG.getSplat(VT, DL: getCurSDLoc(), Op);
2004 }
2005
2006 llvm_unreachable("Unknown vector constant");
2007 }
2008
2009 // If this is a static alloca, generate it as the frameindex instead of
2010 // computation.
2011 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Val: V)) {
2012 DenseMap<const AllocaInst*, int>::iterator SI =
2013 FuncInfo.StaticAllocaMap.find(Val: AI);
2014 if (SI != FuncInfo.StaticAllocaMap.end())
2015 return DAG.getFrameIndex(
2016 FI: SI->second, VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: AI->getType()));
2017 }
2018
2019 // If this is an instruction which fast-isel has deferred, select it now.
2020 if (const Instruction *Inst = dyn_cast<Instruction>(Val: V)) {
2021 Register InReg = FuncInfo.InitializeRegForValue(V: Inst);
2022 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
2023 Inst->getType(), std::nullopt);
2024 SDValue Chain = DAG.getEntryNode();
2025 return RFV.getCopyFromRegs(DAG, FuncInfo, dl: getCurSDLoc(), Chain, Glue: nullptr, V);
2026 }
2027
2028 if (const MetadataAsValue *MD = dyn_cast<MetadataAsValue>(Val: V))
2029 return DAG.getMDNode(MD: cast<MDNode>(Val: MD->getMetadata()));
2030
2031 if (const auto *BB = dyn_cast<BasicBlock>(Val: V))
2032 return DAG.getBasicBlock(MBB: FuncInfo.getMBB(BB));
2033
2034 llvm_unreachable("Can't get register for value!");
2035}
2036
2037void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
2038 auto Pers = classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
2039 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
2040 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
2041 bool IsSEH = isAsynchronousEHPersonality(Pers);
2042 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
2043 if (IsSEH) {
2044 // For SEH, EHCont Guard needs to know that this catchpad is a target.
2045 CatchPadMBB->setIsEHContTarget(true);
2046 DAG.getMachineFunction().setHasEHContTarget(true);
2047 } else
2048 CatchPadMBB->setIsEHScopeEntry();
2049 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
2050 if (IsMSVCCXX || IsCoreCLR)
2051 CatchPadMBB->setIsEHFuncletEntry();
2052}
2053
2054void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
2055 // Update machine-CFG edge.
2056 MachineBasicBlock *TargetMBB = FuncInfo.getMBB(BB: I.getSuccessor());
2057 FuncInfo.MBB->addSuccessor(Succ: TargetMBB);
2058
2059 auto Pers = classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
2060 bool IsSEH = isAsynchronousEHPersonality(Pers);
2061 if (IsSEH) {
2062 // If this is not a fall-through branch or optimizations are switched off,
2063 // emit the branch.
2064 if (TargetMBB != NextBlock(MBB: FuncInfo.MBB) ||
2065 TM.getOptLevel() == CodeGenOptLevel::None)
2066 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(), VT: MVT::Other,
2067 N1: getControlRoot(), N2: DAG.getBasicBlock(MBB: TargetMBB)));
2068 return;
2069 }
2070
2071 // For non-SEH, EHCont Guard needs to know that this catchret is a target.
2072 TargetMBB->setIsEHContTarget(true);
2073 DAG.getMachineFunction().setHasEHContTarget(true);
2074
2075 // Figure out the funclet membership for the catchret's successor.
2076 // This will be used by the FuncletLayout pass to determine how to order the
2077 // BB's.
2078 // A 'catchret' returns to the outer scope's color.
2079 Value *ParentPad = I.getCatchSwitchParentPad();
2080 const BasicBlock *SuccessorColor;
2081 if (isa<ConstantTokenNone>(Val: ParentPad))
2082 SuccessorColor = &FuncInfo.Fn->getEntryBlock();
2083 else
2084 SuccessorColor = cast<Instruction>(Val: ParentPad)->getParent();
2085 assert(SuccessorColor && "No parent funclet for catchret!");
2086 MachineBasicBlock *SuccessorColorMBB = FuncInfo.getMBB(BB: SuccessorColor);
2087 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
2088
2089 // Create the terminator node.
2090 SDValue Ret = DAG.getNode(Opcode: ISD::CATCHRET, DL: getCurSDLoc(), VT: MVT::Other,
2091 N1: getControlRoot(), N2: DAG.getBasicBlock(MBB: TargetMBB),
2092 N3: DAG.getBasicBlock(MBB: SuccessorColorMBB));
2093 DAG.setRoot(Ret);
2094}
2095
2096void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
2097 // Don't emit any special code for the cleanuppad instruction. It just marks
2098 // the start of an EH scope/funclet.
2099 FuncInfo.MBB->setIsEHScopeEntry();
2100 auto Pers = classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
2101 if (Pers != EHPersonality::Wasm_CXX) {
2102 FuncInfo.MBB->setIsEHFuncletEntry();
2103 FuncInfo.MBB->setIsCleanupFuncletEntry();
2104 }
2105}
2106
2107/// When an invoke or a cleanupret unwinds to the next EH pad, there are
2108/// many places it could ultimately go. In the IR, we have a single unwind
2109/// destination, but in the machine CFG, we enumerate all the possible blocks.
2110/// This function skips over imaginary basic blocks that hold catchswitch
2111/// instructions, and finds all the "real" machine
2112/// basic block destinations. As those destinations may not be successors of
2113/// EHPadBB, here we also calculate the edge probability to those destinations.
2114/// The passed-in Prob is the edge probability to EHPadBB.
2115static void findUnwindDestinations(
2116 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
2117 BranchProbability Prob,
2118 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
2119 &UnwindDests) {
2120 EHPersonality Personality =
2121 classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
2122 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
2123 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
2124 bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
2125 bool IsSEH = isAsynchronousEHPersonality(Pers: Personality);
2126
2127 while (EHPadBB) {
2128 BasicBlock::const_iterator Pad = EHPadBB->getFirstNonPHIIt();
2129 BasicBlock *NewEHPadBB = nullptr;
2130 if (isa<LandingPadInst>(Val: Pad)) {
2131 // Stop on landingpads. They are not funclets.
2132 UnwindDests.emplace_back(Args: FuncInfo.getMBB(BB: EHPadBB), Args&: Prob);
2133 break;
2134 } else if (isa<CleanupPadInst>(Val: Pad)) {
2135 // Stop on cleanup pads. Cleanups are always funclet entries for all known
2136 // personalities except Wasm. And in Wasm this becomes a catch_all(_ref),
2137 // which always catches an exception.
2138 UnwindDests.emplace_back(Args: FuncInfo.getMBB(BB: EHPadBB), Args&: Prob);
2139 UnwindDests.back().first->setIsEHScopeEntry();
2140 // In Wasm, EH scopes are not funclets
2141 if (!IsWasmCXX)
2142 UnwindDests.back().first->setIsEHFuncletEntry();
2143 break;
2144 } else if (const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Val&: Pad)) {
2145 // Add the catchpad handlers to the possible destinations.
2146 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2147 UnwindDests.emplace_back(Args: FuncInfo.getMBB(BB: CatchPadBB), Args&: Prob);
2148 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
2149 if (IsMSVCCXX || IsCoreCLR)
2150 UnwindDests.back().first->setIsEHFuncletEntry();
2151 if (!IsSEH)
2152 UnwindDests.back().first->setIsEHScopeEntry();
2153 }
2154 NewEHPadBB = CatchSwitch->getUnwindDest();
2155 } else {
2156 continue;
2157 }
2158
2159 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2160 if (BPI && NewEHPadBB)
2161 Prob *= BPI->getEdgeProbability(Src: EHPadBB, Dst: NewEHPadBB);
2162 EHPadBB = NewEHPadBB;
2163 }
2164}
2165
2166void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
2167 // Update successor info.
2168 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2169 auto UnwindDest = I.getUnwindDest();
2170 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2171 BranchProbability UnwindDestProb =
2172 (BPI && UnwindDest)
2173 ? BPI->getEdgeProbability(Src: FuncInfo.MBB->getBasicBlock(), Dst: UnwindDest)
2174 : BranchProbability::getZero();
2175 findUnwindDestinations(FuncInfo, EHPadBB: UnwindDest, Prob: UnwindDestProb, UnwindDests);
2176 for (auto &UnwindDest : UnwindDests) {
2177 UnwindDest.first->setIsEHPad();
2178 addSuccessorWithProb(Src: FuncInfo.MBB, Dst: UnwindDest.first, Prob: UnwindDest.second);
2179 }
2180 FuncInfo.MBB->normalizeSuccProbs();
2181
2182 // Create the terminator node.
2183 MachineBasicBlock *CleanupPadMBB =
2184 FuncInfo.getMBB(BB: I.getCleanupPad()->getParent());
2185 SDValue Ret = DAG.getNode(Opcode: ISD::CLEANUPRET, DL: getCurSDLoc(), VT: MVT::Other,
2186 N1: getControlRoot(), N2: DAG.getBasicBlock(MBB: CleanupPadMBB));
2187 DAG.setRoot(Ret);
2188}
2189
2190void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
2191 report_fatal_error(reason: "visitCatchSwitch not yet implemented!");
2192}
2193
2194void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
2195 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2196 auto &DL = DAG.getDataLayout();
2197 SDValue Chain = getControlRoot();
2198 SmallVector<ISD::OutputArg, 8> Outs;
2199 SmallVector<SDValue, 8> OutVals;
2200
2201 // Calls to @llvm.experimental.deoptimize don't generate a return value, so
2202 // lower
2203 //
2204 // %val = call <ty> @llvm.experimental.deoptimize()
2205 // ret <ty> %val
2206 //
2207 // differently.
2208 if (I.getParent()->getTerminatingDeoptimizeCall()) {
2209 LowerDeoptimizingReturn();
2210 return;
2211 }
2212
2213 if (!FuncInfo.CanLowerReturn) {
2214 Register DemoteReg = FuncInfo.DemoteRegister;
2215
2216 // Emit a store of the return value through the virtual register.
2217 // Leave Outs empty so that LowerReturn won't try to load return
2218 // registers the usual way.
2219 MVT PtrValueVT = TLI.getPointerTy(DL, AS: DL.getAllocaAddrSpace());
2220 SDValue RetPtr =
2221 DAG.getCopyFromReg(Chain, dl: getCurSDLoc(), Reg: DemoteReg, VT: PtrValueVT);
2222 SDValue RetOp = getValue(V: I.getOperand(i_nocapture: 0));
2223
2224 SmallVector<EVT, 4> ValueVTs, MemVTs;
2225 SmallVector<uint64_t, 4> Offsets;
2226 ComputeValueVTs(TLI, DL, Ty: I.getOperand(i_nocapture: 0)->getType(), ValueVTs, MemVTs: &MemVTs,
2227 FixedOffsets: &Offsets, StartingOffset: 0);
2228 unsigned NumValues = ValueVTs.size();
2229
2230 SmallVector<SDValue, 4> Chains(NumValues);
2231 Align BaseAlign = DL.getPrefTypeAlign(Ty: I.getOperand(i_nocapture: 0)->getType());
2232 for (unsigned i = 0; i != NumValues; ++i) {
2233 // An aggregate return value cannot wrap around the address space, so
2234 // offsets to its parts don't wrap either.
2235 SDValue Ptr = DAG.getObjectPtrOffset(SL: getCurSDLoc(), Ptr: RetPtr,
2236 Offset: TypeSize::getFixed(ExactSize: Offsets[i]));
2237
2238 SDValue Val = RetOp.getValue(R: RetOp.getResNo() + i);
2239 if (MemVTs[i] != ValueVTs[i])
2240 Val = DAG.getPtrExtOrTrunc(Op: Val, DL: getCurSDLoc(), VT: MemVTs[i]);
2241 Chains[i] = DAG.getStore(
2242 Chain, dl: getCurSDLoc(), Val,
2243 // FIXME: better loc info would be nice.
2244 Ptr, PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
2245 Alignment: commonAlignment(A: BaseAlign, Offset: Offsets[i]));
2246 }
2247
2248 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: getCurSDLoc(),
2249 VT: MVT::Other, Ops: Chains);
2250 } else if (I.getNumOperands() != 0) {
2251 SmallVector<Type *, 4> Types;
2252 ComputeValueTypes(DL, Ty: I.getOperand(i_nocapture: 0)->getType(), Types);
2253 unsigned NumValues = Types.size();
2254 if (NumValues) {
2255 SDValue RetOp = getValue(V: I.getOperand(i_nocapture: 0));
2256
2257 const Function *F = I.getParent()->getParent();
2258
2259 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
2260 Ty: I.getOperand(i_nocapture: 0)->getType(), CallConv: F->getCallingConv(),
2261 /*IsVarArg*/ isVarArg: false, DL);
2262
2263 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
2264 if (F->getAttributes().hasRetAttr(Kind: Attribute::SExt))
2265 ExtendKind = ISD::SIGN_EXTEND;
2266 else if (F->getAttributes().hasRetAttr(Kind: Attribute::ZExt))
2267 ExtendKind = ISD::ZERO_EXTEND;
2268
2269 LLVMContext &Context = F->getContext();
2270 bool RetInReg = F->getAttributes().hasRetAttr(Kind: Attribute::InReg);
2271
2272 for (unsigned j = 0; j != NumValues; ++j) {
2273 EVT VT = TLI.getValueType(DL, Ty: Types[j]);
2274
2275 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
2276 VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
2277
2278 CallingConv::ID CC = F->getCallingConv();
2279
2280 unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT);
2281 MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT);
2282 SmallVector<SDValue, 4> Parts(NumParts);
2283 getCopyToParts(DAG, DL: getCurSDLoc(),
2284 Val: SDValue(RetOp.getNode(), RetOp.getResNo() + j),
2285 Parts: &Parts[0], NumParts, PartVT, V: &I, CallConv: CC, ExtendKind);
2286
2287 // 'inreg' on function refers to return value
2288 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
2289 if (RetInReg)
2290 Flags.setInReg();
2291
2292 if (I.getOperand(i_nocapture: 0)->getType()->isPointerTy()) {
2293 Flags.setPointer();
2294 Flags.setPointerAddrSpace(
2295 cast<PointerType>(Val: I.getOperand(i_nocapture: 0)->getType())->getAddressSpace());
2296 }
2297
2298 if (NeedsRegBlock) {
2299 Flags.setInConsecutiveRegs();
2300 if (j == NumValues - 1)
2301 Flags.setInConsecutiveRegsLast();
2302 }
2303
2304 // Propagate extension type if any
2305 if (ExtendKind == ISD::SIGN_EXTEND)
2306 Flags.setSExt();
2307 else if (ExtendKind == ISD::ZERO_EXTEND)
2308 Flags.setZExt();
2309 else if (F->getAttributes().hasRetAttr(Kind: Attribute::NoExt))
2310 Flags.setNoExt();
2311
2312 for (unsigned i = 0; i < NumParts; ++i) {
2313 Outs.push_back(Elt: ISD::OutputArg(Flags,
2314 Parts[i].getValueType().getSimpleVT(),
2315 VT, Types[j], 0, 0));
2316 OutVals.push_back(Elt: Parts[i]);
2317 }
2318 }
2319 }
2320 }
2321
2322 // Push in swifterror virtual register as the last element of Outs. This makes
2323 // sure swifterror virtual register will be returned in the swifterror
2324 // physical register.
2325 const Function *F = I.getParent()->getParent();
2326 if (TLI.supportSwiftError() &&
2327 F->getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError)) {
2328 assert(SwiftError.getFunctionArg() && "Need a swift error argument");
2329 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
2330 Flags.setSwiftError();
2331 Outs.push_back(Elt: ISD::OutputArg(Flags, /*vt=*/TLI.getPointerTy(DL),
2332 /*argvt=*/EVT(TLI.getPointerTy(DL)),
2333 PointerType::getUnqual(C&: *DAG.getContext()),
2334 /*origidx=*/1, /*partOffs=*/0));
2335 // Create SDNode for the swifterror virtual register.
2336 OutVals.push_back(
2337 Elt: DAG.getRegister(Reg: SwiftError.getOrCreateVRegUseAt(
2338 &I, FuncInfo.MBB, SwiftError.getFunctionArg()),
2339 VT: EVT(TLI.getPointerTy(DL))));
2340 }
2341
2342 bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg();
2343 CallingConv::ID CallConv =
2344 DAG.getMachineFunction().getFunction().getCallingConv();
2345 Chain = DAG.getTargetLoweringInfo().LowerReturn(
2346 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
2347
2348 // Verify that the target's LowerReturn behaved as expected.
2349 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
2350 "LowerReturn didn't return a valid chain!");
2351
2352 // Update the DAG with the new chain value resulting from return lowering.
2353 DAG.setRoot(Chain);
2354}
2355
2356/// CopyToExportRegsIfNeeded - If the given value has virtual registers
2357/// created for it, emit nodes to copy the value into the virtual
2358/// registers.
2359void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
2360 // Skip empty types
2361 if (V->getType()->isEmptyTy())
2362 return;
2363
2364 DenseMap<const Value *, Register>::iterator VMI = FuncInfo.ValueMap.find(Val: V);
2365 if (VMI != FuncInfo.ValueMap.end()) {
2366 assert((!V->use_empty() || isa<CallBrInst>(V)) &&
2367 "Unused value assigned virtual registers!");
2368 CopyValueToVirtualRegister(V, Reg: VMI->second);
2369 }
2370}
2371
2372/// ExportFromCurrentBlock - If this condition isn't known to be exported from
2373/// the current basic block, add it to ValueMap now so that we'll get a
2374/// CopyTo/FromReg.
2375void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
2376 // No need to export constants.
2377 if (!isa<Instruction>(Val: V) && !isa<Argument>(Val: V)) return;
2378
2379 // Already exported?
2380 if (FuncInfo.isExportedInst(V)) return;
2381
2382 Register Reg = FuncInfo.InitializeRegForValue(V);
2383 CopyValueToVirtualRegister(V, Reg);
2384}
2385
2386bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
2387 const BasicBlock *FromBB) {
2388 // The operands of the setcc have to be in this block. We don't know
2389 // how to export them from some other block.
2390 if (const Instruction *VI = dyn_cast<Instruction>(Val: V)) {
2391 // Can export from current BB.
2392 if (VI->getParent() == FromBB)
2393 return true;
2394
2395 // Is already exported, noop.
2396 return FuncInfo.isExportedInst(V);
2397 }
2398
2399 // If this is an argument, we can export it if the BB is the entry block or
2400 // if it is already exported.
2401 if (isa<Argument>(Val: V)) {
2402 if (FromBB->isEntryBlock())
2403 return true;
2404
2405 // Otherwise, can only export this if it is already exported.
2406 return FuncInfo.isExportedInst(V);
2407 }
2408
2409 // Otherwise, constants can always be exported.
2410 return true;
2411}
2412
2413/// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
2414BranchProbability
2415SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
2416 const MachineBasicBlock *Dst) const {
2417 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2418 const BasicBlock *SrcBB = Src->getBasicBlock();
2419 const BasicBlock *DstBB = Dst->getBasicBlock();
2420 if (!BPI) {
2421 // If BPI is not available, set the default probability as 1 / N, where N is
2422 // the number of successors.
2423 auto SuccSize = std::max<uint32_t>(a: succ_size(BB: SrcBB), b: 1);
2424 return BranchProbability(1, SuccSize);
2425 }
2426 return BPI->getEdgeProbability(Src: SrcBB, Dst: DstBB);
2427}
2428
2429void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
2430 MachineBasicBlock *Dst,
2431 BranchProbability Prob) {
2432 if (!FuncInfo.BPI)
2433 Src->addSuccessorWithoutProb(Succ: Dst);
2434 else {
2435 if (Prob.isUnknown())
2436 Prob = getEdgeProbability(Src, Dst);
2437 Src->addSuccessor(Succ: Dst, Prob);
2438 }
2439}
2440
2441static bool InBlock(const Value *V, const BasicBlock *BB) {
2442 if (const Instruction *I = dyn_cast<Instruction>(Val: V))
2443 return I->getParent() == BB;
2444 return true;
2445}
2446
2447/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
2448/// This function emits a branch and is used at the leaves of an OR or an
2449/// AND operator tree.
2450void
2451SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
2452 MachineBasicBlock *TBB,
2453 MachineBasicBlock *FBB,
2454 MachineBasicBlock *CurBB,
2455 MachineBasicBlock *SwitchBB,
2456 BranchProbability TProb,
2457 BranchProbability FProb,
2458 bool InvertCond) {
2459 const BasicBlock *BB = CurBB->getBasicBlock();
2460
2461 // If the leaf of the tree is a comparison, merge the condition into
2462 // the caseblock.
2463 if (const CmpInst *BOp = dyn_cast<CmpInst>(Val: Cond)) {
2464 // The operands of the cmp have to be in this block. We don't know
2465 // how to export them from some other block. If this is the first block
2466 // of the sequence, no exporting is needed.
2467 if (CurBB == SwitchBB ||
2468 (isExportableFromCurrentBlock(V: BOp->getOperand(i_nocapture: 0), FromBB: BB) &&
2469 isExportableFromCurrentBlock(V: BOp->getOperand(i_nocapture: 1), FromBB: BB))) {
2470 ISD::CondCode Condition;
2471 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Val: Cond)) {
2472 ICmpInst::Predicate Pred =
2473 InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2474 Condition = getICmpCondCode(Pred);
2475 } else {
2476 const FCmpInst *FC = cast<FCmpInst>(Val: Cond);
2477 FCmpInst::Predicate Pred =
2478 InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2479 Condition = getFCmpCondCode(Pred);
2480 if (FC->hasNoNaNs() ||
2481 (isKnownNeverNaN(V: FC->getOperand(i_nocapture: 0),
2482 SQ: SimplifyQuery(DAG.getDataLayout(), FC)) &&
2483 isKnownNeverNaN(V: FC->getOperand(i_nocapture: 1),
2484 SQ: SimplifyQuery(DAG.getDataLayout(), FC))))
2485 Condition = getFCmpCodeWithoutNaN(CC: Condition);
2486 }
2487
2488 CaseBlock CB(Condition, BOp->getOperand(i_nocapture: 0), BOp->getOperand(i_nocapture: 1), nullptr,
2489 TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2490 SL->SwitchCases.push_back(x: CB);
2491 return;
2492 }
2493 }
2494
2495 // Create a CaseBlock record representing this branch.
2496 ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
2497 CaseBlock CB(Opc, Cond, ConstantInt::getTrue(Context&: *DAG.getContext()),
2498 nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2499 SL->SwitchCases.push_back(x: CB);
2500}
2501
2502// Collect dependencies on V recursively. This is used for the cost analysis in
2503// `shouldKeepJumpConditionsTogether`.
2504static bool collectInstructionDeps(
2505 SmallMapVector<const Instruction *, bool, 8> *Deps, const Value *V,
2506 SmallMapVector<const Instruction *, bool, 8> *Necessary = nullptr,
2507 unsigned Depth = 0) {
2508 // Return false if we have an incomplete count.
2509 if (Depth >= SelectionDAG::MaxRecursionDepth)
2510 return false;
2511
2512 auto *I = dyn_cast<Instruction>(Val: V);
2513 if (I == nullptr)
2514 return true;
2515
2516 if (Necessary != nullptr) {
2517 // This instruction is necessary for the other side of the condition so
2518 // don't count it.
2519 if (Necessary->contains(Key: I))
2520 return true;
2521 }
2522
2523 // Already added this dep.
2524 if (!Deps->try_emplace(Key: I, Args: false).second)
2525 return true;
2526
2527 for (unsigned OpIdx = 0, E = I->getNumOperands(); OpIdx < E; ++OpIdx)
2528 if (!collectInstructionDeps(Deps, V: I->getOperand(i: OpIdx), Necessary,
2529 Depth: Depth + 1))
2530 return false;
2531 return true;
2532}
2533
2534bool SelectionDAGBuilder::shouldKeepJumpConditionsTogether(
2535 const FunctionLoweringInfo &FuncInfo, const CondBrInst &I,
2536 Instruction::BinaryOps Opc, const Value *Lhs, const Value *Rhs,
2537 TargetLoweringBase::CondMergingParams Params) const {
2538 if (Params.BaseCost < 0)
2539 return false;
2540
2541 // Baseline cost.
2542 InstructionCost CostThresh = Params.BaseCost;
2543
2544 BranchProbabilityInfo *BPI = nullptr;
2545 if (Params.LikelyBias || Params.UnlikelyBias)
2546 BPI = FuncInfo.BPI;
2547 if (BPI != nullptr) {
2548 // See if we are either likely to get an early out or compute both lhs/rhs
2549 // of the condition.
2550 BasicBlock *IfFalse = I.getSuccessor(i: 0);
2551 BasicBlock *IfTrue = I.getSuccessor(i: 1);
2552
2553 std::optional<bool> Likely;
2554 if (BPI->isEdgeHot(Src: I.getParent(), Dst: IfTrue))
2555 Likely = true;
2556 else if (BPI->isEdgeHot(Src: I.getParent(), Dst: IfFalse))
2557 Likely = false;
2558
2559 if (Likely) {
2560 if (Opc == (*Likely ? Instruction::And : Instruction::Or))
2561 // Its likely we will have to compute both lhs and rhs of condition
2562 CostThresh += Params.LikelyBias;
2563 else {
2564 if (Params.UnlikelyBias < 0)
2565 return false;
2566 // Its likely we will get an early out.
2567 CostThresh -= Params.UnlikelyBias;
2568 }
2569 }
2570 }
2571
2572 if (CostThresh <= 0)
2573 return false;
2574
2575 // Collect "all" instructions that lhs condition is dependent on.
2576 // Use map for stable iteration (to avoid non-determanism of iteration of
2577 // SmallPtrSet). The `bool` value is just a dummy.
2578 SmallMapVector<const Instruction *, bool, 8> LhsDeps, RhsDeps;
2579 collectInstructionDeps(Deps: &LhsDeps, V: Lhs);
2580 // Collect "all" instructions that rhs condition is dependent on AND are
2581 // dependencies of lhs. This gives us an estimate on which instructions we
2582 // stand to save by splitting the condition.
2583 if (!collectInstructionDeps(Deps: &RhsDeps, V: Rhs, Necessary: &LhsDeps))
2584 return false;
2585 // Add the compare instruction itself unless its a dependency on the LHS.
2586 if (const auto *RhsI = dyn_cast<Instruction>(Val: Rhs))
2587 if (!LhsDeps.contains(Key: RhsI))
2588 RhsDeps.try_emplace(Key: RhsI, Args: false);
2589
2590 InstructionCost CostOfIncluding = 0;
2591 // See if this instruction will need to computed independently of whether RHS
2592 // is.
2593 Value *BrCond = I.getCondition();
2594 auto ShouldCountInsn = [&RhsDeps, &BrCond](const Instruction *Ins) {
2595 for (const auto *U : Ins->users()) {
2596 // If user is independent of RHS calculation we don't need to count it.
2597 if (auto *UIns = dyn_cast<Instruction>(Val: U))
2598 if (UIns != BrCond && !RhsDeps.contains(Key: UIns))
2599 return false;
2600 }
2601 return true;
2602 };
2603
2604 // Prune instructions from RHS Deps that are dependencies of unrelated
2605 // instructions. The value (SelectionDAG::MaxRecursionDepth) is fairly
2606 // arbitrary and just meant to cap the how much time we spend in the pruning
2607 // loop. Its highly unlikely to come into affect.
2608 const unsigned MaxPruneIters = SelectionDAG::MaxRecursionDepth;
2609 // Stop after a certain point. No incorrectness from including too many
2610 // instructions.
2611 for (unsigned PruneIters = 0; PruneIters < MaxPruneIters; ++PruneIters) {
2612 const Instruction *ToDrop = nullptr;
2613 for (const auto &InsPair : RhsDeps) {
2614 if (!ShouldCountInsn(InsPair.first)) {
2615 ToDrop = InsPair.first;
2616 break;
2617 }
2618 }
2619 if (ToDrop == nullptr)
2620 break;
2621 RhsDeps.erase(Key: ToDrop);
2622 }
2623
2624 for (const auto &InsPair : RhsDeps) {
2625 // Finally accumulate latency that we can only attribute to computing the
2626 // RHS condition. Use latency because we are essentially trying to calculate
2627 // the cost of the dependency chain.
2628 // Possible TODO: We could try to estimate ILP and make this more precise.
2629 CostOfIncluding += TTI->getInstructionCost(
2630 U: InsPair.first, CostKind: TargetTransformInfo::TCK_Latency);
2631
2632 if (CostOfIncluding > CostThresh)
2633 return false;
2634 }
2635 return true;
2636}
2637
2638void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
2639 MachineBasicBlock *TBB,
2640 MachineBasicBlock *FBB,
2641 MachineBasicBlock *CurBB,
2642 MachineBasicBlock *SwitchBB,
2643 Instruction::BinaryOps Opc,
2644 BranchProbability TProb,
2645 BranchProbability FProb,
2646 bool InvertCond) {
2647 // Skip over not part of the tree and remember to invert op and operands at
2648 // next level.
2649 Value *NotCond;
2650 if (match(V: Cond, P: m_OneUse(SubPattern: m_Not(V: m_Value(V&: NotCond)))) &&
2651 InBlock(V: NotCond, BB: CurBB->getBasicBlock())) {
2652 FindMergedConditions(Cond: NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
2653 InvertCond: !InvertCond);
2654 return;
2655 }
2656
2657 const Instruction *BOp = dyn_cast<Instruction>(Val: Cond);
2658 const Value *BOpOp0, *BOpOp1;
2659 // Compute the effective opcode for Cond, taking into account whether it needs
2660 // to be inverted, e.g.
2661 // and (not (or A, B)), C
2662 // gets lowered as
2663 // and (and (not A, not B), C)
2664 Instruction::BinaryOps BOpc = (Instruction::BinaryOps)0;
2665 if (BOp) {
2666 BOpc = match(V: BOp, P: m_LogicalAnd(L: m_Value(V&: BOpOp0), R: m_Value(V&: BOpOp1)))
2667 ? Instruction::And
2668 : (match(V: BOp, P: m_LogicalOr(L: m_Value(V&: BOpOp0), R: m_Value(V&: BOpOp1)))
2669 ? Instruction::Or
2670 : (Instruction::BinaryOps)0);
2671 if (InvertCond) {
2672 if (BOpc == Instruction::And)
2673 BOpc = Instruction::Or;
2674 else if (BOpc == Instruction::Or)
2675 BOpc = Instruction::And;
2676 }
2677 }
2678
2679 // If this node is not part of the or/and tree, emit it as a branch.
2680 // Note that all nodes in the tree should have same opcode.
2681 bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->hasOneUse();
2682 if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() ||
2683 !InBlock(V: BOpOp0, BB: CurBB->getBasicBlock()) ||
2684 !InBlock(V: BOpOp1, BB: CurBB->getBasicBlock())) {
2685 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
2686 TProb, FProb, InvertCond);
2687 return;
2688 }
2689
2690 // Create TmpBB after CurBB.
2691 MachineFunction::iterator BBI(CurBB);
2692 MachineFunction &MF = DAG.getMachineFunction();
2693 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(BB: CurBB->getBasicBlock());
2694 CurBB->getParent()->insert(MBBI: ++BBI, MBB: TmpBB);
2695
2696 if (Opc == Instruction::Or) {
2697 // Codegen X | Y as:
2698 // BB1:
2699 // jmp_if_X TBB
2700 // jmp TmpBB
2701 // TmpBB:
2702 // jmp_if_Y TBB
2703 // jmp FBB
2704 //
2705
2706 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2707 // The requirement is that
2708 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
2709 // = TrueProb for original BB.
2710 // Assuming the original probabilities are A and B, one choice is to set
2711 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
2712 // A/(1+B) and 2B/(1+B). This choice assumes that
2713 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
2714 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
2715 // TmpBB, but the math is more complicated.
2716
2717 auto NewTrueProb = TProb / 2;
2718 auto NewFalseProb = TProb / 2 + FProb;
2719 // Emit the LHS condition.
2720 FindMergedConditions(Cond: BOpOp0, TBB, FBB: TmpBB, CurBB, SwitchBB, Opc, TProb: NewTrueProb,
2721 FProb: NewFalseProb, InvertCond);
2722
2723 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
2724 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
2725 BranchProbability::normalizeProbabilities(Begin: Probs.begin(), End: Probs.end());
2726 // Emit the RHS condition into TmpBB.
2727 FindMergedConditions(Cond: BOpOp1, TBB, FBB, CurBB: TmpBB, SwitchBB, Opc, TProb: Probs[0],
2728 FProb: Probs[1], InvertCond);
2729 } else {
2730 assert(Opc == Instruction::And && "Unknown merge op!");
2731 // Codegen X & Y as:
2732 // BB1:
2733 // jmp_if_X TmpBB
2734 // jmp FBB
2735 // TmpBB:
2736 // jmp_if_Y TBB
2737 // jmp FBB
2738 //
2739 // This requires creation of TmpBB after CurBB.
2740
2741 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2742 // The requirement is that
2743 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
2744 // = FalseProb for original BB.
2745 // Assuming the original probabilities are A and B, one choice is to set
2746 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
2747 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
2748 // TrueProb for BB1 * FalseProb for TmpBB.
2749
2750 auto NewTrueProb = TProb + FProb / 2;
2751 auto NewFalseProb = FProb / 2;
2752 // Emit the LHS condition.
2753 FindMergedConditions(Cond: BOpOp0, TBB: TmpBB, FBB, CurBB, SwitchBB, Opc, TProb: NewTrueProb,
2754 FProb: NewFalseProb, InvertCond);
2755
2756 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
2757 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
2758 BranchProbability::normalizeProbabilities(Begin: Probs.begin(), End: Probs.end());
2759 // Emit the RHS condition into TmpBB.
2760 FindMergedConditions(Cond: BOpOp1, TBB, FBB, CurBB: TmpBB, SwitchBB, Opc, TProb: Probs[0],
2761 FProb: Probs[1], InvertCond);
2762 }
2763}
2764
2765/// If the set of cases should be emitted as a series of branches, return true.
2766/// If we should emit this as a bunch of and/or'd together conditions, return
2767/// false.
2768bool
2769SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
2770 if (Cases.size() != 2) return true;
2771
2772 // If this is two comparisons of the same values or'd or and'd together, they
2773 // will get folded into a single comparison, so don't emit two blocks.
2774 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2775 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2776 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2777 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2778 return false;
2779 }
2780
2781 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
2782 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
2783 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2784 Cases[0].CC == Cases[1].CC &&
2785 isa<Constant>(Val: Cases[0].CmpRHS) &&
2786 cast<Constant>(Val: Cases[0].CmpRHS)->isNullValue()) {
2787 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2788 return false;
2789 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2790 return false;
2791 }
2792
2793 return true;
2794}
2795
2796void SelectionDAGBuilder::visitUncondBr(const UncondBrInst &I) {
2797 MachineBasicBlock *BrMBB = FuncInfo.MBB;
2798
2799 MachineBasicBlock *Succ0MBB = FuncInfo.getMBB(BB: I.getSuccessor(i: 0));
2800
2801 // Update machine-CFG edges.
2802 BrMBB->addSuccessor(Succ: Succ0MBB);
2803
2804 // If this is not a fall-through branch or optimizations are switched off,
2805 // emit the branch.
2806 if (Succ0MBB != NextBlock(MBB: BrMBB) ||
2807 TM.getOptLevel() == CodeGenOptLevel::None) {
2808 auto Br = DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(), VT: MVT::Other, N1: getControlRoot(),
2809 N2: DAG.getBasicBlock(MBB: Succ0MBB));
2810 setValue(V: &I, NewN: Br);
2811 DAG.setRoot(Br);
2812 }
2813}
2814
2815void SelectionDAGBuilder::visitCondBr(const CondBrInst &I) {
2816 MachineBasicBlock *BrMBB = FuncInfo.MBB;
2817
2818 MachineBasicBlock *Succ0MBB = FuncInfo.getMBB(BB: I.getSuccessor(i: 0));
2819
2820 // If this condition is one of the special cases we handle, do special stuff
2821 // now.
2822 const Value *CondVal = I.getCondition();
2823 MachineBasicBlock *Succ1MBB = FuncInfo.getMBB(BB: I.getSuccessor(i: 1));
2824
2825 // If this is a series of conditions that are or'd or and'd together, emit
2826 // this as a sequence of branches instead of setcc's with and/or operations.
2827 // As long as jumps are not expensive (exceptions for multi-use logic ops,
2828 // unpredictable branches, and vector extracts because those jumps are likely
2829 // expensive for any target), this should improve performance.
2830 // For example, instead of something like:
2831 // cmp A, B
2832 // C = seteq
2833 // cmp D, E
2834 // F = setle
2835 // or C, F
2836 // jnz foo
2837 // Emit:
2838 // cmp A, B
2839 // je foo
2840 // cmp D, E
2841 // jle foo
2842 bool IsUnpredictable = I.hasMetadata(KindID: LLVMContext::MD_unpredictable);
2843 const Instruction *BOp = dyn_cast<Instruction>(Val: CondVal);
2844 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp &&
2845 BOp->hasOneUse() && !IsUnpredictable) {
2846 Value *Vec;
2847 const Value *BOp0, *BOp1;
2848 Instruction::BinaryOps Opcode = (Instruction::BinaryOps)0;
2849 if (match(V: BOp, P: m_LogicalAnd(L: m_Value(V&: BOp0), R: m_Value(V&: BOp1))))
2850 Opcode = Instruction::And;
2851 else if (match(V: BOp, P: m_LogicalOr(L: m_Value(V&: BOp0), R: m_Value(V&: BOp1))))
2852 Opcode = Instruction::Or;
2853
2854 if (Opcode &&
2855 !(match(V: BOp0, P: m_ExtractElt(Val: m_Value(V&: Vec), Idx: m_Value())) &&
2856 match(V: BOp1, P: m_ExtractElt(Val: m_Specific(V: Vec), Idx: m_Value()))) &&
2857 !shouldKeepJumpConditionsTogether(
2858 FuncInfo, I, Opc: Opcode, Lhs: BOp0, Rhs: BOp1,
2859 Params: DAG.getTargetLoweringInfo().getJumpConditionMergingParams(
2860 Opcode, BOp0, BOp1))) {
2861 FindMergedConditions(Cond: BOp, TBB: Succ0MBB, FBB: Succ1MBB, CurBB: BrMBB, SwitchBB: BrMBB, Opc: Opcode,
2862 TProb: getEdgeProbability(Src: BrMBB, Dst: Succ0MBB),
2863 FProb: getEdgeProbability(Src: BrMBB, Dst: Succ1MBB),
2864 /*InvertCond=*/false);
2865 // If the compares in later blocks need to use values not currently
2866 // exported from this block, export them now. This block should always
2867 // be the first entry.
2868 assert(SL->SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
2869
2870 // Allow some cases to be rejected.
2871 if (ShouldEmitAsBranches(Cases: SL->SwitchCases)) {
2872 for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) {
2873 ExportFromCurrentBlock(V: SL->SwitchCases[i].CmpLHS);
2874 ExportFromCurrentBlock(V: SL->SwitchCases[i].CmpRHS);
2875 }
2876
2877 // Emit the branch for this block.
2878 visitSwitchCase(CB&: SL->SwitchCases[0], SwitchBB: BrMBB);
2879 SL->SwitchCases.erase(position: SL->SwitchCases.begin());
2880 return;
2881 }
2882
2883 // Okay, we decided not to do this, remove any inserted MBB's and clear
2884 // SwitchCases.
2885 for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i)
2886 FuncInfo.MF->erase(MBBI: SL->SwitchCases[i].ThisBB);
2887
2888 SL->SwitchCases.clear();
2889 }
2890 }
2891
2892 // Create a CaseBlock record representing this branch.
2893 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(Context&: *DAG.getContext()),
2894 nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc(),
2895 BranchProbability::getUnknown(), BranchProbability::getUnknown(),
2896 IsUnpredictable);
2897
2898 // Use visitSwitchCase to actually insert the fast branch sequence for this
2899 // cond branch.
2900 visitSwitchCase(CB, SwitchBB: BrMBB);
2901}
2902
2903/// visitSwitchCase - Emits the necessary code to represent a single node in
2904/// the binary search tree resulting from lowering a switch instruction.
2905void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
2906 MachineBasicBlock *SwitchBB) {
2907 SDValue Cond;
2908 SDValue CondLHS = getValue(V: CB.CmpLHS);
2909 SDLoc dl = CB.DL;
2910
2911 if (CB.CC == ISD::SETTRUE) {
2912 // Branch or fall through to TrueBB.
2913 addSuccessorWithProb(Src: SwitchBB, Dst: CB.TrueBB, Prob: CB.TrueProb);
2914 SwitchBB->normalizeSuccProbs();
2915 if (CB.TrueBB != NextBlock(MBB: SwitchBB)) {
2916 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: getControlRoot(),
2917 N2: DAG.getBasicBlock(MBB: CB.TrueBB)));
2918 }
2919 return;
2920 }
2921
2922 auto &TLI = DAG.getTargetLoweringInfo();
2923 EVT MemVT = TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: CB.CmpLHS->getType());
2924
2925 // Build the setcc now.
2926 if (!CB.CmpMHS) {
2927 // Fold "(X == true)" to X and "(X == false)" to !X to
2928 // handle common cases produced by branch lowering.
2929 if (CB.CmpRHS == ConstantInt::getTrue(Context&: *DAG.getContext()) &&
2930 CB.CC == ISD::SETEQ)
2931 Cond = CondLHS;
2932 else if (CB.CmpRHS == ConstantInt::getFalse(Context&: *DAG.getContext()) &&
2933 CB.CC == ISD::SETEQ) {
2934 SDValue True = DAG.getConstant(Val: 1, DL: dl, VT: CondLHS.getValueType());
2935 Cond = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: CondLHS.getValueType(), N1: CondLHS, N2: True);
2936 } else {
2937 SDValue CondRHS = getValue(V: CB.CmpRHS);
2938
2939 // If a pointer's DAG type is larger than its memory type then the DAG
2940 // values are zero-extended. This breaks signed comparisons so truncate
2941 // back to the underlying type before doing the compare.
2942 if (CondLHS.getValueType() != MemVT) {
2943 CondLHS = DAG.getPtrExtOrTrunc(Op: CondLHS, DL: getCurSDLoc(), VT: MemVT);
2944 CondRHS = DAG.getPtrExtOrTrunc(Op: CondRHS, DL: getCurSDLoc(), VT: MemVT);
2945 }
2946 Cond = DAG.getSetCC(DL: dl, VT: MVT::i1, LHS: CondLHS, RHS: CondRHS, Cond: CB.CC);
2947 }
2948 } else {
2949 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
2950
2951 const APInt& Low = cast<ConstantInt>(Val: CB.CmpLHS)->getValue();
2952 const APInt& High = cast<ConstantInt>(Val: CB.CmpRHS)->getValue();
2953
2954 SDValue CmpOp = getValue(V: CB.CmpMHS);
2955 EVT VT = CmpOp.getValueType();
2956
2957 if (cast<ConstantInt>(Val: CB.CmpLHS)->isMinValue(IsSigned: true)) {
2958 Cond = DAG.getSetCC(DL: dl, VT: MVT::i1, LHS: CmpOp, RHS: DAG.getConstant(Val: High, DL: dl, VT),
2959 Cond: ISD::SETLE);
2960 } else {
2961 SDValue SUB = DAG.getNode(Opcode: ISD::SUB, DL: dl,
2962 VT, N1: CmpOp, N2: DAG.getConstant(Val: Low, DL: dl, VT));
2963 Cond = DAG.getSetCC(DL: dl, VT: MVT::i1, LHS: SUB,
2964 RHS: DAG.getConstant(Val: High-Low, DL: dl, VT), Cond: ISD::SETULE);
2965 }
2966 }
2967
2968 // Update successor info
2969 addSuccessorWithProb(Src: SwitchBB, Dst: CB.TrueBB, Prob: CB.TrueProb);
2970 // TrueBB and FalseBB are always different unless the incoming IR is
2971 // degenerate. This only happens when running llc on weird IR.
2972 if (CB.TrueBB != CB.FalseBB)
2973 addSuccessorWithProb(Src: SwitchBB, Dst: CB.FalseBB, Prob: CB.FalseProb);
2974 SwitchBB->normalizeSuccProbs();
2975
2976 // If the lhs block is the next block, invert the condition so that we can
2977 // fall through to the lhs instead of the rhs block.
2978 if (CB.TrueBB == NextBlock(MBB: SwitchBB)) {
2979 std::swap(a&: CB.TrueBB, b&: CB.FalseBB);
2980 SDValue True = DAG.getConstant(Val: 1, DL: dl, VT: Cond.getValueType());
2981 Cond = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: Cond.getValueType(), N1: Cond, N2: True);
2982 }
2983
2984 SDNodeFlags Flags;
2985 Flags.setUnpredictable(CB.IsUnpredictable);
2986 SDValue BrCond = DAG.getNode(Opcode: ISD::BRCOND, DL: dl, VT: MVT::Other, N1: getControlRoot(),
2987 N2: Cond, N3: DAG.getBasicBlock(MBB: CB.TrueBB), Flags);
2988
2989 setValue(V: CurInst, NewN: BrCond);
2990
2991 // Insert the false branch. Do this even if it's a fall through branch,
2992 // this makes it easier to do DAG optimizations which require inverting
2993 // the branch condition.
2994 BrCond = DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: BrCond,
2995 N2: DAG.getBasicBlock(MBB: CB.FalseBB));
2996
2997 DAG.setRoot(BrCond);
2998}
2999
3000/// visitJumpTable - Emit JumpTable node in the current MBB
3001void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) {
3002 // Emit the code for the jump table
3003 assert(JT.SL && "Should set SDLoc for SelectionDAG!");
3004 assert(JT.Reg && "Should lower JT Header first!");
3005 EVT PTy = DAG.getTargetLoweringInfo().getJumpTableRegTy(DL: DAG.getDataLayout());
3006 SDValue Index = DAG.getCopyFromReg(Chain: getControlRoot(), dl: *JT.SL, Reg: JT.Reg, VT: PTy);
3007 SDValue Table = DAG.getJumpTable(JTI: JT.JTI, VT: PTy);
3008 SDValue BrJumpTable = DAG.getNode(Opcode: ISD::BR_JT, DL: *JT.SL, VT: MVT::Other,
3009 N1: Index.getValue(R: 1), N2: Table, N3: Index);
3010 DAG.setRoot(BrJumpTable);
3011}
3012
3013/// visitJumpTableHeader - This function emits necessary code to produce index
3014/// in the JumpTable from switch case.
3015void SelectionDAGBuilder::visitJumpTableHeader(SwitchCG::JumpTable &JT,
3016 JumpTableHeader &JTH,
3017 MachineBasicBlock *SwitchBB) {
3018 assert(JT.SL && "Should set SDLoc for SelectionDAG!");
3019 const SDLoc &dl = *JT.SL;
3020
3021 // Subtract the lowest switch case value from the value being switched on.
3022 SDValue SwitchOp = getValue(V: JTH.SValue);
3023 EVT VT = SwitchOp.getValueType();
3024 SDValue Sub = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: SwitchOp,
3025 N2: DAG.getConstant(Val: JTH.First, DL: dl, VT));
3026
3027 // The SDNode we just created, which holds the value being switched on minus
3028 // the smallest case value, needs to be copied to a virtual register so it
3029 // can be used as an index into the jump table in a subsequent basic block.
3030 // This value may be smaller or larger than the target's pointer type, and
3031 // therefore require extension or truncating.
3032 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3033 SwitchOp =
3034 DAG.getZExtOrTrunc(Op: Sub, DL: dl, VT: TLI.getJumpTableRegTy(DL: DAG.getDataLayout()));
3035
3036 Register JumpTableReg =
3037 FuncInfo.CreateReg(VT: TLI.getJumpTableRegTy(DL: DAG.getDataLayout()));
3038 SDValue CopyTo =
3039 DAG.getCopyToReg(Chain: getControlRoot(), dl, Reg: JumpTableReg, N: SwitchOp);
3040 JT.Reg = JumpTableReg;
3041
3042 if (!JTH.FallthroughUnreachable) {
3043 // Emit the range check for the jump table, and branch to the default block
3044 // for the switch statement if the value being switched on exceeds the
3045 // largest case in the switch.
3046 SDValue CMP = DAG.getSetCC(
3047 DL: dl, VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(),
3048 VT: Sub.getValueType()),
3049 LHS: Sub, RHS: DAG.getConstant(Val: JTH.Last - JTH.First, DL: dl, VT), Cond: ISD::SETUGT);
3050
3051 SDValue BrCond = DAG.getNode(Opcode: ISD::BRCOND, DL: dl,
3052 VT: MVT::Other, N1: CopyTo, N2: CMP,
3053 N3: DAG.getBasicBlock(MBB: JT.Default));
3054
3055 // Avoid emitting unnecessary branches to the next block.
3056 if (JT.MBB != NextBlock(MBB: SwitchBB))
3057 BrCond = DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: BrCond,
3058 N2: DAG.getBasicBlock(MBB: JT.MBB));
3059
3060 DAG.setRoot(BrCond);
3061 } else {
3062 // Avoid emitting unnecessary branches to the next block.
3063 if (JT.MBB != NextBlock(MBB: SwitchBB))
3064 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: CopyTo,
3065 N2: DAG.getBasicBlock(MBB: JT.MBB)));
3066 else
3067 DAG.setRoot(CopyTo);
3068 }
3069}
3070
3071/// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
3072/// variable if there exists one.
3073static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL,
3074 SDValue &Chain) {
3075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3076 EVT PtrTy = TLI.getPointerTy(DL: DAG.getDataLayout());
3077 EVT PtrMemTy = TLI.getPointerMemTy(DL: DAG.getDataLayout());
3078 MachineFunction &MF = DAG.getMachineFunction();
3079 Value *Global =
3080 TLI.getSDagStackGuard(M: *MF.getFunction().getParent(), Libcalls: DAG.getLibcalls());
3081 MachineSDNode *Node =
3082 DAG.getMachineNode(Opcode: TargetOpcode::LOAD_STACK_GUARD, dl: DL, VT: PtrTy, Op1: Chain);
3083 if (Global) {
3084 MachinePointerInfo MPInfo(Global);
3085 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
3086 MachineMemOperand::MODereferenceable;
3087 MachineMemOperand *MemRef = MF.getMachineMemOperand(
3088 PtrInfo: MPInfo, F: Flags, Size: PtrTy.getSizeInBits() / 8, BaseAlignment: DAG.getEVTAlign(MemoryVT: PtrTy));
3089 DAG.setNodeMemRefs(N: Node, NewMemRefs: {MemRef});
3090 }
3091 if (PtrTy != PtrMemTy)
3092 return DAG.getPtrExtOrTrunc(Op: SDValue(Node, 0), DL, VT: PtrMemTy);
3093 return SDValue(Node, 0);
3094}
3095
3096/// Codegen a new tail for a stack protector check ParentMBB which has had its
3097/// tail spliced into a stack protector check success bb.
3098///
3099/// For a high level explanation of how this fits into the stack protector
3100/// generation see the comment on the declaration of class
3101/// StackProtectorDescriptor.
3102void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
3103 MachineBasicBlock *ParentBB) {
3104
3105 // First create the loads to the guard/stack slot for the comparison.
3106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3107 auto &DL = DAG.getDataLayout();
3108 EVT PtrTy = TLI.getFrameIndexTy(DL);
3109 EVT PtrMemTy = TLI.getPointerMemTy(DL, AS: DL.getAllocaAddrSpace());
3110
3111 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
3112 int FI = MFI.getStackProtectorIndex();
3113
3114 SDValue Guard;
3115 SDLoc dl = getCurSDLoc();
3116 SDValue StackSlotPtr = DAG.getFrameIndex(FI, VT: PtrTy);
3117 const Module &M = *ParentBB->getParent()->getFunction().getParent();
3118 Align Align = DL.getPrefTypeAlign(
3119 Ty: PointerType::get(C&: M.getContext(), AddressSpace: DL.getAllocaAddrSpace()));
3120
3121 // Generate code to load the content of the guard slot.
3122 SDValue GuardVal = DAG.getLoad(
3123 VT: PtrMemTy, dl, Chain: DAG.getEntryNode(), Ptr: StackSlotPtr,
3124 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI), Alignment: Align,
3125 MMOFlags: MachineMemOperand::MOVolatile);
3126
3127 if (TLI.useStackGuardXorFP())
3128 GuardVal = TLI.emitStackGuardXorFP(DAG, Val: GuardVal, DL: dl);
3129
3130 // If we're using function-based instrumentation, call the guard check
3131 // function
3132 if (SPD.shouldEmitFunctionBasedCheckStackProtector()) {
3133 // Get the guard check function from the target and verify it exists since
3134 // we're using function-based instrumentation
3135 const Function *GuardCheckFn =
3136 TLI.getSSPStackGuardCheck(M, Libcalls: DAG.getLibcalls());
3137 assert(GuardCheckFn && "Guard check function is null");
3138
3139 // The target provides a guard check function to validate the guard value.
3140 // Generate a call to that function with the content of the guard slot as
3141 // argument.
3142 FunctionType *FnTy = GuardCheckFn->getFunctionType();
3143 assert(FnTy->getNumParams() == 1 && "Invalid function signature");
3144
3145 TargetLowering::ArgListTy Args;
3146 TargetLowering::ArgListEntry Entry(GuardVal, FnTy->getParamType(i: 0));
3147 if (GuardCheckFn->hasParamAttribute(ArgNo: 0, Kind: Attribute::AttrKind::InReg))
3148 Entry.IsInReg = true;
3149 Args.push_back(x: Entry);
3150
3151 TargetLowering::CallLoweringInfo CLI(DAG);
3152 CLI.setDebugLoc(getCurSDLoc())
3153 .setChain(DAG.getEntryNode())
3154 .setCallee(CC: GuardCheckFn->getCallingConv(), ResultType: FnTy->getReturnType(),
3155 Target: getValue(V: GuardCheckFn), ArgsList: std::move(Args));
3156
3157 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
3158 DAG.setRoot(Result.second);
3159 return;
3160 }
3161
3162 // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
3163 // Otherwise, emit a volatile load to retrieve the stack guard value.
3164 SDValue Chain = DAG.getEntryNode();
3165 if (TLI.useLoadStackGuardNode(M)) {
3166 Guard = getLoadStackGuard(DAG, DL: dl, Chain);
3167 } else {
3168 if (const Value *IRGuard = TLI.getSDagStackGuard(M, Libcalls: DAG.getLibcalls())) {
3169 SDValue GuardPtr = getValue(V: IRGuard);
3170 Guard = DAG.getLoad(VT: PtrMemTy, dl, Chain, Ptr: GuardPtr,
3171 PtrInfo: MachinePointerInfo(IRGuard, 0), Alignment: Align,
3172 MMOFlags: MachineMemOperand::MOVolatile);
3173 } else {
3174 LLVMContext &Ctx = *DAG.getContext();
3175 Ctx.diagnose(DI: DiagnosticInfoGeneric("unable to lower stackguard"));
3176 Guard = DAG.getPOISON(VT: PtrMemTy);
3177 }
3178 }
3179
3180 // Perform the comparison via a getsetcc.
3181 SDValue Cmp = DAG.getSetCC(
3182 DL: dl, VT: TLI.getSetCCResultType(DL, Context&: *DAG.getContext(), VT: Guard.getValueType()),
3183 LHS: Guard, RHS: GuardVal, Cond: ISD::SETNE);
3184
3185 // If the guard/stackslot do not equal, branch to failure MBB.
3186 SDValue BrCond = DAG.getNode(Opcode: ISD::BRCOND, DL: dl, VT: MVT::Other, N1: getControlRoot(),
3187 N2: Cmp, N3: DAG.getBasicBlock(MBB: SPD.getFailureMBB()));
3188 // Otherwise branch to success MBB.
3189 SDValue Br = DAG.getNode(Opcode: ISD::BR, DL: dl,
3190 VT: MVT::Other, N1: BrCond,
3191 N2: DAG.getBasicBlock(MBB: SPD.getSuccessMBB()));
3192
3193 DAG.setRoot(Br);
3194}
3195
3196/// Codegen the failure basic block for a stack protector check.
3197///
3198/// A failure stack protector machine basic block consists simply of a call to
3199/// __stack_chk_fail().
3200///
3201/// For a high level explanation of how this fits into the stack protector
3202/// generation see the comment on the declaration of class
3203/// StackProtectorDescriptor.
3204void SelectionDAGBuilder::visitSPDescriptorFailure(
3205 StackProtectorDescriptor &SPD) {
3206
3207 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3208 MachineBasicBlock *ParentBB = SPD.getParentMBB();
3209 const Module &M = *ParentBB->getParent()->getFunction().getParent();
3210 SDValue Chain;
3211
3212 // For -Oz builds with a guard check function, we use function-based
3213 // instrumentation. Otherwise, if we have a guard check function, we call it
3214 // in the failure block.
3215 auto *GuardCheckFn = TLI.getSSPStackGuardCheck(M, Libcalls: DAG.getLibcalls());
3216 if (GuardCheckFn && !SPD.shouldEmitFunctionBasedCheckStackProtector()) {
3217 // First create the loads to the guard/stack slot for the comparison.
3218 auto &DL = DAG.getDataLayout();
3219 EVT PtrTy = TLI.getFrameIndexTy(DL);
3220 EVT PtrMemTy = TLI.getPointerMemTy(DL, AS: DL.getAllocaAddrSpace());
3221
3222 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
3223 int FI = MFI.getStackProtectorIndex();
3224
3225 SDLoc dl = getCurSDLoc();
3226 SDValue StackSlotPtr = DAG.getFrameIndex(FI, VT: PtrTy);
3227 Align Align = DL.getPrefTypeAlign(
3228 Ty: PointerType::get(C&: M.getContext(), AddressSpace: DL.getAllocaAddrSpace()));
3229
3230 // Generate code to load the content of the guard slot.
3231 SDValue GuardVal = DAG.getLoad(
3232 VT: PtrMemTy, dl, Chain: DAG.getEntryNode(), Ptr: StackSlotPtr,
3233 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI), Alignment: Align,
3234 MMOFlags: MachineMemOperand::MOVolatile);
3235
3236 if (TLI.useStackGuardXorFP())
3237 GuardVal = TLI.emitStackGuardXorFP(DAG, Val: GuardVal, DL: dl);
3238
3239 // The target provides a guard check function to validate the guard value.
3240 // Generate a call to that function with the content of the guard slot as
3241 // argument.
3242 FunctionType *FnTy = GuardCheckFn->getFunctionType();
3243 assert(FnTy->getNumParams() == 1 && "Invalid function signature");
3244
3245 TargetLowering::ArgListTy Args;
3246 TargetLowering::ArgListEntry Entry(GuardVal, FnTy->getParamType(i: 0));
3247 if (GuardCheckFn->hasParamAttribute(ArgNo: 0, Kind: Attribute::AttrKind::InReg))
3248 Entry.IsInReg = true;
3249 Args.push_back(x: Entry);
3250
3251 TargetLowering::CallLoweringInfo CLI(DAG);
3252 CLI.setDebugLoc(getCurSDLoc())
3253 .setChain(DAG.getEntryNode())
3254 .setCallee(CC: GuardCheckFn->getCallingConv(), ResultType: FnTy->getReturnType(),
3255 Target: getValue(V: GuardCheckFn), ArgsList: std::move(Args));
3256
3257 Chain = TLI.LowerCallTo(CLI).second;
3258 } else {
3259 TargetLowering::MakeLibCallOptions CallOptions;
3260 CallOptions.setDiscardResult(true);
3261 Chain = TLI.makeLibCall(DAG, LC: RTLIB::STACKPROTECTOR_CHECK_FAIL, RetVT: MVT::isVoid,
3262 Ops: {}, CallOptions, dl: getCurSDLoc())
3263 .second;
3264 }
3265
3266 // Emit a trap instruction if we are required to do so.
3267 const TargetOptions &TargetOpts = DAG.getTarget().Options;
3268 if (TargetOpts.TrapUnreachable && !TargetOpts.NoTrapAfterNoreturn)
3269 Chain = DAG.getNode(Opcode: ISD::TRAP, DL: getCurSDLoc(), VT: MVT::Other, Operand: Chain);
3270
3271 DAG.setRoot(Chain);
3272}
3273
3274/// visitBitTestHeader - This function emits necessary code to produce value
3275/// suitable for "bit tests"
3276void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
3277 MachineBasicBlock *SwitchBB) {
3278 SDLoc dl = getCurSDLoc();
3279
3280 // Subtract the minimum value.
3281 SDValue SwitchOp = getValue(V: B.SValue);
3282 EVT VT = SwitchOp.getValueType();
3283 SDValue RangeSub =
3284 DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: SwitchOp, N2: DAG.getConstant(Val: B.First, DL: dl, VT));
3285
3286 // Determine the type of the test operands.
3287 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3288 bool UsePtrType = false;
3289 if (!TLI.isTypeLegal(VT)) {
3290 UsePtrType = true;
3291 } else {
3292 for (const BitTestCase &Case : B.Cases)
3293 if (!isUIntN(N: VT.getSizeInBits(), x: Case.Mask)) {
3294 // Switch table case range are encoded into series of masks.
3295 // Just use pointer type, it's guaranteed to fit.
3296 UsePtrType = true;
3297 break;
3298 }
3299 }
3300 SDValue Sub = RangeSub;
3301 if (UsePtrType) {
3302 VT = TLI.getPointerTy(DL: DAG.getDataLayout());
3303 Sub = DAG.getZExtOrTrunc(Op: Sub, DL: dl, VT);
3304 }
3305
3306 B.RegVT = VT.getSimpleVT();
3307 B.Reg = FuncInfo.CreateReg(VT: B.RegVT);
3308 SDValue CopyTo = DAG.getCopyToReg(Chain: getControlRoot(), dl, Reg: B.Reg, N: Sub);
3309
3310 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
3311
3312 if (!B.FallthroughUnreachable)
3313 addSuccessorWithProb(Src: SwitchBB, Dst: B.Default, Prob: B.DefaultProb);
3314 addSuccessorWithProb(Src: SwitchBB, Dst: MBB, Prob: B.Prob);
3315 SwitchBB->normalizeSuccProbs();
3316
3317 SDValue Root = CopyTo;
3318 if (!B.FallthroughUnreachable) {
3319 // Conditional branch to the default block.
3320 SDValue RangeCmp = DAG.getSetCC(DL: dl,
3321 VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(),
3322 VT: RangeSub.getValueType()),
3323 LHS: RangeSub, RHS: DAG.getConstant(Val: B.Range, DL: dl, VT: RangeSub.getValueType()),
3324 Cond: ISD::SETUGT);
3325
3326 Root = DAG.getNode(Opcode: ISD::BRCOND, DL: dl, VT: MVT::Other, N1: Root, N2: RangeCmp,
3327 N3: DAG.getBasicBlock(MBB: B.Default));
3328 }
3329
3330 // Avoid emitting unnecessary branches to the next block.
3331 if (MBB != NextBlock(MBB: SwitchBB))
3332 Root = DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: Root, N2: DAG.getBasicBlock(MBB));
3333
3334 DAG.setRoot(Root);
3335}
3336
3337/// visitBitTestCase - this function produces one "bit test"
3338void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
3339 MachineBasicBlock *NextMBB,
3340 BranchProbability BranchProbToNext,
3341 Register Reg, BitTestCase &B,
3342 MachineBasicBlock *SwitchBB) {
3343 SDLoc dl = getCurSDLoc();
3344 MVT VT = BB.RegVT;
3345 SDValue ShiftOp = DAG.getCopyFromReg(Chain: getControlRoot(), dl, Reg, VT);
3346 SDValue Cmp;
3347 unsigned PopCount = llvm::popcount(Value: B.Mask);
3348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3349 if (PopCount == 1) {
3350 // Testing for a single bit; just compare the shift count with what it
3351 // would need to be to shift a 1 bit in that position.
3352 Cmp = DAG.getSetCC(
3353 DL: dl, VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT),
3354 LHS: ShiftOp, RHS: DAG.getConstant(Val: llvm::countr_zero(Val: B.Mask), DL: dl, VT),
3355 Cond: ISD::SETEQ);
3356 } else if (PopCount == BB.Range) {
3357 // There is only one zero bit in the range, test for it directly.
3358 Cmp = DAG.getSetCC(
3359 DL: dl, VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT),
3360 LHS: ShiftOp, RHS: DAG.getConstant(Val: llvm::countr_one(Value: B.Mask), DL: dl, VT), Cond: ISD::SETNE);
3361 } else {
3362 // Make desired shift
3363 SDValue SwitchVal = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT,
3364 N1: DAG.getConstant(Val: 1, DL: dl, VT), N2: ShiftOp);
3365
3366 // Emit bit tests and jumps
3367 SDValue AndOp = DAG.getNode(Opcode: ISD::AND, DL: dl,
3368 VT, N1: SwitchVal, N2: DAG.getConstant(Val: B.Mask, DL: dl, VT));
3369 Cmp = DAG.getSetCC(
3370 DL: dl, VT: TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT),
3371 LHS: AndOp, RHS: DAG.getConstant(Val: 0, DL: dl, VT), Cond: ISD::SETNE);
3372 }
3373
3374 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
3375 addSuccessorWithProb(Src: SwitchBB, Dst: B.TargetBB, Prob: B.ExtraProb);
3376 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
3377 addSuccessorWithProb(Src: SwitchBB, Dst: NextMBB, Prob: BranchProbToNext);
3378 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
3379 // one as they are relative probabilities (and thus work more like weights),
3380 // and hence we need to normalize them to let the sum of them become one.
3381 SwitchBB->normalizeSuccProbs();
3382
3383 SDValue BrAnd = DAG.getNode(Opcode: ISD::BRCOND, DL: dl,
3384 VT: MVT::Other, N1: getControlRoot(),
3385 N2: Cmp, N3: DAG.getBasicBlock(MBB: B.TargetBB));
3386
3387 // Avoid emitting unnecessary branches to the next block.
3388 if (NextMBB != NextBlock(MBB: SwitchBB))
3389 BrAnd = DAG.getNode(Opcode: ISD::BR, DL: dl, VT: MVT::Other, N1: BrAnd,
3390 N2: DAG.getBasicBlock(MBB: NextMBB));
3391
3392 DAG.setRoot(BrAnd);
3393}
3394
3395void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
3396 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
3397
3398 // Retrieve successors. Look through artificial IR level blocks like
3399 // catchswitch for successors.
3400 MachineBasicBlock *Return = FuncInfo.getMBB(BB: I.getSuccessor(i: 0));
3401 const BasicBlock *EHPadBB = I.getSuccessor(i: 1);
3402 MachineBasicBlock *EHPadMBB = FuncInfo.getMBB(BB: EHPadBB);
3403
3404 // Deopt and ptrauth bundles are lowered in helper functions, and we don't
3405 // have to do anything here to lower funclet bundles.
3406 failForInvalidBundles(I, Name: "invokes",
3407 AllowedBundles: {LLVMContext::OB_deopt, LLVMContext::OB_gc_transition,
3408 LLVMContext::OB_gc_live, LLVMContext::OB_funclet,
3409 LLVMContext::OB_cfguardtarget, LLVMContext::OB_ptrauth,
3410 LLVMContext::OB_clang_arc_attachedcall,
3411 LLVMContext::OB_kcfi});
3412
3413 const Value *Callee(I.getCalledOperand());
3414 const Function *Fn = dyn_cast<Function>(Val: Callee);
3415 if (isa<InlineAsm>(Val: Callee))
3416 visitInlineAsm(Call: I, EHPadBB);
3417 else if (Fn && Fn->isIntrinsic()) {
3418 switch (Fn->getIntrinsicID()) {
3419 default:
3420 llvm_unreachable("Cannot invoke this intrinsic");
3421 case Intrinsic::donothing:
3422 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
3423 case Intrinsic::seh_try_begin:
3424 case Intrinsic::seh_scope_begin:
3425 case Intrinsic::seh_try_end:
3426 case Intrinsic::seh_scope_end:
3427 if (EHPadMBB)
3428 // a block referenced by EH table
3429 // so dtor-funclet not removed by opts
3430 EHPadMBB->setMachineBlockAddressTaken();
3431 break;
3432 case Intrinsic::experimental_patchpoint_void:
3433 case Intrinsic::experimental_patchpoint:
3434 visitPatchpoint(CB: I, EHPadBB);
3435 break;
3436 case Intrinsic::experimental_gc_statepoint:
3437 LowerStatepoint(I: cast<GCStatepointInst>(Val: I), EHPadBB);
3438 break;
3439 // wasm_throw, wasm_rethrow: This is usually done in visitTargetIntrinsic,
3440 // but these intrinsics are special because they can be invoked, so we
3441 // manually lower it to a DAG node here.
3442 case Intrinsic::wasm_throw: {
3443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3444 std::array<SDValue, 4> Ops = {
3445 getControlRoot(), // inchain for the terminator node
3446 DAG.getTargetConstant(Val: Intrinsic::wasm_throw, DL: getCurSDLoc(),
3447 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
3448 getValue(V: I.getArgOperand(i: 0)), // tag
3449 getValue(V: I.getArgOperand(i: 1)) // thrown value
3450 };
3451 SDVTList VTs = DAG.getVTList(VTs: ArrayRef<EVT>({MVT::Other})); // outchain
3452 DAG.setRoot(DAG.getNode(Opcode: ISD::INTRINSIC_VOID, DL: getCurSDLoc(), VTList: VTs, Ops));
3453 break;
3454 }
3455 case Intrinsic::wasm_rethrow: {
3456 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3457 std::array<SDValue, 2> Ops = {
3458 getControlRoot(), // inchain for the terminator node
3459 DAG.getTargetConstant(Val: Intrinsic::wasm_rethrow, DL: getCurSDLoc(),
3460 VT: TLI.getPointerTy(DL: DAG.getDataLayout()))};
3461 SDVTList VTs = DAG.getVTList(VTs: ArrayRef<EVT>({MVT::Other})); // outchain
3462 DAG.setRoot(DAG.getNode(Opcode: ISD::INTRINSIC_VOID, DL: getCurSDLoc(), VTList: VTs, Ops));
3463 break;
3464 }
3465 }
3466 } else if (I.hasDeoptState()) {
3467 // Currently we do not lower any intrinsic calls with deopt operand bundles.
3468 // Eventually we will support lowering the @llvm.experimental.deoptimize
3469 // intrinsic, and right now there are no plans to support other intrinsics
3470 // with deopt state.
3471 LowerCallSiteWithDeoptBundle(Call: &I, Callee: getValue(V: Callee), EHPadBB);
3472 } else if (I.countOperandBundlesOfType(ID: LLVMContext::OB_ptrauth)) {
3473 LowerCallSiteWithPtrAuthBundle(CB: cast<CallBase>(Val: I), EHPadBB);
3474 } else {
3475 LowerCallTo(CB: I, Callee: getValue(V: Callee), IsTailCall: false, IsMustTailCall: false, EHPadBB);
3476 }
3477
3478 // If the value of the invoke is used outside of its defining block, make it
3479 // available as a virtual register.
3480 // We already took care of the exported value for the statepoint instruction
3481 // during call to the LowerStatepoint.
3482 if (!isa<GCStatepointInst>(Val: I)) {
3483 CopyToExportRegsIfNeeded(V: &I);
3484 }
3485
3486 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
3487 BranchProbabilityInfo *BPI = FuncInfo.BPI;
3488 BranchProbability EHPadBBProb =
3489 BPI ? BPI->getEdgeProbability(Src: InvokeMBB->getBasicBlock(), Dst: EHPadBB)
3490 : BranchProbability::getZero();
3491 findUnwindDestinations(FuncInfo, EHPadBB, Prob: EHPadBBProb, UnwindDests);
3492
3493 // Update successor info.
3494 addSuccessorWithProb(Src: InvokeMBB, Dst: Return);
3495 for (auto &UnwindDest : UnwindDests) {
3496 UnwindDest.first->setIsEHPad();
3497 addSuccessorWithProb(Src: InvokeMBB, Dst: UnwindDest.first, Prob: UnwindDest.second);
3498 }
3499 InvokeMBB->normalizeSuccProbs();
3500
3501 // Drop into normal successor.
3502 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(), VT: MVT::Other, N1: getControlRoot(),
3503 N2: DAG.getBasicBlock(MBB: Return)));
3504}
3505
3506/// The intrinsics currently supported by callbr are implicit control flow
3507/// intrinsics such as amdgcn.kill.
3508/// - they should be called (no "dontcall-" attributes)
3509/// - they do not touch memory on the target (= !TLI.getTgtMemIntrinsic())
3510/// - they do not need custom argument handling (no
3511/// TLI.CollectTargetIntrinsicOperands())
3512void SelectionDAGBuilder::visitCallBrIntrinsic(const CallBrInst &I) {
3513#ifndef NDEBUG
3514 SmallVector<TargetLowering::IntrinsicInfo, 2> Infos;
3515 DAG.getTargetLoweringInfo().getTgtMemIntrinsic(
3516 Infos, I, DAG.getMachineFunction(), I.getIntrinsicID());
3517 assert(Infos.empty() && "Intrinsic touches memory");
3518#endif
3519
3520 auto [HasChain, OnlyLoad] = getTargetIntrinsicCallProperties(I);
3521
3522 SmallVector<SDValue, 8> Ops =
3523 getTargetIntrinsicOperands(I, HasChain, OnlyLoad);
3524 SDVTList VTs = getTargetIntrinsicVTList(I, HasChain);
3525
3526 // Create the node.
3527 SDValue Result =
3528 getTargetNonMemIntrinsicNode(IntrinsicVT: *I.getType(), HasChain, Ops, VTs);
3529 Result = handleTargetIntrinsicRet(I, HasChain, OnlyLoad, Result);
3530
3531 setValue(V: &I, NewN: Result);
3532}
3533
3534void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) {
3535 MachineBasicBlock *CallBrMBB = FuncInfo.MBB;
3536
3537 if (I.isInlineAsm()) {
3538 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
3539 // have to do anything here to lower funclet bundles.
3540 failForInvalidBundles(I, Name: "callbrs",
3541 AllowedBundles: {LLVMContext::OB_deopt, LLVMContext::OB_funclet});
3542 visitInlineAsm(Call: I);
3543 } else {
3544 assert(!I.hasOperandBundles() &&
3545 "Can't have operand bundles for intrinsics");
3546 visitCallBrIntrinsic(I);
3547 }
3548 CopyToExportRegsIfNeeded(V: &I);
3549
3550 // Retrieve successors.
3551 SmallPtrSet<BasicBlock *, 8> Dests;
3552 Dests.insert(Ptr: I.getDefaultDest());
3553 MachineBasicBlock *Return = FuncInfo.getMBB(BB: I.getDefaultDest());
3554
3555 // Update successor info.
3556 addSuccessorWithProb(Src: CallBrMBB, Dst: Return, Prob: BranchProbability::getOne());
3557 // TODO: For most of the cases where there is an intrinsic callbr, we're
3558 // having exactly one indirect target, which will be unreachable. As soon as
3559 // this changes, we might need to enhance
3560 // Target->setIsInlineAsmBrIndirectTarget or add something similar for
3561 // intrinsic indirect branches.
3562 if (I.isInlineAsm()) {
3563 for (BasicBlock *Dest : I.getIndirectDests()) {
3564 MachineBasicBlock *Target = FuncInfo.getMBB(BB: Dest);
3565 Target->setIsInlineAsmBrIndirectTarget();
3566 // If we introduce a type of asm goto statement that is permitted to use
3567 // an indirect call instruction to jump to its labels, then we should add
3568 // a call to Target->setMachineBlockAddressTaken() here, to mark the
3569 // target block as requiring a BTI.
3570
3571 Target->setLabelMustBeEmitted();
3572 // Don't add duplicate machine successors.
3573 if (Dests.insert(Ptr: Dest).second)
3574 addSuccessorWithProb(Src: CallBrMBB, Dst: Target, Prob: BranchProbability::getZero());
3575 }
3576 }
3577 CallBrMBB->normalizeSuccProbs();
3578
3579 // Drop into default successor.
3580 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(),
3581 VT: MVT::Other, N1: getControlRoot(),
3582 N2: DAG.getBasicBlock(MBB: Return)));
3583}
3584
3585void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
3586 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
3587}
3588
3589void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
3590 assert(FuncInfo.MBB->isEHPad() &&
3591 "Call to landingpad not in landing pad!");
3592
3593 // If there aren't registers to copy the values into (e.g., during SjLj
3594 // exceptions), then don't bother to create these DAG nodes.
3595 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3596 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
3597 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
3598 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
3599 return;
3600
3601 // If landingpad's return type is token type, we don't create DAG nodes
3602 // for its exception pointer and selector value. The extraction of exception
3603 // pointer or selector value from token type landingpads is not currently
3604 // supported.
3605 if (LP.getType()->isTokenTy())
3606 return;
3607
3608 SmallVector<EVT, 2> ValueVTs;
3609 SDLoc dl = getCurSDLoc();
3610 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: LP.getType(), ValueVTs);
3611 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
3612
3613 // Get the two live-in registers as SDValues. The physregs have already been
3614 // copied into virtual registers.
3615 SDValue Ops[2];
3616 if (FuncInfo.ExceptionPointerVirtReg) {
3617 Ops[0] = DAG.getZExtOrTrunc(
3618 Op: DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl,
3619 Reg: FuncInfo.ExceptionPointerVirtReg,
3620 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
3621 DL: dl, VT: ValueVTs[0]);
3622 } else {
3623 Ops[0] = DAG.getConstant(Val: 0, DL: dl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
3624 }
3625 Ops[1] = DAG.getZExtOrTrunc(
3626 Op: DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl,
3627 Reg: FuncInfo.ExceptionSelectorVirtReg,
3628 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
3629 DL: dl, VT: ValueVTs[1]);
3630
3631 // Merge into one.
3632 SDValue Res = DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: dl,
3633 VTList: DAG.getVTList(VTs: ValueVTs), Ops);
3634 setValue(V: &LP, NewN: Res);
3635}
3636
3637void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
3638 MachineBasicBlock *Last) {
3639 // Update JTCases.
3640 for (JumpTableBlock &JTB : SL->JTCases)
3641 if (JTB.first.HeaderBB == First)
3642 JTB.first.HeaderBB = Last;
3643
3644 // Update BitTestCases.
3645 for (BitTestBlock &BTB : SL->BitTestCases)
3646 if (BTB.Parent == First)
3647 BTB.Parent = Last;
3648}
3649
3650void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
3651 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
3652
3653 // Update machine-CFG edges with unique successors.
3654 SmallPtrSet<BasicBlock *, 32> Done;
3655 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
3656 BasicBlock *BB = I.getSuccessor(i);
3657 bool Inserted = Done.insert(Ptr: BB).second;
3658 if (!Inserted)
3659 continue;
3660
3661 MachineBasicBlock *Succ = FuncInfo.getMBB(BB);
3662 addSuccessorWithProb(Src: IndirectBrMBB, Dst: Succ);
3663 }
3664 IndirectBrMBB->normalizeSuccProbs();
3665
3666 DAG.setRoot(DAG.getNode(Opcode: ISD::BRIND, DL: getCurSDLoc(),
3667 VT: MVT::Other, N1: getControlRoot(),
3668 N2: getValue(V: I.getAddress())));
3669}
3670
3671void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
3672 if (!I.shouldLowerToTrap(TrapUnreachable: DAG.getTarget().Options.TrapUnreachable,
3673 NoTrapAfterNoreturn: DAG.getTarget().Options.NoTrapAfterNoreturn))
3674 return;
3675
3676 DAG.setRoot(DAG.getNode(Opcode: ISD::TRAP, DL: getCurSDLoc(), VT: MVT::Other, Operand: DAG.getRoot()));
3677}
3678
3679void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) {
3680 SDNodeFlags Flags;
3681 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
3682 Flags.copyFMF(FPMO: *FPOp);
3683
3684 SDValue Op = getValue(V: I.getOperand(i: 0));
3685 SDValue UnNodeValue = DAG.getNode(Opcode, DL: getCurSDLoc(), VT: Op.getValueType(),
3686 Operand: Op, Flags);
3687 setValue(V: &I, NewN: UnNodeValue);
3688}
3689
3690void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) {
3691 SDNodeFlags Flags;
3692 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(Val: &I)) {
3693 Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
3694 Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
3695 }
3696 if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(Val: &I))
3697 Flags.setExact(ExactOp->isExact());
3698 if (auto *DisjointOp = dyn_cast<PossiblyDisjointInst>(Val: &I))
3699 Flags.setDisjoint(DisjointOp->isDisjoint());
3700 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
3701 Flags.copyFMF(FPMO: *FPOp);
3702
3703 SDValue Op1 = getValue(V: I.getOperand(i: 0));
3704 SDValue Op2 = getValue(V: I.getOperand(i: 1));
3705 SDValue BinNodeValue = DAG.getNode(Opcode, DL: getCurSDLoc(), VT: Op1.getValueType(),
3706 N1: Op1, N2: Op2, Flags);
3707 setValue(V: &I, NewN: BinNodeValue);
3708}
3709
3710void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
3711 SDValue Op1 = getValue(V: I.getOperand(i: 0));
3712 SDValue Op2 = getValue(V: I.getOperand(i: 1));
3713
3714 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
3715 LHSTy: Op1.getValueType(), DL: DAG.getDataLayout());
3716
3717 // Coerce the shift amount to the right type if we can. This exposes the
3718 // truncate or zext to optimization early.
3719 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
3720 assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) &&
3721 "Unexpected shift type");
3722 Op2 = DAG.getZExtOrTrunc(Op: Op2, DL: getCurSDLoc(), VT: ShiftTy);
3723 }
3724
3725 bool nuw = false;
3726 bool nsw = false;
3727 bool exact = false;
3728
3729 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
3730
3731 if (const OverflowingBinaryOperator *OFBinOp =
3732 dyn_cast<const OverflowingBinaryOperator>(Val: &I)) {
3733 nuw = OFBinOp->hasNoUnsignedWrap();
3734 nsw = OFBinOp->hasNoSignedWrap();
3735 }
3736 if (const PossiblyExactOperator *ExactOp =
3737 dyn_cast<const PossiblyExactOperator>(Val: &I))
3738 exact = ExactOp->isExact();
3739 }
3740 SDNodeFlags Flags;
3741 Flags.setExact(exact);
3742 Flags.setNoSignedWrap(nsw);
3743 Flags.setNoUnsignedWrap(nuw);
3744 SDValue Res = DAG.getNode(Opcode, DL: getCurSDLoc(), VT: Op1.getValueType(), N1: Op1, N2: Op2,
3745 Flags);
3746 setValue(V: &I, NewN: Res);
3747}
3748
3749void SelectionDAGBuilder::visitSDiv(const User &I) {
3750 SDValue Op1 = getValue(V: I.getOperand(i: 0));
3751 SDValue Op2 = getValue(V: I.getOperand(i: 1));
3752
3753 SDNodeFlags Flags;
3754 Flags.setExact(isa<PossiblyExactOperator>(Val: &I) &&
3755 cast<PossiblyExactOperator>(Val: &I)->isExact());
3756 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SDIV, DL: getCurSDLoc(), VT: Op1.getValueType(), N1: Op1,
3757 N2: Op2, Flags));
3758}
3759
3760void SelectionDAGBuilder::visitICmp(const ICmpInst &I) {
3761 ICmpInst::Predicate predicate = I.getPredicate();
3762 SDValue Op1 = getValue(V: I.getOperand(i_nocapture: 0));
3763 SDValue Op2 = getValue(V: I.getOperand(i_nocapture: 1));
3764 ISD::CondCode Opcode = getICmpCondCode(Pred: predicate);
3765
3766 auto &TLI = DAG.getTargetLoweringInfo();
3767 EVT MemVT =
3768 TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getOperand(i_nocapture: 0)->getType());
3769
3770 // If a pointer's DAG type is larger than its memory type then the DAG values
3771 // are zero-extended. This breaks signed comparisons so truncate back to the
3772 // underlying type before doing the compare.
3773 if (Op1.getValueType() != MemVT) {
3774 Op1 = DAG.getPtrExtOrTrunc(Op: Op1, DL: getCurSDLoc(), VT: MemVT);
3775 Op2 = DAG.getPtrExtOrTrunc(Op: Op2, DL: getCurSDLoc(), VT: MemVT);
3776 }
3777
3778 SDNodeFlags Flags;
3779 Flags.setSameSign(I.hasSameSign());
3780 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
3781
3782 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
3783 Ty: I.getType());
3784 setValue(V: &I, NewN: DAG.getSetCC(DL: getCurSDLoc(), VT: DestVT, LHS: Op1, RHS: Op2, Cond: Opcode));
3785}
3786
3787void SelectionDAGBuilder::visitFCmp(const FCmpInst &I) {
3788 FCmpInst::Predicate predicate = I.getPredicate();
3789 SDValue Op1 = getValue(V: I.getOperand(i_nocapture: 0));
3790 SDValue Op2 = getValue(V: I.getOperand(i_nocapture: 1));
3791
3792 ISD::CondCode Condition = getFCmpCondCode(Pred: predicate);
3793 auto *FPMO = cast<FPMathOperator>(Val: &I);
3794 if (FPMO->hasNoNaNs() ||
3795 (DAG.isKnownNeverNaN(Op: Op1) && DAG.isKnownNeverNaN(Op: Op2)))
3796 Condition = getFCmpCodeWithoutNaN(CC: Condition);
3797
3798 SDNodeFlags Flags;
3799 Flags.copyFMF(FPMO: *FPMO);
3800 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
3801
3802 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
3803 Ty: I.getType());
3804 setValue(V: &I, NewN: DAG.getSetCC(DL: getCurSDLoc(), VT: DestVT, LHS: Op1, RHS: Op2, Cond: Condition,
3805 /*Chian=*/Chain: {}, /*IsSignaling=*/false, Flags));
3806}
3807
3808// Check if the condition of the select has one use or two users that are both
3809// selects with the same condition.
3810static bool hasOnlySelectUsers(const Value *Cond) {
3811 return llvm::all_of(Range: Cond->users(), P: [](const Value *V) {
3812 return isa<SelectInst>(Val: V);
3813 });
3814}
3815
3816void SelectionDAGBuilder::visitSelect(const User &I) {
3817 SmallVector<EVT, 4> ValueVTs;
3818 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(), Ty: I.getType(),
3819 ValueVTs);
3820 unsigned NumValues = ValueVTs.size();
3821 if (NumValues == 0) return;
3822
3823 SmallVector<SDValue, 4> Values(NumValues);
3824 SDValue Cond = getValue(V: I.getOperand(i: 0));
3825 SDValue LHSVal = getValue(V: I.getOperand(i: 1));
3826 SDValue RHSVal = getValue(V: I.getOperand(i: 2));
3827 SmallVector<SDValue, 1> BaseOps(1, Cond);
3828 ISD::NodeType OpCode =
3829 Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
3830
3831 bool IsUnaryAbs = false;
3832 bool Negate = false;
3833
3834 SDNodeFlags Flags;
3835 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
3836 Flags.copyFMF(FPMO: *FPOp);
3837
3838 Flags.setUnpredictable(
3839 cast<SelectInst>(Val: I).getMetadata(KindID: LLVMContext::MD_unpredictable));
3840
3841 // Min/max matching is only viable if all output VTs are the same.
3842 if (all_equal(Range&: ValueVTs)) {
3843 EVT VT = ValueVTs[0];
3844 LLVMContext &Ctx = *DAG.getContext();
3845 auto &TLI = DAG.getTargetLoweringInfo();
3846
3847 // We care about the legality of the operation after it has been type
3848 // legalized.
3849 while (TLI.getTypeAction(Context&: Ctx, VT) != TargetLoweringBase::TypeLegal)
3850 VT = TLI.getTypeToTransformTo(Context&: Ctx, VT);
3851
3852 // If the vselect is legal, assume we want to leave this as a vector setcc +
3853 // vselect. Otherwise, if this is going to be scalarized, we want to see if
3854 // min/max is legal on the scalar type.
3855 bool UseScalarMinMax = VT.isVector() &&
3856 !TLI.isOperationLegalOrCustom(Op: ISD::VSELECT, VT);
3857
3858 // ValueTracking's select pattern matching does not account for -0.0,
3859 // so we can't lower to FMINIMUM/FMAXIMUM because those nodes specify that
3860 // -0.0 is less than +0.0.
3861 const Value *LHS, *RHS;
3862 auto SPR = matchSelectPattern(V: &I, LHS, RHS);
3863 ISD::NodeType Opc = ISD::DELETED_NODE;
3864 switch (SPR.Flavor) {
3865 case SPF_UMAX: Opc = ISD::UMAX; break;
3866 case SPF_UMIN: Opc = ISD::UMIN; break;
3867 case SPF_SMAX: Opc = ISD::SMAX; break;
3868 case SPF_SMIN: Opc = ISD::SMIN; break;
3869 case SPF_FMINNUM:
3870 if (!TLI.isProfitableToCombineMinNumMaxNum(VT))
3871 break;
3872
3873 switch (SPR.NaNBehavior) {
3874 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3875 case SPNB_RETURNS_NAN: break;
3876 case SPNB_RETURNS_OTHER:
3877 Opc = ISD::FMINIMUMNUM;
3878 Flags.setNoSignedZeros(true);
3879 break;
3880 case SPNB_RETURNS_ANY:
3881 if (TLI.isOperationLegalOrCustom(Op: ISD::FMINNUM, VT) ||
3882 (UseScalarMinMax &&
3883 TLI.isOperationLegalOrCustom(Op: ISD::FMINNUM, VT: VT.getScalarType())))
3884 Opc = ISD::FMINNUM;
3885 break;
3886 }
3887 break;
3888 case SPF_FMAXNUM:
3889 if (!TLI.isProfitableToCombineMinNumMaxNum(VT))
3890 break;
3891
3892 switch (SPR.NaNBehavior) {
3893 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3894 case SPNB_RETURNS_NAN: break;
3895 case SPNB_RETURNS_OTHER:
3896 Opc = ISD::FMAXIMUMNUM;
3897 Flags.setNoSignedZeros(true);
3898 break;
3899 case SPNB_RETURNS_ANY:
3900 if (TLI.isOperationLegalOrCustom(Op: ISD::FMAXNUM, VT) ||
3901 (UseScalarMinMax &&
3902 TLI.isOperationLegalOrCustom(Op: ISD::FMAXNUM, VT: VT.getScalarType())))
3903 Opc = ISD::FMAXNUM;
3904 break;
3905 }
3906 break;
3907 case SPF_NABS:
3908 Negate = true;
3909 [[fallthrough]];
3910 case SPF_ABS:
3911 IsUnaryAbs = true;
3912 Opc = ISD::ABS;
3913 break;
3914 default: break;
3915 }
3916
3917 if (!IsUnaryAbs && Opc != ISD::DELETED_NODE &&
3918 (TLI.isOperationLegalOrCustom(Op: Opc, VT) ||
3919 (UseScalarMinMax &&
3920 TLI.isOperationLegalOrCustom(Op: Opc, VT: VT.getScalarType()))) &&
3921 // If the underlying comparison instruction is used by any other
3922 // instruction, the consumed instructions won't be destroyed, so it is
3923 // not profitable to convert to a min/max.
3924 hasOnlySelectUsers(Cond: cast<SelectInst>(Val: I).getCondition())) {
3925 OpCode = Opc;
3926 LHSVal = getValue(V: LHS);
3927 RHSVal = getValue(V: RHS);
3928 BaseOps.clear();
3929 }
3930
3931 if (IsUnaryAbs) {
3932 OpCode = Opc;
3933 LHSVal = getValue(V: LHS);
3934 BaseOps.clear();
3935 }
3936 }
3937
3938 if (IsUnaryAbs) {
3939 for (unsigned i = 0; i != NumValues; ++i) {
3940 SDLoc dl = getCurSDLoc();
3941 EVT VT = LHSVal.getNode()->getValueType(ResNo: LHSVal.getResNo() + i);
3942 Values[i] =
3943 DAG.getNode(Opcode: OpCode, DL: dl, VT, Operand: LHSVal.getValue(R: LHSVal.getResNo() + i));
3944 if (Negate)
3945 Values[i] = DAG.getNegative(Val: Values[i], DL: dl, VT);
3946 }
3947 } else {
3948 for (unsigned i = 0; i != NumValues; ++i) {
3949 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
3950 Ops.push_back(Elt: SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3951 Ops.push_back(Elt: SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
3952 Values[i] = DAG.getNode(
3953 Opcode: OpCode, DL: getCurSDLoc(),
3954 VT: LHSVal.getNode()->getValueType(ResNo: LHSVal.getResNo() + i), Ops, Flags);
3955 }
3956 }
3957
3958 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
3959 VTList: DAG.getVTList(VTs: ValueVTs), Ops: Values));
3960}
3961
3962void SelectionDAGBuilder::visitTrunc(const User &I) {
3963 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3964 SDValue N = getValue(V: I.getOperand(i: 0));
3965 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
3966 Ty: I.getType());
3967 SDNodeFlags Flags;
3968 if (auto *Trunc = dyn_cast<TruncInst>(Val: &I)) {
3969 Flags.setNoSignedWrap(Trunc->hasNoSignedWrap());
3970 Flags.setNoUnsignedWrap(Trunc->hasNoUnsignedWrap());
3971 }
3972
3973 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::TRUNCATE, DL: getCurSDLoc(), VT: DestVT, Operand: N, Flags));
3974}
3975
3976void SelectionDAGBuilder::visitZExt(const User &I) {
3977 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3978 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3979 SDValue N = getValue(V: I.getOperand(i: 0));
3980 auto &TLI = DAG.getTargetLoweringInfo();
3981 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
3982
3983 SDNodeFlags Flags;
3984 if (auto *PNI = dyn_cast<PossiblyNonNegInst>(Val: &I))
3985 Flags.setNonNeg(PNI->hasNonNeg());
3986
3987 // Eagerly use nonneg information to canonicalize towards sign_extend if
3988 // that is the target's preference.
3989 // TODO: Let the target do this later.
3990 if (Flags.hasNonNeg() &&
3991 TLI.isSExtCheaperThanZExt(FromTy: N.getValueType(), ToTy: DestVT)) {
3992 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: getCurSDLoc(), VT: DestVT, Operand: N));
3993 return;
3994 }
3995
3996 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: getCurSDLoc(), VT: DestVT, Operand: N, Flags));
3997}
3998
3999void SelectionDAGBuilder::visitSExt(const User &I) {
4000 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
4001 // SExt also can't be a cast to bool for same reason. So, nothing much to do
4002 SDValue N = getValue(V: I.getOperand(i: 0));
4003 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4004 Ty: I.getType());
4005 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: getCurSDLoc(), VT: DestVT, Operand: N));
4006}
4007
4008void SelectionDAGBuilder::visitFPTrunc(const User &I) {
4009 // FPTrunc is never a no-op cast, no need to check
4010 SDValue N = getValue(V: I.getOperand(i: 0));
4011 SDLoc dl = getCurSDLoc();
4012 SDNodeFlags Flags;
4013 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
4014 Flags.copyFMF(FPMO: *FPOp);
4015 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4016 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4017 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: DestVT, N1: N,
4018 N2: DAG.getTargetConstant(
4019 Val: 0, DL: dl, VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
4020 Flags));
4021}
4022
4023void SelectionDAGBuilder::visitFPExt(const User &I) {
4024 // FPExt is never a no-op cast, no need to check
4025 SDValue N = getValue(V: I.getOperand(i: 0));
4026 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4027 Ty: I.getType());
4028 SDNodeFlags Flags;
4029 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
4030 Flags.copyFMF(FPMO: *FPOp);
4031 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_EXTEND, DL: getCurSDLoc(), VT: DestVT, Operand: N, Flags));
4032}
4033
4034void SelectionDAGBuilder::visitFPToUI(const User &I) {
4035 // FPToUI is never a no-op cast, no need to check
4036 SDValue N = getValue(V: I.getOperand(i: 0));
4037 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4038 Ty: I.getType());
4039 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_TO_UINT, DL: getCurSDLoc(), VT: DestVT, Operand: N));
4040}
4041
4042void SelectionDAGBuilder::visitFPToSI(const User &I) {
4043 // FPToSI is never a no-op cast, no need to check
4044 SDValue N = getValue(V: I.getOperand(i: 0));
4045 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4046 Ty: I.getType());
4047 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_TO_SINT, DL: getCurSDLoc(), VT: DestVT, Operand: N));
4048}
4049
4050void SelectionDAGBuilder::visitUIToFP(const User &I) {
4051 // UIToFP is never a no-op cast, no need to check
4052 SDValue N = getValue(V: I.getOperand(i: 0));
4053 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4054 Ty: I.getType());
4055 SDNodeFlags Flags;
4056 if (auto *PNI = dyn_cast<PossiblyNonNegInst>(Val: &I))
4057 Flags.setNonNeg(PNI->hasNonNeg());
4058
4059 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UINT_TO_FP, DL: getCurSDLoc(), VT: DestVT, Operand: N, Flags));
4060}
4061
4062void SelectionDAGBuilder::visitSIToFP(const User &I) {
4063 // SIToFP is never a no-op cast, no need to check
4064 SDValue N = getValue(V: I.getOperand(i: 0));
4065 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4066 Ty: I.getType());
4067 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: getCurSDLoc(), VT: DestVT, Operand: N));
4068}
4069
4070void SelectionDAGBuilder::visitPtrToAddr(const User &I) {
4071 SDValue N = getValue(V: I.getOperand(i: 0));
4072 // By definition the type of the ptrtoaddr must be equal to the address type.
4073 const auto &TLI = DAG.getTargetLoweringInfo();
4074 EVT AddrVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4075 // The address width must be smaller or equal to the pointer representation
4076 // width, so we lower ptrtoaddr as a truncate (possibly folded to a no-op).
4077 N = DAG.getNode(Opcode: ISD::TRUNCATE, DL: getCurSDLoc(), VT: AddrVT, Operand: N);
4078 setValue(V: &I, NewN: N);
4079}
4080
4081void SelectionDAGBuilder::visitPtrToInt(const User &I) {
4082 // What to do depends on the size of the integer and the size of the pointer.
4083 // We can either truncate, zero extend, or no-op, accordingly.
4084 SDValue N = getValue(V: I.getOperand(i: 0));
4085 auto &TLI = DAG.getTargetLoweringInfo();
4086 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4087 Ty: I.getType());
4088 EVT PtrMemVT =
4089 TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getOperand(i: 0)->getType());
4090 N = DAG.getPtrExtOrTrunc(Op: N, DL: getCurSDLoc(), VT: PtrMemVT);
4091 N = DAG.getZExtOrTrunc(Op: N, DL: getCurSDLoc(), VT: DestVT);
4092 setValue(V: &I, NewN: N);
4093}
4094
4095void SelectionDAGBuilder::visitIntToPtr(const User &I) {
4096 // What to do depends on the size of the integer and the size of the pointer.
4097 // We can either truncate, zero extend, or no-op, accordingly.
4098 SDValue N = getValue(V: I.getOperand(i: 0));
4099 auto &TLI = DAG.getTargetLoweringInfo();
4100 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4101 EVT PtrMemVT = TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4102 N = DAG.getZExtOrTrunc(Op: N, DL: getCurSDLoc(), VT: PtrMemVT);
4103 N = DAG.getPtrExtOrTrunc(Op: N, DL: getCurSDLoc(), VT: DestVT);
4104 setValue(V: &I, NewN: N);
4105}
4106
4107void SelectionDAGBuilder::visitBitCast(const User &I) {
4108 SDValue N = getValue(V: I.getOperand(i: 0));
4109 SDLoc dl = getCurSDLoc();
4110 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
4111 Ty: I.getType());
4112
4113 // BitCast assures us that source and destination are the same size so this is
4114 // either a BITCAST or a no-op.
4115 if (DestVT != N.getValueType())
4116 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::BITCAST, DL: dl,
4117 VT: DestVT, Operand: N)); // convert types.
4118 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
4119 // might fold any kind of constant expression to an integer constant and that
4120 // is not what we are looking for. Only recognize a bitcast of a genuine
4121 // constant integer as an opaque constant.
4122 else if(ConstantInt *C = dyn_cast<ConstantInt>(Val: I.getOperand(i: 0)))
4123 setValue(V: &I, NewN: DAG.getConstant(Val: C->getValue(), DL: dl, VT: DestVT, /*isTarget=*/false,
4124 /*isOpaque*/true));
4125 else
4126 setValue(V: &I, NewN: N); // noop cast.
4127}
4128
4129void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
4130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4131 const Value *SV = I.getOperand(i: 0);
4132 SDValue N = getValue(V: SV);
4133 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4134
4135 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
4136 unsigned DestAS = I.getType()->getPointerAddressSpace();
4137
4138 if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS))
4139 N = DAG.getAddrSpaceCast(dl: getCurSDLoc(), VT: DestVT, Ptr: N, SrcAS, DestAS);
4140
4141 setValue(V: &I, NewN: N);
4142}
4143
4144void SelectionDAGBuilder::visitInsertElement(const User &I) {
4145 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4146 SDValue InVec = getValue(V: I.getOperand(i: 0));
4147 SDValue InVal = getValue(V: I.getOperand(i: 1));
4148 SDValue InIdx = DAG.getZExtOrTrunc(Op: getValue(V: I.getOperand(i: 2)), DL: getCurSDLoc(),
4149 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
4150 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: getCurSDLoc(),
4151 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
4152 N1: InVec, N2: InVal, N3: InIdx));
4153}
4154
4155void SelectionDAGBuilder::visitExtractElement(const User &I) {
4156 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4157 SDValue InVec = getValue(V: I.getOperand(i: 0));
4158 SDValue InIdx = DAG.getZExtOrTrunc(Op: getValue(V: I.getOperand(i: 1)), DL: getCurSDLoc(),
4159 VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
4160 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: getCurSDLoc(),
4161 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
4162 N1: InVec, N2: InIdx));
4163}
4164
4165void SelectionDAGBuilder::visitShuffleVector(const User &I) {
4166 SDValue Src1 = getValue(V: I.getOperand(i: 0));
4167 SDValue Src2 = getValue(V: I.getOperand(i: 1));
4168 ArrayRef<int> Mask;
4169 if (auto *SVI = dyn_cast<ShuffleVectorInst>(Val: &I))
4170 Mask = SVI->getShuffleMask();
4171 else
4172 Mask = cast<ConstantExpr>(Val: I).getShuffleMask();
4173 SDLoc DL = getCurSDLoc();
4174 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4175 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
4176 EVT SrcVT = Src1.getValueType();
4177
4178 if (all_of(Range&: Mask, P: equal_to(Arg: 0)) && VT.isScalableVector()) {
4179 // Canonical splat form of first element of first input vector.
4180 SDValue FirstElt =
4181 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: SrcVT.getScalarType(), N1: Src1,
4182 N2: DAG.getVectorIdxConstant(Val: 0, DL));
4183 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SPLAT_VECTOR, DL, VT, Operand: FirstElt));
4184 return;
4185 }
4186
4187 // For now, we only handle splats for scalable vectors.
4188 // The DAGCombiner will perform a BUILD_VECTOR -> SPLAT_VECTOR transformation
4189 // for targets that support a SPLAT_VECTOR for non-scalable vector types.
4190 assert(!VT.isScalableVector() && "Unsupported scalable vector shuffle");
4191
4192 unsigned SrcNumElts = SrcVT.getVectorNumElements();
4193 unsigned MaskNumElts = Mask.size();
4194
4195 if (SrcNumElts == MaskNumElts) {
4196 setValue(V: &I, NewN: DAG.getVectorShuffle(VT, dl: DL, N1: Src1, N2: Src2, Mask));
4197 return;
4198 }
4199
4200 // Normalize the shuffle vector since mask and vector length don't match.
4201 if (SrcNumElts < MaskNumElts) {
4202 // Mask is longer than the source vectors. We can use concatenate vector to
4203 // make the mask and vectors lengths match.
4204
4205 if (MaskNumElts % SrcNumElts == 0) {
4206 // Mask length is a multiple of the source vector length.
4207 // Check if the shuffle is some kind of concatenation of the input
4208 // vectors.
4209 unsigned NumConcat = MaskNumElts / SrcNumElts;
4210 bool IsConcat = true;
4211 SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
4212 for (unsigned i = 0; i != MaskNumElts; ++i) {
4213 int Idx = Mask[i];
4214 if (Idx < 0)
4215 continue;
4216 // Ensure the indices in each SrcVT sized piece are sequential and that
4217 // the same source is used for the whole piece.
4218 if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
4219 (ConcatSrcs[i / SrcNumElts] >= 0 &&
4220 ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
4221 IsConcat = false;
4222 break;
4223 }
4224 // Remember which source this index came from.
4225 ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
4226 }
4227
4228 // The shuffle is concatenating multiple vectors together. Just emit
4229 // a CONCAT_VECTORS operation.
4230 if (IsConcat) {
4231 SmallVector<SDValue, 8> ConcatOps;
4232 for (auto Src : ConcatSrcs) {
4233 if (Src < 0)
4234 ConcatOps.push_back(Elt: DAG.getUNDEF(VT: SrcVT));
4235 else if (Src == 0)
4236 ConcatOps.push_back(Elt: Src1);
4237 else
4238 ConcatOps.push_back(Elt: Src2);
4239 }
4240 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT, Ops: ConcatOps));
4241 return;
4242 }
4243 }
4244
4245 unsigned PaddedMaskNumElts = alignTo(Value: MaskNumElts, Align: SrcNumElts);
4246 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
4247 EVT PaddedVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: VT.getScalarType(),
4248 NumElements: PaddedMaskNumElts);
4249
4250 // Pad both vectors with undefs to make them the same length as the mask.
4251 SDValue UndefVal = DAG.getUNDEF(VT: SrcVT);
4252
4253 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
4254 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
4255 MOps1[0] = Src1;
4256 MOps2[0] = Src2;
4257
4258 Src1 = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: PaddedVT, Ops: MOps1);
4259 Src2 = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: PaddedVT, Ops: MOps2);
4260
4261 // Readjust mask for new input vector length.
4262 SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
4263 for (unsigned i = 0; i != MaskNumElts; ++i) {
4264 int Idx = Mask[i];
4265 if (Idx >= (int)SrcNumElts)
4266 Idx -= SrcNumElts - PaddedMaskNumElts;
4267 MappedOps[i] = Idx;
4268 }
4269
4270 SDValue Result = DAG.getVectorShuffle(VT: PaddedVT, dl: DL, N1: Src1, N2: Src2, Mask: MappedOps);
4271
4272 // If the concatenated vector was padded, extract a subvector with the
4273 // correct number of elements.
4274 if (MaskNumElts != PaddedMaskNumElts)
4275 Result = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT, N1: Result,
4276 N2: DAG.getVectorIdxConstant(Val: 0, DL));
4277
4278 setValue(V: &I, NewN: Result);
4279 return;
4280 }
4281
4282 assert(SrcNumElts > MaskNumElts);
4283
4284 // Analyze the access pattern of the vector to see if we can extract
4285 // two subvectors and do the shuffle.
4286 int StartIdx[2] = {-1, -1}; // StartIdx to extract from
4287 bool CanExtract = true;
4288 for (int Idx : Mask) {
4289 unsigned Input = 0;
4290 if (Idx < 0)
4291 continue;
4292
4293 if (Idx >= (int)SrcNumElts) {
4294 Input = 1;
4295 Idx -= SrcNumElts;
4296 }
4297
4298 // If all the indices come from the same MaskNumElts sized portion of
4299 // the sources we can use extract. Also make sure the extract wouldn't
4300 // extract past the end of the source.
4301 int NewStartIdx = alignDown(Value: Idx, Align: MaskNumElts);
4302 if (NewStartIdx + MaskNumElts > SrcNumElts ||
4303 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
4304 CanExtract = false;
4305 // Make sure we always update StartIdx as we use it to track if all
4306 // elements are undef.
4307 StartIdx[Input] = NewStartIdx;
4308 }
4309
4310 if (StartIdx[0] < 0 && StartIdx[1] < 0) {
4311 setValue(V: &I, NewN: DAG.getUNDEF(VT)); // Vectors are not used.
4312 return;
4313 }
4314 if (CanExtract) {
4315 // Extract appropriate subvector and generate a vector shuffle
4316 for (unsigned Input = 0; Input < 2; ++Input) {
4317 SDValue &Src = Input == 0 ? Src1 : Src2;
4318 if (StartIdx[Input] < 0)
4319 Src = DAG.getUNDEF(VT);
4320 else {
4321 Src = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT, N1: Src,
4322 N2: DAG.getVectorIdxConstant(Val: StartIdx[Input], DL));
4323 }
4324 }
4325
4326 // Calculate new mask.
4327 SmallVector<int, 8> MappedOps(Mask);
4328 for (int &Idx : MappedOps) {
4329 if (Idx >= (int)SrcNumElts)
4330 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
4331 else if (Idx >= 0)
4332 Idx -= StartIdx[0];
4333 }
4334
4335 setValue(V: &I, NewN: DAG.getVectorShuffle(VT, dl: DL, N1: Src1, N2: Src2, Mask: MappedOps));
4336 return;
4337 }
4338
4339 // We can't use either concat vectors or extract subvectors so fall back to
4340 // replacing the shuffle with extract and build vector.
4341 // to insert and build vector.
4342 EVT EltVT = VT.getVectorElementType();
4343 SmallVector<SDValue,8> Ops;
4344 for (int Idx : Mask) {
4345 SDValue Res;
4346
4347 if (Idx < 0) {
4348 Res = DAG.getUNDEF(VT: EltVT);
4349 } else {
4350 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
4351 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
4352
4353 Res = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: EltVT, N1: Src,
4354 N2: DAG.getVectorIdxConstant(Val: Idx, DL));
4355 }
4356
4357 Ops.push_back(Elt: Res);
4358 }
4359
4360 setValue(V: &I, NewN: DAG.getBuildVector(VT, DL, Ops));
4361}
4362
4363void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
4364 ArrayRef<unsigned> Indices = I.getIndices();
4365 const Value *Op0 = I.getOperand(i_nocapture: 0);
4366 const Value *Op1 = I.getOperand(i_nocapture: 1);
4367 Type *AggTy = I.getType();
4368 Type *ValTy = Op1->getType();
4369 bool IntoUndef = isa<UndefValue>(Val: Op0);
4370 bool FromUndef = isa<UndefValue>(Val: Op1);
4371
4372 unsigned LinearIndex = ComputeLinearIndex(Ty: AggTy, Indices);
4373
4374 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4375 SmallVector<EVT, 4> AggValueVTs;
4376 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: AggTy, ValueVTs&: AggValueVTs);
4377 SmallVector<EVT, 4> ValValueVTs;
4378 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: ValTy, ValueVTs&: ValValueVTs);
4379
4380 unsigned NumAggValues = AggValueVTs.size();
4381 unsigned NumValValues = ValValueVTs.size();
4382 SmallVector<SDValue, 4> Values(NumAggValues);
4383
4384 // Ignore an insertvalue that produces an empty object
4385 if (!NumAggValues) {
4386 setValue(V: &I, NewN: DAG.getUNDEF(VT: MVT(MVT::Other)));
4387 return;
4388 }
4389
4390 SDValue Agg = getValue(V: Op0);
4391 unsigned i = 0;
4392 // Copy the beginning value(s) from the original aggregate.
4393 for (; i != LinearIndex; ++i)
4394 Values[i] = IntoUndef ? DAG.getUNDEF(VT: AggValueVTs[i]) :
4395 SDValue(Agg.getNode(), Agg.getResNo() + i);
4396 // Copy values from the inserted value(s).
4397 if (NumValValues) {
4398 SDValue Val = getValue(V: Op1);
4399 for (; i != LinearIndex + NumValValues; ++i)
4400 Values[i] = FromUndef ? DAG.getUNDEF(VT: AggValueVTs[i]) :
4401 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
4402 }
4403 // Copy remaining value(s) from the original aggregate.
4404 for (; i != NumAggValues; ++i)
4405 Values[i] = IntoUndef ? DAG.getUNDEF(VT: AggValueVTs[i]) :
4406 SDValue(Agg.getNode(), Agg.getResNo() + i);
4407
4408 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
4409 VTList: DAG.getVTList(VTs: AggValueVTs), Ops: Values));
4410}
4411
4412void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
4413 ArrayRef<unsigned> Indices = I.getIndices();
4414 const Value *Op0 = I.getOperand(i_nocapture: 0);
4415 Type *AggTy = Op0->getType();
4416 Type *ValTy = I.getType();
4417 bool OutOfUndef = isa<UndefValue>(Val: Op0);
4418
4419 unsigned LinearIndex = ComputeLinearIndex(Ty: AggTy, Indices);
4420
4421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4422 SmallVector<EVT, 4> ValValueVTs;
4423 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: ValTy, ValueVTs&: ValValueVTs);
4424
4425 unsigned NumValValues = ValValueVTs.size();
4426
4427 // Ignore a extractvalue that produces an empty object
4428 if (!NumValValues) {
4429 setValue(V: &I, NewN: DAG.getUNDEF(VT: MVT(MVT::Other)));
4430 return;
4431 }
4432
4433 SmallVector<SDValue, 4> Values(NumValValues);
4434
4435 SDValue Agg = getValue(V: Op0);
4436 // Copy out the selected value(s).
4437 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
4438 Values[i - LinearIndex] =
4439 OutOfUndef ?
4440 DAG.getUNDEF(VT: Agg.getNode()->getValueType(ResNo: Agg.getResNo() + i)) :
4441 SDValue(Agg.getNode(), Agg.getResNo() + i);
4442
4443 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
4444 VTList: DAG.getVTList(VTs: ValValueVTs), Ops: Values));
4445}
4446
4447void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
4448 Value *Op0 = I.getOperand(i: 0);
4449 // Note that the pointer operand may be a vector of pointers. Take the scalar
4450 // element which holds a pointer.
4451 unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
4452 SDValue N = getValue(V: Op0);
4453 SDLoc dl = getCurSDLoc();
4454 auto &TLI = DAG.getTargetLoweringInfo();
4455 GEPNoWrapFlags NW = cast<GEPOperator>(Val: I).getNoWrapFlags();
4456
4457 // For a vector GEP, keep the prefix scalar as long as possible, then
4458 // convert any scalars encountered after the first vector operand to vectors.
4459 bool IsVectorGEP = I.getType()->isVectorTy();
4460 ElementCount VectorElementCount =
4461 IsVectorGEP ? cast<VectorType>(Val: I.getType())->getElementCount()
4462 : ElementCount::getFixed(MinVal: 0);
4463
4464 for (gep_type_iterator GTI = gep_type_begin(GEP: &I), E = gep_type_end(GEP: &I);
4465 GTI != E; ++GTI) {
4466 const Value *Idx = GTI.getOperand();
4467 if (StructType *StTy = GTI.getStructTypeOrNull()) {
4468 unsigned Field = cast<Constant>(Val: Idx)->getUniqueInteger().getZExtValue();
4469 if (Field) {
4470 // N = N + Offset
4471 uint64_t Offset =
4472 DAG.getDataLayout().getStructLayout(Ty: StTy)->getElementOffset(Idx: Field);
4473
4474 // In an inbounds GEP with an offset that is nonnegative even when
4475 // interpreted as signed, assume there is no unsigned overflow.
4476 SDNodeFlags Flags;
4477 if (NW.hasNoUnsignedWrap() ||
4478 (int64_t(Offset) >= 0 && NW.hasNoUnsignedSignedWrap()))
4479 Flags |= SDNodeFlags::NoUnsignedWrap;
4480 Flags.setInBounds(NW.isInBounds());
4481
4482 N = DAG.getMemBasePlusOffset(
4483 Base: N, Offset: DAG.getConstant(Val: Offset, DL: dl, VT: N.getValueType()), DL: dl, Flags);
4484 }
4485 } else {
4486 // IdxSize is the width of the arithmetic according to IR semantics.
4487 // In SelectionDAG, we may prefer to do arithmetic in a wider bitwidth
4488 // (and fix up the result later).
4489 unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS);
4490 MVT IdxTy = MVT::getIntegerVT(BitWidth: IdxSize);
4491 TypeSize ElementSize =
4492 GTI.getSequentialElementStride(DL: DAG.getDataLayout());
4493 // We intentionally mask away the high bits here; ElementSize may not
4494 // fit in IdxTy.
4495 APInt ElementMul(IdxSize, ElementSize.getKnownMinValue(),
4496 /*isSigned=*/false, /*implicitTrunc=*/true);
4497 bool ElementScalable = ElementSize.isScalable();
4498
4499 // If this is a scalar constant or a splat vector of constants,
4500 // handle it quickly.
4501 const auto *C = dyn_cast<Constant>(Val: Idx);
4502 if (C && isa<VectorType>(Val: C->getType()))
4503 C = C->getSplatValue();
4504
4505 const auto *CI = dyn_cast_or_null<ConstantInt>(Val: C);
4506 if (CI && CI->isZero())
4507 continue;
4508 if (CI && !ElementScalable) {
4509 APInt Offs = ElementMul * CI->getValue().sextOrTrunc(width: IdxSize);
4510 LLVMContext &Context = *DAG.getContext();
4511 SDValue OffsVal;
4512 if (N.getValueType().isVector())
4513 OffsVal = DAG.getConstant(
4514 Val: Offs, DL: dl, VT: EVT::getVectorVT(Context, VT: IdxTy, EC: VectorElementCount));
4515 else
4516 OffsVal = DAG.getConstant(Val: Offs, DL: dl, VT: IdxTy);
4517
4518 // In an inbounds GEP with an offset that is nonnegative even when
4519 // interpreted as signed, assume there is no unsigned overflow.
4520 SDNodeFlags Flags;
4521 if (NW.hasNoUnsignedWrap() ||
4522 (Offs.isNonNegative() && NW.hasNoUnsignedSignedWrap()))
4523 Flags.setNoUnsignedWrap(true);
4524 Flags.setInBounds(NW.isInBounds());
4525
4526 OffsVal = DAG.getSExtOrTrunc(Op: OffsVal, DL: dl, VT: N.getValueType());
4527
4528 N = DAG.getMemBasePlusOffset(Base: N, Offset: OffsVal, DL: dl, Flags);
4529 continue;
4530 }
4531
4532 // N = N + Idx * ElementMul;
4533 SDValue IdxN = getValue(V: Idx);
4534
4535 if (IdxN.getValueType().isVector() != N.getValueType().isVector()) {
4536 if (N.getValueType().isVector()) {
4537 EVT VT = EVT::getVectorVT(Context&: *Context, VT: IdxN.getValueType(),
4538 EC: VectorElementCount);
4539 IdxN = DAG.getSplat(VT, DL: dl, Op: IdxN);
4540 } else {
4541 EVT VT =
4542 EVT::getVectorVT(Context&: *Context, VT: N.getValueType(), EC: VectorElementCount);
4543 N = DAG.getSplat(VT, DL: dl, Op: N);
4544 }
4545 }
4546
4547 // If the index is smaller or larger than intptr_t, truncate or extend
4548 // it.
4549 IdxN = DAG.getSExtOrTrunc(Op: IdxN, DL: dl, VT: N.getValueType());
4550
4551 SDNodeFlags ScaleFlags;
4552 // The multiplication of an index by the type size does not wrap the
4553 // pointer index type in a signed sense (mul nsw).
4554 ScaleFlags.setNoSignedWrap(NW.hasNoUnsignedSignedWrap());
4555
4556 // The multiplication of an index by the type size does not wrap the
4557 // pointer index type in an unsigned sense (mul nuw).
4558 ScaleFlags.setNoUnsignedWrap(NW.hasNoUnsignedWrap());
4559
4560 if (ElementScalable) {
4561 EVT VScaleTy = N.getValueType().getScalarType();
4562 SDValue VScale = DAG.getNode(
4563 Opcode: ISD::VSCALE, DL: dl, VT: VScaleTy,
4564 Operand: DAG.getConstant(Val: ElementMul.getZExtValue(), DL: dl, VT: VScaleTy));
4565 if (N.getValueType().isVector())
4566 VScale = DAG.getSplatVector(VT: N.getValueType(), DL: dl, Op: VScale);
4567 IdxN = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: N.getValueType(), N1: IdxN, N2: VScale,
4568 Flags: ScaleFlags);
4569 } else {
4570 // If this is a multiply by a power of two, turn it into a shl
4571 // immediately. This is a very common case.
4572 if (ElementMul != 1) {
4573 if (ElementMul.isPowerOf2()) {
4574 unsigned Amt = ElementMul.logBase2();
4575 IdxN = DAG.getNode(
4576 Opcode: ISD::SHL, DL: dl, VT: N.getValueType(), N1: IdxN,
4577 N2: DAG.getShiftAmountConstant(Val: Amt, VT: N.getValueType(), DL: dl),
4578 Flags: ScaleFlags);
4579 } else {
4580 SDValue Scale = DAG.getConstant(Val: ElementMul.getZExtValue(), DL: dl,
4581 VT: IdxN.getValueType());
4582 IdxN = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: N.getValueType(), N1: IdxN, N2: Scale,
4583 Flags: ScaleFlags);
4584 }
4585 }
4586 }
4587
4588 // The successive addition of the current address, truncated to the
4589 // pointer index type and interpreted as an unsigned number, and each
4590 // offset, also interpreted as an unsigned number, does not wrap the
4591 // pointer index type (add nuw).
4592 SDNodeFlags AddFlags;
4593 AddFlags.setNoUnsignedWrap(NW.hasNoUnsignedWrap());
4594 AddFlags.setInBounds(NW.isInBounds());
4595
4596 N = DAG.getMemBasePlusOffset(Base: N, Offset: IdxN, DL: dl, Flags: AddFlags);
4597 }
4598 }
4599
4600 if (IsVectorGEP && !N.getValueType().isVector()) {
4601 EVT VT = EVT::getVectorVT(Context&: *Context, VT: N.getValueType(), EC: VectorElementCount);
4602 N = DAG.getSplat(VT, DL: dl, Op: N);
4603 }
4604
4605 MVT PtrTy = TLI.getPointerTy(DL: DAG.getDataLayout(), AS);
4606 MVT PtrMemTy = TLI.getPointerMemTy(DL: DAG.getDataLayout(), AS);
4607 if (IsVectorGEP) {
4608 PtrTy = MVT::getVectorVT(VT: PtrTy, EC: VectorElementCount);
4609 PtrMemTy = MVT::getVectorVT(VT: PtrMemTy, EC: VectorElementCount);
4610 }
4611
4612 if (PtrMemTy != PtrTy && !cast<GEPOperator>(Val: I).isInBounds())
4613 N = DAG.getPtrExtendInReg(Op: N, DL: dl, VT: PtrMemTy);
4614
4615 setValue(V: &I, NewN: N);
4616}
4617
4618void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
4619 // If this is a fixed sized alloca in the entry block of the function,
4620 // allocate it statically on the stack.
4621 if (FuncInfo.StaticAllocaMap.count(Val: &I))
4622 return; // getValue will auto-populate this.
4623
4624 SDLoc dl = getCurSDLoc();
4625 Type *Ty = I.getAllocatedType();
4626 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4627 auto &DL = DAG.getDataLayout();
4628 TypeSize TySize = DL.getTypeAllocSize(Ty);
4629 MaybeAlign Alignment = I.getAlign();
4630
4631 SDValue AllocSize = getValue(V: I.getArraySize());
4632
4633 EVT IntPtr = TLI.getPointerTy(DL, AS: I.getAddressSpace());
4634 if (AllocSize.getValueType() != IntPtr)
4635 AllocSize = DAG.getZExtOrTrunc(Op: AllocSize, DL: dl, VT: IntPtr);
4636
4637 AllocSize = DAG.getNode(
4638 Opcode: ISD::MUL, DL: dl, VT: IntPtr, N1: AllocSize,
4639 N2: DAG.getZExtOrTrunc(Op: DAG.getTypeSize(DL: dl, VT: MVT::i64, TS: TySize), DL: dl, VT: IntPtr));
4640
4641 // Handle alignment. If the requested alignment is less than or equal to
4642 // the stack alignment, ignore it. If the size is greater than or equal to
4643 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
4644 Align StackAlign = DAG.getSubtarget().getFrameLowering()->getStackAlign();
4645 if (*Alignment <= StackAlign)
4646 Alignment = std::nullopt;
4647
4648 const uint64_t StackAlignMask = StackAlign.value() - 1U;
4649 // Round the size of the allocation up to the stack alignment size
4650 // by add SA-1 to the size. This doesn't overflow because we're computing
4651 // an address inside an alloca.
4652 AllocSize = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: AllocSize.getValueType(), N1: AllocSize,
4653 N2: DAG.getConstant(Val: StackAlignMask, DL: dl, VT: IntPtr),
4654 Flags: SDNodeFlags::NoUnsignedWrap);
4655
4656 // Mask out the low bits for alignment purposes.
4657 AllocSize = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AllocSize.getValueType(), N1: AllocSize,
4658 N2: DAG.getSignedConstant(Val: ~StackAlignMask, DL: dl, VT: IntPtr));
4659
4660 SDValue Ops[] = {
4661 getRoot(), AllocSize,
4662 DAG.getConstant(Val: Alignment ? Alignment->value() : 0, DL: dl, VT: IntPtr)};
4663 SDVTList VTs = DAG.getVTList(VT1: AllocSize.getValueType(), VT2: MVT::Other);
4664 SDValue DSA = DAG.getNode(Opcode: ISD::DYNAMIC_STACKALLOC, DL: dl, VTList: VTs, Ops);
4665 setValue(V: &I, NewN: DSA);
4666 DAG.setRoot(DSA.getValue(R: 1));
4667
4668 assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects());
4669}
4670
4671static const MDNode *getRangeMetadata(const Instruction &I) {
4672 return I.getMetadata(KindID: LLVMContext::MD_range);
4673}
4674
4675static std::optional<ConstantRange> getRange(const Instruction &I) {
4676 if (const auto *CB = dyn_cast<CallBase>(Val: &I))
4677 if (std::optional<ConstantRange> CR = CB->getRange())
4678 return CR;
4679 if (const MDNode *Range = getRangeMetadata(I))
4680 return getConstantRangeFromMetadata(RangeMD: *Range);
4681 return std::nullopt;
4682}
4683
4684static FPClassTest getNoFPClass(const Instruction &I) {
4685 if (const auto *CB = dyn_cast<CallBase>(Val: &I))
4686 return CB->getRetNoFPClass();
4687 return fcNone;
4688}
4689
4690void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
4691 if (I.isAtomic())
4692 return visitAtomicLoad(I);
4693
4694 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4695 const Value *SV = I.getOperand(i_nocapture: 0);
4696 if (TLI.supportSwiftError()) {
4697 // Swifterror values can come from either a function parameter with
4698 // swifterror attribute or an alloca with swifterror attribute.
4699 if (const Argument *Arg = dyn_cast<Argument>(Val: SV)) {
4700 if (Arg->hasSwiftErrorAttr())
4701 return visitLoadFromSwiftError(I);
4702 }
4703
4704 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: SV)) {
4705 if (Alloca->isSwiftError())
4706 return visitLoadFromSwiftError(I);
4707 }
4708 }
4709
4710 SDValue Ptr = getValue(V: SV);
4711
4712 Type *Ty = I.getType();
4713 SmallVector<EVT, 4> ValueVTs, MemVTs;
4714 SmallVector<TypeSize, 4> Offsets;
4715 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty, ValueVTs, MemVTs: &MemVTs, Offsets: &Offsets);
4716 unsigned NumValues = ValueVTs.size();
4717 if (NumValues == 0)
4718 return;
4719
4720 Align Alignment = I.getAlign();
4721 AAMDNodes AAInfo = I.getAAMetadata();
4722 const MDNode *Ranges = getRangeMetadata(I);
4723 bool isVolatile = I.isVolatile();
4724 MachineMemOperand::Flags MMOFlags =
4725 TLI.getLoadMemOperandFlags(LI: I, DL: DAG.getDataLayout(), AC, LibInfo);
4726
4727 SDValue Root;
4728 bool ConstantMemory = false;
4729 if (isVolatile)
4730 // Serialize volatile loads with other side effects.
4731 Root = getRoot();
4732 else if (NumValues > MaxParallelChains)
4733 Root = getMemoryRoot();
4734 else if (BatchAA &&
4735 BatchAA->pointsToConstantMemory(Loc: MemoryLocation(
4736 SV,
4737 LocationSize::precise(Value: DAG.getDataLayout().getTypeStoreSize(Ty)),
4738 AAInfo))) {
4739 // Do not serialize (non-volatile) loads of constant memory with anything.
4740 Root = DAG.getEntryNode();
4741 ConstantMemory = true;
4742 MMOFlags |= MachineMemOperand::MOInvariant;
4743 } else {
4744 // Do not serialize non-volatile loads against each other.
4745 Root = DAG.getRoot();
4746 }
4747
4748 SDLoc dl = getCurSDLoc();
4749
4750 if (isVolatile)
4751 Root = TLI.prepareVolatileOrAtomicLoad(Chain: Root, DL: dl, DAG);
4752
4753 SmallVector<SDValue, 4> Values(NumValues);
4754 SmallVector<SDValue, 4> Chains(std::min(a: MaxParallelChains, b: NumValues));
4755
4756 unsigned ChainI = 0;
4757 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4758 // Serializing loads here may result in excessive register pressure, and
4759 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
4760 // could recover a bit by hoisting nodes upward in the chain by recognizing
4761 // they are side-effect free or do not alias. The optimizer should really
4762 // avoid this case by converting large object/array copies to llvm.memcpy
4763 // (MaxParallelChains should always remain as failsafe).
4764 if (ChainI == MaxParallelChains) {
4765 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
4766 SDValue Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other,
4767 Ops: ArrayRef(Chains.data(), ChainI));
4768 Root = Chain;
4769 ChainI = 0;
4770 }
4771
4772 // TODO: MachinePointerInfo only supports a fixed length offset.
4773 MachinePointerInfo PtrInfo =
4774 !Offsets[i].isScalable() || Offsets[i].isZero()
4775 ? MachinePointerInfo(SV, Offsets[i].getKnownMinValue())
4776 : MachinePointerInfo();
4777
4778 SDValue A = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: Offsets[i]);
4779 SDValue L = DAG.getLoad(VT: MemVTs[i], dl, Chain: Root, Ptr: A, PtrInfo, Alignment,
4780 MMOFlags, AAInfo, Ranges);
4781 Chains[ChainI] = L.getValue(R: 1);
4782
4783 if (MemVTs[i] != ValueVTs[i])
4784 L = DAG.getPtrExtOrTrunc(Op: L, DL: dl, VT: ValueVTs[i]);
4785
4786 if (MDNode *NoFPClassMD = I.getMetadata(KindID: LLVMContext::MD_nofpclass)) {
4787 uint64_t FPTestInt =
4788 cast<ConstantInt>(
4789 Val: cast<ConstantAsMetadata>(Val: NoFPClassMD->getOperand(I: 0))->getValue())
4790 ->getZExtValue();
4791 if (FPTestInt != fcNone) {
4792 SDValue FPTestConst =
4793 DAG.getTargetConstant(Val: FPTestInt, DL: SDLoc(), VT: MVT::i32);
4794 L = DAG.getNode(Opcode: ISD::AssertNoFPClass, DL: dl, VT: L.getValueType(), N1: L,
4795 N2: FPTestConst);
4796 }
4797 }
4798 Values[i] = L;
4799 }
4800
4801 if (!ConstantMemory) {
4802 SDValue Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other,
4803 Ops: ArrayRef(Chains.data(), ChainI));
4804 if (isVolatile)
4805 DAG.setRoot(Chain);
4806 else
4807 PendingLoads.push_back(Elt: Chain);
4808 }
4809
4810 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: dl,
4811 VTList: DAG.getVTList(VTs: ValueVTs), Ops: Values));
4812}
4813
4814void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
4815 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&
4816 "call visitStoreToSwiftError when backend supports swifterror");
4817
4818 SmallVector<EVT, 4> ValueVTs;
4819 SmallVector<uint64_t, 4> Offsets;
4820 const Value *SrcV = I.getOperand(i_nocapture: 0);
4821 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(),
4822 Ty: SrcV->getType(), ValueVTs, /*MemVTs=*/nullptr, FixedOffsets: &Offsets, StartingOffset: 0);
4823 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4824 "expect a single EVT for swifterror");
4825
4826 SDValue Src = getValue(V: SrcV);
4827 // Create a virtual register, then update the virtual register.
4828 Register VReg =
4829 SwiftError.getOrCreateVRegDefAt(&I, FuncInfo.MBB, I.getPointerOperand());
4830 // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
4831 // Chain can be getRoot or getControlRoot.
4832 SDValue CopyNode = DAG.getCopyToReg(Chain: getRoot(), dl: getCurSDLoc(), Reg: VReg,
4833 N: SDValue(Src.getNode(), Src.getResNo()));
4834 DAG.setRoot(CopyNode);
4835}
4836
4837void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
4838 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&
4839 "call visitLoadFromSwiftError when backend supports swifterror");
4840
4841 assert(!I.isVolatile() &&
4842 !I.hasMetadata(LLVMContext::MD_nontemporal) &&
4843 !I.hasMetadata(LLVMContext::MD_invariant_load) &&
4844 "Support volatile, non temporal, invariant for load_from_swift_error");
4845
4846 const Value *SV = I.getOperand(i_nocapture: 0);
4847 Type *Ty = I.getType();
4848 assert(
4849 (!BatchAA ||
4850 !BatchAA->pointsToConstantMemory(MemoryLocation(
4851 SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),
4852 I.getAAMetadata()))) &&
4853 "load_from_swift_error should not be constant memory");
4854
4855 SmallVector<EVT, 4> ValueVTs;
4856 SmallVector<uint64_t, 4> Offsets;
4857 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(), Ty,
4858 ValueVTs, /*MemVTs=*/nullptr, FixedOffsets: &Offsets, StartingOffset: 0);
4859 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4860 "expect a single EVT for swifterror");
4861
4862 // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
4863 SDValue L = DAG.getCopyFromReg(
4864 Chain: getRoot(), dl: getCurSDLoc(),
4865 Reg: SwiftError.getOrCreateVRegUseAt(&I, FuncInfo.MBB, SV), VT: ValueVTs[0]);
4866
4867 setValue(V: &I, NewN: L);
4868}
4869
4870void SelectionDAGBuilder::visitStore(const StoreInst &I) {
4871 if (I.isAtomic())
4872 return visitAtomicStore(I);
4873
4874 const Value *SrcV = I.getOperand(i_nocapture: 0);
4875 const Value *PtrV = I.getOperand(i_nocapture: 1);
4876
4877 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4878 if (TLI.supportSwiftError()) {
4879 // Swifterror values can come from either a function parameter with
4880 // swifterror attribute or an alloca with swifterror attribute.
4881 if (const Argument *Arg = dyn_cast<Argument>(Val: PtrV)) {
4882 if (Arg->hasSwiftErrorAttr())
4883 return visitStoreToSwiftError(I);
4884 }
4885
4886 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: PtrV)) {
4887 if (Alloca->isSwiftError())
4888 return visitStoreToSwiftError(I);
4889 }
4890 }
4891
4892 SmallVector<EVT, 4> ValueVTs, MemVTs;
4893 SmallVector<TypeSize, 4> Offsets;
4894 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(),
4895 Ty: SrcV->getType(), ValueVTs, MemVTs: &MemVTs, Offsets: &Offsets);
4896 unsigned NumValues = ValueVTs.size();
4897 if (NumValues == 0)
4898 return;
4899
4900 // Get the lowered operands. Note that we do this after
4901 // checking if NumResults is zero, because with zero results
4902 // the operands won't have values in the map.
4903 SDValue Src = getValue(V: SrcV);
4904 SDValue Ptr = getValue(V: PtrV);
4905
4906 SDValue Root = I.isVolatile() ? getRoot() : getMemoryRoot();
4907 SmallVector<SDValue, 4> Chains(std::min(a: MaxParallelChains, b: NumValues));
4908 SDLoc dl = getCurSDLoc();
4909 Align Alignment = I.getAlign();
4910 AAMDNodes AAInfo = I.getAAMetadata();
4911
4912 auto MMOFlags = TLI.getStoreMemOperandFlags(SI: I, DL: DAG.getDataLayout());
4913
4914 unsigned ChainI = 0;
4915 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4916 // See visitLoad comments.
4917 if (ChainI == MaxParallelChains) {
4918 SDValue Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other,
4919 Ops: ArrayRef(Chains.data(), ChainI));
4920 Root = Chain;
4921 ChainI = 0;
4922 }
4923
4924 // TODO: MachinePointerInfo only supports a fixed length offset.
4925 MachinePointerInfo PtrInfo =
4926 !Offsets[i].isScalable() || Offsets[i].isZero()
4927 ? MachinePointerInfo(PtrV, Offsets[i].getKnownMinValue())
4928 : MachinePointerInfo();
4929
4930 SDValue Add = DAG.getObjectPtrOffset(SL: dl, Ptr, Offset: Offsets[i]);
4931 SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
4932 if (MemVTs[i] != ValueVTs[i])
4933 Val = DAG.getPtrExtOrTrunc(Op: Val, DL: dl, VT: MemVTs[i]);
4934 SDValue St =
4935 DAG.getStore(Chain: Root, dl, Val, Ptr: Add, PtrInfo, Alignment, MMOFlags, AAInfo);
4936 Chains[ChainI] = St;
4937 }
4938
4939 SDValue StoreNode = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other,
4940 Ops: ArrayRef(Chains.data(), ChainI));
4941 setValue(V: &I, NewN: StoreNode);
4942 DAG.setRoot(StoreNode);
4943}
4944
4945void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
4946 bool IsCompressing) {
4947 SDLoc sdl = getCurSDLoc();
4948
4949 Value *Src0Operand = I.getArgOperand(i: 0);
4950 Value *PtrOperand = I.getArgOperand(i: 1);
4951 Value *MaskOperand = I.getArgOperand(i: 2);
4952 Align Alignment = I.getParamAlign(ArgNo: 1).valueOrOne();
4953
4954 SDValue Ptr = getValue(V: PtrOperand);
4955 SDValue Src0 = getValue(V: Src0Operand);
4956 SDValue Mask = getValue(V: MaskOperand);
4957 SDValue Offset = DAG.getUNDEF(VT: Ptr.getValueType());
4958
4959 EVT VT = Src0.getValueType();
4960
4961 auto MMOFlags = MachineMemOperand::MOStore;
4962 if (I.hasMetadata(KindID: LLVMContext::MD_nontemporal))
4963 MMOFlags |= MachineMemOperand::MONonTemporal;
4964
4965 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4966 PtrInfo: MachinePointerInfo(PtrOperand), F: MMOFlags,
4967 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: Alignment, AAInfo: I.getAAMetadata());
4968
4969 const auto &TLI = DAG.getTargetLoweringInfo();
4970
4971 SDValue StoreNode =
4972 !IsCompressing && TTI->hasConditionalLoadStoreForType(
4973 Ty: I.getArgOperand(i: 0)->getType(), /*IsStore=*/true)
4974 ? TLI.visitMaskedStore(DAG, DL: sdl, Chain: getMemoryRoot(), MMO, Ptr, Val: Src0,
4975 Mask)
4976 : DAG.getMaskedStore(Chain: getMemoryRoot(), dl: sdl, Val: Src0, Base: Ptr, Offset, Mask,
4977 MemVT: VT, MMO, AM: ISD::UNINDEXED, /*Truncating=*/IsTruncating: false,
4978 IsCompressing);
4979 DAG.setRoot(StoreNode);
4980 setValue(V: &I, NewN: StoreNode);
4981}
4982
4983// Get a uniform base for the Gather/Scatter intrinsic.
4984// The first argument of the Gather/Scatter intrinsic is a vector of pointers.
4985// We try to represent it as a base pointer + vector of indices.
4986// Usually, the vector of pointers comes from a 'getelementptr' instruction.
4987// The first operand of the GEP may be a single pointer or a vector of pointers
4988// Example:
4989// %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
4990// or
4991// %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
4992// %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
4993//
4994// When the first GEP operand is a single pointer - it is the uniform base we
4995// are looking for. If first operand of the GEP is a splat vector - we
4996// extract the splat value and use it as a uniform base.
4997// In all other cases the function returns 'false'.
4998static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index,
4999 SDValue &Scale, SelectionDAGBuilder *SDB,
5000 const BasicBlock *CurBB, uint64_t ElemSize) {
5001 SelectionDAG& DAG = SDB->DAG;
5002 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5003 const DataLayout &DL = DAG.getDataLayout();
5004
5005 assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type");
5006
5007 // Handle splat constant pointer.
5008 if (auto *C = dyn_cast<Constant>(Val: Ptr)) {
5009 C = C->getSplatValue();
5010 if (!C)
5011 return false;
5012
5013 Base = SDB->getValue(V: C);
5014
5015 ElementCount NumElts = cast<VectorType>(Val: Ptr->getType())->getElementCount();
5016 EVT VT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: TLI.getPointerTy(DL), EC: NumElts);
5017 Index = DAG.getConstant(Val: 0, DL: SDB->getCurSDLoc(), VT);
5018 Scale = DAG.getTargetConstant(Val: 1, DL: SDB->getCurSDLoc(), VT: TLI.getPointerTy(DL));
5019 return true;
5020 }
5021
5022 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Val: Ptr);
5023 if (!GEP || GEP->getParent() != CurBB)
5024 return false;
5025
5026 if (GEP->getNumOperands() != 2)
5027 return false;
5028
5029 const Value *BasePtr = GEP->getPointerOperand();
5030 const Value *IndexVal = GEP->getOperand(i_nocapture: GEP->getNumOperands() - 1);
5031
5032 // Make sure the base is scalar and the index is a vector.
5033 if (BasePtr->getType()->isVectorTy() || !IndexVal->getType()->isVectorTy())
5034 return false;
5035
5036 TypeSize ScaleVal = DL.getTypeAllocSize(Ty: GEP->getResultElementType());
5037 if (ScaleVal.isScalable())
5038 return false;
5039
5040 // Target may not support the required addressing mode.
5041 if (ScaleVal != 1 &&
5042 !TLI.isLegalScaleForGatherScatter(Scale: ScaleVal.getFixedValue(), ElemSize))
5043 return false;
5044
5045 Base = SDB->getValue(V: BasePtr);
5046 Index = SDB->getValue(V: IndexVal);
5047
5048 Scale =
5049 DAG.getTargetConstant(Val: ScaleVal, DL: SDB->getCurSDLoc(), VT: TLI.getPointerTy(DL));
5050 return true;
5051}
5052
5053void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
5054 SDLoc sdl = getCurSDLoc();
5055
5056 // llvm.masked.scatter.*(Src0, Ptrs, Mask)
5057 const Value *Ptr = I.getArgOperand(i: 1);
5058 SDValue Src0 = getValue(V: I.getArgOperand(i: 0));
5059 SDValue Mask = getValue(V: I.getArgOperand(i: 2));
5060 EVT VT = Src0.getValueType();
5061 Align Alignment = I.getParamAlign(ArgNo: 1).valueOrOne();
5062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5063
5064 SDValue Base;
5065 SDValue Index;
5066 SDValue Scale;
5067 bool UniformBase = getUniformBase(Ptr, Base, Index, Scale, SDB: this,
5068 CurBB: I.getParent(), ElemSize: VT.getScalarStoreSize());
5069
5070 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
5071 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
5072 PtrInfo: MachinePointerInfo(AS), F: MachineMemOperand::MOStore,
5073 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: Alignment, AAInfo: I.getAAMetadata());
5074 if (!UniformBase) {
5075 Base = DAG.getConstant(Val: 0, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
5076 Index = getValue(V: Ptr);
5077 Scale =
5078 DAG.getTargetConstant(Val: 1, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
5079 }
5080
5081 EVT IdxVT = Index.getValueType();
5082 EVT EltTy = IdxVT.getVectorElementType();
5083 if (TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
5084 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
5085 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: sdl, VT: NewIdxVT, Operand: Index);
5086 }
5087
5088 SDValue Ops[] = { getMemoryRoot(), Src0, Mask, Base, Index, Scale };
5089 SDValue Scatter = DAG.getMaskedScatter(VTs: DAG.getVTList(VT: MVT::Other), MemVT: VT, dl: sdl,
5090 Ops, MMO, IndexType: ISD::SIGNED_SCALED, IsTruncating: false);
5091 DAG.setRoot(Scatter);
5092 setValue(V: &I, NewN: Scatter);
5093}
5094
5095void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
5096 SDLoc sdl = getCurSDLoc();
5097
5098 Value *PtrOperand = I.getArgOperand(i: 0);
5099 Value *MaskOperand = I.getArgOperand(i: 1);
5100 Value *Src0Operand = I.getArgOperand(i: 2);
5101 Align Alignment = I.getParamAlign(ArgNo: 0).valueOrOne();
5102
5103 SDValue Ptr = getValue(V: PtrOperand);
5104 SDValue Src0 = getValue(V: Src0Operand);
5105 SDValue Mask = getValue(V: MaskOperand);
5106 SDValue Offset = DAG.getUNDEF(VT: Ptr.getValueType());
5107
5108 EVT VT = Src0.getValueType();
5109 AAMDNodes AAInfo = I.getAAMetadata();
5110 const MDNode *Ranges = getRangeMetadata(I);
5111
5112 // Do not serialize masked loads of constant memory with anything.
5113 MemoryLocation ML = MemoryLocation::getAfter(Ptr: PtrOperand, AATags: AAInfo);
5114 bool AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(Loc: ML);
5115
5116 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
5117
5118 auto MMOFlags = MachineMemOperand::MOLoad;
5119 if (I.hasMetadata(KindID: LLVMContext::MD_nontemporal))
5120 MMOFlags |= MachineMemOperand::MONonTemporal;
5121 if (I.hasMetadata(KindID: LLVMContext::MD_invariant_load))
5122 MMOFlags |= MachineMemOperand::MOInvariant;
5123
5124 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
5125 PtrInfo: MachinePointerInfo(PtrOperand), F: MMOFlags,
5126 Size: VT.getStoreSize(), BaseAlignment: Alignment, AAInfo, Ranges);
5127
5128 const auto &TLI = DAG.getTargetLoweringInfo();
5129
5130 // The Load/Res may point to different values and both of them are output
5131 // variables.
5132 SDValue Load;
5133 SDValue Res;
5134 if (!IsExpanding &&
5135 TTI->hasConditionalLoadStoreForType(Ty: Src0Operand->getType(),
5136 /*IsStore=*/false))
5137 Res = TLI.visitMaskedLoad(DAG, DL: sdl, Chain: InChain, MMO, NewLoad&: Load, Ptr, PassThru: Src0, Mask);
5138 else
5139 Res = Load =
5140 DAG.getMaskedLoad(VT, dl: sdl, Chain: InChain, Base: Ptr, Offset, Mask, Src0, MemVT: VT, MMO,
5141 AM: ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding);
5142 if (AddToChain)
5143 PendingLoads.push_back(Elt: Load.getValue(R: 1));
5144 setValue(V: &I, NewN: Res);
5145}
5146
5147void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
5148 SDLoc sdl = getCurSDLoc();
5149
5150 // @llvm.masked.gather.*(Ptrs, Mask, Src0)
5151 const Value *Ptr = I.getArgOperand(i: 0);
5152 SDValue Src0 = getValue(V: I.getArgOperand(i: 2));
5153 SDValue Mask = getValue(V: I.getArgOperand(i: 1));
5154
5155 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5156 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
5157 Align Alignment = I.getParamAlign(ArgNo: 0).valueOrOne();
5158
5159 const MDNode *Ranges = getRangeMetadata(I);
5160
5161 SDValue Root = DAG.getRoot();
5162 SDValue Base;
5163 SDValue Index;
5164 SDValue Scale;
5165 bool UniformBase = getUniformBase(Ptr, Base, Index, Scale, SDB: this,
5166 CurBB: I.getParent(), ElemSize: VT.getScalarStoreSize());
5167 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
5168 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
5169 PtrInfo: MachinePointerInfo(AS), F: MachineMemOperand::MOLoad,
5170 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: Alignment, AAInfo: I.getAAMetadata(),
5171 Ranges);
5172
5173 if (!UniformBase) {
5174 Base = DAG.getConstant(Val: 0, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
5175 Index = getValue(V: Ptr);
5176 Scale =
5177 DAG.getTargetConstant(Val: 1, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
5178 }
5179
5180 EVT IdxVT = Index.getValueType();
5181 EVT EltTy = IdxVT.getVectorElementType();
5182 if (TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
5183 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
5184 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: sdl, VT: NewIdxVT, Operand: Index);
5185 }
5186
5187 SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale };
5188 SDValue Gather =
5189 DAG.getMaskedGather(VTs: DAG.getVTList(VT1: VT, VT2: MVT::Other), MemVT: VT, dl: sdl, Ops, MMO,
5190 IndexType: ISD::SIGNED_SCALED, ExtTy: ISD::NON_EXTLOAD);
5191
5192 PendingLoads.push_back(Elt: Gather.getValue(R: 1));
5193 setValue(V: &I, NewN: Gather);
5194}
5195
5196void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
5197 SDLoc dl = getCurSDLoc();
5198 AtomicOrdering SuccessOrdering = I.getSuccessOrdering();
5199 AtomicOrdering FailureOrdering = I.getFailureOrdering();
5200 SyncScope::ID SSID = I.getSyncScopeID();
5201
5202 SDValue InChain = getRoot();
5203
5204 MVT MemVT = getValue(V: I.getCompareOperand()).getSimpleValueType();
5205 SDVTList VTs = DAG.getVTList(VT1: MemVT, VT2: MVT::i1, VT3: MVT::Other);
5206
5207 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5208 auto Flags = TLI.getAtomicMemOperandFlags(AI: I, DL: DAG.getDataLayout());
5209
5210 MachineFunction &MF = DAG.getMachineFunction();
5211 MachineMemOperand *MMO = MF.getMachineMemOperand(
5212 PtrInfo: MachinePointerInfo(I.getPointerOperand()), F: Flags, Size: MemVT.getStoreSize(),
5213 BaseAlignment: DAG.getEVTAlign(MemoryVT: MemVT), AAInfo: AAMDNodes(), Ranges: nullptr, SSID, Ordering: SuccessOrdering,
5214 FailureOrdering);
5215
5216 SDValue L = DAG.getAtomicCmpSwap(Opcode: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
5217 dl, MemVT, VTs, Chain: InChain,
5218 Ptr: getValue(V: I.getPointerOperand()),
5219 Cmp: getValue(V: I.getCompareOperand()),
5220 Swp: getValue(V: I.getNewValOperand()), MMO);
5221
5222 SDValue OutChain = L.getValue(R: 2);
5223
5224 setValue(V: &I, NewN: L);
5225 DAG.setRoot(OutChain);
5226}
5227
5228void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
5229 SDLoc dl = getCurSDLoc();
5230 ISD::NodeType NT;
5231 switch (I.getOperation()) {
5232 default: llvm_unreachable("Unknown atomicrmw operation");
5233 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
5234 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
5235 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
5236 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
5237 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
5238 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
5239 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
5240 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
5241 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
5242 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
5243 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
5244 case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break;
5245 case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break;
5246 case AtomicRMWInst::FMax: NT = ISD::ATOMIC_LOAD_FMAX; break;
5247 case AtomicRMWInst::FMin: NT = ISD::ATOMIC_LOAD_FMIN; break;
5248 case AtomicRMWInst::FMaximum:
5249 NT = ISD::ATOMIC_LOAD_FMAXIMUM;
5250 break;
5251 case AtomicRMWInst::FMinimum:
5252 NT = ISD::ATOMIC_LOAD_FMINIMUM;
5253 break;
5254 case AtomicRMWInst::FMaximumNum:
5255 NT = ISD::ATOMIC_LOAD_FMAXIMUMNUM;
5256 break;
5257 case AtomicRMWInst::FMinimumNum:
5258 NT = ISD::ATOMIC_LOAD_FMINIMUMNUM;
5259 break;
5260 case AtomicRMWInst::UIncWrap:
5261 NT = ISD::ATOMIC_LOAD_UINC_WRAP;
5262 break;
5263 case AtomicRMWInst::UDecWrap:
5264 NT = ISD::ATOMIC_LOAD_UDEC_WRAP;
5265 break;
5266 case AtomicRMWInst::USubCond:
5267 NT = ISD::ATOMIC_LOAD_USUB_COND;
5268 break;
5269 case AtomicRMWInst::USubSat:
5270 NT = ISD::ATOMIC_LOAD_USUB_SAT;
5271 break;
5272 }
5273 AtomicOrdering Ordering = I.getOrdering();
5274 SyncScope::ID SSID = I.getSyncScopeID();
5275
5276 SDValue InChain = getRoot();
5277
5278 auto MemVT = getValue(V: I.getValOperand()).getSimpleValueType();
5279 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5280 auto Flags = TLI.getAtomicMemOperandFlags(AI: I, DL: DAG.getDataLayout());
5281
5282 MachineFunction &MF = DAG.getMachineFunction();
5283 MachineMemOperand *MMO = MF.getMachineMemOperand(
5284 PtrInfo: MachinePointerInfo(I.getPointerOperand()), F: Flags, Size: MemVT.getStoreSize(),
5285 BaseAlignment: DAG.getEVTAlign(MemoryVT: MemVT), AAInfo: AAMDNodes(), Ranges: nullptr, SSID, Ordering);
5286
5287 SDValue L =
5288 DAG.getAtomic(Opcode: NT, dl, MemVT, Chain: InChain,
5289 Ptr: getValue(V: I.getPointerOperand()), Val: getValue(V: I.getValOperand()),
5290 MMO);
5291
5292 SDValue OutChain = L.getValue(R: 1);
5293
5294 setValue(V: &I, NewN: L);
5295 DAG.setRoot(OutChain);
5296}
5297
5298void SelectionDAGBuilder::visitFence(const FenceInst &I) {
5299 SDLoc dl = getCurSDLoc();
5300 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5301 SDValue Ops[3];
5302 Ops[0] = getRoot();
5303 Ops[1] = DAG.getTargetConstant(Val: (unsigned)I.getOrdering(), DL: dl,
5304 VT: TLI.getFenceOperandTy(DL: DAG.getDataLayout()));
5305 Ops[2] = DAG.getTargetConstant(Val: I.getSyncScopeID(), DL: dl,
5306 VT: TLI.getFenceOperandTy(DL: DAG.getDataLayout()));
5307 SDValue N = DAG.getNode(Opcode: ISD::ATOMIC_FENCE, DL: dl, VT: MVT::Other, Ops);
5308 setValue(V: &I, NewN: N);
5309 DAG.setRoot(N);
5310}
5311
5312void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
5313 SDLoc dl = getCurSDLoc();
5314 AtomicOrdering Order = I.getOrdering();
5315 SyncScope::ID SSID = I.getSyncScopeID();
5316
5317 SDValue InChain = getRoot();
5318
5319 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5320 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
5321 EVT MemVT = TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getType());
5322
5323 if (!TLI.supportsUnalignedAtomics() &&
5324 I.getAlign().value() < MemVT.getSizeInBits() / 8)
5325 report_fatal_error(reason: "Cannot generate unaligned atomic load");
5326
5327 auto Flags = TLI.getLoadMemOperandFlags(LI: I, DL: DAG.getDataLayout(), AC, LibInfo);
5328
5329 const MDNode *Ranges = getRangeMetadata(I);
5330 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
5331 PtrInfo: MachinePointerInfo(I.getPointerOperand()), F: Flags, Size: MemVT.getStoreSize(),
5332 BaseAlignment: I.getAlign(), AAInfo: AAMDNodes(), Ranges, SSID, Ordering: Order);
5333
5334 InChain = TLI.prepareVolatileOrAtomicLoad(Chain: InChain, DL: dl, DAG);
5335
5336 SDValue Ptr = getValue(V: I.getPointerOperand());
5337 SDValue L =
5338 DAG.getAtomicLoad(ExtType: ISD::NON_EXTLOAD, dl, MemVT, VT: MemVT, Chain: InChain, Ptr, MMO);
5339
5340 SDValue OutChain = L.getValue(R: 1);
5341 if (MemVT != VT)
5342 L = DAG.getPtrExtOrTrunc(Op: L, DL: dl, VT);
5343
5344 setValue(V: &I, NewN: L);
5345 DAG.setRoot(OutChain);
5346}
5347
5348void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
5349 SDLoc dl = getCurSDLoc();
5350
5351 AtomicOrdering Ordering = I.getOrdering();
5352 SyncScope::ID SSID = I.getSyncScopeID();
5353
5354 SDValue InChain = getRoot();
5355
5356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5357 EVT MemVT =
5358 TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getValueOperand()->getType());
5359
5360 if (!TLI.supportsUnalignedAtomics() &&
5361 I.getAlign().value() < MemVT.getSizeInBits() / 8)
5362 report_fatal_error(reason: "Cannot generate unaligned atomic store");
5363
5364 auto Flags = TLI.getStoreMemOperandFlags(SI: I, DL: DAG.getDataLayout());
5365
5366 MachineFunction &MF = DAG.getMachineFunction();
5367 MachineMemOperand *MMO = MF.getMachineMemOperand(
5368 PtrInfo: MachinePointerInfo(I.getPointerOperand()), F: Flags, Size: MemVT.getStoreSize(),
5369 BaseAlignment: I.getAlign(), AAInfo: AAMDNodes(), Ranges: nullptr, SSID, Ordering);
5370
5371 SDValue Val = getValue(V: I.getValueOperand());
5372 if (Val.getValueType() != MemVT)
5373 Val = DAG.getPtrExtOrTrunc(Op: Val, DL: dl, VT: MemVT);
5374 SDValue Ptr = getValue(V: I.getPointerOperand());
5375
5376 SDValue OutChain =
5377 DAG.getAtomic(Opcode: ISD::ATOMIC_STORE, dl, MemVT, Chain: InChain, Ptr: Val, Val: Ptr, MMO);
5378
5379 setValue(V: &I, NewN: OutChain);
5380 DAG.setRoot(OutChain);
5381}
5382
5383/// Check if this intrinsic call depends on the chain (1st return value)
5384/// and if it only *loads* memory.
5385/// Ignore the callsite's attributes. A specific call site may be marked with
5386/// readnone, but the lowering code will expect the chain based on the
5387/// definition.
5388std::pair<bool, bool>
5389SelectionDAGBuilder::getTargetIntrinsicCallProperties(const CallBase &I) {
5390 const Function *F = I.getCalledFunction();
5391 bool HasChain = !F->doesNotAccessMemory();
5392 bool OnlyLoad =
5393 HasChain && F->onlyReadsMemory() && F->willReturn() && F->doesNotThrow();
5394
5395 return {HasChain, OnlyLoad};
5396}
5397
5398SmallVector<SDValue, 8> SelectionDAGBuilder::getTargetIntrinsicOperands(
5399 const CallBase &I, bool HasChain, bool OnlyLoad,
5400 TargetLowering::IntrinsicInfo *TgtMemIntrinsicInfo) {
5401 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5402
5403 // Build the operand list.
5404 SmallVector<SDValue, 8> Ops;
5405 if (HasChain) { // If this intrinsic has side-effects, chainify it.
5406 if (OnlyLoad) {
5407 // We don't need to serialize loads against other loads.
5408 Ops.push_back(Elt: DAG.getRoot());
5409 } else {
5410 Ops.push_back(Elt: getRoot());
5411 }
5412 }
5413
5414 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
5415 if (!TgtMemIntrinsicInfo || TgtMemIntrinsicInfo->opc == ISD::INTRINSIC_VOID ||
5416 TgtMemIntrinsicInfo->opc == ISD::INTRINSIC_W_CHAIN)
5417 Ops.push_back(Elt: DAG.getTargetConstant(Val: I.getIntrinsicID(), DL: getCurSDLoc(),
5418 VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
5419
5420 // Add all operands of the call to the operand list.
5421 for (unsigned i = 0, e = I.arg_size(); i != e; ++i) {
5422 const Value *Arg = I.getArgOperand(i);
5423 if (!I.paramHasAttr(ArgNo: i, Kind: Attribute::ImmArg)) {
5424 Ops.push_back(Elt: getValue(V: Arg));
5425 continue;
5426 }
5427
5428 // Use TargetConstant instead of a regular constant for immarg.
5429 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: Arg->getType(), AllowUnknown: true);
5430 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: Arg)) {
5431 assert(CI->getBitWidth() <= 64 &&
5432 "large intrinsic immediates not handled");
5433 Ops.push_back(Elt: DAG.getTargetConstant(Val: *CI, DL: SDLoc(), VT));
5434 } else {
5435 Ops.push_back(
5436 Elt: DAG.getTargetConstantFP(Val: *cast<ConstantFP>(Val: Arg), DL: SDLoc(), VT));
5437 }
5438 }
5439
5440 if (std::optional<OperandBundleUse> Bundle =
5441 I.getOperandBundle(ID: LLVMContext::OB_deactivation_symbol)) {
5442 auto *Sym = Bundle->Inputs[0].get();
5443 SDValue SDSym = getValue(V: Sym);
5444 SDSym = DAG.getDeactivationSymbol(GV: cast<GlobalValue>(Val: Sym));
5445 Ops.push_back(Elt: SDSym);
5446 }
5447
5448 if (std::optional<OperandBundleUse> Bundle =
5449 I.getOperandBundle(ID: LLVMContext::OB_convergencectrl)) {
5450 Value *Token = Bundle->Inputs[0].get();
5451 SDValue ConvControlToken = getValue(V: Token);
5452 assert(Ops.back().getValueType() != MVT::Glue &&
5453 "Did not expect another glue node here.");
5454 ConvControlToken =
5455 DAG.getNode(Opcode: ISD::CONVERGENCECTRL_GLUE, DL: {}, VT: MVT::Glue, Operand: ConvControlToken);
5456 Ops.push_back(Elt: ConvControlToken);
5457 }
5458
5459 return Ops;
5460}
5461
5462SDVTList SelectionDAGBuilder::getTargetIntrinsicVTList(const CallBase &I,
5463 bool HasChain) {
5464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5465
5466 SmallVector<EVT, 4> ValueVTs;
5467 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: I.getType(), ValueVTs);
5468
5469 if (HasChain)
5470 ValueVTs.push_back(Elt: MVT::Other);
5471
5472 return DAG.getVTList(VTs: ValueVTs);
5473}
5474
5475/// Get an INTRINSIC node for a target intrinsic which does not touch memory.
5476SDValue SelectionDAGBuilder::getTargetNonMemIntrinsicNode(
5477 const Type &IntrinsicVT, bool HasChain, ArrayRef<SDValue> Ops,
5478 const SDVTList &VTs) {
5479 if (!HasChain)
5480 return DAG.getNode(Opcode: ISD::INTRINSIC_WO_CHAIN, DL: getCurSDLoc(), VTList: VTs, Ops);
5481 if (!IntrinsicVT.isVoidTy())
5482 return DAG.getNode(Opcode: ISD::INTRINSIC_W_CHAIN, DL: getCurSDLoc(), VTList: VTs, Ops);
5483 return DAG.getNode(Opcode: ISD::INTRINSIC_VOID, DL: getCurSDLoc(), VTList: VTs, Ops);
5484}
5485
5486/// Set root, convert return type if necessary and check alignment.
5487SDValue SelectionDAGBuilder::handleTargetIntrinsicRet(const CallBase &I,
5488 bool HasChain,
5489 bool OnlyLoad,
5490 SDValue Result) {
5491 if (HasChain) {
5492 SDValue Chain = Result.getValue(R: Result.getNode()->getNumValues() - 1);
5493 if (OnlyLoad)
5494 PendingLoads.push_back(Elt: Chain);
5495 else
5496 DAG.setRoot(Chain);
5497 }
5498
5499 if (I.getType()->isVoidTy())
5500 return Result;
5501
5502 if (MaybeAlign Alignment = I.getRetAlign(); InsertAssertAlign && Alignment) {
5503 // Insert `assertalign` node if there's an alignment.
5504 Result = DAG.getAssertAlign(DL: getCurSDLoc(), V: Result, A: Alignment.valueOrOne());
5505 } else if (!isa<VectorType>(Val: I.getType())) {
5506 Result = lowerRangeToAssertZExt(DAG, I, Op: Result);
5507 }
5508
5509 return Result;
5510}
5511
5512/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
5513/// node.
5514void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
5515 unsigned Intrinsic) {
5516 auto [HasChain, OnlyLoad] = getTargetIntrinsicCallProperties(I);
5517
5518 // Infos is set by getTgtMemIntrinsic.
5519 SmallVector<TargetLowering::IntrinsicInfo> Infos;
5520 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5521 TLI.getTgtMemIntrinsic(Infos, I, MF&: DAG.getMachineFunction(), Intrinsic);
5522 // Use the first (primary) info determines the node opcode.
5523 TargetLowering::IntrinsicInfo *Info = !Infos.empty() ? &Infos[0] : nullptr;
5524
5525 SmallVector<SDValue, 8> Ops =
5526 getTargetIntrinsicOperands(I, HasChain, OnlyLoad, TgtMemIntrinsicInfo: Info);
5527 SDVTList VTs = getTargetIntrinsicVTList(I, HasChain);
5528
5529 // Propagate fast-math-flags from IR to node(s).
5530 SDNodeFlags Flags;
5531 if (auto *FPMO = dyn_cast<FPMathOperator>(Val: &I))
5532 Flags.copyFMF(FPMO: *FPMO);
5533 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
5534
5535 // Create the node.
5536 SDValue Result;
5537
5538 // In some cases, custom collection of operands from CallInst I may be needed.
5539 TLI.CollectTargetIntrinsicOperands(I, Ops, DAG);
5540 if (!Infos.empty()) {
5541 // This is target intrinsic that touches memory
5542 // Create MachineMemOperands for each memory access described by the target.
5543 MachineFunction &MF = DAG.getMachineFunction();
5544 SmallVector<MachineMemOperand *> MMOs;
5545 for (const auto &Info : Infos) {
5546 // TODO: We currently just fallback to address space 0 if
5547 // getTgtMemIntrinsic didn't yield anything useful.
5548 MachinePointerInfo MPI;
5549 if (Info.ptrVal)
5550 MPI = MachinePointerInfo(Info.ptrVal, Info.offset);
5551 else if (Info.fallbackAddressSpace)
5552 MPI = MachinePointerInfo(*Info.fallbackAddressSpace);
5553 EVT MemVT = Info.memVT;
5554 LocationSize Size = LocationSize::precise(Value: Info.size);
5555 if (Size.hasValue() && !Size.getValue())
5556 Size = LocationSize::precise(Value: MemVT.getStoreSize());
5557 Align Alignment = Info.align.value_or(u: DAG.getEVTAlign(MemoryVT: MemVT));
5558 MachineMemOperand *MMO = MF.getMachineMemOperand(
5559 PtrInfo: MPI, F: Info.flags, Size, BaseAlignment: Alignment, AAInfo: I.getAAMetadata(),
5560 /*Ranges=*/nullptr, SSID: Info.ssid, Ordering: Info.order, FailureOrdering: Info.failureOrder);
5561 MMOs.push_back(Elt: MMO);
5562 }
5563
5564 Result = DAG.getMemIntrinsicNode(Opcode: Info->opc, dl: getCurSDLoc(), VTList: VTs, Ops,
5565 MemVT: Info->memVT, MMOs);
5566 } else {
5567 Result = getTargetNonMemIntrinsicNode(IntrinsicVT: *I.getType(), HasChain, Ops, VTs);
5568 }
5569
5570 Result = handleTargetIntrinsicRet(I, HasChain, OnlyLoad, Result);
5571
5572 setValue(V: &I, NewN: Result);
5573}
5574
5575/// GetSignificand - Get the significand and build it into a floating-point
5576/// number with exponent of 1:
5577///
5578/// Op = (Op & 0x007fffff) | 0x3f800000;
5579///
5580/// where Op is the hexadecimal representation of floating point value.
5581static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) {
5582 SDValue t1 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: MVT::i32, N1: Op,
5583 N2: DAG.getConstant(Val: 0x007fffff, DL: dl, VT: MVT::i32));
5584 SDValue t2 = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: MVT::i32, N1: t1,
5585 N2: DAG.getConstant(Val: 0x3f800000, DL: dl, VT: MVT::i32));
5586 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32, Operand: t2);
5587}
5588
5589/// GetExponent - Get the exponent:
5590///
5591/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
5592///
5593/// where Op is the hexadecimal representation of floating point value.
5594static SDValue GetExponent(SelectionDAG &DAG, SDValue Op,
5595 const TargetLowering &TLI, const SDLoc &dl) {
5596 SDValue t0 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: MVT::i32, N1: Op,
5597 N2: DAG.getConstant(Val: 0x7f800000, DL: dl, VT: MVT::i32));
5598 SDValue t1 = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: MVT::i32, N1: t0,
5599 N2: DAG.getShiftAmountConstant(Val: 23, VT: MVT::i32, DL: dl));
5600 SDValue t2 = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: MVT::i32, N1: t1,
5601 N2: DAG.getConstant(Val: 127, DL: dl, VT: MVT::i32));
5602 return DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: MVT::f32, Operand: t2);
5603}
5604
5605/// getF32Constant - Get 32-bit floating point constant.
5606static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
5607 const SDLoc &dl) {
5608 return DAG.getConstantFP(Val: APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), DL: dl,
5609 VT: MVT::f32);
5610}
5611
5612static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl,
5613 SelectionDAG &DAG) {
5614 // TODO: What fast-math-flags should be set on the floating-point nodes?
5615
5616 // IntegerPartOfX = ((int32_t)(t0);
5617 SDValue IntegerPartOfX = DAG.getNode(Opcode: ISD::FP_TO_SINT, DL: dl, VT: MVT::i32, Operand: t0);
5618
5619 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
5620 SDValue t1 = DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: MVT::f32, Operand: IntegerPartOfX);
5621 SDValue X = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t0, N2: t1);
5622
5623 // IntegerPartOfX <<= 23;
5624 IntegerPartOfX = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: MVT::i32, N1: IntegerPartOfX,
5625 N2: DAG.getShiftAmountConstant(Val: 23, VT: MVT::i32, DL: dl));
5626
5627 SDValue TwoToFractionalPartOfX;
5628 if (LimitFloatPrecision <= 6) {
5629 // For floating-point precision of 6:
5630 //
5631 // TwoToFractionalPartOfX =
5632 // 0.997535578f +
5633 // (0.735607626f + 0.252464424f * x) * x;
5634 //
5635 // error 0.0144103317, which is 6 bits
5636 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5637 N2: getF32Constant(DAG, Flt: 0x3e814304, dl));
5638 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
5639 N2: getF32Constant(DAG, Flt: 0x3f3c50c8, dl));
5640 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5641 TwoToFractionalPartOfX = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5642 N2: getF32Constant(DAG, Flt: 0x3f7f5e7e, dl));
5643 } else if (LimitFloatPrecision <= 12) {
5644 // For floating-point precision of 12:
5645 //
5646 // TwoToFractionalPartOfX =
5647 // 0.999892986f +
5648 // (0.696457318f +
5649 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
5650 //
5651 // error 0.000107046256, which is 13 to 14 bits
5652 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5653 N2: getF32Constant(DAG, Flt: 0x3da235e3, dl));
5654 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
5655 N2: getF32Constant(DAG, Flt: 0x3e65b8f3, dl));
5656 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5657 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5658 N2: getF32Constant(DAG, Flt: 0x3f324b07, dl));
5659 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5660 TwoToFractionalPartOfX = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t6,
5661 N2: getF32Constant(DAG, Flt: 0x3f7ff8fd, dl));
5662 } else { // LimitFloatPrecision <= 18
5663 // For floating-point precision of 18:
5664 //
5665 // TwoToFractionalPartOfX =
5666 // 0.999999982f +
5667 // (0.693148872f +
5668 // (0.240227044f +
5669 // (0.554906021e-1f +
5670 // (0.961591928e-2f +
5671 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
5672 // error 2.47208000*10^(-7), which is better than 18 bits
5673 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5674 N2: getF32Constant(DAG, Flt: 0x3924b03e, dl));
5675 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
5676 N2: getF32Constant(DAG, Flt: 0x3ab24b87, dl));
5677 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5678 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5679 N2: getF32Constant(DAG, Flt: 0x3c1d8c17, dl));
5680 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5681 SDValue t7 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t6,
5682 N2: getF32Constant(DAG, Flt: 0x3d634a1d, dl));
5683 SDValue t8 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t7, N2: X);
5684 SDValue t9 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t8,
5685 N2: getF32Constant(DAG, Flt: 0x3e75fe14, dl));
5686 SDValue t10 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t9, N2: X);
5687 SDValue t11 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t10,
5688 N2: getF32Constant(DAG, Flt: 0x3f317234, dl));
5689 SDValue t12 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t11, N2: X);
5690 TwoToFractionalPartOfX = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t12,
5691 N2: getF32Constant(DAG, Flt: 0x3f800000, dl));
5692 }
5693
5694 // Add the exponent into the result in integer domain.
5695 SDValue t13 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: TwoToFractionalPartOfX);
5696 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32,
5697 Operand: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: t13, N2: IntegerPartOfX));
5698}
5699
5700/// expandExp - Lower an exp intrinsic. Handles the special sequences for
5701/// limited-precision mode.
5702static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5703 const TargetLowering &TLI, SDNodeFlags Flags) {
5704 if (Op.getValueType() == MVT::f32 &&
5705 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5706
5707 // Put the exponent in the right bit position for later addition to the
5708 // final result:
5709 //
5710 // t0 = Op * log2(e)
5711
5712 // TODO: What fast-math-flags should be set here?
5713 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: Op,
5714 N2: DAG.getConstantFP(Val: numbers::log2ef, DL: dl, VT: MVT::f32));
5715 return getLimitedPrecisionExp2(t0, dl, DAG);
5716 }
5717
5718 // No special expansion.
5719 return DAG.getNode(Opcode: ISD::FEXP, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
5720}
5721
5722/// expandLog - Lower a log intrinsic. Handles the special sequences for
5723/// limited-precision mode.
5724static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5725 const TargetLowering &TLI, SDNodeFlags Flags) {
5726 // TODO: What fast-math-flags should be set on the floating-point nodes?
5727
5728 if (Op.getValueType() == MVT::f32 &&
5729 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5730 SDValue Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Op);
5731
5732 // Scale the exponent by log(2).
5733 SDValue Exp = GetExponent(DAG, Op: Op1, TLI, dl);
5734 SDValue LogOfExponent =
5735 DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: Exp,
5736 N2: DAG.getConstantFP(Val: numbers::ln2f, DL: dl, VT: MVT::f32));
5737
5738 // Get the significand and build it into a floating-point number with
5739 // exponent of 1.
5740 SDValue X = GetSignificand(DAG, Op: Op1, dl);
5741
5742 SDValue LogOfMantissa;
5743 if (LimitFloatPrecision <= 6) {
5744 // For floating-point precision of 6:
5745 //
5746 // LogofMantissa =
5747 // -1.1609546f +
5748 // (1.4034025f - 0.23903021f * x) * x;
5749 //
5750 // error 0.0034276066, which is better than 8 bits
5751 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5752 N2: getF32Constant(DAG, Flt: 0xbe74c456, dl));
5753 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5754 N2: getF32Constant(DAG, Flt: 0x3fb3a2b1, dl));
5755 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5756 LogOfMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5757 N2: getF32Constant(DAG, Flt: 0x3f949a29, dl));
5758 } else if (LimitFloatPrecision <= 12) {
5759 // For floating-point precision of 12:
5760 //
5761 // LogOfMantissa =
5762 // -1.7417939f +
5763 // (2.8212026f +
5764 // (-1.4699568f +
5765 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
5766 //
5767 // error 0.000061011436, which is 14 bits
5768 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5769 N2: getF32Constant(DAG, Flt: 0xbd67b6d6, dl));
5770 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5771 N2: getF32Constant(DAG, Flt: 0x3ee4f4b8, dl));
5772 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5773 SDValue t3 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5774 N2: getF32Constant(DAG, Flt: 0x3fbc278b, dl));
5775 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5776 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5777 N2: getF32Constant(DAG, Flt: 0x40348e95, dl));
5778 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5779 LogOfMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t6,
5780 N2: getF32Constant(DAG, Flt: 0x3fdef31a, dl));
5781 } else { // LimitFloatPrecision <= 18
5782 // For floating-point precision of 18:
5783 //
5784 // LogOfMantissa =
5785 // -2.1072184f +
5786 // (4.2372794f +
5787 // (-3.7029485f +
5788 // (2.2781945f +
5789 // (-0.87823314f +
5790 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
5791 //
5792 // error 0.0000023660568, which is better than 18 bits
5793 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5794 N2: getF32Constant(DAG, Flt: 0xbc91e5ac, dl));
5795 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5796 N2: getF32Constant(DAG, Flt: 0x3e4350aa, dl));
5797 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5798 SDValue t3 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5799 N2: getF32Constant(DAG, Flt: 0x3f60d3e3, dl));
5800 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5801 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5802 N2: getF32Constant(DAG, Flt: 0x4011cdf0, dl));
5803 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5804 SDValue t7 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t6,
5805 N2: getF32Constant(DAG, Flt: 0x406cfd1c, dl));
5806 SDValue t8 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t7, N2: X);
5807 SDValue t9 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t8,
5808 N2: getF32Constant(DAG, Flt: 0x408797cb, dl));
5809 SDValue t10 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t9, N2: X);
5810 LogOfMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t10,
5811 N2: getF32Constant(DAG, Flt: 0x4006dcab, dl));
5812 }
5813
5814 return DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: LogOfExponent, N2: LogOfMantissa);
5815 }
5816
5817 // No special expansion.
5818 return DAG.getNode(Opcode: ISD::FLOG, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
5819}
5820
5821/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
5822/// limited-precision mode.
5823static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5824 const TargetLowering &TLI, SDNodeFlags Flags) {
5825 // TODO: What fast-math-flags should be set on the floating-point nodes?
5826
5827 if (Op.getValueType() == MVT::f32 &&
5828 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5829 SDValue Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Op);
5830
5831 // Get the exponent.
5832 SDValue LogOfExponent = GetExponent(DAG, Op: Op1, TLI, dl);
5833
5834 // Get the significand and build it into a floating-point number with
5835 // exponent of 1.
5836 SDValue X = GetSignificand(DAG, Op: Op1, dl);
5837
5838 // Different possible minimax approximations of significand in
5839 // floating-point for various degrees of accuracy over [1,2].
5840 SDValue Log2ofMantissa;
5841 if (LimitFloatPrecision <= 6) {
5842 // For floating-point precision of 6:
5843 //
5844 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
5845 //
5846 // error 0.0049451742, which is more than 7 bits
5847 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5848 N2: getF32Constant(DAG, Flt: 0xbeb08fe0, dl));
5849 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5850 N2: getF32Constant(DAG, Flt: 0x40019463, dl));
5851 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5852 Log2ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5853 N2: getF32Constant(DAG, Flt: 0x3fd6633d, dl));
5854 } else if (LimitFloatPrecision <= 12) {
5855 // For floating-point precision of 12:
5856 //
5857 // Log2ofMantissa =
5858 // -2.51285454f +
5859 // (4.07009056f +
5860 // (-2.12067489f +
5861 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
5862 //
5863 // error 0.0000876136000, which is better than 13 bits
5864 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5865 N2: getF32Constant(DAG, Flt: 0xbda7262e, dl));
5866 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5867 N2: getF32Constant(DAG, Flt: 0x3f25280b, dl));
5868 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5869 SDValue t3 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5870 N2: getF32Constant(DAG, Flt: 0x4007b923, dl));
5871 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5872 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5873 N2: getF32Constant(DAG, Flt: 0x40823e2f, dl));
5874 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5875 Log2ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t6,
5876 N2: getF32Constant(DAG, Flt: 0x4020d29c, dl));
5877 } else { // LimitFloatPrecision <= 18
5878 // For floating-point precision of 18:
5879 //
5880 // Log2ofMantissa =
5881 // -3.0400495f +
5882 // (6.1129976f +
5883 // (-5.3420409f +
5884 // (3.2865683f +
5885 // (-1.2669343f +
5886 // (0.27515199f -
5887 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
5888 //
5889 // error 0.0000018516, which is better than 18 bits
5890 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5891 N2: getF32Constant(DAG, Flt: 0xbcd2769e, dl));
5892 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5893 N2: getF32Constant(DAG, Flt: 0x3e8ce0b9, dl));
5894 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5895 SDValue t3 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5896 N2: getF32Constant(DAG, Flt: 0x3fa22ae7, dl));
5897 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5898 SDValue t5 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t4,
5899 N2: getF32Constant(DAG, Flt: 0x40525723, dl));
5900 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5901 SDValue t7 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t6,
5902 N2: getF32Constant(DAG, Flt: 0x40aaf200, dl));
5903 SDValue t8 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t7, N2: X);
5904 SDValue t9 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t8,
5905 N2: getF32Constant(DAG, Flt: 0x40c39dad, dl));
5906 SDValue t10 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t9, N2: X);
5907 Log2ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t10,
5908 N2: getF32Constant(DAG, Flt: 0x4042902c, dl));
5909 }
5910
5911 return DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: LogOfExponent, N2: Log2ofMantissa);
5912 }
5913
5914 // No special expansion.
5915 return DAG.getNode(Opcode: ISD::FLOG2, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
5916}
5917
5918/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
5919/// limited-precision mode.
5920static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5921 const TargetLowering &TLI, SDNodeFlags Flags) {
5922 // TODO: What fast-math-flags should be set on the floating-point nodes?
5923
5924 if (Op.getValueType() == MVT::f32 &&
5925 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5926 SDValue Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Op);
5927
5928 // Scale the exponent by log10(2) [0.30102999f].
5929 SDValue Exp = GetExponent(DAG, Op: Op1, TLI, dl);
5930 SDValue LogOfExponent = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: Exp,
5931 N2: getF32Constant(DAG, Flt: 0x3e9a209a, dl));
5932
5933 // Get the significand and build it into a floating-point number with
5934 // exponent of 1.
5935 SDValue X = GetSignificand(DAG, Op: Op1, dl);
5936
5937 SDValue Log10ofMantissa;
5938 if (LimitFloatPrecision <= 6) {
5939 // For floating-point precision of 6:
5940 //
5941 // Log10ofMantissa =
5942 // -0.50419619f +
5943 // (0.60948995f - 0.10380950f * x) * x;
5944 //
5945 // error 0.0014886165, which is 6 bits
5946 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5947 N2: getF32Constant(DAG, Flt: 0xbdd49a13, dl));
5948 SDValue t1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t0,
5949 N2: getF32Constant(DAG, Flt: 0x3f1c0789, dl));
5950 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5951 Log10ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t2,
5952 N2: getF32Constant(DAG, Flt: 0x3f011300, dl));
5953 } else if (LimitFloatPrecision <= 12) {
5954 // For floating-point precision of 12:
5955 //
5956 // Log10ofMantissa =
5957 // -0.64831180f +
5958 // (0.91751397f +
5959 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
5960 //
5961 // error 0.00019228036, which is better than 12 bits
5962 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5963 N2: getF32Constant(DAG, Flt: 0x3d431f31, dl));
5964 SDValue t1 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t0,
5965 N2: getF32Constant(DAG, Flt: 0x3ea21fb2, dl));
5966 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5967 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
5968 N2: getF32Constant(DAG, Flt: 0x3f6ae232, dl));
5969 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5970 Log10ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t4,
5971 N2: getF32Constant(DAG, Flt: 0x3f25f7c3, dl));
5972 } else { // LimitFloatPrecision <= 18
5973 // For floating-point precision of 18:
5974 //
5975 // Log10ofMantissa =
5976 // -0.84299375f +
5977 // (1.5327582f +
5978 // (-1.0688956f +
5979 // (0.49102474f +
5980 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
5981 //
5982 // error 0.0000037995730, which is better than 18 bits
5983 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: X,
5984 N2: getF32Constant(DAG, Flt: 0x3c5d51ce, dl));
5985 SDValue t1 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t0,
5986 N2: getF32Constant(DAG, Flt: 0x3e00685a, dl));
5987 SDValue t2 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t1, N2: X);
5988 SDValue t3 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t2,
5989 N2: getF32Constant(DAG, Flt: 0x3efb6798, dl));
5990 SDValue t4 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t3, N2: X);
5991 SDValue t5 = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t4,
5992 N2: getF32Constant(DAG, Flt: 0x3f88d192, dl));
5993 SDValue t6 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t5, N2: X);
5994 SDValue t7 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: t6,
5995 N2: getF32Constant(DAG, Flt: 0x3fc4316c, dl));
5996 SDValue t8 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: t7, N2: X);
5997 Log10ofMantissa = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f32, N1: t8,
5998 N2: getF32Constant(DAG, Flt: 0x3f57ce70, dl));
5999 }
6000
6001 return DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: MVT::f32, N1: LogOfExponent, N2: Log10ofMantissa);
6002 }
6003
6004 // No special expansion.
6005 return DAG.getNode(Opcode: ISD::FLOG10, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
6006}
6007
6008/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
6009/// limited-precision mode.
6010static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
6011 const TargetLowering &TLI, SDNodeFlags Flags) {
6012 if (Op.getValueType() == MVT::f32 &&
6013 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
6014 return getLimitedPrecisionExp2(t0: Op, dl, DAG);
6015
6016 // No special expansion.
6017 return DAG.getNode(Opcode: ISD::FEXP2, DL: dl, VT: Op.getValueType(), Operand: Op, Flags);
6018}
6019
6020/// visitPow - Lower a pow intrinsic. Handles the special sequences for
6021/// limited-precision mode with x == 10.0f.
6022static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS,
6023 SelectionDAG &DAG, const TargetLowering &TLI,
6024 SDNodeFlags Flags) {
6025 bool IsExp10 = false;
6026 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
6027 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
6028 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(Val&: LHS)) {
6029 APFloat Ten(10.0f);
6030 IsExp10 = LHSC->isExactlyValue(V: Ten);
6031 }
6032 }
6033
6034 // TODO: What fast-math-flags should be set on the FMUL node?
6035 if (IsExp10) {
6036 // Put the exponent in the right bit position for later addition to the
6037 // final result:
6038 //
6039 // #define LOG2OF10 3.3219281f
6040 // t0 = Op * LOG2OF10;
6041 SDValue t0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT: MVT::f32, N1: RHS,
6042 N2: getF32Constant(DAG, Flt: 0x40549a78, dl));
6043 return getLimitedPrecisionExp2(t0, dl, DAG);
6044 }
6045
6046 // No special expansion.
6047 return DAG.getNode(Opcode: ISD::FPOW, DL: dl, VT: LHS.getValueType(), N1: LHS, N2: RHS, Flags);
6048}
6049
6050/// ExpandPowI - Expand a llvm.powi intrinsic.
6051static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
6052 SelectionDAG &DAG) {
6053 // If RHS is a constant, we can expand this out to a multiplication tree if
6054 // it's beneficial on the target, otherwise we end up lowering to a call to
6055 // __powidf2 (for example).
6056 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Val&: RHS)) {
6057 unsigned Val = RHSC->getSExtValue();
6058
6059 // powi(x, 0) -> 1.0
6060 if (Val == 0)
6061 return DAG.getConstantFP(Val: 1.0, DL, VT: LHS.getValueType());
6062
6063 if (DAG.getTargetLoweringInfo().isBeneficialToExpandPowI(
6064 Exponent: Val, OptForSize: DAG.shouldOptForSize())) {
6065 // Get the exponent as a positive value.
6066 if ((int)Val < 0)
6067 Val = -Val;
6068 // We use the simple binary decomposition method to generate the multiply
6069 // sequence. There are more optimal ways to do this (for example,
6070 // powi(x,15) generates one more multiply than it should), but this has
6071 // the benefit of being both really simple and much better than a libcall.
6072 SDValue Res; // Logically starts equal to 1.0
6073 SDValue CurSquare = LHS;
6074 // TODO: Intrinsics should have fast-math-flags that propagate to these
6075 // nodes.
6076 while (Val) {
6077 if (Val & 1) {
6078 if (Res.getNode())
6079 Res =
6080 DAG.getNode(Opcode: ISD::FMUL, DL, VT: Res.getValueType(), N1: Res, N2: CurSquare);
6081 else
6082 Res = CurSquare; // 1.0*CurSquare.
6083 }
6084
6085 CurSquare = DAG.getNode(Opcode: ISD::FMUL, DL, VT: CurSquare.getValueType(),
6086 N1: CurSquare, N2: CurSquare);
6087 Val >>= 1;
6088 }
6089
6090 // If the original was negative, invert the result, producing 1/(x*x*x).
6091 if (RHSC->getSExtValue() < 0)
6092 Res = DAG.getNode(Opcode: ISD::FDIV, DL, VT: LHS.getValueType(),
6093 N1: DAG.getConstantFP(Val: 1.0, DL, VT: LHS.getValueType()), N2: Res);
6094 return Res;
6095 }
6096 }
6097
6098 // Otherwise, expand to a libcall.
6099 return DAG.getNode(Opcode: ISD::FPOWI, DL, VT: LHS.getValueType(), N1: LHS, N2: RHS);
6100}
6101
6102static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL,
6103 SDValue LHS, SDValue RHS, SDValue Scale,
6104 SelectionDAG &DAG, const TargetLowering &TLI) {
6105 EVT VT = LHS.getValueType();
6106 bool Signed = Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT;
6107 bool Saturating = Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIXSAT;
6108 LLVMContext &Ctx = *DAG.getContext();
6109
6110 // If the type is legal but the operation isn't, this node might survive all
6111 // the way to operation legalization. If we end up there and we do not have
6112 // the ability to widen the type (if VT*2 is not legal), we cannot expand the
6113 // node.
6114
6115 // Coax the legalizer into expanding the node during type legalization instead
6116 // by bumping the size by one bit. This will force it to Promote, enabling the
6117 // early expansion and avoiding the need to expand later.
6118
6119 // We don't have to do this if Scale is 0; that can always be expanded, unless
6120 // it's a saturating signed operation. Those can experience true integer
6121 // division overflow, a case which we must avoid.
6122
6123 // FIXME: We wouldn't have to do this (or any of the early
6124 // expansion/promotion) if it was possible to expand a libcall of an
6125 // illegal type during operation legalization. But it's not, so things
6126 // get a bit hacky.
6127 unsigned ScaleInt = Scale->getAsZExtVal();
6128 if ((ScaleInt > 0 || (Saturating && Signed)) &&
6129 (TLI.isTypeLegal(VT) ||
6130 (VT.isVector() && TLI.isTypeLegal(VT: VT.getVectorElementType())))) {
6131 TargetLowering::LegalizeAction Action = TLI.getFixedPointOperationAction(
6132 Op: Opcode, VT, Scale: ScaleInt);
6133 if (Action != TargetLowering::Legal && Action != TargetLowering::Custom) {
6134 EVT PromVT;
6135 if (VT.isScalarInteger())
6136 PromVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: VT.getSizeInBits() + 1);
6137 else if (VT.isVector()) {
6138 PromVT = VT.getVectorElementType();
6139 PromVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: PromVT.getSizeInBits() + 1);
6140 PromVT = EVT::getVectorVT(Context&: Ctx, VT: PromVT, EC: VT.getVectorElementCount());
6141 } else
6142 llvm_unreachable("Wrong VT for DIVFIX?");
6143 LHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: LHS, DL, VT: PromVT);
6144 RHS = DAG.getExtOrTrunc(IsSigned: Signed, Op: RHS, DL, VT: PromVT);
6145 EVT ShiftTy = TLI.getShiftAmountTy(LHSTy: PromVT, DL: DAG.getDataLayout());
6146 // For saturating operations, we need to shift up the LHS to get the
6147 // proper saturation width, and then shift down again afterwards.
6148 if (Saturating)
6149 LHS = DAG.getNode(Opcode: ISD::SHL, DL, VT: PromVT, N1: LHS,
6150 N2: DAG.getConstant(Val: 1, DL, VT: ShiftTy));
6151 SDValue Res = DAG.getNode(Opcode, DL, VT: PromVT, N1: LHS, N2: RHS, N3: Scale);
6152 if (Saturating)
6153 Res = DAG.getNode(Opcode: Signed ? ISD::SRA : ISD::SRL, DL, VT: PromVT, N1: Res,
6154 N2: DAG.getConstant(Val: 1, DL, VT: ShiftTy));
6155 return DAG.getZExtOrTrunc(Op: Res, DL, VT);
6156 }
6157 }
6158
6159 return DAG.getNode(Opcode, DL, VT, N1: LHS, N2: RHS, N3: Scale);
6160}
6161
6162// getUnderlyingArgRegs - Find underlying registers used for a truncated,
6163// bitcasted, or split argument. Returns a list of <Register, size in bits>
6164static void
6165getUnderlyingArgRegs(SmallVectorImpl<std::pair<Register, TypeSize>> &Regs,
6166 const SDValue &N) {
6167 switch (N.getOpcode()) {
6168 case ISD::CopyFromReg: {
6169 SDValue Op = N.getOperand(i: 1);
6170 Regs.emplace_back(Args: cast<RegisterSDNode>(Val&: Op)->getReg(),
6171 Args: Op.getValueType().getSizeInBits());
6172 return;
6173 }
6174 case ISD::BITCAST:
6175 case ISD::AssertZext:
6176 case ISD::AssertSext:
6177 case ISD::TRUNCATE:
6178 getUnderlyingArgRegs(Regs, N: N.getOperand(i: 0));
6179 return;
6180 case ISD::BUILD_PAIR:
6181 case ISD::BUILD_VECTOR:
6182 case ISD::CONCAT_VECTORS:
6183 for (SDValue Op : N->op_values())
6184 getUnderlyingArgRegs(Regs, N: Op);
6185 return;
6186 default:
6187 return;
6188 }
6189}
6190
6191/// If the DbgValueInst is a dbg_value of a function argument, create the
6192/// corresponding DBG_VALUE machine instruction for it now. At the end of
6193/// instruction selection, they will be inserted to the entry BB.
6194/// We don't currently support this for variadic dbg_values, as they shouldn't
6195/// appear for function arguments or in the prologue.
6196bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
6197 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
6198 DILocation *DL, FuncArgumentDbgValueKind Kind, const SDValue &N) {
6199 const Argument *Arg = dyn_cast<Argument>(Val: V);
6200 if (!Arg)
6201 return false;
6202
6203 MachineFunction &MF = DAG.getMachineFunction();
6204 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
6205
6206 // Helper to create DBG_INSTR_REFs or DBG_VALUEs, depending on what kind
6207 // we've been asked to pursue.
6208 auto MakeVRegDbgValue = [&](Register Reg, DIExpression *FragExpr,
6209 bool Indirect) {
6210 if (Reg.isVirtual() && MF.useDebugInstrRef()) {
6211 // For VRegs, in instruction referencing mode, create a DBG_INSTR_REF
6212 // pointing at the VReg, which will be patched up later.
6213 auto &Inst = TII->get(Opcode: TargetOpcode::DBG_INSTR_REF);
6214 SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg(
6215 /* Reg */ Reg, /* isDef */ false, /* isImp */ false,
6216 /* isKill */ false, /* isDead */ false,
6217 /* isUndef */ false, /* isEarlyClobber */ false,
6218 /* SubReg */ 0, /* isDebug */ true)});
6219
6220 auto *NewDIExpr = FragExpr;
6221 // We don't have an "Indirect" field in DBG_INSTR_REF, fold that into
6222 // the DIExpression.
6223 if (Indirect)
6224 NewDIExpr = DIExpression::prepend(Expr: FragExpr, Flags: DIExpression::DerefBefore);
6225 SmallVector<uint64_t, 2> Ops({dwarf::DW_OP_LLVM_arg, 0});
6226 NewDIExpr = DIExpression::prependOpcodes(Expr: NewDIExpr, Ops);
6227 return BuildMI(MF, DL, MCID: Inst, IsIndirect: false, MOs, Variable, Expr: NewDIExpr);
6228 } else {
6229 // Create a completely standard DBG_VALUE.
6230 auto &Inst = TII->get(Opcode: TargetOpcode::DBG_VALUE);
6231 return BuildMI(MF, DL, MCID: Inst, IsIndirect: Indirect, Reg, Variable, Expr: FragExpr);
6232 }
6233 };
6234
6235 if (Kind == FuncArgumentDbgValueKind::Value) {
6236 // ArgDbgValues are hoisted to the beginning of the entry block. So we
6237 // should only emit as ArgDbgValue if the dbg.value intrinsic is found in
6238 // the entry block.
6239 bool IsInEntryBlock = FuncInfo.MBB == &FuncInfo.MF->front();
6240 if (!IsInEntryBlock)
6241 return false;
6242
6243 // ArgDbgValues are hoisted to the beginning of the entry block. So we
6244 // should only emit as ArgDbgValue if the dbg.value intrinsic describes a
6245 // variable that also is a param.
6246 //
6247 // Although, if we are at the top of the entry block already, we can still
6248 // emit using ArgDbgValue. This might catch some situations when the
6249 // dbg.value refers to an argument that isn't used in the entry block, so
6250 // any CopyToReg node would be optimized out and the only way to express
6251 // this DBG_VALUE is by using the physical reg (or FI) as done in this
6252 // method. ArgDbgValues are hoisted to the beginning of the entry block. So
6253 // we should only emit as ArgDbgValue if the Variable is an argument to the
6254 // current function, and the dbg.value intrinsic is found in the entry
6255 // block.
6256 bool VariableIsFunctionInputArg = Variable->isParameter() &&
6257 !DL->getInlinedAt();
6258 bool IsInPrologue = SDNodeOrder == LowestSDNodeOrder;
6259 if (!IsInPrologue && !VariableIsFunctionInputArg)
6260 return false;
6261
6262 // Here we assume that a function argument on IR level only can be used to
6263 // describe one input parameter on source level. If we for example have
6264 // source code like this
6265 //
6266 // struct A { long x, y; };
6267 // void foo(struct A a, long b) {
6268 // ...
6269 // b = a.x;
6270 // ...
6271 // }
6272 //
6273 // and IR like this
6274 //
6275 // define void @foo(i32 %a1, i32 %a2, i32 %b) {
6276 // entry:
6277 // call void @llvm.dbg.value(metadata i32 %a1, "a", DW_OP_LLVM_fragment
6278 // call void @llvm.dbg.value(metadata i32 %a2, "a", DW_OP_LLVM_fragment
6279 // call void @llvm.dbg.value(metadata i32 %b, "b",
6280 // ...
6281 // call void @llvm.dbg.value(metadata i32 %a1, "b"
6282 // ...
6283 //
6284 // then the last dbg.value is describing a parameter "b" using a value that
6285 // is an argument. But since we already has used %a1 to describe a parameter
6286 // we should not handle that last dbg.value here (that would result in an
6287 // incorrect hoisting of the DBG_VALUE to the function entry).
6288 // Notice that we allow one dbg.value per IR level argument, to accommodate
6289 // for the situation with fragments above.
6290 // If there is no node for the value being handled, we return true to skip
6291 // the normal generation of debug info, as it would kill existing debug
6292 // info for the parameter in case of duplicates.
6293 if (VariableIsFunctionInputArg) {
6294 unsigned ArgNo = Arg->getArgNo();
6295 if (ArgNo >= FuncInfo.DescribedArgs.size())
6296 FuncInfo.DescribedArgs.resize(N: ArgNo + 1, t: false);
6297 else if (!IsInPrologue && FuncInfo.DescribedArgs.test(Idx: ArgNo))
6298 return !NodeMap[V].getNode();
6299 FuncInfo.DescribedArgs.set(ArgNo);
6300 }
6301 }
6302
6303 bool IsIndirect = false;
6304 std::optional<MachineOperand> Op;
6305 // Some arguments' frame index is recorded during argument lowering.
6306 int FI = FuncInfo.getArgumentFrameIndex(A: Arg);
6307 if (FI != std::numeric_limits<int>::max())
6308 Op = MachineOperand::CreateFI(Idx: FI);
6309
6310 SmallVector<std::pair<Register, TypeSize>, 8> ArgRegsAndSizes;
6311 if (!Op && N.getNode()) {
6312 getUnderlyingArgRegs(Regs&: ArgRegsAndSizes, N);
6313 Register Reg;
6314 if (ArgRegsAndSizes.size() == 1)
6315 Reg = ArgRegsAndSizes.front().first;
6316
6317 if (Reg && Reg.isVirtual()) {
6318 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6319 Register PR = RegInfo.getLiveInPhysReg(VReg: Reg);
6320 if (PR)
6321 Reg = PR;
6322 }
6323 if (Reg) {
6324 Op = MachineOperand::CreateReg(Reg, isDef: false);
6325 IsIndirect = Kind != FuncArgumentDbgValueKind::Value;
6326 }
6327 }
6328
6329 if (!Op && N.getNode()) {
6330 // Check if frame index is available.
6331 SDValue LCandidate = peekThroughBitcasts(V: N);
6332 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(Val: LCandidate.getNode()))
6333 if (FrameIndexSDNode *FINode =
6334 dyn_cast<FrameIndexSDNode>(Val: LNode->getBasePtr().getNode()))
6335 Op = MachineOperand::CreateFI(Idx: FINode->getIndex());
6336 }
6337
6338 if (!Op) {
6339 // Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg
6340 auto splitMultiRegDbgValue =
6341 [&](ArrayRef<std::pair<Register, TypeSize>> SplitRegs) -> bool {
6342 unsigned Offset = 0;
6343 for (const auto &[Reg, RegSizeInBits] : SplitRegs) {
6344 // FIXME: Scalable sizes are not supported in fragment expressions.
6345 if (RegSizeInBits.isScalable())
6346 return false;
6347
6348 // If the expression is already a fragment, the current register
6349 // offset+size might extend beyond the fragment. In this case, only
6350 // the register bits that are inside the fragment are relevant.
6351 int RegFragmentSizeInBits = RegSizeInBits.getFixedValue();
6352 if (auto ExprFragmentInfo = Expr->getFragmentInfo()) {
6353 uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits;
6354 // The register is entirely outside the expression fragment,
6355 // so is irrelevant for debug info.
6356 if (Offset >= ExprFragmentSizeInBits)
6357 break;
6358 // The register is partially outside the expression fragment, only
6359 // the low bits within the fragment are relevant for debug info.
6360 if (Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) {
6361 RegFragmentSizeInBits = ExprFragmentSizeInBits - Offset;
6362 }
6363 }
6364
6365 auto FragmentExpr = DIExpression::createFragmentExpression(
6366 Expr, OffsetInBits: Offset, SizeInBits: RegFragmentSizeInBits);
6367 Offset += RegSizeInBits.getFixedValue();
6368 // If a valid fragment expression cannot be created, the variable's
6369 // correct value cannot be determined and so it is set as poison.
6370 if (!FragmentExpr) {
6371 SDDbgValue *SDV = DAG.getConstantDbgValue(
6372 Var: Variable, Expr, C: PoisonValue::get(T: V->getType()), DL, O: SDNodeOrder);
6373 DAG.AddDbgValue(DB: SDV, isParameter: false);
6374 continue;
6375 }
6376 MachineInstr *NewMI = MakeVRegDbgValue(
6377 Reg, *FragmentExpr, Kind != FuncArgumentDbgValueKind::Value);
6378 FuncInfo.ArgDbgValues.push_back(Elt: NewMI);
6379 }
6380
6381 return true;
6382 };
6383
6384 // Check if ValueMap has reg number.
6385 DenseMap<const Value *, Register>::const_iterator
6386 VMI = FuncInfo.ValueMap.find(Val: V);
6387 if (VMI != FuncInfo.ValueMap.end()) {
6388 const auto &TLI = DAG.getTargetLoweringInfo();
6389 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second,
6390 V->getType(), std::nullopt);
6391 if (RFV.occupiesMultipleRegs())
6392 return splitMultiRegDbgValue(RFV.getRegsAndSizes());
6393
6394 Op = MachineOperand::CreateReg(Reg: VMI->second, isDef: false);
6395 IsIndirect = Kind != FuncArgumentDbgValueKind::Value;
6396 } else if (ArgRegsAndSizes.size() > 1) {
6397 // This was split due to the calling convention, and no virtual register
6398 // mapping exists for the value.
6399 return splitMultiRegDbgValue(ArgRegsAndSizes);
6400 }
6401 }
6402
6403 if (!Op)
6404 return false;
6405
6406 assert(Variable->isValidLocationForIntrinsic(DL) &&
6407 "Expected inlined-at fields to agree");
6408 MachineInstr *NewMI = nullptr;
6409
6410 if (Op->isReg())
6411 NewMI = MakeVRegDbgValue(Op->getReg(), Expr, IsIndirect);
6412 else
6413 NewMI = BuildMI(MF, DL, MCID: TII->get(Opcode: TargetOpcode::DBG_VALUE), IsIndirect: true, MOs: *Op,
6414 Variable, Expr);
6415
6416 // Otherwise, use ArgDbgValues.
6417 FuncInfo.ArgDbgValues.push_back(Elt: NewMI);
6418 return true;
6419}
6420
6421/// Return the appropriate SDDbgValue based on N.
6422SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N,
6423 DILocalVariable *Variable,
6424 DIExpression *Expr,
6425 const DebugLoc &dl,
6426 unsigned DbgSDNodeOrder) {
6427 if (auto *FISDN = dyn_cast<FrameIndexSDNode>(Val: N.getNode())) {
6428 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe
6429 // stack slot locations.
6430 //
6431 // Consider "int x = 0; int *px = &x;". There are two kinds of interesting
6432 // debug values here after optimization:
6433 //
6434 // dbg.value(i32* %px, !"int *px", !DIExpression()), and
6435 // dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref))
6436 //
6437 // Both describe the direct values of their associated variables.
6438 return DAG.getFrameIndexDbgValue(Var: Variable, Expr, FI: FISDN->getIndex(),
6439 /*IsIndirect*/ false, DL: dl, O: DbgSDNodeOrder);
6440 }
6441 return DAG.getDbgValue(Var: Variable, Expr, N: N.getNode(), R: N.getResNo(),
6442 /*IsIndirect*/ false, DL: dl, O: DbgSDNodeOrder);
6443}
6444
6445static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic) {
6446 switch (Intrinsic) {
6447 case Intrinsic::smul_fix:
6448 return ISD::SMULFIX;
6449 case Intrinsic::umul_fix:
6450 return ISD::UMULFIX;
6451 case Intrinsic::smul_fix_sat:
6452 return ISD::SMULFIXSAT;
6453 case Intrinsic::umul_fix_sat:
6454 return ISD::UMULFIXSAT;
6455 case Intrinsic::sdiv_fix:
6456 return ISD::SDIVFIX;
6457 case Intrinsic::udiv_fix:
6458 return ISD::UDIVFIX;
6459 case Intrinsic::sdiv_fix_sat:
6460 return ISD::SDIVFIXSAT;
6461 case Intrinsic::udiv_fix_sat:
6462 return ISD::UDIVFIXSAT;
6463 default:
6464 llvm_unreachable("Unhandled fixed point intrinsic");
6465 }
6466}
6467
6468/// Given a @llvm.call.preallocated.setup, return the corresponding
6469/// preallocated call.
6470static const CallBase *FindPreallocatedCall(const Value *PreallocatedSetup) {
6471 assert(cast<CallBase>(PreallocatedSetup)
6472 ->getCalledFunction()
6473 ->getIntrinsicID() == Intrinsic::call_preallocated_setup &&
6474 "expected call_preallocated_setup Value");
6475 for (const auto *U : PreallocatedSetup->users()) {
6476 auto *UseCall = cast<CallBase>(Val: U);
6477 const Function *Fn = UseCall->getCalledFunction();
6478 if (!Fn || Fn->getIntrinsicID() != Intrinsic::call_preallocated_arg) {
6479 return UseCall;
6480 }
6481 }
6482 llvm_unreachable("expected corresponding call to preallocated setup/arg");
6483}
6484
6485/// If DI is a debug value with an EntryValue expression, lower it using the
6486/// corresponding physical register of the associated Argument value
6487/// (guaranteed to exist by the verifier).
6488bool SelectionDAGBuilder::visitEntryValueDbgValue(
6489 ArrayRef<const Value *> Values, DILocalVariable *Variable,
6490 DIExpression *Expr, DebugLoc DbgLoc) {
6491 if (!Expr->isEntryValue() || !hasSingleElement(C&: Values))
6492 return false;
6493
6494 // These properties are guaranteed by the verifier.
6495 const Argument *Arg = cast<Argument>(Val: Values[0]);
6496 assert(Arg->hasAttribute(Attribute::AttrKind::SwiftAsync));
6497
6498 auto ArgIt = FuncInfo.ValueMap.find(Val: Arg);
6499 if (ArgIt == FuncInfo.ValueMap.end()) {
6500 LLVM_DEBUG(
6501 dbgs() << "Dropping dbg.value: expression is entry_value but "
6502 "couldn't find an associated register for the Argument\n");
6503 return true;
6504 }
6505 Register ArgVReg = ArgIt->getSecond();
6506
6507 for (auto [PhysReg, VirtReg] : FuncInfo.RegInfo->liveins())
6508 if (ArgVReg == VirtReg || ArgVReg == PhysReg) {
6509 SDDbgValue *SDV = DAG.getVRegDbgValue(
6510 Var: Variable, Expr, VReg: PhysReg, IsIndirect: false /*IsIndidrect*/, DL: DbgLoc, O: SDNodeOrder);
6511 DAG.AddDbgValue(DB: SDV, isParameter: false /*treat as dbg.declare byval parameter*/);
6512 return true;
6513 }
6514 LLVM_DEBUG(dbgs() << "Dropping dbg.value: expression is entry_value but "
6515 "couldn't find a physical register\n");
6516 return true;
6517}
6518
6519/// Lower the call to the specified intrinsic function.
6520void SelectionDAGBuilder::visitConvergenceControl(const CallInst &I,
6521 unsigned Intrinsic) {
6522 SDLoc sdl = getCurSDLoc();
6523 switch (Intrinsic) {
6524 case Intrinsic::experimental_convergence_anchor:
6525 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONVERGENCECTRL_ANCHOR, DL: sdl, VT: MVT::Untyped));
6526 break;
6527 case Intrinsic::experimental_convergence_entry:
6528 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONVERGENCECTRL_ENTRY, DL: sdl, VT: MVT::Untyped));
6529 break;
6530 case Intrinsic::experimental_convergence_loop: {
6531 auto Bundle = I.getOperandBundle(ID: LLVMContext::OB_convergencectrl);
6532 auto *Token = Bundle->Inputs[0].get();
6533 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONVERGENCECTRL_LOOP, DL: sdl, VT: MVT::Untyped,
6534 Operand: getValue(V: Token)));
6535 break;
6536 }
6537 }
6538}
6539
6540void SelectionDAGBuilder::visitVectorHistogram(const CallInst &I,
6541 unsigned IntrinsicID) {
6542 // For now, we're only lowering an 'add' histogram.
6543 // We can add others later, e.g. saturating adds, min/max.
6544 assert(IntrinsicID == Intrinsic::experimental_vector_histogram_add &&
6545 "Tried to lower unsupported histogram type");
6546 SDLoc sdl = getCurSDLoc();
6547 Value *Ptr = I.getOperand(i_nocapture: 0);
6548 SDValue Inc = getValue(V: I.getOperand(i_nocapture: 1));
6549 SDValue Mask = getValue(V: I.getOperand(i_nocapture: 2));
6550
6551 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6552 DataLayout TargetDL = DAG.getDataLayout();
6553 EVT VT = Inc.getValueType();
6554 Align Alignment = DAG.getEVTAlign(MemoryVT: VT);
6555
6556 const MDNode *Ranges = getRangeMetadata(I);
6557
6558 SDValue Root = DAG.getRoot();
6559 SDValue Base;
6560 SDValue Index;
6561 SDValue Scale;
6562 bool UniformBase = getUniformBase(Ptr, Base, Index, Scale, SDB: this,
6563 CurBB: I.getParent(), ElemSize: VT.getScalarStoreSize());
6564
6565 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
6566
6567 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
6568 PtrInfo: MachinePointerInfo(AS),
6569 F: MachineMemOperand::MOLoad | MachineMemOperand::MOStore,
6570 Size: MemoryLocation::UnknownSize, BaseAlignment: Alignment, AAInfo: I.getAAMetadata(), Ranges);
6571
6572 if (!UniformBase) {
6573 Base = DAG.getConstant(Val: 0, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
6574 Index = getValue(V: Ptr);
6575 Scale =
6576 DAG.getTargetConstant(Val: 1, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
6577 }
6578
6579 EVT IdxVT = Index.getValueType();
6580
6581 // Avoid using e.g. i32 as index type when the increment must be performed
6582 // on i64's.
6583 bool MustExtendIndex = VT.getScalarSizeInBits() > IdxVT.getScalarSizeInBits();
6584 EVT EltTy = MustExtendIndex ? VT : IdxVT.getVectorElementType();
6585 if (MustExtendIndex || TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
6586 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
6587 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: sdl, VT: NewIdxVT, Operand: Index);
6588 }
6589
6590 SDValue ID = DAG.getTargetConstant(Val: IntrinsicID, DL: sdl, VT: MVT::i32);
6591
6592 SDValue Ops[] = {Root, Inc, Mask, Base, Index, Scale, ID};
6593 SDValue Histogram = DAG.getMaskedHistogram(VTs: DAG.getVTList(VT: MVT::Other), MemVT: VT, dl: sdl,
6594 Ops, MMO, IndexType: ISD::SIGNED_SCALED);
6595
6596 setValue(V: &I, NewN: Histogram);
6597 DAG.setRoot(Histogram);
6598}
6599
6600void SelectionDAGBuilder::visitVectorExtractLastActive(const CallInst &I,
6601 unsigned Intrinsic) {
6602 assert(Intrinsic == Intrinsic::experimental_vector_extract_last_active &&
6603 "Tried lowering invalid vector extract last");
6604 SDLoc sdl = getCurSDLoc();
6605 const DataLayout &Layout = DAG.getDataLayout();
6606 SDValue Data = getValue(V: I.getOperand(i_nocapture: 0));
6607 SDValue Mask = getValue(V: I.getOperand(i_nocapture: 1));
6608
6609 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6610 EVT ResVT = TLI.getValueType(DL: Layout, Ty: I.getType());
6611
6612 EVT ExtVT = TLI.getVectorIdxTy(DL: Layout);
6613 SDValue Idx = DAG.getNode(Opcode: ISD::VECTOR_FIND_LAST_ACTIVE, DL: sdl, VT: ExtVT, Operand: Mask);
6614 SDValue Result = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: sdl, VT: ResVT, N1: Data, N2: Idx);
6615
6616 Value *Default = I.getOperand(i_nocapture: 2);
6617 if (!isa<PoisonValue>(Val: Default) && !isa<UndefValue>(Val: Default)) {
6618 SDValue PassThru = getValue(V: Default);
6619 EVT BoolVT = Mask.getValueType().getScalarType();
6620 SDValue AnyActive = DAG.getNode(Opcode: ISD::VECREDUCE_OR, DL: sdl, VT: BoolVT, Operand: Mask);
6621 Result = DAG.getSelect(DL: sdl, VT: ResVT, Cond: AnyActive, LHS: Result, RHS: PassThru);
6622 }
6623
6624 setValue(V: &I, NewN: Result);
6625}
6626
6627/// Lower the call to the specified intrinsic function.
6628void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
6629 unsigned Intrinsic) {
6630 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6631 SDLoc sdl = getCurSDLoc();
6632 DebugLoc dl = getCurDebugLoc();
6633 SDValue Res;
6634
6635 SDNodeFlags Flags;
6636 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &I))
6637 Flags.copyFMF(FPMO: *FPOp);
6638
6639 switch (Intrinsic) {
6640 default:
6641 // By default, turn this into a target intrinsic node.
6642 visitTargetIntrinsic(I, Intrinsic);
6643 return;
6644 case Intrinsic::vscale: {
6645 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
6646 setValue(V: &I, NewN: DAG.getVScale(DL: sdl, VT, MulImm: APInt(VT.getSizeInBits(), 1)));
6647 return;
6648 }
6649 case Intrinsic::vastart: visitVAStart(I); return;
6650 case Intrinsic::vaend: visitVAEnd(I); return;
6651 case Intrinsic::vacopy: visitVACopy(I); return;
6652 case Intrinsic::returnaddress:
6653 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::RETURNADDR, DL: sdl,
6654 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
6655 Operand: getValue(V: I.getArgOperand(i: 0))));
6656 return;
6657 case Intrinsic::addressofreturnaddress:
6658 setValue(V: &I,
6659 NewN: DAG.getNode(Opcode: ISD::ADDROFRETURNADDR, DL: sdl,
6660 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType())));
6661 return;
6662 case Intrinsic::sponentry:
6663 setValue(V: &I,
6664 NewN: DAG.getNode(Opcode: ISD::SPONENTRY, DL: sdl,
6665 VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType())));
6666 return;
6667 case Intrinsic::frameaddress:
6668 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FRAMEADDR, DL: sdl,
6669 VT: TLI.getFrameIndexTy(DL: DAG.getDataLayout()),
6670 Operand: getValue(V: I.getArgOperand(i: 0))));
6671 return;
6672 case Intrinsic::read_volatile_register:
6673 case Intrinsic::read_register: {
6674 Value *Reg = I.getArgOperand(i: 0);
6675 SDValue Chain = getRoot();
6676 SDValue RegName =
6677 DAG.getMDNode(MD: cast<MDNode>(Val: cast<MetadataAsValue>(Val: Reg)->getMetadata()));
6678 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
6679 Res = DAG.getNode(Opcode: ISD::READ_REGISTER, DL: sdl,
6680 VTList: DAG.getVTList(VT1: VT, VT2: MVT::Other), N1: Chain, N2: RegName);
6681 setValue(V: &I, NewN: Res);
6682 DAG.setRoot(Res.getValue(R: 1));
6683 return;
6684 }
6685 case Intrinsic::write_register: {
6686 Value *Reg = I.getArgOperand(i: 0);
6687 Value *RegValue = I.getArgOperand(i: 1);
6688 SDValue Chain = getRoot();
6689 SDValue RegName =
6690 DAG.getMDNode(MD: cast<MDNode>(Val: cast<MetadataAsValue>(Val: Reg)->getMetadata()));
6691 DAG.setRoot(DAG.getNode(Opcode: ISD::WRITE_REGISTER, DL: sdl, VT: MVT::Other, N1: Chain,
6692 N2: RegName, N3: getValue(V: RegValue)));
6693 return;
6694 }
6695 case Intrinsic::memcpy:
6696 case Intrinsic::memcpy_inline: {
6697 const auto &MCI = cast<MemCpyInst>(Val: I);
6698 SDValue Dst = getValue(V: I.getArgOperand(i: 0));
6699 SDValue Src = getValue(V: I.getArgOperand(i: 1));
6700 SDValue Size = getValue(V: I.getArgOperand(i: 2));
6701 assert((!MCI.isForceInlined() || isa<ConstantSDNode>(Size)) &&
6702 "memcpy_inline needs constant size");
6703 // @llvm.memcpy.inline defines 0 and 1 to both mean no alignment.
6704 Align DstAlign = MCI.getDestAlign().valueOrOne();
6705 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6706 Align Alignment = std::min(a: DstAlign, b: SrcAlign);
6707 bool isVol = MCI.isVolatile();
6708 // FIXME: Support passing different dest/src alignments to the memcpy DAG
6709 // node.
6710 SDValue Root = isVol ? getRoot() : getMemoryRoot();
6711 SDValue MC = DAG.getMemcpy(Chain: Root, dl: sdl, Dst, Src, Size, Alignment, isVol,
6712 AlwaysInline: MCI.isForceInlined(), CI: &I, OverrideTailCall: std::nullopt,
6713 DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
6714 SrcPtrInfo: MachinePointerInfo(I.getArgOperand(i: 1)),
6715 AAInfo: I.getAAMetadata(), BatchAA);
6716 updateDAGForMaybeTailCall(MaybeTC: MC);
6717 return;
6718 }
6719 case Intrinsic::memset:
6720 case Intrinsic::memset_inline: {
6721 const auto &MSII = cast<MemSetInst>(Val: I);
6722 SDValue Dst = getValue(V: I.getArgOperand(i: 0));
6723 SDValue Value = getValue(V: I.getArgOperand(i: 1));
6724 SDValue Size = getValue(V: I.getArgOperand(i: 2));
6725 assert((!MSII.isForceInlined() || isa<ConstantSDNode>(Size)) &&
6726 "memset_inline needs constant size");
6727 // @llvm.memset defines 0 and 1 to both mean no alignment.
6728 Align DstAlign = MSII.getDestAlign().valueOrOne();
6729 bool isVol = MSII.isVolatile();
6730 SDValue Root = isVol ? getRoot() : getMemoryRoot();
6731 SDValue MC = DAG.getMemset(
6732 Chain: Root, dl: sdl, Dst, Src: Value, Size, Alignment: DstAlign, isVol, AlwaysInline: MSII.isForceInlined(),
6733 CI: &I, DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)), AAInfo: I.getAAMetadata());
6734 updateDAGForMaybeTailCall(MaybeTC: MC);
6735 return;
6736 }
6737 case Intrinsic::memmove: {
6738 const auto &MMI = cast<MemMoveInst>(Val: I);
6739 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
6740 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
6741 SDValue Op3 = getValue(V: I.getArgOperand(i: 2));
6742 // @llvm.memmove defines 0 and 1 to both mean no alignment.
6743 Align DstAlign = MMI.getDestAlign().valueOrOne();
6744 Align SrcAlign = MMI.getSourceAlign().valueOrOne();
6745 Align Alignment = std::min(a: DstAlign, b: SrcAlign);
6746 bool isVol = MMI.isVolatile();
6747 // FIXME: Support passing different dest/src alignments to the memmove DAG
6748 // node.
6749 SDValue Root = isVol ? getRoot() : getMemoryRoot();
6750 SDValue MM = DAG.getMemmove(Chain: Root, dl: sdl, Dst: Op1, Src: Op2, Size: Op3, Alignment, isVol, CI: &I,
6751 /* OverrideTailCall */ std::nullopt,
6752 DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
6753 SrcPtrInfo: MachinePointerInfo(I.getArgOperand(i: 1)),
6754 AAInfo: I.getAAMetadata(), BatchAA);
6755 updateDAGForMaybeTailCall(MaybeTC: MM);
6756 return;
6757 }
6758 case Intrinsic::memcpy_element_unordered_atomic: {
6759 auto &MI = cast<AnyMemCpyInst>(Val: I);
6760 SDValue Dst = getValue(V: MI.getRawDest());
6761 SDValue Src = getValue(V: MI.getRawSource());
6762 SDValue Length = getValue(V: MI.getLength());
6763
6764 Type *LengthTy = MI.getLength()->getType();
6765 unsigned ElemSz = MI.getElementSizeInBytes();
6766 bool isTC = I.isTailCall() && isInTailCallPosition(Call: I, TM: DAG.getTarget());
6767 SDValue MC =
6768 DAG.getAtomicMemcpy(Chain: getRoot(), dl: sdl, Dst, Src, Size: Length, SizeTy: LengthTy, ElemSz,
6769 isTailCall: isTC, DstPtrInfo: MachinePointerInfo(MI.getRawDest()),
6770 SrcPtrInfo: MachinePointerInfo(MI.getRawSource()));
6771 updateDAGForMaybeTailCall(MaybeTC: MC);
6772 return;
6773 }
6774 case Intrinsic::memmove_element_unordered_atomic: {
6775 auto &MI = cast<AnyMemMoveInst>(Val: I);
6776 SDValue Dst = getValue(V: MI.getRawDest());
6777 SDValue Src = getValue(V: MI.getRawSource());
6778 SDValue Length = getValue(V: MI.getLength());
6779
6780 Type *LengthTy = MI.getLength()->getType();
6781 unsigned ElemSz = MI.getElementSizeInBytes();
6782 bool isTC = I.isTailCall() && isInTailCallPosition(Call: I, TM: DAG.getTarget());
6783 SDValue MC =
6784 DAG.getAtomicMemmove(Chain: getRoot(), dl: sdl, Dst, Src, Size: Length, SizeTy: LengthTy, ElemSz,
6785 isTailCall: isTC, DstPtrInfo: MachinePointerInfo(MI.getRawDest()),
6786 SrcPtrInfo: MachinePointerInfo(MI.getRawSource()));
6787 updateDAGForMaybeTailCall(MaybeTC: MC);
6788 return;
6789 }
6790 case Intrinsic::memset_element_unordered_atomic: {
6791 auto &MI = cast<AnyMemSetInst>(Val: I);
6792 SDValue Dst = getValue(V: MI.getRawDest());
6793 SDValue Val = getValue(V: MI.getValue());
6794 SDValue Length = getValue(V: MI.getLength());
6795
6796 Type *LengthTy = MI.getLength()->getType();
6797 unsigned ElemSz = MI.getElementSizeInBytes();
6798 bool isTC = I.isTailCall() && isInTailCallPosition(Call: I, TM: DAG.getTarget());
6799 SDValue MC =
6800 DAG.getAtomicMemset(Chain: getRoot(), dl: sdl, Dst, Value: Val, Size: Length, SizeTy: LengthTy, ElemSz,
6801 isTailCall: isTC, DstPtrInfo: MachinePointerInfo(MI.getRawDest()));
6802 updateDAGForMaybeTailCall(MaybeTC: MC);
6803 return;
6804 }
6805 case Intrinsic::call_preallocated_setup: {
6806 const CallBase *PreallocatedCall = FindPreallocatedCall(PreallocatedSetup: &I);
6807 SDValue SrcValue = DAG.getSrcValue(v: PreallocatedCall);
6808 SDValue Res = DAG.getNode(Opcode: ISD::PREALLOCATED_SETUP, DL: sdl, VT: MVT::Other,
6809 N1: getRoot(), N2: SrcValue);
6810 setValue(V: &I, NewN: Res);
6811 DAG.setRoot(Res);
6812 return;
6813 }
6814 case Intrinsic::call_preallocated_arg: {
6815 const CallBase *PreallocatedCall = FindPreallocatedCall(PreallocatedSetup: I.getOperand(i_nocapture: 0));
6816 SDValue SrcValue = DAG.getSrcValue(v: PreallocatedCall);
6817 SDValue Ops[3];
6818 Ops[0] = getRoot();
6819 Ops[1] = SrcValue;
6820 Ops[2] = DAG.getTargetConstant(Val: *cast<ConstantInt>(Val: I.getArgOperand(i: 1)), DL: sdl,
6821 VT: MVT::i32); // arg index
6822 SDValue Res = DAG.getNode(
6823 Opcode: ISD::PREALLOCATED_ARG, DL: sdl,
6824 VTList: DAG.getVTList(VT1: TLI.getPointerTy(DL: DAG.getDataLayout()), VT2: MVT::Other), Ops);
6825 setValue(V: &I, NewN: Res);
6826 DAG.setRoot(Res.getValue(R: 1));
6827 return;
6828 }
6829
6830 case Intrinsic::eh_typeid_for: {
6831 // Find the type id for the given typeinfo.
6832 GlobalValue *GV = ExtractTypeInfo(V: I.getArgOperand(i: 0));
6833 unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(TI: GV);
6834 Res = DAG.getConstant(Val: TypeID, DL: sdl, VT: MVT::i32);
6835 setValue(V: &I, NewN: Res);
6836 return;
6837 }
6838
6839 case Intrinsic::eh_return_i32:
6840 case Intrinsic::eh_return_i64:
6841 DAG.getMachineFunction().setCallsEHReturn(true);
6842 DAG.setRoot(DAG.getNode(Opcode: ISD::EH_RETURN, DL: sdl,
6843 VT: MVT::Other,
6844 N1: getControlRoot(),
6845 N2: getValue(V: I.getArgOperand(i: 0)),
6846 N3: getValue(V: I.getArgOperand(i: 1))));
6847 return;
6848 case Intrinsic::eh_unwind_init:
6849 DAG.getMachineFunction().setCallsUnwindInit(true);
6850 return;
6851 case Intrinsic::eh_dwarf_cfa:
6852 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::EH_DWARF_CFA, DL: sdl,
6853 VT: TLI.getPointerTy(DL: DAG.getDataLayout()),
6854 Operand: getValue(V: I.getArgOperand(i: 0))));
6855 return;
6856 case Intrinsic::eh_sjlj_callsite: {
6857 ConstantInt *CI = cast<ConstantInt>(Val: I.getArgOperand(i: 0));
6858 assert(FuncInfo.getCurrentCallSite() == 0 && "Overlapping call sites!");
6859
6860 FuncInfo.setCurrentCallSite(CI->getZExtValue());
6861 return;
6862 }
6863 case Intrinsic::eh_sjlj_functioncontext: {
6864 // Get and store the index of the function context.
6865 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
6866 AllocaInst *FnCtx =
6867 cast<AllocaInst>(Val: I.getArgOperand(i: 0)->stripPointerCasts());
6868 int FI = FuncInfo.StaticAllocaMap[FnCtx];
6869 MFI.setFunctionContextIndex(FI);
6870 return;
6871 }
6872 case Intrinsic::eh_sjlj_setjmp: {
6873 SDValue Ops[2];
6874 Ops[0] = getRoot();
6875 Ops[1] = getValue(V: I.getArgOperand(i: 0));
6876 SDValue Op = DAG.getNode(Opcode: ISD::EH_SJLJ_SETJMP, DL: sdl,
6877 VTList: DAG.getVTList(VT1: MVT::i32, VT2: MVT::Other), Ops);
6878 setValue(V: &I, NewN: Op.getValue(R: 0));
6879 DAG.setRoot(Op.getValue(R: 1));
6880 return;
6881 }
6882 case Intrinsic::eh_sjlj_longjmp:
6883 DAG.setRoot(DAG.getNode(Opcode: ISD::EH_SJLJ_LONGJMP, DL: sdl, VT: MVT::Other,
6884 N1: getRoot(), N2: getValue(V: I.getArgOperand(i: 0))));
6885 return;
6886 case Intrinsic::eh_sjlj_setup_dispatch:
6887 DAG.setRoot(DAG.getNode(Opcode: ISD::EH_SJLJ_SETUP_DISPATCH, DL: sdl, VT: MVT::Other,
6888 Operand: getRoot()));
6889 return;
6890 case Intrinsic::masked_gather:
6891 visitMaskedGather(I);
6892 return;
6893 case Intrinsic::masked_load:
6894 visitMaskedLoad(I);
6895 return;
6896 case Intrinsic::masked_scatter:
6897 visitMaskedScatter(I);
6898 return;
6899 case Intrinsic::masked_store:
6900 visitMaskedStore(I);
6901 return;
6902 case Intrinsic::masked_expandload:
6903 visitMaskedLoad(I, IsExpanding: true /* IsExpanding */);
6904 return;
6905 case Intrinsic::masked_compressstore:
6906 visitMaskedStore(I, IsCompressing: true /* IsCompressing */);
6907 return;
6908 case Intrinsic::powi:
6909 setValue(V: &I, NewN: ExpandPowI(DL: sdl, LHS: getValue(V: I.getArgOperand(i: 0)),
6910 RHS: getValue(V: I.getArgOperand(i: 1)), DAG));
6911 return;
6912 case Intrinsic::log:
6913 setValue(V: &I, NewN: expandLog(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
6914 return;
6915 case Intrinsic::log2:
6916 setValue(V: &I,
6917 NewN: expandLog2(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
6918 return;
6919 case Intrinsic::log10:
6920 setValue(V: &I,
6921 NewN: expandLog10(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
6922 return;
6923 case Intrinsic::exp:
6924 setValue(V: &I, NewN: expandExp(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
6925 return;
6926 case Intrinsic::exp2:
6927 setValue(V: &I,
6928 NewN: expandExp2(dl: sdl, Op: getValue(V: I.getArgOperand(i: 0)), DAG, TLI, Flags));
6929 return;
6930 case Intrinsic::pow:
6931 setValue(V: &I, NewN: expandPow(dl: sdl, LHS: getValue(V: I.getArgOperand(i: 0)),
6932 RHS: getValue(V: I.getArgOperand(i: 1)), DAG, TLI, Flags));
6933 return;
6934 case Intrinsic::sqrt:
6935 case Intrinsic::fabs:
6936 case Intrinsic::sin:
6937 case Intrinsic::cos:
6938 case Intrinsic::tan:
6939 case Intrinsic::asin:
6940 case Intrinsic::acos:
6941 case Intrinsic::atan:
6942 case Intrinsic::sinh:
6943 case Intrinsic::cosh:
6944 case Intrinsic::tanh:
6945 case Intrinsic::exp10:
6946 case Intrinsic::floor:
6947 case Intrinsic::ceil:
6948 case Intrinsic::trunc:
6949 case Intrinsic::rint:
6950 case Intrinsic::nearbyint:
6951 case Intrinsic::round:
6952 case Intrinsic::roundeven:
6953 case Intrinsic::canonicalize: {
6954 unsigned Opcode;
6955 // clang-format off
6956 switch (Intrinsic) {
6957 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6958 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
6959 case Intrinsic::fabs: Opcode = ISD::FABS; break;
6960 case Intrinsic::sin: Opcode = ISD::FSIN; break;
6961 case Intrinsic::cos: Opcode = ISD::FCOS; break;
6962 case Intrinsic::tan: Opcode = ISD::FTAN; break;
6963 case Intrinsic::asin: Opcode = ISD::FASIN; break;
6964 case Intrinsic::acos: Opcode = ISD::FACOS; break;
6965 case Intrinsic::atan: Opcode = ISD::FATAN; break;
6966 case Intrinsic::sinh: Opcode = ISD::FSINH; break;
6967 case Intrinsic::cosh: Opcode = ISD::FCOSH; break;
6968 case Intrinsic::tanh: Opcode = ISD::FTANH; break;
6969 case Intrinsic::exp10: Opcode = ISD::FEXP10; break;
6970 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
6971 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
6972 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
6973 case Intrinsic::rint: Opcode = ISD::FRINT; break;
6974 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
6975 case Intrinsic::round: Opcode = ISD::FROUND; break;
6976 case Intrinsic::roundeven: Opcode = ISD::FROUNDEVEN; break;
6977 case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break;
6978 }
6979 // clang-format on
6980
6981 setValue(V: &I, NewN: DAG.getNode(Opcode, DL: sdl,
6982 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
6983 Operand: getValue(V: I.getArgOperand(i: 0)), Flags));
6984 return;
6985 }
6986 case Intrinsic::atan2:
6987 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FATAN2, DL: sdl,
6988 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
6989 N1: getValue(V: I.getArgOperand(i: 0)),
6990 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
6991 return;
6992 case Intrinsic::lround:
6993 case Intrinsic::llround:
6994 case Intrinsic::lrint:
6995 case Intrinsic::llrint: {
6996 unsigned Opcode;
6997 // clang-format off
6998 switch (Intrinsic) {
6999 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7000 case Intrinsic::lround: Opcode = ISD::LROUND; break;
7001 case Intrinsic::llround: Opcode = ISD::LLROUND; break;
7002 case Intrinsic::lrint: Opcode = ISD::LRINT; break;
7003 case Intrinsic::llrint: Opcode = ISD::LLRINT; break;
7004 }
7005 // clang-format on
7006
7007 EVT RetVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7008 setValue(V: &I, NewN: DAG.getNode(Opcode, DL: sdl, VT: RetVT,
7009 Operand: getValue(V: I.getArgOperand(i: 0))));
7010 return;
7011 }
7012 case Intrinsic::minnum:
7013 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMINNUM, DL: sdl,
7014 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7015 N1: getValue(V: I.getArgOperand(i: 0)),
7016 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7017 return;
7018 case Intrinsic::maxnum:
7019 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMAXNUM, DL: sdl,
7020 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7021 N1: getValue(V: I.getArgOperand(i: 0)),
7022 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7023 return;
7024 case Intrinsic::minimum:
7025 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMINIMUM, DL: sdl,
7026 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7027 N1: getValue(V: I.getArgOperand(i: 0)),
7028 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7029 return;
7030 case Intrinsic::maximum:
7031 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMAXIMUM, DL: sdl,
7032 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7033 N1: getValue(V: I.getArgOperand(i: 0)),
7034 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7035 return;
7036 case Intrinsic::minimumnum:
7037 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMINIMUMNUM, DL: sdl,
7038 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7039 N1: getValue(V: I.getArgOperand(i: 0)),
7040 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7041 return;
7042 case Intrinsic::maximumnum:
7043 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMAXIMUMNUM, DL: sdl,
7044 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7045 N1: getValue(V: I.getArgOperand(i: 0)),
7046 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7047 return;
7048 case Intrinsic::copysign:
7049 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FCOPYSIGN, DL: sdl,
7050 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7051 N1: getValue(V: I.getArgOperand(i: 0)),
7052 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7053 return;
7054 case Intrinsic::ldexp:
7055 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FLDEXP, DL: sdl,
7056 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7057 N1: getValue(V: I.getArgOperand(i: 0)),
7058 N2: getValue(V: I.getArgOperand(i: 1)), Flags));
7059 return;
7060 case Intrinsic::modf:
7061 case Intrinsic::sincos:
7062 case Intrinsic::sincospi:
7063 case Intrinsic::frexp: {
7064 unsigned Opcode;
7065 switch (Intrinsic) {
7066 default:
7067 llvm_unreachable("unexpected intrinsic");
7068 case Intrinsic::sincos:
7069 Opcode = ISD::FSINCOS;
7070 break;
7071 case Intrinsic::sincospi:
7072 Opcode = ISD::FSINCOSPI;
7073 break;
7074 case Intrinsic::modf:
7075 Opcode = ISD::FMODF;
7076 break;
7077 case Intrinsic::frexp:
7078 Opcode = ISD::FFREXP;
7079 break;
7080 }
7081 SmallVector<EVT, 2> ValueVTs;
7082 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: I.getType(), ValueVTs);
7083 SDVTList VTs = DAG.getVTList(VTs: ValueVTs);
7084 setValue(
7085 V: &I, NewN: DAG.getNode(Opcode, DL: sdl, VTList: VTs, Ops: getValue(V: I.getArgOperand(i: 0)), Flags));
7086 return;
7087 }
7088 case Intrinsic::arithmetic_fence: {
7089 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::ARITH_FENCE, DL: sdl,
7090 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7091 Operand: getValue(V: I.getArgOperand(i: 0)), Flags));
7092 return;
7093 }
7094 case Intrinsic::fma:
7095 setValue(V: &I, NewN: DAG.getNode(
7096 Opcode: ISD::FMA, DL: sdl, VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7097 N1: getValue(V: I.getArgOperand(i: 0)), N2: getValue(V: I.getArgOperand(i: 1)),
7098 N3: getValue(V: I.getArgOperand(i: 2)), Flags));
7099 return;
7100#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
7101 case Intrinsic::INTRINSIC:
7102#include "llvm/IR/ConstrainedOps.def"
7103 visitConstrainedFPIntrinsic(FPI: cast<ConstrainedFPIntrinsic>(Val: I));
7104 return;
7105#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
7106#include "llvm/IR/VPIntrinsics.def"
7107 visitVectorPredicationIntrinsic(VPIntrin: cast<VPIntrinsic>(Val: I));
7108 return;
7109 case Intrinsic::fptrunc_round: {
7110 // Get the last argument, the metadata and convert it to an integer in the
7111 // call
7112 Metadata *MD = cast<MetadataAsValue>(Val: I.getArgOperand(i: 1))->getMetadata();
7113 std::optional<RoundingMode> RoundMode =
7114 convertStrToRoundingMode(cast<MDString>(Val: MD)->getString());
7115
7116 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7117
7118 // Propagate fast-math-flags from IR to node(s).
7119 SDNodeFlags Flags;
7120 Flags.copyFMF(FPMO: *cast<FPMathOperator>(Val: &I));
7121 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
7122
7123 SDValue Result;
7124 Result = DAG.getNode(
7125 Opcode: ISD::FPTRUNC_ROUND, DL: sdl, VT, N1: getValue(V: I.getArgOperand(i: 0)),
7126 N2: DAG.getTargetConstant(Val: (int)*RoundMode, DL: sdl, VT: MVT::i32));
7127 setValue(V: &I, NewN: Result);
7128
7129 return;
7130 }
7131 case Intrinsic::fmuladd: {
7132 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7133 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
7134 TLI.isFMAFasterThanFMulAndFAdd(MF: DAG.getMachineFunction(), VT)) {
7135 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMA, DL: sdl,
7136 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7137 N1: getValue(V: I.getArgOperand(i: 0)),
7138 N2: getValue(V: I.getArgOperand(i: 1)),
7139 N3: getValue(V: I.getArgOperand(i: 2)), Flags));
7140 } else if (TLI.isOperationLegalOrCustom(Op: ISD::FMULADD, VT)) {
7141 // TODO: Support splitting the vector.
7142 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FMULADD, DL: sdl,
7143 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7144 N1: getValue(V: I.getArgOperand(i: 0)),
7145 N2: getValue(V: I.getArgOperand(i: 1)),
7146 N3: getValue(V: I.getArgOperand(i: 2)), Flags));
7147 } else {
7148 // TODO: Intrinsic calls should have fast-math-flags.
7149 SDValue Mul = DAG.getNode(
7150 Opcode: ISD::FMUL, DL: sdl, VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7151 N1: getValue(V: I.getArgOperand(i: 0)), N2: getValue(V: I.getArgOperand(i: 1)), Flags);
7152 SDValue Add = DAG.getNode(Opcode: ISD::FADD, DL: sdl,
7153 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7154 N1: Mul, N2: getValue(V: I.getArgOperand(i: 2)), Flags);
7155 setValue(V: &I, NewN: Add);
7156 }
7157 return;
7158 }
7159 case Intrinsic::fptosi_sat: {
7160 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7161 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_TO_SINT_SAT, DL: sdl, VT,
7162 N1: getValue(V: I.getArgOperand(i: 0)),
7163 N2: DAG.getValueType(VT.getScalarType())));
7164 return;
7165 }
7166 case Intrinsic::fptoui_sat: {
7167 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7168 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FP_TO_UINT_SAT, DL: sdl, VT,
7169 N1: getValue(V: I.getArgOperand(i: 0)),
7170 N2: DAG.getValueType(VT.getScalarType())));
7171 return;
7172 }
7173 case Intrinsic::convert_from_arbitrary_fp: {
7174 // Extract format metadata and convert to semantics enum.
7175 EVT DstVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7176 Metadata *MD = cast<MetadataAsValue>(Val: I.getArgOperand(i: 1))->getMetadata();
7177 StringRef FormatStr = cast<MDString>(Val: MD)->getString();
7178 const fltSemantics *SrcSem =
7179 APFloatBase::getArbitraryFPSemantics(Format: FormatStr);
7180 if (!SrcSem) {
7181 DAG.getContext()->emitError(
7182 ErrorStr: "convert_from_arbitrary_fp: not implemented format '" + FormatStr +
7183 "'");
7184 setValue(V: &I, NewN: DAG.getPOISON(VT: DstVT));
7185 return;
7186 }
7187 APFloatBase::Semantics SemEnum = APFloatBase::SemanticsToEnum(Sem: *SrcSem);
7188
7189 SDValue IntVal = getValue(V: I.getArgOperand(i: 0));
7190
7191 // Emit ISD::CONVERT_FROM_ARBITRARY_FP node.
7192 SDValue SemConst =
7193 DAG.getTargetConstant(Val: static_cast<int>(SemEnum), DL: sdl, VT: MVT::i32);
7194 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CONVERT_FROM_ARBITRARY_FP, DL: sdl, VT: DstVT, N1: IntVal,
7195 N2: SemConst));
7196 return;
7197 }
7198 case Intrinsic::set_rounding:
7199 Res = DAG.getNode(Opcode: ISD::SET_ROUNDING, DL: sdl, VT: MVT::Other,
7200 Ops: {getRoot(), getValue(V: I.getArgOperand(i: 0))});
7201 setValue(V: &I, NewN: Res);
7202 DAG.setRoot(Res.getValue(R: 0));
7203 return;
7204 case Intrinsic::is_fpclass: {
7205 const DataLayout DLayout = DAG.getDataLayout();
7206 EVT DestVT = TLI.getValueType(DL: DLayout, Ty: I.getType());
7207 EVT ArgVT = TLI.getValueType(DL: DLayout, Ty: I.getArgOperand(i: 0)->getType());
7208 FPClassTest Test = static_cast<FPClassTest>(
7209 cast<ConstantInt>(Val: I.getArgOperand(i: 1))->getZExtValue());
7210 MachineFunction &MF = DAG.getMachineFunction();
7211 const Function &F = MF.getFunction();
7212 SDValue Op = getValue(V: I.getArgOperand(i: 0));
7213 SDNodeFlags Flags;
7214 Flags.setNoFPExcept(
7215 !F.getAttributes().hasFnAttr(Kind: llvm::Attribute::StrictFP));
7216 // If ISD::IS_FPCLASS should be expanded, do it right now, because the
7217 // expansion can use illegal types. Making expansion early allows
7218 // legalizing these types prior to selection.
7219 if (!TLI.isOperationLegal(Op: ISD::IS_FPCLASS, VT: ArgVT) &&
7220 !TLI.isOperationCustom(Op: ISD::IS_FPCLASS, VT: ArgVT)) {
7221 SDValue Result = TLI.expandIS_FPCLASS(ResultVT: DestVT, Op, Test, Flags, DL: sdl, DAG);
7222 setValue(V: &I, NewN: Result);
7223 return;
7224 }
7225
7226 SDValue Check = DAG.getTargetConstant(Val: Test, DL: sdl, VT: MVT::i32);
7227 SDValue V = DAG.getNode(Opcode: ISD::IS_FPCLASS, DL: sdl, VT: DestVT, Ops: {Op, Check}, Flags);
7228 setValue(V: &I, NewN: V);
7229 return;
7230 }
7231 case Intrinsic::get_fpenv: {
7232 const DataLayout DLayout = DAG.getDataLayout();
7233 EVT EnvVT = TLI.getValueType(DL: DLayout, Ty: I.getType());
7234 Align TempAlign = DAG.getEVTAlign(MemoryVT: EnvVT);
7235 SDValue Chain = getRoot();
7236 // Use GET_FPENV if it is legal or custom. Otherwise use memory-based node
7237 // and temporary storage in stack.
7238 if (TLI.isOperationLegalOrCustom(Op: ISD::GET_FPENV, VT: EnvVT)) {
7239 Res = DAG.getNode(
7240 Opcode: ISD::GET_FPENV, DL: sdl,
7241 VTList: DAG.getVTList(VT1: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
7242 VT2: MVT::Other),
7243 N: Chain);
7244 } else {
7245 SDValue Temp = DAG.CreateStackTemporary(VT: EnvVT, minAlign: TempAlign.value());
7246 int SPFI = cast<FrameIndexSDNode>(Val: Temp.getNode())->getIndex();
7247 auto MPI =
7248 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI);
7249 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7250 PtrInfo: MPI, F: MachineMemOperand::MOStore, Size: LocationSize::beforeOrAfterPointer(),
7251 BaseAlignment: TempAlign);
7252 Chain = DAG.getGetFPEnv(Chain, dl: sdl, Ptr: Temp, MemVT: EnvVT, MMO);
7253 Res = DAG.getLoad(VT: EnvVT, dl: sdl, Chain, Ptr: Temp, PtrInfo: MPI);
7254 }
7255 setValue(V: &I, NewN: Res);
7256 DAG.setRoot(Res.getValue(R: 1));
7257 return;
7258 }
7259 case Intrinsic::set_fpenv: {
7260 const DataLayout DLayout = DAG.getDataLayout();
7261 SDValue Env = getValue(V: I.getArgOperand(i: 0));
7262 EVT EnvVT = Env.getValueType();
7263 Align TempAlign = DAG.getEVTAlign(MemoryVT: EnvVT);
7264 SDValue Chain = getRoot();
7265 // If SET_FPENV is custom or legal, use it. Otherwise use loading
7266 // environment from memory.
7267 if (TLI.isOperationLegalOrCustom(Op: ISD::SET_FPENV, VT: EnvVT)) {
7268 Chain = DAG.getNode(Opcode: ISD::SET_FPENV, DL: sdl, VT: MVT::Other, N1: Chain, N2: Env);
7269 } else {
7270 // Allocate space in stack, copy environment bits into it and use this
7271 // memory in SET_FPENV_MEM.
7272 SDValue Temp = DAG.CreateStackTemporary(VT: EnvVT, minAlign: TempAlign.value());
7273 int SPFI = cast<FrameIndexSDNode>(Val: Temp.getNode())->getIndex();
7274 auto MPI =
7275 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI);
7276 Chain = DAG.getStore(Chain, dl: sdl, Val: Env, Ptr: Temp, PtrInfo: MPI, Alignment: TempAlign,
7277 MMOFlags: MachineMemOperand::MOStore);
7278 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
7279 PtrInfo: MPI, F: MachineMemOperand::MOLoad, Size: LocationSize::beforeOrAfterPointer(),
7280 BaseAlignment: TempAlign);
7281 Chain = DAG.getSetFPEnv(Chain, dl: sdl, Ptr: Temp, MemVT: EnvVT, MMO);
7282 }
7283 DAG.setRoot(Chain);
7284 return;
7285 }
7286 case Intrinsic::reset_fpenv:
7287 DAG.setRoot(DAG.getNode(Opcode: ISD::RESET_FPENV, DL: sdl, VT: MVT::Other, Operand: getRoot()));
7288 return;
7289 case Intrinsic::get_fpmode:
7290 Res = DAG.getNode(
7291 Opcode: ISD::GET_FPMODE, DL: sdl,
7292 VTList: DAG.getVTList(VT1: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()),
7293 VT2: MVT::Other),
7294 N: DAG.getRoot());
7295 setValue(V: &I, NewN: Res);
7296 DAG.setRoot(Res.getValue(R: 1));
7297 return;
7298 case Intrinsic::set_fpmode:
7299 Res = DAG.getNode(Opcode: ISD::SET_FPMODE, DL: sdl, VT: MVT::Other, N1: {DAG.getRoot()},
7300 N2: getValue(V: I.getArgOperand(i: 0)));
7301 DAG.setRoot(Res);
7302 return;
7303 case Intrinsic::reset_fpmode: {
7304 Res = DAG.getNode(Opcode: ISD::RESET_FPMODE, DL: sdl, VT: MVT::Other, Operand: getRoot());
7305 DAG.setRoot(Res);
7306 return;
7307 }
7308 case Intrinsic::pcmarker: {
7309 SDValue Tmp = getValue(V: I.getArgOperand(i: 0));
7310 DAG.setRoot(DAG.getNode(Opcode: ISD::PCMARKER, DL: sdl, VT: MVT::Other, N1: getRoot(), N2: Tmp));
7311 return;
7312 }
7313 case Intrinsic::readcyclecounter: {
7314 SDValue Op = getRoot();
7315 Res = DAG.getNode(Opcode: ISD::READCYCLECOUNTER, DL: sdl,
7316 VTList: DAG.getVTList(VT1: MVT::i64, VT2: MVT::Other), N: Op);
7317 setValue(V: &I, NewN: Res);
7318 DAG.setRoot(Res.getValue(R: 1));
7319 return;
7320 }
7321 case Intrinsic::readsteadycounter: {
7322 SDValue Op = getRoot();
7323 Res = DAG.getNode(Opcode: ISD::READSTEADYCOUNTER, DL: sdl,
7324 VTList: DAG.getVTList(VT1: MVT::i64, VT2: MVT::Other), N: Op);
7325 setValue(V: &I, NewN: Res);
7326 DAG.setRoot(Res.getValue(R: 1));
7327 return;
7328 }
7329 case Intrinsic::bitreverse:
7330 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::BITREVERSE, DL: sdl,
7331 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7332 Operand: getValue(V: I.getArgOperand(i: 0))));
7333 return;
7334 case Intrinsic::bswap:
7335 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::BSWAP, DL: sdl,
7336 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
7337 Operand: getValue(V: I.getArgOperand(i: 0))));
7338 return;
7339 case Intrinsic::cttz: {
7340 SDValue Arg = getValue(V: I.getArgOperand(i: 0));
7341 ConstantInt *CI = cast<ConstantInt>(Val: I.getArgOperand(i: 1));
7342 EVT Ty = Arg.getValueType();
7343 setValue(V: &I, NewN: DAG.getNode(Opcode: CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
7344 DL: sdl, VT: Ty, Operand: Arg));
7345 return;
7346 }
7347 case Intrinsic::ctlz: {
7348 SDValue Arg = getValue(V: I.getArgOperand(i: 0));
7349 ConstantInt *CI = cast<ConstantInt>(Val: I.getArgOperand(i: 1));
7350 EVT Ty = Arg.getValueType();
7351 setValue(V: &I, NewN: DAG.getNode(Opcode: CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
7352 DL: sdl, VT: Ty, Operand: Arg));
7353 return;
7354 }
7355 case Intrinsic::ctpop: {
7356 SDValue Arg = getValue(V: I.getArgOperand(i: 0));
7357 EVT Ty = Arg.getValueType();
7358 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CTPOP, DL: sdl, VT: Ty, Operand: Arg));
7359 return;
7360 }
7361 case Intrinsic::fshl:
7362 case Intrinsic::fshr: {
7363 bool IsFSHL = Intrinsic == Intrinsic::fshl;
7364 SDValue X = getValue(V: I.getArgOperand(i: 0));
7365 SDValue Y = getValue(V: I.getArgOperand(i: 1));
7366 SDValue Z = getValue(V: I.getArgOperand(i: 2));
7367 EVT VT = X.getValueType();
7368
7369 if (X == Y) {
7370 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
7371 setValue(V: &I, NewN: DAG.getNode(Opcode: RotateOpcode, DL: sdl, VT, N1: X, N2: Z));
7372 } else {
7373 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;
7374 setValue(V: &I, NewN: DAG.getNode(Opcode: FunnelOpcode, DL: sdl, VT, N1: X, N2: Y, N3: Z));
7375 }
7376 return;
7377 }
7378 case Intrinsic::clmul: {
7379 SDValue X = getValue(V: I.getArgOperand(i: 0));
7380 SDValue Y = getValue(V: I.getArgOperand(i: 1));
7381 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::CLMUL, DL: sdl, VT: X.getValueType(), N1: X, N2: Y));
7382 return;
7383 }
7384 case Intrinsic::sadd_sat: {
7385 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7386 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7387 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SADDSAT, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7388 return;
7389 }
7390 case Intrinsic::uadd_sat: {
7391 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7392 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7393 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UADDSAT, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7394 return;
7395 }
7396 case Intrinsic::ssub_sat: {
7397 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7398 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7399 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SSUBSAT, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7400 return;
7401 }
7402 case Intrinsic::usub_sat: {
7403 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7404 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7405 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::USUBSAT, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7406 return;
7407 }
7408 case Intrinsic::sshl_sat:
7409 case Intrinsic::ushl_sat: {
7410 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7411 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7412
7413 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
7414 LHSTy: Op1.getValueType(), DL: DAG.getDataLayout());
7415
7416 // Coerce the shift amount to the right type if we can. This exposes the
7417 // truncate or zext to optimization early.
7418 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
7419 assert(ShiftTy.getSizeInBits() >=
7420 Log2_32_Ceil(Op1.getValueSizeInBits()) &&
7421 "Unexpected shift type");
7422 Op2 = DAG.getZExtOrTrunc(Op: Op2, DL: getCurSDLoc(), VT: ShiftTy);
7423 }
7424
7425 unsigned Opc =
7426 Intrinsic == Intrinsic::sshl_sat ? ISD::SSHLSAT : ISD::USHLSAT;
7427 setValue(V: &I, NewN: DAG.getNode(Opcode: Opc, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7428 return;
7429 }
7430 case Intrinsic::smul_fix:
7431 case Intrinsic::umul_fix:
7432 case Intrinsic::smul_fix_sat:
7433 case Intrinsic::umul_fix_sat: {
7434 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7435 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7436 SDValue Op3 = getValue(V: I.getArgOperand(i: 2));
7437 setValue(V: &I, NewN: DAG.getNode(Opcode: FixedPointIntrinsicToOpcode(Intrinsic), DL: sdl,
7438 VT: Op1.getValueType(), N1: Op1, N2: Op2, N3: Op3));
7439 return;
7440 }
7441 case Intrinsic::sdiv_fix:
7442 case Intrinsic::udiv_fix:
7443 case Intrinsic::sdiv_fix_sat:
7444 case Intrinsic::udiv_fix_sat: {
7445 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7446 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7447 SDValue Op3 = getValue(V: I.getArgOperand(i: 2));
7448 setValue(V: &I, NewN: expandDivFix(Opcode: FixedPointIntrinsicToOpcode(Intrinsic), DL: sdl,
7449 LHS: Op1, RHS: Op2, Scale: Op3, DAG, TLI));
7450 return;
7451 }
7452 case Intrinsic::smax: {
7453 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7454 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7455 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SMAX, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7456 return;
7457 }
7458 case Intrinsic::smin: {
7459 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7460 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7461 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SMIN, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7462 return;
7463 }
7464 case Intrinsic::umax: {
7465 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7466 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7467 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UMAX, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7468 return;
7469 }
7470 case Intrinsic::umin: {
7471 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7472 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7473 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UMIN, DL: sdl, VT: Op1.getValueType(), N1: Op1, N2: Op2));
7474 return;
7475 }
7476 case Intrinsic::abs: {
7477 // TODO: Preserve "int min is poison" arg in SDAG?
7478 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7479 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::ABS, DL: sdl, VT: Op1.getValueType(), Operand: Op1));
7480 return;
7481 }
7482 case Intrinsic::scmp: {
7483 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7484 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7485 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7486 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::SCMP, DL: sdl, VT: DestVT, N1: Op1, N2: Op2));
7487 break;
7488 }
7489 case Intrinsic::ucmp: {
7490 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7491 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7492 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7493 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::UCMP, DL: sdl, VT: DestVT, N1: Op1, N2: Op2));
7494 break;
7495 }
7496 case Intrinsic::stackaddress:
7497 case Intrinsic::stacksave: {
7498 unsigned SDOpcode = Intrinsic == Intrinsic::stackaddress ? ISD::STACKADDRESS
7499 : ISD::STACKSAVE;
7500 SDValue Op = getRoot();
7501 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7502 Res = DAG.getNode(Opcode: SDOpcode, DL: sdl, VTList: DAG.getVTList(VT1: VT, VT2: MVT::Other), N: Op);
7503 setValue(V: &I, NewN: Res);
7504 DAG.setRoot(Res.getValue(R: 1));
7505 return;
7506 }
7507 case Intrinsic::stackrestore:
7508 Res = getValue(V: I.getArgOperand(i: 0));
7509 DAG.setRoot(DAG.getNode(Opcode: ISD::STACKRESTORE, DL: sdl, VT: MVT::Other, N1: getRoot(), N2: Res));
7510 return;
7511 case Intrinsic::get_dynamic_area_offset: {
7512 SDValue Op = getRoot();
7513 EVT ResTy = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7514 Res = DAG.getNode(Opcode: ISD::GET_DYNAMIC_AREA_OFFSET, DL: sdl, VTList: DAG.getVTList(VT: ResTy),
7515 N: Op);
7516 DAG.setRoot(Op);
7517 setValue(V: &I, NewN: Res);
7518 return;
7519 }
7520 case Intrinsic::stackguard: {
7521 MachineFunction &MF = DAG.getMachineFunction();
7522 const Module &M = *MF.getFunction().getParent();
7523 EVT PtrTy = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
7524 SDValue Chain = getRoot();
7525 if (TLI.useLoadStackGuardNode(M)) {
7526 Res = getLoadStackGuard(DAG, DL: sdl, Chain);
7527 Res = DAG.getPtrExtOrTrunc(Op: Res, DL: sdl, VT: PtrTy);
7528 } else {
7529 const Value *Global = TLI.getSDagStackGuard(M, Libcalls: DAG.getLibcalls());
7530 if (!Global) {
7531 LLVMContext &Ctx = *DAG.getContext();
7532 Ctx.diagnose(DI: DiagnosticInfoGeneric("unable to lower stackguard"));
7533 setValue(V: &I, NewN: DAG.getPOISON(VT: PtrTy));
7534 return;
7535 }
7536
7537 Align Align = DAG.getDataLayout().getPrefTypeAlign(Ty: Global->getType());
7538 Res = DAG.getLoad(VT: PtrTy, dl: sdl, Chain, Ptr: getValue(V: Global),
7539 PtrInfo: MachinePointerInfo(Global, 0), Alignment: Align,
7540 MMOFlags: MachineMemOperand::MOVolatile);
7541 }
7542 if (TLI.useStackGuardXorFP())
7543 Res = TLI.emitStackGuardXorFP(DAG, Val: Res, DL: sdl);
7544 DAG.setRoot(Chain);
7545 setValue(V: &I, NewN: Res);
7546 return;
7547 }
7548 case Intrinsic::stackprotector: {
7549 // Emit code into the DAG to store the stack guard onto the stack.
7550 MachineFunction &MF = DAG.getMachineFunction();
7551 MachineFrameInfo &MFI = MF.getFrameInfo();
7552 const Module &M = *MF.getFunction().getParent();
7553 SDValue Src, Chain = getRoot();
7554
7555 if (TLI.useLoadStackGuardNode(M))
7556 Src = getLoadStackGuard(DAG, DL: sdl, Chain);
7557 else
7558 Src = getValue(V: I.getArgOperand(i: 0)); // The guard's value.
7559
7560 AllocaInst *Slot = cast<AllocaInst>(Val: I.getArgOperand(i: 1));
7561
7562 int FI = FuncInfo.StaticAllocaMap[Slot];
7563 MFI.setStackProtectorIndex(FI);
7564 EVT PtrTy = TLI.getFrameIndexTy(DL: DAG.getDataLayout());
7565
7566 SDValue FIN = DAG.getFrameIndex(FI, VT: PtrTy);
7567
7568 // Store the stack protector onto the stack.
7569 Res = DAG.getStore(
7570 Chain, dl: sdl, Val: Src, Ptr: FIN,
7571 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI),
7572 Alignment: MaybeAlign(), MMOFlags: MachineMemOperand::MOVolatile);
7573 setValue(V: &I, NewN: Res);
7574 DAG.setRoot(Res);
7575 return;
7576 }
7577 case Intrinsic::objectsize:
7578 llvm_unreachable("llvm.objectsize.* should have been lowered already");
7579
7580 case Intrinsic::is_constant:
7581 llvm_unreachable("llvm.is.constant.* should have been lowered already");
7582
7583 case Intrinsic::annotation:
7584 case Intrinsic::ptr_annotation:
7585 case Intrinsic::launder_invariant_group:
7586 case Intrinsic::strip_invariant_group:
7587 // Drop the intrinsic, but forward the value
7588 setValue(V: &I, NewN: getValue(V: I.getOperand(i_nocapture: 0)));
7589 return;
7590
7591 case Intrinsic::type_test:
7592 case Intrinsic::public_type_test:
7593 reportFatalUsageError(reason: "llvm.type.test intrinsic must be lowered by the "
7594 "LowerTypeTests pass before code generation");
7595 return;
7596
7597 case Intrinsic::assume:
7598 case Intrinsic::experimental_noalias_scope_decl:
7599 case Intrinsic::var_annotation:
7600 case Intrinsic::sideeffect:
7601 // Discard annotate attributes, noalias scope declarations, assumptions, and
7602 // artificial side-effects.
7603 return;
7604
7605 case Intrinsic::codeview_annotation: {
7606 // Emit a label associated with this metadata.
7607 MachineFunction &MF = DAG.getMachineFunction();
7608 MCSymbol *Label = MF.getContext().createTempSymbol(Name: "annotation", AlwaysAddSuffix: true);
7609 Metadata *MD = cast<MetadataAsValue>(Val: I.getArgOperand(i: 0))->getMetadata();
7610 MF.addCodeViewAnnotation(Label, MD: cast<MDNode>(Val: MD));
7611 Res = DAG.getLabelNode(Opcode: ISD::ANNOTATION_LABEL, dl: sdl, Root: getRoot(), Label);
7612 DAG.setRoot(Res);
7613 return;
7614 }
7615
7616 case Intrinsic::init_trampoline: {
7617 const Function *F = cast<Function>(Val: I.getArgOperand(i: 1)->stripPointerCasts());
7618
7619 SDValue Ops[6];
7620 Ops[0] = getRoot();
7621 Ops[1] = getValue(V: I.getArgOperand(i: 0));
7622 Ops[2] = getValue(V: I.getArgOperand(i: 1));
7623 Ops[3] = getValue(V: I.getArgOperand(i: 2));
7624 Ops[4] = DAG.getSrcValue(v: I.getArgOperand(i: 0));
7625 Ops[5] = DAG.getSrcValue(v: F);
7626
7627 Res = DAG.getNode(Opcode: ISD::INIT_TRAMPOLINE, DL: sdl, VT: MVT::Other, Ops);
7628
7629 DAG.setRoot(Res);
7630 return;
7631 }
7632 case Intrinsic::adjust_trampoline:
7633 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::ADJUST_TRAMPOLINE, DL: sdl,
7634 VT: TLI.getPointerTy(DL: DAG.getDataLayout()),
7635 Operand: getValue(V: I.getArgOperand(i: 0))));
7636 return;
7637 case Intrinsic::gcroot: {
7638 assert(DAG.getMachineFunction().getFunction().hasGC() &&
7639 "only valid in functions with gc specified, enforced by Verifier");
7640 assert(GFI && "implied by previous");
7641 const Value *Alloca = I.getArgOperand(i: 0)->stripPointerCasts();
7642 const Constant *TypeMap = cast<Constant>(Val: I.getArgOperand(i: 1));
7643
7644 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Val: getValue(V: Alloca).getNode());
7645 GFI->addStackRoot(Num: FI->getIndex(), Metadata: TypeMap);
7646 return;
7647 }
7648 case Intrinsic::gcread:
7649 case Intrinsic::gcwrite:
7650 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
7651 case Intrinsic::get_rounding:
7652 Res = DAG.getNode(Opcode: ISD::GET_ROUNDING, DL: sdl, ResultTys: {MVT::i32, MVT::Other}, Ops: getRoot());
7653 setValue(V: &I, NewN: Res);
7654 DAG.setRoot(Res.getValue(R: 1));
7655 return;
7656
7657 case Intrinsic::expect:
7658 case Intrinsic::expect_with_probability:
7659 // Just replace __builtin_expect(exp, c) and
7660 // __builtin_expect_with_probability(exp, c, p) with EXP.
7661 setValue(V: &I, NewN: getValue(V: I.getArgOperand(i: 0)));
7662 return;
7663
7664 case Intrinsic::ubsantrap:
7665 case Intrinsic::debugtrap:
7666 case Intrinsic::trap: {
7667 StringRef TrapFuncName =
7668 I.getAttributes().getFnAttr(Kind: "trap-func-name").getValueAsString();
7669 if (TrapFuncName.empty()) {
7670 switch (Intrinsic) {
7671 case Intrinsic::trap:
7672 DAG.setRoot(DAG.getNode(Opcode: ISD::TRAP, DL: sdl, VT: MVT::Other, Operand: getRoot()));
7673 break;
7674 case Intrinsic::debugtrap:
7675 DAG.setRoot(DAG.getNode(Opcode: ISD::DEBUGTRAP, DL: sdl, VT: MVT::Other, Operand: getRoot()));
7676 break;
7677 case Intrinsic::ubsantrap:
7678 DAG.setRoot(DAG.getNode(
7679 Opcode: ISD::UBSANTRAP, DL: sdl, VT: MVT::Other, N1: getRoot(),
7680 N2: DAG.getTargetConstant(
7681 Val: cast<ConstantInt>(Val: I.getArgOperand(i: 0))->getZExtValue(), DL: sdl,
7682 VT: MVT::i32)));
7683 break;
7684 default: llvm_unreachable("unknown trap intrinsic");
7685 }
7686 DAG.addNoMergeSiteInfo(Node: DAG.getRoot().getNode(),
7687 NoMerge: I.hasFnAttr(Kind: Attribute::NoMerge));
7688 return;
7689 }
7690 TargetLowering::ArgListTy Args;
7691 if (Intrinsic == Intrinsic::ubsantrap) {
7692 Value *Arg = I.getArgOperand(i: 0);
7693 Args.emplace_back(args&: Arg, args: getValue(V: Arg));
7694 }
7695
7696 TargetLowering::CallLoweringInfo CLI(DAG);
7697 CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee(
7698 CC: CallingConv::C, ResultType: I.getType(),
7699 Target: DAG.getExternalSymbol(Sym: TrapFuncName.data(),
7700 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
7701 ArgsList: std::move(Args));
7702 CLI.NoMerge = I.hasFnAttr(Kind: Attribute::NoMerge);
7703 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
7704 DAG.setRoot(Result.second);
7705 return;
7706 }
7707
7708 case Intrinsic::allow_runtime_check:
7709 case Intrinsic::allow_ubsan_check:
7710 setValue(V: &I, NewN: getValue(V: ConstantInt::getTrue(Ty: I.getType())));
7711 return;
7712
7713 case Intrinsic::uadd_with_overflow:
7714 case Intrinsic::sadd_with_overflow:
7715 case Intrinsic::usub_with_overflow:
7716 case Intrinsic::ssub_with_overflow:
7717 case Intrinsic::umul_with_overflow:
7718 case Intrinsic::smul_with_overflow: {
7719 ISD::NodeType Op;
7720 switch (Intrinsic) {
7721 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7722 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
7723 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
7724 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
7725 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
7726 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
7727 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
7728 }
7729 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
7730 SDValue Op2 = getValue(V: I.getArgOperand(i: 1));
7731
7732 EVT ResultVT = Op1.getValueType();
7733 EVT OverflowVT = ResultVT.changeElementType(Context&: *Context, EltVT: MVT::i1);
7734
7735 SDVTList VTs = DAG.getVTList(VT1: ResultVT, VT2: OverflowVT);
7736 setValue(V: &I, NewN: DAG.getNode(Opcode: Op, DL: sdl, VTList: VTs, N1: Op1, N2: Op2));
7737 return;
7738 }
7739 case Intrinsic::prefetch: {
7740 SDValue Ops[5];
7741 unsigned rw = cast<ConstantInt>(Val: I.getArgOperand(i: 1))->getZExtValue();
7742 auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore;
7743 Ops[0] = DAG.getRoot();
7744 Ops[1] = getValue(V: I.getArgOperand(i: 0));
7745 Ops[2] = DAG.getTargetConstant(Val: *cast<ConstantInt>(Val: I.getArgOperand(i: 1)), DL: sdl,
7746 VT: MVT::i32);
7747 Ops[3] = DAG.getTargetConstant(Val: *cast<ConstantInt>(Val: I.getArgOperand(i: 2)), DL: sdl,
7748 VT: MVT::i32);
7749 Ops[4] = DAG.getTargetConstant(Val: *cast<ConstantInt>(Val: I.getArgOperand(i: 3)), DL: sdl,
7750 VT: MVT::i32);
7751 SDValue Result = DAG.getMemIntrinsicNode(
7752 Opcode: ISD::PREFETCH, dl: sdl, VTList: DAG.getVTList(VT: MVT::Other), Ops,
7753 MemVT: EVT::getIntegerVT(Context&: *Context, BitWidth: 8), PtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
7754 /* align */ Alignment: std::nullopt, Flags);
7755
7756 // Chain the prefetch in parallel with any pending loads, to stay out of
7757 // the way of later optimizations.
7758 PendingLoads.push_back(Elt: Result);
7759 Result = getRoot();
7760 DAG.setRoot(Result);
7761 return;
7762 }
7763 case Intrinsic::lifetime_start:
7764 case Intrinsic::lifetime_end: {
7765 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
7766 // Stack coloring is not enabled in O0, discard region information.
7767 if (TM.getOptLevel() == CodeGenOptLevel::None)
7768 return;
7769
7770 const AllocaInst *LifetimeObject = dyn_cast<AllocaInst>(Val: I.getArgOperand(i: 0));
7771 if (!LifetimeObject)
7772 return;
7773
7774 // First check that the Alloca is static, otherwise it won't have a
7775 // valid frame index.
7776 auto SI = FuncInfo.StaticAllocaMap.find(Val: LifetimeObject);
7777 if (SI == FuncInfo.StaticAllocaMap.end())
7778 return;
7779
7780 const int FrameIndex = SI->second;
7781 Res = DAG.getLifetimeNode(IsStart, dl: sdl, Chain: getRoot(), FrameIndex);
7782 DAG.setRoot(Res);
7783 return;
7784 }
7785 case Intrinsic::pseudoprobe: {
7786 auto Guid = cast<ConstantInt>(Val: I.getArgOperand(i: 0))->getZExtValue();
7787 auto Index = cast<ConstantInt>(Val: I.getArgOperand(i: 1))->getZExtValue();
7788 auto Attr = cast<ConstantInt>(Val: I.getArgOperand(i: 2))->getZExtValue();
7789 Res = DAG.getPseudoProbeNode(Dl: sdl, Chain: getRoot(), Guid, Index, Attr);
7790 DAG.setRoot(Res);
7791 return;
7792 }
7793 case Intrinsic::invariant_start:
7794 // Discard region information.
7795 setValue(V: &I,
7796 NewN: DAG.getUNDEF(VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType())));
7797 return;
7798 case Intrinsic::invariant_end:
7799 // Discard region information.
7800 return;
7801 case Intrinsic::clear_cache: {
7802 SDValue InputChain = DAG.getRoot();
7803 SDValue StartVal = getValue(V: I.getArgOperand(i: 0));
7804 SDValue EndVal = getValue(V: I.getArgOperand(i: 1));
7805 Res = DAG.getNode(Opcode: ISD::CLEAR_CACHE, DL: sdl, VTList: DAG.getVTList(VT: MVT::Other),
7806 Ops: {InputChain, StartVal, EndVal});
7807 setValue(V: &I, NewN: Res);
7808 DAG.setRoot(Res);
7809 return;
7810 }
7811 case Intrinsic::donothing:
7812 case Intrinsic::seh_try_begin:
7813 case Intrinsic::seh_scope_begin:
7814 case Intrinsic::seh_try_end:
7815 case Intrinsic::seh_scope_end:
7816 // ignore
7817 return;
7818 case Intrinsic::experimental_stackmap:
7819 visitStackmap(I);
7820 return;
7821 case Intrinsic::experimental_patchpoint_void:
7822 case Intrinsic::experimental_patchpoint:
7823 visitPatchpoint(CB: I);
7824 return;
7825 case Intrinsic::experimental_gc_statepoint:
7826 LowerStatepoint(I: cast<GCStatepointInst>(Val: I));
7827 return;
7828 case Intrinsic::experimental_gc_result:
7829 visitGCResult(I: cast<GCResultInst>(Val: I));
7830 return;
7831 case Intrinsic::experimental_gc_relocate:
7832 visitGCRelocate(Relocate: cast<GCRelocateInst>(Val: I));
7833 return;
7834 case Intrinsic::instrprof_cover:
7835 llvm_unreachable("instrprof failed to lower a cover");
7836 case Intrinsic::instrprof_increment:
7837 llvm_unreachable("instrprof failed to lower an increment");
7838 case Intrinsic::instrprof_timestamp:
7839 llvm_unreachable("instrprof failed to lower a timestamp");
7840 case Intrinsic::instrprof_value_profile:
7841 llvm_unreachable("instrprof failed to lower a value profiling call");
7842 case Intrinsic::instrprof_mcdc_parameters:
7843 llvm_unreachable("instrprof failed to lower mcdc parameters");
7844 case Intrinsic::instrprof_mcdc_tvbitmap_update:
7845 llvm_unreachable("instrprof failed to lower an mcdc tvbitmap update");
7846 case Intrinsic::localescape: {
7847 MachineFunction &MF = DAG.getMachineFunction();
7848 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
7849
7850 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
7851 // is the same on all targets.
7852 for (unsigned Idx = 0, E = I.arg_size(); Idx < E; ++Idx) {
7853 Value *Arg = I.getArgOperand(i: Idx)->stripPointerCasts();
7854 if (isa<ConstantPointerNull>(Val: Arg))
7855 continue; // Skip null pointers. They represent a hole in index space.
7856 AllocaInst *Slot = cast<AllocaInst>(Val: Arg);
7857 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
7858 "can only escape static allocas");
7859 int FI = FuncInfo.StaticAllocaMap[Slot];
7860 MCSymbol *FrameAllocSym = MF.getContext().getOrCreateFrameAllocSymbol(
7861 FuncName: GlobalValue::dropLLVMManglingEscape(Name: MF.getName()), Idx);
7862 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD: dl,
7863 MCID: TII->get(Opcode: TargetOpcode::LOCAL_ESCAPE))
7864 .addSym(Sym: FrameAllocSym)
7865 .addFrameIndex(Idx: FI);
7866 }
7867
7868 return;
7869 }
7870
7871 case Intrinsic::localrecover: {
7872 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
7873 MachineFunction &MF = DAG.getMachineFunction();
7874
7875 // Get the symbol that defines the frame offset.
7876 auto *Fn = cast<Function>(Val: I.getArgOperand(i: 0)->stripPointerCasts());
7877 auto *Idx = cast<ConstantInt>(Val: I.getArgOperand(i: 2));
7878 unsigned IdxVal =
7879 unsigned(Idx->getLimitedValue(Limit: std::numeric_limits<int>::max()));
7880 MCSymbol *FrameAllocSym = MF.getContext().getOrCreateFrameAllocSymbol(
7881 FuncName: GlobalValue::dropLLVMManglingEscape(Name: Fn->getName()), Idx: IdxVal);
7882
7883 Value *FP = I.getArgOperand(i: 1);
7884 SDValue FPVal = getValue(V: FP);
7885 EVT PtrVT = FPVal.getValueType();
7886
7887 // Create a MCSymbol for the label to avoid any target lowering
7888 // that would make this PC relative.
7889 SDValue OffsetSym = DAG.getMCSymbol(Sym: FrameAllocSym, VT: PtrVT);
7890 SDValue OffsetVal =
7891 DAG.getNode(Opcode: ISD::LOCAL_RECOVER, DL: sdl, VT: PtrVT, Operand: OffsetSym);
7892
7893 // Add the offset to the FP.
7894 SDValue Add = DAG.getMemBasePlusOffset(Base: FPVal, Offset: OffsetVal, DL: sdl);
7895 setValue(V: &I, NewN: Add);
7896
7897 return;
7898 }
7899
7900 case Intrinsic::fake_use: {
7901 Value *V = I.getArgOperand(i: 0);
7902 SDValue Ops[2];
7903 // For Values not declared or previously used in this basic block, the
7904 // NodeMap will not have an entry, and `getValue` will assert if V has no
7905 // valid register value.
7906 auto FakeUseValue = [&]() -> SDValue {
7907 SDValue &N = NodeMap[V];
7908 if (N.getNode())
7909 return N;
7910
7911 // If there's a virtual register allocated and initialized for this
7912 // value, use it.
7913 if (SDValue copyFromReg = getCopyFromRegs(V, Ty: V->getType()))
7914 return copyFromReg;
7915 // FIXME: Do we want to preserve constants? It seems pointless.
7916 if (isa<Constant>(Val: V))
7917 return getValue(V);
7918 return SDValue();
7919 }();
7920 if (!FakeUseValue || FakeUseValue.isUndef())
7921 return;
7922 Ops[0] = getRoot();
7923 Ops[1] = FakeUseValue;
7924 // Also, do not translate a fake use with an undef operand, or any other
7925 // empty SDValues.
7926 if (!Ops[1] || Ops[1].isUndef())
7927 return;
7928 DAG.setRoot(DAG.getNode(Opcode: ISD::FAKE_USE, DL: sdl, VT: MVT::Other, Ops));
7929 return;
7930 }
7931
7932 case Intrinsic::reloc_none: {
7933 Metadata *MD = cast<MetadataAsValue>(Val: I.getArgOperand(i: 0))->getMetadata();
7934 StringRef SymbolName = cast<MDString>(Val: MD)->getString();
7935 SDValue Ops[2] = {
7936 getRoot(),
7937 DAG.getTargetExternalSymbol(
7938 Sym: SymbolName.data(), VT: TLI.getProgramPointerTy(DL: DAG.getDataLayout()))};
7939 DAG.setRoot(DAG.getNode(Opcode: ISD::RELOC_NONE, DL: sdl, VT: MVT::Other, Ops));
7940 return;
7941 }
7942
7943 case Intrinsic::cond_loop: {
7944 SDValue InputChain = DAG.getRoot();
7945 SDValue P = getValue(V: I.getArgOperand(i: 0));
7946 Res = DAG.getNode(Opcode: ISD::COND_LOOP, DL: sdl, VTList: DAG.getVTList(VT: MVT::Other),
7947 Ops: {InputChain, P});
7948 setValue(V: &I, NewN: Res);
7949 DAG.setRoot(Res);
7950 return;
7951 }
7952
7953 case Intrinsic::eh_exceptionpointer:
7954 case Intrinsic::eh_exceptioncode: {
7955 // Get the exception pointer vreg, copy from it, and resize it to fit.
7956 const auto *CPI = cast<CatchPadInst>(Val: I.getArgOperand(i: 0));
7957 MVT PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
7958 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(VT: PtrVT);
7959 Register VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, RC: PtrRC);
7960 SDValue N = DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl: sdl, Reg: VReg, VT: PtrVT);
7961 if (Intrinsic == Intrinsic::eh_exceptioncode)
7962 N = DAG.getZExtOrTrunc(Op: N, DL: sdl, VT: MVT::i32);
7963 setValue(V: &I, NewN: N);
7964 return;
7965 }
7966 case Intrinsic::xray_customevent: {
7967 // Here we want to make sure that the intrinsic behaves as if it has a
7968 // specific calling convention.
7969 const auto &Triple = DAG.getTarget().getTargetTriple();
7970 if (!Triple.isAArch64(PointerWidth: 64) && Triple.getArch() != Triple::x86_64)
7971 return;
7972
7973 SmallVector<SDValue, 8> Ops;
7974
7975 // We want to say that we always want the arguments in registers.
7976 SDValue LogEntryVal = getValue(V: I.getArgOperand(i: 0));
7977 SDValue StrSizeVal = getValue(V: I.getArgOperand(i: 1));
7978 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
7979 SDValue Chain = getRoot();
7980 Ops.push_back(Elt: LogEntryVal);
7981 Ops.push_back(Elt: StrSizeVal);
7982 Ops.push_back(Elt: Chain);
7983
7984 // We need to enforce the calling convention for the callsite, so that
7985 // argument ordering is enforced correctly, and that register allocation can
7986 // see that some registers may be assumed clobbered and have to preserve
7987 // them across calls to the intrinsic.
7988 MachineSDNode *MN = DAG.getMachineNode(Opcode: TargetOpcode::PATCHABLE_EVENT_CALL,
7989 dl: sdl, VTs: NodeTys, Ops);
7990 SDValue patchableNode = SDValue(MN, 0);
7991 DAG.setRoot(patchableNode);
7992 setValue(V: &I, NewN: patchableNode);
7993 return;
7994 }
7995 case Intrinsic::xray_typedevent: {
7996 // Here we want to make sure that the intrinsic behaves as if it has a
7997 // specific calling convention.
7998 const auto &Triple = DAG.getTarget().getTargetTriple();
7999 if (!Triple.isAArch64(PointerWidth: 64) && Triple.getArch() != Triple::x86_64)
8000 return;
8001
8002 SmallVector<SDValue, 8> Ops;
8003
8004 // We want to say that we always want the arguments in registers.
8005 // It's unclear to me how manipulating the selection DAG here forces callers
8006 // to provide arguments in registers instead of on the stack.
8007 SDValue LogTypeId = getValue(V: I.getArgOperand(i: 0));
8008 SDValue LogEntryVal = getValue(V: I.getArgOperand(i: 1));
8009 SDValue StrSizeVal = getValue(V: I.getArgOperand(i: 2));
8010 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
8011 SDValue Chain = getRoot();
8012 Ops.push_back(Elt: LogTypeId);
8013 Ops.push_back(Elt: LogEntryVal);
8014 Ops.push_back(Elt: StrSizeVal);
8015 Ops.push_back(Elt: Chain);
8016
8017 // We need to enforce the calling convention for the callsite, so that
8018 // argument ordering is enforced correctly, and that register allocation can
8019 // see that some registers may be assumed clobbered and have to preserve
8020 // them across calls to the intrinsic.
8021 MachineSDNode *MN = DAG.getMachineNode(
8022 Opcode: TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, dl: sdl, VTs: NodeTys, Ops);
8023 SDValue patchableNode = SDValue(MN, 0);
8024 DAG.setRoot(patchableNode);
8025 setValue(V: &I, NewN: patchableNode);
8026 return;
8027 }
8028 case Intrinsic::experimental_deoptimize:
8029 LowerDeoptimizeCall(CI: &I);
8030 return;
8031 case Intrinsic::stepvector:
8032 visitStepVector(I);
8033 return;
8034 case Intrinsic::vector_reduce_fadd:
8035 case Intrinsic::vector_reduce_fmul:
8036 case Intrinsic::vector_reduce_add:
8037 case Intrinsic::vector_reduce_mul:
8038 case Intrinsic::vector_reduce_and:
8039 case Intrinsic::vector_reduce_or:
8040 case Intrinsic::vector_reduce_xor:
8041 case Intrinsic::vector_reduce_smax:
8042 case Intrinsic::vector_reduce_smin:
8043 case Intrinsic::vector_reduce_umax:
8044 case Intrinsic::vector_reduce_umin:
8045 case Intrinsic::vector_reduce_fmax:
8046 case Intrinsic::vector_reduce_fmin:
8047 case Intrinsic::vector_reduce_fmaximum:
8048 case Intrinsic::vector_reduce_fminimum:
8049 visitVectorReduce(I, Intrinsic);
8050 return;
8051
8052 case Intrinsic::icall_branch_funnel: {
8053 SmallVector<SDValue, 16> Ops;
8054 Ops.push_back(Elt: getValue(V: I.getArgOperand(i: 0)));
8055
8056 int64_t Offset;
8057 auto *Base = dyn_cast<GlobalObject>(Val: GetPointerBaseWithConstantOffset(
8058 Ptr: I.getArgOperand(i: 1), Offset, DL: DAG.getDataLayout()));
8059 if (!Base)
8060 report_fatal_error(
8061 reason: "llvm.icall.branch.funnel operand must be a GlobalValue");
8062 Ops.push_back(Elt: DAG.getTargetGlobalAddress(GV: Base, DL: sdl, VT: MVT::i64, offset: 0));
8063
8064 struct BranchFunnelTarget {
8065 int64_t Offset;
8066 SDValue Target;
8067 };
8068 SmallVector<BranchFunnelTarget, 8> Targets;
8069
8070 for (unsigned Op = 1, N = I.arg_size(); Op != N; Op += 2) {
8071 auto *ElemBase = dyn_cast<GlobalObject>(Val: GetPointerBaseWithConstantOffset(
8072 Ptr: I.getArgOperand(i: Op), Offset, DL: DAG.getDataLayout()));
8073 if (ElemBase != Base)
8074 report_fatal_error(reason: "all llvm.icall.branch.funnel operands must refer "
8075 "to the same GlobalValue");
8076
8077 SDValue Val = getValue(V: I.getArgOperand(i: Op + 1));
8078 auto *GA = dyn_cast<GlobalAddressSDNode>(Val);
8079 if (!GA)
8080 report_fatal_error(
8081 reason: "llvm.icall.branch.funnel operand must be a GlobalValue");
8082 Targets.push_back(Elt: {.Offset: Offset, .Target: DAG.getTargetGlobalAddress(
8083 GV: GA->getGlobal(), DL: sdl, VT: Val.getValueType(),
8084 offset: GA->getOffset())});
8085 }
8086 llvm::sort(C&: Targets,
8087 Comp: [](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) {
8088 return T1.Offset < T2.Offset;
8089 });
8090
8091 for (auto &T : Targets) {
8092 Ops.push_back(Elt: DAG.getTargetConstant(Val: T.Offset, DL: sdl, VT: MVT::i32));
8093 Ops.push_back(Elt: T.Target);
8094 }
8095
8096 Ops.push_back(Elt: DAG.getRoot()); // Chain
8097 SDValue N(DAG.getMachineNode(Opcode: TargetOpcode::ICALL_BRANCH_FUNNEL, dl: sdl,
8098 VT: MVT::Other, Ops),
8099 0);
8100 DAG.setRoot(N);
8101 setValue(V: &I, NewN: N);
8102 HasTailCall = true;
8103 return;
8104 }
8105
8106 case Intrinsic::wasm_landingpad_index:
8107 // Information this intrinsic contained has been transferred to
8108 // MachineFunction in SelectionDAGISel::PrepareEHLandingPad. We can safely
8109 // delete it now.
8110 return;
8111
8112 case Intrinsic::aarch64_settag:
8113 case Intrinsic::aarch64_settag_zero: {
8114 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
8115 bool ZeroMemory = Intrinsic == Intrinsic::aarch64_settag_zero;
8116 SDValue Val = TSI.EmitTargetCodeForSetTag(
8117 DAG, dl: sdl, Chain: getRoot(), Addr: getValue(V: I.getArgOperand(i: 0)),
8118 Size: getValue(V: I.getArgOperand(i: 1)), DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
8119 ZeroData: ZeroMemory);
8120 DAG.setRoot(Val);
8121 setValue(V: &I, NewN: Val);
8122 return;
8123 }
8124 case Intrinsic::amdgcn_cs_chain: {
8125 // At this point we don't care if it's amdgpu_cs_chain or
8126 // amdgpu_cs_chain_preserve.
8127 CallingConv::ID CC = CallingConv::AMDGPU_CS_Chain;
8128
8129 Type *RetTy = I.getType();
8130 assert(RetTy->isVoidTy() && "Should not return");
8131
8132 SDValue Callee = getValue(V: I.getOperand(i_nocapture: 0));
8133
8134 // We only have 2 actual args: one for the SGPRs and one for the VGPRs.
8135 // We'll also tack the value of the EXEC mask at the end.
8136 TargetLowering::ArgListTy Args;
8137 Args.reserve(n: 3);
8138
8139 for (unsigned Idx : {2, 3, 1}) {
8140 TargetLowering::ArgListEntry Arg(getValue(V: I.getOperand(i_nocapture: Idx)),
8141 I.getOperand(i_nocapture: Idx)->getType());
8142 Arg.setAttributes(Call: &I, ArgIdx: Idx);
8143 Args.push_back(x: Arg);
8144 }
8145
8146 assert(Args[0].IsInReg && "SGPR args should be marked inreg");
8147 assert(!Args[1].IsInReg && "VGPR args should not be marked inreg");
8148 Args[2].IsInReg = true; // EXEC should be inreg
8149
8150 // Forward the flags and any additional arguments.
8151 for (unsigned Idx = 4; Idx < I.arg_size(); ++Idx) {
8152 TargetLowering::ArgListEntry Arg(getValue(V: I.getOperand(i_nocapture: Idx)),
8153 I.getOperand(i_nocapture: Idx)->getType());
8154 Arg.setAttributes(Call: &I, ArgIdx: Idx);
8155 Args.push_back(x: Arg);
8156 }
8157
8158 TargetLowering::CallLoweringInfo CLI(DAG);
8159 CLI.setDebugLoc(getCurSDLoc())
8160 .setChain(getRoot())
8161 .setCallee(CC, ResultType: RetTy, Target: Callee, ArgsList: std::move(Args))
8162 .setNoReturn(true)
8163 .setTailCall(true)
8164 .setConvergent(I.isConvergent());
8165 CLI.CB = &I;
8166 std::pair<SDValue, SDValue> Result =
8167 lowerInvokable(CLI, /*EHPadBB*/ nullptr);
8168 (void)Result;
8169 assert(!Result.first.getNode() && !Result.second.getNode() &&
8170 "Should've lowered as tail call");
8171
8172 HasTailCall = true;
8173 return;
8174 }
8175 case Intrinsic::amdgcn_call_whole_wave: {
8176 TargetLowering::ArgListTy Args;
8177 bool isTailCall = I.isTailCall();
8178
8179 // The first argument is the callee. Skip it when assembling the call args.
8180 for (unsigned Idx = 1; Idx < I.arg_size(); ++Idx) {
8181 TargetLowering::ArgListEntry Arg(getValue(V: I.getArgOperand(i: Idx)),
8182 I.getArgOperand(i: Idx)->getType());
8183 Arg.setAttributes(Call: &I, ArgIdx: Idx);
8184
8185 // If we have an explicit sret argument that is an Instruction, (i.e., it
8186 // might point to function-local memory), we can't meaningfully tail-call.
8187 if (Arg.IsSRet && isa<Instruction>(Val: I.getArgOperand(i: Idx)))
8188 isTailCall = false;
8189
8190 Args.push_back(x: Arg);
8191 }
8192
8193 SDValue ConvControlToken;
8194 if (auto Bundle = I.getOperandBundle(ID: LLVMContext::OB_convergencectrl)) {
8195 auto *Token = Bundle->Inputs[0].get();
8196 ConvControlToken = getValue(V: Token);
8197 }
8198
8199 TargetLowering::CallLoweringInfo CLI(DAG);
8200 CLI.setDebugLoc(getCurSDLoc())
8201 .setChain(getRoot())
8202 .setCallee(CC: CallingConv::AMDGPU_Gfx_WholeWave, ResultType: I.getType(),
8203 Target: getValue(V: I.getArgOperand(i: 0)), ArgsList: std::move(Args))
8204 .setTailCall(isTailCall && canTailCall(CB: I))
8205 .setIsPreallocated(
8206 I.countOperandBundlesOfType(ID: LLVMContext::OB_preallocated) != 0)
8207 .setConvergent(I.isConvergent())
8208 .setConvergenceControlToken(ConvControlToken);
8209 CLI.CB = &I;
8210
8211 std::pair<SDValue, SDValue> Result =
8212 lowerInvokable(CLI, /*EHPadBB=*/nullptr);
8213
8214 if (Result.first.getNode())
8215 setValue(V: &I, NewN: Result.first);
8216 return;
8217 }
8218 case Intrinsic::ptrmask: {
8219 SDValue Ptr = getValue(V: I.getOperand(i_nocapture: 0));
8220 SDValue Mask = getValue(V: I.getOperand(i_nocapture: 1));
8221
8222 // On arm64_32, pointers are 32 bits when stored in memory, but
8223 // zero-extended to 64 bits when in registers. Thus the mask is 32 bits to
8224 // match the index type, but the pointer is 64 bits, so the mask must be
8225 // zero-extended up to 64 bits to match the pointer.
8226 EVT PtrVT =
8227 TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getOperand(i_nocapture: 0)->getType());
8228 EVT MemVT =
8229 TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getOperand(i_nocapture: 0)->getType());
8230 assert(PtrVT == Ptr.getValueType());
8231 if (Mask.getValueType().getFixedSizeInBits() < MemVT.getFixedSizeInBits()) {
8232 // For AMDGPU buffer descriptors the mask is 48 bits, but the pointer is
8233 // 128-bit, so we have to pad the mask with ones for unused bits.
8234 auto HighOnes = DAG.getNode(
8235 Opcode: ISD::SHL, DL: sdl, VT: PtrVT, N1: DAG.getAllOnesConstant(DL: sdl, VT: PtrVT),
8236 N2: DAG.getShiftAmountConstant(Val: Mask.getValueType().getFixedSizeInBits(),
8237 VT: PtrVT, DL: sdl));
8238 Mask = DAG.getNode(Opcode: ISD::OR, DL: sdl, VT: PtrVT,
8239 N1: DAG.getZExtOrTrunc(Op: Mask, DL: sdl, VT: PtrVT), N2: HighOnes);
8240 } else if (Mask.getValueType() != PtrVT)
8241 Mask = DAG.getPtrExtOrTrunc(Op: Mask, DL: sdl, VT: PtrVT);
8242
8243 assert(Mask.getValueType() == PtrVT);
8244 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::AND, DL: sdl, VT: PtrVT, N1: Ptr, N2: Mask));
8245 return;
8246 }
8247 case Intrinsic::threadlocal_address: {
8248 setValue(V: &I, NewN: getValue(V: I.getOperand(i_nocapture: 0)));
8249 return;
8250 }
8251 case Intrinsic::get_active_lane_mask: {
8252 EVT CCVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8253 SDValue Index = getValue(V: I.getOperand(i_nocapture: 0));
8254 SDValue TripCount = getValue(V: I.getOperand(i_nocapture: 1));
8255 EVT ElementVT = Index.getValueType();
8256
8257 if (!TLI.shouldExpandGetActiveLaneMask(VT: CCVT, OpVT: ElementVT)) {
8258 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::GET_ACTIVE_LANE_MASK, DL: sdl, VT: CCVT, N1: Index,
8259 N2: TripCount));
8260 return;
8261 }
8262
8263 EVT VecTy = EVT::getVectorVT(Context&: *DAG.getContext(), VT: ElementVT,
8264 EC: CCVT.getVectorElementCount());
8265
8266 SDValue VectorIndex = DAG.getSplat(VT: VecTy, DL: sdl, Op: Index);
8267 SDValue VectorTripCount = DAG.getSplat(VT: VecTy, DL: sdl, Op: TripCount);
8268 SDValue VectorStep = DAG.getStepVector(DL: sdl, ResVT: VecTy);
8269 SDValue VectorInduction = DAG.getNode(
8270 Opcode: ISD::UADDSAT, DL: sdl, VT: VecTy, N1: VectorIndex, N2: VectorStep);
8271 SDValue SetCC = DAG.getSetCC(DL: sdl, VT: CCVT, LHS: VectorInduction,
8272 RHS: VectorTripCount, Cond: ISD::CondCode::SETULT);
8273 setValue(V: &I, NewN: SetCC);
8274 return;
8275 }
8276 case Intrinsic::experimental_get_vector_length: {
8277 assert(cast<ConstantInt>(I.getOperand(1))->getSExtValue() > 0 &&
8278 "Expected positive VF");
8279 unsigned VF = cast<ConstantInt>(Val: I.getOperand(i_nocapture: 1))->getZExtValue();
8280 bool IsScalable = cast<ConstantInt>(Val: I.getOperand(i_nocapture: 2))->isOne();
8281
8282 SDValue Count = getValue(V: I.getOperand(i_nocapture: 0));
8283 EVT CountVT = Count.getValueType();
8284
8285 if (!TLI.shouldExpandGetVectorLength(CountVT, VF, IsScalable)) {
8286 visitTargetIntrinsic(I, Intrinsic);
8287 return;
8288 }
8289
8290 // Expand to a umin between the trip count and the maximum elements the type
8291 // can hold.
8292 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8293
8294 // Extend the trip count to at least the result VT.
8295 if (CountVT.bitsLT(VT)) {
8296 Count = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: sdl, VT, Operand: Count);
8297 CountVT = VT;
8298 }
8299
8300 SDValue MaxEVL = DAG.getElementCount(DL: sdl, VT: CountVT,
8301 EC: ElementCount::get(MinVal: VF, Scalable: IsScalable));
8302
8303 SDValue UMin = DAG.getNode(Opcode: ISD::UMIN, DL: sdl, VT: CountVT, N1: Count, N2: MaxEVL);
8304 // Clip to the result type if needed.
8305 SDValue Trunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: sdl, VT, Operand: UMin);
8306
8307 setValue(V: &I, NewN: Trunc);
8308 return;
8309 }
8310 case Intrinsic::vector_partial_reduce_add: {
8311 SDValue Acc = getValue(V: I.getOperand(i_nocapture: 0));
8312 SDValue Input = getValue(V: I.getOperand(i_nocapture: 1));
8313 setValue(V: &I,
8314 NewN: DAG.getNode(Opcode: ISD::PARTIAL_REDUCE_UMLA, DL: sdl, VT: Acc.getValueType(), N1: Acc,
8315 N2: Input, N3: DAG.getConstant(Val: 1, DL: sdl, VT: Input.getValueType())));
8316 return;
8317 }
8318 case Intrinsic::vector_partial_reduce_fadd: {
8319 SDValue Acc = getValue(V: I.getOperand(i_nocapture: 0));
8320 SDValue Input = getValue(V: I.getOperand(i_nocapture: 1));
8321 setValue(V: &I, NewN: DAG.getNode(
8322 Opcode: ISD::PARTIAL_REDUCE_FMLA, DL: sdl, VT: Acc.getValueType(), N1: Acc,
8323 N2: Input, N3: DAG.getConstantFP(Val: 1.0, DL: sdl, VT: Input.getValueType())));
8324 return;
8325 }
8326 case Intrinsic::experimental_cttz_elts: {
8327 SDValue Op = getValue(V: I.getOperand(i_nocapture: 0));
8328 EVT OpVT = Op.getValueType();
8329 EVT RetTy = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8330 bool ZeroIsPoison =
8331 !cast<ConstantSDNode>(Val: getValue(V: I.getOperand(i_nocapture: 1)))->isZero();
8332 if (OpVT.getVectorElementType() != MVT::i1) {
8333 // Compare the input vector elements to zero & use to count trailing
8334 // zeros.
8335 SDValue AllZero = DAG.getConstant(Val: 0, DL: sdl, VT: OpVT);
8336 EVT I1OpVT = OpVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: MVT::i1);
8337 Op = DAG.getSetCC(DL: sdl, VT: I1OpVT, LHS: Op, RHS: AllZero, Cond: ISD::SETNE);
8338 }
8339 setValue(V: &I, NewN: DAG.getNode(Opcode: ZeroIsPoison ? ISD::CTTZ_ELTS_ZERO_POISON
8340 : ISD::CTTZ_ELTS,
8341 DL: sdl, VT: RetTy, Operand: Op));
8342 return;
8343 }
8344 case Intrinsic::vector_insert: {
8345 SDValue Vec = getValue(V: I.getOperand(i_nocapture: 0));
8346 SDValue SubVec = getValue(V: I.getOperand(i_nocapture: 1));
8347 SDValue Index = getValue(V: I.getOperand(i_nocapture: 2));
8348
8349 // The intrinsic's index type is i64, but the SDNode requires an index type
8350 // suitable for the target. Convert the index as required.
8351 MVT VectorIdxTy = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
8352 if (Index.getValueType() != VectorIdxTy)
8353 Index = DAG.getVectorIdxConstant(Val: Index->getAsZExtVal(), DL: sdl);
8354
8355 EVT ResultVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8356 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::INSERT_SUBVECTOR, DL: sdl, VT: ResultVT, N1: Vec, N2: SubVec,
8357 N3: Index));
8358 return;
8359 }
8360 case Intrinsic::vector_extract: {
8361 SDValue Vec = getValue(V: I.getOperand(i_nocapture: 0));
8362 SDValue Index = getValue(V: I.getOperand(i_nocapture: 1));
8363 EVT ResultVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
8364
8365 // The intrinsic's index type is i64, but the SDNode requires an index type
8366 // suitable for the target. Convert the index as required.
8367 MVT VectorIdxTy = TLI.getVectorIdxTy(DL: DAG.getDataLayout());
8368 if (Index.getValueType() != VectorIdxTy)
8369 Index = DAG.getVectorIdxConstant(Val: Index->getAsZExtVal(), DL: sdl);
8370
8371 setValue(V: &I,
8372 NewN: DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: sdl, VT: ResultVT, N1: Vec, N2: Index));
8373 return;
8374 }
8375 case Intrinsic::experimental_vector_match: {
8376 SDValue Op1 = getValue(V: I.getOperand(i_nocapture: 0));
8377 SDValue Op2 = getValue(V: I.getOperand(i_nocapture: 1));
8378 SDValue Mask = getValue(V: I.getOperand(i_nocapture: 2));
8379 EVT Op1VT = Op1.getValueType();
8380 EVT Op2VT = Op2.getValueType();
8381 EVT ResVT = Mask.getValueType();
8382 unsigned SearchSize = Op2VT.getVectorNumElements();
8383
8384 // If the target has native support for this vector match operation, lower
8385 // the intrinsic untouched; otherwise, expand it below.
8386 if (!TLI.shouldExpandVectorMatch(VT: Op1VT, SearchSize)) {
8387 visitTargetIntrinsic(I, Intrinsic);
8388 return;
8389 }
8390
8391 SDValue Ret = DAG.getConstant(Val: 0, DL: sdl, VT: ResVT);
8392
8393 for (unsigned i = 0; i < SearchSize; ++i) {
8394 SDValue Op2Elem = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: sdl,
8395 VT: Op2VT.getVectorElementType(), N1: Op2,
8396 N2: DAG.getVectorIdxConstant(Val: i, DL: sdl));
8397 SDValue Splat = DAG.getNode(Opcode: ISD::SPLAT_VECTOR, DL: sdl, VT: Op1VT, Operand: Op2Elem);
8398 SDValue Cmp = DAG.getSetCC(DL: sdl, VT: ResVT, LHS: Op1, RHS: Splat, Cond: ISD::SETEQ);
8399 Ret = DAG.getNode(Opcode: ISD::OR, DL: sdl, VT: ResVT, N1: Ret, N2: Cmp);
8400 }
8401
8402 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::AND, DL: sdl, VT: ResVT, N1: Ret, N2: Mask));
8403 return;
8404 }
8405 case Intrinsic::vector_reverse:
8406 visitVectorReverse(I);
8407 return;
8408 case Intrinsic::vector_splice_left:
8409 case Intrinsic::vector_splice_right:
8410 visitVectorSplice(I);
8411 return;
8412 case Intrinsic::callbr_landingpad:
8413 visitCallBrLandingPad(I);
8414 return;
8415 case Intrinsic::vector_interleave2:
8416 visitVectorInterleave(I, Factor: 2);
8417 return;
8418 case Intrinsic::vector_interleave3:
8419 visitVectorInterleave(I, Factor: 3);
8420 return;
8421 case Intrinsic::vector_interleave4:
8422 visitVectorInterleave(I, Factor: 4);
8423 return;
8424 case Intrinsic::vector_interleave5:
8425 visitVectorInterleave(I, Factor: 5);
8426 return;
8427 case Intrinsic::vector_interleave6:
8428 visitVectorInterleave(I, Factor: 6);
8429 return;
8430 case Intrinsic::vector_interleave7:
8431 visitVectorInterleave(I, Factor: 7);
8432 return;
8433 case Intrinsic::vector_interleave8:
8434 visitVectorInterleave(I, Factor: 8);
8435 return;
8436 case Intrinsic::vector_deinterleave2:
8437 visitVectorDeinterleave(I, Factor: 2);
8438 return;
8439 case Intrinsic::vector_deinterleave3:
8440 visitVectorDeinterleave(I, Factor: 3);
8441 return;
8442 case Intrinsic::vector_deinterleave4:
8443 visitVectorDeinterleave(I, Factor: 4);
8444 return;
8445 case Intrinsic::vector_deinterleave5:
8446 visitVectorDeinterleave(I, Factor: 5);
8447 return;
8448 case Intrinsic::vector_deinterleave6:
8449 visitVectorDeinterleave(I, Factor: 6);
8450 return;
8451 case Intrinsic::vector_deinterleave7:
8452 visitVectorDeinterleave(I, Factor: 7);
8453 return;
8454 case Intrinsic::vector_deinterleave8:
8455 visitVectorDeinterleave(I, Factor: 8);
8456 return;
8457 case Intrinsic::experimental_vector_compress:
8458 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::VECTOR_COMPRESS, DL: sdl,
8459 VT: getValue(V: I.getArgOperand(i: 0)).getValueType(),
8460 N1: getValue(V: I.getArgOperand(i: 0)),
8461 N2: getValue(V: I.getArgOperand(i: 1)),
8462 N3: getValue(V: I.getArgOperand(i: 2)), Flags));
8463 return;
8464 case Intrinsic::experimental_convergence_anchor:
8465 case Intrinsic::experimental_convergence_entry:
8466 case Intrinsic::experimental_convergence_loop:
8467 visitConvergenceControl(I, Intrinsic);
8468 return;
8469 case Intrinsic::experimental_vector_histogram_add: {
8470 visitVectorHistogram(I, IntrinsicID: Intrinsic);
8471 return;
8472 }
8473 case Intrinsic::experimental_vector_extract_last_active: {
8474 visitVectorExtractLastActive(I, Intrinsic);
8475 return;
8476 }
8477 case Intrinsic::loop_dependence_war_mask:
8478 setValue(V: &I,
8479 NewN: DAG.getNode(Opcode: ISD::LOOP_DEPENDENCE_WAR_MASK, DL: sdl,
8480 VT: EVT::getEVT(Ty: I.getType()), N1: getValue(V: I.getOperand(i_nocapture: 0)),
8481 N2: getValue(V: I.getOperand(i_nocapture: 1)), N3: getValue(V: I.getOperand(i_nocapture: 2)),
8482 N4: DAG.getConstant(Val: 0, DL: sdl, VT: MVT::i64)));
8483 return;
8484 case Intrinsic::loop_dependence_raw_mask:
8485 setValue(V: &I,
8486 NewN: DAG.getNode(Opcode: ISD::LOOP_DEPENDENCE_RAW_MASK, DL: sdl,
8487 VT: EVT::getEVT(Ty: I.getType()), N1: getValue(V: I.getOperand(i_nocapture: 0)),
8488 N2: getValue(V: I.getOperand(i_nocapture: 1)), N3: getValue(V: I.getOperand(i_nocapture: 2)),
8489 N4: DAG.getConstant(Val: 0, DL: sdl, VT: MVT::i64)));
8490 return;
8491 }
8492}
8493
8494void SelectionDAGBuilder::pushFPOpOutChain(SDValue Result,
8495 fp::ExceptionBehavior EB) {
8496 assert(Result.getNode()->getNumValues() == 2);
8497 SDValue OutChain = Result.getValue(R: 1);
8498 assert(OutChain.getValueType() == MVT::Other);
8499
8500 // Instead of updating the root immediately, push the produced chain to the
8501 // appropriate list, deferring the update until the root is requested. In this
8502 // case, the nodes from the lists are chained using TokenFactor, indicating
8503 // that the operations are independent.
8504 //
8505 // In particular, the root is updated before any call that might access the
8506 // floating-point environment, except for constrained intrinsics.
8507 switch (EB) {
8508 case fp::ExceptionBehavior::ebMayTrap:
8509 case fp::ExceptionBehavior::ebIgnore:
8510 PendingConstrainedFP.push_back(Elt: OutChain);
8511 break;
8512 case fp::ExceptionBehavior::ebStrict:
8513 PendingConstrainedFPStrict.push_back(Elt: OutChain);
8514 break;
8515 }
8516}
8517
8518void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
8519 const ConstrainedFPIntrinsic &FPI) {
8520 SDLoc sdl = getCurSDLoc();
8521
8522 // We do not need to serialize constrained FP intrinsics against
8523 // each other or against (nonvolatile) loads, so they can be
8524 // chained like loads.
8525 fp::ExceptionBehavior EB = *FPI.getExceptionBehavior();
8526 SDValue Chain = getFPOperationRoot(EB);
8527 SmallVector<SDValue, 4> Opers;
8528 Opers.push_back(Elt: Chain);
8529 for (unsigned I = 0, E = FPI.getNonMetadataArgCount(); I != E; ++I)
8530 Opers.push_back(Elt: getValue(V: FPI.getArgOperand(i: I)));
8531
8532 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8533 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: FPI.getType());
8534 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::Other);
8535
8536 SDNodeFlags Flags;
8537 if (EB == fp::ExceptionBehavior::ebIgnore)
8538 Flags.setNoFPExcept(true);
8539
8540 if (auto *FPOp = dyn_cast<FPMathOperator>(Val: &FPI))
8541 Flags.copyFMF(FPMO: *FPOp);
8542
8543 unsigned Opcode;
8544 switch (FPI.getIntrinsicID()) {
8545 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
8546#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
8547 case Intrinsic::INTRINSIC: \
8548 Opcode = ISD::STRICT_##DAGN; \
8549 break;
8550#include "llvm/IR/ConstrainedOps.def"
8551 case Intrinsic::experimental_constrained_fmuladd: {
8552 Opcode = ISD::STRICT_FMA;
8553 // Break fmuladd into fmul and fadd.
8554 if (TM.Options.AllowFPOpFusion == FPOpFusion::Strict ||
8555 !TLI.isFMAFasterThanFMulAndFAdd(MF: DAG.getMachineFunction(), VT)) {
8556 Opers.pop_back();
8557 SDValue Mul = DAG.getNode(Opcode: ISD::STRICT_FMUL, DL: sdl, VTList: VTs, Ops: Opers, Flags);
8558 pushFPOpOutChain(Result: Mul, EB);
8559 Opcode = ISD::STRICT_FADD;
8560 Opers.clear();
8561 Opers.push_back(Elt: Mul.getValue(R: 1));
8562 Opers.push_back(Elt: Mul.getValue(R: 0));
8563 Opers.push_back(Elt: getValue(V: FPI.getArgOperand(i: 2)));
8564 }
8565 break;
8566 }
8567 }
8568
8569 // A few strict DAG nodes carry additional operands that are not
8570 // set up by the default code above.
8571 switch (Opcode) {
8572 default: break;
8573 case ISD::STRICT_FP_ROUND:
8574 Opers.push_back(
8575 Elt: DAG.getTargetConstant(Val: 0, DL: sdl, VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
8576 break;
8577 case ISD::STRICT_FSETCC:
8578 case ISD::STRICT_FSETCCS: {
8579 auto *FPCmp = dyn_cast<ConstrainedFPCmpIntrinsic>(Val: &FPI);
8580 ISD::CondCode Condition = getFCmpCondCode(Pred: FPCmp->getPredicate());
8581 if (DAG.isKnownNeverNaN(Op: Opers[1]) && DAG.isKnownNeverNaN(Op: Opers[2]))
8582 Condition = getFCmpCodeWithoutNaN(CC: Condition);
8583 Opers.push_back(Elt: DAG.getCondCode(Cond: Condition));
8584 break;
8585 }
8586 }
8587
8588 SDValue Result = DAG.getNode(Opcode, DL: sdl, VTList: VTs, Ops: Opers, Flags);
8589 pushFPOpOutChain(Result, EB);
8590
8591 SDValue FPResult = Result.getValue(R: 0);
8592 setValue(V: &FPI, NewN: FPResult);
8593}
8594
8595static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) {
8596 std::optional<unsigned> ResOPC;
8597 switch (VPIntrin.getIntrinsicID()) {
8598 case Intrinsic::vp_ctlz: {
8599 bool IsZeroUndef = cast<ConstantInt>(Val: VPIntrin.getArgOperand(i: 1))->isOne();
8600 ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ;
8601 break;
8602 }
8603 case Intrinsic::vp_cttz: {
8604 bool IsZeroUndef = cast<ConstantInt>(Val: VPIntrin.getArgOperand(i: 1))->isOne();
8605 ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ;
8606 break;
8607 }
8608 case Intrinsic::vp_cttz_elts: {
8609 bool IsZeroPoison = cast<ConstantInt>(Val: VPIntrin.getArgOperand(i: 1))->isOne();
8610 ResOPC = IsZeroPoison ? ISD::VP_CTTZ_ELTS_ZERO_UNDEF : ISD::VP_CTTZ_ELTS;
8611 break;
8612 }
8613#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
8614 case Intrinsic::VPID: \
8615 ResOPC = ISD::VPSD; \
8616 break;
8617#include "llvm/IR/VPIntrinsics.def"
8618 }
8619
8620 if (!ResOPC)
8621 llvm_unreachable(
8622 "Inconsistency: no SDNode available for this VPIntrinsic!");
8623
8624 if (*ResOPC == ISD::VP_REDUCE_SEQ_FADD ||
8625 *ResOPC == ISD::VP_REDUCE_SEQ_FMUL) {
8626 if (VPIntrin.getFastMathFlags().allowReassoc())
8627 return *ResOPC == ISD::VP_REDUCE_SEQ_FADD ? ISD::VP_REDUCE_FADD
8628 : ISD::VP_REDUCE_FMUL;
8629 }
8630
8631 return *ResOPC;
8632}
8633
8634void SelectionDAGBuilder::visitVPLoad(
8635 const VPIntrinsic &VPIntrin, EVT VT,
8636 const SmallVectorImpl<SDValue> &OpValues) {
8637 SDLoc DL = getCurSDLoc();
8638 Value *PtrOperand = VPIntrin.getArgOperand(i: 0);
8639 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8640 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8641 const MDNode *Ranges = getRangeMetadata(I: VPIntrin);
8642 SDValue LD;
8643 // Do not serialize variable-length loads of constant memory with
8644 // anything.
8645 if (!Alignment)
8646 Alignment = DAG.getEVTAlign(MemoryVT: VT);
8647 MemoryLocation ML = MemoryLocation::getAfter(Ptr: PtrOperand, AATags: AAInfo);
8648 bool AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(Loc: ML);
8649 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
8650 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8651 MachineMemOperand::Flags MMOFlags =
8652 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8653 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8654 PtrInfo: MachinePointerInfo(PtrOperand), F: MMOFlags,
8655 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: *Alignment, AAInfo, Ranges);
8656 LD = DAG.getLoadVP(VT, dl: DL, Chain: InChain, Ptr: OpValues[0], Mask: OpValues[1], EVL: OpValues[2],
8657 MMO, IsExpanding: false /*IsExpanding */);
8658 if (AddToChain)
8659 PendingLoads.push_back(Elt: LD.getValue(R: 1));
8660 setValue(V: &VPIntrin, NewN: LD);
8661}
8662
8663void SelectionDAGBuilder::visitVPLoadFF(
8664 const VPIntrinsic &VPIntrin, EVT VT, EVT EVLVT,
8665 const SmallVectorImpl<SDValue> &OpValues) {
8666 assert(OpValues.size() == 3 && "Unexpected number of operands");
8667 SDLoc DL = getCurSDLoc();
8668 Value *PtrOperand = VPIntrin.getArgOperand(i: 0);
8669 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8670 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8671 const MDNode *Ranges = VPIntrin.getMetadata(KindID: LLVMContext::MD_range);
8672 SDValue LD;
8673 // Do not serialize variable-length loads of constant memory with
8674 // anything.
8675 if (!Alignment)
8676 Alignment = DAG.getEVTAlign(MemoryVT: VT);
8677 MemoryLocation ML = MemoryLocation::getAfter(Ptr: PtrOperand, AATags: AAInfo);
8678 bool AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(Loc: ML);
8679 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
8680 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8681 PtrInfo: MachinePointerInfo(PtrOperand), F: MachineMemOperand::MOLoad,
8682 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: *Alignment, AAInfo, Ranges);
8683 LD = DAG.getLoadFFVP(VT, DL, Chain: InChain, Ptr: OpValues[0], Mask: OpValues[1], EVL: OpValues[2],
8684 MMO);
8685 SDValue Trunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: EVLVT, Operand: LD.getValue(R: 1));
8686 if (AddToChain)
8687 PendingLoads.push_back(Elt: LD.getValue(R: 2));
8688 setValue(V: &VPIntrin, NewN: DAG.getMergeValues(Ops: {LD.getValue(R: 0), Trunc}, dl: DL));
8689}
8690
8691void SelectionDAGBuilder::visitVPGather(
8692 const VPIntrinsic &VPIntrin, EVT VT,
8693 const SmallVectorImpl<SDValue> &OpValues) {
8694 SDLoc DL = getCurSDLoc();
8695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8696 Value *PtrOperand = VPIntrin.getArgOperand(i: 0);
8697 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8698 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8699 const MDNode *Ranges = getRangeMetadata(I: VPIntrin);
8700 SDValue LD;
8701 if (!Alignment)
8702 Alignment = DAG.getEVTAlign(MemoryVT: VT.getScalarType());
8703 unsigned AS =
8704 PtrOperand->getType()->getScalarType()->getPointerAddressSpace();
8705 MachineMemOperand::Flags MMOFlags =
8706 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8707 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8708 PtrInfo: MachinePointerInfo(AS), F: MMOFlags, Size: LocationSize::beforeOrAfterPointer(),
8709 BaseAlignment: *Alignment, AAInfo, Ranges);
8710 SDValue Base, Index, Scale;
8711 bool UniformBase =
8712 getUniformBase(Ptr: PtrOperand, Base, Index, Scale, SDB: this, CurBB: VPIntrin.getParent(),
8713 ElemSize: VT.getScalarStoreSize());
8714 if (!UniformBase) {
8715 Base = DAG.getConstant(Val: 0, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
8716 Index = getValue(V: PtrOperand);
8717 Scale = DAG.getTargetConstant(Val: 1, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
8718 }
8719 EVT IdxVT = Index.getValueType();
8720 EVT EltTy = IdxVT.getVectorElementType();
8721 if (TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
8722 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
8723 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: NewIdxVT, Operand: Index);
8724 }
8725 LD = DAG.getGatherVP(
8726 VTs: DAG.getVTList(VT1: VT, VT2: MVT::Other), VT, dl: DL,
8727 Ops: {DAG.getRoot(), Base, Index, Scale, OpValues[1], OpValues[2]}, MMO,
8728 IndexType: ISD::SIGNED_SCALED);
8729 PendingLoads.push_back(Elt: LD.getValue(R: 1));
8730 setValue(V: &VPIntrin, NewN: LD);
8731}
8732
8733void SelectionDAGBuilder::visitVPStore(
8734 const VPIntrinsic &VPIntrin, const SmallVectorImpl<SDValue> &OpValues) {
8735 SDLoc DL = getCurSDLoc();
8736 Value *PtrOperand = VPIntrin.getArgOperand(i: 1);
8737 EVT VT = OpValues[0].getValueType();
8738 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8739 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8740 SDValue ST;
8741 if (!Alignment)
8742 Alignment = DAG.getEVTAlign(MemoryVT: VT);
8743 SDValue Ptr = OpValues[1];
8744 SDValue Offset = DAG.getUNDEF(VT: Ptr.getValueType());
8745 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8746 MachineMemOperand::Flags MMOFlags =
8747 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8748 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8749 PtrInfo: MachinePointerInfo(PtrOperand), F: MMOFlags,
8750 Size: LocationSize::beforeOrAfterPointer(), BaseAlignment: *Alignment, AAInfo);
8751 ST = DAG.getStoreVP(Chain: getMemoryRoot(), dl: DL, Val: OpValues[0], Ptr, Offset,
8752 Mask: OpValues[2], EVL: OpValues[3], MemVT: VT, MMO, AM: ISD::UNINDEXED,
8753 /* IsTruncating */ false, /*IsCompressing*/ false);
8754 DAG.setRoot(ST);
8755 setValue(V: &VPIntrin, NewN: ST);
8756}
8757
8758void SelectionDAGBuilder::visitVPScatter(
8759 const VPIntrinsic &VPIntrin, const SmallVectorImpl<SDValue> &OpValues) {
8760 SDLoc DL = getCurSDLoc();
8761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8762 Value *PtrOperand = VPIntrin.getArgOperand(i: 1);
8763 EVT VT = OpValues[0].getValueType();
8764 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8765 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8766 SDValue ST;
8767 if (!Alignment)
8768 Alignment = DAG.getEVTAlign(MemoryVT: VT.getScalarType());
8769 unsigned AS =
8770 PtrOperand->getType()->getScalarType()->getPointerAddressSpace();
8771 MachineMemOperand::Flags MMOFlags =
8772 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8773 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8774 PtrInfo: MachinePointerInfo(AS), F: MMOFlags, Size: LocationSize::beforeOrAfterPointer(),
8775 BaseAlignment: *Alignment, AAInfo);
8776 SDValue Base, Index, Scale;
8777 bool UniformBase =
8778 getUniformBase(Ptr: PtrOperand, Base, Index, Scale, SDB: this, CurBB: VPIntrin.getParent(),
8779 ElemSize: VT.getScalarStoreSize());
8780 if (!UniformBase) {
8781 Base = DAG.getConstant(Val: 0, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
8782 Index = getValue(V: PtrOperand);
8783 Scale = DAG.getTargetConstant(Val: 1, DL, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
8784 }
8785 EVT IdxVT = Index.getValueType();
8786 EVT EltTy = IdxVT.getVectorElementType();
8787 if (TLI.shouldExtendGSIndex(VT: IdxVT, EltTy)) {
8788 EVT NewIdxVT = IdxVT.changeVectorElementType(Context&: *DAG.getContext(), EltVT: EltTy);
8789 Index = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: NewIdxVT, Operand: Index);
8790 }
8791 ST = DAG.getScatterVP(VTs: DAG.getVTList(VT: MVT::Other), VT, dl: DL,
8792 Ops: {getMemoryRoot(), OpValues[0], Base, Index, Scale,
8793 OpValues[2], OpValues[3]},
8794 MMO, IndexType: ISD::SIGNED_SCALED);
8795 DAG.setRoot(ST);
8796 setValue(V: &VPIntrin, NewN: ST);
8797}
8798
8799void SelectionDAGBuilder::visitVPStridedLoad(
8800 const VPIntrinsic &VPIntrin, EVT VT,
8801 const SmallVectorImpl<SDValue> &OpValues) {
8802 SDLoc DL = getCurSDLoc();
8803 Value *PtrOperand = VPIntrin.getArgOperand(i: 0);
8804 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8805 if (!Alignment)
8806 Alignment = DAG.getEVTAlign(MemoryVT: VT.getScalarType());
8807 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8808 const MDNode *Ranges = getRangeMetadata(I: VPIntrin);
8809 MemoryLocation ML = MemoryLocation::getAfter(Ptr: PtrOperand, AATags: AAInfo);
8810 bool AddToChain = !BatchAA || !BatchAA->pointsToConstantMemory(Loc: ML);
8811 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
8812 unsigned AS = PtrOperand->getType()->getPointerAddressSpace();
8813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8814 MachineMemOperand::Flags MMOFlags =
8815 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8816 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8817 PtrInfo: MachinePointerInfo(AS), F: MMOFlags, Size: LocationSize::beforeOrAfterPointer(),
8818 BaseAlignment: *Alignment, AAInfo, Ranges);
8819
8820 SDValue LD = DAG.getStridedLoadVP(VT, DL, Chain: InChain, Ptr: OpValues[0], Stride: OpValues[1],
8821 Mask: OpValues[2], EVL: OpValues[3], MMO,
8822 IsExpanding: false /*IsExpanding*/);
8823
8824 if (AddToChain)
8825 PendingLoads.push_back(Elt: LD.getValue(R: 1));
8826 setValue(V: &VPIntrin, NewN: LD);
8827}
8828
8829void SelectionDAGBuilder::visitVPStridedStore(
8830 const VPIntrinsic &VPIntrin, const SmallVectorImpl<SDValue> &OpValues) {
8831 SDLoc DL = getCurSDLoc();
8832 Value *PtrOperand = VPIntrin.getArgOperand(i: 1);
8833 EVT VT = OpValues[0].getValueType();
8834 MaybeAlign Alignment = VPIntrin.getPointerAlignment();
8835 if (!Alignment)
8836 Alignment = DAG.getEVTAlign(MemoryVT: VT.getScalarType());
8837 AAMDNodes AAInfo = VPIntrin.getAAMetadata();
8838 unsigned AS = PtrOperand->getType()->getPointerAddressSpace();
8839 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8840 MachineMemOperand::Flags MMOFlags =
8841 TLI.getVPIntrinsicMemOperandFlags(VPIntrin);
8842 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
8843 PtrInfo: MachinePointerInfo(AS), F: MMOFlags, Size: LocationSize::beforeOrAfterPointer(),
8844 BaseAlignment: *Alignment, AAInfo);
8845
8846 SDValue ST = DAG.getStridedStoreVP(
8847 Chain: getMemoryRoot(), DL, Val: OpValues[0], Ptr: OpValues[1],
8848 Offset: DAG.getUNDEF(VT: OpValues[1].getValueType()), Stride: OpValues[2], Mask: OpValues[3],
8849 EVL: OpValues[4], MemVT: VT, MMO, AM: ISD::UNINDEXED, /*IsTruncating*/ false,
8850 /*IsCompressing*/ false);
8851
8852 DAG.setRoot(ST);
8853 setValue(V: &VPIntrin, NewN: ST);
8854}
8855
8856void SelectionDAGBuilder::visitVPCmp(const VPCmpIntrinsic &VPIntrin) {
8857 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8858 SDLoc DL = getCurSDLoc();
8859
8860 ISD::CondCode Condition;
8861 CmpInst::Predicate CondCode = VPIntrin.getPredicate();
8862
8863 Value *Op1 = VPIntrin.getOperand(i_nocapture: 0);
8864 Value *Op2 = VPIntrin.getOperand(i_nocapture: 1);
8865 // #2 is the condition code
8866 SDValue MaskOp = getValue(V: VPIntrin.getOperand(i_nocapture: 3));
8867 SDValue EVL = getValue(V: VPIntrin.getOperand(i_nocapture: 4));
8868 MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy();
8869 assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) &&
8870 "Unexpected target EVL type");
8871 EVL = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: EVLParamVT, Operand: EVL);
8872
8873 if (VPIntrin.getOperand(i_nocapture: 0)->getType()->isFPOrFPVectorTy()) {
8874 Condition = getFCmpCondCode(Pred: CondCode);
8875 SimplifyQuery SQ(DAG.getDataLayout(), &VPIntrin);
8876 if (isKnownNeverNaN(V: Op2, SQ) && isKnownNeverNaN(V: Op1, SQ))
8877 Condition = getFCmpCodeWithoutNaN(CC: Condition);
8878 } else {
8879 Condition = getICmpCondCode(Pred: CondCode);
8880 }
8881
8882 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
8883 Ty: VPIntrin.getType());
8884 setValue(V: &VPIntrin, NewN: DAG.getSetCCVP(DL, VT: DestVT, LHS: getValue(V: Op1), RHS: getValue(V: Op2),
8885 Cond: Condition, Mask: MaskOp, EVL));
8886}
8887
8888void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
8889 const VPIntrinsic &VPIntrin) {
8890 SDLoc DL = getCurSDLoc();
8891 unsigned Opcode = getISDForVPIntrinsic(VPIntrin);
8892
8893 auto IID = VPIntrin.getIntrinsicID();
8894
8895 if (const auto *CmpI = dyn_cast<VPCmpIntrinsic>(Val: &VPIntrin))
8896 return visitVPCmp(VPIntrin: *CmpI);
8897
8898 SmallVector<EVT, 4> ValueVTs;
8899 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8900 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: VPIntrin.getType(), ValueVTs);
8901 SDVTList VTs = DAG.getVTList(VTs: ValueVTs);
8902
8903 auto EVLParamPos = VPIntrinsic::getVectorLengthParamPos(IntrinsicID: IID);
8904
8905 MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy();
8906 assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) &&
8907 "Unexpected target EVL type");
8908
8909 // Request operands.
8910 SmallVector<SDValue, 7> OpValues;
8911 for (unsigned I = 0; I < VPIntrin.arg_size(); ++I) {
8912 auto Op = getValue(V: VPIntrin.getArgOperand(i: I));
8913 if (I == EVLParamPos)
8914 Op = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: EVLParamVT, Operand: Op);
8915 OpValues.push_back(Elt: Op);
8916 }
8917
8918 switch (Opcode) {
8919 default: {
8920 SDNodeFlags SDFlags;
8921 if (auto *FPMO = dyn_cast<FPMathOperator>(Val: &VPIntrin))
8922 SDFlags.copyFMF(FPMO: *FPMO);
8923 SDValue Result = DAG.getNode(Opcode, DL, VTList: VTs, Ops: OpValues, Flags: SDFlags);
8924 setValue(V: &VPIntrin, NewN: Result);
8925 break;
8926 }
8927 case ISD::VP_LOAD:
8928 visitVPLoad(VPIntrin, VT: ValueVTs[0], OpValues);
8929 break;
8930 case ISD::VP_LOAD_FF:
8931 visitVPLoadFF(VPIntrin, VT: ValueVTs[0], EVLVT: ValueVTs[1], OpValues);
8932 break;
8933 case ISD::VP_GATHER:
8934 visitVPGather(VPIntrin, VT: ValueVTs[0], OpValues);
8935 break;
8936 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
8937 visitVPStridedLoad(VPIntrin, VT: ValueVTs[0], OpValues);
8938 break;
8939 case ISD::VP_STORE:
8940 visitVPStore(VPIntrin, OpValues);
8941 break;
8942 case ISD::VP_SCATTER:
8943 visitVPScatter(VPIntrin, OpValues);
8944 break;
8945 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
8946 visitVPStridedStore(VPIntrin, OpValues);
8947 break;
8948 case ISD::VP_FMULADD: {
8949 assert(OpValues.size() == 5 && "Unexpected number of operands");
8950 SDNodeFlags SDFlags;
8951 if (auto *FPMO = dyn_cast<FPMathOperator>(Val: &VPIntrin))
8952 SDFlags.copyFMF(FPMO: *FPMO);
8953 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
8954 TLI.isFMAFasterThanFMulAndFAdd(MF: DAG.getMachineFunction(), ValueVTs[0])) {
8955 setValue(V: &VPIntrin, NewN: DAG.getNode(Opcode: ISD::VP_FMA, DL, VTList: VTs, Ops: OpValues, Flags: SDFlags));
8956 } else {
8957 SDValue Mul = DAG.getNode(
8958 Opcode: ISD::VP_FMUL, DL, VTList: VTs,
8959 Ops: {OpValues[0], OpValues[1], OpValues[3], OpValues[4]}, Flags: SDFlags);
8960 SDValue Add =
8961 DAG.getNode(Opcode: ISD::VP_FADD, DL, VTList: VTs,
8962 Ops: {Mul, OpValues[2], OpValues[3], OpValues[4]}, Flags: SDFlags);
8963 setValue(V: &VPIntrin, NewN: Add);
8964 }
8965 break;
8966 }
8967 case ISD::VP_IS_FPCLASS: {
8968 const DataLayout DLayout = DAG.getDataLayout();
8969 EVT DestVT = TLI.getValueType(DL: DLayout, Ty: VPIntrin.getType());
8970 auto Constant = OpValues[1]->getAsZExtVal();
8971 SDValue Check = DAG.getTargetConstant(Val: Constant, DL, VT: MVT::i32);
8972 SDValue V = DAG.getNode(Opcode: ISD::VP_IS_FPCLASS, DL, VT: DestVT,
8973 Ops: {OpValues[0], Check, OpValues[2], OpValues[3]});
8974 setValue(V: &VPIntrin, NewN: V);
8975 return;
8976 }
8977 case ISD::VP_INTTOPTR: {
8978 SDValue N = OpValues[0];
8979 EVT DestVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: VPIntrin.getType());
8980 EVT PtrMemVT = TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: VPIntrin.getType());
8981 N = DAG.getVPPtrExtOrTrunc(DL: getCurSDLoc(), VT: DestVT, Op: N, Mask: OpValues[1],
8982 EVL: OpValues[2]);
8983 N = DAG.getVPZExtOrTrunc(DL: getCurSDLoc(), VT: PtrMemVT, Op: N, Mask: OpValues[1],
8984 EVL: OpValues[2]);
8985 setValue(V: &VPIntrin, NewN: N);
8986 break;
8987 }
8988 case ISD::VP_PTRTOINT: {
8989 SDValue N = OpValues[0];
8990 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
8991 Ty: VPIntrin.getType());
8992 EVT PtrMemVT = TLI.getMemValueType(DL: DAG.getDataLayout(),
8993 Ty: VPIntrin.getOperand(i_nocapture: 0)->getType());
8994 N = DAG.getVPPtrExtOrTrunc(DL: getCurSDLoc(), VT: PtrMemVT, Op: N, Mask: OpValues[1],
8995 EVL: OpValues[2]);
8996 N = DAG.getVPZExtOrTrunc(DL: getCurSDLoc(), VT: DestVT, Op: N, Mask: OpValues[1],
8997 EVL: OpValues[2]);
8998 setValue(V: &VPIntrin, NewN: N);
8999 break;
9000 }
9001 case ISD::VP_ABS:
9002 case ISD::VP_CTLZ:
9003 case ISD::VP_CTLZ_ZERO_UNDEF:
9004 case ISD::VP_CTTZ:
9005 case ISD::VP_CTTZ_ZERO_UNDEF:
9006 case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
9007 case ISD::VP_CTTZ_ELTS: {
9008 SDValue Result =
9009 DAG.getNode(Opcode, DL, VTList: VTs, Ops: {OpValues[0], OpValues[2], OpValues[3]});
9010 setValue(V: &VPIntrin, NewN: Result);
9011 break;
9012 }
9013 }
9014}
9015
9016SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain,
9017 const BasicBlock *EHPadBB,
9018 MCSymbol *&BeginLabel) {
9019 MachineFunction &MF = DAG.getMachineFunction();
9020
9021 // Insert a label before the invoke call to mark the try range. This can be
9022 // used to detect deletion of the invoke via the MachineModuleInfo.
9023 BeginLabel = MF.getContext().createTempSymbol();
9024
9025 // For SjLj, keep track of which landing pads go with which invokes
9026 // so as to maintain the ordering of pads in the LSDA.
9027 unsigned CallSiteIndex = FuncInfo.getCurrentCallSite();
9028 if (CallSiteIndex) {
9029 MF.setCallSiteBeginLabel(BeginLabel, Site: CallSiteIndex);
9030 LPadToCallSiteMap[FuncInfo.getMBB(BB: EHPadBB)].push_back(Elt: CallSiteIndex);
9031
9032 // Now that the call site is handled, stop tracking it.
9033 FuncInfo.setCurrentCallSite(0);
9034 }
9035
9036 return DAG.getEHLabel(dl: getCurSDLoc(), Root: Chain, Label: BeginLabel);
9037}
9038
9039SDValue SelectionDAGBuilder::lowerEndEH(SDValue Chain, const InvokeInst *II,
9040 const BasicBlock *EHPadBB,
9041 MCSymbol *BeginLabel) {
9042 assert(BeginLabel && "BeginLabel should've been set");
9043
9044 MachineFunction &MF = DAG.getMachineFunction();
9045
9046 // Insert a label at the end of the invoke call to mark the try range. This
9047 // can be used to detect deletion of the invoke via the MachineModuleInfo.
9048 MCSymbol *EndLabel = MF.getContext().createTempSymbol();
9049 Chain = DAG.getEHLabel(dl: getCurSDLoc(), Root: Chain, Label: EndLabel);
9050
9051 // Inform MachineModuleInfo of range.
9052 auto Pers = classifyEHPersonality(Pers: FuncInfo.Fn->getPersonalityFn());
9053 // There is a platform (e.g. wasm) that uses funclet style IR but does not
9054 // actually use outlined funclets and their LSDA info style.
9055 if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) {
9056 assert(II && "II should've been set");
9057 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
9058 EHInfo->addIPToStateRange(II, InvokeBegin: BeginLabel, InvokeEnd: EndLabel);
9059 } else if (!isScopedEHPersonality(Pers)) {
9060 assert(EHPadBB);
9061 MF.addInvoke(LandingPad: FuncInfo.getMBB(BB: EHPadBB), BeginLabel, EndLabel);
9062 }
9063
9064 return Chain;
9065}
9066
9067std::pair<SDValue, SDValue>
9068SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
9069 const BasicBlock *EHPadBB) {
9070 MCSymbol *BeginLabel = nullptr;
9071
9072 if (EHPadBB) {
9073 // Both PendingLoads and PendingExports must be flushed here;
9074 // this call might not return.
9075 (void)getRoot();
9076 DAG.setRoot(lowerStartEH(Chain: getControlRoot(), EHPadBB, BeginLabel));
9077 CLI.setChain(getRoot());
9078 }
9079
9080 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9081 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
9082
9083 assert((CLI.IsTailCall || Result.second.getNode()) &&
9084 "Non-null chain expected with non-tail call!");
9085 assert((Result.second.getNode() || !Result.first.getNode()) &&
9086 "Null value expected with tail call!");
9087
9088 if (!Result.second.getNode()) {
9089 // As a special case, a null chain means that a tail call has been emitted
9090 // and the DAG root is already updated.
9091 HasTailCall = true;
9092
9093 // Since there's no actual continuation from this block, nothing can be
9094 // relying on us setting vregs for them.
9095 PendingExports.clear();
9096 } else {
9097 DAG.setRoot(Result.second);
9098 }
9099
9100 if (EHPadBB) {
9101 DAG.setRoot(lowerEndEH(Chain: getRoot(), II: cast_or_null<InvokeInst>(Val: CLI.CB), EHPadBB,
9102 BeginLabel));
9103 Result.second = getRoot();
9104 }
9105
9106 return Result;
9107}
9108
9109bool SelectionDAGBuilder::canTailCall(const CallBase &CB) const {
9110 bool isMustTailCall = CB.isMustTailCall();
9111
9112 // Avoid emitting tail calls in functions with the disable-tail-calls
9113 // attribute.
9114 const Function *Caller = CB.getParent()->getParent();
9115 if (!isMustTailCall &&
9116 Caller->getFnAttribute(Kind: "disable-tail-calls").getValueAsBool())
9117 return false;
9118
9119 // We can't tail call inside a function with a swifterror argument. Lowering
9120 // does not support this yet. It would have to move into the swifterror
9121 // register before the call.
9122 if (DAG.getTargetLoweringInfo().supportSwiftError() &&
9123 Caller->getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError))
9124 return false;
9125
9126 // Check if target-independent constraints permit a tail call here.
9127 // Target-dependent constraints are checked within TLI->LowerCallTo.
9128 return isInTailCallPosition(Call: CB, TM: DAG.getTarget());
9129}
9130
9131void SelectionDAGBuilder::LowerCallTo(const CallBase &CB, SDValue Callee,
9132 bool isTailCall, bool isMustTailCall,
9133 const BasicBlock *EHPadBB,
9134 const TargetLowering::PtrAuthInfo *PAI) {
9135 auto &DL = DAG.getDataLayout();
9136 FunctionType *FTy = CB.getFunctionType();
9137 Type *RetTy = CB.getType();
9138
9139 TargetLowering::ArgListTy Args;
9140 Args.reserve(n: CB.arg_size());
9141
9142 const Value *SwiftErrorVal = nullptr;
9143 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9144
9145 if (isTailCall)
9146 isTailCall = canTailCall(CB);
9147
9148 for (auto I = CB.arg_begin(), E = CB.arg_end(); I != E; ++I) {
9149 const Value *V = *I;
9150
9151 // Skip empty types
9152 if (V->getType()->isEmptyTy())
9153 continue;
9154
9155 SDValue ArgNode = getValue(V);
9156 TargetLowering::ArgListEntry Entry(ArgNode, V->getType());
9157 Entry.setAttributes(Call: &CB, ArgIdx: I - CB.arg_begin());
9158
9159 // Use swifterror virtual register as input to the call.
9160 if (Entry.IsSwiftError && TLI.supportSwiftError()) {
9161 SwiftErrorVal = V;
9162 // We find the virtual register for the actual swifterror argument.
9163 // Instead of using the Value, we use the virtual register instead.
9164 Entry.Node =
9165 DAG.getRegister(Reg: SwiftError.getOrCreateVRegUseAt(&CB, FuncInfo.MBB, V),
9166 VT: EVT(TLI.getPointerTy(DL)));
9167 }
9168
9169 Args.push_back(x: Entry);
9170
9171 // If we have an explicit sret argument that is an Instruction, (i.e., it
9172 // might point to function-local memory), we can't meaningfully tail-call.
9173 if (Entry.IsSRet && isa<Instruction>(Val: V))
9174 isTailCall = false;
9175 }
9176
9177 // If call site has a cfguardtarget operand bundle, create and add an
9178 // additional ArgListEntry.
9179 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_cfguardtarget)) {
9180 Value *V = Bundle->Inputs[0];
9181 TargetLowering::ArgListEntry Entry(V, getValue(V));
9182 Entry.IsCFGuardTarget = true;
9183 Args.push_back(x: Entry);
9184 }
9185
9186 // Disable tail calls if there is an swifterror argument. Targets have not
9187 // been updated to support tail calls.
9188 if (TLI.supportSwiftError() && SwiftErrorVal)
9189 isTailCall = false;
9190
9191 ConstantInt *CFIType = nullptr;
9192 if (CB.isIndirectCall()) {
9193 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_kcfi)) {
9194 if (!TLI.supportKCFIBundles())
9195 report_fatal_error(
9196 reason: "Target doesn't support calls with kcfi operand bundles.");
9197 CFIType = cast<ConstantInt>(Val: Bundle->Inputs[0]);
9198 assert(CFIType->getType()->isIntegerTy(32) && "Invalid CFI type");
9199 }
9200 }
9201
9202 SDValue ConvControlToken;
9203 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_convergencectrl)) {
9204 auto *Token = Bundle->Inputs[0].get();
9205 ConvControlToken = getValue(V: Token);
9206 }
9207
9208 GlobalValue *DeactivationSymbol = nullptr;
9209 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_deactivation_symbol)) {
9210 DeactivationSymbol = cast<GlobalValue>(Val: Bundle->Inputs[0].get());
9211 }
9212
9213 TargetLowering::CallLoweringInfo CLI(DAG);
9214 CLI.setDebugLoc(getCurSDLoc())
9215 .setChain(getRoot())
9216 .setCallee(ResultType: RetTy, FTy, Target: Callee, ArgsList: std::move(Args), Call: CB)
9217 .setTailCall(isTailCall)
9218 .setConvergent(CB.isConvergent())
9219 .setIsPreallocated(
9220 CB.countOperandBundlesOfType(ID: LLVMContext::OB_preallocated) != 0)
9221 .setCFIType(CFIType)
9222 .setConvergenceControlToken(ConvControlToken)
9223 .setDeactivationSymbol(DeactivationSymbol);
9224
9225 // Set the pointer authentication info if we have it.
9226 if (PAI) {
9227 if (!TLI.supportPtrAuthBundles())
9228 report_fatal_error(
9229 reason: "This target doesn't support calls with ptrauth operand bundles.");
9230 CLI.setPtrAuth(*PAI);
9231 }
9232
9233 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
9234
9235 if (Result.first.getNode()) {
9236 Result.first = lowerRangeToAssertZExt(DAG, I: CB, Op: Result.first);
9237 Result.first = lowerNoFPClassToAssertNoFPClass(DAG, I: CB, Op: Result.first);
9238 setValue(V: &CB, NewN: Result.first);
9239 }
9240
9241 // The last element of CLI.InVals has the SDValue for swifterror return.
9242 // Here we copy it to a virtual register and update SwiftErrorMap for
9243 // book-keeping.
9244 if (SwiftErrorVal && TLI.supportSwiftError()) {
9245 // Get the last element of InVals.
9246 SDValue Src = CLI.InVals.back();
9247 Register VReg =
9248 SwiftError.getOrCreateVRegDefAt(&CB, FuncInfo.MBB, SwiftErrorVal);
9249 SDValue CopyNode = CLI.DAG.getCopyToReg(Chain: Result.second, dl: CLI.DL, Reg: VReg, N: Src);
9250 DAG.setRoot(CopyNode);
9251 }
9252}
9253
9254static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
9255 SelectionDAGBuilder &Builder) {
9256 // Check to see if this load can be trivially constant folded, e.g. if the
9257 // input is from a string literal.
9258 if (const Constant *LoadInput = dyn_cast<Constant>(Val: PtrVal)) {
9259 // Cast pointer to the type we really want to load.
9260 Type *LoadTy =
9261 Type::getIntNTy(C&: PtrVal->getContext(), N: LoadVT.getScalarSizeInBits());
9262 if (LoadVT.isVector())
9263 LoadTy = FixedVectorType::get(ElementType: LoadTy, NumElts: LoadVT.getVectorNumElements());
9264 if (const Constant *LoadCst =
9265 ConstantFoldLoadFromConstPtr(C: const_cast<Constant *>(LoadInput),
9266 Ty: LoadTy, DL: Builder.DAG.getDataLayout()))
9267 return Builder.getValue(V: LoadCst);
9268 }
9269
9270 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
9271 // still constant memory, the input chain can be the entry node.
9272 SDValue Root;
9273 bool ConstantMemory = false;
9274
9275 // Do not serialize (non-volatile) loads of constant memory with anything.
9276 if (Builder.BatchAA && Builder.BatchAA->pointsToConstantMemory(P: PtrVal)) {
9277 Root = Builder.DAG.getEntryNode();
9278 ConstantMemory = true;
9279 } else {
9280 // Do not serialize non-volatile loads against each other.
9281 Root = Builder.DAG.getRoot();
9282 }
9283
9284 SDValue Ptr = Builder.getValue(V: PtrVal);
9285 SDValue LoadVal =
9286 Builder.DAG.getLoad(VT: LoadVT, dl: Builder.getCurSDLoc(), Chain: Root, Ptr,
9287 PtrInfo: MachinePointerInfo(PtrVal), Alignment: Align(1));
9288
9289 if (!ConstantMemory)
9290 Builder.PendingLoads.push_back(Elt: LoadVal.getValue(R: 1));
9291 return LoadVal;
9292}
9293
9294/// Record the value for an instruction that produces an integer result,
9295/// converting the type where necessary.
9296void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
9297 SDValue Value,
9298 bool IsSigned) {
9299 EVT VT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
9300 Ty: I.getType(), AllowUnknown: true);
9301 Value = DAG.getExtOrTrunc(IsSigned, Op: Value, DL: getCurSDLoc(), VT);
9302 setValue(V: &I, NewN: Value);
9303}
9304
9305/// See if we can lower a memcmp/bcmp call into an optimized form. If so, return
9306/// true and lower it. Otherwise return false, and it will be lowered like a
9307/// normal call.
9308/// The caller already checked that \p I calls the appropriate LibFunc with a
9309/// correct prototype.
9310bool SelectionDAGBuilder::visitMemCmpBCmpCall(const CallInst &I) {
9311 const Value *LHS = I.getArgOperand(i: 0), *RHS = I.getArgOperand(i: 1);
9312 const Value *Size = I.getArgOperand(i: 2);
9313 const ConstantSDNode *CSize = dyn_cast<ConstantSDNode>(Val: getValue(V: Size));
9314 if (CSize && CSize->getZExtValue() == 0) {
9315 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DL: DAG.getDataLayout(),
9316 Ty: I.getType(), AllowUnknown: true);
9317 setValue(V: &I, NewN: DAG.getConstant(Val: 0, DL: getCurSDLoc(), VT: CallVT));
9318 return true;
9319 }
9320
9321 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9322 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemcmp(
9323 DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(), Op1: getValue(V: LHS), Op2: getValue(V: RHS),
9324 Op3: getValue(V: Size), CI: &I);
9325 if (Res.first.getNode()) {
9326 processIntegerCallValue(I, Value: Res.first, IsSigned: true);
9327 PendingLoads.push_back(Elt: Res.second);
9328 return true;
9329 }
9330
9331 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
9332 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
9333 if (!CSize || !isOnlyUsedInZeroEqualityComparison(CxtI: &I))
9334 return false;
9335
9336 // If the target has a fast compare for the given size, it will return a
9337 // preferred load type for that size. Require that the load VT is legal and
9338 // that the target supports unaligned loads of that type. Otherwise, return
9339 // INVALID.
9340 auto hasFastLoadsAndCompare = [&](unsigned NumBits) {
9341 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9342 MVT LVT = TLI.hasFastEqualityCompare(NumBits);
9343 if (LVT != MVT::INVALID_SIMPLE_VALUE_TYPE) {
9344 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
9345 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
9346 // TODO: Check alignment of src and dest ptrs.
9347 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
9348 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
9349 if (!TLI.isTypeLegal(VT: LVT) ||
9350 !TLI.allowsMisalignedMemoryAccesses(LVT, AddrSpace: SrcAS) ||
9351 !TLI.allowsMisalignedMemoryAccesses(LVT, AddrSpace: DstAS))
9352 LVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
9353 }
9354
9355 return LVT;
9356 };
9357
9358 // This turns into unaligned loads. We only do this if the target natively
9359 // supports the MVT we'll be loading or if it is small enough (<= 4) that
9360 // we'll only produce a small number of byte loads.
9361 MVT LoadVT;
9362 unsigned NumBitsToCompare = CSize->getZExtValue() * 8;
9363 switch (NumBitsToCompare) {
9364 default:
9365 return false;
9366 case 16:
9367 LoadVT = MVT::i16;
9368 break;
9369 case 32:
9370 LoadVT = MVT::i32;
9371 break;
9372 case 64:
9373 case 128:
9374 case 256:
9375 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare);
9376 break;
9377 }
9378
9379 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE)
9380 return false;
9381
9382 SDValue LoadL = getMemCmpLoad(PtrVal: LHS, LoadVT, Builder&: *this);
9383 SDValue LoadR = getMemCmpLoad(PtrVal: RHS, LoadVT, Builder&: *this);
9384
9385 // Bitcast to a wide integer type if the loads are vectors.
9386 if (LoadVT.isVector()) {
9387 EVT CmpVT = EVT::getIntegerVT(Context&: LHS->getContext(), BitWidth: LoadVT.getSizeInBits());
9388 LoadL = DAG.getBitcast(VT: CmpVT, V: LoadL);
9389 LoadR = DAG.getBitcast(VT: CmpVT, V: LoadR);
9390 }
9391
9392 SDValue Cmp = DAG.getSetCC(DL: getCurSDLoc(), VT: MVT::i1, LHS: LoadL, RHS: LoadR, Cond: ISD::SETNE);
9393 processIntegerCallValue(I, Value: Cmp, IsSigned: false);
9394 return true;
9395}
9396
9397/// See if we can lower a memchr call into an optimized form. If so, return
9398/// true and lower it. Otherwise return false, and it will be lowered like a
9399/// normal call.
9400/// The caller already checked that \p I calls the appropriate LibFunc with a
9401/// correct prototype.
9402bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
9403 const Value *Src = I.getArgOperand(i: 0);
9404 const Value *Char = I.getArgOperand(i: 1);
9405 const Value *Length = I.getArgOperand(i: 2);
9406
9407 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9408 std::pair<SDValue, SDValue> Res =
9409 TSI.EmitTargetCodeForMemchr(DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(),
9410 Src: getValue(V: Src), Char: getValue(V: Char), Length: getValue(V: Length),
9411 SrcPtrInfo: MachinePointerInfo(Src));
9412 if (Res.first.getNode()) {
9413 setValue(V: &I, NewN: Res.first);
9414 PendingLoads.push_back(Elt: Res.second);
9415 return true;
9416 }
9417
9418 return false;
9419}
9420
9421/// See if we can lower a memccpy call into an optimized form. If so, return
9422/// true and lower it, otherwise return false and it will be lowered like a
9423/// normal call.
9424/// The caller already checked that \p I calls the appropriate LibFunc with a
9425/// correct prototype.
9426bool SelectionDAGBuilder::visitMemCCpyCall(const CallInst &I) {
9427 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9428 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemccpy(
9429 DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(), Dst: getValue(V: I.getArgOperand(i: 0)),
9430 Src: getValue(V: I.getArgOperand(i: 1)), C: getValue(V: I.getArgOperand(i: 2)),
9431 Size: getValue(V: I.getArgOperand(i: 3)), CI: &I);
9432
9433 if (Res.first) {
9434 processIntegerCallValue(I, Value: Res.first, IsSigned: true);
9435 PendingLoads.push_back(Elt: Res.second);
9436 return true;
9437 }
9438 return false;
9439}
9440
9441/// See if we can lower a mempcpy call into an optimized form. If so, return
9442/// true and lower it. Otherwise return false, and it will be lowered like a
9443/// normal call.
9444/// The caller already checked that \p I calls the appropriate LibFunc with a
9445/// correct prototype.
9446bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) {
9447 SDValue Dst = getValue(V: I.getArgOperand(i: 0));
9448 SDValue Src = getValue(V: I.getArgOperand(i: 1));
9449 SDValue Size = getValue(V: I.getArgOperand(i: 2));
9450
9451 Align DstAlign = DAG.InferPtrAlign(Ptr: Dst).valueOrOne();
9452 Align SrcAlign = DAG.InferPtrAlign(Ptr: Src).valueOrOne();
9453 // DAG::getMemcpy needs Alignment to be defined.
9454 Align Alignment = std::min(a: DstAlign, b: SrcAlign);
9455
9456 SDLoc sdl = getCurSDLoc();
9457
9458 // In the mempcpy context we need to pass in a false value for isTailCall
9459 // because the return pointer needs to be adjusted by the size of
9460 // the copied memory.
9461 SDValue Root = getMemoryRoot();
9462 SDValue MC = DAG.getMemcpy(
9463 Chain: Root, dl: sdl, Dst, Src, Size, Alignment, isVol: false, AlwaysInline: false, /*CI=*/nullptr,
9464 OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(I.getArgOperand(i: 0)),
9465 SrcPtrInfo: MachinePointerInfo(I.getArgOperand(i: 1)), AAInfo: I.getAAMetadata());
9466 assert(MC.getNode() != nullptr &&
9467 "** memcpy should not be lowered as TailCall in mempcpy context **");
9468 DAG.setRoot(MC);
9469
9470 // Check if Size needs to be truncated or extended.
9471 Size = DAG.getSExtOrTrunc(Op: Size, DL: sdl, VT: Dst.getValueType());
9472
9473 // Adjust return pointer to point just past the last dst byte.
9474 SDValue DstPlusSize = DAG.getMemBasePlusOffset(Base: Dst, Offset: Size, DL: sdl);
9475 setValue(V: &I, NewN: DstPlusSize);
9476 return true;
9477}
9478
9479/// See if we can lower a strcpy call into an optimized form. If so, return
9480/// true and lower it, otherwise return false and it will be lowered like a
9481/// normal call.
9482/// The caller already checked that \p I calls the appropriate LibFunc with a
9483/// correct prototype.
9484bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
9485 const Value *Arg0 = I.getArgOperand(i: 0), *Arg1 = I.getArgOperand(i: 1);
9486
9487 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9488 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForStrcpy(
9489 DAG, DL: getCurSDLoc(), Chain: getRoot(), Dest: getValue(V: Arg0), Src: getValue(V: Arg1),
9490 DestPtrInfo: MachinePointerInfo(Arg0), SrcPtrInfo: MachinePointerInfo(Arg1), isStpcpy, CI: &I);
9491 if (Res.first.getNode()) {
9492 setValue(V: &I, NewN: Res.first);
9493 DAG.setRoot(Res.second);
9494 return true;
9495 }
9496
9497 return false;
9498}
9499
9500/// See if we can lower a strcmp call into an optimized form. If so, return
9501/// true and lower it, otherwise return false and it will be lowered like a
9502/// normal call.
9503/// The caller already checked that \p I calls the appropriate LibFunc with a
9504/// correct prototype.
9505bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
9506 const Value *Arg0 = I.getArgOperand(i: 0), *Arg1 = I.getArgOperand(i: 1);
9507
9508 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9509 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForStrcmp(
9510 DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(), Op1: getValue(V: Arg0), Op2: getValue(V: Arg1),
9511 Op1PtrInfo: MachinePointerInfo(Arg0), Op2PtrInfo: MachinePointerInfo(Arg1), CI: &I);
9512 if (Res.first.getNode()) {
9513 processIntegerCallValue(I, Value: Res.first, IsSigned: true);
9514 PendingLoads.push_back(Elt: Res.second);
9515 return true;
9516 }
9517
9518 return false;
9519}
9520
9521/// See if we can lower a strlen call into an optimized form. If so, return
9522/// true and lower it, otherwise return false and it will be lowered like a
9523/// normal call.
9524/// The caller already checked that \p I calls the appropriate LibFunc with a
9525/// correct prototype.
9526bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
9527 const Value *Arg0 = I.getArgOperand(i: 0);
9528
9529 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9530 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForStrlen(
9531 DAG, DL: getCurSDLoc(), Chain: DAG.getRoot(), Src: getValue(V: Arg0), CI: &I);
9532 if (Res.first.getNode()) {
9533 processIntegerCallValue(I, Value: Res.first, IsSigned: false);
9534 PendingLoads.push_back(Elt: Res.second);
9535 return true;
9536 }
9537
9538 return false;
9539}
9540
9541/// See if we can lower a strnlen call into an optimized form. If so, return
9542/// true and lower it, otherwise return false and it will be lowered like a
9543/// normal call.
9544/// The caller already checked that \p I calls the appropriate LibFunc with a
9545/// correct prototype.
9546bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
9547 const Value *Arg0 = I.getArgOperand(i: 0), *Arg1 = I.getArgOperand(i: 1);
9548
9549 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9550 std::pair<SDValue, SDValue> Res =
9551 TSI.EmitTargetCodeForStrnlen(DAG, DL: getCurSDLoc(), Chain: DAG.getRoot(),
9552 Src: getValue(V: Arg0), MaxLength: getValue(V: Arg1),
9553 SrcPtrInfo: MachinePointerInfo(Arg0));
9554 if (Res.first.getNode()) {
9555 processIntegerCallValue(I, Value: Res.first, IsSigned: false);
9556 PendingLoads.push_back(Elt: Res.second);
9557 return true;
9558 }
9559
9560 return false;
9561}
9562
9563/// See if we can lower a Strstr call into an optimized form. If so, return
9564/// true and lower it, otherwise return false and it will be lowered like a
9565/// normal call.
9566/// The caller already checked that \p I calls the appropriate LibFunc with a
9567/// correct prototype.
9568bool SelectionDAGBuilder::visitStrstrCall(const CallInst &I) {
9569 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
9570 const Value *Arg0 = I.getArgOperand(i: 0), *Arg1 = I.getArgOperand(i: 1);
9571 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForStrstr(
9572 DAG, dl: getCurSDLoc(), Chain: DAG.getRoot(), Op1: getValue(V: Arg0), Op2: getValue(V: Arg1), CI: &I);
9573 if (Res.first) {
9574 processIntegerCallValue(I, Value: Res.first, IsSigned: false);
9575 PendingLoads.push_back(Elt: Res.second);
9576 return true;
9577 }
9578 return false;
9579}
9580
9581/// See if we can lower a unary floating-point operation into an SDNode with
9582/// the specified Opcode. If so, return true and lower it, otherwise return
9583/// false and it will be lowered like a normal call.
9584/// The caller already checked that \p I calls the appropriate LibFunc with a
9585/// correct prototype.
9586bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
9587 unsigned Opcode) {
9588 // We already checked this call's prototype; verify it doesn't modify errno.
9589 // Do not perform optimizations for call sites that require strict
9590 // floating-point semantics.
9591 if (!I.onlyReadsMemory() || I.isStrictFP())
9592 return false;
9593
9594 SDNodeFlags Flags;
9595 Flags.copyFMF(FPMO: cast<FPMathOperator>(Val: I));
9596
9597 SDValue Tmp = getValue(V: I.getArgOperand(i: 0));
9598 setValue(V: &I,
9599 NewN: DAG.getNode(Opcode, DL: getCurSDLoc(), VT: Tmp.getValueType(), Operand: Tmp, Flags));
9600 return true;
9601}
9602
9603/// See if we can lower a binary floating-point operation into an SDNode with
9604/// the specified Opcode. If so, return true and lower it. Otherwise return
9605/// false, and it will be lowered like a normal call.
9606/// The caller already checked that \p I calls the appropriate LibFunc with a
9607/// correct prototype.
9608bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
9609 unsigned Opcode) {
9610 // We already checked this call's prototype; verify it doesn't modify errno.
9611 // Do not perform optimizations for call sites that require strict
9612 // floating-point semantics.
9613 if (!I.onlyReadsMemory() || I.isStrictFP())
9614 return false;
9615
9616 SDNodeFlags Flags;
9617 Flags.copyFMF(FPMO: cast<FPMathOperator>(Val: I));
9618
9619 SDValue Tmp0 = getValue(V: I.getArgOperand(i: 0));
9620 SDValue Tmp1 = getValue(V: I.getArgOperand(i: 1));
9621 EVT VT = Tmp0.getValueType();
9622 setValue(V: &I, NewN: DAG.getNode(Opcode, DL: getCurSDLoc(), VT, N1: Tmp0, N2: Tmp1, Flags));
9623 return true;
9624}
9625
9626void SelectionDAGBuilder::visitCall(const CallInst &I) {
9627 // Handle inline assembly differently.
9628 if (I.isInlineAsm()) {
9629 visitInlineAsm(Call: I);
9630 return;
9631 }
9632
9633 diagnoseDontCall(CI: I);
9634
9635 if (Function *F = I.getCalledFunction()) {
9636 if (F->isDeclaration()) {
9637 // Is this an LLVM intrinsic?
9638 if (unsigned IID = F->getIntrinsicID()) {
9639 visitIntrinsicCall(I, Intrinsic: IID);
9640 return;
9641 }
9642 }
9643
9644 // Check for well-known libc/libm calls. If the function is internal, it
9645 // can't be a library call. Don't do the check if marked as nobuiltin for
9646 // some reason.
9647 // This code should not handle libcalls that are already canonicalized to
9648 // intrinsics by the middle-end.
9649 LibFunc Func;
9650 if (!I.isNoBuiltin() && !F->hasLocalLinkage() && F->hasName() &&
9651 LibInfo->getLibFunc(FDecl: *F, F&: Func) && LibInfo->hasOptimizedCodeGen(F: Func)) {
9652 switch (Func) {
9653 default: break;
9654 case LibFunc_bcmp:
9655 if (visitMemCmpBCmpCall(I))
9656 return;
9657 break;
9658 case LibFunc_copysign:
9659 case LibFunc_copysignf:
9660 case LibFunc_copysignl:
9661 // We already checked this call's prototype; verify it doesn't modify
9662 // errno.
9663 if (I.onlyReadsMemory()) {
9664 SDValue LHS = getValue(V: I.getArgOperand(i: 0));
9665 SDValue RHS = getValue(V: I.getArgOperand(i: 1));
9666 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::FCOPYSIGN, DL: getCurSDLoc(),
9667 VT: LHS.getValueType(), N1: LHS, N2: RHS));
9668 return;
9669 }
9670 break;
9671 case LibFunc_sin:
9672 case LibFunc_sinf:
9673 case LibFunc_sinl:
9674 if (visitUnaryFloatCall(I, Opcode: ISD::FSIN))
9675 return;
9676 break;
9677 case LibFunc_cos:
9678 case LibFunc_cosf:
9679 case LibFunc_cosl:
9680 if (visitUnaryFloatCall(I, Opcode: ISD::FCOS))
9681 return;
9682 break;
9683 case LibFunc_tan:
9684 case LibFunc_tanf:
9685 case LibFunc_tanl:
9686 if (visitUnaryFloatCall(I, Opcode: ISD::FTAN))
9687 return;
9688 break;
9689 case LibFunc_asin:
9690 case LibFunc_asinf:
9691 case LibFunc_asinl:
9692 if (visitUnaryFloatCall(I, Opcode: ISD::FASIN))
9693 return;
9694 break;
9695 case LibFunc_acos:
9696 case LibFunc_acosf:
9697 case LibFunc_acosl:
9698 if (visitUnaryFloatCall(I, Opcode: ISD::FACOS))
9699 return;
9700 break;
9701 case LibFunc_atan:
9702 case LibFunc_atanf:
9703 case LibFunc_atanl:
9704 if (visitUnaryFloatCall(I, Opcode: ISD::FATAN))
9705 return;
9706 break;
9707 case LibFunc_atan2:
9708 case LibFunc_atan2f:
9709 case LibFunc_atan2l:
9710 if (visitBinaryFloatCall(I, Opcode: ISD::FATAN2))
9711 return;
9712 break;
9713 case LibFunc_sinh:
9714 case LibFunc_sinhf:
9715 case LibFunc_sinhl:
9716 if (visitUnaryFloatCall(I, Opcode: ISD::FSINH))
9717 return;
9718 break;
9719 case LibFunc_cosh:
9720 case LibFunc_coshf:
9721 case LibFunc_coshl:
9722 if (visitUnaryFloatCall(I, Opcode: ISD::FCOSH))
9723 return;
9724 break;
9725 case LibFunc_tanh:
9726 case LibFunc_tanhf:
9727 case LibFunc_tanhl:
9728 if (visitUnaryFloatCall(I, Opcode: ISD::FTANH))
9729 return;
9730 break;
9731 case LibFunc_sqrt:
9732 case LibFunc_sqrtf:
9733 case LibFunc_sqrtl:
9734 case LibFunc_sqrt_finite:
9735 case LibFunc_sqrtf_finite:
9736 case LibFunc_sqrtl_finite:
9737 if (visitUnaryFloatCall(I, Opcode: ISD::FSQRT))
9738 return;
9739 break;
9740 case LibFunc_log2:
9741 case LibFunc_log2f:
9742 case LibFunc_log2l:
9743 if (visitUnaryFloatCall(I, Opcode: ISD::FLOG2))
9744 return;
9745 break;
9746 case LibFunc_exp2:
9747 case LibFunc_exp2f:
9748 case LibFunc_exp2l:
9749 if (visitUnaryFloatCall(I, Opcode: ISD::FEXP2))
9750 return;
9751 break;
9752 case LibFunc_exp10:
9753 case LibFunc_exp10f:
9754 case LibFunc_exp10l:
9755 if (visitUnaryFloatCall(I, Opcode: ISD::FEXP10))
9756 return;
9757 break;
9758 case LibFunc_ldexp:
9759 case LibFunc_ldexpf:
9760 case LibFunc_ldexpl:
9761 if (visitBinaryFloatCall(I, Opcode: ISD::FLDEXP))
9762 return;
9763 break;
9764 case LibFunc_strstr:
9765 if (visitStrstrCall(I))
9766 return;
9767 break;
9768 case LibFunc_memcmp:
9769 if (visitMemCmpBCmpCall(I))
9770 return;
9771 break;
9772 case LibFunc_memccpy:
9773 if (visitMemCCpyCall(I))
9774 return;
9775 break;
9776 case LibFunc_mempcpy:
9777 if (visitMemPCpyCall(I))
9778 return;
9779 break;
9780 case LibFunc_memchr:
9781 if (visitMemChrCall(I))
9782 return;
9783 break;
9784 case LibFunc_strcpy:
9785 if (visitStrCpyCall(I, isStpcpy: false))
9786 return;
9787 break;
9788 case LibFunc_stpcpy:
9789 if (visitStrCpyCall(I, isStpcpy: true))
9790 return;
9791 break;
9792 case LibFunc_strcmp:
9793 if (visitStrCmpCall(I))
9794 return;
9795 break;
9796 case LibFunc_strlen:
9797 if (visitStrLenCall(I))
9798 return;
9799 break;
9800 case LibFunc_strnlen:
9801 if (visitStrNLenCall(I))
9802 return;
9803 break;
9804 }
9805 }
9806 }
9807
9808 if (I.countOperandBundlesOfType(ID: LLVMContext::OB_ptrauth)) {
9809 LowerCallSiteWithPtrAuthBundle(CB: cast<CallBase>(Val: I), /*EHPadBB=*/nullptr);
9810 return;
9811 }
9812
9813 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
9814 // have to do anything here to lower funclet bundles.
9815 // CFGuardTarget bundles are lowered in LowerCallTo.
9816 failForInvalidBundles(
9817 I, Name: "calls",
9818 AllowedBundles: {LLVMContext::OB_deopt, LLVMContext::OB_funclet,
9819 LLVMContext::OB_cfguardtarget, LLVMContext::OB_preallocated,
9820 LLVMContext::OB_clang_arc_attachedcall, LLVMContext::OB_kcfi,
9821 LLVMContext::OB_convergencectrl, LLVMContext::OB_deactivation_symbol});
9822
9823 SDValue Callee = getValue(V: I.getCalledOperand());
9824
9825 if (I.hasDeoptState())
9826 LowerCallSiteWithDeoptBundle(Call: &I, Callee, EHPadBB: nullptr);
9827 else
9828 // Check if we can potentially perform a tail call. More detailed checking
9829 // is be done within LowerCallTo, after more information about the call is
9830 // known.
9831 LowerCallTo(CB: I, Callee, isTailCall: I.isTailCall(), isMustTailCall: I.isMustTailCall());
9832}
9833
9834void SelectionDAGBuilder::LowerCallSiteWithPtrAuthBundle(
9835 const CallBase &CB, const BasicBlock *EHPadBB) {
9836 auto PAB = CB.getOperandBundle(Name: "ptrauth");
9837 const Value *CalleeV = CB.getCalledOperand();
9838
9839 // Gather the call ptrauth data from the operand bundle:
9840 // [ i32 <key>, i64 <discriminator> ]
9841 const auto *Key = cast<ConstantInt>(Val: PAB->Inputs[0]);
9842 const Value *Discriminator = PAB->Inputs[1];
9843
9844 assert(Key->getType()->isIntegerTy(32) && "Invalid ptrauth key");
9845 assert(Discriminator->getType()->isIntegerTy(64) &&
9846 "Invalid ptrauth discriminator");
9847
9848 // Look through ptrauth constants to find the raw callee.
9849 // Do a direct unauthenticated call if we found it and everything matches.
9850 if (const auto *CalleeCPA = dyn_cast<ConstantPtrAuth>(Val: CalleeV))
9851 if (CalleeCPA->isKnownCompatibleWith(Key, Discriminator,
9852 DL: DAG.getDataLayout()))
9853 return LowerCallTo(CB, Callee: getValue(V: CalleeCPA->getPointer()), isTailCall: CB.isTailCall(),
9854 isMustTailCall: CB.isMustTailCall(), EHPadBB);
9855
9856 // Functions should never be ptrauth-called directly.
9857 assert(!isa<Function>(CalleeV) && "invalid direct ptrauth call");
9858
9859 // Otherwise, do an authenticated indirect call.
9860 TargetLowering::PtrAuthInfo PAI = {.Key: Key->getZExtValue(),
9861 .Discriminator: getValue(V: Discriminator)};
9862
9863 LowerCallTo(CB, Callee: getValue(V: CalleeV), isTailCall: CB.isTailCall(), isMustTailCall: CB.isMustTailCall(),
9864 EHPadBB, PAI: &PAI);
9865}
9866
9867namespace {
9868
9869/// AsmOperandInfo - This contains information for each constraint that we are
9870/// lowering.
9871class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
9872public:
9873 /// CallOperand - If this is the result output operand or a clobber
9874 /// this is null, otherwise it is the incoming operand to the CallInst.
9875 /// This gets modified as the asm is processed.
9876 SDValue CallOperand;
9877
9878 /// AssignedRegs - If this is a register or register class operand, this
9879 /// contains the set of register corresponding to the operand.
9880 RegsForValue AssignedRegs;
9881
9882 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
9883 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr, 0) {
9884 }
9885
9886 /// Whether or not this operand accesses memory
9887 bool hasMemory(const TargetLowering &TLI) const {
9888 // Indirect operand accesses access memory.
9889 if (isIndirect)
9890 return true;
9891
9892 for (const auto &Code : Codes)
9893 if (TLI.getConstraintType(Constraint: Code) == TargetLowering::C_Memory)
9894 return true;
9895
9896 return false;
9897 }
9898};
9899
9900
9901} // end anonymous namespace
9902
9903/// Make sure that the output operand \p OpInfo and its corresponding input
9904/// operand \p MatchingOpInfo have compatible constraint types (otherwise error
9905/// out).
9906static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo,
9907 SDISelAsmOperandInfo &MatchingOpInfo,
9908 SelectionDAG &DAG) {
9909 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
9910 return;
9911
9912 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
9913 const auto &TLI = DAG.getTargetLoweringInfo();
9914
9915 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
9916 TLI.getRegForInlineAsmConstraint(TRI, Constraint: OpInfo.ConstraintCode,
9917 VT: OpInfo.ConstraintVT);
9918 std::pair<unsigned, const TargetRegisterClass *> InputRC =
9919 TLI.getRegForInlineAsmConstraint(TRI, Constraint: MatchingOpInfo.ConstraintCode,
9920 VT: MatchingOpInfo.ConstraintVT);
9921 const bool OutOpIsIntOrFP =
9922 OpInfo.ConstraintVT.isInteger() || OpInfo.ConstraintVT.isFloatingPoint();
9923 const bool InOpIsIntOrFP = MatchingOpInfo.ConstraintVT.isInteger() ||
9924 MatchingOpInfo.ConstraintVT.isFloatingPoint();
9925 if ((OutOpIsIntOrFP != InOpIsIntOrFP) || (MatchRC.second != InputRC.second)) {
9926 // FIXME: error out in a more elegant fashion
9927 report_fatal_error(reason: "Unsupported asm: input constraint"
9928 " with a matching output constraint of"
9929 " incompatible type!");
9930 }
9931 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
9932}
9933
9934/// Get a direct memory input to behave well as an indirect operand.
9935/// This may introduce stores, hence the need for a \p Chain.
9936/// \return The (possibly updated) chain.
9937static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
9938 SDISelAsmOperandInfo &OpInfo,
9939 SelectionDAG &DAG) {
9940 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9941
9942 // If we don't have an indirect input, put it in the constpool if we can,
9943 // otherwise spill it to a stack slot.
9944 // TODO: This isn't quite right. We need to handle these according to
9945 // the addressing mode that the constraint wants. Also, this may take
9946 // an additional register for the computation and we don't want that
9947 // either.
9948
9949 // If the operand is a float, integer, or vector constant, spill to a
9950 // constant pool entry to get its address.
9951 const Value *OpVal = OpInfo.CallOperandVal;
9952 if (isa<ConstantFP>(Val: OpVal) || isa<ConstantInt>(Val: OpVal) ||
9953 isa<ConstantVector>(Val: OpVal) || isa<ConstantDataVector>(Val: OpVal)) {
9954 OpInfo.CallOperand = DAG.getConstantPool(
9955 C: cast<Constant>(Val: OpVal), VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
9956 return Chain;
9957 }
9958
9959 // Otherwise, create a stack slot and emit a store to it before the asm.
9960 Type *Ty = OpVal->getType();
9961 auto &DL = DAG.getDataLayout();
9962 TypeSize TySize = DL.getTypeAllocSize(Ty);
9963 MachineFunction &MF = DAG.getMachineFunction();
9964 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
9965 int StackID = 0;
9966 if (TySize.isScalable())
9967 StackID = TFI->getStackIDForScalableVectors();
9968 int SSFI = MF.getFrameInfo().CreateStackObject(Size: TySize.getKnownMinValue(),
9969 Alignment: DL.getPrefTypeAlign(Ty), isSpillSlot: false,
9970 Alloca: nullptr, ID: StackID);
9971 SDValue StackSlot = DAG.getFrameIndex(FI: SSFI, VT: TLI.getFrameIndexTy(DL));
9972 Chain = DAG.getTruncStore(Chain, dl: Location, Val: OpInfo.CallOperand, Ptr: StackSlot,
9973 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI: SSFI),
9974 SVT: TLI.getMemValueType(DL, Ty));
9975 OpInfo.CallOperand = StackSlot;
9976
9977 return Chain;
9978}
9979
9980/// GetRegistersForValue - Assign registers (virtual or physical) for the
9981/// specified operand. We prefer to assign virtual registers, to allow the
9982/// register allocator to handle the assignment process. However, if the asm
9983/// uses features that we can't model on machineinstrs, we have SDISel do the
9984/// allocation. This produces generally horrible, but correct, code.
9985///
9986/// OpInfo describes the operand
9987/// RefOpInfo describes the matching operand if any, the operand otherwise
9988static std::optional<unsigned>
9989getRegistersForValue(SelectionDAG &DAG, const SDLoc &DL,
9990 SDISelAsmOperandInfo &OpInfo,
9991 SDISelAsmOperandInfo &RefOpInfo) {
9992 LLVMContext &Context = *DAG.getContext();
9993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9994
9995 MachineFunction &MF = DAG.getMachineFunction();
9996 SmallVector<Register, 4> Regs;
9997 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
9998
9999 // No work to do for memory/address operands.
10000 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
10001 OpInfo.ConstraintType == TargetLowering::C_Address)
10002 return std::nullopt;
10003
10004 // If this is a constraint for a single physreg, or a constraint for a
10005 // register class, find it.
10006 unsigned AssignedReg;
10007 const TargetRegisterClass *RC;
10008 std::tie(args&: AssignedReg, args&: RC) = TLI.getRegForInlineAsmConstraint(
10009 TRI: &TRI, Constraint: RefOpInfo.ConstraintCode, VT: RefOpInfo.ConstraintVT);
10010 // RC is unset only on failure. Return immediately.
10011 if (!RC)
10012 return std::nullopt;
10013
10014 // Get the actual register value type. This is important, because the user
10015 // may have asked for (e.g.) the AX register in i32 type. We need to
10016 // remember that AX is actually i16 to get the right extension.
10017 const MVT RegVT = *TRI.legalclasstypes_begin(RC: *RC);
10018
10019 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) {
10020 // If this is an FP operand in an integer register (or visa versa), or more
10021 // generally if the operand value disagrees with the register class we plan
10022 // to stick it in, fix the operand type.
10023 //
10024 // If this is an input value, the bitcast to the new type is done now.
10025 // Bitcast for output value is done at the end of visitInlineAsm().
10026 if ((OpInfo.Type == InlineAsm::isOutput ||
10027 OpInfo.Type == InlineAsm::isInput) &&
10028 !TRI.isTypeLegalForClass(RC: *RC, T: OpInfo.ConstraintVT)) {
10029 // Try to convert to the first EVT that the reg class contains. If the
10030 // types are identical size, use a bitcast to convert (e.g. two differing
10031 // vector types). Note: output bitcast is done at the end of
10032 // visitInlineAsm().
10033 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
10034 // Exclude indirect inputs while they are unsupported because the code
10035 // to perform the load is missing and thus OpInfo.CallOperand still
10036 // refers to the input address rather than the pointed-to value.
10037 if (OpInfo.Type == InlineAsm::isInput && !OpInfo.isIndirect)
10038 OpInfo.CallOperand =
10039 DAG.getNode(Opcode: ISD::BITCAST, DL, VT: RegVT, Operand: OpInfo.CallOperand);
10040 OpInfo.ConstraintVT = RegVT;
10041 // If the operand is an FP value and we want it in integer registers,
10042 // use the corresponding integer type. This turns an f64 value into
10043 // i64, which can be passed with two i32 values on a 32-bit machine.
10044 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
10045 MVT VT = MVT::getIntegerVT(BitWidth: OpInfo.ConstraintVT.getSizeInBits());
10046 if (OpInfo.Type == InlineAsm::isInput)
10047 OpInfo.CallOperand =
10048 DAG.getNode(Opcode: ISD::BITCAST, DL, VT, Operand: OpInfo.CallOperand);
10049 OpInfo.ConstraintVT = VT;
10050 }
10051 }
10052 }
10053
10054 // No need to allocate a matching input constraint since the constraint it's
10055 // matching to has already been allocated.
10056 if (OpInfo.isMatchingInputConstraint())
10057 return std::nullopt;
10058
10059 EVT ValueVT = OpInfo.ConstraintVT;
10060 if (OpInfo.ConstraintVT == MVT::Other)
10061 ValueVT = RegVT;
10062
10063 // Initialize NumRegs.
10064 unsigned NumRegs = 1;
10065 if (OpInfo.ConstraintVT != MVT::Other)
10066 NumRegs = TLI.getNumRegisters(Context, VT: OpInfo.ConstraintVT, RegisterVT: RegVT);
10067
10068 // If this is a constraint for a specific physical register, like {r17},
10069 // assign it now.
10070
10071 // If this associated to a specific register, initialize iterator to correct
10072 // place. If virtual, make sure we have enough registers
10073
10074 // Initialize iterator if necessary
10075 TargetRegisterClass::iterator I = RC->begin();
10076 MachineRegisterInfo &RegInfo = MF.getRegInfo();
10077
10078 // Do not check for single registers.
10079 if (AssignedReg) {
10080 I = std::find(first: I, last: RC->end(), val: AssignedReg);
10081 if (I == RC->end()) {
10082 // RC does not contain the selected register, which indicates a
10083 // mismatch between the register and the required type/bitwidth.
10084 return {AssignedReg};
10085 }
10086 }
10087
10088 for (; NumRegs; --NumRegs, ++I) {
10089 assert(I != RC->end() && "Ran out of registers to allocate!");
10090 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RegClass: RC);
10091 Regs.push_back(Elt: R);
10092 }
10093
10094 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
10095 return std::nullopt;
10096}
10097
10098static unsigned
10099findMatchingInlineAsmOperand(unsigned OperandNo,
10100 const std::vector<SDValue> &AsmNodeOperands) {
10101 // Scan until we find the definition we already emitted of this operand.
10102 unsigned CurOp = InlineAsm::Op_FirstOperand;
10103 for (; OperandNo; --OperandNo) {
10104 // Advance to the next operand.
10105 unsigned OpFlag = AsmNodeOperands[CurOp]->getAsZExtVal();
10106 const InlineAsm::Flag F(OpFlag);
10107 assert(
10108 (F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isMemKind()) &&
10109 "Skipped past definitions?");
10110 CurOp += F.getNumOperandRegisters() + 1;
10111 }
10112 return CurOp;
10113}
10114
10115namespace {
10116
10117class ExtraFlags {
10118 unsigned Flags = 0;
10119
10120public:
10121 explicit ExtraFlags(const CallBase &Call) {
10122 const InlineAsm *IA = cast<InlineAsm>(Val: Call.getCalledOperand());
10123 if (IA->hasSideEffects())
10124 Flags |= InlineAsm::Extra_HasSideEffects;
10125 if (IA->isAlignStack())
10126 Flags |= InlineAsm::Extra_IsAlignStack;
10127 if (IA->canThrow())
10128 Flags |= InlineAsm::Extra_MayUnwind;
10129 if (Call.isConvergent())
10130 Flags |= InlineAsm::Extra_IsConvergent;
10131 Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
10132 }
10133
10134 void update(const TargetLowering::AsmOperandInfo &OpInfo) {
10135 // Ideally, we would only check against memory constraints. However, the
10136 // meaning of an Other constraint can be target-specific and we can't easily
10137 // reason about it. Therefore, be conservative and set MayLoad/MayStore
10138 // for Other constraints as well.
10139 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
10140 OpInfo.ConstraintType == TargetLowering::C_Other) {
10141 if (OpInfo.Type == InlineAsm::isInput)
10142 Flags |= InlineAsm::Extra_MayLoad;
10143 else if (OpInfo.Type == InlineAsm::isOutput)
10144 Flags |= InlineAsm::Extra_MayStore;
10145 else if (OpInfo.Type == InlineAsm::isClobber)
10146 Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
10147 }
10148 }
10149
10150 unsigned get() const { return Flags; }
10151};
10152
10153} // end anonymous namespace
10154
10155static bool isFunction(SDValue Op) {
10156 if (Op && Op.getOpcode() == ISD::GlobalAddress) {
10157 if (auto *GA = dyn_cast<GlobalAddressSDNode>(Val&: Op)) {
10158 auto Fn = dyn_cast_or_null<Function>(Val: GA->getGlobal());
10159
10160 // In normal "call dllimport func" instruction (non-inlineasm) it force
10161 // indirect access by specifing call opcode. And usually specially print
10162 // asm with indirect symbol (i.g: "*") according to opcode. Inline asm can
10163 // not do in this way now. (In fact, this is similar with "Data Access"
10164 // action). So here we ignore dllimport function.
10165 if (Fn && !Fn->hasDLLImportStorageClass())
10166 return true;
10167 }
10168 }
10169 return false;
10170}
10171
10172/// visitInlineAsm - Handle a call to an InlineAsm object.
10173void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
10174 const BasicBlock *EHPadBB) {
10175 const InlineAsm *IA = cast<InlineAsm>(Val: Call.getCalledOperand());
10176
10177 /// ConstraintOperands - Information about all of the constraints.
10178 SmallVector<SDISelAsmOperandInfo, 16> ConstraintOperands;
10179
10180 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10181 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
10182 DL: DAG.getDataLayout(), TRI: DAG.getSubtarget().getRegisterInfo(), Call);
10183
10184 // First Pass: Calculate HasSideEffects and ExtraFlags (AlignStack,
10185 // AsmDialect, MayLoad, MayStore).
10186 bool HasSideEffect = IA->hasSideEffects();
10187 ExtraFlags ExtraInfo(Call);
10188
10189 for (auto &T : TargetConstraints) {
10190 ConstraintOperands.push_back(Elt: SDISelAsmOperandInfo(T));
10191 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
10192
10193 if (OpInfo.CallOperandVal)
10194 OpInfo.CallOperand = getValue(V: OpInfo.CallOperandVal);
10195
10196 if (!HasSideEffect)
10197 HasSideEffect = OpInfo.hasMemory(TLI);
10198
10199 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
10200 // FIXME: Could we compute this on OpInfo rather than T?
10201
10202 // Compute the constraint code and ConstraintType to use.
10203 TLI.ComputeConstraintToUse(OpInfo&: T, Op: SDValue());
10204
10205 if (T.ConstraintType == TargetLowering::C_Immediate &&
10206 OpInfo.CallOperand && !isa<ConstantSDNode>(Val: OpInfo.CallOperand))
10207 // We've delayed emitting a diagnostic like the "n" constraint because
10208 // inlining could cause an integer showing up.
10209 return emitInlineAsmError(Call, Message: "constraint '" + Twine(T.ConstraintCode) +
10210 "' expects an integer constant "
10211 "expression");
10212
10213 ExtraInfo.update(OpInfo: T);
10214 }
10215
10216 // We won't need to flush pending loads if this asm doesn't touch
10217 // memory and is nonvolatile.
10218 SDValue Glue, Chain = (HasSideEffect) ? getRoot() : DAG.getRoot();
10219
10220 bool EmitEHLabels = isa<InvokeInst>(Val: Call);
10221 if (EmitEHLabels) {
10222 assert(EHPadBB && "InvokeInst must have an EHPadBB");
10223 }
10224 bool IsCallBr = isa<CallBrInst>(Val: Call);
10225
10226 if (IsCallBr || EmitEHLabels) {
10227 // If this is a callbr or invoke we need to flush pending exports since
10228 // inlineasm_br and invoke are terminators.
10229 // We need to do this before nodes are glued to the inlineasm_br node.
10230 Chain = getControlRoot();
10231 }
10232
10233 MCSymbol *BeginLabel = nullptr;
10234 if (EmitEHLabels) {
10235 Chain = lowerStartEH(Chain, EHPadBB, BeginLabel);
10236 }
10237
10238 int OpNo = -1;
10239 SmallVector<StringRef> AsmStrs;
10240 IA->collectAsmStrs(AsmStrs);
10241
10242 // Second pass over the constraints: compute which constraint option to use.
10243 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
10244 if (OpInfo.hasArg() || OpInfo.Type == InlineAsm::isOutput)
10245 OpNo++;
10246
10247 // If this is an output operand with a matching input operand, look up the
10248 // matching input. If their types mismatch, e.g. one is an integer, the
10249 // other is floating point, or their sizes are different, flag it as an
10250 // error.
10251 if (OpInfo.hasMatchingInput()) {
10252 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
10253 patchMatchingInput(OpInfo, MatchingOpInfo&: Input, DAG);
10254 }
10255
10256 // Compute the constraint code and ConstraintType to use.
10257 TLI.ComputeConstraintToUse(OpInfo, Op: OpInfo.CallOperand, DAG: &DAG);
10258
10259 if ((OpInfo.ConstraintType == TargetLowering::C_Memory &&
10260 OpInfo.Type == InlineAsm::isClobber) ||
10261 OpInfo.ConstraintType == TargetLowering::C_Address)
10262 continue;
10263
10264 // In Linux PIC model, there are 4 cases about value/label addressing:
10265 //
10266 // 1: Function call or Label jmp inside the module.
10267 // 2: Data access (such as global variable, static variable) inside module.
10268 // 3: Function call or Label jmp outside the module.
10269 // 4: Data access (such as global variable) outside the module.
10270 //
10271 // Due to current llvm inline asm architecture designed to not "recognize"
10272 // the asm code, there are quite troubles for us to treat mem addressing
10273 // differently for same value/adress used in different instuctions.
10274 // For example, in pic model, call a func may in plt way or direclty
10275 // pc-related, but lea/mov a function adress may use got.
10276 //
10277 // Here we try to "recognize" function call for the case 1 and case 3 in
10278 // inline asm. And try to adjust the constraint for them.
10279 //
10280 // TODO: Due to current inline asm didn't encourage to jmp to the outsider
10281 // label, so here we don't handle jmp function label now, but we need to
10282 // enhance it (especilly in PIC model) if we meet meaningful requirements.
10283 if (OpInfo.isIndirect && isFunction(Op: OpInfo.CallOperand) &&
10284 TLI.isInlineAsmTargetBranch(AsmStrs, OpNo) &&
10285 TM.getCodeModel() != CodeModel::Large) {
10286 OpInfo.isIndirect = false;
10287 OpInfo.ConstraintType = TargetLowering::C_Address;
10288 }
10289
10290 // If this is a memory input, and if the operand is not indirect, do what we
10291 // need to provide an address for the memory input.
10292 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
10293 !OpInfo.isIndirect) {
10294 assert((OpInfo.isMultipleAlternative ||
10295 (OpInfo.Type == InlineAsm::isInput)) &&
10296 "Can only indirectify direct input operands!");
10297
10298 // Memory operands really want the address of the value.
10299 Chain = getAddressForMemoryInput(Chain, Location: getCurSDLoc(), OpInfo, DAG);
10300
10301 // There is no longer a Value* corresponding to this operand.
10302 OpInfo.CallOperandVal = nullptr;
10303
10304 // It is now an indirect operand.
10305 OpInfo.isIndirect = true;
10306 }
10307
10308 }
10309
10310 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
10311 std::vector<SDValue> AsmNodeOperands;
10312 AsmNodeOperands.push_back(x: SDValue()); // reserve space for input chain
10313 AsmNodeOperands.push_back(x: DAG.getTargetExternalSymbol(
10314 Sym: IA->getAsmString().data(), VT: TLI.getProgramPointerTy(DL: DAG.getDataLayout())));
10315
10316 // If we have a !srcloc metadata node associated with it, we want to attach
10317 // this to the ultimately generated inline asm machineinstr. To do this, we
10318 // pass in the third operand as this (potentially null) inline asm MDNode.
10319 const MDNode *SrcLoc = Call.getMetadata(Kind: "srcloc");
10320 AsmNodeOperands.push_back(x: DAG.getMDNode(MD: SrcLoc));
10321
10322 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
10323 // bits as operand 3.
10324 AsmNodeOperands.push_back(x: DAG.getTargetConstant(
10325 Val: ExtraInfo.get(), DL: getCurSDLoc(), VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
10326
10327 // Third pass: Loop over operands to prepare DAG-level operands.. As part of
10328 // this, assign virtual and physical registers for inputs and otput.
10329 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
10330 // Assign Registers.
10331 SDISelAsmOperandInfo &RefOpInfo =
10332 OpInfo.isMatchingInputConstraint()
10333 ? ConstraintOperands[OpInfo.getMatchedOperand()]
10334 : OpInfo;
10335 const auto RegError =
10336 getRegistersForValue(DAG, DL: getCurSDLoc(), OpInfo, RefOpInfo);
10337 if (RegError) {
10338 const MachineFunction &MF = DAG.getMachineFunction();
10339 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
10340 const char *RegName = TRI.getName(RegNo: *RegError);
10341 emitInlineAsmError(Call, Message: "register '" + Twine(RegName) +
10342 "' allocated for constraint '" +
10343 Twine(OpInfo.ConstraintCode) +
10344 "' does not match required type");
10345 return;
10346 }
10347
10348 auto DetectWriteToReservedRegister = [&]() {
10349 const MachineFunction &MF = DAG.getMachineFunction();
10350 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
10351 for (Register Reg : OpInfo.AssignedRegs.Regs) {
10352 if (Reg.isPhysical() && TRI.isInlineAsmReadOnlyReg(MF, PhysReg: Reg)) {
10353 const char *RegName = TRI.getName(RegNo: Reg);
10354 emitInlineAsmError(Call, Message: "write to reserved register '" +
10355 Twine(RegName) + "'");
10356 return true;
10357 }
10358 }
10359 return false;
10360 };
10361 assert((OpInfo.ConstraintType != TargetLowering::C_Address ||
10362 (OpInfo.Type == InlineAsm::isInput &&
10363 !OpInfo.isMatchingInputConstraint())) &&
10364 "Only address as input operand is allowed.");
10365
10366 switch (OpInfo.Type) {
10367 case InlineAsm::isOutput:
10368 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
10369 const InlineAsm::ConstraintCode ConstraintID =
10370 TLI.getInlineAsmMemConstraint(ConstraintCode: OpInfo.ConstraintCode);
10371 assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
10372 "Failed to convert memory constraint code to constraint id.");
10373
10374 // Add information to the INLINEASM node to know about this output.
10375 InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
10376 OpFlags.setMemConstraint(ConstraintID);
10377 AsmNodeOperands.push_back(x: DAG.getTargetConstant(Val: OpFlags, DL: getCurSDLoc(),
10378 VT: MVT::i32));
10379 AsmNodeOperands.push_back(x: OpInfo.CallOperand);
10380 } else {
10381 // Otherwise, this outputs to a register (directly for C_Register /
10382 // C_RegisterClass, and a target-defined fashion for
10383 // C_Immediate/C_Other). Find a register that we can use.
10384 if (OpInfo.AssignedRegs.Regs.empty()) {
10385 emitInlineAsmError(
10386 Call, Message: "couldn't allocate output register for constraint '" +
10387 Twine(OpInfo.ConstraintCode) + "'");
10388 return;
10389 }
10390
10391 if (DetectWriteToReservedRegister())
10392 return;
10393
10394 // Add information to the INLINEASM node to know that this register is
10395 // set.
10396 OpInfo.AssignedRegs.AddInlineAsmOperands(
10397 Code: OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
10398 : InlineAsm::Kind::RegDef,
10399 HasMatching: false, MatchingIdx: 0, dl: getCurSDLoc(), DAG, Ops&: AsmNodeOperands);
10400 }
10401 break;
10402
10403 case InlineAsm::isInput:
10404 case InlineAsm::isLabel: {
10405 SDValue InOperandVal = OpInfo.CallOperand;
10406
10407 if (OpInfo.isMatchingInputConstraint()) {
10408 // If this is required to match an output register we have already set,
10409 // just use its register.
10410 auto CurOp = findMatchingInlineAsmOperand(OperandNo: OpInfo.getMatchedOperand(),
10411 AsmNodeOperands);
10412 InlineAsm::Flag Flag(AsmNodeOperands[CurOp]->getAsZExtVal());
10413 if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) {
10414 if (OpInfo.isIndirect) {
10415 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
10416 emitInlineAsmError(Call, Message: "inline asm not supported yet: "
10417 "don't know how to handle tied "
10418 "indirect register inputs");
10419 return;
10420 }
10421
10422 SmallVector<Register, 4> Regs;
10423 MachineFunction &MF = DAG.getMachineFunction();
10424 MachineRegisterInfo &MRI = MF.getRegInfo();
10425 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
10426 auto *R = cast<RegisterSDNode>(Val&: AsmNodeOperands[CurOp+1]);
10427 Register TiedReg = R->getReg();
10428 MVT RegVT = R->getSimpleValueType(ResNo: 0);
10429 const TargetRegisterClass *RC =
10430 TiedReg.isVirtual() ? MRI.getRegClass(Reg: TiedReg)
10431 : RegVT != MVT::Untyped ? TLI.getRegClassFor(VT: RegVT)
10432 : TRI.getMinimalPhysRegClass(Reg: TiedReg);
10433 for (unsigned i = 0, e = Flag.getNumOperandRegisters(); i != e; ++i)
10434 Regs.push_back(Elt: MRI.createVirtualRegister(RegClass: RC));
10435
10436 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
10437
10438 SDLoc dl = getCurSDLoc();
10439 // Use the produced MatchedRegs object to
10440 MatchedRegs.getCopyToRegs(Val: InOperandVal, DAG, dl, Chain, Glue: &Glue, V: &Call);
10441 MatchedRegs.AddInlineAsmOperands(Code: InlineAsm::Kind::RegUse, HasMatching: true,
10442 MatchingIdx: OpInfo.getMatchedOperand(), dl, DAG,
10443 Ops&: AsmNodeOperands);
10444 break;
10445 }
10446
10447 assert(Flag.isMemKind() && "Unknown matching constraint!");
10448 assert(Flag.getNumOperandRegisters() == 1 &&
10449 "Unexpected number of operands");
10450 // Add information to the INLINEASM node to know about this input.
10451 // See InlineAsm.h isUseOperandTiedToDef.
10452 Flag.clearMemConstraint();
10453 Flag.setMatchingOp(OpInfo.getMatchedOperand());
10454 AsmNodeOperands.push_back(x: DAG.getTargetConstant(
10455 Val: Flag, DL: getCurSDLoc(), VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
10456 AsmNodeOperands.push_back(x: AsmNodeOperands[CurOp+1]);
10457 break;
10458 }
10459
10460 // Treat indirect 'X' constraint as memory.
10461 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
10462 OpInfo.isIndirect)
10463 OpInfo.ConstraintType = TargetLowering::C_Memory;
10464
10465 if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
10466 OpInfo.ConstraintType == TargetLowering::C_Other) {
10467 std::vector<SDValue> Ops;
10468 TLI.LowerAsmOperandForConstraint(Op: InOperandVal, Constraint: OpInfo.ConstraintCode,
10469 Ops, DAG);
10470 if (Ops.empty()) {
10471 if (OpInfo.ConstraintType == TargetLowering::C_Immediate)
10472 if (isa<ConstantSDNode>(Val: InOperandVal)) {
10473 emitInlineAsmError(Call, Message: "value out of range for constraint '" +
10474 Twine(OpInfo.ConstraintCode) + "'");
10475 return;
10476 }
10477
10478 emitInlineAsmError(Call,
10479 Message: "invalid operand for inline asm constraint '" +
10480 Twine(OpInfo.ConstraintCode) + "'");
10481 return;
10482 }
10483
10484 // Add information to the INLINEASM node to know about this input.
10485 InlineAsm::Flag ResOpType(InlineAsm::Kind::Imm, Ops.size());
10486 AsmNodeOperands.push_back(x: DAG.getTargetConstant(
10487 Val: ResOpType, DL: getCurSDLoc(), VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
10488 llvm::append_range(C&: AsmNodeOperands, R&: Ops);
10489 break;
10490 }
10491
10492 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
10493 assert((OpInfo.isIndirect ||
10494 OpInfo.ConstraintType != TargetLowering::C_Memory) &&
10495 "Operand must be indirect to be a mem!");
10496 assert(InOperandVal.getValueType() ==
10497 TLI.getPointerTy(DAG.getDataLayout()) &&
10498 "Memory operands expect pointer values");
10499
10500 const InlineAsm::ConstraintCode ConstraintID =
10501 TLI.getInlineAsmMemConstraint(ConstraintCode: OpInfo.ConstraintCode);
10502 assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
10503 "Failed to convert memory constraint code to constraint id.");
10504
10505 // Add information to the INLINEASM node to know about this input.
10506 InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
10507 ResOpType.setMemConstraint(ConstraintID);
10508 AsmNodeOperands.push_back(x: DAG.getTargetConstant(Val: ResOpType,
10509 DL: getCurSDLoc(),
10510 VT: MVT::i32));
10511 AsmNodeOperands.push_back(x: InOperandVal);
10512 break;
10513 }
10514
10515 if (OpInfo.ConstraintType == TargetLowering::C_Address) {
10516 const InlineAsm::ConstraintCode ConstraintID =
10517 TLI.getInlineAsmMemConstraint(ConstraintCode: OpInfo.ConstraintCode);
10518 assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
10519 "Failed to convert memory constraint code to constraint id.");
10520
10521 InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
10522
10523 SDValue AsmOp = InOperandVal;
10524 if (isFunction(Op: InOperandVal)) {
10525 auto *GA = cast<GlobalAddressSDNode>(Val&: InOperandVal);
10526 ResOpType = InlineAsm::Flag(InlineAsm::Kind::Func, 1);
10527 AsmOp = DAG.getTargetGlobalAddress(GV: GA->getGlobal(), DL: getCurSDLoc(),
10528 VT: InOperandVal.getValueType(),
10529 offset: GA->getOffset());
10530 }
10531
10532 // Add information to the INLINEASM node to know about this input.
10533 ResOpType.setMemConstraint(ConstraintID);
10534
10535 AsmNodeOperands.push_back(
10536 x: DAG.getTargetConstant(Val: ResOpType, DL: getCurSDLoc(), VT: MVT::i32));
10537
10538 AsmNodeOperands.push_back(x: AsmOp);
10539 break;
10540 }
10541
10542 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
10543 OpInfo.ConstraintType != TargetLowering::C_Register) {
10544 emitInlineAsmError(Call, Message: "unknown asm constraint '" +
10545 Twine(OpInfo.ConstraintCode) + "'");
10546 return;
10547 }
10548
10549 // TODO: Support this.
10550 if (OpInfo.isIndirect) {
10551 emitInlineAsmError(
10552 Call, Message: "Don't know how to handle indirect register inputs yet "
10553 "for constraint '" +
10554 Twine(OpInfo.ConstraintCode) + "'");
10555 return;
10556 }
10557
10558 // Copy the input into the appropriate registers.
10559 if (OpInfo.AssignedRegs.Regs.empty()) {
10560 emitInlineAsmError(Call,
10561 Message: "couldn't allocate input reg for constraint '" +
10562 Twine(OpInfo.ConstraintCode) + "'");
10563 return;
10564 }
10565
10566 if (DetectWriteToReservedRegister())
10567 return;
10568
10569 SDLoc dl = getCurSDLoc();
10570
10571 OpInfo.AssignedRegs.getCopyToRegs(Val: InOperandVal, DAG, dl, Chain, Glue: &Glue,
10572 V: &Call);
10573
10574 OpInfo.AssignedRegs.AddInlineAsmOperands(Code: InlineAsm::Kind::RegUse, HasMatching: false,
10575 MatchingIdx: 0, dl, DAG, Ops&: AsmNodeOperands);
10576 break;
10577 }
10578 case InlineAsm::isClobber:
10579 // Add the clobbered value to the operand list, so that the register
10580 // allocator is aware that the physreg got clobbered.
10581 if (!OpInfo.AssignedRegs.Regs.empty())
10582 OpInfo.AssignedRegs.AddInlineAsmOperands(Code: InlineAsm::Kind::Clobber,
10583 HasMatching: false, MatchingIdx: 0, dl: getCurSDLoc(), DAG,
10584 Ops&: AsmNodeOperands);
10585 break;
10586 }
10587 }
10588
10589 // Finish up input operands. Set the input chain and add the flag last.
10590 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
10591 if (Glue.getNode()) AsmNodeOperands.push_back(x: Glue);
10592
10593 unsigned ISDOpc = IsCallBr ? ISD::INLINEASM_BR : ISD::INLINEASM;
10594 Chain = DAG.getNode(Opcode: ISDOpc, DL: getCurSDLoc(),
10595 VTList: DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue), Ops: AsmNodeOperands);
10596 Glue = Chain.getValue(R: 1);
10597
10598 // Do additional work to generate outputs.
10599
10600 SmallVector<EVT, 1> ResultVTs;
10601 SmallVector<SDValue, 1> ResultValues;
10602 SmallVector<SDValue, 8> OutChains;
10603
10604 llvm::Type *CallResultType = Call.getType();
10605 ArrayRef<Type *> ResultTypes;
10606 if (StructType *StructResult = dyn_cast<StructType>(Val: CallResultType))
10607 ResultTypes = StructResult->elements();
10608 else if (!CallResultType->isVoidTy())
10609 ResultTypes = ArrayRef(CallResultType);
10610
10611 auto CurResultType = ResultTypes.begin();
10612 auto handleRegAssign = [&](SDValue V) {
10613 assert(CurResultType != ResultTypes.end() && "Unexpected value");
10614 assert((*CurResultType)->isSized() && "Unexpected unsized type");
10615 EVT ResultVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: *CurResultType);
10616 ++CurResultType;
10617 // If the type of the inline asm call site return value is different but has
10618 // same size as the type of the asm output bitcast it. One example of this
10619 // is for vectors with different width / number of elements. This can
10620 // happen for register classes that can contain multiple different value
10621 // types. The preg or vreg allocated may not have the same VT as was
10622 // expected.
10623 //
10624 // This can also happen for a return value that disagrees with the register
10625 // class it is put in, eg. a double in a general-purpose register on a
10626 // 32-bit machine.
10627 if (ResultVT != V.getValueType() &&
10628 ResultVT.getSizeInBits() == V.getValueSizeInBits())
10629 V = DAG.getNode(Opcode: ISD::BITCAST, DL: getCurSDLoc(), VT: ResultVT, Operand: V);
10630 else if (ResultVT != V.getValueType() && ResultVT.isInteger() &&
10631 V.getValueType().isInteger()) {
10632 // If a result value was tied to an input value, the computed result
10633 // may have a wider width than the expected result. Extract the
10634 // relevant portion.
10635 V = DAG.getNode(Opcode: ISD::TRUNCATE, DL: getCurSDLoc(), VT: ResultVT, Operand: V);
10636 }
10637 assert(ResultVT == V.getValueType() && "Asm result value mismatch!");
10638 ResultVTs.push_back(Elt: ResultVT);
10639 ResultValues.push_back(Elt: V);
10640 };
10641
10642 // Deal with output operands.
10643 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
10644 if (OpInfo.Type == InlineAsm::isOutput) {
10645 SDValue Val;
10646 // Skip trivial output operands.
10647 if (OpInfo.AssignedRegs.Regs.empty())
10648 continue;
10649
10650 switch (OpInfo.ConstraintType) {
10651 case TargetLowering::C_Register:
10652 case TargetLowering::C_RegisterClass:
10653 Val = OpInfo.AssignedRegs.getCopyFromRegs(DAG, FuncInfo, dl: getCurSDLoc(),
10654 Chain, Glue: &Glue, V: &Call);
10655 break;
10656 case TargetLowering::C_Immediate:
10657 case TargetLowering::C_Other:
10658 Val = TLI.LowerAsmOutputForConstraint(Chain, Glue, DL: getCurSDLoc(),
10659 OpInfo, DAG);
10660 break;
10661 case TargetLowering::C_Memory:
10662 break; // Already handled.
10663 case TargetLowering::C_Address:
10664 break; // Silence warning.
10665 case TargetLowering::C_Unknown:
10666 assert(false && "Unexpected unknown constraint");
10667 }
10668
10669 // Indirect output manifest as stores. Record output chains.
10670 if (OpInfo.isIndirect) {
10671 const Value *Ptr = OpInfo.CallOperandVal;
10672 assert(Ptr && "Expected value CallOperandVal for indirect asm operand");
10673 SDValue Store = DAG.getStore(Chain, dl: getCurSDLoc(), Val, Ptr: getValue(V: Ptr),
10674 PtrInfo: MachinePointerInfo(Ptr));
10675 OutChains.push_back(Elt: Store);
10676 } else {
10677 // generate CopyFromRegs to associated registers.
10678 assert(!Call.getType()->isVoidTy() && "Bad inline asm!");
10679 if (Val.getOpcode() == ISD::MERGE_VALUES) {
10680 for (const SDValue &V : Val->op_values())
10681 handleRegAssign(V);
10682 } else
10683 handleRegAssign(Val);
10684 }
10685 }
10686 }
10687
10688 // Set results.
10689 if (!ResultValues.empty()) {
10690 assert(CurResultType == ResultTypes.end() &&
10691 "Mismatch in number of ResultTypes");
10692 assert(ResultValues.size() == ResultTypes.size() &&
10693 "Mismatch in number of output operands in asm result");
10694
10695 SDValue V = DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
10696 VTList: DAG.getVTList(VTs: ResultVTs), Ops: ResultValues);
10697 setValue(V: &Call, NewN: V);
10698 }
10699
10700 // Collect store chains.
10701 if (!OutChains.empty())
10702 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: getCurSDLoc(), VT: MVT::Other, Ops: OutChains);
10703
10704 if (EmitEHLabels) {
10705 Chain = lowerEndEH(Chain, II: cast<InvokeInst>(Val: &Call), EHPadBB, BeginLabel);
10706 }
10707
10708 // Only Update Root if inline assembly has a memory effect.
10709 if (ResultValues.empty() || HasSideEffect || !OutChains.empty() || IsCallBr ||
10710 EmitEHLabels)
10711 DAG.setRoot(Chain);
10712}
10713
10714void SelectionDAGBuilder::emitInlineAsmError(const CallBase &Call,
10715 const Twine &Message) {
10716 LLVMContext &Ctx = *DAG.getContext();
10717 Ctx.diagnose(DI: DiagnosticInfoInlineAsm(Call, Message));
10718
10719 // Make sure we leave the DAG in a valid state
10720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10721 SmallVector<EVT, 1> ValueVTs;
10722 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: Call.getType(), ValueVTs);
10723
10724 if (ValueVTs.empty())
10725 return;
10726
10727 SmallVector<SDValue, 1> Ops;
10728 for (const EVT &VT : ValueVTs)
10729 Ops.push_back(Elt: DAG.getUNDEF(VT));
10730
10731 setValue(V: &Call, NewN: DAG.getMergeValues(Ops, dl: getCurSDLoc()));
10732}
10733
10734void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
10735 DAG.setRoot(DAG.getNode(Opcode: ISD::VASTART, DL: getCurSDLoc(),
10736 VT: MVT::Other, N1: getRoot(),
10737 N2: getValue(V: I.getArgOperand(i: 0)),
10738 N3: DAG.getSrcValue(v: I.getArgOperand(i: 0))));
10739}
10740
10741void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
10742 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10743 const DataLayout &DL = DAG.getDataLayout();
10744 SDValue V = DAG.getVAArg(
10745 VT: TLI.getMemValueType(DL: DAG.getDataLayout(), Ty: I.getType()), dl: getCurSDLoc(),
10746 Chain: getRoot(), Ptr: getValue(V: I.getOperand(i_nocapture: 0)), SV: DAG.getSrcValue(v: I.getOperand(i_nocapture: 0)),
10747 Align: DL.getABITypeAlign(Ty: I.getType()).value());
10748 DAG.setRoot(V.getValue(R: 1));
10749
10750 if (I.getType()->isPointerTy())
10751 V = DAG.getPtrExtOrTrunc(
10752 Op: V, DL: getCurSDLoc(), VT: TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType()));
10753 setValue(V: &I, NewN: V);
10754}
10755
10756void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
10757 DAG.setRoot(DAG.getNode(Opcode: ISD::VAEND, DL: getCurSDLoc(),
10758 VT: MVT::Other, N1: getRoot(),
10759 N2: getValue(V: I.getArgOperand(i: 0)),
10760 N3: DAG.getSrcValue(v: I.getArgOperand(i: 0))));
10761}
10762
10763void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
10764 DAG.setRoot(DAG.getNode(Opcode: ISD::VACOPY, DL: getCurSDLoc(),
10765 VT: MVT::Other, N1: getRoot(),
10766 N2: getValue(V: I.getArgOperand(i: 0)),
10767 N3: getValue(V: I.getArgOperand(i: 1)),
10768 N4: DAG.getSrcValue(v: I.getArgOperand(i: 0)),
10769 N5: DAG.getSrcValue(v: I.getArgOperand(i: 1))));
10770}
10771
10772SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
10773 const Instruction &I,
10774 SDValue Op) {
10775 std::optional<ConstantRange> CR = getRange(I);
10776
10777 if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
10778 return Op;
10779
10780 APInt Lo = CR->getUnsignedMin();
10781 if (!Lo.isMinValue())
10782 return Op;
10783
10784 APInt Hi = CR->getUnsignedMax();
10785 unsigned Bits = std::max(a: Hi.getActiveBits(),
10786 b: static_cast<unsigned>(IntegerType::MIN_INT_BITS));
10787
10788 EVT SmallVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: Bits);
10789
10790 SDLoc SL = getCurSDLoc();
10791
10792 SDValue ZExt = DAG.getNode(Opcode: ISD::AssertZext, DL: SL, VT: Op.getValueType(), N1: Op,
10793 N2: DAG.getValueType(SmallVT));
10794 unsigned NumVals = Op.getNode()->getNumValues();
10795 if (NumVals == 1)
10796 return ZExt;
10797
10798 SmallVector<SDValue, 4> Ops;
10799
10800 Ops.push_back(Elt: ZExt);
10801 for (unsigned I = 1; I != NumVals; ++I)
10802 Ops.push_back(Elt: Op.getValue(R: I));
10803
10804 return DAG.getMergeValues(Ops, dl: SL);
10805}
10806
10807SDValue SelectionDAGBuilder::lowerNoFPClassToAssertNoFPClass(
10808 SelectionDAG &DAG, const Instruction &I, SDValue Op) {
10809 FPClassTest Classes = getNoFPClass(I);
10810 if (Classes == fcNone)
10811 return Op;
10812
10813 SDLoc SL = getCurSDLoc();
10814 SDValue TestConst = DAG.getTargetConstant(Val: Classes, DL: SDLoc(), VT: MVT::i32);
10815
10816 if (Op.getOpcode() != ISD::MERGE_VALUES) {
10817 return DAG.getNode(Opcode: ISD::AssertNoFPClass, DL: SL, VT: Op.getValueType(), N1: Op,
10818 N2: TestConst);
10819 }
10820
10821 SmallVector<SDValue, 8> Ops(Op.getNumOperands());
10822 for (unsigned I = 0, E = Ops.size(); I != E; ++I) {
10823 SDValue MergeOp = Op.getOperand(i: I);
10824 Ops[I] = DAG.getNode(Opcode: ISD::AssertNoFPClass, DL: SL, VT: MergeOp.getValueType(),
10825 N1: MergeOp, N2: TestConst);
10826 }
10827
10828 return DAG.getMergeValues(Ops, dl: SL);
10829}
10830
10831/// Populate a CallLowerinInfo (into \p CLI) based on the properties of
10832/// the call being lowered.
10833///
10834/// This is a helper for lowering intrinsics that follow a target calling
10835/// convention or require stack pointer adjustment. Only a subset of the
10836/// intrinsic's operands need to participate in the calling convention.
10837void SelectionDAGBuilder::populateCallLoweringInfo(
10838 TargetLowering::CallLoweringInfo &CLI, const CallBase *Call,
10839 unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy,
10840 AttributeSet RetAttrs, bool IsPatchPoint) {
10841 TargetLowering::ArgListTy Args;
10842 Args.reserve(n: NumArgs);
10843
10844 // Populate the argument list.
10845 // Attributes for args start at offset 1, after the return attribute.
10846 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs;
10847 ArgI != ArgE; ++ArgI) {
10848 const Value *V = Call->getOperand(i_nocapture: ArgI);
10849
10850 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
10851
10852 TargetLowering::ArgListEntry Entry(getValue(V), V->getType());
10853 Entry.setAttributes(Call, ArgIdx: ArgI);
10854 Args.push_back(x: Entry);
10855 }
10856
10857 CLI.setDebugLoc(getCurSDLoc())
10858 .setChain(getRoot())
10859 .setCallee(CC: Call->getCallingConv(), ResultType: ReturnTy, Target: Callee, ArgsList: std::move(Args),
10860 ResultAttrs: RetAttrs)
10861 .setDiscardResult(Call->use_empty())
10862 .setIsPatchPoint(IsPatchPoint)
10863 .setIsPreallocated(
10864 Call->countOperandBundlesOfType(ID: LLVMContext::OB_preallocated) != 0);
10865}
10866
10867/// Add a stack map intrinsic call's live variable operands to a stackmap
10868/// or patchpoint target node's operand list.
10869///
10870/// Constants are converted to TargetConstants purely as an optimization to
10871/// avoid constant materialization and register allocation.
10872///
10873/// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
10874/// generate addess computation nodes, and so FinalizeISel can convert the
10875/// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
10876/// address materialization and register allocation, but may also be required
10877/// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
10878/// alloca in the entry block, then the runtime may assume that the alloca's
10879/// StackMap location can be read immediately after compilation and that the
10880/// location is valid at any point during execution (this is similar to the
10881/// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
10882/// only available in a register, then the runtime would need to trap when
10883/// execution reaches the StackMap in order to read the alloca's location.
10884static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx,
10885 const SDLoc &DL, SmallVectorImpl<SDValue> &Ops,
10886 SelectionDAGBuilder &Builder) {
10887 SelectionDAG &DAG = Builder.DAG;
10888 for (unsigned I = StartIdx; I < Call.arg_size(); I++) {
10889 SDValue Op = Builder.getValue(V: Call.getArgOperand(i: I));
10890
10891 // Things on the stack are pointer-typed, meaning that they are already
10892 // legal and can be emitted directly to target nodes.
10893 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Val&: Op)) {
10894 Ops.push_back(Elt: DAG.getTargetFrameIndex(FI: FI->getIndex(), VT: Op.getValueType()));
10895 } else {
10896 // Otherwise emit a target independent node to be legalised.
10897 Ops.push_back(Elt: Builder.getValue(V: Call.getArgOperand(i: I)));
10898 }
10899 }
10900}
10901
10902/// Lower llvm.experimental.stackmap.
10903void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
10904 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
10905 // [live variables...])
10906
10907 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
10908
10909 SDValue Chain, InGlue, Callee;
10910 SmallVector<SDValue, 32> Ops;
10911
10912 SDLoc DL = getCurSDLoc();
10913 Callee = getValue(V: CI.getCalledOperand());
10914
10915 // The stackmap intrinsic only records the live variables (the arguments
10916 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
10917 // intrinsic, this won't be lowered to a function call. This means we don't
10918 // have to worry about calling conventions and target specific lowering code.
10919 // Instead we perform the call lowering right here.
10920 //
10921 // chain, flag = CALLSEQ_START(chain, 0, 0)
10922 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
10923 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
10924 //
10925 Chain = DAG.getCALLSEQ_START(Chain: getRoot(), InSize: 0, OutSize: 0, DL);
10926 InGlue = Chain.getValue(R: 1);
10927
10928 // Add the STACKMAP operands, starting with DAG house-keeping.
10929 Ops.push_back(Elt: Chain);
10930 Ops.push_back(Elt: InGlue);
10931
10932 // Add the <id>, <numShadowBytes> operands.
10933 //
10934 // These do not require legalisation, and can be emitted directly to target
10935 // constant nodes.
10936 SDValue ID = getValue(V: CI.getArgOperand(i: 0));
10937 assert(ID.getValueType() == MVT::i64);
10938 SDValue IDConst =
10939 DAG.getTargetConstant(Val: ID->getAsZExtVal(), DL, VT: ID.getValueType());
10940 Ops.push_back(Elt: IDConst);
10941
10942 SDValue Shad = getValue(V: CI.getArgOperand(i: 1));
10943 assert(Shad.getValueType() == MVT::i32);
10944 SDValue ShadConst =
10945 DAG.getTargetConstant(Val: Shad->getAsZExtVal(), DL, VT: Shad.getValueType());
10946 Ops.push_back(Elt: ShadConst);
10947
10948 // Add the live variables.
10949 addStackMapLiveVars(Call: CI, StartIdx: 2, DL, Ops, Builder&: *this);
10950
10951 // Create the STACKMAP node.
10952 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
10953 Chain = DAG.getNode(Opcode: ISD::STACKMAP, DL, VTList: NodeTys, Ops);
10954 InGlue = Chain.getValue(R: 1);
10955
10956 Chain = DAG.getCALLSEQ_END(Chain, Size1: 0, Size2: 0, Glue: InGlue, DL);
10957
10958 // Stackmaps don't generate values, so nothing goes into the NodeMap.
10959
10960 // Set the root to the target-lowered call chain.
10961 DAG.setRoot(Chain);
10962
10963 // Inform the Frame Information that we have a stackmap in this function.
10964 FuncInfo.MF->getFrameInfo().setHasStackMap();
10965}
10966
10967/// Lower llvm.experimental.patchpoint directly to its target opcode.
10968void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB,
10969 const BasicBlock *EHPadBB) {
10970 // <ty> @llvm.experimental.patchpoint.<ty>(i64 <id>,
10971 // i32 <numBytes>,
10972 // i8* <target>,
10973 // i32 <numArgs>,
10974 // [Args...],
10975 // [live variables...])
10976
10977 CallingConv::ID CC = CB.getCallingConv();
10978 bool IsAnyRegCC = CC == CallingConv::AnyReg;
10979 bool HasDef = !CB.getType()->isVoidTy();
10980 SDLoc dl = getCurSDLoc();
10981 SDValue Callee = getValue(V: CB.getArgOperand(i: PatchPointOpers::TargetPos));
10982
10983 // Handle immediate and symbolic callees.
10984 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Val&: Callee))
10985 Callee = DAG.getIntPtrConstant(Val: ConstCallee->getZExtValue(), DL: dl,
10986 /*isTarget=*/true);
10987 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
10988 Callee = DAG.getTargetGlobalAddress(GV: SymbolicCallee->getGlobal(),
10989 DL: SDLoc(SymbolicCallee),
10990 VT: SymbolicCallee->getValueType(ResNo: 0));
10991
10992 // Get the real number of arguments participating in the call <numArgs>
10993 SDValue NArgVal = getValue(V: CB.getArgOperand(i: PatchPointOpers::NArgPos));
10994 unsigned NumArgs = NArgVal->getAsZExtVal();
10995
10996 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
10997 // Intrinsics include all meta-operands up to but not including CC.
10998 unsigned NumMetaOpers = PatchPointOpers::CCPos;
10999 assert(CB.arg_size() >= NumMetaOpers + NumArgs &&
11000 "Not enough arguments provided to the patchpoint intrinsic");
11001
11002 // For AnyRegCC the arguments are lowered later on manually.
11003 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
11004 Type *ReturnTy =
11005 IsAnyRegCC ? Type::getVoidTy(C&: *DAG.getContext()) : CB.getType();
11006
11007 TargetLowering::CallLoweringInfo CLI(DAG);
11008 populateCallLoweringInfo(CLI, Call: &CB, ArgIdx: NumMetaOpers, NumArgs: NumCallArgs, Callee,
11009 ReturnTy, RetAttrs: CB.getAttributes().getRetAttrs(), IsPatchPoint: true);
11010 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
11011
11012 SDNode *CallEnd = Result.second.getNode();
11013 if (CallEnd->getOpcode() == ISD::EH_LABEL)
11014 CallEnd = CallEnd->getOperand(Num: 0).getNode();
11015 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
11016 CallEnd = CallEnd->getOperand(Num: 0).getNode();
11017
11018 /// Get a call instruction from the call sequence chain.
11019 /// Tail calls are not allowed.
11020 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
11021 "Expected a callseq node.");
11022 SDNode *Call = CallEnd->getOperand(Num: 0).getNode();
11023 bool HasGlue = Call->getGluedNode();
11024
11025 // Replace the target specific call node with the patchable intrinsic.
11026 SmallVector<SDValue, 8> Ops;
11027
11028 // Push the chain.
11029 Ops.push_back(Elt: *(Call->op_begin()));
11030
11031 // Optionally, push the glue (if any).
11032 if (HasGlue)
11033 Ops.push_back(Elt: *(Call->op_end() - 1));
11034
11035 // Push the register mask info.
11036 if (HasGlue)
11037 Ops.push_back(Elt: *(Call->op_end() - 2));
11038 else
11039 Ops.push_back(Elt: *(Call->op_end() - 1));
11040
11041 // Add the <id> and <numBytes> constants.
11042 SDValue IDVal = getValue(V: CB.getArgOperand(i: PatchPointOpers::IDPos));
11043 Ops.push_back(Elt: DAG.getTargetConstant(Val: IDVal->getAsZExtVal(), DL: dl, VT: MVT::i64));
11044 SDValue NBytesVal = getValue(V: CB.getArgOperand(i: PatchPointOpers::NBytesPos));
11045 Ops.push_back(Elt: DAG.getTargetConstant(Val: NBytesVal->getAsZExtVal(), DL: dl, VT: MVT::i32));
11046
11047 // Add the callee.
11048 Ops.push_back(Elt: Callee);
11049
11050 // Adjust <numArgs> to account for any arguments that have been passed on the
11051 // stack instead.
11052 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
11053 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
11054 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
11055 Ops.push_back(Elt: DAG.getTargetConstant(Val: NumCallRegArgs, DL: dl, VT: MVT::i32));
11056
11057 // Add the calling convention
11058 Ops.push_back(Elt: DAG.getTargetConstant(Val: (unsigned)CC, DL: dl, VT: MVT::i32));
11059
11060 // Add the arguments we omitted previously. The register allocator should
11061 // place these in any free register.
11062 if (IsAnyRegCC)
11063 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
11064 Ops.push_back(Elt: getValue(V: CB.getArgOperand(i)));
11065
11066 // Push the arguments from the call instruction.
11067 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
11068 Ops.append(in_start: Call->op_begin() + 2, in_end: e);
11069
11070 // Push live variables for the stack map.
11071 addStackMapLiveVars(Call: CB, StartIdx: NumMetaOpers + NumArgs, DL: dl, Ops, Builder&: *this);
11072
11073 SDVTList NodeTys;
11074 if (IsAnyRegCC && HasDef) {
11075 // Create the return types based on the intrinsic definition
11076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11077 SmallVector<EVT, 3> ValueVTs;
11078 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: CB.getType(), ValueVTs);
11079 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
11080
11081 // There is always a chain and a glue type at the end
11082 ValueVTs.push_back(Elt: MVT::Other);
11083 ValueVTs.push_back(Elt: MVT::Glue);
11084 NodeTys = DAG.getVTList(VTs: ValueVTs);
11085 } else
11086 NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
11087
11088 // Replace the target specific call node with a PATCHPOINT node.
11089 SDValue PPV = DAG.getNode(Opcode: ISD::PATCHPOINT, DL: dl, VTList: NodeTys, Ops);
11090
11091 // Update the NodeMap.
11092 if (HasDef) {
11093 if (IsAnyRegCC)
11094 setValue(V: &CB, NewN: SDValue(PPV.getNode(), 0));
11095 else
11096 setValue(V: &CB, NewN: Result.first);
11097 }
11098
11099 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
11100 // call sequence. Furthermore the location of the chain and glue can change
11101 // when the AnyReg calling convention is used and the intrinsic returns a
11102 // value.
11103 if (IsAnyRegCC && HasDef) {
11104 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
11105 SDValue To[] = {PPV.getValue(R: 1), PPV.getValue(R: 2)};
11106 DAG.ReplaceAllUsesOfValuesWith(From, To, Num: 2);
11107 } else
11108 DAG.ReplaceAllUsesWith(From: Call, To: PPV.getNode());
11109 DAG.DeleteNode(N: Call);
11110
11111 // Inform the Frame Information that we have a patchpoint in this function.
11112 FuncInfo.MF->getFrameInfo().setHasPatchPoint();
11113}
11114
11115void SelectionDAGBuilder::visitVectorReduce(const CallInst &I,
11116 unsigned Intrinsic) {
11117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11118 SDValue Op1 = getValue(V: I.getArgOperand(i: 0));
11119 SDValue Op2;
11120 if (I.arg_size() > 1)
11121 Op2 = getValue(V: I.getArgOperand(i: 1));
11122 SDLoc dl = getCurSDLoc();
11123 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
11124 SDValue Res;
11125 SDNodeFlags SDFlags;
11126 if (auto *FPMO = dyn_cast<FPMathOperator>(Val: &I))
11127 SDFlags.copyFMF(FPMO: *FPMO);
11128
11129 switch (Intrinsic) {
11130 case Intrinsic::vector_reduce_fadd:
11131 if (SDFlags.hasAllowReassociation())
11132 Res = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT, N1: Op1,
11133 N2: DAG.getNode(Opcode: ISD::VECREDUCE_FADD, DL: dl, VT, Operand: Op2, Flags: SDFlags),
11134 Flags: SDFlags);
11135 else
11136 Res = DAG.getNode(Opcode: ISD::VECREDUCE_SEQ_FADD, DL: dl, VT, N1: Op1, N2: Op2, Flags: SDFlags);
11137 break;
11138 case Intrinsic::vector_reduce_fmul:
11139 if (SDFlags.hasAllowReassociation())
11140 Res = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: Op1,
11141 N2: DAG.getNode(Opcode: ISD::VECREDUCE_FMUL, DL: dl, VT, Operand: Op2, Flags: SDFlags),
11142 Flags: SDFlags);
11143 else
11144 Res = DAG.getNode(Opcode: ISD::VECREDUCE_SEQ_FMUL, DL: dl, VT, N1: Op1, N2: Op2, Flags: SDFlags);
11145 break;
11146 case Intrinsic::vector_reduce_add:
11147 Res = DAG.getNode(Opcode: ISD::VECREDUCE_ADD, DL: dl, VT, Operand: Op1);
11148 break;
11149 case Intrinsic::vector_reduce_mul:
11150 Res = DAG.getNode(Opcode: ISD::VECREDUCE_MUL, DL: dl, VT, Operand: Op1);
11151 break;
11152 case Intrinsic::vector_reduce_and:
11153 Res = DAG.getNode(Opcode: ISD::VECREDUCE_AND, DL: dl, VT, Operand: Op1);
11154 break;
11155 case Intrinsic::vector_reduce_or:
11156 Res = DAG.getNode(Opcode: ISD::VECREDUCE_OR, DL: dl, VT, Operand: Op1);
11157 break;
11158 case Intrinsic::vector_reduce_xor:
11159 Res = DAG.getNode(Opcode: ISD::VECREDUCE_XOR, DL: dl, VT, Operand: Op1);
11160 break;
11161 case Intrinsic::vector_reduce_smax:
11162 Res = DAG.getNode(Opcode: ISD::VECREDUCE_SMAX, DL: dl, VT, Operand: Op1);
11163 break;
11164 case Intrinsic::vector_reduce_smin:
11165 Res = DAG.getNode(Opcode: ISD::VECREDUCE_SMIN, DL: dl, VT, Operand: Op1);
11166 break;
11167 case Intrinsic::vector_reduce_umax:
11168 Res = DAG.getNode(Opcode: ISD::VECREDUCE_UMAX, DL: dl, VT, Operand: Op1);
11169 break;
11170 case Intrinsic::vector_reduce_umin:
11171 Res = DAG.getNode(Opcode: ISD::VECREDUCE_UMIN, DL: dl, VT, Operand: Op1);
11172 break;
11173 case Intrinsic::vector_reduce_fmax:
11174 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMAX, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11175 break;
11176 case Intrinsic::vector_reduce_fmin:
11177 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMIN, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11178 break;
11179 case Intrinsic::vector_reduce_fmaximum:
11180 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMAXIMUM, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11181 break;
11182 case Intrinsic::vector_reduce_fminimum:
11183 Res = DAG.getNode(Opcode: ISD::VECREDUCE_FMINIMUM, DL: dl, VT, Operand: Op1, Flags: SDFlags);
11184 break;
11185 default:
11186 llvm_unreachable("Unhandled vector reduce intrinsic");
11187 }
11188 setValue(V: &I, NewN: Res);
11189}
11190
11191/// Returns an AttributeList representing the attributes applied to the return
11192/// value of the given call.
11193static AttributeList getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
11194 SmallVector<Attribute::AttrKind, 2> Attrs;
11195 if (CLI.RetSExt)
11196 Attrs.push_back(Elt: Attribute::SExt);
11197 if (CLI.RetZExt)
11198 Attrs.push_back(Elt: Attribute::ZExt);
11199 if (CLI.IsInReg)
11200 Attrs.push_back(Elt: Attribute::InReg);
11201
11202 return AttributeList::get(C&: CLI.RetTy->getContext(), Index: AttributeList::ReturnIndex,
11203 Kinds: Attrs);
11204}
11205
11206/// TargetLowering::LowerCallTo - This is the default LowerCallTo
11207/// implementation, which just calls LowerCall.
11208/// FIXME: When all targets are
11209/// migrated to using LowerCall, this hook should be integrated into SDISel.
11210std::pair<SDValue, SDValue>
11211TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
11212 LLVMContext &Context = CLI.RetTy->getContext();
11213
11214 // Handle the incoming return values from the call.
11215 CLI.Ins.clear();
11216 SmallVector<Type *, 4> RetOrigTys;
11217 SmallVector<TypeSize, 4> Offsets;
11218 auto &DL = CLI.DAG.getDataLayout();
11219 ComputeValueTypes(DL, Ty: CLI.OrigRetTy, Types&: RetOrigTys, Offsets: &Offsets);
11220
11221 SmallVector<EVT, 4> RetVTs;
11222 if (CLI.RetTy != CLI.OrigRetTy) {
11223 assert(RetOrigTys.size() == 1 &&
11224 "Only supported for non-aggregate returns");
11225 RetVTs.push_back(Elt: getValueType(DL, Ty: CLI.RetTy));
11226 } else {
11227 for (Type *Ty : RetOrigTys)
11228 RetVTs.push_back(Elt: getValueType(DL, Ty));
11229 }
11230
11231 if (CLI.IsPostTypeLegalization) {
11232 // If we are lowering a libcall after legalization, split the return type.
11233 SmallVector<Type *, 4> OldRetOrigTys;
11234 SmallVector<EVT, 4> OldRetVTs;
11235 SmallVector<TypeSize, 4> OldOffsets;
11236 RetOrigTys.swap(RHS&: OldRetOrigTys);
11237 RetVTs.swap(RHS&: OldRetVTs);
11238 Offsets.swap(RHS&: OldOffsets);
11239
11240 for (size_t i = 0, e = OldRetVTs.size(); i != e; ++i) {
11241 EVT RetVT = OldRetVTs[i];
11242 uint64_t Offset = OldOffsets[i];
11243 MVT RegisterVT = getRegisterType(Context, VT: RetVT);
11244 unsigned NumRegs = getNumRegisters(Context, VT: RetVT);
11245 unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8;
11246 RetOrigTys.append(NumInputs: NumRegs, Elt: OldRetOrigTys[i]);
11247 RetVTs.append(NumInputs: NumRegs, Elt: RegisterVT);
11248 for (unsigned j = 0; j != NumRegs; ++j)
11249 Offsets.push_back(Elt: TypeSize::getFixed(ExactSize: Offset + j * RegisterVTByteSZ));
11250 }
11251 }
11252
11253 SmallVector<ISD::OutputArg, 4> Outs;
11254 GetReturnInfo(CC: CLI.CallConv, ReturnType: CLI.RetTy, attr: getReturnAttrs(CLI), Outs, TLI: *this, DL);
11255
11256 bool CanLowerReturn =
11257 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
11258 CLI.IsVarArg, Outs, Context, RetTy: CLI.RetTy);
11259
11260 SDValue DemoteStackSlot;
11261 int DemoteStackIdx = -100;
11262 if (!CanLowerReturn) {
11263 // FIXME: equivalent assert?
11264 // assert(!CS.hasInAllocaArgument() &&
11265 // "sret demotion is incompatible with inalloca");
11266 uint64_t TySize = DL.getTypeAllocSize(Ty: CLI.RetTy);
11267 Align Alignment = DL.getPrefTypeAlign(Ty: CLI.RetTy);
11268 MachineFunction &MF = CLI.DAG.getMachineFunction();
11269 DemoteStackIdx =
11270 MF.getFrameInfo().CreateStackObject(Size: TySize, Alignment, isSpillSlot: false);
11271 Type *StackSlotPtrType = PointerType::get(C&: Context, AddressSpace: DL.getAllocaAddrSpace());
11272
11273 DemoteStackSlot = CLI.DAG.getFrameIndex(FI: DemoteStackIdx, VT: getFrameIndexTy(DL));
11274 ArgListEntry Entry(DemoteStackSlot, StackSlotPtrType);
11275 Entry.IsSRet = true;
11276 Entry.Alignment = Alignment;
11277 CLI.getArgs().insert(position: CLI.getArgs().begin(), x: Entry);
11278 CLI.NumFixedArgs += 1;
11279 CLI.getArgs()[0].IndirectType = CLI.RetTy;
11280 CLI.RetTy = CLI.OrigRetTy = Type::getVoidTy(C&: Context);
11281
11282 // sret demotion isn't compatible with tail-calls, since the sret argument
11283 // points into the callers stack frame.
11284 CLI.IsTailCall = false;
11285 } else {
11286 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
11287 Ty: CLI.RetTy, CallConv: CLI.CallConv, isVarArg: CLI.IsVarArg, DL);
11288 for (unsigned I = 0, E = RetVTs.size(); I != E; ++I) {
11289 ISD::ArgFlagsTy Flags;
11290 if (NeedsRegBlock) {
11291 Flags.setInConsecutiveRegs();
11292 if (I == RetVTs.size() - 1)
11293 Flags.setInConsecutiveRegsLast();
11294 }
11295 EVT VT = RetVTs[I];
11296 MVT RegisterVT = getRegisterTypeForCallingConv(Context, CC: CLI.CallConv, VT);
11297 unsigned NumRegs =
11298 getNumRegistersForCallingConv(Context, CC: CLI.CallConv, VT);
11299 for (unsigned i = 0; i != NumRegs; ++i) {
11300 ISD::InputArg Ret(Flags, RegisterVT, VT, RetOrigTys[I],
11301 CLI.IsReturnValueUsed, ISD::InputArg::NoArgIndex, 0);
11302 if (CLI.RetTy->isPointerTy()) {
11303 Ret.Flags.setPointer();
11304 Ret.Flags.setPointerAddrSpace(
11305 cast<PointerType>(Val: CLI.RetTy)->getAddressSpace());
11306 }
11307 if (CLI.RetSExt)
11308 Ret.Flags.setSExt();
11309 if (CLI.RetZExt)
11310 Ret.Flags.setZExt();
11311 if (CLI.IsInReg)
11312 Ret.Flags.setInReg();
11313 CLI.Ins.push_back(Elt: Ret);
11314 }
11315 }
11316 }
11317
11318 // We push in swifterror return as the last element of CLI.Ins.
11319 ArgListTy &Args = CLI.getArgs();
11320 if (supportSwiftError()) {
11321 for (const ArgListEntry &Arg : Args) {
11322 if (Arg.IsSwiftError) {
11323 ISD::ArgFlagsTy Flags;
11324 Flags.setSwiftError();
11325 ISD::InputArg Ret(Flags, getPointerTy(DL), EVT(getPointerTy(DL)),
11326 PointerType::getUnqual(C&: Context),
11327 /*Used=*/true, ISD::InputArg::NoArgIndex, 0);
11328 CLI.Ins.push_back(Elt: Ret);
11329 }
11330 }
11331 }
11332
11333 // Handle all of the outgoing arguments.
11334 CLI.Outs.clear();
11335 CLI.OutVals.clear();
11336 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
11337 SmallVector<Type *, 4> OrigArgTys;
11338 ComputeValueTypes(DL, Ty: Args[i].OrigTy, Types&: OrigArgTys);
11339 // FIXME: Split arguments if CLI.IsPostTypeLegalization
11340 Type *FinalType = Args[i].Ty;
11341 if (Args[i].IsByVal)
11342 FinalType = Args[i].IndirectType;
11343 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
11344 Ty: FinalType, CallConv: CLI.CallConv, isVarArg: CLI.IsVarArg, DL);
11345 for (unsigned Value = 0, NumValues = OrigArgTys.size(); Value != NumValues;
11346 ++Value) {
11347 Type *OrigArgTy = OrigArgTys[Value];
11348 Type *ArgTy = OrigArgTy;
11349 if (Args[i].Ty != Args[i].OrigTy) {
11350 assert(Value == 0 && "Only supported for non-aggregate arguments");
11351 ArgTy = Args[i].Ty;
11352 }
11353
11354 EVT VT = getValueType(DL, Ty: ArgTy);
11355 SDValue Op = SDValue(Args[i].Node.getNode(),
11356 Args[i].Node.getResNo() + Value);
11357 ISD::ArgFlagsTy Flags;
11358
11359 // Certain targets (such as MIPS), may have a different ABI alignment
11360 // for a type depending on the context. Give the target a chance to
11361 // specify the alignment it wants.
11362 const Align OriginalAlignment(getABIAlignmentForCallingConv(ArgTy, DL));
11363 Flags.setOrigAlign(OriginalAlignment);
11364
11365 if (i >= CLI.NumFixedArgs)
11366 Flags.setVarArg();
11367 if (ArgTy->isPointerTy()) {
11368 Flags.setPointer();
11369 Flags.setPointerAddrSpace(cast<PointerType>(Val: ArgTy)->getAddressSpace());
11370 }
11371 if (Args[i].IsZExt)
11372 Flags.setZExt();
11373 if (Args[i].IsSExt)
11374 Flags.setSExt();
11375 if (Args[i].IsNoExt)
11376 Flags.setNoExt();
11377 if (Args[i].IsInReg) {
11378 // If we are using vectorcall calling convention, a structure that is
11379 // passed InReg - is surely an HVA
11380 if (CLI.CallConv == CallingConv::X86_VectorCall &&
11381 isa<StructType>(Val: FinalType)) {
11382 // The first value of a structure is marked
11383 if (0 == Value)
11384 Flags.setHvaStart();
11385 Flags.setHva();
11386 }
11387 // Set InReg Flag
11388 Flags.setInReg();
11389 }
11390 if (Args[i].IsSRet)
11391 Flags.setSRet();
11392 if (Args[i].IsSwiftSelf)
11393 Flags.setSwiftSelf();
11394 if (Args[i].IsSwiftAsync)
11395 Flags.setSwiftAsync();
11396 if (Args[i].IsSwiftError)
11397 Flags.setSwiftError();
11398 if (Args[i].IsCFGuardTarget)
11399 Flags.setCFGuardTarget();
11400 if (Args[i].IsByVal)
11401 Flags.setByVal();
11402 if (Args[i].IsByRef)
11403 Flags.setByRef();
11404 if (Args[i].IsPreallocated) {
11405 Flags.setPreallocated();
11406 // Set the byval flag for CCAssignFn callbacks that don't know about
11407 // preallocated. This way we can know how many bytes we should've
11408 // allocated and how many bytes a callee cleanup function will pop. If
11409 // we port preallocated to more targets, we'll have to add custom
11410 // preallocated handling in the various CC lowering callbacks.
11411 Flags.setByVal();
11412 }
11413 if (Args[i].IsInAlloca) {
11414 Flags.setInAlloca();
11415 // Set the byval flag for CCAssignFn callbacks that don't know about
11416 // inalloca. This way we can know how many bytes we should've allocated
11417 // and how many bytes a callee cleanup function will pop. If we port
11418 // inalloca to more targets, we'll have to add custom inalloca handling
11419 // in the various CC lowering callbacks.
11420 Flags.setByVal();
11421 }
11422 Align MemAlign;
11423 if (Args[i].IsByVal || Args[i].IsInAlloca || Args[i].IsPreallocated) {
11424 unsigned FrameSize = DL.getTypeAllocSize(Ty: Args[i].IndirectType);
11425 Flags.setByValSize(FrameSize);
11426
11427 // info is not there but there are cases it cannot get right.
11428 if (auto MA = Args[i].Alignment)
11429 MemAlign = *MA;
11430 else
11431 MemAlign = getByValTypeAlignment(Ty: Args[i].IndirectType, DL);
11432 } else if (auto MA = Args[i].Alignment) {
11433 MemAlign = *MA;
11434 } else {
11435 MemAlign = OriginalAlignment;
11436 }
11437 Flags.setMemAlign(MemAlign);
11438 if (Args[i].IsNest)
11439 Flags.setNest();
11440 if (NeedsRegBlock)
11441 Flags.setInConsecutiveRegs();
11442
11443 MVT PartVT = getRegisterTypeForCallingConv(Context, CC: CLI.CallConv, VT);
11444 unsigned NumParts =
11445 getNumRegistersForCallingConv(Context, CC: CLI.CallConv, VT);
11446 SmallVector<SDValue, 4> Parts(NumParts);
11447 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
11448
11449 if (Args[i].IsSExt)
11450 ExtendKind = ISD::SIGN_EXTEND;
11451 else if (Args[i].IsZExt)
11452 ExtendKind = ISD::ZERO_EXTEND;
11453
11454 // Conservatively only handle 'returned' on non-vectors that can be lowered,
11455 // for now.
11456 if (Args[i].IsReturned && !Op.getValueType().isVector() &&
11457 CanLowerReturn) {
11458 assert((CLI.RetTy == Args[i].Ty ||
11459 (CLI.RetTy->isPointerTy() && Args[i].Ty->isPointerTy() &&
11460 CLI.RetTy->getPointerAddressSpace() ==
11461 Args[i].Ty->getPointerAddressSpace())) &&
11462 RetVTs.size() == NumValues && "unexpected use of 'returned'");
11463 // Before passing 'returned' to the target lowering code, ensure that
11464 // either the register MVT and the actual EVT are the same size or that
11465 // the return value and argument are extended in the same way; in these
11466 // cases it's safe to pass the argument register value unchanged as the
11467 // return register value (although it's at the target's option whether
11468 // to do so)
11469 // TODO: allow code generation to take advantage of partially preserved
11470 // registers rather than clobbering the entire register when the
11471 // parameter extension method is not compatible with the return
11472 // extension method
11473 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
11474 (ExtendKind != ISD::ANY_EXTEND && CLI.RetSExt == Args[i].IsSExt &&
11475 CLI.RetZExt == Args[i].IsZExt))
11476 Flags.setReturned();
11477 }
11478
11479 getCopyToParts(DAG&: CLI.DAG, DL: CLI.DL, Val: Op, Parts: &Parts[0], NumParts, PartVT, V: CLI.CB,
11480 CallConv: CLI.CallConv, ExtendKind);
11481
11482 for (unsigned j = 0; j != NumParts; ++j) {
11483 // if it isn't first piece, alignment must be 1
11484 // For scalable vectors the scalable part is currently handled
11485 // by individual targets, so we just use the known minimum size here.
11486 ISD::OutputArg MyFlags(
11487 Flags, Parts[j].getValueType().getSimpleVT(), VT, OrigArgTy, i,
11488 j * Parts[j].getValueType().getStoreSize().getKnownMinValue());
11489 if (NumParts > 1 && j == 0)
11490 MyFlags.Flags.setSplit();
11491 else if (j != 0) {
11492 MyFlags.Flags.setOrigAlign(Align(1));
11493 if (j == NumParts - 1)
11494 MyFlags.Flags.setSplitEnd();
11495 }
11496
11497 CLI.Outs.push_back(Elt: MyFlags);
11498 CLI.OutVals.push_back(Elt: Parts[j]);
11499 }
11500
11501 if (NeedsRegBlock && Value == NumValues - 1)
11502 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
11503 }
11504 }
11505
11506 SmallVector<SDValue, 4> InVals;
11507 CLI.Chain = LowerCall(CLI, InVals);
11508
11509 // Update CLI.InVals to use outside of this function.
11510 CLI.InVals = InVals;
11511
11512 // Verify that the target's LowerCall behaved as expected.
11513 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
11514 "LowerCall didn't return a valid chain!");
11515 assert((!CLI.IsTailCall || InVals.empty()) &&
11516 "LowerCall emitted a return value for a tail call!");
11517 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
11518 "LowerCall didn't emit the correct number of values!");
11519
11520 // For a tail call, the return value is merely live-out and there aren't
11521 // any nodes in the DAG representing it. Return a special value to
11522 // indicate that a tail call has been emitted and no more Instructions
11523 // should be processed in the current block.
11524 if (CLI.IsTailCall) {
11525 CLI.DAG.setRoot(CLI.Chain);
11526 return std::make_pair(x: SDValue(), y: SDValue());
11527 }
11528
11529#ifndef NDEBUG
11530 for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
11531 assert(InVals[i].getNode() && "LowerCall emitted a null value!");
11532 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
11533 "LowerCall emitted a value with the wrong type!");
11534 }
11535#endif
11536
11537 SmallVector<SDValue, 4> ReturnValues;
11538 if (!CanLowerReturn) {
11539 // The instruction result is the result of loading from the
11540 // hidden sret parameter.
11541 MVT PtrVT = getPointerTy(DL, AS: DL.getAllocaAddrSpace());
11542
11543 unsigned NumValues = RetVTs.size();
11544 ReturnValues.resize(N: NumValues);
11545 SmallVector<SDValue, 4> Chains(NumValues);
11546
11547 // An aggregate return value cannot wrap around the address space, so
11548 // offsets to its parts don't wrap either.
11549 MachineFunction &MF = CLI.DAG.getMachineFunction();
11550 Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(ObjectIdx: DemoteStackIdx);
11551 for (unsigned i = 0; i < NumValues; ++i) {
11552 SDValue Add = CLI.DAG.getMemBasePlusOffset(
11553 Base: DemoteStackSlot, Offset: CLI.DAG.getConstant(Val: Offsets[i], DL: CLI.DL, VT: PtrVT),
11554 DL: CLI.DL, Flags: SDNodeFlags::NoUnsignedWrap);
11555 SDValue L = CLI.DAG.getLoad(
11556 VT: RetVTs[i], dl: CLI.DL, Chain: CLI.Chain, Ptr: Add,
11557 PtrInfo: MachinePointerInfo::getFixedStack(MF&: CLI.DAG.getMachineFunction(),
11558 FI: DemoteStackIdx, Offset: Offsets[i]),
11559 Alignment: HiddenSRetAlign);
11560 ReturnValues[i] = L;
11561 Chains[i] = L.getValue(R: 1);
11562 }
11563
11564 CLI.Chain = CLI.DAG.getNode(Opcode: ISD::TokenFactor, DL: CLI.DL, VT: MVT::Other, Ops: Chains);
11565 } else {
11566 // Collect the legal value parts into potentially illegal values
11567 // that correspond to the original function's return values.
11568 std::optional<ISD::NodeType> AssertOp;
11569 if (CLI.RetSExt)
11570 AssertOp = ISD::AssertSext;
11571 else if (CLI.RetZExt)
11572 AssertOp = ISD::AssertZext;
11573 unsigned CurReg = 0;
11574 for (EVT VT : RetVTs) {
11575 MVT RegisterVT = getRegisterTypeForCallingConv(Context, CC: CLI.CallConv, VT);
11576 unsigned NumRegs =
11577 getNumRegistersForCallingConv(Context, CC: CLI.CallConv, VT);
11578
11579 ReturnValues.push_back(Elt: getCopyFromParts(
11580 DAG&: CLI.DAG, DL: CLI.DL, Parts: &InVals[CurReg], NumParts: NumRegs, PartVT: RegisterVT, ValueVT: VT, V: nullptr,
11581 InChain: CLI.Chain, CC: CLI.CallConv, AssertOp));
11582 CurReg += NumRegs;
11583 }
11584
11585 // For a function returning void, there is no return value. We can't create
11586 // such a node, so we just return a null return value in that case. In
11587 // that case, nothing will actually look at the value.
11588 if (ReturnValues.empty())
11589 return std::make_pair(x: SDValue(), y&: CLI.Chain);
11590 }
11591
11592 SDValue Res = CLI.DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: CLI.DL,
11593 VTList: CLI.DAG.getVTList(VTs: RetVTs), Ops: ReturnValues);
11594 return std::make_pair(x&: Res, y&: CLI.Chain);
11595}
11596
11597/// Places new result values for the node in Results (their number
11598/// and types must exactly match those of the original return values of
11599/// the node), or leaves Results empty, which indicates that the node is not
11600/// to be custom lowered after all.
11601void TargetLowering::LowerOperationWrapper(SDNode *N,
11602 SmallVectorImpl<SDValue> &Results,
11603 SelectionDAG &DAG) const {
11604 SDValue Res = LowerOperation(Op: SDValue(N, 0), DAG);
11605
11606 if (!Res.getNode())
11607 return;
11608
11609 // If the original node has one result, take the return value from
11610 // LowerOperation as is. It might not be result number 0.
11611 if (N->getNumValues() == 1) {
11612 Results.push_back(Elt: Res);
11613 return;
11614 }
11615
11616 // If the original node has multiple results, then the return node should
11617 // have the same number of results.
11618 assert((N->getNumValues() == Res->getNumValues()) &&
11619 "Lowering returned the wrong number of results!");
11620
11621 // Places new result values base on N result number.
11622 for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
11623 Results.push_back(Elt: Res.getValue(R: I));
11624}
11625
11626SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
11627 llvm_unreachable("LowerOperation not implemented for this target!");
11628}
11629
11630void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V,
11631 Register Reg,
11632 ISD::NodeType ExtendType) {
11633 SDValue Op = getNonRegisterValue(V);
11634 assert((Op.getOpcode() != ISD::CopyFromReg ||
11635 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
11636 "Copy from a reg to the same reg!");
11637 assert(!Reg.isPhysical() && "Is a physreg");
11638
11639 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11640 // If this is an InlineAsm we have to match the registers required, not the
11641 // notional registers required by the type.
11642
11643 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, V->getType(),
11644 std::nullopt); // This is not an ABI copy.
11645 SDValue Chain = DAG.getEntryNode();
11646
11647 if (ExtendType == ISD::ANY_EXTEND) {
11648 auto PreferredExtendIt = FuncInfo.PreferredExtendType.find(Val: V);
11649 if (PreferredExtendIt != FuncInfo.PreferredExtendType.end())
11650 ExtendType = PreferredExtendIt->second;
11651 }
11652 RFV.getCopyToRegs(Val: Op, DAG, dl: getCurSDLoc(), Chain, Glue: nullptr, V, PreferredExtendType: ExtendType);
11653 PendingExports.push_back(Elt: Chain);
11654}
11655
11656#include "llvm/CodeGen/SelectionDAGISel.h"
11657
11658/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
11659/// entry block, return true. This includes arguments used by switches, since
11660/// the switch may expand into multiple basic blocks.
11661static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
11662 // With FastISel active, we may be splitting blocks, so force creation
11663 // of virtual registers for all non-dead arguments.
11664 if (FastISel)
11665 return A->use_empty();
11666
11667 const BasicBlock &Entry = A->getParent()->front();
11668 for (const User *U : A->users())
11669 if (cast<Instruction>(Val: U)->getParent() != &Entry || isa<SwitchInst>(Val: U))
11670 return false; // Use not in entry block.
11671
11672 return true;
11673}
11674
11675using ArgCopyElisionMapTy =
11676 DenseMap<const Argument *,
11677 std::pair<const AllocaInst *, const StoreInst *>>;
11678
11679/// Scan the entry block of the function in FuncInfo for arguments that look
11680/// like copies into a local alloca. Record any copied arguments in
11681/// ArgCopyElisionCandidates.
11682static void
11683findArgumentCopyElisionCandidates(const DataLayout &DL,
11684 FunctionLoweringInfo *FuncInfo,
11685 ArgCopyElisionMapTy &ArgCopyElisionCandidates) {
11686 // Record the state of every static alloca used in the entry block. Argument
11687 // allocas are all used in the entry block, so we need approximately as many
11688 // entries as we have arguments.
11689 enum StaticAllocaInfo { Unknown, Clobbered, Elidable };
11690 SmallDenseMap<const AllocaInst *, StaticAllocaInfo, 8> StaticAllocas;
11691 unsigned NumArgs = FuncInfo->Fn->arg_size();
11692 StaticAllocas.reserve(NumEntries: NumArgs * 2);
11693
11694 auto GetInfoIfStaticAlloca = [&](const Value *V) -> StaticAllocaInfo * {
11695 if (!V)
11696 return nullptr;
11697 V = V->stripPointerCasts();
11698 const auto *AI = dyn_cast<AllocaInst>(Val: V);
11699 if (!AI || !AI->isStaticAlloca() || !FuncInfo->StaticAllocaMap.count(Val: AI))
11700 return nullptr;
11701 auto Iter = StaticAllocas.insert(KV: {AI, Unknown});
11702 return &Iter.first->second;
11703 };
11704
11705 // Look for stores of arguments to static allocas. Look through bitcasts and
11706 // GEPs to handle type coercions, as long as the alloca is fully initialized
11707 // by the store. Any non-store use of an alloca escapes it and any subsequent
11708 // unanalyzed store might write it.
11709 // FIXME: Handle structs initialized with multiple stores.
11710 for (const Instruction &I : FuncInfo->Fn->getEntryBlock()) {
11711 // Look for stores, and handle non-store uses conservatively.
11712 const auto *SI = dyn_cast<StoreInst>(Val: &I);
11713 if (!SI) {
11714 // We will look through cast uses, so ignore them completely.
11715 if (I.isCast())
11716 continue;
11717 // Ignore debug info and pseudo op intrinsics, they don't escape or store
11718 // to allocas.
11719 if (I.isDebugOrPseudoInst())
11720 continue;
11721 // This is an unknown instruction. Assume it escapes or writes to all
11722 // static alloca operands.
11723 for (const Use &U : I.operands()) {
11724 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(U))
11725 *Info = StaticAllocaInfo::Clobbered;
11726 }
11727 continue;
11728 }
11729
11730 // If the stored value is a static alloca, mark it as escaped.
11731 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(SI->getValueOperand()))
11732 *Info = StaticAllocaInfo::Clobbered;
11733
11734 // Check if the destination is a static alloca.
11735 const Value *Dst = SI->getPointerOperand()->stripPointerCasts();
11736 StaticAllocaInfo *Info = GetInfoIfStaticAlloca(Dst);
11737 if (!Info)
11738 continue;
11739 const AllocaInst *AI = cast<AllocaInst>(Val: Dst);
11740
11741 // Skip allocas that have been initialized or clobbered.
11742 if (*Info != StaticAllocaInfo::Unknown)
11743 continue;
11744
11745 // Check if the stored value is an argument, and that this store fully
11746 // initializes the alloca.
11747 // If the argument type has padding bits we can't directly forward a pointer
11748 // as the upper bits may contain garbage.
11749 // Don't elide copies from the same argument twice.
11750 const Value *Val = SI->getValueOperand()->stripPointerCasts();
11751 const auto *Arg = dyn_cast<Argument>(Val);
11752 std::optional<TypeSize> AllocaSize = AI->getAllocationSize(DL);
11753 if (!Arg || Arg->hasPassPointeeByValueCopyAttr() ||
11754 Arg->getType()->isEmptyTy() || !AllocaSize ||
11755 DL.getTypeStoreSize(Ty: Arg->getType()) != *AllocaSize ||
11756 !DL.typeSizeEqualsStoreSize(Ty: Arg->getType()) ||
11757 ArgCopyElisionCandidates.count(Val: Arg)) {
11758 *Info = StaticAllocaInfo::Clobbered;
11759 continue;
11760 }
11761
11762 LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AI
11763 << '\n');
11764
11765 // Mark this alloca and store for argument copy elision.
11766 *Info = StaticAllocaInfo::Elidable;
11767 ArgCopyElisionCandidates.insert(KV: {Arg, {AI, SI}});
11768
11769 // Stop scanning if we've seen all arguments. This will happen early in -O0
11770 // builds, which is useful, because -O0 builds have large entry blocks and
11771 // many allocas.
11772 if (ArgCopyElisionCandidates.size() == NumArgs)
11773 break;
11774 }
11775}
11776
11777/// Try to elide argument copies from memory into a local alloca. Succeeds if
11778/// ArgVal is a load from a suitable fixed stack object.
11779static void tryToElideArgumentCopy(
11780 FunctionLoweringInfo &FuncInfo, SmallVectorImpl<SDValue> &Chains,
11781 DenseMap<int, int> &ArgCopyElisionFrameIndexMap,
11782 SmallPtrSetImpl<const Instruction *> &ElidedArgCopyInstrs,
11783 ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg,
11784 ArrayRef<SDValue> ArgVals, bool &ArgHasUses) {
11785 // Check if this is a load from a fixed stack object.
11786 auto *LNode = dyn_cast<LoadSDNode>(Val: ArgVals[0]);
11787 if (!LNode)
11788 return;
11789 auto *FINode = dyn_cast<FrameIndexSDNode>(Val: LNode->getBasePtr().getNode());
11790 if (!FINode)
11791 return;
11792
11793 // Check that the fixed stack object is the right size and alignment.
11794 // Look at the alignment that the user wrote on the alloca instead of looking
11795 // at the stack object.
11796 auto ArgCopyIter = ArgCopyElisionCandidates.find(Val: &Arg);
11797 assert(ArgCopyIter != ArgCopyElisionCandidates.end());
11798 const AllocaInst *AI = ArgCopyIter->second.first;
11799 int FixedIndex = FINode->getIndex();
11800 int &AllocaIndex = FuncInfo.StaticAllocaMap[AI];
11801 int OldIndex = AllocaIndex;
11802 MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
11803 if (MFI.getObjectSize(ObjectIdx: FixedIndex) != MFI.getObjectSize(ObjectIdx: OldIndex)) {
11804 LLVM_DEBUG(
11805 dbgs() << " argument copy elision failed due to bad fixed stack "
11806 "object size\n");
11807 return;
11808 }
11809 Align RequiredAlignment = AI->getAlign();
11810 if (MFI.getObjectAlign(ObjectIdx: FixedIndex) < RequiredAlignment) {
11811 LLVM_DEBUG(dbgs() << " argument copy elision failed: alignment of alloca "
11812 "greater than stack argument alignment ("
11813 << DebugStr(RequiredAlignment) << " vs "
11814 << DebugStr(MFI.getObjectAlign(FixedIndex)) << ")\n");
11815 return;
11816 }
11817
11818 // Perform the elision. Delete the old stack object and replace its only use
11819 // in the variable info map. Mark the stack object as mutable and aliased.
11820 LLVM_DEBUG({
11821 dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n'
11822 << " Replacing frame index " << OldIndex << " with " << FixedIndex
11823 << '\n';
11824 });
11825 MFI.RemoveStackObject(ObjectIdx: OldIndex);
11826 MFI.setIsImmutableObjectIndex(ObjectIdx: FixedIndex, IsImmutable: false);
11827 MFI.setIsAliasedObjectIndex(ObjectIdx: FixedIndex, IsAliased: true);
11828 AllocaIndex = FixedIndex;
11829 ArgCopyElisionFrameIndexMap.insert(KV: {OldIndex, FixedIndex});
11830 for (SDValue ArgVal : ArgVals)
11831 Chains.push_back(Elt: ArgVal.getValue(R: 1));
11832
11833 // Avoid emitting code for the store implementing the copy.
11834 const StoreInst *SI = ArgCopyIter->second.second;
11835 ElidedArgCopyInstrs.insert(Ptr: SI);
11836
11837 // Check for uses of the argument again so that we can avoid exporting ArgVal
11838 // if it is't used by anything other than the store.
11839 for (const Value *U : Arg.users()) {
11840 if (U != SI) {
11841 ArgHasUses = true;
11842 break;
11843 }
11844 }
11845}
11846
11847void SelectionDAGISel::LowerArguments(const Function &F) {
11848 SelectionDAG &DAG = SDB->DAG;
11849 SDLoc dl = SDB->getCurSDLoc();
11850 const DataLayout &DL = DAG.getDataLayout();
11851 SmallVector<ISD::InputArg, 16> Ins;
11852
11853 // In Naked functions we aren't going to save any registers.
11854 if (F.hasFnAttribute(Kind: Attribute::Naked))
11855 return;
11856
11857 if (!FuncInfo->CanLowerReturn) {
11858 // Put in an sret pointer parameter before all the other parameters.
11859 MVT ValueVT = TLI->getPointerTy(DL, AS: DL.getAllocaAddrSpace());
11860
11861 ISD::ArgFlagsTy Flags;
11862 Flags.setSRet();
11863 MVT RegisterVT = TLI->getRegisterType(Context&: *DAG.getContext(), VT: ValueVT);
11864 ISD::InputArg RetArg(Flags, RegisterVT, ValueVT, F.getReturnType(), true,
11865 ISD::InputArg::NoArgIndex, 0);
11866 Ins.push_back(Elt: RetArg);
11867 }
11868
11869 // Look for stores of arguments to static allocas. Mark such arguments with a
11870 // flag to ask the target to give us the memory location of that argument if
11871 // available.
11872 ArgCopyElisionMapTy ArgCopyElisionCandidates;
11873 findArgumentCopyElisionCandidates(DL, FuncInfo: FuncInfo.get(),
11874 ArgCopyElisionCandidates);
11875
11876 // Set up the incoming argument description vector.
11877 for (const Argument &Arg : F.args()) {
11878 unsigned ArgNo = Arg.getArgNo();
11879 SmallVector<Type *, 4> Types;
11880 ComputeValueTypes(DL: DAG.getDataLayout(), Ty: Arg.getType(), Types);
11881 bool isArgValueUsed = !Arg.use_empty();
11882 Type *FinalType = Arg.getType();
11883 if (Arg.hasAttribute(Kind: Attribute::ByVal))
11884 FinalType = Arg.getParamByValType();
11885 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
11886 Ty: FinalType, CallConv: F.getCallingConv(), isVarArg: F.isVarArg(), DL);
11887 for (unsigned Value = 0, NumValues = Types.size(); Value != NumValues;
11888 ++Value) {
11889 Type *ArgTy = Types[Value];
11890 EVT VT = TLI->getValueType(DL, Ty: ArgTy);
11891 ISD::ArgFlagsTy Flags;
11892
11893 if (ArgTy->isPointerTy()) {
11894 Flags.setPointer();
11895 Flags.setPointerAddrSpace(cast<PointerType>(Val: ArgTy)->getAddressSpace());
11896 }
11897 if (Arg.hasAttribute(Kind: Attribute::ZExt))
11898 Flags.setZExt();
11899 if (Arg.hasAttribute(Kind: Attribute::SExt))
11900 Flags.setSExt();
11901 if (Arg.hasAttribute(Kind: Attribute::InReg)) {
11902 // If we are using vectorcall calling convention, a structure that is
11903 // passed InReg - is surely an HVA
11904 if (F.getCallingConv() == CallingConv::X86_VectorCall &&
11905 isa<StructType>(Val: Arg.getType())) {
11906 // The first value of a structure is marked
11907 if (0 == Value)
11908 Flags.setHvaStart();
11909 Flags.setHva();
11910 }
11911 // Set InReg Flag
11912 Flags.setInReg();
11913 }
11914 if (Arg.hasAttribute(Kind: Attribute::StructRet))
11915 Flags.setSRet();
11916 if (Arg.hasAttribute(Kind: Attribute::SwiftSelf))
11917 Flags.setSwiftSelf();
11918 if (Arg.hasAttribute(Kind: Attribute::SwiftAsync))
11919 Flags.setSwiftAsync();
11920 if (Arg.hasAttribute(Kind: Attribute::SwiftError))
11921 Flags.setSwiftError();
11922 if (Arg.hasAttribute(Kind: Attribute::ByVal))
11923 Flags.setByVal();
11924 if (Arg.hasAttribute(Kind: Attribute::ByRef))
11925 Flags.setByRef();
11926 if (Arg.hasAttribute(Kind: Attribute::InAlloca)) {
11927 Flags.setInAlloca();
11928 // Set the byval flag for CCAssignFn callbacks that don't know about
11929 // inalloca. This way we can know how many bytes we should've allocated
11930 // and how many bytes a callee cleanup function will pop. If we port
11931 // inalloca to more targets, we'll have to add custom inalloca handling
11932 // in the various CC lowering callbacks.
11933 Flags.setByVal();
11934 }
11935 if (Arg.hasAttribute(Kind: Attribute::Preallocated)) {
11936 Flags.setPreallocated();
11937 // Set the byval flag for CCAssignFn callbacks that don't know about
11938 // preallocated. This way we can know how many bytes we should've
11939 // allocated and how many bytes a callee cleanup function will pop. If
11940 // we port preallocated to more targets, we'll have to add custom
11941 // preallocated handling in the various CC lowering callbacks.
11942 Flags.setByVal();
11943 }
11944
11945 // Certain targets (such as MIPS), may have a different ABI alignment
11946 // for a type depending on the context. Give the target a chance to
11947 // specify the alignment it wants.
11948 const Align OriginalAlignment(
11949 TLI->getABIAlignmentForCallingConv(ArgTy, DL));
11950 Flags.setOrigAlign(OriginalAlignment);
11951
11952 Align MemAlign;
11953 Type *ArgMemTy = nullptr;
11954 if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated() ||
11955 Flags.isByRef()) {
11956 if (!ArgMemTy)
11957 ArgMemTy = Arg.getPointeeInMemoryValueType();
11958
11959 uint64_t MemSize = DL.getTypeAllocSize(Ty: ArgMemTy);
11960
11961 // For in-memory arguments, size and alignment should be passed from FE.
11962 // BE will guess if this info is not there but there are cases it cannot
11963 // get right.
11964 if (auto ParamAlign = Arg.getParamStackAlign())
11965 MemAlign = *ParamAlign;
11966 else if ((ParamAlign = Arg.getParamAlign()))
11967 MemAlign = *ParamAlign;
11968 else
11969 MemAlign = TLI->getByValTypeAlignment(Ty: ArgMemTy, DL);
11970 if (Flags.isByRef())
11971 Flags.setByRefSize(MemSize);
11972 else
11973 Flags.setByValSize(MemSize);
11974 } else if (auto ParamAlign = Arg.getParamStackAlign()) {
11975 MemAlign = *ParamAlign;
11976 } else {
11977 MemAlign = OriginalAlignment;
11978 }
11979 Flags.setMemAlign(MemAlign);
11980
11981 if (Arg.hasAttribute(Kind: Attribute::Nest))
11982 Flags.setNest();
11983 if (NeedsRegBlock)
11984 Flags.setInConsecutiveRegs();
11985 if (ArgCopyElisionCandidates.count(Val: &Arg))
11986 Flags.setCopyElisionCandidate();
11987 if (Arg.hasAttribute(Kind: Attribute::Returned))
11988 Flags.setReturned();
11989
11990 MVT RegisterVT = TLI->getRegisterTypeForCallingConv(
11991 Context&: *CurDAG->getContext(), CC: F.getCallingConv(), VT);
11992 unsigned NumRegs = TLI->getNumRegistersForCallingConv(
11993 Context&: *CurDAG->getContext(), CC: F.getCallingConv(), VT);
11994 for (unsigned i = 0; i != NumRegs; ++i) {
11995 // For scalable vectors, use the minimum size; individual targets
11996 // are responsible for handling scalable vector arguments and
11997 // return values.
11998 ISD::InputArg MyFlags(
11999 Flags, RegisterVT, VT, ArgTy, isArgValueUsed, ArgNo,
12000 i * RegisterVT.getStoreSize().getKnownMinValue());
12001 if (NumRegs > 1 && i == 0)
12002 MyFlags.Flags.setSplit();
12003 // if it isn't first piece, alignment must be 1
12004 else if (i > 0) {
12005 MyFlags.Flags.setOrigAlign(Align(1));
12006 if (i == NumRegs - 1)
12007 MyFlags.Flags.setSplitEnd();
12008 }
12009 Ins.push_back(Elt: MyFlags);
12010 }
12011 if (NeedsRegBlock && Value == NumValues - 1)
12012 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
12013 }
12014 }
12015
12016 // Call the target to set up the argument values.
12017 SmallVector<SDValue, 8> InVals;
12018 SDValue NewRoot = TLI->LowerFormalArguments(
12019 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
12020
12021 // Verify that the target's LowerFormalArguments behaved as expected.
12022 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
12023 "LowerFormalArguments didn't return a valid chain!");
12024 assert(InVals.size() == Ins.size() &&
12025 "LowerFormalArguments didn't emit the correct number of values!");
12026 LLVM_DEBUG({
12027 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
12028 assert(InVals[i].getNode() &&
12029 "LowerFormalArguments emitted a null value!");
12030 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
12031 "LowerFormalArguments emitted a value with the wrong type!");
12032 }
12033 });
12034
12035 // Update the DAG with the new chain value resulting from argument lowering.
12036 DAG.setRoot(NewRoot);
12037
12038 // Set up the argument values.
12039 unsigned i = 0;
12040 if (!FuncInfo->CanLowerReturn) {
12041 // Create a virtual register for the sret pointer, and put in a copy
12042 // from the sret argument into it.
12043 MVT VT = TLI->getPointerTy(DL, AS: DL.getAllocaAddrSpace());
12044 MVT RegVT = TLI->getRegisterType(Context&: *CurDAG->getContext(), VT);
12045 std::optional<ISD::NodeType> AssertOp;
12046 SDValue ArgValue =
12047 getCopyFromParts(DAG, DL: dl, Parts: &InVals[0], NumParts: 1, PartVT: RegVT, ValueVT: VT, V: nullptr, InChain: NewRoot,
12048 CC: F.getCallingConv(), AssertOp);
12049
12050 MachineFunction& MF = SDB->DAG.getMachineFunction();
12051 MachineRegisterInfo& RegInfo = MF.getRegInfo();
12052 Register SRetReg =
12053 RegInfo.createVirtualRegister(RegClass: TLI->getRegClassFor(VT: RegVT));
12054 FuncInfo->DemoteRegister = SRetReg;
12055 NewRoot =
12056 SDB->DAG.getCopyToReg(Chain: NewRoot, dl: SDB->getCurSDLoc(), Reg: SRetReg, N: ArgValue);
12057 DAG.setRoot(NewRoot);
12058
12059 // i indexes lowered arguments. Bump it past the hidden sret argument.
12060 ++i;
12061 }
12062
12063 SmallVector<SDValue, 4> Chains;
12064 DenseMap<int, int> ArgCopyElisionFrameIndexMap;
12065 for (const Argument &Arg : F.args()) {
12066 SmallVector<SDValue, 4> ArgValues;
12067 SmallVector<EVT, 4> ValueVTs;
12068 ComputeValueVTs(TLI: *TLI, DL: DAG.getDataLayout(), Ty: Arg.getType(), ValueVTs);
12069 unsigned NumValues = ValueVTs.size();
12070 if (NumValues == 0)
12071 continue;
12072
12073 bool ArgHasUses = !Arg.use_empty();
12074
12075 // Elide the copying store if the target loaded this argument from a
12076 // suitable fixed stack object.
12077 if (Ins[i].Flags.isCopyElisionCandidate()) {
12078 unsigned NumParts = 0;
12079 for (EVT VT : ValueVTs)
12080 NumParts += TLI->getNumRegistersForCallingConv(Context&: *CurDAG->getContext(),
12081 CC: F.getCallingConv(), VT);
12082
12083 tryToElideArgumentCopy(FuncInfo&: *FuncInfo, Chains, ArgCopyElisionFrameIndexMap,
12084 ElidedArgCopyInstrs, ArgCopyElisionCandidates, Arg,
12085 ArgVals: ArrayRef(&InVals[i], NumParts), ArgHasUses);
12086 }
12087
12088 // If this argument is unused then remember its value. It is used to generate
12089 // debugging information.
12090 bool isSwiftErrorArg =
12091 TLI->supportSwiftError() &&
12092 Arg.hasAttribute(Kind: Attribute::SwiftError);
12093 if (!ArgHasUses && !isSwiftErrorArg) {
12094 SDB->setUnusedArgValue(V: &Arg, NewN: InVals[i]);
12095
12096 // Also remember any frame index for use in FastISel.
12097 if (FrameIndexSDNode *FI =
12098 dyn_cast<FrameIndexSDNode>(Val: InVals[i].getNode()))
12099 FuncInfo->setArgumentFrameIndex(A: &Arg, FI: FI->getIndex());
12100 }
12101
12102 for (unsigned Val = 0; Val != NumValues; ++Val) {
12103 EVT VT = ValueVTs[Val];
12104 MVT PartVT = TLI->getRegisterTypeForCallingConv(Context&: *CurDAG->getContext(),
12105 CC: F.getCallingConv(), VT);
12106 unsigned NumParts = TLI->getNumRegistersForCallingConv(
12107 Context&: *CurDAG->getContext(), CC: F.getCallingConv(), VT);
12108
12109 // Even an apparent 'unused' swifterror argument needs to be returned. So
12110 // we do generate a copy for it that can be used on return from the
12111 // function.
12112 if (ArgHasUses || isSwiftErrorArg) {
12113 std::optional<ISD::NodeType> AssertOp;
12114 if (Arg.hasAttribute(Kind: Attribute::SExt))
12115 AssertOp = ISD::AssertSext;
12116 else if (Arg.hasAttribute(Kind: Attribute::ZExt))
12117 AssertOp = ISD::AssertZext;
12118
12119 SDValue OutVal =
12120 getCopyFromParts(DAG, DL: dl, Parts: &InVals[i], NumParts, PartVT, ValueVT: VT, V: nullptr,
12121 InChain: NewRoot, CC: F.getCallingConv(), AssertOp);
12122
12123 FPClassTest NoFPClass = Arg.getNoFPClass();
12124 if (NoFPClass != fcNone) {
12125 SDValue SDNoFPClass = DAG.getTargetConstant(
12126 Val: static_cast<uint64_t>(NoFPClass), DL: dl, VT: MVT::i32);
12127 OutVal = DAG.getNode(Opcode: ISD::AssertNoFPClass, DL: dl, VT: OutVal.getValueType(),
12128 N1: OutVal, N2: SDNoFPClass);
12129 }
12130 ArgValues.push_back(Elt: OutVal);
12131 }
12132
12133 i += NumParts;
12134 }
12135
12136 // We don't need to do anything else for unused arguments.
12137 if (ArgValues.empty())
12138 continue;
12139
12140 // Note down frame index.
12141 if (FrameIndexSDNode *FI =
12142 dyn_cast<FrameIndexSDNode>(Val: ArgValues[0].getNode()))
12143 FuncInfo->setArgumentFrameIndex(A: &Arg, FI: FI->getIndex());
12144
12145 SDValue Res = DAG.getMergeValues(Ops: ArrayRef(ArgValues.data(), NumValues),
12146 dl: SDB->getCurSDLoc());
12147
12148 SDB->setValue(V: &Arg, NewN: Res);
12149 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
12150 // We want to associate the argument with the frame index, among
12151 // involved operands, that correspond to the lowest address. The
12152 // getCopyFromParts function, called earlier, is swapping the order of
12153 // the operands to BUILD_PAIR depending on endianness. The result of
12154 // that swapping is that the least significant bits of the argument will
12155 // be in the first operand of the BUILD_PAIR node, and the most
12156 // significant bits will be in the second operand.
12157 unsigned LowAddressOp = DAG.getDataLayout().isBigEndian() ? 1 : 0;
12158 if (LoadSDNode *LNode =
12159 dyn_cast<LoadSDNode>(Val: Res.getOperand(i: LowAddressOp).getNode()))
12160 if (FrameIndexSDNode *FI =
12161 dyn_cast<FrameIndexSDNode>(Val: LNode->getBasePtr().getNode()))
12162 FuncInfo->setArgumentFrameIndex(A: &Arg, FI: FI->getIndex());
12163 }
12164
12165 // Analyses past this point are naive and don't expect an assertion.
12166 if (Res.getOpcode() == ISD::AssertZext)
12167 Res = Res.getOperand(i: 0);
12168
12169 // Update the SwiftErrorVRegDefMap.
12170 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) {
12171 Register Reg = cast<RegisterSDNode>(Val: Res.getOperand(i: 1))->getReg();
12172 if (Reg.isVirtual())
12173 SwiftError->setCurrentVReg(MBB: FuncInfo->MBB, SwiftError->getFunctionArg(),
12174 Reg);
12175 }
12176
12177 // If this argument is live outside of the entry block, insert a copy from
12178 // wherever we got it to the vreg that other BB's will reference it as.
12179 if (Res.getOpcode() == ISD::CopyFromReg) {
12180 // If we can, though, try to skip creating an unnecessary vreg.
12181 // FIXME: This isn't very clean... it would be nice to make this more
12182 // general.
12183 Register Reg = cast<RegisterSDNode>(Val: Res.getOperand(i: 1))->getReg();
12184 if (Reg.isVirtual()) {
12185 FuncInfo->ValueMap[&Arg] = Reg;
12186 continue;
12187 }
12188 }
12189 if (!isOnlyUsedInEntryBlock(A: &Arg, FastISel: TM.Options.EnableFastISel)) {
12190 FuncInfo->InitializeRegForValue(V: &Arg);
12191 SDB->CopyToExportRegsIfNeeded(V: &Arg);
12192 }
12193 }
12194
12195 if (!Chains.empty()) {
12196 Chains.push_back(Elt: NewRoot);
12197 NewRoot = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: Chains);
12198 }
12199
12200 DAG.setRoot(NewRoot);
12201
12202 assert(i == InVals.size() && "Argument register count mismatch!");
12203
12204 // If any argument copy elisions occurred and we have debug info, update the
12205 // stale frame indices used in the dbg.declare variable info table.
12206 if (!ArgCopyElisionFrameIndexMap.empty()) {
12207 for (MachineFunction::VariableDbgInfo &VI :
12208 MF->getInStackSlotVariableDbgInfo()) {
12209 auto I = ArgCopyElisionFrameIndexMap.find(Val: VI.getStackSlot());
12210 if (I != ArgCopyElisionFrameIndexMap.end())
12211 VI.updateStackSlot(NewSlot: I->second);
12212 }
12213 }
12214
12215 // Finally, if the target has anything special to do, allow it to do so.
12216 emitFunctionEntryCode();
12217}
12218
12219/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
12220/// ensure constants are generated when needed. Remember the virtual registers
12221/// that need to be added to the Machine PHI nodes as input. We cannot just
12222/// directly add them, because expansion might result in multiple MBB's for one
12223/// BB. As such, the start of the BB might correspond to a different MBB than
12224/// the end.
12225void
12226SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
12227 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12228
12229 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
12230
12231 // Check PHI nodes in successors that expect a value to be available from this
12232 // block.
12233 for (const BasicBlock *SuccBB : successors(I: LLVMBB->getTerminator())) {
12234 if (!isa<PHINode>(Val: SuccBB->begin())) continue;
12235 MachineBasicBlock *SuccMBB = FuncInfo.getMBB(BB: SuccBB);
12236
12237 // If this terminator has multiple identical successors (common for
12238 // switches), only handle each succ once.
12239 if (!SuccsHandled.insert(Ptr: SuccMBB).second)
12240 continue;
12241
12242 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
12243
12244 // At this point we know that there is a 1-1 correspondence between LLVM PHI
12245 // nodes and Machine PHI nodes, but the incoming operands have not been
12246 // emitted yet.
12247 for (const PHINode &PN : SuccBB->phis()) {
12248 // Ignore dead phi's.
12249 if (PN.use_empty())
12250 continue;
12251
12252 // Skip empty types
12253 if (PN.getType()->isEmptyTy())
12254 continue;
12255
12256 Register Reg;
12257 const Value *PHIOp = PN.getIncomingValueForBlock(BB: LLVMBB);
12258
12259 if (const auto *C = dyn_cast<Constant>(Val: PHIOp)) {
12260 Register &RegOut = ConstantsOut[C];
12261 if (!RegOut) {
12262 RegOut = FuncInfo.CreateRegs(V: &PN);
12263 // We need to zero/sign extend ConstantInt phi operands to match
12264 // assumptions in FunctionLoweringInfo::ComputePHILiveOutRegInfo.
12265 ISD::NodeType ExtendType = ISD::ANY_EXTEND;
12266 if (auto *CI = dyn_cast<ConstantInt>(Val: C))
12267 ExtendType = TLI.signExtendConstant(C: CI) ? ISD::SIGN_EXTEND
12268 : ISD::ZERO_EXTEND;
12269 CopyValueToVirtualRegister(V: C, Reg: RegOut, ExtendType);
12270 }
12271 Reg = RegOut;
12272 } else {
12273 DenseMap<const Value *, Register>::iterator I =
12274 FuncInfo.ValueMap.find(Val: PHIOp);
12275 if (I != FuncInfo.ValueMap.end())
12276 Reg = I->second;
12277 else {
12278 assert(isa<AllocaInst>(PHIOp) &&
12279 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
12280 "Didn't codegen value into a register!??");
12281 Reg = FuncInfo.CreateRegs(V: &PN);
12282 CopyValueToVirtualRegister(V: PHIOp, Reg);
12283 }
12284 }
12285
12286 // Remember that this register needs to added to the machine PHI node as
12287 // the input for this MBB.
12288 SmallVector<EVT, 4> ValueVTs;
12289 ComputeValueVTs(TLI, DL: DAG.getDataLayout(), Ty: PN.getType(), ValueVTs);
12290 for (EVT VT : ValueVTs) {
12291 const unsigned NumRegisters = TLI.getNumRegisters(Context&: *DAG.getContext(), VT);
12292 for (unsigned i = 0; i != NumRegisters; ++i)
12293 FuncInfo.PHINodesToUpdate.emplace_back(args: &*MBBI++, args: Reg + i);
12294 Reg += NumRegisters;
12295 }
12296 }
12297 }
12298
12299 ConstantsOut.clear();
12300}
12301
12302MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
12303 MachineFunction::iterator I(MBB);
12304 if (++I == FuncInfo.MF->end())
12305 return nullptr;
12306 return &*I;
12307}
12308
12309/// During lowering new call nodes can be created (such as memset, etc.).
12310/// Those will become new roots of the current DAG, but complications arise
12311/// when they are tail calls. In such cases, the call lowering will update
12312/// the root, but the builder still needs to know that a tail call has been
12313/// lowered in order to avoid generating an additional return.
12314void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
12315 // If the node is null, we do have a tail call.
12316 if (MaybeTC.getNode() != nullptr)
12317 DAG.setRoot(MaybeTC);
12318 else
12319 HasTailCall = true;
12320}
12321
12322void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
12323 MachineBasicBlock *SwitchMBB,
12324 MachineBasicBlock *DefaultMBB) {
12325 MachineFunction *CurMF = FuncInfo.MF;
12326 MachineBasicBlock *NextMBB = nullptr;
12327 MachineFunction::iterator BBI(W.MBB);
12328 if (++BBI != FuncInfo.MF->end())
12329 NextMBB = &*BBI;
12330
12331 unsigned Size = W.LastCluster - W.FirstCluster + 1;
12332
12333 BranchProbabilityInfo *BPI = FuncInfo.BPI;
12334
12335 if (Size == 2 && W.MBB == SwitchMBB) {
12336 // If any two of the cases has the same destination, and if one value
12337 // is the same as the other, but has one bit unset that the other has set,
12338 // use bit manipulation to do two compares at once. For example:
12339 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
12340 // TODO: This could be extended to merge any 2 cases in switches with 3
12341 // cases.
12342 // TODO: Handle cases where W.CaseBB != SwitchBB.
12343 CaseCluster &Small = *W.FirstCluster;
12344 CaseCluster &Big = *W.LastCluster;
12345
12346 if (Small.Low == Small.High && Big.Low == Big.High &&
12347 Small.MBB == Big.MBB) {
12348 const APInt &SmallValue = Small.Low->getValue();
12349 const APInt &BigValue = Big.Low->getValue();
12350
12351 // Check that there is only one bit different.
12352 APInt CommonBit = BigValue ^ SmallValue;
12353 if (CommonBit.isPowerOf2()) {
12354 SDValue CondLHS = getValue(V: Cond);
12355 EVT VT = CondLHS.getValueType();
12356 SDLoc DL = getCurSDLoc();
12357
12358 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: CondLHS,
12359 N2: DAG.getConstant(Val: CommonBit, DL, VT));
12360 SDValue Cond = DAG.getSetCC(
12361 DL, VT: MVT::i1, LHS: Or, RHS: DAG.getConstant(Val: BigValue | SmallValue, DL, VT),
12362 Cond: ISD::SETEQ);
12363
12364 // Update successor info.
12365 // Both Small and Big will jump to Small.BB, so we sum up the
12366 // probabilities.
12367 addSuccessorWithProb(Src: SwitchMBB, Dst: Small.MBB, Prob: Small.Prob + Big.Prob);
12368 if (BPI)
12369 addSuccessorWithProb(
12370 Src: SwitchMBB, Dst: DefaultMBB,
12371 // The default destination is the first successor in IR.
12372 Prob: BPI->getEdgeProbability(Src: SwitchMBB->getBasicBlock(), IndexInSuccessors: (unsigned)0));
12373 else
12374 addSuccessorWithProb(Src: SwitchMBB, Dst: DefaultMBB);
12375
12376 // Insert the true branch.
12377 SDValue BrCond =
12378 DAG.getNode(Opcode: ISD::BRCOND, DL, VT: MVT::Other, N1: getControlRoot(), N2: Cond,
12379 N3: DAG.getBasicBlock(MBB: Small.MBB));
12380 // Insert the false branch.
12381 BrCond = DAG.getNode(Opcode: ISD::BR, DL, VT: MVT::Other, N1: BrCond,
12382 N2: DAG.getBasicBlock(MBB: DefaultMBB));
12383
12384 DAG.setRoot(BrCond);
12385 return;
12386 }
12387 }
12388 }
12389
12390 if (TM.getOptLevel() != CodeGenOptLevel::None) {
12391 // Here, we order cases by probability so the most likely case will be
12392 // checked first. However, two clusters can have the same probability in
12393 // which case their relative ordering is non-deterministic. So we use Low
12394 // as a tie-breaker as clusters are guaranteed to never overlap.
12395 llvm::sort(Start: W.FirstCluster, End: W.LastCluster + 1,
12396 Comp: [](const CaseCluster &a, const CaseCluster &b) {
12397 return a.Prob != b.Prob ?
12398 a.Prob > b.Prob :
12399 a.Low->getValue().slt(RHS: b.Low->getValue());
12400 });
12401
12402 // Rearrange the case blocks so that the last one falls through if possible
12403 // without changing the order of probabilities.
12404 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
12405 --I;
12406 if (I->Prob > W.LastCluster->Prob)
12407 break;
12408 if (I->Kind == CC_Range && I->MBB == NextMBB) {
12409 std::swap(a&: *I, b&: *W.LastCluster);
12410 break;
12411 }
12412 }
12413 }
12414
12415 // Compute total probability.
12416 BranchProbability DefaultProb = W.DefaultProb;
12417 BranchProbability UnhandledProbs = DefaultProb;
12418 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
12419 UnhandledProbs += I->Prob;
12420
12421 MachineBasicBlock *CurMBB = W.MBB;
12422 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
12423 bool FallthroughUnreachable = false;
12424 MachineBasicBlock *Fallthrough;
12425 if (I == W.LastCluster) {
12426 // For the last cluster, fall through to the default destination.
12427 Fallthrough = DefaultMBB;
12428 FallthroughUnreachable = isa<UnreachableInst>(
12429 Val: DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
12430 } else {
12431 Fallthrough = CurMF->CreateMachineBasicBlock(BB: CurMBB->getBasicBlock());
12432 CurMF->insert(MBBI: BBI, MBB: Fallthrough);
12433 // Put Cond in a virtual register to make it available from the new blocks.
12434 ExportFromCurrentBlock(V: Cond);
12435 }
12436 UnhandledProbs -= I->Prob;
12437
12438 switch (I->Kind) {
12439 case CC_JumpTable: {
12440 // FIXME: Optimize away range check based on pivot comparisons.
12441 JumpTableHeader *JTH = &SL->JTCases[I->JTCasesIndex].first;
12442 SwitchCG::JumpTable *JT = &SL->JTCases[I->JTCasesIndex].second;
12443
12444 // The jump block hasn't been inserted yet; insert it here.
12445 MachineBasicBlock *JumpMBB = JT->MBB;
12446 CurMF->insert(MBBI: BBI, MBB: JumpMBB);
12447
12448 auto JumpProb = I->Prob;
12449 auto FallthroughProb = UnhandledProbs;
12450
12451 // If the default statement is a target of the jump table, we evenly
12452 // distribute the default probability to successors of CurMBB. Also
12453 // update the probability on the edge from JumpMBB to Fallthrough.
12454 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
12455 SE = JumpMBB->succ_end();
12456 SI != SE; ++SI) {
12457 if (*SI == DefaultMBB) {
12458 JumpProb += DefaultProb / 2;
12459 FallthroughProb -= DefaultProb / 2;
12460 JumpMBB->setSuccProbability(I: SI, Prob: DefaultProb / 2);
12461 JumpMBB->normalizeSuccProbs();
12462 break;
12463 }
12464 }
12465
12466 // If the default clause is unreachable, propagate that knowledge into
12467 // JTH->FallthroughUnreachable which will use it to suppress the range
12468 // check.
12469 //
12470 // However, don't do this if we're doing branch target enforcement,
12471 // because a table branch _without_ a range check can be a tempting JOP
12472 // gadget - out-of-bounds inputs that are impossible in correct
12473 // execution become possible again if an attacker can influence the
12474 // control flow. So if an attacker doesn't already have a BTI bypass
12475 // available, we don't want them to be able to get one out of this
12476 // table branch.
12477 if (FallthroughUnreachable) {
12478 Function &CurFunc = CurMF->getFunction();
12479 if (!CurFunc.hasFnAttribute(Kind: "branch-target-enforcement"))
12480 JTH->FallthroughUnreachable = true;
12481 }
12482
12483 if (!JTH->FallthroughUnreachable)
12484 addSuccessorWithProb(Src: CurMBB, Dst: Fallthrough, Prob: FallthroughProb);
12485 addSuccessorWithProb(Src: CurMBB, Dst: JumpMBB, Prob: JumpProb);
12486 CurMBB->normalizeSuccProbs();
12487
12488 // The jump table header will be inserted in our current block, do the
12489 // range check, and fall through to our fallthrough block.
12490 JTH->HeaderBB = CurMBB;
12491 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
12492
12493 // If we're in the right place, emit the jump table header right now.
12494 if (CurMBB == SwitchMBB) {
12495 visitJumpTableHeader(JT&: *JT, JTH&: *JTH, SwitchBB: SwitchMBB);
12496 JTH->Emitted = true;
12497 }
12498 break;
12499 }
12500 case CC_BitTests: {
12501 // FIXME: Optimize away range check based on pivot comparisons.
12502 BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex];
12503
12504 // The bit test blocks haven't been inserted yet; insert them here.
12505 for (BitTestCase &BTC : BTB->Cases)
12506 CurMF->insert(MBBI: BBI, MBB: BTC.ThisBB);
12507
12508 // Fill in fields of the BitTestBlock.
12509 BTB->Parent = CurMBB;
12510 BTB->Default = Fallthrough;
12511
12512 BTB->DefaultProb = UnhandledProbs;
12513 // If the cases in bit test don't form a contiguous range, we evenly
12514 // distribute the probability on the edge to Fallthrough to two
12515 // successors of CurMBB.
12516 if (!BTB->ContiguousRange) {
12517 BTB->Prob += DefaultProb / 2;
12518 BTB->DefaultProb -= DefaultProb / 2;
12519 }
12520
12521 if (FallthroughUnreachable)
12522 BTB->FallthroughUnreachable = true;
12523
12524 // If we're in the right place, emit the bit test header right now.
12525 if (CurMBB == SwitchMBB) {
12526 visitBitTestHeader(B&: *BTB, SwitchBB: SwitchMBB);
12527 BTB->Emitted = true;
12528 }
12529 break;
12530 }
12531 case CC_Range: {
12532 const Value *RHS, *LHS, *MHS;
12533 ISD::CondCode CC;
12534 if (I->Low == I->High) {
12535 // Check Cond == I->Low.
12536 CC = ISD::SETEQ;
12537 LHS = Cond;
12538 RHS=I->Low;
12539 MHS = nullptr;
12540 } else {
12541 // Check I->Low <= Cond <= I->High.
12542 CC = ISD::SETLE;
12543 LHS = I->Low;
12544 MHS = Cond;
12545 RHS = I->High;
12546 }
12547
12548 // If Fallthrough is unreachable, fold away the comparison.
12549 if (FallthroughUnreachable)
12550 CC = ISD::SETTRUE;
12551
12552 // The false probability is the sum of all unhandled cases.
12553 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB,
12554 getCurSDLoc(), I->Prob, UnhandledProbs);
12555
12556 if (CurMBB == SwitchMBB)
12557 visitSwitchCase(CB, SwitchBB: SwitchMBB);
12558 else
12559 SL->SwitchCases.push_back(x: CB);
12560
12561 break;
12562 }
12563 }
12564 CurMBB = Fallthrough;
12565 }
12566}
12567
12568void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
12569 const SwitchWorkListItem &W,
12570 Value *Cond,
12571 MachineBasicBlock *SwitchMBB) {
12572 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
12573 "Clusters not sorted?");
12574 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
12575
12576 auto [LastLeft, FirstRight, LeftProb, RightProb] =
12577 SL->computeSplitWorkItemInfo(W);
12578
12579 // Use the first element on the right as pivot since we will make less-than
12580 // comparisons against it.
12581 CaseClusterIt PivotCluster = FirstRight;
12582 assert(PivotCluster > W.FirstCluster);
12583 assert(PivotCluster <= W.LastCluster);
12584
12585 CaseClusterIt FirstLeft = W.FirstCluster;
12586 CaseClusterIt LastRight = W.LastCluster;
12587
12588 const ConstantInt *Pivot = PivotCluster->Low;
12589
12590 // New blocks will be inserted immediately after the current one.
12591 MachineFunction::iterator BBI(W.MBB);
12592 ++BBI;
12593
12594 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
12595 // we can branch to its destination directly if it's squeezed exactly in
12596 // between the known lower bound and Pivot - 1.
12597 MachineBasicBlock *LeftMBB;
12598 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
12599 FirstLeft->Low == W.GE &&
12600 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
12601 LeftMBB = FirstLeft->MBB;
12602 } else {
12603 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(BB: W.MBB->getBasicBlock());
12604 FuncInfo.MF->insert(MBBI: BBI, MBB: LeftMBB);
12605 WorkList.push_back(
12606 Elt: {.MBB: LeftMBB, .FirstCluster: FirstLeft, .LastCluster: LastLeft, .GE: W.GE, .LT: Pivot, .DefaultProb: W.DefaultProb / 2});
12607 // Put Cond in a virtual register to make it available from the new blocks.
12608 ExportFromCurrentBlock(V: Cond);
12609 }
12610
12611 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
12612 // single cluster, RHS.Low == Pivot, and we can branch to its destination
12613 // directly if RHS.High equals the current upper bound.
12614 MachineBasicBlock *RightMBB;
12615 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
12616 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
12617 RightMBB = FirstRight->MBB;
12618 } else {
12619 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(BB: W.MBB->getBasicBlock());
12620 FuncInfo.MF->insert(MBBI: BBI, MBB: RightMBB);
12621 WorkList.push_back(
12622 Elt: {.MBB: RightMBB, .FirstCluster: FirstRight, .LastCluster: LastRight, .GE: Pivot, .LT: W.LT, .DefaultProb: W.DefaultProb / 2});
12623 // Put Cond in a virtual register to make it available from the new blocks.
12624 ExportFromCurrentBlock(V: Cond);
12625 }
12626
12627 // Create the CaseBlock record that will be used to lower the branch.
12628 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
12629 getCurSDLoc(), LeftProb, RightProb);
12630
12631 if (W.MBB == SwitchMBB)
12632 visitSwitchCase(CB, SwitchBB: SwitchMBB);
12633 else
12634 SL->SwitchCases.push_back(x: CB);
12635}
12636
12637// Scale CaseProb after peeling a case with the probablity of PeeledCaseProb
12638// from the swith statement.
12639static BranchProbability scaleCaseProbality(BranchProbability CaseProb,
12640 BranchProbability PeeledCaseProb) {
12641 if (PeeledCaseProb == BranchProbability::getOne())
12642 return BranchProbability::getZero();
12643 BranchProbability SwitchProb = PeeledCaseProb.getCompl();
12644
12645 uint32_t Numerator = CaseProb.getNumerator();
12646 uint32_t Denominator = SwitchProb.scale(Num: CaseProb.getDenominator());
12647 return BranchProbability(Numerator, std::max(a: Numerator, b: Denominator));
12648}
12649
12650// Try to peel the top probability case if it exceeds the threshold.
12651// Return current MachineBasicBlock for the switch statement if the peeling
12652// does not occur.
12653// If the peeling is performed, return the newly created MachineBasicBlock
12654// for the peeled switch statement. Also update Clusters to remove the peeled
12655// case. PeeledCaseProb is the BranchProbability for the peeled case.
12656MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster(
12657 const SwitchInst &SI, CaseClusterVector &Clusters,
12658 BranchProbability &PeeledCaseProb) {
12659 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
12660 // Don't perform if there is only one cluster or optimizing for size.
12661 if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 ||
12662 TM.getOptLevel() == CodeGenOptLevel::None ||
12663 SwitchMBB->getParent()->getFunction().hasMinSize())
12664 return SwitchMBB;
12665
12666 BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100);
12667 unsigned PeeledCaseIndex = 0;
12668 bool SwitchPeeled = false;
12669 for (unsigned Index = 0; Index < Clusters.size(); ++Index) {
12670 CaseCluster &CC = Clusters[Index];
12671 if (CC.Prob < TopCaseProb)
12672 continue;
12673 TopCaseProb = CC.Prob;
12674 PeeledCaseIndex = Index;
12675 SwitchPeeled = true;
12676 }
12677 if (!SwitchPeeled)
12678 return SwitchMBB;
12679
12680 LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: "
12681 << TopCaseProb << "\n");
12682
12683 // Record the MBB for the peeled switch statement.
12684 MachineFunction::iterator BBI(SwitchMBB);
12685 ++BBI;
12686 MachineBasicBlock *PeeledSwitchMBB =
12687 FuncInfo.MF->CreateMachineBasicBlock(BB: SwitchMBB->getBasicBlock());
12688 FuncInfo.MF->insert(MBBI: BBI, MBB: PeeledSwitchMBB);
12689
12690 ExportFromCurrentBlock(V: SI.getCondition());
12691 auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
12692 SwitchWorkListItem W = {.MBB: SwitchMBB, .FirstCluster: PeeledCaseIt, .LastCluster: PeeledCaseIt,
12693 .GE: nullptr, .LT: nullptr, .DefaultProb: TopCaseProb.getCompl()};
12694 lowerWorkItem(W, Cond: SI.getCondition(), SwitchMBB, DefaultMBB: PeeledSwitchMBB);
12695
12696 Clusters.erase(position: PeeledCaseIt);
12697 for (CaseCluster &CC : Clusters) {
12698 LLVM_DEBUG(
12699 dbgs() << "Scale the probablity for one cluster, before scaling: "
12700 << CC.Prob << "\n");
12701 CC.Prob = scaleCaseProbality(CaseProb: CC.Prob, PeeledCaseProb: TopCaseProb);
12702 LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n");
12703 }
12704 PeeledCaseProb = TopCaseProb;
12705 return PeeledSwitchMBB;
12706}
12707
12708void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
12709 // Extract cases from the switch.
12710 BranchProbabilityInfo *BPI = FuncInfo.BPI;
12711 CaseClusterVector Clusters;
12712 Clusters.reserve(n: SI.getNumCases());
12713 for (auto I : SI.cases()) {
12714 MachineBasicBlock *Succ = FuncInfo.getMBB(BB: I.getCaseSuccessor());
12715 const ConstantInt *CaseVal = I.getCaseValue();
12716 BranchProbability Prob =
12717 BPI ? BPI->getEdgeProbability(Src: SI.getParent(), IndexInSuccessors: I.getSuccessorIndex())
12718 : BranchProbability(1, SI.getNumCases() + 1);
12719 Clusters.push_back(x: CaseCluster::range(Low: CaseVal, High: CaseVal, MBB: Succ, Prob));
12720 }
12721
12722 MachineBasicBlock *DefaultMBB = FuncInfo.getMBB(BB: SI.getDefaultDest());
12723
12724 // Cluster adjacent cases with the same destination. We do this at all
12725 // optimization levels because it's cheap to do and will make codegen faster
12726 // if there are many clusters.
12727 sortAndRangeify(Clusters);
12728
12729 // The branch probablity of the peeled case.
12730 BranchProbability PeeledCaseProb = BranchProbability::getZero();
12731 MachineBasicBlock *PeeledSwitchMBB =
12732 peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);
12733
12734 // If there is only the default destination, jump there directly.
12735 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
12736 if (Clusters.empty()) {
12737 assert(PeeledSwitchMBB == SwitchMBB);
12738 SwitchMBB->addSuccessor(Succ: DefaultMBB);
12739 if (DefaultMBB != NextBlock(MBB: SwitchMBB)) {
12740 DAG.setRoot(DAG.getNode(Opcode: ISD::BR, DL: getCurSDLoc(), VT: MVT::Other,
12741 N1: getControlRoot(), N2: DAG.getBasicBlock(MBB: DefaultMBB)));
12742 }
12743 return;
12744 }
12745
12746 SL->findJumpTables(Clusters, SI: &SI, SL: getCurSDLoc(), DefaultMBB, PSI: DAG.getPSI(),
12747 BFI: DAG.getBFI());
12748 SL->findBitTestClusters(Clusters, SI: &SI);
12749
12750 LLVM_DEBUG({
12751 dbgs() << "Case clusters: ";
12752 for (const CaseCluster &C : Clusters) {
12753 if (C.Kind == CC_JumpTable)
12754 dbgs() << "JT:";
12755 if (C.Kind == CC_BitTests)
12756 dbgs() << "BT:";
12757
12758 C.Low->getValue().print(dbgs(), true);
12759 if (C.Low != C.High) {
12760 dbgs() << '-';
12761 C.High->getValue().print(dbgs(), true);
12762 }
12763 dbgs() << ' ';
12764 }
12765 dbgs() << '\n';
12766 });
12767
12768 assert(!Clusters.empty());
12769 SwitchWorkList WorkList;
12770 CaseClusterIt First = Clusters.begin();
12771 CaseClusterIt Last = Clusters.end() - 1;
12772 auto DefaultProb = getEdgeProbability(Src: PeeledSwitchMBB, Dst: DefaultMBB);
12773 // Scale the branchprobability for DefaultMBB if the peel occurs and
12774 // DefaultMBB is not replaced.
12775 if (PeeledCaseProb != BranchProbability::getZero() &&
12776 DefaultMBB == FuncInfo.getMBB(BB: SI.getDefaultDest()))
12777 DefaultProb = scaleCaseProbality(CaseProb: DefaultProb, PeeledCaseProb);
12778 WorkList.push_back(
12779 Elt: {.MBB: PeeledSwitchMBB, .FirstCluster: First, .LastCluster: Last, .GE: nullptr, .LT: nullptr, .DefaultProb: DefaultProb});
12780
12781 while (!WorkList.empty()) {
12782 SwitchWorkListItem W = WorkList.pop_back_val();
12783 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
12784
12785 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOptLevel::None &&
12786 !DefaultMBB->getParent()->getFunction().hasMinSize()) {
12787 // For optimized builds, lower large range as a balanced binary tree.
12788 splitWorkItem(WorkList, W, Cond: SI.getCondition(), SwitchMBB);
12789 continue;
12790 }
12791
12792 lowerWorkItem(W, Cond: SI.getCondition(), SwitchMBB, DefaultMBB);
12793 }
12794}
12795
12796void SelectionDAGBuilder::visitStepVector(const CallInst &I) {
12797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12798 auto DL = getCurSDLoc();
12799 EVT ResultVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
12800 setValue(V: &I, NewN: DAG.getStepVector(DL, ResVT: ResultVT));
12801}
12802
12803void SelectionDAGBuilder::visitVectorReverse(const CallInst &I) {
12804 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12805 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
12806
12807 SDLoc DL = getCurSDLoc();
12808 SDValue V = getValue(V: I.getOperand(i_nocapture: 0));
12809 assert(VT == V.getValueType() && "Malformed vector.reverse!");
12810
12811 if (VT.isScalableVector()) {
12812 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::VECTOR_REVERSE, DL, VT, Operand: V));
12813 return;
12814 }
12815
12816 // Use VECTOR_SHUFFLE for the fixed-length vector
12817 // to maintain existing behavior.
12818 SmallVector<int, 8> Mask;
12819 unsigned NumElts = VT.getVectorMinNumElements();
12820 for (unsigned i = 0; i != NumElts; ++i)
12821 Mask.push_back(Elt: NumElts - 1 - i);
12822
12823 setValue(V: &I, NewN: DAG.getVectorShuffle(VT, dl: DL, N1: V, N2: DAG.getUNDEF(VT), Mask));
12824}
12825
12826void SelectionDAGBuilder::visitVectorDeinterleave(const CallInst &I,
12827 unsigned Factor) {
12828 auto DL = getCurSDLoc();
12829 SDValue InVec = getValue(V: I.getOperand(i_nocapture: 0));
12830
12831 SmallVector<EVT, 4> ValueVTs;
12832 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(), Ty: I.getType(),
12833 ValueVTs);
12834
12835 EVT OutVT = ValueVTs[0];
12836 unsigned OutNumElts = OutVT.getVectorMinNumElements();
12837
12838 SmallVector<SDValue, 4> SubVecs(Factor);
12839 for (unsigned i = 0; i != Factor; ++i) {
12840 assert(ValueVTs[i] == OutVT && "Expected VTs to be the same");
12841 SubVecs[i] = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT: OutVT, N1: InVec,
12842 N2: DAG.getVectorIdxConstant(Val: OutNumElts * i, DL));
12843 }
12844
12845 // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
12846 // from existing legalisation and combines.
12847 if (OutVT.isFixedLengthVector() && Factor == 2) {
12848 SDValue Even = DAG.getVectorShuffle(VT: OutVT, dl: DL, N1: SubVecs[0], N2: SubVecs[1],
12849 Mask: createStrideMask(Start: 0, Stride: 2, VF: OutNumElts));
12850 SDValue Odd = DAG.getVectorShuffle(VT: OutVT, dl: DL, N1: SubVecs[0], N2: SubVecs[1],
12851 Mask: createStrideMask(Start: 1, Stride: 2, VF: OutNumElts));
12852 SDValue Res = DAG.getMergeValues(Ops: {Even, Odd}, dl: getCurSDLoc());
12853 setValue(V: &I, NewN: Res);
12854 return;
12855 }
12856
12857 SDValue Res = DAG.getNode(Opcode: ISD::VECTOR_DEINTERLEAVE, DL,
12858 VTList: DAG.getVTList(VTs: ValueVTs), Ops: SubVecs);
12859 setValue(V: &I, NewN: Res);
12860}
12861
12862void SelectionDAGBuilder::visitVectorInterleave(const CallInst &I,
12863 unsigned Factor) {
12864 auto DL = getCurSDLoc();
12865 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12866 EVT InVT = getValue(V: I.getOperand(i_nocapture: 0)).getValueType();
12867 EVT OutVT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
12868
12869 SmallVector<SDValue, 8> InVecs(Factor);
12870 for (unsigned i = 0; i < Factor; ++i) {
12871 InVecs[i] = getValue(V: I.getOperand(i_nocapture: i));
12872 assert(InVecs[i].getValueType() == InVecs[0].getValueType() &&
12873 "Expected VTs to be the same");
12874 }
12875
12876 // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
12877 // from existing legalisation and combines.
12878 if (OutVT.isFixedLengthVector() && Factor == 2) {
12879 unsigned NumElts = InVT.getVectorMinNumElements();
12880 SDValue V = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: OutVT, Ops: InVecs);
12881 setValue(V: &I, NewN: DAG.getVectorShuffle(VT: OutVT, dl: DL, N1: V, N2: DAG.getUNDEF(VT: OutVT),
12882 Mask: createInterleaveMask(VF: NumElts, NumVecs: 2)));
12883 return;
12884 }
12885
12886 SmallVector<EVT, 8> ValueVTs(Factor, InVT);
12887 SDValue Res =
12888 DAG.getNode(Opcode: ISD::VECTOR_INTERLEAVE, DL, VTList: DAG.getVTList(VTs: ValueVTs), Ops: InVecs);
12889
12890 SmallVector<SDValue, 8> Results(Factor);
12891 for (unsigned i = 0; i < Factor; ++i)
12892 Results[i] = Res.getValue(R: i);
12893
12894 Res = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: OutVT, Ops: Results);
12895 setValue(V: &I, NewN: Res);
12896}
12897
12898void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) {
12899 SmallVector<EVT, 4> ValueVTs;
12900 ComputeValueVTs(TLI: DAG.getTargetLoweringInfo(), DL: DAG.getDataLayout(), Ty: I.getType(),
12901 ValueVTs);
12902 unsigned NumValues = ValueVTs.size();
12903 if (NumValues == 0) return;
12904
12905 SmallVector<SDValue, 4> Values(NumValues);
12906 SDValue Op = getValue(V: I.getOperand(i_nocapture: 0));
12907
12908 for (unsigned i = 0; i != NumValues; ++i)
12909 Values[i] = DAG.getNode(Opcode: ISD::FREEZE, DL: getCurSDLoc(), VT: ValueVTs[i],
12910 Operand: SDValue(Op.getNode(), Op.getResNo() + i));
12911
12912 setValue(V: &I, NewN: DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
12913 VTList: DAG.getVTList(VTs: ValueVTs), Ops: Values));
12914}
12915
12916void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) {
12917 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12918 EVT VT = TLI.getValueType(DL: DAG.getDataLayout(), Ty: I.getType());
12919
12920 SDLoc DL = getCurSDLoc();
12921 SDValue V1 = getValue(V: I.getOperand(i_nocapture: 0));
12922 SDValue V2 = getValue(V: I.getOperand(i_nocapture: 1));
12923 const bool IsLeft = I.getIntrinsicID() == Intrinsic::vector_splice_left;
12924
12925 // VECTOR_SHUFFLE doesn't support a scalable or non-constant mask.
12926 if (VT.isScalableVector() || !isa<ConstantInt>(Val: I.getOperand(i_nocapture: 2))) {
12927 SDValue Offset = DAG.getZExtOrTrunc(
12928 Op: getValue(V: I.getOperand(i_nocapture: 2)), DL, VT: TLI.getVectorIdxTy(DL: DAG.getDataLayout()));
12929 setValue(V: &I, NewN: DAG.getNode(Opcode: IsLeft ? ISD::VECTOR_SPLICE_LEFT
12930 : ISD::VECTOR_SPLICE_RIGHT,
12931 DL, VT, N1: V1, N2: V2, N3: Offset));
12932 return;
12933 }
12934 uint64_t Imm = cast<ConstantInt>(Val: I.getOperand(i_nocapture: 2))->getZExtValue();
12935
12936 unsigned NumElts = VT.getVectorNumElements();
12937
12938 uint64_t Idx = IsLeft ? Imm : NumElts - Imm;
12939
12940 // Use VECTOR_SHUFFLE to maintain original behaviour for fixed-length vectors.
12941 SmallVector<int, 8> Mask;
12942 for (unsigned i = 0; i < NumElts; ++i)
12943 Mask.push_back(Elt: Idx + i);
12944 setValue(V: &I, NewN: DAG.getVectorShuffle(VT, dl: DL, N1: V1, N2: V2, Mask));
12945}
12946
12947// Consider the following MIR after SelectionDAG, which produces output in
12948// phyregs in the first case or virtregs in the second case.
12949//
12950// INLINEASM_BR ..., implicit-def $ebx, ..., implicit-def $edx
12951// %5:gr32 = COPY $ebx
12952// %6:gr32 = COPY $edx
12953// %1:gr32 = COPY %6:gr32
12954// %0:gr32 = COPY %5:gr32
12955//
12956// INLINEASM_BR ..., def %5:gr32, ..., def %6:gr32
12957// %1:gr32 = COPY %6:gr32
12958// %0:gr32 = COPY %5:gr32
12959//
12960// Given %0, we'd like to return $ebx in the first case and %5 in the second.
12961// Given %1, we'd like to return $edx in the first case and %6 in the second.
12962//
12963// If a callbr has outputs, it will have a single mapping in FuncInfo.ValueMap
12964// to a single virtreg (such as %0). The remaining outputs monotonically
12965// increase in virtreg number from there. If a callbr has no outputs, then it
12966// should not have a corresponding callbr landingpad; in fact, the callbr
12967// landingpad would not even be able to refer to such a callbr.
12968static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg) {
12969 MachineInstr *MI = MRI.def_begin(RegNo: Reg)->getParent();
12970 // There is definitely at least one copy.
12971 assert(MI->getOpcode() == TargetOpcode::COPY &&
12972 "start of copy chain MUST be COPY");
12973 Reg = MI->getOperand(i: 1).getReg();
12974
12975 // If the copied register in the first copy must be virtual.
12976 assert(Reg.isVirtual() && "expected COPY of virtual register");
12977 MI = MRI.def_begin(RegNo: Reg)->getParent();
12978
12979 // There may be an optional second copy.
12980 if (MI->getOpcode() == TargetOpcode::COPY) {
12981 assert(Reg.isVirtual() && "expected COPY of virtual register");
12982 Reg = MI->getOperand(i: 1).getReg();
12983 assert(Reg.isPhysical() && "expected COPY of physical register");
12984 } else {
12985 // The start of the chain must be an INLINEASM_BR.
12986 assert(MI->getOpcode() == TargetOpcode::INLINEASM_BR &&
12987 "end of copy chain MUST be INLINEASM_BR");
12988 }
12989
12990 return Reg;
12991}
12992
12993// We must do this walk rather than the simpler
12994// setValue(&I, getCopyFromRegs(CBR, CBR->getType()));
12995// otherwise we will end up with copies of virtregs only valid along direct
12996// edges.
12997void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) {
12998 SmallVector<EVT, 8> ResultVTs;
12999 SmallVector<SDValue, 8> ResultValues;
13000 const auto *CBR =
13001 cast<CallBrInst>(Val: I.getParent()->getUniquePredecessor()->getTerminator());
13002
13003 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13004 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
13005 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
13006
13007 Register InitialDef = FuncInfo.ValueMap[CBR];
13008 SDValue Chain = DAG.getRoot();
13009
13010 // Re-parse the asm constraints string.
13011 TargetLowering::AsmOperandInfoVector TargetConstraints =
13012 TLI.ParseConstraints(DL: DAG.getDataLayout(), TRI, Call: *CBR);
13013 for (auto &T : TargetConstraints) {
13014 SDISelAsmOperandInfo OpInfo(T);
13015 if (OpInfo.Type != InlineAsm::isOutput)
13016 continue;
13017
13018 // Pencil in OpInfo.ConstraintType and OpInfo.ConstraintVT based on the
13019 // individual constraint.
13020 TLI.ComputeConstraintToUse(OpInfo, Op: OpInfo.CallOperand, DAG: &DAG);
13021
13022 switch (OpInfo.ConstraintType) {
13023 case TargetLowering::C_Register:
13024 case TargetLowering::C_RegisterClass: {
13025 // Fill in OpInfo.AssignedRegs.Regs.
13026 getRegistersForValue(DAG, DL: getCurSDLoc(), OpInfo, RefOpInfo&: OpInfo);
13027
13028 // getRegistersForValue may produce 1 to many registers based on whether
13029 // the OpInfo.ConstraintVT is legal on the target or not.
13030 for (Register &Reg : OpInfo.AssignedRegs.Regs) {
13031 Register OriginalDef = FollowCopyChain(MRI, Reg: InitialDef++);
13032 if (OriginalDef.isPhysical())
13033 FuncInfo.MBB->addLiveIn(PhysReg: OriginalDef);
13034 // Update the assigned registers to use the original defs.
13035 Reg = OriginalDef;
13036 }
13037
13038 SDValue V = OpInfo.AssignedRegs.getCopyFromRegs(
13039 DAG, FuncInfo, dl: getCurSDLoc(), Chain, Glue: nullptr, V: CBR);
13040 ResultValues.push_back(Elt: V);
13041 ResultVTs.push_back(Elt: OpInfo.ConstraintVT);
13042 break;
13043 }
13044 case TargetLowering::C_Other: {
13045 SDValue Flag;
13046 SDValue V = TLI.LowerAsmOutputForConstraint(Chain, Glue&: Flag, DL: getCurSDLoc(),
13047 OpInfo, DAG);
13048 ++InitialDef;
13049 ResultValues.push_back(Elt: V);
13050 ResultVTs.push_back(Elt: OpInfo.ConstraintVT);
13051 break;
13052 }
13053 default:
13054 break;
13055 }
13056 }
13057 SDValue V = DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: getCurSDLoc(),
13058 VTList: DAG.getVTList(VTs: ResultVTs), Ops: ResultValues);
13059 setValue(V: &I, NewN: V);
13060}
13061