1//===- AArch64PostCoalescerPass.cpp - AArch64 Post Coalescer pass ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//===----------------------------------------------------------------------===//
9
10#include "AArch64MachineFunctionInfo.h"
11#include "llvm/CodeGen/LiveIntervals.h"
12#include "llvm/CodeGen/MachineRegisterInfo.h"
13#include "llvm/InitializePasses.h"
14
15using namespace llvm;
16
17#define DEBUG_TYPE "aarch64-post-coalescer-pass"
18
19namespace {
20
21struct AArch64PostCoalescer : public MachineFunctionPass {
22 static char ID;
23
24 AArch64PostCoalescer() : MachineFunctionPass(ID) {}
25
26 LiveIntervals *LIS;
27 MachineRegisterInfo *MRI;
28
29 bool runOnMachineFunction(MachineFunction &MF) override;
30
31 StringRef getPassName() const override {
32 return "AArch64 Post Coalescer pass";
33 }
34
35 void getAnalysisUsage(AnalysisUsage &AU) const override {
36 AU.setPreservesAll();
37 AU.addRequired<LiveIntervalsWrapperPass>();
38 MachineFunctionPass::getAnalysisUsage(AU);
39 }
40};
41
42char AArch64PostCoalescer::ID = 0;
43
44} // end anonymous namespace
45
46INITIALIZE_PASS_BEGIN(AArch64PostCoalescer, "aarch64-post-coalescer-pass",
47 "AArch64 Post Coalescer Pass", false, false)
48INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
49INITIALIZE_PASS_END(AArch64PostCoalescer, "aarch64-post-coalescer-pass",
50 "AArch64 Post Coalescer Pass", false, false)
51
52bool AArch64PostCoalescer::runOnMachineFunction(MachineFunction &MF) {
53 if (skipFunction(F: MF.getFunction()))
54 return false;
55
56 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
57 if (!FuncInfo->hasStreamingModeChanges())
58 return false;
59
60 MRI = &MF.getRegInfo();
61 LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
62 bool Changed = false;
63
64 for (MachineBasicBlock &MBB : MF) {
65 for (MachineInstr &MI : make_early_inc_range(Range&: MBB)) {
66 switch (MI.getOpcode()) {
67 default:
68 break;
69 case AArch64::COALESCER_BARRIER_FPR16:
70 case AArch64::COALESCER_BARRIER_FPR32:
71 case AArch64::COALESCER_BARRIER_FPR64:
72 case AArch64::COALESCER_BARRIER_FPR128: {
73 Register Src = MI.getOperand(i: 1).getReg();
74 Register Dst = MI.getOperand(i: 0).getReg();
75 if (Src != Dst)
76 MRI->replaceRegWith(FromReg: Dst, ToReg: Src);
77
78 if (MI.getOperand(i: 1).isUndef())
79 for (MachineOperand &MO : MRI->use_operands(Reg: Dst))
80 MO.setIsUndef();
81
82 // MI must be erased from the basic block before recalculating the live
83 // interval.
84 LIS->RemoveMachineInstrFromMaps(MI);
85 MI.eraseFromParent();
86
87 LIS->removeInterval(Reg: Src);
88 LIS->createAndComputeVirtRegInterval(Reg: Src);
89
90 Changed = true;
91 break;
92 }
93 }
94 }
95 }
96
97 return Changed;
98}
99
100FunctionPass *llvm::createAArch64PostCoalescerPass() {
101 return new AArch64PostCoalescer();
102}
103