1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "AMDGPUArgumentUsageInfo.h"
10#include "SIRegisterInfo.h"
11#include "llvm/CodeGen/TargetRegisterInfo.h"
12#include "llvm/Support/NativeFormatting.h"
13#include "llvm/Support/raw_ostream.h"
14
15using namespace llvm;
16
17void ArgDescriptor::print(raw_ostream &OS,
18 const TargetRegisterInfo *TRI) const {
19 if (!isSet()) {
20 OS << "<not set>\n";
21 return;
22 }
23
24 if (isRegister())
25 OS << "Reg " << printReg(Reg: getRegister(), TRI);
26 else
27 OS << "Stack offset " << getStackOffset();
28
29 if (isMasked()) {
30 OS << " & ";
31 llvm::write_hex(S&: OS, N: Mask, Style: llvm::HexPrintStyle::PrefixLower);
32 }
33
34 OS << '\n';
35}
36
37// Hardcoded registers from fixed function ABI
38const AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::FixedABIFunctionInfo =
39 AMDGPUFunctionArgInfo::fixedABILayout();
40
41std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
42AMDGPUFunctionArgInfo::getPreloadedValue(
43 AMDGPUFunctionArgInfo::PreloadedValue Value) const {
44 switch (Value) {
45 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {
46 return std::tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
47 &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32));
48 }
49 case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR:
50 return std::tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
51 &AMDGPU::SGPR_64RegClass,
52 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
53 case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:
54 return std::tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
55 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
56 case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y:
57 return std::tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
58 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
59 case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z:
60 return std::tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
61 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
62 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_X:
63 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Y:
64 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Z:
65 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_X:
66 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Y:
67 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Z:
68 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_FLAT_ID:
69 return std::tuple(nullptr, &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
70 case AMDGPUFunctionArgInfo::LDS_KERNEL_ID:
71 return std::tuple(LDSKernelId ? &LDSKernelId : nullptr,
72 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
73 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET:
74 return std::tuple(
75 PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
76 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
77 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_SIZE:
78 return {PrivateSegmentSize ? &PrivateSegmentSize : nullptr,
79 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32)};
80 case AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR:
81 return std::tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
82 &AMDGPU::SGPR_64RegClass,
83 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
84 case AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR:
85 return std::tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
86 &AMDGPU::SGPR_64RegClass,
87 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
88 case AMDGPUFunctionArgInfo::DISPATCH_ID:
89 return std::tuple(DispatchID ? &DispatchID : nullptr,
90 &AMDGPU::SGPR_64RegClass, LLT::scalar(SizeInBits: 64));
91 case AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT:
92 return std::tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
93 &AMDGPU::SGPR_64RegClass, LLT::scalar(SizeInBits: 64));
94 case AMDGPUFunctionArgInfo::DISPATCH_PTR:
95 return std::tuple(DispatchPtr ? &DispatchPtr : nullptr,
96 &AMDGPU::SGPR_64RegClass,
97 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
98 case AMDGPUFunctionArgInfo::QUEUE_PTR:
99 return std::tuple(QueuePtr ? &QueuePtr : nullptr, &AMDGPU::SGPR_64RegClass,
100 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
101 case AMDGPUFunctionArgInfo::WORKITEM_ID_X:
102 return std::tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
103 &AMDGPU::VGPR_32RegClass, LLT::integer(SizeInBits: 32));
104 case AMDGPUFunctionArgInfo::WORKITEM_ID_Y:
105 return std::tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
106 &AMDGPU::VGPR_32RegClass, LLT::integer(SizeInBits: 32));
107 case AMDGPUFunctionArgInfo::WORKITEM_ID_Z:
108 return std::tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
109 &AMDGPU::VGPR_32RegClass, LLT::integer(SizeInBits: 32));
110 }
111 llvm_unreachable("unexpected preloaded value type");
112}
113
114AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::fixedABILayout() {
115 AMDGPUFunctionArgInfo AI;
116 AI.PrivateSegmentBuffer
117 = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
118 AI.DispatchPtr = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR4_SGPR5);
119 AI.QueuePtr = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR6_SGPR7);
120
121 // Do not pass kernarg segment pointer, only pass increment version in its
122 // place.
123 AI.ImplicitArgPtr = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR8_SGPR9);
124 AI.DispatchID = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR10_SGPR11);
125
126 // Skip FlatScratchInit/PrivateSegmentSize
127 AI.WorkGroupIDX = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR12);
128 AI.WorkGroupIDY = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR13);
129 AI.WorkGroupIDZ = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR14);
130 AI.LDSKernelId = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR15);
131
132 const unsigned Mask = 0x3ff;
133 AI.WorkItemIDX = ArgDescriptor::createRegister(Reg: AMDGPU::VGPR31, Mask);
134 AI.WorkItemIDY = ArgDescriptor::createRegister(Reg: AMDGPU::VGPR31, Mask: Mask << 10);
135 AI.WorkItemIDZ = ArgDescriptor::createRegister(Reg: AMDGPU::VGPR31, Mask: Mask << 20);
136 return AI;
137}
138