1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "AMDGPUArgumentUsageInfo.h"
10#include "AMDGPU.h"
11#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12#include "SIRegisterInfo.h"
13#include "llvm/CodeGen/TargetRegisterInfo.h"
14#include "llvm/Support/NativeFormatting.h"
15#include "llvm/Support/raw_ostream.h"
16
17using namespace llvm;
18
19void ArgDescriptor::print(raw_ostream &OS,
20 const TargetRegisterInfo *TRI) const {
21 if (!isSet()) {
22 OS << "<not set>\n";
23 return;
24 }
25
26 if (isRegister())
27 OS << "Reg " << printReg(Reg: getRegister(), TRI);
28 else
29 OS << "Stack offset " << getStackOffset();
30
31 if (isMasked()) {
32 OS << " & ";
33 llvm::write_hex(S&: OS, N: Mask, Style: llvm::HexPrintStyle::PrefixLower);
34 }
35
36 OS << '\n';
37}
38
39// Hardcoded registers from fixed function ABI
40const AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::FixedABIFunctionInfo =
41 AMDGPUFunctionArgInfo::fixedABILayout();
42
43std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
44AMDGPUFunctionArgInfo::getPreloadedValue(
45 AMDGPUFunctionArgInfo::PreloadedValue Value) const {
46 switch (Value) {
47 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {
48 return std::tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
49 &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32));
50 }
51 case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR:
52 return std::tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
53 &AMDGPU::SGPR_64RegClass,
54 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
55 case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:
56 return std::tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
57 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
58 case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y:
59 return std::tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
60 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
61 case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z:
62 return std::tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
63 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
64 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_X:
65 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Y:
66 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Z:
67 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_X:
68 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Y:
69 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Z:
70 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_FLAT_ID:
71 return std::tuple(nullptr, &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
72 case AMDGPUFunctionArgInfo::LDS_KERNEL_ID:
73 return std::tuple(LDSKernelId ? &LDSKernelId : nullptr,
74 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
75 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET:
76 return std::tuple(
77 PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
78 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
79 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_SIZE:
80 return {PrivateSegmentSize ? &PrivateSegmentSize : nullptr,
81 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32)};
82 case AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR:
83 return std::tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
84 &AMDGPU::SGPR_64RegClass,
85 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
86 case AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR:
87 return std::tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
88 &AMDGPU::SGPR_64RegClass,
89 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
90 case AMDGPUFunctionArgInfo::DISPATCH_ID:
91 return std::tuple(DispatchID ? &DispatchID : nullptr,
92 &AMDGPU::SGPR_64RegClass, LLT::scalar(SizeInBits: 64));
93 case AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT:
94 return std::tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
95 &AMDGPU::SGPR_64RegClass, LLT::scalar(SizeInBits: 64));
96 case AMDGPUFunctionArgInfo::DISPATCH_PTR:
97 return std::tuple(DispatchPtr ? &DispatchPtr : nullptr,
98 &AMDGPU::SGPR_64RegClass,
99 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
100 case AMDGPUFunctionArgInfo::QUEUE_PTR:
101 return std::tuple(QueuePtr ? &QueuePtr : nullptr, &AMDGPU::SGPR_64RegClass,
102 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
103 case AMDGPUFunctionArgInfo::WORKITEM_ID_X:
104 return std::tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
105 &AMDGPU::VGPR_32RegClass, LLT::scalar(SizeInBits: 32));
106 case AMDGPUFunctionArgInfo::WORKITEM_ID_Y:
107 return std::tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
108 &AMDGPU::VGPR_32RegClass, LLT::scalar(SizeInBits: 32));
109 case AMDGPUFunctionArgInfo::WORKITEM_ID_Z:
110 return std::tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
111 &AMDGPU::VGPR_32RegClass, LLT::scalar(SizeInBits: 32));
112 }
113 llvm_unreachable("unexpected preloaded value type");
114}
115
116AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::fixedABILayout() {
117 AMDGPUFunctionArgInfo AI;
118 AI.PrivateSegmentBuffer
119 = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
120 AI.DispatchPtr = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR4_SGPR5);
121 AI.QueuePtr = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR6_SGPR7);
122
123 // Do not pass kernarg segment pointer, only pass increment version in its
124 // place.
125 AI.ImplicitArgPtr = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR8_SGPR9);
126 AI.DispatchID = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR10_SGPR11);
127
128 // Skip FlatScratchInit/PrivateSegmentSize
129 AI.WorkGroupIDX = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR12);
130 AI.WorkGroupIDY = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR13);
131 AI.WorkGroupIDZ = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR14);
132 AI.LDSKernelId = ArgDescriptor::createRegister(Reg: AMDGPU::SGPR15);
133
134 const unsigned Mask = 0x3ff;
135 AI.WorkItemIDX = ArgDescriptor::createRegister(Reg: AMDGPU::VGPR31, Mask);
136 AI.WorkItemIDY = ArgDescriptor::createRegister(Reg: AMDGPU::VGPR31, Mask: Mask << 10);
137 AI.WorkItemIDZ = ArgDescriptor::createRegister(Reg: AMDGPU::VGPR31, Mask: Mask << 20);
138 return AI;
139}
140