1//===--- AMDGPUBarrierLatency.cpp - AMDGPU Barrier Latency ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file contains a DAG scheduling mutation to add latency to:
10/// 1. Barrier edges between ATOMIC_FENCE instructions and preceding
11/// memory accesses potentially affected by the fence.
12/// This encourages the scheduling of more instructions before
13/// ATOMIC_FENCE instructions. ATOMIC_FENCE instructions may
14/// introduce wait counting or indicate an impending S_BARRIER
15/// wait. Having more instructions in-flight across these
16/// constructs improves latency hiding.
17/// 2. Barrier edges from S_BARRIER_SIGNAL to S_BARRIER_WAIT.
18/// This encourages independent work to be scheduled between
19/// signal and wait, hiding barrier synchronization latency.
20//
21//===----------------------------------------------------------------------===//
22
23#include "AMDGPUBarrierLatency.h"
24#include "GCNSubtarget.h"
25#include "SIInstrInfo.h"
26#include "llvm/CodeGen/ScheduleDAGInstrs.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/TargetParser/AtomicScope.h"
29
30using namespace llvm;
31
32static cl::opt<unsigned> BarrierSignalWaitLatencyOpt(
33 "amdgpu-barrier-signal-wait-latency",
34 cl::desc("Synthetic latency between S_BARRIER_SIGNAL and S_BARRIER_WAIT "
35 "to encourage scheduling independent work between them"),
36 cl::init(Val: 16), cl::Hidden);
37
38namespace {
39
40class BarrierLatency : public ScheduleDAGMutation {
41private:
42 SmallSet<SyncScope::ID, 4> IgnoredScopes;
43
44public:
45 BarrierLatency(MachineFunction *MF) {
46 LLVMContext &Context = MF->getFunction().getContext();
47 const Triple &TT = MF->getSubtarget<GCNSubtarget>().getTargetTriple();
48 auto ScopeID = [&](AtomicScope Scope, bool OneAS) {
49 return Context.getOrInsertSyncScopeID(
50 SSN: *getAtomicScopeIRString(T: TT, S: Scope, IsSingleAddressSpace: OneAS));
51 };
52 IgnoredScopes.insert(V: SyncScope::SingleThread);
53 IgnoredScopes.insert(V: ScopeID(AtomicScope::Wavefront, /*OneAS=*/false));
54 IgnoredScopes.insert(V: ScopeID(AtomicScope::Wavefront, /*OneAS=*/true));
55 IgnoredScopes.insert(V: ScopeID(AtomicScope::Single, /*OneAS=*/true));
56
57 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
58 bool TgSplit =
59 ST.hasTgSplitSupport() && AMDGPU::isTgSplitEnabled(F: MF->getFunction());
60 if (!ST.requiresWaitOnWorkgroupReleaseFence(TgSplit)) {
61 // Prior to GFX10 workgroup scope does not normally require waitcnts
62 IgnoredScopes.insert(V: ScopeID(AtomicScope::Workgroup, /*OneAS=*/false));
63 }
64 }
65 void apply(ScheduleDAGInstrs *DAG) override;
66};
67
68void addLatencyToEdge(SDep &PredDep, SUnit &SU, unsigned Latency) {
69 SUnit *PredSU = PredDep.getSUnit();
70 SDep ForwardD = PredDep;
71 ForwardD.setSUnit(&SU);
72 for (SDep &SuccDep : PredSU->Succs) {
73 if (SuccDep == ForwardD) {
74 SuccDep.setLatency(SuccDep.getLatency() + Latency);
75 break;
76 }
77 }
78 PredDep.setLatency(PredDep.getLatency() + Latency);
79 PredSU->setDepthDirty();
80 SU.setDepthDirty();
81}
82
83void setLatencyForEdge(SDep &PredDep, SUnit &SU, unsigned Latency) {
84 SUnit *PredSU = PredDep.getSUnit();
85 SDep ForwardD = PredDep;
86 ForwardD.setSUnit(&SU);
87 for (SDep &SuccDep : PredSU->Succs) {
88 if (SuccDep == ForwardD) {
89 SuccDep.setLatency(Latency);
90 break;
91 }
92 }
93 PredDep.setLatency(Latency);
94 PredSU->setDepthDirty();
95 SU.setDepthDirty();
96}
97
98void BarrierLatency::apply(ScheduleDAGInstrs *DAG) {
99 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(DAG->TII);
100 constexpr unsigned FenceLatency = 2000;
101 const unsigned BarrierSignalWaitLatency = BarrierSignalWaitLatencyOpt;
102 SmallVector<SUnit *, 8> RegionTDM;
103 SmallVector<SUnit *, 8> RegionAsync;
104 const TargetSchedModel *SchedModel = DAG->getSchedModel();
105
106 for (SUnit &SU : DAG->SUnits) {
107 const MachineInstr *MI = SU.getInstr();
108 unsigned Op = MI->getOpcode();
109
110 if (Op == AMDGPU::ATOMIC_FENCE) {
111 // Update latency on barrier edges of ATOMIC_FENCE.
112 // Ignore scopes not expected to have any latency.
113 SyncScope::ID SSID =
114 static_cast<SyncScope::ID>(MI->getOperand(i: 1).getImm());
115 if (IgnoredScopes.contains(V: SSID))
116 continue;
117
118 for (SDep &PredDep : SU.Preds) {
119 if (!PredDep.isBarrier())
120 continue;
121 SUnit *PredSU = PredDep.getSUnit();
122 MachineInstr *MI = PredSU->getInstr();
123 // Only consider memory loads
124 if (!MI->mayLoad() || MI->mayStore())
125 continue;
126
127 addLatencyToEdge(PredDep, SU,
128 Latency: SchedModel ? SchedModel->computeInstrLatency(MI, UseDefaultDefLatency: false)
129 : FenceLatency);
130 }
131 } else if (Op == AMDGPU::S_BARRIER_WAIT) {
132 for (SDep &PredDep : SU.Preds) {
133 SUnit *PredSU = PredDep.getSUnit();
134 const MachineInstr *PredMI = PredSU->getInstr();
135 if (TII->isBarrierStart(Opcode: PredMI->getOpcode())) {
136 addLatencyToEdge(PredDep, SU, Latency: BarrierSignalWaitLatency);
137 }
138 }
139 } else if (TII->isLDSDMA(MI: *MI)) {
140 if (SIInstrFlags::usesTENSOR_CNT(O: *MI))
141 RegionTDM.push_back(Elt: &SU);
142 else if (SIInstrFlags::usesASYNC_CNT(O: *MI))
143 RegionAsync.push_back(Elt: &SU);
144 } else if (Op == AMDGPU::S_WAIT_TENSORCNT ||
145 Op == AMDGPU::S_WAIT_ASYNCCNT) {
146 auto needWaitFor = [&](SmallVectorImpl<SUnit *> &RegionLDSDMA, SUnit *SU,
147 int64_t Count) {
148 if (RegionLDSDMA.size() <= static_cast<uint64_t>(Count)) {
149 return false;
150 }
151
152 int64_t Counter = 0;
153 auto I = RegionLDSDMA.rbegin(), E = RegionLDSDMA.rend();
154 for (; I != E; I++) {
155 if (Counter >= Count)
156 return true;
157
158 if (SU->NodeNum == (*I)->NodeNum)
159 return false;
160
161 ++Counter;
162 }
163 llvm_unreachable("Malformed RegionLDSDMA");
164 };
165
166 int64_t WaitVal = MI->getOperand(i: 0).getImm();
167 for (SDep &PredDep : SU.Preds) {
168 if (PredDep.getKind() != SDep::Kind::Data)
169 continue;
170
171 Register DepReg = PredDep.getReg();
172 bool IsAsync = Op == AMDGPU::S_WAIT_ASYNCCNT;
173 Register LDSDMACnt = IsAsync ? AMDGPU::ASYNCcnt : AMDGPU::TENSORcnt;
174
175 if (DepReg != LDSDMACnt)
176 continue;
177
178 SUnit *PredSU = PredDep.getSUnit();
179
180 // The data dep can be carried by a non-LDSDMA SU
181 // (e.g. an intervening COPY or pseudo). Such predecessors are not
182 // tracked, so needWaitFor cannot reason about them.
183 const MachineInstr &PredMI = *PredSU->getInstr();
184 if (IsAsync ? !SIInstrFlags::usesASYNC_CNT(O: PredMI)
185 : !SIInstrFlags::usesTENSOR_CNT(O: PredMI))
186 continue;
187
188 if (!needWaitFor(Op == AMDGPU::S_WAIT_ASYNCCNT ? RegionAsync
189 : RegionTDM,
190 PredSU, WaitVal)) {
191 setLatencyForEdge(PredDep, SU, Latency: 1);
192 }
193 }
194 }
195 }
196}
197
198} // end namespace
199
200std::unique_ptr<ScheduleDAGMutation>
201llvm::createAMDGPUBarrierLatencyDAGMutation(MachineFunction *MF) {
202 return std::make_unique<BarrierLatency>(args&: MF);
203}
204