1//=== lib/CodeGen/GlobalISel/AMDGPUCombinerHelper.h -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This contains common combine transformations that may be used in a combine
11/// pass.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUCOMBINERHELPER_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUCOMBINERHELPER_H
17
18#include "GCNSubtarget.h"
19#include "llvm/CodeGen/GlobalISel/Combiner.h"
20#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
21
22namespace llvm {
23class AMDGPUCombinerHelper : public CombinerHelper {
24protected:
25 const GCNSubtarget &STI;
26 const SIInstrInfo &TII;
27
28public:
29 using CombinerHelper::CombinerHelper;
30 AMDGPUCombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B,
31 bool IsPreLegalize, GISelValueTracking *VT,
32 MachineDominatorTree *MDT, const LegalizerInfo *LI,
33 const GCNSubtarget &STI);
34
35 bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;
36 void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;
37
38 bool matchFoldFAbsFptrunc(MachineInstr &Fabs, MachineInstr &Fptrunc) const;
39 void applyFoldFAbsFptrunc(MachineInstr &Fabs, MachineInstr &Fptrunc) const;
40
41 bool matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
42 Register Src1, Register Src2) const;
43 void applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
44 Register Src1, Register Src2) const;
45
46 bool matchCombineFmulWithSelectToFldexp(
47 MachineInstr &MI, MachineInstr &Sel,
48 std::function<void(MachineIRBuilder &)> &MatchInfo) const;
49
50 bool matchConstantIs32BitMask(Register Reg) const;
51
52 /// Match an s64 and/or where one operand is a 32-bit mask (see
53 /// matchConstantIs32BitMask), used to narrow it into two s32 ops. Bails when
54 /// both operands are constants, since folding the binop to a single constant
55 /// is strictly better than narrowing.
56 bool matchBinopWith32BitMask(Register X, Register Y) const;
57
58 /// fmin_legacy/fmax_legacy select s1 on NaN, and on a +0.0/-0.0 tie (s1 for
59 /// min, s0 for max). Returns true if that tie cannot be observed: nsz on
60 /// \p MI, or a known non-logical-zero \p LHS or \p RHS.
61 bool canIgnoreLegacyMinMaxTies(const MachineInstr &MI, Register LHS,
62 Register RHS) const;
63};
64
65} // namespace llvm
66
67#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUCOMBINERHELPER_H
68