1//===-- AMDGPUReserveWWMRegs.cpp - Add WWM Regs to reserved regs list -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This pass should be invoked at the end of wwm-regalloc pipeline.
11/// It identifies the WWM regs allocated during this pipeline and add
12/// them to the list of reserved registers so that they won't be available for
13/// per-thread VGPR allocation in the subsequent regalloc pipeline.
14//
15//===----------------------------------------------------------------------===//
16
17#include "AMDGPUReserveWWMRegs.h"
18#include "AMDGPU.h"
19#include "SIMachineFunctionInfo.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/RegisterClassInfo.h"
22#include "llvm/CodeGen/VirtRegMap.h"
23#include "llvm/InitializePasses.h"
24
25using namespace llvm;
26
27#define DEBUG_TYPE "amdgpu-reserve-wwm-regs"
28
29namespace {
30
31class AMDGPUReserveWWMRegsLegacy : public MachineFunctionPass {
32public:
33 static char ID;
34
35 AMDGPUReserveWWMRegsLegacy() : MachineFunctionPass(ID) {}
36
37 bool runOnMachineFunction(MachineFunction &MF) override;
38
39 StringRef getPassName() const override {
40 return "AMDGPU Reserve WWM Registers";
41 }
42
43 void getAnalysisUsage(AnalysisUsage &AU) const override {
44 AU.addRequired<MachineRegisterClassInfoWrapperPass>();
45 AU.setPreservesAll();
46 MachineFunctionPass::getAnalysisUsage(AU);
47 }
48};
49
50class AMDGPUReserveWWMRegs {
51 RegisterClassInfo &RCI;
52
53public:
54 explicit AMDGPUReserveWWMRegs(RegisterClassInfo &RCI) : RCI(RCI) {}
55
56 bool run(MachineFunction &MF);
57};
58
59} // End anonymous namespace.
60
61INITIALIZE_PASS_BEGIN(AMDGPUReserveWWMRegsLegacy, DEBUG_TYPE,
62 "AMDGPU Reserve WWM Registers", false, false)
63INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
64INITIALIZE_PASS_END(AMDGPUReserveWWMRegsLegacy, DEBUG_TYPE,
65 "AMDGPU Reserve WWM Registers", false, false)
66
67char AMDGPUReserveWWMRegsLegacy::ID = 0;
68
69char &llvm::AMDGPUReserveWWMRegsLegacyID = AMDGPUReserveWWMRegsLegacy::ID;
70
71bool AMDGPUReserveWWMRegsLegacy::runOnMachineFunction(MachineFunction &MF) {
72 auto &RCI = getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
73 return AMDGPUReserveWWMRegs(RCI).run(MF);
74}
75
76PreservedAnalyses
77AMDGPUReserveWWMRegsPass::run(MachineFunction &MF,
78 MachineFunctionAnalysisManager &MFAM) {
79 auto &RCI = MFAM.getResult<MachineRegisterClassAnalysis>(IR&: MF);
80 AMDGPUReserveWWMRegs(RCI).run(MF);
81 // RegisterClassInfo was updated in place, so it need not be abandoned.
82 return PreservedAnalyses::all();
83}
84
85bool AMDGPUReserveWWMRegs::run(MachineFunction &MF) {
86 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
87
88 bool Changed = false;
89 for (MachineBasicBlock &MBB : MF) {
90 for (MachineInstr &MI : MBB) {
91 unsigned Opc = MI.getOpcode();
92 if (Opc != AMDGPU::SI_SPILL_S32_TO_VGPR &&
93 Opc != AMDGPU::SI_RESTORE_S32_FROM_VGPR)
94 continue;
95
96 Register Reg = Opc == AMDGPU::SI_SPILL_S32_TO_VGPR
97 ? MI.getOperand(i: 0).getReg()
98 : MI.getOperand(i: 1).getReg();
99
100 assert(Reg.isPhysical() &&
101 "All WWM registers should have been allocated by now.");
102
103 MFI->reserveWWMRegister(Reg);
104 Changed |= true;
105 }
106 }
107
108 // The renamable flag can't be set for reserved registers. Reset the flag for
109 // MOs involving wwm-regs as they will be reserved during vgpr-regalloc
110 // pipeline.
111 const MachineRegisterInfo &MRI = MF.getRegInfo();
112 for (Register Reg : MFI->getWWMReservedRegs()) {
113 for (MachineOperand &MO : MRI.reg_operands(Reg))
114 MO.setIsRenamable(false);
115 }
116
117 // Now clear the PerLaneVGPRMask earlier set during wwm-regalloc.
118 MFI->clearPerLaneVGPRAllocMask();
119
120 // reserveWWMRegister() and clearPerLaneVGPRAllocMask() both feed
121 // getReservedRegs(): the WWM registers are now reserved, the per-lane VGPRs
122 // no longer are. Refresh the shared RegisterClassInfo, as the register
123 // allocator refreshes only its own copy. Do not freeze the set into MRI:
124 // LiveIntervals does not extend a reserved register's unit ranges to its
125 // uses, so unreserving the per-lane VGPRs here would fail verification.
126 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
127 RCI.updateReservedRegs(ReservedInput: TRI->getReservedRegs(MF));
128
129 return Changed;
130}
131