1//==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15
16#include "AMDGPUArgumentUsageInfo.h"
17#include "AMDGPUMachineFunctionInfo.h"
18#include "AMDGPUTargetMachine.h"
19#include "GCNSubtarget.h"
20#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
21#include "SIInstrInfo.h"
22#include "SIModeRegisterDefaults.h"
23#include "llvm/ADT/SetVector.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/CodeGen/MIRYamlMapping.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/Support/raw_ostream.h"
28#include <optional>
29
30namespace llvm {
31
32class MachineFrameInfo;
33class MachineFunction;
34class SIMachineFunctionInfo;
35class SIRegisterInfo;
36class TargetRegisterClass;
37
38class AMDGPUPseudoSourceValue : public PseudoSourceValue {
39public:
40 enum AMDGPUPSVKind : unsigned {
41 PSVImage = PseudoSourceValue::TargetCustom,
42 GWSResource
43 };
44
45protected:
46 AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
47 : PseudoSourceValue(Kind, TM) {}
48
49public:
50 bool isConstant(const MachineFrameInfo *) const override {
51 // This should probably be true for most images, but we will start by being
52 // conservative.
53 return false;
54 }
55
56 bool isAliased(const MachineFrameInfo *) const override {
57 return true;
58 }
59
60 bool mayAlias(const MachineFrameInfo *) const override {
61 return true;
62 }
63};
64
65class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
66public:
67 explicit AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
68 : AMDGPUPseudoSourceValue(GWSResource, TM) {}
69
70 static bool classof(const PseudoSourceValue *V) {
71 return V->kind() == GWSResource;
72 }
73
74 // These are inaccessible memory from IR.
75 bool isAliased(const MachineFrameInfo *) const override {
76 return false;
77 }
78
79 // These are inaccessible memory from IR.
80 bool mayAlias(const MachineFrameInfo *) const override {
81 return false;
82 }
83
84 void printCustom(raw_ostream &OS) const override {
85 OS << "GWSResource";
86 }
87};
88
89namespace yaml {
90
91struct SIArgument {
92 bool IsRegister;
93 union {
94 StringValue RegisterName;
95 unsigned StackOffset;
96 };
97 std::optional<unsigned> Mask;
98
99 // Default constructor, which creates a stack argument.
100 SIArgument() : IsRegister(false), StackOffset(0) {}
101 SIArgument(const SIArgument &Other) {
102 IsRegister = Other.IsRegister;
103 if (IsRegister)
104 new (&RegisterName) StringValue(Other.RegisterName);
105 else
106 StackOffset = Other.StackOffset;
107 Mask = Other.Mask;
108 }
109 SIArgument &operator=(const SIArgument &Other) {
110 // Default-construct or destruct the old RegisterName in case of switching
111 // union members
112 if (IsRegister != Other.IsRegister) {
113 if (Other.IsRegister)
114 new (&RegisterName) StringValue();
115 else
116 RegisterName.~StringValue();
117 }
118 IsRegister = Other.IsRegister;
119 if (IsRegister)
120 RegisterName = Other.RegisterName;
121 else
122 StackOffset = Other.StackOffset;
123 Mask = Other.Mask;
124 return *this;
125 }
126 ~SIArgument() {
127 if (IsRegister)
128 RegisterName.~StringValue();
129 }
130
131 // Helper to create a register or stack argument.
132 static inline SIArgument createArgument(bool IsReg) {
133 if (IsReg)
134 return SIArgument(IsReg);
135 return SIArgument();
136 }
137
138private:
139 // Construct a register argument.
140 SIArgument(bool) : IsRegister(true), RegisterName() {}
141};
142
143template <> struct MappingTraits<SIArgument> {
144 static void mapping(IO &YamlIO, SIArgument &A) {
145 if (YamlIO.outputting()) {
146 if (A.IsRegister)
147 YamlIO.mapRequired(Key: "reg", Val&: A.RegisterName);
148 else
149 YamlIO.mapRequired(Key: "offset", Val&: A.StackOffset);
150 } else {
151 auto Keys = YamlIO.keys();
152 if (is_contained(Range&: Keys, Element: "reg")) {
153 A = SIArgument::createArgument(IsReg: true);
154 YamlIO.mapRequired(Key: "reg", Val&: A.RegisterName);
155 } else if (is_contained(Range&: Keys, Element: "offset"))
156 YamlIO.mapRequired(Key: "offset", Val&: A.StackOffset);
157 else
158 YamlIO.setError("missing required key 'reg' or 'offset'");
159 }
160 YamlIO.mapOptional(Key: "mask", Val&: A.Mask);
161 }
162 static const bool flow = true;
163};
164
165struct SIArgumentInfo {
166 std::optional<SIArgument> PrivateSegmentBuffer;
167 std::optional<SIArgument> DispatchPtr;
168 std::optional<SIArgument> QueuePtr;
169 std::optional<SIArgument> KernargSegmentPtr;
170 std::optional<SIArgument> DispatchID;
171 std::optional<SIArgument> FlatScratchInit;
172 std::optional<SIArgument> PrivateSegmentSize;
173 std::optional<SIArgument> FirstKernArgPreloadReg;
174
175 std::optional<SIArgument> WorkGroupIDX;
176 std::optional<SIArgument> WorkGroupIDY;
177 std::optional<SIArgument> WorkGroupIDZ;
178 std::optional<SIArgument> WorkGroupInfo;
179 std::optional<SIArgument> LDSKernelId;
180 std::optional<SIArgument> PrivateSegmentWaveByteOffset;
181
182 std::optional<SIArgument> ImplicitArgPtr;
183 std::optional<SIArgument> ImplicitBufferPtr;
184
185 std::optional<SIArgument> WorkItemIDX;
186 std::optional<SIArgument> WorkItemIDY;
187 std::optional<SIArgument> WorkItemIDZ;
188};
189
190template <> struct MappingTraits<SIArgumentInfo> {
191 static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
192 YamlIO.mapOptional(Key: "privateSegmentBuffer", Val&: AI.PrivateSegmentBuffer);
193 YamlIO.mapOptional(Key: "dispatchPtr", Val&: AI.DispatchPtr);
194 YamlIO.mapOptional(Key: "queuePtr", Val&: AI.QueuePtr);
195 YamlIO.mapOptional(Key: "kernargSegmentPtr", Val&: AI.KernargSegmentPtr);
196 YamlIO.mapOptional(Key: "dispatchID", Val&: AI.DispatchID);
197 YamlIO.mapOptional(Key: "flatScratchInit", Val&: AI.FlatScratchInit);
198 YamlIO.mapOptional(Key: "privateSegmentSize", Val&: AI.PrivateSegmentSize);
199 YamlIO.mapOptional(Key: "firstKernArgPreloadReg", Val&: AI.FirstKernArgPreloadReg);
200
201 YamlIO.mapOptional(Key: "workGroupIDX", Val&: AI.WorkGroupIDX);
202 YamlIO.mapOptional(Key: "workGroupIDY", Val&: AI.WorkGroupIDY);
203 YamlIO.mapOptional(Key: "workGroupIDZ", Val&: AI.WorkGroupIDZ);
204 YamlIO.mapOptional(Key: "workGroupInfo", Val&: AI.WorkGroupInfo);
205 YamlIO.mapOptional(Key: "LDSKernelId", Val&: AI.LDSKernelId);
206 YamlIO.mapOptional(Key: "privateSegmentWaveByteOffset",
207 Val&: AI.PrivateSegmentWaveByteOffset);
208
209 YamlIO.mapOptional(Key: "implicitArgPtr", Val&: AI.ImplicitArgPtr);
210 YamlIO.mapOptional(Key: "implicitBufferPtr", Val&: AI.ImplicitBufferPtr);
211
212 YamlIO.mapOptional(Key: "workItemIDX", Val&: AI.WorkItemIDX);
213 YamlIO.mapOptional(Key: "workItemIDY", Val&: AI.WorkItemIDY);
214 YamlIO.mapOptional(Key: "workItemIDZ", Val&: AI.WorkItemIDZ);
215 }
216};
217
218// Default to default mode for default calling convention.
219struct SIMode {
220 bool IEEE = true;
221 bool DX10Clamp = true;
222 bool FP32InputDenormals = true;
223 bool FP32OutputDenormals = true;
224 bool FP64FP16InputDenormals = true;
225 bool FP64FP16OutputDenormals = true;
226
227 SIMode() = default;
228
229 SIMode(const SIModeRegisterDefaults &Mode) {
230 IEEE = Mode.IEEE;
231 DX10Clamp = Mode.DX10Clamp;
232 FP32InputDenormals = Mode.FP32Denormals.Input != DenormalMode::PreserveSign;
233 FP32OutputDenormals =
234 Mode.FP32Denormals.Output != DenormalMode::PreserveSign;
235 FP64FP16InputDenormals =
236 Mode.FP64FP16Denormals.Input != DenormalMode::PreserveSign;
237 FP64FP16OutputDenormals =
238 Mode.FP64FP16Denormals.Output != DenormalMode::PreserveSign;
239 }
240
241 bool operator ==(const SIMode Other) const {
242 return IEEE == Other.IEEE &&
243 DX10Clamp == Other.DX10Clamp &&
244 FP32InputDenormals == Other.FP32InputDenormals &&
245 FP32OutputDenormals == Other.FP32OutputDenormals &&
246 FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
247 FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
248 }
249};
250
251template <> struct MappingTraits<SIMode> {
252 static void mapping(IO &YamlIO, SIMode &Mode) {
253 YamlIO.mapOptional(Key: "ieee", Val&: Mode.IEEE, Default: true);
254 YamlIO.mapOptional(Key: "dx10-clamp", Val&: Mode.DX10Clamp, Default: true);
255 YamlIO.mapOptional(Key: "fp32-input-denormals", Val&: Mode.FP32InputDenormals, Default: true);
256 YamlIO.mapOptional(Key: "fp32-output-denormals", Val&: Mode.FP32OutputDenormals, Default: true);
257 YamlIO.mapOptional(Key: "fp64-fp16-input-denormals", Val&: Mode.FP64FP16InputDenormals, Default: true);
258 YamlIO.mapOptional(Key: "fp64-fp16-output-denormals", Val&: Mode.FP64FP16OutputDenormals, Default: true);
259 }
260};
261
262struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
263 uint64_t ExplicitKernArgSize = 0;
264 Align MaxKernArgAlign;
265 uint32_t LDSSize = 0;
266 uint32_t GDSSize = 0;
267 Align DynLDSAlign;
268 bool IsEntryFunction = false;
269 bool IsChainFunction = false;
270 bool MemoryBound = false;
271 bool WaveLimiter = false;
272 bool HasSpilledSGPRs = false;
273 bool HasSpilledVGPRs = false;
274 uint16_t NumWaveDispatchSGPRs = 0;
275 uint16_t NumWaveDispatchVGPRs = 0;
276 uint32_t HighBitsOf32BitAddress = 0;
277
278 // TODO: 10 may be a better default since it's the maximum.
279 unsigned Occupancy = 0;
280
281 SmallVector<StringValue, 2> SpillPhysVGPRS;
282 SmallVector<StringValue> WWMReservedRegs;
283
284 StringValue ScratchRSrcReg = "$private_rsrc_reg";
285 StringValue FrameOffsetReg = "$fp_reg";
286 StringValue StackPtrOffsetReg = "$sp_reg";
287
288 unsigned BytesInStackArgArea = 0;
289 bool ReturnsVoid = true;
290
291 std::optional<SIArgumentInfo> ArgInfo;
292
293 unsigned PSInputAddr = 0;
294 unsigned PSInputEnable = 0;
295 unsigned MaxMemoryClusterDWords = DefaultMemoryClusterDWordsLimit;
296
297 SIMode Mode;
298 std::optional<FrameIndex> ScavengeFI;
299 StringValue VGPRForAGPRCopy;
300 StringValue SGPRForEXECCopy;
301 StringValue LongBranchReservedReg;
302
303 bool HasInitWholeWave = false;
304 bool IsWholeWaveFunction = false;
305
306 std::optional<unsigned> DynamicVGPRBlockSize;
307 unsigned ScratchReservedForDynamicVGPRs = 0;
308
309 unsigned NumKernargPreloadSGPRs = 0;
310
311 unsigned MinNumAGPRs = ~0u;
312
313 SIMachineFunctionInfo() = default;
314 SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
315 const TargetRegisterInfo &TRI,
316 const llvm::MachineFunction &MF);
317
318 void mappingImpl(yaml::IO &YamlIO) override;
319 ~SIMachineFunctionInfo() override = default;
320};
321
322template <> struct MappingTraits<SIMachineFunctionInfo> {
323 static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
324 YamlIO.mapOptional(Key: "explicitKernArgSize", Val&: MFI.ExplicitKernArgSize,
325 UINT64_C(0));
326 YamlIO.mapOptional(Key: "maxKernArgAlign", Val&: MFI.MaxKernArgAlign);
327 YamlIO.mapOptional(Key: "ldsSize", Val&: MFI.LDSSize, Default: 0u);
328 YamlIO.mapOptional(Key: "gdsSize", Val&: MFI.GDSSize, Default: 0u);
329 YamlIO.mapOptional(Key: "dynLDSAlign", Val&: MFI.DynLDSAlign, Default: Align());
330 YamlIO.mapOptional(Key: "isEntryFunction", Val&: MFI.IsEntryFunction, Default: false);
331 YamlIO.mapOptional(Key: "isChainFunction", Val&: MFI.IsChainFunction, Default: false);
332 YamlIO.mapOptional(Key: "memoryBound", Val&: MFI.MemoryBound, Default: false);
333 YamlIO.mapOptional(Key: "waveLimiter", Val&: MFI.WaveLimiter, Default: false);
334 YamlIO.mapOptional(Key: "hasSpilledSGPRs", Val&: MFI.HasSpilledSGPRs, Default: false);
335 YamlIO.mapOptional(Key: "hasSpilledVGPRs", Val&: MFI.HasSpilledVGPRs, Default: false);
336 YamlIO.mapOptional(Key: "numWaveDispatchSGPRs", Val&: MFI.NumWaveDispatchSGPRs, Default: false);
337 YamlIO.mapOptional(Key: "numWaveDispatchVGPRs", Val&: MFI.NumWaveDispatchVGPRs, Default: false);
338 YamlIO.mapOptional(Key: "scratchRSrcReg", Val&: MFI.ScratchRSrcReg,
339 Default: StringValue("$private_rsrc_reg"));
340 YamlIO.mapOptional(Key: "frameOffsetReg", Val&: MFI.FrameOffsetReg,
341 Default: StringValue("$fp_reg"));
342 YamlIO.mapOptional(Key: "stackPtrOffsetReg", Val&: MFI.StackPtrOffsetReg,
343 Default: StringValue("$sp_reg"));
344 YamlIO.mapOptional(Key: "bytesInStackArgArea", Val&: MFI.BytesInStackArgArea, Default: 0u);
345 YamlIO.mapOptional(Key: "returnsVoid", Val&: MFI.ReturnsVoid, Default: true);
346 YamlIO.mapOptional(Key: "argumentInfo", Val&: MFI.ArgInfo);
347 YamlIO.mapOptional(Key: "psInputAddr", Val&: MFI.PSInputAddr, Default: 0u);
348 YamlIO.mapOptional(Key: "psInputEnable", Val&: MFI.PSInputEnable, Default: 0u);
349 YamlIO.mapOptional(Key: "maxMemoryClusterDWords", Val&: MFI.MaxMemoryClusterDWords,
350 Default: DefaultMemoryClusterDWordsLimit);
351 YamlIO.mapOptional(Key: "mode", Val&: MFI.Mode, Default: SIMode());
352 YamlIO.mapOptional(Key: "highBitsOf32BitAddress",
353 Val&: MFI.HighBitsOf32BitAddress, Default: 0u);
354 YamlIO.mapOptional(Key: "occupancy", Val&: MFI.Occupancy, Default: 0);
355 YamlIO.mapOptional(Key: "spillPhysVGPRs", Val&: MFI.SpillPhysVGPRS);
356 YamlIO.mapOptional(Key: "wwmReservedRegs", Val&: MFI.WWMReservedRegs);
357 YamlIO.mapOptional(Key: "scavengeFI", Val&: MFI.ScavengeFI);
358 YamlIO.mapOptional(Key: "vgprForAGPRCopy", Val&: MFI.VGPRForAGPRCopy,
359 Default: StringValue()); // Don't print out when it's empty.
360 YamlIO.mapOptional(Key: "sgprForEXECCopy", Val&: MFI.SGPRForEXECCopy,
361 Default: StringValue()); // Don't print out when it's empty.
362 YamlIO.mapOptional(Key: "longBranchReservedReg", Val&: MFI.LongBranchReservedReg,
363 Default: StringValue());
364 YamlIO.mapOptional(Key: "hasInitWholeWave", Val&: MFI.HasInitWholeWave, Default: false);
365 YamlIO.mapOptional(Key: "dynamicVGPRBlockSize", Val&: MFI.DynamicVGPRBlockSize);
366 YamlIO.mapOptional(Key: "scratchReservedForDynamicVGPRs",
367 Val&: MFI.ScratchReservedForDynamicVGPRs, Default: 0);
368 YamlIO.mapOptional(Key: "numKernargPreloadSGPRs", Val&: MFI.NumKernargPreloadSGPRs, Default: 0);
369 YamlIO.mapOptional(Key: "isWholeWaveFunction", Val&: MFI.IsWholeWaveFunction, Default: false);
370 YamlIO.mapOptional(Key: "minNumAGPRs", Val&: MFI.MinNumAGPRs, Default: ~0u);
371 }
372};
373
374} // end namespace yaml
375
376// A CSR SGPR value can be preserved inside a callee using one of the following
377// methods.
378// 1. Copy to an unused scratch SGPR.
379// 2. Spill to a VGPR lane.
380// 3. Spill to memory via. a scratch VGPR.
381// class PrologEpilogSGPRSaveRestoreInfo represents the save/restore method used
382// for an SGPR at function prolog/epilog.
383enum class SGPRSaveKind : uint8_t {
384 COPY_TO_SCRATCH_SGPR,
385 SPILL_TO_VGPR_LANE,
386 SPILL_TO_MEM
387};
388
389class PrologEpilogSGPRSaveRestoreInfo {
390 SGPRSaveKind Kind;
391 union {
392 int Index;
393 Register Reg;
394 };
395
396public:
397 PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, int I) : Kind(K), Index(I) {}
398 PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
399 : Kind(K), Reg(R) {}
400 Register getReg() const { return Reg; }
401 int getIndex() const { return Index; }
402 SGPRSaveKind getKind() const { return Kind; }
403};
404
405struct VGPRBlock2IndexFunctor {
406 using argument_type = Register;
407 unsigned operator()(Register Reg) const {
408 assert(AMDGPU::VReg_1024RegClass.contains(Reg) && "Expecting a VGPR block");
409
410 const MCRegister FirstVGPRBlock = AMDGPU::VReg_1024RegClass.getRegister(i: 0);
411 return Reg - FirstVGPRBlock;
412 }
413};
414
415/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
416/// tells the hardware which interpolation parameters to load.
417class SIMachineFunctionInfo final : public AMDGPUMachineFunctionInfo,
418 private MachineRegisterInfo::Delegate {
419 friend class GCNTargetMachine;
420
421 // State of MODE register, assumed FP mode.
422 SIModeRegisterDefaults Mode;
423
424 // Registers that may be reserved for spilling purposes. These may be the same
425 // as the input registers.
426 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
427
428 // This is the unswizzled offset from the current dispatch's scratch wave
429 // base to the beginning of the current function's frame.
430 Register FrameOffsetReg = AMDGPU::FP_REG;
431
432 // This is an ABI register used in the non-entry calling convention to
433 // communicate the unswizzled offset from the current dispatch's scratch wave
434 // base to the beginning of the new function's frame.
435 Register StackPtrOffsetReg = AMDGPU::SP_REG;
436
437 // Registers that may be reserved when RA doesn't allocate enough
438 // registers to plan for the case where an indirect branch ends up
439 // being needed during branch relaxation.
440 Register LongBranchReservedReg;
441
442 AMDGPUFunctionArgInfo ArgInfo;
443
444 // Graphics info.
445 unsigned PSInputAddr = 0;
446 unsigned PSInputEnable = 0;
447
448 /// Number of bytes of arguments this function has on the stack. If the callee
449 /// is expected to restore the argument stack this should be a multiple of 16,
450 /// all usable during a tail call.
451 ///
452 /// The alternative would forbid tail call optimisation in some cases: if we
453 /// want to transfer control from a function with 8-bytes of stack-argument
454 /// space to a function with 16-bytes then misalignment of this value would
455 /// make a stack adjustment necessary, which could not be undone by the
456 /// callee.
457 unsigned BytesInStackArgArea = 0;
458
459 bool ReturnsVoid = true;
460
461 // A pair of default/requested minimum/maximum flat work group sizes.
462 // Minimum - first, maximum - second.
463 std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
464
465 // A pair of default/requested minimum/maximum number of waves per execution
466 // unit. Minimum - first, maximum - second.
467 std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
468
469 const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
470
471 // Default/requested number of work groups for the function.
472 SmallVector<unsigned> MaxNumWorkGroups = {0, 0, 0};
473
474 // Requested cluster dimensions.
475 AMDGPU::ClusterDimsAttr ClusterDims;
476
477private:
478 unsigned NumUserSGPRs = 0;
479 unsigned NumSystemSGPRs = 0;
480
481 unsigned NumWaveDispatchSGPRs = 0;
482 unsigned NumWaveDispatchVGPRs = 0;
483
484 bool HasSpilledSGPRs = false;
485 bool HasSpilledVGPRs = false;
486 bool HasNonSpillStackObjects = false;
487 bool IsStackRealigned = false;
488
489 unsigned NumSpilledSGPRs = 0;
490 unsigned NumSpilledVGPRs = 0;
491
492 unsigned DynamicVGPRBlockSize = 0;
493
494 // The size in bytes of the scratch space reserved for the CWSR trap handler
495 // to spill some of the dynamic VGPRs.
496 unsigned ScratchReservedForDynamicVGPRs = 0;
497
498 // Tracks information about user SGPRs that will be setup by hardware which
499 // will apply to all wavefronts of the grid.
500 GCNUserSGPRUsageInfo UserSGPRInfo;
501
502 // Feature bits required for inputs passed in system SGPRs.
503 bool WorkGroupIDX : 1; // Always initialized.
504 bool WorkGroupIDY : 1;
505 bool WorkGroupIDZ : 1;
506 bool WorkGroupInfo : 1;
507 bool LDSKernelId : 1;
508 bool PrivateSegmentWaveByteOffset : 1;
509
510 bool WorkItemIDX : 1; // Always initialized.
511 bool WorkItemIDY : 1;
512 bool WorkItemIDZ : 1;
513
514 // Pointer to where the ABI inserts special kernel arguments separate from the
515 // user arguments. This is an offset from the KernargSegmentPtr.
516 bool ImplicitArgPtr : 1;
517
518 /// Minimum number of AGPRs required to allocate in the function. Only
519 /// relevant for gfx90a-gfx950. For gfx908, this should be infinite.
520 unsigned MinNumAGPRs = ~0u;
521
522 // The hard-wired high half of the address of the global information table
523 // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
524 // current hardware only allows a 16 bit value.
525 unsigned GITPtrHigh;
526
527 unsigned HighBitsOf32BitAddress;
528
529 // Flags associated with the virtual registers.
530 IndexedMap<uint8_t, VirtReg2IndexFunctor> VRegFlags;
531
532 // Current recorded maximum possible occupancy.
533 unsigned Occupancy;
534
535 // Maximum number of dwords that can be clusterred during instruction
536 // scheduler stage.
537 unsigned MaxMemoryClusterDWords = DefaultMemoryClusterDWordsLimit;
538
539 MCPhysReg getNextUserSGPR() const;
540
541 MCPhysReg getNextSystemSGPR() const;
542
543 // MachineRegisterInfo callback functions to notify events.
544 void MRI_NoteNewVirtualRegister(Register Reg) override;
545 void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;
546
547public:
548 static bool MFMAVGPRForm;
549
550 struct VGPRSpillToAGPR {
551 SmallVector<MCPhysReg, 32> Lanes;
552 bool FullyAllocated = false;
553 bool IsDead = false;
554 };
555
556private:
557 // To track virtual VGPR + lane index for each subregister of the SGPR spilled
558 // to frameindex key during SILowerSGPRSpills pass.
559 DenseMap<int, std::vector<SIRegisterInfo::SpilledReg>>
560 SGPRSpillsToVirtualVGPRLanes;
561 // To track physical VGPR + lane index for CSR SGPR spills and special SGPRs
562 // like Frame Pointer identified during PrologEpilogInserter.
563 DenseMap<int, std::vector<SIRegisterInfo::SpilledReg>>
564 SGPRSpillsToPhysicalVGPRLanes;
565 unsigned NumVirtualVGPRSpillLanes = 0;
566 unsigned NumPhysicalVGPRSpillLanes = 0;
567 SmallVector<Register, 2> SpillVGPRs;
568 SmallVector<Register, 2> SpillPhysVGPRs;
569 using WWMSpillsMap = MapVector<Register, int>;
570 // To track the registers used in instructions that can potentially modify the
571 // inactive lanes. The WWM instructions and the writelane instructions for
572 // spilling SGPRs to VGPRs fall under such category of operations. The VGPRs
573 // modified by them should be spilled/restored at function prolog/epilog to
574 // avoid any undesired outcome. Each entry in this map holds a pair of values,
575 // the VGPR and its stack slot index.
576 WWMSpillsMap WWMSpills;
577
578 // Before allocation, the VGPR registers are partitioned into two distinct
579 // sets, the first one for WWM-values and the second set for non-WWM values.
580 // The latter set should be reserved during WWM-regalloc.
581 BitVector NonWWMRegMask;
582
583 using ReservedRegSet = SmallSetVector<Register, 8>;
584 // To track the VGPRs reserved for WWM instructions. They get stack slots
585 // later during PrologEpilogInserter and get added into the superset WWMSpills
586 // for actual spilling. A separate set makes the register reserved part and
587 // the serialization easier.
588 ReservedRegSet WWMReservedRegs;
589
590 bool IsWholeWaveFunction = false;
591
592 using PrologEpilogSGPRSpill =
593 std::pair<Register, PrologEpilogSGPRSaveRestoreInfo>;
594 // To track the SGPR spill method used for a CSR SGPR register during
595 // frame lowering. Even though the SGPR spills are handled during
596 // SILowerSGPRSpills pass, some special handling needed later during the
597 // PrologEpilogInserter.
598 SmallVector<PrologEpilogSGPRSpill, 3> PrologEpilogSGPRSpills;
599
600 // To save/restore EXEC MASK around WWM spills and copies.
601 Register SGPRForEXECCopy;
602
603 DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
604
605 // AGPRs used for VGPR spills.
606 SmallVector<MCPhysReg, 32> SpillAGPR;
607
608 // VGPRs used for AGPR spills.
609 SmallVector<MCPhysReg, 32> SpillVGPR;
610
611 // Emergency stack slot. Sometimes, we create this before finalizing the stack
612 // frame, so save it here and add it to the RegScavenger later.
613 std::optional<int> ScavengeFI;
614
615 // Map each VGPR CSR to the mask needed to save and restore it using block
616 // load/store instructions. Only used if the subtarget feature for VGPR block
617 // load/store is enabled.
618 IndexedMap<uint32_t, VGPRBlock2IndexFunctor> MaskForVGPRBlockOps;
619
620private:
621 Register VGPRForAGPRCopy;
622
623 bool allocateVirtualVGPRForSGPRSpills(MachineFunction &MF, int FI,
624 unsigned LaneIndex);
625 bool allocatePhysicalVGPRForSGPRSpills(MachineFunction &MF, int FI,
626 unsigned LaneIndex,
627 bool IsPrologEpilog);
628
629public:
630 Register getVGPRForAGPRCopy() const {
631 return VGPRForAGPRCopy;
632 }
633
634 void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
635 VGPRForAGPRCopy = NewVGPRForAGPRCopy;
636 }
637
638 bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const;
639
640 void setMaskForVGPRBlockOps(Register RegisterBlock, uint32_t Mask) {
641 MaskForVGPRBlockOps.grow(N: RegisterBlock);
642 MaskForVGPRBlockOps[RegisterBlock] = Mask;
643 }
644
645 uint32_t getMaskForVGPRBlockOps(Register RegisterBlock) const {
646 return MaskForVGPRBlockOps[RegisterBlock];
647 }
648
649 bool hasMaskForVGPRBlockOps(Register RegisterBlock) const {
650 return MaskForVGPRBlockOps.inBounds(N: RegisterBlock);
651 }
652
653public:
654 SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
655 SIMachineFunctionInfo(const Function &F, const GCNSubtarget *STI);
656
657 MachineFunctionInfo *
658 clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
659 const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
660 const override;
661
662 bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI,
663 const MachineFunction &MF,
664 PerFunctionMIParsingState &PFS,
665 SMDiagnostic &Error, SMRange &SourceRange);
666
667 void reserveWWMRegister(Register Reg) { WWMReservedRegs.insert(X: Reg); }
668 bool isWWMReg(Register Reg) const {
669 return Reg.isVirtual() ? checkFlag(Reg, Flag: AMDGPU::VirtRegFlag::WWM_REG)
670 : WWMReservedRegs.contains(key: Reg);
671 }
672
673 void updateNonWWMRegMask(BitVector &RegMask) { NonWWMRegMask = RegMask; }
674 BitVector getNonWWMRegMask() const { return NonWWMRegMask; }
675 void clearNonWWMRegAllocMask() { NonWWMRegMask.clear(); }
676
677 SIModeRegisterDefaults getMode() const { return Mode; }
678
679 ArrayRef<SIRegisterInfo::SpilledReg>
680 getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const {
681 auto I = SGPRSpillsToVirtualVGPRLanes.find(Val: FrameIndex);
682 return (I == SGPRSpillsToVirtualVGPRLanes.end())
683 ? ArrayRef<SIRegisterInfo::SpilledReg>()
684 : ArrayRef(I->second);
685 }
686
687 ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
688 ArrayRef<Register> getSGPRSpillPhysVGPRs() const { return SpillPhysVGPRs; }
689
690 const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
691 const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }
692
693 bool isWWMReservedRegister(Register Reg) const {
694 return WWMReservedRegs.contains(key: Reg);
695 }
696
697 bool isWholeWaveFunction() const { return IsWholeWaveFunction; }
698
699 ArrayRef<PrologEpilogSGPRSpill> getPrologEpilogSGPRSpills() const {
700 assert(is_sorted(PrologEpilogSGPRSpills, llvm::less_first()));
701 return PrologEpilogSGPRSpills;
702 }
703
704 GCNUserSGPRUsageInfo &getUserSGPRInfo() { return UserSGPRInfo; }
705
706 const GCNUserSGPRUsageInfo &getUserSGPRInfo() const { return UserSGPRInfo; }
707
708 void addToPrologEpilogSGPRSpills(Register Reg,
709 PrologEpilogSGPRSaveRestoreInfo SI) {
710 assert(!hasPrologEpilogSGPRSpillEntry(Reg));
711
712 // Insert a new entry in the right place to keep the vector in sorted order.
713 // This should be cheap since the vector is expected to be very short.
714 PrologEpilogSGPRSpills.insert(
715 I: upper_bound(
716 Range&: PrologEpilogSGPRSpills, Value&: Reg,
717 C: [](const auto &LHS, const auto &RHS) { return LHS < RHS.first; }),
718 Elt: std::make_pair(x&: Reg, y&: SI));
719 }
720
721 // Check if an entry created for \p Reg in PrologEpilogSGPRSpills. Return true
722 // on success and false otherwise.
723 bool hasPrologEpilogSGPRSpillEntry(Register Reg) const {
724 const auto *I = find_if(Range: PrologEpilogSGPRSpills, P: [&Reg](const auto &Spill) {
725 return Spill.first == Reg;
726 });
727 return I != PrologEpilogSGPRSpills.end();
728 }
729
730 // Get the scratch SGPR if allocated to save/restore \p Reg.
731 Register getScratchSGPRCopyDstReg(Register Reg) const {
732 const auto *I = find_if(Range: PrologEpilogSGPRSpills, P: [&Reg](const auto &Spill) {
733 return Spill.first == Reg;
734 });
735 if (I != PrologEpilogSGPRSpills.end() &&
736 I->second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
737 return I->second.getReg();
738
739 return AMDGPU::NoRegister;
740 }
741
742 // Get all scratch SGPRs allocated to copy/restore the SGPR spills.
743 void getAllScratchSGPRCopyDstRegs(SmallVectorImpl<Register> &Regs) const {
744 for (const auto &SI : PrologEpilogSGPRSpills) {
745 if (SI.second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
746 Regs.push_back(Elt: SI.second.getReg());
747 }
748 }
749
750 // Check if \p FI is allocated for any SGPR spill to a VGPR lane during PEI.
751 bool checkIndexInPrologEpilogSGPRSpills(int FI) const {
752 return find_if(Range: PrologEpilogSGPRSpills,
753 P: [FI](const std::pair<Register,
754 PrologEpilogSGPRSaveRestoreInfo> &SI) {
755 return SI.second.getKind() ==
756 SGPRSaveKind::SPILL_TO_VGPR_LANE &&
757 SI.second.getIndex() == FI;
758 }) != PrologEpilogSGPRSpills.end();
759 }
760
761 // Remove if an entry created for \p Reg.
762 void removePrologEpilogSGPRSpillEntry(Register Reg) {
763 auto I = find_if(Range&: PrologEpilogSGPRSpills,
764 P: [&Reg](const auto &Spill) { return Spill.first == Reg; });
765 if (I == PrologEpilogSGPRSpills.end())
766 return;
767
768 PrologEpilogSGPRSpills.erase(CI: I);
769 }
770
771 const PrologEpilogSGPRSaveRestoreInfo &
772 getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const {
773 const auto *I = find_if(Range: PrologEpilogSGPRSpills, P: [&Reg](const auto &Spill) {
774 return Spill.first == Reg;
775 });
776 assert(I != PrologEpilogSGPRSpills.end());
777
778 return I->second;
779 }
780
781 ArrayRef<SIRegisterInfo::SpilledReg>
782 getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const {
783 auto I = SGPRSpillsToPhysicalVGPRLanes.find(Val: FrameIndex);
784 return (I == SGPRSpillsToPhysicalVGPRLanes.end())
785 ? ArrayRef<SIRegisterInfo::SpilledReg>()
786 : ArrayRef(I->second);
787 }
788
789 void setFlag(Register Reg, uint8_t Flag) {
790 assert(Reg.isVirtual());
791 if (VRegFlags.inBounds(N: Reg))
792 VRegFlags[Reg] |= Flag;
793 }
794
795 bool checkFlag(Register Reg, uint8_t Flag) const {
796 if (Reg.isPhysical())
797 return false;
798
799 return VRegFlags.inBounds(N: Reg) && VRegFlags[Reg] & Flag;
800 }
801
802 bool hasVRegFlags() { return VRegFlags.size(); }
803
804 void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size = 4,
805 Align Alignment = Align(4));
806
807 void splitWWMSpillRegisters(
808 MachineFunction &MF,
809 SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
810 SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const;
811
812 ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
813 return SpillAGPR;
814 }
815
816 Register getSGPRForEXECCopy() const { return SGPRForEXECCopy; }
817
818 void setSGPRForEXECCopy(Register Reg) { SGPRForEXECCopy = Reg; }
819
820 ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
821 return SpillVGPR;
822 }
823
824 MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
825 auto I = VGPRToAGPRSpills.find(Val: FrameIndex);
826 return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
827 : I->second.Lanes[Lane];
828 }
829
830 void setVGPRToAGPRSpillDead(int FrameIndex) {
831 auto I = VGPRToAGPRSpills.find(Val: FrameIndex);
832 if (I != VGPRToAGPRSpills.end())
833 I->second.IsDead = true;
834 }
835
836 // To bring the allocated WWM registers in \p WWMVGPRs to the lowest available
837 // range.
838 void shiftWwmVGPRsToLowestRange(MachineFunction &MF,
839 SmallVectorImpl<Register> &WWMVGPRs,
840 BitVector &SavedVGPRs);
841
842 bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI,
843 bool SpillToPhysVGPRLane = false,
844 bool IsPrologEpilog = false);
845 bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
846
847 /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
848 /// to the default stack.
849 bool removeDeadFrameIndices(MachineFrameInfo &MFI,
850 bool ResetSGPRSpillStackIDs);
851
852 int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
853 std::optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
854
855 unsigned getBytesInStackArgArea() const {
856 return BytesInStackArgArea;
857 }
858
859 void setBytesInStackArgArea(unsigned Bytes) {
860 BytesInStackArgArea = Bytes;
861 }
862
863 bool isDynamicVGPREnabled() const { return DynamicVGPRBlockSize != 0; }
864 unsigned getDynamicVGPRBlockSize() const { return DynamicVGPRBlockSize; }
865
866 // This is only used if we need to save any dynamic VGPRs in scratch.
867 unsigned getScratchReservedForDynamicVGPRs() const {
868 return ScratchReservedForDynamicVGPRs;
869 }
870
871 void setScratchReservedForDynamicVGPRs(unsigned SizeInBytes) {
872 ScratchReservedForDynamicVGPRs = SizeInBytes;
873 }
874
875 // Add user SGPRs.
876 Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
877 Register addDispatchPtr(const SIRegisterInfo &TRI);
878 Register addQueuePtr(const SIRegisterInfo &TRI);
879 Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
880 Register addDispatchID(const SIRegisterInfo &TRI);
881 Register addFlatScratchInit(const SIRegisterInfo &TRI);
882 Register addPrivateSegmentSize(const SIRegisterInfo &TRI);
883 Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
884 Register addLDSKernelId();
885 SmallVectorImpl<MCRegister> *
886 addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC,
887 unsigned AllocSizeDWord, int KernArgIdx,
888 int PaddingSGPRs);
889
890 /// Increment user SGPRs used for padding the argument list only.
891 Register addReservedUserSGPR() {
892 Register Next = getNextUserSGPR();
893 ++NumUserSGPRs;
894 return Next;
895 }
896
897 // Add system SGPRs.
898 Register addWorkGroupIDX() {
899 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
900 NumSystemSGPRs += 1;
901 return ArgInfo.WorkGroupIDX.getRegister();
902 }
903
904 Register addWorkGroupIDY() {
905 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
906 NumSystemSGPRs += 1;
907 return ArgInfo.WorkGroupIDY.getRegister();
908 }
909
910 Register addWorkGroupIDZ() {
911 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
912 NumSystemSGPRs += 1;
913 return ArgInfo.WorkGroupIDZ.getRegister();
914 }
915
916 Register addWorkGroupInfo() {
917 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
918 NumSystemSGPRs += 1;
919 return ArgInfo.WorkGroupInfo.getRegister();
920 }
921
922 bool hasLDSKernelId() const { return LDSKernelId; }
923
924 // Add special VGPR inputs
925 void setWorkItemIDX(ArgDescriptor Arg) {
926 ArgInfo.WorkItemIDX = Arg;
927 }
928
929 void setWorkItemIDY(ArgDescriptor Arg) {
930 ArgInfo.WorkItemIDY = Arg;
931 }
932
933 void setWorkItemIDZ(ArgDescriptor Arg) {
934 ArgInfo.WorkItemIDZ = Arg;
935 }
936
937 Register addPrivateSegmentWaveByteOffset() {
938 ArgInfo.PrivateSegmentWaveByteOffset
939 = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
940 NumSystemSGPRs += 1;
941 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
942 }
943
944 void setPrivateSegmentWaveByteOffset(Register Reg) {
945 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
946 }
947
948 bool hasWorkGroupIDX() const {
949 return WorkGroupIDX;
950 }
951
952 bool hasWorkGroupIDY() const {
953 return WorkGroupIDY;
954 }
955
956 bool hasWorkGroupIDZ() const {
957 return WorkGroupIDZ;
958 }
959
960 bool hasWorkGroupInfo() const {
961 return WorkGroupInfo;
962 }
963
964 bool hasPrivateSegmentWaveByteOffset() const {
965 return PrivateSegmentWaveByteOffset;
966 }
967
968 bool hasWorkItemIDX() const {
969 return WorkItemIDX;
970 }
971
972 bool hasWorkItemIDY() const {
973 return WorkItemIDY;
974 }
975
976 bool hasWorkItemIDZ() const {
977 return WorkItemIDZ;
978 }
979
980 bool hasImplicitArgPtr() const {
981 return ImplicitArgPtr;
982 }
983
984 AMDGPUFunctionArgInfo &getArgInfo() {
985 return ArgInfo;
986 }
987
988 const AMDGPUFunctionArgInfo &getArgInfo() const {
989 return ArgInfo;
990 }
991
992 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
993 getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
994 return ArgInfo.getPreloadedValue(Value);
995 }
996
997 MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
998 const auto *Arg = std::get<0>(t: ArgInfo.getPreloadedValue(Value));
999 return Arg ? Arg->getRegister() : MCRegister();
1000 }
1001
1002 unsigned getGITPtrHigh() const {
1003 return GITPtrHigh;
1004 }
1005
1006 Register getGITPtrLoReg(const MachineFunction &MF) const;
1007
1008 uint32_t get32BitAddressHighBits() const {
1009 return HighBitsOf32BitAddress;
1010 }
1011
1012 unsigned getNumUserSGPRs() const {
1013 return NumUserSGPRs;
1014 }
1015
1016 unsigned getNumPreloadedSGPRs() const {
1017 return NumUserSGPRs + NumSystemSGPRs;
1018 }
1019
1020 unsigned getNumKernargPreloadedSGPRs() const {
1021 return UserSGPRInfo.getNumKernargPreloadSGPRs();
1022 }
1023
1024 unsigned getNumWaveDispatchSGPRs() const { return NumWaveDispatchSGPRs; }
1025
1026 void setNumWaveDispatchSGPRs(unsigned Count) { NumWaveDispatchSGPRs = Count; }
1027
1028 unsigned getNumWaveDispatchVGPRs() const { return NumWaveDispatchVGPRs; }
1029
1030 void setNumWaveDispatchVGPRs(unsigned Count) { NumWaveDispatchVGPRs = Count; }
1031
1032 Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
1033 if (ArgInfo.PrivateSegmentWaveByteOffset)
1034 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
1035 return MCRegister();
1036 }
1037
1038 /// Returns the physical register reserved for use as the resource
1039 /// descriptor for scratch accesses.
1040 Register getScratchRSrcReg() const {
1041 return ScratchRSrcReg;
1042 }
1043
1044 void setScratchRSrcReg(Register Reg) {
1045 assert(Reg != 0 && "Should never be unset");
1046 ScratchRSrcReg = Reg;
1047 }
1048
1049 Register getFrameOffsetReg() const {
1050 return FrameOffsetReg;
1051 }
1052
1053 void setFrameOffsetReg(Register Reg) {
1054 assert(Reg != 0 && "Should never be unset");
1055 FrameOffsetReg = Reg;
1056 }
1057
1058 void setStackPtrOffsetReg(Register Reg) {
1059 assert(Reg != 0 && "Should never be unset");
1060 StackPtrOffsetReg = Reg;
1061 }
1062
1063 void setLongBranchReservedReg(Register Reg) { LongBranchReservedReg = Reg; }
1064
1065 // Note the unset value for this is AMDGPU::SP_REG rather than
1066 // NoRegister. This is mostly a workaround for MIR tests where state that
1067 // can't be directly computed from the function is not preserved in serialized
1068 // MIR.
1069 Register getStackPtrOffsetReg() const {
1070 return StackPtrOffsetReg;
1071 }
1072
1073 Register getLongBranchReservedReg() const { return LongBranchReservedReg; }
1074
1075 Register getQueuePtrUserSGPR() const {
1076 return ArgInfo.QueuePtr.getRegister();
1077 }
1078
1079 Register getImplicitBufferPtrUserSGPR() const {
1080 return ArgInfo.ImplicitBufferPtr.getRegister();
1081 }
1082
1083 bool hasSpilledSGPRs() const {
1084 return HasSpilledSGPRs;
1085 }
1086
1087 void setHasSpilledSGPRs(bool Spill = true) {
1088 HasSpilledSGPRs = Spill;
1089 }
1090
1091 bool hasSpilledVGPRs() const {
1092 return HasSpilledVGPRs;
1093 }
1094
1095 void setHasSpilledVGPRs(bool Spill = true) {
1096 HasSpilledVGPRs = Spill;
1097 }
1098
1099 bool hasNonSpillStackObjects() const {
1100 return HasNonSpillStackObjects;
1101 }
1102
1103 void setHasNonSpillStackObjects(bool StackObject = true) {
1104 HasNonSpillStackObjects = StackObject;
1105 }
1106
1107 bool isStackRealigned() const {
1108 return IsStackRealigned;
1109 }
1110
1111 void setIsStackRealigned(bool Realigned = true) {
1112 IsStackRealigned = Realigned;
1113 }
1114
1115 unsigned getNumSpilledSGPRs() const {
1116 return NumSpilledSGPRs;
1117 }
1118
1119 unsigned getNumSpilledVGPRs() const {
1120 return NumSpilledVGPRs;
1121 }
1122
1123 void addToSpilledSGPRs(unsigned num) {
1124 NumSpilledSGPRs += num;
1125 }
1126
1127 void addToSpilledVGPRs(unsigned num) {
1128 NumSpilledVGPRs += num;
1129 }
1130
1131 unsigned getPSInputAddr() const {
1132 return PSInputAddr;
1133 }
1134
1135 unsigned getPSInputEnable() const {
1136 return PSInputEnable;
1137 }
1138
1139 bool isPSInputAllocated(unsigned Index) const {
1140 return PSInputAddr & (1 << Index);
1141 }
1142
1143 void markPSInputAllocated(unsigned Index) {
1144 PSInputAddr |= 1 << Index;
1145 }
1146
1147 void markPSInputEnabled(unsigned Index) {
1148 PSInputEnable |= 1 << Index;
1149 }
1150
1151 bool returnsVoid() const {
1152 return ReturnsVoid;
1153 }
1154
1155 void setIfReturnsVoid(bool Value) {
1156 ReturnsVoid = Value;
1157 }
1158
1159 /// \returns A pair of default/requested minimum/maximum flat work group sizes
1160 /// for this function.
1161 std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
1162 return FlatWorkGroupSizes;
1163 }
1164
1165 /// \returns Default/requested minimum flat work group size for this function.
1166 unsigned getMinFlatWorkGroupSize() const {
1167 return FlatWorkGroupSizes.first;
1168 }
1169
1170 /// \returns Default/requested maximum flat work group size for this function.
1171 unsigned getMaxFlatWorkGroupSize() const {
1172 return FlatWorkGroupSizes.second;
1173 }
1174
1175 /// \returns A pair of default/requested minimum/maximum number of waves per
1176 /// execution unit.
1177 std::pair<unsigned, unsigned> getWavesPerEU() const {
1178 return WavesPerEU;
1179 }
1180
1181 /// \returns Default/requested minimum number of waves per execution unit.
1182 unsigned getMinWavesPerEU() const {
1183 return WavesPerEU.first;
1184 }
1185
1186 /// \returns Default/requested maximum number of waves per execution unit.
1187 unsigned getMaxWavesPerEU() const {
1188 return WavesPerEU.second;
1189 }
1190
1191 const AMDGPUGWSResourcePseudoSourceValue *
1192 getGWSPSV(const AMDGPUTargetMachine &TM) {
1193 return &GWSResourcePSV;
1194 }
1195
1196 unsigned getOccupancy() const {
1197 return Occupancy;
1198 }
1199
1200 unsigned getMinAllowedOccupancy() const {
1201 if (!isMemoryBound() && !needsWaveLimiter())
1202 return Occupancy;
1203 return (Occupancy < 4) ? Occupancy : 4;
1204 }
1205
1206 void limitOccupancy(const MachineFunction &MF);
1207
1208 void limitOccupancy(unsigned Limit) {
1209 if (Occupancy > Limit)
1210 Occupancy = Limit;
1211 }
1212
1213 void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
1214 if (Occupancy < Limit)
1215 Occupancy = Limit;
1216 limitOccupancy(MF);
1217 }
1218
1219 unsigned getMaxMemoryClusterDWords() const { return MaxMemoryClusterDWords; }
1220
1221 unsigned getMinNumAGPRs() const { return MinNumAGPRs; }
1222
1223 /// Return true if an MFMA that requires at least \p NumRegs should select to
1224 /// the AGPR form, instead of the VGPR form.
1225 bool selectAGPRFormMFMA(unsigned NumRegs) const {
1226 return !MFMAVGPRForm && getMinNumAGPRs() >= NumRegs;
1227 }
1228
1229 // \returns true if a function has a use of AGPRs via inline asm or
1230 // has a call which may use it.
1231 bool mayUseAGPRs(const Function &F) const;
1232
1233 /// \returns Default/requested number of work groups for this function.
1234 SmallVector<unsigned> getMaxNumWorkGroups() const { return MaxNumWorkGroups; }
1235
1236 unsigned getMaxNumWorkGroupsX() const { return MaxNumWorkGroups[0]; }
1237 unsigned getMaxNumWorkGroupsY() const { return MaxNumWorkGroups[1]; }
1238 unsigned getMaxNumWorkGroupsZ() const { return MaxNumWorkGroups[2]; }
1239
1240 AMDGPU::ClusterDimsAttr getClusterDims() const { return ClusterDims; }
1241};
1242
1243} // end namespace llvm
1244
1245#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
1246