1//==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15
16#include "AMDGPUArgumentUsageInfo.h"
17#include "AMDGPUMachineFunctionInfo.h"
18#include "AMDGPUTargetMachine.h"
19#include "GCNSubtarget.h"
20#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
21#include "SIInstrInfo.h"
22#include "SIModeRegisterDefaults.h"
23#include "llvm/ADT/SetVector.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/CodeGen/MIRYamlMapping.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/Support/raw_ostream.h"
28#include <optional>
29
30namespace llvm {
31
32class MachineFrameInfo;
33class MachineFunction;
34class SIMachineFunctionInfo;
35class SIRegisterInfo;
36class MCRegisterClass;
37using TargetRegisterClass = MCRegisterClass;
38
39class AMDGPUPseudoSourceValue : public PseudoSourceValue {
40public:
41 enum AMDGPUPSVKind : unsigned {
42 PSVImage = PseudoSourceValue::TargetCustom,
43 GWSResource
44 };
45
46protected:
47 AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
48 : PseudoSourceValue(Kind, TM) {}
49
50public:
51 bool isConstant(const MachineFrameInfo *) const override {
52 // This should probably be true for most images, but we will start by being
53 // conservative.
54 return false;
55 }
56
57 bool isAliased(const MachineFrameInfo *) const override {
58 return true;
59 }
60
61 bool mayAlias(const MachineFrameInfo *) const override {
62 return true;
63 }
64};
65
66class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
67public:
68 explicit AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
69 : AMDGPUPseudoSourceValue(GWSResource, TM) {}
70
71 static bool classof(const PseudoSourceValue *V) {
72 return V->kind() == GWSResource;
73 }
74
75 // These are inaccessible memory from IR.
76 bool isAliased(const MachineFrameInfo *) const override {
77 return false;
78 }
79
80 // These are inaccessible memory from IR.
81 bool mayAlias(const MachineFrameInfo *) const override {
82 return false;
83 }
84
85 void printCustom(raw_ostream &OS) const override {
86 OS << "GWSResource";
87 }
88};
89
90namespace yaml {
91
92struct SIArgument {
93 bool IsRegister;
94 union {
95 StringValue RegisterName;
96 unsigned StackOffset;
97 };
98 std::optional<unsigned> Mask;
99
100 // Default constructor, which creates a stack argument.
101 SIArgument() : IsRegister(false), StackOffset(0) {}
102 SIArgument(const SIArgument &Other) {
103 IsRegister = Other.IsRegister;
104 if (IsRegister)
105 new (&RegisterName) StringValue(Other.RegisterName);
106 else
107 StackOffset = Other.StackOffset;
108 Mask = Other.Mask;
109 }
110 SIArgument &operator=(const SIArgument &Other) {
111 // Default-construct or destruct the old RegisterName in case of switching
112 // union members
113 if (IsRegister != Other.IsRegister) {
114 if (Other.IsRegister)
115 new (&RegisterName) StringValue();
116 else
117 RegisterName.~StringValue();
118 }
119 IsRegister = Other.IsRegister;
120 if (IsRegister)
121 RegisterName = Other.RegisterName;
122 else
123 StackOffset = Other.StackOffset;
124 Mask = Other.Mask;
125 return *this;
126 }
127 ~SIArgument() {
128 if (IsRegister)
129 RegisterName.~StringValue();
130 }
131
132 // Helper to create a register or stack argument.
133 static inline SIArgument createArgument(bool IsReg) {
134 if (IsReg)
135 return SIArgument(IsReg);
136 return SIArgument();
137 }
138
139private:
140 // Construct a register argument.
141 SIArgument(bool) : IsRegister(true), RegisterName() {}
142};
143
144template <> struct MappingTraits<SIArgument> {
145 static void mapping(IO &YamlIO, SIArgument &A) {
146 if (YamlIO.outputting()) {
147 if (A.IsRegister)
148 YamlIO.mapRequired(Key: "reg", Val&: A.RegisterName);
149 else
150 YamlIO.mapRequired(Key: "offset", Val&: A.StackOffset);
151 } else {
152 auto Keys = YamlIO.keys();
153 if (is_contained(Range&: Keys, Element: "reg")) {
154 A = SIArgument::createArgument(IsReg: true);
155 YamlIO.mapRequired(Key: "reg", Val&: A.RegisterName);
156 } else if (is_contained(Range&: Keys, Element: "offset"))
157 YamlIO.mapRequired(Key: "offset", Val&: A.StackOffset);
158 else
159 YamlIO.setError("missing required key 'reg' or 'offset'");
160 }
161 YamlIO.mapOptional(Key: "mask", Val&: A.Mask);
162 }
163 static const bool flow = true;
164};
165
166struct SIArgumentInfo {
167 std::optional<SIArgument> PrivateSegmentBuffer;
168 std::optional<SIArgument> DispatchPtr;
169 std::optional<SIArgument> QueuePtr;
170 std::optional<SIArgument> KernargSegmentPtr;
171 std::optional<SIArgument> DispatchID;
172 std::optional<SIArgument> FlatScratchInit;
173 std::optional<SIArgument> PrivateSegmentSize;
174 std::optional<SIArgument> FirstKernArgPreloadReg;
175
176 std::optional<SIArgument> WorkGroupIDX;
177 std::optional<SIArgument> WorkGroupIDY;
178 std::optional<SIArgument> WorkGroupIDZ;
179 std::optional<SIArgument> WorkGroupInfo;
180 std::optional<SIArgument> LDSKernelId;
181 std::optional<SIArgument> PrivateSegmentWaveByteOffset;
182
183 std::optional<SIArgument> ImplicitArgPtr;
184 std::optional<SIArgument> ImplicitBufferPtr;
185
186 std::optional<SIArgument> WorkItemIDX;
187 std::optional<SIArgument> WorkItemIDY;
188 std::optional<SIArgument> WorkItemIDZ;
189};
190
191template <> struct MappingTraits<SIArgumentInfo> {
192 static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
193 YamlIO.mapOptional(Key: "privateSegmentBuffer", Val&: AI.PrivateSegmentBuffer);
194 YamlIO.mapOptional(Key: "dispatchPtr", Val&: AI.DispatchPtr);
195 YamlIO.mapOptional(Key: "queuePtr", Val&: AI.QueuePtr);
196 YamlIO.mapOptional(Key: "kernargSegmentPtr", Val&: AI.KernargSegmentPtr);
197 YamlIO.mapOptional(Key: "dispatchID", Val&: AI.DispatchID);
198 YamlIO.mapOptional(Key: "flatScratchInit", Val&: AI.FlatScratchInit);
199 YamlIO.mapOptional(Key: "privateSegmentSize", Val&: AI.PrivateSegmentSize);
200 YamlIO.mapOptional(Key: "firstKernArgPreloadReg", Val&: AI.FirstKernArgPreloadReg);
201
202 YamlIO.mapOptional(Key: "workGroupIDX", Val&: AI.WorkGroupIDX);
203 YamlIO.mapOptional(Key: "workGroupIDY", Val&: AI.WorkGroupIDY);
204 YamlIO.mapOptional(Key: "workGroupIDZ", Val&: AI.WorkGroupIDZ);
205 YamlIO.mapOptional(Key: "workGroupInfo", Val&: AI.WorkGroupInfo);
206 YamlIO.mapOptional(Key: "LDSKernelId", Val&: AI.LDSKernelId);
207 YamlIO.mapOptional(Key: "privateSegmentWaveByteOffset",
208 Val&: AI.PrivateSegmentWaveByteOffset);
209
210 YamlIO.mapOptional(Key: "implicitArgPtr", Val&: AI.ImplicitArgPtr);
211 YamlIO.mapOptional(Key: "implicitBufferPtr", Val&: AI.ImplicitBufferPtr);
212
213 YamlIO.mapOptional(Key: "workItemIDX", Val&: AI.WorkItemIDX);
214 YamlIO.mapOptional(Key: "workItemIDY", Val&: AI.WorkItemIDY);
215 YamlIO.mapOptional(Key: "workItemIDZ", Val&: AI.WorkItemIDZ);
216 }
217};
218
219// Default to default mode for default calling convention.
220struct SIMode {
221 bool IEEE = true;
222 bool DX10Clamp = true;
223 bool FP32InputDenormals = true;
224 bool FP32OutputDenormals = true;
225 bool FP64FP16InputDenormals = true;
226 bool FP64FP16OutputDenormals = true;
227
228 SIMode() = default;
229
230 SIMode(const SIModeRegisterDefaults &Mode) {
231 IEEE = Mode.IEEE;
232 DX10Clamp = Mode.DX10Clamp;
233 FP32InputDenormals = Mode.FP32Denormals.Input != DenormalMode::PreserveSign;
234 FP32OutputDenormals =
235 Mode.FP32Denormals.Output != DenormalMode::PreserveSign;
236 FP64FP16InputDenormals =
237 Mode.FP64FP16Denormals.Input != DenormalMode::PreserveSign;
238 FP64FP16OutputDenormals =
239 Mode.FP64FP16Denormals.Output != DenormalMode::PreserveSign;
240 }
241
242 bool operator ==(const SIMode Other) const {
243 return IEEE == Other.IEEE &&
244 DX10Clamp == Other.DX10Clamp &&
245 FP32InputDenormals == Other.FP32InputDenormals &&
246 FP32OutputDenormals == Other.FP32OutputDenormals &&
247 FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
248 FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
249 }
250};
251
252template <> struct MappingTraits<SIMode> {
253 static void mapping(IO &YamlIO, SIMode &Mode) {
254 YamlIO.mapOptional(Key: "ieee", Val&: Mode.IEEE, Default: true);
255 YamlIO.mapOptional(Key: "dx10-clamp", Val&: Mode.DX10Clamp, Default: true);
256 YamlIO.mapOptional(Key: "fp32-input-denormals", Val&: Mode.FP32InputDenormals, Default: true);
257 YamlIO.mapOptional(Key: "fp32-output-denormals", Val&: Mode.FP32OutputDenormals, Default: true);
258 YamlIO.mapOptional(Key: "fp64-fp16-input-denormals", Val&: Mode.FP64FP16InputDenormals, Default: true);
259 YamlIO.mapOptional(Key: "fp64-fp16-output-denormals", Val&: Mode.FP64FP16OutputDenormals, Default: true);
260 }
261};
262
263struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
264 uint64_t ExplicitKernArgSize = 0;
265 Align MaxKernArgAlign;
266 uint32_t LDSSize = 0;
267 uint32_t GDSSize = 0;
268 Align DynLDSAlign;
269 bool IsEntryFunction = false;
270 bool IsChainFunction = false;
271 bool MemoryBound = false;
272 bool WaveLimiter = false;
273 bool HasSpilledSGPRs = false;
274 bool HasSpilledVGPRs = false;
275 uint16_t NumWaveDispatchSGPRs = 0;
276 uint16_t NumWaveDispatchVGPRs = 0;
277 uint32_t HighBitsOf32BitAddress = 0;
278
279 // TODO: 10 may be a better default since it's the maximum.
280 unsigned Occupancy = 0;
281
282 SmallVector<StringValue, 2> SpillPhysVGPRS;
283 SmallVector<StringValue> WWMReservedRegs;
284
285 StringValue ScratchRSrcReg = "$private_rsrc_reg";
286 StringValue FrameOffsetReg = "$fp_reg";
287 StringValue StackPtrOffsetReg = "$sp_reg";
288
289 unsigned BytesInStackArgArea = 0;
290 bool ReturnsVoid = true;
291
292 std::optional<SIArgumentInfo> ArgInfo;
293
294 unsigned PSInputAddr = 0;
295 unsigned PSInputEnable = 0;
296 unsigned MaxMemoryClusterDWords = DefaultMemoryClusterDWordsLimit;
297
298 SIMode Mode;
299 std::optional<FrameIndex> ScavengeFI;
300 StringValue VGPRForAGPRCopy;
301 StringValue SGPRForEXECCopy;
302 StringValue LongBranchReservedReg;
303
304 bool HasInitWholeWave = false;
305 bool IsWholeWaveFunction = false;
306
307 std::optional<unsigned> DynamicVGPRBlockSize;
308 unsigned ScratchReservedForDynamicVGPRs = 0;
309
310 unsigned NumKernargPreloadSGPRs = 0;
311
312 unsigned MinNumAGPRs = ~0u;
313
314 SIMachineFunctionInfo() = default;
315 SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
316 const TargetRegisterInfo &TRI,
317 const llvm::MachineFunction &MF);
318
319 void mappingImpl(yaml::IO &YamlIO) override;
320 ~SIMachineFunctionInfo() override = default;
321};
322
323template <> struct MappingTraits<SIMachineFunctionInfo> {
324 static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
325 YamlIO.mapOptional(Key: "explicitKernArgSize", Val&: MFI.ExplicitKernArgSize,
326 UINT64_C(0));
327 YamlIO.mapOptional(Key: "maxKernArgAlign", Val&: MFI.MaxKernArgAlign);
328 YamlIO.mapOptional(Key: "ldsSize", Val&: MFI.LDSSize, Default: 0u);
329 YamlIO.mapOptional(Key: "gdsSize", Val&: MFI.GDSSize, Default: 0u);
330 YamlIO.mapOptional(Key: "dynLDSAlign", Val&: MFI.DynLDSAlign, Default: Align());
331 YamlIO.mapOptional(Key: "isEntryFunction", Val&: MFI.IsEntryFunction, Default: false);
332 YamlIO.mapOptional(Key: "isChainFunction", Val&: MFI.IsChainFunction, Default: false);
333 YamlIO.mapOptional(Key: "memoryBound", Val&: MFI.MemoryBound, Default: false);
334 YamlIO.mapOptional(Key: "waveLimiter", Val&: MFI.WaveLimiter, Default: false);
335 YamlIO.mapOptional(Key: "hasSpilledSGPRs", Val&: MFI.HasSpilledSGPRs, Default: false);
336 YamlIO.mapOptional(Key: "hasSpilledVGPRs", Val&: MFI.HasSpilledVGPRs, Default: false);
337 YamlIO.mapOptional(Key: "numWaveDispatchSGPRs", Val&: MFI.NumWaveDispatchSGPRs, Default: false);
338 YamlIO.mapOptional(Key: "numWaveDispatchVGPRs", Val&: MFI.NumWaveDispatchVGPRs, Default: false);
339 YamlIO.mapOptional(Key: "scratchRSrcReg", Val&: MFI.ScratchRSrcReg,
340 Default: StringValue("$private_rsrc_reg"));
341 YamlIO.mapOptional(Key: "frameOffsetReg", Val&: MFI.FrameOffsetReg,
342 Default: StringValue("$fp_reg"));
343 YamlIO.mapOptional(Key: "stackPtrOffsetReg", Val&: MFI.StackPtrOffsetReg,
344 Default: StringValue("$sp_reg"));
345 YamlIO.mapOptional(Key: "bytesInStackArgArea", Val&: MFI.BytesInStackArgArea, Default: 0u);
346 YamlIO.mapOptional(Key: "returnsVoid", Val&: MFI.ReturnsVoid, Default: true);
347 YamlIO.mapOptional(Key: "argumentInfo", Val&: MFI.ArgInfo);
348 YamlIO.mapOptional(Key: "psInputAddr", Val&: MFI.PSInputAddr, Default: 0u);
349 YamlIO.mapOptional(Key: "psInputEnable", Val&: MFI.PSInputEnable, Default: 0u);
350 YamlIO.mapOptional(Key: "maxMemoryClusterDWords", Val&: MFI.MaxMemoryClusterDWords,
351 Default: DefaultMemoryClusterDWordsLimit);
352 YamlIO.mapOptional(Key: "mode", Val&: MFI.Mode, Default: SIMode());
353 YamlIO.mapOptional(Key: "highBitsOf32BitAddress",
354 Val&: MFI.HighBitsOf32BitAddress, Default: 0u);
355 YamlIO.mapOptional(Key: "occupancy", Val&: MFI.Occupancy, Default: 0);
356 YamlIO.mapOptional(Key: "spillPhysVGPRs", Val&: MFI.SpillPhysVGPRS);
357 YamlIO.mapOptional(Key: "wwmReservedRegs", Val&: MFI.WWMReservedRegs);
358 YamlIO.mapOptional(Key: "scavengeFI", Val&: MFI.ScavengeFI);
359 YamlIO.mapOptional(Key: "vgprForAGPRCopy", Val&: MFI.VGPRForAGPRCopy,
360 Default: StringValue()); // Don't print out when it's empty.
361 YamlIO.mapOptional(Key: "sgprForEXECCopy", Val&: MFI.SGPRForEXECCopy,
362 Default: StringValue()); // Don't print out when it's empty.
363 YamlIO.mapOptional(Key: "longBranchReservedReg", Val&: MFI.LongBranchReservedReg,
364 Default: StringValue());
365 YamlIO.mapOptional(Key: "hasInitWholeWave", Val&: MFI.HasInitWholeWave, Default: false);
366 YamlIO.mapOptional(Key: "dynamicVGPRBlockSize", Val&: MFI.DynamicVGPRBlockSize);
367 YamlIO.mapOptional(Key: "scratchReservedForDynamicVGPRs",
368 Val&: MFI.ScratchReservedForDynamicVGPRs, Default: 0);
369 YamlIO.mapOptional(Key: "numKernargPreloadSGPRs", Val&: MFI.NumKernargPreloadSGPRs, Default: 0);
370 YamlIO.mapOptional(Key: "isWholeWaveFunction", Val&: MFI.IsWholeWaveFunction, Default: false);
371 YamlIO.mapOptional(Key: "minNumAGPRs", Val&: MFI.MinNumAGPRs, Default: ~0u);
372 }
373};
374
375} // end namespace yaml
376
377// A CSR SGPR value can be preserved inside a callee using one of the following
378// methods.
379// 1. Copy to an unused scratch SGPR.
380// 2. Spill to a VGPR lane.
381// 3. Spill to memory via. a scratch VGPR.
382// class PrologEpilogSGPRSaveRestoreInfo represents the save/restore method used
383// for an SGPR at function prolog/epilog.
384enum class SGPRSaveKind : uint8_t {
385 COPY_TO_SCRATCH_SGPR,
386 SPILL_TO_VGPR_LANE,
387 SPILL_TO_MEM
388};
389
390class PrologEpilogSGPRSaveRestoreInfo {
391 SGPRSaveKind Kind;
392 union {
393 int Index;
394 Register Reg;
395 };
396
397public:
398 PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, int I) : Kind(K), Index(I) {}
399 PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
400 : Kind(K), Reg(R) {}
401 Register getReg() const { return Reg; }
402 int getIndex() const { return Index; }
403 SGPRSaveKind getKind() const { return Kind; }
404};
405
406struct VGPRBlock2IndexFunctor {
407 using argument_type = Register;
408 unsigned operator()(Register Reg) const {
409 assert(AMDGPU::VReg_1024RegClass.contains(Reg) && "Expecting a VGPR block");
410
411 const MCRegister FirstVGPRBlock = AMDGPU::VReg_1024RegClass.getRegister(i: 0);
412 return Reg - FirstVGPRBlock;
413 }
414};
415
416/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
417/// tells the hardware which interpolation parameters to load.
418class SIMachineFunctionInfo final : public AMDGPUMachineFunctionInfo,
419 private MachineRegisterInfo::Delegate {
420 friend class GCNTargetMachine;
421
422 // State of MODE register, assumed FP mode.
423 SIModeRegisterDefaults Mode;
424
425 // Registers that may be reserved for spilling purposes. These may be the same
426 // as the input registers.
427 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
428
429 // This is the unswizzled offset from the current dispatch's scratch wave
430 // base to the beginning of the current function's frame.
431 Register FrameOffsetReg = AMDGPU::FP_REG;
432
433 // This is an ABI register used in the non-entry calling convention to
434 // communicate the unswizzled offset from the current dispatch's scratch wave
435 // base to the beginning of the new function's frame.
436 Register StackPtrOffsetReg = AMDGPU::SP_REG;
437
438 // Registers that may be reserved when RA doesn't allocate enough
439 // registers to plan for the case where an indirect branch ends up
440 // being needed during branch relaxation.
441 Register LongBranchReservedReg;
442
443 AMDGPUFunctionArgInfo ArgInfo;
444
445 // Graphics info.
446 unsigned PSInputAddr = 0;
447 unsigned PSInputEnable = 0;
448
449 /// Number of bytes of arguments this function has on the stack. If the callee
450 /// is expected to restore the argument stack this should be a multiple of 16,
451 /// all usable during a tail call.
452 ///
453 /// The alternative would forbid tail call optimisation in some cases: if we
454 /// want to transfer control from a function with 8-bytes of stack-argument
455 /// space to a function with 16-bytes then misalignment of this value would
456 /// make a stack adjustment necessary, which could not be undone by the
457 /// callee.
458 unsigned BytesInStackArgArea = 0;
459
460 bool ReturnsVoid = true;
461
462 // A pair of default/requested minimum/maximum flat work group sizes.
463 // Minimum - first, maximum - second.
464 std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
465
466 // A pair of default/requested minimum/maximum number of waves per execution
467 // unit. Minimum - first, maximum - second.
468 std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
469
470 const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
471
472 // Default/requested number of work groups for the function.
473 SmallVector<unsigned> MaxNumWorkGroups = {0, 0, 0};
474
475 // Requested cluster dimensions.
476 AMDGPU::ClusterDimsAttr ClusterDims;
477
478private:
479 unsigned NumUserSGPRs = 0;
480 unsigned NumSystemSGPRs = 0;
481
482 unsigned NumWaveDispatchSGPRs = 0;
483 unsigned NumWaveDispatchVGPRs = 0;
484
485 bool HasSpilledSGPRs = false;
486 bool HasSpilledVGPRs = false;
487 bool HasNonSpillStackObjects = false;
488 bool IsStackRealigned = false;
489
490 unsigned NumSpilledSGPRs = 0;
491 unsigned NumSpilledVGPRs = 0;
492
493 unsigned DynamicVGPRBlockSize = 0;
494
495 // The size in bytes of the scratch space reserved for the CWSR trap handler
496 // to spill some of the dynamic VGPRs.
497 unsigned ScratchReservedForDynamicVGPRs = 0;
498
499 // Tracks information about user SGPRs that will be setup by hardware which
500 // will apply to all wavefronts of the grid.
501 GCNUserSGPRUsageInfo UserSGPRInfo;
502
503 // Feature bits required for inputs passed in system SGPRs.
504 bool WorkGroupIDX : 1; // Always initialized.
505 bool WorkGroupIDY : 1;
506 bool WorkGroupIDZ : 1;
507 bool WorkGroupInfo : 1;
508 bool LDSKernelId : 1;
509 bool PrivateSegmentWaveByteOffset : 1;
510
511 bool WorkItemIDX : 1; // Always initialized.
512 bool WorkItemIDY : 1;
513 bool WorkItemIDZ : 1;
514
515 // Pointer to where the ABI inserts special kernel arguments separate from the
516 // user arguments. This is an offset from the KernargSegmentPtr.
517 bool ImplicitArgPtr : 1;
518
519 /// Minimum number of AGPRs required to allocate in the function. Only
520 /// relevant for gfx90a-gfx950. For gfx908, this should be infinite.
521 unsigned MinNumAGPRs = ~0u;
522
523 // The hard-wired high half of the address of the global information table
524 // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
525 // current hardware only allows a 16 bit value.
526 unsigned GITPtrHigh;
527
528 unsigned HighBitsOf32BitAddress;
529
530 // Flags associated with the virtual registers.
531 IndexedMap<uint8_t, VirtReg2IndexFunctor> VRegFlags;
532
533 // Current recorded maximum possible occupancy.
534 unsigned Occupancy;
535
536 // Maximum number of dwords that can be clusterred during instruction
537 // scheduler stage.
538 unsigned MaxMemoryClusterDWords = DefaultMemoryClusterDWordsLimit;
539
540 MCPhysReg getNextUserSGPR() const;
541
542 MCPhysReg getNextSystemSGPR() const;
543
544 // MachineRegisterInfo callback functions to notify events.
545 void MRI_NoteNewVirtualRegister(Register Reg) override;
546 void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;
547
548public:
549 static bool MFMAVGPRForm;
550
551 struct VGPRSpillToAGPR {
552 SmallVector<MCPhysReg, 32> Lanes;
553 bool FullyAllocated = false;
554 bool IsDead = false;
555 };
556
557private:
558 // To track virtual VGPR + lane index for each subregister of the SGPR spilled
559 // to frameindex key during SILowerSGPRSpills pass.
560 DenseMap<int, std::vector<SIRegisterInfo::SpilledReg>>
561 SGPRSpillsToVirtualVGPRLanes;
562 // To track physical VGPR + lane index for CSR SGPR spills and special SGPRs
563 // like Frame Pointer identified during PrologEpilogInserter.
564 DenseMap<int, std::vector<SIRegisterInfo::SpilledReg>>
565 SGPRSpillsToPhysicalVGPRLanes;
566 unsigned NumVirtualVGPRSpillLanes = 0;
567 unsigned NumPhysicalVGPRSpillLanes = 0;
568 SmallVector<Register, 2> SpillVGPRs;
569 SmallVector<Register, 2> SpillPhysVGPRs;
570 using WWMSpillsMap = MapVector<Register, int>;
571 // To track the registers used in instructions that can potentially modify the
572 // inactive lanes. The WWM instructions and the writelane instructions for
573 // spilling SGPRs to VGPRs fall under such category of operations. The VGPRs
574 // modified by them should be spilled/restored at function prolog/epilog to
575 // avoid any undesired outcome. Each entry in this map holds a pair of values,
576 // the VGPR and its stack slot index.
577 WWMSpillsMap WWMSpills;
578
579 // Before allocation, the VGPR registers are partitioned into two distinct
580 // sets, the first one for WWM-values and the second set for non-WWM values.
581 // The latter set should be reserved during WWM-regalloc.
582 BitVector NonWWMRegMask;
583
584 using ReservedRegSet = SmallSetVector<Register, 8>;
585 // To track the VGPRs reserved for WWM instructions. They get stack slots
586 // later during PrologEpilogInserter and get added into the superset WWMSpills
587 // for actual spilling. A separate set makes the register reserved part and
588 // the serialization easier.
589 ReservedRegSet WWMReservedRegs;
590
591 bool IsWholeWaveFunction = false;
592
593 using PrologEpilogSGPRSpill =
594 std::pair<Register, PrologEpilogSGPRSaveRestoreInfo>;
595 // To track the SGPR spill method used for a CSR SGPR register during
596 // frame lowering. Even though the SGPR spills are handled during
597 // SILowerSGPRSpills pass, some special handling needed later during the
598 // PrologEpilogInserter.
599 SmallVector<PrologEpilogSGPRSpill, 3> PrologEpilogSGPRSpills;
600
601 // To save/restore EXEC MASK around WWM spills and copies.
602 Register SGPRForEXECCopy;
603
604 DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
605
606 // AGPRs used for VGPR spills.
607 SmallVector<MCPhysReg, 32> SpillAGPR;
608
609 // VGPRs used for AGPR spills.
610 SmallVector<MCPhysReg, 32> SpillVGPR;
611
612 // Emergency stack slot. Sometimes, we create this before finalizing the stack
613 // frame, so save it here and add it to the RegScavenger later.
614 std::optional<int> ScavengeFI;
615
616 // Map each VGPR CSR to the mask needed to save and restore it using block
617 // load/store instructions. Only used if the subtarget feature for VGPR block
618 // load/store is enabled.
619 IndexedMap<uint32_t, VGPRBlock2IndexFunctor> MaskForVGPRBlockOps;
620
621private:
622 Register VGPRForAGPRCopy;
623
624 bool allocateVirtualVGPRForSGPRSpills(MachineFunction &MF, int FI,
625 unsigned LaneIndex);
626 bool allocatePhysicalVGPRForSGPRSpills(MachineFunction &MF, int FI,
627 unsigned LaneIndex,
628 bool IsPrologEpilog);
629
630public:
631 Register getVGPRForAGPRCopy() const {
632 return VGPRForAGPRCopy;
633 }
634
635 void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
636 VGPRForAGPRCopy = NewVGPRForAGPRCopy;
637 }
638
639 bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const;
640
641 void setMaskForVGPRBlockOps(Register RegisterBlock, uint32_t Mask) {
642 MaskForVGPRBlockOps.grow(N: RegisterBlock);
643 MaskForVGPRBlockOps[RegisterBlock] = Mask;
644 }
645
646 uint32_t getMaskForVGPRBlockOps(Register RegisterBlock) const {
647 return MaskForVGPRBlockOps[RegisterBlock];
648 }
649
650 bool hasMaskForVGPRBlockOps(Register RegisterBlock) const {
651 return MaskForVGPRBlockOps.inBounds(N: RegisterBlock);
652 }
653
654public:
655 SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
656 SIMachineFunctionInfo(const Function &F, const GCNSubtarget *STI);
657
658 MachineFunctionInfo *
659 clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
660 const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
661 const override;
662
663 bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI,
664 const MachineFunction &MF,
665 PerFunctionMIParsingState &PFS,
666 SMDiagnostic &Error, SMRange &SourceRange);
667
668 void reserveWWMRegister(Register Reg) { WWMReservedRegs.insert(X: Reg); }
669 bool isWWMReg(Register Reg) const {
670 return Reg.isVirtual() ? checkFlag(Reg, Flag: AMDGPU::VirtRegFlag::WWM_REG)
671 : WWMReservedRegs.contains(key: Reg);
672 }
673
674 void updateNonWWMRegMask(BitVector &RegMask) { NonWWMRegMask = RegMask; }
675 BitVector getNonWWMRegMask() const { return NonWWMRegMask; }
676 void clearNonWWMRegAllocMask() { NonWWMRegMask.clear(); }
677
678 SIModeRegisterDefaults getMode() const { return Mode; }
679
680 ArrayRef<SIRegisterInfo::SpilledReg>
681 getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const {
682 auto I = SGPRSpillsToVirtualVGPRLanes.find(Val: FrameIndex);
683 return (I == SGPRSpillsToVirtualVGPRLanes.end())
684 ? ArrayRef<SIRegisterInfo::SpilledReg>()
685 : ArrayRef(I->second);
686 }
687
688 ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
689 ArrayRef<Register> getSGPRSpillPhysVGPRs() const { return SpillPhysVGPRs; }
690
691 const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
692 const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }
693
694 bool isWWMReservedRegister(Register Reg) const {
695 return WWMReservedRegs.contains(key: Reg);
696 }
697
698 bool isWholeWaveFunction() const { return IsWholeWaveFunction; }
699
700 ArrayRef<PrologEpilogSGPRSpill> getPrologEpilogSGPRSpills() const {
701 assert(is_sorted(PrologEpilogSGPRSpills, llvm::less_first()));
702 return PrologEpilogSGPRSpills;
703 }
704
705 GCNUserSGPRUsageInfo &getUserSGPRInfo() { return UserSGPRInfo; }
706
707 const GCNUserSGPRUsageInfo &getUserSGPRInfo() const { return UserSGPRInfo; }
708
709 void addToPrologEpilogSGPRSpills(Register Reg,
710 PrologEpilogSGPRSaveRestoreInfo SI) {
711 assert(!hasPrologEpilogSGPRSpillEntry(Reg));
712
713 // Insert a new entry in the right place to keep the vector in sorted order.
714 // This should be cheap since the vector is expected to be very short.
715 PrologEpilogSGPRSpills.insert(
716 I: upper_bound(
717 Range&: PrologEpilogSGPRSpills, Value&: Reg,
718 C: [](const auto &LHS, const auto &RHS) { return LHS < RHS.first; }),
719 Elt: std::make_pair(x&: Reg, y&: SI));
720 }
721
722 // Check if an entry created for \p Reg in PrologEpilogSGPRSpills. Return true
723 // on success and false otherwise.
724 bool hasPrologEpilogSGPRSpillEntry(Register Reg) const {
725 const auto *I = find_if(Range: PrologEpilogSGPRSpills, P: [&Reg](const auto &Spill) {
726 return Spill.first == Reg;
727 });
728 return I != PrologEpilogSGPRSpills.end();
729 }
730
731 // Get the scratch SGPR if allocated to save/restore \p Reg.
732 Register getScratchSGPRCopyDstReg(Register Reg) const {
733 const auto *I = find_if(Range: PrologEpilogSGPRSpills, P: [&Reg](const auto &Spill) {
734 return Spill.first == Reg;
735 });
736 if (I != PrologEpilogSGPRSpills.end() &&
737 I->second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
738 return I->second.getReg();
739
740 return AMDGPU::NoRegister;
741 }
742
743 // Get all scratch SGPRs allocated to copy/restore the SGPR spills.
744 void getAllScratchSGPRCopyDstRegs(SmallVectorImpl<Register> &Regs) const {
745 for (const auto &SI : PrologEpilogSGPRSpills) {
746 if (SI.second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
747 Regs.push_back(Elt: SI.second.getReg());
748 }
749 }
750
751 // Check if \p FI is allocated for any SGPR spill to a VGPR lane during PEI.
752 bool checkIndexInPrologEpilogSGPRSpills(int FI) const {
753 return find_if(Range: PrologEpilogSGPRSpills,
754 P: [FI](const std::pair<Register,
755 PrologEpilogSGPRSaveRestoreInfo> &SI) {
756 return SI.second.getKind() ==
757 SGPRSaveKind::SPILL_TO_VGPR_LANE &&
758 SI.second.getIndex() == FI;
759 }) != PrologEpilogSGPRSpills.end();
760 }
761
762 // Remove if an entry created for \p Reg.
763 void removePrologEpilogSGPRSpillEntry(Register Reg) {
764 auto I = find_if(Range&: PrologEpilogSGPRSpills,
765 P: [&Reg](const auto &Spill) { return Spill.first == Reg; });
766 if (I == PrologEpilogSGPRSpills.end())
767 return;
768
769 PrologEpilogSGPRSpills.erase(CI: I);
770 }
771
772 const PrologEpilogSGPRSaveRestoreInfo &
773 getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const {
774 const auto *I = find_if(Range: PrologEpilogSGPRSpills, P: [&Reg](const auto &Spill) {
775 return Spill.first == Reg;
776 });
777 assert(I != PrologEpilogSGPRSpills.end());
778
779 return I->second;
780 }
781
782 ArrayRef<SIRegisterInfo::SpilledReg>
783 getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const {
784 auto I = SGPRSpillsToPhysicalVGPRLanes.find(Val: FrameIndex);
785 return (I == SGPRSpillsToPhysicalVGPRLanes.end())
786 ? ArrayRef<SIRegisterInfo::SpilledReg>()
787 : ArrayRef(I->second);
788 }
789
790 void setFlag(Register Reg, uint8_t Flag) {
791 assert(Reg.isVirtual());
792 if (VRegFlags.inBounds(N: Reg))
793 VRegFlags[Reg] |= Flag;
794 }
795
796 bool checkFlag(Register Reg, uint8_t Flag) const {
797 if (Reg.isPhysical())
798 return false;
799
800 return VRegFlags.inBounds(N: Reg) && VRegFlags[Reg] & Flag;
801 }
802
803 bool hasVRegFlags() { return VRegFlags.size(); }
804
805 void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size = 4,
806 Align Alignment = Align(4));
807
808 void splitWWMSpillRegisters(
809 MachineFunction &MF,
810 SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
811 SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const;
812
813 ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
814 return SpillAGPR;
815 }
816
817 Register getSGPRForEXECCopy() const { return SGPRForEXECCopy; }
818
819 void setSGPRForEXECCopy(Register Reg) { SGPRForEXECCopy = Reg; }
820
821 ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
822 return SpillVGPR;
823 }
824
825 MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
826 auto I = VGPRToAGPRSpills.find(Val: FrameIndex);
827 return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
828 : I->second.Lanes[Lane];
829 }
830
831 void setVGPRToAGPRSpillDead(int FrameIndex) {
832 auto I = VGPRToAGPRSpills.find(Val: FrameIndex);
833 if (I != VGPRToAGPRSpills.end())
834 I->second.IsDead = true;
835 }
836
837 // To bring the allocated WWM registers in \p WWMVGPRs to the lowest available
838 // range.
839 void shiftWwmVGPRsToLowestRange(MachineFunction &MF,
840 SmallVectorImpl<Register> &WWMVGPRs,
841 BitVector &SavedVGPRs);
842
843 bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI,
844 bool SpillToPhysVGPRLane = false,
845 bool IsPrologEpilog = false);
846 bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
847
848 /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
849 /// to the default stack.
850 bool removeDeadFrameIndices(MachineFrameInfo &MFI,
851 bool ResetSGPRSpillStackIDs);
852
853 int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
854 std::optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
855
856 unsigned getBytesInStackArgArea() const {
857 return BytesInStackArgArea;
858 }
859
860 void setBytesInStackArgArea(unsigned Bytes) {
861 BytesInStackArgArea = Bytes;
862 }
863
864 bool isDynamicVGPREnabled() const { return DynamicVGPRBlockSize != 0; }
865 unsigned getDynamicVGPRBlockSize() const { return DynamicVGPRBlockSize; }
866
867 // This is only used if we need to save any dynamic VGPRs in scratch.
868 unsigned getScratchReservedForDynamicVGPRs() const {
869 return ScratchReservedForDynamicVGPRs;
870 }
871
872 void setScratchReservedForDynamicVGPRs(unsigned SizeInBytes) {
873 ScratchReservedForDynamicVGPRs = SizeInBytes;
874 }
875
876 // Add user SGPRs.
877 Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
878 Register addDispatchPtr(const SIRegisterInfo &TRI);
879 Register addQueuePtr(const SIRegisterInfo &TRI);
880 Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
881 Register addDispatchID(const SIRegisterInfo &TRI);
882 Register addFlatScratchInit(const SIRegisterInfo &TRI);
883 Register addPrivateSegmentSize(const SIRegisterInfo &TRI);
884 Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
885 Register addLDSKernelId();
886 SmallVectorImpl<MCRegister> *
887 addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC,
888 unsigned AllocSizeDWord, int KernArgIdx,
889 int PaddingSGPRs);
890
891 /// Increment user SGPRs used for padding the argument list only.
892 Register addReservedUserSGPR() {
893 Register Next = getNextUserSGPR();
894 ++NumUserSGPRs;
895 return Next;
896 }
897
898 // Add system SGPRs.
899 Register addWorkGroupIDX() {
900 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
901 NumSystemSGPRs += 1;
902 return ArgInfo.WorkGroupIDX.getRegister();
903 }
904
905 Register addWorkGroupIDY() {
906 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
907 NumSystemSGPRs += 1;
908 return ArgInfo.WorkGroupIDY.getRegister();
909 }
910
911 Register addWorkGroupIDZ() {
912 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
913 NumSystemSGPRs += 1;
914 return ArgInfo.WorkGroupIDZ.getRegister();
915 }
916
917 Register addWorkGroupInfo() {
918 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
919 NumSystemSGPRs += 1;
920 return ArgInfo.WorkGroupInfo.getRegister();
921 }
922
923 bool hasLDSKernelId() const { return LDSKernelId; }
924
925 // Add special VGPR inputs
926 void setWorkItemIDX(ArgDescriptor Arg) {
927 ArgInfo.WorkItemIDX = Arg;
928 }
929
930 void setWorkItemIDY(ArgDescriptor Arg) {
931 ArgInfo.WorkItemIDY = Arg;
932 }
933
934 void setWorkItemIDZ(ArgDescriptor Arg) {
935 ArgInfo.WorkItemIDZ = Arg;
936 }
937
938 Register addPrivateSegmentWaveByteOffset() {
939 ArgInfo.PrivateSegmentWaveByteOffset
940 = ArgDescriptor::createRegister(Reg: getNextSystemSGPR());
941 NumSystemSGPRs += 1;
942 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
943 }
944
945 void setPrivateSegmentWaveByteOffset(Register Reg) {
946 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
947 }
948
949 bool hasWorkGroupIDX() const {
950 return WorkGroupIDX;
951 }
952
953 bool hasWorkGroupIDY() const {
954 return WorkGroupIDY;
955 }
956
957 bool hasWorkGroupIDZ() const {
958 return WorkGroupIDZ;
959 }
960
961 bool hasWorkGroupInfo() const {
962 return WorkGroupInfo;
963 }
964
965 bool hasPrivateSegmentWaveByteOffset() const {
966 return PrivateSegmentWaveByteOffset;
967 }
968
969 bool hasWorkItemIDX() const {
970 return WorkItemIDX;
971 }
972
973 bool hasWorkItemIDY() const {
974 return WorkItemIDY;
975 }
976
977 bool hasWorkItemIDZ() const {
978 return WorkItemIDZ;
979 }
980
981 bool hasImplicitArgPtr() const {
982 return ImplicitArgPtr;
983 }
984
985 AMDGPUFunctionArgInfo &getArgInfo() {
986 return ArgInfo;
987 }
988
989 const AMDGPUFunctionArgInfo &getArgInfo() const {
990 return ArgInfo;
991 }
992
993 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
994 getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
995 return ArgInfo.getPreloadedValue(Value);
996 }
997
998 MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
999 const auto *Arg = std::get<0>(t: ArgInfo.getPreloadedValue(Value));
1000 return Arg ? Arg->getRegister() : MCRegister();
1001 }
1002
1003 unsigned getGITPtrHigh() const {
1004 return GITPtrHigh;
1005 }
1006
1007 Register getGITPtrLoReg(const MachineFunction &MF) const;
1008
1009 uint32_t get32BitAddressHighBits() const {
1010 return HighBitsOf32BitAddress;
1011 }
1012
1013 unsigned getNumUserSGPRs() const {
1014 return NumUserSGPRs;
1015 }
1016
1017 unsigned getNumPreloadedSGPRs() const {
1018 return NumUserSGPRs + NumSystemSGPRs;
1019 }
1020
1021 unsigned getNumKernargPreloadedSGPRs() const {
1022 return UserSGPRInfo.getNumKernargPreloadSGPRs();
1023 }
1024
1025 unsigned getNumWaveDispatchSGPRs() const { return NumWaveDispatchSGPRs; }
1026
1027 void setNumWaveDispatchSGPRs(unsigned Count) { NumWaveDispatchSGPRs = Count; }
1028
1029 unsigned getNumWaveDispatchVGPRs() const { return NumWaveDispatchVGPRs; }
1030
1031 void setNumWaveDispatchVGPRs(unsigned Count) { NumWaveDispatchVGPRs = Count; }
1032
1033 Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
1034 if (ArgInfo.PrivateSegmentWaveByteOffset)
1035 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
1036 return MCRegister();
1037 }
1038
1039 /// Returns the physical register reserved for use as the resource
1040 /// descriptor for scratch accesses.
1041 Register getScratchRSrcReg() const {
1042 return ScratchRSrcReg;
1043 }
1044
1045 void setScratchRSrcReg(Register Reg) {
1046 assert(Reg != 0 && "Should never be unset");
1047 ScratchRSrcReg = Reg;
1048 }
1049
1050 Register getFrameOffsetReg() const {
1051 return FrameOffsetReg;
1052 }
1053
1054 void setFrameOffsetReg(Register Reg) {
1055 assert(Reg != 0 && "Should never be unset");
1056 FrameOffsetReg = Reg;
1057 }
1058
1059 void setStackPtrOffsetReg(Register Reg) {
1060 assert(Reg != 0 && "Should never be unset");
1061 StackPtrOffsetReg = Reg;
1062 }
1063
1064 void setLongBranchReservedReg(Register Reg) { LongBranchReservedReg = Reg; }
1065
1066 // Note the unset value for this is AMDGPU::SP_REG rather than
1067 // NoRegister. This is mostly a workaround for MIR tests where state that
1068 // can't be directly computed from the function is not preserved in serialized
1069 // MIR.
1070 Register getStackPtrOffsetReg() const {
1071 return StackPtrOffsetReg;
1072 }
1073
1074 Register getLongBranchReservedReg() const { return LongBranchReservedReg; }
1075
1076 Register getQueuePtrUserSGPR() const {
1077 return ArgInfo.QueuePtr.getRegister();
1078 }
1079
1080 Register getImplicitBufferPtrUserSGPR() const {
1081 return ArgInfo.ImplicitBufferPtr.getRegister();
1082 }
1083
1084 bool hasSpilledSGPRs() const {
1085 return HasSpilledSGPRs;
1086 }
1087
1088 void setHasSpilledSGPRs(bool Spill = true) {
1089 HasSpilledSGPRs = Spill;
1090 }
1091
1092 bool hasSpilledVGPRs() const {
1093 return HasSpilledVGPRs;
1094 }
1095
1096 void setHasSpilledVGPRs(bool Spill = true) {
1097 HasSpilledVGPRs = Spill;
1098 }
1099
1100 bool hasNonSpillStackObjects() const {
1101 return HasNonSpillStackObjects;
1102 }
1103
1104 void setHasNonSpillStackObjects(bool StackObject = true) {
1105 HasNonSpillStackObjects = StackObject;
1106 }
1107
1108 bool isStackRealigned() const {
1109 return IsStackRealigned;
1110 }
1111
1112 void setIsStackRealigned(bool Realigned = true) {
1113 IsStackRealigned = Realigned;
1114 }
1115
1116 unsigned getNumSpilledSGPRs() const {
1117 return NumSpilledSGPRs;
1118 }
1119
1120 unsigned getNumSpilledVGPRs() const {
1121 return NumSpilledVGPRs;
1122 }
1123
1124 void addToSpilledSGPRs(unsigned num) {
1125 NumSpilledSGPRs += num;
1126 }
1127
1128 void addToSpilledVGPRs(unsigned num) {
1129 NumSpilledVGPRs += num;
1130 }
1131
1132 unsigned getPSInputAddr() const {
1133 return PSInputAddr;
1134 }
1135
1136 unsigned getPSInputEnable() const {
1137 return PSInputEnable;
1138 }
1139
1140 bool isPSInputAllocated(unsigned Index) const {
1141 return PSInputAddr & (1 << Index);
1142 }
1143
1144 void markPSInputAllocated(unsigned Index) {
1145 PSInputAddr |= 1 << Index;
1146 }
1147
1148 void markPSInputEnabled(unsigned Index) {
1149 PSInputEnable |= 1 << Index;
1150 }
1151
1152 bool returnsVoid() const {
1153 return ReturnsVoid;
1154 }
1155
1156 void setIfReturnsVoid(bool Value) {
1157 ReturnsVoid = Value;
1158 }
1159
1160 /// \returns A pair of default/requested minimum/maximum flat work group sizes
1161 /// for this function.
1162 std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
1163 return FlatWorkGroupSizes;
1164 }
1165
1166 /// \returns Default/requested minimum flat work group size for this function.
1167 unsigned getMinFlatWorkGroupSize() const {
1168 return FlatWorkGroupSizes.first;
1169 }
1170
1171 /// \returns Default/requested maximum flat work group size for this function.
1172 unsigned getMaxFlatWorkGroupSize() const {
1173 return FlatWorkGroupSizes.second;
1174 }
1175
1176 /// \returns A pair of default/requested minimum/maximum number of waves per
1177 /// execution unit.
1178 std::pair<unsigned, unsigned> getWavesPerEU() const {
1179 return WavesPerEU;
1180 }
1181
1182 /// \returns Default/requested minimum number of waves per execution unit.
1183 unsigned getMinWavesPerEU() const {
1184 return WavesPerEU.first;
1185 }
1186
1187 /// \returns Default/requested maximum number of waves per execution unit.
1188 unsigned getMaxWavesPerEU() const {
1189 return WavesPerEU.second;
1190 }
1191
1192 const AMDGPUGWSResourcePseudoSourceValue *
1193 getGWSPSV(const AMDGPUTargetMachine &TM) {
1194 return &GWSResourcePSV;
1195 }
1196
1197 unsigned getOccupancy() const {
1198 return Occupancy;
1199 }
1200
1201 unsigned getMinAllowedOccupancy() const {
1202 if (!isMemoryBound() && !needsWaveLimiter())
1203 return Occupancy;
1204 return (Occupancy < 4) ? Occupancy : 4;
1205 }
1206
1207 void limitOccupancy(const MachineFunction &MF);
1208
1209 void limitOccupancy(unsigned Limit) {
1210 if (Occupancy > Limit)
1211 Occupancy = Limit;
1212 }
1213
1214 void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
1215 if (Occupancy < Limit)
1216 Occupancy = Limit;
1217 limitOccupancy(MF);
1218 }
1219
1220 unsigned getMaxMemoryClusterDWords() const { return MaxMemoryClusterDWords; }
1221
1222 unsigned getMinNumAGPRs() const { return MinNumAGPRs; }
1223
1224 /// Return true if an MFMA that requires at least \p NumRegs should select to
1225 /// the AGPR form, instead of the VGPR form.
1226 bool selectAGPRFormMFMA(unsigned NumRegs) const {
1227 return !MFMAVGPRForm && getMinNumAGPRs() >= NumRegs;
1228 }
1229
1230 // \returns true if a function has a use of AGPRs via inline asm or
1231 // has a call which may use it.
1232 bool mayUseAGPRs(const Function &F) const;
1233
1234 /// \returns Default/requested number of work groups for this function.
1235 SmallVector<unsigned> getMaxNumWorkGroups() const { return MaxNumWorkGroups; }
1236
1237 unsigned getMaxNumWorkGroupsX() const { return MaxNumWorkGroups[0]; }
1238 unsigned getMaxNumWorkGroupsY() const { return MaxNumWorkGroups[1]; }
1239 unsigned getMaxNumWorkGroupsZ() const { return MaxNumWorkGroups[2]; }
1240
1241 AMDGPU::ClusterDimsAttr getClusterDims() const { return ClusterDims; }
1242};
1243
1244} // end namespace llvm
1245
1246#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
1247