1//===-- SIModeRegisterDefaults.h --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
10#define LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
11
12#include "Utils/AMDGPUBaseInfo.h"
13#include "llvm/ADT/FloatingPointMode.h"
14
15namespace llvm {
16
17class GCNSubtarget;
18
19// Track defaults for fields in the MODE register.
20struct SIModeRegisterDefaults {
21 /// Floating point opcodes that support exception flag gathering quiet and
22 /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
23 /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
24 /// quieting.
25 bool IEEE : 1;
26
27 /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
28 /// clamp NaN to zero; otherwise, pass NaN through.
29 bool DX10Clamp : 1;
30
31 /// If this is set, neither input or output denormals are flushed for most f32
32 /// instructions.
33 DenormalMode FP32Denormals;
34
35 /// If this is set, neither input or output denormals are flushed for both f64
36 /// and f16/v2f16 instructions.
37 DenormalMode FP64FP16Denormals;
38
39 SIModeRegisterDefaults() :
40 IEEE(true),
41 DX10Clamp(true),
42 FP32Denormals(DenormalMode::getIEEE()),
43 FP64FP16Denormals(DenormalMode::getIEEE()) {}
44
45 SIModeRegisterDefaults(const Function &F, const GCNSubtarget &ST);
46
47 static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
48 SIModeRegisterDefaults Mode;
49 Mode.IEEE = !AMDGPU::isShader(CC);
50 return Mode;
51 }
52
53 bool operator==(const SIModeRegisterDefaults Other) const {
54 return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
55 FP32Denormals == Other.FP32Denormals &&
56 FP64FP16Denormals == Other.FP64FP16Denormals;
57 }
58
59 /// Get the denormal handling described by this mode.
60 DenormalFPEnv getDenormalFPEnv() const {
61 return DenormalFPEnv(FP64FP16Denormals, FP32Denormals);
62 }
63
64 /// Get the encoding value for the FP_DENORM bits of the mode register for the
65 /// FP32 denormal mode.
66 uint32_t fpDenormModeSPValue() const {
67 if (FP32Denormals == DenormalMode::getPreserveSign())
68 return FP_DENORM_FLUSH_IN_FLUSH_OUT;
69 if (FP32Denormals.Output == DenormalMode::PreserveSign)
70 return FP_DENORM_FLUSH_OUT;
71 if (FP32Denormals.Input == DenormalMode::PreserveSign)
72 return FP_DENORM_FLUSH_IN;
73 return FP_DENORM_FLUSH_NONE;
74 }
75
76 /// Get the encoding value for the FP_DENORM bits of the mode register for the
77 /// FP64/FP16 denormal mode.
78 uint32_t fpDenormModeDPValue() const {
79 if (FP64FP16Denormals == DenormalMode::getPreserveSign())
80 return FP_DENORM_FLUSH_IN_FLUSH_OUT;
81 if (FP64FP16Denormals.Output == DenormalMode::PreserveSign)
82 return FP_DENORM_FLUSH_OUT;
83 if (FP64FP16Denormals.Input == DenormalMode::PreserveSign)
84 return FP_DENORM_FLUSH_IN;
85 return FP_DENORM_FLUSH_NONE;
86 }
87
88 // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
89 // be able to override.
90 bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
91 return DX10Clamp == CalleeMode.DX10Clamp && IEEE == CalleeMode.IEEE;
92 }
93};
94
95namespace AMDGPU {
96
97/// Return values used for llvm.get.rounding
98///
99/// When both the F32 and F64/F16 modes are the same, returns the standard
100/// values. If they differ, returns an extended mode starting at 8.
101enum AMDGPUFltRounds : int8_t {
102 // Inherit everything from RoundingMode
103 TowardZero = static_cast<int8_t>(RoundingMode::TowardZero),
104 NearestTiesToEven = static_cast<int8_t>(RoundingMode::NearestTiesToEven),
105 TowardPositive = static_cast<int8_t>(RoundingMode::TowardPositive),
106 TowardNegative = static_cast<int8_t>(RoundingMode::TowardNegative),
107 NearestTiesToAwayUnsupported =
108 static_cast<int8_t>(RoundingMode::NearestTiesToAway),
109
110 Dynamic = static_cast<int8_t>(RoundingMode::Dynamic),
111
112 // Permute the mismatched rounding mode cases. If the modes are the same, use
113 // the standard values, otherwise, these values are sorted such that higher
114 // hardware encoded values have higher enum values.
115 NearestTiesToEvenF32_NearestTiesToEvenF64 = NearestTiesToEven,
116 NearestTiesToEvenF32_TowardPositiveF64 = 8,
117 NearestTiesToEvenF32_TowardNegativeF64 = 9,
118 NearestTiesToEvenF32_TowardZeroF64 = 10,
119
120 TowardPositiveF32_NearestTiesToEvenF64 = 11,
121 TowardPositiveF32_TowardPositiveF64 = TowardPositive,
122 TowardPositiveF32_TowardNegativeF64 = 12,
123 TowardPositiveF32_TowardZeroF64 = 13,
124
125 TowardNegativeF32_NearestTiesToEvenF64 = 14,
126 TowardNegativeF32_TowardPositiveF64 = 15,
127 TowardNegativeF32_TowardNegativeF64 = TowardNegative,
128 TowardNegativeF32_TowardZeroF64 = 16,
129
130 TowardZeroF32_NearestTiesToEvenF64 = 17,
131 TowardZeroF32_TowardPositiveF64 = 18,
132 TowardZeroF32_TowardNegativeF64 = 19,
133 TowardZeroF32_TowardZeroF64 = TowardZero,
134
135 Invalid = static_cast<int8_t>(RoundingMode::Invalid)
136};
137
138/// Offset of nonstandard values for llvm.get.rounding results from the largest
139/// supported mode.
140static constexpr uint32_t ExtendedFltRoundOffset = 4;
141
142/// Offset in mode register of f32 rounding mode.
143static constexpr uint32_t F32FltRoundOffset = 0;
144
145/// Offset in mode register of f64/f16 rounding mode.
146static constexpr uint32_t F64FltRoundOffset = 2;
147
148// Bit indexed table to convert from hardware rounding mode values to FLT_ROUNDS
149// values.
150extern const uint64_t FltRoundConversionTable;
151
152// Bit indexed table to convert from FLT_ROUNDS values to hardware rounding mode
153// values
154extern const uint64_t FltRoundToHWConversionTable;
155
156/// Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.
157uint32_t decodeFltRoundToHWConversionTable(uint32_t FltRounds);
158
159} // end namespace AMDGPU
160
161} // end namespace llvm
162
163#endif // LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
164