1//===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/AMDGPUFixupKinds.h"
11#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12#include "Utils/AMDGPUBaseInfo.h"
13#include "llvm/ADT/StringSwitch.h"
14#include "llvm/BinaryFormat/ELF.h"
15#include "llvm/MC/MCAsmBackend.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCAssembler.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCObjectWriter.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/MC/MCValue.h"
22#include "llvm/MC/TargetRegistry.h"
23#include "llvm/Support/EndianStream.h"
24#include "llvm/TargetParser/TargetParser.h"
25
26using namespace llvm;
27using namespace llvm::AMDGPU;
28
29namespace {
30
31class AMDGPUAsmBackend : public MCAsmBackend {
32public:
33 AMDGPUAsmBackend(const Target &T) : MCAsmBackend(llvm::endianness::little) {}
34
35 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,
36 uint8_t *Data, uint64_t Value, bool IsResolved) override;
37 bool fixupNeedsRelaxationAdvanced(const MCFragment &, const MCFixup &,
38 const MCValue &, uint64_t,
39 bool) const override;
40
41 void relaxInstruction(MCInst &Inst,
42 const MCSubtargetInfo &STI) const override;
43
44 bool mayNeedRelaxation(unsigned Opcode, ArrayRef<MCOperand> Operands,
45 const MCSubtargetInfo &STI) const override;
46
47 unsigned getMinimumNopSize() const override;
48 bool writeNopData(raw_ostream &OS, uint64_t Count,
49 const MCSubtargetInfo *STI) const override;
50
51 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
52 MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override;
53};
54
55} //End anonymous namespace
56
57void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst,
58 const MCSubtargetInfo &STI) const {
59 MCInst Res;
60 unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Opcode: Inst.getOpcode());
61 Res.setOpcode(RelaxedOpcode);
62 Res.addOperand(Op: Inst.getOperand(i: 0));
63 Inst = std::move(Res);
64}
65
66bool AMDGPUAsmBackend::fixupNeedsRelaxationAdvanced(const MCFragment &,
67 const MCFixup &Fixup,
68 const MCValue &,
69 uint64_t Value,
70 bool Resolved) const {
71 if (!Resolved)
72 return true;
73 // if the branch target has an offset of x3f this needs to be relaxed to
74 // add a s_nop 0 immediately after branch to effectively increment offset
75 // for hardware workaround in gfx1010
76 return (((int64_t(Value)/4)-1) == 0x3f);
77}
78
79bool AMDGPUAsmBackend::mayNeedRelaxation(unsigned Opcode,
80 ArrayRef<MCOperand> Operands,
81 const MCSubtargetInfo &STI) const {
82 if (!STI.hasFeature(Feature: AMDGPU::FeatureOffset3fBug))
83 return false;
84
85 if (AMDGPU::getSOPPWithRelaxation(Opcode) >= 0)
86 return true;
87
88 return false;
89}
90
91static unsigned getFixupKindNumBytes(unsigned Kind) {
92 switch (Kind) {
93 case AMDGPU::fixup_si_sopp_br:
94 return 2;
95 case FK_SecRel_1:
96 case FK_Data_1:
97 return 1;
98 case FK_SecRel_2:
99 case FK_Data_2:
100 return 2;
101 case FK_SecRel_4:
102 case FK_Data_4:
103 return 4;
104 case FK_SecRel_8:
105 case FK_Data_8:
106 return 8;
107 default:
108 llvm_unreachable("Unknown fixup kind!");
109 }
110}
111
112static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
113 MCContext *Ctx) {
114 int64_t SignedValue = static_cast<int64_t>(Value);
115
116 switch (Fixup.getKind()) {
117 case AMDGPU::fixup_si_sopp_br: {
118 int64_t BrImm = (SignedValue - 4) / 4;
119
120 if (Ctx && !isInt<16>(x: BrImm))
121 Ctx->reportError(L: Fixup.getLoc(), Msg: "branch size exceeds simm16");
122
123 return BrImm;
124 }
125 case FK_Data_1:
126 case FK_Data_2:
127 case FK_Data_4:
128 case FK_Data_8:
129 case FK_SecRel_4:
130 return Value;
131 default:
132 llvm_unreachable("unhandled fixup kind");
133 }
134}
135
136void AMDGPUAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
137 const MCValue &Target, uint8_t *Data,
138 uint64_t Value, bool IsResolved) {
139 if (Target.getSpecifier())
140 IsResolved = false;
141 maybeAddReloc(F, Fixup, Target, Value, IsResolved);
142 if (mc::isRelocation(FixupKind: Fixup.getKind()))
143 return;
144
145 Value = adjustFixupValue(Fixup, Value, Ctx: &getContext());
146 if (!Value)
147 return; // Doesn't change encoding.
148
149 MCFixupKindInfo Info = getFixupKindInfo(Kind: Fixup.getKind());
150
151 // Shift the value into position.
152 Value <<= Info.TargetOffset;
153
154 unsigned NumBytes = getFixupKindNumBytes(Kind: Fixup.getKind());
155 assert(Fixup.getOffset() + NumBytes <= F.getSize() &&
156 "Invalid fixup offset!");
157
158 // For each byte of the fragment that the fixup touches, mask in the bits from
159 // the fixup value.
160 for (unsigned i = 0; i != NumBytes; ++i)
161 Data[i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
162}
163
164std::optional<MCFixupKind>
165AMDGPUAsmBackend::getFixupKind(StringRef Name) const {
166 auto Type = StringSwitch<unsigned>(Name)
167#define ELF_RELOC(Name, Value) .Case(#Name, Value)
168#include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def"
169#undef ELF_RELOC
170 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_AMDGPU_NONE)
171 .Case(S: "BFD_RELOC_32", Value: ELF::R_AMDGPU_ABS32)
172 .Case(S: "BFD_RELOC_64", Value: ELF::R_AMDGPU_ABS64)
173 .Default(Value: -1u);
174 if (Type != -1u)
175 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
176 return std::nullopt;
177}
178
179MCFixupKindInfo AMDGPUAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
180 const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
181 // name offset bits flags
182 {.Name: "fixup_si_sopp_br", .TargetOffset: 0, .TargetSize: 16, .Flags: 0},
183 };
184
185 if (mc::isRelocation(FixupKind: Kind))
186 return {};
187
188 if (Kind < FirstTargetFixupKind)
189 return MCAsmBackend::getFixupKindInfo(Kind);
190
191 assert(unsigned(Kind - FirstTargetFixupKind) < AMDGPU::NumTargetFixupKinds &&
192 "Invalid kind!");
193 return Infos[Kind - FirstTargetFixupKind];
194}
195
196unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
197 return 4;
198}
199
200bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
201 const MCSubtargetInfo *STI) const {
202 // If the count is not aligned to the minimum instruction alignment, we must
203 // be writing data into the text section (otherwise we have unaligned
204 // instructions, and thus have far bigger problems), so just write zeros
205 // instead.
206 unsigned MinInstAlignment = getContext().getAsmInfo()->getMinInstAlignment();
207 OS.write_zeros(NumZeros: Count % MinInstAlignment);
208
209 // We are properly aligned, so write NOPs as requested.
210 Count /= MinInstAlignment;
211
212 // FIXME: R600 support.
213 // s_nop 0
214 const uint32_t Encoded_S_NOP_0 = 0xbf800000;
215
216 assert(MinInstAlignment == sizeof(Encoded_S_NOP_0));
217 for (uint64_t I = 0; I != Count; ++I)
218 support::endian::write<uint32_t>(os&: OS, value: Encoded_S_NOP_0, endian: Endian);
219
220 return true;
221}
222
223//===----------------------------------------------------------------------===//
224// ELFAMDGPUAsmBackend class
225//===----------------------------------------------------------------------===//
226
227namespace {
228
229class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
230 bool Is64Bit;
231 bool HasRelocationAddend;
232 uint8_t OSABI = ELF::ELFOSABI_NONE;
233
234public:
235 ELFAMDGPUAsmBackend(const Target &T, const Triple &TT)
236 : AMDGPUAsmBackend(T), Is64Bit(TT.isAMDGCN()),
237 HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {
238 switch (TT.getOS()) {
239 case Triple::AMDHSA:
240 OSABI = ELF::ELFOSABI_AMDGPU_HSA;
241 break;
242 case Triple::AMDPAL:
243 OSABI = ELF::ELFOSABI_AMDGPU_PAL;
244 break;
245 case Triple::Mesa3D:
246 OSABI = ELF::ELFOSABI_AMDGPU_MESA3D;
247 break;
248 default:
249 break;
250 }
251 }
252
253 std::unique_ptr<MCObjectTargetWriter>
254 createObjectTargetWriter() const override {
255 return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend);
256 }
257};
258
259} // end anonymous namespace
260
261MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
262 const MCSubtargetInfo &STI,
263 const MCRegisterInfo &MRI,
264 const MCTargetOptions &Options) {
265 return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());
266}
267