| 1 | //===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | |
| 9 | #include "MipsABIInfo.h" |
| 10 | #include "Mips.h" |
| 11 | #include "llvm/ADT/StringRef.h" |
| 12 | #include "llvm/MC/MCTargetOptions.h" |
| 13 | #include "llvm/Support/CommandLine.h" |
| 14 | |
| 15 | using namespace llvm; |
| 16 | |
| 17 | // Note: this option is defined here to be visible from libLLVMMipsAsmParser |
| 18 | // and libLLVMMipsCodeGen |
| 19 | cl::opt<bool> |
| 20 | EmitJalrReloc("mips-jalr-reloc" , cl::Hidden, |
| 21 | cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr" ), |
| 22 | cl::init(Val: true)); |
| 23 | cl::opt<bool> |
| 24 | NoZeroDivCheck("mno-check-zero-division" , cl::Hidden, |
| 25 | cl::desc("MIPS: Don't trap on integer division by zero." ), |
| 26 | cl::init(Val: false)); |
| 27 | |
| 28 | namespace { |
| 29 | static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3}; |
| 30 | |
| 31 | static const MCPhysReg Mips64IntRegs[8] = { |
| 32 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, |
| 33 | Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}; |
| 34 | } |
| 35 | |
| 36 | ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const { |
| 37 | if (IsO32()) |
| 38 | return ArrayRef(O32IntRegs); |
| 39 | if (IsN32() || IsN64()) |
| 40 | return ArrayRef(Mips64IntRegs); |
| 41 | llvm_unreachable("Unhandled ABI" ); |
| 42 | } |
| 43 | |
| 44 | ArrayRef<MCPhysReg> MipsABIInfo::getVarArgRegs(bool isGP64bit) const { |
| 45 | if (IsO32()) { |
| 46 | if (isGP64bit) |
| 47 | return ArrayRef(Mips64IntRegs); |
| 48 | else |
| 49 | return ArrayRef(O32IntRegs); |
| 50 | } |
| 51 | if (IsN32() || IsN64()) |
| 52 | return ArrayRef(Mips64IntRegs); |
| 53 | llvm_unreachable("Unhandled ABI" ); |
| 54 | } |
| 55 | |
| 56 | unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const { |
| 57 | if (IsO32()) |
| 58 | return CC != CallingConv::Fast ? 16 : 0; |
| 59 | if (IsN32() || IsN64()) |
| 60 | return 0; |
| 61 | llvm_unreachable("Unhandled ABI" ); |
| 62 | } |
| 63 | |
| 64 | MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef ABIName) { |
| 65 | if (ABIName.starts_with(Prefix: "o32" )) |
| 66 | return MipsABIInfo::O32(); |
| 67 | if (ABIName.starts_with(Prefix: "n32" )) |
| 68 | return MipsABIInfo::N32(); |
| 69 | if (ABIName.starts_with(Prefix: "n64" )) |
| 70 | return MipsABIInfo::N64(); |
| 71 | if (TT.isABIN32()) |
| 72 | return MipsABIInfo::N32(); |
| 73 | assert(ABIName.empty() && "Unknown ABI option for MIPS" ); |
| 74 | |
| 75 | if (TT.isMIPS64()) |
| 76 | return MipsABIInfo::N64(); |
| 77 | return MipsABIInfo::O32(); |
| 78 | } |
| 79 | |
| 80 | unsigned MipsABIInfo::GetStackPtr() const { |
| 81 | return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; |
| 82 | } |
| 83 | |
| 84 | unsigned MipsABIInfo::GetFramePtr() const { |
| 85 | return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; |
| 86 | } |
| 87 | |
| 88 | unsigned MipsABIInfo::GetBasePtr() const { |
| 89 | return ArePtrs64bit() ? Mips::S7_64 : Mips::S7; |
| 90 | } |
| 91 | |
| 92 | unsigned MipsABIInfo::GetGlobalPtr() const { |
| 93 | return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; |
| 94 | } |
| 95 | |
| 96 | unsigned MipsABIInfo::GetNullPtr() const { |
| 97 | return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO; |
| 98 | } |
| 99 | |
| 100 | unsigned MipsABIInfo::GetZeroReg() const { |
| 101 | return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO; |
| 102 | } |
| 103 | |
| 104 | unsigned MipsABIInfo::GetPtrAdduOp() const { |
| 105 | return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; |
| 106 | } |
| 107 | |
| 108 | unsigned MipsABIInfo::GetPtrAddiuOp() const { |
| 109 | return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu; |
| 110 | } |
| 111 | |
| 112 | unsigned MipsABIInfo::GetPtrSubuOp() const { |
| 113 | return ArePtrs64bit() ? Mips::DSUBu : Mips::SUBu; |
| 114 | } |
| 115 | |
| 116 | unsigned MipsABIInfo::GetPtrAndOp() const { |
| 117 | return ArePtrs64bit() ? Mips::AND64 : Mips::AND; |
| 118 | } |
| 119 | |
| 120 | unsigned MipsABIInfo::GetGPRMoveOp() const { |
| 121 | return ArePtrs64bit() ? Mips::OR64 : Mips::OR; |
| 122 | } |
| 123 | |
| 124 | unsigned MipsABIInfo::GetEhDataReg(unsigned I) const { |
| 125 | static const unsigned EhDataReg[] = { |
| 126 | Mips::A0, Mips::A1, Mips::A2, Mips::A3 |
| 127 | }; |
| 128 | static const unsigned EhDataReg64[] = { |
| 129 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64 |
| 130 | }; |
| 131 | |
| 132 | return IsN64() ? EhDataReg64[I] : EhDataReg[I]; |
| 133 | } |
| 134 | |