1//===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===---------------------------------------------------------------------===//
8//
9// This pass performs peephole optimizations to clean up ugly code
10// sequences at the MachineInstruction layer. It runs at the end of
11// the SSA phases, following VSX swap removal. A pass of dead code
12// elimination follows this one for quick clean-up of any dead
13// instructions introduced here. Although we could do this as callbacks
14// from the generic peephole pass, this would have a couple of bad
15// effects: it might remove optimization opportunities for VSX swap
16// removal, and it would miss cleanups made possible following VSX
17// swap removal.
18//
19// NOTE: We run the verifier after this pass in Asserts/Debug builds so it
20// is important to keep the code valid after transformations.
21// Common causes of errors stem from violating the contract specified
22// by kill flags. Whenever a transformation changes the live range of
23// a register, that register should be added to the work list using
24// addRegToUpdate(RegsToUpdate, <Reg>). Furthermore, if a transformation
25// is changing the definition of a register (i.e. removing the single
26// definition of the original vreg), it needs to provide a dummy
27// definition of that register using addDummyDef(<MBB>, <Reg>).
28//===---------------------------------------------------------------------===//
29
30#include "MCTargetDesc/PPCMCTargetDesc.h"
31#include "MCTargetDesc/PPCPredicates.h"
32#include "PPC.h"
33#include "PPCInstrInfo.h"
34#include "PPCMachineFunctionInfo.h"
35#include "PPCTargetMachine.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/CodeGen/LiveVariables.h"
38#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
39#include "llvm/CodeGen/MachineDominators.h"
40#include "llvm/CodeGen/MachineFrameInfo.h"
41#include "llvm/CodeGen/MachineFunctionPass.h"
42#include "llvm/CodeGen/MachineInstrBuilder.h"
43#include "llvm/CodeGen/MachinePostDominators.h"
44#include "llvm/CodeGen/MachineRegisterInfo.h"
45#include "llvm/CodeGen/RegisterClassInfo.h"
46#include "llvm/IR/GlobalVariable.h"
47#include "llvm/InitializePasses.h"
48#include "llvm/Support/Debug.h"
49#include "llvm/Support/DebugCounter.h"
50
51using namespace llvm;
52
53#define DEBUG_TYPE "ppc-mi-peepholes"
54
55STATISTIC(RemoveTOCSave, "Number of TOC saves removed");
56STATISTIC(MultiTOCSaves,
57 "Number of functions with multiple TOC saves that must be kept");
58STATISTIC(NumTOCSavesInPrologue, "Number of TOC saves placed in the prologue");
59STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions");
60STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions");
61STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI");
62STATISTIC(NumConvertedToImmediateForm,
63 "Number of instructions converted to their immediate form");
64STATISTIC(NumFunctionsEnteredInMIPeephole,
65 "Number of functions entered in PPC MI Peepholes");
66STATISTIC(NumFixedPointIterations,
67 "Number of fixed-point iterations converting reg-reg instructions "
68 "to reg-imm ones");
69STATISTIC(NumRotatesCollapsed,
70 "Number of pairs of rotate left, clear left/right collapsed");
71STATISTIC(NumEXTSWAndSLDICombined,
72 "Number of pairs of EXTSW and SLDI combined as EXTSWSLI");
73STATISTIC(NumLoadImmZeroFoldedAndRemoved,
74 "Number of LI(8) reg, 0 that are folded to r0 and removed");
75
76static cl::opt<bool>
77FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(Val: true),
78 cl::desc("Iterate to a fixed point when attempting to "
79 "convert reg-reg instructions to reg-imm"));
80
81static cl::opt<bool>
82ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(Val: true),
83 cl::desc("Convert eligible reg+reg instructions to reg+imm"));
84
85static cl::opt<bool>
86 EnableSExtElimination("ppc-eliminate-signext",
87 cl::desc("enable elimination of sign-extensions"),
88 cl::init(Val: true), cl::Hidden);
89
90static cl::opt<bool>
91 EnableZExtElimination("ppc-eliminate-zeroext",
92 cl::desc("enable elimination of zero-extensions"),
93 cl::init(Val: true), cl::Hidden);
94
95static cl::opt<bool>
96 EnableTrapOptimization("ppc-opt-conditional-trap",
97 cl::desc("enable optimization of conditional traps"),
98 cl::init(Val: false), cl::Hidden);
99
100DEBUG_COUNTER(
101 PeepholeXToICounter, "ppc-xtoi-peephole",
102 "Controls whether PPC reg+reg to reg+imm peephole is performed on a MI");
103
104DEBUG_COUNTER(PeepholePerOpCounter, "ppc-per-op-peephole",
105 "Controls whether PPC per opcode peephole is performed on a MI");
106
107namespace {
108
109struct PPCMIPeephole : public MachineFunctionPass {
110
111 static char ID;
112 const PPCInstrInfo *TII;
113 MachineFunction *MF;
114 MachineRegisterInfo *MRI;
115 LiveVariables *LV;
116
117 PPCMIPeephole() : MachineFunctionPass(ID) {}
118
119private:
120 MachineDominatorTree *MDT;
121 MachinePostDominatorTree *MPDT;
122 MachineBlockFrequencyInfo *MBFI;
123 BlockFrequency EntryFreq;
124 SmallSet<Register, 16> RegsToUpdate;
125
126 // Initialize class variables.
127 void initialize(MachineFunction &MFParm);
128
129 // Perform peepholes.
130 bool simplifyCode();
131
132 // Perform peepholes.
133 bool eliminateRedundantCompare();
134 bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves);
135 bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase);
136 bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI,
137 MachineInstr *&ToErase);
138 void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves,
139 MachineInstr *MI);
140
141 // A number of transformations will eliminate the definition of a register
142 // as all of its uses will be removed. However, this leaves a register
143 // without a definition for LiveVariables. Such transformations should
144 // use this function to provide a dummy definition of the register that
145 // will simply be removed by DCE.
146 void addDummyDef(MachineBasicBlock &MBB, MachineInstr *At, Register Reg) {
147 BuildMI(BB&: MBB, I: At, MIMD: At->getDebugLoc(), MCID: TII->get(Opcode: PPC::IMPLICIT_DEF), DestReg: Reg);
148 }
149 void addRegToUpdateWithLine(Register Reg, int Line);
150 void convertUnprimedAccPHIs(const PPCInstrInfo *TII, MachineRegisterInfo *MRI,
151 SmallVectorImpl<MachineInstr *> &PHIs,
152 Register Dst);
153
154public:
155
156 void getAnalysisUsage(AnalysisUsage &AU) const override {
157 AU.addRequired<LiveVariablesWrapperPass>();
158 AU.addRequired<MachineDominatorTreeWrapperPass>();
159 AU.addRequired<MachinePostDominatorTreeWrapperPass>();
160 AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
161 AU.addPreserved<LiveVariablesWrapperPass>();
162 AU.addPreserved<MachineDominatorTreeWrapperPass>();
163 AU.addPreserved<MachinePostDominatorTreeWrapperPass>();
164 AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
165 AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
166 MachineFunctionPass::getAnalysisUsage(AU);
167 }
168
169 // Main entry point for this pass.
170 bool runOnMachineFunction(MachineFunction &MF) override {
171 initialize(MFParm&: MF);
172 // At this point, TOC pointer should not be used in a function that uses
173 // PC-Relative addressing.
174 assert((MF.getRegInfo().use_empty(PPC::X2) ||
175 !MF.getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls()) &&
176 "TOC pointer used in a function using PC-Relative addressing!");
177 if (skipFunction(F: MF.getFunction()))
178 return false;
179 return simplifyCode();
180 }
181};
182
183#define addRegToUpdate(R) addRegToUpdateWithLine(R, __LINE__)
184void PPCMIPeephole::addRegToUpdateWithLine(Register Reg, int Line) {
185 if (!Reg.isVirtual())
186 return;
187 if (RegsToUpdate.insert(V: Reg).second)
188 LLVM_DEBUG(dbgs() << "Adding register: " << printReg(Reg) << " on line "
189 << Line << " for re-computation of kill flags\n");
190}
191
192// Initialize class variables.
193void PPCMIPeephole::initialize(MachineFunction &MFParm) {
194 MF = &MFParm;
195 MRI = &MF->getRegInfo();
196 MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
197 MPDT = &getAnalysis<MachinePostDominatorTreeWrapperPass>().getPostDomTree();
198 MBFI = &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
199 LV = &getAnalysis<LiveVariablesWrapperPass>().getLV();
200 EntryFreq = MBFI->getEntryFreq();
201 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
202 RegsToUpdate.clear();
203 LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
204 LLVM_DEBUG(MF->dump());
205}
206
207static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
208 MachineRegisterInfo *MRI) {
209 assert(Op && "Invalid Operand!");
210 if (!Op->isReg())
211 return nullptr;
212
213 Register Reg = Op->getReg();
214 if (!Reg.isVirtual())
215 return nullptr;
216
217 return MRI->getVRegDef(Reg);
218}
219
220// This function returns number of known zero bits in output of MI
221// starting from the most significant bit.
222static unsigned getKnownLeadingZeroCount(const unsigned Reg,
223 const PPCInstrInfo *TII,
224 const MachineRegisterInfo *MRI) {
225 MachineInstr *MI = MRI->getVRegDef(Reg);
226 unsigned Opcode = MI->getOpcode();
227 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
228 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec)
229 return MI->getOperand(i: 3).getImm();
230
231 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
232 MI->getOperand(i: 3).getImm() <= 63 - MI->getOperand(i: 2).getImm())
233 return MI->getOperand(i: 3).getImm();
234
235 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
236 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
237 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
238 MI->getOperand(i: 3).getImm() <= MI->getOperand(i: 4).getImm())
239 return 32 + MI->getOperand(i: 3).getImm();
240
241 if (Opcode == PPC::ANDI_rec) {
242 uint16_t Imm = MI->getOperand(i: 2).getImm();
243 return 48 + llvm::countl_zero(Val: Imm);
244 }
245
246 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
247 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
248 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8)
249 // The result ranges from 0 to 32.
250 return 58;
251
252 if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
253 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec)
254 // The result ranges from 0 to 64.
255 return 57;
256
257 if (Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
258 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
259 Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
260 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8)
261 return 48;
262
263 if (Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
264 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
265 Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
266 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
267 return 56;
268
269 if (Opcode == PPC::AND || Opcode == PPC::AND8 || Opcode == PPC::AND_rec ||
270 Opcode == PPC::AND8_rec)
271 return std::max(
272 a: getKnownLeadingZeroCount(Reg: MI->getOperand(i: 1).getReg(), TII, MRI),
273 b: getKnownLeadingZeroCount(Reg: MI->getOperand(i: 2).getReg(), TII, MRI));
274
275 if (Opcode == PPC::OR || Opcode == PPC::OR8 || Opcode == PPC::XOR ||
276 Opcode == PPC::XOR8 || Opcode == PPC::OR_rec ||
277 Opcode == PPC::OR8_rec || Opcode == PPC::XOR_rec ||
278 Opcode == PPC::XOR8_rec)
279 return std::min(
280 a: getKnownLeadingZeroCount(Reg: MI->getOperand(i: 1).getReg(), TII, MRI),
281 b: getKnownLeadingZeroCount(Reg: MI->getOperand(i: 2).getReg(), TII, MRI));
282
283 if (TII->isZeroExtended(Reg, MRI))
284 return 32;
285
286 return 0;
287}
288
289// This function maintains a map for the pairs <TOC Save Instr, Keep>
290// Each time a new TOC save is encountered, it checks if any of the existing
291// ones are dominated by the new one. If so, it marks the existing one as
292// redundant by setting it's entry in the map as false. It then adds the new
293// instruction to the map with either true or false depending on if any
294// existing instructions dominated the new one.
295void PPCMIPeephole::UpdateTOCSaves(
296 std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) {
297 assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here");
298 // FIXME: Saving TOC in prologue hasn't been implemented well in AIX ABI part,
299 // here only support it under ELFv2.
300 if (MF->getSubtarget<PPCSubtarget>().isELFv2ABI()) {
301 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
302
303 MachineBasicBlock *Entry = &MF->front();
304 BlockFrequency CurrBlockFreq = MBFI->getBlockFreq(MBB: MI->getParent());
305
306 // If the block in which the TOC save resides is in a block that
307 // post-dominates Entry, or a block that is hotter than entry (keep in mind
308 // that early MachineLICM has already run so the TOC save won't be hoisted)
309 // we can just do the save in the prologue.
310 if (CurrBlockFreq > EntryFreq || MPDT->dominates(A: MI->getParent(), B: Entry))
311 FI->setMustSaveTOC(true);
312
313 // If we are saving the TOC in the prologue, all the TOC saves can be
314 // removed from the code.
315 if (FI->mustSaveTOC()) {
316 for (auto &TOCSave : TOCSaves)
317 TOCSave.second = false;
318 // Add new instruction to map.
319 TOCSaves[MI] = false;
320 return;
321 }
322 }
323
324 bool Keep = true;
325 for (auto &I : TOCSaves) {
326 MachineInstr *CurrInst = I.first;
327 // If new instruction dominates an existing one, mark existing one as
328 // redundant.
329 if (I.second && MDT->dominates(A: MI, B: CurrInst))
330 I.second = false;
331 // Check if the new instruction is redundant.
332 if (MDT->dominates(A: CurrInst, B: MI)) {
333 Keep = false;
334 break;
335 }
336 }
337 // Add new instruction to map.
338 TOCSaves[MI] = Keep;
339}
340
341// This function returns a list of all PHI nodes in the tree starting from
342// the RootPHI node. We perform a BFS traversal to get an ordered list of nodes.
343// The list initially only contains the root PHI. When we visit a PHI node, we
344// add it to the list. We continue to look for other PHI node operands while
345// there are nodes to visit in the list. The function returns false if the
346// optimization cannot be applied on this tree.
347static bool collectUnprimedAccPHIs(MachineRegisterInfo *MRI,
348 MachineInstr *RootPHI,
349 SmallVectorImpl<MachineInstr *> &PHIs) {
350 PHIs.push_back(Elt: RootPHI);
351 unsigned VisitedIndex = 0;
352 while (VisitedIndex < PHIs.size()) {
353 MachineInstr *VisitedPHI = PHIs[VisitedIndex];
354 for (unsigned PHIOp = 1, NumOps = VisitedPHI->getNumOperands();
355 PHIOp != NumOps; PHIOp += 2) {
356 Register RegOp = VisitedPHI->getOperand(i: PHIOp).getReg();
357 if (!RegOp.isVirtual())
358 return false;
359 MachineInstr *Instr = MRI->getVRegDef(Reg: RegOp);
360 // While collecting the PHI nodes, we check if they can be converted (i.e.
361 // all the operands are either copies, implicit defs or PHI nodes).
362 unsigned Opcode = Instr->getOpcode();
363 if (Opcode == PPC::COPY) {
364 Register Reg = Instr->getOperand(i: 1).getReg();
365 if (!Reg.isVirtual() || MRI->getRegClass(Reg) != &PPC::ACCRCRegClass)
366 return false;
367 } else if (Opcode != PPC::IMPLICIT_DEF && Opcode != PPC::PHI)
368 return false;
369 // If we detect a cycle in the PHI nodes, we exit. It would be
370 // possible to change cycles as well, but that would add a lot
371 // of complexity for a case that is unlikely to occur with MMA
372 // code.
373 if (Opcode != PPC::PHI)
374 continue;
375 if (llvm::is_contained(Range&: PHIs, Element: Instr))
376 return false;
377 PHIs.push_back(Elt: Instr);
378 }
379 VisitedIndex++;
380 }
381 return true;
382}
383
384// This function changes the unprimed accumulator PHI nodes in the PHIs list to
385// primed accumulator PHI nodes. The list is traversed in reverse order to
386// change all the PHI operands of a PHI node before changing the node itself.
387// We keep a map to associate each changed PHI node to its non-changed form.
388void PPCMIPeephole::convertUnprimedAccPHIs(
389 const PPCInstrInfo *TII, MachineRegisterInfo *MRI,
390 SmallVectorImpl<MachineInstr *> &PHIs, Register Dst) {
391 DenseMap<MachineInstr *, MachineInstr *> ChangedPHIMap;
392 for (MachineInstr *PHI : llvm::reverse(C&: PHIs)) {
393 SmallVector<std::pair<MachineOperand, MachineOperand>, 4> PHIOps;
394 // We check if the current PHI node can be changed by looking at its
395 // operands. If all the operands are either copies from primed
396 // accumulators, implicit definitions or other unprimed accumulator
397 // PHI nodes, we change it.
398 for (unsigned PHIOp = 1, NumOps = PHI->getNumOperands(); PHIOp != NumOps;
399 PHIOp += 2) {
400 Register RegOp = PHI->getOperand(i: PHIOp).getReg();
401 MachineInstr *PHIInput = MRI->getVRegDef(Reg: RegOp);
402 unsigned Opcode = PHIInput->getOpcode();
403 assert((Opcode == PPC::COPY || Opcode == PPC::IMPLICIT_DEF ||
404 Opcode == PPC::PHI) &&
405 "Unexpected instruction");
406 if (Opcode == PPC::COPY) {
407 assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) ==
408 &PPC::ACCRCRegClass &&
409 "Unexpected register class");
410 PHIOps.push_back(Elt: {PHIInput->getOperand(i: 1), PHI->getOperand(i: PHIOp + 1)});
411 } else if (Opcode == PPC::IMPLICIT_DEF) {
412 Register AccReg = MRI->createVirtualRegister(RegClass: &PPC::ACCRCRegClass);
413 BuildMI(BB&: *PHIInput->getParent(), I: PHIInput, MIMD: PHIInput->getDebugLoc(),
414 MCID: TII->get(Opcode: PPC::IMPLICIT_DEF), DestReg: AccReg);
415 PHIOps.push_back(Elt: {MachineOperand::CreateReg(Reg: AccReg, isDef: false),
416 PHI->getOperand(i: PHIOp + 1)});
417 } else if (Opcode == PPC::PHI) {
418 // We found a PHI operand. At this point we know this operand
419 // has already been changed so we get its associated changed form
420 // from the map.
421 assert(ChangedPHIMap.count(PHIInput) == 1 &&
422 "This PHI node should have already been changed.");
423 MachineInstr *PrimedAccPHI = ChangedPHIMap.lookup(Val: PHIInput);
424 PHIOps.push_back(Elt: {MachineOperand::CreateReg(
425 Reg: PrimedAccPHI->getOperand(i: 0).getReg(), isDef: false),
426 PHI->getOperand(i: PHIOp + 1)});
427 }
428 }
429 Register AccReg = Dst;
430 // If the PHI node we are changing is the root node, the register it defines
431 // will be the destination register of the original copy (of the PHI def).
432 // For all other PHI's in the list, we need to create another primed
433 // accumulator virtual register as the PHI will no longer define the
434 // unprimed accumulator.
435 if (PHI != PHIs[0])
436 AccReg = MRI->createVirtualRegister(RegClass: &PPC::ACCRCRegClass);
437 MachineInstrBuilder NewPHI = BuildMI(
438 BB&: *PHI->getParent(), I: PHI, MIMD: PHI->getDebugLoc(), MCID: TII->get(Opcode: PPC::PHI), DestReg: AccReg);
439 for (auto RegMBB : PHIOps) {
440 NewPHI.add(MO: RegMBB.first).add(MO: RegMBB.second);
441 if (MRI->isSSA())
442 addRegToUpdate(RegMBB.first.getReg());
443 }
444 // The liveness of old PHI and new PHI have to be updated.
445 addRegToUpdate(PHI->getOperand(0).getReg());
446 addRegToUpdate(AccReg);
447 ChangedPHIMap[PHI] = NewPHI.getInstr();
448 LLVM_DEBUG(dbgs() << "Converting PHI: ");
449 LLVM_DEBUG(PHI->dump());
450 LLVM_DEBUG(dbgs() << "To: ");
451 LLVM_DEBUG(NewPHI.getInstr()->dump());
452 }
453}
454
455// Perform peephole optimizations.
456bool PPCMIPeephole::simplifyCode() {
457 bool Simplified = false;
458 bool TrapOpt = false;
459 MachineInstr* ToErase = nullptr;
460 std::map<MachineInstr *, bool> TOCSaves;
461 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
462 NumFunctionsEnteredInMIPeephole++;
463 if (ConvertRegReg) {
464 // Fixed-point conversion of reg/reg instructions fed by load-immediate
465 // into reg/imm instructions. FIXME: This is expensive, control it with
466 // an option.
467 bool SomethingChanged = false;
468 do {
469 NumFixedPointIterations++;
470 SomethingChanged = false;
471 for (MachineBasicBlock &MBB : *MF) {
472 for (MachineInstr &MI : MBB) {
473 if (MI.isDebugInstr())
474 continue;
475
476 if (!DebugCounter::shouldExecute(Counter&: PeepholeXToICounter))
477 continue;
478
479 SmallSet<Register, 4> RRToRIRegsToUpdate;
480 if (!TII->convertToImmediateForm(MI, RegsToUpdate&: RRToRIRegsToUpdate))
481 continue;
482 for (Register R : RRToRIRegsToUpdate)
483 addRegToUpdate(R);
484 // The updated instruction may now have new register operands.
485 // Conservatively add them to recompute the flags as well.
486 for (const MachineOperand &MO : MI.operands())
487 if (MO.isReg())
488 addRegToUpdate(MO.getReg());
489 // We don't erase anything in case the def has other uses. Let DCE
490 // remove it if it can be removed.
491 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
492 LLVM_DEBUG(MI.dump());
493 NumConvertedToImmediateForm++;
494 SomethingChanged = true;
495 Simplified = true;
496 }
497 }
498 } while (SomethingChanged && FixedPointRegToImm);
499 }
500
501 // Since we are deleting this instruction, we need to run LiveVariables
502 // on any of its definitions that are marked as needing an update since
503 // we can't run LiveVariables on a deleted register. This only needs
504 // to be done for defs since uses will have their own defining
505 // instructions so we won't be running LiveVariables on a deleted reg.
506 auto recomputeLVForDyingInstr = [&]() {
507 if (RegsToUpdate.empty())
508 return;
509 for (MachineOperand &MO : ToErase->operands()) {
510 if (!MO.isReg() || !MO.isDef() || !RegsToUpdate.count(V: MO.getReg()))
511 continue;
512 Register RegToUpdate = MO.getReg();
513 RegsToUpdate.erase(V: RegToUpdate);
514 // If some transformation has introduced an additional definition of
515 // this register (breaking SSA), we can safely convert this def to
516 // a def of an invalid register as the instruction is going away.
517 if (!MRI->getUniqueVRegDef(Reg: RegToUpdate))
518 MO.setReg(PPC::NoRegister);
519 LV->recomputeForSingleDefVirtReg(Reg: RegToUpdate);
520 }
521 };
522
523 for (MachineBasicBlock &MBB : *MF) {
524 for (MachineInstr &MI : MBB) {
525
526 // If the previous instruction was marked for elimination,
527 // remove it now.
528 if (ToErase) {
529 LLVM_DEBUG(dbgs() << "Deleting instruction: ");
530 LLVM_DEBUG(ToErase->dump());
531 recomputeLVForDyingInstr();
532 ToErase->eraseFromParent();
533 ToErase = nullptr;
534 }
535 // If a conditional trap instruction got optimized to an
536 // unconditional trap, eliminate all the instructions after
537 // the trap.
538 if (EnableTrapOptimization && TrapOpt) {
539 ToErase = &MI;
540 continue;
541 }
542
543 // Ignore debug instructions.
544 if (MI.isDebugInstr())
545 continue;
546
547 if (!DebugCounter::shouldExecute(Counter&: PeepholePerOpCounter))
548 continue;
549
550 // Per-opcode peepholes.
551 switch (MI.getOpcode()) {
552
553 default:
554 break;
555 case PPC::COPY: {
556 Register Src = MI.getOperand(i: 1).getReg();
557 Register Dst = MI.getOperand(i: 0).getReg();
558 if (!Src.isVirtual() || !Dst.isVirtual())
559 break;
560 if (MRI->getRegClass(Reg: Src) != &PPC::UACCRCRegClass ||
561 MRI->getRegClass(Reg: Dst) != &PPC::ACCRCRegClass)
562 break;
563
564 // We are copying an unprimed accumulator to a primed accumulator.
565 // If the input to the copy is a PHI that is fed only by (i) copies in
566 // the other direction (ii) implicitly defined unprimed accumulators or
567 // (iii) other PHI nodes satisfying (i) and (ii), we can change
568 // the PHI to a PHI on primed accumulators (as long as we also change
569 // its operands). To detect and change such copies, we first get a list
570 // of all the PHI nodes starting from the root PHI node in BFS order.
571 // We then visit all these PHI nodes to check if they can be changed to
572 // primed accumulator PHI nodes and if so, we change them.
573 MachineInstr *RootPHI = MRI->getVRegDef(Reg: Src);
574 if (RootPHI->getOpcode() != PPC::PHI)
575 break;
576
577 SmallVector<MachineInstr *, 4> PHIs;
578 if (!collectUnprimedAccPHIs(MRI, RootPHI, PHIs))
579 break;
580
581 convertUnprimedAccPHIs(TII, MRI, PHIs, Dst);
582
583 ToErase = &MI;
584 break;
585 }
586 case PPC::LI:
587 case PPC::LI8: {
588 // If we are materializing a zero, look for any use operands for which
589 // zero means immediate zero. All such operands can be replaced with
590 // PPC::ZERO.
591 if (!MI.getOperand(i: 1).isImm() || MI.getOperand(i: 1).getImm() != 0)
592 break;
593 Register MIDestReg = MI.getOperand(i: 0).getReg();
594 bool Folded = false;
595 for (MachineInstr& UseMI : MRI->use_instructions(Reg: MIDestReg))
596 Folded |= TII->onlyFoldImmediate(UseMI, DefMI&: MI, Reg: MIDestReg);
597 if (MRI->use_nodbg_empty(RegNo: MIDestReg)) {
598 ++NumLoadImmZeroFoldedAndRemoved;
599 ToErase = &MI;
600 }
601 if (Folded)
602 addRegToUpdate(MIDestReg);
603 Simplified |= Folded;
604 break;
605 }
606 case PPC::STW:
607 case PPC::STD: {
608 MachineFrameInfo &MFI = MF->getFrameInfo();
609 if (MFI.hasVarSizedObjects() ||
610 (!MF->getSubtarget<PPCSubtarget>().isELFv2ABI() &&
611 !MF->getSubtarget<PPCSubtarget>().isAIXABI()))
612 break;
613 // When encountering a TOC save instruction, call UpdateTOCSaves
614 // to add it to the TOCSaves map and mark any existing TOC saves
615 // it dominates as redundant.
616 if (TII->isTOCSaveMI(MI))
617 UpdateTOCSaves(TOCSaves, MI: &MI);
618 break;
619 }
620 case PPC::XXPERMDI: {
621 // Perform simplifications of 2x64 vector swaps and splats.
622 // A swap is identified by an immediate value of 2, and a splat
623 // is identified by an immediate value of 0 or 3.
624 int Immed = MI.getOperand(i: 3).getImm();
625
626 if (Immed == 1)
627 break;
628
629 // For each of these simplifications, we need the two source
630 // regs to match. Unfortunately, MachineCSE ignores COPY and
631 // SUBREG_TO_REG, so for example we can see
632 // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed.
633 // We have to look through chains of COPY and SUBREG_TO_REG
634 // to find the real source values for comparison.
635 Register TrueReg1 =
636 TRI->lookThruCopyLike(SrcReg: MI.getOperand(i: 1).getReg(), MRI);
637 Register TrueReg2 =
638 TRI->lookThruCopyLike(SrcReg: MI.getOperand(i: 2).getReg(), MRI);
639
640 if (!(TrueReg1 == TrueReg2 && TrueReg1.isVirtual()))
641 break;
642
643 MachineInstr *DefMI = MRI->getVRegDef(Reg: TrueReg1);
644
645 if (!DefMI)
646 break;
647
648 unsigned DefOpc = DefMI->getOpcode();
649
650 // If this is a splat fed by a splatting load, the splat is
651 // redundant. Replace with a copy. This doesn't happen directly due
652 // to code in PPCDAGToDAGISel.cpp, but it can happen when converting
653 // a load of a double to a vector of 64-bit integers.
654 auto isConversionOfLoadAndSplat = [=]() -> bool {
655 if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS)
656 return false;
657 Register FeedReg1 =
658 TRI->lookThruCopyLike(SrcReg: DefMI->getOperand(i: 1).getReg(), MRI);
659 if (FeedReg1.isVirtual()) {
660 MachineInstr *LoadMI = MRI->getVRegDef(Reg: FeedReg1);
661 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX)
662 return true;
663 }
664 return false;
665 };
666 if ((Immed == 0 || Immed == 3) &&
667 (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat())) {
668 LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat "
669 "to load-and-splat/copy: ");
670 LLVM_DEBUG(MI.dump());
671 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::COPY),
672 DestReg: MI.getOperand(i: 0).getReg())
673 .add(MO: MI.getOperand(i: 1));
674 addRegToUpdate(MI.getOperand(1).getReg());
675 ToErase = &MI;
676 Simplified = true;
677 }
678
679 // If this is a splat or a swap fed by another splat, we
680 // can replace it with a copy.
681 if (DefOpc == PPC::XXPERMDI) {
682 Register DefReg1 = DefMI->getOperand(i: 1).getReg();
683 Register DefReg2 = DefMI->getOperand(i: 2).getReg();
684 unsigned DefImmed = DefMI->getOperand(i: 3).getImm();
685
686 // If the two inputs are not the same register, check to see if
687 // they originate from the same virtual register after only
688 // copy-like instructions.
689 if (DefReg1 != DefReg2) {
690 Register FeedReg1 = TRI->lookThruCopyLike(SrcReg: DefReg1, MRI);
691 Register FeedReg2 = TRI->lookThruCopyLike(SrcReg: DefReg2, MRI);
692
693 if (!(FeedReg1 == FeedReg2 && FeedReg1.isVirtual()))
694 break;
695 }
696
697 if (DefImmed == 0 || DefImmed == 3) {
698 LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat "
699 "to splat/copy: ");
700 LLVM_DEBUG(MI.dump());
701 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::COPY),
702 DestReg: MI.getOperand(i: 0).getReg())
703 .add(MO: MI.getOperand(i: 1));
704 addRegToUpdate(MI.getOperand(1).getReg());
705 ToErase = &MI;
706 Simplified = true;
707 }
708
709 // If this is a splat fed by a swap, we can simplify modify
710 // the splat to splat the other value from the swap's input
711 // parameter.
712 else if ((Immed == 0 || Immed == 3) && DefImmed == 2) {
713 LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
714 LLVM_DEBUG(MI.dump());
715 addRegToUpdate(MI.getOperand(1).getReg());
716 addRegToUpdate(MI.getOperand(2).getReg());
717 MI.getOperand(i: 1).setReg(DefReg1);
718 MI.getOperand(i: 2).setReg(DefReg2);
719 MI.getOperand(i: 3).setImm(3 - Immed);
720 addRegToUpdate(DefReg1);
721 addRegToUpdate(DefReg2);
722 Simplified = true;
723 }
724
725 // If this is a swap fed by a swap, we can replace it
726 // with a copy from the first swap's input.
727 else if (Immed == 2 && DefImmed == 2) {
728 LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
729 LLVM_DEBUG(MI.dump());
730 addRegToUpdate(MI.getOperand(1).getReg());
731
732 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::COPY),
733 DestReg: MI.getOperand(i: 0).getReg())
734 .add(MO: DefMI->getOperand(i: 1));
735 addRegToUpdate(DefMI->getOperand(0).getReg());
736 addRegToUpdate(DefMI->getOperand(1).getReg());
737 ToErase = &MI;
738 Simplified = true;
739 }
740 } else if ((Immed == 0 || Immed == 3 || Immed == 2) &&
741 DefOpc == PPC::XXPERMDIs &&
742 (DefMI->getOperand(i: 2).getImm() == 0 ||
743 DefMI->getOperand(i: 2).getImm() == 3)) {
744
745 if (!MRI->hasOneNonDBGUser(RegNo: DefMI->getOperand(i: 0).getReg()))
746 break;
747 Simplified = true;
748 // Swap of a splat, convert to copy.
749 if (Immed == 2) {
750 LLVM_DEBUG(dbgs() << "Optimizing swap(splat) => copy(splat): ");
751 LLVM_DEBUG(MI.dump());
752 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::COPY),
753 DestReg: MI.getOperand(i: 0).getReg())
754 .add(MO: MI.getOperand(i: 1));
755 addRegToUpdate(MI.getOperand(1).getReg());
756 ToErase = &MI;
757 break;
758 }
759 // Splat fed by another splat - switch the output of the first
760 // and remove the second.
761 ToErase = &MI;
762 DefMI->getOperand(i: 0).setReg(MI.getOperand(i: 0).getReg());
763 LLVM_DEBUG(dbgs() << "Removing redundant splat: ");
764 LLVM_DEBUG(MI.dump());
765 } else if (Immed == 2 &&
766 (DefOpc == PPC::VSPLTB || DefOpc == PPC::VSPLTH ||
767 DefOpc == PPC::VSPLTW || DefOpc == PPC::XXSPLTW ||
768 DefOpc == PPC::VSPLTISB || DefOpc == PPC::VSPLTISH ||
769 DefOpc == PPC::VSPLTISW)) {
770 // Swap of various vector splats, convert to copy.
771 ToErase = &MI;
772 Simplified = true;
773 LLVM_DEBUG(dbgs() << "Optimizing swap(vsplt(is)?[b|h|w]|xxspltw) => "
774 "copy(vsplt(is)?[b|h|w]|xxspltw): ");
775 LLVM_DEBUG(MI.dump());
776 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::COPY),
777 DestReg: MI.getOperand(i: 0).getReg())
778 .add(MO: MI.getOperand(i: 1));
779 addRegToUpdate(MI.getOperand(1).getReg());
780 } else if ((Immed == 0 || Immed == 3 || Immed == 2) &&
781 TII->isLoadFromConstantPool(I: DefMI)) {
782 const Constant *C = TII->getConstantFromConstantPool(I: DefMI);
783 if (C && C->getType()->isVectorTy() && C->getSplatValue()) {
784 ToErase = &MI;
785 Simplified = true;
786 LLVM_DEBUG(dbgs()
787 << "Optimizing swap(splat pattern from constant-pool) "
788 "=> copy(splat pattern from constant-pool): ");
789 LLVM_DEBUG(MI.dump());
790 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::COPY),
791 DestReg: MI.getOperand(i: 0).getReg())
792 .add(MO: MI.getOperand(i: 1));
793 addRegToUpdate(MI.getOperand(1).getReg());
794 }
795 }
796 break;
797 }
798 case PPC::VSPLTB:
799 case PPC::VSPLTH:
800 case PPC::XXSPLTW: {
801 unsigned MyOpcode = MI.getOpcode();
802 // The operand number of the source register in the splat instruction.
803 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
804 Register TrueReg =
805 TRI->lookThruCopyLike(SrcReg: MI.getOperand(i: OpNo).getReg(), MRI);
806 if (!TrueReg.isVirtual())
807 break;
808 MachineInstr *DefMI = MRI->getVRegDef(Reg: TrueReg);
809 if (!DefMI)
810 break;
811 unsigned DefOpcode = DefMI->getOpcode();
812 auto isConvertOfSplat = [=]() -> bool {
813 if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS)
814 return false;
815 Register ConvReg = DefMI->getOperand(i: 1).getReg();
816 if (!ConvReg.isVirtual())
817 return false;
818 MachineInstr *Splt = MRI->getVRegDef(Reg: ConvReg);
819 return Splt && (Splt->getOpcode() == PPC::LXVWSX ||
820 Splt->getOpcode() == PPC::XXSPLTW);
821 };
822 bool AlreadySplat = (MyOpcode == DefOpcode) ||
823 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) ||
824 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) ||
825 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) ||
826 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) ||
827 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)||
828 (MyOpcode == PPC::XXSPLTW && isConvertOfSplat());
829
830 // If the instruction[s] that feed this splat have already splat
831 // the value, this splat is redundant.
832 if (AlreadySplat) {
833 LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: ");
834 LLVM_DEBUG(MI.dump());
835 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::COPY),
836 DestReg: MI.getOperand(i: 0).getReg())
837 .add(MO: MI.getOperand(i: OpNo));
838 addRegToUpdate(MI.getOperand(OpNo).getReg());
839 ToErase = &MI;
840 Simplified = true;
841 }
842
843 // Splat fed by a shift. Usually when we align value to splat into
844 // vector element zero.
845 if (DefOpcode == PPC::XXSLDWI) {
846 Register ShiftOp1 = DefMI->getOperand(i: 1).getReg();
847
848 if (ShiftOp1 == DefMI->getOperand(i: 2).getReg()) {
849 // For example, We can erase XXSLDWI from in following:
850 // %2:vrrc = XXSLDWI killed %1:vrrc, %1:vrrc, 1
851 // %6:vrrc = VSPLTB 15, killed %2:vrrc
852 // %7:vsrc = XXLAND killed %6:vrrc, killed %1:vrrc
853 //
854 // --->
855 //
856 // %6:vrrc = VSPLTB 3, killed %1:vrrc
857 // %7:vsrc = XXLAND killed %6:vrrc, killed %1:vrrc
858
859 if (MRI->hasOneNonDBGUse(RegNo: DefMI->getOperand(i: 0).getReg())) {
860 LLVM_DEBUG(dbgs() << "Removing redundant shift: ");
861 LLVM_DEBUG(DefMI->dump());
862 ToErase = DefMI;
863 }
864 Simplified = true;
865 unsigned ShiftImm = DefMI->getOperand(i: 3).getImm();
866 // The operand number of the splat Imm in the instruction.
867 unsigned SplatImmNo = MyOpcode == PPC::XXSPLTW ? 2 : 1;
868 unsigned SplatImm = MI.getOperand(i: SplatImmNo).getImm();
869
870 // Calculate the new splat-element immediate. We need to convert the
871 // element index into the proper unit (byte for VSPLTB, halfword for
872 // VSPLTH, word for VSPLTW) because PPC::XXSLDWI interprets its
873 // ShiftImm in 32-bit word units.
874 auto CalculateNewElementIdx = [&](unsigned Opcode) {
875 if (Opcode == PPC::VSPLTB)
876 return (SplatImm + ShiftImm * 4) & 0xF;
877 else if (Opcode == PPC::VSPLTH)
878 return (SplatImm + ShiftImm * 2) & 0x7;
879 else
880 return (SplatImm + ShiftImm) & 0x3;
881 };
882
883 unsigned NewElem = CalculateNewElementIdx(MyOpcode);
884
885 LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm
886 << " to " << NewElem << " in instruction: ");
887 LLVM_DEBUG(MI.dump());
888 if (!MRI->constrainRegClass(Reg: ShiftOp1, RC: &PPC::VRRCRegClass))
889 llvm_unreachable("Can't fail because vrrc is subset of vsrc");
890 addRegToUpdate(MI.getOperand(OpNo).getReg());
891 addRegToUpdate(ShiftOp1);
892 MI.getOperand(i: OpNo).setReg(ShiftOp1);
893 MI.getOperand(i: SplatImmNo).setImm(NewElem);
894 }
895 }
896 break;
897 }
898 case PPC::XVCVDPSP: {
899 // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
900 Register TrueReg =
901 TRI->lookThruCopyLike(SrcReg: MI.getOperand(i: 1).getReg(), MRI);
902 if (!TrueReg.isVirtual())
903 break;
904 MachineInstr *DefMI = MRI->getVRegDef(Reg: TrueReg);
905
906 // This can occur when building a vector of single precision or integer
907 // values.
908 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
909 Register DefsReg1 =
910 TRI->lookThruCopyLike(SrcReg: DefMI->getOperand(i: 1).getReg(), MRI);
911 Register DefsReg2 =
912 TRI->lookThruCopyLike(SrcReg: DefMI->getOperand(i: 2).getReg(), MRI);
913 if (!DefsReg1.isVirtual() || !DefsReg2.isVirtual())
914 break;
915 MachineInstr *P1 = MRI->getVRegDef(Reg: DefsReg1);
916 MachineInstr *P2 = MRI->getVRegDef(Reg: DefsReg2);
917
918 if (!P1 || !P2)
919 break;
920
921 // Remove the passed FRSP/XSRSP instruction if it only feeds this MI
922 // and set any uses of that FRSP/XSRSP (in this MI) to the source of
923 // the FRSP/XSRSP.
924 auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) {
925 unsigned Opc = RoundInstr->getOpcode();
926 if ((Opc == PPC::FRSP || Opc == PPC::XSRSP) &&
927 MRI->hasOneNonDBGUse(RegNo: RoundInstr->getOperand(i: 0).getReg())) {
928 Simplified = true;
929 Register ConvReg1 = RoundInstr->getOperand(i: 1).getReg();
930 Register FRSPDefines = RoundInstr->getOperand(i: 0).getReg();
931 MachineInstr &Use = *(MRI->use_instr_nodbg_begin(RegNo: FRSPDefines));
932 for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
933 if (Use.getOperand(i).isReg() &&
934 Use.getOperand(i).getReg() == FRSPDefines)
935 Use.getOperand(i).setReg(ConvReg1);
936 LLVM_DEBUG(dbgs() << "Removing redundant FRSP/XSRSP:\n");
937 LLVM_DEBUG(RoundInstr->dump());
938 LLVM_DEBUG(dbgs() << "As it feeds instruction:\n");
939 LLVM_DEBUG(MI.dump());
940 LLVM_DEBUG(dbgs() << "Through instruction:\n");
941 LLVM_DEBUG(DefMI->dump());
942 addRegToUpdate(ConvReg1);
943 addRegToUpdate(FRSPDefines);
944 ToErase = RoundInstr;
945 }
946 };
947
948 // If the input to XVCVDPSP is a vector that was built (even
949 // partially) out of FRSP's, the FRSP(s) can safely be removed
950 // since this instruction performs the same operation.
951 if (P1 != P2) {
952 removeFRSPIfPossible(P1);
953 removeFRSPIfPossible(P2);
954 break;
955 }
956 removeFRSPIfPossible(P1);
957 }
958 break;
959 }
960 case PPC::EXTSH:
961 case PPC::EXTSH8:
962 case PPC::EXTSH8_32_64: {
963 if (!EnableSExtElimination) break;
964 Register NarrowReg = MI.getOperand(i: 1).getReg();
965 if (!NarrowReg.isVirtual())
966 break;
967
968 MachineInstr *SrcMI = MRI->getVRegDef(Reg: NarrowReg);
969 unsigned SrcOpcode = SrcMI->getOpcode();
970 // If we've used a zero-extending load that we will sign-extend,
971 // just do a sign-extending load.
972 if (SrcOpcode == PPC::LHZ || SrcOpcode == PPC::LHZX) {
973 if (!MRI->hasOneNonDBGUse(RegNo: SrcMI->getOperand(i: 0).getReg()))
974 break;
975 // Determine the new opcode. We need to make sure that if the original
976 // instruction has a 64 bit opcode we keep using a 64 bit opcode.
977 // Likewise if the source is X-Form the new opcode should also be
978 // X-Form.
979 unsigned Opc = PPC::LHA;
980 bool SourceIsXForm = SrcOpcode == PPC::LHZX;
981 bool MIIs64Bit = MI.getOpcode() == PPC::EXTSH8 ||
982 MI.getOpcode() == PPC::EXTSH8_32_64;
983
984 if (SourceIsXForm && MIIs64Bit)
985 Opc = PPC::LHAX8;
986 else if (SourceIsXForm && !MIIs64Bit)
987 Opc = PPC::LHAX;
988 else if (MIIs64Bit)
989 Opc = PPC::LHA8;
990
991 addRegToUpdate(NarrowReg);
992 addRegToUpdate(MI.getOperand(0).getReg());
993
994 // We are removing a definition of NarrowReg which will cause
995 // problems in AliveBlocks. Add an implicit def that will be
996 // removed so that AliveBlocks are updated correctly.
997 addDummyDef(MBB, At: &MI, Reg: NarrowReg);
998 LLVM_DEBUG(dbgs() << "Zero-extending load\n");
999 LLVM_DEBUG(SrcMI->dump());
1000 LLVM_DEBUG(dbgs() << "and sign-extension\n");
1001 LLVM_DEBUG(MI.dump());
1002 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
1003 SrcMI->setDesc(TII->get(Opcode: Opc));
1004 SrcMI->getOperand(i: 0).setReg(MI.getOperand(i: 0).getReg());
1005 ToErase = &MI;
1006 Simplified = true;
1007 NumEliminatedSExt++;
1008 }
1009 break;
1010 }
1011 case PPC::EXTSW:
1012 case PPC::EXTSW_32:
1013 case PPC::EXTSW_32_64: {
1014 if (!EnableSExtElimination) break;
1015 Register NarrowReg = MI.getOperand(i: 1).getReg();
1016 if (!NarrowReg.isVirtual())
1017 break;
1018
1019 MachineInstr *SrcMI = MRI->getVRegDef(Reg: NarrowReg);
1020 unsigned SrcOpcode = SrcMI->getOpcode();
1021 // If we've used a zero-extending load that we will sign-extend,
1022 // just do a sign-extending load.
1023 if (SrcOpcode == PPC::LWZ || SrcOpcode == PPC::LWZX) {
1024 if (!MRI->hasOneNonDBGUse(RegNo: SrcMI->getOperand(i: 0).getReg()))
1025 break;
1026
1027 // The transformation from a zero-extending load to a sign-extending
1028 // load is only legal when the displacement is a multiple of 4.
1029 // If the displacement is not at least 4 byte aligned, don't perform
1030 // the transformation.
1031 bool IsWordAligned = false;
1032 if (SrcMI->getOperand(i: 1).isGlobal()) {
1033 const GlobalVariable *GV =
1034 dyn_cast<GlobalVariable>(Val: SrcMI->getOperand(i: 1).getGlobal());
1035 if (GV && GV->getAlign() && *GV->getAlign() >= 4 &&
1036 (SrcMI->getOperand(i: 1).getOffset() % 4 == 0))
1037 IsWordAligned = true;
1038 } else if (SrcMI->getOperand(i: 1).isImm()) {
1039 int64_t Value = SrcMI->getOperand(i: 1).getImm();
1040 if (Value % 4 == 0)
1041 IsWordAligned = true;
1042 }
1043
1044 // Determine the new opcode. We need to make sure that if the original
1045 // instruction has a 64 bit opcode we keep using a 64 bit opcode.
1046 // Likewise if the source is X-Form the new opcode should also be
1047 // X-Form.
1048 unsigned Opc = PPC::LWA_32;
1049 bool SourceIsXForm = SrcOpcode == PPC::LWZX;
1050 bool MIIs64Bit = MI.getOpcode() == PPC::EXTSW ||
1051 MI.getOpcode() == PPC::EXTSW_32_64;
1052
1053 if (SourceIsXForm && MIIs64Bit)
1054 Opc = PPC::LWAX;
1055 else if (SourceIsXForm && !MIIs64Bit)
1056 Opc = PPC::LWAX_32;
1057 else if (MIIs64Bit)
1058 Opc = PPC::LWA;
1059
1060 if (!IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32))
1061 break;
1062
1063 addRegToUpdate(NarrowReg);
1064 addRegToUpdate(MI.getOperand(0).getReg());
1065
1066 // We are removing a definition of NarrowReg which will cause
1067 // problems in AliveBlocks. Add an implicit def that will be
1068 // removed so that AliveBlocks are updated correctly.
1069 addDummyDef(MBB, At: &MI, Reg: NarrowReg);
1070 LLVM_DEBUG(dbgs() << "Zero-extending load\n");
1071 LLVM_DEBUG(SrcMI->dump());
1072 LLVM_DEBUG(dbgs() << "and sign-extension\n");
1073 LLVM_DEBUG(MI.dump());
1074 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
1075 SrcMI->setDesc(TII->get(Opcode: Opc));
1076 SrcMI->getOperand(i: 0).setReg(MI.getOperand(i: 0).getReg());
1077 ToErase = &MI;
1078 Simplified = true;
1079 NumEliminatedSExt++;
1080 } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
1081 TII->isSignExtended(Reg: NarrowReg, MRI)) {
1082 // We can eliminate EXTSW if the input is known to be already
1083 // sign-extended. However, we are not sure whether a spill will occur
1084 // during register allocation. If there is no promotion, it will use
1085 // 'stw' instead of 'std', and 'lwz' instead of 'ld' when spilling,
1086 // since the register class is 32-bits. Consequently, the high 32-bit
1087 // information will be lost. Therefore, all these instructions in the
1088 // chain used to deduce sign extension to eliminate the 'extsw' will
1089 // need to be promoted to 64-bit pseudo instructions when the 'extsw'
1090 // is eliminated.
1091 TII->promoteInstr32To64ForElimEXTSW(Reg: NarrowReg, MRI, BinOpDepth: 0, LV);
1092
1093 LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
1094 Register TmpReg =
1095 MF->getRegInfo().createVirtualRegister(RegClass: &PPC::G8RCRegClass);
1096 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::IMPLICIT_DEF),
1097 DestReg: TmpReg);
1098 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::INSERT_SUBREG),
1099 DestReg: MI.getOperand(i: 0).getReg())
1100 .addReg(RegNo: TmpReg)
1101 .addReg(RegNo: NarrowReg)
1102 .addImm(Val: PPC::sub_32);
1103 ToErase = &MI;
1104 Simplified = true;
1105 NumEliminatedSExt++;
1106 }
1107 break;
1108 }
1109 case PPC::RLDICL: {
1110 // We can eliminate RLDICL (e.g. for zero-extension)
1111 // if all bits to clear are already zero in the input.
1112 // This code assume following code sequence for zero-extension.
1113 // %6 = COPY %5:sub_32; (optional)
1114 // %8 = IMPLICIT_DEF;
1115 // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32;
1116 if (!EnableZExtElimination) break;
1117
1118 if (MI.getOperand(i: 2).getImm() != 0)
1119 break;
1120
1121 Register SrcReg = MI.getOperand(i: 1).getReg();
1122 if (!SrcReg.isVirtual())
1123 break;
1124
1125 MachineInstr *SrcMI = MRI->getVRegDef(Reg: SrcReg);
1126 if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG &&
1127 SrcMI->getOperand(i: 0).isReg() && SrcMI->getOperand(i: 1).isReg()))
1128 break;
1129
1130 MachineInstr *ImpDefMI, *SubRegMI;
1131 ImpDefMI = MRI->getVRegDef(Reg: SrcMI->getOperand(i: 1).getReg());
1132 SubRegMI = MRI->getVRegDef(Reg: SrcMI->getOperand(i: 2).getReg());
1133 if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break;
1134
1135 SrcMI = SubRegMI;
1136 if (SubRegMI->getOpcode() == PPC::COPY) {
1137 Register CopyReg = SubRegMI->getOperand(i: 1).getReg();
1138 if (CopyReg.isVirtual())
1139 SrcMI = MRI->getVRegDef(Reg: CopyReg);
1140 }
1141 if (!SrcMI->getOperand(i: 0).isReg())
1142 break;
1143
1144 unsigned KnownZeroCount =
1145 getKnownLeadingZeroCount(Reg: SrcMI->getOperand(i: 0).getReg(), TII, MRI);
1146 if (MI.getOperand(i: 3).getImm() <= KnownZeroCount) {
1147 LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
1148 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::COPY),
1149 DestReg: MI.getOperand(i: 0).getReg())
1150 .addReg(RegNo: SrcReg);
1151 addRegToUpdate(SrcReg);
1152 ToErase = &MI;
1153 Simplified = true;
1154 NumEliminatedZExt++;
1155 }
1156 break;
1157 }
1158
1159 // TODO: Any instruction that has an immediate form fed only by a PHI
1160 // whose operands are all load immediate can be folded away. We currently
1161 // do this for ADD instructions, but should expand it to arithmetic and
1162 // binary instructions with immediate forms in the future.
1163 case PPC::ADD4:
1164 case PPC::ADD8: {
1165 auto isSingleUsePHI = [&](MachineOperand *PhiOp) {
1166 assert(PhiOp && "Invalid Operand!");
1167 MachineInstr *DefPhiMI = getVRegDefOrNull(Op: PhiOp, MRI);
1168
1169 return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) &&
1170 MRI->hasOneNonDBGUse(RegNo: DefPhiMI->getOperand(i: 0).getReg());
1171 };
1172
1173 auto dominatesAllSingleUseLIs = [&](MachineOperand *DominatorOp,
1174 MachineOperand *PhiOp) {
1175 assert(PhiOp && "Invalid Operand!");
1176 assert(DominatorOp && "Invalid Operand!");
1177 MachineInstr *DefPhiMI = getVRegDefOrNull(Op: PhiOp, MRI);
1178 MachineInstr *DefDomMI = getVRegDefOrNull(Op: DominatorOp, MRI);
1179
1180 // Note: the vregs only show up at odd indices position of PHI Node,
1181 // the even indices position save the BB info.
1182 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
1183 MachineInstr *LiMI =
1184 getVRegDefOrNull(Op: &DefPhiMI->getOperand(i), MRI);
1185 if (!LiMI ||
1186 (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8)
1187 || !MRI->hasOneNonDBGUse(RegNo: LiMI->getOperand(i: 0).getReg()) ||
1188 !MDT->dominates(A: DefDomMI, B: LiMI))
1189 return false;
1190 }
1191
1192 return true;
1193 };
1194
1195 MachineOperand Op1 = MI.getOperand(i: 1);
1196 MachineOperand Op2 = MI.getOperand(i: 2);
1197 if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2))
1198 std::swap(a&: Op1, b&: Op2);
1199 else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1))
1200 break; // We don't have an ADD fed by LI's that can be transformed
1201
1202 // Now we know that Op1 is the PHI node and Op2 is the dominator
1203 Register DominatorReg = Op2.getReg();
1204
1205 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8
1206 ? &PPC::G8RC_and_G8RC_NOX0RegClass
1207 : &PPC::GPRC_and_GPRC_NOR0RegClass;
1208 MRI->setRegClass(Reg: DominatorReg, RC: TRC);
1209
1210 // replace LIs with ADDIs
1211 MachineInstr *DefPhiMI = getVRegDefOrNull(Op: &Op1, MRI);
1212 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
1213 MachineInstr *LiMI = getVRegDefOrNull(Op: &DefPhiMI->getOperand(i), MRI);
1214 LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: ");
1215 LLVM_DEBUG(LiMI->dump());
1216
1217 // There could be repeated registers in the PHI, e.g: %1 =
1218 // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've
1219 // already replaced the def instruction, skip.
1220 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8)
1221 continue;
1222
1223 assert((LiMI->getOpcode() == PPC::LI ||
1224 LiMI->getOpcode() == PPC::LI8) &&
1225 "Invalid Opcode!");
1226 auto LiImm = LiMI->getOperand(i: 1).getImm(); // save the imm of LI
1227 LiMI->removeOperand(OpNo: 1); // remove the imm of LI
1228 LiMI->setDesc(TII->get(Opcode: LiMI->getOpcode() == PPC::LI ? PPC::ADDI
1229 : PPC::ADDI8));
1230 MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI)
1231 .addReg(RegNo: DominatorReg)
1232 .addImm(Val: LiImm); // restore the imm of LI
1233 LLVM_DEBUG(LiMI->dump());
1234 }
1235
1236 // Replace ADD with COPY
1237 LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: ");
1238 LLVM_DEBUG(MI.dump());
1239 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::COPY),
1240 DestReg: MI.getOperand(i: 0).getReg())
1241 .add(MO: Op1);
1242 addRegToUpdate(Op1.getReg());
1243 addRegToUpdate(Op2.getReg());
1244 ToErase = &MI;
1245 Simplified = true;
1246 NumOptADDLIs++;
1247 break;
1248 }
1249 case PPC::RLDICR: {
1250 Simplified |= emitRLDICWhenLoweringJumpTables(MI, ToErase) ||
1251 combineSEXTAndSHL(MI, ToErase);
1252 break;
1253 }
1254 case PPC::ANDI_rec:
1255 case PPC::ANDI8_rec:
1256 case PPC::ANDIS_rec:
1257 case PPC::ANDIS8_rec: {
1258 Register TrueReg =
1259 TRI->lookThruCopyLike(SrcReg: MI.getOperand(i: 1).getReg(), MRI);
1260 if (!TrueReg.isVirtual() || !MRI->hasOneNonDBGUse(RegNo: TrueReg))
1261 break;
1262
1263 MachineInstr *SrcMI = MRI->getVRegDef(Reg: TrueReg);
1264 if (!SrcMI)
1265 break;
1266
1267 unsigned SrcOpCode = SrcMI->getOpcode();
1268 if (SrcOpCode != PPC::RLDICL && SrcOpCode != PPC::RLDICR)
1269 break;
1270
1271 Register SrcReg, DstReg;
1272 SrcReg = SrcMI->getOperand(i: 1).getReg();
1273 DstReg = MI.getOperand(i: 1).getReg();
1274 const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(Reg: SrcReg);
1275 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Reg: DstReg);
1276 if (DstRC != SrcRC)
1277 break;
1278
1279 uint64_t AndImm = MI.getOperand(i: 2).getImm();
1280 if (MI.getOpcode() == PPC::ANDIS_rec ||
1281 MI.getOpcode() == PPC::ANDIS8_rec)
1282 AndImm <<= 16;
1283 uint64_t LZeroAndImm = llvm::countl_zero<uint64_t>(Val: AndImm);
1284 uint64_t RZeroAndImm = llvm::countr_zero<uint64_t>(Val: AndImm);
1285 uint64_t ImmSrc = SrcMI->getOperand(i: 3).getImm();
1286
1287 // We can transfer `RLDICL/RLDICR + ANDI_rec/ANDIS_rec` to `ANDI_rec 0`
1288 // if all bits to AND are already zero in the input.
1289 bool PatternResultZero =
1290 (SrcOpCode == PPC::RLDICL && (RZeroAndImm + ImmSrc > 63)) ||
1291 (SrcOpCode == PPC::RLDICR && LZeroAndImm > ImmSrc);
1292
1293 // We can eliminate RLDICL/RLDICR if it's used to clear bits and all
1294 // bits cleared will be ANDed with 0 by ANDI_rec/ANDIS_rec.
1295 bool PatternRemoveRotate =
1296 SrcMI->getOperand(i: 2).getImm() == 0 &&
1297 ((SrcOpCode == PPC::RLDICL && LZeroAndImm >= ImmSrc) ||
1298 (SrcOpCode == PPC::RLDICR && (RZeroAndImm + ImmSrc > 63)));
1299
1300 if (!PatternResultZero && !PatternRemoveRotate)
1301 break;
1302
1303 LLVM_DEBUG(dbgs() << "Combining pair: ");
1304 LLVM_DEBUG(SrcMI->dump());
1305 LLVM_DEBUG(MI.dump());
1306 if (PatternResultZero)
1307 MI.getOperand(i: 2).setImm(0);
1308 MI.getOperand(i: 1).setReg(SrcMI->getOperand(i: 1).getReg());
1309 LLVM_DEBUG(dbgs() << "To: ");
1310 LLVM_DEBUG(MI.dump());
1311 addRegToUpdate(MI.getOperand(1).getReg());
1312 addRegToUpdate(SrcMI->getOperand(0).getReg());
1313 Simplified = true;
1314 break;
1315 }
1316 case PPC::RLWINM:
1317 case PPC::RLWINM_rec:
1318 case PPC::RLWINM8:
1319 case PPC::RLWINM8_rec: {
1320 // We might replace operand 1 of the instruction which will
1321 // require we recompute kill flags for it.
1322 Register OrigOp1Reg = MI.getOperand(i: 1).isReg()
1323 ? MI.getOperand(i: 1).getReg()
1324 : PPC::NoRegister;
1325 Simplified = TII->combineRLWINM(MI, ToErase: &ToErase);
1326 if (Simplified) {
1327 addRegToUpdate(OrigOp1Reg);
1328 if (MI.getOperand(i: 1).isReg())
1329 addRegToUpdate(MI.getOperand(1).getReg());
1330 if (ToErase && ToErase->getOperand(i: 1).isReg())
1331 for (auto UseReg : ToErase->explicit_uses())
1332 if (UseReg.isReg())
1333 addRegToUpdate(UseReg.getReg());
1334 ++NumRotatesCollapsed;
1335 }
1336 break;
1337 }
1338 // We will replace TD/TW/TDI/TWI with an unconditional trap if it will
1339 // always trap, we will delete the node if it will never trap.
1340 case PPC::TDI:
1341 case PPC::TWI:
1342 case PPC::TD:
1343 case PPC::TW: {
1344 if (!EnableTrapOptimization) break;
1345 MachineInstr *LiMI1 = getVRegDefOrNull(Op: &MI.getOperand(i: 1), MRI);
1346 MachineInstr *LiMI2 = getVRegDefOrNull(Op: &MI.getOperand(i: 2), MRI);
1347 bool IsOperand2Immediate = MI.getOperand(i: 2).isImm();
1348 // We can only do the optimization if we can get immediates
1349 // from both operands
1350 if (!(LiMI1 && (LiMI1->getOpcode() == PPC::LI ||
1351 LiMI1->getOpcode() == PPC::LI8)))
1352 break;
1353 if (!IsOperand2Immediate &&
1354 !(LiMI2 && (LiMI2->getOpcode() == PPC::LI ||
1355 LiMI2->getOpcode() == PPC::LI8)))
1356 break;
1357
1358 auto ImmOperand0 = MI.getOperand(i: 0).getImm();
1359 auto ImmOperand1 = LiMI1->getOperand(i: 1).getImm();
1360 auto ImmOperand2 = IsOperand2Immediate ? MI.getOperand(i: 2).getImm()
1361 : LiMI2->getOperand(i: 1).getImm();
1362
1363 // We will replace the MI with an unconditional trap if it will always
1364 // trap.
1365 if ((ImmOperand0 == 31) ||
1366 ((ImmOperand0 & 0x10) &&
1367 ((int64_t)ImmOperand1 < (int64_t)ImmOperand2)) ||
1368 ((ImmOperand0 & 0x8) &&
1369 ((int64_t)ImmOperand1 > (int64_t)ImmOperand2)) ||
1370 ((ImmOperand0 & 0x2) &&
1371 ((uint64_t)ImmOperand1 < (uint64_t)ImmOperand2)) ||
1372 ((ImmOperand0 & 0x1) &&
1373 ((uint64_t)ImmOperand1 > (uint64_t)ImmOperand2)) ||
1374 ((ImmOperand0 & 0x4) && (ImmOperand1 == ImmOperand2))) {
1375 BuildMI(BB&: MBB, I: &MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PPC::TRAP));
1376 TrapOpt = true;
1377 }
1378 // We will delete the MI if it will never trap.
1379 ToErase = &MI;
1380 Simplified = true;
1381 break;
1382 }
1383 }
1384 }
1385
1386 // If the last instruction was marked for elimination,
1387 // remove it now.
1388 if (ToErase) {
1389 recomputeLVForDyingInstr();
1390 ToErase->eraseFromParent();
1391 ToErase = nullptr;
1392 }
1393 // Reset TrapOpt to false at the end of the basic block.
1394 if (EnableTrapOptimization)
1395 TrapOpt = false;
1396 }
1397
1398 // Eliminate all the TOC save instructions which are redundant.
1399 Simplified |= eliminateRedundantTOCSaves(TOCSaves);
1400 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
1401 if (FI->mustSaveTOC())
1402 NumTOCSavesInPrologue++;
1403
1404 // We try to eliminate redundant compare instruction.
1405 Simplified |= eliminateRedundantCompare();
1406
1407 // If we have made any modifications and added any registers to the set of
1408 // registers for which we need to update the kill flags, do so by recomputing
1409 // LiveVariables for those registers.
1410 for (Register Reg : RegsToUpdate) {
1411 if (!MRI->reg_empty(RegNo: Reg))
1412 LV->recomputeForSingleDefVirtReg(Reg);
1413 }
1414 return Simplified;
1415}
1416
1417// helper functions for eliminateRedundantCompare
1418static bool isEqOrNe(MachineInstr *BI) {
1419 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(i: 0).getImm();
1420 unsigned PredCond = PPC::getPredicateCondition(Opcode: Pred);
1421 return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE);
1422}
1423
1424static bool isSupportedCmpOp(unsigned opCode) {
1425 return (opCode == PPC::CMPLD || opCode == PPC::CMPD ||
1426 opCode == PPC::CMPLW || opCode == PPC::CMPW ||
1427 opCode == PPC::CMPLDI || opCode == PPC::CMPDI ||
1428 opCode == PPC::CMPLWI || opCode == PPC::CMPWI);
1429}
1430
1431static bool is64bitCmpOp(unsigned opCode) {
1432 return (opCode == PPC::CMPLD || opCode == PPC::CMPD ||
1433 opCode == PPC::CMPLDI || opCode == PPC::CMPDI);
1434}
1435
1436static bool isSignedCmpOp(unsigned opCode) {
1437 return (opCode == PPC::CMPD || opCode == PPC::CMPW ||
1438 opCode == PPC::CMPDI || opCode == PPC::CMPWI);
1439}
1440
1441static unsigned getSignedCmpOpCode(unsigned opCode) {
1442 if (opCode == PPC::CMPLD) return PPC::CMPD;
1443 if (opCode == PPC::CMPLW) return PPC::CMPW;
1444 if (opCode == PPC::CMPLDI) return PPC::CMPDI;
1445 if (opCode == PPC::CMPLWI) return PPC::CMPWI;
1446 return opCode;
1447}
1448
1449// We can decrement immediate x in (GE x) by changing it to (GT x-1) or
1450// (LT x) to (LE x-1)
1451static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) {
1452 uint64_t Imm = CMPI->getOperand(i: 2).getImm();
1453 bool SignedCmp = isSignedCmpOp(opCode: CMPI->getOpcode());
1454 if ((!SignedCmp && Imm == 0) || (SignedCmp && Imm == 0x8000))
1455 return 0;
1456
1457 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(i: 0).getImm();
1458 unsigned PredCond = PPC::getPredicateCondition(Opcode: Pred);
1459 unsigned PredHint = PPC::getPredicateHint(Opcode: Pred);
1460 if (PredCond == PPC::PRED_GE)
1461 return PPC::getPredicate(Condition: PPC::PRED_GT, Hint: PredHint);
1462 if (PredCond == PPC::PRED_LT)
1463 return PPC::getPredicate(Condition: PPC::PRED_LE, Hint: PredHint);
1464
1465 return 0;
1466}
1467
1468// We can increment immediate x in (GT x) by changing it to (GE x+1) or
1469// (LE x) to (LT x+1)
1470static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) {
1471 uint64_t Imm = CMPI->getOperand(i: 2).getImm();
1472 bool SignedCmp = isSignedCmpOp(opCode: CMPI->getOpcode());
1473 if ((!SignedCmp && Imm == 0xFFFF) || (SignedCmp && Imm == 0x7FFF))
1474 return 0;
1475
1476 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(i: 0).getImm();
1477 unsigned PredCond = PPC::getPredicateCondition(Opcode: Pred);
1478 unsigned PredHint = PPC::getPredicateHint(Opcode: Pred);
1479 if (PredCond == PPC::PRED_GT)
1480 return PPC::getPredicate(Condition: PPC::PRED_GE, Hint: PredHint);
1481 if (PredCond == PPC::PRED_LE)
1482 return PPC::getPredicate(Condition: PPC::PRED_LT, Hint: PredHint);
1483
1484 return 0;
1485}
1486
1487// This takes a Phi node and returns a register value for the specified BB.
1488static unsigned getIncomingRegForBlock(MachineInstr *Phi,
1489 MachineBasicBlock *MBB) {
1490 for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) {
1491 MachineOperand &MO = Phi->getOperand(i: I);
1492 if (MO.getMBB() == MBB)
1493 return Phi->getOperand(i: I-1).getReg();
1494 }
1495 llvm_unreachable("invalid src basic block for this Phi node\n");
1496 return 0;
1497}
1498
1499// This function tracks the source of the register through register copy.
1500// If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2
1501// assuming that the control comes from BB1 into BB2.
1502static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1,
1503 MachineBasicBlock *BB2, MachineRegisterInfo *MRI) {
1504 unsigned SrcReg = Reg;
1505 while (true) {
1506 unsigned NextReg = SrcReg;
1507 MachineInstr *Inst = MRI->getVRegDef(Reg: SrcReg);
1508 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) {
1509 NextReg = getIncomingRegForBlock(Phi: Inst, MBB: BB1);
1510 // We track through PHI only once to avoid infinite loop.
1511 BB1 = nullptr;
1512 }
1513 else if (Inst->isFullCopy())
1514 NextReg = Inst->getOperand(i: 1).getReg();
1515 if (NextReg == SrcReg || !Register::isVirtualRegister(Reg: NextReg))
1516 break;
1517 SrcReg = NextReg;
1518 }
1519 return SrcReg;
1520}
1521
1522static bool eligibleForCompareElimination(MachineBasicBlock &MBB,
1523 MachineBasicBlock *&PredMBB,
1524 MachineBasicBlock *&MBBtoMoveCmp,
1525 MachineRegisterInfo *MRI) {
1526
1527 auto isEligibleBB = [&](MachineBasicBlock &BB) {
1528 auto BII = BB.getFirstInstrTerminator();
1529 // We optimize BBs ending with a conditional branch.
1530 // We check only for BCC here, not BCCLR, because BCCLR
1531 // will be formed only later in the pipeline.
1532 if (BB.succ_size() == 2 &&
1533 BII != BB.instr_end() &&
1534 (*BII).getOpcode() == PPC::BCC &&
1535 (*BII).getOperand(i: 1).isReg()) {
1536 // We optimize only if the condition code is used only by one BCC.
1537 Register CndReg = (*BII).getOperand(i: 1).getReg();
1538 if (!CndReg.isVirtual() || !MRI->hasOneNonDBGUse(RegNo: CndReg))
1539 return false;
1540
1541 MachineInstr *CMPI = MRI->getVRegDef(Reg: CndReg);
1542 // We assume compare and branch are in the same BB for ease of analysis.
1543 if (CMPI->getParent() != &BB)
1544 return false;
1545
1546 // We skip this BB if a physical register is used in comparison.
1547 for (MachineOperand &MO : CMPI->operands())
1548 if (MO.isReg() && !MO.getReg().isVirtual())
1549 return false;
1550
1551 return true;
1552 }
1553 return false;
1554 };
1555
1556 // If this BB has more than one successor, we can create a new BB and
1557 // move the compare instruction in the new BB.
1558 // So far, we do not move compare instruction to a BB having multiple
1559 // successors to avoid potentially increasing code size.
1560 auto isEligibleForMoveCmp = [](MachineBasicBlock &BB) {
1561 return BB.succ_size() == 1;
1562 };
1563
1564 if (!isEligibleBB(MBB))
1565 return false;
1566
1567 unsigned NumPredBBs = MBB.pred_size();
1568 if (NumPredBBs == 1) {
1569 MachineBasicBlock *TmpMBB = *MBB.pred_begin();
1570 if (isEligibleBB(*TmpMBB)) {
1571 PredMBB = TmpMBB;
1572 MBBtoMoveCmp = nullptr;
1573 return true;
1574 }
1575 }
1576 else if (NumPredBBs == 2) {
1577 // We check for partially redundant case.
1578 // So far, we support cases with only two predecessors
1579 // to avoid increasing the number of instructions.
1580 MachineBasicBlock::pred_iterator PI = MBB.pred_begin();
1581 MachineBasicBlock *Pred1MBB = *PI;
1582 MachineBasicBlock *Pred2MBB = *(PI+1);
1583
1584 if (isEligibleBB(*Pred1MBB) && isEligibleForMoveCmp(*Pred2MBB)) {
1585 // We assume Pred1MBB is the BB containing the compare to be merged and
1586 // Pred2MBB is the BB to which we will append a compare instruction.
1587 // Proceed as is if Pred1MBB is different from MBB.
1588 }
1589 else if (isEligibleBB(*Pred2MBB) && isEligibleForMoveCmp(*Pred1MBB)) {
1590 // We need to swap Pred1MBB and Pred2MBB to canonicalize.
1591 std::swap(a&: Pred1MBB, b&: Pred2MBB);
1592 }
1593 else return false;
1594
1595 if (Pred1MBB == &MBB)
1596 return false;
1597
1598 // Here, Pred2MBB is the BB to which we need to append a compare inst.
1599 // We cannot move the compare instruction if operands are not available
1600 // in Pred2MBB (i.e. defined in MBB by an instruction other than PHI).
1601 MachineInstr *BI = &*MBB.getFirstInstrTerminator();
1602 MachineInstr *CMPI = MRI->getVRegDef(Reg: BI->getOperand(i: 1).getReg());
1603 for (int I = 1; I <= 2; I++)
1604 if (CMPI->getOperand(i: I).isReg()) {
1605 MachineInstr *Inst = MRI->getVRegDef(Reg: CMPI->getOperand(i: I).getReg());
1606 if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI)
1607 return false;
1608 }
1609
1610 PredMBB = Pred1MBB;
1611 MBBtoMoveCmp = Pred2MBB;
1612 return true;
1613 }
1614
1615 return false;
1616}
1617
1618// This function will iterate over the input map containing a pair of TOC save
1619// instruction and a flag. The flag will be set to false if the TOC save is
1620// proven redundant. This function will erase from the basic block all the TOC
1621// saves marked as redundant.
1622bool PPCMIPeephole::eliminateRedundantTOCSaves(
1623 std::map<MachineInstr *, bool> &TOCSaves) {
1624 bool Simplified = false;
1625 int NumKept = 0;
1626 for (auto TOCSave : TOCSaves) {
1627 if (!TOCSave.second) {
1628 TOCSave.first->eraseFromParent();
1629 RemoveTOCSave++;
1630 Simplified = true;
1631 } else {
1632 NumKept++;
1633 }
1634 }
1635
1636 if (NumKept > 1)
1637 MultiTOCSaves++;
1638
1639 return Simplified;
1640}
1641
1642// If multiple conditional branches are executed based on the (essentially)
1643// same comparison, we merge compare instructions into one and make multiple
1644// conditional branches on this comparison.
1645// For example,
1646// if (a == 0) { ... }
1647// else if (a < 0) { ... }
1648// can be executed by one compare and two conditional branches instead of
1649// two pairs of a compare and a conditional branch.
1650//
1651// This method merges two compare instructions in two MBBs and modifies the
1652// compare and conditional branch instructions if needed.
1653// For the above example, the input for this pass looks like:
1654// cmplwi r3, 0
1655// beq 0, .LBB0_3
1656// cmpwi r3, -1
1657// bgt 0, .LBB0_4
1658// So, before merging two compares, we need to modify these instructions as
1659// cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq
1660// beq 0, .LBB0_3
1661// cmpwi r3, 0 ; greather than -1 means greater or equal to 0
1662// bge 0, .LBB0_4
1663
1664bool PPCMIPeephole::eliminateRedundantCompare() {
1665 bool Simplified = false;
1666
1667 for (MachineBasicBlock &MBB2 : *MF) {
1668 MachineBasicBlock *MBB1 = nullptr, *MBBtoMoveCmp = nullptr;
1669
1670 // For fully redundant case, we select two basic blocks MBB1 and MBB2
1671 // as an optimization target if
1672 // - both MBBs end with a conditional branch,
1673 // - MBB1 is the only predecessor of MBB2, and
1674 // - compare does not take a physical register as a operand in both MBBs.
1675 // In this case, eligibleForCompareElimination sets MBBtoMoveCmp nullptr.
1676 //
1677 // As partially redundant case, we additionally handle if MBB2 has one
1678 // additional predecessor, which has only one successor (MBB2).
1679 // In this case, we move the compare instruction originally in MBB2 into
1680 // MBBtoMoveCmp. This partially redundant case is typically appear by
1681 // compiling a while loop; here, MBBtoMoveCmp is the loop preheader.
1682 //
1683 // Overview of CFG of related basic blocks
1684 // Fully redundant case Partially redundant case
1685 // -------- ---------------- --------
1686 // | MBB1 | (w/ 2 succ) | MBBtoMoveCmp | | MBB1 | (w/ 2 succ)
1687 // -------- ---------------- --------
1688 // | \ (w/ 1 succ) \ | \
1689 // | \ \ | \
1690 // | \ |
1691 // -------- --------
1692 // | MBB2 | (w/ 1 pred | MBB2 | (w/ 2 pred
1693 // -------- and 2 succ) -------- and 2 succ)
1694 // | \ | \
1695 // | \ | \
1696 //
1697 if (!eligibleForCompareElimination(MBB&: MBB2, PredMBB&: MBB1, MBBtoMoveCmp, MRI))
1698 continue;
1699
1700 MachineInstr *BI1 = &*MBB1->getFirstInstrTerminator();
1701 MachineInstr *CMPI1 = MRI->getVRegDef(Reg: BI1->getOperand(i: 1).getReg());
1702
1703 MachineInstr *BI2 = &*MBB2.getFirstInstrTerminator();
1704 MachineInstr *CMPI2 = MRI->getVRegDef(Reg: BI2->getOperand(i: 1).getReg());
1705 bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr);
1706
1707 // We cannot optimize an unsupported compare opcode or
1708 // a mix of 32-bit and 64-bit comparisons
1709 if (!isSupportedCmpOp(opCode: CMPI1->getOpcode()) ||
1710 !isSupportedCmpOp(opCode: CMPI2->getOpcode()) ||
1711 is64bitCmpOp(opCode: CMPI1->getOpcode()) != is64bitCmpOp(opCode: CMPI2->getOpcode()))
1712 continue;
1713
1714 unsigned NewOpCode = 0;
1715 unsigned NewPredicate1 = 0, NewPredicate2 = 0;
1716 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0;
1717 bool SwapOperands = false;
1718
1719 if (CMPI1->getOpcode() != CMPI2->getOpcode()) {
1720 // Typically, unsigned comparison is used for equality check, but
1721 // we replace it with a signed comparison if the comparison
1722 // to be merged is a signed comparison.
1723 // In other cases of opcode mismatch, we cannot optimize this.
1724
1725 // We cannot change opcode when comparing against an immediate
1726 // if the most significant bit of the immediate is one
1727 // due to the difference in sign extension.
1728 auto CmpAgainstImmWithSignBit = [](MachineInstr *I) {
1729 if (!I->getOperand(i: 2).isImm())
1730 return false;
1731 int16_t Imm = (int16_t)I->getOperand(i: 2).getImm();
1732 return Imm < 0;
1733 };
1734
1735 if (isEqOrNe(BI: BI2) && !CmpAgainstImmWithSignBit(CMPI2) &&
1736 CMPI1->getOpcode() == getSignedCmpOpCode(opCode: CMPI2->getOpcode()))
1737 NewOpCode = CMPI1->getOpcode();
1738 else if (isEqOrNe(BI: BI1) && !CmpAgainstImmWithSignBit(CMPI1) &&
1739 getSignedCmpOpCode(opCode: CMPI1->getOpcode()) == CMPI2->getOpcode())
1740 NewOpCode = CMPI2->getOpcode();
1741 else continue;
1742 }
1743
1744 if (CMPI1->getOperand(i: 2).isReg() && CMPI2->getOperand(i: 2).isReg()) {
1745 // In case of comparisons between two registers, these two registers
1746 // must be same to merge two comparisons.
1747 unsigned Cmp1Operand1 = getSrcVReg(Reg: CMPI1->getOperand(i: 1).getReg(),
1748 BB1: nullptr, BB2: nullptr, MRI);
1749 unsigned Cmp1Operand2 = getSrcVReg(Reg: CMPI1->getOperand(i: 2).getReg(),
1750 BB1: nullptr, BB2: nullptr, MRI);
1751 unsigned Cmp2Operand1 = getSrcVReg(Reg: CMPI2->getOperand(i: 1).getReg(),
1752 BB1: MBB1, BB2: &MBB2, MRI);
1753 unsigned Cmp2Operand2 = getSrcVReg(Reg: CMPI2->getOperand(i: 2).getReg(),
1754 BB1: MBB1, BB2: &MBB2, MRI);
1755
1756 if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) {
1757 // Same pair of registers in the same order; ready to merge as is.
1758 }
1759 else if (Cmp1Operand1 == Cmp2Operand2 && Cmp1Operand2 == Cmp2Operand1) {
1760 // Same pair of registers in different order.
1761 // We reverse the predicate to merge compare instructions.
1762 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(i: 0).getImm();
1763 NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Opcode: Pred);
1764 // In case of partial redundancy, we need to swap operands
1765 // in another compare instruction.
1766 SwapOperands = true;
1767 }
1768 else continue;
1769 }
1770 else if (CMPI1->getOperand(i: 2).isImm() && CMPI2->getOperand(i: 2).isImm()) {
1771 // In case of comparisons between a register and an immediate,
1772 // the operand register must be same for two compare instructions.
1773 unsigned Cmp1Operand1 = getSrcVReg(Reg: CMPI1->getOperand(i: 1).getReg(),
1774 BB1: nullptr, BB2: nullptr, MRI);
1775 unsigned Cmp2Operand1 = getSrcVReg(Reg: CMPI2->getOperand(i: 1).getReg(),
1776 BB1: MBB1, BB2: &MBB2, MRI);
1777 if (Cmp1Operand1 != Cmp2Operand1)
1778 continue;
1779
1780 NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(i: 2).getImm();
1781 NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(i: 2).getImm();
1782
1783 // If immediate are not same, we try to adjust by changing predicate;
1784 // e.g. GT imm means GE (imm+1).
1785 if (Imm1 != Imm2 && (!isEqOrNe(BI: BI2) || !isEqOrNe(BI: BI1))) {
1786 int Diff = Imm1 - Imm2;
1787 if (Diff < -2 || Diff > 2)
1788 continue;
1789
1790 unsigned PredToInc1 = getPredicateToIncImm(BI: BI1, CMPI: CMPI1);
1791 unsigned PredToDec1 = getPredicateToDecImm(BI: BI1, CMPI: CMPI1);
1792 unsigned PredToInc2 = getPredicateToIncImm(BI: BI2, CMPI: CMPI2);
1793 unsigned PredToDec2 = getPredicateToDecImm(BI: BI2, CMPI: CMPI2);
1794 if (Diff == 2) {
1795 if (PredToInc2 && PredToDec1) {
1796 NewPredicate2 = PredToInc2;
1797 NewPredicate1 = PredToDec1;
1798 NewImm2++;
1799 NewImm1--;
1800 }
1801 }
1802 else if (Diff == 1) {
1803 if (PredToInc2) {
1804 NewImm2++;
1805 NewPredicate2 = PredToInc2;
1806 }
1807 else if (PredToDec1) {
1808 NewImm1--;
1809 NewPredicate1 = PredToDec1;
1810 }
1811 }
1812 else if (Diff == -1) {
1813 if (PredToDec2) {
1814 NewImm2--;
1815 NewPredicate2 = PredToDec2;
1816 }
1817 else if (PredToInc1) {
1818 NewImm1++;
1819 NewPredicate1 = PredToInc1;
1820 }
1821 }
1822 else if (Diff == -2) {
1823 if (PredToDec2 && PredToInc1) {
1824 NewPredicate2 = PredToDec2;
1825 NewPredicate1 = PredToInc1;
1826 NewImm2--;
1827 NewImm1++;
1828 }
1829 }
1830 }
1831
1832 // We cannot merge two compares if the immediates are not same.
1833 if (NewImm2 != NewImm1)
1834 continue;
1835 }
1836
1837 LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n");
1838 LLVM_DEBUG(CMPI1->dump());
1839 LLVM_DEBUG(BI1->dump());
1840 LLVM_DEBUG(CMPI2->dump());
1841 LLVM_DEBUG(BI2->dump());
1842 for (const MachineOperand &MO : CMPI1->operands())
1843 if (MO.isReg())
1844 addRegToUpdate(MO.getReg());
1845 for (const MachineOperand &MO : CMPI2->operands())
1846 if (MO.isReg())
1847 addRegToUpdate(MO.getReg());
1848
1849 // We adjust opcode, predicates and immediate as we determined above.
1850 if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) {
1851 CMPI1->setDesc(TII->get(Opcode: NewOpCode));
1852 }
1853 if (NewPredicate1) {
1854 BI1->getOperand(i: 0).setImm(NewPredicate1);
1855 }
1856 if (NewPredicate2) {
1857 BI2->getOperand(i: 0).setImm(NewPredicate2);
1858 }
1859 if (NewImm1 != Imm1) {
1860 CMPI1->getOperand(i: 2).setImm(NewImm1);
1861 }
1862
1863 if (IsPartiallyRedundant) {
1864 // We touch up the compare instruction in MBB2 and move it to
1865 // a previous BB to handle partially redundant case.
1866 if (SwapOperands) {
1867 Register Op1 = CMPI2->getOperand(i: 1).getReg();
1868 Register Op2 = CMPI2->getOperand(i: 2).getReg();
1869 CMPI2->getOperand(i: 1).setReg(Op2);
1870 CMPI2->getOperand(i: 2).setReg(Op1);
1871 }
1872 if (NewImm2 != Imm2)
1873 CMPI2->getOperand(i: 2).setImm(NewImm2);
1874
1875 for (int I = 1; I <= 2; I++) {
1876 if (CMPI2->getOperand(i: I).isReg()) {
1877 MachineInstr *Inst = MRI->getVRegDef(Reg: CMPI2->getOperand(i: I).getReg());
1878 if (Inst->getParent() != &MBB2)
1879 continue;
1880
1881 assert(Inst->getOpcode() == PPC::PHI &&
1882 "We cannot support if an operand comes from this BB.");
1883 unsigned SrcReg = getIncomingRegForBlock(Phi: Inst, MBB: MBBtoMoveCmp);
1884 CMPI2->getOperand(i: I).setReg(SrcReg);
1885 addRegToUpdate(SrcReg);
1886 }
1887 }
1888 auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator());
1889 MBBtoMoveCmp->splice(Where: I, Other: &MBB2, From: MachineBasicBlock::iterator(CMPI2));
1890
1891 DebugLoc DL = CMPI2->getDebugLoc();
1892 Register NewVReg = MRI->createVirtualRegister(RegClass: &PPC::CRRCRegClass);
1893 BuildMI(BB&: MBB2, I: MBB2.begin(), MIMD: DL,
1894 MCID: TII->get(Opcode: PPC::PHI), DestReg: NewVReg)
1895 .addReg(RegNo: BI1->getOperand(i: 1).getReg()).addMBB(MBB: MBB1)
1896 .addReg(RegNo: BI2->getOperand(i: 1).getReg()).addMBB(MBB: MBBtoMoveCmp);
1897 BI2->getOperand(i: 1).setReg(NewVReg);
1898 addRegToUpdate(NewVReg);
1899 }
1900 else {
1901 // We finally eliminate compare instruction in MBB2.
1902 // We do not need to treat CMPI2 specially here in terms of re-computing
1903 // live variables even though it is being deleted because:
1904 // - It defines a register that has a single use (already checked in
1905 // eligibleForCompareElimination())
1906 // - The only user (BI2) is no longer using it so the register is dead (no
1907 // def, no uses)
1908 // - We do not attempt to recompute live variables for dead registers
1909 BI2->getOperand(i: 1).setReg(BI1->getOperand(i: 1).getReg());
1910 CMPI2->eraseFromParent();
1911 }
1912
1913 LLVM_DEBUG(dbgs() << "into a compare and two branches:\n");
1914 LLVM_DEBUG(CMPI1->dump());
1915 LLVM_DEBUG(BI1->dump());
1916 LLVM_DEBUG(BI2->dump());
1917 if (IsPartiallyRedundant) {
1918 LLVM_DEBUG(dbgs() << "The following compare is moved into "
1919 << printMBBReference(*MBBtoMoveCmp)
1920 << " to handle partial redundancy.\n");
1921 LLVM_DEBUG(CMPI2->dump());
1922 }
1923 Simplified = true;
1924 }
1925
1926 return Simplified;
1927}
1928
1929// We miss the opportunity to emit an RLDIC when lowering jump tables
1930// since ISEL sees only a single basic block. When selecting, the clear
1931// and shift left will be in different blocks.
1932bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI,
1933 MachineInstr *&ToErase) {
1934 if (MI.getOpcode() != PPC::RLDICR)
1935 return false;
1936
1937 Register SrcReg = MI.getOperand(i: 1).getReg();
1938 if (!SrcReg.isVirtual())
1939 return false;
1940
1941 MachineInstr *SrcMI = MRI->getVRegDef(Reg: SrcReg);
1942 if (SrcMI->getOpcode() != PPC::RLDICL)
1943 return false;
1944
1945 MachineOperand MOpSHSrc = SrcMI->getOperand(i: 2);
1946 MachineOperand MOpMBSrc = SrcMI->getOperand(i: 3);
1947 MachineOperand MOpSHMI = MI.getOperand(i: 2);
1948 MachineOperand MOpMEMI = MI.getOperand(i: 3);
1949 if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() &&
1950 MOpMEMI.isImm()))
1951 return false;
1952
1953 uint64_t SHSrc = MOpSHSrc.getImm();
1954 uint64_t MBSrc = MOpMBSrc.getImm();
1955 uint64_t SHMI = MOpSHMI.getImm();
1956 uint64_t MEMI = MOpMEMI.getImm();
1957 uint64_t NewSH = SHSrc + SHMI;
1958 uint64_t NewMB = MBSrc - SHMI;
1959 if (NewMB > 63 || NewSH > 63)
1960 return false;
1961
1962 // The bits cleared with RLDICL are [0, MBSrc).
1963 // The bits cleared with RLDICR are (MEMI, 63].
1964 // After the sequence, the bits cleared are:
1965 // [0, MBSrc-SHMI) and (MEMI, 63).
1966 //
1967 // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63].
1968 if ((63 - NewSH) != MEMI)
1969 return false;
1970
1971 LLVM_DEBUG(dbgs() << "Converting pair: ");
1972 LLVM_DEBUG(SrcMI->dump());
1973 LLVM_DEBUG(MI.dump());
1974
1975 MI.setDesc(TII->get(Opcode: PPC::RLDIC));
1976 MI.getOperand(i: 1).setReg(SrcMI->getOperand(i: 1).getReg());
1977 MI.getOperand(i: 2).setImm(NewSH);
1978 MI.getOperand(i: 3).setImm(NewMB);
1979 addRegToUpdate(MI.getOperand(1).getReg());
1980 addRegToUpdate(SrcMI->getOperand(0).getReg());
1981
1982 LLVM_DEBUG(dbgs() << "To: ");
1983 LLVM_DEBUG(MI.dump());
1984 NumRotatesCollapsed++;
1985 // If SrcReg has no non-debug use it's safe to delete its def SrcMI.
1986 if (MRI->use_nodbg_empty(RegNo: SrcReg)) {
1987 assert(!SrcMI->hasImplicitDef() &&
1988 "Not expecting an implicit def with this instr.");
1989 ToErase = SrcMI;
1990 }
1991 return true;
1992}
1993
1994// For case in LLVM IR
1995// entry:
1996// %iconv = sext i32 %index to i64
1997// br i1 undef label %true, label %false
1998// true:
1999// %ptr = getelementptr inbounds i32, i32* null, i64 %iconv
2000// ...
2001// PPCISelLowering::combineSHL fails to combine, because sext and shl are in
2002// different BBs when conducting instruction selection. We can do a peephole
2003// optimization to combine these two instructions into extswsli after
2004// instruction selection.
2005bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI,
2006 MachineInstr *&ToErase) {
2007 if (MI.getOpcode() != PPC::RLDICR)
2008 return false;
2009
2010 if (!MF->getSubtarget<PPCSubtarget>().isISA3_0())
2011 return false;
2012
2013 assert(MI.getNumOperands() == 4 && "RLDICR should have 4 operands");
2014
2015 MachineOperand MOpSHMI = MI.getOperand(i: 2);
2016 MachineOperand MOpMEMI = MI.getOperand(i: 3);
2017 if (!(MOpSHMI.isImm() && MOpMEMI.isImm()))
2018 return false;
2019
2020 uint64_t SHMI = MOpSHMI.getImm();
2021 uint64_t MEMI = MOpMEMI.getImm();
2022 if (SHMI + MEMI != 63)
2023 return false;
2024
2025 Register SrcReg = MI.getOperand(i: 1).getReg();
2026 if (!SrcReg.isVirtual())
2027 return false;
2028
2029 MachineInstr *SrcMI = MRI->getVRegDef(Reg: SrcReg);
2030 if (SrcMI->getOpcode() != PPC::EXTSW &&
2031 SrcMI->getOpcode() != PPC::EXTSW_32_64)
2032 return false;
2033
2034 // If the register defined by extsw has more than one use, combination is not
2035 // needed.
2036 if (!MRI->hasOneNonDBGUse(RegNo: SrcReg))
2037 return false;
2038
2039 assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands");
2040 assert(SrcMI->getOperand(1).isReg() &&
2041 "EXTSW's second operand should be a register");
2042 if (!SrcMI->getOperand(i: 1).getReg().isVirtual())
2043 return false;
2044
2045 LLVM_DEBUG(dbgs() << "Combining pair: ");
2046 LLVM_DEBUG(SrcMI->dump());
2047 LLVM_DEBUG(MI.dump());
2048
2049 MachineInstr *NewInstr =
2050 BuildMI(BB&: *MI.getParent(), I: &MI, MIMD: MI.getDebugLoc(),
2051 MCID: SrcMI->getOpcode() == PPC::EXTSW ? TII->get(Opcode: PPC::EXTSWSLI)
2052 : TII->get(Opcode: PPC::EXTSWSLI_32_64),
2053 DestReg: MI.getOperand(i: 0).getReg())
2054 .add(MO: SrcMI->getOperand(i: 1))
2055 .add(MO: MOpSHMI);
2056 (void)NewInstr;
2057
2058 LLVM_DEBUG(dbgs() << "TO: ");
2059 LLVM_DEBUG(NewInstr->dump());
2060 ++NumEXTSWAndSLDICombined;
2061 ToErase = &MI;
2062 // SrcMI, which is extsw, is of no use now, but we don't erase it here so we
2063 // can recompute its kill flags. We run DCE immediately after this pass
2064 // to clean up dead instructions such as this.
2065 addRegToUpdate(NewInstr->getOperand(1).getReg());
2066 addRegToUpdate(SrcMI->getOperand(0).getReg());
2067 return true;
2068}
2069
2070} // end default namespace
2071
2072INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
2073 "PowerPC MI Peephole Optimization", false, false)
2074INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfoWrapperPass)
2075INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
2076INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTreeWrapperPass)
2077INITIALIZE_PASS_DEPENDENCY(LiveVariablesWrapperPass)
2078INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE,
2079 "PowerPC MI Peephole Optimization", false, false)
2080
2081char PPCMIPeephole::ID = 0;
2082FunctionPass*
2083llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }
2084