1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the PowerPC target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCTargetMachine.h"
14#include "MCTargetDesc/PPCMCTargetDesc.h"
15#include "PPC.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCMachineScheduler.h"
18#include "PPCMacroFusion.h"
19#include "PPCSubtarget.h"
20#include "PPCTargetObjectFile.h"
21#include "PPCTargetTransformInfo.h"
22#include "TargetInfo/PowerPCTargetInfo.h"
23#include "llvm/ADT/StringRef.h"
24#include "llvm/Analysis/TargetTransformInfo.h"
25#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
26#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
27#include "llvm/CodeGen/GlobalISel/Legalizer.h"
28#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
29#include "llvm/CodeGen/MachineScheduler.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/CodeGen/TargetPassConfig.h"
32#include "llvm/IR/Attributes.h"
33#include "llvm/IR/DataLayout.h"
34#include "llvm/IR/Function.h"
35#include "llvm/InitializePasses.h"
36#include "llvm/MC/TargetRegistry.h"
37#include "llvm/Pass.h"
38#include "llvm/Support/CodeGen.h"
39#include "llvm/Support/CommandLine.h"
40#include "llvm/Support/Compiler.h"
41#include "llvm/Target/TargetLoweringObjectFile.h"
42#include "llvm/Target/TargetOptions.h"
43#include "llvm/TargetParser/Triple.h"
44#include "llvm/Transforms/Scalar.h"
45#include <cassert>
46#include <memory>
47#include <optional>
48#include <string>
49
50using namespace llvm;
51
52
53static cl::opt<bool>
54 EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
55 cl::desc("enable coalescing of duplicate branches for PPC"));
56static cl::
57opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
58 cl::desc("Disable CTR loops for PPC"));
59
60static cl::
61opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
62 cl::desc("Disable PPC loop instr form prep"));
63
64static cl::opt<bool>
65VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
66 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
67
68static cl::
69opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
70 cl::desc("Disable VSX Swap Removal for PPC"));
71
72static cl::
73opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
74 cl::desc("Disable machine peepholes for PPC"));
75
76static cl::opt<bool>
77EnableGEPOpt("ppc-gep-opt", cl::Hidden,
78 cl::desc("Enable optimizations on complex GEPs"),
79 cl::init(Val: true));
80
81static cl::opt<bool>
82EnablePrefetch("enable-ppc-prefetching",
83 cl::desc("enable software prefetching on PPC"),
84 cl::init(Val: false), cl::Hidden);
85
86static cl::opt<bool>
87EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
88 cl::desc("Add extra TOC register dependencies"),
89 cl::init(Val: true), cl::Hidden);
90
91static cl::opt<bool>
92EnableMachineCombinerPass("ppc-machine-combiner",
93 cl::desc("Enable the machine combiner pass"),
94 cl::init(Val: true), cl::Hidden);
95
96static cl::opt<bool>
97 ReduceCRLogical("ppc-reduce-cr-logicals",
98 cl::desc("Expand eligible cr-logical binary ops to branches"),
99 cl::init(Val: true), cl::Hidden);
100
101cl::opt<bool> EnablePPCGenScalarMASSEntries(
102 "enable-ppc-gen-scalar-mass", cl::init(Val: false),
103 cl::desc("Enable lowering math functions to their corresponding MASS "
104 "(scalar) entries"),
105 cl::Hidden);
106
107static cl::opt<bool>
108 EnableGlobalMerge("ppc-global-merge", cl::Hidden, cl::init(Val: false),
109 cl::desc("Enable the global merge pass"));
110
111static cl::opt<unsigned>
112 GlobalMergeMaxOffset("ppc-global-merge-max-offset", cl::Hidden,
113 cl::init(Val: 0x7fff),
114 cl::desc("Maximum global merge offset"));
115
116extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
117LLVMInitializePowerPCTarget() {
118 // Register the targets
119 RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
120 RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget());
121 RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target());
122 RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget());
123
124 PassRegistry &PR = *PassRegistry::getPassRegistry();
125#ifndef NDEBUG
126 initializePPCCTRLoopsVerifyPass(PR);
127#endif
128 initializePPCLoopInstrFormPrepPass(PR);
129 initializePPCTOCRegDepsPass(PR);
130 initializePPCEarlyReturnPass(PR);
131 initializePPCVSXWACCCopyPass(PR);
132 initializePPCVSXFMAMutatePass(PR);
133 initializePPCVSXSwapRemovalPass(PR);
134 initializePPCReduceCRLogicalsPass(PR);
135 initializePPCBSelPass(PR);
136 initializePPCBranchCoalescingPass(PR);
137 initializePPCBoolRetToIntPass(PR);
138 initializePPCPreEmitPeepholePass(PR);
139 initializePPCTLSDynamicCallPass(PR);
140 initializePPCMIPeepholePass(PR);
141 initializePPCLowerMASSVEntriesPass(PR);
142 initializePPCGenScalarMASSEntriesPass(PR);
143 initializePPCExpandAtomicPseudoPass(PR);
144 initializeGlobalISel(PR);
145 initializePPCCTRLoopsPass(PR);
146 initializePPCDAGToDAGISelLegacyPass(PR);
147 initializePPCPrepareIFuncsOnAIXPass(PR);
148 initializePPCLinuxAsmPrinterPass(PR);
149 initializePPCAIXAsmPrinterPass(PR);
150}
151
152static std::string computeFSAdditions(StringRef FS, CodeGenOptLevel OL,
153 const Triple &TT) {
154 std::string FullFS = std::string(FS);
155
156 // Make sure 64-bit features are available when CPUname is generic
157 if (TT.isPPC64()) {
158 if (!FullFS.empty())
159 FullFS = "+64bit," + FullFS;
160 else
161 FullFS = "+64bit";
162 }
163
164 if (OL >= CodeGenOptLevel::Default) {
165 if (!FullFS.empty())
166 FullFS = "+crbits," + FullFS;
167 else
168 FullFS = "+crbits";
169 }
170
171 if (OL != CodeGenOptLevel::None) {
172 if (!FullFS.empty())
173 FullFS = "+invariant-function-descriptors," + FullFS;
174 else
175 FullFS = "+invariant-function-descriptors";
176 }
177
178 if (TT.isOSAIX()) {
179 if (!FullFS.empty())
180 FullFS = "+aix," + FullFS;
181 else
182 FullFS = "+aix";
183 }
184
185 return FullFS;
186}
187
188static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
189 if (TT.isOSAIX())
190 return std::make_unique<TargetLoweringObjectFileXCOFF>();
191
192 return std::make_unique<PPC64LinuxTargetObjectFile>();
193}
194
195// An explicit ABI name takes precedence; otherwise use the triple default.
196PPCABI PPCTargetMachine::computeABI(const Triple &TT, StringRef ABIName) {
197 if (ABIName.starts_with(Prefix: "elfv1"))
198 return PPC_ABI_ELFv1;
199 if (ABIName.starts_with(Prefix: "elfv2"))
200 return PPC_ABI_ELFv2;
201
202 if (TT.isOSAIX())
203 return ABIName == "vec-extabi" ? PPC_ABI_AIX_EXTABI : PPC_ABI_UNKNOWN;
204
205 switch (TT.getArch()) {
206 case Triple::ppc64le:
207 return PPC_ABI_ELFv2;
208 case Triple::ppc64:
209 return TT.isPPC64ELFv2ABI() ? PPC_ABI_ELFv2 : PPC_ABI_ELFv1;
210 default:
211 return PPC_ABI_UNKNOWN;
212 }
213}
214
215static Reloc::Model getEffectiveRelocModel(const Triple &TT,
216 std::optional<Reloc::Model> RM) {
217 if (TT.isOSAIX() && RM && *RM != Reloc::PIC_)
218 report_fatal_error(reason: "invalid relocation model, AIX only supports PIC",
219 gen_crash_diag: false);
220
221 if (RM)
222 return *RM;
223
224 // Big Endian PPC and AIX default to PIC.
225 if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
226 return Reloc::PIC_;
227
228 // Rest are static by default.
229 return Reloc::Static;
230}
231
232static CodeModel::Model
233getEffectivePPCCodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
234 bool JIT) {
235 if (CM) {
236 if (*CM == CodeModel::Tiny)
237 report_fatal_error(reason: "Target does not support the tiny CodeModel", gen_crash_diag: false);
238 if (*CM == CodeModel::Kernel)
239 report_fatal_error(reason: "Target does not support the kernel CodeModel", gen_crash_diag: false);
240 return *CM;
241 }
242
243 if (JIT)
244 return CodeModel::Small;
245 if (TT.isOSAIX()) {
246 // Use large code model for 64-bit AIX by default.
247 if (TT.isArch64Bit())
248 return CodeModel::Large;
249 return CodeModel::Small;
250 }
251
252 assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
253
254 if (TT.isArch32Bit())
255 return CodeModel::Small;
256
257 assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
258 return CodeModel::Medium;
259}
260
261
262static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
263 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
264 ScheduleDAGMILive *DAG = ST.usePPCPreRASchedStrategy()
265 ? createSchedLive<PPCPreRASchedStrategy>(C)
266 : createSchedLive<GenericScheduler>(C);
267 // add DAG Mutations here.
268 if (ST.hasStoreFusion())
269 DAG->addMutation(Mutation: createStoreClusterDAGMutation(TII: DAG->TII));
270 if (ST.hasFusion())
271 DAG->addMutation(Mutation: createPowerPCMacroFusionDAGMutation());
272
273 return DAG;
274}
275
276static ScheduleDAGInstrs *
277createPPCPostMachineScheduler(MachineSchedContext *C) {
278 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
279 ScheduleDAGMI *DAG = ST.usePPCPostRASchedStrategy()
280 ? createSchedPostRA<PPCPostRASchedStrategy>(C)
281 : createSchedPostRA<PostGenericScheduler>(C);
282 // add DAG Mutations here.
283 if (ST.hasStoreFusion())
284 DAG->addMutation(Mutation: createStoreClusterDAGMutation(TII: DAG->TII));
285 if (ST.hasFusion())
286 DAG->addMutation(Mutation: createPowerPCMacroFusionDAGMutation());
287 return DAG;
288}
289
290// The FeatureString here is a little subtle. We are modifying the feature
291// string with what are (currently) non-function specific overrides as it goes
292// into the CodeGenTargetMachineImpl constructor and then using the stored value
293// in the Subtarget constructor below it.
294PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
295 StringRef CPU, StringRef FS,
296 const TargetOptions &Options,
297 std::optional<Reloc::Model> RM,
298 std::optional<CodeModel::Model> CM,
299 CodeGenOptLevel OL, bool JIT)
300 : CodeGenTargetMachineImpl(T, TT, CPU, computeFSAdditions(FS, OL, TT),
301 Options, getEffectiveRelocModel(TT, RM),
302 getEffectivePPCCodeModel(TT, CM, JIT), OL),
303 TLOF(createTLOF(TT: getTargetTriple())),
304 Endianness(TT.isLittleEndian() ? Endian::LITTLE : Endian::BIG) {
305 initAsmInfo();
306}
307
308PPCTargetMachine::~PPCTargetMachine() = default;
309
310const PPCSubtarget *
311PPCTargetMachine::getSubtargetImpl(const Function &F) const {
312 Attribute CPUAttr = F.getFnAttribute(Kind: "target-cpu");
313 Attribute TuneAttr = F.getFnAttribute(Kind: "tune-cpu");
314 Attribute FSAttr = F.getFnAttribute(Kind: "target-features");
315
316 std::string CPU =
317 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
318 std::string TuneCPU =
319 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
320 std::string FS =
321 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
322
323 // FIXME: This is related to the code below to reset the target options,
324 // we need to know whether or not the soft float flag is set on the
325 // function before we can generate a subtarget. We also need to use
326 // it as a key for the subtarget since that can be the only difference
327 // between two functions.
328 bool SoftFloat = F.getFnAttribute(Kind: "use-soft-float").getValueAsBool();
329 // If the soft float attribute is set on the function turn on the soft float
330 // subtarget feature.
331 if (SoftFloat)
332 FS += FS.empty() ? "-hard-float" : ",-hard-float";
333
334 // Prefer the "target-abi" module flag, falling back to the -target-abi
335 // option.
336 StringRef ABIName = getTargetABIName(M: *F.getParent());
337
338 auto &I = SubtargetMap[CPU + TuneCPU + FS + ABIName.str()];
339 if (!I) {
340 I = std::make_unique<PPCSubtarget>(
341 args: TargetTriple, args&: CPU, args&: TuneCPU,
342 // FIXME: It would be good to have the subtarget additions here
343 // not necessary. Anything that turns them on/off (overrides) ends
344 // up being put at the end of the feature string, but the defaults
345 // shouldn't require adding them. Fixing this means pulling Feature64Bit
346 // out of most of the target cpus in the .td file and making it set only
347 // as part of initialization via the TargetTriple.
348 args: computeFSAdditions(FS, OL: getOptLevel(), TT: getTargetTriple()), args&: ABIName,
349 args: *this);
350 }
351 return I.get();
352}
353
354ScheduleDAGInstrs *
355PPCTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
356 return createPPCMachineScheduler(C);
357}
358
359ScheduleDAGInstrs *
360PPCTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
361 return createPPCPostMachineScheduler(C);
362}
363
364//===----------------------------------------------------------------------===//
365// Pass Pipeline Configuration
366//===----------------------------------------------------------------------===//
367
368namespace {
369
370/// PPC Code Generator Pass Configuration Options.
371class PPCPassConfig : public TargetPassConfig {
372public:
373 PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
374 : TargetPassConfig(TM, PM) {
375 // At any optimization level above -O0 we use the Machine Scheduler and not
376 // the default Post RA List Scheduler.
377 if (TM.getOptLevel() != CodeGenOptLevel::None)
378 substitutePass(StandardID: &PostRASchedulerID, TargetID: &PostMachineSchedulerID);
379 }
380
381 PPCTargetMachine &getPPCTargetMachine() const {
382 return getTM<PPCTargetMachine>();
383 }
384
385 void addIRPasses() override;
386 bool addPreISel() override;
387 bool addILPOpts() override;
388 bool addInstSelector() override;
389 void addMachineSSAOptimization() override;
390 void addPreRegAlloc() override;
391 void addPreSched2() override;
392 void addPreEmitPass() override;
393 void addPreEmitPass2() override;
394 // GlobalISEL
395 bool addIRTranslator() override;
396 bool addLegalizeMachineIR() override;
397 bool addRegBankSelect() override;
398 bool addGlobalInstructionSelect() override;
399};
400
401} // end anonymous namespace
402
403TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
404 return new PPCPassConfig(*this, PM);
405}
406
407void PPCPassConfig::addIRPasses() {
408 if (TM->getOptLevel() != CodeGenOptLevel::None)
409 addPass(P: createPPCBoolRetToIntPass());
410 addPass(P: createAtomicExpandLegacyPass());
411
412 // Lower generic MASSV routines to PowerPC subtarget-specific entries.
413 addPass(P: createPPCLowerMASSVEntriesPass());
414
415 // Generate PowerPC target-specific entries for scalar math functions
416 // that are available in IBM MASS (scalar) library.
417 if (TM->getOptLevel() == CodeGenOptLevel::Aggressive &&
418 EnablePPCGenScalarMASSEntries)
419 addPass(P: createPPCGenScalarMASSEntriesPass());
420
421 // If explicitly requested, add explicit data prefetch intrinsics.
422 if (EnablePrefetch.getNumOccurrences() > 0)
423 addPass(P: createLoopDataPrefetchPass());
424
425 if (TM->getOptLevel() >= CodeGenOptLevel::Default && EnableGEPOpt) {
426 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
427 // and lower a GEP with multiple indices to either arithmetic operations or
428 // multiple GEPs with single index.
429 addPass(P: createSeparateConstOffsetFromGEPPass(LowerGEP: true));
430 // Call EarlyCSE pass to find and remove subexpressions in the lowered
431 // result.
432 addPass(P: createEarlyCSEPass());
433 // Do loop invariant code motion in case part of the lowered result is
434 // invariant.
435 addPass(P: createLICMPass());
436 }
437
438 if (TM->getTargetTriple().isOSAIX())
439 addPass(P: createPPCPrepareIFuncsOnAIXPass());
440
441 TargetPassConfig::addIRPasses();
442}
443
444bool PPCPassConfig::addPreISel() {
445 // The GlobalMerge pass is intended to be on by default on AIX.
446 // Specifying the command line option overrides the AIX default.
447 if ((EnableGlobalMerge.getNumOccurrences() > 0)
448 ? EnableGlobalMerge
449 : getOptLevel() != CodeGenOptLevel::None)
450 addPass(P: createGlobalMergePass(TM, MaximalOffset: GlobalMergeMaxOffset, OnlyOptimizeForSize: false, MergeExternalByDefault: false, MergeConstantByDefault: true,
451 MergeConstAggressiveByDefault: true));
452
453 if (!DisableInstrFormPrep && getOptLevel() != CodeGenOptLevel::None)
454 addPass(P: createPPCLoopInstrFormPrepPass(TM&: getPPCTargetMachine()));
455
456 if (!DisableCTRLoops && getOptLevel() != CodeGenOptLevel::None)
457 addPass(P: createHardwareLoopsLegacyPass());
458
459 return false;
460}
461
462bool PPCPassConfig::addILPOpts() {
463 addPass(PassID: &EarlyIfConverterLegacyID);
464
465 if (EnableMachineCombinerPass)
466 addPass(PassID: &MachineCombinerID);
467
468 return true;
469}
470
471bool PPCPassConfig::addInstSelector() {
472 // Install an instruction selector.
473 addPass(P: createPPCISelDag(TM&: getPPCTargetMachine(), OL: getOptLevel()));
474
475#ifndef NDEBUG
476 if (!DisableCTRLoops && getOptLevel() != CodeGenOptLevel::None)
477 addPass(createPPCCTRLoopsVerify());
478#endif
479
480 addPass(P: createPPCVSXWACCCopyPass());
481 return false;
482}
483
484void PPCPassConfig::addMachineSSAOptimization() {
485 // Run CTR loops pass before any cfg modification pass to prevent the
486 // canonical form of hardware loop from being destroied.
487 if (!DisableCTRLoops && getOptLevel() != CodeGenOptLevel::None)
488 addPass(P: createPPCCTRLoopsPass());
489
490 // PPCBranchCoalescingPass need to be done before machine sinking
491 // since it merges empty blocks.
492 if (EnableBranchCoalescing && getOptLevel() != CodeGenOptLevel::None)
493 addPass(P: createPPCBranchCoalescingPass());
494 TargetPassConfig::addMachineSSAOptimization();
495 // For little endian, remove where possible the vector swap instructions
496 // introduced at code generation to normalize vector element order.
497 if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
498 !DisableVSXSwapRemoval)
499 addPass(P: createPPCVSXSwapRemovalPass());
500 // Reduce the number of cr-logical ops.
501 if (ReduceCRLogical && getOptLevel() != CodeGenOptLevel::None)
502 addPass(P: createPPCReduceCRLogicalsPass());
503 // Target-specific peephole cleanups performed after instruction
504 // selection.
505 if (!DisableMIPeephole) {
506 addPass(P: createPPCMIPeepholePass());
507 addPass(PassID: &DeadMachineInstructionElimID);
508 }
509}
510
511void PPCPassConfig::addPreRegAlloc() {
512 if (getOptLevel() != CodeGenOptLevel::None) {
513 insertPass(TargetPassID: VSXFMAMutateEarly ? &TwoAddressInstructionPassID
514 : &MachineSchedulerID,
515 InsertedPassID: &PPCVSXFMAMutateID);
516 }
517
518 // FIXME: We probably don't need to run these for -fPIE.
519 if (getPPCTargetMachine().isPositionIndependent()) {
520 // FIXME: LiveVariables should not be necessary here!
521 // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
522 // LiveVariables. This (unnecessary) dependency has been removed now,
523 // however a stage-2 clang build fails without LiveVariables computed here.
524 addPass(PassID: &LiveVariablesID);
525 addPass(P: createPPCTLSDynamicCallPass());
526 }
527 if (EnableExtraTOCRegDeps)
528 addPass(P: createPPCTOCRegDepsPass());
529
530 if (getOptLevel() != CodeGenOptLevel::None)
531 addPass(PassID: &MachinePipelinerID);
532}
533
534void PPCPassConfig::addPreSched2() {
535 if (getOptLevel() != CodeGenOptLevel::None)
536 addPass(PassID: &IfConverterID);
537}
538
539void PPCPassConfig::addPreEmitPass() {
540 addPass(P: createPPCPreEmitPeepholePass());
541
542 if (getOptLevel() != CodeGenOptLevel::None)
543 addPass(P: createPPCEarlyReturnPass());
544}
545
546void PPCPassConfig::addPreEmitPass2() {
547 // Schedule the expansion of AMOs at the last possible moment, avoiding the
548 // possibility for other passes to break the requirements for forward
549 // progress in the LL/SC block.
550 addPass(P: createPPCExpandAtomicPseudoPass());
551 // Must run branch selection immediately preceding the asm printer.
552 addPass(P: createPPCBranchSelectionPass());
553}
554
555TargetTransformInfo
556PPCTargetMachine::getTargetTransformInfo(const Function &F) const {
557 return TargetTransformInfo(std::make_unique<PPCTTIImpl>(args: this, args: F));
558}
559
560bool PPCTargetMachine::isLittleEndian() const {
561 assert(Endianness != Endian::NOT_DETECTED &&
562 "Unable to determine endianness");
563 return Endianness == Endian::LITTLE;
564}
565
566MachineFunctionInfo *PPCTargetMachine::createMachineFunctionInfo(
567 BumpPtrAllocator &Allocator, const Function &F,
568 const TargetSubtargetInfo *STI) const {
569 return PPCFunctionInfo::create<PPCFunctionInfo>(Allocator, F, STI);
570}
571
572static MachineSchedRegistry
573PPCPreRASchedRegistry("ppc-prera",
574 "Run PowerPC PreRA specific scheduler",
575 createPPCMachineScheduler);
576
577static MachineSchedRegistry
578PPCPostRASchedRegistry("ppc-postra",
579 "Run PowerPC PostRA specific scheduler",
580 createPPCPostMachineScheduler);
581
582// Global ISEL
583bool PPCPassConfig::addIRTranslator() {
584 addPass(P: new IRTranslatorLegacy());
585 return false;
586}
587
588bool PPCPassConfig::addLegalizeMachineIR() {
589 addPass(P: new LegalizerLegacy());
590 return false;
591}
592
593bool PPCPassConfig::addRegBankSelect() {
594 addPass(P: new RegBankSelectLegacy());
595 return false;
596}
597
598bool PPCPassConfig::addGlobalInstructionSelect() {
599 addPass(P: new InstructionSelectLegacy(getOptLevel()));
600 return false;
601}
602