1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the PowerPC target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCTargetMachine.h"
14#include "MCTargetDesc/PPCMCTargetDesc.h"
15#include "PPC.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCMachineScheduler.h"
18#include "PPCMacroFusion.h"
19#include "PPCSubtarget.h"
20#include "PPCTargetObjectFile.h"
21#include "PPCTargetTransformInfo.h"
22#include "TargetInfo/PowerPCTargetInfo.h"
23#include "llvm/ADT/StringRef.h"
24#include "llvm/Analysis/TargetTransformInfo.h"
25#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
26#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
27#include "llvm/CodeGen/GlobalISel/Legalizer.h"
28#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
29#include "llvm/CodeGen/MachineScheduler.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/CodeGen/TargetPassConfig.h"
32#include "llvm/IR/Attributes.h"
33#include "llvm/IR/DataLayout.h"
34#include "llvm/IR/Function.h"
35#include "llvm/InitializePasses.h"
36#include "llvm/MC/TargetRegistry.h"
37#include "llvm/Pass.h"
38#include "llvm/Support/CodeGen.h"
39#include "llvm/Support/CommandLine.h"
40#include "llvm/Support/Compiler.h"
41#include "llvm/Target/TargetLoweringObjectFile.h"
42#include "llvm/Target/TargetOptions.h"
43#include "llvm/TargetParser/Triple.h"
44#include "llvm/Transforms/Scalar.h"
45#include <cassert>
46#include <memory>
47#include <optional>
48#include <string>
49
50using namespace llvm;
51
52static cl::opt<bool> EnableBranchCoalescing(
53 "ppc-branch-coalesce", cl::Hidden,
54 cl::desc("enable coalescing of duplicate branches for PPC"));
55static cl::opt<bool> EnableCTRLoops("ppc-ctr-loops",
56 cl::desc("Enable CTR loops for PPC"),
57 cl::init(Val: true), cl::Hidden);
58
59static cl::opt<bool>
60 EnableInstrFormPrep("ppc-instr-form-prep",
61 cl::desc("Enable PPC loop instr form prep"),
62 cl::init(Val: true), cl::Hidden);
63
64static cl::opt<bool>
65 VSXFMAMutateEarly("ppc-schedule-vsx-fma-mutation-early", cl::Hidden,
66 cl::desc("Schedule VSX FMA instruction mutation early"));
67
68static cl::opt<bool>
69 EnableVSXSwapRemoval("ppc-vsx-swap-removal",
70 cl::desc("Enable VSX Swap Removal for PPC"),
71 cl::init(Val: true), cl::Hidden);
72
73static cl::opt<bool>
74 EnableMIPeephole("ppc-peephole",
75 cl::desc("Enable machine peepholes for PPC"),
76 cl::init(Val: true), cl::Hidden);
77
78static cl::opt<bool>
79EnableGEPOpt("ppc-gep-opt", cl::Hidden,
80 cl::desc("Enable optimizations on complex GEPs"),
81 cl::init(Val: true));
82
83static cl::opt<bool>
84 EnablePrefetch("ppc-prefetching",
85 cl::desc("enable software prefetching on PPC"),
86 cl::init(Val: false), cl::Hidden);
87
88static cl::opt<bool>
89 EnableExtraTOCRegDeps("ppc-extra-toc-reg-deps",
90 cl::desc("Add extra TOC register dependencies"),
91 cl::init(Val: true), cl::Hidden);
92
93static cl::opt<bool>
94EnableMachineCombinerPass("ppc-machine-combiner",
95 cl::desc("Enable the machine combiner pass"),
96 cl::init(Val: true), cl::Hidden);
97
98static cl::opt<bool>
99 ReduceCRLogical("ppc-reduce-cr-logicals",
100 cl::desc("Expand eligible cr-logical binary ops to branches"),
101 cl::init(Val: true), cl::Hidden);
102
103cl::opt<bool> EnablePPCGenScalarMASSEntries(
104 "ppc-scalar-mass", cl::init(Val: false),
105 cl::desc("Enable lowering math functions to their corresponding MASS "
106 "(scalar) entries"),
107 cl::Hidden);
108
109static cl::opt<bool>
110 EnableGlobalMerge("ppc-global-merge", cl::Hidden, cl::init(Val: false),
111 cl::desc("Enable the global merge pass"));
112
113static cl::opt<unsigned>
114 GlobalMergeMaxOffset("ppc-global-merge-max-offset", cl::Hidden,
115 cl::init(Val: 0x7fff),
116 cl::desc("Maximum global merge offset"));
117
118extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
119LLVMInitializePowerPCTarget() {
120 // Register the targets
121 RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
122 RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget());
123 RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target());
124 RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget());
125
126 PassRegistry &PR = *PassRegistry::getPassRegistry();
127#ifndef NDEBUG
128 initializePPCCTRLoopsVerifyPass(PR);
129#endif
130 initializePPCLoopInstrFormPrepPass(PR);
131 initializePPCTOCRegDepsPass(PR);
132 initializePPCEarlyReturnPass(PR);
133 initializePPCVSXWACCCopyPass(PR);
134 initializePPCVSXFMAMutatePass(PR);
135 initializePPCVSXSwapRemovalPass(PR);
136 initializePPCReduceCRLogicalsPass(PR);
137 initializePPCBSelPass(PR);
138 initializePPCBranchCoalescingPass(PR);
139 initializePPCBoolRetToIntPass(PR);
140 initializePPCPreEmitPeepholePass(PR);
141 initializePPCTLSDynamicCallPass(PR);
142 initializePPCMIPeepholePass(PR);
143 initializePPCLowerMASSVEntriesPass(PR);
144 initializePPCGenScalarMASSEntriesPass(PR);
145 initializePPCExpandAtomicPseudoPass(PR);
146 initializeGlobalISel(PR);
147 initializePPCCTRLoopsPass(PR);
148 initializePPCDAGToDAGISelLegacyPass(PR);
149 initializePPCPrepareIFuncsOnAIXPass(PR);
150 initializePPCLinuxAsmPrinterPass(PR);
151 initializePPCAIXAsmPrinterPass(PR);
152}
153
154static std::string computeFSAdditions(StringRef FS, CodeGenOptLevel OL,
155 const Triple &TT) {
156 std::string FullFS = std::string(FS);
157
158 // Make sure 64-bit features are available when CPUname is generic
159 if (TT.isPPC64()) {
160 if (!FullFS.empty())
161 FullFS = "+64bit," + FullFS;
162 else
163 FullFS = "+64bit";
164 }
165
166 if (OL >= CodeGenOptLevel::Default) {
167 if (!FullFS.empty())
168 FullFS = "+crbits," + FullFS;
169 else
170 FullFS = "+crbits";
171 }
172
173 if (OL != CodeGenOptLevel::None) {
174 if (!FullFS.empty())
175 FullFS = "+invariant-function-descriptors," + FullFS;
176 else
177 FullFS = "+invariant-function-descriptors";
178 }
179
180 if (TT.isOSAIX()) {
181 if (!FullFS.empty())
182 FullFS = "+aix," + FullFS;
183 else
184 FullFS = "+aix";
185 }
186
187 return FullFS;
188}
189
190static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
191 if (TT.isOSAIX())
192 return std::make_unique<TargetLoweringObjectFileXCOFF>();
193
194 return std::make_unique<PPC64LinuxTargetObjectFile>();
195}
196
197// An explicit ABI name takes precedence; otherwise use the triple default.
198PPCABI PPCTargetMachine::computeABI(const Triple &TT, StringRef ABIName) {
199 if (ABIName.starts_with(Prefix: "elfv1"))
200 return PPC_ABI_ELFv1;
201 if (ABIName.starts_with(Prefix: "elfv2"))
202 return PPC_ABI_ELFv2;
203
204 if (TT.isOSAIX())
205 return ABIName == "vec-extabi" ? PPC_ABI_AIX_EXTABI : PPC_ABI_UNKNOWN;
206
207 switch (TT.getArch()) {
208 case Triple::ppc64le:
209 return PPC_ABI_ELFv2;
210 case Triple::ppc64:
211 return TT.isPPC64ELFv2ABI() ? PPC_ABI_ELFv2 : PPC_ABI_ELFv1;
212 default:
213 return PPC_ABI_UNKNOWN;
214 }
215}
216
217static Reloc::Model getEffectiveRelocModel(const Triple &TT,
218 std::optional<Reloc::Model> RM) {
219 if (TT.isOSAIX() && RM && *RM != Reloc::PIC_)
220 report_fatal_error(reason: "invalid relocation model, AIX only supports PIC",
221 gen_crash_diag: false);
222
223 if (RM)
224 return *RM;
225
226 // Big Endian PPC and AIX default to PIC.
227 if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
228 return Reloc::PIC_;
229
230 // Rest are static by default.
231 return Reloc::Static;
232}
233
234static CodeModel::Model
235getEffectivePPCCodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
236 bool JIT) {
237 if (CM) {
238 if (*CM == CodeModel::Tiny)
239 report_fatal_error(reason: "Target does not support the tiny CodeModel", gen_crash_diag: false);
240 if (*CM == CodeModel::Kernel)
241 report_fatal_error(reason: "Target does not support the kernel CodeModel", gen_crash_diag: false);
242 return *CM;
243 }
244
245 if (JIT)
246 return CodeModel::Small;
247 if (TT.isOSAIX()) {
248 // Use large code model for 64-bit AIX by default.
249 if (TT.isArch64Bit())
250 return CodeModel::Large;
251 return CodeModel::Small;
252 }
253
254 assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
255
256 if (TT.isArch32Bit())
257 return CodeModel::Small;
258
259 assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
260 return CodeModel::Medium;
261}
262
263
264static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
265 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
266 ScheduleDAGMILive *DAG = ST.usePPCPreRASchedStrategy()
267 ? createSchedLive<PPCPreRASchedStrategy>(C)
268 : createSchedLive<GenericScheduler>(C);
269 // add DAG Mutations here.
270 if (ST.hasStoreFusion())
271 DAG->addMutation(Mutation: createStoreClusterDAGMutation(TII: DAG->TII));
272 if (ST.hasFusion())
273 DAG->addMutation(Mutation: createPowerPCMacroFusionDAGMutation());
274
275 return DAG;
276}
277
278static ScheduleDAGInstrs *
279createPPCPostMachineScheduler(MachineSchedContext *C) {
280 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
281 ScheduleDAGMI *DAG = ST.usePPCPostRASchedStrategy()
282 ? createSchedPostRA<PPCPostRASchedStrategy>(C)
283 : createSchedPostRA<PostGenericScheduler>(C);
284 // add DAG Mutations here.
285 if (ST.hasStoreFusion())
286 DAG->addMutation(Mutation: createStoreClusterDAGMutation(TII: DAG->TII));
287 if (ST.hasFusion())
288 DAG->addMutation(Mutation: createPowerPCMacroFusionDAGMutation());
289 return DAG;
290}
291
292// The FeatureString here is a little subtle. We are modifying the feature
293// string with what are (currently) non-function specific overrides as it goes
294// into the CodeGenTargetMachineImpl constructor and then using the stored value
295// in the Subtarget constructor below it.
296PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
297 StringRef CPU, StringRef FS,
298 const TargetOptions &Options,
299 std::optional<Reloc::Model> RM,
300 std::optional<CodeModel::Model> CM,
301 CodeGenOptLevel OL, bool JIT)
302 : CodeGenTargetMachineImpl(T, TT, CPU, computeFSAdditions(FS, OL, TT),
303 Options, getEffectiveRelocModel(TT, RM),
304 getEffectivePPCCodeModel(TT, CM, JIT), OL),
305 TLOF(createTLOF(TT: getTargetTriple())),
306 Endianness(TT.isLittleEndian() ? Endian::LITTLE : Endian::BIG) {
307 initAsmInfo();
308}
309
310PPCTargetMachine::~PPCTargetMachine() = default;
311
312const PPCSubtarget *
313PPCTargetMachine::getSubtargetImpl(const Function &F) const {
314 Attribute CPUAttr = F.getFnAttribute(Kind: "target-cpu");
315 Attribute TuneAttr = F.getFnAttribute(Kind: "tune-cpu");
316 Attribute FSAttr = F.getFnAttribute(Kind: "target-features");
317
318 std::string CPU =
319 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
320 std::string TuneCPU =
321 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
322 std::string FS =
323 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
324
325 // FIXME: This is related to the code below to reset the target options,
326 // we need to know whether or not the soft float flag is set on the
327 // function before we can generate a subtarget. We also need to use
328 // it as a key for the subtarget since that can be the only difference
329 // between two functions.
330 bool SoftFloat = F.getFnAttribute(Kind: "use-soft-float").getValueAsBool();
331 // If the soft float attribute is set on the function turn on the soft float
332 // subtarget feature.
333 if (SoftFloat)
334 FS += FS.empty() ? "-hard-float" : ",-hard-float";
335
336 // Prefer the "target-abi" module flag, falling back to the -target-abi
337 // option.
338 StringRef ABIName = getTargetABIName(M: *F.getParent());
339
340 auto &I = SubtargetMap[CPU + TuneCPU + FS + ABIName.str()];
341 if (!I) {
342 I = std::make_unique<PPCSubtarget>(
343 args: TargetTriple, args&: CPU, args&: TuneCPU,
344 // FIXME: It would be good to have the subtarget additions here
345 // not necessary. Anything that turns them on/off (overrides) ends
346 // up being put at the end of the feature string, but the defaults
347 // shouldn't require adding them. Fixing this means pulling Feature64Bit
348 // out of most of the target cpus in the .td file and making it set only
349 // as part of initialization via the TargetTriple.
350 args: computeFSAdditions(FS, OL: getOptLevel(), TT: getTargetTriple()), args&: ABIName,
351 args: *this);
352 }
353 return I.get();
354}
355
356ScheduleDAGInstrs *
357PPCTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
358 return createPPCMachineScheduler(C);
359}
360
361ScheduleDAGInstrs *
362PPCTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
363 return createPPCPostMachineScheduler(C);
364}
365
366//===----------------------------------------------------------------------===//
367// Pass Pipeline Configuration
368//===----------------------------------------------------------------------===//
369
370namespace {
371
372/// PPC Code Generator Pass Configuration Options.
373class PPCPassConfig : public TargetPassConfig {
374public:
375 PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
376 : TargetPassConfig(TM, PM) {
377 // At any optimization level above -O0 we use the Machine Scheduler and not
378 // the default Post RA List Scheduler.
379 if (TM.getOptLevel() != CodeGenOptLevel::None)
380 substitutePass(StandardID: &PostRASchedulerID, TargetID: &PostMachineSchedulerID);
381 }
382
383 PPCTargetMachine &getPPCTargetMachine() const {
384 return getTM<PPCTargetMachine>();
385 }
386
387 void addIRPasses() override;
388 bool addPreISel() override;
389 bool addILPOpts() override;
390 bool addInstSelector() override;
391 void addMachineSSAOptimization() override;
392 void addPreRegAlloc() override;
393 void addPreSched2() override;
394 void addPreEmitPass() override;
395 void addPreEmitPass2() override;
396 // GlobalISEL
397 bool addIRTranslator() override;
398 bool addLegalizeMachineIR() override;
399 bool addRegBankSelect() override;
400 bool addGlobalInstructionSelect() override;
401};
402
403} // end anonymous namespace
404
405TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
406 return new PPCPassConfig(*this, PM);
407}
408
409void PPCPassConfig::addIRPasses() {
410 if (TM->getOptLevel() != CodeGenOptLevel::None)
411 addPass(P: createPPCBoolRetToIntPass());
412 addPass(P: createAtomicExpandLegacyPass());
413
414 // Lower generic MASSV routines to PowerPC subtarget-specific entries.
415 addPass(P: createPPCLowerMASSVEntriesPass());
416
417 // Generate PowerPC target-specific entries for scalar math functions
418 // that are available in IBM MASS (scalar) library.
419 if (TM->getOptLevel() == CodeGenOptLevel::Aggressive &&
420 EnablePPCGenScalarMASSEntries)
421 addPass(P: createPPCGenScalarMASSEntriesPass());
422
423 // If explicitly requested, add explicit data prefetch intrinsics.
424 if (EnablePrefetch.getNumOccurrences() > 0)
425 addPass(P: createLoopDataPrefetchPass());
426
427 if (TM->getOptLevel() >= CodeGenOptLevel::Default && EnableGEPOpt) {
428 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
429 // and lower a GEP with multiple indices to either arithmetic operations or
430 // multiple GEPs with single index.
431 addPass(P: createSeparateConstOffsetFromGEPPass(LowerGEP: true));
432 // Call EarlyCSE pass to find and remove subexpressions in the lowered
433 // result.
434 addPass(P: createEarlyCSEPass());
435 // Do loop invariant code motion in case part of the lowered result is
436 // invariant.
437 addPass(P: createLICMPass());
438 }
439
440 if (TM->getTargetTriple().isOSAIX())
441 addPass(P: createPPCPrepareIFuncsOnAIXPass());
442
443 TargetPassConfig::addIRPasses();
444}
445
446bool PPCPassConfig::addPreISel() {
447 // The GlobalMerge pass is intended to be on by default on AIX.
448 // Specifying the command line option overrides the AIX default.
449 if ((EnableGlobalMerge.getNumOccurrences() > 0)
450 ? EnableGlobalMerge
451 : getOptLevel() != CodeGenOptLevel::None)
452 addPass(P: createGlobalMergePass(TM, MaximalOffset: GlobalMergeMaxOffset, OnlyOptimizeForSize: false, MergeExternalByDefault: false, MergeConstantByDefault: true,
453 MergeConstAggressiveByDefault: true));
454
455 if (EnableInstrFormPrep && getOptLevel() != CodeGenOptLevel::None)
456 addPass(P: createPPCLoopInstrFormPrepPass(TM&: getPPCTargetMachine()));
457
458 if (EnableCTRLoops && getOptLevel() != CodeGenOptLevel::None)
459 addPass(P: createHardwareLoopsLegacyPass());
460
461 return false;
462}
463
464bool PPCPassConfig::addILPOpts() {
465 addPass(PassID: &EarlyIfConverterLegacyID);
466
467 if (EnableMachineCombinerPass)
468 addPass(PassID: &MachineCombinerID);
469
470 return true;
471}
472
473bool PPCPassConfig::addInstSelector() {
474 // Install an instruction selector.
475 addPass(P: createPPCISelDag(TM&: getPPCTargetMachine(), OL: getOptLevel()));
476
477#ifndef NDEBUG
478 if (EnableCTRLoops && getOptLevel() != CodeGenOptLevel::None)
479 addPass(createPPCCTRLoopsVerify());
480#endif
481
482 addPass(P: createPPCVSXWACCCopyPass());
483 return false;
484}
485
486void PPCPassConfig::addMachineSSAOptimization() {
487 // Run CTR loops pass before any cfg modification pass to prevent the
488 // canonical form of hardware loop from being destroied.
489 if (EnableCTRLoops && getOptLevel() != CodeGenOptLevel::None)
490 addPass(P: createPPCCTRLoopsPass());
491
492 // PPCBranchCoalescingPass need to be done before machine sinking
493 // since it merges empty blocks.
494 if (EnableBranchCoalescing && getOptLevel() != CodeGenOptLevel::None)
495 addPass(P: createPPCBranchCoalescingPass());
496 TargetPassConfig::addMachineSSAOptimization();
497 // For little endian, remove where possible the vector swap instructions
498 // introduced at code generation to normalize vector element order.
499 if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
500 EnableVSXSwapRemoval)
501 addPass(P: createPPCVSXSwapRemovalPass());
502 // Reduce the number of cr-logical ops.
503 if (ReduceCRLogical && getOptLevel() != CodeGenOptLevel::None)
504 addPass(P: createPPCReduceCRLogicalsPass());
505 // Target-specific peephole cleanups performed after instruction
506 // selection.
507 if (EnableMIPeephole) {
508 addPass(P: createPPCMIPeepholePass());
509 addPass(PassID: &DeadMachineInstructionElimID);
510 }
511}
512
513void PPCPassConfig::addPreRegAlloc() {
514 if (getOptLevel() != CodeGenOptLevel::None) {
515 insertPass(TargetPassID: VSXFMAMutateEarly ? &TwoAddressInstructionPassID
516 : &MachineSchedulerID,
517 InsertedPassID: &PPCVSXFMAMutateID);
518 }
519
520 // FIXME: We probably don't need to run these for -fPIE.
521 if (getPPCTargetMachine().isPositionIndependent()) {
522 // FIXME: LiveVariables should not be necessary here!
523 // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
524 // LiveVariables. This (unnecessary) dependency has been removed now,
525 // however a stage-2 clang build fails without LiveVariables computed here.
526 addPass(PassID: &LiveVariablesID);
527 addPass(P: createPPCTLSDynamicCallPass());
528 }
529 if (EnableExtraTOCRegDeps)
530 addPass(P: createPPCTOCRegDepsPass());
531
532 if (getOptLevel() != CodeGenOptLevel::None)
533 addPass(PassID: &MachinePipelinerID);
534}
535
536void PPCPassConfig::addPreSched2() {
537 if (getOptLevel() != CodeGenOptLevel::None)
538 addPass(PassID: &IfConverterID);
539}
540
541void PPCPassConfig::addPreEmitPass() {
542 addPass(P: createPPCPreEmitPeepholePass());
543
544 if (getOptLevel() != CodeGenOptLevel::None)
545 addPass(P: createPPCEarlyReturnPass());
546}
547
548void PPCPassConfig::addPreEmitPass2() {
549 // Schedule the expansion of AMOs at the last possible moment, avoiding the
550 // possibility for other passes to break the requirements for forward
551 // progress in the LL/SC block.
552 addPass(P: createPPCExpandAtomicPseudoPass());
553 // Must run branch selection immediately preceding the asm printer.
554 addPass(P: createPPCBranchSelectionPass());
555}
556
557TargetTransformInfo
558PPCTargetMachine::getTargetTransformInfo(const Function &F) const {
559 return TargetTransformInfo(std::make_unique<PPCTTIImpl>(args: this, args: F));
560}
561
562bool PPCTargetMachine::isLittleEndian() const {
563 assert(Endianness != Endian::NOT_DETECTED &&
564 "Unable to determine endianness");
565 return Endianness == Endian::LITTLE;
566}
567
568MachineFunctionInfo *PPCTargetMachine::createMachineFunctionInfo(
569 BumpPtrAllocator &Allocator, const Function &F,
570 const TargetSubtargetInfo *STI) const {
571 return PPCFunctionInfo::create<PPCFunctionInfo>(Allocator, F, STI);
572}
573
574static MachineSchedRegistry
575PPCPreRASchedRegistry("ppc-prera",
576 "Run PowerPC PreRA specific scheduler",
577 createPPCMachineScheduler);
578
579static MachineSchedRegistry
580PPCPostRASchedRegistry("ppc-postra",
581 "Run PowerPC PostRA specific scheduler",
582 createPPCPostMachineScheduler);
583
584// Global ISEL
585bool PPCPassConfig::addIRTranslator() {
586 addPass(P: new IRTranslatorLegacy());
587 return false;
588}
589
590bool PPCPassConfig::addLegalizeMachineIR() {
591 addPass(P: new LegalizerLegacy());
592 return false;
593}
594
595bool PPCPassConfig::addRegBankSelect() {
596 addPass(P: new RegBankSelectLegacy());
597 return false;
598}
599
600bool PPCPassConfig::addGlobalInstructionSelect() {
601 addPass(P: new InstructionSelectLegacy(getOptLevel()));
602 return false;
603}
604