1//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVMCTargetDesc.h"
15#include "TargetInfo/RISCVTargetInfo.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Endian.h"
27
28using namespace llvm;
29using namespace llvm::MCD;
30
31#define DEBUG_TYPE "riscv-disassembler"
32
33typedef MCDisassembler::DecodeStatus DecodeStatus;
34
35namespace {
36class RISCVDisassembler : public MCDisassembler {
37 std::unique_ptr<MCInstrInfo const> const MCII;
38
39public:
40 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
41 MCInstrInfo const *MCII)
42 : MCDisassembler(STI, Ctx), MCII(MCII) {}
43
44 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
45 ArrayRef<uint8_t> Bytes, uint64_t Address,
46 raw_ostream &CStream) const override;
47
48private:
49 DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
50 ArrayRef<uint8_t> Bytes, uint64_t Address,
51 raw_ostream &CStream) const;
52
53 DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
54 ArrayRef<uint8_t> Bytes, uint64_t Address,
55 raw_ostream &CStream) const;
56 DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
57 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream) const;
59};
60} // end anonymous namespace
61
62static MCDisassembler *createRISCVDisassembler(const Target &T,
63 const MCSubtargetInfo &STI,
64 MCContext &Ctx) {
65 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
66}
67
68static MCSymbolizer *
69createRISCVMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
70 LLVMSymbolLookupCallback /*SymbolLookUp*/,
71 void *DisInfo, MCContext *Ctx,
72 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
73 // RISC-V only asks MCSymbolizer to decode HI20/LO12 address fragments. They
74 // require relocation information and cannot be looked up as absolute
75 // addresses when GetOpInfo fails.
76 return llvm::createMCSymbolizer(TT, GetOpInfo, /*SymbolLookUp=*/nullptr,
77 DisInfo, Ctx, RelInfo: std::move(RelInfo));
78}
79
80extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
81LLVMInitializeRISCVDisassembler() {
82 // Register the disassembler for each target.
83 TargetRegistry::RegisterMCDisassembler(T&: getTheRISCV32Target(),
84 Fn: createRISCVDisassembler);
85 TargetRegistry::RegisterMCSymbolizer(T&: getTheRISCV32Target(),
86 Fn: createRISCVMCSymbolizer);
87 TargetRegistry::RegisterMCDisassembler(T&: getTheRISCV64Target(),
88 Fn: createRISCVDisassembler);
89 TargetRegistry::RegisterMCSymbolizer(T&: getTheRISCV64Target(),
90 Fn: createRISCVMCSymbolizer);
91 TargetRegistry::RegisterMCDisassembler(T&: getTheRISCV32beTarget(),
92 Fn: createRISCVDisassembler);
93 TargetRegistry::RegisterMCSymbolizer(T&: getTheRISCV32beTarget(),
94 Fn: createRISCVMCSymbolizer);
95 TargetRegistry::RegisterMCDisassembler(T&: getTheRISCV64beTarget(),
96 Fn: createRISCVDisassembler);
97 TargetRegistry::RegisterMCSymbolizer(T&: getTheRISCV64beTarget(),
98 Fn: createRISCVMCSymbolizer);
99}
100
101template <unsigned FirstReg, unsigned NumRegsInClass, unsigned RVELimit = 0>
102static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, uint32_t RegNo,
103 uint64_t Address,
104 const MCDisassembler *Decoder) {
105 bool CheckRVE = RVELimit != 0 &&
106 Decoder->getSubtargetInfo().hasFeature(Feature: RISCV::FeatureStdExtE);
107
108 if (RegNo >= NumRegsInClass || (CheckRVE && RegNo >= RVELimit))
109 return MCDisassembler::Fail;
110
111 MCRegister Reg = FirstReg + RegNo;
112 Inst.addOperand(Op: MCOperand::createReg(Reg));
113 return MCDisassembler::Success;
114}
115
116constexpr auto DecodeGPRRegisterClass =
117 DecodeSimpleRegisterClass<RISCV::X0, 32, /*RVELimit=*/16>;
118
119static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
120 uint64_t Address,
121 const MCDisassembler *Decoder) {
122 MCRegister Reg = RISCV::X0 + RegNo;
123 if (Reg != RISCV::X1 && Reg != RISCV::X5)
124 return MCDisassembler::Fail;
125
126 Inst.addOperand(Op: MCOperand::createReg(Reg));
127 return MCDisassembler::Success;
128}
129
130static DecodeStatus DecodeGPRX1RegisterClass(MCInst &Inst,
131 const MCDisassembler *Decoder) {
132 Inst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X1));
133 return MCDisassembler::Success;
134}
135
136static DecodeStatus DecodeSPRegisterClass(MCInst &Inst,
137 const MCDisassembler *Decoder) {
138 Inst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
139 return MCDisassembler::Success;
140}
141
142static DecodeStatus DecodeSPRegisterClass(MCInst &Inst, uint64_t RegNo,
143 uint32_t Address,
144 const MCDisassembler *Decoder) {
145 assert(RegNo == 2);
146 Inst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2));
147 return MCDisassembler::Success;
148}
149
150static DecodeStatus DecodeGPRX5RegisterClass(MCInst &Inst,
151 const MCDisassembler *Decoder) {
152 Inst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X5));
153 return MCDisassembler::Success;
154}
155
156template <auto DecodeFn, auto PredicateFn>
157static DecodeStatus DecodeFilteredRegisterClass(MCInst &Inst, uint32_t RegNo,
158 uint64_t Address,
159 const MCDisassembler *Decoder) {
160 if (!PredicateFn(RegNo))
161 return MCDisassembler::Fail;
162 return DecodeFn(Inst, RegNo, Address, Decoder);
163}
164
165constexpr bool PredNoX0(uint32_t RegNo) { return RegNo != 0; }
166constexpr bool PredNoX2(uint32_t RegNo) { return RegNo != 2; }
167constexpr bool PredNoX31(uint32_t RegNo) { return RegNo != 31; }
168
169constexpr auto DecodeGPRNoX0RegisterClass =
170 DecodeFilteredRegisterClass<DecodeGPRRegisterClass, PredNoX0>;
171constexpr auto DecodeGPRNoX2RegisterClass =
172 DecodeFilteredRegisterClass<DecodeGPRRegisterClass, PredNoX2>;
173constexpr auto DecodeGPRNoX31RegisterClass =
174 DecodeFilteredRegisterClass<DecodeGPRRegisterClass, PredNoX31>;
175
176static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
177 uint64_t Address,
178 const MCDisassembler *Decoder) {
179 if (RegNo >= 32 || RegNo % 2)
180 return MCDisassembler::Fail;
181
182 const RISCVDisassembler *Dis =
183 static_cast<const RISCVDisassembler *>(Decoder);
184 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
185 MCRegister Reg = RI->getMatchingSuperReg(
186 Reg: RISCV::X0 + RegNo, SubIdx: RISCV::sub_gpr_even,
187 RC: &getRISCVMCRegisterClass(RC: RISCV::GPRPairRegClassID));
188 Inst.addOperand(Op: MCOperand::createReg(Reg));
189 return MCDisassembler::Success;
190}
191
192constexpr auto DecodeGPRPairNoX0RegisterClass =
193 DecodeFilteredRegisterClass<DecodeGPRPairRegisterClass, PredNoX0>;
194
195static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo,
196 uint64_t Address,
197 const MCDisassembler *Decoder) {
198 if (RegNo >= 8 || RegNo % 2)
199 return MCDisassembler::Fail;
200
201 const RISCVDisassembler *Dis =
202 static_cast<const RISCVDisassembler *>(Decoder);
203 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
204 MCRegister Reg = RI->getMatchingSuperReg(
205 Reg: RISCV::X8 + RegNo, SubIdx: RISCV::sub_gpr_even,
206 RC: &getRISCVMCRegisterClass(RC: RISCV::GPRPairCRegClassID));
207 Inst.addOperand(Op: MCOperand::createReg(Reg));
208 return MCDisassembler::Success;
209}
210
211static DecodeStatus DecodeGPRS07RegisterClass(MCInst &Inst, uint32_t RegNo,
212 uint64_t Address,
213 const void *Decoder) {
214 if (RegNo >= 8)
215 return MCDisassembler::Fail;
216
217 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
218 Inst.addOperand(Op: MCOperand::createReg(Reg));
219 return MCDisassembler::Success;
220}
221
222template <unsigned RegisterClass, unsigned NumRegsInClass, unsigned LMul>
223static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, uint32_t RegNo,
224 uint64_t Address,
225 const MCDisassembler *Decoder) {
226 if (RegNo >= NumRegsInClass || RegNo % LMul)
227 return MCDisassembler::Fail;
228
229 const RISCVDisassembler *Dis =
230 static_cast<const RISCVDisassembler *>(Decoder);
231 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
232 MCRegister Reg =
233 RI->getMatchingSuperReg(Reg: RISCV::V0 + RegNo, SubIdx: RISCV::sub_vrm1_0,
234 RC: &getRISCVMCRegisterClass(RC: RegisterClass));
235
236 Inst.addOperand(Op: MCOperand::createReg(Reg));
237 return MCDisassembler::Success;
238}
239
240static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
241 uint64_t Address,
242 const MCDisassembler *Decoder) {
243 if (RegNo > 15 || RegNo % 2)
244 return MCDisassembler::Fail;
245
246 MCRegister Reg = RISCV::T0 + RegNo;
247 Inst.addOperand(Op: MCOperand::createReg(Reg));
248 return MCDisassembler::Success;
249}
250
251static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
252 uint64_t Address,
253 const MCDisassembler *Decoder) {
254 if (RegNo > 15 || RegNo % 4)
255 return MCDisassembler::Fail;
256
257 MCRegister Reg = RISCV::T0 + RegNo;
258 Inst.addOperand(Op: MCOperand::createReg(Reg));
259 return MCDisassembler::Success;
260}
261
262static DecodeStatus DecodeYBNDSWImm(MCInst &Inst, uint64_t Imm, int64_t Address,
263 const MCDisassembler *Decoder) {
264 assert(isUInt<9>(Imm) && "Invalid immediate");
265 uint64_t Result;
266 if (Imm == 0) {
267 // If imm[8:0] == 0, result is 4096.
268 Result = 4096;
269 } else if (Imm <= 255) {
270 // If imm[8] == 0 and imm[7:0] != 0, result is imm[7:0].
271 Result = Imm;
272 } else {
273 uint64_t Imm7To0 = Imm & 0xFF;
274 if (Imm7To0 <= 31) {
275 // If imm[8] == 1 and imm[7:5] == 0 (i.e. imm[7:0] <= 31), result is
276 // `256 | (imm[3:0] << 4) | (imm[4] << 3)`.
277 Result = 256 + ((Imm & 0xF) << 4) + (((Imm >> 4) & 1) << 3);
278 } else {
279 // Otherwise, result is imm[7:0] << 4.
280 Result = Imm7To0 << 4;
281 }
282 }
283 Inst.addOperand(Op: MCOperand::createImm(Val: Result));
284 return MCDisassembler::Success;
285}
286
287static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
288 uint64_t Address,
289 const MCDisassembler *Decoder) {
290 if (RegNo >= 2)
291 return MCDisassembler::Fail;
292
293 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
294
295 Inst.addOperand(Op: MCOperand::createReg(Reg));
296 return MCDisassembler::Success;
297}
298
299static DecodeStatus decodeImmThreeOperand(MCInst &Inst,
300 const MCDisassembler *Decoder) {
301 Inst.addOperand(Op: MCOperand::createImm(Val: 3));
302 return MCDisassembler::Success;
303}
304
305static DecodeStatus decodeImmFourOperand(MCInst &Inst,
306 const MCDisassembler *Decoder) {
307 Inst.addOperand(Op: MCOperand::createImm(Val: 4));
308 return MCDisassembler::Success;
309}
310
311template <unsigned N>
312static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
313 int64_t Address,
314 const MCDisassembler *Decoder) {
315 assert(isUInt<N>(Imm) && "Invalid immediate");
316 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
317 return MCDisassembler::Success;
318}
319
320template <unsigned Width, unsigned LowerBound>
321static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm,
322 int64_t Address,
323 const MCDisassembler *Decoder) {
324 assert(isUInt<Width>(Imm) && "Invalid immediate");
325
326 if (Imm < LowerBound)
327 return MCDisassembler::Fail;
328
329 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
330 return MCDisassembler::Success;
331}
332
333template <unsigned Width, unsigned LowerBound>
334static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
335 int64_t Address,
336 const MCDisassembler *Decoder) {
337 assert(isUInt<Width>(Imm) && "Invalid immediate");
338
339 if ((Imm + 1) < LowerBound)
340 return MCDisassembler::Fail;
341
342 Inst.addOperand(Op: MCOperand::createImm(Val: Imm + 1));
343 return MCDisassembler::Success;
344}
345
346static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm,
347 int64_t Address,
348 const MCDisassembler *Decoder) {
349 assert(isUInt<3>(Imm) && "Invalid Slist immediate");
350 const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};
351 Inst.addOperand(Op: MCOperand::createImm(Val: Slist[Imm]));
352 return MCDisassembler::Success;
353}
354
355static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
356 int64_t Address,
357 const MCDisassembler *Decoder) {
358 assert(isUInt<6>(Imm) && "Invalid immediate");
359
360 if (!Decoder->getSubtargetInfo().hasFeature(Feature: RISCV::Feature64Bit) &&
361 !isUInt<5>(x: Imm))
362 return MCDisassembler::Fail;
363
364 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
365 return MCDisassembler::Success;
366}
367
368static DecodeStatus decodeUImm7EqXLenOperand(MCInst &Inst, uint32_t Imm,
369 int64_t Address,
370 const MCDisassembler *Decoder) {
371 assert(isUInt<7>(Imm) && "Invalid immediate");
372
373 uint32_t ExpectedValue =
374 Decoder->getSubtargetInfo().hasFeature(Feature: RISCV::Feature64Bit) ? 64 : 32;
375 if (Imm != ExpectedValue)
376 return MCDisassembler::Fail;
377
378 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
379 return MCDisassembler::Success;
380}
381
382template <unsigned N>
383static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
384 int64_t Address,
385 const MCDisassembler *Decoder) {
386 if (Imm == 0)
387 return MCDisassembler::Fail;
388 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
389}
390
391static DecodeStatus
392decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
393 const MCDisassembler *Decoder) {
394 if (Imm == 0)
395 return MCDisassembler::Fail;
396 return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
397}
398
399template <unsigned N>
400static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm,
401 int64_t Address,
402 const MCDisassembler *Decoder) {
403 assert(isUInt<N>(Imm) && "Invalid immediate");
404 Inst.addOperand(Op: MCOperand::createImm(Val: Imm + 1));
405 return MCDisassembler::Success;
406}
407
408static DecodeStatus decodeImmZibiOperand(MCInst &Inst, uint32_t Imm,
409 int64_t Address,
410 const MCDisassembler *Decoder) {
411 assert(isUInt<5>(Imm) && "Invalid immediate");
412 Inst.addOperand(Op: MCOperand::createImm(Val: Imm ? Imm : -1LL));
413 return MCDisassembler::Success;
414}
415
416template <unsigned N>
417static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
418 int64_t Address,
419 const MCDisassembler *Decoder) {
420 assert(isUInt<N>(Imm) && "Invalid immediate");
421 // Sign-extend the number in the bottom N bits of Imm
422 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend64<N>(Imm)));
423 return MCDisassembler::Success;
424}
425
426static DecodeStatus decodeSImm12LoOperand(MCInst &Inst, uint32_t Imm,
427 int64_t Address,
428 const MCDisassembler *Decoder) {
429 assert(isUInt<12>(Imm) && "Invalid immediate");
430 const int64_t Value = SignExtend64<12>(x: Imm);
431 if (!Decoder->tryAddingSymbolicOperand(Inst, Value, Address,
432 /*IsBranch=*/false,
433 /*Offset=*/0, /*OpSize=*/4,
434 /*InstSize=*/4))
435 Inst.addOperand(Op: MCOperand::createImm(Val: Value));
436 return MCDisassembler::Success;
437}
438
439static DecodeStatus decodeUImm20Operand(MCInst &Inst, uint32_t Imm,
440 int64_t Address,
441 const MCDisassembler *Decoder) {
442 assert(isUInt<20>(Imm) && "Invalid immediate");
443 const int64_t Value = SignExtend64<32>(x: Imm << 12);
444 if (!Decoder->tryAddingSymbolicOperand(Inst, Value, Address,
445 /*IsBranch=*/false,
446 /*Offset=*/0, /*OpSize=*/4,
447 /*InstSize=*/4))
448 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
449 return MCDisassembler::Success;
450}
451
452template <unsigned N>
453static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
454 int64_t Address,
455 const MCDisassembler *Decoder) {
456 if (Imm == 0)
457 return MCDisassembler::Fail;
458 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
459}
460
461template <unsigned T, unsigned N>
462static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm,
463 int64_t Address,
464 const MCDisassembler *Decoder) {
465 assert(isUInt<T - N + 1>(Imm) && "Invalid immediate");
466 // Sign-extend the number in the bottom T bits of Imm after accounting for
467 // the fact that the T bit immediate is stored in T-N bits (the LSB is
468 // always zero)
469 Inst.addOperand(Op: MCOperand::createImm(Val: SignExtend64<T>(Imm << N)));
470 return MCDisassembler::Success;
471}
472
473static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
474 int64_t Address,
475 const MCDisassembler *Decoder) {
476 assert(isUInt<6>(Imm) && "Invalid immediate");
477 if (Imm == 0)
478 return MCDisassembler::Fail;
479 Imm = SignExtend64<6>(x: Imm) & 0xfffff;
480 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
481 return MCDisassembler::Success;
482}
483
484static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
485 const MCDisassembler *Decoder) {
486 assert(isUInt<3>(Imm) && "Invalid immediate");
487 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Mode: Imm))
488 return MCDisassembler::Fail;
489
490 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
491 return MCDisassembler::Success;
492}
493
494static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
495 uint64_t Address,
496 const MCDisassembler *Decoder) {
497 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(Feature: RISCV::FeatureStdExtE);
498 if (Imm < RISCVZC::RA || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
499 return MCDisassembler::Fail;
500 Inst.addOperand(Op: MCOperand::createImm(Val: Imm));
501 return MCDisassembler::Success;
502}
503
504static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
505 uint64_t Address,
506 const MCDisassembler *Decoder) {
507 if (Imm < RISCVZC::RA_S0)
508 return MCDisassembler::Fail;
509 return decodeZcmpRlist(Inst, Imm, Address, Decoder);
510}
511
512#include "RISCVGenDisassemblerTables.inc"
513
514namespace {
515
516struct DecoderListEntry {
517 const uint8_t *Table;
518 FeatureBitset ContainedFeatures;
519 const char *Desc;
520
521 bool haveContainedFeatures(const FeatureBitset &ActiveFeatures) const {
522 return ContainedFeatures.none() ||
523 (ContainedFeatures & ActiveFeatures).any();
524 }
525};
526
527} // end anonymous namespace
528
529static constexpr FeatureBitset XCVFeatureGroup = {
530 RISCV::FeatureVendorXCVbitmanip, RISCV::FeatureVendorXCVelw,
531 RISCV::FeatureVendorXCVmac, RISCV::FeatureVendorXCVmem,
532 RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,
533 RISCV::FeatureVendorXCVbi};
534
535static constexpr FeatureBitset XqciFeatureGroup = {
536 RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
537 RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
538 RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
539 RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
540 RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqciio,
541 RISCV::FeatureVendorXqcilb, RISCV::FeatureVendorXqcili,
542 RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
543 RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
544 RISCV::FeatureVendorXqcisls, RISCV::FeatureVendorXqcisync,
545};
546
547static constexpr FeatureBitset XSfVectorGroup = {
548 RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
549 RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
550 RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase,
551 RISCV::FeatureVendorXSfvfexpa, RISCV::FeatureVendorXSfvfexpa64e,
552 RISCV::FeatureVendorXSfvfbfexp16e, RISCV::FeatureVendorXSfvfexp16e,
553 RISCV::FeatureVendorXSfvfexp32e};
554static constexpr FeatureBitset XSfSystemGroup = {
555 RISCV::FeatureVendorXSiFivecdiscarddlone,
556 RISCV::FeatureVendorXSiFivecflushdlone,
557};
558
559static constexpr FeatureBitset XMIPSGroup = {
560 RISCV::FeatureVendorXMIPSLSP,
561 RISCV::FeatureVendorXMIPSCMov,
562 RISCV::FeatureVendorXMIPSCBOP,
563 RISCV::FeatureVendorXMIPSEXECTL,
564};
565
566static constexpr FeatureBitset XTHeadGroup = {
567 RISCV::FeatureVendorXTHeadBa, RISCV::FeatureVendorXTHeadBb,
568 RISCV::FeatureVendorXTHeadBs, RISCV::FeatureVendorXTHeadCondMov,
569 RISCV::FeatureVendorXTHeadCmo, RISCV::FeatureVendorXTHeadFMemIdx,
570 RISCV::FeatureVendorXTHeadMac, RISCV::FeatureVendorXTHeadMemIdx,
571 RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync,
572 RISCV::FeatureVendorXTHeadVdot};
573
574static constexpr FeatureBitset XAndesGroup = {
575 RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
576 RISCV::FeatureVendorXAndesVBFHCvt, RISCV::FeatureVendorXAndesVSIntH,
577 RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
578 RISCV::FeatureVendorXAndesVDot};
579
580static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot,
581 RISCV::FeatureVendorXSMTVDotII};
582
583static constexpr FeatureBitset XAIFGroup = {RISCV::FeatureVendorXAIFET};
584
585static constexpr DecoderListEntry DecoderList32[]{
586 // Vendor Extensions
587 {.Table: DecoderTableXCV32, .ContainedFeatures: XCVFeatureGroup, .Desc: "CORE-V extensions"},
588 {.Table: DecoderTableXqci32, .ContainedFeatures: XqciFeatureGroup, .Desc: "Qualcomm uC Extensions"},
589 {.Table: DecoderTableXVentana32,
590 .ContainedFeatures: {RISCV::FeatureVendorXVentanaCondOps},
591 .Desc: "XVentanaCondOps"},
592 {.Table: DecoderTableXTHead32, .ContainedFeatures: XTHeadGroup, .Desc: "T-Head extensions"},
593 {.Table: DecoderTableXSfvector32, .ContainedFeatures: XSfVectorGroup, .Desc: "SiFive vector extensions"},
594 {.Table: DecoderTableXSfsystem32, .ContainedFeatures: XSfSystemGroup, .Desc: "SiFive system extensions"},
595 {.Table: DecoderTableXSfcease32, .ContainedFeatures: {RISCV::FeatureVendorXSfcease}, .Desc: "SiFive sf.cease"},
596 {.Table: DecoderTableXMIPS32, .ContainedFeatures: XMIPSGroup, .Desc: "Mips extensions"},
597 {.Table: DecoderTableXAndes32, .ContainedFeatures: XAndesGroup, .Desc: "Andes extensions"},
598 {.Table: DecoderTableXSMT32, .ContainedFeatures: XSMTGroup, .Desc: "SpacemiT extensions"},
599 {.Table: DecoderTableXAIF32, .ContainedFeatures: XAIFGroup, .Desc: "AI Foundry extensions"},
600 // Standard Extensions
601 {.Table: DecoderTable32, .ContainedFeatures: {}, .Desc: "standard 32-bit instructions"},
602 {.Table: DecoderTableRV32Only32, .ContainedFeatures: {}, .Desc: "RV32-only standard 32-bit instructions"},
603 {.Table: DecoderTableZfinx32, .ContainedFeatures: {}, .Desc: "Zfinx (Float in Integer)"},
604 {.Table: DecoderTableZdinxRV32Only32, .ContainedFeatures: {}, .Desc: "RV32-only Zdinx (Double in Integer)"},
605};
606
607namespace {
608// Define bitwidths for various types used to instantiate the decoder.
609template <> constexpr uint32_t InsnBitWidth<uint16_t> = 16;
610template <> constexpr uint32_t InsnBitWidth<uint32_t> = 32;
611// Use uint64_t to represent 48 bit instructions.
612template <> constexpr uint32_t InsnBitWidth<uint64_t> = 48;
613} // namespace
614
615DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
616 ArrayRef<uint8_t> Bytes,
617 uint64_t Address,
618 raw_ostream &CS) const {
619 if (Bytes.size() < 4) {
620 Size = 0;
621 return MCDisassembler::Fail;
622 }
623 Size = 4;
624
625 uint32_t Insn = support::endian::read32le(P: Bytes.data());
626
627 for (const DecoderListEntry &Entry : DecoderList32) {
628 if (!Entry.haveContainedFeatures(ActiveFeatures: STI.getFeatureBits()))
629 continue;
630
631 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
632 DecodeStatus Result =
633 decodeInstruction(DecodeTable: Entry.Table, MI, insn: Insn, Address, DisAsm: this, STI);
634 if (Result == MCDisassembler::Fail)
635 continue;
636
637 return Result;
638 }
639
640 return MCDisassembler::Fail;
641}
642
643static constexpr DecoderListEntry DecoderList16[]{
644 // Vendor Extensions
645 {.Table: DecoderTableXqci16, .ContainedFeatures: XqciFeatureGroup, .Desc: "Qualcomm uC 16-bit"},
646 {.Table: DecoderTableXqccmp16,
647 .ContainedFeatures: {RISCV::FeatureVendorXqccmp},
648 .Desc: "Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
649 {.Table: DecoderTableXqccmt16,
650 .ContainedFeatures: {RISCV::FeatureVendorXqccmt},
651 .Desc: "Xqccmt (Qualcomm 16-bit Table Jump Instructions)"},
652 {.Table: DecoderTableXwchc16, .ContainedFeatures: {RISCV::FeatureVendorXwchc}, .Desc: "WCH QingKe XW"},
653 // Standard Extensions
654 // DecoderTableZicfiss16 must be checked before DecoderTable16.
655 {.Table: DecoderTableZicfiss16, .ContainedFeatures: {}, .Desc: "Zicfiss (Shadow Stack 16-bit)"},
656 {.Table: DecoderTable16, .ContainedFeatures: {}, .Desc: "standard 16-bit instructions"},
657 {.Table: DecoderTableRV32Only16, .ContainedFeatures: {}, .Desc: "RV32-only 16-bit instructions"},
658 // Zc* instructions incompatible with Zcf or Zcd
659 {.Table: DecoderTableZcOverlap16,
660 .ContainedFeatures: {},
661 .Desc: "ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)"},
662};
663
664DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
665 ArrayRef<uint8_t> Bytes,
666 uint64_t Address,
667 raw_ostream &CS) const {
668 if (Bytes.size() < 2) {
669 Size = 0;
670 return MCDisassembler::Fail;
671 }
672 Size = 2;
673
674 uint16_t Insn = support::endian::read16le(P: Bytes.data());
675
676 for (const DecoderListEntry &Entry : DecoderList16) {
677 if (!Entry.haveContainedFeatures(ActiveFeatures: STI.getFeatureBits()))
678 continue;
679
680 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
681 DecodeStatus Result =
682 decodeInstruction(DecodeTable: Entry.Table, MI, insn: Insn, Address, DisAsm: this, STI);
683 if (Result != MCDisassembler::Fail)
684 return Result;
685 }
686
687 return MCDisassembler::Fail;
688}
689
690static constexpr DecoderListEntry DecoderList48[]{
691 {.Table: DecoderTableXqci48, .ContainedFeatures: XqciFeatureGroup, .Desc: "Qualcomm uC 48bit"},
692};
693
694DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
695 ArrayRef<uint8_t> Bytes,
696 uint64_t Address,
697 raw_ostream &CS) const {
698 if (Bytes.size() < 6) {
699 Size = 0;
700 return MCDisassembler::Fail;
701 }
702 Size = 6;
703
704 uint64_t Insn = 0;
705 for (size_t i = Size; i-- != 0;)
706 Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
707
708 for (const DecoderListEntry &Entry : DecoderList48) {
709 if (!Entry.haveContainedFeatures(ActiveFeatures: STI.getFeatureBits()))
710 continue;
711
712 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
713 DecodeStatus Result =
714 decodeInstruction(DecodeTable: Entry.Table, MI, insn: Insn, Address, DisAsm: this, STI);
715 if (Result == MCDisassembler::Fail)
716 continue;
717
718 return Result;
719 }
720
721 return MCDisassembler::Fail;
722}
723
724DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
725 ArrayRef<uint8_t> Bytes,
726 uint64_t Address,
727 raw_ostream &CS) const {
728 CommentStream = &CS;
729 // It's a 16 bit instruction if bit 0 and 1 are not 0b11.
730 if ((Bytes[0] & 0b11) != 0b11)
731 return getInstruction16(MI, Size, Bytes, Address, CS);
732
733 // Try to decode as a 32-bit instruction first.
734 DecodeStatus Result = getInstruction32(MI, Size, Bytes, Address, CS);
735 if (Result != MCDisassembler::Fail)
736 return Result;
737
738 // If bits [4:2] are 0b111 this might be a 48-bit or larger instruction,
739 // otherwise assume it's an unknown 32-bit instruction.
740 if ((Bytes[0] & 0b1'1100) != 0b1'1100) {
741 Size = Bytes.size() >= 4 ? 4 : 0;
742 return MCDisassembler::Fail;
743 }
744
745 // 48-bit instructions are encoded as 0bxx011111.
746 if ((Bytes[0] & 0b11'1111) == 0b01'1111)
747 return getInstruction48(MI, Size, Bytes, Address, CS);
748
749 // 64-bit instructions are encoded as 0x0111111.
750 if ((Bytes[0] & 0b111'1111) == 0b011'1111) {
751 Size = Bytes.size() >= 8 ? 8 : 0;
752 return MCDisassembler::Fail;
753 }
754
755 // Remaining cases need to check a second byte.
756 if (Bytes.size() < 2) {
757 Size = 0;
758 return MCDisassembler::Fail;
759 }
760
761 // 80-bit through 176-bit instructions are encoded as 0bxnnnxxxx_x1111111.
762 // Where the number of bits is (80 + (nnn * 16)) for nnn != 0b111.
763 unsigned nnn = (Bytes[1] >> 4) & 0b111;
764 if (nnn != 0b111) {
765 Size = 10 + (nnn * 2);
766 if (Bytes.size() < Size)
767 Size = 0;
768 return MCDisassembler::Fail;
769 }
770
771 // Remaining encodings are reserved for > 176-bit instructions.
772 Size = 0;
773 return MCDisassembler::Fail;
774}
775