1//===-- RISCVAsmBackend.cpp - RISC-V Assembler Backend --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCVAsmBackend.h"
10#include "RISCVFixupKinds.h"
11#include "llvm/ADT/APInt.h"
12#include "llvm/MC/MCAsmInfo.h"
13#include "llvm/MC/MCAssembler.h"
14#include "llvm/MC/MCContext.h"
15#include "llvm/MC/MCELFObjectWriter.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCMachObjectWriter.h"
18#include "llvm/MC/MCObjectWriter.h"
19#include "llvm/MC/MCSymbol.h"
20#include "llvm/MC/MCValue.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/EndianStream.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/LEB128.h"
25#include "llvm/Support/raw_ostream.h"
26
27using namespace llvm;
28
29// Temporary workaround for old linkers that do not support ULEB128 relocations,
30// which are abused by DWARF v5 DW_LLE_offset_pair/DW_RLE_offset_pair
31// implemented in Clang/LLVM.
32static cl::opt<bool> ULEB128Reloc(
33 "riscv-uleb128-reloc", cl::init(Val: true), cl::Hidden,
34 cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate"));
35
36static cl::opt<bool>
37 AlignRvc("riscv-align-rvc", cl::init(Val: true), cl::Hidden,
38 cl::desc("When generating R_RISCV_ALIGN, insert $alignment-2 "
39 "bytes of NOPs even in norvc code"));
40
41RISCVAsmBackend::RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI,
42 bool Is64Bit, bool IsLittleEndian,
43 const MCTargetOptions &Options)
44 : MCAsmBackend(IsLittleEndian ? llvm::endianness::little
45 : llvm::endianness::big),
46 STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
47 RISCVFeatures::validate(TT: STI.getTargetTriple(), FeatureBits: STI.getFeatureBits());
48}
49
50std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
51 if (STI.getTargetTriple().isOSBinFormatELF()) {
52 unsigned Type;
53 Type = llvm::StringSwitch<unsigned>(Name)
54#define ELF_RELOC(NAME, ID) .Case(#NAME, ID)
55#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
56#undef ELF_RELOC
57#define ELF_RISCV_NONSTANDARD_RELOC(_VENDOR, NAME, ID) .Case(#NAME, ID)
58#include "llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def"
59#undef ELF_RISCV_NONSTANDARD_RELOC
60 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_RISCV_NONE)
61 .Case(S: "BFD_RELOC_32", Value: ELF::R_RISCV_32)
62 .Case(S: "BFD_RELOC_64", Value: ELF::R_RISCV_64)
63 .Default(Value: -1u);
64 if (Type != -1u)
65 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
66 }
67 return std::nullopt;
68}
69
70MCFixupKindInfo RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
71 const static MCFixupKindInfo Infos[] = {
72 // This table *must* be in the order that the fixup_* kinds are defined in
73 // RISCVFixupKinds.h.
74 //
75 // name offset bits flags
76 {.Name: "fixup_riscv_hi20", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
77 {.Name: "fixup_riscv_lo12_i", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
78 {.Name: "fixup_riscv_12_i", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
79 {.Name: "fixup_riscv_lo12_s", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
80 {.Name: "fixup_riscv_pcrel_hi20", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
81 {.Name: "fixup_riscv_pcrel_lo12_i", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
82 {.Name: "fixup_riscv_pcrel_lo12_s", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
83 {.Name: "fixup_riscv_jal", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
84 {.Name: "fixup_riscv_branch", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
85 {.Name: "fixup_riscv_rvc_jump", .TargetOffset: 2, .TargetSize: 11, .Flags: 0},
86 {.Name: "fixup_riscv_rvc_branch", .TargetOffset: 0, .TargetSize: 16, .Flags: 0},
87 {.Name: "fixup_riscv_rvc_imm", .TargetOffset: 0, .TargetSize: 16, .Flags: 0},
88 {.Name: "fixup_riscv_call", .TargetOffset: 0, .TargetSize: 64, .Flags: 0},
89 {.Name: "fixup_riscv_call_plt", .TargetOffset: 0, .TargetSize: 64, .Flags: 0},
90
91 {.Name: "fixup_riscv_qc_e_branch", .TargetOffset: 0, .TargetSize: 48, .Flags: 0},
92 {.Name: "fixup_riscv_qc_e_32", .TargetOffset: 16, .TargetSize: 32, .Flags: 0},
93 {.Name: "fixup_riscv_qc_abs20_u", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
94 {.Name: "fixup_riscv_qc_e_call_plt", .TargetOffset: 0, .TargetSize: 48, .Flags: 0},
95
96 // Andes fixups
97 {.Name: "fixup_riscv_nds_branch_10", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
98 };
99 static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
100 "Not all fixup kinds added to Infos array");
101
102 // Fixup kinds from raw relocation types and .reloc directives force
103 // relocations and do not use these fields.
104 if (mc::isRelocation(FixupKind: Kind))
105 return {};
106
107 if (Kind < FirstTargetFixupKind)
108 return MCAsmBackend::getFixupKindInfo(Kind);
109
110 assert(unsigned(Kind - FirstTargetFixupKind) < RISCV::NumTargetFixupKinds &&
111 "Invalid kind!");
112 return Infos[Kind - FirstTargetFixupKind];
113}
114
115bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFragment &,
116 const MCFixup &Fixup,
117 const MCValue &,
118 uint64_t Value,
119 bool Resolved) const {
120 int64_t Offset = int64_t(Value);
121 auto Kind = Fixup.getKind();
122
123 // Return true if the symbol is unresolved.
124 if (!Resolved)
125 return true;
126
127 switch (Kind) {
128 default:
129 return false;
130 case RISCV::fixup_riscv_rvc_branch:
131 // For compressed branch instructions the immediate must be
132 // in the range [-256, 254].
133 return Offset > 254 || Offset < -256;
134 case RISCV::fixup_riscv_rvc_jump:
135 // For compressed jump instructions the immediate must be
136 // in the range [-2048, 2046].
137 return Offset > 2046 || Offset < -2048;
138 case RISCV::fixup_riscv_branch:
139 case RISCV::fixup_riscv_qc_e_branch:
140 // For conditional branch instructions the immediate must be
141 // in the range [-4096, 4094].
142 return Offset > 4094 || Offset < -4096;
143 case RISCV::fixup_riscv_jal:
144 // For jump instructions the immediate must be in the range
145 // [-1048576, 1048574]
146 return Offset > 1048574 || Offset < -1048576;
147 case RISCV::fixup_riscv_rvc_imm:
148 // This fixup can never be emitted as a relocation, so always needs to be
149 // relaxed.
150 return true;
151 }
152}
153
154// Given a compressed control flow instruction this function returns
155// the expanded instruction, or the original instruction code if no
156// expansion is available.
157static unsigned getRelaxedOpcode(unsigned Opcode, ArrayRef<MCOperand> Operands,
158 const MCSubtargetInfo &STI) {
159 switch (Opcode) {
160 case RISCV::C_BEQZ:
161 return RISCV::BEQ;
162 case RISCV::C_BNEZ:
163 return RISCV::BNE;
164 case RISCV::C_J:
165 case RISCV::C_JAL: // fall through.
166 // This only relaxes one "step" - i.e. from C.J to JAL, not from C.J to
167 // QC.E.J, because we can always relax again if needed.
168 return RISCV::JAL;
169 case RISCV::C_LI:
170 if (!STI.hasFeature(Feature: RISCV::FeatureVendorXqcili))
171 break;
172 // We only need this because `QC.E.LI` can be compressed into a `C.LI`. This
173 // happens because the `simm6` MCOperandPredicate accepts bare symbols, and
174 // `QC.E.LI` is the only instruction that accepts bare symbols at parse-time
175 // and compresses to `C.LI`. `C.LI` does not itself accept bare symbols at
176 // parse time.
177 //
178 // If we have a bare symbol, we need to turn this back to a `QC.E.LI`, as we
179 // have no way to emit a relocation on a `C.LI` instruction.
180 return RISCV::QC_E_LI;
181 case RISCV::JAL: {
182 // We can only relax JAL if we have Xqcilb
183 if (!STI.hasFeature(Feature: RISCV::FeatureVendorXqcilb))
184 break;
185
186 // And only if it is using X0 or X1 for rd.
187 MCRegister Reg = Operands[0].getReg();
188 if (Reg == RISCV::X0)
189 return RISCV::QC_E_J;
190 if (Reg == RISCV::X1)
191 return RISCV::QC_E_JAL;
192
193 break;
194 }
195 case RISCV::BEQ:
196 return RISCV::PseudoLongBEQ;
197 case RISCV::BNE:
198 return RISCV::PseudoLongBNE;
199 case RISCV::BLT:
200 return RISCV::PseudoLongBLT;
201 case RISCV::BGE:
202 return RISCV::PseudoLongBGE;
203 case RISCV::BLTU:
204 return RISCV::PseudoLongBLTU;
205 case RISCV::BGEU:
206 return RISCV::PseudoLongBGEU;
207 case RISCV::QC_BEQI:
208 return RISCV::PseudoLongQC_BEQI;
209 case RISCV::QC_BNEI:
210 return RISCV::PseudoLongQC_BNEI;
211 case RISCV::QC_BLTI:
212 return RISCV::PseudoLongQC_BLTI;
213 case RISCV::QC_BGEI:
214 return RISCV::PseudoLongQC_BGEI;
215 case RISCV::QC_BLTUI:
216 return RISCV::PseudoLongQC_BLTUI;
217 case RISCV::QC_BGEUI:
218 return RISCV::PseudoLongQC_BGEUI;
219 case RISCV::QC_E_BEQI:
220 return RISCV::PseudoLongQC_E_BEQI;
221 case RISCV::QC_E_BNEI:
222 return RISCV::PseudoLongQC_E_BNEI;
223 case RISCV::QC_E_BLTI:
224 return RISCV::PseudoLongQC_E_BLTI;
225 case RISCV::QC_E_BGEI:
226 return RISCV::PseudoLongQC_E_BGEI;
227 case RISCV::QC_E_BLTUI:
228 return RISCV::PseudoLongQC_E_BLTUI;
229 case RISCV::QC_E_BGEUI:
230 return RISCV::PseudoLongQC_E_BGEUI;
231 }
232
233 // Returning the original opcode means we cannot relax the instruction.
234 return Opcode;
235}
236
237void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
238 const MCSubtargetInfo &STI) const {
239 if (STI.hasFeature(Feature: RISCV::FeatureExactAssembly))
240 return;
241
242 MCInst Res;
243 switch (Inst.getOpcode()) {
244 default:
245 llvm_unreachable("Opcode not expected!");
246 case RISCV::C_BEQZ:
247 case RISCV::C_BNEZ:
248 case RISCV::C_J:
249 case RISCV::C_JAL: {
250 [[maybe_unused]] bool Success = RISCVRVC::uncompress(OutInst&: Res, MI: Inst, STI);
251 assert(Success && "Can't uncompress instruction");
252 assert(Res.getOpcode() ==
253 getRelaxedOpcode(Inst.getOpcode(), Inst.getOperands(), STI) &&
254 "Branch Relaxation Error");
255 break;
256 }
257 case RISCV::JAL: {
258 // This has to be written manually because the QC.E.J -> JAL is
259 // compression-only, so that it is not used when printing disassembly.
260 assert(STI.hasFeature(RISCV::FeatureVendorXqcilb) &&
261 "JAL is only relaxable with Xqcilb");
262 assert((Inst.getOperand(0).getReg() == RISCV::X0 ||
263 Inst.getOperand(0).getReg() == RISCV::X1) &&
264 "JAL only relaxable with rd=x0 or rd=x1");
265 Res.setOpcode(getRelaxedOpcode(Opcode: Inst.getOpcode(), Operands: Inst.getOperands(), STI));
266 Res.addOperand(Op: Inst.getOperand(i: 1));
267 break;
268 }
269 case RISCV::C_LI: {
270 // This should only be hit when trying to relax a `C.LI` into a `QC.E.LI`
271 // because the `C.LI` has a bare symbol. We cannot use
272 // `RISCVRVC::uncompress` because it will use decompression patterns. The
273 // `QC.E.LI` compression pattern to `C.LI` is compression-only (because we
274 // don't want `c.li` ever printed as `qc.e.li`, which might be done if the
275 // pattern applied to decompression), but that doesn't help much becuase
276 // `C.LI` with a bare symbol will decompress to an `ADDI` anyway (because
277 // `simm12`'s MCOperandPredicate accepts a bare symbol and that pattern
278 // comes first), and we still cannot emit an `ADDI` with a bare symbol.
279 assert(STI.hasFeature(RISCV::FeatureVendorXqcili) &&
280 "C.LI is only relaxable with Xqcili");
281 Res.setOpcode(getRelaxedOpcode(Opcode: Inst.getOpcode(), Operands: Inst.getOperands(), STI));
282 Res.addOperand(Op: Inst.getOperand(i: 0));
283 Res.addOperand(Op: Inst.getOperand(i: 1));
284 break;
285 }
286 case RISCV::BEQ:
287 case RISCV::BNE:
288 case RISCV::BLT:
289 case RISCV::BGE:
290 case RISCV::BLTU:
291 case RISCV::BGEU:
292 case RISCV::QC_BEQI:
293 case RISCV::QC_BNEI:
294 case RISCV::QC_BLTI:
295 case RISCV::QC_BGEI:
296 case RISCV::QC_BLTUI:
297 case RISCV::QC_BGEUI:
298 case RISCV::QC_E_BEQI:
299 case RISCV::QC_E_BNEI:
300 case RISCV::QC_E_BLTI:
301 case RISCV::QC_E_BGEI:
302 case RISCV::QC_E_BLTUI:
303 case RISCV::QC_E_BGEUI:
304 Res.setOpcode(getRelaxedOpcode(Opcode: Inst.getOpcode(), Operands: Inst.getOperands(), STI));
305 Res.addOperand(Op: Inst.getOperand(i: 0));
306 Res.addOperand(Op: Inst.getOperand(i: 1));
307 Res.addOperand(Op: Inst.getOperand(i: 2));
308 break;
309 }
310 Inst = std::move(Res);
311}
312
313// Check if an R_RISCV_ALIGN relocation is needed for an alignment directive.
314// If conditions are met, compute the padding size and create a fixup encoding
315// the padding size in the addend.
316bool RISCVAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) {
317 // Alignments before the first linker-relaxable instruction have fixed sizes
318 // and do not require relocations. Alignments after a linker-relaxable
319 // instruction require a relocation, even if the STI specifies norelax.
320 //
321 // firstLinkerRelaxable is the layout order within the subsection, which may
322 // be smaller than the section's order. Therefore, alignments in a
323 // lower-numbered subsection may be unnecessarily treated as linker-relaxable.
324 auto *Sec = F.getParent();
325 if (F.getLayoutOrder() <= Sec->firstLinkerRelaxable())
326 return false;
327
328 // Use default handling unless the alignment is larger than the nop size.
329 const MCSubtargetInfo *STI = F.getSubtargetInfo();
330 unsigned MinNopLen =
331 AlignRvc || STI->hasFeature(Feature: RISCV::FeatureStdExtZca) ? 2 : 4;
332 if (F.getAlignment() <= MinNopLen)
333 return false;
334
335 Size = F.getAlignment().value() - MinNopLen;
336 auto *Expr = MCConstantExpr::create(Value: Size, Ctx&: getContext());
337 MCFixup Fixup =
338 MCFixup::create(Offset: 0, Value: Expr, Kind: FirstLiteralRelocationKind + ELF::R_RISCV_ALIGN);
339 F.setVarFixups({Fixup});
340 F.setLinkerRelaxable();
341 return true;
342}
343
344bool RISCVAsmBackend::relaxDwarfLineAddr(MCFragment &F) const {
345 int64_t LineDelta = F.getDwarfLineDelta();
346 const MCExpr &AddrDelta = F.getDwarfAddrDelta();
347 int64_t Value;
348 // If the label difference can be resolved, use the default handling, which
349 // utilizes a shorter special opcode.
350 if (AddrDelta.evaluateAsAbsolute(Res&: Value, Asm: *Asm))
351 return false;
352 [[maybe_unused]] bool IsAbsolute =
353 AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm: *Asm);
354 assert(IsAbsolute && "CFA with invalid expression");
355
356 SmallVector<char> Data;
357 raw_svector_ostream OS(Data);
358
359 // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
360 if (LineDelta != INT64_MAX) {
361 OS << uint8_t(dwarf::DW_LNS_advance_line);
362 encodeSLEB128(Value: LineDelta, OS);
363 }
364
365 // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
366 // takes a single unsigned half (unencoded) operand. The maximum encodable
367 // value is therefore 65535. Set a conservative upper bound for relaxation.
368 unsigned PCBytes;
369 if (Value > 60000) {
370 PCBytes = getContext().getAsmInfo()->getCodePointerSize();
371 OS << uint8_t(dwarf::DW_LNS_extended_op) << uint8_t(PCBytes + 1)
372 << uint8_t(dwarf::DW_LNE_set_address);
373 OS.write_zeros(NumZeros: PCBytes);
374 } else {
375 PCBytes = 2;
376 OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
377 support::endian::write<uint16_t>(os&: OS, value: 0, endian: Endian);
378 }
379 auto Offset = OS.tell() - PCBytes;
380
381 if (LineDelta == INT64_MAX) {
382 OS << uint8_t(dwarf::DW_LNS_extended_op);
383 OS << uint8_t(1);
384 OS << uint8_t(dwarf::DW_LNE_end_sequence);
385 } else {
386 OS << uint8_t(dwarf::DW_LNS_copy);
387 }
388
389 F.setVarContents(Data);
390 F.setVarFixups({MCFixup::create(Offset, Value: &AddrDelta,
391 Kind: MCFixup::getDataKindForSize(Size: PCBytes))});
392 return true;
393}
394
395bool RISCVAsmBackend::relaxDwarfCFA(MCFragment &F) const {
396 const MCExpr &AddrDelta = F.getDwarfAddrDelta();
397 SmallVector<MCFixup, 2> Fixups;
398 int64_t Value;
399 if (AddrDelta.evaluateAsAbsolute(Res&: Value, Asm: *Asm))
400 return false;
401 [[maybe_unused]] bool IsAbsolute =
402 AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm: *Asm);
403 assert(IsAbsolute && "CFA with invalid expression");
404
405 assert(getContext().getAsmInfo()->getMinInstAlignment() == 1 &&
406 "expected 1-byte alignment");
407 if (Value == 0) {
408 F.clearVarContents();
409 F.clearVarFixups();
410 return true;
411 }
412
413 auto AddFixups = [&Fixups, &AddrDelta](unsigned Offset,
414 std::pair<unsigned, unsigned> Fixup) {
415 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(Val: AddrDelta);
416 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getLHS(), Kind: std::get<0>(in&: Fixup)));
417 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getRHS(), Kind: std::get<1>(in&: Fixup)));
418 };
419
420 SmallVector<char, 8> Data;
421 raw_svector_ostream OS(Data);
422 if (isUIntN(N: 6, x: Value)) {
423 OS << uint8_t(dwarf::DW_CFA_advance_loc);
424 AddFixups(0, {ELF::R_RISCV_SET6, ELF::R_RISCV_SUB6});
425 } else if (isUInt<8>(x: Value)) {
426 OS << uint8_t(dwarf::DW_CFA_advance_loc1);
427 support::endian::write<uint8_t>(os&: OS, value: 0, endian: Endian);
428 AddFixups(1, {ELF::R_RISCV_SET8, ELF::R_RISCV_SUB8});
429 } else if (isUInt<16>(x: Value)) {
430 OS << uint8_t(dwarf::DW_CFA_advance_loc2);
431 support::endian::write<uint16_t>(os&: OS, value: 0, endian: Endian);
432 AddFixups(1, {ELF::R_RISCV_SET16, ELF::R_RISCV_SUB16});
433 } else if (isUInt<32>(x: Value)) {
434 OS << uint8_t(dwarf::DW_CFA_advance_loc4);
435 support::endian::write<uint32_t>(os&: OS, value: 0, endian: Endian);
436 AddFixups(1, {ELF::R_RISCV_SET32, ELF::R_RISCV_SUB32});
437 } else {
438 llvm_unreachable("unsupported CFA encoding");
439 }
440 F.setVarContents(Data);
441 F.setVarFixups(Fixups);
442 return true;
443}
444
445std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(MCFragment &LF,
446 int64_t &Value) const {
447 if (LF.isLEBSigned())
448 return std::make_pair(x: false, y: false);
449 const MCExpr &Expr = LF.getLEBValue();
450 if (ULEB128Reloc) {
451 LF.setVarFixups({MCFixup::create(Offset: 0, Value: &Expr, Kind: FK_Data_leb128)});
452 }
453 return std::make_pair(x: Expr.evaluateKnownAbsolute(Res&: Value, Asm: *Asm), y: false);
454}
455
456bool RISCVAsmBackend::mayNeedRelaxation(unsigned Opcode,
457 ArrayRef<MCOperand> Operands,
458 const MCSubtargetInfo &STI) const {
459 // This function has access to two STIs, the member of the AsmBackend, and the
460 // one passed as an argument. The latter is more specific, so we query it for
461 // specific features.
462 if (STI.hasFeature(Feature: RISCV::FeatureExactAssembly))
463 return false;
464
465 return getRelaxedOpcode(Opcode, Operands, STI) != Opcode;
466}
467
468bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
469 const MCSubtargetInfo *STI) const {
470 // We mostly follow binutils' convention here: align to even boundary with a
471 // 0-fill padding. We emit up to 1 2-byte nop, though we use c.nop if RVC is
472 // enabled or 0-fill otherwise. The remainder is now padded with 4-byte nops.
473
474 // Instructions always are at even addresses. We must be in a data area or
475 // be unaligned due to some other reason.
476 if (Count % 2) {
477 OS.write(Ptr: "\0", Size: 1);
478 Count -= 1;
479 }
480
481 // TODO: emit a mapping symbol right here
482
483 if (Count % 4 == 2) {
484 // The canonical nop with Zca is c.nop. For .balign 4, we generate a 2-byte
485 // c.nop even in a norvc region.
486 OS.write(Ptr: "\x01\0", Size: 2);
487 Count -= 2;
488 }
489
490 // The canonical nop on RISC-V is addi x0, x0, 0.
491 for (; Count >= 4; Count -= 4)
492 OS.write(Ptr: "\x13\0\0\0", Size: 4);
493
494 return true;
495}
496
497static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
498 MCContext &Ctx) {
499 switch (Fixup.getKind()) {
500 default:
501 llvm_unreachable("Unknown fixup kind!");
502 case FK_Data_1:
503 case FK_Data_2:
504 case FK_Data_4:
505 case FK_Data_8:
506 case FK_Data_leb128:
507 return Value;
508 case RISCV::fixup_riscv_lo12_i:
509 case RISCV::fixup_riscv_pcrel_lo12_i:
510 return Value & 0xfff;
511 case RISCV::fixup_riscv_12_i:
512 if (!isInt<12>(x: Value)) {
513 Ctx.reportError(L: Fixup.getLoc(),
514 Msg: "operand must be a constant 12-bit integer");
515 }
516 return Value & 0xfff;
517 case RISCV::fixup_riscv_lo12_s:
518 case RISCV::fixup_riscv_pcrel_lo12_s:
519 return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
520 case RISCV::fixup_riscv_hi20:
521 case RISCV::fixup_riscv_pcrel_hi20:
522 // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
523 return ((Value + 0x800) >> 12) & 0xfffff;
524 case RISCV::fixup_riscv_jal: {
525 if (!isInt<21>(x: Value))
526 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
527 if (Value & 0x1)
528 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
529 // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
530 unsigned Sbit = (Value >> 20) & 0x1;
531 unsigned Hi8 = (Value >> 12) & 0xff;
532 unsigned Mid1 = (Value >> 11) & 0x1;
533 unsigned Lo10 = (Value >> 1) & 0x3ff;
534 // Inst{31} = Sbit;
535 // Inst{30-21} = Lo10;
536 // Inst{20} = Mid1;
537 // Inst{19-12} = Hi8;
538 Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
539 return Value;
540 }
541 case RISCV::fixup_riscv_qc_e_branch:
542 case RISCV::fixup_riscv_branch: {
543 if (!isInt<13>(x: Value))
544 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
545 if (Value & 0x1)
546 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
547 // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
548 // Value.
549 unsigned Sbit = (Value >> 12) & 0x1;
550 unsigned Hi1 = (Value >> 11) & 0x1;
551 unsigned Mid6 = (Value >> 5) & 0x3f;
552 unsigned Lo4 = (Value >> 1) & 0xf;
553 // Inst{31} = Sbit;
554 // Inst{30-25} = Mid6;
555 // Inst{11-8} = Lo4;
556 // Inst{7} = Hi1;
557 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
558 return Value;
559 }
560 case RISCV::fixup_riscv_call:
561 case RISCV::fixup_riscv_call_plt: {
562 // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
563 // we need to add 0x800ULL before extract upper bits to reflect the
564 // effect of the sign extension.
565 uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
566 uint64_t LowerImm = Value & 0xfffULL;
567 return UpperImm | ((LowerImm << 20) << 32);
568 }
569 case RISCV::fixup_riscv_rvc_jump: {
570 if (!isInt<12>(x: Value))
571 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
572 // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
573 unsigned Bit11 = (Value >> 11) & 0x1;
574 unsigned Bit4 = (Value >> 4) & 0x1;
575 unsigned Bit9_8 = (Value >> 8) & 0x3;
576 unsigned Bit10 = (Value >> 10) & 0x1;
577 unsigned Bit6 = (Value >> 6) & 0x1;
578 unsigned Bit7 = (Value >> 7) & 0x1;
579 unsigned Bit3_1 = (Value >> 1) & 0x7;
580 unsigned Bit5 = (Value >> 5) & 0x1;
581 Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
582 (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
583 return Value;
584 }
585 case RISCV::fixup_riscv_rvc_branch: {
586 if (!isInt<9>(x: Value))
587 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
588 // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
589 unsigned Bit8 = (Value >> 8) & 0x1;
590 unsigned Bit7_6 = (Value >> 6) & 0x3;
591 unsigned Bit5 = (Value >> 5) & 0x1;
592 unsigned Bit4_3 = (Value >> 3) & 0x3;
593 unsigned Bit2_1 = (Value >> 1) & 0x3;
594 Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
595 (Bit5 << 2);
596 return Value;
597 }
598 case RISCV::fixup_riscv_rvc_imm: {
599 if (!isInt<6>(x: Value))
600 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
601 unsigned Bit5 = (Value >> 5) & 0x1;
602 unsigned Bit4_0 = Value & 0x1f;
603 Value = (Bit5 << 12) | (Bit4_0 << 2);
604 return Value;
605 }
606 case RISCV::fixup_riscv_qc_e_32: {
607 if (!isInt<32>(x: Value))
608 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
609 return Value & 0xffffffffu;
610 }
611 case RISCV::fixup_riscv_qc_abs20_u: {
612 if (!isInt<20>(x: Value))
613 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
614 unsigned Bit19 = (Value >> 19) & 0x1;
615 unsigned Bit14_0 = Value & 0x7fff;
616 unsigned Bit18_15 = (Value >> 15) & 0xf;
617 Value = (Bit19 << 31) | (Bit14_0 << 16) | (Bit18_15 << 12);
618 return Value;
619 }
620 case RISCV::fixup_riscv_qc_e_call_plt: {
621 if (!isInt<32>(x: Value))
622 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
623 if (Value & 0x1)
624 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
625 uint64_t Bit31_16 = (Value >> 16) & 0xffff;
626 uint64_t Bit12 = (Value >> 12) & 0x1;
627 uint64_t Bit10_5 = (Value >> 5) & 0x3f;
628 uint64_t Bit15_13 = (Value >> 13) & 0x7;
629 uint64_t Bit4_1 = (Value >> 1) & 0xf;
630 uint64_t Bit11 = (Value >> 11) & 0x1;
631 Value = (Bit31_16 << 32ull) | (Bit12 << 31) | (Bit10_5 << 25) |
632 (Bit15_13 << 17) | (Bit4_1 << 8) | (Bit11 << 7);
633 return Value;
634 }
635 case RISCV::fixup_riscv_nds_branch_10: {
636 if (!isInt<11>(x: Value))
637 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
638 if (Value & 0x1)
639 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
640 // Need to extract imm[10], imm[9:5], imm[4:1] from the 11-bit Value.
641 unsigned Sbit = (Value >> 10) & 0x1;
642 unsigned Hi5 = (Value >> 5) & 0x1f;
643 unsigned Lo4 = (Value >> 1) & 0xf;
644 // Inst{31} = Sbit;
645 // Inst{29-25} = Hi5;
646 // Inst{11-8} = Lo4;
647 Value = (Sbit << 31) | (Hi5 << 25) | (Lo4 << 8);
648 return Value;
649 }
650 }
651}
652
653bool RISCVAsmBackend::isPCRelFixupResolved(const MCSymbol *SymA,
654 const MCFragment &F) {
655 // If the section does not contain linker-relaxable fragments, PC-relative
656 // fixups can be resolved.
657 if (!F.getParent()->isLinkerRelaxable())
658 return true;
659
660 // Otherwise, check if the offset between the symbol and fragment is fully
661 // resolved, unaffected by linker-relaxable fragments (e.g. instructions or
662 // offset-affected FT_Align fragments). Complements the generic
663 // isSymbolRefDifferenceFullyResolvedImpl.
664 if (!PCRelTemp)
665 PCRelTemp = getContext().createTempSymbol();
666 PCRelTemp->setFragment(const_cast<MCFragment *>(&F));
667 MCValue Res;
668 MCExpr::evaluateSymbolicAdd(Asm, false, MCValue::get(SymA),
669 MCValue::get(SymA: nullptr, SymB: PCRelTemp), Res);
670 return !Res.getSubSym();
671}
672
673// Get the corresponding PC-relative HI fixup that a S_PCREL_LO points to, and
674// optionally the fragment containing it.
675//
676// \returns nullptr if this isn't a S_PCREL_LO pointing to a known PC-relative
677// HI fixup.
678const MCFixup *getPCRelHiFixup(const MCSpecifierExpr &Expr,
679 const MCFragment **DFOut) {
680 MCValue AUIPCLoc;
681 if (!Expr.getSubExpr()->evaluateAsRelocatable(Res&: AUIPCLoc, Asm: nullptr))
682 return nullptr;
683
684 const MCSymbol *AUIPCSymbol = AUIPCLoc.getAddSym();
685 if (!AUIPCSymbol)
686 return nullptr;
687 const auto *DF = AUIPCSymbol->getFragment();
688 if (!DF)
689 return nullptr;
690
691 uint64_t Offset = AUIPCSymbol->getOffset();
692 if (DF->getContents().size() == Offset) {
693 DF = DF->getNext();
694 if (!DF)
695 return nullptr;
696 Offset = 0;
697 }
698
699 for (const MCFixup &F : DF->getFixups()) {
700 if (F.getOffset() != Offset)
701 continue;
702 auto Kind = F.getKind();
703 if (!mc::isRelocation(FixupKind: F.getKind())) {
704 if (Kind == RISCV::fixup_riscv_pcrel_hi20) {
705 *DFOut = DF;
706 return &F;
707 }
708 break;
709 }
710 switch (Kind) {
711 case ELF::R_RISCV_GOT_HI20:
712 case ELF::R_RISCV_TLS_GOT_HI20:
713 case ELF::R_RISCV_TLS_GD_HI20:
714 case ELF::R_RISCV_TLSDESC_HI20:
715 *DFOut = DF;
716 return &F;
717 }
718 }
719
720 return nullptr;
721}
722
723std::optional<bool> RISCVAsmBackend::evaluateFixup(const MCFragment &,
724 MCFixup &Fixup,
725 MCValue &Target,
726 uint64_t &Value) {
727 const MCFixup *AUIPCFixup;
728 const MCFragment *AUIPCDF;
729 MCValue AUIPCTarget;
730 switch (Fixup.getKind()) {
731 default:
732 // Use default handling for `Value` and `IsResolved`.
733 return {};
734 case RISCV::fixup_riscv_pcrel_lo12_i:
735 case RISCV::fixup_riscv_pcrel_lo12_s: {
736 AUIPCFixup =
737 getPCRelHiFixup(Expr: cast<MCSpecifierExpr>(Val: *Fixup.getValue()), DFOut: &AUIPCDF);
738 if (!AUIPCFixup) {
739 getContext().reportError(L: Fixup.getLoc(),
740 Msg: "could not find corresponding %pcrel_hi");
741 return true;
742 }
743
744 // MCAssembler::evaluateFixup will emit an error for this case when it sees
745 // the %pcrel_hi, so don't duplicate it when also seeing the %pcrel_lo.
746 const MCExpr *AUIPCExpr = AUIPCFixup->getValue();
747 if (!AUIPCExpr->evaluateAsRelocatable(Res&: AUIPCTarget, Asm))
748 return true;
749 break;
750 }
751 }
752
753 if (!AUIPCTarget.getAddSym())
754 return false;
755
756 auto &SA = static_cast<const MCSymbolELF &>(*AUIPCTarget.getAddSym());
757 if (SA.isUndefined())
758 return false;
759
760 bool IsResolved = &SA.getSection() == AUIPCDF->getParent() &&
761 SA.getBinding() == ELF::STB_LOCAL &&
762 SA.getType() != ELF::STT_GNU_IFUNC;
763 if (!IsResolved)
764 return false;
765
766 Value = Asm->getSymbolOffset(S: SA) + AUIPCTarget.getConstant();
767 Value -= Asm->getFragmentOffset(F: *AUIPCDF) + AUIPCFixup->getOffset();
768
769 return AUIPCFixup->getKind() == RISCV::fixup_riscv_pcrel_hi20 &&
770 isPCRelFixupResolved(SymA: AUIPCTarget.getAddSym(), F: *AUIPCDF);
771}
772
773void RISCVAsmBackend::maybeAddVendorReloc(const MCFragment &F,
774 const MCFixup &Fixup) {
775 StringRef VendorIdentifier;
776 switch (Fixup.getKind()) {
777 default:
778 // No Vendor Relocation Required.
779 return;
780 case RISCV::fixup_riscv_qc_e_branch:
781 case RISCV::fixup_riscv_qc_abs20_u:
782 case RISCV::fixup_riscv_qc_e_32:
783 case RISCV::fixup_riscv_qc_e_call_plt:
784 VendorIdentifier = "QUALCOMM";
785 break;
786 case RISCV::fixup_riscv_nds_branch_10:
787 VendorIdentifier = "ANDES";
788 break;
789 }
790
791 // Create a local symbol for the vendor relocation to reference. It's fine if
792 // the symbol has the same name as an existing symbol.
793 MCContext &Ctx = Asm->getContext();
794 MCSymbol *VendorSymbol = Ctx.createLocalSymbol(Name: VendorIdentifier);
795 auto [It, Inserted] =
796 VendorSymbols.try_emplace(Key: VendorIdentifier, Args&: VendorSymbol);
797
798 if (Inserted) {
799 // Setup the just-created symbol
800 VendorSymbol->setVariableValue(MCConstantExpr::create(Value: 0, Ctx));
801 Asm->registerSymbol(Symbol: *VendorSymbol);
802 } else {
803 // Fetch the existing symbol
804 VendorSymbol = It->getValue();
805 }
806
807 MCFixup VendorFixup =
808 MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: ELF::R_RISCV_VENDOR);
809 // Explicitly create MCValue rather than using an MCExpr and evaluating it so
810 // that the absolute vendor symbol is not evaluated to constant 0.
811 MCValue VendorTarget = MCValue::get(SymA: VendorSymbol);
812 uint64_t VendorValue;
813 Asm->getWriter().recordRelocation(F, Fixup: VendorFixup, Target: VendorTarget, FixedValue&: VendorValue);
814}
815
816static bool relaxableFixupNeedsRelocation(const MCFixupKind Kind) {
817 // Some Fixups are marked as LinkerRelaxable by
818 // `RISCVMCCodeEmitter::getImmOpValue` only because they may be
819 // (assembly-)relaxed into a linker-relaxable instruction. This function
820 // should return `false` for those fixups so they do not get a `R_RISCV_RELAX`
821 // relocation emitted in addition to the relocation.
822 switch (Kind) {
823 default:
824 break;
825 case RISCV::fixup_riscv_rvc_jump:
826 case RISCV::fixup_riscv_branch:
827 case RISCV::fixup_riscv_rvc_branch:
828 case RISCV::fixup_riscv_qc_e_branch:
829 case RISCV::fixup_riscv_rvc_imm:
830 return false;
831 }
832 return true;
833}
834
835bool RISCVAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
836 const MCValue &Target, uint64_t &FixedValue,
837 bool IsResolved) {
838 uint64_t FixedValueA, FixedValueB;
839 if (Target.getSubSym()) {
840 assert(Target.getSpecifier() == 0 &&
841 "relocatable SymA-SymB cannot have relocation specifier");
842 unsigned TA = 0, TB = 0;
843 switch (Fixup.getKind()) {
844 case llvm::FK_Data_1:
845 TA = ELF::R_RISCV_ADD8;
846 TB = ELF::R_RISCV_SUB8;
847 break;
848 case llvm::FK_Data_2:
849 TA = ELF::R_RISCV_ADD16;
850 TB = ELF::R_RISCV_SUB16;
851 break;
852 case llvm::FK_Data_4:
853 TA = ELF::R_RISCV_ADD32;
854 TB = ELF::R_RISCV_SUB32;
855 break;
856 case llvm::FK_Data_8:
857 TA = ELF::R_RISCV_ADD64;
858 TB = ELF::R_RISCV_SUB64;
859 break;
860 case llvm::FK_Data_leb128:
861 TA = ELF::R_RISCV_SET_ULEB128;
862 TB = ELF::R_RISCV_SUB_ULEB128;
863 break;
864 default:
865 llvm_unreachable("unsupported fixup size");
866 }
867 MCValue A = MCValue::get(SymA: Target.getAddSym(), SymB: nullptr, Val: Target.getConstant());
868 MCValue B = MCValue::get(SymA: Target.getSubSym());
869 auto FA = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: TA);
870 auto FB = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: TB);
871 Asm->getWriter().recordRelocation(F, Fixup: FA, Target: A, FixedValue&: FixedValueA);
872 Asm->getWriter().recordRelocation(F, Fixup: FB, Target: B, FixedValue&: FixedValueB);
873 FixedValue = FixedValueA - FixedValueB;
874 return false;
875 }
876
877 // If linker relaxation is enabled and supported by the current fixup, then we
878 // always want to generate a relocation.
879 bool NeedsRelax = Fixup.isLinkerRelaxable() &&
880 relaxableFixupNeedsRelocation(Kind: Fixup.getKind());
881 if (NeedsRelax)
882 IsResolved = false;
883
884 if (IsResolved && Fixup.isPCRel())
885 IsResolved = isPCRelFixupResolved(SymA: Target.getAddSym(), F);
886
887 if (!IsResolved) {
888 // Some Fixups require a VENDOR relocation, record it (directly) before we
889 // add the relocation.
890 maybeAddVendorReloc(F, Fixup);
891
892 Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
893
894 if (NeedsRelax) {
895 // Some Fixups get a RELAX relocation, record it (directly) after we add
896 // the relocation.
897 MCFixup RelaxFixup =
898 MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: ELF::R_RISCV_RELAX);
899 MCValue RelaxTarget = MCValue::get(SymA: nullptr);
900 uint64_t RelaxValue;
901 Asm->getWriter().recordRelocation(F, Fixup: RelaxFixup, Target: RelaxTarget, FixedValue&: RelaxValue);
902 }
903 }
904
905 return false;
906}
907
908// Data fixups should be swapped for big endian cores.
909// Instruction fixups should not be swapped as RISC-V instructions
910// are always little-endian.
911static bool isDataFixup(unsigned Kind) {
912 switch (Kind) {
913 default:
914 return false;
915
916 case FK_Data_1:
917 case FK_Data_2:
918 case FK_Data_4:
919 case FK_Data_8:
920 return true;
921 }
922}
923
924void RISCVAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
925 const MCValue &Target, uint8_t *Data,
926 uint64_t Value, bool IsResolved) {
927 IsResolved = addReloc(F, Fixup, Target, FixedValue&: Value, IsResolved);
928 MCFixupKind Kind = Fixup.getKind();
929 if (mc::isRelocation(FixupKind: Kind))
930 return;
931 MCContext &Ctx = getContext();
932 MCFixupKindInfo Info = getFixupKindInfo(Kind);
933 if (!Value)
934 return; // Doesn't change encoding.
935 // Apply any target-specific value adjustments.
936 Value = adjustFixupValue(Fixup, Value, Ctx);
937
938 // Shift the value into position.
939 Value <<= Info.TargetOffset;
940
941 unsigned NumBytes = alignTo(Value: Info.TargetSize + Info.TargetOffset, Align: 8) / 8;
942 assert(Fixup.getOffset() + NumBytes <= F.getSize() &&
943 "Invalid fixup offset!");
944
945 // For each byte of the fragment that the fixup touches, mask in the
946 // bits from the fixup value.
947 // For big endian cores, data fixup should be swapped.
948 bool SwapValue = Endian == llvm::endianness::big && isDataFixup(Kind);
949 for (unsigned i = 0; i != NumBytes; ++i) {
950 unsigned Idx = SwapValue ? (NumBytes - 1 - i) : i;
951 Data[Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
952 }
953}
954
955std::unique_ptr<MCObjectTargetWriter>
956RISCVAsmBackend::createObjectTargetWriter() const {
957 return createRISCVELFObjectWriter(OSABI, Is64Bit);
958}
959
960class DarwinRISCVAsmBackend : public RISCVAsmBackend {
961public:
962 DarwinRISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
963 bool IsLittleEndian, const MCTargetOptions &Options)
964 : RISCVAsmBackend(STI, OSABI, Is64Bit, IsLittleEndian, Options) {}
965
966 std::unique_ptr<MCObjectTargetWriter>
967 createObjectTargetWriter() const override {
968 const Triple &TT = STI.getTargetTriple();
969 uint32_t CPUType = cantFail(ValOrErr: MachO::getCPUType(T: TT));
970 uint32_t CPUSubType = cantFail(ValOrErr: MachO::getCPUSubType(T: TT));
971 return createRISCVMachObjectWriter(CPUType, CPUSubtype: CPUSubType);
972 }
973
974 bool addReloc(const MCFragment &, const MCFixup &, const MCValue &,
975 uint64_t &FixedValue, bool IsResolved) override;
976
977 std::optional<bool> evaluateFixup(const MCFragment &F, MCFixup &Fixup,
978 MCValue &Target, uint64_t &Value) override {
979 const MCFixup *AUIPCFixup;
980 const MCFragment *AUIPCDF;
981 const MCFixupKind FKind = Fixup.getKind();
982 if ((FKind == RISCV::fixup_riscv_pcrel_lo12_i) ||
983 (FKind == RISCV::fixup_riscv_pcrel_lo12_s)) {
984 AUIPCFixup =
985 getPCRelHiFixup(Expr: cast<MCSpecifierExpr>(Val: *Fixup.getValue()), DFOut: &AUIPCDF);
986 if (!AUIPCFixup) {
987 getContext().reportError(L: Fixup.getLoc(),
988 Msg: "could not find corresponding %pcrel_hi");
989 return true;
990 }
991
992 return false;
993 }
994
995 // Use default handling for all other cases.
996 return {};
997 }
998};
999
1000MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
1001 const MCSubtargetInfo &STI,
1002 const MCRegisterInfo &MRI,
1003 const MCTargetOptions &Options) {
1004 const Triple &TT = STI.getTargetTriple();
1005 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType: TT.getOS());
1006 if (TT.isOSBinFormatMachO())
1007 return new DarwinRISCVAsmBackend(STI, OSABI, TT.isArch64Bit(),
1008 TT.isLittleEndian(), Options);
1009
1010 return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), TT.isLittleEndian(),
1011 Options);
1012}
1013
1014bool DarwinRISCVAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
1015 const MCValue &Target,
1016 uint64_t &FixedValue, bool IsResolved) {
1017 if (!IsResolved)
1018 Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
1019 return IsResolved;
1020}
1021