1//===-- RISCVAsmBackend.cpp - RISC-V Assembler Backend --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCVAsmBackend.h"
10#include "RISCVFixupKinds.h"
11#include "llvm/ADT/APInt.h"
12#include "llvm/MC/MCAsmInfo.h"
13#include "llvm/MC/MCAssembler.h"
14#include "llvm/MC/MCContext.h"
15#include "llvm/MC/MCELFObjectWriter.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCMachObjectWriter.h"
18#include "llvm/MC/MCObjectWriter.h"
19#include "llvm/MC/MCSymbol.h"
20#include "llvm/MC/MCValue.h"
21#include "llvm/Support/EndianStream.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/LEB128.h"
24#include "llvm/Support/raw_ostream.h"
25
26using namespace llvm;
27
28RISCVAsmBackend::RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI,
29 bool Is64Bit, bool IsLittleEndian,
30 const MCTargetOptions &Options)
31 : MCAsmBackend(IsLittleEndian ? llvm::endianness::little
32 : llvm::endianness::big),
33 CLOpts(RISCVMCOptions::Global), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
34 TargetOptions(Options) {
35 RISCVFeatures::validate(TT: STI.getTargetTriple(), FeatureBits: STI.getFeatureBits());
36}
37
38std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
39 if (STI.getTargetTriple().isOSBinFormatELF()) {
40 unsigned Type;
41 Type = llvm::StringSwitch<unsigned>(Name)
42#define ELF_RELOC(NAME, ID) .Case(#NAME, ID)
43#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
44#undef ELF_RELOC
45#define ELF_RISCV_NONSTANDARD_RELOC(_VENDOR, NAME, ID) .Case(#NAME, ID)
46#include "llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def"
47#undef ELF_RISCV_NONSTANDARD_RELOC
48 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_RISCV_NONE)
49 .Case(S: "BFD_RELOC_32", Value: ELF::R_RISCV_32)
50 .Case(S: "BFD_RELOC_64", Value: ELF::R_RISCV_64)
51 .Default(Value: -1u);
52 if (Type != -1u)
53 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
54 }
55 return std::nullopt;
56}
57
58MCFixupKindInfo RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
59 const static MCFixupKindInfo Infos[] = {
60 // This table *must* be in the order that the fixup_* kinds are defined in
61 // RISCVFixupKinds.h.
62 //
63 // name offset bits flags
64 {.Name: "fixup_riscv_hi20", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
65 {.Name: "fixup_riscv_lo12_i", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
66 {.Name: "fixup_riscv_12_i", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
67 {.Name: "fixup_riscv_lo12_s", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
68 {.Name: "fixup_riscv_pcrel_hi20", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
69 {.Name: "fixup_riscv_pcrel_lo12_i", .TargetOffset: 20, .TargetSize: 12, .Flags: 0},
70 {.Name: "fixup_riscv_pcrel_lo12_s", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
71 {.Name: "fixup_riscv_jal", .TargetOffset: 12, .TargetSize: 20, .Flags: 0},
72 {.Name: "fixup_riscv_branch", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
73 {.Name: "fixup_riscv_rvc_jump", .TargetOffset: 2, .TargetSize: 11, .Flags: 0},
74 {.Name: "fixup_riscv_rvc_branch", .TargetOffset: 0, .TargetSize: 16, .Flags: 0},
75 {.Name: "fixup_riscv_rvc_imm", .TargetOffset: 0, .TargetSize: 16, .Flags: 0},
76 {.Name: "fixup_riscv_call", .TargetOffset: 0, .TargetSize: 64, .Flags: 0},
77 {.Name: "fixup_riscv_call_plt", .TargetOffset: 0, .TargetSize: 64, .Flags: 0},
78
79 // Qualcomm fixups
80 {.Name: "fixup_riscv_qc_e_branch", .TargetOffset: 0, .TargetSize: 48, .Flags: 0},
81 {.Name: "fixup_riscv_qc_e_32", .TargetOffset: 16, .TargetSize: 32, .Flags: 0},
82 {.Name: "fixup_riscv_qc_abs20_u", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
83 {.Name: "fixup_riscv_qc_e_call_plt", .TargetOffset: 0, .TargetSize: 48, .Flags: 0},
84 {.Name: "fixup_qc_access_16", .TargetOffset: 0, .TargetSize: 0, .Flags: 0},
85 {.Name: "fixup_qc_access_32", .TargetOffset: 0, .TargetSize: 0, .Flags: 0},
86
87 // Andes fixups
88 {.Name: "fixup_riscv_nds_branch_10", .TargetOffset: 0, .TargetSize: 32, .Flags: 0},
89 };
90 static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
91 "Not all fixup kinds added to Infos array");
92
93 // Fixup kinds from raw relocation types and .reloc directives force
94 // relocations and do not use these fields.
95 if (mc::isRelocation(FixupKind: Kind))
96 return {};
97
98 if (Kind < FirstTargetFixupKind)
99 return MCAsmBackend::getFixupKindInfo(Kind);
100
101 assert(unsigned(Kind - FirstTargetFixupKind) < RISCV::NumTargetFixupKinds &&
102 "Invalid kind!");
103 return Infos[Kind - FirstTargetFixupKind];
104}
105
106bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFragment &,
107 const MCFixup &Fixup,
108 const MCValue &,
109 uint64_t Value,
110 bool Resolved) const {
111 int64_t Offset = int64_t(Value);
112 auto Kind = Fixup.getKind();
113
114 // Return true if the symbol is unresolved.
115 if (!Resolved)
116 return true;
117
118 switch (Kind) {
119 default:
120 return false;
121 case RISCV::fixup_riscv_rvc_branch:
122 // For compressed branch instructions the immediate must be
123 // in the range [-256, 254].
124 return Offset > 254 || Offset < -256;
125 case RISCV::fixup_riscv_rvc_jump:
126 // For compressed jump instructions the immediate must be
127 // in the range [-2048, 2046].
128 return Offset > 2046 || Offset < -2048;
129 case RISCV::fixup_riscv_branch:
130 case RISCV::fixup_riscv_qc_e_branch:
131 // For conditional branch instructions the immediate must be
132 // in the range [-4096, 4094].
133 return Offset > 4094 || Offset < -4096;
134 case RISCV::fixup_riscv_jal:
135 // For jump instructions the immediate must be in the range
136 // [-1048576, 1048574]
137 return Offset > 1048574 || Offset < -1048576;
138 case RISCV::fixup_riscv_rvc_imm:
139 // This fixup can never be emitted as a relocation, so always needs to be
140 // relaxed.
141 return true;
142 }
143}
144
145// Given a compressed control flow instruction this function returns
146// the expanded instruction, or the original instruction code if no
147// expansion is available.
148static unsigned getRelaxedOpcode(unsigned Opcode, ArrayRef<MCOperand> Operands,
149 const MCSubtargetInfo &STI) {
150 switch (Opcode) {
151 case RISCV::C_BEQZ:
152 return RISCV::BEQ;
153 case RISCV::C_BNEZ:
154 return RISCV::BNE;
155 case RISCV::C_J:
156 case RISCV::C_JAL: // fall through.
157 // This only relaxes one "step" - i.e. from C.J to JAL, not from C.J to
158 // QC.E.J, because we can always relax again if needed.
159 return RISCV::JAL;
160 case RISCV::C_LI:
161 if (!STI.hasFeature(Feature: RISCV::FeatureVendorXqcili))
162 break;
163 // We only need this because `QC.E.LI` can be compressed into a `C.LI`. This
164 // happens because the `simm6` MCOperandPredicate accepts bare symbols, and
165 // `QC.E.LI` is the only instruction that accepts bare symbols at parse-time
166 // and compresses to `C.LI`. `C.LI` does not itself accept bare symbols at
167 // parse time.
168 //
169 // If we have a bare symbol, we need to turn this back to a `QC.E.LI`, as we
170 // have no way to emit a relocation on a `C.LI` instruction.
171 return RISCV::QC_E_LI;
172 case RISCV::JAL: {
173 // We can only relax JAL if we have Xqcilb
174 if (!STI.hasFeature(Feature: RISCV::FeatureVendorXqcilb))
175 break;
176
177 // And only if it is using X0 or X1 for rd.
178 MCRegister Reg = Operands[0].getReg();
179 if (Reg == RISCV::X0)
180 return RISCV::QC_E_J;
181 if (Reg == RISCV::X1)
182 return RISCV::QC_E_JAL;
183
184 break;
185 }
186 case RISCV::BEQ:
187 return RISCV::PseudoLongBEQ;
188 case RISCV::BNE:
189 return RISCV::PseudoLongBNE;
190 case RISCV::BEQI:
191 return RISCV::PseudoLongBEQI;
192 case RISCV::BNEI:
193 return RISCV::PseudoLongBNEI;
194 case RISCV::BLT:
195 return RISCV::PseudoLongBLT;
196 case RISCV::BGE:
197 return RISCV::PseudoLongBGE;
198 case RISCV::BLTU:
199 return RISCV::PseudoLongBLTU;
200 case RISCV::BGEU:
201 return RISCV::PseudoLongBGEU;
202 case RISCV::QC_BEQI:
203 return RISCV::PseudoLongQC_BEQI;
204 case RISCV::QC_BNEI:
205 return RISCV::PseudoLongQC_BNEI;
206 case RISCV::QC_BLTI:
207 return RISCV::PseudoLongQC_BLTI;
208 case RISCV::QC_BGEI:
209 return RISCV::PseudoLongQC_BGEI;
210 case RISCV::QC_BLTUI:
211 return RISCV::PseudoLongQC_BLTUI;
212 case RISCV::QC_BGEUI:
213 return RISCV::PseudoLongQC_BGEUI;
214 case RISCV::QC_E_BEQI:
215 return RISCV::PseudoLongQC_E_BEQI;
216 case RISCV::QC_E_BNEI:
217 return RISCV::PseudoLongQC_E_BNEI;
218 case RISCV::QC_E_BLTI:
219 return RISCV::PseudoLongQC_E_BLTI;
220 case RISCV::QC_E_BGEI:
221 return RISCV::PseudoLongQC_E_BGEI;
222 case RISCV::QC_E_BLTUI:
223 return RISCV::PseudoLongQC_E_BLTUI;
224 case RISCV::QC_E_BGEUI:
225 return RISCV::PseudoLongQC_E_BGEUI;
226 case RISCV::CV_BEQIMM:
227 return RISCV::PseudoLongCV_BEQIMM;
228 case RISCV::CV_BNEIMM:
229 return RISCV::PseudoLongCV_BNEIMM;
230 }
231
232 // Returning the original opcode means we cannot relax the instruction.
233 return Opcode;
234}
235
236void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
237 const MCSubtargetInfo &STI) const {
238 if (STI.hasFeature(Feature: RISCV::FeatureExactAssembly))
239 return;
240
241 MCInst Res;
242 switch (Inst.getOpcode()) {
243 default:
244 llvm_unreachable("Opcode not expected!");
245 case RISCV::C_BEQZ:
246 case RISCV::C_BNEZ:
247 case RISCV::C_J:
248 case RISCV::C_JAL: {
249 [[maybe_unused]] bool Success = RISCVRVC::uncompress(OutInst&: Res, MI: Inst, STI);
250 assert(Success && "Can't uncompress instruction");
251 assert(Res.getOpcode() ==
252 getRelaxedOpcode(Inst.getOpcode(), Inst.getOperands(), STI) &&
253 "Branch Relaxation Error");
254 break;
255 }
256 case RISCV::JAL: {
257 // This has to be written manually because the QC.E.J -> JAL is
258 // compression-only, so that it is not used when printing disassembly.
259 assert(STI.hasFeature(RISCV::FeatureVendorXqcilb) &&
260 "JAL is only relaxable with Xqcilb");
261 assert((Inst.getOperand(0).getReg() == RISCV::X0 ||
262 Inst.getOperand(0).getReg() == RISCV::X1) &&
263 "JAL only relaxable with rd=x0 or rd=x1");
264 Res.setOpcode(getRelaxedOpcode(Opcode: Inst.getOpcode(), Operands: Inst.getOperands(), STI));
265 Res.addOperand(Op: Inst.getOperand(i: 1));
266 break;
267 }
268 case RISCV::C_LI: {
269 // This should only be hit when trying to relax a `C.LI` into a `QC.E.LI`
270 // because the `C.LI` has a bare symbol. We cannot use
271 // `RISCVRVC::uncompress` because it will use decompression patterns. The
272 // `QC.E.LI` compression pattern to `C.LI` is compression-only (because we
273 // don't want `c.li` ever printed as `qc.e.li`, which might be done if the
274 // pattern applied to decompression), but that doesn't help much becuase
275 // `C.LI` with a bare symbol will decompress to an `ADDI` anyway (because
276 // `simm12`'s MCOperandPredicate accepts a bare symbol and that pattern
277 // comes first), and we still cannot emit an `ADDI` with a bare symbol.
278 assert(STI.hasFeature(RISCV::FeatureVendorXqcili) &&
279 "C.LI is only relaxable with Xqcili");
280 Res.setOpcode(getRelaxedOpcode(Opcode: Inst.getOpcode(), Operands: Inst.getOperands(), STI));
281 Res.addOperand(Op: Inst.getOperand(i: 0));
282 Res.addOperand(Op: Inst.getOperand(i: 1));
283 break;
284 }
285 case RISCV::BEQ:
286 case RISCV::BNE:
287 case RISCV::BEQI:
288 case RISCV::BNEI:
289 case RISCV::BLT:
290 case RISCV::BGE:
291 case RISCV::BLTU:
292 case RISCV::BGEU:
293 case RISCV::QC_BEQI:
294 case RISCV::QC_BNEI:
295 case RISCV::QC_BLTI:
296 case RISCV::QC_BGEI:
297 case RISCV::QC_BLTUI:
298 case RISCV::QC_BGEUI:
299 case RISCV::QC_E_BEQI:
300 case RISCV::QC_E_BNEI:
301 case RISCV::QC_E_BLTI:
302 case RISCV::QC_E_BGEI:
303 case RISCV::QC_E_BLTUI:
304 case RISCV::QC_E_BGEUI:
305 case RISCV::CV_BEQIMM:
306 case RISCV::CV_BNEIMM:
307 Res.setOpcode(getRelaxedOpcode(Opcode: Inst.getOpcode(), Operands: Inst.getOperands(), STI));
308 Res.addOperand(Op: Inst.getOperand(i: 0));
309 Res.addOperand(Op: Inst.getOperand(i: 1));
310 Res.addOperand(Op: Inst.getOperand(i: 2));
311 break;
312 }
313 Inst = std::move(Res);
314}
315
316// Check if an R_RISCV_ALIGN relocation is needed for an alignment directive.
317// If conditions are met, compute the padding size and create a fixup encoding
318// the padding size in the addend.
319bool RISCVAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) {
320 // Alignments before the first linker-relaxable instruction have fixed sizes
321 // and do not require relocations. Alignments after a linker-relaxable
322 // instruction require a relocation, even if the STI specifies norelax.
323 //
324 // firstLinkerRelaxable is the layout order within the subsection, which may
325 // be smaller than the section's order. Therefore, alignments in a
326 // lower-numbered subsection may be unnecessarily treated as linker-relaxable.
327 auto *Sec = F.getParent();
328 if (F.getLayoutOrder() <= Sec->firstLinkerRelaxable())
329 return false;
330
331 // Use default handling unless the alignment is larger than the nop size.
332 const MCSubtargetInfo *STI = F.getSubtargetInfo();
333 unsigned MinNopLen =
334 CLOpts.align_rvc || STI->hasFeature(Feature: RISCV::FeatureStdExtZca) ? 2 : 4;
335 if (F.getAlignment() <= MinNopLen)
336 return false;
337
338 Size = F.getAlignment().value() - MinNopLen;
339 auto *Expr = MCConstantExpr::create(Value: Size, Ctx&: getContext());
340 MCFixup Fixup =
341 MCFixup::create(Offset: 0, Value: Expr, Kind: FirstLiteralRelocationKind + ELF::R_RISCV_ALIGN);
342 F.setVarFixups({Fixup});
343 F.setLinkerRelaxable();
344 return true;
345}
346
347bool RISCVAsmBackend::relaxDwarfLineAddr(MCFragment &F) const {
348 int64_t LineDelta = F.getDwarfLineDelta();
349 const MCExpr &AddrDelta = F.getDwarfAddrDelta();
350 int64_t Value;
351 // If the label difference can be resolved, use the default handling, which
352 // utilizes a shorter special opcode.
353 if (AddrDelta.evaluateAsAbsolute(Res&: Value, Asm: *Asm))
354 return false;
355 [[maybe_unused]] bool IsAbsolute =
356 AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm: *Asm);
357 assert(IsAbsolute && "CFA with invalid expression");
358
359 SmallVector<char> Data;
360 raw_svector_ostream OS(Data);
361
362 // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
363 if (LineDelta != INT64_MAX) {
364 OS << uint8_t(dwarf::DW_LNS_advance_line);
365 encodeSLEB128(Value: LineDelta, OS);
366 }
367
368 // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
369 // takes a single unsigned half (unencoded) operand. The maximum encodable
370 // value is therefore 65535. Set a conservative upper bound for relaxation.
371 unsigned PCBytes;
372 if (Value > 60000) {
373 PCBytes = getContext().getAsmInfo().getCodePointerSize();
374 OS << uint8_t(dwarf::DW_LNS_extended_op) << uint8_t(PCBytes + 1)
375 << uint8_t(dwarf::DW_LNE_set_address);
376 OS.write_zeros(NumZeros: PCBytes);
377 } else {
378 PCBytes = 2;
379 OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
380 support::endian::write<uint16_t>(os&: OS, value: 0, endian: Endian);
381 }
382 auto Offset = OS.tell() - PCBytes;
383
384 if (LineDelta == INT64_MAX) {
385 OS << uint8_t(dwarf::DW_LNS_extended_op);
386 OS << uint8_t(1);
387 OS << uint8_t(dwarf::DW_LNE_end_sequence);
388 } else {
389 OS << uint8_t(dwarf::DW_LNS_copy);
390 }
391
392 F.setVarContents(Data);
393 F.setVarFixups({MCFixup::create(Offset, Value: &AddrDelta,
394 Kind: MCFixup::getDataKindForSize(Size: PCBytes))});
395 return true;
396}
397
398bool RISCVAsmBackend::relaxDwarfCFA(MCFragment &F) const {
399 const MCExpr &AddrDelta = F.getDwarfAddrDelta();
400 SmallVector<MCFixup, 2> Fixups;
401 int64_t Value;
402 if (AddrDelta.evaluateAsAbsolute(Res&: Value, Asm: *Asm))
403 return false;
404 [[maybe_unused]] bool IsAbsolute =
405 AddrDelta.evaluateKnownAbsolute(Res&: Value, Asm: *Asm);
406 assert(IsAbsolute && "CFA with invalid expression");
407
408 assert(getContext().getAsmInfo().getMinInstAlignment() == 1 &&
409 "expected 1-byte alignment");
410 if (Value == 0) {
411 F.clearVarContents();
412 F.clearVarFixups();
413 return true;
414 }
415
416 auto AddFixups = [&Fixups, &AddrDelta](unsigned Offset,
417 std::pair<unsigned, unsigned> Fixup) {
418 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(Val: AddrDelta);
419 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getLHS(), Kind: std::get<0>(in&: Fixup)));
420 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MBE.getRHS(), Kind: std::get<1>(in&: Fixup)));
421 };
422
423 SmallVector<char, 8> Data;
424 raw_svector_ostream OS(Data);
425 if (isUIntN(N: 6, x: Value)) {
426 OS << uint8_t(dwarf::DW_CFA_advance_loc);
427 AddFixups(0, {ELF::R_RISCV_SET6, ELF::R_RISCV_SUB6});
428 } else if (isUInt<8>(x: Value)) {
429 OS << uint8_t(dwarf::DW_CFA_advance_loc1);
430 support::endian::write<uint8_t>(os&: OS, value: 0, endian: Endian);
431 AddFixups(1, {ELF::R_RISCV_SET8, ELF::R_RISCV_SUB8});
432 } else if (isUInt<16>(x: Value)) {
433 OS << uint8_t(dwarf::DW_CFA_advance_loc2);
434 support::endian::write<uint16_t>(os&: OS, value: 0, endian: Endian);
435 AddFixups(1, {ELF::R_RISCV_SET16, ELF::R_RISCV_SUB16});
436 } else if (isUInt<32>(x: Value)) {
437 OS << uint8_t(dwarf::DW_CFA_advance_loc4);
438 support::endian::write<uint32_t>(os&: OS, value: 0, endian: Endian);
439 AddFixups(1, {ELF::R_RISCV_SET32, ELF::R_RISCV_SUB32});
440 } else {
441 llvm_unreachable("unsupported CFA encoding");
442 }
443 F.setVarContents(Data);
444 F.setVarFixups(Fixups);
445 return true;
446}
447
448std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(MCFragment &LF,
449 int64_t &Value) const {
450 if (LF.isLEBSigned())
451 return std::make_pair(x: false, y: false);
452 const MCExpr &Expr = LF.getLEBValue();
453 if (CLOpts.uleb128_reloc) {
454 LF.setVarFixups({MCFixup::create(Offset: 0, Value: &Expr, Kind: FK_Data_leb128)});
455 }
456 return std::make_pair(x: Expr.evaluateKnownAbsolute(Res&: Value, Asm: *Asm), y: false);
457}
458
459bool RISCVAsmBackend::mayNeedRelaxation(unsigned Opcode,
460 ArrayRef<MCOperand> Operands,
461 const MCSubtargetInfo &STI) const {
462 // This function has access to two STIs, the member of the AsmBackend, and the
463 // one passed as an argument. The latter is more specific, so we query it for
464 // specific features.
465 if (STI.hasFeature(Feature: RISCV::FeatureExactAssembly))
466 return false;
467
468 return getRelaxedOpcode(Opcode, Operands, STI) != Opcode;
469}
470
471bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
472 const MCSubtargetInfo *STI) const {
473 // We mostly follow binutils' convention here: align to even boundary with a
474 // 0-fill padding. We emit up to 1 2-byte nop, though we use c.nop if RVC is
475 // enabled or 0-fill otherwise. The remainder is now padded with 4-byte nops.
476
477 // Instructions always are at even addresses. We must be in a data area or
478 // be unaligned due to some other reason.
479 if (Count % 2) {
480 OS.write(Ptr: "\0", Size: 1);
481 Count -= 1;
482 }
483
484 // TODO: emit a mapping symbol right here
485
486 if (Count % 4 == 2) {
487 // The canonical nop with Zca is c.nop. For .balign 4, we generate a 2-byte
488 // c.nop even in a norvc region.
489 OS.write(Ptr: "\x01\0", Size: 2);
490 Count -= 2;
491 }
492
493 // The canonical nop on RISC-V is addi x0, x0, 0.
494 for (; Count >= 4; Count -= 4)
495 OS.write(Ptr: "\x13\0\0\0", Size: 4);
496
497 return true;
498}
499
500static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
501 MCContext &Ctx) {
502 switch (Fixup.getKind()) {
503 default:
504 llvm_unreachable("Unknown fixup kind!");
505 case FK_Data_1:
506 case FK_Data_2:
507 case FK_Data_4:
508 case FK_Data_8:
509 case FK_Data_leb128:
510 return Value;
511 case RISCV::fixup_riscv_lo12_i:
512 case RISCV::fixup_riscv_pcrel_lo12_i:
513 return Value & 0xfff;
514 case RISCV::fixup_riscv_12_i:
515 if (!isInt<12>(x: Value)) {
516 Ctx.reportError(L: Fixup.getLoc(),
517 Msg: "operand must be a constant 12-bit integer");
518 }
519 return Value & 0xfff;
520 case RISCV::fixup_riscv_lo12_s:
521 case RISCV::fixup_riscv_pcrel_lo12_s:
522 return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
523 case RISCV::fixup_riscv_hi20:
524 case RISCV::fixup_riscv_pcrel_hi20:
525 // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
526 return ((Value + 0x800) >> 12) & 0xfffff;
527 case RISCV::fixup_riscv_jal: {
528 if (!isInt<21>(x: Value))
529 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
530 if (Value & 0x1)
531 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
532 // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
533 unsigned Sbit = (Value >> 20) & 0x1;
534 unsigned Hi8 = (Value >> 12) & 0xff;
535 unsigned Mid1 = (Value >> 11) & 0x1;
536 unsigned Lo10 = (Value >> 1) & 0x3ff;
537 // Inst{31} = Sbit;
538 // Inst{30-21} = Lo10;
539 // Inst{20} = Mid1;
540 // Inst{19-12} = Hi8;
541 Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
542 return Value;
543 }
544 case RISCV::fixup_riscv_qc_e_branch:
545 case RISCV::fixup_riscv_branch: {
546 if (!isInt<13>(x: Value))
547 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
548 if (Value & 0x1)
549 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
550 // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
551 // Value.
552 unsigned Sbit = (Value >> 12) & 0x1;
553 unsigned Hi1 = (Value >> 11) & 0x1;
554 unsigned Mid6 = (Value >> 5) & 0x3f;
555 unsigned Lo4 = (Value >> 1) & 0xf;
556 // Inst{31} = Sbit;
557 // Inst{30-25} = Mid6;
558 // Inst{11-8} = Lo4;
559 // Inst{7} = Hi1;
560 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
561 return Value;
562 }
563 case RISCV::fixup_riscv_call:
564 case RISCV::fixup_riscv_call_plt: {
565 // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
566 // we need to add 0x800ULL before extract upper bits to reflect the
567 // effect of the sign extension.
568 uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
569 uint64_t LowerImm = Value & 0xfffULL;
570 return UpperImm | ((LowerImm << 20) << 32);
571 }
572 case RISCV::fixup_riscv_rvc_jump: {
573 if (!isInt<12>(x: Value))
574 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
575 // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
576 unsigned Bit11 = (Value >> 11) & 0x1;
577 unsigned Bit4 = (Value >> 4) & 0x1;
578 unsigned Bit9_8 = (Value >> 8) & 0x3;
579 unsigned Bit10 = (Value >> 10) & 0x1;
580 unsigned Bit6 = (Value >> 6) & 0x1;
581 unsigned Bit7 = (Value >> 7) & 0x1;
582 unsigned Bit3_1 = (Value >> 1) & 0x7;
583 unsigned Bit5 = (Value >> 5) & 0x1;
584 Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
585 (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
586 return Value;
587 }
588 case RISCV::fixup_riscv_rvc_branch: {
589 if (!isInt<9>(x: Value))
590 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
591 // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
592 unsigned Bit8 = (Value >> 8) & 0x1;
593 unsigned Bit7_6 = (Value >> 6) & 0x3;
594 unsigned Bit5 = (Value >> 5) & 0x1;
595 unsigned Bit4_3 = (Value >> 3) & 0x3;
596 unsigned Bit2_1 = (Value >> 1) & 0x3;
597 Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
598 (Bit5 << 2);
599 return Value;
600 }
601 case RISCV::fixup_riscv_rvc_imm: {
602 if (!isInt<6>(x: Value))
603 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
604 unsigned Bit5 = (Value >> 5) & 0x1;
605 unsigned Bit4_0 = Value & 0x1f;
606 Value = (Bit5 << 12) | (Bit4_0 << 2);
607 return Value;
608 }
609 case RISCV::fixup_riscv_qc_e_32: {
610 if (!isInt<32>(x: Value))
611 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
612 return Value & 0xffffffffu;
613 }
614 case RISCV::fixup_riscv_qc_abs20_u: {
615 if (!isInt<20>(x: Value))
616 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
617 unsigned Bit19 = (Value >> 19) & 0x1;
618 unsigned Bit14_0 = Value & 0x7fff;
619 unsigned Bit18_15 = (Value >> 15) & 0xf;
620 Value = (Bit19 << 31) | (Bit14_0 << 16) | (Bit18_15 << 12);
621 return Value;
622 }
623 case RISCV::fixup_riscv_qc_e_call_plt: {
624 if (!isInt<32>(x: Value))
625 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
626 if (Value & 0x1)
627 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
628 uint64_t Bit31_16 = (Value >> 16) & 0xffff;
629 uint64_t Bit12 = (Value >> 12) & 0x1;
630 uint64_t Bit10_5 = (Value >> 5) & 0x3f;
631 uint64_t Bit15_13 = (Value >> 13) & 0x7;
632 uint64_t Bit4_1 = (Value >> 1) & 0xf;
633 uint64_t Bit11 = (Value >> 11) & 0x1;
634 Value = (Bit31_16 << 32ull) | (Bit12 << 31) | (Bit10_5 << 25) |
635 (Bit15_13 << 17) | (Bit4_1 << 8) | (Bit11 << 7);
636 return Value;
637 }
638 case RISCV::fixup_qc_access_16:
639 case RISCV::fixup_qc_access_32:
640 return 0;
641 case RISCV::fixup_riscv_nds_branch_10: {
642 if (!isInt<11>(x: Value))
643 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value out of range");
644 if (Value & 0x1)
645 Ctx.reportError(L: Fixup.getLoc(), Msg: "fixup value must be 2-byte aligned");
646 // Need to extract imm[10], imm[9:5], imm[4:1] from the 11-bit Value.
647 unsigned Sbit = (Value >> 10) & 0x1;
648 unsigned Hi5 = (Value >> 5) & 0x1f;
649 unsigned Lo4 = (Value >> 1) & 0xf;
650 // Inst{31} = Sbit;
651 // Inst{29-25} = Hi5;
652 // Inst{11-8} = Lo4;
653 Value = (Sbit << 31) | (Hi5 << 25) | (Lo4 << 8);
654 return Value;
655 }
656 }
657}
658
659bool RISCVAsmBackend::isPCRelFixupResolved(const MCSymbol *SymA,
660 const MCFragment &F) {
661 // If the section does not contain linker-relaxable fragments, PC-relative
662 // fixups can be resolved.
663 if (!F.getParent()->isLinkerRelaxable())
664 return true;
665
666 // Otherwise, check if the offset between the symbol and fragment is fully
667 // resolved, unaffected by linker-relaxable fragments (e.g. instructions or
668 // offset-affected FT_Align fragments). Complements the generic
669 // isSymbolRefDifferenceFullyResolvedImpl.
670 if (!PCRelTemp)
671 PCRelTemp = getContext().createTempSymbol();
672 PCRelTemp->setFragment(const_cast<MCFragment *>(&F));
673 MCValue Res;
674 MCExpr::evaluateSymbolicAdd(Asm, false, MCValue::get(SymA),
675 MCValue::get(SymA: nullptr, SymB: PCRelTemp), Res);
676 return !Res.getSubSym();
677}
678
679// Get the corresponding PC-relative HI fixup that a S_PCREL_LO points to, and
680// optionally the fragment containing it.
681//
682// \returns nullptr if this isn't a S_PCREL_LO pointing to a known PC-relative
683// HI fixup.
684const MCFixup *getPCRelHiFixup(const MCSpecifierExpr &Expr,
685 const MCFragment **DFOut) {
686 MCValue AUIPCLoc;
687 if (!Expr.getSubExpr()->evaluateAsRelocatable(Res&: AUIPCLoc, Asm: nullptr))
688 return nullptr;
689
690 const MCSymbol *AUIPCSymbol = AUIPCLoc.getAddSym();
691 if (!AUIPCSymbol)
692 return nullptr;
693 const auto *DF = AUIPCSymbol->getFragment();
694 if (!DF)
695 return nullptr;
696
697 uint64_t Offset = AUIPCSymbol->getOffset();
698 if (DF->getContents().size() == Offset) {
699 DF = DF->getNext();
700 if (!DF)
701 return nullptr;
702 Offset = 0;
703 }
704
705 for (const MCFixup &F : DF->getFixups()) {
706 if (F.getOffset() != Offset)
707 continue;
708 auto Kind = F.getKind();
709 if (!mc::isRelocation(FixupKind: F.getKind())) {
710 if (Kind == RISCV::fixup_riscv_pcrel_hi20) {
711 *DFOut = DF;
712 return &F;
713 }
714 break;
715 }
716 switch (Kind) {
717 case ELF::R_RISCV_GOT_HI20:
718 case ELF::R_RISCV_TLS_GOT_HI20:
719 case ELF::R_RISCV_TLS_GD_HI20:
720 case ELF::R_RISCV_TLSDESC_HI20:
721 *DFOut = DF;
722 return &F;
723 }
724 }
725
726 return nullptr;
727}
728
729std::optional<bool> RISCVAsmBackend::evaluateFixup(const MCFragment &,
730 MCFixup &Fixup,
731 MCValue &Target,
732 uint64_t &Value) {
733 const MCFixup *AUIPCFixup;
734 const MCFragment *AUIPCDF;
735 MCValue AUIPCTarget;
736 switch (Fixup.getKind()) {
737 default:
738 // Use default handling for `Value` and `IsResolved`.
739 return {};
740 case RISCV::fixup_qc_access_16:
741 case RISCV::fixup_qc_access_32:
742 // Never resolved in the assembler
743 return false;
744 case RISCV::fixup_riscv_pcrel_lo12_i:
745 case RISCV::fixup_riscv_pcrel_lo12_s: {
746 AUIPCFixup =
747 getPCRelHiFixup(Expr: cast<MCSpecifierExpr>(Val: *Fixup.getValue()), DFOut: &AUIPCDF);
748 if (!AUIPCFixup) {
749 getContext().reportError(L: Fixup.getLoc(),
750 Msg: "could not find corresponding %pcrel_hi");
751 return true;
752 }
753
754 // MCAssembler::evaluateFixup will emit an error for this case when it sees
755 // the %pcrel_hi, so don't duplicate it when also seeing the %pcrel_lo.
756 const MCExpr *AUIPCExpr = AUIPCFixup->getValue();
757 if (!AUIPCExpr->evaluateAsRelocatable(Res&: AUIPCTarget, Asm))
758 return true;
759 break;
760 }
761 }
762
763 if (!AUIPCTarget.getAddSym())
764 return false;
765
766 auto &SA = static_cast<const MCSymbolELF &>(*AUIPCTarget.getAddSym());
767 if (SA.isUndefined())
768 return false;
769
770 bool IsResolved = &SA.getSection() == AUIPCDF->getParent() &&
771 SA.getBinding() == ELF::STB_LOCAL &&
772 SA.getType() != ELF::STT_GNU_IFUNC;
773 if (!IsResolved)
774 return false;
775
776 Value = Asm->getSymbolOffset(S: SA) + AUIPCTarget.getConstant();
777 Value -= Asm->getFragmentOffset(F: *AUIPCDF) + AUIPCFixup->getOffset();
778
779 return AUIPCFixup->getKind() == RISCV::fixup_riscv_pcrel_hi20 &&
780 isPCRelFixupResolved(SymA: AUIPCTarget.getAddSym(), F: *AUIPCDF);
781}
782
783void RISCVAsmBackend::maybeAddVendorReloc(const MCFragment &F,
784 const MCFixup &Fixup) {
785 StringRef VendorIdentifier;
786 switch (Fixup.getKind()) {
787 default:
788 // No Vendor Relocation Required.
789 return;
790 case RISCV::fixup_riscv_qc_e_branch:
791 case RISCV::fixup_riscv_qc_abs20_u:
792 case RISCV::fixup_riscv_qc_e_32:
793 case RISCV::fixup_riscv_qc_e_call_plt:
794 case RISCV::fixup_qc_access_16:
795 case RISCV::fixup_qc_access_32:
796 VendorIdentifier = "QUALCOMM";
797 break;
798 case RISCV::fixup_riscv_nds_branch_10:
799 VendorIdentifier = "ANDES";
800 break;
801 }
802
803 // Create a local symbol for the vendor relocation to reference. It's fine if
804 // the symbol has the same name as an existing symbol.
805 MCContext &Ctx = Asm->getContext();
806 MCSymbol *VendorSymbol = Ctx.createLocalSymbol(Name: VendorIdentifier);
807 auto [It, Inserted] =
808 VendorSymbols.try_emplace(Key: VendorIdentifier, Args&: VendorSymbol);
809
810 if (Inserted) {
811 // Setup the just-created symbol
812 VendorSymbol->setVariableValue(MCConstantExpr::create(Value: 0, Ctx));
813 Asm->registerSymbol(Symbol: *VendorSymbol);
814 } else {
815 // Fetch the existing symbol
816 VendorSymbol = It->getValue();
817 }
818
819 MCFixup VendorFixup =
820 MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: ELF::R_RISCV_VENDOR);
821 // Explicitly create MCValue rather than using an MCExpr and evaluating it so
822 // that the absolute vendor symbol is not evaluated to constant 0.
823 MCValue VendorTarget = MCValue::get(SymA: VendorSymbol);
824 uint64_t VendorValue;
825 Asm->getWriter().recordRelocation(F, Fixup: VendorFixup, Target: VendorTarget, FixedValue&: VendorValue);
826}
827
828static bool relaxableFixupNeedsRelocation(const MCFixupKind Kind) {
829 // Some Fixups are marked as LinkerRelaxable by
830 // `RISCVMCCodeEmitter::getImmOpValue` only because they may be
831 // (assembly-)relaxed into a linker-relaxable instruction. This function
832 // should return `false` for those fixups so they do not get a `R_RISCV_RELAX`
833 // relocation emitted in addition to the relocation.
834 switch (Kind) {
835 default:
836 break;
837 case RISCV::fixup_riscv_rvc_jump:
838 case RISCV::fixup_riscv_branch:
839 case RISCV::fixup_riscv_rvc_branch:
840 case RISCV::fixup_riscv_qc_e_branch:
841 case RISCV::fixup_riscv_rvc_imm:
842 return false;
843 }
844 return true;
845}
846
847bool RISCVAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
848 const MCValue &Target, uint64_t &FixedValue,
849 bool IsResolved) {
850 uint64_t FixedValueA, FixedValueB;
851 if (Target.getSubSym()) {
852 assert(Target.getSpecifier() == 0 &&
853 "relocatable SymA-SymB cannot have relocation specifier");
854 unsigned TA = 0, TB = 0;
855 switch (Fixup.getKind()) {
856 case llvm::FK_Data_1:
857 TA = ELF::R_RISCV_ADD8;
858 TB = ELF::R_RISCV_SUB8;
859 break;
860 case llvm::FK_Data_2:
861 TA = ELF::R_RISCV_ADD16;
862 TB = ELF::R_RISCV_SUB16;
863 break;
864 case llvm::FK_Data_4:
865 TA = ELF::R_RISCV_ADD32;
866 TB = ELF::R_RISCV_SUB32;
867 break;
868 case llvm::FK_Data_8:
869 TA = ELF::R_RISCV_ADD64;
870 TB = ELF::R_RISCV_SUB64;
871 break;
872 case llvm::FK_Data_leb128:
873 TA = ELF::R_RISCV_SET_ULEB128;
874 TB = ELF::R_RISCV_SUB_ULEB128;
875 break;
876 default:
877 llvm_unreachable("unsupported fixup size");
878 }
879 MCValue A = MCValue::get(SymA: Target.getAddSym(), SymB: nullptr, Val: Target.getConstant());
880 MCValue B = MCValue::get(SymA: Target.getSubSym());
881 auto FA = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: TA);
882 auto FB = MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: TB);
883 Asm->getWriter().recordRelocation(F, Fixup: FA, Target: A, FixedValue&: FixedValueA);
884 Asm->getWriter().recordRelocation(F, Fixup: FB, Target: B, FixedValue&: FixedValueB);
885 FixedValue = FixedValueA - FixedValueB;
886 return false;
887 }
888
889 // If linker relaxation is enabled and supported by the current fixup, then we
890 // always want to generate a relocation.
891 bool NeedsRelax = Fixup.isLinkerRelaxable() &&
892 relaxableFixupNeedsRelocation(Kind: Fixup.getKind());
893 if (NeedsRelax)
894 IsResolved = false;
895
896 if (IsResolved && Fixup.isPCRel())
897 IsResolved = isPCRelFixupResolved(SymA: Target.getAddSym(), F);
898
899 if (!IsResolved) {
900 // Some Fixups require a VENDOR relocation, record it (directly) before we
901 // add the relocation.
902 maybeAddVendorReloc(F, Fixup);
903
904 Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
905
906 if (NeedsRelax) {
907 // Some Fixups get a RELAX relocation, record it (directly) after we add
908 // the relocation.
909 MCFixup RelaxFixup =
910 MCFixup::create(Offset: Fixup.getOffset(), Value: nullptr, Kind: ELF::R_RISCV_RELAX);
911 MCValue RelaxTarget = MCValue::get(SymA: nullptr);
912 uint64_t RelaxValue;
913 Asm->getWriter().recordRelocation(F, Fixup: RelaxFixup, Target: RelaxTarget, FixedValue&: RelaxValue);
914 }
915 }
916
917 return false;
918}
919
920// Data fixups should be swapped for big endian cores.
921// Instruction fixups should not be swapped as RISC-V instructions
922// are always little-endian.
923static bool isDataFixup(unsigned Kind) {
924 switch (Kind) {
925 default:
926 return false;
927
928 case FK_Data_1:
929 case FK_Data_2:
930 case FK_Data_4:
931 case FK_Data_8:
932 return true;
933 }
934}
935
936void RISCVAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
937 const MCValue &Target, uint8_t *Data,
938 uint64_t Value, bool IsResolved) {
939 IsResolved = addReloc(F, Fixup, Target, FixedValue&: Value, IsResolved);
940 MCFixupKind Kind = Fixup.getKind();
941 if (mc::isRelocation(FixupKind: Kind))
942 return;
943 MCContext &Ctx = getContext();
944 MCFixupKindInfo Info = getFixupKindInfo(Kind);
945 if (!Value)
946 return; // Doesn't change encoding.
947 // Apply any target-specific value adjustments.
948 Value = adjustFixupValue(Fixup, Value, Ctx);
949
950 // Shift the value into position.
951 Value <<= Info.TargetOffset;
952
953 unsigned NumBytes = alignTo(Value: Info.TargetSize + Info.TargetOffset, Align: 8) / 8;
954 assert(Fixup.getOffset() + NumBytes <= F.getSize() &&
955 "Invalid fixup offset!");
956
957 // For each byte of the fragment that the fixup touches, mask in the
958 // bits from the fixup value.
959 // For big endian cores, data fixup should be swapped.
960 bool SwapValue = Endian == llvm::endianness::big && isDataFixup(Kind);
961 for (unsigned i = 0; i != NumBytes; ++i) {
962 unsigned Idx = SwapValue ? (NumBytes - 1 - i) : i;
963 Data[Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
964 }
965}
966
967std::unique_ptr<MCObjectTargetWriter>
968RISCVAsmBackend::createObjectTargetWriter() const {
969 return createRISCVELFObjectWriter(OSABI, Is64Bit);
970}
971
972class DarwinRISCVAsmBackend : public RISCVAsmBackend {
973public:
974 DarwinRISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
975 bool IsLittleEndian, const MCTargetOptions &Options)
976 : RISCVAsmBackend(STI, OSABI, Is64Bit, IsLittleEndian, Options) {}
977
978 std::unique_ptr<MCObjectTargetWriter>
979 createObjectTargetWriter() const override {
980 const Triple &TT = STI.getTargetTriple();
981 uint32_t CPUType = cantFail(ValOrErr: MachO::getCPUType(T: TT));
982 uint32_t CPUSubType = cantFail(ValOrErr: MachO::getCPUSubType(T: TT));
983 return createRISCVMachObjectWriter(CPUType, CPUSubtype: CPUSubType);
984 }
985
986 bool addReloc(const MCFragment &, const MCFixup &, const MCValue &,
987 uint64_t &FixedValue, bool IsResolved) override;
988
989 std::optional<bool> evaluateFixup(const MCFragment &F, MCFixup &Fixup,
990 MCValue &Target, uint64_t &Value) override {
991 const MCFixup *AUIPCFixup;
992 const MCFragment *AUIPCDF;
993 const MCFixupKind FKind = Fixup.getKind();
994 if ((FKind == RISCV::fixup_riscv_pcrel_lo12_i) ||
995 (FKind == RISCV::fixup_riscv_pcrel_lo12_s)) {
996 AUIPCFixup =
997 getPCRelHiFixup(Expr: cast<MCSpecifierExpr>(Val: *Fixup.getValue()), DFOut: &AUIPCDF);
998 if (!AUIPCFixup) {
999 getContext().reportError(L: Fixup.getLoc(),
1000 Msg: "could not find corresponding %pcrel_hi");
1001 return true;
1002 }
1003
1004 return false;
1005 }
1006
1007 // Use default handling for all other cases.
1008 return {};
1009 }
1010};
1011
1012MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
1013 const MCSubtargetInfo &STI,
1014 const MCRegisterInfo &MRI,
1015 const MCTargetOptions &Options) {
1016 const Triple &TT = STI.getTargetTriple();
1017 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType: TT.getOS());
1018 if (TT.isOSBinFormatMachO())
1019 return new DarwinRISCVAsmBackend(STI, OSABI, TT.isArch64Bit(),
1020 TT.isLittleEndian(), Options);
1021
1022 return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), TT.isLittleEndian(),
1023 Options);
1024}
1025
1026bool DarwinRISCVAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
1027 const MCValue &Target,
1028 uint64_t &FixedValue, bool IsResolved) {
1029 if (!IsResolved)
1030 Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
1031 return IsResolved;
1032}
1033