1//===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides RISC-V specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetStreamer.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCTargetDesc.h"
16#include "llvm/BinaryFormat/ELF.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCSectionELF.h"
20#include "llvm/MC/MCStreamer.h"
21#include "llvm/MC/MCSymbol.h"
22#include "llvm/Support/Alignment.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/FormattedStream.h"
26#include "llvm/Support/RISCVAttributes.h"
27#include "llvm/TargetParser/RISCVISAInfo.h"
28
29using namespace llvm;
30
31// This option controls whether or not we emit ELF attributes for ABI features,
32// like RISC-V atomics or X3 usage.
33static cl::opt<bool> RiscvAbiAttr(
34 "riscv-abi-attributes",
35 cl::desc("Enable emitting RISC-V ELF attributes for ABI features"),
36 cl::Hidden);
37
38RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
39
40void RISCVTargetStreamer::finish() { finishAttributeSection(); }
41void RISCVTargetStreamer::reset() {}
42
43void RISCVTargetStreamer::emitDirectiveOptionArch(
44 ArrayRef<RISCVOptionArchArg> Args) {}
45void RISCVTargetStreamer::emitDirectiveOptionExact() {}
46void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
47void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
48void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
49void RISCVTargetStreamer::emitDirectiveOptionPop() {}
50void RISCVTargetStreamer::emitDirectiveOptionPush() {}
51void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
52void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
53void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
54void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
55void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
56void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
57void RISCVTargetStreamer::finishAttributeSection() {}
58void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
59 StringRef String) {}
60void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
61 unsigned IntValue,
62 StringRef StringValue) {}
63
64void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
65 assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
66 TargetABI = ABI;
67}
68
69void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) {
70 HasRVC = STI.hasFeature(Feature: RISCV::FeatureStdExtZca);
71 HasTSO = STI.hasFeature(Feature: RISCV::FeatureStdExtZtso);
72}
73
74void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
75 bool EmitStackAlign) {
76 if (EmitStackAlign) {
77 unsigned StackAlign;
78 if (TargetABI == RISCVABI::ABI_ILP32E)
79 StackAlign = 4;
80 else if (TargetABI == RISCVABI::ABI_LP64E)
81 StackAlign = 8;
82 else
83 StackAlign = 16;
84 emitAttribute(Attribute: RISCVAttrs::STACK_ALIGN, Value: StackAlign);
85 }
86
87 auto ParseResult = RISCVFeatures::parseFeatureBits(STI);
88 if (!ParseResult) {
89 report_fatal_error(Err: ParseResult.takeError());
90 } else {
91 auto &ISAInfo = *ParseResult;
92 emitTextAttribute(Attribute: RISCVAttrs::ARCH, String: ISAInfo->toString());
93 }
94
95 if (RiscvAbiAttr && STI.hasFeature(Feature: RISCV::FeatureStdExtA)) {
96 unsigned AtomicABITag;
97 if (STI.hasFeature(Feature: RISCV::FeatureStdExtZalasr))
98 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A7);
99 else if (STI.hasFeature(Feature: RISCV::FeatureNoTrailingSeqCstFence))
100 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6C);
101 else
102 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6S);
103 emitAttribute(Attribute: RISCVAttrs::ATOMIC_ABI, Value: AtomicABITag);
104 }
105}
106
107// This part is for ascii assembly output
108RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
109 formatted_raw_ostream &OS)
110 : RISCVTargetStreamer(S), OS(OS) {}
111
112void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
113 OS << "\t.option\tpush\n";
114}
115
116void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
117 OS << "\t.option\tpop\n";
118}
119
120void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
121 OS << "\t.option\tpic\n";
122}
123
124void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
125 OS << "\t.option\tnopic\n";
126}
127
128void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
129 OS << "\t.option\trvc\n";
130}
131
132void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
133 OS << "\t.option\tnorvc\n";
134}
135
136void RISCVTargetAsmStreamer::emitDirectiveOptionExact() {
137 OS << "\t.option\texact\n";
138}
139
140void RISCVTargetAsmStreamer::emitDirectiveOptionNoExact() {
141 OS << "\t.option\tnoexact\n";
142}
143
144void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
145 OS << "\t.option\trelax\n";
146}
147
148void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
149 OS << "\t.option\tnorelax\n";
150}
151
152void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
153 ArrayRef<RISCVOptionArchArg> Args) {
154 OS << "\t.option\tarch";
155 for (const auto &Arg : Args) {
156 OS << ", ";
157 switch (Arg.Type) {
158 case RISCVOptionArchArgType::Full:
159 break;
160 case RISCVOptionArchArgType::Plus:
161 OS << "+";
162 break;
163 case RISCVOptionArchArgType::Minus:
164 OS << "-";
165 break;
166 }
167 OS << Arg.Value;
168 }
169 OS << "\n";
170}
171
172void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {
173 OS << "\t.variant_cc\t" << Symbol.getName() << "\n";
174}
175
176void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
177 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
178}
179
180void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
181 StringRef String) {
182 OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
183}
184
185void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
186 unsigned IntValue,
187 StringRef StringValue) {}
188
189void RISCVTargetAsmStreamer::finishAttributeSection() {}
190