1//===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides RISC-V specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetStreamer.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCTargetDesc.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCSymbol.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/FormattedStream.h"
23#include "llvm/Support/RISCVAttributes.h"
24#include "llvm/TargetParser/RISCVISAInfo.h"
25
26using namespace llvm;
27
28// This option controls whether or not we emit ELF attributes for ABI features,
29// like RISC-V atomics or X3 usage.
30static cl::opt<bool> RiscvAbiAttr(
31 "riscv-abi-attributes",
32 cl::desc("Enable emitting RISC-V ELF attributes for ABI features"),
33 cl::Hidden);
34
35RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
36
37void RISCVTargetStreamer::finish() { finishAttributeSection(); }
38void RISCVTargetStreamer::reset() {}
39
40void RISCVTargetStreamer::emitDirectiveOptionArch(
41 ArrayRef<RISCVOptionArchArg> Args) {}
42void RISCVTargetStreamer::emitDirectiveOptionExact() {}
43void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
44void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
45void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
46void RISCVTargetStreamer::emitDirectiveOptionPop() {}
47void RISCVTargetStreamer::emitDirectiveOptionPush() {}
48void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
49void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
50void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
51void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
52void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
53void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
54void RISCVTargetStreamer::finishAttributeSection() {}
55void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
56 StringRef String) {}
57void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
58 unsigned IntValue,
59 StringRef StringValue) {}
60
61void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
62 assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
63 TargetABI = ABI;
64}
65
66void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) {
67 HasRVC = STI.hasFeature(Feature: RISCV::FeatureStdExtZca);
68 HasTSO = STI.hasFeature(Feature: RISCV::FeatureStdExtZtso);
69}
70
71void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
72 bool EmitStackAlign) {
73 if (EmitStackAlign) {
74 unsigned StackAlign;
75 if (TargetABI == RISCVABI::ABI_ILP32E)
76 StackAlign = 4;
77 else if (TargetABI == RISCVABI::ABI_LP64E)
78 StackAlign = 8;
79 else
80 StackAlign = 16;
81 emitAttribute(Attribute: RISCVAttrs::STACK_ALIGN, Value: StackAlign);
82 }
83
84 auto ParseResult = RISCVFeatures::parseFeatureBits(STI);
85 if (!ParseResult) {
86 report_fatal_error(Err: ParseResult.takeError());
87 } else {
88 auto &ISAInfo = *ParseResult;
89 emitTextAttribute(Attribute: RISCVAttrs::ARCH, String: ISAInfo->toString());
90 }
91
92 if (RiscvAbiAttr && STI.hasFeature(Feature: RISCV::FeatureStdExtA)) {
93 unsigned AtomicABITag;
94 if (STI.hasFeature(Feature: RISCV::FeatureStdExtZalasr))
95 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A7);
96 else if (STI.hasFeature(Feature: RISCV::FeatureNoTrailingSeqCstFence))
97 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6C);
98 else
99 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6S);
100 emitAttribute(Attribute: RISCVAttrs::ATOMIC_ABI, Value: AtomicABITag);
101 }
102}
103
104// This part is for ascii assembly output
105RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
106 formatted_raw_ostream &OS)
107 : RISCVTargetStreamer(S), OS(OS) {}
108
109void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
110 OS << "\t.option\tpush\n";
111}
112
113void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
114 OS << "\t.option\tpop\n";
115}
116
117void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
118 OS << "\t.option\tpic\n";
119}
120
121void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
122 OS << "\t.option\tnopic\n";
123}
124
125void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
126 OS << "\t.option\trvc\n";
127}
128
129void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
130 OS << "\t.option\tnorvc\n";
131}
132
133void RISCVTargetAsmStreamer::emitDirectiveOptionExact() {
134 OS << "\t.option\texact\n";
135}
136
137void RISCVTargetAsmStreamer::emitDirectiveOptionNoExact() {
138 OS << "\t.option\tnoexact\n";
139}
140
141void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
142 OS << "\t.option\trelax\n";
143}
144
145void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
146 OS << "\t.option\tnorelax\n";
147}
148
149void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
150 ArrayRef<RISCVOptionArchArg> Args) {
151 OS << "\t.option\tarch";
152 for (const auto &Arg : Args) {
153 OS << ", ";
154 switch (Arg.Type) {
155 case RISCVOptionArchArgType::Full:
156 break;
157 case RISCVOptionArchArgType::Plus:
158 OS << "+";
159 break;
160 case RISCVOptionArchArgType::Minus:
161 OS << "-";
162 break;
163 }
164 OS << Arg.Value;
165 }
166 OS << "\n";
167}
168
169void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {
170 OS << "\t.variant_cc\t" << Symbol.getName() << "\n";
171}
172
173void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
174 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
175}
176
177void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
178 StringRef String) {
179 OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
180}
181
182void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
183 unsigned IntValue,
184 StringRef StringValue) {}
185
186void RISCVTargetAsmStreamer::finishAttributeSection() {}
187