1//===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides RISC-V specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetStreamer.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCTargetDesc.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCSymbol.h"
20#include "llvm/Support/ErrorHandling.h"
21#include "llvm/Support/FormattedStream.h"
22#include "llvm/Support/RISCVAttributes.h"
23#include "llvm/TargetParser/RISCVISAInfo.h"
24
25using namespace llvm;
26
27RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S)
28 : MCTargetStreamer(S), CLOpts(RISCVMCOptions::Global) {}
29
30void RISCVTargetStreamer::finish() { finishAttributeSection(); }
31void RISCVTargetStreamer::reset() {}
32
33void RISCVTargetStreamer::emitDirectiveOptionArch(
34 ArrayRef<RISCVOptionArchArg> Args) {}
35void RISCVTargetStreamer::emitDirectiveOptionExact() {}
36void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
37void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
38void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
39void RISCVTargetStreamer::emitDirectiveOptionPop() {}
40void RISCVTargetStreamer::emitDirectiveOptionPush() {}
41void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
42void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
43void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
44void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
45void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
46void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
47void RISCVTargetStreamer::finishAttributeSection() {}
48void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
49 StringRef String) {}
50void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
51 unsigned IntValue,
52 StringRef StringValue) {}
53
54void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
55 assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
56 TargetABI = ABI;
57}
58
59void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) {
60 HasRVC = STI.hasFeature(Feature: RISCV::FeatureStdExtZca);
61 HasTSO = STI.hasFeature(Feature: RISCV::FeatureStdExtZtso);
62}
63
64void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
65 bool EmitStackAlign) {
66 if (EmitStackAlign) {
67 unsigned StackAlign;
68 if (TargetABI == RISCVABI::ABI_ILP32E)
69 StackAlign = 4;
70 else if (TargetABI == RISCVABI::ABI_LP64E)
71 StackAlign = 8;
72 else
73 StackAlign = 16;
74 emitAttribute(Attribute: RISCVAttrs::STACK_ALIGN, Value: StackAlign);
75 }
76
77 auto ParseResult = RISCVFeatures::parseFeatureBits(STI);
78 if (!ParseResult) {
79 report_fatal_error(Err: ParseResult.takeError());
80 } else {
81 auto &ISAInfo = *ParseResult;
82 std::string Arch = ISAInfo->toString();
83 emitTextAttribute(Attribute: RISCVAttrs::ARCH, String: Arch);
84 setArchString(Arch);
85 }
86
87 if (CLOpts.abi_attributes && STI.hasFeature(Feature: RISCV::FeatureStdExtA)) {
88 unsigned AtomicABITag;
89 if (STI.hasFeature(Feature: RISCV::FeatureStdExtZalasr))
90 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A7);
91 else if (STI.hasFeature(Feature: RISCV::FeatureNoTrailingSeqCstFence))
92 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6C);
93 else
94 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6S);
95 emitAttribute(Attribute: RISCVAttrs::ATOMIC_ABI, Value: AtomicABITag);
96 }
97}
98
99// This part is for ascii assembly output
100RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
101 formatted_raw_ostream &OS)
102 : RISCVTargetStreamer(S), OS(OS) {}
103
104void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
105 OS << "\t.option\tpush\n";
106}
107
108void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
109 OS << "\t.option\tpop\n";
110}
111
112void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
113 OS << "\t.option\tpic\n";
114}
115
116void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
117 OS << "\t.option\tnopic\n";
118}
119
120void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
121 OS << "\t.option\trvc\n";
122}
123
124void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
125 OS << "\t.option\tnorvc\n";
126}
127
128void RISCVTargetAsmStreamer::emitDirectiveOptionExact() {
129 OS << "\t.option\texact\n";
130}
131
132void RISCVTargetAsmStreamer::emitDirectiveOptionNoExact() {
133 OS << "\t.option\tnoexact\n";
134}
135
136void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
137 OS << "\t.option\trelax\n";
138}
139
140void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
141 OS << "\t.option\tnorelax\n";
142}
143
144void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
145 ArrayRef<RISCVOptionArchArg> Args) {
146 OS << "\t.option\tarch";
147 for (const auto &Arg : Args) {
148 OS << ", ";
149 switch (Arg.Type) {
150 case RISCVOptionArchArgType::Full:
151 break;
152 case RISCVOptionArchArgType::Plus:
153 OS << "+";
154 break;
155 case RISCVOptionArchArgType::Minus:
156 OS << "-";
157 break;
158 }
159 OS << Arg.Value;
160 }
161 OS << "\n";
162}
163
164void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {
165 OS << "\t.variant_cc\t" << Symbol.getName() << "\n";
166}
167
168void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
169 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
170}
171
172void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
173 StringRef String) {
174 OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
175}
176
177void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
178 unsigned IntValue,
179 StringRef StringValue) {}
180
181void RISCVTargetAsmStreamer::finishAttributeSection() {}
182