1//===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides RISC-V specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetStreamer.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCTargetDesc.h"
16#include "llvm/BinaryFormat/ELF.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCSectionELF.h"
20#include "llvm/MC/MCStreamer.h"
21#include "llvm/MC/MCSymbol.h"
22#include "llvm/Support/Alignment.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/FormattedStream.h"
26#include "llvm/Support/RISCVAttributes.h"
27#include "llvm/TargetParser/RISCVISAInfo.h"
28
29using namespace llvm;
30
31// This option controls whether or not we emit ELF attributes for ABI features,
32// like RISC-V atomics or X3 usage.
33static cl::opt<bool> RiscvAbiAttr(
34 "riscv-abi-attributes",
35 cl::desc("Enable emitting RISC-V ELF attributes for ABI features"),
36 cl::Hidden);
37
38RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
39
40void RISCVTargetStreamer::finish() { finishAttributeSection(); }
41void RISCVTargetStreamer::reset() {}
42
43void RISCVTargetStreamer::emitDirectiveOptionArch(
44 ArrayRef<RISCVOptionArchArg> Args) {}
45void RISCVTargetStreamer::emitDirectiveOptionExact() {}
46void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
47void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
48void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
49void RISCVTargetStreamer::emitDirectiveOptionPop() {}
50void RISCVTargetStreamer::emitDirectiveOptionPush() {}
51void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
52void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
53void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
54void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
55void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
56void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
57void RISCVTargetStreamer::finishAttributeSection() {}
58void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
59 StringRef String) {}
60void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
61 unsigned IntValue,
62 StringRef StringValue) {}
63
64void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
65 assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
66 TargetABI = ABI;
67}
68
69void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) {
70 HasRVC = STI.hasFeature(Feature: RISCV::FeatureStdExtZca);
71 HasTSO = STI.hasFeature(Feature: RISCV::FeatureStdExtZtso);
72}
73
74void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
75 bool EmitStackAlign) {
76 if (EmitStackAlign) {
77 unsigned StackAlign;
78 if (TargetABI == RISCVABI::ABI_ILP32E)
79 StackAlign = 4;
80 else if (TargetABI == RISCVABI::ABI_LP64E)
81 StackAlign = 8;
82 else
83 StackAlign = 16;
84 emitAttribute(Attribute: RISCVAttrs::STACK_ALIGN, Value: StackAlign);
85 }
86
87 auto ParseResult = RISCVFeatures::parseFeatureBits(
88 IsRV64: STI.hasFeature(Feature: RISCV::Feature64Bit), FeatureBits: STI.getFeatureBits());
89 if (!ParseResult) {
90 report_fatal_error(Err: ParseResult.takeError());
91 } else {
92 auto &ISAInfo = *ParseResult;
93 emitTextAttribute(Attribute: RISCVAttrs::ARCH, String: ISAInfo->toString());
94 }
95
96 if (RiscvAbiAttr && STI.hasFeature(Feature: RISCV::FeatureStdExtA)) {
97 unsigned AtomicABITag;
98 if (STI.hasFeature(Feature: RISCV::FeatureStdExtZalasr))
99 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A7);
100 else if (STI.hasFeature(Feature: RISCV::FeatureNoTrailingSeqCstFence))
101 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6C);
102 else
103 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6S);
104 emitAttribute(Attribute: RISCVAttrs::ATOMIC_ABI, Value: AtomicABITag);
105 }
106}
107
108// This part is for ascii assembly output
109RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
110 formatted_raw_ostream &OS)
111 : RISCVTargetStreamer(S), OS(OS) {}
112
113void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
114 OS << "\t.option\tpush\n";
115}
116
117void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
118 OS << "\t.option\tpop\n";
119}
120
121void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
122 OS << "\t.option\tpic\n";
123}
124
125void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
126 OS << "\t.option\tnopic\n";
127}
128
129void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
130 OS << "\t.option\trvc\n";
131}
132
133void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
134 OS << "\t.option\tnorvc\n";
135}
136
137void RISCVTargetAsmStreamer::emitDirectiveOptionExact() {
138 OS << "\t.option\texact\n";
139}
140
141void RISCVTargetAsmStreamer::emitDirectiveOptionNoExact() {
142 OS << "\t.option\tnoexact\n";
143}
144
145void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
146 OS << "\t.option\trelax\n";
147}
148
149void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
150 OS << "\t.option\tnorelax\n";
151}
152
153void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
154 ArrayRef<RISCVOptionArchArg> Args) {
155 OS << "\t.option\tarch";
156 for (const auto &Arg : Args) {
157 OS << ", ";
158 switch (Arg.Type) {
159 case RISCVOptionArchArgType::Full:
160 break;
161 case RISCVOptionArchArgType::Plus:
162 OS << "+";
163 break;
164 case RISCVOptionArchArgType::Minus:
165 OS << "-";
166 break;
167 }
168 OS << Arg.Value;
169 }
170 OS << "\n";
171}
172
173void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {
174 OS << "\t.variant_cc\t" << Symbol.getName() << "\n";
175}
176
177void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
178 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
179}
180
181void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
182 StringRef String) {
183 OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
184}
185
186void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
187 unsigned IntValue,
188 StringRef StringValue) {}
189
190void RISCVTargetAsmStreamer::finishAttributeSection() {}
191