1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains one of the several passes that expand pseudo instructions
10// into target instructions. This pass is run before register allocation.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCV.h"
15#include "RISCVExpandPseudoBase.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVSubtarget.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/MC/MCContext.h"
21
22using namespace llvm;
23
24#define RISCV_EXPAND_PSEUDO_PRE_RA_NAME \
25 "RISC-V Pseudo Instruction Expansion - Pre-RA"
26
27namespace {
28
29class RISCVExpandPseudoPreRAImpl final : public RISCVExpandPseudoImplBase {
30 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
31 MachineBasicBlock::iterator &NextMBBI) const override;
32
33 bool expandAuipcInstPair(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MBBI, unsigned FlagsHi,
35 unsigned SecondOpcode) const;
36
37 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MBBI) const;
39
40 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
41 MachineBasicBlock::iterator MBBI) const;
42
43 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MBBI) const;
45
46 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MBBI) const;
48
49 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI) const;
51};
52
53class RISCVExpandPseudoPreRALegacy : public MachineFunctionPass {
54public:
55 static char ID;
56
57 RISCVExpandPseudoPreRALegacy() : MachineFunctionPass(ID) {}
58
59 bool runOnMachineFunction(MachineFunction &MF) override {
60 return RISCVExpandPseudoPreRAImpl().run(MF);
61 }
62
63 MachineFunctionProperties getRequiredProperties() const override {
64 return MachineFunctionProperties().setIsSSA();
65 }
66
67 void getAnalysisUsage(AnalysisUsage &AU) const override {
68 AU.setPreservesCFG();
69 MachineFunctionPass::getAnalysisUsage(AU);
70 }
71 StringRef getPassName() const override {
72 return RISCV_EXPAND_PSEUDO_PRE_RA_NAME;
73 }
74};
75
76} // anonymous namespace
77
78bool RISCVExpandPseudoPreRAImpl::expandMI(
79 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
80 MachineBasicBlock::iterator &NextMBBI) const {
81
82 switch (MBBI->getOpcode()) {
83 case RISCV::PseudoLLA:
84 return expandLoadLocalAddress(MBB, MBBI);
85 case RISCV::PseudoLGA:
86 return expandLoadGlobalAddress(MBB, MBBI);
87 case RISCV::PseudoLA_TLS_IE:
88 return expandLoadTLSIEAddress(MBB, MBBI);
89 case RISCV::PseudoLA_TLS_GD:
90 return expandLoadTLSGDAddress(MBB, MBBI);
91 case RISCV::PseudoLA_TLSDESC:
92 return expandLoadTLSDescAddress(MBB, MBBI);
93 }
94
95 return false;
96}
97
98bool RISCVExpandPseudoPreRAImpl::expandAuipcInstPair(
99 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned FlagsHi,
100 unsigned SecondOpcode) const {
101 MachineFunction *MF = MBB.getParent();
102 MachineInstr &MI = *MBBI;
103 DebugLoc DL = MI.getDebugLoc();
104
105 Register DestReg = MI.getOperand(i: 0).getReg();
106 Register ScratchReg =
107 MF->getRegInfo().createVirtualRegister(RegClass: &RISCV::GPRRegClass);
108
109 MachineOperand &Symbol = MI.getOperand(i: 1);
110 Symbol.setTargetFlags(FlagsHi);
111 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol(Name: "pcrel_hi");
112
113 MachineInstr *MIAUIPC =
114 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::AUIPC), DestReg: ScratchReg).add(MO: Symbol);
115 MIAUIPC->setPreInstrSymbol(MF&: *MF, Symbol: AUIPCSymbol);
116
117 MachineInstr *SecondMI =
118 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: SecondOpcode), DestReg)
119 .addReg(RegNo: ScratchReg)
120 .addSym(Sym: AUIPCSymbol, TargetFlags: RISCVII::MO_PCREL_LO);
121
122 if (MI.hasOneMemOperand())
123 SecondMI->addMemOperand(MF&: *MF, MO: *MI.memoperands_begin());
124
125 MI.eraseFromParent();
126 return true;
127}
128
129bool RISCVExpandPseudoPreRAImpl::expandLoadLocalAddress(
130 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
131 return expandAuipcInstPair(MBB, MBBI, FlagsHi: RISCVII::MO_PCREL_HI, SecondOpcode: RISCV::ADDI);
132}
133
134bool RISCVExpandPseudoPreRAImpl::expandLoadGlobalAddress(
135 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
136 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
137 return expandAuipcInstPair(MBB, MBBI, FlagsHi: RISCVII::MO_GOT_HI, SecondOpcode);
138}
139
140bool RISCVExpandPseudoPreRAImpl::expandLoadTLSIEAddress(
141 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
142 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
143 return expandAuipcInstPair(MBB, MBBI, FlagsHi: RISCVII::MO_TLS_GOT_HI, SecondOpcode);
144}
145
146bool RISCVExpandPseudoPreRAImpl::expandLoadTLSGDAddress(
147 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
148 return expandAuipcInstPair(MBB, MBBI, FlagsHi: RISCVII::MO_TLS_GD_HI, SecondOpcode: RISCV::ADDI);
149}
150
151bool RISCVExpandPseudoPreRAImpl::expandLoadTLSDescAddress(
152 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
153 MachineFunction *MF = MBB.getParent();
154 MachineInstr &MI = *MBBI;
155 DebugLoc DL = MI.getDebugLoc();
156
157 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
158 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
159
160 Register FinalReg = MI.getOperand(i: 0).getReg();
161 Register DestReg =
162 MF->getRegInfo().createVirtualRegister(RegClass: &RISCV::GPRRegClass);
163 Register ScratchReg =
164 MF->getRegInfo().createVirtualRegister(RegClass: &RISCV::GPRRegClass);
165
166 MachineOperand &Symbol = MI.getOperand(i: 1);
167 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
168 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol(Name: "tlsdesc_hi");
169
170 MachineInstr *MIAUIPC =
171 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::AUIPC), DestReg: ScratchReg).add(MO: Symbol);
172 MIAUIPC->setPreInstrSymbol(MF&: *MF, Symbol: AUIPCSymbol);
173
174 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: SecondOpcode), DestReg)
175 .addReg(RegNo: ScratchReg)
176 .addSym(Sym: AUIPCSymbol, TargetFlags: RISCVII::MO_TLSDESC_LOAD_LO);
177
178 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg: RISCV::X10)
179 .addReg(RegNo: ScratchReg)
180 .addSym(Sym: AUIPCSymbol, TargetFlags: RISCVII::MO_TLSDESC_ADD_LO);
181
182 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoTLSDESCCall), DestReg: RISCV::X5)
183 .addReg(RegNo: DestReg)
184 .addImm(Val: 0)
185 .addSym(Sym: AUIPCSymbol, TargetFlags: RISCVII::MO_TLSDESC_CALL);
186
187 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADD), DestReg: FinalReg)
188 .addReg(RegNo: RISCV::X10)
189 .addReg(RegNo: RISCV::X4);
190
191 MI.eraseFromParent();
192 return true;
193}
194
195char RISCVExpandPseudoPreRALegacy::ID = 0;
196
197INITIALIZE_PASS(RISCVExpandPseudoPreRALegacy, "riscv-expand-pseudo-pre-ra",
198 RISCV_EXPAND_PSEUDO_PRE_RA_NAME, false, false)
199
200FunctionPass *llvm::createRISCVExpandPseudoPreRALegacyPass() {
201 return new RISCVExpandPseudoPreRALegacy();
202}
203
204PreservedAnalyses
205RISCVExpandPseudoPreRAPass::run(MachineFunction &MF,
206 MachineFunctionAnalysisManager &MFAM) {
207 MFPropsModifier _(*this, MF);
208 bool Changed = RISCVExpandPseudoPreRAImpl().run(MF);
209 if (!Changed)
210 return PreservedAnalyses::all();
211
212 PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
213 PA.preserveSet<CFGAnalyses>();
214 return PA;
215}
216