1//===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a function pass that inserts VSETVLI instructions where
10// needed and expands the vl outputs of VLEFF/VLSEGFF to PseudoReadVL
11// instructions.
12//
13// This pass consists of 3 phases:
14//
15// Phase 1 collects how each basic block affects VL/VTYPE.
16//
17// Phase 2 uses the information from phase 1 to do a data flow analysis to
18// propagate the VL/VTYPE changes through the function. This gives us the
19// VL/VTYPE at the start of each basic block.
20//
21// Phase 3 inserts VSETVLI instructions in each basic block. Information from
22// phase 2 is used to prevent inserting a VSETVLI before the first vector
23// instruction in the block if possible.
24//
25//===----------------------------------------------------------------------===//
26
27#include "RISCV.h"
28#include "RISCVSubtarget.h"
29#include "RISCVVSETVLIInfoAnalysis.h"
30#include "llvm/ADT/PostOrderIterator.h"
31#include "llvm/ADT/Statistic.h"
32#include "llvm/CodeGen/LiveDebugVariables.h"
33#include "llvm/CodeGen/LiveIntervals.h"
34#include "llvm/CodeGen/LiveStacks.h"
35#include "llvm/CodeGen/MachineFunctionPass.h"
36#include <queue>
37using namespace llvm;
38using namespace RISCV;
39
40#define DEBUG_TYPE "riscv-insert-vsetvli"
41#define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass"
42
43STATISTIC(NumInsertedVSETVL, "Number of VSETVL inst inserted");
44STATISTIC(NumCoalescedVSETVL, "Number of VSETVL inst coalesced");
45
46static cl::opt<bool> EnsureWholeVectorRegisterMoveValidVTYPE(
47 DEBUG_TYPE "-whole-vector-register-move-valid-vtype", cl::Hidden,
48 cl::desc("Insert vsetvlis before vmvNr.vs to ensure vtype is valid and "
49 "vill is cleared"),
50 cl::init(Val: true));
51
52namespace {
53
54/// Given a virtual register \p Reg, return the corresponding VNInfo for it.
55/// This will return nullptr if the virtual register is an implicit_def or
56/// if LiveIntervals is not available.
57static VNInfo *getVNInfoFromReg(Register Reg, const MachineInstr &MI,
58 const LiveIntervals *LIS) {
59 assert(Reg.isVirtual());
60 if (!LIS)
61 return nullptr;
62 auto &LI = LIS->getInterval(Reg);
63 SlotIndex SI = LIS->getSlotIndexes()->getInstructionIndex(MI);
64 return LI.getVNInfoBefore(Idx: SI);
65}
66
67static unsigned getVLOpNum(const MachineInstr &MI) {
68 return RISCVII::getVLOpNum(Desc: MI.getDesc());
69}
70
71struct BlockData {
72 // The VSETVLIInfo that represents the VL/VTYPE settings on exit from this
73 // block. Calculated in Phase 2.
74 VSETVLIInfo Exit;
75
76 // The VSETVLIInfo that represents the VL/VTYPE settings from all predecessor
77 // blocks. Calculated in Phase 2, and used by Phase 3.
78 VSETVLIInfo Pred;
79
80 // Keeps track of whether the block is already in the queue.
81 bool InQueue = false;
82
83 BlockData() = default;
84};
85
86enum TKTMMode {
87 VSETTK = 0,
88 VSETTM = 1,
89};
90
91class RISCVInsertVSETVLI : public MachineFunctionPass {
92 const RISCVSubtarget *ST;
93 const TargetInstrInfo *TII;
94 MachineRegisterInfo *MRI;
95 // Possibly null!
96 LiveIntervals *LIS;
97 RISCVVSETVLIInfoAnalysis VIA;
98
99 std::vector<BlockData> BlockInfo;
100 std::queue<const MachineBasicBlock *> WorkList;
101
102public:
103 static char ID;
104
105 RISCVInsertVSETVLI() : MachineFunctionPass(ID) {}
106 bool runOnMachineFunction(MachineFunction &MF) override;
107
108 void getAnalysisUsage(AnalysisUsage &AU) const override {
109 AU.setPreservesCFG();
110
111 AU.addUsedIfAvailable<LiveIntervalsWrapperPass>();
112 AU.addPreserved<LiveIntervalsWrapperPass>();
113 AU.addPreserved<SlotIndexesWrapperPass>();
114 AU.addPreserved<LiveDebugVariablesWrapperLegacy>();
115 AU.addPreserved<LiveStacksWrapperLegacy>();
116
117 MachineFunctionPass::getAnalysisUsage(AU);
118 }
119
120 StringRef getPassName() const override { return RISCV_INSERT_VSETVLI_NAME; }
121
122private:
123 bool needVSETVLI(const DemandedFields &Used, const VSETVLIInfo &Require,
124 const VSETVLIInfo &CurInfo) const;
125 bool needVSETVLIPHI(const VSETVLIInfo &Require,
126 const MachineBasicBlock &MBB) const;
127 void insertVSETVLI(MachineBasicBlock &MBB,
128 MachineBasicBlock::iterator InsertPt, DebugLoc DL,
129 const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo);
130
131 void transferBefore(VSETVLIInfo &Info, const MachineInstr &MI) const;
132 void transferAfter(VSETVLIInfo &Info, const MachineInstr &MI) const;
133 bool computeVLVTYPEChanges(const MachineBasicBlock &MBB,
134 VSETVLIInfo &Info) const;
135 void computeIncomingVLVTYPE(const MachineBasicBlock &MBB);
136 void emitVSETVLIs(MachineBasicBlock &MBB);
137 void doPRE(MachineBasicBlock &MBB);
138 void insertReadVL(MachineBasicBlock &MBB);
139
140 bool canMutatePriorConfig(const MachineInstr &PrevMI, const MachineInstr &MI,
141 const DemandedFields &Used) const;
142 void coalesceVSETVLIs(MachineBasicBlock &MBB) const;
143 bool insertVSETMTK(MachineBasicBlock &MBB, TKTMMode Mode) const;
144};
145
146} // end anonymous namespace
147
148char RISCVInsertVSETVLI::ID = 0;
149char &llvm::RISCVInsertVSETVLIID = RISCVInsertVSETVLI::ID;
150
151INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME,
152 false, false)
153
154void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
155 MachineBasicBlock::iterator InsertPt,
156 DebugLoc DL, const VSETVLIInfo &Info,
157 const VSETVLIInfo &PrevInfo) {
158 ++NumInsertedVSETVL;
159
160 if (Info.getTWiden()) {
161 if (Info.hasAVLVLMAX()) {
162 Register DestReg = MRI->createVirtualRegister(RegClass: &RISCV::GPRNoX0RegClass);
163 auto MI = BuildMI(BB&: MBB, I: InsertPt, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoSF_VSETTNTX0))
164 .addReg(RegNo: DestReg, Flags: RegState::Define | RegState::Dead)
165 .addReg(RegNo: RISCV::X0, Flags: RegState::Kill)
166 .addImm(Val: Info.encodeVTYPE());
167 if (LIS) {
168 LIS->InsertMachineInstrInMaps(MI&: *MI);
169 LIS->createAndComputeVirtRegInterval(Reg: DestReg);
170 }
171 } else {
172 auto MI = BuildMI(BB&: MBB, I: InsertPt, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoSF_VSETTNT))
173 .addReg(RegNo: RISCV::X0, Flags: RegState::Define | RegState::Dead)
174 .addReg(RegNo: Info.getAVLReg())
175 .addImm(Val: Info.encodeVTYPE());
176 if (LIS)
177 LIS->InsertMachineInstrInMaps(MI&: *MI);
178 }
179 return;
180 }
181
182 if (PrevInfo.isValid() && !PrevInfo.isUnknown()) {
183 // Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same
184 // VLMAX.
185 if (Info.hasSameAVL(Other: PrevInfo) && Info.hasSameVLMAX(Other: PrevInfo)) {
186 auto MI = BuildMI(BB&: MBB, I: InsertPt, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoVSETVLIX0X0))
187 .addReg(RegNo: RISCV::X0, Flags: RegState::Define | RegState::Dead)
188 .addReg(RegNo: RISCV::X0, Flags: RegState::Kill)
189 .addImm(Val: Info.encodeVTYPE())
190 .addReg(RegNo: RISCV::VL, Flags: RegState::Implicit);
191 if (LIS)
192 LIS->InsertMachineInstrInMaps(MI&: *MI);
193 return;
194 }
195
196 // If our AVL is a virtual register, it might be defined by a VSET(I)VLI. If
197 // it has the same VLMAX we want and the last VL/VTYPE we observed is the
198 // same, we can use the X0, X0 form.
199 if (Info.hasSameVLMAX(Other: PrevInfo) && Info.hasAVLReg()) {
200 if (const MachineInstr *DefMI = Info.getAVLDefMI(LIS);
201 DefMI && RISCVInstrInfo::isVectorConfigInstr(MI: *DefMI)) {
202 VSETVLIInfo DefInfo = VIA.getInfoForVSETVLI(MI: *DefMI);
203 if (DefInfo.hasSameAVL(Other: PrevInfo) && DefInfo.hasSameVLMAX(Other: PrevInfo)) {
204 auto MI =
205 BuildMI(BB&: MBB, I: InsertPt, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoVSETVLIX0X0))
206 .addReg(RegNo: RISCV::X0, Flags: RegState::Define | RegState::Dead)
207 .addReg(RegNo: RISCV::X0, Flags: RegState::Kill)
208 .addImm(Val: Info.encodeVTYPE())
209 .addReg(RegNo: RISCV::VL, Flags: RegState::Implicit);
210 if (LIS)
211 LIS->InsertMachineInstrInMaps(MI&: *MI);
212 return;
213 }
214 }
215 }
216 }
217
218 if (Info.hasAVLImm()) {
219 auto MI = BuildMI(BB&: MBB, I: InsertPt, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoVSETIVLI))
220 .addReg(RegNo: RISCV::X0, Flags: RegState::Define | RegState::Dead)
221 .addImm(Val: Info.getAVLImm())
222 .addImm(Val: Info.encodeVTYPE());
223 if (LIS)
224 LIS->InsertMachineInstrInMaps(MI&: *MI);
225 return;
226 }
227
228 if (Info.hasAVLVLMAX()) {
229 Register DestReg = MRI->createVirtualRegister(RegClass: &RISCV::GPRNoX0RegClass);
230 auto MI = BuildMI(BB&: MBB, I: InsertPt, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoVSETVLIX0))
231 .addReg(RegNo: DestReg, Flags: RegState::Define | RegState::Dead)
232 .addReg(RegNo: RISCV::X0, Flags: RegState::Kill)
233 .addImm(Val: Info.encodeVTYPE());
234 if (LIS) {
235 LIS->InsertMachineInstrInMaps(MI&: *MI);
236 LIS->createAndComputeVirtRegInterval(Reg: DestReg);
237 }
238 return;
239 }
240
241 Register AVLReg = Info.getAVLReg();
242 MRI->constrainRegClass(Reg: AVLReg, RC: &RISCV::GPRNoX0RegClass);
243 auto MI = BuildMI(BB&: MBB, I: InsertPt, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoVSETVLI))
244 .addReg(RegNo: RISCV::X0, Flags: RegState::Define | RegState::Dead)
245 .addReg(RegNo: AVLReg)
246 .addImm(Val: Info.encodeVTYPE());
247 if (LIS) {
248 LIS->InsertMachineInstrInMaps(MI&: *MI);
249 LiveInterval &LI = LIS->getInterval(Reg: AVLReg);
250 SlotIndex SI = LIS->getInstructionIndex(Instr: *MI).getRegSlot();
251 const VNInfo *CurVNI = Info.getAVLVNInfo();
252 // If the AVL value isn't live at MI, do a quick check to see if it's easily
253 // extendable. Otherwise, we need to copy it.
254 if (LI.getVNInfoBefore(Idx: SI) != CurVNI) {
255 if (!LI.liveAt(index: SI) && LI.containsOneValue())
256 LIS->extendToIndices(LR&: LI, Indices: SI);
257 else {
258 Register AVLCopyReg =
259 MRI->createVirtualRegister(RegClass: &RISCV::GPRNoX0RegClass);
260 MachineBasicBlock *MBB = LIS->getMBBFromIndex(index: CurVNI->def);
261 MachineBasicBlock::iterator II;
262 if (CurVNI->isPHIDef())
263 II = MBB->getFirstNonPHI();
264 else {
265 II = LIS->getInstructionFromIndex(index: CurVNI->def);
266 II = std::next(x: II);
267 }
268 assert(II.isValid());
269 auto AVLCopy = BuildMI(BB&: *MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::COPY), DestReg: AVLCopyReg)
270 .addReg(RegNo: AVLReg);
271 LIS->InsertMachineInstrInMaps(MI&: *AVLCopy);
272 MI->getOperand(i: 1).setReg(AVLCopyReg);
273 LIS->createAndComputeVirtRegInterval(Reg: AVLCopyReg);
274 }
275 }
276 }
277}
278
279/// Return true if a VSETVLI is required to transition from CurInfo to Require
280/// given a set of DemandedFields \p Used.
281bool RISCVInsertVSETVLI::needVSETVLI(const DemandedFields &Used,
282 const VSETVLIInfo &Require,
283 const VSETVLIInfo &CurInfo) const {
284 if (!CurInfo.isValid() || CurInfo.isUnknown() || CurInfo.hasSEWLMULRatioOnly())
285 return true;
286
287 if (CurInfo.isCompatible(Used, Require, LIS))
288 return false;
289
290 return true;
291}
292
293// If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we
294// maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more
295// places.
296static VSETVLIInfo adjustIncoming(const VSETVLIInfo &PrevInfo,
297 const VSETVLIInfo &NewInfo,
298 DemandedFields &Demanded) {
299 VSETVLIInfo Info = NewInfo;
300
301 if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() &&
302 !PrevInfo.isUnknown()) {
303 if (auto NewVLMul = RISCVVType::getSameRatioLMUL(Ratio: PrevInfo.getSEWLMULRatio(),
304 EEW: Info.getSEW()))
305 Info.setVLMul(*NewVLMul);
306 Demanded.LMUL = DemandedFields::LMULEqual;
307 }
308
309 return Info;
310}
311
312// Given an incoming state reaching MI, minimally modifies that state so that it
313// is compatible with MI. The resulting state is guaranteed to be semantically
314// legal for MI, but may not be the state requested by MI.
315void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
316 const MachineInstr &MI) const {
317 if (RISCV::isVectorCopy(TRI: ST->getRegisterInfo(), MI) &&
318 (Info.isUnknown() || !Info.isValid() || Info.hasSEWLMULRatioOnly())) {
319 // Use an arbitrary but valid AVL and VTYPE so vill will be cleared. It may
320 // be coalesced into another vsetvli since we won't demand any fields.
321 VSETVLIInfo NewInfo; // Need a new VSETVLIInfo to clear SEWLMULRatioOnly
322 NewInfo.setAVLImm(1);
323 NewInfo.setVTYPE(L: RISCVVType::LMUL_1, /*sew*/ S: 8, /*ta*/ TA: true, /*ma*/ MA: true,
324 /*AltFmt*/ Altfmt: false, /*W*/ 0);
325 Info = NewInfo;
326 return;
327 }
328
329 if (!RISCVII::hasSEWOp(TSFlags: MI.getDesc().TSFlags))
330 return;
331
332 DemandedFields Demanded = getDemanded(MI, ST);
333
334 const VSETVLIInfo NewInfo = VIA.computeInfoForInstr(MI);
335 assert(NewInfo.isValid() && !NewInfo.isUnknown());
336 if (Info.isValid() && !needVSETVLI(Used: Demanded, Require: NewInfo, CurInfo: Info))
337 return;
338
339 const VSETVLIInfo PrevInfo = Info;
340 if (!Info.isValid() || Info.isUnknown())
341 Info = NewInfo;
342
343 const VSETVLIInfo IncomingInfo = adjustIncoming(PrevInfo, NewInfo, Demanded);
344
345 // If MI only demands that VL has the same zeroness, we only need to set the
346 // AVL if the zeroness differs. This removes a vsetvli entirely if the types
347 // match or allows use of cheaper avl preserving variant if VLMAX doesn't
348 // change. If VLMAX might change, we couldn't use the 'vsetvli x0, x0, vtype"
349 // variant, so we avoid the transform to prevent extending live range of an
350 // avl register operand.
351 // TODO: We can probably relax this for immediates.
352 bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(Other: PrevInfo, LIS) &&
353 IncomingInfo.hasSameVLMAX(Other: PrevInfo);
354 if (Demanded.VLAny || (Demanded.VLZeroness && !EquallyZero))
355 Info.setAVL(IncomingInfo);
356
357 // If we only knew the sew/lmul ratio previously, replace the VTYPE.
358 if (Info.hasSEWLMULRatioOnly()) {
359 VSETVLIInfo RatiolessInfo = IncomingInfo;
360 RatiolessInfo.setAVL(Info);
361 Info = RatiolessInfo;
362 } else {
363 Info.setVTYPE(
364 L: ((Demanded.LMUL || Demanded.SEWLMULRatio) ? IncomingInfo : Info)
365 .getVLMUL(),
366 S: ((Demanded.SEW || Demanded.SEWLMULRatio) ? IncomingInfo : Info)
367 .getSEW(),
368 // Prefer tail/mask agnostic since it can be relaxed to undisturbed
369 // later if needed.
370 TA: (Demanded.TailPolicy ? IncomingInfo : Info).getTailAgnostic() ||
371 IncomingInfo.getTailAgnostic(),
372 MA: (Demanded.MaskPolicy ? IncomingInfo : Info).getMaskAgnostic() ||
373 IncomingInfo.getMaskAgnostic(),
374 Altfmt: (Demanded.AltFmt ? IncomingInfo : Info).getAltFmt(),
375 W: Demanded.TWiden ? IncomingInfo.getTWiden() : 0);
376 }
377}
378
379// Given a state with which we evaluated MI (see transferBefore above for why
380// this might be different that the state MI requested), modify the state to
381// reflect the changes MI might make.
382void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
383 const MachineInstr &MI) const {
384 if (RISCVInstrInfo::isVectorConfigInstr(MI)) {
385 Info = VIA.getInfoForVSETVLI(MI);
386 return;
387 }
388
389 if (RISCVInstrInfo::isFaultOnlyFirstLoad(MI)) {
390 // Update AVL to vl-output of the fault first load.
391 assert(MI.getOperand(1).getReg().isVirtual());
392 if (LIS) {
393 auto &LI = LIS->getInterval(Reg: MI.getOperand(i: 1).getReg());
394 SlotIndex SI =
395 LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
396 VNInfo *VNI = LI.getVNInfoAt(Idx: SI);
397 Info.setAVLRegDef(VNInfo: VNI, AVLReg: MI.getOperand(i: 1).getReg());
398 } else
399 Info.setAVLRegDef(VNInfo: nullptr, AVLReg: MI.getOperand(i: 1).getReg());
400 return;
401 }
402
403 // If this is something that updates VL/VTYPE that we don't know about, set
404 // the state to unknown.
405 if (MI.isCall() || MI.isInlineAsm() ||
406 MI.modifiesRegister(Reg: RISCV::VL, /*TRI=*/nullptr) ||
407 MI.modifiesRegister(Reg: RISCV::VTYPE, /*TRI=*/nullptr))
408 Info = VSETVLIInfo::getUnknown();
409}
410
411bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB,
412 VSETVLIInfo &Info) const {
413 bool HadVectorOp = false;
414
415 Info = BlockInfo[MBB.getNumber()].Pred;
416 for (const MachineInstr &MI : MBB) {
417 transferBefore(Info, MI);
418
419 if (RISCVInstrInfo::isVectorConfigInstr(MI) ||
420 RISCVII::hasSEWOp(TSFlags: MI.getDesc().TSFlags) ||
421 RISCV::isVectorCopy(TRI: ST->getRegisterInfo(), MI) ||
422 RISCVInstrInfo::isXSfmmVectorConfigInstr(MI))
423 HadVectorOp = true;
424
425 transferAfter(Info, MI);
426 }
427
428 return HadVectorOp;
429}
430
431void RISCVInsertVSETVLI::computeIncomingVLVTYPE(const MachineBasicBlock &MBB) {
432
433 BlockData &BBInfo = BlockInfo[MBB.getNumber()];
434
435 BBInfo.InQueue = false;
436
437 // Start with the previous entry so that we keep the most conservative state
438 // we have ever found.
439 VSETVLIInfo InInfo = BBInfo.Pred;
440 if (MBB.pred_empty()) {
441 // There are no predecessors, so use the default starting status.
442 InInfo.setUnknown();
443 } else {
444 for (MachineBasicBlock *P : MBB.predecessors())
445 InInfo = InInfo.intersect(Other: BlockInfo[P->getNumber()].Exit);
446 }
447
448 // If we don't have any valid predecessor value, wait until we do.
449 if (!InInfo.isValid())
450 return;
451
452 // If no change, no need to rerun block
453 if (InInfo == BBInfo.Pred)
454 return;
455
456 BBInfo.Pred = InInfo;
457 LLVM_DEBUG(dbgs() << "Entry state of " << printMBBReference(MBB)
458 << " changed to " << BBInfo.Pred << "\n");
459
460 // Note: It's tempting to cache the state changes here, but due to the
461 // compatibility checks performed a blocks output state can change based on
462 // the input state. To cache, we'd have to add logic for finding
463 // never-compatible state changes.
464 VSETVLIInfo TmpStatus;
465 computeVLVTYPEChanges(MBB, Info&: TmpStatus);
466
467 // If the new exit value matches the old exit value, we don't need to revisit
468 // any blocks.
469 if (BBInfo.Exit == TmpStatus)
470 return;
471
472 BBInfo.Exit = TmpStatus;
473 LLVM_DEBUG(dbgs() << "Exit state of " << printMBBReference(MBB)
474 << " changed to " << BBInfo.Exit << "\n");
475
476 // Add the successors to the work list so we can propagate the changed exit
477 // status.
478 for (MachineBasicBlock *S : MBB.successors())
479 if (!BlockInfo[S->getNumber()].InQueue) {
480 BlockInfo[S->getNumber()].InQueue = true;
481 WorkList.push(x: S);
482 }
483}
484
485// If we weren't able to prove a vsetvli was directly unneeded, it might still
486// be unneeded if the AVL was a phi node where all incoming values are VL
487// outputs from the last VSETVLI in their respective basic blocks.
488bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
489 const MachineBasicBlock &MBB) const {
490 if (!Require.hasAVLReg())
491 return true;
492
493 if (!LIS)
494 return true;
495
496 // We need the AVL to have been produced by a PHI node in this basic block.
497 const VNInfo *Valno = Require.getAVLVNInfo();
498 if (!Valno->isPHIDef() || LIS->getMBBFromIndex(index: Valno->def) != &MBB)
499 return true;
500
501 const LiveRange &LR = LIS->getInterval(Reg: Require.getAVLReg());
502
503 for (auto *PBB : MBB.predecessors()) {
504 const VSETVLIInfo &PBBExit = BlockInfo[PBB->getNumber()].Exit;
505
506 // We need the PHI input to the be the output of a VSET(I)VLI.
507 const VNInfo *Value = LR.getVNInfoBefore(Idx: LIS->getMBBEndIdx(mbb: PBB));
508 if (!Value)
509 return true;
510 MachineInstr *DefMI = LIS->getInstructionFromIndex(index: Value->def);
511 if (!DefMI || !RISCVInstrInfo::isVectorConfigInstr(MI: *DefMI))
512 return true;
513
514 // We found a VSET(I)VLI make sure it matches the output of the
515 // predecessor block.
516 VSETVLIInfo DefInfo = VIA.getInfoForVSETVLI(MI: *DefMI);
517 if (DefInfo != PBBExit)
518 return true;
519
520 // Require has the same VL as PBBExit, so if the exit from the
521 // predecessor has the VTYPE we are looking for we might be able
522 // to avoid a VSETVLI.
523 if (PBBExit.isUnknown() || !PBBExit.hasSameVTYPE(Other: Require))
524 return true;
525 }
526
527 // If all the incoming values to the PHI checked out, we don't need
528 // to insert a VSETVLI.
529 return false;
530}
531
532void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
533 VSETVLIInfo CurInfo = BlockInfo[MBB.getNumber()].Pred;
534 // Track whether the prefix of the block we've scanned is transparent
535 // (meaning has not yet changed the abstract state).
536 bool PrefixTransparent = true;
537 for (MachineInstr &MI : MBB) {
538 const VSETVLIInfo PrevInfo = CurInfo;
539 transferBefore(Info&: CurInfo, MI);
540
541 // If this is an explicit VSETVLI or VSETIVLI, update our state.
542 if (RISCVInstrInfo::isVectorConfigInstr(MI)) {
543 // Conservatively, mark the VL and VTYPE as live.
544 assert(MI.getOperand(3).getReg() == RISCV::VL &&
545 MI.getOperand(4).getReg() == RISCV::VTYPE &&
546 "Unexpected operands where VL and VTYPE should be");
547 MI.getOperand(i: 3).setIsDead(false);
548 MI.getOperand(i: 4).setIsDead(false);
549 PrefixTransparent = false;
550 }
551
552 if (EnsureWholeVectorRegisterMoveValidVTYPE &&
553 RISCV::isVectorCopy(TRI: ST->getRegisterInfo(), MI)) {
554 if (!PrevInfo.isCompatible(Used: DemandedFields::all(), Require: CurInfo, LIS)) {
555 insertVSETVLI(MBB, InsertPt: MI, DL: MI.getDebugLoc(), Info: CurInfo, PrevInfo);
556 PrefixTransparent = false;
557 }
558 MI.addOperand(Op: MachineOperand::CreateReg(Reg: RISCV::VTYPE, /*isDef*/ false,
559 /*isImp*/ true));
560 }
561
562 uint64_t TSFlags = MI.getDesc().TSFlags;
563 if (RISCVII::hasSEWOp(TSFlags)) {
564 if (!PrevInfo.isCompatible(Used: DemandedFields::all(), Require: CurInfo, LIS)) {
565 // If this is the first implicit state change, and the state change
566 // requested can be proven to produce the same register contents, we
567 // can skip emitting the actual state change and continue as if we
568 // had since we know the GPR result of the implicit state change
569 // wouldn't be used and VL/VTYPE registers are correct. Note that
570 // we *do* need to model the state as if it changed as while the
571 // register contents are unchanged, the abstract model can change.
572 if (!PrefixTransparent || needVSETVLIPHI(Require: CurInfo, MBB))
573 insertVSETVLI(MBB, InsertPt: MI, DL: MI.getDebugLoc(), Info: CurInfo, PrevInfo);
574 PrefixTransparent = false;
575 }
576
577 if (RISCVII::hasVLOp(TSFlags)) {
578 MachineOperand &VLOp = MI.getOperand(i: getVLOpNum(MI));
579 if (VLOp.isReg()) {
580 Register Reg = VLOp.getReg();
581
582 // Erase the AVL operand from the instruction.
583 VLOp.setReg(Register());
584 VLOp.setIsKill(false);
585 if (LIS) {
586 LiveInterval &LI = LIS->getInterval(Reg);
587 SmallVector<MachineInstr *> DeadMIs;
588 LIS->shrinkToUses(li: &LI, dead: &DeadMIs);
589 // We might have separate components that need split due to
590 // needVSETVLIPHI causing us to skip inserting a new VL def.
591 SmallVector<LiveInterval *> SplitLIs;
592 LIS->splitSeparateComponents(LI, SplitLIs);
593
594 // If the AVL was an immediate > 31, then it would have been emitted
595 // as an ADDI. However, the ADDI might not have been used in the
596 // vsetvli, or a vsetvli might not have been emitted, so it may be
597 // dead now.
598 for (MachineInstr *DeadMI : DeadMIs) {
599 if (!TII->isAddImmediate(MI: *DeadMI, Reg))
600 continue;
601 LIS->RemoveMachineInstrFromMaps(MI&: *DeadMI);
602 Register AddReg = DeadMI->getOperand(i: 1).getReg();
603 DeadMI->eraseFromParent();
604 if (AddReg.isVirtual())
605 LIS->shrinkToUses(li: &LIS->getInterval(Reg: AddReg));
606 }
607 }
608 }
609 MI.addOperand(Op: MachineOperand::CreateReg(Reg: RISCV::VL, /*isDef*/ false,
610 /*isImp*/ true));
611 }
612 MI.addOperand(Op: MachineOperand::CreateReg(Reg: RISCV::VTYPE, /*isDef*/ false,
613 /*isImp*/ true));
614 }
615
616 if (MI.isInlineAsm()) {
617 MI.addOperand(Op: MachineOperand::CreateReg(Reg: RISCV::VL, /*isDef*/ true,
618 /*isImp*/ true));
619 MI.addOperand(Op: MachineOperand::CreateReg(Reg: RISCV::VTYPE, /*isDef*/ true,
620 /*isImp*/ true));
621 }
622
623 if (MI.isCall() || MI.isInlineAsm() ||
624 MI.modifiesRegister(Reg: RISCV::VL, /*TRI=*/nullptr) ||
625 MI.modifiesRegister(Reg: RISCV::VTYPE, /*TRI=*/nullptr))
626 PrefixTransparent = false;
627
628 transferAfter(Info&: CurInfo, MI);
629 }
630
631 const auto &Info = BlockInfo[MBB.getNumber()];
632 if (CurInfo != Info.Exit) {
633 LLVM_DEBUG(dbgs() << "in block " << printMBBReference(MBB) << "\n");
634 LLVM_DEBUG(dbgs() << " begin state: " << Info.Pred << "\n");
635 LLVM_DEBUG(dbgs() << " expected end state: " << Info.Exit << "\n");
636 LLVM_DEBUG(dbgs() << " actual end state: " << CurInfo << "\n");
637 }
638 assert(CurInfo == Info.Exit && "InsertVSETVLI dataflow invariant violated");
639}
640
641/// Perform simple partial redundancy elimination of the VSETVLI instructions
642/// we're about to insert by looking for cases where we can PRE from the
643/// beginning of one block to the end of one of its predecessors. Specifically,
644/// this is geared to catch the common case of a fixed length vsetvl in a single
645/// block loop when it could execute once in the preheader instead.
646void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
647 if (!BlockInfo[MBB.getNumber()].Pred.isUnknown())
648 return;
649
650 MachineBasicBlock *UnavailablePred = nullptr;
651 VSETVLIInfo AvailableInfo;
652 for (MachineBasicBlock *P : MBB.predecessors()) {
653 const VSETVLIInfo &PredInfo = BlockInfo[P->getNumber()].Exit;
654 if (PredInfo.isUnknown()) {
655 if (UnavailablePred)
656 return;
657 UnavailablePred = P;
658 } else if (!AvailableInfo.isValid()) {
659 AvailableInfo = PredInfo;
660 } else if (AvailableInfo != PredInfo) {
661 return;
662 }
663 }
664
665 // Unreachable, single pred, or full redundancy. Note that FRE is handled by
666 // phase 3.
667 if (!UnavailablePred || !AvailableInfo.isValid())
668 return;
669
670 if (!LIS)
671 return;
672
673 // If we don't know the exact VTYPE, we can't copy the vsetvli to the exit of
674 // the unavailable pred.
675 if (AvailableInfo.hasSEWLMULRatioOnly())
676 return;
677
678 // Critical edge - TODO: consider splitting?
679 if (UnavailablePred->succ_size() != 1)
680 return;
681
682 // If the AVL value is a register (other than our VLMAX sentinel),
683 // we need to prove the value is available at the point we're going
684 // to insert the vsetvli at.
685 if (AvailableInfo.hasAVLReg()) {
686 SlotIndex SI = AvailableInfo.getAVLVNInfo()->def;
687 // This is an inline dominance check which covers the case of
688 // UnavailablePred being the preheader of a loop.
689 if (LIS->getMBBFromIndex(index: SI) != UnavailablePred)
690 return;
691 if (!UnavailablePred->terminators().empty() &&
692 SI >= LIS->getInstructionIndex(Instr: *UnavailablePred->getFirstTerminator()))
693 return;
694 }
695
696 // Model the effect of changing the input state of the block MBB to
697 // AvailableInfo. We're looking for two issues here; one legality,
698 // one profitability.
699 // 1) If the block doesn't use some of the fields from VL or VTYPE, we
700 // may hit the end of the block with a different end state. We can
701 // not make this change without reflowing later blocks as well.
702 // 2) If we don't actually remove a transition, inserting a vsetvli
703 // into the predecessor block would be correct, but unprofitable.
704 VSETVLIInfo OldInfo = BlockInfo[MBB.getNumber()].Pred;
705 VSETVLIInfo CurInfo = AvailableInfo;
706 int TransitionsRemoved = 0;
707 for (const MachineInstr &MI : MBB) {
708 const VSETVLIInfo LastInfo = CurInfo;
709 const VSETVLIInfo LastOldInfo = OldInfo;
710 transferBefore(Info&: CurInfo, MI);
711 transferBefore(Info&: OldInfo, MI);
712 if (CurInfo == LastInfo)
713 TransitionsRemoved++;
714 if (LastOldInfo == OldInfo)
715 TransitionsRemoved--;
716 transferAfter(Info&: CurInfo, MI);
717 transferAfter(Info&: OldInfo, MI);
718 if (CurInfo == OldInfo)
719 // Convergence. All transitions after this must match by construction.
720 break;
721 }
722 if (CurInfo != OldInfo || TransitionsRemoved <= 0)
723 // Issues 1 and 2 above
724 return;
725
726 // Finally, update both data flow state and insert the actual vsetvli.
727 // Doing both keeps the code in sync with the dataflow results, which
728 // is critical for correctness of phase 3.
729 auto OldExit = BlockInfo[UnavailablePred->getNumber()].Exit;
730 LLVM_DEBUG(dbgs() << "PRE VSETVLI from " << MBB.getName() << " to "
731 << UnavailablePred->getName() << " with state "
732 << AvailableInfo << "\n");
733 BlockInfo[UnavailablePred->getNumber()].Exit = AvailableInfo;
734 BlockInfo[MBB.getNumber()].Pred = AvailableInfo;
735
736 // Note there's an implicit assumption here that terminators never use
737 // or modify VL or VTYPE. Also, fallthrough will return end().
738 auto InsertPt = UnavailablePred->getFirstInstrTerminator();
739 insertVSETVLI(MBB&: *UnavailablePred, InsertPt,
740 DL: UnavailablePred->findDebugLoc(MBBI: InsertPt),
741 Info: AvailableInfo, PrevInfo: OldExit);
742}
743
744// Return true if we can mutate PrevMI to match MI without changing any the
745// fields which would be observed.
746bool RISCVInsertVSETVLI::canMutatePriorConfig(
747 const MachineInstr &PrevMI, const MachineInstr &MI,
748 const DemandedFields &Used) const {
749 // If the VL values aren't equal, return false if either a) the former is
750 // demanded, or b) we can't rewrite the former to be the later for
751 // implementation reasons.
752 if (!RISCVInstrInfo::isVLPreservingConfig(MI)) {
753 if (Used.VLAny)
754 return false;
755
756 if (Used.VLZeroness) {
757 if (RISCVInstrInfo::isVLPreservingConfig(MI: PrevMI))
758 return false;
759 if (!VIA.getInfoForVSETVLI(MI: PrevMI).hasEquallyZeroAVL(
760 Other: VIA.getInfoForVSETVLI(MI), LIS))
761 return false;
762 }
763
764 auto &AVL = MI.getOperand(i: 1);
765
766 // If the AVL is a register, we need to make sure its definition is the same
767 // at PrevMI as it was at MI.
768 if (AVL.isReg() && AVL.getReg() != RISCV::X0) {
769 VNInfo *VNI = getVNInfoFromReg(Reg: AVL.getReg(), MI, LIS);
770 VNInfo *PrevVNI = getVNInfoFromReg(Reg: AVL.getReg(), MI: PrevMI, LIS);
771 if (!VNI || !PrevVNI || VNI != PrevVNI)
772 return false;
773 }
774
775 // If we define VL and need to move the definition up, check we can extend
776 // the live interval upwards from MI to PrevMI.
777 Register VL = MI.getOperand(i: 0).getReg();
778 if (VL.isVirtual() && LIS &&
779 LIS->getInterval(Reg: VL).overlaps(Start: LIS->getInstructionIndex(Instr: PrevMI),
780 End: LIS->getInstructionIndex(Instr: MI)))
781 return false;
782 }
783
784 assert(PrevMI.getOperand(2).isImm() && MI.getOperand(2).isImm());
785 auto PriorVType = PrevMI.getOperand(i: 2).getImm();
786 auto VType = MI.getOperand(i: 2).getImm();
787 return areCompatibleVTYPEs(CurVType: PriorVType, NewVType: VType, Used);
788}
789
790void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
791 MachineInstr *NextMI = nullptr;
792 // We can have arbitrary code in successors, so VL and VTYPE
793 // must be considered demanded.
794 DemandedFields Used;
795 Used.demandVL();
796 Used.demandVTYPE();
797 SmallVector<MachineInstr*> ToDelete;
798
799 auto dropAVLUse = [&](MachineOperand &MO) {
800 if (!MO.isReg() || !MO.getReg().isVirtual())
801 return;
802 Register OldVLReg = MO.getReg();
803 MO.setReg(Register());
804
805 if (LIS)
806 LIS->shrinkToUses(li: &LIS->getInterval(Reg: OldVLReg));
807
808 MachineInstr *VLOpDef = MRI->getUniqueVRegDef(Reg: OldVLReg);
809 if (VLOpDef && TII->isAddImmediate(MI: *VLOpDef, Reg: OldVLReg) &&
810 MRI->use_nodbg_empty(RegNo: OldVLReg))
811 ToDelete.push_back(Elt: VLOpDef);
812 };
813
814 for (MachineInstr &MI : make_early_inc_range(Range: reverse(C&: MBB))) {
815 // TODO: Support XSfmm.
816 if (RISCVII::hasTWidenOp(TSFlags: MI.getDesc().TSFlags) ||
817 RISCVInstrInfo::isXSfmmVectorConfigInstr(MI)) {
818 NextMI = nullptr;
819 continue;
820 }
821
822 if (!RISCVInstrInfo::isVectorConfigInstr(MI)) {
823 Used.doUnion(B: getDemanded(MI, ST));
824 if (MI.isCall() || MI.isInlineAsm() ||
825 MI.modifiesRegister(Reg: RISCV::VL, /*TRI=*/nullptr) ||
826 MI.modifiesRegister(Reg: RISCV::VTYPE, /*TRI=*/nullptr))
827 NextMI = nullptr;
828 continue;
829 }
830
831 if (!MI.getOperand(i: 0).isDead())
832 Used.demandVL();
833
834 if (NextMI) {
835 if (!Used.usedVL() && !Used.usedVTYPE()) {
836 dropAVLUse(MI.getOperand(i: 1));
837 if (LIS)
838 LIS->RemoveMachineInstrFromMaps(MI);
839 MI.eraseFromParent();
840 NumCoalescedVSETVL++;
841 // Leave NextMI unchanged
842 continue;
843 }
844
845 if (canMutatePriorConfig(PrevMI: MI, MI: *NextMI, Used)) {
846 if (!RISCVInstrInfo::isVLPreservingConfig(MI: *NextMI)) {
847 Register DefReg = NextMI->getOperand(i: 0).getReg();
848
849 MI.getOperand(i: 0).setReg(DefReg);
850 MI.getOperand(i: 0).setIsDead(false);
851
852 // Move the AVL from NextMI to MI
853 dropAVLUse(MI.getOperand(i: 1));
854 if (NextMI->getOperand(i: 1).isImm())
855 MI.getOperand(i: 1).ChangeToImmediate(ImmVal: NextMI->getOperand(i: 1).getImm());
856 else
857 MI.getOperand(i: 1).ChangeToRegister(Reg: NextMI->getOperand(i: 1).getReg(),
858 isDef: false);
859 dropAVLUse(NextMI->getOperand(i: 1));
860
861 // The def of DefReg moved to MI, so extend the LiveInterval up to
862 // it.
863 if (DefReg.isVirtual() && LIS) {
864 LiveInterval &DefLI = LIS->getInterval(Reg: DefReg);
865 SlotIndex MISlot = LIS->getInstructionIndex(Instr: MI).getRegSlot();
866 SlotIndex NextMISlot =
867 LIS->getInstructionIndex(Instr: *NextMI).getRegSlot();
868 VNInfo *DefVNI = DefLI.getVNInfoAt(Idx: NextMISlot);
869 LiveInterval::Segment S(MISlot, NextMISlot, DefVNI);
870 DefLI.addSegment(S);
871 DefVNI->def = MISlot;
872 // Mark DefLI as spillable if it was previously unspillable
873 DefLI.setWeight(0);
874
875 // DefReg may have had no uses, in which case we need to shrink
876 // the LiveInterval up to MI.
877 LIS->shrinkToUses(li: &DefLI);
878 }
879
880 MI.setDesc(NextMI->getDesc());
881 }
882 MI.getOperand(i: 2).setImm(NextMI->getOperand(i: 2).getImm());
883
884 dropAVLUse(NextMI->getOperand(i: 1));
885 if (LIS)
886 LIS->RemoveMachineInstrFromMaps(MI&: *NextMI);
887 NextMI->eraseFromParent();
888 NumCoalescedVSETVL++;
889 // fallthrough
890 }
891 }
892 NextMI = &MI;
893 Used = getDemanded(MI, ST);
894 }
895
896 // Loop over the dead AVL values, and delete them now. This has
897 // to be outside the above loop to avoid invalidating iterators.
898 for (auto *MI : ToDelete) {
899 assert(MI->getOpcode() == RISCV::ADDI);
900 Register AddReg = MI->getOperand(i: 1).getReg();
901 if (LIS) {
902 LIS->removeInterval(Reg: MI->getOperand(i: 0).getReg());
903 LIS->RemoveMachineInstrFromMaps(MI&: *MI);
904 }
905 MI->eraseFromParent();
906 if (LIS && AddReg.isVirtual())
907 LIS->shrinkToUses(li: &LIS->getInterval(Reg: AddReg));
908 }
909}
910
911void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
912 for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
913 MachineInstr &MI = *I++;
914 if (RISCVInstrInfo::isFaultOnlyFirstLoad(MI)) {
915 Register VLOutput = MI.getOperand(i: 1).getReg();
916 assert(VLOutput.isVirtual());
917 if (!MI.getOperand(i: 1).isDead()) {
918 auto ReadVLMI = BuildMI(BB&: MBB, I, MIMD: MI.getDebugLoc(),
919 MCID: TII->get(Opcode: RISCV::PseudoReadVL), DestReg: VLOutput);
920 // Move the LiveInterval's definition down to PseudoReadVL.
921 if (LIS) {
922 SlotIndex NewDefSI =
923 LIS->InsertMachineInstrInMaps(MI&: *ReadVLMI).getRegSlot();
924 LiveInterval &DefLI = LIS->getInterval(Reg: VLOutput);
925 LiveRange::Segment *DefSeg = DefLI.getSegmentContaining(Idx: NewDefSI);
926 VNInfo *DefVNI = DefLI.getVNInfoAt(Idx: DefSeg->start);
927 DefLI.removeSegment(Start: DefSeg->start, End: NewDefSI);
928 DefVNI->def = NewDefSI;
929 }
930 }
931 // We don't use the vl output of the VLEFF/VLSEGFF anymore.
932 MI.getOperand(i: 1).setReg(RISCV::X0);
933 MI.addRegisterDefined(Reg: RISCV::VL, RegInfo: MRI->getTargetRegisterInfo());
934 }
935 }
936}
937
938bool RISCVInsertVSETVLI::insertVSETMTK(MachineBasicBlock &MBB,
939 TKTMMode Mode) const {
940
941 bool Changed = false;
942 for (auto &MI : MBB) {
943 uint64_t TSFlags = MI.getDesc().TSFlags;
944 if (RISCVInstrInfo::isXSfmmVectorConfigTMTKInstr(MI) ||
945 !RISCVII::hasSEWOp(TSFlags) || !RISCVII::hasTWidenOp(TSFlags))
946 continue;
947
948 VSETVLIInfo CurrInfo = VIA.computeInfoForInstr(MI);
949
950 if (Mode == VSETTK && !RISCVII::hasTKOp(TSFlags))
951 continue;
952
953 if (Mode == VSETTM && !RISCVII::hasTMOp(TSFlags))
954 continue;
955
956 unsigned OpNum = 0;
957 unsigned Opcode = 0;
958 switch (Mode) {
959 case VSETTK:
960 OpNum = RISCVII::getTKOpNum(Desc: MI.getDesc());
961 Opcode = RISCV::PseudoSF_VSETTK;
962 break;
963 case VSETTM:
964 OpNum = RISCVII::getTMOpNum(Desc: MI.getDesc());
965 Opcode = RISCV::PseudoSF_VSETTM;
966 break;
967 }
968
969 assert(OpNum && Opcode && "Invalid OpNum or Opcode");
970
971 MachineOperand &Op = MI.getOperand(i: OpNum);
972
973 auto TmpMI = BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode))
974 .addReg(RegNo: RISCV::X0, Flags: RegState::Define | RegState::Dead)
975 .addReg(RegNo: Op.getReg())
976 .addImm(Val: Log2_32(Value: CurrInfo.getSEW()))
977 .addImm(Val: CurrInfo.getTWiden());
978
979 Changed = true;
980 Register Reg = Op.getReg();
981 Op.setReg(Register());
982 Op.setIsKill(false);
983 if (LIS) {
984 LIS->InsertMachineInstrInMaps(MI&: *TmpMI);
985 LiveInterval &LI = LIS->getInterval(Reg);
986
987 // Erase the AVL operand from the instruction.
988 LIS->shrinkToUses(li: &LI);
989 // TODO: Enable this once needVSETVLIPHI is supported.
990 // SmallVector<LiveInterval *> SplitLIs;
991 // LIS->splitSeparateComponents(LI, SplitLIs);
992 }
993 }
994 return Changed;
995}
996
997bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
998 // Skip if the vector extension is not enabled.
999 ST = &MF.getSubtarget<RISCVSubtarget>();
1000 if (!ST->hasVInstructions())
1001 return false;
1002
1003 LLVM_DEBUG(dbgs() << "Entering InsertVSETVLI for " << MF.getName() << "\n");
1004
1005 TII = ST->getInstrInfo();
1006 MRI = &MF.getRegInfo();
1007 auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
1008 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
1009 VIA = RISCVVSETVLIInfoAnalysis(ST, LIS);
1010
1011 assert(BlockInfo.empty() && "Expect empty block infos");
1012 BlockInfo.resize(new_size: MF.getNumBlockIDs());
1013
1014 bool HaveVectorOp = false;
1015
1016 // Phase 1 - determine how VL/VTYPE are affected by the each block.
1017 for (const MachineBasicBlock &MBB : MF) {
1018 VSETVLIInfo TmpStatus;
1019 HaveVectorOp |= computeVLVTYPEChanges(MBB, Info&: TmpStatus);
1020 // Initial exit state is whatever change we found in the block.
1021 BlockData &BBInfo = BlockInfo[MBB.getNumber()];
1022 BBInfo.Exit = TmpStatus;
1023 LLVM_DEBUG(dbgs() << "Initial exit state of " << printMBBReference(MBB)
1024 << " is " << BBInfo.Exit << "\n");
1025
1026 }
1027
1028 // If we didn't find any instructions that need VSETVLI, we're done.
1029 if (!HaveVectorOp) {
1030 BlockInfo.clear();
1031 return false;
1032 }
1033
1034 // Phase 2 - determine the exit VL/VTYPE from each block. We add all
1035 // blocks to the list here, but will also add any that need to be revisited
1036 // during Phase 2 processing.
1037 for (const MachineBasicBlock &MBB : MF) {
1038 WorkList.push(x: &MBB);
1039 BlockInfo[MBB.getNumber()].InQueue = true;
1040 }
1041 while (!WorkList.empty()) {
1042 const MachineBasicBlock &MBB = *WorkList.front();
1043 WorkList.pop();
1044 computeIncomingVLVTYPE(MBB);
1045 }
1046
1047 // Perform partial redundancy elimination of vsetvli transitions.
1048 for (MachineBasicBlock &MBB : MF)
1049 doPRE(MBB);
1050
1051 // Phase 3 - add any vsetvli instructions needed in the block. Use the
1052 // Phase 2 information to avoid adding vsetvlis before the first vector
1053 // instruction in the block if the VL/VTYPE is satisfied by its
1054 // predecessors.
1055 for (MachineBasicBlock &MBB : MF)
1056 emitVSETVLIs(MBB);
1057
1058 // Now that all vsetvlis are explicit, go through and do block local
1059 // DSE and peephole based demanded fields based transforms. Note that
1060 // this *must* be done outside the main dataflow so long as we allow
1061 // any cross block analysis within the dataflow. We can't have both
1062 // demanded fields based mutation and non-local analysis in the
1063 // dataflow at the same time without introducing inconsistencies.
1064 // We're visiting blocks from the bottom up because a VSETVLI in the
1065 // earlier block might become dead when its uses in later blocks are
1066 // optimized away.
1067 for (MachineBasicBlock *MBB : post_order(G: &MF))
1068 coalesceVSETVLIs(MBB&: *MBB);
1069
1070 // Insert PseudoReadVL after VLEFF/VLSEGFF and replace it with the vl output
1071 // of VLEFF/VLSEGFF.
1072 for (MachineBasicBlock &MBB : MF)
1073 insertReadVL(MBB);
1074
1075 for (MachineBasicBlock &MBB : MF) {
1076 insertVSETMTK(MBB, Mode: VSETTM);
1077 insertVSETMTK(MBB, Mode: VSETTK);
1078 }
1079
1080 BlockInfo.clear();
1081 return HaveVectorOp;
1082}
1083
1084/// Returns an instance of the Insert VSETVLI pass.
1085FunctionPass *llvm::createRISCVInsertVSETVLIPass() {
1086 return new RISCVInsertVSETVLI();
1087}
1088