| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Assembly Writer Source Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* From: Mips.td *| |
| 7 | |* *| |
| 8 | \*===----------------------------------------------------------------------===*/ |
| 9 | |
| 10 | /// getMnemonic - This method is automatically generated by tablegen |
| 11 | /// from the instruction set description. |
| 12 | std::pair<const char *, uint64_t> |
| 13 | MipsInstPrinter::getMnemonic(const MCInst &MI) const { |
| 14 | |
| 15 | #ifdef __GNUC__ |
| 16 | #pragma GCC diagnostic push |
| 17 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 18 | #endif |
| 19 | static const char AsmStrs[] = { |
| 20 | /* 0 */ "dmfc0\t\000" |
| 21 | /* 7 */ "dmfgc0\t\000" |
| 22 | /* 15 */ "mfhgc0\t\000" |
| 23 | /* 23 */ "mthgc0\t\000" |
| 24 | /* 31 */ "dmtgc0\t\000" |
| 25 | /* 39 */ "mfhc0\t\000" |
| 26 | /* 46 */ "mthc0\t\000" |
| 27 | /* 53 */ "dmtc0\t\000" |
| 28 | /* 60 */ "vmm0\t\000" |
| 29 | /* 66 */ "mtm0\t\000" |
| 30 | /* 72 */ "mtp0\t\000" |
| 31 | /* 78 */ "bbit0\t\000" |
| 32 | /* 85 */ "ldc1\t\000" |
| 33 | /* 91 */ "sdc1\t\000" |
| 34 | /* 97 */ "cfc1\t\000" |
| 35 | /* 103 */ "dmfc1\t\000" |
| 36 | /* 110 */ "mfhc1\t\000" |
| 37 | /* 117 */ "mthc1\t\000" |
| 38 | /* 124 */ "ctc1\t\000" |
| 39 | /* 130 */ "dmtc1\t\000" |
| 40 | /* 137 */ "lwc1\t\000" |
| 41 | /* 143 */ "swc1\t\000" |
| 42 | /* 149 */ "ldxc1\t\000" |
| 43 | /* 156 */ "sdxc1\t\000" |
| 44 | /* 163 */ "luxc1\t\000" |
| 45 | /* 170 */ "suxc1\t\000" |
| 46 | /* 177 */ "lwxc1\t\000" |
| 47 | /* 184 */ "swxc1\t\000" |
| 48 | /* 191 */ "mtm1\t\000" |
| 49 | /* 197 */ "mtp1\t\000" |
| 50 | /* 203 */ "bbit1\t\000" |
| 51 | /* 210 */ "bbit032\t\000" |
| 52 | /* 219 */ "bbit132\t\000" |
| 53 | /* 228 */ "dsra32\t\000" |
| 54 | /* 236 */ "bposge32\t\000" |
| 55 | /* 246 */ "dsll32\t\000" |
| 56 | /* 254 */ "dsrl32\t\000" |
| 57 | /* 262 */ "lwm32\t\000" |
| 58 | /* 269 */ "swm32\t\000" |
| 59 | /* 276 */ "drotr32\t\000" |
| 60 | /* 285 */ "cins32\t\000" |
| 61 | /* 293 */ "exts32\t\000" |
| 62 | /* 301 */ "ldc2\t\000" |
| 63 | /* 307 */ "sdc2\t\000" |
| 64 | /* 313 */ "cfc2\t\000" |
| 65 | /* 319 */ "dmfc2\t\000" |
| 66 | /* 326 */ "mfhc2\t\000" |
| 67 | /* 333 */ "mthc2\t\000" |
| 68 | /* 340 */ "ctc2\t\000" |
| 69 | /* 346 */ "dmtc2\t\000" |
| 70 | /* 353 */ "lwc2\t\000" |
| 71 | /* 359 */ "swc2\t\000" |
| 72 | /* 365 */ "mtm2\t\000" |
| 73 | /* 371 */ "mtp2\t\000" |
| 74 | /* 377 */ "addiur2\t\000" |
| 75 | /* 386 */ "ldc3\t\000" |
| 76 | /* 392 */ "sdc3\t\000" |
| 77 | /* 398 */ "lwc3\t\000" |
| 78 | /* 404 */ "swc3\t\000" |
| 79 | /* 410 */ "addius5\t\000" |
| 80 | /* 419 */ "sb16\t\000" |
| 81 | /* 425 */ "bc16\t\000" |
| 82 | /* 431 */ "jrc16\t\000" |
| 83 | /* 438 */ "bnezc16\t\000" |
| 84 | /* 447 */ "beqzc16\t\000" |
| 85 | /* 456 */ "and16\t\000" |
| 86 | /* 463 */ "move16\t\000" |
| 87 | /* 471 */ "sh16\t\000" |
| 88 | /* 477 */ "andi16\t\000" |
| 89 | /* 485 */ "mfhi16\t\000" |
| 90 | /* 493 */ "li16\t\000" |
| 91 | /* 499 */ "break16\t\000" |
| 92 | /* 508 */ "sll16\t\000" |
| 93 | /* 515 */ "srl16\t\000" |
| 94 | /* 522 */ "lwm16\t\000" |
| 95 | /* 529 */ "swm16\t\000" |
| 96 | /* 536 */ "mflo16\t\000" |
| 97 | /* 544 */ "sdbbp16\t\000" |
| 98 | /* 553 */ "jr16\t\000" |
| 99 | /* 559 */ "xor16\t\000" |
| 100 | /* 566 */ "jalrs16\t\000" |
| 101 | /* 575 */ "not16\t\000" |
| 102 | /* 582 */ "lbu16\t\000" |
| 103 | /* 589 */ "subu16\t\000" |
| 104 | /* 597 */ "addu16\t\000" |
| 105 | /* 605 */ "lhu16\t\000" |
| 106 | /* 612 */ "lw16\t\000" |
| 107 | /* 618 */ "sw16\t\000" |
| 108 | /* 624 */ "bnez16\t\000" |
| 109 | /* 632 */ "beqz16\t\000" |
| 110 | /* 640 */ "saa\t\000" |
| 111 | /* 645 */ "preceu.ph.qbla\t\000" |
| 112 | /* 661 */ "precequ.ph.qbla\t\000" |
| 113 | /* 678 */ "dla\t\000" |
| 114 | /* 683 */ "preceu.ph.qbra\t\000" |
| 115 | /* 699 */ "precequ.ph.qbra\t\000" |
| 116 | /* 716 */ "dsra\t\000" |
| 117 | /* 722 */ "dlsa\t\000" |
| 118 | /* 728 */ "cfcmsa\t\000" |
| 119 | /* 736 */ "ctcmsa\t\000" |
| 120 | /* 744 */ "add_a.b\t\000" |
| 121 | /* 753 */ "min_a.b\t\000" |
| 122 | /* 762 */ "adds_a.b\t\000" |
| 123 | /* 772 */ "max_a.b\t\000" |
| 124 | /* 781 */ "sra.b\t\000" |
| 125 | /* 788 */ "nloc.b\t\000" |
| 126 | /* 796 */ "nlzc.b\t\000" |
| 127 | /* 804 */ "sld.b\t\000" |
| 128 | /* 811 */ "pckod.b\t\000" |
| 129 | /* 820 */ "ilvod.b\t\000" |
| 130 | /* 829 */ "insve.b\t\000" |
| 131 | /* 838 */ "vshf.b\t\000" |
| 132 | /* 846 */ "bneg.b\t\000" |
| 133 | /* 854 */ "srai.b\t\000" |
| 134 | /* 862 */ "sldi.b\t\000" |
| 135 | /* 870 */ "andi.b\t\000" |
| 136 | /* 878 */ "bnegi.b\t\000" |
| 137 | /* 887 */ "bseli.b\t\000" |
| 138 | /* 896 */ "slli.b\t\000" |
| 139 | /* 904 */ "srli.b\t\000" |
| 140 | /* 912 */ "binsli.b\t\000" |
| 141 | /* 922 */ "ceqi.b\t\000" |
| 142 | /* 930 */ "srari.b\t\000" |
| 143 | /* 939 */ "bclri.b\t\000" |
| 144 | /* 948 */ "srlri.b\t\000" |
| 145 | /* 957 */ "nori.b\t\000" |
| 146 | /* 965 */ "xori.b\t\000" |
| 147 | /* 973 */ "binsri.b\t\000" |
| 148 | /* 983 */ "splati.b\t\000" |
| 149 | /* 993 */ "bseti.b\t\000" |
| 150 | /* 1002 */ "subvi.b\t\000" |
| 151 | /* 1011 */ "addvi.b\t\000" |
| 152 | /* 1020 */ "bmzi.b\t\000" |
| 153 | /* 1028 */ "bmnzi.b\t\000" |
| 154 | /* 1037 */ "fill.b\t\000" |
| 155 | /* 1045 */ "sll.b\t\000" |
| 156 | /* 1052 */ "srl.b\t\000" |
| 157 | /* 1059 */ "binsl.b\t\000" |
| 158 | /* 1068 */ "ilvl.b\t\000" |
| 159 | /* 1076 */ "ceq.b\t\000" |
| 160 | /* 1083 */ "srar.b\t\000" |
| 161 | /* 1091 */ "bclr.b\t\000" |
| 162 | /* 1099 */ "srlr.b\t\000" |
| 163 | /* 1107 */ "binsr.b\t\000" |
| 164 | /* 1116 */ "ilvr.b\t\000" |
| 165 | /* 1124 */ "asub_s.b\t\000" |
| 166 | /* 1134 */ "mod_s.b\t\000" |
| 167 | /* 1143 */ "cle_s.b\t\000" |
| 168 | /* 1152 */ "ave_s.b\t\000" |
| 169 | /* 1161 */ "clei_s.b\t\000" |
| 170 | /* 1171 */ "mini_s.b\t\000" |
| 171 | /* 1181 */ "clti_s.b\t\000" |
| 172 | /* 1191 */ "maxi_s.b\t\000" |
| 173 | /* 1201 */ "min_s.b\t\000" |
| 174 | /* 1210 */ "aver_s.b\t\000" |
| 175 | /* 1220 */ "subs_s.b\t\000" |
| 176 | /* 1230 */ "adds_s.b\t\000" |
| 177 | /* 1240 */ "sat_s.b\t\000" |
| 178 | /* 1249 */ "clt_s.b\t\000" |
| 179 | /* 1258 */ "subsuu_s.b\t\000" |
| 180 | /* 1270 */ "div_s.b\t\000" |
| 181 | /* 1279 */ "max_s.b\t\000" |
| 182 | /* 1288 */ "copy_s.b\t\000" |
| 183 | /* 1298 */ "splat.b\t\000" |
| 184 | /* 1307 */ "bset.b\t\000" |
| 185 | /* 1315 */ "pcnt.b\t\000" |
| 186 | /* 1323 */ "insert.b\t\000" |
| 187 | /* 1333 */ "st.b\t\000" |
| 188 | /* 1339 */ "asub_u.b\t\000" |
| 189 | /* 1349 */ "mod_u.b\t\000" |
| 190 | /* 1358 */ "cle_u.b\t\000" |
| 191 | /* 1367 */ "ave_u.b\t\000" |
| 192 | /* 1376 */ "clei_u.b\t\000" |
| 193 | /* 1386 */ "mini_u.b\t\000" |
| 194 | /* 1396 */ "clti_u.b\t\000" |
| 195 | /* 1406 */ "maxi_u.b\t\000" |
| 196 | /* 1416 */ "min_u.b\t\000" |
| 197 | /* 1425 */ "aver_u.b\t\000" |
| 198 | /* 1435 */ "subs_u.b\t\000" |
| 199 | /* 1445 */ "adds_u.b\t\000" |
| 200 | /* 1455 */ "subsus_u.b\t\000" |
| 201 | /* 1467 */ "sat_u.b\t\000" |
| 202 | /* 1476 */ "clt_u.b\t\000" |
| 203 | /* 1485 */ "div_u.b\t\000" |
| 204 | /* 1494 */ "max_u.b\t\000" |
| 205 | /* 1503 */ "copy_u.b\t\000" |
| 206 | /* 1513 */ "msubv.b\t\000" |
| 207 | /* 1522 */ "maddv.b\t\000" |
| 208 | /* 1531 */ "pckev.b\t\000" |
| 209 | /* 1540 */ "ilvev.b\t\000" |
| 210 | /* 1549 */ "mulv.b\t\000" |
| 211 | /* 1557 */ "bz.b\t\000" |
| 212 | /* 1563 */ "bnz.b\t\000" |
| 213 | /* 1570 */ "crc32b\t\000" |
| 214 | /* 1578 */ "crc32cb\t\000" |
| 215 | /* 1587 */ "seb\t\000" |
| 216 | /* 1592 */ "jalrc.hb\t\000" |
| 217 | /* 1602 */ "jr.hb\t\000" |
| 218 | /* 1609 */ "jalr.hb\t\000" |
| 219 | /* 1618 */ "lb\t\000" |
| 220 | /* 1622 */ "shra.qb\t\000" |
| 221 | /* 1631 */ "cmpgdu.le.qb\t\000" |
| 222 | /* 1645 */ "cmpgu.le.qb\t\000" |
| 223 | /* 1658 */ "cmpu.le.qb\t\000" |
| 224 | /* 1670 */ "subuh.qb\t\000" |
| 225 | /* 1680 */ "adduh.qb\t\000" |
| 226 | /* 1690 */ "pick.qb\t\000" |
| 227 | /* 1699 */ "shll.qb\t\000" |
| 228 | /* 1708 */ "repl.qb\t\000" |
| 229 | /* 1717 */ "shrl.qb\t\000" |
| 230 | /* 1726 */ "cmpgdu.eq.qb\t\000" |
| 231 | /* 1740 */ "cmpgu.eq.qb\t\000" |
| 232 | /* 1753 */ "cmpu.eq.qb\t\000" |
| 233 | /* 1765 */ "shra_r.qb\t\000" |
| 234 | /* 1776 */ "subuh_r.qb\t\000" |
| 235 | /* 1788 */ "adduh_r.qb\t\000" |
| 236 | /* 1800 */ "shrav_r.qb\t\000" |
| 237 | /* 1812 */ "absq_s.qb\t\000" |
| 238 | /* 1823 */ "subu_s.qb\t\000" |
| 239 | /* 1834 */ "addu_s.qb\t\000" |
| 240 | /* 1845 */ "cmpgdu.lt.qb\t\000" |
| 241 | /* 1859 */ "cmpgu.lt.qb\t\000" |
| 242 | /* 1872 */ "cmpu.lt.qb\t\000" |
| 243 | /* 1884 */ "subu.qb\t\000" |
| 244 | /* 1893 */ "addu.qb\t\000" |
| 245 | /* 1902 */ "shrav.qb\t\000" |
| 246 | /* 1912 */ "shllv.qb\t\000" |
| 247 | /* 1922 */ "replv.qb\t\000" |
| 248 | /* 1932 */ "shrlv.qb\t\000" |
| 249 | /* 1942 */ "raddu.w.qb\t\000" |
| 250 | /* 1954 */ "sb\t\000" |
| 251 | /* 1958 */ "modsub\t\000" |
| 252 | /* 1966 */ "msub\t\000" |
| 253 | /* 1972 */ "bposge32c\t\000" |
| 254 | /* 1983 */ "bc\t\000" |
| 255 | /* 1987 */ "bgec\t\000" |
| 256 | /* 1993 */ "bnec\t\000" |
| 257 | /* 1999 */ "jic\t\000" |
| 258 | /* 2004 */ "balc\t\000" |
| 259 | /* 2010 */ "jialc\t\000" |
| 260 | /* 2017 */ "bgezalc\t\000" |
| 261 | /* 2026 */ "blezalc\t\000" |
| 262 | /* 2035 */ "bnezalc\t\000" |
| 263 | /* 2044 */ "beqzalc\t\000" |
| 264 | /* 2053 */ "bgtzalc\t\000" |
| 265 | /* 2062 */ "bltzalc\t\000" |
| 266 | /* 2071 */ "sync\t\000" |
| 267 | /* 2077 */ "ldpc\t\000" |
| 268 | /* 2083 */ "auipc\t\000" |
| 269 | /* 2090 */ "aluipc\t\000" |
| 270 | /* 2098 */ "addiupc\t\000" |
| 271 | /* 2107 */ "lwupc\t\000" |
| 272 | /* 2114 */ "lwpc\t\000" |
| 273 | /* 2120 */ "beqc\t\000" |
| 274 | /* 2126 */ "jrc\t\000" |
| 275 | /* 2131 */ "jalrc\t\000" |
| 276 | /* 2138 */ "addsc\t\000" |
| 277 | /* 2145 */ "bltc\t\000" |
| 278 | /* 2151 */ "bgeuc\t\000" |
| 279 | /* 2158 */ "bltuc\t\000" |
| 280 | /* 2165 */ "bnvc\t\000" |
| 281 | /* 2171 */ "bovc\t\000" |
| 282 | /* 2177 */ "addwc\t\000" |
| 283 | /* 2184 */ "bgezc\t\000" |
| 284 | /* 2191 */ "blezc\t\000" |
| 285 | /* 2198 */ "bc1nezc\t\000" |
| 286 | /* 2207 */ "bc2nezc\t\000" |
| 287 | /* 2216 */ "bnezc\t\000" |
| 288 | /* 2223 */ "bc1eqzc\t\000" |
| 289 | /* 2232 */ "bc2eqzc\t\000" |
| 290 | /* 2241 */ "beqzc\t\000" |
| 291 | /* 2248 */ "bgtzc\t\000" |
| 292 | /* 2255 */ "bltzc\t\000" |
| 293 | /* 2262 */ "flog2.d\t\000" |
| 294 | /* 2271 */ "fexp2.d\t\000" |
| 295 | /* 2280 */ "add_a.d\t\000" |
| 296 | /* 2289 */ "fmin_a.d\t\000" |
| 297 | /* 2299 */ "adds_a.d\t\000" |
| 298 | /* 2309 */ "fmax_a.d\t\000" |
| 299 | /* 2319 */ "mina.d\t\000" |
| 300 | /* 2327 */ "sra.d\t\000" |
| 301 | /* 2334 */ "maxa.d\t\000" |
| 302 | /* 2342 */ "fsub.d\t\000" |
| 303 | /* 2350 */ "fmsub.d\t\000" |
| 304 | /* 2359 */ "nmsub.d\t\000" |
| 305 | /* 2368 */ "nloc.d\t\000" |
| 306 | /* 2376 */ "nlzc.d\t\000" |
| 307 | /* 2384 */ "fadd.d\t\000" |
| 308 | /* 2392 */ "fmadd.d\t\000" |
| 309 | /* 2401 */ "nmadd.d\t\000" |
| 310 | /* 2410 */ "sld.d\t\000" |
| 311 | /* 2417 */ "pckod.d\t\000" |
| 312 | /* 2426 */ "ilvod.d\t\000" |
| 313 | /* 2435 */ "c.nge.d\t\000" |
| 314 | /* 2444 */ "c.le.d\t\000" |
| 315 | /* 2452 */ "cmp.le.d\t\000" |
| 316 | /* 2462 */ "fcle.d\t\000" |
| 317 | /* 2470 */ "c.ngle.d\t\000" |
| 318 | /* 2480 */ "c.ole.d\t\000" |
| 319 | /* 2489 */ "cmp.sle.d\t\000" |
| 320 | /* 2500 */ "fsle.d\t\000" |
| 321 | /* 2508 */ "c.ule.d\t\000" |
| 322 | /* 2517 */ "cmp.ule.d\t\000" |
| 323 | /* 2528 */ "fcule.d\t\000" |
| 324 | /* 2537 */ "cmp.sule.d\t\000" |
| 325 | /* 2549 */ "fsule.d\t\000" |
| 326 | /* 2558 */ "fcne.d\t\000" |
| 327 | /* 2566 */ "fsne.d\t\000" |
| 328 | /* 2574 */ "fcune.d\t\000" |
| 329 | /* 2583 */ "fsune.d\t\000" |
| 330 | /* 2592 */ "insve.d\t\000" |
| 331 | /* 2601 */ "c.f.d\t\000" |
| 332 | /* 2608 */ "cmp.af.d\t\000" |
| 333 | /* 2618 */ "fcaf.d\t\000" |
| 334 | /* 2626 */ "cmp.saf.d\t\000" |
| 335 | /* 2637 */ "fsaf.d\t\000" |
| 336 | /* 2645 */ "msubf.d\t\000" |
| 337 | /* 2654 */ "maddf.d\t\000" |
| 338 | /* 2663 */ "vshf.d\t\000" |
| 339 | /* 2671 */ "c.sf.d\t\000" |
| 340 | /* 2679 */ "movf.d\t\000" |
| 341 | /* 2687 */ "bneg.d\t\000" |
| 342 | /* 2695 */ "srai.d\t\000" |
| 343 | /* 2703 */ "sldi.d\t\000" |
| 344 | /* 2711 */ "bnegi.d\t\000" |
| 345 | /* 2720 */ "slli.d\t\000" |
| 346 | /* 2728 */ "srli.d\t\000" |
| 347 | /* 2736 */ "binsli.d\t\000" |
| 348 | /* 2746 */ "ceqi.d\t\000" |
| 349 | /* 2754 */ "srari.d\t\000" |
| 350 | /* 2763 */ "bclri.d\t\000" |
| 351 | /* 2772 */ "srlri.d\t\000" |
| 352 | /* 2781 */ "binsri.d\t\000" |
| 353 | /* 2791 */ "splati.d\t\000" |
| 354 | /* 2801 */ "bseti.d\t\000" |
| 355 | /* 2810 */ "subvi.d\t\000" |
| 356 | /* 2819 */ "addvi.d\t\000" |
| 357 | /* 2828 */ "trunc.l.d\t\000" |
| 358 | /* 2839 */ "round.l.d\t\000" |
| 359 | /* 2850 */ "ceil.l.d\t\000" |
| 360 | /* 2860 */ "floor.l.d\t\000" |
| 361 | /* 2871 */ "cvt.l.d\t\000" |
| 362 | /* 2880 */ "sel.d\t\000" |
| 363 | /* 2887 */ "c.ngl.d\t\000" |
| 364 | /* 2896 */ "fill.d\t\000" |
| 365 | /* 2904 */ "sll.d\t\000" |
| 366 | /* 2911 */ "fexupl.d\t\000" |
| 367 | /* 2921 */ "ffql.d\t\000" |
| 368 | /* 2929 */ "srl.d\t\000" |
| 369 | /* 2936 */ "binsl.d\t\000" |
| 370 | /* 2945 */ "fmul.d\t\000" |
| 371 | /* 2953 */ "ilvl.d\t\000" |
| 372 | /* 2961 */ "fmin.d\t\000" |
| 373 | /* 2969 */ "c.un.d\t\000" |
| 374 | /* 2977 */ "cmp.un.d\t\000" |
| 375 | /* 2987 */ "fcun.d\t\000" |
| 376 | /* 2995 */ "cmp.sun.d\t\000" |
| 377 | /* 3006 */ "fsun.d\t\000" |
| 378 | /* 3014 */ "movn.d\t\000" |
| 379 | /* 3022 */ "frcp.d\t\000" |
| 380 | /* 3030 */ "recip.d\t\000" |
| 381 | /* 3039 */ "c.eq.d\t\000" |
| 382 | /* 3047 */ "cmp.eq.d\t\000" |
| 383 | /* 3057 */ "fceq.d\t\000" |
| 384 | /* 3065 */ "c.seq.d\t\000" |
| 385 | /* 3074 */ "cmp.seq.d\t\000" |
| 386 | /* 3085 */ "fseq.d\t\000" |
| 387 | /* 3093 */ "c.ueq.d\t\000" |
| 388 | /* 3102 */ "cmp.ueq.d\t\000" |
| 389 | /* 3113 */ "fcueq.d\t\000" |
| 390 | /* 3122 */ "cmp.sueq.d\t\000" |
| 391 | /* 3134 */ "fsueq.d\t\000" |
| 392 | /* 3143 */ "srar.d\t\000" |
| 393 | /* 3151 */ "bclr.d\t\000" |
| 394 | /* 3159 */ "srlr.d\t\000" |
| 395 | /* 3167 */ "fcor.d\t\000" |
| 396 | /* 3175 */ "fsor.d\t\000" |
| 397 | /* 3183 */ "fexupr.d\t\000" |
| 398 | /* 3193 */ "ffqr.d\t\000" |
| 399 | /* 3201 */ "binsr.d\t\000" |
| 400 | /* 3210 */ "ilvr.d\t\000" |
| 401 | /* 3218 */ "cvt.s.d\t\000" |
| 402 | /* 3227 */ "asub_s.d\t\000" |
| 403 | /* 3237 */ "hsub_s.d\t\000" |
| 404 | /* 3247 */ "dpsub_s.d\t\000" |
| 405 | /* 3258 */ "ftrunc_s.d\t\000" |
| 406 | /* 3270 */ "hadd_s.d\t\000" |
| 407 | /* 3280 */ "dpadd_s.d\t\000" |
| 408 | /* 3291 */ "mod_s.d\t\000" |
| 409 | /* 3300 */ "cle_s.d\t\000" |
| 410 | /* 3309 */ "ave_s.d\t\000" |
| 411 | /* 3318 */ "clei_s.d\t\000" |
| 412 | /* 3328 */ "mini_s.d\t\000" |
| 413 | /* 3338 */ "clti_s.d\t\000" |
| 414 | /* 3348 */ "maxi_s.d\t\000" |
| 415 | /* 3358 */ "min_s.d\t\000" |
| 416 | /* 3367 */ "dotp_s.d\t\000" |
| 417 | /* 3377 */ "aver_s.d\t\000" |
| 418 | /* 3387 */ "subs_s.d\t\000" |
| 419 | /* 3397 */ "adds_s.d\t\000" |
| 420 | /* 3407 */ "sat_s.d\t\000" |
| 421 | /* 3416 */ "clt_s.d\t\000" |
| 422 | /* 3425 */ "ffint_s.d\t\000" |
| 423 | /* 3436 */ "ftint_s.d\t\000" |
| 424 | /* 3447 */ "subsuu_s.d\t\000" |
| 425 | /* 3459 */ "div_s.d\t\000" |
| 426 | /* 3468 */ "max_s.d\t\000" |
| 427 | /* 3477 */ "copy_s.d\t\000" |
| 428 | /* 3487 */ "abs.d\t\000" |
| 429 | /* 3494 */ "fclass.d\t\000" |
| 430 | /* 3504 */ "splat.d\t\000" |
| 431 | /* 3513 */ "bset.d\t\000" |
| 432 | /* 3521 */ "c.ngt.d\t\000" |
| 433 | /* 3530 */ "c.lt.d\t\000" |
| 434 | /* 3538 */ "cmp.lt.d\t\000" |
| 435 | /* 3548 */ "fclt.d\t\000" |
| 436 | /* 3556 */ "c.olt.d\t\000" |
| 437 | /* 3565 */ "cmp.slt.d\t\000" |
| 438 | /* 3576 */ "fslt.d\t\000" |
| 439 | /* 3584 */ "c.ult.d\t\000" |
| 440 | /* 3593 */ "cmp.ult.d\t\000" |
| 441 | /* 3604 */ "fcult.d\t\000" |
| 442 | /* 3613 */ "cmp.sult.d\t\000" |
| 443 | /* 3625 */ "fsult.d\t\000" |
| 444 | /* 3634 */ "pcnt.d\t\000" |
| 445 | /* 3642 */ "frint.d\t\000" |
| 446 | /* 3651 */ "insert.d\t\000" |
| 447 | /* 3661 */ "fsqrt.d\t\000" |
| 448 | /* 3670 */ "frsqrt.d\t\000" |
| 449 | /* 3680 */ "st.d\t\000" |
| 450 | /* 3686 */ "movt.d\t\000" |
| 451 | /* 3694 */ "asub_u.d\t\000" |
| 452 | /* 3704 */ "hsub_u.d\t\000" |
| 453 | /* 3714 */ "dpsub_u.d\t\000" |
| 454 | /* 3725 */ "ftrunc_u.d\t\000" |
| 455 | /* 3737 */ "hadd_u.d\t\000" |
| 456 | /* 3747 */ "dpadd_u.d\t\000" |
| 457 | /* 3758 */ "mod_u.d\t\000" |
| 458 | /* 3767 */ "cle_u.d\t\000" |
| 459 | /* 3776 */ "ave_u.d\t\000" |
| 460 | /* 3785 */ "clei_u.d\t\000" |
| 461 | /* 3795 */ "mini_u.d\t\000" |
| 462 | /* 3805 */ "clti_u.d\t\000" |
| 463 | /* 3815 */ "maxi_u.d\t\000" |
| 464 | /* 3825 */ "min_u.d\t\000" |
| 465 | /* 3834 */ "dotp_u.d\t\000" |
| 466 | /* 3844 */ "aver_u.d\t\000" |
| 467 | /* 3854 */ "subs_u.d\t\000" |
| 468 | /* 3864 */ "adds_u.d\t\000" |
| 469 | /* 3874 */ "subsus_u.d\t\000" |
| 470 | /* 3886 */ "sat_u.d\t\000" |
| 471 | /* 3895 */ "clt_u.d\t\000" |
| 472 | /* 3904 */ "ffint_u.d\t\000" |
| 473 | /* 3915 */ "ftint_u.d\t\000" |
| 474 | /* 3926 */ "div_u.d\t\000" |
| 475 | /* 3935 */ "max_u.d\t\000" |
| 476 | /* 3944 */ "msubv.d\t\000" |
| 477 | /* 3953 */ "maddv.d\t\000" |
| 478 | /* 3962 */ "pckev.d\t\000" |
| 479 | /* 3971 */ "ilvev.d\t\000" |
| 480 | /* 3980 */ "fdiv.d\t\000" |
| 481 | /* 3988 */ "mulv.d\t\000" |
| 482 | /* 3996 */ "mov.d\t\000" |
| 483 | /* 4003 */ "trunc.w.d\t\000" |
| 484 | /* 4014 */ "round.w.d\t\000" |
| 485 | /* 4025 */ "ceil.w.d\t\000" |
| 486 | /* 4035 */ "floor.w.d\t\000" |
| 487 | /* 4046 */ "cvt.w.d\t\000" |
| 488 | /* 4055 */ "fmax.d\t\000" |
| 489 | /* 4063 */ "bz.d\t\000" |
| 490 | /* 4069 */ "selnez.d\t\000" |
| 491 | /* 4079 */ "bnz.d\t\000" |
| 492 | /* 4086 */ "seleqz.d\t\000" |
| 493 | /* 4096 */ "movz.d\t\000" |
| 494 | /* 4104 */ "crc32d\t\000" |
| 495 | /* 4112 */ "saad\t\000" |
| 496 | /* 4118 */ "crc32cd\t\000" |
| 497 | /* 4127 */ "scd\t\000" |
| 498 | /* 4132 */ "dadd\t\000" |
| 499 | /* 4138 */ "madd\t\000" |
| 500 | /* 4144 */ "dshd\t\000" |
| 501 | /* 4150 */ "yield\t\000" |
| 502 | /* 4157 */ "lld\t\000" |
| 503 | /* 4162 */ "and\t\000" |
| 504 | /* 4167 */ "prepend\t\000" |
| 505 | /* 4176 */ "append\t\000" |
| 506 | /* 4184 */ "dmod\t\000" |
| 507 | /* 4190 */ "sd\t\000" |
| 508 | /* 4194 */ "lbe\t\000" |
| 509 | /* 4199 */ "sbe\t\000" |
| 510 | /* 4204 */ "sce\t\000" |
| 511 | /* 4209 */ "cachee\t\000" |
| 512 | /* 4217 */ "prefe\t\000" |
| 513 | /* 4224 */ "bge\t\000" |
| 514 | /* 4229 */ "sge\t\000" |
| 515 | /* 4234 */ "tge\t\000" |
| 516 | /* 4239 */ "cache\t\000" |
| 517 | /* 4246 */ "lhe\t\000" |
| 518 | /* 4251 */ "she\t\000" |
| 519 | /* 4256 */ "sigrie\t\000" |
| 520 | /* 4264 */ "ble\t\000" |
| 521 | /* 4269 */ "lle\t\000" |
| 522 | /* 4274 */ "sle\t\000" |
| 523 | /* 4279 */ "lwle\t\000" |
| 524 | /* 4285 */ "swle\t\000" |
| 525 | /* 4291 */ "bne\t\000" |
| 526 | /* 4296 */ "sne\t\000" |
| 527 | /* 4301 */ "tne\t\000" |
| 528 | /* 4306 */ "dvpe\t\000" |
| 529 | /* 4312 */ "evpe\t\000" |
| 530 | /* 4318 */ "lwre\t\000" |
| 531 | /* 4324 */ "swre\t\000" |
| 532 | /* 4330 */ "lbue\t\000" |
| 533 | /* 4336 */ "lhue\t\000" |
| 534 | /* 4342 */ "move\t\000" |
| 535 | /* 4348 */ "lwe\t\000" |
| 536 | /* 4353 */ "swe\t\000" |
| 537 | /* 4358 */ "bc1f\t\000" |
| 538 | /* 4364 */ "pref\t\000" |
| 539 | /* 4370 */ "movf\t\000" |
| 540 | /* 4376 */ "neg\t\000" |
| 541 | /* 4381 */ "add_a.h\t\000" |
| 542 | /* 4390 */ "min_a.h\t\000" |
| 543 | /* 4399 */ "adds_a.h\t\000" |
| 544 | /* 4409 */ "max_a.h\t\000" |
| 545 | /* 4418 */ "sra.h\t\000" |
| 546 | /* 4425 */ "nloc.h\t\000" |
| 547 | /* 4433 */ "nlzc.h\t\000" |
| 548 | /* 4441 */ "sld.h\t\000" |
| 549 | /* 4448 */ "pckod.h\t\000" |
| 550 | /* 4457 */ "ilvod.h\t\000" |
| 551 | /* 4466 */ "insve.h\t\000" |
| 552 | /* 4475 */ "vshf.h\t\000" |
| 553 | /* 4483 */ "bneg.h\t\000" |
| 554 | /* 4491 */ "srai.h\t\000" |
| 555 | /* 4499 */ "sldi.h\t\000" |
| 556 | /* 4507 */ "bnegi.h\t\000" |
| 557 | /* 4516 */ "slli.h\t\000" |
| 558 | /* 4524 */ "srli.h\t\000" |
| 559 | /* 4532 */ "binsli.h\t\000" |
| 560 | /* 4542 */ "ceqi.h\t\000" |
| 561 | /* 4550 */ "srari.h\t\000" |
| 562 | /* 4559 */ "bclri.h\t\000" |
| 563 | /* 4568 */ "srlri.h\t\000" |
| 564 | /* 4577 */ "binsri.h\t\000" |
| 565 | /* 4587 */ "splati.h\t\000" |
| 566 | /* 4597 */ "bseti.h\t\000" |
| 567 | /* 4606 */ "subvi.h\t\000" |
| 568 | /* 4615 */ "addvi.h\t\000" |
| 569 | /* 4624 */ "fill.h\t\000" |
| 570 | /* 4632 */ "sll.h\t\000" |
| 571 | /* 4639 */ "srl.h\t\000" |
| 572 | /* 4646 */ "binsl.h\t\000" |
| 573 | /* 4655 */ "ilvl.h\t\000" |
| 574 | /* 4663 */ "fexdo.h\t\000" |
| 575 | /* 4672 */ "msub_q.h\t\000" |
| 576 | /* 4682 */ "madd_q.h\t\000" |
| 577 | /* 4692 */ "mul_q.h\t\000" |
| 578 | /* 4701 */ "msubr_q.h\t\000" |
| 579 | /* 4712 */ "maddr_q.h\t\000" |
| 580 | /* 4723 */ "mulr_q.h\t\000" |
| 581 | /* 4733 */ "ceq.h\t\000" |
| 582 | /* 4740 */ "ftq.h\t\000" |
| 583 | /* 4747 */ "srar.h\t\000" |
| 584 | /* 4755 */ "bclr.h\t\000" |
| 585 | /* 4763 */ "srlr.h\t\000" |
| 586 | /* 4771 */ "binsr.h\t\000" |
| 587 | /* 4780 */ "ilvr.h\t\000" |
| 588 | /* 4788 */ "asub_s.h\t\000" |
| 589 | /* 4798 */ "hsub_s.h\t\000" |
| 590 | /* 4808 */ "dpsub_s.h\t\000" |
| 591 | /* 4819 */ "hadd_s.h\t\000" |
| 592 | /* 4829 */ "dpadd_s.h\t\000" |
| 593 | /* 4840 */ "mod_s.h\t\000" |
| 594 | /* 4849 */ "cle_s.h\t\000" |
| 595 | /* 4858 */ "ave_s.h\t\000" |
| 596 | /* 4867 */ "clei_s.h\t\000" |
| 597 | /* 4877 */ "mini_s.h\t\000" |
| 598 | /* 4887 */ "clti_s.h\t\000" |
| 599 | /* 4897 */ "maxi_s.h\t\000" |
| 600 | /* 4907 */ "min_s.h\t\000" |
| 601 | /* 4916 */ "dotp_s.h\t\000" |
| 602 | /* 4926 */ "aver_s.h\t\000" |
| 603 | /* 4936 */ "extr_s.h\t\000" |
| 604 | /* 4946 */ "subs_s.h\t\000" |
| 605 | /* 4956 */ "adds_s.h\t\000" |
| 606 | /* 4966 */ "sat_s.h\t\000" |
| 607 | /* 4975 */ "clt_s.h\t\000" |
| 608 | /* 4984 */ "subsuu_s.h\t\000" |
| 609 | /* 4996 */ "div_s.h\t\000" |
| 610 | /* 5005 */ "extrv_s.h\t\000" |
| 611 | /* 5016 */ "max_s.h\t\000" |
| 612 | /* 5025 */ "copy_s.h\t\000" |
| 613 | /* 5035 */ "splat.h\t\000" |
| 614 | /* 5044 */ "bset.h\t\000" |
| 615 | /* 5052 */ "pcnt.h\t\000" |
| 616 | /* 5060 */ "insert.h\t\000" |
| 617 | /* 5070 */ "st.h\t\000" |
| 618 | /* 5076 */ "asub_u.h\t\000" |
| 619 | /* 5086 */ "hsub_u.h\t\000" |
| 620 | /* 5096 */ "dpsub_u.h\t\000" |
| 621 | /* 5107 */ "hadd_u.h\t\000" |
| 622 | /* 5117 */ "dpadd_u.h\t\000" |
| 623 | /* 5128 */ "mod_u.h\t\000" |
| 624 | /* 5137 */ "cle_u.h\t\000" |
| 625 | /* 5146 */ "ave_u.h\t\000" |
| 626 | /* 5155 */ "clei_u.h\t\000" |
| 627 | /* 5165 */ "mini_u.h\t\000" |
| 628 | /* 5175 */ "clti_u.h\t\000" |
| 629 | /* 5185 */ "maxi_u.h\t\000" |
| 630 | /* 5195 */ "min_u.h\t\000" |
| 631 | /* 5204 */ "dotp_u.h\t\000" |
| 632 | /* 5214 */ "aver_u.h\t\000" |
| 633 | /* 5224 */ "subs_u.h\t\000" |
| 634 | /* 5234 */ "adds_u.h\t\000" |
| 635 | /* 5244 */ "subsus_u.h\t\000" |
| 636 | /* 5256 */ "sat_u.h\t\000" |
| 637 | /* 5265 */ "clt_u.h\t\000" |
| 638 | /* 5274 */ "div_u.h\t\000" |
| 639 | /* 5283 */ "max_u.h\t\000" |
| 640 | /* 5292 */ "copy_u.h\t\000" |
| 641 | /* 5302 */ "msubv.h\t\000" |
| 642 | /* 5311 */ "maddv.h\t\000" |
| 643 | /* 5320 */ "pckev.h\t\000" |
| 644 | /* 5329 */ "ilvev.h\t\000" |
| 645 | /* 5338 */ "mulv.h\t\000" |
| 646 | /* 5346 */ "bz.h\t\000" |
| 647 | /* 5352 */ "bnz.h\t\000" |
| 648 | /* 5359 */ "crc32h\t\000" |
| 649 | /* 5367 */ "dsbh\t\000" |
| 650 | /* 5373 */ "wsbh\t\000" |
| 651 | /* 5379 */ "crc32ch\t\000" |
| 652 | /* 5388 */ "seh\t\000" |
| 653 | /* 5393 */ "ulh\t\000" |
| 654 | /* 5398 */ "shra.ph\t\000" |
| 655 | /* 5407 */ "precrq.qb.ph\t\000" |
| 656 | /* 5421 */ "precr.qb.ph\t\000" |
| 657 | /* 5434 */ "precrqu_s.qb.ph\t\000" |
| 658 | /* 5451 */ "cmp.le.ph\t\000" |
| 659 | /* 5462 */ "subqh.ph\t\000" |
| 660 | /* 5472 */ "addqh.ph\t\000" |
| 661 | /* 5482 */ "pick.ph\t\000" |
| 662 | /* 5491 */ "shll.ph\t\000" |
| 663 | /* 5500 */ "repl.ph\t\000" |
| 664 | /* 5509 */ "shrl.ph\t\000" |
| 665 | /* 5518 */ "packrl.ph\t\000" |
| 666 | /* 5529 */ "mul.ph\t\000" |
| 667 | /* 5537 */ "subq.ph\t\000" |
| 668 | /* 5546 */ "addq.ph\t\000" |
| 669 | /* 5555 */ "cmp.eq.ph\t\000" |
| 670 | /* 5566 */ "shra_r.ph\t\000" |
| 671 | /* 5577 */ "subqh_r.ph\t\000" |
| 672 | /* 5589 */ "addqh_r.ph\t\000" |
| 673 | /* 5601 */ "shrav_r.ph\t\000" |
| 674 | /* 5613 */ "shll_s.ph\t\000" |
| 675 | /* 5624 */ "mul_s.ph\t\000" |
| 676 | /* 5634 */ "subq_s.ph\t\000" |
| 677 | /* 5645 */ "addq_s.ph\t\000" |
| 678 | /* 5656 */ "mulq_s.ph\t\000" |
| 679 | /* 5667 */ "absq_s.ph\t\000" |
| 680 | /* 5678 */ "subu_s.ph\t\000" |
| 681 | /* 5689 */ "addu_s.ph\t\000" |
| 682 | /* 5700 */ "shllv_s.ph\t\000" |
| 683 | /* 5712 */ "mulq_rs.ph\t\000" |
| 684 | /* 5724 */ "cmp.lt.ph\t\000" |
| 685 | /* 5735 */ "subu.ph\t\000" |
| 686 | /* 5744 */ "addu.ph\t\000" |
| 687 | /* 5753 */ "shrav.ph\t\000" |
| 688 | /* 5763 */ "shllv.ph\t\000" |
| 689 | /* 5773 */ "replv.ph\t\000" |
| 690 | /* 5783 */ "shrlv.ph\t\000" |
| 691 | /* 5793 */ "dpa.w.ph\t\000" |
| 692 | /* 5803 */ "dpaqx_sa.w.ph\t\000" |
| 693 | /* 5818 */ "dpsqx_sa.w.ph\t\000" |
| 694 | /* 5833 */ "mulsa.w.ph\t\000" |
| 695 | /* 5845 */ "dpaq_s.w.ph\t\000" |
| 696 | /* 5858 */ "mulsaq_s.w.ph\t\000" |
| 697 | /* 5873 */ "dpsq_s.w.ph\t\000" |
| 698 | /* 5886 */ "dpaqx_s.w.ph\t\000" |
| 699 | /* 5900 */ "dpsqx_s.w.ph\t\000" |
| 700 | /* 5914 */ "dps.w.ph\t\000" |
| 701 | /* 5924 */ "dpax.w.ph\t\000" |
| 702 | /* 5935 */ "dpsx.w.ph\t\000" |
| 703 | /* 5946 */ "ush\t\000" |
| 704 | /* 5951 */ "dmuh\t\000" |
| 705 | /* 5957 */ "synci\t\000" |
| 706 | /* 5964 */ "daddi\t\000" |
| 707 | /* 5971 */ "andi\t\000" |
| 708 | /* 5977 */ "tgei\t\000" |
| 709 | /* 5983 */ "snei\t\000" |
| 710 | /* 5989 */ "tnei\t\000" |
| 711 | /* 5995 */ "dahi\t\000" |
| 712 | /* 6001 */ "mfhi\t\000" |
| 713 | /* 6007 */ "mthi\t\000" |
| 714 | /* 6013 */ ".align 2\n\tli\t\000" |
| 715 | /* 6027 */ "dli\t\000" |
| 716 | /* 6032 */ "cmpi\t\000" |
| 717 | /* 6038 */ "seqi\t\000" |
| 718 | /* 6044 */ "teqi\t\000" |
| 719 | /* 6050 */ "xori\t\000" |
| 720 | /* 6056 */ "dati\t\000" |
| 721 | /* 6062 */ "slti\t\000" |
| 722 | /* 6068 */ "tlti\t\000" |
| 723 | /* 6074 */ "daui\t\000" |
| 724 | /* 6080 */ "lui\t\000" |
| 725 | /* 6085 */ "ginvi\t\000" |
| 726 | /* 6092 */ "j\t\000" |
| 727 | /* 6095 */ "break\t\000" |
| 728 | /* 6102 */ "fork\t\000" |
| 729 | /* 6108 */ "cvt.d.l\t\000" |
| 730 | /* 6117 */ "cvt.s.l\t\000" |
| 731 | /* 6126 */ "bal\t\000" |
| 732 | /* 6131 */ "jal\t\000" |
| 733 | /* 6136 */ "bgezal\t\000" |
| 734 | /* 6144 */ "bltzal\t\000" |
| 735 | /* 6152 */ "dpau.h.qbl\t\000" |
| 736 | /* 6164 */ "dpsu.h.qbl\t\000" |
| 737 | /* 6176 */ "muleu_s.ph.qbl\t\000" |
| 738 | /* 6192 */ "preceu.ph.qbl\t\000" |
| 739 | /* 6207 */ "precequ.ph.qbl\t\000" |
| 740 | /* 6223 */ "ldl\t\000" |
| 741 | /* 6228 */ "sdl\t\000" |
| 742 | /* 6233 */ "bgel\t\000" |
| 743 | /* 6239 */ "blel\t\000" |
| 744 | /* 6245 */ "bnel\t\000" |
| 745 | /* 6251 */ "bc1fl\t\000" |
| 746 | /* 6258 */ "maq_sa.w.phl\t\000" |
| 747 | /* 6272 */ "preceq.w.phl\t\000" |
| 748 | /* 6286 */ "maq_s.w.phl\t\000" |
| 749 | /* 6299 */ "muleq_s.w.phl\t\000" |
| 750 | /* 6314 */ "hypcall\t\000" |
| 751 | /* 6323 */ "syscall\t\000" |
| 752 | /* 6332 */ "bgezall\t\000" |
| 753 | /* 6341 */ "bltzall\t\000" |
| 754 | /* 6350 */ "dsll\t\000" |
| 755 | /* 6356 */ "drol\t\000" |
| 756 | /* 6362 */ "cvt.s.pl\t\000" |
| 757 | /* 6372 */ "beql\t\000" |
| 758 | /* 6378 */ "dsrl\t\000" |
| 759 | /* 6384 */ "bc1tl\t\000" |
| 760 | /* 6391 */ "bgtl\t\000" |
| 761 | /* 6397 */ "bltl\t\000" |
| 762 | /* 6403 */ "bgeul\t\000" |
| 763 | /* 6410 */ "bleul\t\000" |
| 764 | /* 6417 */ "dmul\t\000" |
| 765 | /* 6423 */ "bgtul\t\000" |
| 766 | /* 6430 */ "bltul\t\000" |
| 767 | /* 6437 */ "lwl\t\000" |
| 768 | /* 6442 */ "swl\t\000" |
| 769 | /* 6447 */ "bgezl\t\000" |
| 770 | /* 6454 */ "blezl\t\000" |
| 771 | /* 6461 */ "bgtzl\t\000" |
| 772 | /* 6468 */ "bltzl\t\000" |
| 773 | /* 6475 */ "drem\t\000" |
| 774 | /* 6481 */ "dinsm\t\000" |
| 775 | /* 6488 */ "dextm\t\000" |
| 776 | /* 6495 */ "lwm\t\000" |
| 777 | /* 6500 */ "swm\t\000" |
| 778 | /* 6505 */ "balign\t\000" |
| 779 | /* 6513 */ "dalign\t\000" |
| 780 | /* 6521 */ "movn\t\000" |
| 781 | /* 6527 */ "dclo\t\000" |
| 782 | /* 6533 */ "mflo\t\000" |
| 783 | /* 6539 */ "shilo\t\000" |
| 784 | /* 6546 */ "mtlo\t\000" |
| 785 | /* 6552 */ "dmulo\t\000" |
| 786 | /* 6559 */ "dbitswap\t\000" |
| 787 | /* 6569 */ "sdbbp\t\000" |
| 788 | /* 6576 */ "extpdp\t\000" |
| 789 | /* 6584 */ "movep\t\000" |
| 790 | /* 6591 */ "mthlip\t\000" |
| 791 | /* 6599 */ "cmp\t\000" |
| 792 | /* 6604 */ "dpop\t\000" |
| 793 | /* 6610 */ "addiur1sp\t\000" |
| 794 | /* 6621 */ "load_ccond_dsp\t\000" |
| 795 | /* 6637 */ "store_ccond_dsp\t\000" |
| 796 | /* 6654 */ "rddsp\t\000" |
| 797 | /* 6661 */ "wrdsp\t\000" |
| 798 | /* 6668 */ "jrcaddiusp\t\000" |
| 799 | /* 6680 */ "jraddiusp\t\000" |
| 800 | /* 6691 */ "swsp\t\000" |
| 801 | /* 6697 */ "extp\t\000" |
| 802 | /* 6703 */ "dvp\t\000" |
| 803 | /* 6708 */ "evp\t\000" |
| 804 | /* 6713 */ "lwp\t\000" |
| 805 | /* 6718 */ "swp\t\000" |
| 806 | /* 6723 */ "beq\t\000" |
| 807 | /* 6728 */ "seq\t\000" |
| 808 | /* 6733 */ "teq\t\000" |
| 809 | /* 6738 */ "dpau.h.qbr\t\000" |
| 810 | /* 6750 */ "dpsu.h.qbr\t\000" |
| 811 | /* 6762 */ "muleu_s.ph.qbr\t\000" |
| 812 | /* 6778 */ "preceu.ph.qbr\t\000" |
| 813 | /* 6793 */ "precequ.ph.qbr\t\000" |
| 814 | /* 6809 */ "ldr\t\000" |
| 815 | /* 6814 */ "sdr\t\000" |
| 816 | /* 6819 */ "maq_sa.w.phr\t\000" |
| 817 | /* 6833 */ "preceq.w.phr\t\000" |
| 818 | /* 6847 */ "maq_s.w.phr\t\000" |
| 819 | /* 6860 */ "muleq_s.w.phr\t\000" |
| 820 | /* 6875 */ "jr\t\000" |
| 821 | /* 6879 */ "jalr\t\000" |
| 822 | /* 6885 */ "nor\t\000" |
| 823 | /* 6890 */ "dror\t\000" |
| 824 | /* 6896 */ "xor\t\000" |
| 825 | /* 6901 */ "rdpgpr\t\000" |
| 826 | /* 6909 */ "wrpgpr\t\000" |
| 827 | /* 6917 */ "mftr\t\000" |
| 828 | /* 6923 */ "drotr\t\000" |
| 829 | /* 6930 */ "mttr\t\000" |
| 830 | /* 6936 */ "rdhwr\t\000" |
| 831 | /* 6943 */ "lwr\t\000" |
| 832 | /* 6948 */ "swr\t\000" |
| 833 | /* 6953 */ "mina.s\t\000" |
| 834 | /* 6961 */ "maxa.s\t\000" |
| 835 | /* 6969 */ "nmsub.s\t\000" |
| 836 | /* 6978 */ "cvt.d.s\t\000" |
| 837 | /* 6987 */ "nmadd.s\t\000" |
| 838 | /* 6996 */ "c.nge.s\t\000" |
| 839 | /* 7005 */ "c.le.s\t\000" |
| 840 | /* 7013 */ "cmp.le.s\t\000" |
| 841 | /* 7023 */ "c.ngle.s\t\000" |
| 842 | /* 7033 */ "c.ole.s\t\000" |
| 843 | /* 7042 */ "cmp.sle.s\t\000" |
| 844 | /* 7053 */ "c.ule.s\t\000" |
| 845 | /* 7062 */ "cmp.ule.s\t\000" |
| 846 | /* 7073 */ "cmp.sule.s\t\000" |
| 847 | /* 7085 */ "c.f.s\t\000" |
| 848 | /* 7092 */ "cmp.af.s\t\000" |
| 849 | /* 7102 */ "cmp.saf.s\t\000" |
| 850 | /* 7113 */ "msubf.s\t\000" |
| 851 | /* 7122 */ "maddf.s\t\000" |
| 852 | /* 7131 */ "c.sf.s\t\000" |
| 853 | /* 7139 */ "movf.s\t\000" |
| 854 | /* 7147 */ "neg.s\t\000" |
| 855 | /* 7154 */ "li.s\t\000" |
| 856 | /* 7160 */ "trunc.l.s\t\000" |
| 857 | /* 7171 */ "round.l.s\t\000" |
| 858 | /* 7182 */ "ceil.l.s\t\000" |
| 859 | /* 7192 */ "floor.l.s\t\000" |
| 860 | /* 7203 */ "cvt.l.s\t\000" |
| 861 | /* 7212 */ "sel.s\t\000" |
| 862 | /* 7219 */ "c.ngl.s\t\000" |
| 863 | /* 7228 */ "mul.s\t\000" |
| 864 | /* 7235 */ "min.s\t\000" |
| 865 | /* 7242 */ "c.un.s\t\000" |
| 866 | /* 7250 */ "cmp.un.s\t\000" |
| 867 | /* 7260 */ "cmp.sun.s\t\000" |
| 868 | /* 7271 */ "movn.s\t\000" |
| 869 | /* 7279 */ "recip.s\t\000" |
| 870 | /* 7288 */ "c.eq.s\t\000" |
| 871 | /* 7296 */ "cmp.eq.s\t\000" |
| 872 | /* 7306 */ "c.seq.s\t\000" |
| 873 | /* 7315 */ "cmp.seq.s\t\000" |
| 874 | /* 7326 */ "c.ueq.s\t\000" |
| 875 | /* 7335 */ "cmp.ueq.s\t\000" |
| 876 | /* 7346 */ "cmp.sueq.s\t\000" |
| 877 | /* 7358 */ "abs.s\t\000" |
| 878 | /* 7365 */ "cvt.ps.s\t\000" |
| 879 | /* 7375 */ "class.s\t\000" |
| 880 | /* 7384 */ "c.ngt.s\t\000" |
| 881 | /* 7393 */ "c.lt.s\t\000" |
| 882 | /* 7401 */ "cmp.lt.s\t\000" |
| 883 | /* 7411 */ "c.olt.s\t\000" |
| 884 | /* 7420 */ "cmp.slt.s\t\000" |
| 885 | /* 7431 */ "c.ult.s\t\000" |
| 886 | /* 7440 */ "cmp.ult.s\t\000" |
| 887 | /* 7451 */ "cmp.sult.s\t\000" |
| 888 | /* 7463 */ "rint.s\t\000" |
| 889 | /* 7471 */ "rsqrt.s\t\000" |
| 890 | /* 7480 */ "movt.s\t\000" |
| 891 | /* 7488 */ "div.s\t\000" |
| 892 | /* 7495 */ "mov.s\t\000" |
| 893 | /* 7502 */ "trunc.w.s\t\000" |
| 894 | /* 7513 */ "round.w.s\t\000" |
| 895 | /* 7524 */ "ceil.w.s\t\000" |
| 896 | /* 7534 */ "floor.w.s\t\000" |
| 897 | /* 7545 */ "cvt.w.s\t\000" |
| 898 | /* 7554 */ "max.s\t\000" |
| 899 | /* 7561 */ "selnez.s\t\000" |
| 900 | /* 7571 */ "seleqz.s\t\000" |
| 901 | /* 7581 */ "movz.s\t\000" |
| 902 | /* 7589 */ "abs\t\000" |
| 903 | /* 7594 */ "jals\t\000" |
| 904 | /* 7600 */ "bgezals\t\000" |
| 905 | /* 7609 */ "bltzals\t\000" |
| 906 | /* 7618 */ "cins\t\000" |
| 907 | /* 7624 */ "dins\t\000" |
| 908 | /* 7630 */ "sub.ps\t\000" |
| 909 | /* 7638 */ "add.ps\t\000" |
| 910 | /* 7646 */ "pll.ps\t\000" |
| 911 | /* 7654 */ "mul.ps\t\000" |
| 912 | /* 7662 */ "pul.ps\t\000" |
| 913 | /* 7670 */ "addr.ps\t\000" |
| 914 | /* 7679 */ "mulr.ps\t\000" |
| 915 | /* 7688 */ "plu.ps\t\000" |
| 916 | /* 7696 */ "puu.ps\t\000" |
| 917 | /* 7704 */ "cvt.pw.ps\t\000" |
| 918 | /* 7715 */ "jalrs\t\000" |
| 919 | /* 7722 */ "exts\t\000" |
| 920 | /* 7728 */ "lwxs\t\000" |
| 921 | /* 7734 */ "bc1t\t\000" |
| 922 | /* 7740 */ "bgt\t\000" |
| 923 | /* 7745 */ "sgt\t\000" |
| 924 | /* 7750 */ "wait\t\000" |
| 925 | /* 7756 */ "blt\t\000" |
| 926 | /* 7761 */ "slt\t\000" |
| 927 | /* 7766 */ "tlt\t\000" |
| 928 | /* 7771 */ "dmult\t\000" |
| 929 | /* 7778 */ "dmt\t\000" |
| 930 | /* 7783 */ "emt\t\000" |
| 931 | /* 7788 */ "not\t\000" |
| 932 | /* 7793 */ "ginvt\t\000" |
| 933 | /* 7800 */ "movt\t\000" |
| 934 | /* 7806 */ "dext\t\000" |
| 935 | /* 7812 */ "lbu\t\000" |
| 936 | /* 7817 */ "dsubu\t\000" |
| 937 | /* 7824 */ "msubu\t\000" |
| 938 | /* 7831 */ "baddu\t\000" |
| 939 | /* 7838 */ "daddu\t\000" |
| 940 | /* 7845 */ "maddu\t\000" |
| 941 | /* 7852 */ "dmodu\t\000" |
| 942 | /* 7859 */ "bgeu\t\000" |
| 943 | /* 7865 */ "sgeu\t\000" |
| 944 | /* 7871 */ "tgeu\t\000" |
| 945 | /* 7877 */ "bleu\t\000" |
| 946 | /* 7883 */ "sleu\t\000" |
| 947 | /* 7889 */ "ulhu\t\000" |
| 948 | /* 7895 */ "dmuhu\t\000" |
| 949 | /* 7902 */ "daddiu\t\000" |
| 950 | /* 7910 */ "tgeiu\t\000" |
| 951 | /* 7917 */ "sltiu\t\000" |
| 952 | /* 7924 */ "tltiu\t\000" |
| 953 | /* 7931 */ "v3mulu\t\000" |
| 954 | /* 7939 */ "dmulu\t\000" |
| 955 | /* 7946 */ "vmulu\t\000" |
| 956 | /* 7953 */ "dremu\t\000" |
| 957 | /* 7960 */ "dmulou\t\000" |
| 958 | /* 7968 */ "cvt.s.pu\t\000" |
| 959 | /* 7978 */ "dinsu\t\000" |
| 960 | /* 7985 */ "bgtu\t\000" |
| 961 | /* 7991 */ "sgtu\t\000" |
| 962 | /* 7997 */ "bltu\t\000" |
| 963 | /* 8003 */ "sltu\t\000" |
| 964 | /* 8009 */ "tltu\t\000" |
| 965 | /* 8015 */ "dmultu\t\000" |
| 966 | /* 8023 */ "dextu\t\000" |
| 967 | /* 8030 */ "ddivu\t\000" |
| 968 | /* 8037 */ "lwu\t\000" |
| 969 | /* 8042 */ "and.v\t\000" |
| 970 | /* 8049 */ "move.v\t\000" |
| 971 | /* 8057 */ "bsel.v\t\000" |
| 972 | /* 8065 */ "nor.v\t\000" |
| 973 | /* 8072 */ "xor.v\t\000" |
| 974 | /* 8079 */ "bz.v\t\000" |
| 975 | /* 8085 */ "bmz.v\t\000" |
| 976 | /* 8092 */ "bnz.v\t\000" |
| 977 | /* 8099 */ "bmnz.v\t\000" |
| 978 | /* 8107 */ "dsrav\t\000" |
| 979 | /* 8114 */ "bitrev\t\000" |
| 980 | /* 8122 */ "ddiv\t\000" |
| 981 | /* 8128 */ "dsllv\t\000" |
| 982 | /* 8135 */ "dsrlv\t\000" |
| 983 | /* 8142 */ "shilov\t\000" |
| 984 | /* 8150 */ "extpdpv\t\000" |
| 985 | /* 8159 */ "extpv\t\000" |
| 986 | /* 8166 */ "drotrv\t\000" |
| 987 | /* 8174 */ "insv\t\000" |
| 988 | /* 8180 */ "flog2.w\t\000" |
| 989 | /* 8189 */ "fexp2.w\t\000" |
| 990 | /* 8198 */ "add_a.w\t\000" |
| 991 | /* 8207 */ "fmin_a.w\t\000" |
| 992 | /* 8217 */ "adds_a.w\t\000" |
| 993 | /* 8227 */ "fmax_a.w\t\000" |
| 994 | /* 8237 */ "sra.w\t\000" |
| 995 | /* 8244 */ "fsub.w\t\000" |
| 996 | /* 8252 */ "fmsub.w\t\000" |
| 997 | /* 8261 */ "nloc.w\t\000" |
| 998 | /* 8269 */ "nlzc.w\t\000" |
| 999 | /* 8277 */ "cvt.d.w\t\000" |
| 1000 | /* 8286 */ "fadd.w\t\000" |
| 1001 | /* 8294 */ "fmadd.w\t\000" |
| 1002 | /* 8303 */ "sld.w\t\000" |
| 1003 | /* 8310 */ "pckod.w\t\000" |
| 1004 | /* 8319 */ "ilvod.w\t\000" |
| 1005 | /* 8328 */ "fcle.w\t\000" |
| 1006 | /* 8336 */ "fsle.w\t\000" |
| 1007 | /* 8344 */ "fcule.w\t\000" |
| 1008 | /* 8353 */ "fsule.w\t\000" |
| 1009 | /* 8362 */ "fcne.w\t\000" |
| 1010 | /* 8370 */ "fsne.w\t\000" |
| 1011 | /* 8378 */ "fcune.w\t\000" |
| 1012 | /* 8387 */ "fsune.w\t\000" |
| 1013 | /* 8396 */ "insve.w\t\000" |
| 1014 | /* 8405 */ "fcaf.w\t\000" |
| 1015 | /* 8413 */ "fsaf.w\t\000" |
| 1016 | /* 8421 */ "vshf.w\t\000" |
| 1017 | /* 8429 */ "bneg.w\t\000" |
| 1018 | /* 8437 */ "precr_sra.ph.w\t\000" |
| 1019 | /* 8453 */ "precrq.ph.w\t\000" |
| 1020 | /* 8466 */ "precr_sra_r.ph.w\t\000" |
| 1021 | /* 8484 */ "precrq_rs.ph.w\t\000" |
| 1022 | /* 8500 */ "subqh.w\t\000" |
| 1023 | /* 8509 */ "addqh.w\t\000" |
| 1024 | /* 8518 */ "srai.w\t\000" |
| 1025 | /* 8526 */ "sldi.w\t\000" |
| 1026 | /* 8534 */ "bnegi.w\t\000" |
| 1027 | /* 8543 */ "slli.w\t\000" |
| 1028 | /* 8551 */ "srli.w\t\000" |
| 1029 | /* 8559 */ "binsli.w\t\000" |
| 1030 | /* 8569 */ "ceqi.w\t\000" |
| 1031 | /* 8577 */ "srari.w\t\000" |
| 1032 | /* 8586 */ "bclri.w\t\000" |
| 1033 | /* 8595 */ "srlri.w\t\000" |
| 1034 | /* 8604 */ "binsri.w\t\000" |
| 1035 | /* 8614 */ "splati.w\t\000" |
| 1036 | /* 8624 */ "bseti.w\t\000" |
| 1037 | /* 8633 */ "subvi.w\t\000" |
| 1038 | /* 8642 */ "addvi.w\t\000" |
| 1039 | /* 8651 */ "dpaq_sa.l.w\t\000" |
| 1040 | /* 8664 */ "dpsq_sa.l.w\t\000" |
| 1041 | /* 8677 */ "fill.w\t\000" |
| 1042 | /* 8685 */ "sll.w\t\000" |
| 1043 | /* 8692 */ "fexupl.w\t\000" |
| 1044 | /* 8702 */ "ffql.w\t\000" |
| 1045 | /* 8710 */ "srl.w\t\000" |
| 1046 | /* 8717 */ "binsl.w\t\000" |
| 1047 | /* 8726 */ "fmul.w\t\000" |
| 1048 | /* 8734 */ "ilvl.w\t\000" |
| 1049 | /* 8742 */ "fmin.w\t\000" |
| 1050 | /* 8750 */ "fcun.w\t\000" |
| 1051 | /* 8758 */ "fsun.w\t\000" |
| 1052 | /* 8766 */ "fexdo.w\t\000" |
| 1053 | /* 8775 */ "frcp.w\t\000" |
| 1054 | /* 8783 */ "msub_q.w\t\000" |
| 1055 | /* 8793 */ "madd_q.w\t\000" |
| 1056 | /* 8803 */ "mul_q.w\t\000" |
| 1057 | /* 8812 */ "msubr_q.w\t\000" |
| 1058 | /* 8823 */ "maddr_q.w\t\000" |
| 1059 | /* 8834 */ "mulr_q.w\t\000" |
| 1060 | /* 8844 */ "fceq.w\t\000" |
| 1061 | /* 8852 */ "fseq.w\t\000" |
| 1062 | /* 8860 */ "fcueq.w\t\000" |
| 1063 | /* 8869 */ "fsueq.w\t\000" |
| 1064 | /* 8878 */ "ftq.w\t\000" |
| 1065 | /* 8885 */ "shra_r.w\t\000" |
| 1066 | /* 8895 */ "subqh_r.w\t\000" |
| 1067 | /* 8906 */ "addqh_r.w\t\000" |
| 1068 | /* 8917 */ "extr_r.w\t\000" |
| 1069 | /* 8927 */ "shrav_r.w\t\000" |
| 1070 | /* 8938 */ "extrv_r.w\t\000" |
| 1071 | /* 8949 */ "srar.w\t\000" |
| 1072 | /* 8957 */ "bclr.w\t\000" |
| 1073 | /* 8965 */ "srlr.w\t\000" |
| 1074 | /* 8973 */ "fcor.w\t\000" |
| 1075 | /* 8981 */ "fsor.w\t\000" |
| 1076 | /* 8989 */ "fexupr.w\t\000" |
| 1077 | /* 8999 */ "ffqr.w\t\000" |
| 1078 | /* 9007 */ "binsr.w\t\000" |
| 1079 | /* 9016 */ "extr.w\t\000" |
| 1080 | /* 9024 */ "ilvr.w\t\000" |
| 1081 | /* 9032 */ "cvt.s.w\t\000" |
| 1082 | /* 9041 */ "asub_s.w\t\000" |
| 1083 | /* 9051 */ "hsub_s.w\t\000" |
| 1084 | /* 9061 */ "dpsub_s.w\t\000" |
| 1085 | /* 9072 */ "ftrunc_s.w\t\000" |
| 1086 | /* 9084 */ "hadd_s.w\t\000" |
| 1087 | /* 9094 */ "dpadd_s.w\t\000" |
| 1088 | /* 9105 */ "mod_s.w\t\000" |
| 1089 | /* 9114 */ "cle_s.w\t\000" |
| 1090 | /* 9123 */ "ave_s.w\t\000" |
| 1091 | /* 9132 */ "clei_s.w\t\000" |
| 1092 | /* 9142 */ "mini_s.w\t\000" |
| 1093 | /* 9152 */ "clti_s.w\t\000" |
| 1094 | /* 9162 */ "maxi_s.w\t\000" |
| 1095 | /* 9172 */ "shll_s.w\t\000" |
| 1096 | /* 9182 */ "min_s.w\t\000" |
| 1097 | /* 9191 */ "dotp_s.w\t\000" |
| 1098 | /* 9201 */ "subq_s.w\t\000" |
| 1099 | /* 9211 */ "addq_s.w\t\000" |
| 1100 | /* 9221 */ "mulq_s.w\t\000" |
| 1101 | /* 9231 */ "absq_s.w\t\000" |
| 1102 | /* 9241 */ "aver_s.w\t\000" |
| 1103 | /* 9251 */ "subs_s.w\t\000" |
| 1104 | /* 9261 */ "adds_s.w\t\000" |
| 1105 | /* 9271 */ "sat_s.w\t\000" |
| 1106 | /* 9280 */ "clt_s.w\t\000" |
| 1107 | /* 9289 */ "ffint_s.w\t\000" |
| 1108 | /* 9300 */ "ftint_s.w\t\000" |
| 1109 | /* 9311 */ "subsuu_s.w\t\000" |
| 1110 | /* 9323 */ "div_s.w\t\000" |
| 1111 | /* 9332 */ "shllv_s.w\t\000" |
| 1112 | /* 9343 */ "max_s.w\t\000" |
| 1113 | /* 9352 */ "copy_s.w\t\000" |
| 1114 | /* 9362 */ "mulq_rs.w\t\000" |
| 1115 | /* 9373 */ "extr_rs.w\t\000" |
| 1116 | /* 9384 */ "extrv_rs.w\t\000" |
| 1117 | /* 9396 */ "fclass.w\t\000" |
| 1118 | /* 9406 */ "splat.w\t\000" |
| 1119 | /* 9415 */ "bset.w\t\000" |
| 1120 | /* 9423 */ "fclt.w\t\000" |
| 1121 | /* 9431 */ "fslt.w\t\000" |
| 1122 | /* 9439 */ "fcult.w\t\000" |
| 1123 | /* 9448 */ "fsult.w\t\000" |
| 1124 | /* 9457 */ "pcnt.w\t\000" |
| 1125 | /* 9465 */ "frint.w\t\000" |
| 1126 | /* 9474 */ "insert.w\t\000" |
| 1127 | /* 9484 */ "fsqrt.w\t\000" |
| 1128 | /* 9493 */ "frsqrt.w\t\000" |
| 1129 | /* 9503 */ "st.w\t\000" |
| 1130 | /* 9509 */ "asub_u.w\t\000" |
| 1131 | /* 9519 */ "hsub_u.w\t\000" |
| 1132 | /* 9529 */ "dpsub_u.w\t\000" |
| 1133 | /* 9540 */ "ftrunc_u.w\t\000" |
| 1134 | /* 9552 */ "hadd_u.w\t\000" |
| 1135 | /* 9562 */ "dpadd_u.w\t\000" |
| 1136 | /* 9573 */ "mod_u.w\t\000" |
| 1137 | /* 9582 */ "cle_u.w\t\000" |
| 1138 | /* 9591 */ "ave_u.w\t\000" |
| 1139 | /* 9600 */ "clei_u.w\t\000" |
| 1140 | /* 9610 */ "mini_u.w\t\000" |
| 1141 | /* 9620 */ "clti_u.w\t\000" |
| 1142 | /* 9630 */ "maxi_u.w\t\000" |
| 1143 | /* 9640 */ "min_u.w\t\000" |
| 1144 | /* 9649 */ "dotp_u.w\t\000" |
| 1145 | /* 9659 */ "aver_u.w\t\000" |
| 1146 | /* 9669 */ "subs_u.w\t\000" |
| 1147 | /* 9679 */ "adds_u.w\t\000" |
| 1148 | /* 9689 */ "subsus_u.w\t\000" |
| 1149 | /* 9701 */ "sat_u.w\t\000" |
| 1150 | /* 9710 */ "clt_u.w\t\000" |
| 1151 | /* 9719 */ "ffint_u.w\t\000" |
| 1152 | /* 9730 */ "ftint_u.w\t\000" |
| 1153 | /* 9741 */ "div_u.w\t\000" |
| 1154 | /* 9750 */ "max_u.w\t\000" |
| 1155 | /* 9759 */ "copy_u.w\t\000" |
| 1156 | /* 9769 */ "msubv.w\t\000" |
| 1157 | /* 9778 */ "maddv.w\t\000" |
| 1158 | /* 9787 */ "pckev.w\t\000" |
| 1159 | /* 9796 */ "ilvev.w\t\000" |
| 1160 | /* 9805 */ "fdiv.w\t\000" |
| 1161 | /* 9813 */ "mulv.w\t\000" |
| 1162 | /* 9821 */ "extrv.w\t\000" |
| 1163 | /* 9830 */ "fmax.w\t\000" |
| 1164 | /* 9838 */ "bz.w\t\000" |
| 1165 | /* 9844 */ "bnz.w\t\000" |
| 1166 | /* 9851 */ "crc32w\t\000" |
| 1167 | /* 9859 */ "crc32cw\t\000" |
| 1168 | /* 9868 */ "ulw\t\000" |
| 1169 | /* 9873 */ "cvt.ps.pw\t\000" |
| 1170 | /* 9884 */ "usw\t\000" |
| 1171 | /* 9889 */ "prefx\t\000" |
| 1172 | /* 9896 */ "lhx\t\000" |
| 1173 | /* 9901 */ "jalx\t\000" |
| 1174 | /* 9907 */ "lbux\t\000" |
| 1175 | /* 9913 */ "lwx\t\000" |
| 1176 | /* 9918 */ "bgez\t\000" |
| 1177 | /* 9924 */ "blez\t\000" |
| 1178 | /* 9930 */ "bnez\t\000" |
| 1179 | /* 9936 */ "selnez\t\000" |
| 1180 | /* 9944 */ "btnez\t\000" |
| 1181 | /* 9951 */ "dclz\t\000" |
| 1182 | /* 9957 */ "beqz\t\000" |
| 1183 | /* 9963 */ "seleqz\t\000" |
| 1184 | /* 9971 */ "bteqz\t\000" |
| 1185 | /* 9978 */ "bgtz\t\000" |
| 1186 | /* 9984 */ "bltz\t\000" |
| 1187 | /* 9990 */ "movz\t\000" |
| 1188 | /* 9996 */ "seb\t \000" |
| 1189 | /* 10002 */ "seh\t \000" |
| 1190 | /* 10008 */ "ddivu\t$zero, \000" |
| 1191 | /* 10022 */ "ddiv\t$zero, \000" |
| 1192 | /* 10035 */ "addiu\t$sp, \000" |
| 1193 | /* 10047 */ "mftc0 \000" |
| 1194 | /* 10054 */ "mttc0 \000" |
| 1195 | /* 10061 */ "mfthc1 \000" |
| 1196 | /* 10069 */ "mtthc1 \000" |
| 1197 | /* 10077 */ "cftc1 \000" |
| 1198 | /* 10084 */ "mftc1 \000" |
| 1199 | /* 10091 */ "cttc1 \000" |
| 1200 | /* 10098 */ "mttc1 \000" |
| 1201 | /* 10105 */ "sync \000" |
| 1202 | /* 10111 */ "ld \000" |
| 1203 | /* 10115 */ "\t.word \000" |
| 1204 | /* 10123 */ "sd \000" |
| 1205 | /* 10127 */ "sne \000" |
| 1206 | /* 10132 */ "mfthi \000" |
| 1207 | /* 10139 */ "mtthi \000" |
| 1208 | /* 10146 */ "mftlo \000" |
| 1209 | /* 10153 */ "mttlo \000" |
| 1210 | /* 10160 */ "mftdsp \000" |
| 1211 | /* 10168 */ "mttdsp \000" |
| 1212 | /* 10176 */ "seq \000" |
| 1213 | /* 10181 */ "mftgpr \000" |
| 1214 | /* 10189 */ "mttgpr \000" |
| 1215 | /* 10197 */ "dext \000" |
| 1216 | /* 10203 */ "mftacx \000" |
| 1217 | /* 10211 */ "mttacx \000" |
| 1218 | /* 10219 */ "bc1nez \000" |
| 1219 | /* 10227 */ "bc2nez \000" |
| 1220 | /* 10235 */ "bc1eqz \000" |
| 1221 | /* 10243 */ "bc2eqz \000" |
| 1222 | /* 10251 */ "# XRay Function Patchable RET.\000" |
| 1223 | /* 10282 */ "c.\000" |
| 1224 | /* 10285 */ "# XRay Typed Event Log.\000" |
| 1225 | /* 10309 */ "# XRay Custom Event Log.\000" |
| 1226 | /* 10334 */ "# XRay Function Enter.\000" |
| 1227 | /* 10357 */ "# XRay Tail Call Exit.\000" |
| 1228 | /* 10380 */ "# XRay Function Exit.\000" |
| 1229 | /* 10402 */ "break 0\000" |
| 1230 | /* 10410 */ "LIFETIME_END\000" |
| 1231 | /* 10423 */ "PSEUDO_PROBE\000" |
| 1232 | /* 10436 */ "BUNDLE\000" |
| 1233 | /* 10443 */ "FAKE_USE\000" |
| 1234 | /* 10452 */ "DBG_VALUE\000" |
| 1235 | /* 10462 */ "DBG_INSTR_REF\000" |
| 1236 | /* 10476 */ "DBG_PHI\000" |
| 1237 | /* 10484 */ "DBG_LABEL\000" |
| 1238 | /* 10494 */ "LIFETIME_START\000" |
| 1239 | /* 10509 */ "DBG_VALUE_LIST\000" |
| 1240 | /* 10524 */ "jrc\t$ra\000" |
| 1241 | /* 10532 */ "jr\t$ra\000" |
| 1242 | /* 10539 */ "ehb\000" |
| 1243 | /* 10543 */ "eretnc\000" |
| 1244 | /* 10550 */ "pause\000" |
| 1245 | /* 10556 */ "tlbinvf\000" |
| 1246 | /* 10564 */ "tlbginvf\000" |
| 1247 | /* 10573 */ "tlbwi\000" |
| 1248 | /* 10579 */ "tlbgwi\000" |
| 1249 | /* 10586 */ "nal\000" |
| 1250 | /* 10590 */ "# FEntry call\000" |
| 1251 | /* 10604 */ "foo\000" |
| 1252 | /* 10608 */ "tlbp\000" |
| 1253 | /* 10613 */ "tlbgp\000" |
| 1254 | /* 10619 */ "ssnop\000" |
| 1255 | /* 10625 */ "tlbr\000" |
| 1256 | /* 10630 */ "tlbgr\000" |
| 1257 | /* 10636 */ "tlbwr\000" |
| 1258 | /* 10642 */ "tlbgwr\000" |
| 1259 | /* 10649 */ "deret\000" |
| 1260 | /* 10655 */ "wait\000" |
| 1261 | /* 10660 */ "tlbinv\000" |
| 1262 | /* 10667 */ "tlbginv\000" |
| 1263 | }; |
| 1264 | #ifdef __GNUC__ |
| 1265 | #pragma GCC diagnostic pop |
| 1266 | #endif |
| 1267 | |
| 1268 | static const uint32_t OpInfo0[] = { |
| 1269 | 0U, // PHI |
| 1270 | 0U, // INLINEASM |
| 1271 | 0U, // INLINEASM_BR |
| 1272 | 0U, // CFI_INSTRUCTION |
| 1273 | 0U, // EH_LABEL |
| 1274 | 0U, // GC_LABEL |
| 1275 | 0U, // ANNOTATION_LABEL |
| 1276 | 0U, // KILL |
| 1277 | 0U, // EXTRACT_SUBREG |
| 1278 | 0U, // INSERT_SUBREG |
| 1279 | 0U, // IMPLICIT_DEF |
| 1280 | 0U, // INIT_UNDEF |
| 1281 | 0U, // SUBREG_TO_REG |
| 1282 | 0U, // COPY_TO_REGCLASS |
| 1283 | 10453U, // DBG_VALUE |
| 1284 | 10510U, // DBG_VALUE_LIST |
| 1285 | 10463U, // DBG_INSTR_REF |
| 1286 | 10477U, // DBG_PHI |
| 1287 | 10485U, // DBG_LABEL |
| 1288 | 0U, // REG_SEQUENCE |
| 1289 | 0U, // COPY |
| 1290 | 10437U, // BUNDLE |
| 1291 | 10495U, // LIFETIME_START |
| 1292 | 10411U, // LIFETIME_END |
| 1293 | 10424U, // PSEUDO_PROBE |
| 1294 | 0U, // ARITH_FENCE |
| 1295 | 0U, // STACKMAP |
| 1296 | 10591U, // FENTRY_CALL |
| 1297 | 0U, // PATCHPOINT |
| 1298 | 0U, // LOAD_STACK_GUARD |
| 1299 | 0U, // PREALLOCATED_SETUP |
| 1300 | 0U, // PREALLOCATED_ARG |
| 1301 | 0U, // STATEPOINT |
| 1302 | 0U, // LOCAL_ESCAPE |
| 1303 | 0U, // FAULTING_OP |
| 1304 | 0U, // PATCHABLE_OP |
| 1305 | 10335U, // PATCHABLE_FUNCTION_ENTER |
| 1306 | 10252U, // PATCHABLE_RET |
| 1307 | 10381U, // PATCHABLE_FUNCTION_EXIT |
| 1308 | 10358U, // PATCHABLE_TAIL_CALL |
| 1309 | 10310U, // PATCHABLE_EVENT_CALL |
| 1310 | 10286U, // PATCHABLE_TYPED_EVENT_CALL |
| 1311 | 0U, // ICALL_BRANCH_FUNNEL |
| 1312 | 10444U, // FAKE_USE |
| 1313 | 0U, // MEMBARRIER |
| 1314 | 0U, // JUMP_TABLE_DEBUG_INFO |
| 1315 | 0U, // CONVERGENCECTRL_ENTRY |
| 1316 | 0U, // CONVERGENCECTRL_ANCHOR |
| 1317 | 0U, // CONVERGENCECTRL_LOOP |
| 1318 | 0U, // CONVERGENCECTRL_GLUE |
| 1319 | 0U, // G_ASSERT_SEXT |
| 1320 | 0U, // G_ASSERT_ZEXT |
| 1321 | 0U, // G_ASSERT_ALIGN |
| 1322 | 0U, // G_ADD |
| 1323 | 0U, // G_SUB |
| 1324 | 0U, // G_MUL |
| 1325 | 0U, // G_SDIV |
| 1326 | 0U, // G_UDIV |
| 1327 | 0U, // G_SREM |
| 1328 | 0U, // G_UREM |
| 1329 | 0U, // G_SDIVREM |
| 1330 | 0U, // G_UDIVREM |
| 1331 | 0U, // G_AND |
| 1332 | 0U, // G_OR |
| 1333 | 0U, // G_XOR |
| 1334 | 0U, // G_ABDS |
| 1335 | 0U, // G_ABDU |
| 1336 | 0U, // G_IMPLICIT_DEF |
| 1337 | 0U, // G_PHI |
| 1338 | 0U, // G_FRAME_INDEX |
| 1339 | 0U, // G_GLOBAL_VALUE |
| 1340 | 0U, // G_PTRAUTH_GLOBAL_VALUE |
| 1341 | 0U, // G_CONSTANT_POOL |
| 1342 | 0U, // G_EXTRACT |
| 1343 | 0U, // G_UNMERGE_VALUES |
| 1344 | 0U, // G_INSERT |
| 1345 | 0U, // G_MERGE_VALUES |
| 1346 | 0U, // G_BUILD_VECTOR |
| 1347 | 0U, // G_BUILD_VECTOR_TRUNC |
| 1348 | 0U, // G_CONCAT_VECTORS |
| 1349 | 0U, // G_PTRTOINT |
| 1350 | 0U, // G_INTTOPTR |
| 1351 | 0U, // G_BITCAST |
| 1352 | 0U, // G_FREEZE |
| 1353 | 0U, // G_CONSTANT_FOLD_BARRIER |
| 1354 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 1355 | 0U, // G_INTRINSIC_TRUNC |
| 1356 | 0U, // G_INTRINSIC_ROUND |
| 1357 | 0U, // G_INTRINSIC_LRINT |
| 1358 | 0U, // G_INTRINSIC_LLRINT |
| 1359 | 0U, // G_INTRINSIC_ROUNDEVEN |
| 1360 | 0U, // G_READCYCLECOUNTER |
| 1361 | 0U, // G_READSTEADYCOUNTER |
| 1362 | 0U, // G_LOAD |
| 1363 | 0U, // G_SEXTLOAD |
| 1364 | 0U, // G_ZEXTLOAD |
| 1365 | 0U, // G_INDEXED_LOAD |
| 1366 | 0U, // G_INDEXED_SEXTLOAD |
| 1367 | 0U, // G_INDEXED_ZEXTLOAD |
| 1368 | 0U, // G_STORE |
| 1369 | 0U, // G_INDEXED_STORE |
| 1370 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 1371 | 0U, // G_ATOMIC_CMPXCHG |
| 1372 | 0U, // G_ATOMICRMW_XCHG |
| 1373 | 0U, // G_ATOMICRMW_ADD |
| 1374 | 0U, // G_ATOMICRMW_SUB |
| 1375 | 0U, // G_ATOMICRMW_AND |
| 1376 | 0U, // G_ATOMICRMW_NAND |
| 1377 | 0U, // G_ATOMICRMW_OR |
| 1378 | 0U, // G_ATOMICRMW_XOR |
| 1379 | 0U, // G_ATOMICRMW_MAX |
| 1380 | 0U, // G_ATOMICRMW_MIN |
| 1381 | 0U, // G_ATOMICRMW_UMAX |
| 1382 | 0U, // G_ATOMICRMW_UMIN |
| 1383 | 0U, // G_ATOMICRMW_FADD |
| 1384 | 0U, // G_ATOMICRMW_FSUB |
| 1385 | 0U, // G_ATOMICRMW_FMAX |
| 1386 | 0U, // G_ATOMICRMW_FMIN |
| 1387 | 0U, // G_ATOMICRMW_FMAXIMUM |
| 1388 | 0U, // G_ATOMICRMW_FMINIMUM |
| 1389 | 0U, // G_ATOMICRMW_UINC_WRAP |
| 1390 | 0U, // G_ATOMICRMW_UDEC_WRAP |
| 1391 | 0U, // G_ATOMICRMW_USUB_COND |
| 1392 | 0U, // G_ATOMICRMW_USUB_SAT |
| 1393 | 0U, // G_FENCE |
| 1394 | 0U, // G_PREFETCH |
| 1395 | 0U, // G_BRCOND |
| 1396 | 0U, // G_BRINDIRECT |
| 1397 | 0U, // G_INVOKE_REGION_START |
| 1398 | 0U, // G_INTRINSIC |
| 1399 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 1400 | 0U, // G_INTRINSIC_CONVERGENT |
| 1401 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 1402 | 0U, // G_ANYEXT |
| 1403 | 0U, // G_TRUNC |
| 1404 | 0U, // G_CONSTANT |
| 1405 | 0U, // G_FCONSTANT |
| 1406 | 0U, // G_VASTART |
| 1407 | 0U, // G_VAARG |
| 1408 | 0U, // G_SEXT |
| 1409 | 0U, // G_SEXT_INREG |
| 1410 | 0U, // G_ZEXT |
| 1411 | 0U, // G_SHL |
| 1412 | 0U, // G_LSHR |
| 1413 | 0U, // G_ASHR |
| 1414 | 0U, // G_FSHL |
| 1415 | 0U, // G_FSHR |
| 1416 | 0U, // G_ROTR |
| 1417 | 0U, // G_ROTL |
| 1418 | 0U, // G_ICMP |
| 1419 | 0U, // G_FCMP |
| 1420 | 0U, // G_SCMP |
| 1421 | 0U, // G_UCMP |
| 1422 | 0U, // G_SELECT |
| 1423 | 0U, // G_UADDO |
| 1424 | 0U, // G_UADDE |
| 1425 | 0U, // G_USUBO |
| 1426 | 0U, // G_USUBE |
| 1427 | 0U, // G_SADDO |
| 1428 | 0U, // G_SADDE |
| 1429 | 0U, // G_SSUBO |
| 1430 | 0U, // G_SSUBE |
| 1431 | 0U, // G_UMULO |
| 1432 | 0U, // G_SMULO |
| 1433 | 0U, // G_UMULH |
| 1434 | 0U, // G_SMULH |
| 1435 | 0U, // G_UADDSAT |
| 1436 | 0U, // G_SADDSAT |
| 1437 | 0U, // G_USUBSAT |
| 1438 | 0U, // G_SSUBSAT |
| 1439 | 0U, // G_USHLSAT |
| 1440 | 0U, // G_SSHLSAT |
| 1441 | 0U, // G_SMULFIX |
| 1442 | 0U, // G_UMULFIX |
| 1443 | 0U, // G_SMULFIXSAT |
| 1444 | 0U, // G_UMULFIXSAT |
| 1445 | 0U, // G_SDIVFIX |
| 1446 | 0U, // G_UDIVFIX |
| 1447 | 0U, // G_SDIVFIXSAT |
| 1448 | 0U, // G_UDIVFIXSAT |
| 1449 | 0U, // G_FADD |
| 1450 | 0U, // G_FSUB |
| 1451 | 0U, // G_FMUL |
| 1452 | 0U, // G_FMA |
| 1453 | 0U, // G_FMAD |
| 1454 | 0U, // G_FDIV |
| 1455 | 0U, // G_FREM |
| 1456 | 0U, // G_FPOW |
| 1457 | 0U, // G_FPOWI |
| 1458 | 0U, // G_FEXP |
| 1459 | 0U, // G_FEXP2 |
| 1460 | 0U, // G_FEXP10 |
| 1461 | 0U, // G_FLOG |
| 1462 | 0U, // G_FLOG2 |
| 1463 | 0U, // G_FLOG10 |
| 1464 | 0U, // G_FLDEXP |
| 1465 | 0U, // G_FFREXP |
| 1466 | 0U, // G_FNEG |
| 1467 | 0U, // G_FPEXT |
| 1468 | 0U, // G_FPTRUNC |
| 1469 | 0U, // G_FPTOSI |
| 1470 | 0U, // G_FPTOUI |
| 1471 | 0U, // G_SITOFP |
| 1472 | 0U, // G_UITOFP |
| 1473 | 0U, // G_FPTOSI_SAT |
| 1474 | 0U, // G_FPTOUI_SAT |
| 1475 | 0U, // G_FABS |
| 1476 | 0U, // G_FCOPYSIGN |
| 1477 | 0U, // G_IS_FPCLASS |
| 1478 | 0U, // G_FCANONICALIZE |
| 1479 | 0U, // G_FMINNUM |
| 1480 | 0U, // G_FMAXNUM |
| 1481 | 0U, // G_FMINNUM_IEEE |
| 1482 | 0U, // G_FMAXNUM_IEEE |
| 1483 | 0U, // G_FMINIMUM |
| 1484 | 0U, // G_FMAXIMUM |
| 1485 | 0U, // G_FMINIMUMNUM |
| 1486 | 0U, // G_FMAXIMUMNUM |
| 1487 | 0U, // G_GET_FPENV |
| 1488 | 0U, // G_SET_FPENV |
| 1489 | 0U, // G_RESET_FPENV |
| 1490 | 0U, // G_GET_FPMODE |
| 1491 | 0U, // G_SET_FPMODE |
| 1492 | 0U, // G_RESET_FPMODE |
| 1493 | 0U, // G_PTR_ADD |
| 1494 | 0U, // G_PTRMASK |
| 1495 | 0U, // G_SMIN |
| 1496 | 0U, // G_SMAX |
| 1497 | 0U, // G_UMIN |
| 1498 | 0U, // G_UMAX |
| 1499 | 0U, // G_ABS |
| 1500 | 0U, // G_LROUND |
| 1501 | 0U, // G_LLROUND |
| 1502 | 0U, // G_BR |
| 1503 | 0U, // G_BRJT |
| 1504 | 0U, // G_VSCALE |
| 1505 | 0U, // G_INSERT_SUBVECTOR |
| 1506 | 0U, // G_EXTRACT_SUBVECTOR |
| 1507 | 0U, // G_INSERT_VECTOR_ELT |
| 1508 | 0U, // G_EXTRACT_VECTOR_ELT |
| 1509 | 0U, // G_SHUFFLE_VECTOR |
| 1510 | 0U, // G_SPLAT_VECTOR |
| 1511 | 0U, // G_STEP_VECTOR |
| 1512 | 0U, // G_VECTOR_COMPRESS |
| 1513 | 0U, // G_CTTZ |
| 1514 | 0U, // G_CTTZ_ZERO_UNDEF |
| 1515 | 0U, // G_CTLZ |
| 1516 | 0U, // G_CTLZ_ZERO_UNDEF |
| 1517 | 0U, // G_CTPOP |
| 1518 | 0U, // G_BSWAP |
| 1519 | 0U, // G_BITREVERSE |
| 1520 | 0U, // G_FCEIL |
| 1521 | 0U, // G_FCOS |
| 1522 | 0U, // G_FSIN |
| 1523 | 0U, // G_FSINCOS |
| 1524 | 0U, // G_FTAN |
| 1525 | 0U, // G_FACOS |
| 1526 | 0U, // G_FASIN |
| 1527 | 0U, // G_FATAN |
| 1528 | 0U, // G_FATAN2 |
| 1529 | 0U, // G_FCOSH |
| 1530 | 0U, // G_FSINH |
| 1531 | 0U, // G_FTANH |
| 1532 | 0U, // G_FSQRT |
| 1533 | 0U, // G_FFLOOR |
| 1534 | 0U, // G_FRINT |
| 1535 | 0U, // G_FNEARBYINT |
| 1536 | 0U, // G_ADDRSPACE_CAST |
| 1537 | 0U, // G_BLOCK_ADDR |
| 1538 | 0U, // G_JUMP_TABLE |
| 1539 | 0U, // G_DYN_STACKALLOC |
| 1540 | 0U, // G_STACKSAVE |
| 1541 | 0U, // G_STACKRESTORE |
| 1542 | 0U, // G_STRICT_FADD |
| 1543 | 0U, // G_STRICT_FSUB |
| 1544 | 0U, // G_STRICT_FMUL |
| 1545 | 0U, // G_STRICT_FDIV |
| 1546 | 0U, // G_STRICT_FREM |
| 1547 | 0U, // G_STRICT_FMA |
| 1548 | 0U, // G_STRICT_FSQRT |
| 1549 | 0U, // G_STRICT_FLDEXP |
| 1550 | 0U, // G_READ_REGISTER |
| 1551 | 0U, // G_WRITE_REGISTER |
| 1552 | 0U, // G_MEMCPY |
| 1553 | 0U, // G_MEMCPY_INLINE |
| 1554 | 0U, // G_MEMMOVE |
| 1555 | 0U, // G_MEMSET |
| 1556 | 0U, // G_BZERO |
| 1557 | 0U, // G_TRAP |
| 1558 | 0U, // G_DEBUGTRAP |
| 1559 | 0U, // G_UBSANTRAP |
| 1560 | 0U, // G_VECREDUCE_SEQ_FADD |
| 1561 | 0U, // G_VECREDUCE_SEQ_FMUL |
| 1562 | 0U, // G_VECREDUCE_FADD |
| 1563 | 0U, // G_VECREDUCE_FMUL |
| 1564 | 0U, // G_VECREDUCE_FMAX |
| 1565 | 0U, // G_VECREDUCE_FMIN |
| 1566 | 0U, // G_VECREDUCE_FMAXIMUM |
| 1567 | 0U, // G_VECREDUCE_FMINIMUM |
| 1568 | 0U, // G_VECREDUCE_ADD |
| 1569 | 0U, // G_VECREDUCE_MUL |
| 1570 | 0U, // G_VECREDUCE_AND |
| 1571 | 0U, // G_VECREDUCE_OR |
| 1572 | 0U, // G_VECREDUCE_XOR |
| 1573 | 0U, // G_VECREDUCE_SMAX |
| 1574 | 0U, // G_VECREDUCE_SMIN |
| 1575 | 0U, // G_VECREDUCE_UMAX |
| 1576 | 0U, // G_VECREDUCE_UMIN |
| 1577 | 0U, // G_SBFX |
| 1578 | 0U, // G_UBFX |
| 1579 | 23974U, // ABSMacro |
| 1580 | 0U, // ADJCALLSTACKDOWN |
| 1581 | 0U, // ADJCALLSTACKUP |
| 1582 | 0U, // AND_V_D_PSEUDO |
| 1583 | 0U, // AND_V_H_PSEUDO |
| 1584 | 0U, // AND_V_W_PSEUDO |
| 1585 | 0U, // ATOMIC_CMP_SWAP_I16 |
| 1586 | 0U, // ATOMIC_CMP_SWAP_I16_POSTRA |
| 1587 | 0U, // ATOMIC_CMP_SWAP_I32 |
| 1588 | 0U, // ATOMIC_CMP_SWAP_I32_POSTRA |
| 1589 | 0U, // ATOMIC_CMP_SWAP_I64 |
| 1590 | 0U, // ATOMIC_CMP_SWAP_I64_POSTRA |
| 1591 | 0U, // ATOMIC_CMP_SWAP_I8 |
| 1592 | 0U, // ATOMIC_CMP_SWAP_I8_POSTRA |
| 1593 | 0U, // ATOMIC_LOAD_ADD_I16 |
| 1594 | 0U, // ATOMIC_LOAD_ADD_I16_POSTRA |
| 1595 | 0U, // ATOMIC_LOAD_ADD_I32 |
| 1596 | 0U, // ATOMIC_LOAD_ADD_I32_POSTRA |
| 1597 | 0U, // ATOMIC_LOAD_ADD_I64 |
| 1598 | 0U, // ATOMIC_LOAD_ADD_I64_POSTRA |
| 1599 | 0U, // ATOMIC_LOAD_ADD_I8 |
| 1600 | 0U, // ATOMIC_LOAD_ADD_I8_POSTRA |
| 1601 | 0U, // ATOMIC_LOAD_AND_I16 |
| 1602 | 0U, // ATOMIC_LOAD_AND_I16_POSTRA |
| 1603 | 0U, // ATOMIC_LOAD_AND_I32 |
| 1604 | 0U, // ATOMIC_LOAD_AND_I32_POSTRA |
| 1605 | 0U, // ATOMIC_LOAD_AND_I64 |
| 1606 | 0U, // ATOMIC_LOAD_AND_I64_POSTRA |
| 1607 | 0U, // ATOMIC_LOAD_AND_I8 |
| 1608 | 0U, // ATOMIC_LOAD_AND_I8_POSTRA |
| 1609 | 0U, // ATOMIC_LOAD_MAX_I16 |
| 1610 | 0U, // ATOMIC_LOAD_MAX_I16_POSTRA |
| 1611 | 0U, // ATOMIC_LOAD_MAX_I32 |
| 1612 | 0U, // ATOMIC_LOAD_MAX_I32_POSTRA |
| 1613 | 0U, // ATOMIC_LOAD_MAX_I64 |
| 1614 | 0U, // ATOMIC_LOAD_MAX_I64_POSTRA |
| 1615 | 0U, // ATOMIC_LOAD_MAX_I8 |
| 1616 | 0U, // ATOMIC_LOAD_MAX_I8_POSTRA |
| 1617 | 0U, // ATOMIC_LOAD_MIN_I16 |
| 1618 | 0U, // ATOMIC_LOAD_MIN_I16_POSTRA |
| 1619 | 0U, // ATOMIC_LOAD_MIN_I32 |
| 1620 | 0U, // ATOMIC_LOAD_MIN_I32_POSTRA |
| 1621 | 0U, // ATOMIC_LOAD_MIN_I64 |
| 1622 | 0U, // ATOMIC_LOAD_MIN_I64_POSTRA |
| 1623 | 0U, // ATOMIC_LOAD_MIN_I8 |
| 1624 | 0U, // ATOMIC_LOAD_MIN_I8_POSTRA |
| 1625 | 0U, // ATOMIC_LOAD_NAND_I16 |
| 1626 | 0U, // ATOMIC_LOAD_NAND_I16_POSTRA |
| 1627 | 0U, // ATOMIC_LOAD_NAND_I32 |
| 1628 | 0U, // ATOMIC_LOAD_NAND_I32_POSTRA |
| 1629 | 0U, // ATOMIC_LOAD_NAND_I64 |
| 1630 | 0U, // ATOMIC_LOAD_NAND_I64_POSTRA |
| 1631 | 0U, // ATOMIC_LOAD_NAND_I8 |
| 1632 | 0U, // ATOMIC_LOAD_NAND_I8_POSTRA |
| 1633 | 0U, // ATOMIC_LOAD_OR_I16 |
| 1634 | 0U, // ATOMIC_LOAD_OR_I16_POSTRA |
| 1635 | 0U, // ATOMIC_LOAD_OR_I32 |
| 1636 | 0U, // ATOMIC_LOAD_OR_I32_POSTRA |
| 1637 | 0U, // ATOMIC_LOAD_OR_I64 |
| 1638 | 0U, // ATOMIC_LOAD_OR_I64_POSTRA |
| 1639 | 0U, // ATOMIC_LOAD_OR_I8 |
| 1640 | 0U, // ATOMIC_LOAD_OR_I8_POSTRA |
| 1641 | 0U, // ATOMIC_LOAD_SUB_I16 |
| 1642 | 0U, // ATOMIC_LOAD_SUB_I16_POSTRA |
| 1643 | 0U, // ATOMIC_LOAD_SUB_I32 |
| 1644 | 0U, // ATOMIC_LOAD_SUB_I32_POSTRA |
| 1645 | 0U, // ATOMIC_LOAD_SUB_I64 |
| 1646 | 0U, // ATOMIC_LOAD_SUB_I64_POSTRA |
| 1647 | 0U, // ATOMIC_LOAD_SUB_I8 |
| 1648 | 0U, // ATOMIC_LOAD_SUB_I8_POSTRA |
| 1649 | 0U, // ATOMIC_LOAD_UMAX_I16 |
| 1650 | 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA |
| 1651 | 0U, // ATOMIC_LOAD_UMAX_I32 |
| 1652 | 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA |
| 1653 | 0U, // ATOMIC_LOAD_UMAX_I64 |
| 1654 | 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA |
| 1655 | 0U, // ATOMIC_LOAD_UMAX_I8 |
| 1656 | 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA |
| 1657 | 0U, // ATOMIC_LOAD_UMIN_I16 |
| 1658 | 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA |
| 1659 | 0U, // ATOMIC_LOAD_UMIN_I32 |
| 1660 | 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA |
| 1661 | 0U, // ATOMIC_LOAD_UMIN_I64 |
| 1662 | 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA |
| 1663 | 0U, // ATOMIC_LOAD_UMIN_I8 |
| 1664 | 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA |
| 1665 | 0U, // ATOMIC_LOAD_XOR_I16 |
| 1666 | 0U, // ATOMIC_LOAD_XOR_I16_POSTRA |
| 1667 | 0U, // ATOMIC_LOAD_XOR_I32 |
| 1668 | 0U, // ATOMIC_LOAD_XOR_I32_POSTRA |
| 1669 | 0U, // ATOMIC_LOAD_XOR_I64 |
| 1670 | 0U, // ATOMIC_LOAD_XOR_I64_POSTRA |
| 1671 | 0U, // ATOMIC_LOAD_XOR_I8 |
| 1672 | 0U, // ATOMIC_LOAD_XOR_I8_POSTRA |
| 1673 | 0U, // ATOMIC_SWAP_I16 |
| 1674 | 0U, // ATOMIC_SWAP_I16_POSTRA |
| 1675 | 0U, // ATOMIC_SWAP_I32 |
| 1676 | 0U, // ATOMIC_SWAP_I32_POSTRA |
| 1677 | 0U, // ATOMIC_SWAP_I64 |
| 1678 | 0U, // ATOMIC_SWAP_I64_POSTRA |
| 1679 | 0U, // ATOMIC_SWAP_I8 |
| 1680 | 0U, // ATOMIC_SWAP_I8_POSTRA |
| 1681 | 0U, // B |
| 1682 | 0U, // BAL_BR |
| 1683 | 0U, // BAL_BR_MM |
| 1684 | 536893669U, // BEQLImmMacro |
| 1685 | 536891521U, // BGE |
| 1686 | 536891521U, // BGEImmMacro |
| 1687 | 536893530U, // BGEL |
| 1688 | 536893530U, // BGELImmMacro |
| 1689 | 536895156U, // BGEU |
| 1690 | 536895156U, // BGEUImmMacro |
| 1691 | 536893700U, // BGEUL |
| 1692 | 536893700U, // BGEULImmMacro |
| 1693 | 536895037U, // BGT |
| 1694 | 536895037U, // BGTImmMacro |
| 1695 | 536893688U, // BGTL |
| 1696 | 536893688U, // BGTLImmMacro |
| 1697 | 536895282U, // BGTU |
| 1698 | 536895282U, // BGTUImmMacro |
| 1699 | 536893720U, // BGTUL |
| 1700 | 536893720U, // BGTULImmMacro |
| 1701 | 536891561U, // BLE |
| 1702 | 536891561U, // BLEImmMacro |
| 1703 | 536893536U, // BLEL |
| 1704 | 536893536U, // BLELImmMacro |
| 1705 | 536895174U, // BLEU |
| 1706 | 536895174U, // BLEUImmMacro |
| 1707 | 536893707U, // BLEUL |
| 1708 | 536893707U, // BLEULImmMacro |
| 1709 | 536895053U, // BLT |
| 1710 | 536895053U, // BLTImmMacro |
| 1711 | 536893694U, // BLTL |
| 1712 | 536893694U, // BLTLImmMacro |
| 1713 | 536895294U, // BLTU |
| 1714 | 536895294U, // BLTUImmMacro |
| 1715 | 536893727U, // BLTUL |
| 1716 | 536893727U, // BLTULImmMacro |
| 1717 | 536893542U, // BNELImmMacro |
| 1718 | 0U, // BPOSGE32_PSEUDO |
| 1719 | 0U, // BSEL_D_PSEUDO |
| 1720 | 0U, // BSEL_FD_PSEUDO |
| 1721 | 0U, // BSEL_FW_PSEUDO |
| 1722 | 0U, // BSEL_H_PSEUDO |
| 1723 | 0U, // BSEL_W_PSEUDO |
| 1724 | 0U, // B_MM |
| 1725 | 557807U, // B_MMR6_Pseudo |
| 1726 | 557807U, // B_MM_Pseudo |
| 1727 | 536894020U, // BeqImm |
| 1728 | 536891588U, // BneImm |
| 1729 | 1073764808U, // BteqzT8CmpX16 |
| 1730 | 1073764241U, // BteqzT8CmpiX16 |
| 1731 | 1073765970U, // BteqzT8SltX16 |
| 1732 | 1073764271U, // BteqzT8SltiX16 |
| 1733 | 1073766126U, // BteqzT8SltiuX16 |
| 1734 | 1073766212U, // BteqzT8SltuX16 |
| 1735 | 1610635720U, // BtnezT8CmpX16 |
| 1736 | 1610635153U, // BtnezT8CmpiX16 |
| 1737 | 1610636882U, // BtnezT8SltX16 |
| 1738 | 1610635183U, // BtnezT8SltiX16 |
| 1739 | 1610637038U, // BtnezT8SltiuX16 |
| 1740 | 1610637124U, // BtnezT8SltuX16 |
| 1741 | 0U, // BuildPairF64 |
| 1742 | 0U, // BuildPairF64_64 |
| 1743 | 26462U, // CFTC1 |
| 1744 | 10605U, // CONSTPOOL_ENTRY |
| 1745 | 0U, // COPY_FD_PSEUDO |
| 1746 | 0U, // COPY_FW_PSEUDO |
| 1747 | 17885036U, // CTTC1 |
| 1748 | 550788U, // Constant32 |
| 1749 | 536893714U, // DMULImmMacro |
| 1750 | 536893714U, // DMULMacro |
| 1751 | 536893849U, // DMULOMacro |
| 1752 | 536895257U, // DMULOUMacro |
| 1753 | 536893653U, // DROL |
| 1754 | 536893653U, // DROLImm |
| 1755 | 536894187U, // DROR |
| 1756 | 536894187U, // DRORImm |
| 1757 | 536895419U, // DSDivIMacro |
| 1758 | 536895419U, // DSDivMacro |
| 1759 | 536893772U, // DSRemIMacro |
| 1760 | 536893772U, // DSRemMacro |
| 1761 | 536895327U, // DUDivIMacro |
| 1762 | 536895327U, // DUDivMacro |
| 1763 | 536895250U, // DURemIMacro |
| 1764 | 536895250U, // DURemMacro |
| 1765 | 0U, // ERet |
| 1766 | 0U, // ExtractElementF64 |
| 1767 | 0U, // ExtractElementF64_64 |
| 1768 | 0U, // FABS_D |
| 1769 | 0U, // FABS_W |
| 1770 | 0U, // FEXP2_D_1_PSEUDO |
| 1771 | 0U, // FEXP2_W_1_PSEUDO |
| 1772 | 0U, // FILL_FD_PSEUDO |
| 1773 | 0U, // FILL_FW_PSEUDO |
| 1774 | 2181060488U, // GotPrologue16 |
| 1775 | 0U, // INSERT_B_VIDX64_PSEUDO |
| 1776 | 0U, // INSERT_B_VIDX_PSEUDO |
| 1777 | 0U, // INSERT_D_VIDX64_PSEUDO |
| 1778 | 0U, // INSERT_D_VIDX_PSEUDO |
| 1779 | 0U, // INSERT_FD_PSEUDO |
| 1780 | 0U, // INSERT_FD_VIDX64_PSEUDO |
| 1781 | 0U, // INSERT_FD_VIDX_PSEUDO |
| 1782 | 0U, // INSERT_FW_PSEUDO |
| 1783 | 0U, // INSERT_FW_VIDX64_PSEUDO |
| 1784 | 0U, // INSERT_FW_VIDX_PSEUDO |
| 1785 | 0U, // INSERT_H_VIDX64_PSEUDO |
| 1786 | 0U, // INSERT_H_VIDX_PSEUDO |
| 1787 | 0U, // INSERT_W_VIDX64_PSEUDO |
| 1788 | 0U, // INSERT_W_VIDX_PSEUDO |
| 1789 | 0U, // JALR64Pseudo |
| 1790 | 0U, // JALRHB64Pseudo |
| 1791 | 0U, // JALRHBPseudo |
| 1792 | 0U, // JALRPseudo |
| 1793 | 0U, // JAL_MMR6 |
| 1794 | 546804U, // JalOneReg |
| 1795 | 22516U, // JalTwoReg |
| 1796 | 50358144U, // LDMacro |
| 1797 | 0U, // LDR_D |
| 1798 | 0U, // LDR_W |
| 1799 | 0U, // LD_F16 |
| 1800 | 50348038U, // LOAD_ACC128 |
| 1801 | 50348038U, // LOAD_ACC64 |
| 1802 | 50348038U, // LOAD_ACC64DSP |
| 1803 | 50354654U, // LOAD_CCOND_DSP |
| 1804 | 0U, // LONG_BRANCH_ADDiu |
| 1805 | 0U, // LONG_BRANCH_ADDiu2Op |
| 1806 | 0U, // LONG_BRANCH_DADDiu |
| 1807 | 0U, // LONG_BRANCH_DADDiu2Op |
| 1808 | 0U, // LONG_BRANCH_LUi |
| 1809 | 0U, // LONG_BRANCH_LUi2Op |
| 1810 | 0U, // LONG_BRANCH_LUi2Op_64 |
| 1811 | 72032U, // LWM_MM |
| 1812 | 17042U, // LoadAddrImm32 |
| 1813 | 17063U, // LoadAddrImm64 |
| 1814 | 50348690U, // LoadAddrReg32 |
| 1815 | 50348711U, // LoadAddrReg64 |
| 1816 | 22408U, // LoadImm32 |
| 1817 | 22412U, // LoadImm64 |
| 1818 | 19107U, // LoadImmDoubleFGR |
| 1819 | 19107U, // LoadImmDoubleFGR_32 |
| 1820 | 19107U, // LoadImmDoubleGPR |
| 1821 | 23539U, // LoadImmSingleFGR |
| 1822 | 23539U, // LoadImmSingleGPR |
| 1823 | 1599118U, // LwConstant32 |
| 1824 | 26588U, // MFTACX |
| 1825 | 536897344U, // MFTC0 |
| 1826 | 26469U, // MFTC1 |
| 1827 | 550833U, // MFTDSP |
| 1828 | 26566U, // MFTGPR |
| 1829 | 26446U, // MFTHC1 |
| 1830 | 26517U, // MFTHI |
| 1831 | 26531U, // MFTLO |
| 1832 | 0U, // MIPSeh_return32 |
| 1833 | 0U, // MIPSeh_return64 |
| 1834 | 0U, // MSA_FP_EXTEND_D_PSEUDO |
| 1835 | 0U, // MSA_FP_EXTEND_W_PSEUDO |
| 1836 | 0U, // MSA_FP_ROUND_D_PSEUDO |
| 1837 | 0U, // MSA_FP_ROUND_W_PSEUDO |
| 1838 | 17885156U, // MTTACX |
| 1839 | 2752571207U, // MTTC0 |
| 1840 | 17885043U, // MTTC1 |
| 1841 | 550841U, // MTTDSP |
| 1842 | 17885134U, // MTTGPR |
| 1843 | 17885014U, // MTTHC1 |
| 1844 | 17885084U, // MTTHI |
| 1845 | 17885098U, // MTTLO |
| 1846 | 536893715U, // MULImmMacro |
| 1847 | 536893850U, // MULOMacro |
| 1848 | 536895258U, // MULOUMacro |
| 1849 | 24157U, // MultRxRy16 |
| 1850 | 86040157U, // MultRxRyRz16 |
| 1851 | 24401U, // MultuRxRy16 |
| 1852 | 86040401U, // MultuRxRyRz16 |
| 1853 | 0U, // NOP |
| 1854 | 536894182U, // NORImm |
| 1855 | 536894182U, // NORImm64 |
| 1856 | 0U, // NOR_V_D_PSEUDO |
| 1857 | 0U, // NOR_V_H_PSEUDO |
| 1858 | 0U, // NOR_V_W_PSEUDO |
| 1859 | 0U, // OR_V_D_PSEUDO |
| 1860 | 0U, // OR_V_H_PSEUDO |
| 1861 | 0U, // OR_V_W_PSEUDO |
| 1862 | 0U, // PseudoCMPU_EQ_QB |
| 1863 | 0U, // PseudoCMPU_LE_QB |
| 1864 | 0U, // PseudoCMPU_LT_QB |
| 1865 | 0U, // PseudoCMP_EQ_PH |
| 1866 | 0U, // PseudoCMP_LE_PH |
| 1867 | 0U, // PseudoCMP_LT_PH |
| 1868 | 16390U, // PseudoCVT_D32_W |
| 1869 | 16390U, // PseudoCVT_D64_L |
| 1870 | 16390U, // PseudoCVT_D64_W |
| 1871 | 16390U, // PseudoCVT_S_L |
| 1872 | 16390U, // PseudoCVT_S_W |
| 1873 | 0U, // PseudoDMULT |
| 1874 | 0U, // PseudoDMULTu |
| 1875 | 0U, // PseudoDSDIV |
| 1876 | 0U, // PseudoDUDIV |
| 1877 | 0U, // PseudoD_SELECT_I |
| 1878 | 0U, // PseudoD_SELECT_I64 |
| 1879 | 0U, // PseudoIndirectBranch |
| 1880 | 0U, // PseudoIndirectBranch64 |
| 1881 | 0U, // PseudoIndirectBranch64R6 |
| 1882 | 0U, // PseudoIndirectBranchR6 |
| 1883 | 0U, // PseudoIndirectBranch_MM |
| 1884 | 0U, // PseudoIndirectBranch_MMR6 |
| 1885 | 0U, // PseudoIndirectHazardBranch |
| 1886 | 0U, // PseudoIndirectHazardBranch64 |
| 1887 | 0U, // PseudoIndrectHazardBranch64R6 |
| 1888 | 0U, // PseudoIndrectHazardBranchR6 |
| 1889 | 0U, // PseudoMADD |
| 1890 | 0U, // PseudoMADDU |
| 1891 | 0U, // PseudoMADDU_MM |
| 1892 | 0U, // PseudoMADD_MM |
| 1893 | 0U, // PseudoMFHI |
| 1894 | 0U, // PseudoMFHI64 |
| 1895 | 0U, // PseudoMFHI_MM |
| 1896 | 0U, // PseudoMFLO |
| 1897 | 0U, // PseudoMFLO64 |
| 1898 | 0U, // PseudoMFLO_MM |
| 1899 | 0U, // PseudoMSUB |
| 1900 | 0U, // PseudoMSUBU |
| 1901 | 0U, // PseudoMSUBU_MM |
| 1902 | 0U, // PseudoMSUB_MM |
| 1903 | 0U, // PseudoMTLOHI |
| 1904 | 0U, // PseudoMTLOHI64 |
| 1905 | 0U, // PseudoMTLOHI_DSP |
| 1906 | 0U, // PseudoMTLOHI_MM |
| 1907 | 0U, // PseudoMULT |
| 1908 | 0U, // PseudoMULT_MM |
| 1909 | 0U, // PseudoMULTu |
| 1910 | 0U, // PseudoMULTu_MM |
| 1911 | 0U, // PseudoPICK_PH |
| 1912 | 0U, // PseudoPICK_QB |
| 1913 | 0U, // PseudoReturn |
| 1914 | 0U, // PseudoReturn64 |
| 1915 | 0U, // PseudoSDIV |
| 1916 | 0U, // PseudoSELECTFP_F_D32 |
| 1917 | 0U, // PseudoSELECTFP_F_D64 |
| 1918 | 0U, // PseudoSELECTFP_F_I |
| 1919 | 0U, // PseudoSELECTFP_F_I64 |
| 1920 | 0U, // PseudoSELECTFP_F_S |
| 1921 | 0U, // PseudoSELECTFP_T_D32 |
| 1922 | 0U, // PseudoSELECTFP_T_D64 |
| 1923 | 0U, // PseudoSELECTFP_T_I |
| 1924 | 0U, // PseudoSELECTFP_T_I64 |
| 1925 | 0U, // PseudoSELECTFP_T_S |
| 1926 | 0U, // PseudoSELECT_D32 |
| 1927 | 0U, // PseudoSELECT_D64 |
| 1928 | 0U, // PseudoSELECT_I |
| 1929 | 0U, // PseudoSELECT_I64 |
| 1930 | 0U, // PseudoSELECT_S |
| 1931 | 536891300U, // PseudoTRUNC_W_D |
| 1932 | 536891300U, // PseudoTRUNC_W_D32 |
| 1933 | 536894799U, // PseudoTRUNC_W_S |
| 1934 | 0U, // PseudoUDIV |
| 1935 | 536893654U, // ROL |
| 1936 | 536893654U, // ROLImm |
| 1937 | 536894188U, // ROR |
| 1938 | 536894188U, // RORImm |
| 1939 | 0U, // RetRA |
| 1940 | 0U, // RetRA16 |
| 1941 | 50351255U, // SDC1_M1 |
| 1942 | 0U, // SDIV_MM_Pseudo |
| 1943 | 50358156U, // SDMacro |
| 1944 | 536895420U, // SDivIMacro |
| 1945 | 536895420U, // SDivMacro |
| 1946 | 536897473U, // SEQIMacro |
| 1947 | 536897473U, // SEQMacro |
| 1948 | 536891526U, // SGE |
| 1949 | 536891526U, // SGEImm |
| 1950 | 536891526U, // SGEImm64 |
| 1951 | 536895162U, // SGEU |
| 1952 | 536895162U, // SGEUImm |
| 1953 | 536895162U, // SGEUImm64 |
| 1954 | 536895042U, // SGTImm |
| 1955 | 536895042U, // SGTImm64 |
| 1956 | 536895288U, // SGTUImm |
| 1957 | 536895288U, // SGTUImm64 |
| 1958 | 536891571U, // SLE |
| 1959 | 536891571U, // SLEImm |
| 1960 | 536891571U, // SLEImm64 |
| 1961 | 536895180U, // SLEU |
| 1962 | 536895180U, // SLEUImm |
| 1963 | 536895180U, // SLEUImm64 |
| 1964 | 536895058U, // SLTImm64 |
| 1965 | 536895300U, // SLTUImm64 |
| 1966 | 536897424U, // SNEIMacro |
| 1967 | 536897424U, // SNEMacro |
| 1968 | 0U, // SNZ_B_PSEUDO |
| 1969 | 0U, // SNZ_D_PSEUDO |
| 1970 | 0U, // SNZ_H_PSEUDO |
| 1971 | 0U, // SNZ_V_PSEUDO |
| 1972 | 0U, // SNZ_W_PSEUDO |
| 1973 | 536893773U, // SRemIMacro |
| 1974 | 536893773U, // SRemMacro |
| 1975 | 50348038U, // STORE_ACC128 |
| 1976 | 50348038U, // STORE_ACC64 |
| 1977 | 50348038U, // STORE_ACC64DSP |
| 1978 | 50354670U, // STORE_CCOND_DSP |
| 1979 | 0U, // STR_D |
| 1980 | 0U, // STR_W |
| 1981 | 0U, // ST_F16 |
| 1982 | 72037U, // SWM_MM |
| 1983 | 0U, // SZ_B_PSEUDO |
| 1984 | 0U, // SZ_D_PSEUDO |
| 1985 | 0U, // SZ_H_PSEUDO |
| 1986 | 0U, // SZ_V_PSEUDO |
| 1987 | 0U, // SZ_W_PSEUDO |
| 1988 | 50348673U, // SaaAddr |
| 1989 | 50352145U, // SaadAddr |
| 1990 | 2713318U, // SelBeqZ |
| 1991 | 2713291U, // SelBneZ |
| 1992 | 3321977288U, // SelTBteqZCmp |
| 1993 | 3321976721U, // SelTBteqZCmpi |
| 1994 | 3321978450U, // SelTBteqZSlt |
| 1995 | 3321976751U, // SelTBteqZSlti |
| 1996 | 3321978606U, // SelTBteqZSltiu |
| 1997 | 3321978692U, // SelTBteqZSltu |
| 1998 | 3858848200U, // SelTBtneZCmp |
| 1999 | 3858847633U, // SelTBtneZCmpi |
| 2000 | 3858849362U, // SelTBtneZSlt |
| 2001 | 3858847663U, // SelTBtneZSlti |
| 2002 | 3858849518U, // SelTBtneZSltiu |
| 2003 | 3858849604U, // SelTBtneZSltu |
| 2004 | 119594578U, // SltCCRxRy16 |
| 2005 | 119592879U, // SltiCCRxImmX16 |
| 2006 | 119594734U, // SltiuCCRxImmX16 |
| 2007 | 119594820U, // SltuCCRxRy16 |
| 2008 | 119594820U, // SltuRxRyRz16 |
| 2009 | 0U, // TAILCALL |
| 2010 | 0U, // TAILCALL64R6REG |
| 2011 | 0U, // TAILCALLHB64R6REG |
| 2012 | 0U, // TAILCALLHBR6REG |
| 2013 | 0U, // TAILCALLR6REG |
| 2014 | 0U, // TAILCALLREG |
| 2015 | 0U, // TAILCALLREG64 |
| 2016 | 0U, // TAILCALLREGHB |
| 2017 | 0U, // TAILCALLREGHB64 |
| 2018 | 0U, // TAILCALLREG_MM |
| 2019 | 0U, // TAILCALLREG_MMR6 |
| 2020 | 0U, // TAILCALL_MM |
| 2021 | 0U, // TAILCALL_MMR6 |
| 2022 | 0U, // TRAP |
| 2023 | 0U, // TRAP_MM |
| 2024 | 0U, // UDIV_MM_Pseudo |
| 2025 | 536895328U, // UDivIMacro |
| 2026 | 536895328U, // UDivMacro |
| 2027 | 536895251U, // URemIMacro |
| 2028 | 536895251U, // URemMacro |
| 2029 | 50353426U, // Ulh |
| 2030 | 50355922U, // Ulhu |
| 2031 | 50357901U, // Ulw |
| 2032 | 50353979U, // Ush |
| 2033 | 50357917U, // Usw |
| 2034 | 0U, // XOR_V_D_PSEUDO |
| 2035 | 0U, // XOR_V_H_PSEUDO |
| 2036 | 0U, // XOR_V_W_PSEUDO |
| 2037 | 22052U, // ABSQ_S_PH |
| 2038 | 22052U, // ABSQ_S_PH_MM |
| 2039 | 18197U, // ABSQ_S_QB |
| 2040 | 18197U, // ABSQ_S_QB_MMR2 |
| 2041 | 25616U, // ABSQ_S_W |
| 2042 | 25616U, // ABSQ_S_W_MM |
| 2043 | 536891430U, // ADD |
| 2044 | 18483U, // ADDIUPC |
| 2045 | 18483U, // ADDIUPC_MM |
| 2046 | 18483U, // ADDIUPC_MMR6 |
| 2047 | 22995U, // ADDIUR1SP_MM |
| 2048 | 536887674U, // ADDIUR2_MM |
| 2049 | 18923931U, // ADDIUS5_MM |
| 2050 | 547344U, // ADDIUSP_MM |
| 2051 | 536895200U, // ADDIU_MMR6 |
| 2052 | 536892769U, // ADDQH_PH |
| 2053 | 536892769U, // ADDQH_PH_MMR2 |
| 2054 | 536892886U, // ADDQH_R_PH |
| 2055 | 536892886U, // ADDQH_R_PH_MMR2 |
| 2056 | 536896203U, // ADDQH_R_W |
| 2057 | 536896203U, // ADDQH_R_W_MMR2 |
| 2058 | 536895806U, // ADDQH_W |
| 2059 | 536895806U, // ADDQH_W_MMR2 |
| 2060 | 536892843U, // ADDQ_PH |
| 2061 | 536892843U, // ADDQ_PH_MM |
| 2062 | 536892942U, // ADDQ_S_PH |
| 2063 | 536892942U, // ADDQ_S_PH_MM |
| 2064 | 536896508U, // ADDQ_S_W |
| 2065 | 536896508U, // ADDQ_S_W_MM |
| 2066 | 536894967U, // ADDR_PS64 |
| 2067 | 536889435U, // ADDSC |
| 2068 | 536889435U, // ADDSC_MM |
| 2069 | 536888059U, // ADDS_A_B |
| 2070 | 536889596U, // ADDS_A_D |
| 2071 | 536891696U, // ADDS_A_H |
| 2072 | 536895514U, // ADDS_A_W |
| 2073 | 536888527U, // ADDS_S_B |
| 2074 | 536890694U, // ADDS_S_D |
| 2075 | 536892253U, // ADDS_S_H |
| 2076 | 536896558U, // ADDS_S_W |
| 2077 | 536888742U, // ADDS_U_B |
| 2078 | 536891161U, // ADDS_U_D |
| 2079 | 536892531U, // ADDS_U_H |
| 2080 | 536896976U, // ADDS_U_W |
| 2081 | 536887894U, // ADDU16_MM |
| 2082 | 536887894U, // ADDU16_MMR6 |
| 2083 | 536888977U, // ADDUH_QB |
| 2084 | 536888977U, // ADDUH_QB_MMR2 |
| 2085 | 536889085U, // ADDUH_R_QB |
| 2086 | 536889085U, // ADDUH_R_QB_MMR2 |
| 2087 | 536895129U, // ADDU_MMR6 |
| 2088 | 536893041U, // ADDU_PH |
| 2089 | 536893041U, // ADDU_PH_MMR2 |
| 2090 | 536889190U, // ADDU_QB |
| 2091 | 536889190U, // ADDU_QB_MM |
| 2092 | 536892986U, // ADDU_S_PH |
| 2093 | 536892986U, // ADDU_S_PH_MMR2 |
| 2094 | 536889131U, // ADDU_S_QB |
| 2095 | 536889131U, // ADDU_S_QB_MM |
| 2096 | 536888308U, // ADDVI_B |
| 2097 | 536890116U, // ADDVI_D |
| 2098 | 536891912U, // ADDVI_H |
| 2099 | 536895939U, // ADDVI_W |
| 2100 | 536888820U, // ADDV_B |
| 2101 | 536891251U, // ADDV_D |
| 2102 | 536892609U, // ADDV_H |
| 2103 | 536897076U, // ADDV_W |
| 2104 | 536889474U, // ADDWC |
| 2105 | 536889474U, // ADDWC_MM |
| 2106 | 536888041U, // ADD_A_B |
| 2107 | 536889577U, // ADD_A_D |
| 2108 | 536891678U, // ADD_A_H |
| 2109 | 536895495U, // ADD_A_W |
| 2110 | 536891430U, // ADD_MM |
| 2111 | 536891430U, // ADD_MMR6 |
| 2112 | 536893262U, // ADDi |
| 2113 | 536893262U, // ADDi_MM |
| 2114 | 536895200U, // ADDiu |
| 2115 | 536895200U, // ADDiu_MM |
| 2116 | 536895129U, // ADDu |
| 2117 | 536895129U, // ADDu_MM |
| 2118 | 536893803U, // ALIGN |
| 2119 | 536893803U, // ALIGN_MMR6 |
| 2120 | 18475U, // ALUIPC |
| 2121 | 18475U, // ALUIPC_MMR6 |
| 2122 | 536891459U, // AND |
| 2123 | 20021705U, // AND16_MM |
| 2124 | 20021705U, // AND16_MMR6 |
| 2125 | 536891459U, // AND64 |
| 2126 | 536887774U, // ANDI16_MM |
| 2127 | 536887774U, // ANDI16_MMR6 |
| 2128 | 536888167U, // ANDI_B |
| 2129 | 536893268U, // ANDI_MMR6 |
| 2130 | 536891459U, // AND_MM |
| 2131 | 536891459U, // AND_MMR6 |
| 2132 | 536895339U, // AND_V |
| 2133 | 536893268U, // ANDi |
| 2134 | 536893268U, // ANDi64 |
| 2135 | 536893268U, // ANDi_MM |
| 2136 | 536891473U, // APPEND |
| 2137 | 536891473U, // APPEND_MMR2 |
| 2138 | 536888421U, // ASUB_S_B |
| 2139 | 536890524U, // ASUB_S_D |
| 2140 | 536892085U, // ASUB_S_H |
| 2141 | 536896338U, // ASUB_S_W |
| 2142 | 536888636U, // ASUB_U_B |
| 2143 | 536890991U, // ASUB_U_D |
| 2144 | 536892373U, // ASUB_U_H |
| 2145 | 536896806U, // ASUB_U_W |
| 2146 | 536893372U, // AUI |
| 2147 | 18468U, // AUIPC |
| 2148 | 18468U, // AUIPC_MMR6 |
| 2149 | 536893372U, // AUI_MMR6 |
| 2150 | 536888507U, // AVER_S_B |
| 2151 | 536890674U, // AVER_S_D |
| 2152 | 536892223U, // AVER_S_H |
| 2153 | 536896538U, // AVER_S_W |
| 2154 | 536888722U, // AVER_U_B |
| 2155 | 536891141U, // AVER_U_D |
| 2156 | 536892511U, // AVER_U_H |
| 2157 | 536896956U, // AVER_U_W |
| 2158 | 536888449U, // AVE_S_B |
| 2159 | 536890606U, // AVE_S_D |
| 2160 | 536892155U, // AVE_S_H |
| 2161 | 536896420U, // AVE_S_W |
| 2162 | 536888664U, // AVE_U_B |
| 2163 | 536891073U, // AVE_U_D |
| 2164 | 536892443U, // AVE_U_H |
| 2165 | 536896888U, // AVE_U_W |
| 2166 | 24288U, // AddiuRxImmX16 |
| 2167 | 3694304U, // AddiuRxPcImmX16 |
| 2168 | 33578720U, // AddiuRxRxImm16 |
| 2169 | 33578720U, // AddiuRxRxImmX16 |
| 2170 | 134242016U, // AddiuRxRyOffMemX16 |
| 2171 | 4220724U, // AddiuSpImm16 |
| 2172 | 550708U, // AddiuSpImmX16 |
| 2173 | 536895129U, // AdduRxRyRz16 |
| 2174 | 33574979U, // AndRxRxRy16 |
| 2175 | 557477U, // B16_MM |
| 2176 | 536895128U, // BADDu |
| 2177 | 563183U, // BAL |
| 2178 | 559061U, // BALC |
| 2179 | 559061U, // BALC_MMR6 |
| 2180 | 536893802U, // BALIGN |
| 2181 | 536893802U, // BALIGN_MMR2 |
| 2182 | 151011407U, // BBIT0 |
| 2183 | 151011539U, // BBIT032 |
| 2184 | 151011532U, // BBIT1 |
| 2185 | 151011548U, // BBIT132 |
| 2186 | 559040U, // BC |
| 2187 | 557482U, // BC16_MMR6 |
| 2188 | 167798780U, // BC1EQZ |
| 2189 | 167790768U, // BC1EQZC_MMR6 |
| 2190 | 167792903U, // BC1F |
| 2191 | 167794796U, // BC1FL |
| 2192 | 167792903U, // BC1F_MM |
| 2193 | 167798764U, // BC1NEZ |
| 2194 | 167790743U, // BC1NEZC_MMR6 |
| 2195 | 167796279U, // BC1T |
| 2196 | 167794929U, // BC1TL |
| 2197 | 167796279U, // BC1T_MM |
| 2198 | 167798788U, // BC2EQZ |
| 2199 | 167790777U, // BC2EQZC_MMR6 |
| 2200 | 167798772U, // BC2NEZ |
| 2201 | 167790752U, // BC2NEZC_MMR6 |
| 2202 | 536888236U, // BCLRI_B |
| 2203 | 536890060U, // BCLRI_D |
| 2204 | 536891856U, // BCLRI_H |
| 2205 | 536895883U, // BCLRI_W |
| 2206 | 536888388U, // BCLR_B |
| 2207 | 536890448U, // BCLR_D |
| 2208 | 536892052U, // BCLR_H |
| 2209 | 536896254U, // BCLR_W |
| 2210 | 559040U, // BC_MMR6 |
| 2211 | 536894020U, // BEQ |
| 2212 | 536894020U, // BEQ64 |
| 2213 | 536889417U, // BEQC |
| 2214 | 536889417U, // BEQC64 |
| 2215 | 536889417U, // BEQC_MMR6 |
| 2216 | 536893669U, // BEQL |
| 2217 | 167789177U, // BEQZ16_MM |
| 2218 | 167790589U, // BEQZALC |
| 2219 | 167790589U, // BEQZALC_MMR6 |
| 2220 | 167790786U, // BEQZC |
| 2221 | 167788992U, // BEQZC16_MMR6 |
| 2222 | 167790786U, // BEQZC64 |
| 2223 | 167790786U, // BEQZC_MM |
| 2224 | 167790786U, // BEQZC_MMR6 |
| 2225 | 536894020U, // BEQ_MM |
| 2226 | 536889284U, // BGEC |
| 2227 | 536889284U, // BGEC64 |
| 2228 | 536889284U, // BGEC_MMR6 |
| 2229 | 536889448U, // BGEUC |
| 2230 | 536889448U, // BGEUC64 |
| 2231 | 536889448U, // BGEUC_MMR6 |
| 2232 | 167798463U, // BGEZ |
| 2233 | 167798463U, // BGEZ64 |
| 2234 | 167794681U, // BGEZAL |
| 2235 | 167790562U, // BGEZALC |
| 2236 | 167790562U, // BGEZALC_MMR6 |
| 2237 | 167794877U, // BGEZALL |
| 2238 | 167796145U, // BGEZALS_MM |
| 2239 | 167794681U, // BGEZAL_MM |
| 2240 | 167790729U, // BGEZC |
| 2241 | 167790729U, // BGEZC64 |
| 2242 | 167790729U, // BGEZC_MMR6 |
| 2243 | 167794992U, // BGEZL |
| 2244 | 167798463U, // BGEZ_MM |
| 2245 | 167798523U, // BGTZ |
| 2246 | 167798523U, // BGTZ64 |
| 2247 | 167790598U, // BGTZALC |
| 2248 | 167790598U, // BGTZALC_MMR6 |
| 2249 | 167790793U, // BGTZC |
| 2250 | 167790793U, // BGTZC64 |
| 2251 | 167790793U, // BGTZC_MMR6 |
| 2252 | 167795006U, // BGTZL |
| 2253 | 167798523U, // BGTZ_MM |
| 2254 | 570442641U, // BINSLI_B |
| 2255 | 570444465U, // BINSLI_D |
| 2256 | 570446261U, // BINSLI_H |
| 2257 | 570450288U, // BINSLI_W |
| 2258 | 570442788U, // BINSL_B |
| 2259 | 570444665U, // BINSL_D |
| 2260 | 570446375U, // BINSL_H |
| 2261 | 570450446U, // BINSL_W |
| 2262 | 570442702U, // BINSRI_B |
| 2263 | 570444510U, // BINSRI_D |
| 2264 | 570446306U, // BINSRI_H |
| 2265 | 570450333U, // BINSRI_W |
| 2266 | 570442836U, // BINSR_B |
| 2267 | 570444930U, // BINSR_D |
| 2268 | 570446500U, // BINSR_H |
| 2269 | 570450736U, // BINSR_W |
| 2270 | 24499U, // BITREV |
| 2271 | 24499U, // BITREV_MM |
| 2272 | 22945U, // BITSWAP |
| 2273 | 22945U, // BITSWAP_MMR6 |
| 2274 | 167798469U, // BLEZ |
| 2275 | 167798469U, // BLEZ64 |
| 2276 | 167790571U, // BLEZALC |
| 2277 | 167790571U, // BLEZALC_MMR6 |
| 2278 | 167790736U, // BLEZC |
| 2279 | 167790736U, // BLEZC64 |
| 2280 | 167790736U, // BLEZC_MMR6 |
| 2281 | 167794999U, // BLEZL |
| 2282 | 167798469U, // BLEZ_MM |
| 2283 | 536889442U, // BLTC |
| 2284 | 536889442U, // BLTC64 |
| 2285 | 536889442U, // BLTC_MMR6 |
| 2286 | 536889455U, // BLTUC |
| 2287 | 536889455U, // BLTUC64 |
| 2288 | 536889455U, // BLTUC_MMR6 |
| 2289 | 167798529U, // BLTZ |
| 2290 | 167798529U, // BLTZ64 |
| 2291 | 167794689U, // BLTZAL |
| 2292 | 167790607U, // BLTZALC |
| 2293 | 167790607U, // BLTZALC_MMR6 |
| 2294 | 167794886U, // BLTZALL |
| 2295 | 167796154U, // BLTZALS_MM |
| 2296 | 167794689U, // BLTZAL_MM |
| 2297 | 167790800U, // BLTZC |
| 2298 | 167790800U, // BLTZC64 |
| 2299 | 167790800U, // BLTZC_MMR6 |
| 2300 | 167795013U, // BLTZL |
| 2301 | 167798529U, // BLTZ_MM |
| 2302 | 570442757U, // BMNZI_B |
| 2303 | 570449828U, // BMNZ_V |
| 2304 | 570442749U, // BMZI_B |
| 2305 | 570449814U, // BMZ_V |
| 2306 | 536891588U, // BNE |
| 2307 | 536891588U, // BNE64 |
| 2308 | 536889290U, // BNEC |
| 2309 | 536889290U, // BNEC64 |
| 2310 | 536889290U, // BNEC_MMR6 |
| 2311 | 536888175U, // BNEGI_B |
| 2312 | 536890008U, // BNEGI_D |
| 2313 | 536891804U, // BNEGI_H |
| 2314 | 536895831U, // BNEGI_W |
| 2315 | 536888143U, // BNEG_B |
| 2316 | 536889984U, // BNEG_D |
| 2317 | 536891780U, // BNEG_H |
| 2318 | 536895726U, // BNEG_W |
| 2319 | 536893542U, // BNEL |
| 2320 | 167789169U, // BNEZ16_MM |
| 2321 | 167790580U, // BNEZALC |
| 2322 | 167790580U, // BNEZALC_MMR6 |
| 2323 | 167790761U, // BNEZC |
| 2324 | 167788983U, // BNEZC16_MMR6 |
| 2325 | 167790761U, // BNEZC64 |
| 2326 | 167790761U, // BNEZC_MM |
| 2327 | 167790761U, // BNEZC_MMR6 |
| 2328 | 536891588U, // BNE_MM |
| 2329 | 536889462U, // BNVC |
| 2330 | 536889462U, // BNVC_MMR6 |
| 2331 | 167790108U, // BNZ_B |
| 2332 | 167792624U, // BNZ_D |
| 2333 | 167793897U, // BNZ_H |
| 2334 | 167796637U, // BNZ_V |
| 2335 | 167798389U, // BNZ_W |
| 2336 | 536889468U, // BOVC |
| 2337 | 536889468U, // BOVC_MMR6 |
| 2338 | 557293U, // BPOSGE32 |
| 2339 | 559029U, // BPOSGE32C_MMR3 |
| 2340 | 557293U, // BPOSGE32_MM |
| 2341 | 184670160U, // BREAK |
| 2342 | 131572U, // BREAK16_MM |
| 2343 | 131572U, // BREAK16_MMR6 |
| 2344 | 184670160U, // BREAK_MM |
| 2345 | 184670160U, // BREAK_MMR6 |
| 2346 | 570442616U, // BSELI_B |
| 2347 | 570449786U, // BSEL_V |
| 2348 | 536888290U, // BSETI_B |
| 2349 | 536890098U, // BSETI_D |
| 2350 | 536891894U, // BSETI_H |
| 2351 | 536895921U, // BSETI_W |
| 2352 | 536888604U, // BSET_B |
| 2353 | 536890810U, // BSET_D |
| 2354 | 536892341U, // BSET_H |
| 2355 | 536896712U, // BSET_W |
| 2356 | 167790102U, // BZ_B |
| 2357 | 167792608U, // BZ_D |
| 2358 | 167793891U, // BZ_H |
| 2359 | 167796624U, // BZ_V |
| 2360 | 167798383U, // BZ_W |
| 2361 | 704669414U, // BeqzRxImm16 |
| 2362 | 167798502U, // BeqzRxImmX16 |
| 2363 | 4227823U, // Bimm16 |
| 2364 | 557807U, // BimmX16 |
| 2365 | 704669387U, // BnezRxImm16 |
| 2366 | 167798475U, // BnezRxImmX16 |
| 2367 | 10403U, // Break16 |
| 2368 | 4744948U, // Bteqz16 |
| 2369 | 550644U, // BteqzX16 |
| 2370 | 4744921U, // Btnez16 |
| 2371 | 550617U, // BtnezX16 |
| 2372 | 5394576U, // CACHE |
| 2373 | 5394546U, // CACHEE |
| 2374 | 5394546U, // CACHEE_MM |
| 2375 | 5394576U, // CACHE_MM |
| 2376 | 5394576U, // CACHE_MMR6 |
| 2377 | 5394576U, // CACHE_R6 |
| 2378 | 19235U, // CEIL_L_D64 |
| 2379 | 19235U, // CEIL_L_D_MMR6 |
| 2380 | 23567U, // CEIL_L_S |
| 2381 | 23567U, // CEIL_L_S_MMR6 |
| 2382 | 20410U, // CEIL_W_D32 |
| 2383 | 20410U, // CEIL_W_D64 |
| 2384 | 20410U, // CEIL_W_D_MMR6 |
| 2385 | 20410U, // CEIL_W_MM |
| 2386 | 23909U, // CEIL_W_S |
| 2387 | 23909U, // CEIL_W_S_MM |
| 2388 | 23909U, // CEIL_W_S_MMR6 |
| 2389 | 536888219U, // CEQI_B |
| 2390 | 536890043U, // CEQI_D |
| 2391 | 536891839U, // CEQI_H |
| 2392 | 536895866U, // CEQI_W |
| 2393 | 536888373U, // CEQ_B |
| 2394 | 536890355U, // CEQ_D |
| 2395 | 536892030U, // CEQ_H |
| 2396 | 536896142U, // CEQ_W |
| 2397 | 16482U, // CFC1 |
| 2398 | 16482U, // CFC1_MM |
| 2399 | 16698U, // CFC2_MM |
| 2400 | 17113U, // CFCMSA |
| 2401 | 536894915U, // CINS |
| 2402 | 536887582U, // CINS32 |
| 2403 | 536894915U, // CINS64_32 |
| 2404 | 536894915U, // CINS_i32 |
| 2405 | 19880U, // CLASS_D |
| 2406 | 19880U, // CLASS_D_MMR6 |
| 2407 | 23760U, // CLASS_S |
| 2408 | 23760U, // CLASS_S_MMR6 |
| 2409 | 536888458U, // CLEI_S_B |
| 2410 | 536890615U, // CLEI_S_D |
| 2411 | 536892164U, // CLEI_S_H |
| 2412 | 536896429U, // CLEI_S_W |
| 2413 | 536888673U, // CLEI_U_B |
| 2414 | 536891082U, // CLEI_U_D |
| 2415 | 536892452U, // CLEI_U_H |
| 2416 | 536896897U, // CLEI_U_W |
| 2417 | 536888440U, // CLE_S_B |
| 2418 | 536890597U, // CLE_S_D |
| 2419 | 536892146U, // CLE_S_H |
| 2420 | 536896411U, // CLE_S_W |
| 2421 | 536888655U, // CLE_U_B |
| 2422 | 536891064U, // CLE_U_D |
| 2423 | 536892434U, // CLE_U_H |
| 2424 | 536896879U, // CLE_U_W |
| 2425 | 22913U, // CLO |
| 2426 | 22913U, // CLO_MM |
| 2427 | 22913U, // CLO_MMR6 |
| 2428 | 22913U, // CLO_R6 |
| 2429 | 536888478U, // CLTI_S_B |
| 2430 | 536890635U, // CLTI_S_D |
| 2431 | 536892184U, // CLTI_S_H |
| 2432 | 536896449U, // CLTI_S_W |
| 2433 | 536888693U, // CLTI_U_B |
| 2434 | 536891102U, // CLTI_U_D |
| 2435 | 536892472U, // CLTI_U_H |
| 2436 | 536896917U, // CLTI_U_W |
| 2437 | 536888546U, // CLT_S_B |
| 2438 | 536890713U, // CLT_S_D |
| 2439 | 536892272U, // CLT_S_H |
| 2440 | 536896577U, // CLT_S_W |
| 2441 | 536888773U, // CLT_U_B |
| 2442 | 536891192U, // CLT_U_D |
| 2443 | 536892562U, // CLT_U_H |
| 2444 | 536897007U, // CLT_U_W |
| 2445 | 26337U, // CLZ |
| 2446 | 26337U, // CLZ_MM |
| 2447 | 26337U, // CLZ_MMR6 |
| 2448 | 26337U, // CLZ_R6 |
| 2449 | 536889023U, // CMPGDU_EQ_QB |
| 2450 | 536889023U, // CMPGDU_EQ_QB_MMR2 |
| 2451 | 536888928U, // CMPGDU_LE_QB |
| 2452 | 536888928U, // CMPGDU_LE_QB_MMR2 |
| 2453 | 536889142U, // CMPGDU_LT_QB |
| 2454 | 536889142U, // CMPGDU_LT_QB_MMR2 |
| 2455 | 536889037U, // CMPGU_EQ_QB |
| 2456 | 536889037U, // CMPGU_EQ_QB_MM |
| 2457 | 536888942U, // CMPGU_LE_QB |
| 2458 | 536888942U, // CMPGU_LE_QB_MM |
| 2459 | 536889156U, // CMPGU_LT_QB |
| 2460 | 536889156U, // CMPGU_LT_QB_MM |
| 2461 | 18138U, // CMPU_EQ_QB |
| 2462 | 18138U, // CMPU_EQ_QB_MM |
| 2463 | 18043U, // CMPU_LE_QB |
| 2464 | 18043U, // CMPU_LE_QB_MM |
| 2465 | 18257U, // CMPU_LT_QB |
| 2466 | 18257U, // CMPU_LT_QB_MM |
| 2467 | 536889905U, // CMP_AF_D_MMR6 |
| 2468 | 536894389U, // CMP_AF_S_MMR6 |
| 2469 | 536890344U, // CMP_EQ_D |
| 2470 | 536890344U, // CMP_EQ_D_MMR6 |
| 2471 | 21940U, // CMP_EQ_PH |
| 2472 | 21940U, // CMP_EQ_PH_MM |
| 2473 | 536894593U, // CMP_EQ_S |
| 2474 | 536894593U, // CMP_EQ_S_MMR6 |
| 2475 | 536889905U, // CMP_F_D |
| 2476 | 536894389U, // CMP_F_S |
| 2477 | 536889749U, // CMP_LE_D |
| 2478 | 536889749U, // CMP_LE_D_MMR6 |
| 2479 | 21836U, // CMP_LE_PH |
| 2480 | 21836U, // CMP_LE_PH_MM |
| 2481 | 536894310U, // CMP_LE_S |
| 2482 | 536894310U, // CMP_LE_S_MMR6 |
| 2483 | 536890835U, // CMP_LT_D |
| 2484 | 536890835U, // CMP_LT_D_MMR6 |
| 2485 | 22109U, // CMP_LT_PH |
| 2486 | 22109U, // CMP_LT_PH_MM |
| 2487 | 536894698U, // CMP_LT_S |
| 2488 | 536894698U, // CMP_LT_S_MMR6 |
| 2489 | 536889923U, // CMP_SAF_D |
| 2490 | 536889923U, // CMP_SAF_D_MMR6 |
| 2491 | 536894399U, // CMP_SAF_S |
| 2492 | 536894399U, // CMP_SAF_S_MMR6 |
| 2493 | 536890371U, // CMP_SEQ_D |
| 2494 | 536890371U, // CMP_SEQ_D_MMR6 |
| 2495 | 536894612U, // CMP_SEQ_S |
| 2496 | 536894612U, // CMP_SEQ_S_MMR6 |
| 2497 | 536889786U, // CMP_SLE_D |
| 2498 | 536889786U, // CMP_SLE_D_MMR6 |
| 2499 | 536894339U, // CMP_SLE_S |
| 2500 | 536894339U, // CMP_SLE_S_MMR6 |
| 2501 | 536890862U, // CMP_SLT_D |
| 2502 | 536890862U, // CMP_SLT_D_MMR6 |
| 2503 | 536894717U, // CMP_SLT_S |
| 2504 | 536894717U, // CMP_SLT_S_MMR6 |
| 2505 | 536890419U, // CMP_SUEQ_D |
| 2506 | 536890419U, // CMP_SUEQ_D_MMR6 |
| 2507 | 536894643U, // CMP_SUEQ_S |
| 2508 | 536894643U, // CMP_SUEQ_S_MMR6 |
| 2509 | 536889834U, // CMP_SULE_D |
| 2510 | 536889834U, // CMP_SULE_D_MMR6 |
| 2511 | 536894370U, // CMP_SULE_S |
| 2512 | 536894370U, // CMP_SULE_S_MMR6 |
| 2513 | 536890910U, // CMP_SULT_D |
| 2514 | 536890910U, // CMP_SULT_D_MMR6 |
| 2515 | 536894748U, // CMP_SULT_S |
| 2516 | 536894748U, // CMP_SULT_S_MMR6 |
| 2517 | 536890292U, // CMP_SUN_D |
| 2518 | 536890292U, // CMP_SUN_D_MMR6 |
| 2519 | 536894557U, // CMP_SUN_S |
| 2520 | 536894557U, // CMP_SUN_S_MMR6 |
| 2521 | 536890399U, // CMP_UEQ_D |
| 2522 | 536890399U, // CMP_UEQ_D_MMR6 |
| 2523 | 536894632U, // CMP_UEQ_S |
| 2524 | 536894632U, // CMP_UEQ_S_MMR6 |
| 2525 | 536889814U, // CMP_ULE_D |
| 2526 | 536889814U, // CMP_ULE_D_MMR6 |
| 2527 | 536894359U, // CMP_ULE_S |
| 2528 | 536894359U, // CMP_ULE_S_MMR6 |
| 2529 | 536890890U, // CMP_ULT_D |
| 2530 | 536890890U, // CMP_ULT_D_MMR6 |
| 2531 | 536894737U, // CMP_ULT_S |
| 2532 | 536894737U, // CMP_ULT_S_MMR6 |
| 2533 | 536890274U, // CMP_UN_D |
| 2534 | 536890274U, // CMP_UN_D_MMR6 |
| 2535 | 536894547U, // CMP_UN_S |
| 2536 | 536894547U, // CMP_UN_S_MMR6 |
| 2537 | 1073759497U, // COPY_S_B |
| 2538 | 1073761686U, // COPY_S_D |
| 2539 | 1073763234U, // COPY_S_H |
| 2540 | 1073767561U, // COPY_S_W |
| 2541 | 1073759712U, // COPY_U_B |
| 2542 | 1073763501U, // COPY_U_H |
| 2543 | 1073767968U, // COPY_U_W |
| 2544 | 536888867U, // CRC32B |
| 2545 | 536888875U, // CRC32CB |
| 2546 | 536891415U, // CRC32CD |
| 2547 | 536892676U, // CRC32CH |
| 2548 | 536897156U, // CRC32CW |
| 2549 | 536891401U, // CRC32D |
| 2550 | 536892656U, // CRC32H |
| 2551 | 536897148U, // CRC32W |
| 2552 | 17875069U, // CTC1 |
| 2553 | 17875069U, // CTC1_MM |
| 2554 | 17875285U, // CTC2_MM |
| 2555 | 17121U, // CTCMSA |
| 2556 | 23363U, // CVT_D32_S |
| 2557 | 23363U, // CVT_D32_S_MM |
| 2558 | 24662U, // CVT_D32_W |
| 2559 | 24662U, // CVT_D32_W_MM |
| 2560 | 22493U, // CVT_D64_L |
| 2561 | 23363U, // CVT_D64_S |
| 2562 | 23363U, // CVT_D64_S_MM |
| 2563 | 24662U, // CVT_D64_W |
| 2564 | 24662U, // CVT_D64_W_MM |
| 2565 | 22493U, // CVT_D_L_MMR6 |
| 2566 | 19256U, // CVT_L_D64 |
| 2567 | 19256U, // CVT_L_D64_MM |
| 2568 | 19256U, // CVT_L_D_MMR6 |
| 2569 | 23588U, // CVT_L_S |
| 2570 | 23588U, // CVT_L_S_MM |
| 2571 | 23588U, // CVT_L_S_MMR6 |
| 2572 | 26258U, // CVT_PS_PW64 |
| 2573 | 536894662U, // CVT_PS_S64 |
| 2574 | 24089U, // CVT_PW_PS64 |
| 2575 | 19603U, // CVT_S_D32 |
| 2576 | 19603U, // CVT_S_D32_MM |
| 2577 | 19603U, // CVT_S_D64 |
| 2578 | 19603U, // CVT_S_D64_MM |
| 2579 | 22502U, // CVT_S_L |
| 2580 | 22502U, // CVT_S_L_MMR6 |
| 2581 | 22747U, // CVT_S_PL64 |
| 2582 | 24353U, // CVT_S_PU64 |
| 2583 | 25417U, // CVT_S_W |
| 2584 | 25417U, // CVT_S_W_MM |
| 2585 | 25417U, // CVT_S_W_MMR6 |
| 2586 | 20431U, // CVT_W_D32 |
| 2587 | 20431U, // CVT_W_D32_MM |
| 2588 | 20431U, // CVT_W_D64 |
| 2589 | 20431U, // CVT_W_D64_MM |
| 2590 | 23930U, // CVT_W_S |
| 2591 | 23930U, // CVT_W_S_MM |
| 2592 | 23930U, // CVT_W_S_MMR6 |
| 2593 | 536890336U, // C_EQ_D32 |
| 2594 | 536890336U, // C_EQ_D32_MM |
| 2595 | 536890336U, // C_EQ_D64 |
| 2596 | 536890336U, // C_EQ_D64_MM |
| 2597 | 536894585U, // C_EQ_S |
| 2598 | 536894585U, // C_EQ_S_MM |
| 2599 | 536889898U, // C_F_D32 |
| 2600 | 536889898U, // C_F_D32_MM |
| 2601 | 536889898U, // C_F_D64 |
| 2602 | 536889898U, // C_F_D64_MM |
| 2603 | 536894382U, // C_F_S |
| 2604 | 536894382U, // C_F_S_MM |
| 2605 | 536889741U, // C_LE_D32 |
| 2606 | 536889741U, // C_LE_D32_MM |
| 2607 | 536889741U, // C_LE_D64 |
| 2608 | 536889741U, // C_LE_D64_MM |
| 2609 | 536894302U, // C_LE_S |
| 2610 | 536894302U, // C_LE_S_MM |
| 2611 | 536890827U, // C_LT_D32 |
| 2612 | 536890827U, // C_LT_D32_MM |
| 2613 | 536890827U, // C_LT_D64 |
| 2614 | 536890827U, // C_LT_D64_MM |
| 2615 | 536894690U, // C_LT_S |
| 2616 | 536894690U, // C_LT_S_MM |
| 2617 | 536889732U, // C_NGE_D32 |
| 2618 | 536889732U, // C_NGE_D32_MM |
| 2619 | 536889732U, // C_NGE_D64 |
| 2620 | 536889732U, // C_NGE_D64_MM |
| 2621 | 536894293U, // C_NGE_S |
| 2622 | 536894293U, // C_NGE_S_MM |
| 2623 | 536889767U, // C_NGLE_D32 |
| 2624 | 536889767U, // C_NGLE_D32_MM |
| 2625 | 536889767U, // C_NGLE_D64 |
| 2626 | 536889767U, // C_NGLE_D64_MM |
| 2627 | 536894320U, // C_NGLE_S |
| 2628 | 536894320U, // C_NGLE_S_MM |
| 2629 | 536890184U, // C_NGL_D32 |
| 2630 | 536890184U, // C_NGL_D32_MM |
| 2631 | 536890184U, // C_NGL_D64 |
| 2632 | 536890184U, // C_NGL_D64_MM |
| 2633 | 536894516U, // C_NGL_S |
| 2634 | 536894516U, // C_NGL_S_MM |
| 2635 | 536890818U, // C_NGT_D32 |
| 2636 | 536890818U, // C_NGT_D32_MM |
| 2637 | 536890818U, // C_NGT_D64 |
| 2638 | 536890818U, // C_NGT_D64_MM |
| 2639 | 536894681U, // C_NGT_S |
| 2640 | 536894681U, // C_NGT_S_MM |
| 2641 | 536889777U, // C_OLE_D32 |
| 2642 | 536889777U, // C_OLE_D32_MM |
| 2643 | 536889777U, // C_OLE_D64 |
| 2644 | 536889777U, // C_OLE_D64_MM |
| 2645 | 536894330U, // C_OLE_S |
| 2646 | 536894330U, // C_OLE_S_MM |
| 2647 | 536890853U, // C_OLT_D32 |
| 2648 | 536890853U, // C_OLT_D32_MM |
| 2649 | 536890853U, // C_OLT_D64 |
| 2650 | 536890853U, // C_OLT_D64_MM |
| 2651 | 536894708U, // C_OLT_S |
| 2652 | 536894708U, // C_OLT_S_MM |
| 2653 | 536890362U, // C_SEQ_D32 |
| 2654 | 536890362U, // C_SEQ_D32_MM |
| 2655 | 536890362U, // C_SEQ_D64 |
| 2656 | 536890362U, // C_SEQ_D64_MM |
| 2657 | 536894603U, // C_SEQ_S |
| 2658 | 536894603U, // C_SEQ_S_MM |
| 2659 | 536889968U, // C_SF_D32 |
| 2660 | 536889968U, // C_SF_D32_MM |
| 2661 | 536889968U, // C_SF_D64 |
| 2662 | 536889968U, // C_SF_D64_MM |
| 2663 | 536894428U, // C_SF_S |
| 2664 | 536894428U, // C_SF_S_MM |
| 2665 | 536890390U, // C_UEQ_D32 |
| 2666 | 536890390U, // C_UEQ_D32_MM |
| 2667 | 536890390U, // C_UEQ_D64 |
| 2668 | 536890390U, // C_UEQ_D64_MM |
| 2669 | 536894623U, // C_UEQ_S |
| 2670 | 536894623U, // C_UEQ_S_MM |
| 2671 | 536889805U, // C_ULE_D32 |
| 2672 | 536889805U, // C_ULE_D32_MM |
| 2673 | 536889805U, // C_ULE_D64 |
| 2674 | 536889805U, // C_ULE_D64_MM |
| 2675 | 536894350U, // C_ULE_S |
| 2676 | 536894350U, // C_ULE_S_MM |
| 2677 | 536890881U, // C_ULT_D32 |
| 2678 | 536890881U, // C_ULT_D32_MM |
| 2679 | 536890881U, // C_ULT_D64 |
| 2680 | 536890881U, // C_ULT_D64_MM |
| 2681 | 536894728U, // C_ULT_S |
| 2682 | 536894728U, // C_ULT_S_MM |
| 2683 | 536890266U, // C_UN_D32 |
| 2684 | 536890266U, // C_UN_D32_MM |
| 2685 | 536890266U, // C_UN_D64 |
| 2686 | 536890266U, // C_UN_D64_MM |
| 2687 | 536894539U, // C_UN_S |
| 2688 | 536894539U, // C_UN_S_MM |
| 2689 | 22984U, // CmpRxRy16 |
| 2690 | 1610635153U, // CmpiRxImm16 |
| 2691 | 22417U, // CmpiRxImmX16 |
| 2692 | 536891429U, // DADD |
| 2693 | 536893261U, // DADDi |
| 2694 | 536895199U, // DADDiu |
| 2695 | 536895135U, // DADDu |
| 2696 | 536893292U, // DAHI |
| 2697 | 536893810U, // DALIGN |
| 2698 | 536893353U, // DATI |
| 2699 | 536893371U, // DAUI |
| 2700 | 22944U, // DBITSWAP |
| 2701 | 22912U, // DCLO |
| 2702 | 22912U, // DCLO_R6 |
| 2703 | 26336U, // DCLZ |
| 2704 | 26336U, // DCLZ_R6 |
| 2705 | 536895419U, // DDIV |
| 2706 | 536895327U, // DDIVU |
| 2707 | 10650U, // DERET |
| 2708 | 10650U, // DERET_MM |
| 2709 | 10650U, // DERET_MMR6 |
| 2710 | 536895103U, // DEXT |
| 2711 | 536897494U, // DEXT64_32 |
| 2712 | 536893785U, // DEXTM |
| 2713 | 536895320U, // DEXTU |
| 2714 | 546640U, // DI |
| 2715 | 536894921U, // DINS |
| 2716 | 536893778U, // DINSM |
| 2717 | 536895275U, // DINSU |
| 2718 | 536895420U, // DIV |
| 2719 | 536895328U, // DIVU |
| 2720 | 536895328U, // DIVU_MMR6 |
| 2721 | 536895420U, // DIV_MMR6 |
| 2722 | 536888567U, // DIV_S_B |
| 2723 | 536890756U, // DIV_S_D |
| 2724 | 536892293U, // DIV_S_H |
| 2725 | 536896620U, // DIV_S_W |
| 2726 | 536888782U, // DIV_U_B |
| 2727 | 536891223U, // DIV_U_D |
| 2728 | 536892571U, // DIV_U_H |
| 2729 | 536897038U, // DIV_U_W |
| 2730 | 546640U, // DI_MM |
| 2731 | 546640U, // DI_MMR6 |
| 2732 | 536888019U, // DLSA |
| 2733 | 536888019U, // DLSA_R6 |
| 2734 | 536887297U, // DMFC0 |
| 2735 | 16488U, // DMFC1 |
| 2736 | 536887616U, // DMFC2 |
| 2737 | 201343296U, // DMFC2_OCTEON |
| 2738 | 536887304U, // DMFGC0 |
| 2739 | 536891481U, // DMOD |
| 2740 | 536895149U, // DMODU |
| 2741 | 548451U, // DMT |
| 2742 | 2752561206U, // DMTC0 |
| 2743 | 17875075U, // DMTC1 |
| 2744 | 2752561499U, // DMTC2 |
| 2745 | 201343323U, // DMTC2_OCTEON |
| 2746 | 2752561184U, // DMTGC0 |
| 2747 | 536893248U, // DMUH |
| 2748 | 536895192U, // DMUHU |
| 2749 | 536893714U, // DMUL |
| 2750 | 24156U, // DMULT |
| 2751 | 24400U, // DMULTu |
| 2752 | 536895236U, // DMULU |
| 2753 | 536893714U, // DMUL_R6 |
| 2754 | 536890664U, // DOTP_S_D |
| 2755 | 536892213U, // DOTP_S_H |
| 2756 | 536896488U, // DOTP_S_W |
| 2757 | 536891131U, // DOTP_U_D |
| 2758 | 536892501U, // DOTP_U_H |
| 2759 | 536896946U, // DOTP_U_W |
| 2760 | 570445009U, // DPADD_S_D |
| 2761 | 570446558U, // DPADD_S_H |
| 2762 | 570450823U, // DPADD_S_W |
| 2763 | 570445476U, // DPADD_U_D |
| 2764 | 570446846U, // DPADD_U_H |
| 2765 | 570451291U, // DPADD_U_W |
| 2766 | 536893100U, // DPAQX_SA_W_PH |
| 2767 | 536893100U, // DPAQX_SA_W_PH_MMR2 |
| 2768 | 536893183U, // DPAQX_S_W_PH |
| 2769 | 536893183U, // DPAQX_S_W_PH_MMR2 |
| 2770 | 536895948U, // DPAQ_SA_L_W |
| 2771 | 536895948U, // DPAQ_SA_L_W_MM |
| 2772 | 536893142U, // DPAQ_S_W_PH |
| 2773 | 536893142U, // DPAQ_S_W_PH_MM |
| 2774 | 536893449U, // DPAU_H_QBL |
| 2775 | 536893449U, // DPAU_H_QBL_MM |
| 2776 | 536894035U, // DPAU_H_QBR |
| 2777 | 536894035U, // DPAU_H_QBR_MM |
| 2778 | 536893221U, // DPAX_W_PH |
| 2779 | 536893221U, // DPAX_W_PH_MMR2 |
| 2780 | 536893090U, // DPA_W_PH |
| 2781 | 536893090U, // DPA_W_PH_MMR2 |
| 2782 | 22989U, // DPOP |
| 2783 | 536893115U, // DPSQX_SA_W_PH |
| 2784 | 536893115U, // DPSQX_SA_W_PH_MMR2 |
| 2785 | 536893197U, // DPSQX_S_W_PH |
| 2786 | 536893197U, // DPSQX_S_W_PH_MMR2 |
| 2787 | 536895961U, // DPSQ_SA_L_W |
| 2788 | 536895961U, // DPSQ_SA_L_W_MM |
| 2789 | 536893170U, // DPSQ_S_W_PH |
| 2790 | 536893170U, // DPSQ_S_W_PH_MM |
| 2791 | 570444976U, // DPSUB_S_D |
| 2792 | 570446537U, // DPSUB_S_H |
| 2793 | 570450790U, // DPSUB_S_W |
| 2794 | 570445443U, // DPSUB_U_D |
| 2795 | 570446825U, // DPSUB_U_H |
| 2796 | 570451258U, // DPSUB_U_W |
| 2797 | 536893461U, // DPSU_H_QBL |
| 2798 | 536893461U, // DPSU_H_QBL_MM |
| 2799 | 536894047U, // DPSU_H_QBR |
| 2800 | 536894047U, // DPSU_H_QBR_MM |
| 2801 | 536893232U, // DPSX_W_PH |
| 2802 | 536893232U, // DPSX_W_PH_MMR2 |
| 2803 | 536893211U, // DPS_W_PH |
| 2804 | 536893211U, // DPS_W_PH_MMR2 |
| 2805 | 536894220U, // DROTR |
| 2806 | 536887573U, // DROTR32 |
| 2807 | 536895463U, // DROTRV |
| 2808 | 21752U, // DSBH |
| 2809 | 26407U, // DSDIV |
| 2810 | 20529U, // DSHD |
| 2811 | 536893647U, // DSLL |
| 2812 | 536887543U, // DSLL32 |
| 2813 | 2147506383U, // DSLL64_32 |
| 2814 | 536895425U, // DSLLV |
| 2815 | 536888013U, // DSRA |
| 2816 | 536887525U, // DSRA32 |
| 2817 | 536895404U, // DSRAV |
| 2818 | 536893675U, // DSRL |
| 2819 | 536887551U, // DSRL32 |
| 2820 | 536895432U, // DSRLV |
| 2821 | 536889257U, // DSUB |
| 2822 | 536895114U, // DSUBu |
| 2823 | 26393U, // DUDIV |
| 2824 | 547376U, // DVP |
| 2825 | 544979U, // DVPE |
| 2826 | 547376U, // DVP_MMR6 |
| 2827 | 26408U, // DivRxRy16 |
| 2828 | 26394U, // DivuRxRy16 |
| 2829 | 10540U, // EHB |
| 2830 | 10540U, // EHB_MM |
| 2831 | 10540U, // EHB_MMR6 |
| 2832 | 546652U, // EI |
| 2833 | 546652U, // EI_MM |
| 2834 | 546652U, // EI_MMR6 |
| 2835 | 548456U, // EMT |
| 2836 | 10651U, // ERET |
| 2837 | 10544U, // ERETNC |
| 2838 | 10544U, // ERETNC_MMR6 |
| 2839 | 10651U, // ERET_MM |
| 2840 | 10651U, // ERET_MMR6 |
| 2841 | 547381U, // EVP |
| 2842 | 544985U, // EVPE |
| 2843 | 547381U, // EVP_MMR6 |
| 2844 | 536895104U, // EXT |
| 2845 | 536893994U, // EXTP |
| 2846 | 536893873U, // EXTPDP |
| 2847 | 536895447U, // EXTPDPV |
| 2848 | 536895447U, // EXTPDPV_MM |
| 2849 | 536893873U, // EXTPDP_MM |
| 2850 | 536895456U, // EXTPV |
| 2851 | 536895456U, // EXTPV_MM |
| 2852 | 536893994U, // EXTP_MM |
| 2853 | 536896681U, // EXTRV_RS_W |
| 2854 | 536896681U, // EXTRV_RS_W_MM |
| 2855 | 536896235U, // EXTRV_R_W |
| 2856 | 536896235U, // EXTRV_R_W_MM |
| 2857 | 536892302U, // EXTRV_S_H |
| 2858 | 536892302U, // EXTRV_S_H_MM |
| 2859 | 536897118U, // EXTRV_W |
| 2860 | 536897118U, // EXTRV_W_MM |
| 2861 | 536896670U, // EXTR_RS_W |
| 2862 | 536896670U, // EXTR_RS_W_MM |
| 2863 | 536896214U, // EXTR_R_W |
| 2864 | 536896214U, // EXTR_R_W_MM |
| 2865 | 536892233U, // EXTR_S_H |
| 2866 | 536892233U, // EXTR_S_H_MM |
| 2867 | 536896313U, // EXTR_W |
| 2868 | 536896313U, // EXTR_W_MM |
| 2869 | 536895019U, // EXTS |
| 2870 | 536887590U, // EXTS32 |
| 2871 | 536895104U, // EXT_MM |
| 2872 | 536895104U, // EXT_MMR6 |
| 2873 | 19872U, // FABS_D32 |
| 2874 | 19872U, // FABS_D32_MM |
| 2875 | 19872U, // FABS_D64 |
| 2876 | 19872U, // FABS_D64_MM |
| 2877 | 23743U, // FABS_S |
| 2878 | 23743U, // FABS_S_MM |
| 2879 | 536889681U, // FADD_D |
| 2880 | 536889682U, // FADD_D32 |
| 2881 | 536889682U, // FADD_D32_MM |
| 2882 | 536889682U, // FADD_D64 |
| 2883 | 536889682U, // FADD_D64_MM |
| 2884 | 536894935U, // FADD_PS64 |
| 2885 | 536894286U, // FADD_S |
| 2886 | 536894286U, // FADD_S_MM |
| 2887 | 570448718U, // FADD_S_MMR6 |
| 2888 | 536895583U, // FADD_W |
| 2889 | 536889915U, // FCAF_D |
| 2890 | 536895702U, // FCAF_W |
| 2891 | 536890354U, // FCEQ_D |
| 2892 | 536896141U, // FCEQ_W |
| 2893 | 19879U, // FCLASS_D |
| 2894 | 25781U, // FCLASS_W |
| 2895 | 536889759U, // FCLE_D |
| 2896 | 536895625U, // FCLE_W |
| 2897 | 536890845U, // FCLT_D |
| 2898 | 536896720U, // FCLT_W |
| 2899 | 5941291U, // FCMP_D32 |
| 2900 | 5941291U, // FCMP_D32_MM |
| 2901 | 5941291U, // FCMP_D64 |
| 2902 | 6465579U, // FCMP_S32 |
| 2903 | 6465579U, // FCMP_S32_MM |
| 2904 | 536889855U, // FCNE_D |
| 2905 | 536895659U, // FCNE_W |
| 2906 | 536890464U, // FCOR_D |
| 2907 | 536896270U, // FCOR_W |
| 2908 | 536890410U, // FCUEQ_D |
| 2909 | 536896157U, // FCUEQ_W |
| 2910 | 536889825U, // FCULE_D |
| 2911 | 536895641U, // FCULE_W |
| 2912 | 536890901U, // FCULT_D |
| 2913 | 536896736U, // FCULT_W |
| 2914 | 536889871U, // FCUNE_D |
| 2915 | 536895675U, // FCUNE_W |
| 2916 | 536890284U, // FCUN_D |
| 2917 | 536896047U, // FCUN_W |
| 2918 | 536891277U, // FDIV_D |
| 2919 | 536891278U, // FDIV_D32 |
| 2920 | 536891278U, // FDIV_D32_MM |
| 2921 | 536891278U, // FDIV_D64 |
| 2922 | 536891278U, // FDIV_D64_MM |
| 2923 | 536894785U, // FDIV_S |
| 2924 | 536894785U, // FDIV_S_MM |
| 2925 | 570449217U, // FDIV_S_MMR6 |
| 2926 | 536897102U, // FDIV_W |
| 2927 | 536891960U, // FEXDO_H |
| 2928 | 536896063U, // FEXDO_W |
| 2929 | 536889568U, // FEXP2_D |
| 2930 | 536895486U, // FEXP2_W |
| 2931 | 19296U, // FEXUPL_D |
| 2932 | 25077U, // FEXUPL_W |
| 2933 | 19568U, // FEXUPR_D |
| 2934 | 25374U, // FEXUPR_W |
| 2935 | 19810U, // FFINT_S_D |
| 2936 | 25674U, // FFINT_S_W |
| 2937 | 20289U, // FFINT_U_D |
| 2938 | 26104U, // FFINT_U_W |
| 2939 | 19306U, // FFQL_D |
| 2940 | 25087U, // FFQL_W |
| 2941 | 19578U, // FFQR_D |
| 2942 | 25384U, // FFQR_W |
| 2943 | 17422U, // FILL_B |
| 2944 | 19281U, // FILL_D |
| 2945 | 21009U, // FILL_H |
| 2946 | 25062U, // FILL_W |
| 2947 | 18647U, // FLOG2_D |
| 2948 | 24565U, // FLOG2_W |
| 2949 | 19245U, // FLOOR_L_D64 |
| 2950 | 19245U, // FLOOR_L_D_MMR6 |
| 2951 | 23577U, // FLOOR_L_S |
| 2952 | 23577U, // FLOOR_L_S_MMR6 |
| 2953 | 20420U, // FLOOR_W_D32 |
| 2954 | 20420U, // FLOOR_W_D64 |
| 2955 | 20420U, // FLOOR_W_D_MMR6 |
| 2956 | 20420U, // FLOOR_W_MM |
| 2957 | 23919U, // FLOOR_W_S |
| 2958 | 23919U, // FLOOR_W_S_MM |
| 2959 | 23919U, // FLOOR_W_S_MMR6 |
| 2960 | 570444121U, // FMADD_D |
| 2961 | 570450023U, // FMADD_W |
| 2962 | 536889606U, // FMAX_A_D |
| 2963 | 536895524U, // FMAX_A_W |
| 2964 | 536891352U, // FMAX_D |
| 2965 | 536897127U, // FMAX_W |
| 2966 | 536889586U, // FMIN_A_D |
| 2967 | 536895504U, // FMIN_A_W |
| 2968 | 536890258U, // FMIN_D |
| 2969 | 536896039U, // FMIN_W |
| 2970 | 20381U, // FMOV_D32 |
| 2971 | 20381U, // FMOV_D32_MM |
| 2972 | 20381U, // FMOV_D64 |
| 2973 | 20381U, // FMOV_D64_MM |
| 2974 | 20381U, // FMOV_D_MMR6 |
| 2975 | 23880U, // FMOV_S |
| 2976 | 23880U, // FMOV_S_MM |
| 2977 | 23880U, // FMOV_S_MMR6 |
| 2978 | 570444079U, // FMSUB_D |
| 2979 | 570449981U, // FMSUB_W |
| 2980 | 536890242U, // FMUL_D |
| 2981 | 536890243U, // FMUL_D32 |
| 2982 | 536890243U, // FMUL_D32_MM |
| 2983 | 536890243U, // FMUL_D64 |
| 2984 | 536890243U, // FMUL_D64_MM |
| 2985 | 536894951U, // FMUL_PS64 |
| 2986 | 536894525U, // FMUL_S |
| 2987 | 536894525U, // FMUL_S_MM |
| 2988 | 570448957U, // FMUL_S_MMR6 |
| 2989 | 536896023U, // FMUL_W |
| 2990 | 19073U, // FNEG_D32 |
| 2991 | 19073U, // FNEG_D32_MM |
| 2992 | 19073U, // FNEG_D64 |
| 2993 | 19073U, // FNEG_D64_MM |
| 2994 | 23532U, // FNEG_S |
| 2995 | 23532U, // FNEG_S_MM |
| 2996 | 23532U, // FNEG_S_MMR6 |
| 2997 | 2752567255U, // FORK |
| 2998 | 19407U, // FRCP_D |
| 2999 | 25160U, // FRCP_W |
| 3000 | 20027U, // FRINT_D |
| 3001 | 25850U, // FRINT_W |
| 3002 | 20055U, // FRSQRT_D |
| 3003 | 25878U, // FRSQRT_W |
| 3004 | 536889934U, // FSAF_D |
| 3005 | 536895710U, // FSAF_W |
| 3006 | 536890382U, // FSEQ_D |
| 3007 | 536896149U, // FSEQ_W |
| 3008 | 536889797U, // FSLE_D |
| 3009 | 536895633U, // FSLE_W |
| 3010 | 536890873U, // FSLT_D |
| 3011 | 536896728U, // FSLT_W |
| 3012 | 536889863U, // FSNE_D |
| 3013 | 536895667U, // FSNE_W |
| 3014 | 536890472U, // FSOR_D |
| 3015 | 536896278U, // FSOR_W |
| 3016 | 20046U, // FSQRT_D |
| 3017 | 20047U, // FSQRT_D32 |
| 3018 | 20047U, // FSQRT_D32_MM |
| 3019 | 20047U, // FSQRT_D64 |
| 3020 | 20047U, // FSQRT_D64_MM |
| 3021 | 23857U, // FSQRT_S |
| 3022 | 23857U, // FSQRT_S_MM |
| 3023 | 25869U, // FSQRT_W |
| 3024 | 536889639U, // FSUB_D |
| 3025 | 536889640U, // FSUB_D32 |
| 3026 | 536889640U, // FSUB_D32_MM |
| 3027 | 536889640U, // FSUB_D64 |
| 3028 | 536889640U, // FSUB_D64_MM |
| 3029 | 536894927U, // FSUB_PS64 |
| 3030 | 536894268U, // FSUB_S |
| 3031 | 536894268U, // FSUB_S_MM |
| 3032 | 570448700U, // FSUB_S_MMR6 |
| 3033 | 536895541U, // FSUB_W |
| 3034 | 536890431U, // FSUEQ_D |
| 3035 | 536896166U, // FSUEQ_W |
| 3036 | 536889846U, // FSULE_D |
| 3037 | 536895650U, // FSULE_W |
| 3038 | 536890922U, // FSULT_D |
| 3039 | 536896745U, // FSULT_W |
| 3040 | 536889880U, // FSUNE_D |
| 3041 | 536895684U, // FSUNE_W |
| 3042 | 536890303U, // FSUN_D |
| 3043 | 536896055U, // FSUN_W |
| 3044 | 19821U, // FTINT_S_D |
| 3045 | 25685U, // FTINT_S_W |
| 3046 | 20300U, // FTINT_U_D |
| 3047 | 26115U, // FTINT_U_W |
| 3048 | 536892037U, // FTQ_H |
| 3049 | 536896175U, // FTQ_W |
| 3050 | 19643U, // FTRUNC_S_D |
| 3051 | 25457U, // FTRUNC_S_W |
| 3052 | 20110U, // FTRUNC_U_D |
| 3053 | 25925U, // FTRUNC_U_W |
| 3054 | 546758U, // GINVI |
| 3055 | 546758U, // GINVI_MMR6 |
| 3056 | 218127986U, // GINVT |
| 3057 | 218127986U, // GINVT_MMR6 |
| 3058 | 536890567U, // HADD_S_D |
| 3059 | 536892116U, // HADD_S_H |
| 3060 | 536896381U, // HADD_S_W |
| 3061 | 536891034U, // HADD_U_D |
| 3062 | 536892404U, // HADD_U_H |
| 3063 | 536896849U, // HADD_U_W |
| 3064 | 536890534U, // HSUB_S_D |
| 3065 | 536892095U, // HSUB_S_H |
| 3066 | 536896348U, // HSUB_S_W |
| 3067 | 536891001U, // HSUB_U_D |
| 3068 | 536892383U, // HSUB_U_H |
| 3069 | 536896816U, // HSUB_U_W |
| 3070 | 645291U, // HYPCALL |
| 3071 | 645291U, // HYPCALL_MM |
| 3072 | 536888837U, // ILVEV_B |
| 3073 | 536891268U, // ILVEV_D |
| 3074 | 536892626U, // ILVEV_H |
| 3075 | 536897093U, // ILVEV_W |
| 3076 | 536888365U, // ILVL_B |
| 3077 | 536890250U, // ILVL_D |
| 3078 | 536891952U, // ILVL_H |
| 3079 | 536896031U, // ILVL_W |
| 3080 | 536888117U, // ILVOD_B |
| 3081 | 536889723U, // ILVOD_D |
| 3082 | 536891754U, // ILVOD_H |
| 3083 | 536895616U, // ILVOD_W |
| 3084 | 536888413U, // ILVR_B |
| 3085 | 536890507U, // ILVR_D |
| 3086 | 536892077U, // ILVR_H |
| 3087 | 536896321U, // ILVR_W |
| 3088 | 536894916U, // INS |
| 3089 | 241714476U, // INSERT_B |
| 3090 | 258494020U, // INSERT_D |
| 3091 | 275272645U, // INSERT_H |
| 3092 | 292054275U, // INSERT_W |
| 3093 | 33578991U, // INSV |
| 3094 | 308822846U, // INSVE_B |
| 3095 | 325601825U, // INSVE_D |
| 3096 | 342380915U, // INSVE_H |
| 3097 | 359162061U, // INSVE_W |
| 3098 | 33578991U, // INSV_MM |
| 3099 | 536894916U, // INS_MM |
| 3100 | 536894916U, // INS_MMR6 |
| 3101 | 186317U, // J |
| 3102 | 186356U, // JAL |
| 3103 | 23264U, // JALR |
| 3104 | 547552U, // JALR16_MM |
| 3105 | 23264U, // JALR64 |
| 3106 | 547552U, // JALRC16_MMR6 |
| 3107 | 17977U, // JALRC_HB_MMR6 |
| 3108 | 18516U, // JALRC_MMR6 |
| 3109 | 541239U, // JALRS16_MM |
| 3110 | 24100U, // JALRS_MM |
| 3111 | 17994U, // JALR_HB |
| 3112 | 17994U, // JALR_HB64 |
| 3113 | 23264U, // JALR_MM |
| 3114 | 187819U, // JALS_MM |
| 3115 | 190126U, // JALX |
| 3116 | 190126U, // JALX_MM |
| 3117 | 186356U, // JAL_MM |
| 3118 | 18395U, // JIALC |
| 3119 | 18395U, // JIALC64 |
| 3120 | 18395U, // JIALC_MMR6 |
| 3121 | 18384U, // JIC |
| 3122 | 18384U, // JIC64 |
| 3123 | 18384U, // JIC_MMR6 |
| 3124 | 547548U, // JR |
| 3125 | 541226U, // JR16_MM |
| 3126 | 547548U, // JR64 |
| 3127 | 547353U, // JRADDIUSP |
| 3128 | 542799U, // JRC16_MM |
| 3129 | 541104U, // JRC16_MMR6 |
| 3130 | 547341U, // JRCADDIUSP_MMR6 |
| 3131 | 542275U, // JR_HB |
| 3132 | 542275U, // JR_HB64 |
| 3133 | 542275U, // JR_HB64_R6 |
| 3134 | 542275U, // JR_HB_R6 |
| 3135 | 547548U, // JR_MM |
| 3136 | 186317U, // J_MM |
| 3137 | 7542772U, // Jal16 |
| 3138 | 8067060U, // JalB16 |
| 3139 | 10533U, // JrRa16 |
| 3140 | 10525U, // JrcRa16 |
| 3141 | 542799U, // JrcRx16 |
| 3142 | 542804U, // JumpLinkReg16 |
| 3143 | 50349651U, // LB |
| 3144 | 50349651U, // LB64 |
| 3145 | 50352227U, // LBE |
| 3146 | 50352227U, // LBE_MM |
| 3147 | 50348615U, // LBU16_MM |
| 3148 | 3254806196U, // LBUX |
| 3149 | 3254806196U, // LBUX_MM |
| 3150 | 50355845U, // LBU_MMR6 |
| 3151 | 50349651U, // LB_MM |
| 3152 | 50349651U, // LB_MMR6 |
| 3153 | 50355845U, // LBu |
| 3154 | 50355845U, // LBu64 |
| 3155 | 50352363U, // LBuE |
| 3156 | 50352363U, // LBuE_MM |
| 3157 | 50355845U, // LBu_MM |
| 3158 | 50352186U, // LD |
| 3159 | 50348118U, // LDC1 |
| 3160 | 50348118U, // LDC164 |
| 3161 | 50348118U, // LDC1_D64_MMR6 |
| 3162 | 50348118U, // LDC1_MM_D32 |
| 3163 | 50348118U, // LDC1_MM_D64 |
| 3164 | 50348334U, // LDC2 |
| 3165 | 50348334U, // LDC2_MMR6 |
| 3166 | 50348334U, // LDC2_R6 |
| 3167 | 50348419U, // LDC3 |
| 3168 | 17248U, // LDI_B |
| 3169 | 19089U, // LDI_D |
| 3170 | 20885U, // LDI_H |
| 3171 | 24912U, // LDI_W |
| 3172 | 50354256U, // LDL |
| 3173 | 18462U, // LDPC |
| 3174 | 50354842U, // LDR |
| 3175 | 3254796438U, // LDXC1 |
| 3176 | 3254796438U, // LDXC164 |
| 3177 | 50348838U, // LD_B |
| 3178 | 50350444U, // LD_D |
| 3179 | 50352475U, // LD_H |
| 3180 | 50356337U, // LD_W |
| 3181 | 134242016U, // LEA_ADDiu |
| 3182 | 134242015U, // LEA_ADDiu64 |
| 3183 | 134242016U, // LEA_ADDiu_MM |
| 3184 | 50353427U, // LH |
| 3185 | 50353427U, // LH64 |
| 3186 | 50352279U, // LHE |
| 3187 | 50352279U, // LHE_MM |
| 3188 | 50348638U, // LHU16_MM |
| 3189 | 3254806185U, // LHX |
| 3190 | 3254806185U, // LHX_MM |
| 3191 | 50353427U, // LH_MM |
| 3192 | 50355923U, // LHu |
| 3193 | 50355923U, // LHu64 |
| 3194 | 50352369U, // LHuE |
| 3195 | 50352369U, // LHuE_MM |
| 3196 | 50355923U, // LHu_MM |
| 3197 | 16878U, // LI16_MM |
| 3198 | 16878U, // LI16_MMR6 |
| 3199 | 50354352U, // LL |
| 3200 | 50354352U, // LL64 |
| 3201 | 50354352U, // LL64_R6 |
| 3202 | 50352190U, // LLD |
| 3203 | 50352190U, // LLD_R6 |
| 3204 | 50352302U, // LLE |
| 3205 | 50352302U, // LLE_MM |
| 3206 | 50354352U, // LL_MM |
| 3207 | 50354352U, // LL_MMR6 |
| 3208 | 50354352U, // LL_R6 |
| 3209 | 536888020U, // LSA |
| 3210 | 3828450004U, // LSA_MMR6 |
| 3211 | 536888020U, // LSA_R6 |
| 3212 | 201349057U, // LUI_MMR6 |
| 3213 | 3254796452U, // LUXC1 |
| 3214 | 3254796452U, // LUXC164 |
| 3215 | 3254796452U, // LUXC1_MM |
| 3216 | 201349057U, // LUi |
| 3217 | 201349057U, // LUi64 |
| 3218 | 201349057U, // LUi_MM |
| 3219 | 50357902U, // LW |
| 3220 | 50348645U, // LW16_MM |
| 3221 | 50357902U, // LW64 |
| 3222 | 50348170U, // LWC1 |
| 3223 | 50348170U, // LWC1_MM |
| 3224 | 50348386U, // LWC2 |
| 3225 | 50348386U, // LWC2_MMR6 |
| 3226 | 50348386U, // LWC2_R6 |
| 3227 | 50348431U, // LWC3 |
| 3228 | 50357902U, // LWDSP |
| 3229 | 50357902U, // LWDSP_MM |
| 3230 | 50352381U, // LWE |
| 3231 | 50352381U, // LWE_MM |
| 3232 | 50357902U, // LWGP_MM |
| 3233 | 50354470U, // LWL |
| 3234 | 50354470U, // LWL64 |
| 3235 | 50352312U, // LWLE |
| 3236 | 50352312U, // LWLE_MM |
| 3237 | 50354470U, // LWL_MM |
| 3238 | 66059U, // LWM16_MM |
| 3239 | 66059U, // LWM16_MMR6 |
| 3240 | 65799U, // LWM32_MM |
| 3241 | 18499U, // LWPC |
| 3242 | 18499U, // LWPC_MMR6 |
| 3243 | 369121850U, // LWP_MM |
| 3244 | 50354976U, // LWR |
| 3245 | 50354976U, // LWR64 |
| 3246 | 50352351U, // LWRE |
| 3247 | 50352351U, // LWRE_MM |
| 3248 | 50354976U, // LWR_MM |
| 3249 | 50357902U, // LWSP_MM |
| 3250 | 18492U, // LWUPC |
| 3251 | 50356070U, // LWU_MM |
| 3252 | 3254806202U, // LWX |
| 3253 | 3254796466U, // LWXC1 |
| 3254 | 3254796466U, // LWXC1_MM |
| 3255 | 3254804017U, // LWXS_MM |
| 3256 | 3254806202U, // LWX_MM |
| 3257 | 50357902U, // LW_MM |
| 3258 | 50357902U, // LW_MMR6 |
| 3259 | 50356070U, // LWu |
| 3260 | 50349651U, // LbRxRyOffMemX16 |
| 3261 | 50355845U, // LbuRxRyOffMemX16 |
| 3262 | 50353427U, // LhRxRyOffMemX16 |
| 3263 | 50355923U, // LhuRxRyOffMemX16 |
| 3264 | 1610635144U, // LiRxImm16 |
| 3265 | 22398U, // LiRxImmAlignX16 |
| 3266 | 22408U, // LiRxImmX16 |
| 3267 | 26254U, // LwRxPcTcp16 |
| 3268 | 26254U, // LwRxPcTcpX16 |
| 3269 | 50357902U, // LwRxRyOffMemX16 |
| 3270 | 50357902U, // LwRxSpImmX16 |
| 3271 | 20523U, // MADD |
| 3272 | 570444383U, // MADDF_D |
| 3273 | 570444383U, // MADDF_D_MMR6 |
| 3274 | 570448851U, // MADDF_S |
| 3275 | 570448851U, // MADDF_S_MMR6 |
| 3276 | 570446441U, // MADDR_Q_H |
| 3277 | 570450552U, // MADDR_Q_W |
| 3278 | 24230U, // MADDU |
| 3279 | 536895142U, // MADDU_DSP |
| 3280 | 536895142U, // MADDU_DSP_MM |
| 3281 | 24230U, // MADDU_MM |
| 3282 | 570443251U, // MADDV_B |
| 3283 | 570445682U, // MADDV_D |
| 3284 | 570447040U, // MADDV_H |
| 3285 | 570451507U, // MADDV_W |
| 3286 | 536889690U, // MADD_D32 |
| 3287 | 536889690U, // MADD_D32_MM |
| 3288 | 536889690U, // MADD_D64 |
| 3289 | 536891435U, // MADD_DSP |
| 3290 | 536891435U, // MADD_DSP_MM |
| 3291 | 20523U, // MADD_MM |
| 3292 | 570446411U, // MADD_Q_H |
| 3293 | 570450522U, // MADD_Q_W |
| 3294 | 536894285U, // MADD_S |
| 3295 | 536894285U, // MADD_S_MM |
| 3296 | 536893555U, // MAQ_SA_W_PHL |
| 3297 | 536893555U, // MAQ_SA_W_PHL_MM |
| 3298 | 536894116U, // MAQ_SA_W_PHR |
| 3299 | 536894116U, // MAQ_SA_W_PHR_MM |
| 3300 | 536893583U, // MAQ_S_W_PHL |
| 3301 | 536893583U, // MAQ_S_W_PHL_MM |
| 3302 | 536894144U, // MAQ_S_W_PHR |
| 3303 | 536894144U, // MAQ_S_W_PHR_MM |
| 3304 | 536889631U, // MAXA_D |
| 3305 | 536889631U, // MAXA_D_MMR6 |
| 3306 | 536894258U, // MAXA_S |
| 3307 | 536894258U, // MAXA_S_MMR6 |
| 3308 | 536888488U, // MAXI_S_B |
| 3309 | 536890645U, // MAXI_S_D |
| 3310 | 536892194U, // MAXI_S_H |
| 3311 | 536896459U, // MAXI_S_W |
| 3312 | 536888703U, // MAXI_U_B |
| 3313 | 536891112U, // MAXI_U_D |
| 3314 | 536892482U, // MAXI_U_H |
| 3315 | 536896927U, // MAXI_U_W |
| 3316 | 536888069U, // MAX_A_B |
| 3317 | 536889607U, // MAX_A_D |
| 3318 | 536891706U, // MAX_A_H |
| 3319 | 536895525U, // MAX_A_W |
| 3320 | 536891353U, // MAX_D |
| 3321 | 536891353U, // MAX_D_MMR6 |
| 3322 | 536894851U, // MAX_S |
| 3323 | 536888576U, // MAX_S_B |
| 3324 | 536890765U, // MAX_S_D |
| 3325 | 536892313U, // MAX_S_H |
| 3326 | 536894851U, // MAX_S_MMR6 |
| 3327 | 536896640U, // MAX_S_W |
| 3328 | 536888791U, // MAX_U_B |
| 3329 | 536891232U, // MAX_U_D |
| 3330 | 536892580U, // MAX_U_H |
| 3331 | 536897047U, // MAX_U_W |
| 3332 | 536887298U, // MFC0 |
| 3333 | 536887298U, // MFC0_MMR6 |
| 3334 | 16489U, // MFC1 |
| 3335 | 16489U, // MFC1_D64 |
| 3336 | 16489U, // MFC1_MM |
| 3337 | 16489U, // MFC1_MMR6 |
| 3338 | 536887617U, // MFC2 |
| 3339 | 16705U, // MFC2_MMR6 |
| 3340 | 536887305U, // MFGC0 |
| 3341 | 536887305U, // MFGC0_MM |
| 3342 | 536887336U, // MFHC0_MMR6 |
| 3343 | 16495U, // MFHC1_D32 |
| 3344 | 16495U, // MFHC1_D32_MM |
| 3345 | 16495U, // MFHC1_D64 |
| 3346 | 16495U, // MFHC1_D64_MM |
| 3347 | 16711U, // MFHC2_MMR6 |
| 3348 | 536887312U, // MFHGC0 |
| 3349 | 536887312U, // MFHGC0_MM |
| 3350 | 546674U, // MFHI |
| 3351 | 541158U, // MFHI16_MM |
| 3352 | 546674U, // MFHI64 |
| 3353 | 22386U, // MFHI_DSP |
| 3354 | 22386U, // MFHI_DSP_MM |
| 3355 | 546674U, // MFHI_MM |
| 3356 | 547206U, // MFLO |
| 3357 | 541209U, // MFLO16_MM |
| 3358 | 547206U, // MFLO64 |
| 3359 | 22918U, // MFLO_DSP |
| 3360 | 22918U, // MFLO_DSP_MM |
| 3361 | 547206U, // MFLO_MM |
| 3362 | 536894214U, // MFTR |
| 3363 | 536889616U, // MINA_D |
| 3364 | 536889616U, // MINA_D_MMR6 |
| 3365 | 536894250U, // MINA_S |
| 3366 | 536894250U, // MINA_S_MMR6 |
| 3367 | 536888468U, // MINI_S_B |
| 3368 | 536890625U, // MINI_S_D |
| 3369 | 536892174U, // MINI_S_H |
| 3370 | 536896439U, // MINI_S_W |
| 3371 | 536888683U, // MINI_U_B |
| 3372 | 536891092U, // MINI_U_D |
| 3373 | 536892462U, // MINI_U_H |
| 3374 | 536896907U, // MINI_U_W |
| 3375 | 536888050U, // MIN_A_B |
| 3376 | 536889587U, // MIN_A_D |
| 3377 | 536891687U, // MIN_A_H |
| 3378 | 536895505U, // MIN_A_W |
| 3379 | 536890259U, // MIN_D |
| 3380 | 536890259U, // MIN_D_MMR6 |
| 3381 | 536894532U, // MIN_S |
| 3382 | 536888498U, // MIN_S_B |
| 3383 | 536890655U, // MIN_S_D |
| 3384 | 536892204U, // MIN_S_H |
| 3385 | 536894532U, // MIN_S_MMR6 |
| 3386 | 536896479U, // MIN_S_W |
| 3387 | 536888713U, // MIN_U_B |
| 3388 | 536891122U, // MIN_U_D |
| 3389 | 536892492U, // MIN_U_H |
| 3390 | 536896937U, // MIN_U_W |
| 3391 | 536891482U, // MOD |
| 3392 | 536889255U, // MODSUB |
| 3393 | 536889255U, // MODSUB_MM |
| 3394 | 536895150U, // MODU |
| 3395 | 536895150U, // MODU_MMR6 |
| 3396 | 536891482U, // MOD_MMR6 |
| 3397 | 536888431U, // MOD_S_B |
| 3398 | 536890588U, // MOD_S_D |
| 3399 | 536892137U, // MOD_S_H |
| 3400 | 536896402U, // MOD_S_W |
| 3401 | 536888646U, // MOD_U_B |
| 3402 | 536891055U, // MOD_U_D |
| 3403 | 536892425U, // MOD_U_H |
| 3404 | 536896870U, // MOD_U_W |
| 3405 | 20727U, // MOVE16_MM |
| 3406 | 16848U, // MOVE16_MMR6 |
| 3407 | 536893881U, // MOVEP_MM |
| 3408 | 536893881U, // MOVEP_MMR6 |
| 3409 | 24434U, // MOVE_V |
| 3410 | 536889976U, // MOVF_D32 |
| 3411 | 536889976U, // MOVF_D32_MM |
| 3412 | 536889976U, // MOVF_D64 |
| 3413 | 536891667U, // MOVF_I |
| 3414 | 536891667U, // MOVF_I64 |
| 3415 | 536891667U, // MOVF_I_MM |
| 3416 | 536894436U, // MOVF_S |
| 3417 | 536894436U, // MOVF_S_MM |
| 3418 | 536890311U, // MOVN_I64_D64 |
| 3419 | 536893818U, // MOVN_I64_I |
| 3420 | 536893818U, // MOVN_I64_I64 |
| 3421 | 536894568U, // MOVN_I64_S |
| 3422 | 536890311U, // MOVN_I_D32 |
| 3423 | 536890311U, // MOVN_I_D32_MM |
| 3424 | 536890311U, // MOVN_I_D64 |
| 3425 | 536893818U, // MOVN_I_I |
| 3426 | 536893818U, // MOVN_I_I64 |
| 3427 | 536893818U, // MOVN_I_MM |
| 3428 | 536894568U, // MOVN_I_S |
| 3429 | 536894568U, // MOVN_I_S_MM |
| 3430 | 536890983U, // MOVT_D32 |
| 3431 | 536890983U, // MOVT_D32_MM |
| 3432 | 536890983U, // MOVT_D64 |
| 3433 | 536895097U, // MOVT_I |
| 3434 | 536895097U, // MOVT_I64 |
| 3435 | 536895097U, // MOVT_I_MM |
| 3436 | 536894777U, // MOVT_S |
| 3437 | 536894777U, // MOVT_S_MM |
| 3438 | 536891393U, // MOVZ_I64_D64 |
| 3439 | 536897287U, // MOVZ_I64_I |
| 3440 | 536897287U, // MOVZ_I64_I64 |
| 3441 | 536894878U, // MOVZ_I64_S |
| 3442 | 536891393U, // MOVZ_I_D32 |
| 3443 | 536891393U, // MOVZ_I_D32_MM |
| 3444 | 536891393U, // MOVZ_I_D64 |
| 3445 | 536897287U, // MOVZ_I_I |
| 3446 | 536897287U, // MOVZ_I_I64 |
| 3447 | 536897287U, // MOVZ_I_MM |
| 3448 | 536894878U, // MOVZ_I_S |
| 3449 | 536894878U, // MOVZ_I_S_MM |
| 3450 | 18351U, // MSUB |
| 3451 | 570444374U, // MSUBF_D |
| 3452 | 570444374U, // MSUBF_D_MMR6 |
| 3453 | 570448842U, // MSUBF_S |
| 3454 | 570448842U, // MSUBF_S_MMR6 |
| 3455 | 570446430U, // MSUBR_Q_H |
| 3456 | 570450541U, // MSUBR_Q_W |
| 3457 | 24209U, // MSUBU |
| 3458 | 536895121U, // MSUBU_DSP |
| 3459 | 536895121U, // MSUBU_DSP_MM |
| 3460 | 24209U, // MSUBU_MM |
| 3461 | 570443242U, // MSUBV_B |
| 3462 | 570445673U, // MSUBV_D |
| 3463 | 570447031U, // MSUBV_H |
| 3464 | 570451498U, // MSUBV_W |
| 3465 | 536889648U, // MSUB_D32 |
| 3466 | 536889648U, // MSUB_D32_MM |
| 3467 | 536889648U, // MSUB_D64 |
| 3468 | 536889263U, // MSUB_DSP |
| 3469 | 536889263U, // MSUB_DSP_MM |
| 3470 | 18351U, // MSUB_MM |
| 3471 | 570446401U, // MSUB_Q_H |
| 3472 | 570450512U, // MSUB_Q_W |
| 3473 | 536894267U, // MSUB_S |
| 3474 | 536894267U, // MSUB_S_MM |
| 3475 | 2752561207U, // MTC0 |
| 3476 | 2752561207U, // MTC0_MMR6 |
| 3477 | 17875076U, // MTC1 |
| 3478 | 17875076U, // MTC1_D64 |
| 3479 | 17875076U, // MTC1_D64_MM |
| 3480 | 17875076U, // MTC1_MM |
| 3481 | 17875076U, // MTC1_MMR6 |
| 3482 | 2752561500U, // MTC2 |
| 3483 | 17875292U, // MTC2_MMR6 |
| 3484 | 2752561185U, // MTGC0 |
| 3485 | 2752561185U, // MTGC0_MM |
| 3486 | 2752561199U, // MTHC0_MMR6 |
| 3487 | 17924214U, // MTHC1_D32 |
| 3488 | 17924214U, // MTHC1_D32_MM |
| 3489 | 17924214U, // MTHC1_D64 |
| 3490 | 17924214U, // MTHC1_D64_MM |
| 3491 | 17875278U, // MTHC2_MMR6 |
| 3492 | 2752561176U, // MTHGC0 |
| 3493 | 2752561176U, // MTHGC0_MM |
| 3494 | 546680U, // MTHI |
| 3495 | 546680U, // MTHI64 |
| 3496 | 17880952U, // MTHI_DSP |
| 3497 | 17880952U, // MTHI_DSP_MM |
| 3498 | 546680U, // MTHI_MM |
| 3499 | 17881536U, // MTHLIP |
| 3500 | 17881536U, // MTHLIP_MM |
| 3501 | 547219U, // MTLO |
| 3502 | 547219U, // MTLO64 |
| 3503 | 17881491U, // MTLO_DSP |
| 3504 | 17881491U, // MTLO_DSP_MM |
| 3505 | 547219U, // MTLO_MM |
| 3506 | 540739U, // MTM0 |
| 3507 | 540864U, // MTM1 |
| 3508 | 541038U, // MTM2 |
| 3509 | 540745U, // MTP0 |
| 3510 | 540870U, // MTP1 |
| 3511 | 541044U, // MTP2 |
| 3512 | 68213523U, // MTTR |
| 3513 | 536893249U, // MUH |
| 3514 | 536895193U, // MUHU |
| 3515 | 536895193U, // MUHU_MMR6 |
| 3516 | 536893249U, // MUH_MMR6 |
| 3517 | 536893715U, // MUL |
| 3518 | 536893596U, // MULEQ_S_W_PHL |
| 3519 | 536893596U, // MULEQ_S_W_PHL_MM |
| 3520 | 536894157U, // MULEQ_S_W_PHR |
| 3521 | 536894157U, // MULEQ_S_W_PHR_MM |
| 3522 | 536893473U, // MULEU_S_PH_QBL |
| 3523 | 536893473U, // MULEU_S_PH_QBL_MM |
| 3524 | 536894059U, // MULEU_S_PH_QBR |
| 3525 | 536894059U, // MULEU_S_PH_QBR_MM |
| 3526 | 536893009U, // MULQ_RS_PH |
| 3527 | 536893009U, // MULQ_RS_PH_MM |
| 3528 | 536896659U, // MULQ_RS_W |
| 3529 | 536896659U, // MULQ_RS_W_MMR2 |
| 3530 | 536892953U, // MULQ_S_PH |
| 3531 | 536892953U, // MULQ_S_PH_MMR2 |
| 3532 | 536896518U, // MULQ_S_W |
| 3533 | 536896518U, // MULQ_S_W_MMR2 |
| 3534 | 536894976U, // MULR_PS64 |
| 3535 | 536892020U, // MULR_Q_H |
| 3536 | 536896131U, // MULR_Q_W |
| 3537 | 536893155U, // MULSAQ_S_W_PH |
| 3538 | 536893155U, // MULSAQ_S_W_PH_MM |
| 3539 | 536893130U, // MULSA_W_PH |
| 3540 | 536893130U, // MULSA_W_PH_MMR2 |
| 3541 | 24157U, // MULT |
| 3542 | 536895313U, // MULTU_DSP |
| 3543 | 536895313U, // MULTU_DSP_MM |
| 3544 | 536895069U, // MULT_DSP |
| 3545 | 536895069U, // MULT_DSP_MM |
| 3546 | 24157U, // MULT_MM |
| 3547 | 24401U, // MULTu |
| 3548 | 24401U, // MULTu_MM |
| 3549 | 536895230U, // MULU |
| 3550 | 536895230U, // MULU_MMR6 |
| 3551 | 536888846U, // MULV_B |
| 3552 | 536891285U, // MULV_D |
| 3553 | 536892635U, // MULV_H |
| 3554 | 536897110U, // MULV_W |
| 3555 | 536893715U, // MUL_MM |
| 3556 | 536893715U, // MUL_MMR6 |
| 3557 | 536892826U, // MUL_PH |
| 3558 | 536892826U, // MUL_PH_MMR2 |
| 3559 | 536891989U, // MUL_Q_H |
| 3560 | 536896100U, // MUL_Q_W |
| 3561 | 536893715U, // MUL_R6 |
| 3562 | 536892921U, // MUL_S_PH |
| 3563 | 536892921U, // MUL_S_PH_MMR2 |
| 3564 | 546674U, // Mfhi16 |
| 3565 | 547206U, // Mflo16 |
| 3566 | 20727U, // Move32R16 |
| 3567 | 20727U, // MoveR3216 |
| 3568 | 10587U, // NAL |
| 3569 | 17173U, // NLOC_B |
| 3570 | 18753U, // NLOC_D |
| 3571 | 20810U, // NLOC_H |
| 3572 | 24646U, // NLOC_W |
| 3573 | 17181U, // NLZC_B |
| 3574 | 18761U, // NLZC_D |
| 3575 | 20818U, // NLZC_H |
| 3576 | 24654U, // NLZC_W |
| 3577 | 536889698U, // NMADD_D32 |
| 3578 | 536889698U, // NMADD_D32_MM |
| 3579 | 536889698U, // NMADD_D64 |
| 3580 | 536894284U, // NMADD_S |
| 3581 | 536894284U, // NMADD_S_MM |
| 3582 | 536889656U, // NMSUB_D32 |
| 3583 | 536889656U, // NMSUB_D32_MM |
| 3584 | 536889656U, // NMSUB_D64 |
| 3585 | 536894266U, // NMSUB_S |
| 3586 | 536894266U, // NMSUB_S_MM |
| 3587 | 536894182U, // NOR |
| 3588 | 536894182U, // NOR64 |
| 3589 | 536888254U, // NORI_B |
| 3590 | 536894182U, // NOR_MM |
| 3591 | 536894182U, // NOR_MMR6 |
| 3592 | 536895362U, // NOR_V |
| 3593 | 16960U, // NOT16_MM |
| 3594 | 16960U, // NOT16_MMR6 |
| 3595 | 20761U, // NegRxRy16 |
| 3596 | 24173U, // NotRxRy16 |
| 3597 | 536894183U, // OR |
| 3598 | 20021809U, // OR16_MM |
| 3599 | 20021809U, // OR16_MMR6 |
| 3600 | 536894183U, // OR64 |
| 3601 | 536888255U, // ORI_B |
| 3602 | 536893348U, // ORI_MMR6 |
| 3603 | 536894183U, // OR_MM |
| 3604 | 536894183U, // OR_MMR6 |
| 3605 | 536895363U, // OR_V |
| 3606 | 536893348U, // ORi |
| 3607 | 536893348U, // ORi64 |
| 3608 | 536893348U, // ORi_MM |
| 3609 | 33577703U, // OrRxRxRy16 |
| 3610 | 536892815U, // PACKRL_PH |
| 3611 | 536892815U, // PACKRL_PH_MM |
| 3612 | 10551U, // PAUSE |
| 3613 | 10551U, // PAUSE_MM |
| 3614 | 10551U, // PAUSE_MMR6 |
| 3615 | 536888828U, // PCKEV_B |
| 3616 | 536891259U, // PCKEV_D |
| 3617 | 536892617U, // PCKEV_H |
| 3618 | 536897084U, // PCKEV_W |
| 3619 | 536888108U, // PCKOD_B |
| 3620 | 536889714U, // PCKOD_D |
| 3621 | 536891745U, // PCKOD_H |
| 3622 | 536895607U, // PCKOD_W |
| 3623 | 17700U, // PCNT_B |
| 3624 | 20019U, // PCNT_D |
| 3625 | 21437U, // PCNT_H |
| 3626 | 25842U, // PCNT_W |
| 3627 | 536892779U, // PICK_PH |
| 3628 | 536892779U, // PICK_PH_MM |
| 3629 | 536888987U, // PICK_QB |
| 3630 | 536888987U, // PICK_QB_MM |
| 3631 | 536894943U, // PLL_PS64 |
| 3632 | 536894985U, // PLU_PS64 |
| 3633 | 22990U, // POP |
| 3634 | 22592U, // PRECEQU_PH_QBL |
| 3635 | 17046U, // PRECEQU_PH_QBLA |
| 3636 | 17046U, // PRECEQU_PH_QBLA_MM |
| 3637 | 22592U, // PRECEQU_PH_QBL_MM |
| 3638 | 23178U, // PRECEQU_PH_QBR |
| 3639 | 17084U, // PRECEQU_PH_QBRA |
| 3640 | 17084U, // PRECEQU_PH_QBRA_MM |
| 3641 | 23178U, // PRECEQU_PH_QBR_MM |
| 3642 | 22657U, // PRECEQ_W_PHL |
| 3643 | 22657U, // PRECEQ_W_PHL_MM |
| 3644 | 23218U, // PRECEQ_W_PHR |
| 3645 | 23218U, // PRECEQ_W_PHR_MM |
| 3646 | 22577U, // PRECEU_PH_QBL |
| 3647 | 17030U, // PRECEU_PH_QBLA |
| 3648 | 17030U, // PRECEU_PH_QBLA_MM |
| 3649 | 22577U, // PRECEU_PH_QBL_MM |
| 3650 | 23163U, // PRECEU_PH_QBR |
| 3651 | 17068U, // PRECEU_PH_QBRA |
| 3652 | 17068U, // PRECEU_PH_QBRA_MM |
| 3653 | 23163U, // PRECEU_PH_QBR_MM |
| 3654 | 536892731U, // PRECRQU_S_QB_PH |
| 3655 | 536892731U, // PRECRQU_S_QB_PH_MM |
| 3656 | 536895750U, // PRECRQ_PH_W |
| 3657 | 536895750U, // PRECRQ_PH_W_MM |
| 3658 | 536892704U, // PRECRQ_QB_PH |
| 3659 | 536892704U, // PRECRQ_QB_PH_MM |
| 3660 | 536895781U, // PRECRQ_RS_PH_W |
| 3661 | 536895781U, // PRECRQ_RS_PH_W_MM |
| 3662 | 536892718U, // PRECR_QB_PH |
| 3663 | 536892718U, // PRECR_QB_PH_MMR2 |
| 3664 | 536895734U, // PRECR_SRA_PH_W |
| 3665 | 536895734U, // PRECR_SRA_PH_W_MMR2 |
| 3666 | 536895763U, // PRECR_SRA_R_PH_W |
| 3667 | 536895763U, // PRECR_SRA_R_PH_W_MMR2 |
| 3668 | 5394701U, // PREF |
| 3669 | 5394554U, // PREFE |
| 3670 | 5394554U, // PREFE_MM |
| 3671 | 389179042U, // PREFX_MM |
| 3672 | 5394701U, // PREF_MM |
| 3673 | 5394701U, // PREF_MMR6 |
| 3674 | 5394701U, // PREF_R6 |
| 3675 | 536891464U, // PREPEND |
| 3676 | 536891464U, // PREPEND_MMR2 |
| 3677 | 536894959U, // PUL_PS64 |
| 3678 | 536894993U, // PUU_PS64 |
| 3679 | 18327U, // RADDU_W_QB |
| 3680 | 18327U, // RADDU_W_QB_MM |
| 3681 | 184572415U, // RDDSP |
| 3682 | 402676223U, // RDDSP_MM |
| 3683 | 536894233U, // RDHWR |
| 3684 | 536894233U, // RDHWR64 |
| 3685 | 536894233U, // RDHWR_MM |
| 3686 | 536894233U, // RDHWR_MMR6 |
| 3687 | 23286U, // RDPGPR_MMR6 |
| 3688 | 19415U, // RECIP_D32 |
| 3689 | 19415U, // RECIP_D32_MM |
| 3690 | 19415U, // RECIP_D64 |
| 3691 | 19415U, // RECIP_D64_MM |
| 3692 | 23664U, // RECIP_S |
| 3693 | 23664U, // RECIP_S_MM |
| 3694 | 22158U, // REPLV_PH |
| 3695 | 22158U, // REPLV_PH_MM |
| 3696 | 18307U, // REPLV_QB |
| 3697 | 18307U, // REPLV_QB_MM |
| 3698 | 21885U, // REPL_PH |
| 3699 | 21885U, // REPL_PH_MM |
| 3700 | 419448493U, // REPL_QB |
| 3701 | 419448493U, // REPL_QB_MM |
| 3702 | 20028U, // RINT_D |
| 3703 | 20028U, // RINT_D_MMR6 |
| 3704 | 23848U, // RINT_S |
| 3705 | 23848U, // RINT_S_MMR6 |
| 3706 | 536894221U, // ROTR |
| 3707 | 536895464U, // ROTRV |
| 3708 | 536895464U, // ROTRV_MM |
| 3709 | 536894221U, // ROTR_MM |
| 3710 | 19224U, // ROUND_L_D64 |
| 3711 | 19224U, // ROUND_L_D_MMR6 |
| 3712 | 23556U, // ROUND_L_S |
| 3713 | 23556U, // ROUND_L_S_MMR6 |
| 3714 | 20399U, // ROUND_W_D32 |
| 3715 | 20399U, // ROUND_W_D64 |
| 3716 | 20399U, // ROUND_W_D_MMR6 |
| 3717 | 20399U, // ROUND_W_MM |
| 3718 | 23898U, // ROUND_W_S |
| 3719 | 23898U, // ROUND_W_S_MM |
| 3720 | 23898U, // ROUND_W_S_MMR6 |
| 3721 | 20056U, // RSQRT_D32 |
| 3722 | 20056U, // RSQRT_D32_MM |
| 3723 | 20056U, // RSQRT_D64 |
| 3724 | 20056U, // RSQRT_D64_MM |
| 3725 | 23856U, // RSQRT_S |
| 3726 | 23856U, // RSQRT_S_MM |
| 3727 | 0U, // Restore16 |
| 3728 | 0U, // RestoreX16 |
| 3729 | 8405633U, // SAA |
| 3730 | 8409105U, // SAAD |
| 3731 | 536888537U, // SAT_S_B |
| 3732 | 536890704U, // SAT_S_D |
| 3733 | 536892263U, // SAT_S_H |
| 3734 | 536896568U, // SAT_S_W |
| 3735 | 536888764U, // SAT_U_B |
| 3736 | 536891183U, // SAT_U_D |
| 3737 | 536892553U, // SAT_U_H |
| 3738 | 536896998U, // SAT_U_W |
| 3739 | 50349987U, // SB |
| 3740 | 50348452U, // SB16_MM |
| 3741 | 50348452U, // SB16_MMR6 |
| 3742 | 50349987U, // SB64 |
| 3743 | 50352232U, // SBE |
| 3744 | 50352232U, // SBE_MM |
| 3745 | 50349987U, // SB_MM |
| 3746 | 50349987U, // SB_MMR6 |
| 3747 | 8964190U, // SC |
| 3748 | 8964190U, // SC64 |
| 3749 | 8964190U, // SC64_R6 |
| 3750 | 8966176U, // SCD |
| 3751 | 8966176U, // SCD_R6 |
| 3752 | 8966253U, // SCE |
| 3753 | 8966253U, // SCE_MM |
| 3754 | 8964190U, // SC_MM |
| 3755 | 8964190U, // SC_MMR6 |
| 3756 | 8964190U, // SC_R6 |
| 3757 | 50352223U, // SD |
| 3758 | 219562U, // SDBBP |
| 3759 | 131617U, // SDBBP16_MM |
| 3760 | 131617U, // SDBBP16_MMR6 |
| 3761 | 645546U, // SDBBP_MM |
| 3762 | 219562U, // SDBBP_MMR6 |
| 3763 | 219562U, // SDBBP_R6 |
| 3764 | 50348124U, // SDC1 |
| 3765 | 50348124U, // SDC164 |
| 3766 | 50348124U, // SDC1_D64_MMR6 |
| 3767 | 50348124U, // SDC1_MM_D32 |
| 3768 | 50348124U, // SDC1_MM_D64 |
| 3769 | 50348340U, // SDC2 |
| 3770 | 50348340U, // SDC2_MMR6 |
| 3771 | 50348340U, // SDC2_R6 |
| 3772 | 50348425U, // SDC3 |
| 3773 | 26408U, // SDIV |
| 3774 | 26408U, // SDIV_MM |
| 3775 | 50354261U, // SDL |
| 3776 | 50354847U, // SDR |
| 3777 | 3254796445U, // SDXC1 |
| 3778 | 3254796445U, // SDXC164 |
| 3779 | 17972U, // SEB |
| 3780 | 17972U, // SEB64 |
| 3781 | 17972U, // SEB_MM |
| 3782 | 21773U, // SEH |
| 3783 | 21773U, // SEH64 |
| 3784 | 21773U, // SEH_MM |
| 3785 | 536897260U, // SELEQZ |
| 3786 | 536897260U, // SELEQZ64 |
| 3787 | 536891383U, // SELEQZ_D |
| 3788 | 536891383U, // SELEQZ_D_MMR6 |
| 3789 | 536897260U, // SELEQZ_MMR6 |
| 3790 | 536894868U, // SELEQZ_S |
| 3791 | 536894868U, // SELEQZ_S_MMR6 |
| 3792 | 536897233U, // SELNEZ |
| 3793 | 536897233U, // SELNEZ64 |
| 3794 | 536891366U, // SELNEZ_D |
| 3795 | 536891366U, // SELNEZ_D_MMR6 |
| 3796 | 536897233U, // SELNEZ_MMR6 |
| 3797 | 536894858U, // SELNEZ_S |
| 3798 | 536894858U, // SELNEZ_S_MMR6 |
| 3799 | 570444609U, // SEL_D |
| 3800 | 570444609U, // SEL_D_MMR6 |
| 3801 | 570448941U, // SEL_S |
| 3802 | 570448941U, // SEL_S_MMR6 |
| 3803 | 536894025U, // SEQ |
| 3804 | 536893335U, // SEQi |
| 3805 | 50353980U, // SH |
| 3806 | 50348504U, // SH16_MM |
| 3807 | 50348504U, // SH16_MMR6 |
| 3808 | 50353980U, // SH64 |
| 3809 | 50352284U, // SHE |
| 3810 | 50352284U, // SHE_MM |
| 3811 | 536888136U, // SHF_B |
| 3812 | 536891773U, // SHF_H |
| 3813 | 536895719U, // SHF_W |
| 3814 | 22924U, // SHILO |
| 3815 | 24527U, // SHILOV |
| 3816 | 24527U, // SHILOV_MM |
| 3817 | 22924U, // SHILO_MM |
| 3818 | 536893060U, // SHLLV_PH |
| 3819 | 536893060U, // SHLLV_PH_MM |
| 3820 | 536889209U, // SHLLV_QB |
| 3821 | 536889209U, // SHLLV_QB_MM |
| 3822 | 536892997U, // SHLLV_S_PH |
| 3823 | 536892997U, // SHLLV_S_PH_MM |
| 3824 | 536896629U, // SHLLV_S_W |
| 3825 | 536896629U, // SHLLV_S_W_MM |
| 3826 | 536892788U, // SHLL_PH |
| 3827 | 536892788U, // SHLL_PH_MM |
| 3828 | 536888996U, // SHLL_QB |
| 3829 | 536888996U, // SHLL_QB_MM |
| 3830 | 536892910U, // SHLL_S_PH |
| 3831 | 536892910U, // SHLL_S_PH_MM |
| 3832 | 536896469U, // SHLL_S_W |
| 3833 | 536896469U, // SHLL_S_W_MM |
| 3834 | 536893050U, // SHRAV_PH |
| 3835 | 536893050U, // SHRAV_PH_MM |
| 3836 | 536889199U, // SHRAV_QB |
| 3837 | 536889199U, // SHRAV_QB_MMR2 |
| 3838 | 536892898U, // SHRAV_R_PH |
| 3839 | 536892898U, // SHRAV_R_PH_MM |
| 3840 | 536889097U, // SHRAV_R_QB |
| 3841 | 536889097U, // SHRAV_R_QB_MMR2 |
| 3842 | 536896224U, // SHRAV_R_W |
| 3843 | 536896224U, // SHRAV_R_W_MM |
| 3844 | 536892695U, // SHRA_PH |
| 3845 | 536892695U, // SHRA_PH_MM |
| 3846 | 536888919U, // SHRA_QB |
| 3847 | 536888919U, // SHRA_QB_MMR2 |
| 3848 | 536892863U, // SHRA_R_PH |
| 3849 | 536892863U, // SHRA_R_PH_MM |
| 3850 | 536889062U, // SHRA_R_QB |
| 3851 | 536889062U, // SHRA_R_QB_MMR2 |
| 3852 | 536896182U, // SHRA_R_W |
| 3853 | 536896182U, // SHRA_R_W_MM |
| 3854 | 536893080U, // SHRLV_PH |
| 3855 | 536893080U, // SHRLV_PH_MMR2 |
| 3856 | 536889229U, // SHRLV_QB |
| 3857 | 536889229U, // SHRLV_QB_MM |
| 3858 | 536892806U, // SHRL_PH |
| 3859 | 536892806U, // SHRL_PH_MMR2 |
| 3860 | 536889014U, // SHRL_QB |
| 3861 | 536889014U, // SHRL_QB_MM |
| 3862 | 50353980U, // SH_MM |
| 3863 | 50353980U, // SH_MMR6 |
| 3864 | 233633U, // SIGRIE |
| 3865 | 233633U, // SIGRIE_MMR6 |
| 3866 | 1107313503U, // SLDI_B |
| 3867 | 1107315344U, // SLDI_D |
| 3868 | 1107317140U, // SLDI_H |
| 3869 | 1107321167U, // SLDI_W |
| 3870 | 1107313445U, // SLD_B |
| 3871 | 1107315051U, // SLD_D |
| 3872 | 1107317082U, // SLD_H |
| 3873 | 1107320944U, // SLD_W |
| 3874 | 536893648U, // SLL |
| 3875 | 536887805U, // SLL16_MM |
| 3876 | 536887805U, // SLL16_MMR6 |
| 3877 | 536893648U, // SLL64_32 |
| 3878 | 536893648U, // SLL64_64 |
| 3879 | 536888193U, // SLLI_B |
| 3880 | 536890017U, // SLLI_D |
| 3881 | 536891813U, // SLLI_H |
| 3882 | 536895840U, // SLLI_W |
| 3883 | 536895426U, // SLLV |
| 3884 | 536895426U, // SLLV_MM |
| 3885 | 536888342U, // SLL_B |
| 3886 | 536890201U, // SLL_D |
| 3887 | 536891929U, // SLL_H |
| 3888 | 536893648U, // SLL_MM |
| 3889 | 536893648U, // SLL_MMR6 |
| 3890 | 536895982U, // SLL_W |
| 3891 | 536895058U, // SLT |
| 3892 | 536895058U, // SLT64 |
| 3893 | 536895058U, // SLT_MM |
| 3894 | 536893359U, // SLTi |
| 3895 | 536893359U, // SLTi64 |
| 3896 | 536893359U, // SLTi_MM |
| 3897 | 536895214U, // SLTiu |
| 3898 | 536895214U, // SLTiu64 |
| 3899 | 536895214U, // SLTiu_MM |
| 3900 | 536895300U, // SLTu |
| 3901 | 536895300U, // SLTu64 |
| 3902 | 536895300U, // SLTu_MM |
| 3903 | 536891593U, // SNE |
| 3904 | 536893280U, // SNEi |
| 3905 | 1073759192U, // SPLATI_B |
| 3906 | 1073761000U, // SPLATI_D |
| 3907 | 1073762796U, // SPLATI_H |
| 3908 | 1073766823U, // SPLATI_W |
| 3909 | 1073759507U, // SPLAT_B |
| 3910 | 1073761713U, // SPLAT_D |
| 3911 | 1073763244U, // SPLAT_H |
| 3912 | 1073767615U, // SPLAT_W |
| 3913 | 536888014U, // SRA |
| 3914 | 536888151U, // SRAI_B |
| 3915 | 536889992U, // SRAI_D |
| 3916 | 536891788U, // SRAI_H |
| 3917 | 536895815U, // SRAI_W |
| 3918 | 536888227U, // SRARI_B |
| 3919 | 536890051U, // SRARI_D |
| 3920 | 536891847U, // SRARI_H |
| 3921 | 536895874U, // SRARI_W |
| 3922 | 536888380U, // SRAR_B |
| 3923 | 536890440U, // SRAR_D |
| 3924 | 536892044U, // SRAR_H |
| 3925 | 536896246U, // SRAR_W |
| 3926 | 536895405U, // SRAV |
| 3927 | 536895405U, // SRAV_MM |
| 3928 | 536888078U, // SRA_B |
| 3929 | 536889624U, // SRA_D |
| 3930 | 536891715U, // SRA_H |
| 3931 | 536888014U, // SRA_MM |
| 3932 | 536895534U, // SRA_W |
| 3933 | 536893676U, // SRL |
| 3934 | 536887812U, // SRL16_MM |
| 3935 | 536887812U, // SRL16_MMR6 |
| 3936 | 536888201U, // SRLI_B |
| 3937 | 536890025U, // SRLI_D |
| 3938 | 536891821U, // SRLI_H |
| 3939 | 536895848U, // SRLI_W |
| 3940 | 536888245U, // SRLRI_B |
| 3941 | 536890069U, // SRLRI_D |
| 3942 | 536891865U, // SRLRI_H |
| 3943 | 536895892U, // SRLRI_W |
| 3944 | 536888396U, // SRLR_B |
| 3945 | 536890456U, // SRLR_D |
| 3946 | 536892060U, // SRLR_H |
| 3947 | 536896262U, // SRLR_W |
| 3948 | 536895433U, // SRLV |
| 3949 | 536895433U, // SRLV_MM |
| 3950 | 536888349U, // SRL_B |
| 3951 | 536890226U, // SRL_D |
| 3952 | 536891936U, // SRL_H |
| 3953 | 536893676U, // SRL_MM |
| 3954 | 536896007U, // SRL_W |
| 3955 | 10620U, // SSNOP |
| 3956 | 10620U, // SSNOP_MM |
| 3957 | 10620U, // SSNOP_MMR6 |
| 3958 | 50349366U, // ST_B |
| 3959 | 50351713U, // ST_D |
| 3960 | 50353103U, // ST_H |
| 3961 | 50357536U, // ST_W |
| 3962 | 536889258U, // SUB |
| 3963 | 536892759U, // SUBQH_PH |
| 3964 | 536892759U, // SUBQH_PH_MMR2 |
| 3965 | 536892874U, // SUBQH_R_PH |
| 3966 | 536892874U, // SUBQH_R_PH_MMR2 |
| 3967 | 536896192U, // SUBQH_R_W |
| 3968 | 536896192U, // SUBQH_R_W_MMR2 |
| 3969 | 536895797U, // SUBQH_W |
| 3970 | 536895797U, // SUBQH_W_MMR2 |
| 3971 | 536892834U, // SUBQ_PH |
| 3972 | 536892834U, // SUBQ_PH_MM |
| 3973 | 536892931U, // SUBQ_S_PH |
| 3974 | 536892931U, // SUBQ_S_PH_MM |
| 3975 | 536896498U, // SUBQ_S_W |
| 3976 | 536896498U, // SUBQ_S_W_MM |
| 3977 | 536888752U, // SUBSUS_U_B |
| 3978 | 536891171U, // SUBSUS_U_D |
| 3979 | 536892541U, // SUBSUS_U_H |
| 3980 | 536896986U, // SUBSUS_U_W |
| 3981 | 536888555U, // SUBSUU_S_B |
| 3982 | 536890744U, // SUBSUU_S_D |
| 3983 | 536892281U, // SUBSUU_S_H |
| 3984 | 536896608U, // SUBSUU_S_W |
| 3985 | 536888517U, // SUBS_S_B |
| 3986 | 536890684U, // SUBS_S_D |
| 3987 | 536892243U, // SUBS_S_H |
| 3988 | 536896548U, // SUBS_S_W |
| 3989 | 536888732U, // SUBS_U_B |
| 3990 | 536891151U, // SUBS_U_D |
| 3991 | 536892521U, // SUBS_U_H |
| 3992 | 536896966U, // SUBS_U_W |
| 3993 | 536887886U, // SUBU16_MM |
| 3994 | 536887886U, // SUBU16_MMR6 |
| 3995 | 536888967U, // SUBUH_QB |
| 3996 | 536888967U, // SUBUH_QB_MMR2 |
| 3997 | 536889073U, // SUBUH_R_QB |
| 3998 | 536889073U, // SUBUH_R_QB_MMR2 |
| 3999 | 536895115U, // SUBU_MMR6 |
| 4000 | 536893032U, // SUBU_PH |
| 4001 | 536893032U, // SUBU_PH_MMR2 |
| 4002 | 536889181U, // SUBU_QB |
| 4003 | 536889181U, // SUBU_QB_MM |
| 4004 | 536892975U, // SUBU_S_PH |
| 4005 | 536892975U, // SUBU_S_PH_MMR2 |
| 4006 | 536889120U, // SUBU_S_QB |
| 4007 | 536889120U, // SUBU_S_QB_MM |
| 4008 | 536888299U, // SUBVI_B |
| 4009 | 536890107U, // SUBVI_D |
| 4010 | 536891903U, // SUBVI_H |
| 4011 | 536895930U, // SUBVI_W |
| 4012 | 536888811U, // SUBV_B |
| 4013 | 536891242U, // SUBV_D |
| 4014 | 536892600U, // SUBV_H |
| 4015 | 536897067U, // SUBV_W |
| 4016 | 536889258U, // SUB_MM |
| 4017 | 536889258U, // SUB_MMR6 |
| 4018 | 536895115U, // SUBu |
| 4019 | 536895115U, // SUBu_MM |
| 4020 | 3254796459U, // SUXC1 |
| 4021 | 3254796459U, // SUXC164 |
| 4022 | 3254796459U, // SUXC1_MM |
| 4023 | 50357918U, // SW |
| 4024 | 50348651U, // SW16_MM |
| 4025 | 50348651U, // SW16_MMR6 |
| 4026 | 50357918U, // SW64 |
| 4027 | 50348176U, // SWC1 |
| 4028 | 50348176U, // SWC1_MM |
| 4029 | 50348392U, // SWC2 |
| 4030 | 50348392U, // SWC2_MMR6 |
| 4031 | 50348392U, // SWC2_R6 |
| 4032 | 50348437U, // SWC3 |
| 4033 | 50357918U, // SWDSP |
| 4034 | 50357918U, // SWDSP_MM |
| 4035 | 50352386U, // SWE |
| 4036 | 50352386U, // SWE_MM |
| 4037 | 50354475U, // SWL |
| 4038 | 50354475U, // SWL64 |
| 4039 | 50352318U, // SWLE |
| 4040 | 50352318U, // SWLE_MM |
| 4041 | 50354475U, // SWL_MM |
| 4042 | 66066U, // SWM16_MM |
| 4043 | 66066U, // SWM16_MMR6 |
| 4044 | 65806U, // SWM32_MM |
| 4045 | 369121855U, // SWP_MM |
| 4046 | 50354981U, // SWR |
| 4047 | 50354981U, // SWR64 |
| 4048 | 50352357U, // SWRE |
| 4049 | 50352357U, // SWRE_MM |
| 4050 | 50354981U, // SWR_MM |
| 4051 | 50354724U, // SWSP_MM |
| 4052 | 50357918U, // SWSP_MMR6 |
| 4053 | 3254796473U, // SWXC1 |
| 4054 | 3254796473U, // SWXC1_MM |
| 4055 | 50357918U, // SW_MM |
| 4056 | 50357918U, // SW_MMR6 |
| 4057 | 255866U, // SYNC |
| 4058 | 268102U, // SYNCI |
| 4059 | 268102U, // SYNCI_MM |
| 4060 | 268102U, // SYNCI_MMR6 |
| 4061 | 255866U, // SYNC_MM |
| 4062 | 247832U, // SYNC_MMR6 |
| 4063 | 219316U, // SYSCALL |
| 4064 | 645300U, // SYSCALL_MM |
| 4065 | 0U, // Save16 |
| 4066 | 0U, // SaveX16 |
| 4067 | 50349987U, // SbRxRyOffMemX16 |
| 4068 | 550669U, // SebRx16 |
| 4069 | 550675U, // SehRx16 |
| 4070 | 50353980U, // ShRxRyOffMemX16 |
| 4071 | 536893648U, // SllX16 |
| 4072 | 33578946U, // SllvRxRy16 |
| 4073 | 24146U, // SltRxRy16 |
| 4074 | 1610635183U, // SltiRxImm16 |
| 4075 | 22447U, // SltiRxImmX16 |
| 4076 | 1610637038U, // SltiuRxImm16 |
| 4077 | 24302U, // SltiuRxImmX16 |
| 4078 | 24388U, // SltuRxRy16 |
| 4079 | 536888014U, // SraX16 |
| 4080 | 33578925U, // SravRxRy16 |
| 4081 | 536893676U, // SrlX16 |
| 4082 | 33578953U, // SrlvRxRy16 |
| 4083 | 536895115U, // SubuRxRyRz16 |
| 4084 | 50357918U, // SwRxRyOffMemX16 |
| 4085 | 50357918U, // SwRxSpImmX16 |
| 4086 | 536894030U, // TEQ |
| 4087 | 22429U, // TEQI |
| 4088 | 22429U, // TEQI_MM |
| 4089 | 536894030U, // TEQ_MM |
| 4090 | 536891531U, // TGE |
| 4091 | 22362U, // TGEI |
| 4092 | 24295U, // TGEIU |
| 4093 | 24295U, // TGEIU_MM |
| 4094 | 22362U, // TGEI_MM |
| 4095 | 536895168U, // TGEU |
| 4096 | 536895168U, // TGEU_MM |
| 4097 | 536891531U, // TGE_MM |
| 4098 | 10668U, // TLBGINV |
| 4099 | 10565U, // TLBGINVF |
| 4100 | 10565U, // TLBGINVF_MM |
| 4101 | 10668U, // TLBGINV_MM |
| 4102 | 10614U, // TLBGP |
| 4103 | 10614U, // TLBGP_MM |
| 4104 | 10631U, // TLBGR |
| 4105 | 10631U, // TLBGR_MM |
| 4106 | 10580U, // TLBGWI |
| 4107 | 10580U, // TLBGWI_MM |
| 4108 | 10643U, // TLBGWR |
| 4109 | 10643U, // TLBGWR_MM |
| 4110 | 10661U, // TLBINV |
| 4111 | 10557U, // TLBINVF |
| 4112 | 10557U, // TLBINVF_MMR6 |
| 4113 | 10661U, // TLBINV_MMR6 |
| 4114 | 10609U, // TLBP |
| 4115 | 10609U, // TLBP_MM |
| 4116 | 10626U, // TLBR |
| 4117 | 10626U, // TLBR_MM |
| 4118 | 10574U, // TLBWI |
| 4119 | 10574U, // TLBWI_MM |
| 4120 | 10637U, // TLBWR |
| 4121 | 10637U, // TLBWR_MM |
| 4122 | 536895063U, // TLT |
| 4123 | 22453U, // TLTI |
| 4124 | 24309U, // TLTIU_MM |
| 4125 | 22453U, // TLTI_MM |
| 4126 | 536895306U, // TLTU |
| 4127 | 536895306U, // TLTU_MM |
| 4128 | 536895063U, // TLT_MM |
| 4129 | 536891598U, // TNE |
| 4130 | 22374U, // TNEI |
| 4131 | 22374U, // TNEI_MM |
| 4132 | 536891598U, // TNE_MM |
| 4133 | 19213U, // TRUNC_L_D64 |
| 4134 | 19213U, // TRUNC_L_D_MMR6 |
| 4135 | 23545U, // TRUNC_L_S |
| 4136 | 23545U, // TRUNC_L_S_MMR6 |
| 4137 | 20388U, // TRUNC_W_D32 |
| 4138 | 20388U, // TRUNC_W_D64 |
| 4139 | 20388U, // TRUNC_W_D_MMR6 |
| 4140 | 20388U, // TRUNC_W_MM |
| 4141 | 23887U, // TRUNC_W_S |
| 4142 | 23887U, // TRUNC_W_S_MM |
| 4143 | 23887U, // TRUNC_W_S_MMR6 |
| 4144 | 24309U, // TTLTIU |
| 4145 | 26394U, // UDIV |
| 4146 | 26394U, // UDIV_MM |
| 4147 | 536895228U, // V3MULU |
| 4148 | 536887357U, // VMM0 |
| 4149 | 536895243U, // VMULU |
| 4150 | 570442567U, // VSHF_B |
| 4151 | 570444392U, // VSHF_D |
| 4152 | 570446204U, // VSHF_H |
| 4153 | 570450150U, // VSHF_W |
| 4154 | 10656U, // WAIT |
| 4155 | 646727U, // WAIT_MM |
| 4156 | 646727U, // WAIT_MMR6 |
| 4157 | 184572422U, // WRDSP |
| 4158 | 402676230U, // WRDSP_MM |
| 4159 | 23294U, // WRPGPR_MMR6 |
| 4160 | 21758U, // WSBH |
| 4161 | 21758U, // WSBH_MM |
| 4162 | 21758U, // WSBH_MMR6 |
| 4163 | 536894193U, // XOR |
| 4164 | 20021808U, // XOR16_MM |
| 4165 | 20021808U, // XOR16_MMR6 |
| 4166 | 536894193U, // XOR64 |
| 4167 | 536888262U, // XORI_B |
| 4168 | 536893347U, // XORI_MMR6 |
| 4169 | 536894193U, // XOR_MM |
| 4170 | 536894193U, // XOR_MMR6 |
| 4171 | 536895369U, // XOR_V |
| 4172 | 536893347U, // XORi |
| 4173 | 536893347U, // XORi64 |
| 4174 | 536893347U, // XORi_MM |
| 4175 | 33577713U, // XorRxRxRy16 |
| 4176 | 20535U, // YIELD |
| 4177 | }; |
| 4178 | |
| 4179 | static const uint16_t OpInfo1[] = { |
| 4180 | 0U, // PHI |
| 4181 | 0U, // INLINEASM |
| 4182 | 0U, // INLINEASM_BR |
| 4183 | 0U, // CFI_INSTRUCTION |
| 4184 | 0U, // EH_LABEL |
| 4185 | 0U, // GC_LABEL |
| 4186 | 0U, // ANNOTATION_LABEL |
| 4187 | 0U, // KILL |
| 4188 | 0U, // EXTRACT_SUBREG |
| 4189 | 0U, // INSERT_SUBREG |
| 4190 | 0U, // IMPLICIT_DEF |
| 4191 | 0U, // INIT_UNDEF |
| 4192 | 0U, // SUBREG_TO_REG |
| 4193 | 0U, // COPY_TO_REGCLASS |
| 4194 | 0U, // DBG_VALUE |
| 4195 | 0U, // DBG_VALUE_LIST |
| 4196 | 0U, // DBG_INSTR_REF |
| 4197 | 0U, // DBG_PHI |
| 4198 | 0U, // DBG_LABEL |
| 4199 | 0U, // REG_SEQUENCE |
| 4200 | 0U, // COPY |
| 4201 | 0U, // BUNDLE |
| 4202 | 0U, // LIFETIME_START |
| 4203 | 0U, // LIFETIME_END |
| 4204 | 0U, // PSEUDO_PROBE |
| 4205 | 0U, // ARITH_FENCE |
| 4206 | 0U, // STACKMAP |
| 4207 | 0U, // FENTRY_CALL |
| 4208 | 0U, // PATCHPOINT |
| 4209 | 0U, // LOAD_STACK_GUARD |
| 4210 | 0U, // PREALLOCATED_SETUP |
| 4211 | 0U, // PREALLOCATED_ARG |
| 4212 | 0U, // STATEPOINT |
| 4213 | 0U, // LOCAL_ESCAPE |
| 4214 | 0U, // FAULTING_OP |
| 4215 | 0U, // PATCHABLE_OP |
| 4216 | 0U, // PATCHABLE_FUNCTION_ENTER |
| 4217 | 0U, // PATCHABLE_RET |
| 4218 | 0U, // PATCHABLE_FUNCTION_EXIT |
| 4219 | 0U, // PATCHABLE_TAIL_CALL |
| 4220 | 0U, // PATCHABLE_EVENT_CALL |
| 4221 | 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 4222 | 0U, // ICALL_BRANCH_FUNNEL |
| 4223 | 0U, // FAKE_USE |
| 4224 | 0U, // MEMBARRIER |
| 4225 | 0U, // JUMP_TABLE_DEBUG_INFO |
| 4226 | 0U, // CONVERGENCECTRL_ENTRY |
| 4227 | 0U, // CONVERGENCECTRL_ANCHOR |
| 4228 | 0U, // CONVERGENCECTRL_LOOP |
| 4229 | 0U, // CONVERGENCECTRL_GLUE |
| 4230 | 0U, // G_ASSERT_SEXT |
| 4231 | 0U, // G_ASSERT_ZEXT |
| 4232 | 0U, // G_ASSERT_ALIGN |
| 4233 | 0U, // G_ADD |
| 4234 | 0U, // G_SUB |
| 4235 | 0U, // G_MUL |
| 4236 | 0U, // G_SDIV |
| 4237 | 0U, // G_UDIV |
| 4238 | 0U, // G_SREM |
| 4239 | 0U, // G_UREM |
| 4240 | 0U, // G_SDIVREM |
| 4241 | 0U, // G_UDIVREM |
| 4242 | 0U, // G_AND |
| 4243 | 0U, // G_OR |
| 4244 | 0U, // G_XOR |
| 4245 | 0U, // G_ABDS |
| 4246 | 0U, // G_ABDU |
| 4247 | 0U, // G_IMPLICIT_DEF |
| 4248 | 0U, // G_PHI |
| 4249 | 0U, // G_FRAME_INDEX |
| 4250 | 0U, // G_GLOBAL_VALUE |
| 4251 | 0U, // G_PTRAUTH_GLOBAL_VALUE |
| 4252 | 0U, // G_CONSTANT_POOL |
| 4253 | 0U, // G_EXTRACT |
| 4254 | 0U, // G_UNMERGE_VALUES |
| 4255 | 0U, // G_INSERT |
| 4256 | 0U, // G_MERGE_VALUES |
| 4257 | 0U, // G_BUILD_VECTOR |
| 4258 | 0U, // G_BUILD_VECTOR_TRUNC |
| 4259 | 0U, // G_CONCAT_VECTORS |
| 4260 | 0U, // G_PTRTOINT |
| 4261 | 0U, // G_INTTOPTR |
| 4262 | 0U, // G_BITCAST |
| 4263 | 0U, // G_FREEZE |
| 4264 | 0U, // G_CONSTANT_FOLD_BARRIER |
| 4265 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 4266 | 0U, // G_INTRINSIC_TRUNC |
| 4267 | 0U, // G_INTRINSIC_ROUND |
| 4268 | 0U, // G_INTRINSIC_LRINT |
| 4269 | 0U, // G_INTRINSIC_LLRINT |
| 4270 | 0U, // G_INTRINSIC_ROUNDEVEN |
| 4271 | 0U, // G_READCYCLECOUNTER |
| 4272 | 0U, // G_READSTEADYCOUNTER |
| 4273 | 0U, // G_LOAD |
| 4274 | 0U, // G_SEXTLOAD |
| 4275 | 0U, // G_ZEXTLOAD |
| 4276 | 0U, // G_INDEXED_LOAD |
| 4277 | 0U, // G_INDEXED_SEXTLOAD |
| 4278 | 0U, // G_INDEXED_ZEXTLOAD |
| 4279 | 0U, // G_STORE |
| 4280 | 0U, // G_INDEXED_STORE |
| 4281 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 4282 | 0U, // G_ATOMIC_CMPXCHG |
| 4283 | 0U, // G_ATOMICRMW_XCHG |
| 4284 | 0U, // G_ATOMICRMW_ADD |
| 4285 | 0U, // G_ATOMICRMW_SUB |
| 4286 | 0U, // G_ATOMICRMW_AND |
| 4287 | 0U, // G_ATOMICRMW_NAND |
| 4288 | 0U, // G_ATOMICRMW_OR |
| 4289 | 0U, // G_ATOMICRMW_XOR |
| 4290 | 0U, // G_ATOMICRMW_MAX |
| 4291 | 0U, // G_ATOMICRMW_MIN |
| 4292 | 0U, // G_ATOMICRMW_UMAX |
| 4293 | 0U, // G_ATOMICRMW_UMIN |
| 4294 | 0U, // G_ATOMICRMW_FADD |
| 4295 | 0U, // G_ATOMICRMW_FSUB |
| 4296 | 0U, // G_ATOMICRMW_FMAX |
| 4297 | 0U, // G_ATOMICRMW_FMIN |
| 4298 | 0U, // G_ATOMICRMW_FMAXIMUM |
| 4299 | 0U, // G_ATOMICRMW_FMINIMUM |
| 4300 | 0U, // G_ATOMICRMW_UINC_WRAP |
| 4301 | 0U, // G_ATOMICRMW_UDEC_WRAP |
| 4302 | 0U, // G_ATOMICRMW_USUB_COND |
| 4303 | 0U, // G_ATOMICRMW_USUB_SAT |
| 4304 | 0U, // G_FENCE |
| 4305 | 0U, // G_PREFETCH |
| 4306 | 0U, // G_BRCOND |
| 4307 | 0U, // G_BRINDIRECT |
| 4308 | 0U, // G_INVOKE_REGION_START |
| 4309 | 0U, // G_INTRINSIC |
| 4310 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 4311 | 0U, // G_INTRINSIC_CONVERGENT |
| 4312 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 4313 | 0U, // G_ANYEXT |
| 4314 | 0U, // G_TRUNC |
| 4315 | 0U, // G_CONSTANT |
| 4316 | 0U, // G_FCONSTANT |
| 4317 | 0U, // G_VASTART |
| 4318 | 0U, // G_VAARG |
| 4319 | 0U, // G_SEXT |
| 4320 | 0U, // G_SEXT_INREG |
| 4321 | 0U, // G_ZEXT |
| 4322 | 0U, // G_SHL |
| 4323 | 0U, // G_LSHR |
| 4324 | 0U, // G_ASHR |
| 4325 | 0U, // G_FSHL |
| 4326 | 0U, // G_FSHR |
| 4327 | 0U, // G_ROTR |
| 4328 | 0U, // G_ROTL |
| 4329 | 0U, // G_ICMP |
| 4330 | 0U, // G_FCMP |
| 4331 | 0U, // G_SCMP |
| 4332 | 0U, // G_UCMP |
| 4333 | 0U, // G_SELECT |
| 4334 | 0U, // G_UADDO |
| 4335 | 0U, // G_UADDE |
| 4336 | 0U, // G_USUBO |
| 4337 | 0U, // G_USUBE |
| 4338 | 0U, // G_SADDO |
| 4339 | 0U, // G_SADDE |
| 4340 | 0U, // G_SSUBO |
| 4341 | 0U, // G_SSUBE |
| 4342 | 0U, // G_UMULO |
| 4343 | 0U, // G_SMULO |
| 4344 | 0U, // G_UMULH |
| 4345 | 0U, // G_SMULH |
| 4346 | 0U, // G_UADDSAT |
| 4347 | 0U, // G_SADDSAT |
| 4348 | 0U, // G_USUBSAT |
| 4349 | 0U, // G_SSUBSAT |
| 4350 | 0U, // G_USHLSAT |
| 4351 | 0U, // G_SSHLSAT |
| 4352 | 0U, // G_SMULFIX |
| 4353 | 0U, // G_UMULFIX |
| 4354 | 0U, // G_SMULFIXSAT |
| 4355 | 0U, // G_UMULFIXSAT |
| 4356 | 0U, // G_SDIVFIX |
| 4357 | 0U, // G_UDIVFIX |
| 4358 | 0U, // G_SDIVFIXSAT |
| 4359 | 0U, // G_UDIVFIXSAT |
| 4360 | 0U, // G_FADD |
| 4361 | 0U, // G_FSUB |
| 4362 | 0U, // G_FMUL |
| 4363 | 0U, // G_FMA |
| 4364 | 0U, // G_FMAD |
| 4365 | 0U, // G_FDIV |
| 4366 | 0U, // G_FREM |
| 4367 | 0U, // G_FPOW |
| 4368 | 0U, // G_FPOWI |
| 4369 | 0U, // G_FEXP |
| 4370 | 0U, // G_FEXP2 |
| 4371 | 0U, // G_FEXP10 |
| 4372 | 0U, // G_FLOG |
| 4373 | 0U, // G_FLOG2 |
| 4374 | 0U, // G_FLOG10 |
| 4375 | 0U, // G_FLDEXP |
| 4376 | 0U, // G_FFREXP |
| 4377 | 0U, // G_FNEG |
| 4378 | 0U, // G_FPEXT |
| 4379 | 0U, // G_FPTRUNC |
| 4380 | 0U, // G_FPTOSI |
| 4381 | 0U, // G_FPTOUI |
| 4382 | 0U, // G_SITOFP |
| 4383 | 0U, // G_UITOFP |
| 4384 | 0U, // G_FPTOSI_SAT |
| 4385 | 0U, // G_FPTOUI_SAT |
| 4386 | 0U, // G_FABS |
| 4387 | 0U, // G_FCOPYSIGN |
| 4388 | 0U, // G_IS_FPCLASS |
| 4389 | 0U, // G_FCANONICALIZE |
| 4390 | 0U, // G_FMINNUM |
| 4391 | 0U, // G_FMAXNUM |
| 4392 | 0U, // G_FMINNUM_IEEE |
| 4393 | 0U, // G_FMAXNUM_IEEE |
| 4394 | 0U, // G_FMINIMUM |
| 4395 | 0U, // G_FMAXIMUM |
| 4396 | 0U, // G_FMINIMUMNUM |
| 4397 | 0U, // G_FMAXIMUMNUM |
| 4398 | 0U, // G_GET_FPENV |
| 4399 | 0U, // G_SET_FPENV |
| 4400 | 0U, // G_RESET_FPENV |
| 4401 | 0U, // G_GET_FPMODE |
| 4402 | 0U, // G_SET_FPMODE |
| 4403 | 0U, // G_RESET_FPMODE |
| 4404 | 0U, // G_PTR_ADD |
| 4405 | 0U, // G_PTRMASK |
| 4406 | 0U, // G_SMIN |
| 4407 | 0U, // G_SMAX |
| 4408 | 0U, // G_UMIN |
| 4409 | 0U, // G_UMAX |
| 4410 | 0U, // G_ABS |
| 4411 | 0U, // G_LROUND |
| 4412 | 0U, // G_LLROUND |
| 4413 | 0U, // G_BR |
| 4414 | 0U, // G_BRJT |
| 4415 | 0U, // G_VSCALE |
| 4416 | 0U, // G_INSERT_SUBVECTOR |
| 4417 | 0U, // G_EXTRACT_SUBVECTOR |
| 4418 | 0U, // G_INSERT_VECTOR_ELT |
| 4419 | 0U, // G_EXTRACT_VECTOR_ELT |
| 4420 | 0U, // G_SHUFFLE_VECTOR |
| 4421 | 0U, // G_SPLAT_VECTOR |
| 4422 | 0U, // G_STEP_VECTOR |
| 4423 | 0U, // G_VECTOR_COMPRESS |
| 4424 | 0U, // G_CTTZ |
| 4425 | 0U, // G_CTTZ_ZERO_UNDEF |
| 4426 | 0U, // G_CTLZ |
| 4427 | 0U, // G_CTLZ_ZERO_UNDEF |
| 4428 | 0U, // G_CTPOP |
| 4429 | 0U, // G_BSWAP |
| 4430 | 0U, // G_BITREVERSE |
| 4431 | 0U, // G_FCEIL |
| 4432 | 0U, // G_FCOS |
| 4433 | 0U, // G_FSIN |
| 4434 | 0U, // G_FSINCOS |
| 4435 | 0U, // G_FTAN |
| 4436 | 0U, // G_FACOS |
| 4437 | 0U, // G_FASIN |
| 4438 | 0U, // G_FATAN |
| 4439 | 0U, // G_FATAN2 |
| 4440 | 0U, // G_FCOSH |
| 4441 | 0U, // G_FSINH |
| 4442 | 0U, // G_FTANH |
| 4443 | 0U, // G_FSQRT |
| 4444 | 0U, // G_FFLOOR |
| 4445 | 0U, // G_FRINT |
| 4446 | 0U, // G_FNEARBYINT |
| 4447 | 0U, // G_ADDRSPACE_CAST |
| 4448 | 0U, // G_BLOCK_ADDR |
| 4449 | 0U, // G_JUMP_TABLE |
| 4450 | 0U, // G_DYN_STACKALLOC |
| 4451 | 0U, // G_STACKSAVE |
| 4452 | 0U, // G_STACKRESTORE |
| 4453 | 0U, // G_STRICT_FADD |
| 4454 | 0U, // G_STRICT_FSUB |
| 4455 | 0U, // G_STRICT_FMUL |
| 4456 | 0U, // G_STRICT_FDIV |
| 4457 | 0U, // G_STRICT_FREM |
| 4458 | 0U, // G_STRICT_FMA |
| 4459 | 0U, // G_STRICT_FSQRT |
| 4460 | 0U, // G_STRICT_FLDEXP |
| 4461 | 0U, // G_READ_REGISTER |
| 4462 | 0U, // G_WRITE_REGISTER |
| 4463 | 0U, // G_MEMCPY |
| 4464 | 0U, // G_MEMCPY_INLINE |
| 4465 | 0U, // G_MEMMOVE |
| 4466 | 0U, // G_MEMSET |
| 4467 | 0U, // G_BZERO |
| 4468 | 0U, // G_TRAP |
| 4469 | 0U, // G_DEBUGTRAP |
| 4470 | 0U, // G_UBSANTRAP |
| 4471 | 0U, // G_VECREDUCE_SEQ_FADD |
| 4472 | 0U, // G_VECREDUCE_SEQ_FMUL |
| 4473 | 0U, // G_VECREDUCE_FADD |
| 4474 | 0U, // G_VECREDUCE_FMUL |
| 4475 | 0U, // G_VECREDUCE_FMAX |
| 4476 | 0U, // G_VECREDUCE_FMIN |
| 4477 | 0U, // G_VECREDUCE_FMAXIMUM |
| 4478 | 0U, // G_VECREDUCE_FMINIMUM |
| 4479 | 0U, // G_VECREDUCE_ADD |
| 4480 | 0U, // G_VECREDUCE_MUL |
| 4481 | 0U, // G_VECREDUCE_AND |
| 4482 | 0U, // G_VECREDUCE_OR |
| 4483 | 0U, // G_VECREDUCE_XOR |
| 4484 | 0U, // G_VECREDUCE_SMAX |
| 4485 | 0U, // G_VECREDUCE_SMIN |
| 4486 | 0U, // G_VECREDUCE_UMAX |
| 4487 | 0U, // G_VECREDUCE_UMIN |
| 4488 | 0U, // G_SBFX |
| 4489 | 0U, // G_UBFX |
| 4490 | 0U, // ABSMacro |
| 4491 | 0U, // ADJCALLSTACKDOWN |
| 4492 | 0U, // ADJCALLSTACKUP |
| 4493 | 0U, // AND_V_D_PSEUDO |
| 4494 | 0U, // AND_V_H_PSEUDO |
| 4495 | 0U, // AND_V_W_PSEUDO |
| 4496 | 0U, // ATOMIC_CMP_SWAP_I16 |
| 4497 | 0U, // ATOMIC_CMP_SWAP_I16_POSTRA |
| 4498 | 0U, // ATOMIC_CMP_SWAP_I32 |
| 4499 | 0U, // ATOMIC_CMP_SWAP_I32_POSTRA |
| 4500 | 0U, // ATOMIC_CMP_SWAP_I64 |
| 4501 | 0U, // ATOMIC_CMP_SWAP_I64_POSTRA |
| 4502 | 0U, // ATOMIC_CMP_SWAP_I8 |
| 4503 | 0U, // ATOMIC_CMP_SWAP_I8_POSTRA |
| 4504 | 0U, // ATOMIC_LOAD_ADD_I16 |
| 4505 | 0U, // ATOMIC_LOAD_ADD_I16_POSTRA |
| 4506 | 0U, // ATOMIC_LOAD_ADD_I32 |
| 4507 | 0U, // ATOMIC_LOAD_ADD_I32_POSTRA |
| 4508 | 0U, // ATOMIC_LOAD_ADD_I64 |
| 4509 | 0U, // ATOMIC_LOAD_ADD_I64_POSTRA |
| 4510 | 0U, // ATOMIC_LOAD_ADD_I8 |
| 4511 | 0U, // ATOMIC_LOAD_ADD_I8_POSTRA |
| 4512 | 0U, // ATOMIC_LOAD_AND_I16 |
| 4513 | 0U, // ATOMIC_LOAD_AND_I16_POSTRA |
| 4514 | 0U, // ATOMIC_LOAD_AND_I32 |
| 4515 | 0U, // ATOMIC_LOAD_AND_I32_POSTRA |
| 4516 | 0U, // ATOMIC_LOAD_AND_I64 |
| 4517 | 0U, // ATOMIC_LOAD_AND_I64_POSTRA |
| 4518 | 0U, // ATOMIC_LOAD_AND_I8 |
| 4519 | 0U, // ATOMIC_LOAD_AND_I8_POSTRA |
| 4520 | 0U, // ATOMIC_LOAD_MAX_I16 |
| 4521 | 0U, // ATOMIC_LOAD_MAX_I16_POSTRA |
| 4522 | 0U, // ATOMIC_LOAD_MAX_I32 |
| 4523 | 0U, // ATOMIC_LOAD_MAX_I32_POSTRA |
| 4524 | 0U, // ATOMIC_LOAD_MAX_I64 |
| 4525 | 0U, // ATOMIC_LOAD_MAX_I64_POSTRA |
| 4526 | 0U, // ATOMIC_LOAD_MAX_I8 |
| 4527 | 0U, // ATOMIC_LOAD_MAX_I8_POSTRA |
| 4528 | 0U, // ATOMIC_LOAD_MIN_I16 |
| 4529 | 0U, // ATOMIC_LOAD_MIN_I16_POSTRA |
| 4530 | 0U, // ATOMIC_LOAD_MIN_I32 |
| 4531 | 0U, // ATOMIC_LOAD_MIN_I32_POSTRA |
| 4532 | 0U, // ATOMIC_LOAD_MIN_I64 |
| 4533 | 0U, // ATOMIC_LOAD_MIN_I64_POSTRA |
| 4534 | 0U, // ATOMIC_LOAD_MIN_I8 |
| 4535 | 0U, // ATOMIC_LOAD_MIN_I8_POSTRA |
| 4536 | 0U, // ATOMIC_LOAD_NAND_I16 |
| 4537 | 0U, // ATOMIC_LOAD_NAND_I16_POSTRA |
| 4538 | 0U, // ATOMIC_LOAD_NAND_I32 |
| 4539 | 0U, // ATOMIC_LOAD_NAND_I32_POSTRA |
| 4540 | 0U, // ATOMIC_LOAD_NAND_I64 |
| 4541 | 0U, // ATOMIC_LOAD_NAND_I64_POSTRA |
| 4542 | 0U, // ATOMIC_LOAD_NAND_I8 |
| 4543 | 0U, // ATOMIC_LOAD_NAND_I8_POSTRA |
| 4544 | 0U, // ATOMIC_LOAD_OR_I16 |
| 4545 | 0U, // ATOMIC_LOAD_OR_I16_POSTRA |
| 4546 | 0U, // ATOMIC_LOAD_OR_I32 |
| 4547 | 0U, // ATOMIC_LOAD_OR_I32_POSTRA |
| 4548 | 0U, // ATOMIC_LOAD_OR_I64 |
| 4549 | 0U, // ATOMIC_LOAD_OR_I64_POSTRA |
| 4550 | 0U, // ATOMIC_LOAD_OR_I8 |
| 4551 | 0U, // ATOMIC_LOAD_OR_I8_POSTRA |
| 4552 | 0U, // ATOMIC_LOAD_SUB_I16 |
| 4553 | 0U, // ATOMIC_LOAD_SUB_I16_POSTRA |
| 4554 | 0U, // ATOMIC_LOAD_SUB_I32 |
| 4555 | 0U, // ATOMIC_LOAD_SUB_I32_POSTRA |
| 4556 | 0U, // ATOMIC_LOAD_SUB_I64 |
| 4557 | 0U, // ATOMIC_LOAD_SUB_I64_POSTRA |
| 4558 | 0U, // ATOMIC_LOAD_SUB_I8 |
| 4559 | 0U, // ATOMIC_LOAD_SUB_I8_POSTRA |
| 4560 | 0U, // ATOMIC_LOAD_UMAX_I16 |
| 4561 | 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA |
| 4562 | 0U, // ATOMIC_LOAD_UMAX_I32 |
| 4563 | 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA |
| 4564 | 0U, // ATOMIC_LOAD_UMAX_I64 |
| 4565 | 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA |
| 4566 | 0U, // ATOMIC_LOAD_UMAX_I8 |
| 4567 | 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA |
| 4568 | 0U, // ATOMIC_LOAD_UMIN_I16 |
| 4569 | 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA |
| 4570 | 0U, // ATOMIC_LOAD_UMIN_I32 |
| 4571 | 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA |
| 4572 | 0U, // ATOMIC_LOAD_UMIN_I64 |
| 4573 | 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA |
| 4574 | 0U, // ATOMIC_LOAD_UMIN_I8 |
| 4575 | 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA |
| 4576 | 0U, // ATOMIC_LOAD_XOR_I16 |
| 4577 | 0U, // ATOMIC_LOAD_XOR_I16_POSTRA |
| 4578 | 0U, // ATOMIC_LOAD_XOR_I32 |
| 4579 | 0U, // ATOMIC_LOAD_XOR_I32_POSTRA |
| 4580 | 0U, // ATOMIC_LOAD_XOR_I64 |
| 4581 | 0U, // ATOMIC_LOAD_XOR_I64_POSTRA |
| 4582 | 0U, // ATOMIC_LOAD_XOR_I8 |
| 4583 | 0U, // ATOMIC_LOAD_XOR_I8_POSTRA |
| 4584 | 0U, // ATOMIC_SWAP_I16 |
| 4585 | 0U, // ATOMIC_SWAP_I16_POSTRA |
| 4586 | 0U, // ATOMIC_SWAP_I32 |
| 4587 | 0U, // ATOMIC_SWAP_I32_POSTRA |
| 4588 | 0U, // ATOMIC_SWAP_I64 |
| 4589 | 0U, // ATOMIC_SWAP_I64_POSTRA |
| 4590 | 0U, // ATOMIC_SWAP_I8 |
| 4591 | 0U, // ATOMIC_SWAP_I8_POSTRA |
| 4592 | 0U, // B |
| 4593 | 0U, // BAL_BR |
| 4594 | 0U, // BAL_BR_MM |
| 4595 | 0U, // BEQLImmMacro |
| 4596 | 0U, // BGE |
| 4597 | 0U, // BGEImmMacro |
| 4598 | 0U, // BGEL |
| 4599 | 0U, // BGELImmMacro |
| 4600 | 0U, // BGEU |
| 4601 | 0U, // BGEUImmMacro |
| 4602 | 0U, // BGEUL |
| 4603 | 0U, // BGEULImmMacro |
| 4604 | 0U, // BGT |
| 4605 | 0U, // BGTImmMacro |
| 4606 | 0U, // BGTL |
| 4607 | 0U, // BGTLImmMacro |
| 4608 | 0U, // BGTU |
| 4609 | 0U, // BGTUImmMacro |
| 4610 | 0U, // BGTUL |
| 4611 | 0U, // BGTULImmMacro |
| 4612 | 0U, // BLE |
| 4613 | 0U, // BLEImmMacro |
| 4614 | 0U, // BLEL |
| 4615 | 0U, // BLELImmMacro |
| 4616 | 0U, // BLEU |
| 4617 | 0U, // BLEUImmMacro |
| 4618 | 0U, // BLEUL |
| 4619 | 0U, // BLEULImmMacro |
| 4620 | 0U, // BLT |
| 4621 | 0U, // BLTImmMacro |
| 4622 | 0U, // BLTL |
| 4623 | 0U, // BLTLImmMacro |
| 4624 | 0U, // BLTU |
| 4625 | 0U, // BLTUImmMacro |
| 4626 | 0U, // BLTUL |
| 4627 | 0U, // BLTULImmMacro |
| 4628 | 0U, // BNELImmMacro |
| 4629 | 0U, // BPOSGE32_PSEUDO |
| 4630 | 0U, // BSEL_D_PSEUDO |
| 4631 | 0U, // BSEL_FD_PSEUDO |
| 4632 | 0U, // BSEL_FW_PSEUDO |
| 4633 | 0U, // BSEL_H_PSEUDO |
| 4634 | 0U, // BSEL_W_PSEUDO |
| 4635 | 0U, // B_MM |
| 4636 | 0U, // B_MMR6_Pseudo |
| 4637 | 0U, // B_MM_Pseudo |
| 4638 | 0U, // BeqImm |
| 4639 | 0U, // BneImm |
| 4640 | 0U, // BteqzT8CmpX16 |
| 4641 | 0U, // BteqzT8CmpiX16 |
| 4642 | 0U, // BteqzT8SltX16 |
| 4643 | 0U, // BteqzT8SltiX16 |
| 4644 | 0U, // BteqzT8SltiuX16 |
| 4645 | 0U, // BteqzT8SltuX16 |
| 4646 | 0U, // BtnezT8CmpX16 |
| 4647 | 0U, // BtnezT8CmpiX16 |
| 4648 | 0U, // BtnezT8SltX16 |
| 4649 | 0U, // BtnezT8SltiX16 |
| 4650 | 0U, // BtnezT8SltiuX16 |
| 4651 | 0U, // BtnezT8SltuX16 |
| 4652 | 0U, // BuildPairF64 |
| 4653 | 0U, // BuildPairF64_64 |
| 4654 | 0U, // CFTC1 |
| 4655 | 0U, // CONSTPOOL_ENTRY |
| 4656 | 0U, // COPY_FD_PSEUDO |
| 4657 | 0U, // COPY_FW_PSEUDO |
| 4658 | 0U, // CTTC1 |
| 4659 | 0U, // Constant32 |
| 4660 | 4U, // DMULImmMacro |
| 4661 | 4U, // DMULMacro |
| 4662 | 4U, // DMULOMacro |
| 4663 | 4U, // DMULOUMacro |
| 4664 | 4U, // DROL |
| 4665 | 4U, // DROLImm |
| 4666 | 4U, // DROR |
| 4667 | 4U, // DRORImm |
| 4668 | 4U, // DSDivIMacro |
| 4669 | 4U, // DSDivMacro |
| 4670 | 4U, // DSRemIMacro |
| 4671 | 4U, // DSRemMacro |
| 4672 | 4U, // DUDivIMacro |
| 4673 | 4U, // DUDivMacro |
| 4674 | 4U, // DURemIMacro |
| 4675 | 4U, // DURemMacro |
| 4676 | 0U, // ERet |
| 4677 | 0U, // ExtractElementF64 |
| 4678 | 0U, // ExtractElementF64_64 |
| 4679 | 0U, // FABS_D |
| 4680 | 0U, // FABS_W |
| 4681 | 0U, // FEXP2_D_1_PSEUDO |
| 4682 | 0U, // FEXP2_W_1_PSEUDO |
| 4683 | 0U, // FILL_FD_PSEUDO |
| 4684 | 0U, // FILL_FW_PSEUDO |
| 4685 | 0U, // GotPrologue16 |
| 4686 | 0U, // INSERT_B_VIDX64_PSEUDO |
| 4687 | 0U, // INSERT_B_VIDX_PSEUDO |
| 4688 | 0U, // INSERT_D_VIDX64_PSEUDO |
| 4689 | 0U, // INSERT_D_VIDX_PSEUDO |
| 4690 | 0U, // INSERT_FD_PSEUDO |
| 4691 | 0U, // INSERT_FD_VIDX64_PSEUDO |
| 4692 | 0U, // INSERT_FD_VIDX_PSEUDO |
| 4693 | 0U, // INSERT_FW_PSEUDO |
| 4694 | 0U, // INSERT_FW_VIDX64_PSEUDO |
| 4695 | 0U, // INSERT_FW_VIDX_PSEUDO |
| 4696 | 0U, // INSERT_H_VIDX64_PSEUDO |
| 4697 | 0U, // INSERT_H_VIDX_PSEUDO |
| 4698 | 0U, // INSERT_W_VIDX64_PSEUDO |
| 4699 | 0U, // INSERT_W_VIDX_PSEUDO |
| 4700 | 0U, // JALR64Pseudo |
| 4701 | 0U, // JALRHB64Pseudo |
| 4702 | 0U, // JALRHBPseudo |
| 4703 | 0U, // JALRPseudo |
| 4704 | 0U, // JAL_MMR6 |
| 4705 | 0U, // JalOneReg |
| 4706 | 0U, // JalTwoReg |
| 4707 | 0U, // LDMacro |
| 4708 | 0U, // LDR_D |
| 4709 | 0U, // LDR_W |
| 4710 | 0U, // LD_F16 |
| 4711 | 0U, // LOAD_ACC128 |
| 4712 | 0U, // LOAD_ACC64 |
| 4713 | 0U, // LOAD_ACC64DSP |
| 4714 | 0U, // LOAD_CCOND_DSP |
| 4715 | 0U, // LONG_BRANCH_ADDiu |
| 4716 | 0U, // LONG_BRANCH_ADDiu2Op |
| 4717 | 0U, // LONG_BRANCH_DADDiu |
| 4718 | 0U, // LONG_BRANCH_DADDiu2Op |
| 4719 | 0U, // LONG_BRANCH_LUi |
| 4720 | 0U, // LONG_BRANCH_LUi2Op |
| 4721 | 0U, // LONG_BRANCH_LUi2Op_64 |
| 4722 | 0U, // LWM_MM |
| 4723 | 0U, // LoadAddrImm32 |
| 4724 | 0U, // LoadAddrImm64 |
| 4725 | 0U, // LoadAddrReg32 |
| 4726 | 0U, // LoadAddrReg64 |
| 4727 | 0U, // LoadImm32 |
| 4728 | 0U, // LoadImm64 |
| 4729 | 0U, // LoadImmDoubleFGR |
| 4730 | 0U, // LoadImmDoubleFGR_32 |
| 4731 | 0U, // LoadImmDoubleGPR |
| 4732 | 0U, // LoadImmSingleFGR |
| 4733 | 0U, // LoadImmSingleGPR |
| 4734 | 0U, // LwConstant32 |
| 4735 | 0U, // MFTACX |
| 4736 | 8U, // MFTC0 |
| 4737 | 0U, // MFTC1 |
| 4738 | 0U, // MFTDSP |
| 4739 | 0U, // MFTGPR |
| 4740 | 0U, // MFTHC1 |
| 4741 | 0U, // MFTHI |
| 4742 | 0U, // MFTLO |
| 4743 | 0U, // MIPSeh_return32 |
| 4744 | 0U, // MIPSeh_return64 |
| 4745 | 0U, // MSA_FP_EXTEND_D_PSEUDO |
| 4746 | 0U, // MSA_FP_EXTEND_W_PSEUDO |
| 4747 | 0U, // MSA_FP_ROUND_D_PSEUDO |
| 4748 | 0U, // MSA_FP_ROUND_W_PSEUDO |
| 4749 | 0U, // MTTACX |
| 4750 | 0U, // MTTC0 |
| 4751 | 0U, // MTTC1 |
| 4752 | 0U, // MTTDSP |
| 4753 | 0U, // MTTGPR |
| 4754 | 0U, // MTTHC1 |
| 4755 | 0U, // MTTHI |
| 4756 | 0U, // MTTLO |
| 4757 | 4U, // MULImmMacro |
| 4758 | 4U, // MULOMacro |
| 4759 | 4U, // MULOUMacro |
| 4760 | 0U, // MultRxRy16 |
| 4761 | 0U, // MultRxRyRz16 |
| 4762 | 0U, // MultuRxRy16 |
| 4763 | 0U, // MultuRxRyRz16 |
| 4764 | 0U, // NOP |
| 4765 | 4U, // NORImm |
| 4766 | 4U, // NORImm64 |
| 4767 | 0U, // NOR_V_D_PSEUDO |
| 4768 | 0U, // NOR_V_H_PSEUDO |
| 4769 | 0U, // NOR_V_W_PSEUDO |
| 4770 | 0U, // OR_V_D_PSEUDO |
| 4771 | 0U, // OR_V_H_PSEUDO |
| 4772 | 0U, // OR_V_W_PSEUDO |
| 4773 | 0U, // PseudoCMPU_EQ_QB |
| 4774 | 0U, // PseudoCMPU_LE_QB |
| 4775 | 0U, // PseudoCMPU_LT_QB |
| 4776 | 0U, // PseudoCMP_EQ_PH |
| 4777 | 0U, // PseudoCMP_LE_PH |
| 4778 | 0U, // PseudoCMP_LT_PH |
| 4779 | 0U, // PseudoCVT_D32_W |
| 4780 | 0U, // PseudoCVT_D64_L |
| 4781 | 0U, // PseudoCVT_D64_W |
| 4782 | 0U, // PseudoCVT_S_L |
| 4783 | 0U, // PseudoCVT_S_W |
| 4784 | 0U, // PseudoDMULT |
| 4785 | 0U, // PseudoDMULTu |
| 4786 | 0U, // PseudoDSDIV |
| 4787 | 0U, // PseudoDUDIV |
| 4788 | 0U, // PseudoD_SELECT_I |
| 4789 | 0U, // PseudoD_SELECT_I64 |
| 4790 | 0U, // PseudoIndirectBranch |
| 4791 | 0U, // PseudoIndirectBranch64 |
| 4792 | 0U, // PseudoIndirectBranch64R6 |
| 4793 | 0U, // PseudoIndirectBranchR6 |
| 4794 | 0U, // PseudoIndirectBranch_MM |
| 4795 | 0U, // PseudoIndirectBranch_MMR6 |
| 4796 | 0U, // PseudoIndirectHazardBranch |
| 4797 | 0U, // PseudoIndirectHazardBranch64 |
| 4798 | 0U, // PseudoIndrectHazardBranch64R6 |
| 4799 | 0U, // PseudoIndrectHazardBranchR6 |
| 4800 | 0U, // PseudoMADD |
| 4801 | 0U, // PseudoMADDU |
| 4802 | 0U, // PseudoMADDU_MM |
| 4803 | 0U, // PseudoMADD_MM |
| 4804 | 0U, // PseudoMFHI |
| 4805 | 0U, // PseudoMFHI64 |
| 4806 | 0U, // PseudoMFHI_MM |
| 4807 | 0U, // PseudoMFLO |
| 4808 | 0U, // PseudoMFLO64 |
| 4809 | 0U, // PseudoMFLO_MM |
| 4810 | 0U, // PseudoMSUB |
| 4811 | 0U, // PseudoMSUBU |
| 4812 | 0U, // PseudoMSUBU_MM |
| 4813 | 0U, // PseudoMSUB_MM |
| 4814 | 0U, // PseudoMTLOHI |
| 4815 | 0U, // PseudoMTLOHI64 |
| 4816 | 0U, // PseudoMTLOHI_DSP |
| 4817 | 0U, // PseudoMTLOHI_MM |
| 4818 | 0U, // PseudoMULT |
| 4819 | 0U, // PseudoMULT_MM |
| 4820 | 0U, // PseudoMULTu |
| 4821 | 0U, // PseudoMULTu_MM |
| 4822 | 0U, // PseudoPICK_PH |
| 4823 | 0U, // PseudoPICK_QB |
| 4824 | 0U, // PseudoReturn |
| 4825 | 0U, // PseudoReturn64 |
| 4826 | 0U, // PseudoSDIV |
| 4827 | 0U, // PseudoSELECTFP_F_D32 |
| 4828 | 0U, // PseudoSELECTFP_F_D64 |
| 4829 | 0U, // PseudoSELECTFP_F_I |
| 4830 | 0U, // PseudoSELECTFP_F_I64 |
| 4831 | 0U, // PseudoSELECTFP_F_S |
| 4832 | 0U, // PseudoSELECTFP_T_D32 |
| 4833 | 0U, // PseudoSELECTFP_T_D64 |
| 4834 | 0U, // PseudoSELECTFP_T_I |
| 4835 | 0U, // PseudoSELECTFP_T_I64 |
| 4836 | 0U, // PseudoSELECTFP_T_S |
| 4837 | 0U, // PseudoSELECT_D32 |
| 4838 | 0U, // PseudoSELECT_D64 |
| 4839 | 0U, // PseudoSELECT_I |
| 4840 | 0U, // PseudoSELECT_I64 |
| 4841 | 0U, // PseudoSELECT_S |
| 4842 | 4U, // PseudoTRUNC_W_D |
| 4843 | 4U, // PseudoTRUNC_W_D32 |
| 4844 | 4U, // PseudoTRUNC_W_S |
| 4845 | 0U, // PseudoUDIV |
| 4846 | 4U, // ROL |
| 4847 | 4U, // ROLImm |
| 4848 | 4U, // ROR |
| 4849 | 4U, // RORImm |
| 4850 | 0U, // RetRA |
| 4851 | 0U, // RetRA16 |
| 4852 | 0U, // SDC1_M1 |
| 4853 | 0U, // SDIV_MM_Pseudo |
| 4854 | 0U, // SDMacro |
| 4855 | 4U, // SDivIMacro |
| 4856 | 4U, // SDivMacro |
| 4857 | 4U, // SEQIMacro |
| 4858 | 4U, // SEQMacro |
| 4859 | 4U, // SGE |
| 4860 | 4U, // SGEImm |
| 4861 | 4U, // SGEImm64 |
| 4862 | 4U, // SGEU |
| 4863 | 4U, // SGEUImm |
| 4864 | 4U, // SGEUImm64 |
| 4865 | 4U, // SGTImm |
| 4866 | 4U, // SGTImm64 |
| 4867 | 4U, // SGTUImm |
| 4868 | 4U, // SGTUImm64 |
| 4869 | 4U, // SLE |
| 4870 | 4U, // SLEImm |
| 4871 | 4U, // SLEImm64 |
| 4872 | 4U, // SLEU |
| 4873 | 4U, // SLEUImm |
| 4874 | 4U, // SLEUImm64 |
| 4875 | 4U, // SLTImm64 |
| 4876 | 4U, // SLTUImm64 |
| 4877 | 4U, // SNEIMacro |
| 4878 | 4U, // SNEMacro |
| 4879 | 0U, // SNZ_B_PSEUDO |
| 4880 | 0U, // SNZ_D_PSEUDO |
| 4881 | 0U, // SNZ_H_PSEUDO |
| 4882 | 0U, // SNZ_V_PSEUDO |
| 4883 | 0U, // SNZ_W_PSEUDO |
| 4884 | 4U, // SRemIMacro |
| 4885 | 4U, // SRemMacro |
| 4886 | 0U, // STORE_ACC128 |
| 4887 | 0U, // STORE_ACC64 |
| 4888 | 0U, // STORE_ACC64DSP |
| 4889 | 0U, // STORE_CCOND_DSP |
| 4890 | 0U, // STR_D |
| 4891 | 0U, // STR_W |
| 4892 | 0U, // ST_F16 |
| 4893 | 0U, // SWM_MM |
| 4894 | 0U, // SZ_B_PSEUDO |
| 4895 | 0U, // SZ_D_PSEUDO |
| 4896 | 0U, // SZ_H_PSEUDO |
| 4897 | 0U, // SZ_V_PSEUDO |
| 4898 | 0U, // SZ_W_PSEUDO |
| 4899 | 0U, // SaaAddr |
| 4900 | 0U, // SaadAddr |
| 4901 | 0U, // SelBeqZ |
| 4902 | 0U, // SelBneZ |
| 4903 | 0U, // SelTBteqZCmp |
| 4904 | 0U, // SelTBteqZCmpi |
| 4905 | 0U, // SelTBteqZSlt |
| 4906 | 0U, // SelTBteqZSlti |
| 4907 | 0U, // SelTBteqZSltiu |
| 4908 | 0U, // SelTBteqZSltu |
| 4909 | 0U, // SelTBtneZCmp |
| 4910 | 0U, // SelTBtneZCmpi |
| 4911 | 0U, // SelTBtneZSlt |
| 4912 | 0U, // SelTBtneZSlti |
| 4913 | 0U, // SelTBtneZSltiu |
| 4914 | 0U, // SelTBtneZSltu |
| 4915 | 0U, // SltCCRxRy16 |
| 4916 | 0U, // SltiCCRxImmX16 |
| 4917 | 0U, // SltiuCCRxImmX16 |
| 4918 | 0U, // SltuCCRxRy16 |
| 4919 | 0U, // SltuRxRyRz16 |
| 4920 | 0U, // TAILCALL |
| 4921 | 0U, // TAILCALL64R6REG |
| 4922 | 0U, // TAILCALLHB64R6REG |
| 4923 | 0U, // TAILCALLHBR6REG |
| 4924 | 0U, // TAILCALLR6REG |
| 4925 | 0U, // TAILCALLREG |
| 4926 | 0U, // TAILCALLREG64 |
| 4927 | 0U, // TAILCALLREGHB |
| 4928 | 0U, // TAILCALLREGHB64 |
| 4929 | 0U, // TAILCALLREG_MM |
| 4930 | 0U, // TAILCALLREG_MMR6 |
| 4931 | 0U, // TAILCALL_MM |
| 4932 | 0U, // TAILCALL_MMR6 |
| 4933 | 0U, // TRAP |
| 4934 | 0U, // TRAP_MM |
| 4935 | 0U, // UDIV_MM_Pseudo |
| 4936 | 4U, // UDivIMacro |
| 4937 | 4U, // UDivMacro |
| 4938 | 4U, // URemIMacro |
| 4939 | 4U, // URemMacro |
| 4940 | 0U, // Ulh |
| 4941 | 0U, // Ulhu |
| 4942 | 0U, // Ulw |
| 4943 | 0U, // Ush |
| 4944 | 0U, // Usw |
| 4945 | 0U, // XOR_V_D_PSEUDO |
| 4946 | 0U, // XOR_V_H_PSEUDO |
| 4947 | 0U, // XOR_V_W_PSEUDO |
| 4948 | 0U, // ABSQ_S_PH |
| 4949 | 0U, // ABSQ_S_PH_MM |
| 4950 | 0U, // ABSQ_S_QB |
| 4951 | 0U, // ABSQ_S_QB_MMR2 |
| 4952 | 0U, // ABSQ_S_W |
| 4953 | 0U, // ABSQ_S_W_MM |
| 4954 | 4U, // ADD |
| 4955 | 0U, // ADDIUPC |
| 4956 | 0U, // ADDIUPC_MM |
| 4957 | 0U, // ADDIUPC_MMR6 |
| 4958 | 0U, // ADDIUR1SP_MM |
| 4959 | 4U, // ADDIUR2_MM |
| 4960 | 0U, // ADDIUS5_MM |
| 4961 | 0U, // ADDIUSP_MM |
| 4962 | 4U, // ADDIU_MMR6 |
| 4963 | 4U, // ADDQH_PH |
| 4964 | 4U, // ADDQH_PH_MMR2 |
| 4965 | 4U, // ADDQH_R_PH |
| 4966 | 4U, // ADDQH_R_PH_MMR2 |
| 4967 | 4U, // ADDQH_R_W |
| 4968 | 4U, // ADDQH_R_W_MMR2 |
| 4969 | 4U, // ADDQH_W |
| 4970 | 4U, // ADDQH_W_MMR2 |
| 4971 | 4U, // ADDQ_PH |
| 4972 | 4U, // ADDQ_PH_MM |
| 4973 | 4U, // ADDQ_S_PH |
| 4974 | 4U, // ADDQ_S_PH_MM |
| 4975 | 4U, // ADDQ_S_W |
| 4976 | 4U, // ADDQ_S_W_MM |
| 4977 | 4U, // ADDR_PS64 |
| 4978 | 4U, // ADDSC |
| 4979 | 4U, // ADDSC_MM |
| 4980 | 4U, // ADDS_A_B |
| 4981 | 4U, // ADDS_A_D |
| 4982 | 4U, // ADDS_A_H |
| 4983 | 4U, // ADDS_A_W |
| 4984 | 4U, // ADDS_S_B |
| 4985 | 4U, // ADDS_S_D |
| 4986 | 4U, // ADDS_S_H |
| 4987 | 4U, // ADDS_S_W |
| 4988 | 4U, // ADDS_U_B |
| 4989 | 4U, // ADDS_U_D |
| 4990 | 4U, // ADDS_U_H |
| 4991 | 4U, // ADDS_U_W |
| 4992 | 4U, // ADDU16_MM |
| 4993 | 4U, // ADDU16_MMR6 |
| 4994 | 4U, // ADDUH_QB |
| 4995 | 4U, // ADDUH_QB_MMR2 |
| 4996 | 4U, // ADDUH_R_QB |
| 4997 | 4U, // ADDUH_R_QB_MMR2 |
| 4998 | 4U, // ADDU_MMR6 |
| 4999 | 4U, // ADDU_PH |
| 5000 | 4U, // ADDU_PH_MMR2 |
| 5001 | 4U, // ADDU_QB |
| 5002 | 4U, // ADDU_QB_MM |
| 5003 | 4U, // ADDU_S_PH |
| 5004 | 4U, // ADDU_S_PH_MMR2 |
| 5005 | 4U, // ADDU_S_QB |
| 5006 | 4U, // ADDU_S_QB_MM |
| 5007 | 12U, // ADDVI_B |
| 5008 | 12U, // ADDVI_D |
| 5009 | 12U, // ADDVI_H |
| 5010 | 12U, // ADDVI_W |
| 5011 | 4U, // ADDV_B |
| 5012 | 4U, // ADDV_D |
| 5013 | 4U, // ADDV_H |
| 5014 | 4U, // ADDV_W |
| 5015 | 4U, // ADDWC |
| 5016 | 4U, // ADDWC_MM |
| 5017 | 4U, // ADD_A_B |
| 5018 | 4U, // ADD_A_D |
| 5019 | 4U, // ADD_A_H |
| 5020 | 4U, // ADD_A_W |
| 5021 | 4U, // ADD_MM |
| 5022 | 4U, // ADD_MMR6 |
| 5023 | 4U, // ADDi |
| 5024 | 4U, // ADDi_MM |
| 5025 | 4U, // ADDiu |
| 5026 | 4U, // ADDiu_MM |
| 5027 | 4U, // ADDu |
| 5028 | 4U, // ADDu_MM |
| 5029 | 132U, // ALIGN |
| 5030 | 132U, // ALIGN_MMR6 |
| 5031 | 0U, // ALUIPC |
| 5032 | 0U, // ALUIPC_MMR6 |
| 5033 | 4U, // AND |
| 5034 | 0U, // AND16_MM |
| 5035 | 0U, // AND16_MMR6 |
| 5036 | 4U, // AND64 |
| 5037 | 4U, // ANDI16_MM |
| 5038 | 4U, // ANDI16_MMR6 |
| 5039 | 16U, // ANDI_B |
| 5040 | 20U, // ANDI_MMR6 |
| 5041 | 4U, // AND_MM |
| 5042 | 4U, // AND_MMR6 |
| 5043 | 4U, // AND_V |
| 5044 | 20U, // ANDi |
| 5045 | 20U, // ANDi64 |
| 5046 | 20U, // ANDi_MM |
| 5047 | 12U, // APPEND |
| 5048 | 12U, // APPEND_MMR2 |
| 5049 | 4U, // ASUB_S_B |
| 5050 | 4U, // ASUB_S_D |
| 5051 | 4U, // ASUB_S_H |
| 5052 | 4U, // ASUB_S_W |
| 5053 | 4U, // ASUB_U_B |
| 5054 | 4U, // ASUB_U_D |
| 5055 | 4U, // ASUB_U_H |
| 5056 | 4U, // ASUB_U_W |
| 5057 | 20U, // AUI |
| 5058 | 0U, // AUIPC |
| 5059 | 0U, // AUIPC_MMR6 |
| 5060 | 20U, // AUI_MMR6 |
| 5061 | 4U, // AVER_S_B |
| 5062 | 4U, // AVER_S_D |
| 5063 | 4U, // AVER_S_H |
| 5064 | 4U, // AVER_S_W |
| 5065 | 4U, // AVER_U_B |
| 5066 | 4U, // AVER_U_D |
| 5067 | 4U, // AVER_U_H |
| 5068 | 4U, // AVER_U_W |
| 5069 | 4U, // AVE_S_B |
| 5070 | 4U, // AVE_S_D |
| 5071 | 4U, // AVE_S_H |
| 5072 | 4U, // AVE_S_W |
| 5073 | 4U, // AVE_U_B |
| 5074 | 4U, // AVE_U_D |
| 5075 | 4U, // AVE_U_H |
| 5076 | 4U, // AVE_U_W |
| 5077 | 0U, // AddiuRxImmX16 |
| 5078 | 0U, // AddiuRxPcImmX16 |
| 5079 | 1U, // AddiuRxRxImm16 |
| 5080 | 0U, // AddiuRxRxImmX16 |
| 5081 | 0U, // AddiuRxRyOffMemX16 |
| 5082 | 0U, // AddiuSpImm16 |
| 5083 | 0U, // AddiuSpImmX16 |
| 5084 | 4U, // AdduRxRyRz16 |
| 5085 | 0U, // AndRxRxRy16 |
| 5086 | 0U, // B16_MM |
| 5087 | 4U, // BADDu |
| 5088 | 0U, // BAL |
| 5089 | 0U, // BALC |
| 5090 | 0U, // BALC_MMR6 |
| 5091 | 24U, // BALIGN |
| 5092 | 24U, // BALIGN_MMR2 |
| 5093 | 0U, // BBIT0 |
| 5094 | 0U, // BBIT032 |
| 5095 | 0U, // BBIT1 |
| 5096 | 0U, // BBIT132 |
| 5097 | 0U, // BC |
| 5098 | 0U, // BC16_MMR6 |
| 5099 | 0U, // BC1EQZ |
| 5100 | 0U, // BC1EQZC_MMR6 |
| 5101 | 0U, // BC1F |
| 5102 | 0U, // BC1FL |
| 5103 | 0U, // BC1F_MM |
| 5104 | 0U, // BC1NEZ |
| 5105 | 0U, // BC1NEZC_MMR6 |
| 5106 | 0U, // BC1T |
| 5107 | 0U, // BC1TL |
| 5108 | 0U, // BC1T_MM |
| 5109 | 0U, // BC2EQZ |
| 5110 | 0U, // BC2EQZC_MMR6 |
| 5111 | 0U, // BC2NEZ |
| 5112 | 0U, // BC2NEZC_MMR6 |
| 5113 | 8U, // BCLRI_B |
| 5114 | 28U, // BCLRI_D |
| 5115 | 32U, // BCLRI_H |
| 5116 | 12U, // BCLRI_W |
| 5117 | 4U, // BCLR_B |
| 5118 | 4U, // BCLR_D |
| 5119 | 4U, // BCLR_H |
| 5120 | 4U, // BCLR_W |
| 5121 | 0U, // BC_MMR6 |
| 5122 | 0U, // BEQ |
| 5123 | 0U, // BEQ64 |
| 5124 | 0U, // BEQC |
| 5125 | 0U, // BEQC64 |
| 5126 | 0U, // BEQC_MMR6 |
| 5127 | 0U, // BEQL |
| 5128 | 0U, // BEQZ16_MM |
| 5129 | 0U, // BEQZALC |
| 5130 | 0U, // BEQZALC_MMR6 |
| 5131 | 0U, // BEQZC |
| 5132 | 0U, // BEQZC16_MMR6 |
| 5133 | 0U, // BEQZC64 |
| 5134 | 0U, // BEQZC_MM |
| 5135 | 0U, // BEQZC_MMR6 |
| 5136 | 0U, // BEQ_MM |
| 5137 | 0U, // BGEC |
| 5138 | 0U, // BGEC64 |
| 5139 | 0U, // BGEC_MMR6 |
| 5140 | 0U, // BGEUC |
| 5141 | 0U, // BGEUC64 |
| 5142 | 0U, // BGEUC_MMR6 |
| 5143 | 0U, // BGEZ |
| 5144 | 0U, // BGEZ64 |
| 5145 | 0U, // BGEZAL |
| 5146 | 0U, // BGEZALC |
| 5147 | 0U, // BGEZALC_MMR6 |
| 5148 | 0U, // BGEZALL |
| 5149 | 0U, // BGEZALS_MM |
| 5150 | 0U, // BGEZAL_MM |
| 5151 | 0U, // BGEZC |
| 5152 | 0U, // BGEZC64 |
| 5153 | 0U, // BGEZC_MMR6 |
| 5154 | 0U, // BGEZL |
| 5155 | 0U, // BGEZ_MM |
| 5156 | 0U, // BGTZ |
| 5157 | 0U, // BGTZ64 |
| 5158 | 0U, // BGTZALC |
| 5159 | 0U, // BGTZALC_MMR6 |
| 5160 | 0U, // BGTZC |
| 5161 | 0U, // BGTZC64 |
| 5162 | 0U, // BGTZC_MMR6 |
| 5163 | 0U, // BGTZL |
| 5164 | 0U, // BGTZ_MM |
| 5165 | 36U, // BINSLI_B |
| 5166 | 40U, // BINSLI_D |
| 5167 | 44U, // BINSLI_H |
| 5168 | 48U, // BINSLI_W |
| 5169 | 52U, // BINSL_B |
| 5170 | 52U, // BINSL_D |
| 5171 | 52U, // BINSL_H |
| 5172 | 52U, // BINSL_W |
| 5173 | 36U, // BINSRI_B |
| 5174 | 40U, // BINSRI_D |
| 5175 | 44U, // BINSRI_H |
| 5176 | 48U, // BINSRI_W |
| 5177 | 52U, // BINSR_B |
| 5178 | 52U, // BINSR_D |
| 5179 | 52U, // BINSR_H |
| 5180 | 52U, // BINSR_W |
| 5181 | 0U, // BITREV |
| 5182 | 0U, // BITREV_MM |
| 5183 | 0U, // BITSWAP |
| 5184 | 0U, // BITSWAP_MMR6 |
| 5185 | 0U, // BLEZ |
| 5186 | 0U, // BLEZ64 |
| 5187 | 0U, // BLEZALC |
| 5188 | 0U, // BLEZALC_MMR6 |
| 5189 | 0U, // BLEZC |
| 5190 | 0U, // BLEZC64 |
| 5191 | 0U, // BLEZC_MMR6 |
| 5192 | 0U, // BLEZL |
| 5193 | 0U, // BLEZ_MM |
| 5194 | 0U, // BLTC |
| 5195 | 0U, // BLTC64 |
| 5196 | 0U, // BLTC_MMR6 |
| 5197 | 0U, // BLTUC |
| 5198 | 0U, // BLTUC64 |
| 5199 | 0U, // BLTUC_MMR6 |
| 5200 | 0U, // BLTZ |
| 5201 | 0U, // BLTZ64 |
| 5202 | 0U, // BLTZAL |
| 5203 | 0U, // BLTZALC |
| 5204 | 0U, // BLTZALC_MMR6 |
| 5205 | 0U, // BLTZALL |
| 5206 | 0U, // BLTZALS_MM |
| 5207 | 0U, // BLTZAL_MM |
| 5208 | 0U, // BLTZC |
| 5209 | 0U, // BLTZC64 |
| 5210 | 0U, // BLTZC_MMR6 |
| 5211 | 0U, // BLTZL |
| 5212 | 0U, // BLTZ_MM |
| 5213 | 56U, // BMNZI_B |
| 5214 | 52U, // BMNZ_V |
| 5215 | 56U, // BMZI_B |
| 5216 | 52U, // BMZ_V |
| 5217 | 0U, // BNE |
| 5218 | 0U, // BNE64 |
| 5219 | 0U, // BNEC |
| 5220 | 0U, // BNEC64 |
| 5221 | 0U, // BNEC_MMR6 |
| 5222 | 8U, // BNEGI_B |
| 5223 | 28U, // BNEGI_D |
| 5224 | 32U, // BNEGI_H |
| 5225 | 12U, // BNEGI_W |
| 5226 | 4U, // BNEG_B |
| 5227 | 4U, // BNEG_D |
| 5228 | 4U, // BNEG_H |
| 5229 | 4U, // BNEG_W |
| 5230 | 0U, // BNEL |
| 5231 | 0U, // BNEZ16_MM |
| 5232 | 0U, // BNEZALC |
| 5233 | 0U, // BNEZALC_MMR6 |
| 5234 | 0U, // BNEZC |
| 5235 | 0U, // BNEZC16_MMR6 |
| 5236 | 0U, // BNEZC64 |
| 5237 | 0U, // BNEZC_MM |
| 5238 | 0U, // BNEZC_MMR6 |
| 5239 | 0U, // BNE_MM |
| 5240 | 0U, // BNVC |
| 5241 | 0U, // BNVC_MMR6 |
| 5242 | 0U, // BNZ_B |
| 5243 | 0U, // BNZ_D |
| 5244 | 0U, // BNZ_H |
| 5245 | 0U, // BNZ_V |
| 5246 | 0U, // BNZ_W |
| 5247 | 0U, // BOVC |
| 5248 | 0U, // BOVC_MMR6 |
| 5249 | 0U, // BPOSGE32 |
| 5250 | 0U, // BPOSGE32C_MMR3 |
| 5251 | 0U, // BPOSGE32_MM |
| 5252 | 0U, // BREAK |
| 5253 | 0U, // BREAK16_MM |
| 5254 | 0U, // BREAK16_MMR6 |
| 5255 | 0U, // BREAK_MM |
| 5256 | 0U, // BREAK_MMR6 |
| 5257 | 56U, // BSELI_B |
| 5258 | 52U, // BSEL_V |
| 5259 | 8U, // BSETI_B |
| 5260 | 28U, // BSETI_D |
| 5261 | 32U, // BSETI_H |
| 5262 | 12U, // BSETI_W |
| 5263 | 4U, // BSET_B |
| 5264 | 4U, // BSET_D |
| 5265 | 4U, // BSET_H |
| 5266 | 4U, // BSET_W |
| 5267 | 0U, // BZ_B |
| 5268 | 0U, // BZ_D |
| 5269 | 0U, // BZ_H |
| 5270 | 0U, // BZ_V |
| 5271 | 0U, // BZ_W |
| 5272 | 1U, // BeqzRxImm16 |
| 5273 | 0U, // BeqzRxImmX16 |
| 5274 | 0U, // Bimm16 |
| 5275 | 0U, // BimmX16 |
| 5276 | 1U, // BnezRxImm16 |
| 5277 | 0U, // BnezRxImmX16 |
| 5278 | 0U, // Break16 |
| 5279 | 0U, // Bteqz16 |
| 5280 | 0U, // BteqzX16 |
| 5281 | 0U, // Btnez16 |
| 5282 | 0U, // BtnezX16 |
| 5283 | 0U, // CACHE |
| 5284 | 0U, // CACHEE |
| 5285 | 0U, // CACHEE_MM |
| 5286 | 0U, // CACHE_MM |
| 5287 | 0U, // CACHE_MMR6 |
| 5288 | 0U, // CACHE_R6 |
| 5289 | 0U, // CEIL_L_D64 |
| 5290 | 0U, // CEIL_L_D_MMR6 |
| 5291 | 0U, // CEIL_L_S |
| 5292 | 0U, // CEIL_L_S_MMR6 |
| 5293 | 0U, // CEIL_W_D32 |
| 5294 | 0U, // CEIL_W_D64 |
| 5295 | 0U, // CEIL_W_D_MMR6 |
| 5296 | 0U, // CEIL_W_MM |
| 5297 | 0U, // CEIL_W_S |
| 5298 | 0U, // CEIL_W_S_MM |
| 5299 | 0U, // CEIL_W_S_MMR6 |
| 5300 | 4U, // CEQI_B |
| 5301 | 4U, // CEQI_D |
| 5302 | 4U, // CEQI_H |
| 5303 | 4U, // CEQI_W |
| 5304 | 4U, // CEQ_B |
| 5305 | 4U, // CEQ_D |
| 5306 | 4U, // CEQ_H |
| 5307 | 4U, // CEQ_W |
| 5308 | 0U, // CFC1 |
| 5309 | 0U, // CFC1_MM |
| 5310 | 0U, // CFC2_MM |
| 5311 | 0U, // CFCMSA |
| 5312 | 1164U, // CINS |
| 5313 | 1164U, // CINS32 |
| 5314 | 1164U, // CINS64_32 |
| 5315 | 1164U, // CINS_i32 |
| 5316 | 0U, // CLASS_D |
| 5317 | 0U, // CLASS_D_MMR6 |
| 5318 | 0U, // CLASS_S |
| 5319 | 0U, // CLASS_S_MMR6 |
| 5320 | 4U, // CLEI_S_B |
| 5321 | 4U, // CLEI_S_D |
| 5322 | 4U, // CLEI_S_H |
| 5323 | 4U, // CLEI_S_W |
| 5324 | 12U, // CLEI_U_B |
| 5325 | 12U, // CLEI_U_D |
| 5326 | 12U, // CLEI_U_H |
| 5327 | 12U, // CLEI_U_W |
| 5328 | 4U, // CLE_S_B |
| 5329 | 4U, // CLE_S_D |
| 5330 | 4U, // CLE_S_H |
| 5331 | 4U, // CLE_S_W |
| 5332 | 4U, // CLE_U_B |
| 5333 | 4U, // CLE_U_D |
| 5334 | 4U, // CLE_U_H |
| 5335 | 4U, // CLE_U_W |
| 5336 | 0U, // CLO |
| 5337 | 0U, // CLO_MM |
| 5338 | 0U, // CLO_MMR6 |
| 5339 | 0U, // CLO_R6 |
| 5340 | 4U, // CLTI_S_B |
| 5341 | 4U, // CLTI_S_D |
| 5342 | 4U, // CLTI_S_H |
| 5343 | 4U, // CLTI_S_W |
| 5344 | 12U, // CLTI_U_B |
| 5345 | 12U, // CLTI_U_D |
| 5346 | 12U, // CLTI_U_H |
| 5347 | 12U, // CLTI_U_W |
| 5348 | 4U, // CLT_S_B |
| 5349 | 4U, // CLT_S_D |
| 5350 | 4U, // CLT_S_H |
| 5351 | 4U, // CLT_S_W |
| 5352 | 4U, // CLT_U_B |
| 5353 | 4U, // CLT_U_D |
| 5354 | 4U, // CLT_U_H |
| 5355 | 4U, // CLT_U_W |
| 5356 | 0U, // CLZ |
| 5357 | 0U, // CLZ_MM |
| 5358 | 0U, // CLZ_MMR6 |
| 5359 | 0U, // CLZ_R6 |
| 5360 | 4U, // CMPGDU_EQ_QB |
| 5361 | 4U, // CMPGDU_EQ_QB_MMR2 |
| 5362 | 4U, // CMPGDU_LE_QB |
| 5363 | 4U, // CMPGDU_LE_QB_MMR2 |
| 5364 | 4U, // CMPGDU_LT_QB |
| 5365 | 4U, // CMPGDU_LT_QB_MMR2 |
| 5366 | 4U, // CMPGU_EQ_QB |
| 5367 | 4U, // CMPGU_EQ_QB_MM |
| 5368 | 4U, // CMPGU_LE_QB |
| 5369 | 4U, // CMPGU_LE_QB_MM |
| 5370 | 4U, // CMPGU_LT_QB |
| 5371 | 4U, // CMPGU_LT_QB_MM |
| 5372 | 0U, // CMPU_EQ_QB |
| 5373 | 0U, // CMPU_EQ_QB_MM |
| 5374 | 0U, // CMPU_LE_QB |
| 5375 | 0U, // CMPU_LE_QB_MM |
| 5376 | 0U, // CMPU_LT_QB |
| 5377 | 0U, // CMPU_LT_QB_MM |
| 5378 | 4U, // CMP_AF_D_MMR6 |
| 5379 | 4U, // CMP_AF_S_MMR6 |
| 5380 | 4U, // CMP_EQ_D |
| 5381 | 4U, // CMP_EQ_D_MMR6 |
| 5382 | 0U, // CMP_EQ_PH |
| 5383 | 0U, // CMP_EQ_PH_MM |
| 5384 | 4U, // CMP_EQ_S |
| 5385 | 4U, // CMP_EQ_S_MMR6 |
| 5386 | 4U, // CMP_F_D |
| 5387 | 4U, // CMP_F_S |
| 5388 | 4U, // CMP_LE_D |
| 5389 | 4U, // CMP_LE_D_MMR6 |
| 5390 | 0U, // CMP_LE_PH |
| 5391 | 0U, // CMP_LE_PH_MM |
| 5392 | 4U, // CMP_LE_S |
| 5393 | 4U, // CMP_LE_S_MMR6 |
| 5394 | 4U, // CMP_LT_D |
| 5395 | 4U, // CMP_LT_D_MMR6 |
| 5396 | 0U, // CMP_LT_PH |
| 5397 | 0U, // CMP_LT_PH_MM |
| 5398 | 4U, // CMP_LT_S |
| 5399 | 4U, // CMP_LT_S_MMR6 |
| 5400 | 4U, // CMP_SAF_D |
| 5401 | 4U, // CMP_SAF_D_MMR6 |
| 5402 | 4U, // CMP_SAF_S |
| 5403 | 4U, // CMP_SAF_S_MMR6 |
| 5404 | 4U, // CMP_SEQ_D |
| 5405 | 4U, // CMP_SEQ_D_MMR6 |
| 5406 | 4U, // CMP_SEQ_S |
| 5407 | 4U, // CMP_SEQ_S_MMR6 |
| 5408 | 4U, // CMP_SLE_D |
| 5409 | 4U, // CMP_SLE_D_MMR6 |
| 5410 | 4U, // CMP_SLE_S |
| 5411 | 4U, // CMP_SLE_S_MMR6 |
| 5412 | 4U, // CMP_SLT_D |
| 5413 | 4U, // CMP_SLT_D_MMR6 |
| 5414 | 4U, // CMP_SLT_S |
| 5415 | 4U, // CMP_SLT_S_MMR6 |
| 5416 | 4U, // CMP_SUEQ_D |
| 5417 | 4U, // CMP_SUEQ_D_MMR6 |
| 5418 | 4U, // CMP_SUEQ_S |
| 5419 | 4U, // CMP_SUEQ_S_MMR6 |
| 5420 | 4U, // CMP_SULE_D |
| 5421 | 4U, // CMP_SULE_D_MMR6 |
| 5422 | 4U, // CMP_SULE_S |
| 5423 | 4U, // CMP_SULE_S_MMR6 |
| 5424 | 4U, // CMP_SULT_D |
| 5425 | 4U, // CMP_SULT_D_MMR6 |
| 5426 | 4U, // CMP_SULT_S |
| 5427 | 4U, // CMP_SULT_S_MMR6 |
| 5428 | 4U, // CMP_SUN_D |
| 5429 | 4U, // CMP_SUN_D_MMR6 |
| 5430 | 4U, // CMP_SUN_S |
| 5431 | 4U, // CMP_SUN_S_MMR6 |
| 5432 | 4U, // CMP_UEQ_D |
| 5433 | 4U, // CMP_UEQ_D_MMR6 |
| 5434 | 4U, // CMP_UEQ_S |
| 5435 | 4U, // CMP_UEQ_S_MMR6 |
| 5436 | 4U, // CMP_ULE_D |
| 5437 | 4U, // CMP_ULE_D_MMR6 |
| 5438 | 4U, // CMP_ULE_S |
| 5439 | 4U, // CMP_ULE_S_MMR6 |
| 5440 | 4U, // CMP_ULT_D |
| 5441 | 4U, // CMP_ULT_D_MMR6 |
| 5442 | 4U, // CMP_ULT_S |
| 5443 | 4U, // CMP_ULT_S_MMR6 |
| 5444 | 4U, // CMP_UN_D |
| 5445 | 4U, // CMP_UN_D_MMR6 |
| 5446 | 4U, // CMP_UN_S |
| 5447 | 4U, // CMP_UN_S_MMR6 |
| 5448 | 289U, // COPY_S_B |
| 5449 | 317U, // COPY_S_D |
| 5450 | 265U, // COPY_S_H |
| 5451 | 281U, // COPY_S_W |
| 5452 | 289U, // COPY_U_B |
| 5453 | 265U, // COPY_U_H |
| 5454 | 281U, // COPY_U_W |
| 5455 | 4U, // CRC32B |
| 5456 | 4U, // CRC32CB |
| 5457 | 4U, // CRC32CD |
| 5458 | 4U, // CRC32CH |
| 5459 | 4U, // CRC32CW |
| 5460 | 4U, // CRC32D |
| 5461 | 4U, // CRC32H |
| 5462 | 4U, // CRC32W |
| 5463 | 0U, // CTC1 |
| 5464 | 0U, // CTC1_MM |
| 5465 | 0U, // CTC2_MM |
| 5466 | 0U, // CTCMSA |
| 5467 | 0U, // CVT_D32_S |
| 5468 | 0U, // CVT_D32_S_MM |
| 5469 | 0U, // CVT_D32_W |
| 5470 | 0U, // CVT_D32_W_MM |
| 5471 | 0U, // CVT_D64_L |
| 5472 | 0U, // CVT_D64_S |
| 5473 | 0U, // CVT_D64_S_MM |
| 5474 | 0U, // CVT_D64_W |
| 5475 | 0U, // CVT_D64_W_MM |
| 5476 | 0U, // CVT_D_L_MMR6 |
| 5477 | 0U, // CVT_L_D64 |
| 5478 | 0U, // CVT_L_D64_MM |
| 5479 | 0U, // CVT_L_D_MMR6 |
| 5480 | 0U, // CVT_L_S |
| 5481 | 0U, // CVT_L_S_MM |
| 5482 | 0U, // CVT_L_S_MMR6 |
| 5483 | 0U, // CVT_PS_PW64 |
| 5484 | 4U, // CVT_PS_S64 |
| 5485 | 0U, // CVT_PW_PS64 |
| 5486 | 0U, // CVT_S_D32 |
| 5487 | 0U, // CVT_S_D32_MM |
| 5488 | 0U, // CVT_S_D64 |
| 5489 | 0U, // CVT_S_D64_MM |
| 5490 | 0U, // CVT_S_L |
| 5491 | 0U, // CVT_S_L_MMR6 |
| 5492 | 0U, // CVT_S_PL64 |
| 5493 | 0U, // CVT_S_PU64 |
| 5494 | 0U, // CVT_S_W |
| 5495 | 0U, // CVT_S_W_MM |
| 5496 | 0U, // CVT_S_W_MMR6 |
| 5497 | 0U, // CVT_W_D32 |
| 5498 | 0U, // CVT_W_D32_MM |
| 5499 | 0U, // CVT_W_D64 |
| 5500 | 0U, // CVT_W_D64_MM |
| 5501 | 0U, // CVT_W_S |
| 5502 | 0U, // CVT_W_S_MM |
| 5503 | 0U, // CVT_W_S_MMR6 |
| 5504 | 4U, // C_EQ_D32 |
| 5505 | 4U, // C_EQ_D32_MM |
| 5506 | 4U, // C_EQ_D64 |
| 5507 | 4U, // C_EQ_D64_MM |
| 5508 | 4U, // C_EQ_S |
| 5509 | 4U, // C_EQ_S_MM |
| 5510 | 4U, // C_F_D32 |
| 5511 | 4U, // C_F_D32_MM |
| 5512 | 4U, // C_F_D64 |
| 5513 | 4U, // C_F_D64_MM |
| 5514 | 4U, // C_F_S |
| 5515 | 4U, // C_F_S_MM |
| 5516 | 4U, // C_LE_D32 |
| 5517 | 4U, // C_LE_D32_MM |
| 5518 | 4U, // C_LE_D64 |
| 5519 | 4U, // C_LE_D64_MM |
| 5520 | 4U, // C_LE_S |
| 5521 | 4U, // C_LE_S_MM |
| 5522 | 4U, // C_LT_D32 |
| 5523 | 4U, // C_LT_D32_MM |
| 5524 | 4U, // C_LT_D64 |
| 5525 | 4U, // C_LT_D64_MM |
| 5526 | 4U, // C_LT_S |
| 5527 | 4U, // C_LT_S_MM |
| 5528 | 4U, // C_NGE_D32 |
| 5529 | 4U, // C_NGE_D32_MM |
| 5530 | 4U, // C_NGE_D64 |
| 5531 | 4U, // C_NGE_D64_MM |
| 5532 | 4U, // C_NGE_S |
| 5533 | 4U, // C_NGE_S_MM |
| 5534 | 4U, // C_NGLE_D32 |
| 5535 | 4U, // C_NGLE_D32_MM |
| 5536 | 4U, // C_NGLE_D64 |
| 5537 | 4U, // C_NGLE_D64_MM |
| 5538 | 4U, // C_NGLE_S |
| 5539 | 4U, // C_NGLE_S_MM |
| 5540 | 4U, // C_NGL_D32 |
| 5541 | 4U, // C_NGL_D32_MM |
| 5542 | 4U, // C_NGL_D64 |
| 5543 | 4U, // C_NGL_D64_MM |
| 5544 | 4U, // C_NGL_S |
| 5545 | 4U, // C_NGL_S_MM |
| 5546 | 4U, // C_NGT_D32 |
| 5547 | 4U, // C_NGT_D32_MM |
| 5548 | 4U, // C_NGT_D64 |
| 5549 | 4U, // C_NGT_D64_MM |
| 5550 | 4U, // C_NGT_S |
| 5551 | 4U, // C_NGT_S_MM |
| 5552 | 4U, // C_OLE_D32 |
| 5553 | 4U, // C_OLE_D32_MM |
| 5554 | 4U, // C_OLE_D64 |
| 5555 | 4U, // C_OLE_D64_MM |
| 5556 | 4U, // C_OLE_S |
| 5557 | 4U, // C_OLE_S_MM |
| 5558 | 4U, // C_OLT_D32 |
| 5559 | 4U, // C_OLT_D32_MM |
| 5560 | 4U, // C_OLT_D64 |
| 5561 | 4U, // C_OLT_D64_MM |
| 5562 | 4U, // C_OLT_S |
| 5563 | 4U, // C_OLT_S_MM |
| 5564 | 4U, // C_SEQ_D32 |
| 5565 | 4U, // C_SEQ_D32_MM |
| 5566 | 4U, // C_SEQ_D64 |
| 5567 | 4U, // C_SEQ_D64_MM |
| 5568 | 4U, // C_SEQ_S |
| 5569 | 4U, // C_SEQ_S_MM |
| 5570 | 4U, // C_SF_D32 |
| 5571 | 4U, // C_SF_D32_MM |
| 5572 | 4U, // C_SF_D64 |
| 5573 | 4U, // C_SF_D64_MM |
| 5574 | 4U, // C_SF_S |
| 5575 | 4U, // C_SF_S_MM |
| 5576 | 4U, // C_UEQ_D32 |
| 5577 | 4U, // C_UEQ_D32_MM |
| 5578 | 4U, // C_UEQ_D64 |
| 5579 | 4U, // C_UEQ_D64_MM |
| 5580 | 4U, // C_UEQ_S |
| 5581 | 4U, // C_UEQ_S_MM |
| 5582 | 4U, // C_ULE_D32 |
| 5583 | 4U, // C_ULE_D32_MM |
| 5584 | 4U, // C_ULE_D64 |
| 5585 | 4U, // C_ULE_D64_MM |
| 5586 | 4U, // C_ULE_S |
| 5587 | 4U, // C_ULE_S_MM |
| 5588 | 4U, // C_ULT_D32 |
| 5589 | 4U, // C_ULT_D32_MM |
| 5590 | 4U, // C_ULT_D64 |
| 5591 | 4U, // C_ULT_D64_MM |
| 5592 | 4U, // C_ULT_S |
| 5593 | 4U, // C_ULT_S_MM |
| 5594 | 4U, // C_UN_D32 |
| 5595 | 4U, // C_UN_D32_MM |
| 5596 | 4U, // C_UN_D64 |
| 5597 | 4U, // C_UN_D64_MM |
| 5598 | 4U, // C_UN_S |
| 5599 | 4U, // C_UN_S_MM |
| 5600 | 0U, // CmpRxRy16 |
| 5601 | 1U, // CmpiRxImm16 |
| 5602 | 0U, // CmpiRxImmX16 |
| 5603 | 4U, // DADD |
| 5604 | 4U, // DADDi |
| 5605 | 4U, // DADDiu |
| 5606 | 4U, // DADDu |
| 5607 | 20U, // DAHI |
| 5608 | 2180U, // DALIGN |
| 5609 | 20U, // DATI |
| 5610 | 20U, // DAUI |
| 5611 | 0U, // DBITSWAP |
| 5612 | 0U, // DCLO |
| 5613 | 0U, // DCLO_R6 |
| 5614 | 0U, // DCLZ |
| 5615 | 0U, // DCLZ_R6 |
| 5616 | 4U, // DDIV |
| 5617 | 4U, // DDIVU |
| 5618 | 0U, // DERET |
| 5619 | 0U, // DERET_MM |
| 5620 | 0U, // DERET_MMR6 |
| 5621 | 3228U, // DEXT |
| 5622 | 4252U, // DEXT64_32 |
| 5623 | 5260U, // DEXTM |
| 5624 | 448U, // DEXTU |
| 5625 | 0U, // DI |
| 5626 | 6300U, // DINS |
| 5627 | 7308U, // DINSM |
| 5628 | 576U, // DINSU |
| 5629 | 4U, // DIV |
| 5630 | 4U, // DIVU |
| 5631 | 4U, // DIVU_MMR6 |
| 5632 | 4U, // DIV_MMR6 |
| 5633 | 4U, // DIV_S_B |
| 5634 | 4U, // DIV_S_D |
| 5635 | 4U, // DIV_S_H |
| 5636 | 4U, // DIV_S_W |
| 5637 | 4U, // DIV_U_B |
| 5638 | 4U, // DIV_U_D |
| 5639 | 4U, // DIV_U_H |
| 5640 | 4U, // DIV_U_W |
| 5641 | 0U, // DI_MM |
| 5642 | 0U, // DI_MMR6 |
| 5643 | 8324U, // DLSA |
| 5644 | 8324U, // DLSA_R6 |
| 5645 | 8U, // DMFC0 |
| 5646 | 0U, // DMFC1 |
| 5647 | 8U, // DMFC2 |
| 5648 | 0U, // DMFC2_OCTEON |
| 5649 | 8U, // DMFGC0 |
| 5650 | 4U, // DMOD |
| 5651 | 4U, // DMODU |
| 5652 | 0U, // DMT |
| 5653 | 0U, // DMTC0 |
| 5654 | 0U, // DMTC1 |
| 5655 | 0U, // DMTC2 |
| 5656 | 0U, // DMTC2_OCTEON |
| 5657 | 0U, // DMTGC0 |
| 5658 | 4U, // DMUH |
| 5659 | 4U, // DMUHU |
| 5660 | 4U, // DMUL |
| 5661 | 0U, // DMULT |
| 5662 | 0U, // DMULTu |
| 5663 | 4U, // DMULU |
| 5664 | 4U, // DMUL_R6 |
| 5665 | 4U, // DOTP_S_D |
| 5666 | 4U, // DOTP_S_H |
| 5667 | 4U, // DOTP_S_W |
| 5668 | 4U, // DOTP_U_D |
| 5669 | 4U, // DOTP_U_H |
| 5670 | 4U, // DOTP_U_W |
| 5671 | 52U, // DPADD_S_D |
| 5672 | 52U, // DPADD_S_H |
| 5673 | 52U, // DPADD_S_W |
| 5674 | 52U, // DPADD_U_D |
| 5675 | 52U, // DPADD_U_H |
| 5676 | 52U, // DPADD_U_W |
| 5677 | 4U, // DPAQX_SA_W_PH |
| 5678 | 4U, // DPAQX_SA_W_PH_MMR2 |
| 5679 | 4U, // DPAQX_S_W_PH |
| 5680 | 4U, // DPAQX_S_W_PH_MMR2 |
| 5681 | 4U, // DPAQ_SA_L_W |
| 5682 | 4U, // DPAQ_SA_L_W_MM |
| 5683 | 4U, // DPAQ_S_W_PH |
| 5684 | 4U, // DPAQ_S_W_PH_MM |
| 5685 | 4U, // DPAU_H_QBL |
| 5686 | 4U, // DPAU_H_QBL_MM |
| 5687 | 4U, // DPAU_H_QBR |
| 5688 | 4U, // DPAU_H_QBR_MM |
| 5689 | 4U, // DPAX_W_PH |
| 5690 | 4U, // DPAX_W_PH_MMR2 |
| 5691 | 4U, // DPA_W_PH |
| 5692 | 4U, // DPA_W_PH_MMR2 |
| 5693 | 0U, // DPOP |
| 5694 | 4U, // DPSQX_SA_W_PH |
| 5695 | 4U, // DPSQX_SA_W_PH_MMR2 |
| 5696 | 4U, // DPSQX_S_W_PH |
| 5697 | 4U, // DPSQX_S_W_PH_MMR2 |
| 5698 | 4U, // DPSQ_SA_L_W |
| 5699 | 4U, // DPSQ_SA_L_W_MM |
| 5700 | 4U, // DPSQ_S_W_PH |
| 5701 | 4U, // DPSQ_S_W_PH_MM |
| 5702 | 52U, // DPSUB_S_D |
| 5703 | 52U, // DPSUB_S_H |
| 5704 | 52U, // DPSUB_S_W |
| 5705 | 52U, // DPSUB_U_D |
| 5706 | 52U, // DPSUB_U_H |
| 5707 | 52U, // DPSUB_U_W |
| 5708 | 4U, // DPSU_H_QBL |
| 5709 | 4U, // DPSU_H_QBL_MM |
| 5710 | 4U, // DPSU_H_QBR |
| 5711 | 4U, // DPSU_H_QBR_MM |
| 5712 | 4U, // DPSX_W_PH |
| 5713 | 4U, // DPSX_W_PH_MMR2 |
| 5714 | 4U, // DPS_W_PH |
| 5715 | 4U, // DPS_W_PH_MMR2 |
| 5716 | 28U, // DROTR |
| 5717 | 12U, // DROTR32 |
| 5718 | 4U, // DROTRV |
| 5719 | 0U, // DSBH |
| 5720 | 0U, // DSDIV |
| 5721 | 0U, // DSHD |
| 5722 | 28U, // DSLL |
| 5723 | 12U, // DSLL32 |
| 5724 | 1U, // DSLL64_32 |
| 5725 | 4U, // DSLLV |
| 5726 | 28U, // DSRA |
| 5727 | 12U, // DSRA32 |
| 5728 | 4U, // DSRAV |
| 5729 | 28U, // DSRL |
| 5730 | 12U, // DSRL32 |
| 5731 | 4U, // DSRLV |
| 5732 | 4U, // DSUB |
| 5733 | 4U, // DSUBu |
| 5734 | 0U, // DUDIV |
| 5735 | 0U, // DVP |
| 5736 | 0U, // DVPE |
| 5737 | 0U, // DVP_MMR6 |
| 5738 | 0U, // DivRxRy16 |
| 5739 | 0U, // DivuRxRy16 |
| 5740 | 0U, // EHB |
| 5741 | 0U, // EHB_MM |
| 5742 | 0U, // EHB_MMR6 |
| 5743 | 0U, // EI |
| 5744 | 0U, // EI_MM |
| 5745 | 0U, // EI_MMR6 |
| 5746 | 0U, // EMT |
| 5747 | 0U, // ERET |
| 5748 | 0U, // ERETNC |
| 5749 | 0U, // ERETNC_MMR6 |
| 5750 | 0U, // ERET_MM |
| 5751 | 0U, // ERET_MMR6 |
| 5752 | 0U, // EVP |
| 5753 | 0U, // EVPE |
| 5754 | 0U, // EVP_MMR6 |
| 5755 | 4236U, // EXT |
| 5756 | 12U, // EXTP |
| 5757 | 12U, // EXTPDP |
| 5758 | 4U, // EXTPDPV |
| 5759 | 4U, // EXTPDPV_MM |
| 5760 | 12U, // EXTPDP_MM |
| 5761 | 4U, // EXTPV |
| 5762 | 4U, // EXTPV_MM |
| 5763 | 12U, // EXTP_MM |
| 5764 | 4U, // EXTRV_RS_W |
| 5765 | 4U, // EXTRV_RS_W_MM |
| 5766 | 4U, // EXTRV_R_W |
| 5767 | 4U, // EXTRV_R_W_MM |
| 5768 | 4U, // EXTRV_S_H |
| 5769 | 4U, // EXTRV_S_H_MM |
| 5770 | 4U, // EXTRV_W |
| 5771 | 4U, // EXTRV_W_MM |
| 5772 | 12U, // EXTR_RS_W |
| 5773 | 12U, // EXTR_RS_W_MM |
| 5774 | 12U, // EXTR_R_W |
| 5775 | 12U, // EXTR_R_W_MM |
| 5776 | 12U, // EXTR_S_H |
| 5777 | 12U, // EXTR_S_H_MM |
| 5778 | 12U, // EXTR_W |
| 5779 | 12U, // EXTR_W_MM |
| 5780 | 1164U, // EXTS |
| 5781 | 1164U, // EXTS32 |
| 5782 | 4236U, // EXT_MM |
| 5783 | 4236U, // EXT_MMR6 |
| 5784 | 0U, // FABS_D32 |
| 5785 | 0U, // FABS_D32_MM |
| 5786 | 0U, // FABS_D64 |
| 5787 | 0U, // FABS_D64_MM |
| 5788 | 0U, // FABS_S |
| 5789 | 0U, // FABS_S_MM |
| 5790 | 4U, // FADD_D |
| 5791 | 4U, // FADD_D32 |
| 5792 | 4U, // FADD_D32_MM |
| 5793 | 4U, // FADD_D64 |
| 5794 | 4U, // FADD_D64_MM |
| 5795 | 4U, // FADD_PS64 |
| 5796 | 4U, // FADD_S |
| 5797 | 4U, // FADD_S_MM |
| 5798 | 68U, // FADD_S_MMR6 |
| 5799 | 4U, // FADD_W |
| 5800 | 4U, // FCAF_D |
| 5801 | 4U, // FCAF_W |
| 5802 | 4U, // FCEQ_D |
| 5803 | 4U, // FCEQ_W |
| 5804 | 0U, // FCLASS_D |
| 5805 | 0U, // FCLASS_W |
| 5806 | 4U, // FCLE_D |
| 5807 | 4U, // FCLE_W |
| 5808 | 4U, // FCLT_D |
| 5809 | 4U, // FCLT_W |
| 5810 | 0U, // FCMP_D32 |
| 5811 | 0U, // FCMP_D32_MM |
| 5812 | 0U, // FCMP_D64 |
| 5813 | 0U, // FCMP_S32 |
| 5814 | 0U, // FCMP_S32_MM |
| 5815 | 4U, // FCNE_D |
| 5816 | 4U, // FCNE_W |
| 5817 | 4U, // FCOR_D |
| 5818 | 4U, // FCOR_W |
| 5819 | 4U, // FCUEQ_D |
| 5820 | 4U, // FCUEQ_W |
| 5821 | 4U, // FCULE_D |
| 5822 | 4U, // FCULE_W |
| 5823 | 4U, // FCULT_D |
| 5824 | 4U, // FCULT_W |
| 5825 | 4U, // FCUNE_D |
| 5826 | 4U, // FCUNE_W |
| 5827 | 4U, // FCUN_D |
| 5828 | 4U, // FCUN_W |
| 5829 | 4U, // FDIV_D |
| 5830 | 4U, // FDIV_D32 |
| 5831 | 4U, // FDIV_D32_MM |
| 5832 | 4U, // FDIV_D64 |
| 5833 | 4U, // FDIV_D64_MM |
| 5834 | 4U, // FDIV_S |
| 5835 | 4U, // FDIV_S_MM |
| 5836 | 68U, // FDIV_S_MMR6 |
| 5837 | 4U, // FDIV_W |
| 5838 | 4U, // FEXDO_H |
| 5839 | 4U, // FEXDO_W |
| 5840 | 4U, // FEXP2_D |
| 5841 | 4U, // FEXP2_W |
| 5842 | 0U, // FEXUPL_D |
| 5843 | 0U, // FEXUPL_W |
| 5844 | 0U, // FEXUPR_D |
| 5845 | 0U, // FEXUPR_W |
| 5846 | 0U, // FFINT_S_D |
| 5847 | 0U, // FFINT_S_W |
| 5848 | 0U, // FFINT_U_D |
| 5849 | 0U, // FFINT_U_W |
| 5850 | 0U, // FFQL_D |
| 5851 | 0U, // FFQL_W |
| 5852 | 0U, // FFQR_D |
| 5853 | 0U, // FFQR_W |
| 5854 | 0U, // FILL_B |
| 5855 | 0U, // FILL_D |
| 5856 | 0U, // FILL_H |
| 5857 | 0U, // FILL_W |
| 5858 | 0U, // FLOG2_D |
| 5859 | 0U, // FLOG2_W |
| 5860 | 0U, // FLOOR_L_D64 |
| 5861 | 0U, // FLOOR_L_D_MMR6 |
| 5862 | 0U, // FLOOR_L_S |
| 5863 | 0U, // FLOOR_L_S_MMR6 |
| 5864 | 0U, // FLOOR_W_D32 |
| 5865 | 0U, // FLOOR_W_D64 |
| 5866 | 0U, // FLOOR_W_D_MMR6 |
| 5867 | 0U, // FLOOR_W_MM |
| 5868 | 0U, // FLOOR_W_S |
| 5869 | 0U, // FLOOR_W_S_MM |
| 5870 | 0U, // FLOOR_W_S_MMR6 |
| 5871 | 52U, // FMADD_D |
| 5872 | 52U, // FMADD_W |
| 5873 | 4U, // FMAX_A_D |
| 5874 | 4U, // FMAX_A_W |
| 5875 | 4U, // FMAX_D |
| 5876 | 4U, // FMAX_W |
| 5877 | 4U, // FMIN_A_D |
| 5878 | 4U, // FMIN_A_W |
| 5879 | 4U, // FMIN_D |
| 5880 | 4U, // FMIN_W |
| 5881 | 0U, // FMOV_D32 |
| 5882 | 0U, // FMOV_D32_MM |
| 5883 | 0U, // FMOV_D64 |
| 5884 | 0U, // FMOV_D64_MM |
| 5885 | 0U, // FMOV_D_MMR6 |
| 5886 | 0U, // FMOV_S |
| 5887 | 0U, // FMOV_S_MM |
| 5888 | 0U, // FMOV_S_MMR6 |
| 5889 | 52U, // FMSUB_D |
| 5890 | 52U, // FMSUB_W |
| 5891 | 4U, // FMUL_D |
| 5892 | 4U, // FMUL_D32 |
| 5893 | 4U, // FMUL_D32_MM |
| 5894 | 4U, // FMUL_D64 |
| 5895 | 4U, // FMUL_D64_MM |
| 5896 | 4U, // FMUL_PS64 |
| 5897 | 4U, // FMUL_S |
| 5898 | 4U, // FMUL_S_MM |
| 5899 | 68U, // FMUL_S_MMR6 |
| 5900 | 4U, // FMUL_W |
| 5901 | 0U, // FNEG_D32 |
| 5902 | 0U, // FNEG_D32_MM |
| 5903 | 0U, // FNEG_D64 |
| 5904 | 0U, // FNEG_D64_MM |
| 5905 | 0U, // FNEG_S |
| 5906 | 0U, // FNEG_S_MM |
| 5907 | 0U, // FNEG_S_MMR6 |
| 5908 | 1U, // FORK |
| 5909 | 0U, // FRCP_D |
| 5910 | 0U, // FRCP_W |
| 5911 | 0U, // FRINT_D |
| 5912 | 0U, // FRINT_W |
| 5913 | 0U, // FRSQRT_D |
| 5914 | 0U, // FRSQRT_W |
| 5915 | 4U, // FSAF_D |
| 5916 | 4U, // FSAF_W |
| 5917 | 4U, // FSEQ_D |
| 5918 | 4U, // FSEQ_W |
| 5919 | 4U, // FSLE_D |
| 5920 | 4U, // FSLE_W |
| 5921 | 4U, // FSLT_D |
| 5922 | 4U, // FSLT_W |
| 5923 | 4U, // FSNE_D |
| 5924 | 4U, // FSNE_W |
| 5925 | 4U, // FSOR_D |
| 5926 | 4U, // FSOR_W |
| 5927 | 0U, // FSQRT_D |
| 5928 | 0U, // FSQRT_D32 |
| 5929 | 0U, // FSQRT_D32_MM |
| 5930 | 0U, // FSQRT_D64 |
| 5931 | 0U, // FSQRT_D64_MM |
| 5932 | 0U, // FSQRT_S |
| 5933 | 0U, // FSQRT_S_MM |
| 5934 | 0U, // FSQRT_W |
| 5935 | 4U, // FSUB_D |
| 5936 | 4U, // FSUB_D32 |
| 5937 | 4U, // FSUB_D32_MM |
| 5938 | 4U, // FSUB_D64 |
| 5939 | 4U, // FSUB_D64_MM |
| 5940 | 4U, // FSUB_PS64 |
| 5941 | 4U, // FSUB_S |
| 5942 | 4U, // FSUB_S_MM |
| 5943 | 68U, // FSUB_S_MMR6 |
| 5944 | 4U, // FSUB_W |
| 5945 | 4U, // FSUEQ_D |
| 5946 | 4U, // FSUEQ_W |
| 5947 | 4U, // FSULE_D |
| 5948 | 4U, // FSULE_W |
| 5949 | 4U, // FSULT_D |
| 5950 | 4U, // FSULT_W |
| 5951 | 4U, // FSUNE_D |
| 5952 | 4U, // FSUNE_W |
| 5953 | 4U, // FSUN_D |
| 5954 | 4U, // FSUN_W |
| 5955 | 0U, // FTINT_S_D |
| 5956 | 0U, // FTINT_S_W |
| 5957 | 0U, // FTINT_U_D |
| 5958 | 0U, // FTINT_U_W |
| 5959 | 4U, // FTQ_H |
| 5960 | 4U, // FTQ_W |
| 5961 | 0U, // FTRUNC_S_D |
| 5962 | 0U, // FTRUNC_S_W |
| 5963 | 0U, // FTRUNC_U_D |
| 5964 | 0U, // FTRUNC_U_W |
| 5965 | 0U, // GINVI |
| 5966 | 0U, // GINVI_MMR6 |
| 5967 | 0U, // GINVT |
| 5968 | 0U, // GINVT_MMR6 |
| 5969 | 4U, // HADD_S_D |
| 5970 | 4U, // HADD_S_H |
| 5971 | 4U, // HADD_S_W |
| 5972 | 4U, // HADD_U_D |
| 5973 | 4U, // HADD_U_H |
| 5974 | 4U, // HADD_U_W |
| 5975 | 4U, // HSUB_S_D |
| 5976 | 4U, // HSUB_S_H |
| 5977 | 4U, // HSUB_S_W |
| 5978 | 4U, // HSUB_U_D |
| 5979 | 4U, // HSUB_U_H |
| 5980 | 4U, // HSUB_U_W |
| 5981 | 0U, // HYPCALL |
| 5982 | 0U, // HYPCALL_MM |
| 5983 | 4U, // ILVEV_B |
| 5984 | 4U, // ILVEV_D |
| 5985 | 4U, // ILVEV_H |
| 5986 | 4U, // ILVEV_W |
| 5987 | 4U, // ILVL_B |
| 5988 | 4U, // ILVL_D |
| 5989 | 4U, // ILVL_H |
| 5990 | 4U, // ILVL_W |
| 5991 | 4U, // ILVOD_B |
| 5992 | 4U, // ILVOD_D |
| 5993 | 4U, // ILVOD_H |
| 5994 | 4U, // ILVOD_W |
| 5995 | 4U, // ILVR_B |
| 5996 | 4U, // ILVR_D |
| 5997 | 4U, // ILVR_H |
| 5998 | 4U, // ILVR_W |
| 5999 | 6284U, // INS |
| 6000 | 0U, // INSERT_B |
| 6001 | 0U, // INSERT_D |
| 6002 | 0U, // INSERT_H |
| 6003 | 0U, // INSERT_W |
| 6004 | 0U, // INSV |
| 6005 | 0U, // INSVE_B |
| 6006 | 0U, // INSVE_D |
| 6007 | 0U, // INSVE_H |
| 6008 | 0U, // INSVE_W |
| 6009 | 0U, // INSV_MM |
| 6010 | 6284U, // INS_MM |
| 6011 | 6284U, // INS_MMR6 |
| 6012 | 0U, // J |
| 6013 | 0U, // JAL |
| 6014 | 0U, // JALR |
| 6015 | 0U, // JALR16_MM |
| 6016 | 0U, // JALR64 |
| 6017 | 0U, // JALRC16_MMR6 |
| 6018 | 0U, // JALRC_HB_MMR6 |
| 6019 | 0U, // JALRC_MMR6 |
| 6020 | 0U, // JALRS16_MM |
| 6021 | 0U, // JALRS_MM |
| 6022 | 0U, // JALR_HB |
| 6023 | 0U, // JALR_HB64 |
| 6024 | 0U, // JALR_MM |
| 6025 | 0U, // JALS_MM |
| 6026 | 0U, // JALX |
| 6027 | 0U, // JALX_MM |
| 6028 | 0U, // JAL_MM |
| 6029 | 0U, // JIALC |
| 6030 | 0U, // JIALC64 |
| 6031 | 0U, // JIALC_MMR6 |
| 6032 | 0U, // JIC |
| 6033 | 0U, // JIC64 |
| 6034 | 0U, // JIC_MMR6 |
| 6035 | 0U, // JR |
| 6036 | 0U, // JR16_MM |
| 6037 | 0U, // JR64 |
| 6038 | 0U, // JRADDIUSP |
| 6039 | 0U, // JRC16_MM |
| 6040 | 0U, // JRC16_MMR6 |
| 6041 | 0U, // JRCADDIUSP_MMR6 |
| 6042 | 0U, // JR_HB |
| 6043 | 0U, // JR_HB64 |
| 6044 | 0U, // JR_HB64_R6 |
| 6045 | 0U, // JR_HB_R6 |
| 6046 | 0U, // JR_MM |
| 6047 | 0U, // J_MM |
| 6048 | 0U, // Jal16 |
| 6049 | 0U, // JalB16 |
| 6050 | 0U, // JrRa16 |
| 6051 | 0U, // JrcRa16 |
| 6052 | 0U, // JrcRx16 |
| 6053 | 0U, // JumpLinkReg16 |
| 6054 | 0U, // LB |
| 6055 | 0U, // LB64 |
| 6056 | 0U, // LBE |
| 6057 | 0U, // LBE_MM |
| 6058 | 0U, // LBU16_MM |
| 6059 | 1U, // LBUX |
| 6060 | 1U, // LBUX_MM |
| 6061 | 0U, // LBU_MMR6 |
| 6062 | 0U, // LB_MM |
| 6063 | 0U, // LB_MMR6 |
| 6064 | 0U, // LBu |
| 6065 | 0U, // LBu64 |
| 6066 | 0U, // LBuE |
| 6067 | 0U, // LBuE_MM |
| 6068 | 0U, // LBu_MM |
| 6069 | 0U, // LD |
| 6070 | 0U, // LDC1 |
| 6071 | 0U, // LDC164 |
| 6072 | 0U, // LDC1_D64_MMR6 |
| 6073 | 0U, // LDC1_MM_D32 |
| 6074 | 0U, // LDC1_MM_D64 |
| 6075 | 0U, // LDC2 |
| 6076 | 0U, // LDC2_MMR6 |
| 6077 | 0U, // LDC2_R6 |
| 6078 | 0U, // LDC3 |
| 6079 | 0U, // LDI_B |
| 6080 | 0U, // LDI_D |
| 6081 | 0U, // LDI_H |
| 6082 | 0U, // LDI_W |
| 6083 | 0U, // LDL |
| 6084 | 0U, // LDPC |
| 6085 | 0U, // LDR |
| 6086 | 1U, // LDXC1 |
| 6087 | 1U, // LDXC164 |
| 6088 | 0U, // LD_B |
| 6089 | 0U, // LD_D |
| 6090 | 0U, // LD_H |
| 6091 | 0U, // LD_W |
| 6092 | 0U, // LEA_ADDiu |
| 6093 | 0U, // LEA_ADDiu64 |
| 6094 | 0U, // LEA_ADDiu_MM |
| 6095 | 0U, // LH |
| 6096 | 0U, // LH64 |
| 6097 | 0U, // LHE |
| 6098 | 0U, // LHE_MM |
| 6099 | 0U, // LHU16_MM |
| 6100 | 1U, // LHX |
| 6101 | 1U, // LHX_MM |
| 6102 | 0U, // LH_MM |
| 6103 | 0U, // LHu |
| 6104 | 0U, // LHu64 |
| 6105 | 0U, // LHuE |
| 6106 | 0U, // LHuE_MM |
| 6107 | 0U, // LHu_MM |
| 6108 | 0U, // LI16_MM |
| 6109 | 0U, // LI16_MMR6 |
| 6110 | 0U, // LL |
| 6111 | 0U, // LL64 |
| 6112 | 0U, // LL64_R6 |
| 6113 | 0U, // LLD |
| 6114 | 0U, // LLD_R6 |
| 6115 | 0U, // LLE |
| 6116 | 0U, // LLE_MM |
| 6117 | 0U, // LL_MM |
| 6118 | 0U, // LL_MMR6 |
| 6119 | 0U, // LL_R6 |
| 6120 | 8324U, // LSA |
| 6121 | 1U, // LSA_MMR6 |
| 6122 | 8324U, // LSA_R6 |
| 6123 | 0U, // LUI_MMR6 |
| 6124 | 1U, // LUXC1 |
| 6125 | 1U, // LUXC164 |
| 6126 | 1U, // LUXC1_MM |
| 6127 | 0U, // LUi |
| 6128 | 0U, // LUi64 |
| 6129 | 0U, // LUi_MM |
| 6130 | 0U, // LW |
| 6131 | 0U, // LW16_MM |
| 6132 | 0U, // LW64 |
| 6133 | 0U, // LWC1 |
| 6134 | 0U, // LWC1_MM |
| 6135 | 0U, // LWC2 |
| 6136 | 0U, // LWC2_MMR6 |
| 6137 | 0U, // LWC2_R6 |
| 6138 | 0U, // LWC3 |
| 6139 | 0U, // LWDSP |
| 6140 | 0U, // LWDSP_MM |
| 6141 | 0U, // LWE |
| 6142 | 0U, // LWE_MM |
| 6143 | 0U, // LWGP_MM |
| 6144 | 0U, // LWL |
| 6145 | 0U, // LWL64 |
| 6146 | 0U, // LWLE |
| 6147 | 0U, // LWLE_MM |
| 6148 | 0U, // LWL_MM |
| 6149 | 0U, // LWM16_MM |
| 6150 | 0U, // LWM16_MMR6 |
| 6151 | 0U, // LWM32_MM |
| 6152 | 0U, // LWPC |
| 6153 | 0U, // LWPC_MMR6 |
| 6154 | 0U, // LWP_MM |
| 6155 | 0U, // LWR |
| 6156 | 0U, // LWR64 |
| 6157 | 0U, // LWRE |
| 6158 | 0U, // LWRE_MM |
| 6159 | 0U, // LWR_MM |
| 6160 | 0U, // LWSP_MM |
| 6161 | 0U, // LWUPC |
| 6162 | 0U, // LWU_MM |
| 6163 | 1U, // LWX |
| 6164 | 1U, // LWXC1 |
| 6165 | 1U, // LWXC1_MM |
| 6166 | 1U, // LWXS_MM |
| 6167 | 1U, // LWX_MM |
| 6168 | 0U, // LW_MM |
| 6169 | 0U, // LW_MMR6 |
| 6170 | 0U, // LWu |
| 6171 | 0U, // LbRxRyOffMemX16 |
| 6172 | 0U, // LbuRxRyOffMemX16 |
| 6173 | 0U, // LhRxRyOffMemX16 |
| 6174 | 0U, // LhuRxRyOffMemX16 |
| 6175 | 1U, // LiRxImm16 |
| 6176 | 0U, // LiRxImmAlignX16 |
| 6177 | 0U, // LiRxImmX16 |
| 6178 | 1U, // LwRxPcTcp16 |
| 6179 | 0U, // LwRxPcTcpX16 |
| 6180 | 0U, // LwRxRyOffMemX16 |
| 6181 | 0U, // LwRxSpImmX16 |
| 6182 | 0U, // MADD |
| 6183 | 52U, // MADDF_D |
| 6184 | 52U, // MADDF_D_MMR6 |
| 6185 | 52U, // MADDF_S |
| 6186 | 52U, // MADDF_S_MMR6 |
| 6187 | 52U, // MADDR_Q_H |
| 6188 | 52U, // MADDR_Q_W |
| 6189 | 0U, // MADDU |
| 6190 | 4U, // MADDU_DSP |
| 6191 | 4U, // MADDU_DSP_MM |
| 6192 | 0U, // MADDU_MM |
| 6193 | 52U, // MADDV_B |
| 6194 | 52U, // MADDV_D |
| 6195 | 52U, // MADDV_H |
| 6196 | 52U, // MADDV_W |
| 6197 | 9348U, // MADD_D32 |
| 6198 | 9348U, // MADD_D32_MM |
| 6199 | 9348U, // MADD_D64 |
| 6200 | 4U, // MADD_DSP |
| 6201 | 4U, // MADD_DSP_MM |
| 6202 | 0U, // MADD_MM |
| 6203 | 52U, // MADD_Q_H |
| 6204 | 52U, // MADD_Q_W |
| 6205 | 9348U, // MADD_S |
| 6206 | 9348U, // MADD_S_MM |
| 6207 | 4U, // MAQ_SA_W_PHL |
| 6208 | 4U, // MAQ_SA_W_PHL_MM |
| 6209 | 4U, // MAQ_SA_W_PHR |
| 6210 | 4U, // MAQ_SA_W_PHR_MM |
| 6211 | 4U, // MAQ_S_W_PHL |
| 6212 | 4U, // MAQ_S_W_PHL_MM |
| 6213 | 4U, // MAQ_S_W_PHR |
| 6214 | 4U, // MAQ_S_W_PHR_MM |
| 6215 | 4U, // MAXA_D |
| 6216 | 4U, // MAXA_D_MMR6 |
| 6217 | 4U, // MAXA_S |
| 6218 | 4U, // MAXA_S_MMR6 |
| 6219 | 4U, // MAXI_S_B |
| 6220 | 4U, // MAXI_S_D |
| 6221 | 4U, // MAXI_S_H |
| 6222 | 4U, // MAXI_S_W |
| 6223 | 12U, // MAXI_U_B |
| 6224 | 12U, // MAXI_U_D |
| 6225 | 12U, // MAXI_U_H |
| 6226 | 12U, // MAXI_U_W |
| 6227 | 4U, // MAX_A_B |
| 6228 | 4U, // MAX_A_D |
| 6229 | 4U, // MAX_A_H |
| 6230 | 4U, // MAX_A_W |
| 6231 | 4U, // MAX_D |
| 6232 | 4U, // MAX_D_MMR6 |
| 6233 | 4U, // MAX_S |
| 6234 | 4U, // MAX_S_B |
| 6235 | 4U, // MAX_S_D |
| 6236 | 4U, // MAX_S_H |
| 6237 | 4U, // MAX_S_MMR6 |
| 6238 | 4U, // MAX_S_W |
| 6239 | 4U, // MAX_U_B |
| 6240 | 4U, // MAX_U_D |
| 6241 | 4U, // MAX_U_H |
| 6242 | 4U, // MAX_U_W |
| 6243 | 8U, // MFC0 |
| 6244 | 8U, // MFC0_MMR6 |
| 6245 | 0U, // MFC1 |
| 6246 | 0U, // MFC1_D64 |
| 6247 | 0U, // MFC1_MM |
| 6248 | 0U, // MFC1_MMR6 |
| 6249 | 8U, // MFC2 |
| 6250 | 0U, // MFC2_MMR6 |
| 6251 | 8U, // MFGC0 |
| 6252 | 8U, // MFGC0_MM |
| 6253 | 8U, // MFHC0_MMR6 |
| 6254 | 0U, // MFHC1_D32 |
| 6255 | 0U, // MFHC1_D32_MM |
| 6256 | 0U, // MFHC1_D64 |
| 6257 | 0U, // MFHC1_D64_MM |
| 6258 | 0U, // MFHC2_MMR6 |
| 6259 | 8U, // MFHGC0 |
| 6260 | 8U, // MFHGC0_MM |
| 6261 | 0U, // MFHI |
| 6262 | 0U, // MFHI16_MM |
| 6263 | 0U, // MFHI64 |
| 6264 | 0U, // MFHI_DSP |
| 6265 | 0U, // MFHI_DSP_MM |
| 6266 | 0U, // MFHI_MM |
| 6267 | 0U, // MFLO |
| 6268 | 0U, // MFLO16_MM |
| 6269 | 0U, // MFLO64 |
| 6270 | 0U, // MFLO_DSP |
| 6271 | 0U, // MFLO_DSP_MM |
| 6272 | 0U, // MFLO_MM |
| 6273 | 18620U, // MFTR |
| 6274 | 4U, // MINA_D |
| 6275 | 4U, // MINA_D_MMR6 |
| 6276 | 4U, // MINA_S |
| 6277 | 4U, // MINA_S_MMR6 |
| 6278 | 4U, // MINI_S_B |
| 6279 | 4U, // MINI_S_D |
| 6280 | 4U, // MINI_S_H |
| 6281 | 4U, // MINI_S_W |
| 6282 | 12U, // MINI_U_B |
| 6283 | 12U, // MINI_U_D |
| 6284 | 12U, // MINI_U_H |
| 6285 | 12U, // MINI_U_W |
| 6286 | 4U, // MIN_A_B |
| 6287 | 4U, // MIN_A_D |
| 6288 | 4U, // MIN_A_H |
| 6289 | 4U, // MIN_A_W |
| 6290 | 4U, // MIN_D |
| 6291 | 4U, // MIN_D_MMR6 |
| 6292 | 4U, // MIN_S |
| 6293 | 4U, // MIN_S_B |
| 6294 | 4U, // MIN_S_D |
| 6295 | 4U, // MIN_S_H |
| 6296 | 4U, // MIN_S_MMR6 |
| 6297 | 4U, // MIN_S_W |
| 6298 | 4U, // MIN_U_B |
| 6299 | 4U, // MIN_U_D |
| 6300 | 4U, // MIN_U_H |
| 6301 | 4U, // MIN_U_W |
| 6302 | 4U, // MOD |
| 6303 | 4U, // MODSUB |
| 6304 | 4U, // MODSUB_MM |
| 6305 | 4U, // MODU |
| 6306 | 4U, // MODU_MMR6 |
| 6307 | 4U, // MOD_MMR6 |
| 6308 | 4U, // MOD_S_B |
| 6309 | 4U, // MOD_S_D |
| 6310 | 4U, // MOD_S_H |
| 6311 | 4U, // MOD_S_W |
| 6312 | 4U, // MOD_U_B |
| 6313 | 4U, // MOD_U_D |
| 6314 | 4U, // MOD_U_H |
| 6315 | 4U, // MOD_U_W |
| 6316 | 0U, // MOVE16_MM |
| 6317 | 0U, // MOVE16_MMR6 |
| 6318 | 9348U, // MOVEP_MM |
| 6319 | 9348U, // MOVEP_MMR6 |
| 6320 | 0U, // MOVE_V |
| 6321 | 4U, // MOVF_D32 |
| 6322 | 4U, // MOVF_D32_MM |
| 6323 | 4U, // MOVF_D64 |
| 6324 | 4U, // MOVF_I |
| 6325 | 4U, // MOVF_I64 |
| 6326 | 4U, // MOVF_I_MM |
| 6327 | 4U, // MOVF_S |
| 6328 | 4U, // MOVF_S_MM |
| 6329 | 4U, // MOVN_I64_D64 |
| 6330 | 4U, // MOVN_I64_I |
| 6331 | 4U, // MOVN_I64_I64 |
| 6332 | 4U, // MOVN_I64_S |
| 6333 | 4U, // MOVN_I_D32 |
| 6334 | 4U, // MOVN_I_D32_MM |
| 6335 | 4U, // MOVN_I_D64 |
| 6336 | 4U, // MOVN_I_I |
| 6337 | 4U, // MOVN_I_I64 |
| 6338 | 4U, // MOVN_I_MM |
| 6339 | 4U, // MOVN_I_S |
| 6340 | 4U, // MOVN_I_S_MM |
| 6341 | 4U, // MOVT_D32 |
| 6342 | 4U, // MOVT_D32_MM |
| 6343 | 4U, // MOVT_D64 |
| 6344 | 4U, // MOVT_I |
| 6345 | 4U, // MOVT_I64 |
| 6346 | 4U, // MOVT_I_MM |
| 6347 | 4U, // MOVT_S |
| 6348 | 4U, // MOVT_S_MM |
| 6349 | 4U, // MOVZ_I64_D64 |
| 6350 | 4U, // MOVZ_I64_I |
| 6351 | 4U, // MOVZ_I64_I64 |
| 6352 | 4U, // MOVZ_I64_S |
| 6353 | 4U, // MOVZ_I_D32 |
| 6354 | 4U, // MOVZ_I_D32_MM |
| 6355 | 4U, // MOVZ_I_D64 |
| 6356 | 4U, // MOVZ_I_I |
| 6357 | 4U, // MOVZ_I_I64 |
| 6358 | 4U, // MOVZ_I_MM |
| 6359 | 4U, // MOVZ_I_S |
| 6360 | 4U, // MOVZ_I_S_MM |
| 6361 | 0U, // MSUB |
| 6362 | 52U, // MSUBF_D |
| 6363 | 52U, // MSUBF_D_MMR6 |
| 6364 | 52U, // MSUBF_S |
| 6365 | 52U, // MSUBF_S_MMR6 |
| 6366 | 52U, // MSUBR_Q_H |
| 6367 | 52U, // MSUBR_Q_W |
| 6368 | 0U, // MSUBU |
| 6369 | 4U, // MSUBU_DSP |
| 6370 | 4U, // MSUBU_DSP_MM |
| 6371 | 0U, // MSUBU_MM |
| 6372 | 52U, // MSUBV_B |
| 6373 | 52U, // MSUBV_D |
| 6374 | 52U, // MSUBV_H |
| 6375 | 52U, // MSUBV_W |
| 6376 | 9348U, // MSUB_D32 |
| 6377 | 9348U, // MSUB_D32_MM |
| 6378 | 9348U, // MSUB_D64 |
| 6379 | 4U, // MSUB_DSP |
| 6380 | 4U, // MSUB_DSP_MM |
| 6381 | 0U, // MSUB_MM |
| 6382 | 52U, // MSUB_Q_H |
| 6383 | 52U, // MSUB_Q_W |
| 6384 | 9348U, // MSUB_S |
| 6385 | 9348U, // MSUB_S_MM |
| 6386 | 0U, // MTC0 |
| 6387 | 0U, // MTC0_MMR6 |
| 6388 | 0U, // MTC1 |
| 6389 | 0U, // MTC1_D64 |
| 6390 | 0U, // MTC1_D64_MM |
| 6391 | 0U, // MTC1_MM |
| 6392 | 0U, // MTC1_MMR6 |
| 6393 | 0U, // MTC2 |
| 6394 | 0U, // MTC2_MMR6 |
| 6395 | 0U, // MTGC0 |
| 6396 | 0U, // MTGC0_MM |
| 6397 | 0U, // MTHC0_MMR6 |
| 6398 | 0U, // MTHC1_D32 |
| 6399 | 0U, // MTHC1_D32_MM |
| 6400 | 0U, // MTHC1_D64 |
| 6401 | 0U, // MTHC1_D64_MM |
| 6402 | 0U, // MTHC2_MMR6 |
| 6403 | 0U, // MTHGC0 |
| 6404 | 0U, // MTHGC0_MM |
| 6405 | 0U, // MTHI |
| 6406 | 0U, // MTHI64 |
| 6407 | 0U, // MTHI_DSP |
| 6408 | 0U, // MTHI_DSP_MM |
| 6409 | 0U, // MTHI_MM |
| 6410 | 0U, // MTHLIP |
| 6411 | 0U, // MTHLIP_MM |
| 6412 | 0U, // MTLO |
| 6413 | 0U, // MTLO64 |
| 6414 | 0U, // MTLO_DSP |
| 6415 | 0U, // MTLO_DSP_MM |
| 6416 | 0U, // MTLO_MM |
| 6417 | 0U, // MTM0 |
| 6418 | 0U, // MTM1 |
| 6419 | 0U, // MTM2 |
| 6420 | 0U, // MTP0 |
| 6421 | 0U, // MTP1 |
| 6422 | 0U, // MTP2 |
| 6423 | 2U, // MTTR |
| 6424 | 4U, // MUH |
| 6425 | 4U, // MUHU |
| 6426 | 4U, // MUHU_MMR6 |
| 6427 | 4U, // MUH_MMR6 |
| 6428 | 4U, // MUL |
| 6429 | 4U, // MULEQ_S_W_PHL |
| 6430 | 4U, // MULEQ_S_W_PHL_MM |
| 6431 | 4U, // MULEQ_S_W_PHR |
| 6432 | 4U, // MULEQ_S_W_PHR_MM |
| 6433 | 4U, // MULEU_S_PH_QBL |
| 6434 | 4U, // MULEU_S_PH_QBL_MM |
| 6435 | 4U, // MULEU_S_PH_QBR |
| 6436 | 4U, // MULEU_S_PH_QBR_MM |
| 6437 | 4U, // MULQ_RS_PH |
| 6438 | 4U, // MULQ_RS_PH_MM |
| 6439 | 4U, // MULQ_RS_W |
| 6440 | 4U, // MULQ_RS_W_MMR2 |
| 6441 | 4U, // MULQ_S_PH |
| 6442 | 4U, // MULQ_S_PH_MMR2 |
| 6443 | 4U, // MULQ_S_W |
| 6444 | 4U, // MULQ_S_W_MMR2 |
| 6445 | 4U, // MULR_PS64 |
| 6446 | 4U, // MULR_Q_H |
| 6447 | 4U, // MULR_Q_W |
| 6448 | 4U, // MULSAQ_S_W_PH |
| 6449 | 4U, // MULSAQ_S_W_PH_MM |
| 6450 | 4U, // MULSA_W_PH |
| 6451 | 4U, // MULSA_W_PH_MMR2 |
| 6452 | 0U, // MULT |
| 6453 | 4U, // MULTU_DSP |
| 6454 | 4U, // MULTU_DSP_MM |
| 6455 | 4U, // MULT_DSP |
| 6456 | 4U, // MULT_DSP_MM |
| 6457 | 0U, // MULT_MM |
| 6458 | 0U, // MULTu |
| 6459 | 0U, // MULTu_MM |
| 6460 | 4U, // MULU |
| 6461 | 4U, // MULU_MMR6 |
| 6462 | 4U, // MULV_B |
| 6463 | 4U, // MULV_D |
| 6464 | 4U, // MULV_H |
| 6465 | 4U, // MULV_W |
| 6466 | 4U, // MUL_MM |
| 6467 | 4U, // MUL_MMR6 |
| 6468 | 4U, // MUL_PH |
| 6469 | 4U, // MUL_PH_MMR2 |
| 6470 | 4U, // MUL_Q_H |
| 6471 | 4U, // MUL_Q_W |
| 6472 | 4U, // MUL_R6 |
| 6473 | 4U, // MUL_S_PH |
| 6474 | 4U, // MUL_S_PH_MMR2 |
| 6475 | 0U, // Mfhi16 |
| 6476 | 0U, // Mflo16 |
| 6477 | 0U, // Move32R16 |
| 6478 | 0U, // MoveR3216 |
| 6479 | 0U, // NAL |
| 6480 | 0U, // NLOC_B |
| 6481 | 0U, // NLOC_D |
| 6482 | 0U, // NLOC_H |
| 6483 | 0U, // NLOC_W |
| 6484 | 0U, // NLZC_B |
| 6485 | 0U, // NLZC_D |
| 6486 | 0U, // NLZC_H |
| 6487 | 0U, // NLZC_W |
| 6488 | 9348U, // NMADD_D32 |
| 6489 | 9348U, // NMADD_D32_MM |
| 6490 | 9348U, // NMADD_D64 |
| 6491 | 9348U, // NMADD_S |
| 6492 | 9348U, // NMADD_S_MM |
| 6493 | 9348U, // NMSUB_D32 |
| 6494 | 9348U, // NMSUB_D32_MM |
| 6495 | 9348U, // NMSUB_D64 |
| 6496 | 9348U, // NMSUB_S |
| 6497 | 9348U, // NMSUB_S_MM |
| 6498 | 4U, // NOR |
| 6499 | 4U, // NOR64 |
| 6500 | 16U, // NORI_B |
| 6501 | 4U, // NOR_MM |
| 6502 | 4U, // NOR_MMR6 |
| 6503 | 4U, // NOR_V |
| 6504 | 0U, // NOT16_MM |
| 6505 | 0U, // NOT16_MMR6 |
| 6506 | 0U, // NegRxRy16 |
| 6507 | 0U, // NotRxRy16 |
| 6508 | 4U, // OR |
| 6509 | 0U, // OR16_MM |
| 6510 | 0U, // OR16_MMR6 |
| 6511 | 4U, // OR64 |
| 6512 | 16U, // ORI_B |
| 6513 | 20U, // ORI_MMR6 |
| 6514 | 4U, // OR_MM |
| 6515 | 4U, // OR_MMR6 |
| 6516 | 4U, // OR_V |
| 6517 | 20U, // ORi |
| 6518 | 20U, // ORi64 |
| 6519 | 20U, // ORi_MM |
| 6520 | 0U, // OrRxRxRy16 |
| 6521 | 4U, // PACKRL_PH |
| 6522 | 4U, // PACKRL_PH_MM |
| 6523 | 0U, // PAUSE |
| 6524 | 0U, // PAUSE_MM |
| 6525 | 0U, // PAUSE_MMR6 |
| 6526 | 4U, // PCKEV_B |
| 6527 | 4U, // PCKEV_D |
| 6528 | 4U, // PCKEV_H |
| 6529 | 4U, // PCKEV_W |
| 6530 | 4U, // PCKOD_B |
| 6531 | 4U, // PCKOD_D |
| 6532 | 4U, // PCKOD_H |
| 6533 | 4U, // PCKOD_W |
| 6534 | 0U, // PCNT_B |
| 6535 | 0U, // PCNT_D |
| 6536 | 0U, // PCNT_H |
| 6537 | 0U, // PCNT_W |
| 6538 | 4U, // PICK_PH |
| 6539 | 4U, // PICK_PH_MM |
| 6540 | 4U, // PICK_QB |
| 6541 | 4U, // PICK_QB_MM |
| 6542 | 4U, // PLL_PS64 |
| 6543 | 4U, // PLU_PS64 |
| 6544 | 0U, // POP |
| 6545 | 0U, // PRECEQU_PH_QBL |
| 6546 | 0U, // PRECEQU_PH_QBLA |
| 6547 | 0U, // PRECEQU_PH_QBLA_MM |
| 6548 | 0U, // PRECEQU_PH_QBL_MM |
| 6549 | 0U, // PRECEQU_PH_QBR |
| 6550 | 0U, // PRECEQU_PH_QBRA |
| 6551 | 0U, // PRECEQU_PH_QBRA_MM |
| 6552 | 0U, // PRECEQU_PH_QBR_MM |
| 6553 | 0U, // PRECEQ_W_PHL |
| 6554 | 0U, // PRECEQ_W_PHL_MM |
| 6555 | 0U, // PRECEQ_W_PHR |
| 6556 | 0U, // PRECEQ_W_PHR_MM |
| 6557 | 0U, // PRECEU_PH_QBL |
| 6558 | 0U, // PRECEU_PH_QBLA |
| 6559 | 0U, // PRECEU_PH_QBLA_MM |
| 6560 | 0U, // PRECEU_PH_QBL_MM |
| 6561 | 0U, // PRECEU_PH_QBR |
| 6562 | 0U, // PRECEU_PH_QBRA |
| 6563 | 0U, // PRECEU_PH_QBRA_MM |
| 6564 | 0U, // PRECEU_PH_QBR_MM |
| 6565 | 4U, // PRECRQU_S_QB_PH |
| 6566 | 4U, // PRECRQU_S_QB_PH_MM |
| 6567 | 4U, // PRECRQ_PH_W |
| 6568 | 4U, // PRECRQ_PH_W_MM |
| 6569 | 4U, // PRECRQ_QB_PH |
| 6570 | 4U, // PRECRQ_QB_PH_MM |
| 6571 | 4U, // PRECRQ_RS_PH_W |
| 6572 | 4U, // PRECRQ_RS_PH_W_MM |
| 6573 | 4U, // PRECR_QB_PH |
| 6574 | 4U, // PRECR_QB_PH_MMR2 |
| 6575 | 12U, // PRECR_SRA_PH_W |
| 6576 | 12U, // PRECR_SRA_PH_W_MMR2 |
| 6577 | 12U, // PRECR_SRA_R_PH_W |
| 6578 | 12U, // PRECR_SRA_R_PH_W_MMR2 |
| 6579 | 0U, // PREF |
| 6580 | 0U, // PREFE |
| 6581 | 0U, // PREFE_MM |
| 6582 | 0U, // PREFX_MM |
| 6583 | 0U, // PREF_MM |
| 6584 | 0U, // PREF_MMR6 |
| 6585 | 0U, // PREF_R6 |
| 6586 | 12U, // PREPEND |
| 6587 | 12U, // PREPEND_MMR2 |
| 6588 | 4U, // PUL_PS64 |
| 6589 | 4U, // PUU_PS64 |
| 6590 | 0U, // RADDU_W_QB |
| 6591 | 0U, // RADDU_W_QB_MM |
| 6592 | 0U, // RDDSP |
| 6593 | 0U, // RDDSP_MM |
| 6594 | 16U, // RDHWR |
| 6595 | 16U, // RDHWR64 |
| 6596 | 16U, // RDHWR_MM |
| 6597 | 8U, // RDHWR_MMR6 |
| 6598 | 0U, // RDPGPR_MMR6 |
| 6599 | 0U, // RECIP_D32 |
| 6600 | 0U, // RECIP_D32_MM |
| 6601 | 0U, // RECIP_D64 |
| 6602 | 0U, // RECIP_D64_MM |
| 6603 | 0U, // RECIP_S |
| 6604 | 0U, // RECIP_S_MM |
| 6605 | 0U, // REPLV_PH |
| 6606 | 0U, // REPLV_PH_MM |
| 6607 | 0U, // REPLV_QB |
| 6608 | 0U, // REPLV_QB_MM |
| 6609 | 0U, // REPL_PH |
| 6610 | 0U, // REPL_PH_MM |
| 6611 | 0U, // REPL_QB |
| 6612 | 0U, // REPL_QB_MM |
| 6613 | 0U, // RINT_D |
| 6614 | 0U, // RINT_D_MMR6 |
| 6615 | 0U, // RINT_S |
| 6616 | 0U, // RINT_S_MMR6 |
| 6617 | 12U, // ROTR |
| 6618 | 4U, // ROTRV |
| 6619 | 4U, // ROTRV_MM |
| 6620 | 12U, // ROTR_MM |
| 6621 | 0U, // ROUND_L_D64 |
| 6622 | 0U, // ROUND_L_D_MMR6 |
| 6623 | 0U, // ROUND_L_S |
| 6624 | 0U, // ROUND_L_S_MMR6 |
| 6625 | 0U, // ROUND_W_D32 |
| 6626 | 0U, // ROUND_W_D64 |
| 6627 | 0U, // ROUND_W_D_MMR6 |
| 6628 | 0U, // ROUND_W_MM |
| 6629 | 0U, // ROUND_W_S |
| 6630 | 0U, // ROUND_W_S_MM |
| 6631 | 0U, // ROUND_W_S_MMR6 |
| 6632 | 0U, // RSQRT_D32 |
| 6633 | 0U, // RSQRT_D32_MM |
| 6634 | 0U, // RSQRT_D64 |
| 6635 | 0U, // RSQRT_D64_MM |
| 6636 | 0U, // RSQRT_S |
| 6637 | 0U, // RSQRT_S_MM |
| 6638 | 0U, // Restore16 |
| 6639 | 0U, // RestoreX16 |
| 6640 | 0U, // SAA |
| 6641 | 0U, // SAAD |
| 6642 | 8U, // SAT_S_B |
| 6643 | 28U, // SAT_S_D |
| 6644 | 32U, // SAT_S_H |
| 6645 | 12U, // SAT_S_W |
| 6646 | 8U, // SAT_U_B |
| 6647 | 28U, // SAT_U_D |
| 6648 | 32U, // SAT_U_H |
| 6649 | 12U, // SAT_U_W |
| 6650 | 0U, // SB |
| 6651 | 0U, // SB16_MM |
| 6652 | 0U, // SB16_MMR6 |
| 6653 | 0U, // SB64 |
| 6654 | 0U, // SBE |
| 6655 | 0U, // SBE_MM |
| 6656 | 0U, // SB_MM |
| 6657 | 0U, // SB_MMR6 |
| 6658 | 0U, // SC |
| 6659 | 0U, // SC64 |
| 6660 | 0U, // SC64_R6 |
| 6661 | 0U, // SCD |
| 6662 | 0U, // SCD_R6 |
| 6663 | 0U, // SCE |
| 6664 | 0U, // SCE_MM |
| 6665 | 0U, // SC_MM |
| 6666 | 0U, // SC_MMR6 |
| 6667 | 0U, // SC_R6 |
| 6668 | 0U, // SD |
| 6669 | 0U, // SDBBP |
| 6670 | 0U, // SDBBP16_MM |
| 6671 | 0U, // SDBBP16_MMR6 |
| 6672 | 0U, // SDBBP_MM |
| 6673 | 0U, // SDBBP_MMR6 |
| 6674 | 0U, // SDBBP_R6 |
| 6675 | 0U, // SDC1 |
| 6676 | 0U, // SDC164 |
| 6677 | 0U, // SDC1_D64_MMR6 |
| 6678 | 0U, // SDC1_MM_D32 |
| 6679 | 0U, // SDC1_MM_D64 |
| 6680 | 0U, // SDC2 |
| 6681 | 0U, // SDC2_MMR6 |
| 6682 | 0U, // SDC2_R6 |
| 6683 | 0U, // SDC3 |
| 6684 | 0U, // SDIV |
| 6685 | 0U, // SDIV_MM |
| 6686 | 0U, // SDL |
| 6687 | 0U, // SDR |
| 6688 | 1U, // SDXC1 |
| 6689 | 1U, // SDXC164 |
| 6690 | 0U, // SEB |
| 6691 | 0U, // SEB64 |
| 6692 | 0U, // SEB_MM |
| 6693 | 0U, // SEH |
| 6694 | 0U, // SEH64 |
| 6695 | 0U, // SEH_MM |
| 6696 | 4U, // SELEQZ |
| 6697 | 4U, // SELEQZ64 |
| 6698 | 4U, // SELEQZ_D |
| 6699 | 4U, // SELEQZ_D_MMR6 |
| 6700 | 4U, // SELEQZ_MMR6 |
| 6701 | 4U, // SELEQZ_S |
| 6702 | 4U, // SELEQZ_S_MMR6 |
| 6703 | 4U, // SELNEZ |
| 6704 | 4U, // SELNEZ64 |
| 6705 | 4U, // SELNEZ_D |
| 6706 | 4U, // SELNEZ_D_MMR6 |
| 6707 | 4U, // SELNEZ_MMR6 |
| 6708 | 4U, // SELNEZ_S |
| 6709 | 4U, // SELNEZ_S_MMR6 |
| 6710 | 52U, // SEL_D |
| 6711 | 52U, // SEL_D_MMR6 |
| 6712 | 52U, // SEL_S |
| 6713 | 52U, // SEL_S_MMR6 |
| 6714 | 4U, // SEQ |
| 6715 | 4U, // SEQi |
| 6716 | 0U, // SH |
| 6717 | 0U, // SH16_MM |
| 6718 | 0U, // SH16_MMR6 |
| 6719 | 0U, // SH64 |
| 6720 | 0U, // SHE |
| 6721 | 0U, // SHE_MM |
| 6722 | 16U, // SHF_B |
| 6723 | 16U, // SHF_H |
| 6724 | 16U, // SHF_W |
| 6725 | 0U, // SHILO |
| 6726 | 0U, // SHILOV |
| 6727 | 0U, // SHILOV_MM |
| 6728 | 0U, // SHILO_MM |
| 6729 | 4U, // SHLLV_PH |
| 6730 | 4U, // SHLLV_PH_MM |
| 6731 | 4U, // SHLLV_QB |
| 6732 | 4U, // SHLLV_QB_MM |
| 6733 | 4U, // SHLLV_S_PH |
| 6734 | 4U, // SHLLV_S_PH_MM |
| 6735 | 4U, // SHLLV_S_W |
| 6736 | 4U, // SHLLV_S_W_MM |
| 6737 | 32U, // SHLL_PH |
| 6738 | 32U, // SHLL_PH_MM |
| 6739 | 8U, // SHLL_QB |
| 6740 | 8U, // SHLL_QB_MM |
| 6741 | 32U, // SHLL_S_PH |
| 6742 | 32U, // SHLL_S_PH_MM |
| 6743 | 12U, // SHLL_S_W |
| 6744 | 12U, // SHLL_S_W_MM |
| 6745 | 4U, // SHRAV_PH |
| 6746 | 4U, // SHRAV_PH_MM |
| 6747 | 4U, // SHRAV_QB |
| 6748 | 4U, // SHRAV_QB_MMR2 |
| 6749 | 4U, // SHRAV_R_PH |
| 6750 | 4U, // SHRAV_R_PH_MM |
| 6751 | 4U, // SHRAV_R_QB |
| 6752 | 4U, // SHRAV_R_QB_MMR2 |
| 6753 | 4U, // SHRAV_R_W |
| 6754 | 4U, // SHRAV_R_W_MM |
| 6755 | 32U, // SHRA_PH |
| 6756 | 32U, // SHRA_PH_MM |
| 6757 | 8U, // SHRA_QB |
| 6758 | 8U, // SHRA_QB_MMR2 |
| 6759 | 32U, // SHRA_R_PH |
| 6760 | 32U, // SHRA_R_PH_MM |
| 6761 | 8U, // SHRA_R_QB |
| 6762 | 8U, // SHRA_R_QB_MMR2 |
| 6763 | 12U, // SHRA_R_W |
| 6764 | 12U, // SHRA_R_W_MM |
| 6765 | 4U, // SHRLV_PH |
| 6766 | 4U, // SHRLV_PH_MMR2 |
| 6767 | 4U, // SHRLV_QB |
| 6768 | 4U, // SHRLV_QB_MM |
| 6769 | 32U, // SHRL_PH |
| 6770 | 32U, // SHRL_PH_MMR2 |
| 6771 | 8U, // SHRL_QB |
| 6772 | 8U, // SHRL_QB_MM |
| 6773 | 0U, // SH_MM |
| 6774 | 0U, // SH_MMR6 |
| 6775 | 0U, // SIGRIE |
| 6776 | 0U, // SIGRIE_MMR6 |
| 6777 | 301U, // SLDI_B |
| 6778 | 73U, // SLDI_D |
| 6779 | 293U, // SLDI_H |
| 6780 | 77U, // SLDI_W |
| 6781 | 309U, // SLD_B |
| 6782 | 309U, // SLD_D |
| 6783 | 309U, // SLD_H |
| 6784 | 309U, // SLD_W |
| 6785 | 12U, // SLL |
| 6786 | 4U, // SLL16_MM |
| 6787 | 4U, // SLL16_MMR6 |
| 6788 | 2U, // SLL64_32 |
| 6789 | 2U, // SLL64_64 |
| 6790 | 8U, // SLLI_B |
| 6791 | 28U, // SLLI_D |
| 6792 | 32U, // SLLI_H |
| 6793 | 12U, // SLLI_W |
| 6794 | 4U, // SLLV |
| 6795 | 4U, // SLLV_MM |
| 6796 | 4U, // SLL_B |
| 6797 | 4U, // SLL_D |
| 6798 | 4U, // SLL_H |
| 6799 | 12U, // SLL_MM |
| 6800 | 12U, // SLL_MMR6 |
| 6801 | 4U, // SLL_W |
| 6802 | 4U, // SLT |
| 6803 | 4U, // SLT64 |
| 6804 | 4U, // SLT_MM |
| 6805 | 4U, // SLTi |
| 6806 | 4U, // SLTi64 |
| 6807 | 4U, // SLTi_MM |
| 6808 | 4U, // SLTiu |
| 6809 | 4U, // SLTiu64 |
| 6810 | 4U, // SLTiu_MM |
| 6811 | 4U, // SLTu |
| 6812 | 4U, // SLTu64 |
| 6813 | 4U, // SLTu_MM |
| 6814 | 4U, // SNE |
| 6815 | 4U, // SNEi |
| 6816 | 289U, // SPLATI_B |
| 6817 | 317U, // SPLATI_D |
| 6818 | 265U, // SPLATI_H |
| 6819 | 281U, // SPLATI_W |
| 6820 | 261U, // SPLAT_B |
| 6821 | 261U, // SPLAT_D |
| 6822 | 261U, // SPLAT_H |
| 6823 | 261U, // SPLAT_W |
| 6824 | 12U, // SRA |
| 6825 | 8U, // SRAI_B |
| 6826 | 28U, // SRAI_D |
| 6827 | 32U, // SRAI_H |
| 6828 | 12U, // SRAI_W |
| 6829 | 8U, // SRARI_B |
| 6830 | 28U, // SRARI_D |
| 6831 | 32U, // SRARI_H |
| 6832 | 12U, // SRARI_W |
| 6833 | 4U, // SRAR_B |
| 6834 | 4U, // SRAR_D |
| 6835 | 4U, // SRAR_H |
| 6836 | 4U, // SRAR_W |
| 6837 | 4U, // SRAV |
| 6838 | 4U, // SRAV_MM |
| 6839 | 4U, // SRA_B |
| 6840 | 4U, // SRA_D |
| 6841 | 4U, // SRA_H |
| 6842 | 12U, // SRA_MM |
| 6843 | 4U, // SRA_W |
| 6844 | 12U, // SRL |
| 6845 | 4U, // SRL16_MM |
| 6846 | 4U, // SRL16_MMR6 |
| 6847 | 8U, // SRLI_B |
| 6848 | 28U, // SRLI_D |
| 6849 | 32U, // SRLI_H |
| 6850 | 12U, // SRLI_W |
| 6851 | 8U, // SRLRI_B |
| 6852 | 28U, // SRLRI_D |
| 6853 | 32U, // SRLRI_H |
| 6854 | 12U, // SRLRI_W |
| 6855 | 4U, // SRLR_B |
| 6856 | 4U, // SRLR_D |
| 6857 | 4U, // SRLR_H |
| 6858 | 4U, // SRLR_W |
| 6859 | 4U, // SRLV |
| 6860 | 4U, // SRLV_MM |
| 6861 | 4U, // SRL_B |
| 6862 | 4U, // SRL_D |
| 6863 | 4U, // SRL_H |
| 6864 | 12U, // SRL_MM |
| 6865 | 4U, // SRL_W |
| 6866 | 0U, // SSNOP |
| 6867 | 0U, // SSNOP_MM |
| 6868 | 0U, // SSNOP_MMR6 |
| 6869 | 0U, // ST_B |
| 6870 | 0U, // ST_D |
| 6871 | 0U, // ST_H |
| 6872 | 0U, // ST_W |
| 6873 | 4U, // SUB |
| 6874 | 4U, // SUBQH_PH |
| 6875 | 4U, // SUBQH_PH_MMR2 |
| 6876 | 4U, // SUBQH_R_PH |
| 6877 | 4U, // SUBQH_R_PH_MMR2 |
| 6878 | 4U, // SUBQH_R_W |
| 6879 | 4U, // SUBQH_R_W_MMR2 |
| 6880 | 4U, // SUBQH_W |
| 6881 | 4U, // SUBQH_W_MMR2 |
| 6882 | 4U, // SUBQ_PH |
| 6883 | 4U, // SUBQ_PH_MM |
| 6884 | 4U, // SUBQ_S_PH |
| 6885 | 4U, // SUBQ_S_PH_MM |
| 6886 | 4U, // SUBQ_S_W |
| 6887 | 4U, // SUBQ_S_W_MM |
| 6888 | 4U, // SUBSUS_U_B |
| 6889 | 4U, // SUBSUS_U_D |
| 6890 | 4U, // SUBSUS_U_H |
| 6891 | 4U, // SUBSUS_U_W |
| 6892 | 4U, // SUBSUU_S_B |
| 6893 | 4U, // SUBSUU_S_D |
| 6894 | 4U, // SUBSUU_S_H |
| 6895 | 4U, // SUBSUU_S_W |
| 6896 | 4U, // SUBS_S_B |
| 6897 | 4U, // SUBS_S_D |
| 6898 | 4U, // SUBS_S_H |
| 6899 | 4U, // SUBS_S_W |
| 6900 | 4U, // SUBS_U_B |
| 6901 | 4U, // SUBS_U_D |
| 6902 | 4U, // SUBS_U_H |
| 6903 | 4U, // SUBS_U_W |
| 6904 | 4U, // SUBU16_MM |
| 6905 | 4U, // SUBU16_MMR6 |
| 6906 | 4U, // SUBUH_QB |
| 6907 | 4U, // SUBUH_QB_MMR2 |
| 6908 | 4U, // SUBUH_R_QB |
| 6909 | 4U, // SUBUH_R_QB_MMR2 |
| 6910 | 4U, // SUBU_MMR6 |
| 6911 | 4U, // SUBU_PH |
| 6912 | 4U, // SUBU_PH_MMR2 |
| 6913 | 4U, // SUBU_QB |
| 6914 | 4U, // SUBU_QB_MM |
| 6915 | 4U, // SUBU_S_PH |
| 6916 | 4U, // SUBU_S_PH_MMR2 |
| 6917 | 4U, // SUBU_S_QB |
| 6918 | 4U, // SUBU_S_QB_MM |
| 6919 | 12U, // SUBVI_B |
| 6920 | 12U, // SUBVI_D |
| 6921 | 12U, // SUBVI_H |
| 6922 | 12U, // SUBVI_W |
| 6923 | 4U, // SUBV_B |
| 6924 | 4U, // SUBV_D |
| 6925 | 4U, // SUBV_H |
| 6926 | 4U, // SUBV_W |
| 6927 | 4U, // SUB_MM |
| 6928 | 4U, // SUB_MMR6 |
| 6929 | 4U, // SUBu |
| 6930 | 4U, // SUBu_MM |
| 6931 | 1U, // SUXC1 |
| 6932 | 1U, // SUXC164 |
| 6933 | 1U, // SUXC1_MM |
| 6934 | 0U, // SW |
| 6935 | 0U, // SW16_MM |
| 6936 | 0U, // SW16_MMR6 |
| 6937 | 0U, // SW64 |
| 6938 | 0U, // SWC1 |
| 6939 | 0U, // SWC1_MM |
| 6940 | 0U, // SWC2 |
| 6941 | 0U, // SWC2_MMR6 |
| 6942 | 0U, // SWC2_R6 |
| 6943 | 0U, // SWC3 |
| 6944 | 0U, // SWDSP |
| 6945 | 0U, // SWDSP_MM |
| 6946 | 0U, // SWE |
| 6947 | 0U, // SWE_MM |
| 6948 | 0U, // SWL |
| 6949 | 0U, // SWL64 |
| 6950 | 0U, // SWLE |
| 6951 | 0U, // SWLE_MM |
| 6952 | 0U, // SWL_MM |
| 6953 | 0U, // SWM16_MM |
| 6954 | 0U, // SWM16_MMR6 |
| 6955 | 0U, // SWM32_MM |
| 6956 | 0U, // SWP_MM |
| 6957 | 0U, // SWR |
| 6958 | 0U, // SWR64 |
| 6959 | 0U, // SWRE |
| 6960 | 0U, // SWRE_MM |
| 6961 | 0U, // SWR_MM |
| 6962 | 0U, // SWSP_MM |
| 6963 | 0U, // SWSP_MMR6 |
| 6964 | 1U, // SWXC1 |
| 6965 | 1U, // SWXC1_MM |
| 6966 | 0U, // SW_MM |
| 6967 | 0U, // SW_MMR6 |
| 6968 | 0U, // SYNC |
| 6969 | 0U, // SYNCI |
| 6970 | 0U, // SYNCI_MM |
| 6971 | 0U, // SYNCI_MMR6 |
| 6972 | 0U, // SYNC_MM |
| 6973 | 0U, // SYNC_MMR6 |
| 6974 | 0U, // SYSCALL |
| 6975 | 0U, // SYSCALL_MM |
| 6976 | 0U, // Save16 |
| 6977 | 0U, // SaveX16 |
| 6978 | 0U, // SbRxRyOffMemX16 |
| 6979 | 0U, // SebRx16 |
| 6980 | 0U, // SehRx16 |
| 6981 | 0U, // ShRxRyOffMemX16 |
| 6982 | 12U, // SllX16 |
| 6983 | 0U, // SllvRxRy16 |
| 6984 | 0U, // SltRxRy16 |
| 6985 | 1U, // SltiRxImm16 |
| 6986 | 0U, // SltiRxImmX16 |
| 6987 | 1U, // SltiuRxImm16 |
| 6988 | 0U, // SltiuRxImmX16 |
| 6989 | 0U, // SltuRxRy16 |
| 6990 | 12U, // SraX16 |
| 6991 | 0U, // SravRxRy16 |
| 6992 | 12U, // SrlX16 |
| 6993 | 0U, // SrlvRxRy16 |
| 6994 | 4U, // SubuRxRyRz16 |
| 6995 | 0U, // SwRxRyOffMemX16 |
| 6996 | 0U, // SwRxSpImmX16 |
| 6997 | 80U, // TEQ |
| 6998 | 0U, // TEQI |
| 6999 | 0U, // TEQI_MM |
| 7000 | 32U, // TEQ_MM |
| 7001 | 80U, // TGE |
| 7002 | 0U, // TGEI |
| 7003 | 0U, // TGEIU |
| 7004 | 0U, // TGEIU_MM |
| 7005 | 0U, // TGEI_MM |
| 7006 | 80U, // TGEU |
| 7007 | 32U, // TGEU_MM |
| 7008 | 32U, // TGE_MM |
| 7009 | 0U, // TLBGINV |
| 7010 | 0U, // TLBGINVF |
| 7011 | 0U, // TLBGINVF_MM |
| 7012 | 0U, // TLBGINV_MM |
| 7013 | 0U, // TLBGP |
| 7014 | 0U, // TLBGP_MM |
| 7015 | 0U, // TLBGR |
| 7016 | 0U, // TLBGR_MM |
| 7017 | 0U, // TLBGWI |
| 7018 | 0U, // TLBGWI_MM |
| 7019 | 0U, // TLBGWR |
| 7020 | 0U, // TLBGWR_MM |
| 7021 | 0U, // TLBINV |
| 7022 | 0U, // TLBINVF |
| 7023 | 0U, // TLBINVF_MMR6 |
| 7024 | 0U, // TLBINV_MMR6 |
| 7025 | 0U, // TLBP |
| 7026 | 0U, // TLBP_MM |
| 7027 | 0U, // TLBR |
| 7028 | 0U, // TLBR_MM |
| 7029 | 0U, // TLBWI |
| 7030 | 0U, // TLBWI_MM |
| 7031 | 0U, // TLBWR |
| 7032 | 0U, // TLBWR_MM |
| 7033 | 80U, // TLT |
| 7034 | 0U, // TLTI |
| 7035 | 0U, // TLTIU_MM |
| 7036 | 0U, // TLTI_MM |
| 7037 | 80U, // TLTU |
| 7038 | 32U, // TLTU_MM |
| 7039 | 32U, // TLT_MM |
| 7040 | 80U, // TNE |
| 7041 | 0U, // TNEI |
| 7042 | 0U, // TNEI_MM |
| 7043 | 32U, // TNE_MM |
| 7044 | 0U, // TRUNC_L_D64 |
| 7045 | 0U, // TRUNC_L_D_MMR6 |
| 7046 | 0U, // TRUNC_L_S |
| 7047 | 0U, // TRUNC_L_S_MMR6 |
| 7048 | 0U, // TRUNC_W_D32 |
| 7049 | 0U, // TRUNC_W_D64 |
| 7050 | 0U, // TRUNC_W_D_MMR6 |
| 7051 | 0U, // TRUNC_W_MM |
| 7052 | 0U, // TRUNC_W_S |
| 7053 | 0U, // TRUNC_W_S_MM |
| 7054 | 0U, // TRUNC_W_S_MMR6 |
| 7055 | 0U, // TTLTIU |
| 7056 | 0U, // UDIV |
| 7057 | 0U, // UDIV_MM |
| 7058 | 4U, // V3MULU |
| 7059 | 4U, // VMM0 |
| 7060 | 4U, // VMULU |
| 7061 | 52U, // VSHF_B |
| 7062 | 52U, // VSHF_D |
| 7063 | 52U, // VSHF_H |
| 7064 | 52U, // VSHF_W |
| 7065 | 0U, // WAIT |
| 7066 | 0U, // WAIT_MM |
| 7067 | 0U, // WAIT_MMR6 |
| 7068 | 0U, // WRDSP |
| 7069 | 0U, // WRDSP_MM |
| 7070 | 0U, // WRPGPR_MMR6 |
| 7071 | 0U, // WSBH |
| 7072 | 0U, // WSBH_MM |
| 7073 | 0U, // WSBH_MMR6 |
| 7074 | 4U, // XOR |
| 7075 | 0U, // XOR16_MM |
| 7076 | 0U, // XOR16_MMR6 |
| 7077 | 4U, // XOR64 |
| 7078 | 16U, // XORI_B |
| 7079 | 20U, // XORI_MMR6 |
| 7080 | 4U, // XOR_MM |
| 7081 | 4U, // XOR_MMR6 |
| 7082 | 4U, // XOR_V |
| 7083 | 20U, // XORi |
| 7084 | 20U, // XORi64 |
| 7085 | 20U, // XORi_MM |
| 7086 | 0U, // XorRxRxRy16 |
| 7087 | 0U, // YIELD |
| 7088 | }; |
| 7089 | |
| 7090 | // Emit the opcode for the instruction. |
| 7091 | uint64_t Bits = 0; |
| 7092 | Bits |= (uint64_t)OpInfo0[MI.getOpcode()] << 0; |
| 7093 | Bits |= (uint64_t)OpInfo1[MI.getOpcode()] << 32; |
| 7094 | if (Bits == 0) |
| 7095 | return {nullptr, Bits}; |
| 7096 | return {AsmStrs+(Bits & 16383)-1, Bits}; |
| 7097 | |
| 7098 | } |
| 7099 | /// printInstruction - This method is automatically generated by tablegen |
| 7100 | /// from the instruction set description. |
| 7101 | LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
| 7102 | void MipsInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| 7103 | O << "\t"; |
| 7104 | |
| 7105 | auto MnemonicInfo = getMnemonic(MI: *MI); |
| 7106 | |
| 7107 | O << MnemonicInfo.first; |
| 7108 | |
| 7109 | uint64_t Bits = MnemonicInfo.second; |
| 7110 | assert(Bits != 0 && "Cannot print this instruction."); |
| 7111 | |
| 7112 | // Fragment 0 encoded into 5 bits for 17 unique commands. |
| 7113 | switch ((Bits >> 14) & 31) { |
| 7114 | default: llvm_unreachable("Invalid command number."); |
| 7115 | case 0: |
| 7116 | // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
| 7117 | return; |
| 7118 | break; |
| 7119 | case 1: |
| 7120 | // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... |
| 7121 | printOperand(MI, OpNo: 0, STI, O); |
| 7122 | break; |
| 7123 | case 2: |
| 7124 | // B_MMR6_Pseudo, B_MM_Pseudo, B16_MM, BAL, BALC, BALC_MMR6, BC, BC16_MMR... |
| 7125 | printBranchOperand(MI, Address, OpNo: 0, STI, O); |
| 7126 | break; |
| 7127 | case 3: |
| 7128 | // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, MultRxRyRz1... |
| 7129 | printOperand(MI, OpNo: 1, STI, O); |
| 7130 | O << ", "; |
| 7131 | break; |
| 7132 | case 4: |
| 7133 | // LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ... |
| 7134 | printRegisterList(MI, opNum: 0, STI, O); |
| 7135 | O << ", "; |
| 7136 | printMemOperand(MI, opNum: 1, STI, O); |
| 7137 | return; |
| 7138 | break; |
| 7139 | case 5: |
| 7140 | // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... |
| 7141 | printOperand(MI, OpNo: 3, STI, O); |
| 7142 | break; |
| 7143 | case 6: |
| 7144 | // AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT... |
| 7145 | printOperand(MI, OpNo: 2, STI, O); |
| 7146 | O << ", "; |
| 7147 | break; |
| 7148 | case 7: |
| 7149 | // BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM... |
| 7150 | printUImm<10>(MI, opNum: 0, STI, O); |
| 7151 | break; |
| 7152 | case 8: |
| 7153 | // BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6 |
| 7154 | printUImm<4>(MI, opNum: 0, STI, O); |
| 7155 | return; |
| 7156 | break; |
| 7157 | case 9: |
| 7158 | // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... |
| 7159 | printUImm<5>(MI, opNum: 2, STI, O); |
| 7160 | O << ", "; |
| 7161 | break; |
| 7162 | case 10: |
| 7163 | // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM |
| 7164 | printFCCOperand(MI, opNum: 2, STI, O); |
| 7165 | break; |
| 7166 | case 11: |
| 7167 | // J, JAL, JALS_MM, JALX, JALX_MM, JAL_MM, J_MM |
| 7168 | printJumpOperand(MI, OpNo: 0, STI, O); |
| 7169 | return; |
| 7170 | break; |
| 7171 | case 12: |
| 7172 | // Jal16, JalB16 |
| 7173 | printUImm<26>(MI, opNum: 0, STI, O); |
| 7174 | break; |
| 7175 | case 13: |
| 7176 | // SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL |
| 7177 | printUImm<20>(MI, opNum: 0, STI, O); |
| 7178 | return; |
| 7179 | break; |
| 7180 | case 14: |
| 7181 | // SIGRIE, SIGRIE_MMR6 |
| 7182 | printUImm<16>(MI, opNum: 0, STI, O); |
| 7183 | return; |
| 7184 | break; |
| 7185 | case 15: |
| 7186 | // SYNC, SYNC_MM, SYNC_MMR6 |
| 7187 | printUImm<5>(MI, opNum: 0, STI, O); |
| 7188 | return; |
| 7189 | break; |
| 7190 | case 16: |
| 7191 | // SYNCI, SYNCI_MM, SYNCI_MMR6 |
| 7192 | printMemOperand(MI, opNum: 0, STI, O); |
| 7193 | return; |
| 7194 | break; |
| 7195 | } |
| 7196 | |
| 7197 | |
| 7198 | // Fragment 1 encoded into 5 bits for 18 unique commands. |
| 7199 | switch ((Bits >> 19) & 31) { |
| 7200 | default: llvm_unreachable("Invalid command number."); |
| 7201 | case 0: |
| 7202 | // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... |
| 7203 | O << ", "; |
| 7204 | break; |
| 7205 | case 1: |
| 7206 | // B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MTTDSP, ADD... |
| 7207 | return; |
| 7208 | break; |
| 7209 | case 2: |
| 7210 | // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, CTC1, CTC1_... |
| 7211 | printOperand(MI, OpNo: 0, STI, O); |
| 7212 | break; |
| 7213 | case 3: |
| 7214 | // LwConstant32 |
| 7215 | O << ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"; |
| 7216 | printOperand(MI, OpNo: 1, STI, O); |
| 7217 | O << "\n2:"; |
| 7218 | return; |
| 7219 | break; |
| 7220 | case 4: |
| 7221 | // MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm... |
| 7222 | printOperand(MI, OpNo: 2, STI, O); |
| 7223 | break; |
| 7224 | case 5: |
| 7225 | // SelBeqZ, SelBneZ |
| 7226 | O << ", .+4\n\t\n\tmove "; |
| 7227 | printOperand(MI, OpNo: 1, STI, O); |
| 7228 | O << ", "; |
| 7229 | printOperand(MI, OpNo: 2, STI, O); |
| 7230 | return; |
| 7231 | break; |
| 7232 | case 6: |
| 7233 | // AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM... |
| 7234 | printOperand(MI, OpNo: 1, STI, O); |
| 7235 | break; |
| 7236 | case 7: |
| 7237 | // AddiuRxPcImmX16 |
| 7238 | O << ", $pc, "; |
| 7239 | printOperand(MI, OpNo: 1, STI, O); |
| 7240 | return; |
| 7241 | break; |
| 7242 | case 8: |
| 7243 | // AddiuSpImm16, Bimm16 |
| 7244 | O << " # 16 bit inst"; |
| 7245 | return; |
| 7246 | break; |
| 7247 | case 9: |
| 7248 | // Bteqz16, Btnez16 |
| 7249 | O << " # 16 bit inst"; |
| 7250 | return; |
| 7251 | break; |
| 7252 | case 10: |
| 7253 | // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... |
| 7254 | printMemOperand(MI, opNum: 0, STI, O); |
| 7255 | return; |
| 7256 | break; |
| 7257 | case 11: |
| 7258 | // FCMP_D32, FCMP_D32_MM, FCMP_D64 |
| 7259 | O << ".d\t"; |
| 7260 | printOperand(MI, OpNo: 0, STI, O); |
| 7261 | O << ", "; |
| 7262 | printOperand(MI, OpNo: 1, STI, O); |
| 7263 | return; |
| 7264 | break; |
| 7265 | case 12: |
| 7266 | // FCMP_S32, FCMP_S32_MM |
| 7267 | O << ".s\t"; |
| 7268 | printOperand(MI, OpNo: 0, STI, O); |
| 7269 | O << ", "; |
| 7270 | printOperand(MI, OpNo: 1, STI, O); |
| 7271 | return; |
| 7272 | break; |
| 7273 | case 13: |
| 7274 | // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... |
| 7275 | O << '['; |
| 7276 | break; |
| 7277 | case 14: |
| 7278 | // Jal16 |
| 7279 | O << "\n\tnop"; |
| 7280 | return; |
| 7281 | break; |
| 7282 | case 15: |
| 7283 | // JalB16 |
| 7284 | O << "\t# branch\n\tnop"; |
| 7285 | return; |
| 7286 | break; |
| 7287 | case 16: |
| 7288 | // SAA, SAAD |
| 7289 | O << ", ("; |
| 7290 | printOperand(MI, OpNo: 1, STI, O); |
| 7291 | O << ')'; |
| 7292 | return; |
| 7293 | break; |
| 7294 | case 17: |
| 7295 | // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6 |
| 7296 | printMemOperand(MI, opNum: 2, STI, O); |
| 7297 | return; |
| 7298 | break; |
| 7299 | } |
| 7300 | |
| 7301 | |
| 7302 | // Fragment 2 encoded into 5 bits for 26 unique commands. |
| 7303 | switch ((Bits >> 24) & 31) { |
| 7304 | default: llvm_unreachable("Invalid command number."); |
| 7305 | case 0: |
| 7306 | // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... |
| 7307 | printOperand(MI, OpNo: 1, STI, O); |
| 7308 | break; |
| 7309 | case 1: |
| 7310 | // CTTC1, MTTACX, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, ADDIUS5_MM, AND16_... |
| 7311 | return; |
| 7312 | break; |
| 7313 | case 2: |
| 7314 | // GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,... |
| 7315 | printOperand(MI, OpNo: 2, STI, O); |
| 7316 | break; |
| 7317 | case 3: |
| 7318 | // LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA... |
| 7319 | printMemOperand(MI, opNum: 1, STI, O); |
| 7320 | return; |
| 7321 | break; |
| 7322 | case 4: |
| 7323 | // MTTC0, DMTC0, DMTC2, DMTGC0, FORK, LSA_MMR6, MTC0, MTC0_MMR6, MTC2, MT... |
| 7324 | O << ", "; |
| 7325 | break; |
| 7326 | case 5: |
| 7327 | // MultRxRyRz16, MultuRxRyRz16 |
| 7328 | O << "\n\tmflo\t"; |
| 7329 | printOperand(MI, OpNo: 0, STI, O); |
| 7330 | return; |
| 7331 | break; |
| 7332 | case 6: |
| 7333 | // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... |
| 7334 | printOperand(MI, OpNo: 4, STI, O); |
| 7335 | break; |
| 7336 | case 7: |
| 7337 | // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... |
| 7338 | O << "\n\tmove\t"; |
| 7339 | printOperand(MI, OpNo: 0, STI, O); |
| 7340 | O << ", $t8"; |
| 7341 | return; |
| 7342 | break; |
| 7343 | case 8: |
| 7344 | // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM |
| 7345 | printMemOperandEA(MI, opNum: 1, STI, O); |
| 7346 | return; |
| 7347 | break; |
| 7348 | case 9: |
| 7349 | // BBIT0, BBIT032, BBIT1, BBIT132 |
| 7350 | printUImm<5>(MI, opNum: 1, STI, O); |
| 7351 | O << ", "; |
| 7352 | printBranchOperand(MI, Address, OpNo: 2, STI, O); |
| 7353 | return; |
| 7354 | break; |
| 7355 | case 10: |
| 7356 | // BC1EQZ, BC1EQZC_MMR6, BC1F, BC1FL, BC1F_MM, BC1NEZ, BC1NEZC_MMR6, BC1T... |
| 7357 | printBranchOperand(MI, Address, OpNo: 1, STI, O); |
| 7358 | break; |
| 7359 | case 11: |
| 7360 | // BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP |
| 7361 | printUImm<10>(MI, opNum: 1, STI, O); |
| 7362 | return; |
| 7363 | break; |
| 7364 | case 12: |
| 7365 | // DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM |
| 7366 | printUImm<16>(MI, opNum: 1, STI, O); |
| 7367 | return; |
| 7368 | break; |
| 7369 | case 13: |
| 7370 | // GINVT, GINVT_MMR6 |
| 7371 | printUImm<2>(MI, opNum: 1, STI, O); |
| 7372 | return; |
| 7373 | break; |
| 7374 | case 14: |
| 7375 | // INSERT_B |
| 7376 | printUImm<4>(MI, opNum: 3, STI, O); |
| 7377 | O << "], "; |
| 7378 | printOperand(MI, OpNo: 2, STI, O); |
| 7379 | return; |
| 7380 | break; |
| 7381 | case 15: |
| 7382 | // INSERT_D |
| 7383 | printUImm<1>(MI, opNum: 3, STI, O); |
| 7384 | O << "], "; |
| 7385 | printOperand(MI, OpNo: 2, STI, O); |
| 7386 | return; |
| 7387 | break; |
| 7388 | case 16: |
| 7389 | // INSERT_H |
| 7390 | printUImm<3>(MI, opNum: 3, STI, O); |
| 7391 | O << "], "; |
| 7392 | printOperand(MI, OpNo: 2, STI, O); |
| 7393 | return; |
| 7394 | break; |
| 7395 | case 17: |
| 7396 | // INSERT_W |
| 7397 | printUImm<2>(MI, opNum: 3, STI, O); |
| 7398 | O << "], "; |
| 7399 | printOperand(MI, OpNo: 2, STI, O); |
| 7400 | return; |
| 7401 | break; |
| 7402 | case 18: |
| 7403 | // INSVE_B |
| 7404 | printUImm<4>(MI, opNum: 2, STI, O); |
| 7405 | O << "], "; |
| 7406 | printOperand(MI, OpNo: 3, STI, O); |
| 7407 | O << '['; |
| 7408 | printUImm<0>(MI, opNum: 4, STI, O); |
| 7409 | O << ']'; |
| 7410 | return; |
| 7411 | break; |
| 7412 | case 19: |
| 7413 | // INSVE_D |
| 7414 | printUImm<1>(MI, opNum: 2, STI, O); |
| 7415 | O << "], "; |
| 7416 | printOperand(MI, OpNo: 3, STI, O); |
| 7417 | O << '['; |
| 7418 | printUImm<0>(MI, opNum: 4, STI, O); |
| 7419 | O << ']'; |
| 7420 | return; |
| 7421 | break; |
| 7422 | case 20: |
| 7423 | // INSVE_H |
| 7424 | printUImm<3>(MI, opNum: 2, STI, O); |
| 7425 | O << "], "; |
| 7426 | printOperand(MI, OpNo: 3, STI, O); |
| 7427 | O << '['; |
| 7428 | printUImm<0>(MI, opNum: 4, STI, O); |
| 7429 | O << ']'; |
| 7430 | return; |
| 7431 | break; |
| 7432 | case 21: |
| 7433 | // INSVE_W |
| 7434 | printUImm<2>(MI, opNum: 2, STI, O); |
| 7435 | O << "], "; |
| 7436 | printOperand(MI, OpNo: 3, STI, O); |
| 7437 | O << '['; |
| 7438 | printUImm<0>(MI, opNum: 4, STI, O); |
| 7439 | O << ']'; |
| 7440 | return; |
| 7441 | break; |
| 7442 | case 22: |
| 7443 | // LWP_MM, SWP_MM |
| 7444 | printMemOperand(MI, opNum: 2, STI, O); |
| 7445 | return; |
| 7446 | break; |
| 7447 | case 23: |
| 7448 | // PREFX_MM |
| 7449 | O << '('; |
| 7450 | printOperand(MI, OpNo: 0, STI, O); |
| 7451 | O << ')'; |
| 7452 | return; |
| 7453 | break; |
| 7454 | case 24: |
| 7455 | // RDDSP_MM, WRDSP_MM |
| 7456 | printUImm<7>(MI, opNum: 1, STI, O); |
| 7457 | return; |
| 7458 | break; |
| 7459 | case 25: |
| 7460 | // REPL_QB, REPL_QB_MM |
| 7461 | printUImm<8>(MI, opNum: 1, STI, O); |
| 7462 | return; |
| 7463 | break; |
| 7464 | } |
| 7465 | |
| 7466 | |
| 7467 | // Fragment 3 encoded into 5 bits for 18 unique commands. |
| 7468 | switch ((Bits >> 29) & 31) { |
| 7469 | default: llvm_unreachable("Invalid command number."); |
| 7470 | case 0: |
| 7471 | // ABSMacro, CFTC1, JalTwoReg, LoadAddrImm32, LoadAddrImm64, LoadImm32, L... |
| 7472 | return; |
| 7473 | break; |
| 7474 | case 1: |
| 7475 | // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... |
| 7476 | O << ", "; |
| 7477 | break; |
| 7478 | case 2: |
| 7479 | // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... |
| 7480 | O << "\n\tbteqz\t"; |
| 7481 | printBranchOperand(MI, Address, OpNo: 2, STI, O); |
| 7482 | return; |
| 7483 | break; |
| 7484 | case 3: |
| 7485 | // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... |
| 7486 | O << "\n\tbtnez\t"; |
| 7487 | printBranchOperand(MI, Address, OpNo: 2, STI, O); |
| 7488 | return; |
| 7489 | break; |
| 7490 | case 4: |
| 7491 | // GotPrologue16 |
| 7492 | O << "\n\taddiu\t"; |
| 7493 | printOperand(MI, OpNo: 1, STI, O); |
| 7494 | O << ", $pc, "; |
| 7495 | printOperand(MI, OpNo: 3, STI, O); |
| 7496 | O << "\n "; |
| 7497 | return; |
| 7498 | break; |
| 7499 | case 5: |
| 7500 | // MTTC0, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, MTGC0_MM, M... |
| 7501 | printUImm<3>(MI, opNum: 2, STI, O); |
| 7502 | return; |
| 7503 | break; |
| 7504 | case 6: |
| 7505 | // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... |
| 7506 | O << "\n\tbteqz\t.+4\n\tmove "; |
| 7507 | printOperand(MI, OpNo: 1, STI, O); |
| 7508 | O << ", "; |
| 7509 | printOperand(MI, OpNo: 2, STI, O); |
| 7510 | return; |
| 7511 | break; |
| 7512 | case 7: |
| 7513 | // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... |
| 7514 | O << "\n\tbtnez\t.+4\n\tmove "; |
| 7515 | printOperand(MI, OpNo: 1, STI, O); |
| 7516 | O << ", "; |
| 7517 | printOperand(MI, OpNo: 2, STI, O); |
| 7518 | return; |
| 7519 | break; |
| 7520 | case 8: |
| 7521 | // AddiuRxRxImm16, LwRxPcTcp16 |
| 7522 | O << "\t# 16 bit inst"; |
| 7523 | return; |
| 7524 | break; |
| 7525 | case 9: |
| 7526 | // BeqzRxImm16, BnezRxImm16 |
| 7527 | O << " # 16 bit inst"; |
| 7528 | return; |
| 7529 | break; |
| 7530 | case 10: |
| 7531 | // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... |
| 7532 | O << '['; |
| 7533 | break; |
| 7534 | case 11: |
| 7535 | // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 |
| 7536 | O << " \t# 16 bit inst"; |
| 7537 | return; |
| 7538 | break; |
| 7539 | case 12: |
| 7540 | // DSLL64_32 |
| 7541 | O << ", 32"; |
| 7542 | return; |
| 7543 | break; |
| 7544 | case 13: |
| 7545 | // FORK |
| 7546 | printOperand(MI, OpNo: 2, STI, O); |
| 7547 | return; |
| 7548 | break; |
| 7549 | case 14: |
| 7550 | // LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ... |
| 7551 | O << '('; |
| 7552 | printOperand(MI, OpNo: 1, STI, O); |
| 7553 | O << ')'; |
| 7554 | return; |
| 7555 | break; |
| 7556 | case 15: |
| 7557 | // LSA_MMR6 |
| 7558 | printOperand(MI, OpNo: 0, STI, O); |
| 7559 | O << ", "; |
| 7560 | printUImm<2, 1>(MI, opNum: 3, STI, O); |
| 7561 | return; |
| 7562 | break; |
| 7563 | case 16: |
| 7564 | // MTTR |
| 7565 | printUImm<1>(MI, opNum: 2, STI, O); |
| 7566 | O << ", "; |
| 7567 | printUImm<3>(MI, opNum: 3, STI, O); |
| 7568 | O << ", "; |
| 7569 | printUImm<1>(MI, opNum: 4, STI, O); |
| 7570 | return; |
| 7571 | break; |
| 7572 | case 17: |
| 7573 | // SLL64_32, SLL64_64 |
| 7574 | O << ", 0"; |
| 7575 | return; |
| 7576 | break; |
| 7577 | } |
| 7578 | |
| 7579 | |
| 7580 | // Fragment 4 encoded into 5 bits for 21 unique commands. |
| 7581 | switch ((Bits >> 34) & 31) { |
| 7582 | default: llvm_unreachable("Invalid command number."); |
| 7583 | case 0: |
| 7584 | // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... |
| 7585 | printBranchOperand(MI, Address, OpNo: 2, STI, O); |
| 7586 | return; |
| 7587 | break; |
| 7588 | case 1: |
| 7589 | // DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,... |
| 7590 | printOperand(MI, OpNo: 2, STI, O); |
| 7591 | break; |
| 7592 | case 2: |
| 7593 | // MFTC0, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0, DMFC2, DM... |
| 7594 | printUImm<3>(MI, opNum: 2, STI, O); |
| 7595 | break; |
| 7596 | case 3: |
| 7597 | // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG... |
| 7598 | printUImm<5>(MI, opNum: 2, STI, O); |
| 7599 | break; |
| 7600 | case 4: |
| 7601 | // ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, SHF_H, SHF_W, ... |
| 7602 | printUImm<8>(MI, opNum: 2, STI, O); |
| 7603 | return; |
| 7604 | break; |
| 7605 | case 5: |
| 7606 | // ANDI_MMR6, ANDi, ANDi64, ANDi_MM, AUI, AUI_MMR6, DAHI, DATI, DAUI, ORI... |
| 7607 | printUImm<16>(MI, opNum: 2, STI, O); |
| 7608 | return; |
| 7609 | break; |
| 7610 | case 6: |
| 7611 | // BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W |
| 7612 | printUImm<2>(MI, opNum: 2, STI, O); |
| 7613 | break; |
| 7614 | case 7: |
| 7615 | // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D... |
| 7616 | printUImm<6>(MI, opNum: 2, STI, O); |
| 7617 | break; |
| 7618 | case 8: |
| 7619 | // BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_... |
| 7620 | printUImm<4>(MI, opNum: 2, STI, O); |
| 7621 | break; |
| 7622 | case 9: |
| 7623 | // BINSLI_B, BINSRI_B, SLDI_H |
| 7624 | printUImm<3>(MI, opNum: 3, STI, O); |
| 7625 | break; |
| 7626 | case 10: |
| 7627 | // BINSLI_D, BINSRI_D |
| 7628 | printUImm<6>(MI, opNum: 3, STI, O); |
| 7629 | return; |
| 7630 | break; |
| 7631 | case 11: |
| 7632 | // BINSLI_H, BINSRI_H, SLDI_B |
| 7633 | printUImm<4>(MI, opNum: 3, STI, O); |
| 7634 | break; |
| 7635 | case 12: |
| 7636 | // BINSLI_W, BINSRI_W |
| 7637 | printUImm<5>(MI, opNum: 3, STI, O); |
| 7638 | return; |
| 7639 | break; |
| 7640 | case 13: |
| 7641 | // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... |
| 7642 | printOperand(MI, OpNo: 3, STI, O); |
| 7643 | break; |
| 7644 | case 14: |
| 7645 | // BMNZI_B, BMZI_B, BSELI_B |
| 7646 | printUImm<8>(MI, opNum: 3, STI, O); |
| 7647 | return; |
| 7648 | break; |
| 7649 | case 15: |
| 7650 | // COPY_S_D, MFTR, SPLATI_D |
| 7651 | printUImm<1>(MI, opNum: 2, STI, O); |
| 7652 | break; |
| 7653 | case 16: |
| 7654 | // DEXTU, DINSU |
| 7655 | printUImm<5, 32>(MI, opNum: 2, STI, O); |
| 7656 | O << ", "; |
| 7657 | break; |
| 7658 | case 17: |
| 7659 | // FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6 |
| 7660 | printOperand(MI, OpNo: 1, STI, O); |
| 7661 | return; |
| 7662 | break; |
| 7663 | case 18: |
| 7664 | // SLDI_D |
| 7665 | printUImm<1>(MI, opNum: 3, STI, O); |
| 7666 | O << ']'; |
| 7667 | return; |
| 7668 | break; |
| 7669 | case 19: |
| 7670 | // SLDI_W |
| 7671 | printUImm<2>(MI, opNum: 3, STI, O); |
| 7672 | O << ']'; |
| 7673 | return; |
| 7674 | break; |
| 7675 | case 20: |
| 7676 | // TEQ, TGE, TGEU, TLT, TLTU, TNE |
| 7677 | printUImm<10>(MI, opNum: 2, STI, O); |
| 7678 | return; |
| 7679 | break; |
| 7680 | } |
| 7681 | |
| 7682 | |
| 7683 | // Fragment 5 encoded into 3 bits for 5 unique commands. |
| 7684 | switch ((Bits >> 39) & 7) { |
| 7685 | default: llvm_unreachable("Invalid command number."); |
| 7686 | case 0: |
| 7687 | // DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,... |
| 7688 | return; |
| 7689 | break; |
| 7690 | case 1: |
| 7691 | // ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN, DEXT, DE... |
| 7692 | O << ", "; |
| 7693 | break; |
| 7694 | case 2: |
| 7695 | // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... |
| 7696 | O << ']'; |
| 7697 | return; |
| 7698 | break; |
| 7699 | case 3: |
| 7700 | // DEXTU |
| 7701 | printUImm<5, 1>(MI, opNum: 3, STI, O); |
| 7702 | return; |
| 7703 | break; |
| 7704 | case 4: |
| 7705 | // DINSU |
| 7706 | printUImm<6>(MI, opNum: 3, STI, O); |
| 7707 | return; |
| 7708 | break; |
| 7709 | } |
| 7710 | |
| 7711 | |
| 7712 | // Fragment 6 encoded into 4 bits for 10 unique commands. |
| 7713 | switch ((Bits >> 42) & 15) { |
| 7714 | default: llvm_unreachable("Invalid command number."); |
| 7715 | case 0: |
| 7716 | // ALIGN, ALIGN_MMR6 |
| 7717 | printUImm<2>(MI, opNum: 3, STI, O); |
| 7718 | return; |
| 7719 | break; |
| 7720 | case 1: |
| 7721 | // CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32 |
| 7722 | printUImm<5>(MI, opNum: 3, STI, O); |
| 7723 | return; |
| 7724 | break; |
| 7725 | case 2: |
| 7726 | // DALIGN, MFTR |
| 7727 | printUImm<3>(MI, opNum: 3, STI, O); |
| 7728 | break; |
| 7729 | case 3: |
| 7730 | // DEXT |
| 7731 | printUImm<6, 1>(MI, opNum: 3, STI, O); |
| 7732 | return; |
| 7733 | break; |
| 7734 | case 4: |
| 7735 | // DEXT64_32, EXT, EXT_MM, EXT_MMR6 |
| 7736 | printUImm<5, 1>(MI, opNum: 3, STI, O); |
| 7737 | return; |
| 7738 | break; |
| 7739 | case 5: |
| 7740 | // DEXTM |
| 7741 | printUImm<5, 33>(MI, opNum: 3, STI, O); |
| 7742 | return; |
| 7743 | break; |
| 7744 | case 6: |
| 7745 | // DINS, INS, INS_MM, INS_MMR6 |
| 7746 | printUImm<6>(MI, opNum: 3, STI, O); |
| 7747 | return; |
| 7748 | break; |
| 7749 | case 7: |
| 7750 | // DINSM |
| 7751 | printUImm<6, 2>(MI, opNum: 3, STI, O); |
| 7752 | return; |
| 7753 | break; |
| 7754 | case 8: |
| 7755 | // DLSA, DLSA_R6, LSA, LSA_R6 |
| 7756 | printUImm<2, 1>(MI, opNum: 3, STI, O); |
| 7757 | return; |
| 7758 | break; |
| 7759 | case 9: |
| 7760 | // MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MOVEP_MM, MOVEP_MM... |
| 7761 | printOperand(MI, OpNo: 3, STI, O); |
| 7762 | return; |
| 7763 | break; |
| 7764 | } |
| 7765 | |
| 7766 | |
| 7767 | // Fragment 7 encoded into 1 bits for 2 unique commands. |
| 7768 | if ((Bits >> 46) & 1) { |
| 7769 | // MFTR |
| 7770 | O << ", "; |
| 7771 | printUImm<1>(MI, opNum: 4, STI, O); |
| 7772 | return; |
| 7773 | } else { |
| 7774 | // DALIGN |
| 7775 | return; |
| 7776 | } |
| 7777 | |
| 7778 | } |
| 7779 | |
| 7780 | |
| 7781 | /// getRegisterName - This method is automatically generated by tblgen |
| 7782 | /// from the register set description. This returns the assembler name |
| 7783 | /// for the specified register. |
| 7784 | const char *MipsInstPrinter::getRegisterName(MCRegister Reg) { |
| 7785 | unsigned RegNo = Reg.id(); |
| 7786 | assert(RegNo && RegNo < 442 && "Invalid register number!"); |
| 7787 | |
| 7788 | |
| 7789 | #ifdef __GNUC__ |
| 7790 | #pragma GCC diagnostic push |
| 7791 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 7792 | #endif |
| 7793 | static const char AsmStrs[] = { |
| 7794 | /* 0 */ "f10\000" |
| 7795 | /* 4 */ "w10\000" |
| 7796 | /* 8 */ "f20\000" |
| 7797 | /* 12 */ "DSPOutFlag20\000" |
| 7798 | /* 25 */ "w20\000" |
| 7799 | /* 29 */ "f30\000" |
| 7800 | /* 33 */ "w30\000" |
| 7801 | /* 37 */ "ac0\000" |
| 7802 | /* 41 */ "fcc0\000" |
| 7803 | /* 46 */ "f0\000" |
| 7804 | /* 49 */ "mpl0\000" |
| 7805 | /* 54 */ "p0\000" |
| 7806 | /* 57 */ "w0\000" |
| 7807 | /* 60 */ "f11\000" |
| 7808 | /* 64 */ "w11\000" |
| 7809 | /* 68 */ "f21\000" |
| 7810 | /* 72 */ "DSPOutFlag21\000" |
| 7811 | /* 85 */ "w21\000" |
| 7812 | /* 89 */ "f31\000" |
| 7813 | /* 93 */ "w31\000" |
| 7814 | /* 97 */ "ac1\000" |
| 7815 | /* 101 */ "fcc1\000" |
| 7816 | /* 106 */ "f1\000" |
| 7817 | /* 109 */ "mpl1\000" |
| 7818 | /* 114 */ "p1\000" |
| 7819 | /* 117 */ "w1\000" |
| 7820 | /* 120 */ "f12\000" |
| 7821 | /* 124 */ "w12\000" |
| 7822 | /* 128 */ "f22\000" |
| 7823 | /* 132 */ "DSPOutFlag22\000" |
| 7824 | /* 145 */ "w22\000" |
| 7825 | /* 149 */ "ac2\000" |
| 7826 | /* 153 */ "fcc2\000" |
| 7827 | /* 158 */ "f2\000" |
| 7828 | /* 161 */ "mpl2\000" |
| 7829 | /* 166 */ "p2\000" |
| 7830 | /* 169 */ "w2\000" |
| 7831 | /* 172 */ "f13\000" |
| 7832 | /* 176 */ "w13\000" |
| 7833 | /* 180 */ "f23\000" |
| 7834 | /* 184 */ "DSPOutFlag23\000" |
| 7835 | /* 197 */ "w23\000" |
| 7836 | /* 201 */ "ac3\000" |
| 7837 | /* 205 */ "fcc3\000" |
| 7838 | /* 210 */ "f3\000" |
| 7839 | /* 213 */ "w3\000" |
| 7840 | /* 216 */ "f14\000" |
| 7841 | /* 220 */ "w14\000" |
| 7842 | /* 224 */ "f24\000" |
| 7843 | /* 228 */ "w24\000" |
| 7844 | /* 232 */ "fcc4\000" |
| 7845 | /* 237 */ "f4\000" |
| 7846 | /* 240 */ "w4\000" |
| 7847 | /* 243 */ "f15\000" |
| 7848 | /* 247 */ "w15\000" |
| 7849 | /* 251 */ "f25\000" |
| 7850 | /* 255 */ "w25\000" |
| 7851 | /* 259 */ "fcc5\000" |
| 7852 | /* 264 */ "f5\000" |
| 7853 | /* 267 */ "w5\000" |
| 7854 | /* 270 */ "f16\000" |
| 7855 | /* 274 */ "w16\000" |
| 7856 | /* 278 */ "f26\000" |
| 7857 | /* 282 */ "w26\000" |
| 7858 | /* 286 */ "fcc6\000" |
| 7859 | /* 291 */ "f6\000" |
| 7860 | /* 294 */ "w6\000" |
| 7861 | /* 297 */ "f17\000" |
| 7862 | /* 301 */ "w17\000" |
| 7863 | /* 305 */ "f27\000" |
| 7864 | /* 309 */ "w27\000" |
| 7865 | /* 313 */ "fcc7\000" |
| 7866 | /* 318 */ "f7\000" |
| 7867 | /* 321 */ "w7\000" |
| 7868 | /* 324 */ "f18\000" |
| 7869 | /* 328 */ "w18\000" |
| 7870 | /* 332 */ "f28\000" |
| 7871 | /* 336 */ "w28\000" |
| 7872 | /* 340 */ "f8\000" |
| 7873 | /* 343 */ "w8\000" |
| 7874 | /* 346 */ "DSPOutFlag16_19\000" |
| 7875 | /* 362 */ "f19\000" |
| 7876 | /* 366 */ "w19\000" |
| 7877 | /* 370 */ "f29\000" |
| 7878 | /* 374 */ "w29\000" |
| 7879 | /* 378 */ "f9\000" |
| 7880 | /* 381 */ "w9\000" |
| 7881 | /* 384 */ "DSPEFI\000" |
| 7882 | /* 391 */ "ra\000" |
| 7883 | /* 394 */ "hwr_cc\000" |
| 7884 | /* 401 */ "pc\000" |
| 7885 | /* 404 */ "DSPCCond\000" |
| 7886 | /* 413 */ "DSPOutFlag\000" |
| 7887 | /* 424 */ "hi\000" |
| 7888 | /* 427 */ "hwr_cpunum\000" |
| 7889 | /* 438 */ "lo\000" |
| 7890 | /* 441 */ "zero\000" |
| 7891 | /* 446 */ "hwr_synci_step\000" |
| 7892 | /* 461 */ "fp\000" |
| 7893 | /* 464 */ "gp\000" |
| 7894 | /* 467 */ "sp\000" |
| 7895 | /* 470 */ "hwr_ccres\000" |
| 7896 | /* 480 */ "DSPPos\000" |
| 7897 | /* 487 */ "DSPSCount\000" |
| 7898 | /* 497 */ "DSPCarry\000" |
| 7899 | }; |
| 7900 | #ifdef __GNUC__ |
| 7901 | #pragma GCC diagnostic pop |
| 7902 | #endif |
| 7903 | |
| 7904 | static const uint16_t RegAsmOffset[] = { |
| 7905 | 62, 404, 497, 384, 413, 480, 487, 461, 464, 122, 62, 2, 272, 218, |
| 7906 | 245, 174, 299, 401, 391, 467, 441, 218, 245, 272, 299, 37, 97, 149, |
| 7907 | 201, 62, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 2, 62, |
| 7908 | 122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, 245, |
| 7909 | 272, 299, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, |
| 7910 | 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 1, 61, |
| 7911 | 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, |
| 7912 | 279, 306, 333, 371, 30, 90, 1, 61, 121, 173, 217, 244, 271, 298, |
| 7913 | 325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, |
| 7914 | 46, 158, 237, 291, 340, 0, 120, 216, 270, 324, 8, 128, 224, 278, |
| 7915 | 332, 29, 12, 72, 132, 184, 46, 106, 158, 210, 237, 264, 291, 318, |
| 7916 | 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, |
| 7917 | 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 41, 101, 153, 205, |
| 7918 | 232, 259, 286, 313, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, |
| 7919 | 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, |
| 7920 | 225, 252, 279, 306, 333, 371, 30, 90, 461, 46, 106, 158, 210, 237, |
| 7921 | 264, 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, |
| 7922 | 362, 8, 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 464, |
| 7923 | 37, 97, 149, 201, 427, 446, 394, 470, 218, 245, 272, 299, 326, 360, |
| 7924 | 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, |
| 7925 | 225, 252, 279, 306, 333, 371, 30, 90, 279, 306, 37, 97, 149, 201, |
| 7926 | 49, 109, 161, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, |
| 7927 | 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 54, |
| 7928 | 114, 166, 391, 271, 298, 325, 359, 9, 69, 129, 181, 467, 326, 360, |
| 7929 | 1, 61, 121, 173, 217, 244, 225, 252, 122, 174, 57, 117, 169, 213, |
| 7930 | 240, 267, 294, 321, 343, 381, 4, 64, 124, 176, 220, 247, 274, 301, |
| 7931 | 328, 366, 25, 85, 145, 197, 228, 255, 282, 309, 336, 374, 33, 93, |
| 7932 | 441, 218, 245, 272, 299, 37, 46, 106, 158, 210, 237, 264, 291, 318, |
| 7933 | 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, |
| 7934 | 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 346, 424, 279, 306, |
| 7935 | 438, 271, 298, 325, 359, 9, 69, 129, 181, 326, 360, 1, 61, 121, |
| 7936 | 173, 217, 244, 225, 252, 122, 174, |
| 7937 | }; |
| 7938 | |
| 7939 | assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && |
| 7940 | "Invalid alt name index for register!"); |
| 7941 | return AsmStrs+RegAsmOffset[RegNo-1]; |
| 7942 | } |
| 7943 | |
| 7944 | #ifdef PRINT_ALIAS_INSTR |
| 7945 | #undef PRINT_ALIAS_INSTR |
| 7946 | |
| 7947 | bool MipsInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| 7948 | static const PatternsForOpcode OpToPatterns[] = { |
| 7949 | {.Opcode: Mips::MFTACX, .PatternStart: 0, .NumPatterns: 1 }, |
| 7950 | {.Opcode: Mips::MFTC0, .PatternStart: 1, .NumPatterns: 1 }, |
| 7951 | {.Opcode: Mips::MFTHI, .PatternStart: 2, .NumPatterns: 1 }, |
| 7952 | {.Opcode: Mips::MFTLO, .PatternStart: 3, .NumPatterns: 1 }, |
| 7953 | {.Opcode: Mips::MTTACX, .PatternStart: 4, .NumPatterns: 1 }, |
| 7954 | {.Opcode: Mips::MTTC0, .PatternStart: 5, .NumPatterns: 1 }, |
| 7955 | {.Opcode: Mips::MTTHI, .PatternStart: 6, .NumPatterns: 1 }, |
| 7956 | {.Opcode: Mips::MTTLO, .PatternStart: 7, .NumPatterns: 1 }, |
| 7957 | {.Opcode: Mips::NORImm, .PatternStart: 8, .NumPatterns: 1 }, |
| 7958 | {.Opcode: Mips::NORImm64, .PatternStart: 9, .NumPatterns: 1 }, |
| 7959 | {.Opcode: Mips::SLTImm64, .PatternStart: 10, .NumPatterns: 1 }, |
| 7960 | {.Opcode: Mips::SLTUImm64, .PatternStart: 11, .NumPatterns: 1 }, |
| 7961 | {.Opcode: Mips::ADDIUPC, .PatternStart: 12, .NumPatterns: 1 }, |
| 7962 | {.Opcode: Mips::ADDIUPC_MMR6, .PatternStart: 13, .NumPatterns: 1 }, |
| 7963 | {.Opcode: Mips::ADDu, .PatternStart: 14, .NumPatterns: 1 }, |
| 7964 | {.Opcode: Mips::BC1F, .PatternStart: 15, .NumPatterns: 1 }, |
| 7965 | {.Opcode: Mips::BC1FL, .PatternStart: 16, .NumPatterns: 1 }, |
| 7966 | {.Opcode: Mips::BC1F_MM, .PatternStart: 17, .NumPatterns: 1 }, |
| 7967 | {.Opcode: Mips::BC1T, .PatternStart: 18, .NumPatterns: 1 }, |
| 7968 | {.Opcode: Mips::BC1TL, .PatternStart: 19, .NumPatterns: 1 }, |
| 7969 | {.Opcode: Mips::BC1T_MM, .PatternStart: 20, .NumPatterns: 1 }, |
| 7970 | {.Opcode: Mips::BEQL, .PatternStart: 21, .NumPatterns: 1 }, |
| 7971 | {.Opcode: Mips::BGEZAL, .PatternStart: 22, .NumPatterns: 1 }, |
| 7972 | {.Opcode: Mips::BGEZAL_MM, .PatternStart: 23, .NumPatterns: 1 }, |
| 7973 | {.Opcode: Mips::BLTZAL, .PatternStart: 24, .NumPatterns: 1 }, |
| 7974 | {.Opcode: Mips::BNEL, .PatternStart: 25, .NumPatterns: 1 }, |
| 7975 | {.Opcode: Mips::BREAK, .PatternStart: 26, .NumPatterns: 2 }, |
| 7976 | {.Opcode: Mips::BREAK_MM, .PatternStart: 28, .NumPatterns: 2 }, |
| 7977 | {.Opcode: Mips::C_EQ_D32, .PatternStart: 30, .NumPatterns: 1 }, |
| 7978 | {.Opcode: Mips::C_EQ_D32_MM, .PatternStart: 31, .NumPatterns: 1 }, |
| 7979 | {.Opcode: Mips::C_EQ_D64, .PatternStart: 32, .NumPatterns: 1 }, |
| 7980 | {.Opcode: Mips::C_EQ_D64_MM, .PatternStart: 33, .NumPatterns: 1 }, |
| 7981 | {.Opcode: Mips::C_EQ_S, .PatternStart: 34, .NumPatterns: 1 }, |
| 7982 | {.Opcode: Mips::C_EQ_S_MM, .PatternStart: 35, .NumPatterns: 1 }, |
| 7983 | {.Opcode: Mips::C_F_D32, .PatternStart: 36, .NumPatterns: 1 }, |
| 7984 | {.Opcode: Mips::C_F_D32_MM, .PatternStart: 37, .NumPatterns: 1 }, |
| 7985 | {.Opcode: Mips::C_F_D64, .PatternStart: 38, .NumPatterns: 1 }, |
| 7986 | {.Opcode: Mips::C_F_D64_MM, .PatternStart: 39, .NumPatterns: 1 }, |
| 7987 | {.Opcode: Mips::C_F_S, .PatternStart: 40, .NumPatterns: 1 }, |
| 7988 | {.Opcode: Mips::C_F_S_MM, .PatternStart: 41, .NumPatterns: 1 }, |
| 7989 | {.Opcode: Mips::C_LE_D32, .PatternStart: 42, .NumPatterns: 1 }, |
| 7990 | {.Opcode: Mips::C_LE_D32_MM, .PatternStart: 43, .NumPatterns: 1 }, |
| 7991 | {.Opcode: Mips::C_LE_D64, .PatternStart: 44, .NumPatterns: 1 }, |
| 7992 | {.Opcode: Mips::C_LE_D64_MM, .PatternStart: 45, .NumPatterns: 1 }, |
| 7993 | {.Opcode: Mips::C_LE_S, .PatternStart: 46, .NumPatterns: 1 }, |
| 7994 | {.Opcode: Mips::C_LE_S_MM, .PatternStart: 47, .NumPatterns: 1 }, |
| 7995 | {.Opcode: Mips::C_LT_D32, .PatternStart: 48, .NumPatterns: 1 }, |
| 7996 | {.Opcode: Mips::C_LT_D32_MM, .PatternStart: 49, .NumPatterns: 1 }, |
| 7997 | {.Opcode: Mips::C_LT_D64, .PatternStart: 50, .NumPatterns: 1 }, |
| 7998 | {.Opcode: Mips::C_LT_D64_MM, .PatternStart: 51, .NumPatterns: 1 }, |
| 7999 | {.Opcode: Mips::C_LT_S, .PatternStart: 52, .NumPatterns: 1 }, |
| 8000 | {.Opcode: Mips::C_LT_S_MM, .PatternStart: 53, .NumPatterns: 1 }, |
| 8001 | {.Opcode: Mips::C_NGE_D32, .PatternStart: 54, .NumPatterns: 1 }, |
| 8002 | {.Opcode: Mips::C_NGE_D32_MM, .PatternStart: 55, .NumPatterns: 1 }, |
| 8003 | {.Opcode: Mips::C_NGE_D64, .PatternStart: 56, .NumPatterns: 1 }, |
| 8004 | {.Opcode: Mips::C_NGE_D64_MM, .PatternStart: 57, .NumPatterns: 1 }, |
| 8005 | {.Opcode: Mips::C_NGE_S, .PatternStart: 58, .NumPatterns: 1 }, |
| 8006 | {.Opcode: Mips::C_NGE_S_MM, .PatternStart: 59, .NumPatterns: 1 }, |
| 8007 | {.Opcode: Mips::C_NGLE_D32, .PatternStart: 60, .NumPatterns: 1 }, |
| 8008 | {.Opcode: Mips::C_NGLE_D32_MM, .PatternStart: 61, .NumPatterns: 1 }, |
| 8009 | {.Opcode: Mips::C_NGLE_D64, .PatternStart: 62, .NumPatterns: 1 }, |
| 8010 | {.Opcode: Mips::C_NGLE_D64_MM, .PatternStart: 63, .NumPatterns: 1 }, |
| 8011 | {.Opcode: Mips::C_NGLE_S, .PatternStart: 64, .NumPatterns: 1 }, |
| 8012 | {.Opcode: Mips::C_NGLE_S_MM, .PatternStart: 65, .NumPatterns: 1 }, |
| 8013 | {.Opcode: Mips::C_NGL_D32, .PatternStart: 66, .NumPatterns: 1 }, |
| 8014 | {.Opcode: Mips::C_NGL_D32_MM, .PatternStart: 67, .NumPatterns: 1 }, |
| 8015 | {.Opcode: Mips::C_NGL_D64, .PatternStart: 68, .NumPatterns: 1 }, |
| 8016 | {.Opcode: Mips::C_NGL_D64_MM, .PatternStart: 69, .NumPatterns: 1 }, |
| 8017 | {.Opcode: Mips::C_NGL_S, .PatternStart: 70, .NumPatterns: 1 }, |
| 8018 | {.Opcode: Mips::C_NGL_S_MM, .PatternStart: 71, .NumPatterns: 1 }, |
| 8019 | {.Opcode: Mips::C_NGT_D32, .PatternStart: 72, .NumPatterns: 1 }, |
| 8020 | {.Opcode: Mips::C_NGT_D32_MM, .PatternStart: 73, .NumPatterns: 1 }, |
| 8021 | {.Opcode: Mips::C_NGT_D64, .PatternStart: 74, .NumPatterns: 1 }, |
| 8022 | {.Opcode: Mips::C_NGT_D64_MM, .PatternStart: 75, .NumPatterns: 1 }, |
| 8023 | {.Opcode: Mips::C_NGT_S, .PatternStart: 76, .NumPatterns: 1 }, |
| 8024 | {.Opcode: Mips::C_NGT_S_MM, .PatternStart: 77, .NumPatterns: 1 }, |
| 8025 | {.Opcode: Mips::C_OLE_D32, .PatternStart: 78, .NumPatterns: 1 }, |
| 8026 | {.Opcode: Mips::C_OLE_D32_MM, .PatternStart: 79, .NumPatterns: 1 }, |
| 8027 | {.Opcode: Mips::C_OLE_D64, .PatternStart: 80, .NumPatterns: 1 }, |
| 8028 | {.Opcode: Mips::C_OLE_D64_MM, .PatternStart: 81, .NumPatterns: 1 }, |
| 8029 | {.Opcode: Mips::C_OLE_S, .PatternStart: 82, .NumPatterns: 1 }, |
| 8030 | {.Opcode: Mips::C_OLE_S_MM, .PatternStart: 83, .NumPatterns: 1 }, |
| 8031 | {.Opcode: Mips::C_OLT_D32, .PatternStart: 84, .NumPatterns: 1 }, |
| 8032 | {.Opcode: Mips::C_OLT_D32_MM, .PatternStart: 85, .NumPatterns: 1 }, |
| 8033 | {.Opcode: Mips::C_OLT_D64, .PatternStart: 86, .NumPatterns: 1 }, |
| 8034 | {.Opcode: Mips::C_OLT_D64_MM, .PatternStart: 87, .NumPatterns: 1 }, |
| 8035 | {.Opcode: Mips::C_OLT_S, .PatternStart: 88, .NumPatterns: 1 }, |
| 8036 | {.Opcode: Mips::C_OLT_S_MM, .PatternStart: 89, .NumPatterns: 1 }, |
| 8037 | {.Opcode: Mips::C_SEQ_D32, .PatternStart: 90, .NumPatterns: 1 }, |
| 8038 | {.Opcode: Mips::C_SEQ_D32_MM, .PatternStart: 91, .NumPatterns: 1 }, |
| 8039 | {.Opcode: Mips::C_SEQ_D64, .PatternStart: 92, .NumPatterns: 1 }, |
| 8040 | {.Opcode: Mips::C_SEQ_D64_MM, .PatternStart: 93, .NumPatterns: 1 }, |
| 8041 | {.Opcode: Mips::C_SEQ_S, .PatternStart: 94, .NumPatterns: 1 }, |
| 8042 | {.Opcode: Mips::C_SEQ_S_MM, .PatternStart: 95, .NumPatterns: 1 }, |
| 8043 | {.Opcode: Mips::C_SF_D32, .PatternStart: 96, .NumPatterns: 1 }, |
| 8044 | {.Opcode: Mips::C_SF_D32_MM, .PatternStart: 97, .NumPatterns: 1 }, |
| 8045 | {.Opcode: Mips::C_SF_D64, .PatternStart: 98, .NumPatterns: 1 }, |
| 8046 | {.Opcode: Mips::C_SF_D64_MM, .PatternStart: 99, .NumPatterns: 1 }, |
| 8047 | {.Opcode: Mips::C_SF_S, .PatternStart: 100, .NumPatterns: 1 }, |
| 8048 | {.Opcode: Mips::C_SF_S_MM, .PatternStart: 101, .NumPatterns: 1 }, |
| 8049 | {.Opcode: Mips::C_UEQ_D32, .PatternStart: 102, .NumPatterns: 1 }, |
| 8050 | {.Opcode: Mips::C_UEQ_D32_MM, .PatternStart: 103, .NumPatterns: 1 }, |
| 8051 | {.Opcode: Mips::C_UEQ_D64, .PatternStart: 104, .NumPatterns: 1 }, |
| 8052 | {.Opcode: Mips::C_UEQ_D64_MM, .PatternStart: 105, .NumPatterns: 1 }, |
| 8053 | {.Opcode: Mips::C_UEQ_S, .PatternStart: 106, .NumPatterns: 1 }, |
| 8054 | {.Opcode: Mips::C_UEQ_S_MM, .PatternStart: 107, .NumPatterns: 1 }, |
| 8055 | {.Opcode: Mips::C_ULE_D32, .PatternStart: 108, .NumPatterns: 1 }, |
| 8056 | {.Opcode: Mips::C_ULE_D32_MM, .PatternStart: 109, .NumPatterns: 1 }, |
| 8057 | {.Opcode: Mips::C_ULE_D64, .PatternStart: 110, .NumPatterns: 1 }, |
| 8058 | {.Opcode: Mips::C_ULE_D64_MM, .PatternStart: 111, .NumPatterns: 1 }, |
| 8059 | {.Opcode: Mips::C_ULE_S, .PatternStart: 112, .NumPatterns: 1 }, |
| 8060 | {.Opcode: Mips::C_ULE_S_MM, .PatternStart: 113, .NumPatterns: 1 }, |
| 8061 | {.Opcode: Mips::C_ULT_D32, .PatternStart: 114, .NumPatterns: 1 }, |
| 8062 | {.Opcode: Mips::C_ULT_D32_MM, .PatternStart: 115, .NumPatterns: 1 }, |
| 8063 | {.Opcode: Mips::C_ULT_D64, .PatternStart: 116, .NumPatterns: 1 }, |
| 8064 | {.Opcode: Mips::C_ULT_D64_MM, .PatternStart: 117, .NumPatterns: 1 }, |
| 8065 | {.Opcode: Mips::C_ULT_S, .PatternStart: 118, .NumPatterns: 1 }, |
| 8066 | {.Opcode: Mips::C_ULT_S_MM, .PatternStart: 119, .NumPatterns: 1 }, |
| 8067 | {.Opcode: Mips::C_UN_D32, .PatternStart: 120, .NumPatterns: 1 }, |
| 8068 | {.Opcode: Mips::C_UN_D32_MM, .PatternStart: 121, .NumPatterns: 1 }, |
| 8069 | {.Opcode: Mips::C_UN_D64, .PatternStart: 122, .NumPatterns: 1 }, |
| 8070 | {.Opcode: Mips::C_UN_D64_MM, .PatternStart: 123, .NumPatterns: 1 }, |
| 8071 | {.Opcode: Mips::C_UN_S, .PatternStart: 124, .NumPatterns: 1 }, |
| 8072 | {.Opcode: Mips::C_UN_S_MM, .PatternStart: 125, .NumPatterns: 1 }, |
| 8073 | {.Opcode: Mips::DADDu, .PatternStart: 126, .NumPatterns: 1 }, |
| 8074 | {.Opcode: Mips::DI, .PatternStart: 127, .NumPatterns: 1 }, |
| 8075 | {.Opcode: Mips::DIV, .PatternStart: 128, .NumPatterns: 1 }, |
| 8076 | {.Opcode: Mips::DIVU, .PatternStart: 129, .NumPatterns: 1 }, |
| 8077 | {.Opcode: Mips::DI_MM, .PatternStart: 130, .NumPatterns: 1 }, |
| 8078 | {.Opcode: Mips::DI_MMR6, .PatternStart: 131, .NumPatterns: 1 }, |
| 8079 | {.Opcode: Mips::DMT, .PatternStart: 132, .NumPatterns: 1 }, |
| 8080 | {.Opcode: Mips::DSUB, .PatternStart: 133, .NumPatterns: 2 }, |
| 8081 | {.Opcode: Mips::DSUBu, .PatternStart: 135, .NumPatterns: 2 }, |
| 8082 | {.Opcode: Mips::DVPE, .PatternStart: 137, .NumPatterns: 1 }, |
| 8083 | {.Opcode: Mips::EI, .PatternStart: 138, .NumPatterns: 1 }, |
| 8084 | {.Opcode: Mips::EI_MM, .PatternStart: 139, .NumPatterns: 1 }, |
| 8085 | {.Opcode: Mips::EI_MMR6, .PatternStart: 140, .NumPatterns: 1 }, |
| 8086 | {.Opcode: Mips::EMT, .PatternStart: 141, .NumPatterns: 1 }, |
| 8087 | {.Opcode: Mips::EVPE, .PatternStart: 142, .NumPatterns: 1 }, |
| 8088 | {.Opcode: Mips::HYPCALL, .PatternStart: 143, .NumPatterns: 1 }, |
| 8089 | {.Opcode: Mips::HYPCALL_MM, .PatternStart: 144, .NumPatterns: 1 }, |
| 8090 | {.Opcode: Mips::JALR, .PatternStart: 145, .NumPatterns: 1 }, |
| 8091 | {.Opcode: Mips::JALR64, .PatternStart: 146, .NumPatterns: 1 }, |
| 8092 | {.Opcode: Mips::JALRC_HB_MMR6, .PatternStart: 147, .NumPatterns: 1 }, |
| 8093 | {.Opcode: Mips::JALRC_MMR6, .PatternStart: 148, .NumPatterns: 1 }, |
| 8094 | {.Opcode: Mips::JALR_HB, .PatternStart: 149, .NumPatterns: 1 }, |
| 8095 | {.Opcode: Mips::JALR_HB64, .PatternStart: 150, .NumPatterns: 1 }, |
| 8096 | {.Opcode: Mips::JIALC, .PatternStart: 151, .NumPatterns: 1 }, |
| 8097 | {.Opcode: Mips::JIALC64, .PatternStart: 152, .NumPatterns: 1 }, |
| 8098 | {.Opcode: Mips::JIC, .PatternStart: 153, .NumPatterns: 1 }, |
| 8099 | {.Opcode: Mips::JIC64, .PatternStart: 154, .NumPatterns: 1 }, |
| 8100 | {.Opcode: Mips::MOVE16_MM, .PatternStart: 155, .NumPatterns: 1 }, |
| 8101 | {.Opcode: Mips::Move32R16, .PatternStart: 156, .NumPatterns: 1 }, |
| 8102 | {.Opcode: Mips::OR, .PatternStart: 157, .NumPatterns: 1 }, |
| 8103 | {.Opcode: Mips::OR64, .PatternStart: 158, .NumPatterns: 1 }, |
| 8104 | {.Opcode: Mips::RDHWR, .PatternStart: 159, .NumPatterns: 1 }, |
| 8105 | {.Opcode: Mips::RDHWR64, .PatternStart: 160, .NumPatterns: 1 }, |
| 8106 | {.Opcode: Mips::RDHWR_MM, .PatternStart: 161, .NumPatterns: 1 }, |
| 8107 | {.Opcode: Mips::RDHWR_MMR6, .PatternStart: 162, .NumPatterns: 1 }, |
| 8108 | {.Opcode: Mips::SDBBP, .PatternStart: 163, .NumPatterns: 1 }, |
| 8109 | {.Opcode: Mips::SDBBP_MMR6, .PatternStart: 164, .NumPatterns: 1 }, |
| 8110 | {.Opcode: Mips::SDBBP_R6, .PatternStart: 165, .NumPatterns: 1 }, |
| 8111 | {.Opcode: Mips::SIGRIE, .PatternStart: 166, .NumPatterns: 1 }, |
| 8112 | {.Opcode: Mips::SIGRIE_MMR6, .PatternStart: 167, .NumPatterns: 1 }, |
| 8113 | {.Opcode: Mips::SLL, .PatternStart: 168, .NumPatterns: 1 }, |
| 8114 | {.Opcode: Mips::SLL_MM, .PatternStart: 169, .NumPatterns: 1 }, |
| 8115 | {.Opcode: Mips::SLL_MMR6, .PatternStart: 170, .NumPatterns: 1 }, |
| 8116 | {.Opcode: Mips::SUB, .PatternStart: 171, .NumPatterns: 2 }, |
| 8117 | {.Opcode: Mips::SUBU_MMR6, .PatternStart: 173, .NumPatterns: 2 }, |
| 8118 | {.Opcode: Mips::SUB_MM, .PatternStart: 175, .NumPatterns: 2 }, |
| 8119 | {.Opcode: Mips::SUB_MMR6, .PatternStart: 177, .NumPatterns: 2 }, |
| 8120 | {.Opcode: Mips::SUBu, .PatternStart: 179, .NumPatterns: 2 }, |
| 8121 | {.Opcode: Mips::SUBu_MM, .PatternStart: 181, .NumPatterns: 2 }, |
| 8122 | {.Opcode: Mips::SWSP_MM, .PatternStart: 183, .NumPatterns: 1 }, |
| 8123 | {.Opcode: Mips::SYNC, .PatternStart: 184, .NumPatterns: 1 }, |
| 8124 | {.Opcode: Mips::SYNC_MM, .PatternStart: 185, .NumPatterns: 1 }, |
| 8125 | {.Opcode: Mips::SYNC_MMR6, .PatternStart: 186, .NumPatterns: 1 }, |
| 8126 | {.Opcode: Mips::SYSCALL, .PatternStart: 187, .NumPatterns: 1 }, |
| 8127 | {.Opcode: Mips::SYSCALL_MM, .PatternStart: 188, .NumPatterns: 1 }, |
| 8128 | {.Opcode: Mips::TEQ, .PatternStart: 189, .NumPatterns: 1 }, |
| 8129 | {.Opcode: Mips::TEQ_MM, .PatternStart: 190, .NumPatterns: 1 }, |
| 8130 | {.Opcode: Mips::TGE, .PatternStart: 191, .NumPatterns: 1 }, |
| 8131 | {.Opcode: Mips::TGEU, .PatternStart: 192, .NumPatterns: 1 }, |
| 8132 | {.Opcode: Mips::TGEU_MM, .PatternStart: 193, .NumPatterns: 1 }, |
| 8133 | {.Opcode: Mips::TGE_MM, .PatternStart: 194, .NumPatterns: 1 }, |
| 8134 | {.Opcode: Mips::TLT, .PatternStart: 195, .NumPatterns: 1 }, |
| 8135 | {.Opcode: Mips::TLTU, .PatternStart: 196, .NumPatterns: 1 }, |
| 8136 | {.Opcode: Mips::TLTU_MM, .PatternStart: 197, .NumPatterns: 1 }, |
| 8137 | {.Opcode: Mips::TLT_MM, .PatternStart: 198, .NumPatterns: 1 }, |
| 8138 | {.Opcode: Mips::TNE, .PatternStart: 199, .NumPatterns: 1 }, |
| 8139 | {.Opcode: Mips::TNE_MM, .PatternStart: 200, .NumPatterns: 1 }, |
| 8140 | {.Opcode: Mips::WAIT_MM, .PatternStart: 201, .NumPatterns: 1 }, |
| 8141 | {.Opcode: Mips::WRDSP, .PatternStart: 202, .NumPatterns: 1 }, |
| 8142 | {.Opcode: Mips::WRDSP_MM, .PatternStart: 203, .NumPatterns: 1 }, |
| 8143 | {.Opcode: Mips::YIELD, .PatternStart: 204, .NumPatterns: 1 }, |
| 8144 | }; |
| 8145 | |
| 8146 | static const AliasPattern Patterns[] = { |
| 8147 | // Mips::MFTACX - 0 |
| 8148 | {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 2, .NumConds: 4 }, |
| 8149 | // Mips::MFTC0 - 1 |
| 8150 | {.AsmStrOffset: 10, .AliasCondStart: 4, .NumOperands: 3, .NumConds: 5 }, |
| 8151 | // Mips::MFTHI - 2 |
| 8152 | {.AsmStrOffset: 23, .AliasCondStart: 9, .NumOperands: 2, .NumConds: 4 }, |
| 8153 | // Mips::MFTLO - 3 |
| 8154 | {.AsmStrOffset: 32, .AliasCondStart: 13, .NumOperands: 2, .NumConds: 4 }, |
| 8155 | // Mips::MTTACX - 4 |
| 8156 | {.AsmStrOffset: 41, .AliasCondStart: 17, .NumOperands: 2, .NumConds: 4 }, |
| 8157 | // Mips::MTTC0 - 5 |
| 8158 | {.AsmStrOffset: 51, .AliasCondStart: 21, .NumOperands: 3, .NumConds: 5 }, |
| 8159 | // Mips::MTTHI - 6 |
| 8160 | {.AsmStrOffset: 64, .AliasCondStart: 26, .NumOperands: 2, .NumConds: 4 }, |
| 8161 | // Mips::MTTLO - 7 |
| 8162 | {.AsmStrOffset: 73, .AliasCondStart: 30, .NumOperands: 2, .NumConds: 4 }, |
| 8163 | // Mips::NORImm - 8 |
| 8164 | {.AsmStrOffset: 82, .AliasCondStart: 34, .NumOperands: 3, .NumConds: 3 }, |
| 8165 | // Mips::NORImm64 - 9 |
| 8166 | {.AsmStrOffset: 82, .AliasCondStart: 37, .NumOperands: 3, .NumConds: 3 }, |
| 8167 | // Mips::SLTImm64 - 10 |
| 8168 | {.AsmStrOffset: 93, .AliasCondStart: 40, .NumOperands: 3, .NumConds: 3 }, |
| 8169 | // Mips::SLTUImm64 - 11 |
| 8170 | {.AsmStrOffset: 104, .AliasCondStart: 43, .NumOperands: 3, .NumConds: 3 }, |
| 8171 | // Mips::ADDIUPC - 12 |
| 8172 | {.AsmStrOffset: 116, .AliasCondStart: 46, .NumOperands: 2, .NumConds: 3 }, |
| 8173 | // Mips::ADDIUPC_MMR6 - 13 |
| 8174 | {.AsmStrOffset: 116, .AliasCondStart: 49, .NumOperands: 2, .NumConds: 3 }, |
| 8175 | // Mips::ADDu - 14 |
| 8176 | {.AsmStrOffset: 128, .AliasCondStart: 52, .NumOperands: 3, .NumConds: 6 }, |
| 8177 | // Mips::BC1F - 15 |
| 8178 | {.AsmStrOffset: 140, .AliasCondStart: 58, .NumOperands: 2, .NumConds: 6 }, |
| 8179 | // Mips::BC1FL - 16 |
| 8180 | {.AsmStrOffset: 150, .AliasCondStart: 64, .NumOperands: 2, .NumConds: 7 }, |
| 8181 | // Mips::BC1F_MM - 17 |
| 8182 | {.AsmStrOffset: 140, .AliasCondStart: 71, .NumOperands: 2, .NumConds: 4 }, |
| 8183 | // Mips::BC1T - 18 |
| 8184 | {.AsmStrOffset: 161, .AliasCondStart: 75, .NumOperands: 2, .NumConds: 6 }, |
| 8185 | // Mips::BC1TL - 19 |
| 8186 | {.AsmStrOffset: 171, .AliasCondStart: 81, .NumOperands: 2, .NumConds: 7 }, |
| 8187 | // Mips::BC1T_MM - 20 |
| 8188 | {.AsmStrOffset: 161, .AliasCondStart: 88, .NumOperands: 2, .NumConds: 4 }, |
| 8189 | // Mips::BEQL - 21 |
| 8190 | {.AsmStrOffset: 182, .AliasCondStart: 92, .NumOperands: 3, .NumConds: 5 }, |
| 8191 | // Mips::BGEZAL - 22 |
| 8192 | {.AsmStrOffset: 197, .AliasCondStart: 97, .NumOperands: 2, .NumConds: 5 }, |
| 8193 | // Mips::BGEZAL_MM - 23 |
| 8194 | {.AsmStrOffset: 197, .AliasCondStart: 102, .NumOperands: 2, .NumConds: 3 }, |
| 8195 | // Mips::BLTZAL - 24 |
| 8196 | {.AsmStrOffset: 206, .AliasCondStart: 105, .NumOperands: 2, .NumConds: 5 }, |
| 8197 | // Mips::BNEL - 25 |
| 8198 | {.AsmStrOffset: 210, .AliasCondStart: 110, .NumOperands: 3, .NumConds: 5 }, |
| 8199 | // Mips::BREAK - 26 |
| 8200 | {.AsmStrOffset: 225, .AliasCondStart: 115, .NumOperands: 2, .NumConds: 4 }, |
| 8201 | {.AsmStrOffset: 231, .AliasCondStart: 119, .NumOperands: 2, .NumConds: 4 }, |
| 8202 | // Mips::BREAK_MM - 28 |
| 8203 | {.AsmStrOffset: 225, .AliasCondStart: 123, .NumOperands: 2, .NumConds: 3 }, |
| 8204 | {.AsmStrOffset: 231, .AliasCondStart: 126, .NumOperands: 2, .NumConds: 3 }, |
| 8205 | // Mips::C_EQ_D32 - 30 |
| 8206 | {.AsmStrOffset: 242, .AliasCondStart: 129, .NumOperands: 3, .NumConds: 9 }, |
| 8207 | // Mips::C_EQ_D32_MM - 31 |
| 8208 | {.AsmStrOffset: 242, .AliasCondStart: 138, .NumOperands: 3, .NumConds: 7 }, |
| 8209 | // Mips::C_EQ_D64 - 32 |
| 8210 | {.AsmStrOffset: 242, .AliasCondStart: 145, .NumOperands: 3, .NumConds: 9 }, |
| 8211 | // Mips::C_EQ_D64_MM - 33 |
| 8212 | {.AsmStrOffset: 242, .AliasCondStart: 154, .NumOperands: 3, .NumConds: 7 }, |
| 8213 | // Mips::C_EQ_S - 34 |
| 8214 | {.AsmStrOffset: 256, .AliasCondStart: 161, .NumOperands: 3, .NumConds: 8 }, |
| 8215 | // Mips::C_EQ_S_MM - 35 |
| 8216 | {.AsmStrOffset: 256, .AliasCondStart: 169, .NumOperands: 3, .NumConds: 6 }, |
| 8217 | // Mips::C_F_D32 - 36 |
| 8218 | {.AsmStrOffset: 270, .AliasCondStart: 175, .NumOperands: 3, .NumConds: 9 }, |
| 8219 | // Mips::C_F_D32_MM - 37 |
| 8220 | {.AsmStrOffset: 270, .AliasCondStart: 184, .NumOperands: 3, .NumConds: 7 }, |
| 8221 | // Mips::C_F_D64 - 38 |
| 8222 | {.AsmStrOffset: 270, .AliasCondStart: 191, .NumOperands: 3, .NumConds: 9 }, |
| 8223 | // Mips::C_F_D64_MM - 39 |
| 8224 | {.AsmStrOffset: 270, .AliasCondStart: 200, .NumOperands: 3, .NumConds: 7 }, |
| 8225 | // Mips::C_F_S - 40 |
| 8226 | {.AsmStrOffset: 283, .AliasCondStart: 207, .NumOperands: 3, .NumConds: 8 }, |
| 8227 | // Mips::C_F_S_MM - 41 |
| 8228 | {.AsmStrOffset: 283, .AliasCondStart: 215, .NumOperands: 3, .NumConds: 6 }, |
| 8229 | // Mips::C_LE_D32 - 42 |
| 8230 | {.AsmStrOffset: 296, .AliasCondStart: 221, .NumOperands: 3, .NumConds: 9 }, |
| 8231 | // Mips::C_LE_D32_MM - 43 |
| 8232 | {.AsmStrOffset: 296, .AliasCondStart: 230, .NumOperands: 3, .NumConds: 7 }, |
| 8233 | // Mips::C_LE_D64 - 44 |
| 8234 | {.AsmStrOffset: 296, .AliasCondStart: 237, .NumOperands: 3, .NumConds: 9 }, |
| 8235 | // Mips::C_LE_D64_MM - 45 |
| 8236 | {.AsmStrOffset: 296, .AliasCondStart: 246, .NumOperands: 3, .NumConds: 7 }, |
| 8237 | // Mips::C_LE_S - 46 |
| 8238 | {.AsmStrOffset: 310, .AliasCondStart: 253, .NumOperands: 3, .NumConds: 8 }, |
| 8239 | // Mips::C_LE_S_MM - 47 |
| 8240 | {.AsmStrOffset: 310, .AliasCondStart: 261, .NumOperands: 3, .NumConds: 6 }, |
| 8241 | // Mips::C_LT_D32 - 48 |
| 8242 | {.AsmStrOffset: 324, .AliasCondStart: 267, .NumOperands: 3, .NumConds: 9 }, |
| 8243 | // Mips::C_LT_D32_MM - 49 |
| 8244 | {.AsmStrOffset: 324, .AliasCondStart: 276, .NumOperands: 3, .NumConds: 7 }, |
| 8245 | // Mips::C_LT_D64 - 50 |
| 8246 | {.AsmStrOffset: 324, .AliasCondStart: 283, .NumOperands: 3, .NumConds: 9 }, |
| 8247 | // Mips::C_LT_D64_MM - 51 |
| 8248 | {.AsmStrOffset: 324, .AliasCondStart: 292, .NumOperands: 3, .NumConds: 7 }, |
| 8249 | // Mips::C_LT_S - 52 |
| 8250 | {.AsmStrOffset: 338, .AliasCondStart: 299, .NumOperands: 3, .NumConds: 8 }, |
| 8251 | // Mips::C_LT_S_MM - 53 |
| 8252 | {.AsmStrOffset: 338, .AliasCondStart: 307, .NumOperands: 3, .NumConds: 6 }, |
| 8253 | // Mips::C_NGE_D32 - 54 |
| 8254 | {.AsmStrOffset: 352, .AliasCondStart: 313, .NumOperands: 3, .NumConds: 9 }, |
| 8255 | // Mips::C_NGE_D32_MM - 55 |
| 8256 | {.AsmStrOffset: 352, .AliasCondStart: 322, .NumOperands: 3, .NumConds: 7 }, |
| 8257 | // Mips::C_NGE_D64 - 56 |
| 8258 | {.AsmStrOffset: 352, .AliasCondStart: 329, .NumOperands: 3, .NumConds: 9 }, |
| 8259 | // Mips::C_NGE_D64_MM - 57 |
| 8260 | {.AsmStrOffset: 352, .AliasCondStart: 338, .NumOperands: 3, .NumConds: 7 }, |
| 8261 | // Mips::C_NGE_S - 58 |
| 8262 | {.AsmStrOffset: 367, .AliasCondStart: 345, .NumOperands: 3, .NumConds: 8 }, |
| 8263 | // Mips::C_NGE_S_MM - 59 |
| 8264 | {.AsmStrOffset: 367, .AliasCondStart: 353, .NumOperands: 3, .NumConds: 6 }, |
| 8265 | // Mips::C_NGLE_D32 - 60 |
| 8266 | {.AsmStrOffset: 382, .AliasCondStart: 359, .NumOperands: 3, .NumConds: 9 }, |
| 8267 | // Mips::C_NGLE_D32_MM - 61 |
| 8268 | {.AsmStrOffset: 382, .AliasCondStart: 368, .NumOperands: 3, .NumConds: 7 }, |
| 8269 | // Mips::C_NGLE_D64 - 62 |
| 8270 | {.AsmStrOffset: 382, .AliasCondStart: 375, .NumOperands: 3, .NumConds: 9 }, |
| 8271 | // Mips::C_NGLE_D64_MM - 63 |
| 8272 | {.AsmStrOffset: 382, .AliasCondStart: 384, .NumOperands: 3, .NumConds: 7 }, |
| 8273 | // Mips::C_NGLE_S - 64 |
| 8274 | {.AsmStrOffset: 398, .AliasCondStart: 391, .NumOperands: 3, .NumConds: 8 }, |
| 8275 | // Mips::C_NGLE_S_MM - 65 |
| 8276 | {.AsmStrOffset: 398, .AliasCondStart: 399, .NumOperands: 3, .NumConds: 6 }, |
| 8277 | // Mips::C_NGL_D32 - 66 |
| 8278 | {.AsmStrOffset: 414, .AliasCondStart: 405, .NumOperands: 3, .NumConds: 9 }, |
| 8279 | // Mips::C_NGL_D32_MM - 67 |
| 8280 | {.AsmStrOffset: 414, .AliasCondStart: 414, .NumOperands: 3, .NumConds: 7 }, |
| 8281 | // Mips::C_NGL_D64 - 68 |
| 8282 | {.AsmStrOffset: 414, .AliasCondStart: 421, .NumOperands: 3, .NumConds: 9 }, |
| 8283 | // Mips::C_NGL_D64_MM - 69 |
| 8284 | {.AsmStrOffset: 414, .AliasCondStart: 430, .NumOperands: 3, .NumConds: 7 }, |
| 8285 | // Mips::C_NGL_S - 70 |
| 8286 | {.AsmStrOffset: 429, .AliasCondStart: 437, .NumOperands: 3, .NumConds: 8 }, |
| 8287 | // Mips::C_NGL_S_MM - 71 |
| 8288 | {.AsmStrOffset: 429, .AliasCondStart: 445, .NumOperands: 3, .NumConds: 6 }, |
| 8289 | // Mips::C_NGT_D32 - 72 |
| 8290 | {.AsmStrOffset: 444, .AliasCondStart: 451, .NumOperands: 3, .NumConds: 9 }, |
| 8291 | // Mips::C_NGT_D32_MM - 73 |
| 8292 | {.AsmStrOffset: 444, .AliasCondStart: 460, .NumOperands: 3, .NumConds: 7 }, |
| 8293 | // Mips::C_NGT_D64 - 74 |
| 8294 | {.AsmStrOffset: 444, .AliasCondStart: 467, .NumOperands: 3, .NumConds: 9 }, |
| 8295 | // Mips::C_NGT_D64_MM - 75 |
| 8296 | {.AsmStrOffset: 444, .AliasCondStart: 476, .NumOperands: 3, .NumConds: 7 }, |
| 8297 | // Mips::C_NGT_S - 76 |
| 8298 | {.AsmStrOffset: 459, .AliasCondStart: 483, .NumOperands: 3, .NumConds: 8 }, |
| 8299 | // Mips::C_NGT_S_MM - 77 |
| 8300 | {.AsmStrOffset: 459, .AliasCondStart: 491, .NumOperands: 3, .NumConds: 6 }, |
| 8301 | // Mips::C_OLE_D32 - 78 |
| 8302 | {.AsmStrOffset: 474, .AliasCondStart: 497, .NumOperands: 3, .NumConds: 9 }, |
| 8303 | // Mips::C_OLE_D32_MM - 79 |
| 8304 | {.AsmStrOffset: 474, .AliasCondStart: 506, .NumOperands: 3, .NumConds: 7 }, |
| 8305 | // Mips::C_OLE_D64 - 80 |
| 8306 | {.AsmStrOffset: 474, .AliasCondStart: 513, .NumOperands: 3, .NumConds: 9 }, |
| 8307 | // Mips::C_OLE_D64_MM - 81 |
| 8308 | {.AsmStrOffset: 474, .AliasCondStart: 522, .NumOperands: 3, .NumConds: 7 }, |
| 8309 | // Mips::C_OLE_S - 82 |
| 8310 | {.AsmStrOffset: 489, .AliasCondStart: 529, .NumOperands: 3, .NumConds: 8 }, |
| 8311 | // Mips::C_OLE_S_MM - 83 |
| 8312 | {.AsmStrOffset: 489, .AliasCondStart: 537, .NumOperands: 3, .NumConds: 6 }, |
| 8313 | // Mips::C_OLT_D32 - 84 |
| 8314 | {.AsmStrOffset: 504, .AliasCondStart: 543, .NumOperands: 3, .NumConds: 9 }, |
| 8315 | // Mips::C_OLT_D32_MM - 85 |
| 8316 | {.AsmStrOffset: 504, .AliasCondStart: 552, .NumOperands: 3, .NumConds: 7 }, |
| 8317 | // Mips::C_OLT_D64 - 86 |
| 8318 | {.AsmStrOffset: 504, .AliasCondStart: 559, .NumOperands: 3, .NumConds: 9 }, |
| 8319 | // Mips::C_OLT_D64_MM - 87 |
| 8320 | {.AsmStrOffset: 504, .AliasCondStart: 568, .NumOperands: 3, .NumConds: 7 }, |
| 8321 | // Mips::C_OLT_S - 88 |
| 8322 | {.AsmStrOffset: 519, .AliasCondStart: 575, .NumOperands: 3, .NumConds: 8 }, |
| 8323 | // Mips::C_OLT_S_MM - 89 |
| 8324 | {.AsmStrOffset: 519, .AliasCondStart: 583, .NumOperands: 3, .NumConds: 6 }, |
| 8325 | // Mips::C_SEQ_D32 - 90 |
| 8326 | {.AsmStrOffset: 534, .AliasCondStart: 589, .NumOperands: 3, .NumConds: 9 }, |
| 8327 | // Mips::C_SEQ_D32_MM - 91 |
| 8328 | {.AsmStrOffset: 534, .AliasCondStart: 598, .NumOperands: 3, .NumConds: 7 }, |
| 8329 | // Mips::C_SEQ_D64 - 92 |
| 8330 | {.AsmStrOffset: 534, .AliasCondStart: 605, .NumOperands: 3, .NumConds: 9 }, |
| 8331 | // Mips::C_SEQ_D64_MM - 93 |
| 8332 | {.AsmStrOffset: 534, .AliasCondStart: 614, .NumOperands: 3, .NumConds: 7 }, |
| 8333 | // Mips::C_SEQ_S - 94 |
| 8334 | {.AsmStrOffset: 549, .AliasCondStart: 621, .NumOperands: 3, .NumConds: 8 }, |
| 8335 | // Mips::C_SEQ_S_MM - 95 |
| 8336 | {.AsmStrOffset: 549, .AliasCondStart: 629, .NumOperands: 3, .NumConds: 6 }, |
| 8337 | // Mips::C_SF_D32 - 96 |
| 8338 | {.AsmStrOffset: 564, .AliasCondStart: 635, .NumOperands: 3, .NumConds: 9 }, |
| 8339 | // Mips::C_SF_D32_MM - 97 |
| 8340 | {.AsmStrOffset: 564, .AliasCondStart: 644, .NumOperands: 3, .NumConds: 7 }, |
| 8341 | // Mips::C_SF_D64 - 98 |
| 8342 | {.AsmStrOffset: 564, .AliasCondStart: 651, .NumOperands: 3, .NumConds: 9 }, |
| 8343 | // Mips::C_SF_D64_MM - 99 |
| 8344 | {.AsmStrOffset: 564, .AliasCondStart: 660, .NumOperands: 3, .NumConds: 7 }, |
| 8345 | // Mips::C_SF_S - 100 |
| 8346 | {.AsmStrOffset: 578, .AliasCondStart: 667, .NumOperands: 3, .NumConds: 8 }, |
| 8347 | // Mips::C_SF_S_MM - 101 |
| 8348 | {.AsmStrOffset: 578, .AliasCondStart: 675, .NumOperands: 3, .NumConds: 6 }, |
| 8349 | // Mips::C_UEQ_D32 - 102 |
| 8350 | {.AsmStrOffset: 592, .AliasCondStart: 681, .NumOperands: 3, .NumConds: 9 }, |
| 8351 | // Mips::C_UEQ_D32_MM - 103 |
| 8352 | {.AsmStrOffset: 592, .AliasCondStart: 690, .NumOperands: 3, .NumConds: 7 }, |
| 8353 | // Mips::C_UEQ_D64 - 104 |
| 8354 | {.AsmStrOffset: 592, .AliasCondStart: 697, .NumOperands: 3, .NumConds: 9 }, |
| 8355 | // Mips::C_UEQ_D64_MM - 105 |
| 8356 | {.AsmStrOffset: 592, .AliasCondStart: 706, .NumOperands: 3, .NumConds: 7 }, |
| 8357 | // Mips::C_UEQ_S - 106 |
| 8358 | {.AsmStrOffset: 607, .AliasCondStart: 713, .NumOperands: 3, .NumConds: 8 }, |
| 8359 | // Mips::C_UEQ_S_MM - 107 |
| 8360 | {.AsmStrOffset: 607, .AliasCondStart: 721, .NumOperands: 3, .NumConds: 6 }, |
| 8361 | // Mips::C_ULE_D32 - 108 |
| 8362 | {.AsmStrOffset: 622, .AliasCondStart: 727, .NumOperands: 3, .NumConds: 9 }, |
| 8363 | // Mips::C_ULE_D32_MM - 109 |
| 8364 | {.AsmStrOffset: 622, .AliasCondStart: 736, .NumOperands: 3, .NumConds: 7 }, |
| 8365 | // Mips::C_ULE_D64 - 110 |
| 8366 | {.AsmStrOffset: 622, .AliasCondStart: 743, .NumOperands: 3, .NumConds: 9 }, |
| 8367 | // Mips::C_ULE_D64_MM - 111 |
| 8368 | {.AsmStrOffset: 622, .AliasCondStart: 752, .NumOperands: 3, .NumConds: 7 }, |
| 8369 | // Mips::C_ULE_S - 112 |
| 8370 | {.AsmStrOffset: 637, .AliasCondStart: 759, .NumOperands: 3, .NumConds: 8 }, |
| 8371 | // Mips::C_ULE_S_MM - 113 |
| 8372 | {.AsmStrOffset: 637, .AliasCondStart: 767, .NumOperands: 3, .NumConds: 6 }, |
| 8373 | // Mips::C_ULT_D32 - 114 |
| 8374 | {.AsmStrOffset: 652, .AliasCondStart: 773, .NumOperands: 3, .NumConds: 9 }, |
| 8375 | // Mips::C_ULT_D32_MM - 115 |
| 8376 | {.AsmStrOffset: 652, .AliasCondStart: 782, .NumOperands: 3, .NumConds: 7 }, |
| 8377 | // Mips::C_ULT_D64 - 116 |
| 8378 | {.AsmStrOffset: 652, .AliasCondStart: 789, .NumOperands: 3, .NumConds: 9 }, |
| 8379 | // Mips::C_ULT_D64_MM - 117 |
| 8380 | {.AsmStrOffset: 652, .AliasCondStart: 798, .NumOperands: 3, .NumConds: 7 }, |
| 8381 | // Mips::C_ULT_S - 118 |
| 8382 | {.AsmStrOffset: 667, .AliasCondStart: 805, .NumOperands: 3, .NumConds: 8 }, |
| 8383 | // Mips::C_ULT_S_MM - 119 |
| 8384 | {.AsmStrOffset: 667, .AliasCondStart: 813, .NumOperands: 3, .NumConds: 6 }, |
| 8385 | // Mips::C_UN_D32 - 120 |
| 8386 | {.AsmStrOffset: 682, .AliasCondStart: 819, .NumOperands: 3, .NumConds: 9 }, |
| 8387 | // Mips::C_UN_D32_MM - 121 |
| 8388 | {.AsmStrOffset: 682, .AliasCondStart: 828, .NumOperands: 3, .NumConds: 7 }, |
| 8389 | // Mips::C_UN_D64 - 122 |
| 8390 | {.AsmStrOffset: 682, .AliasCondStart: 835, .NumOperands: 3, .NumConds: 9 }, |
| 8391 | // Mips::C_UN_D64_MM - 123 |
| 8392 | {.AsmStrOffset: 682, .AliasCondStart: 844, .NumOperands: 3, .NumConds: 7 }, |
| 8393 | // Mips::C_UN_S - 124 |
| 8394 | {.AsmStrOffset: 696, .AliasCondStart: 851, .NumOperands: 3, .NumConds: 8 }, |
| 8395 | // Mips::C_UN_S_MM - 125 |
| 8396 | {.AsmStrOffset: 696, .AliasCondStart: 859, .NumOperands: 3, .NumConds: 6 }, |
| 8397 | // Mips::DADDu - 126 |
| 8398 | {.AsmStrOffset: 128, .AliasCondStart: 865, .NumOperands: 3, .NumConds: 5 }, |
| 8399 | // Mips::DI - 127 |
| 8400 | {.AsmStrOffset: 710, .AliasCondStart: 870, .NumOperands: 1, .NumConds: 4 }, |
| 8401 | // Mips::DIV - 128 |
| 8402 | {.AsmStrOffset: 713, .AliasCondStart: 874, .NumOperands: 3, .NumConds: 5 }, |
| 8403 | // Mips::DIVU - 129 |
| 8404 | {.AsmStrOffset: 724, .AliasCondStart: 879, .NumOperands: 3, .NumConds: 5 }, |
| 8405 | // Mips::DI_MM - 130 |
| 8406 | {.AsmStrOffset: 710, .AliasCondStart: 884, .NumOperands: 1, .NumConds: 2 }, |
| 8407 | // Mips::DI_MMR6 - 131 |
| 8408 | {.AsmStrOffset: 710, .AliasCondStart: 886, .NumOperands: 1, .NumConds: 3 }, |
| 8409 | // Mips::DMT - 132 |
| 8410 | {.AsmStrOffset: 736, .AliasCondStart: 889, .NumOperands: 1, .NumConds: 3 }, |
| 8411 | // Mips::DSUB - 133 |
| 8412 | {.AsmStrOffset: 740, .AliasCondStart: 892, .NumOperands: 3, .NumConds: 6 }, |
| 8413 | {.AsmStrOffset: 752, .AliasCondStart: 898, .NumOperands: 3, .NumConds: 6 }, |
| 8414 | // Mips::DSUBu - 135 |
| 8415 | {.AsmStrOffset: 760, .AliasCondStart: 904, .NumOperands: 3, .NumConds: 6 }, |
| 8416 | {.AsmStrOffset: 773, .AliasCondStart: 910, .NumOperands: 3, .NumConds: 6 }, |
| 8417 | // Mips::DVPE - 137 |
| 8418 | {.AsmStrOffset: 782, .AliasCondStart: 916, .NumOperands: 1, .NumConds: 3 }, |
| 8419 | // Mips::EI - 138 |
| 8420 | {.AsmStrOffset: 787, .AliasCondStart: 919, .NumOperands: 1, .NumConds: 4 }, |
| 8421 | // Mips::EI_MM - 139 |
| 8422 | {.AsmStrOffset: 787, .AliasCondStart: 923, .NumOperands: 1, .NumConds: 2 }, |
| 8423 | // Mips::EI_MMR6 - 140 |
| 8424 | {.AsmStrOffset: 787, .AliasCondStart: 925, .NumOperands: 1, .NumConds: 3 }, |
| 8425 | // Mips::EMT - 141 |
| 8426 | {.AsmStrOffset: 790, .AliasCondStart: 928, .NumOperands: 1, .NumConds: 3 }, |
| 8427 | // Mips::EVPE - 142 |
| 8428 | {.AsmStrOffset: 794, .AliasCondStart: 931, .NumOperands: 1, .NumConds: 3 }, |
| 8429 | // Mips::HYPCALL - 143 |
| 8430 | {.AsmStrOffset: 799, .AliasCondStart: 934, .NumOperands: 1, .NumConds: 5 }, |
| 8431 | // Mips::HYPCALL_MM - 144 |
| 8432 | {.AsmStrOffset: 799, .AliasCondStart: 939, .NumOperands: 1, .NumConds: 4 }, |
| 8433 | // Mips::JALR - 145 |
| 8434 | {.AsmStrOffset: 807, .AliasCondStart: 943, .NumOperands: 2, .NumConds: 6 }, |
| 8435 | // Mips::JALR64 - 146 |
| 8436 | {.AsmStrOffset: 807, .AliasCondStart: 949, .NumOperands: 2, .NumConds: 4 }, |
| 8437 | // Mips::JALRC_HB_MMR6 - 147 |
| 8438 | {.AsmStrOffset: 813, .AliasCondStart: 953, .NumOperands: 2, .NumConds: 4 }, |
| 8439 | // Mips::JALRC_MMR6 - 148 |
| 8440 | {.AsmStrOffset: 825, .AliasCondStart: 957, .NumOperands: 2, .NumConds: 4 }, |
| 8441 | // Mips::JALR_HB - 149 |
| 8442 | {.AsmStrOffset: 834, .AliasCondStart: 961, .NumOperands: 2, .NumConds: 5 }, |
| 8443 | // Mips::JALR_HB64 - 150 |
| 8444 | {.AsmStrOffset: 834, .AliasCondStart: 966, .NumOperands: 2, .NumConds: 5 }, |
| 8445 | // Mips::JIALC - 151 |
| 8446 | {.AsmStrOffset: 845, .AliasCondStart: 971, .NumOperands: 2, .NumConds: 6 }, |
| 8447 | // Mips::JIALC64 - 152 |
| 8448 | {.AsmStrOffset: 845, .AliasCondStart: 977, .NumOperands: 2, .NumConds: 4 }, |
| 8449 | // Mips::JIC - 153 |
| 8450 | {.AsmStrOffset: 854, .AliasCondStart: 981, .NumOperands: 2, .NumConds: 5 }, |
| 8451 | // Mips::JIC64 - 154 |
| 8452 | {.AsmStrOffset: 854, .AliasCondStart: 986, .NumOperands: 2, .NumConds: 4 }, |
| 8453 | // Mips::MOVE16_MM - 155 |
| 8454 | {.AsmStrOffset: 861, .AliasCondStart: 990, .NumOperands: 2, .NumConds: 3 }, |
| 8455 | // Mips::Move32R16 - 156 |
| 8456 | {.AsmStrOffset: 861, .AliasCondStart: 993, .NumOperands: 2, .NumConds: 3 }, |
| 8457 | // Mips::OR - 157 |
| 8458 | {.AsmStrOffset: 128, .AliasCondStart: 996, .NumOperands: 3, .NumConds: 6 }, |
| 8459 | // Mips::OR64 - 158 |
| 8460 | {.AsmStrOffset: 128, .AliasCondStart: 1002, .NumOperands: 3, .NumConds: 5 }, |
| 8461 | // Mips::RDHWR - 159 |
| 8462 | {.AsmStrOffset: 865, .AliasCondStart: 1007, .NumOperands: 3, .NumConds: 5 }, |
| 8463 | // Mips::RDHWR64 - 160 |
| 8464 | {.AsmStrOffset: 865, .AliasCondStart: 1012, .NumOperands: 3, .NumConds: 4 }, |
| 8465 | // Mips::RDHWR_MM - 161 |
| 8466 | {.AsmStrOffset: 865, .AliasCondStart: 1016, .NumOperands: 3, .NumConds: 5 }, |
| 8467 | // Mips::RDHWR_MMR6 - 162 |
| 8468 | {.AsmStrOffset: 865, .AliasCondStart: 1021, .NumOperands: 3, .NumConds: 5 }, |
| 8469 | // Mips::SDBBP - 163 |
| 8470 | {.AsmStrOffset: 878, .AliasCondStart: 1026, .NumOperands: 1, .NumConds: 5 }, |
| 8471 | // Mips::SDBBP_MMR6 - 164 |
| 8472 | {.AsmStrOffset: 878, .AliasCondStart: 1031, .NumOperands: 1, .NumConds: 3 }, |
| 8473 | // Mips::SDBBP_R6 - 165 |
| 8474 | {.AsmStrOffset: 878, .AliasCondStart: 1034, .NumOperands: 1, .NumConds: 4 }, |
| 8475 | // Mips::SIGRIE - 166 |
| 8476 | {.AsmStrOffset: 884, .AliasCondStart: 1038, .NumOperands: 1, .NumConds: 4 }, |
| 8477 | // Mips::SIGRIE_MMR6 - 167 |
| 8478 | {.AsmStrOffset: 884, .AliasCondStart: 1042, .NumOperands: 1, .NumConds: 3 }, |
| 8479 | // Mips::SLL - 168 |
| 8480 | {.AsmStrOffset: 861, .AliasCondStart: 1045, .NumOperands: 3, .NumConds: 5 }, |
| 8481 | // Mips::SLL_MM - 169 |
| 8482 | {.AsmStrOffset: 861, .AliasCondStart: 1050, .NumOperands: 3, .NumConds: 4 }, |
| 8483 | // Mips::SLL_MMR6 - 170 |
| 8484 | {.AsmStrOffset: 861, .AliasCondStart: 1054, .NumOperands: 3, .NumConds: 5 }, |
| 8485 | // Mips::SUB - 171 |
| 8486 | {.AsmStrOffset: 891, .AliasCondStart: 1059, .NumOperands: 3, .NumConds: 5 }, |
| 8487 | {.AsmStrOffset: 902, .AliasCondStart: 1064, .NumOperands: 3, .NumConds: 5 }, |
| 8488 | // Mips::SUBU_MMR6 - 173 |
| 8489 | {.AsmStrOffset: 909, .AliasCondStart: 1069, .NumOperands: 3, .NumConds: 5 }, |
| 8490 | {.AsmStrOffset: 921, .AliasCondStart: 1074, .NumOperands: 3, .NumConds: 5 }, |
| 8491 | // Mips::SUB_MM - 175 |
| 8492 | {.AsmStrOffset: 891, .AliasCondStart: 1079, .NumOperands: 3, .NumConds: 5 }, |
| 8493 | {.AsmStrOffset: 902, .AliasCondStart: 1084, .NumOperands: 3, .NumConds: 5 }, |
| 8494 | // Mips::SUB_MMR6 - 177 |
| 8495 | {.AsmStrOffset: 891, .AliasCondStart: 1089, .NumOperands: 3, .NumConds: 5 }, |
| 8496 | {.AsmStrOffset: 902, .AliasCondStart: 1094, .NumOperands: 3, .NumConds: 5 }, |
| 8497 | // Mips::SUBu - 179 |
| 8498 | {.AsmStrOffset: 909, .AliasCondStart: 1099, .NumOperands: 3, .NumConds: 5 }, |
| 8499 | {.AsmStrOffset: 921, .AliasCondStart: 1104, .NumOperands: 3, .NumConds: 5 }, |
| 8500 | // Mips::SUBu_MM - 181 |
| 8501 | {.AsmStrOffset: 909, .AliasCondStart: 1109, .NumOperands: 3, .NumConds: 5 }, |
| 8502 | {.AsmStrOffset: 921, .AliasCondStart: 1114, .NumOperands: 3, .NumConds: 5 }, |
| 8503 | // Mips::SWSP_MM - 183 |
| 8504 | {.AsmStrOffset: 929, .AliasCondStart: 1119, .NumOperands: 3, .NumConds: 2 }, |
| 8505 | // Mips::SYNC - 184 |
| 8506 | {.AsmStrOffset: 941, .AliasCondStart: 1121, .NumOperands: 1, .NumConds: 4 }, |
| 8507 | // Mips::SYNC_MM - 185 |
| 8508 | {.AsmStrOffset: 941, .AliasCondStart: 1125, .NumOperands: 1, .NumConds: 2 }, |
| 8509 | // Mips::SYNC_MMR6 - 186 |
| 8510 | {.AsmStrOffset: 941, .AliasCondStart: 1127, .NumOperands: 1, .NumConds: 3 }, |
| 8511 | // Mips::SYSCALL - 187 |
| 8512 | {.AsmStrOffset: 946, .AliasCondStart: 1130, .NumOperands: 1, .NumConds: 3 }, |
| 8513 | // Mips::SYSCALL_MM - 188 |
| 8514 | {.AsmStrOffset: 946, .AliasCondStart: 1133, .NumOperands: 1, .NumConds: 2 }, |
| 8515 | // Mips::TEQ - 189 |
| 8516 | {.AsmStrOffset: 954, .AliasCondStart: 1135, .NumOperands: 3, .NumConds: 6 }, |
| 8517 | // Mips::TEQ_MM - 190 |
| 8518 | {.AsmStrOffset: 954, .AliasCondStart: 1141, .NumOperands: 3, .NumConds: 4 }, |
| 8519 | // Mips::TGE - 191 |
| 8520 | {.AsmStrOffset: 965, .AliasCondStart: 1145, .NumOperands: 3, .NumConds: 6 }, |
| 8521 | // Mips::TGEU - 192 |
| 8522 | {.AsmStrOffset: 976, .AliasCondStart: 1151, .NumOperands: 3, .NumConds: 6 }, |
| 8523 | // Mips::TGEU_MM - 193 |
| 8524 | {.AsmStrOffset: 976, .AliasCondStart: 1157, .NumOperands: 3, .NumConds: 4 }, |
| 8525 | // Mips::TGE_MM - 194 |
| 8526 | {.AsmStrOffset: 965, .AliasCondStart: 1161, .NumOperands: 3, .NumConds: 4 }, |
| 8527 | // Mips::TLT - 195 |
| 8528 | {.AsmStrOffset: 988, .AliasCondStart: 1165, .NumOperands: 3, .NumConds: 6 }, |
| 8529 | // Mips::TLTU - 196 |
| 8530 | {.AsmStrOffset: 999, .AliasCondStart: 1171, .NumOperands: 3, .NumConds: 6 }, |
| 8531 | // Mips::TLTU_MM - 197 |
| 8532 | {.AsmStrOffset: 999, .AliasCondStart: 1177, .NumOperands: 3, .NumConds: 4 }, |
| 8533 | // Mips::TLT_MM - 198 |
| 8534 | {.AsmStrOffset: 988, .AliasCondStart: 1181, .NumOperands: 3, .NumConds: 4 }, |
| 8535 | // Mips::TNE - 199 |
| 8536 | {.AsmStrOffset: 1011, .AliasCondStart: 1185, .NumOperands: 3, .NumConds: 6 }, |
| 8537 | // Mips::TNE_MM - 200 |
| 8538 | {.AsmStrOffset: 1011, .AliasCondStart: 1191, .NumOperands: 3, .NumConds: 4 }, |
| 8539 | // Mips::WAIT_MM - 201 |
| 8540 | {.AsmStrOffset: 1022, .AliasCondStart: 1195, .NumOperands: 1, .NumConds: 2 }, |
| 8541 | // Mips::WRDSP - 202 |
| 8542 | {.AsmStrOffset: 1027, .AliasCondStart: 1197, .NumOperands: 2, .NumConds: 4 }, |
| 8543 | // Mips::WRDSP_MM - 203 |
| 8544 | {.AsmStrOffset: 1027, .AliasCondStart: 1201, .NumOperands: 2, .NumConds: 4 }, |
| 8545 | // Mips::YIELD - 204 |
| 8546 | {.AsmStrOffset: 1036, .AliasCondStart: 1205, .NumOperands: 2, .NumConds: 4 }, |
| 8547 | }; |
| 8548 | |
| 8549 | static const AliasPatternCond Conds[] = { |
| 8550 | // (MFTACX GPR32Opnd:$rt, AC0) - 0 |
| 8551 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8552 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::AC0}, |
| 8553 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 8554 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8555 | // (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0) - 4 |
| 8556 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8557 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::COP0RegClassID}, |
| 8558 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 8559 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 8560 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8561 | // (MFTHI GPR32Opnd:$rt, AC0) - 9 |
| 8562 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8563 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::AC0}, |
| 8564 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 8565 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8566 | // (MFTLO GPR32Opnd:$rt, AC0) - 13 |
| 8567 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8568 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::AC0}, |
| 8569 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 8570 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8571 | // (MTTACX AC0, GPR32Opnd:$rt) - 17 |
| 8572 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::AC0}, |
| 8573 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8574 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 8575 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8576 | // (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0) - 21 |
| 8577 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::COP0RegClassID}, |
| 8578 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8579 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 8580 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 8581 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8582 | // (MTTHI AC0, GPR32Opnd:$rt) - 26 |
| 8583 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::AC0}, |
| 8584 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8585 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 8586 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8587 | // (MTTLO AC0, GPR32Opnd:$rt) - 30 |
| 8588 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::AC0}, |
| 8589 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8590 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 8591 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8592 | // (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm) - 34 |
| 8593 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8594 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 8595 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureGP64Bit}, |
| 8596 | // (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 37 |
| 8597 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 8598 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 8599 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureGP64Bit}, |
| 8600 | // (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 40 |
| 8601 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 8602 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 8603 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureGP64Bit}, |
| 8604 | // (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 43 |
| 8605 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 8606 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 8607 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureGP64Bit}, |
| 8608 | // (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm) - 46 |
| 8609 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8610 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8611 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 8612 | // (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm) - 49 |
| 8613 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8614 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8615 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 8616 | // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 52 |
| 8617 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8618 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8619 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 8620 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8621 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureGP64Bit}, |
| 8622 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8623 | // (BC1F FCC0, brtarget:$offset) - 58 |
| 8624 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8625 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8626 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8627 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8628 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8629 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8630 | // (BC1FL FCC0, brtarget:$offset) - 64 |
| 8631 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8632 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8633 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 8634 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8635 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8636 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8637 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8638 | // (BC1F_MM FCC0, brtarget:$offset) - 71 |
| 8639 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8640 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8641 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8642 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8643 | // (BC1T FCC0, brtarget:$offset) - 75 |
| 8644 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8645 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8646 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8647 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8648 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8649 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8650 | // (BC1TL FCC0, brtarget:$offset) - 81 |
| 8651 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8652 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8653 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 8654 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8655 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8656 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8657 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8658 | // (BC1T_MM FCC0, brtarget:$offset) - 88 |
| 8659 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8660 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8661 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8662 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8663 | // (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 92 |
| 8664 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8665 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 8666 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8667 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 8668 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8669 | // (BGEZAL ZERO, brtarget:$offset) - 97 |
| 8670 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 8671 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8672 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8673 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8674 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8675 | // (BGEZAL_MM ZERO, brtarget_mm:$offset) - 102 |
| 8676 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 8677 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8678 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8679 | // (BLTZAL ZERO, 0) - 105 |
| 8680 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 8681 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 8682 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8683 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8684 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8685 | // (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 110 |
| 8686 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 8687 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 8688 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8689 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 8690 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8691 | // (BREAK 0, 0) - 115 |
| 8692 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 8693 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 8694 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8695 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8696 | // (BREAK uimm10:$imm, 0) - 119 |
| 8697 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 8698 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 8699 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8700 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8701 | // (BREAK_MM 0, 0) - 123 |
| 8702 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 8703 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 8704 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8705 | // (BREAK_MM uimm10:$imm, 0) - 126 |
| 8706 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 8707 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 8708 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8709 | // (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 129 |
| 8710 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8711 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8712 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8713 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8714 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8715 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8716 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8717 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8718 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8719 | // (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 138 |
| 8720 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8721 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8722 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8723 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8724 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8725 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8726 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8727 | // (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 145 |
| 8728 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8729 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8730 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8731 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8732 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8733 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8734 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8735 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8736 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8737 | // (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 154 |
| 8738 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8739 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8740 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8741 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8742 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8743 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8744 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8745 | // (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 161 |
| 8746 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8747 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8748 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8749 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8750 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8751 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8752 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8753 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8754 | // (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 169 |
| 8755 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8756 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8757 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8758 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8759 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8760 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8761 | // (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 175 |
| 8762 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8763 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8764 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8765 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8766 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8767 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8768 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8769 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8770 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8771 | // (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 184 |
| 8772 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8773 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8774 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8775 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8776 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8777 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8778 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8779 | // (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 191 |
| 8780 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8781 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8782 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8783 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8784 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8785 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8786 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8787 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8788 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8789 | // (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 200 |
| 8790 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8791 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8792 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8793 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8794 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8795 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8796 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8797 | // (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 207 |
| 8798 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8799 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8800 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8801 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8802 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8803 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8804 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8805 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8806 | // (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 215 |
| 8807 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8808 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8809 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8810 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8811 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8812 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8813 | // (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 221 |
| 8814 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8815 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8816 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8817 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8818 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8819 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8820 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8821 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8822 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8823 | // (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 230 |
| 8824 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8825 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8826 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8827 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8828 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8829 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8830 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8831 | // (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 237 |
| 8832 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8833 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8834 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8835 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8836 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8837 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8838 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8839 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8840 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8841 | // (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 246 |
| 8842 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8843 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8844 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8845 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8846 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8847 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8848 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8849 | // (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 253 |
| 8850 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8851 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8852 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8853 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8854 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8855 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8856 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8857 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8858 | // (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 261 |
| 8859 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8860 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8861 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8862 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8863 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8864 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8865 | // (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 267 |
| 8866 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8867 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8868 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8869 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8870 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8871 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8872 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8873 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8874 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8875 | // (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 276 |
| 8876 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8877 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8878 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8879 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8880 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8881 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8882 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8883 | // (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 283 |
| 8884 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8885 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8886 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8887 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8888 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8889 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8890 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8891 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8892 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8893 | // (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 292 |
| 8894 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8895 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8896 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8897 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8898 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8899 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8900 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8901 | // (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 299 |
| 8902 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8903 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8904 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8905 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8906 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8907 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8908 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8909 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8910 | // (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 307 |
| 8911 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8912 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8913 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8914 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8915 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8916 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8917 | // (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 313 |
| 8918 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8919 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8920 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8921 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8922 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8923 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8924 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8925 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8926 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8927 | // (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 322 |
| 8928 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8929 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8930 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8931 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8932 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8933 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8934 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8935 | // (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 329 |
| 8936 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8937 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8938 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8939 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8940 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8941 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8942 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8943 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8944 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8945 | // (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 338 |
| 8946 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8947 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8948 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8949 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8950 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8951 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8952 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8953 | // (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 345 |
| 8954 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8955 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8956 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8957 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8958 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8959 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8960 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8961 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8962 | // (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 353 |
| 8963 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8964 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8965 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 8966 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8967 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8968 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8969 | // (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 359 |
| 8970 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8971 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8972 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8973 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8974 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8975 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8976 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8977 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8978 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8979 | // (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 368 |
| 8980 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8981 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8982 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 8983 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 8984 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 8985 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8986 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8987 | // (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 375 |
| 8988 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8989 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8990 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 8991 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 8992 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 8993 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 8994 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 8995 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 8996 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 8997 | // (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 384 |
| 8998 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 8999 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9000 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9001 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9002 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9003 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9004 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9005 | // (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 391 |
| 9006 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9007 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9008 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9009 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9010 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9011 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9012 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9013 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9014 | // (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 399 |
| 9015 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9016 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9017 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9018 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9019 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9020 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9021 | // (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 405 |
| 9022 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9023 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9024 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9025 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9026 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9027 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9028 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9029 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9030 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9031 | // (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 414 |
| 9032 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9033 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9034 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9035 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9036 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9037 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9038 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9039 | // (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 421 |
| 9040 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9041 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9042 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9043 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9044 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9045 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9046 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9047 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9048 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9049 | // (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 430 |
| 9050 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9051 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9052 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9053 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9054 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9055 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9056 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9057 | // (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 437 |
| 9058 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9059 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9060 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9061 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9062 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9063 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9064 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9065 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9066 | // (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 445 |
| 9067 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9068 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9069 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9070 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9071 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9072 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9073 | // (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 451 |
| 9074 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9075 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9076 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9077 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9078 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9079 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9080 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9081 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9082 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9083 | // (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 460 |
| 9084 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9085 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9086 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9087 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9088 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9089 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9090 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9091 | // (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 467 |
| 9092 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9093 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9094 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9095 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9096 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9097 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9098 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9099 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9100 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9101 | // (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 476 |
| 9102 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9103 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9104 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9105 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9106 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9107 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9108 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9109 | // (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 483 |
| 9110 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9111 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9112 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9113 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9114 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9115 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9116 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9117 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9118 | // (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 491 |
| 9119 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9120 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9121 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9122 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9123 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9124 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9125 | // (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 497 |
| 9126 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9127 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9128 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9129 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9130 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9131 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9132 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9133 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9134 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9135 | // (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 506 |
| 9136 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9137 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9138 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9139 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9140 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9141 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9142 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9143 | // (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 513 |
| 9144 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9145 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9146 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9147 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9148 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9149 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9150 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9151 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9152 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9153 | // (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 522 |
| 9154 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9155 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9156 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9157 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9158 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9159 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9160 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9161 | // (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 529 |
| 9162 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9163 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9164 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9165 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9166 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9167 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9168 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9169 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9170 | // (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 537 |
| 9171 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9172 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9173 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9174 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9175 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9176 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9177 | // (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 543 |
| 9178 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9179 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9180 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9181 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9182 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9183 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9184 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9185 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9186 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9187 | // (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 552 |
| 9188 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9189 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9190 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9191 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9192 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9193 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9194 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9195 | // (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 559 |
| 9196 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9197 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9198 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9199 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9200 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9201 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9202 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9203 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9204 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9205 | // (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 568 |
| 9206 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9207 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9208 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9209 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9210 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9211 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9212 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9213 | // (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 575 |
| 9214 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9215 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9216 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9217 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9218 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9219 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9220 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9221 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9222 | // (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 583 |
| 9223 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9224 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9225 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9226 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9227 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9228 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9229 | // (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 589 |
| 9230 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9231 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9232 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9233 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9234 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9235 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9236 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9237 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9238 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9239 | // (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 598 |
| 9240 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9241 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9242 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9243 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9244 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9245 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9246 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9247 | // (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 605 |
| 9248 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9249 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9250 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9251 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9252 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9253 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9254 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9255 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9256 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9257 | // (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 614 |
| 9258 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9259 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9260 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9261 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9262 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9263 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9264 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9265 | // (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 621 |
| 9266 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9267 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9268 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9269 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9270 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9271 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9272 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9273 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9274 | // (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 629 |
| 9275 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9276 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9277 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9278 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9279 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9280 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9281 | // (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 635 |
| 9282 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9283 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9284 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9285 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9286 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9287 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9288 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9289 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9290 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9291 | // (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 644 |
| 9292 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9293 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9294 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9295 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9296 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9297 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9298 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9299 | // (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 651 |
| 9300 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9301 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9302 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9303 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9304 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9305 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9306 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9307 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9308 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9309 | // (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 660 |
| 9310 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9311 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9312 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9313 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9314 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9315 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9316 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9317 | // (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 667 |
| 9318 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9319 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9320 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9321 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9322 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9323 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9324 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9325 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9326 | // (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 675 |
| 9327 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9328 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9329 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9330 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9331 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9332 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9333 | // (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 681 |
| 9334 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9335 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9336 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9337 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9338 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9339 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9340 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9341 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9342 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9343 | // (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 690 |
| 9344 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9345 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9346 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9347 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9348 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9349 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9350 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9351 | // (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 697 |
| 9352 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9353 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9354 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9355 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9356 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9357 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9358 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9359 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9360 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9361 | // (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 706 |
| 9362 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9363 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9364 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9365 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9366 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9367 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9368 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9369 | // (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 713 |
| 9370 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9371 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9372 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9373 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9374 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9375 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9376 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9377 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9378 | // (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 721 |
| 9379 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9380 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9381 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9382 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9383 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9384 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9385 | // (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 727 |
| 9386 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9387 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9388 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9389 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9390 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9391 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9392 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9393 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9394 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9395 | // (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 736 |
| 9396 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9397 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9398 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9399 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9400 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9401 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9402 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9403 | // (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 743 |
| 9404 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9405 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9406 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9407 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9408 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9409 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9410 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9411 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9412 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9413 | // (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 752 |
| 9414 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9415 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9416 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9417 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9418 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9419 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9420 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9421 | // (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 759 |
| 9422 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9423 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9424 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9425 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9426 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9427 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9428 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9429 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9430 | // (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 767 |
| 9431 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9432 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9433 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9434 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9435 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9436 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9437 | // (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 773 |
| 9438 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9439 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9440 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9441 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9442 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9443 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9444 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9445 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9446 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9447 | // (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 782 |
| 9448 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9449 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9450 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9451 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9452 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9453 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9454 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9455 | // (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 789 |
| 9456 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9457 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9458 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9459 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9460 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9461 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9462 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9463 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9464 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9465 | // (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 798 |
| 9466 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9467 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9468 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9469 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9470 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9471 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9472 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9473 | // (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 805 |
| 9474 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9475 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9476 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9477 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9478 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9479 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9480 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9481 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9482 | // (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 813 |
| 9483 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9484 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9485 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9486 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9487 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9488 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9489 | // (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 819 |
| 9490 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9491 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9492 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9493 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9494 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9495 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9496 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9497 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9498 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9499 | // (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 828 |
| 9500 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9501 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9502 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::AFGR64RegClassID}, |
| 9503 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9504 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureFP64Bit}, |
| 9505 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9506 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9507 | // (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 835 |
| 9508 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9509 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9510 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9511 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9512 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9513 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9514 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9515 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9516 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9517 | // (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 844 |
| 9518 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9519 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9520 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR64RegClassID}, |
| 9521 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9522 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureFP64Bit}, |
| 9523 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9524 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9525 | // (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 851 |
| 9526 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9527 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9528 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9529 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9530 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9531 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9532 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9533 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9534 | // (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 859 |
| 9535 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::FCC0}, |
| 9536 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9537 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::FGR32RegClassID}, |
| 9538 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9539 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9540 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureSoftFloat}, |
| 9541 | // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 865 |
| 9542 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9543 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9544 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO_64}, |
| 9545 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureGP64Bit}, |
| 9546 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9547 | // (DI ZERO) - 870 |
| 9548 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9549 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9550 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r2}, |
| 9551 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9552 | // (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 874 |
| 9553 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9554 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9555 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9556 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9557 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9558 | // (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 879 |
| 9559 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9560 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9561 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9562 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9563 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9564 | // (DI_MM ZERO) - 884 |
| 9565 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9566 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9567 | // (DI_MMR6 ZERO) - 886 |
| 9568 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9569 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9570 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9571 | // (DMT ZERO) - 889 |
| 9572 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9573 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 9574 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9575 | // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 892 |
| 9576 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9577 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO_64}, |
| 9578 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9579 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9580 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips3}, |
| 9581 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9582 | // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 898 |
| 9583 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9584 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO_64}, |
| 9585 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9586 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9587 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips3}, |
| 9588 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9589 | // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 904 |
| 9590 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9591 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO_64}, |
| 9592 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9593 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9594 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips3}, |
| 9595 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9596 | // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 910 |
| 9597 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9598 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO_64}, |
| 9599 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9600 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9601 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips3}, |
| 9602 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9603 | // (DVPE ZERO) - 916 |
| 9604 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9605 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 9606 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9607 | // (EI ZERO) - 919 |
| 9608 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9609 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9610 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r2}, |
| 9611 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9612 | // (EI_MM ZERO) - 923 |
| 9613 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9614 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9615 | // (EI_MMR6 ZERO) - 925 |
| 9616 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9617 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9618 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9619 | // (EMT ZERO) - 928 |
| 9620 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9621 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 9622 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9623 | // (EVPE ZERO) - 931 |
| 9624 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9625 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 9626 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9627 | // (HYPCALL 0) - 934 |
| 9628 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9629 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9630 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r5}, |
| 9631 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureVirt}, |
| 9632 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9633 | // (HYPCALL_MM 0) - 939 |
| 9634 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9635 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9636 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r5}, |
| 9637 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureVirt}, |
| 9638 | // (JALR ZERO, GPR32Opnd:$rs) - 943 |
| 9639 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9640 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9641 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9642 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureGP64Bit}, |
| 9643 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9644 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9645 | // (JALR64 ZERO_64, GPR64Opnd:$rs) - 949 |
| 9646 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO_64}, |
| 9647 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9648 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9649 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips64r6}, |
| 9650 | // (JALRC_HB_MMR6 RA, GPR32Opnd:$rs) - 953 |
| 9651 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::RA}, |
| 9652 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9653 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9654 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9655 | // (JALRC_MMR6 RA, GPR32Opnd:$rs) - 957 |
| 9656 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::RA}, |
| 9657 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9658 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9659 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9660 | // (JALR_HB RA, GPR32Opnd:$rs) - 961 |
| 9661 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::RA}, |
| 9662 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9663 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9664 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32}, |
| 9665 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9666 | // (JALR_HB64 RA_64, GPR64Opnd:$rs) - 966 |
| 9667 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::RA_64}, |
| 9668 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9669 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9670 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips64}, |
| 9671 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9672 | // (JIALC GPR32Opnd:$rs, 0) - 971 |
| 9673 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9674 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9675 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9676 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureGP64Bit}, |
| 9677 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9678 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9679 | // (JIALC64 GPR64Opnd:$rs, 0) - 977 |
| 9680 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9681 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9682 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9683 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips64r6}, |
| 9684 | // (JIC GPR32Opnd:$rs, 0) - 981 |
| 9685 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9686 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9687 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9688 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureGP64Bit}, |
| 9689 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9690 | // (JIC64 GPR64Opnd:$rs, 0) - 986 |
| 9691 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9692 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9693 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9694 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips64r6}, |
| 9695 | // (MOVE16_MM ZERO, ZERO) - 990 |
| 9696 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9697 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9698 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9699 | // (Move32R16 ZERO, S0) - 993 |
| 9700 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9701 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::S0}, |
| 9702 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips16}, |
| 9703 | // (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 996 |
| 9704 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9705 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9706 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9707 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9708 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureGP64Bit}, |
| 9709 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9710 | // (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 1002 |
| 9711 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9712 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9713 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO_64}, |
| 9714 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureGP64Bit}, |
| 9715 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9716 | // (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1007 |
| 9717 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9718 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::HWRegsRegClassID}, |
| 9719 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9720 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9721 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9722 | // (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0) - 1012 |
| 9723 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR64RegClassID}, |
| 9724 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::HWRegsRegClassID}, |
| 9725 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9726 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureGP64Bit}, |
| 9727 | // (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1016 |
| 9728 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9729 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::HWRegsRegClassID}, |
| 9730 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9731 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9732 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9733 | // (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1021 |
| 9734 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9735 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::HWRegsRegClassID}, |
| 9736 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9737 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9738 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9739 | // (SDBBP 0) - 1026 |
| 9740 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9741 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9742 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32}, |
| 9743 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9744 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips64r6}, |
| 9745 | // (SDBBP_MMR6 0) - 1031 |
| 9746 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9747 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9748 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9749 | // (SDBBP_R6 0) - 1034 |
| 9750 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9751 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9752 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9753 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9754 | // (SIGRIE 0) - 1038 |
| 9755 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9756 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9757 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9758 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9759 | // (SIGRIE_MMR6 0) - 1042 |
| 9760 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9761 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9762 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9763 | // (SLL ZERO, ZERO, 0) - 1045 |
| 9764 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9765 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9766 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9767 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9768 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9769 | // (SLL_MM ZERO, ZERO, 0) - 1050 |
| 9770 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9771 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9772 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9773 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9774 | // (SLL_MMR6 ZERO, ZERO, 0) - 1054 |
| 9775 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9776 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9777 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9778 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9779 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9780 | // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1059 |
| 9781 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9782 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9783 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9784 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9785 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9786 | // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1064 |
| 9787 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9788 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9789 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9790 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9791 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9792 | // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1069 |
| 9793 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9794 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9795 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9796 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9797 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9798 | // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1074 |
| 9799 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9800 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9801 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9802 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9803 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9804 | // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1079 |
| 9805 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9806 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9807 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9808 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9809 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9810 | // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1084 |
| 9811 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9812 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9813 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9814 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9815 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9816 | // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1089 |
| 9817 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9818 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9819 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9820 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9821 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9822 | // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1094 |
| 9823 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9824 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9825 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9826 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9827 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9828 | // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1099 |
| 9829 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9830 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9831 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9832 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9833 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9834 | // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1104 |
| 9835 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9836 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9837 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9838 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9839 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9840 | // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1109 |
| 9841 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9842 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9843 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9844 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9845 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9846 | // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1114 |
| 9847 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9848 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9849 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 9850 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9851 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips32r6}, |
| 9852 | // (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset) - 1119 |
| 9853 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9854 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9855 | // (SYNC 0) - 1121 |
| 9856 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9857 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9858 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 9859 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9860 | // (SYNC_MM 0) - 1125 |
| 9861 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9862 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9863 | // (SYNC_MMR6 0) - 1127 |
| 9864 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9865 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9866 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips32r6}, |
| 9867 | // (SYSCALL 0) - 1130 |
| 9868 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9869 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9870 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9871 | // (SYSCALL_MM 0) - 1133 |
| 9872 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9873 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9874 | // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1135 |
| 9875 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9876 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9877 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9878 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9879 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 9880 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9881 | // (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1141 |
| 9882 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9883 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9884 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9885 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9886 | // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1145 |
| 9887 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9888 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9889 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9890 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9891 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 9892 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9893 | // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1151 |
| 9894 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9895 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9896 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9897 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9898 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 9899 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9900 | // (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1157 |
| 9901 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9902 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9903 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9904 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9905 | // (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1161 |
| 9906 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9907 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9908 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9909 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9910 | // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1165 |
| 9911 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9912 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9913 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9914 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9915 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 9916 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9917 | // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1171 |
| 9918 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9919 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9920 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9921 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9922 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 9923 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9924 | // (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1177 |
| 9925 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9926 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9927 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9928 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9929 | // (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1181 |
| 9930 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9931 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9932 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9933 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9934 | // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1185 |
| 9935 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9936 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9937 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9938 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMips16}, |
| 9939 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMips2}, |
| 9940 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9941 | // (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1191 |
| 9942 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9943 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9944 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9945 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9946 | // (WAIT_MM 0) - 1195 |
| 9947 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 9948 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9949 | // (WRDSP GPR32Opnd:$rt, 31) - 1197 |
| 9950 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9951 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 9952 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureDSP}, |
| 9953 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9954 | // (WRDSP_MM GPR32Opnd:$rt, 31) - 1201 |
| 9955 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9956 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 9957 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureDSP}, |
| 9958 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMicroMips}, |
| 9959 | // (YIELD ZERO, GPR32Opnd:$rs) - 1205 |
| 9960 | {.Kind: AliasPatternCond::K_Reg, .Value: Mips::ZERO}, |
| 9961 | {.Kind: AliasPatternCond::K_RegClass, .Value: Mips::GPR32RegClassID}, |
| 9962 | {.Kind: AliasPatternCond::K_Feature, .Value: Mips::FeatureMT}, |
| 9963 | {.Kind: AliasPatternCond::K_NegFeature, .Value: Mips::FeatureMicroMips}, |
| 9964 | }; |
| 9965 | |
| 9966 | static const char AsmStrings[] = |
| 9967 | /* 0 */ "mftacx $\x01\0" |
| 9968 | /* 10 */ "mftc0 $\x01, $\x02\0" |
| 9969 | /* 23 */ "mfthi $\x01\0" |
| 9970 | /* 32 */ "mftlo $\x01\0" |
| 9971 | /* 41 */ "mttacx $\x02\0" |
| 9972 | /* 51 */ "mttc0 $\x02, $\x01\0" |
| 9973 | /* 64 */ "mtthi $\x02\0" |
| 9974 | /* 73 */ "mttlo $\x02\0" |
| 9975 | /* 82 */ "nor $\x01, $\x03\0" |
| 9976 | /* 93 */ "slt $\x01, $\x03\0" |
| 9977 | /* 104 */ "sltu $\x01, $\x03\0" |
| 9978 | /* 116 */ "lapc $\x01, $\x02\0" |
| 9979 | /* 128 */ "move $\x01, $\x02\0" |
| 9980 | /* 140 */ "bc1f $\xFF\x02\x01\0" |
| 9981 | /* 150 */ "bc1fl $\xFF\x02\x01\0" |
| 9982 | /* 161 */ "bc1t $\xFF\x02\x01\0" |
| 9983 | /* 171 */ "bc1tl $\xFF\x02\x01\0" |
| 9984 | /* 182 */ "beqzl $\x01, $\xFF\x03\x01\0" |
| 9985 | /* 197 */ "bal $\xFF\x02\x01\0" |
| 9986 | /* 206 */ "nal\0" |
| 9987 | /* 210 */ "bnezl $\x01, $\xFF\x03\x01\0" |
| 9988 | /* 225 */ "break\0" |
| 9989 | /* 231 */ "break $\xFF\x01\x02\0" |
| 9990 | /* 242 */ "c.eq.d $\x02, $\x03\0" |
| 9991 | /* 256 */ "c.eq.s $\x02, $\x03\0" |
| 9992 | /* 270 */ "c.f.d $\x02, $\x03\0" |
| 9993 | /* 283 */ "c.f.s $\x02, $\x03\0" |
| 9994 | /* 296 */ "c.le.d $\x02, $\x03\0" |
| 9995 | /* 310 */ "c.le.s $\x02, $\x03\0" |
| 9996 | /* 324 */ "c.lt.d $\x02, $\x03\0" |
| 9997 | /* 338 */ "c.lt.s $\x02, $\x03\0" |
| 9998 | /* 352 */ "c.nge.d $\x02, $\x03\0" |
| 9999 | /* 367 */ "c.nge.s $\x02, $\x03\0" |
| 10000 | /* 382 */ "c.ngle.d $\x02, $\x03\0" |
| 10001 | /* 398 */ "c.ngle.s $\x02, $\x03\0" |
| 10002 | /* 414 */ "c.ngl.d $\x02, $\x03\0" |
| 10003 | /* 429 */ "c.ngl.s $\x02, $\x03\0" |
| 10004 | /* 444 */ "c.ngt.d $\x02, $\x03\0" |
| 10005 | /* 459 */ "c.ngt.s $\x02, $\x03\0" |
| 10006 | /* 474 */ "c.ole.d $\x02, $\x03\0" |
| 10007 | /* 489 */ "c.ole.s $\x02, $\x03\0" |
| 10008 | /* 504 */ "c.olt.d $\x02, $\x03\0" |
| 10009 | /* 519 */ "c.olt.s $\x02, $\x03\0" |
| 10010 | /* 534 */ "c.seq.d $\x02, $\x03\0" |
| 10011 | /* 549 */ "c.seq.s $\x02, $\x03\0" |
| 10012 | /* 564 */ "c.sf.d $\x02, $\x03\0" |
| 10013 | /* 578 */ "c.sf.s $\x02, $\x03\0" |
| 10014 | /* 592 */ "c.ueq.d $\x02, $\x03\0" |
| 10015 | /* 607 */ "c.ueq.s $\x02, $\x03\0" |
| 10016 | /* 622 */ "c.ule.d $\x02, $\x03\0" |
| 10017 | /* 637 */ "c.ule.s $\x02, $\x03\0" |
| 10018 | /* 652 */ "c.ult.d $\x02, $\x03\0" |
| 10019 | /* 667 */ "c.ult.s $\x02, $\x03\0" |
| 10020 | /* 682 */ "c.un.d $\x02, $\x03\0" |
| 10021 | /* 696 */ "c.un.s $\x02, $\x03\0" |
| 10022 | /* 710 */ "di\0" |
| 10023 | /* 713 */ "div $\x01, $\x03\0" |
| 10024 | /* 724 */ "divu $\x01, $\x03\0" |
| 10025 | /* 736 */ "dmt\0" |
| 10026 | /* 740 */ "dneg $\x01, $\x03\0" |
| 10027 | /* 752 */ "dneg $\x01\0" |
| 10028 | /* 760 */ "dnegu $\x01, $\x03\0" |
| 10029 | /* 773 */ "dnegu $\x01\0" |
| 10030 | /* 782 */ "dvpe\0" |
| 10031 | /* 787 */ "ei\0" |
| 10032 | /* 790 */ "emt\0" |
| 10033 | /* 794 */ "evpe\0" |
| 10034 | /* 799 */ "hypcall\0" |
| 10035 | /* 807 */ "jr $\x02\0" |
| 10036 | /* 813 */ "jalrc.hb $\x02\0" |
| 10037 | /* 825 */ "jalrc $\x02\0" |
| 10038 | /* 834 */ "jalr.hb $\x02\0" |
| 10039 | /* 845 */ "jalrc $\x01\0" |
| 10040 | /* 854 */ "jrc $\x01\0" |
| 10041 | /* 861 */ "nop\0" |
| 10042 | /* 865 */ "rdhwr $\x01, $\x02\0" |
| 10043 | /* 878 */ "sdbbp\0" |
| 10044 | /* 884 */ "sigrie\0" |
| 10045 | /* 891 */ "neg $\x01, $\x03\0" |
| 10046 | /* 902 */ "neg $\x01\0" |
| 10047 | /* 909 */ "negu $\x01, $\x03\0" |
| 10048 | /* 921 */ "negu $\x01\0" |
| 10049 | /* 929 */ "sw $\x01, $\xFF\x02\x03\0" |
| 10050 | /* 941 */ "sync\0" |
| 10051 | /* 946 */ "syscall\0" |
| 10052 | /* 954 */ "teq $\x01, $\x02\0" |
| 10053 | /* 965 */ "tge $\x01, $\x02\0" |
| 10054 | /* 976 */ "tgeu $\x01, $\x02\0" |
| 10055 | /* 988 */ "tlt $\x01, $\x02\0" |
| 10056 | /* 999 */ "tltu $\x01, $\x02\0" |
| 10057 | /* 1011 */ "tne $\x01, $\x02\0" |
| 10058 | /* 1022 */ "wait\0" |
| 10059 | /* 1027 */ "wrdsp $\x01\0" |
| 10060 | /* 1036 */ "yield $\x02\0" |
| 10061 | ; |
| 10062 | |
| 10063 | #ifndef NDEBUG |
| 10064 | static struct SortCheck { |
| 10065 | SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| 10066 | assert(std::is_sorted( |
| 10067 | OpToPatterns.begin(), OpToPatterns.end(), |
| 10068 | [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| 10069 | return L.Opcode < R.Opcode; |
| 10070 | }) && |
| 10071 | "tablegen failed to sort opcode patterns"); |
| 10072 | } |
| 10073 | } sortCheckVar(OpToPatterns); |
| 10074 | #endif |
| 10075 | |
| 10076 | AliasMatchingData M { |
| 10077 | .OpToPatterns: ArrayRef(OpToPatterns), |
| 10078 | .Patterns: ArrayRef(Patterns), |
| 10079 | .PatternConds: ArrayRef(Conds), |
| 10080 | .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)), |
| 10081 | .ValidateMCOperand: nullptr, |
| 10082 | }; |
| 10083 | const char *AsmString = matchAliasPatterns(MI, STI: &STI, M); |
| 10084 | if (!AsmString) return false; |
| 10085 | |
| 10086 | unsigned I = 0; |
| 10087 | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| 10088 | AsmString[I] != '$' && AsmString[I] != '\0') |
| 10089 | ++I; |
| 10090 | OS << '\t' << StringRef(AsmString, I); |
| 10091 | if (AsmString[I] != '\0') { |
| 10092 | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| 10093 | OS << '\t'; |
| 10094 | ++I; |
| 10095 | } |
| 10096 | do { |
| 10097 | if (AsmString[I] == '$') { |
| 10098 | ++I; |
| 10099 | if (AsmString[I] == (char)0xff) { |
| 10100 | ++I; |
| 10101 | int OpIdx = AsmString[I++] - 1; |
| 10102 | int PrintMethodIdx = AsmString[I++] - 1; |
| 10103 | printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS); |
| 10104 | } else |
| 10105 | printOperand(MI, OpNo: unsigned(AsmString[I++]) - 1, STI, O&: OS); |
| 10106 | } else { |
| 10107 | OS << AsmString[I++]; |
| 10108 | } |
| 10109 | } while (AsmString[I] != '\0'); |
| 10110 | } |
| 10111 | |
| 10112 | return true; |
| 10113 | } |
| 10114 | |
| 10115 | void MipsInstPrinter::printCustomAliasOperand( |
| 10116 | const MCInst *MI, uint64_t Address, unsigned OpIdx, |
| 10117 | unsigned PrintMethodIdx, |
| 10118 | const MCSubtargetInfo &STI, |
| 10119 | raw_ostream &OS) { |
| 10120 | switch (PrintMethodIdx) { |
| 10121 | default: |
| 10122 | llvm_unreachable("Unknown PrintMethod kind"); |
| 10123 | break; |
| 10124 | case 0: |
| 10125 | printBranchOperand(MI, Address, OpNo: OpIdx, STI, O&: OS); |
| 10126 | break; |
| 10127 | case 1: |
| 10128 | printUImm<10>(MI, opNum: OpIdx, STI, O&: OS); |
| 10129 | break; |
| 10130 | case 2: |
| 10131 | printMemOperand(MI, opNum: OpIdx, STI, O&: OS); |
| 10132 | break; |
| 10133 | } |
| 10134 | } |
| 10135 | |
| 10136 | #endif // PRINT_ALIAS_INSTR |
| 10137 |
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