1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Sparc.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10/// getMnemonic - This method is automatically generated by tablegen
11/// from the instruction set description.
12std::pair<const char *, uint64_t>
13SparcInstPrinter::getMnemonic(const MCInst &MI) const {
14
15#ifdef __GNUC__
16#pragma GCC diagnostic push
17#pragma GCC diagnostic ignored "-Woverlength-strings"
18#endif
19 static const char AsmStrs[] = {
20 /* 0 */ "fcmpd %fcc0, \000"
21 /* 14 */ "fcmpq %fcc0, \000"
22 /* 28 */ "fcmps %fcc0, \000"
23 /* 42 */ "rd %wim, \000"
24 /* 52 */ "rdpr %fq, \000"
25 /* 63 */ "rd %tbr, \000"
26 /* 73 */ "rd %psr, \000"
27 /* 83 */ "fsrc1 \000"
28 /* 90 */ "fandnot1 \000"
29 /* 100 */ "fnot1 \000"
30 /* 107 */ "fornot1 \000"
31 /* 116 */ "fsra32 \000"
32 /* 124 */ "fpsub32 \000"
33 /* 133 */ "fpadd32 \000"
34 /* 142 */ "edge32 \000"
35 /* 150 */ "fcmple32 \000"
36 /* 160 */ "fcmpne32 \000"
37 /* 170 */ "fpack32 \000"
38 /* 179 */ "cmask32 \000"
39 /* 188 */ "fsll32 \000"
40 /* 196 */ "fsrl32 \000"
41 /* 204 */ "fcmpeq32 \000"
42 /* 214 */ "fslas32 \000"
43 /* 223 */ "fcmpgt32 \000"
44 /* 233 */ "array32 \000"
45 /* 242 */ "fsrc2 \000"
46 /* 249 */ "fandnot2 \000"
47 /* 259 */ "fnot2 \000"
48 /* 266 */ "fornot2 \000"
49 /* 275 */ "fpadd64 \000"
50 /* 284 */ "fsra16 \000"
51 /* 292 */ "fpsub16 \000"
52 /* 301 */ "fpadd16 \000"
53 /* 310 */ "edge16 \000"
54 /* 318 */ "fcmple16 \000"
55 /* 328 */ "fcmpne16 \000"
56 /* 338 */ "fpack16 \000"
57 /* 347 */ "cmask16 \000"
58 /* 356 */ "fsll16 \000"
59 /* 364 */ "fsrl16 \000"
60 /* 372 */ "fchksm16 \000"
61 /* 382 */ "fmean16 \000"
62 /* 391 */ "fcmpeq16 \000"
63 /* 401 */ "fslas16 \000"
64 /* 410 */ "fcmpgt16 \000"
65 /* 420 */ "fmul8x16 \000"
66 /* 430 */ "fmuld8ulx16 \000"
67 /* 443 */ "fmul8ulx16 \000"
68 /* 455 */ "fmuld8sux16 \000"
69 /* 468 */ "fmul8sux16 \000"
70 /* 480 */ "array16 \000"
71 /* 489 */ "edge8 \000"
72 /* 496 */ "cmask8 \000"
73 /* 504 */ "array8 \000"
74 /* 512 */ "!ADJCALLSTACKDOWN \000"
75 /* 531 */ "!ADJCALLSTACKUP \000"
76 /* 548 */ "stba \000"
77 /* 554 */ "stda \000"
78 /* 560 */ "stha \000"
79 /* 566 */ "stqa \000"
80 /* 572 */ "sra \000"
81 /* 577 */ "faligndata \000"
82 /* 589 */ "sta \000"
83 /* 594 */ "stxa \000"
84 /* 600 */ "stb \000"
85 /* 605 */ "sub \000"
86 /* 610 */ "smac \000"
87 /* 616 */ "umac \000"
88 /* 622 */ "tsubcc \000"
89 /* 630 */ "addxccc \000"
90 /* 639 */ "taddcc \000"
91 /* 647 */ "andcc \000"
92 /* 654 */ "smulcc \000"
93 /* 662 */ "umulcc \000"
94 /* 670 */ "andncc \000"
95 /* 678 */ "orncc \000"
96 /* 685 */ "xnorcc \000"
97 /* 693 */ "xorcc \000"
98 /* 700 */ "mulscc \000"
99 /* 708 */ "sdivcc \000"
100 /* 716 */ "udivcc \000"
101 /* 724 */ "subxcc \000"
102 /* 732 */ "addxcc \000"
103 /* 740 */ "popc \000"
104 /* 746 */ "addxc \000"
105 /* 753 */ "fsubd \000"
106 /* 760 */ "fhsubd \000"
107 /* 768 */ "fmsubd \000"
108 /* 776 */ "fnmsubd \000"
109 /* 785 */ "add \000"
110 /* 790 */ "faddd \000"
111 /* 797 */ "fhaddd \000"
112 /* 805 */ "fnhaddd \000"
113 /* 814 */ "fmaddd \000"
114 /* 822 */ "fnmaddd \000"
115 /* 831 */ "fnaddd \000"
116 /* 839 */ "fcmped \000"
117 /* 847 */ "fnegd \000"
118 /* 854 */ "fmuld \000"
119 /* 861 */ "fnmuld \000"
120 /* 869 */ "fsmuld \000"
121 /* 877 */ "fnsmuld \000"
122 /* 886 */ "fand \000"
123 /* 892 */ "fnand \000"
124 /* 899 */ "fexpand \000"
125 /* 908 */ "fitod \000"
126 /* 915 */ "fqtod \000"
127 /* 922 */ "fstod \000"
128 /* 929 */ "fxtod \000"
129 /* 936 */ "movxtod \000"
130 /* 945 */ "fcmpd \000"
131 /* 952 */ "flcmpd \000"
132 /* 960 */ "rd \000"
133 /* 964 */ "fabsd \000"
134 /* 971 */ "fsqrtd \000"
135 /* 979 */ "std \000"
136 /* 984 */ "fdivd \000"
137 /* 991 */ "fmovd \000"
138 /* 998 */ "fpmerge \000"
139 /* 1007 */ "bshuffle \000"
140 /* 1017 */ "fone \000"
141 /* 1023 */ "restore \000"
142 /* 1032 */ "save \000"
143 /* 1038 */ "flush \000"
144 /* 1045 */ "sth \000"
145 /* 1050 */ "sethi \000"
146 /* 1057 */ "fpmaddxhi \000"
147 /* 1068 */ "umulxhi \000"
148 /* 1077 */ "xmulxhi \000"
149 /* 1086 */ "fdtoi \000"
150 /* 1093 */ "fqtoi \000"
151 /* 1100 */ "fstoi \000"
152 /* 1107 */ "bmask \000"
153 /* 1114 */ "edge32l \000"
154 /* 1123 */ "edge16l \000"
155 /* 1132 */ "edge8l \000"
156 /* 1140 */ "fmul8x16al \000"
157 /* 1152 */ "call \000"
158 /* 1158 */ "sll \000"
159 /* 1163 */ "jmpl \000"
160 /* 1169 */ "alignaddrl \000"
161 /* 1181 */ "srl \000"
162 /* 1186 */ "smul \000"
163 /* 1192 */ "umul \000"
164 /* 1198 */ "siam \000"
165 /* 1204 */ "edge32n \000"
166 /* 1213 */ "edge16n \000"
167 /* 1222 */ "edge8n \000"
168 /* 1230 */ "andn \000"
169 /* 1236 */ "edge32ln \000"
170 /* 1246 */ "edge16ln \000"
171 /* 1256 */ "edge8ln \000"
172 /* 1265 */ "orn \000"
173 /* 1270 */ "pdistn \000"
174 /* 1278 */ "fzero \000"
175 /* 1285 */ "unimp \000"
176 /* 1292 */ "jmp \000"
177 /* 1297 */ "fsubq \000"
178 /* 1304 */ "faddq \000"
179 /* 1311 */ "fcmpeq \000"
180 /* 1319 */ "fnegq \000"
181 /* 1326 */ "fdmulq \000"
182 /* 1334 */ "fmulq \000"
183 /* 1341 */ "fdtoq \000"
184 /* 1348 */ "fitoq \000"
185 /* 1355 */ "fstoq \000"
186 /* 1362 */ "fxtoq \000"
187 /* 1369 */ "fcmpq \000"
188 /* 1376 */ "fabsq \000"
189 /* 1383 */ "fsqrtq \000"
190 /* 1391 */ "stq \000"
191 /* 1396 */ "fdivq \000"
192 /* 1403 */ "fmovq \000"
193 /* 1410 */ "membar \000"
194 /* 1418 */ "alignaddr \000"
195 /* 1429 */ "sir \000"
196 /* 1434 */ "for \000"
197 /* 1439 */ "fnor \000"
198 /* 1445 */ "fxnor \000"
199 /* 1452 */ "fxor \000"
200 /* 1458 */ "rdpr \000"
201 /* 1464 */ "wrpr \000"
202 /* 1470 */ "pwr \000"
203 /* 1475 */ "fsrc1s \000"
204 /* 1483 */ "fandnot1s \000"
205 /* 1494 */ "fnot1s \000"
206 /* 1502 */ "fornot1s \000"
207 /* 1512 */ "fpsub32s \000"
208 /* 1522 */ "fpadd32s \000"
209 /* 1532 */ "fsrc2s \000"
210 /* 1540 */ "fandnot2s \000"
211 /* 1551 */ "fnot2s \000"
212 /* 1559 */ "fornot2s \000"
213 /* 1569 */ "fpsub16s \000"
214 /* 1579 */ "fpadd16s \000"
215 /* 1589 */ "fsubs \000"
216 /* 1596 */ "fhsubs \000"
217 /* 1604 */ "fmsubs \000"
218 /* 1612 */ "fnmsubs \000"
219 /* 1621 */ "fadds \000"
220 /* 1628 */ "fhadds \000"
221 /* 1636 */ "fnhadds \000"
222 /* 1645 */ "fmadds \000"
223 /* 1653 */ "fnmadds \000"
224 /* 1662 */ "fnadds \000"
225 /* 1670 */ "fands \000"
226 /* 1677 */ "fnands \000"
227 /* 1685 */ "fones \000"
228 /* 1692 */ "fcmpes \000"
229 /* 1700 */ "fnegs \000"
230 /* 1707 */ "fmuls \000"
231 /* 1714 */ "fnmuls \000"
232 /* 1722 */ "fzeros \000"
233 /* 1730 */ "fdtos \000"
234 /* 1737 */ "fitos \000"
235 /* 1744 */ "fqtos \000"
236 /* 1751 */ "movwtos \000"
237 /* 1760 */ "fxtos \000"
238 /* 1767 */ "fcmps \000"
239 /* 1774 */ "flcmps \000"
240 /* 1782 */ "fors \000"
241 /* 1788 */ "fnors \000"
242 /* 1795 */ "fxnors \000"
243 /* 1803 */ "fxors \000"
244 /* 1810 */ "fabss \000"
245 /* 1817 */ "fsqrts \000"
246 /* 1825 */ "fdivs \000"
247 /* 1832 */ "fmovs \000"
248 /* 1839 */ "set \000"
249 /* 1844 */ "lzcnt \000"
250 /* 1851 */ "pdist \000"
251 /* 1858 */ "rett \000"
252 /* 1864 */ "fmul8x16au \000"
253 /* 1876 */ "sdiv \000"
254 /* 1882 */ "udiv \000"
255 /* 1888 */ "tsubcctv \000"
256 /* 1898 */ "taddcctv \000"
257 /* 1908 */ "movstosw \000"
258 /* 1918 */ "setsw \000"
259 /* 1925 */ "movstouw \000"
260 /* 1935 */ "srax \000"
261 /* 1941 */ "subx \000"
262 /* 1947 */ "fpmaddx \000"
263 /* 1956 */ "fpackfix \000"
264 /* 1966 */ "sllx \000"
265 /* 1972 */ "srlx \000"
266 /* 1978 */ "xmulx \000"
267 /* 1985 */ "fdtox \000"
268 /* 1992 */ "movdtox \000"
269 /* 2001 */ "fqtox \000"
270 /* 2008 */ "fstox \000"
271 /* 2015 */ "setx \000"
272 /* 2021 */ "stx \000"
273 /* 2026 */ "sdivx \000"
274 /* 2033 */ "udivx \000"
275 /* 2040 */ "; SELECT_CC_DFP_FCC PSEUDO!\000"
276 /* 2068 */ "; SELECT_CC_QFP_FCC PSEUDO!\000"
277 /* 2096 */ "; SELECT_CC_FP_FCC PSEUDO!\000"
278 /* 2123 */ "; SELECT_CC_Int_FCC PSEUDO!\000"
279 /* 2151 */ "; SELECT_CC_DFP_ICC PSEUDO!\000"
280 /* 2179 */ "; SELECT_CC_QFP_ICC PSEUDO!\000"
281 /* 2207 */ "; SELECT_CC_FP_ICC PSEUDO!\000"
282 /* 2234 */ "; SELECT_CC_Int_ICC PSEUDO!\000"
283 /* 2262 */ "; SELECT_CC_DFP_XCC PSEUDO!\000"
284 /* 2290 */ "; SELECT_CC_QFP_XCC PSEUDO!\000"
285 /* 2318 */ "; SELECT_CC_FP_XCC PSEUDO!\000"
286 /* 2345 */ "; SELECT_CC_Int_XCC PSEUDO!\000"
287 /* 2373 */ "jmp %i7+\000"
288 /* 2382 */ "jmp %o7+\000"
289 /* 2391 */ "# XRay Function Patchable RET.\000"
290 /* 2422 */ "# XRay Typed Event Log.\000"
291 /* 2446 */ "# XRay Custom Event Log.\000"
292 /* 2471 */ "# XRay Function Enter.\000"
293 /* 2494 */ "# XRay Tail Call Exit.\000"
294 /* 2517 */ "# XRay Function Exit.\000"
295 /* 2539 */ "flush %g0\000"
296 /* 2549 */ "ta 1\000"
297 /* 2554 */ "ta 3\000"
298 /* 2559 */ "ta 5\000"
299 /* 2564 */ "LIFETIME_END\000"
300 /* 2577 */ "PSEUDO_PROBE\000"
301 /* 2590 */ "BUNDLE\000"
302 /* 2597 */ "FAKE_USE\000"
303 /* 2606 */ "DBG_VALUE\000"
304 /* 2616 */ "DBG_INSTR_REF\000"
305 /* 2630 */ "DBG_PHI\000"
306 /* 2638 */ "DBG_LABEL\000"
307 /* 2648 */ "LIFETIME_START\000"
308 /* 2663 */ "DBG_VALUE_LIST\000"
309 /* 2678 */ "std %cq, [\000"
310 /* 2689 */ "std %fq, [\000"
311 /* 2700 */ "st %csr, [\000"
312 /* 2711 */ "st %fsr, [\000"
313 /* 2722 */ "stx %fsr, [\000"
314 /* 2734 */ "ldsba [\000"
315 /* 2742 */ "lduba [\000"
316 /* 2750 */ "ldstuba [\000"
317 /* 2760 */ "ldda [\000"
318 /* 2767 */ "lda [\000"
319 /* 2773 */ "prefetcha [\000"
320 /* 2785 */ "ldsha [\000"
321 /* 2793 */ "lduha [\000"
322 /* 2801 */ "swapa [\000"
323 /* 2809 */ "ldqa [\000"
324 /* 2816 */ "casa [\000"
325 /* 2823 */ "ldswa [\000"
326 /* 2831 */ "ldxa [\000"
327 /* 2838 */ "casxa [\000"
328 /* 2846 */ "ldsb [\000"
329 /* 2853 */ "ldub [\000"
330 /* 2860 */ "ldstub [\000"
331 /* 2869 */ "ldd [\000"
332 /* 2875 */ "ld [\000"
333 /* 2880 */ "prefetch [\000"
334 /* 2891 */ "ldsh [\000"
335 /* 2898 */ "lduh [\000"
336 /* 2905 */ "swap [\000"
337 /* 2912 */ "ldq [\000"
338 /* 2918 */ "ldsw [\000"
339 /* 2925 */ "ldx [\000"
340 /* 2931 */ "cb\000"
341 /* 2934 */ "fb\000"
342 /* 2937 */ "cwb\000"
343 /* 2941 */ "cxb\000"
344 /* 2945 */ "restored\000"
345 /* 2954 */ "saved\000"
346 /* 2960 */ "fmovrd\000"
347 /* 2967 */ "fmovd\000"
348 /* 2973 */ "done\000"
349 /* 2978 */ "# FEntry call\000"
350 /* 2992 */ "allclean\000"
351 /* 3001 */ "shutdown\000"
352 /* 3010 */ "nop\000"
353 /* 3014 */ "fmovrq\000"
354 /* 3021 */ "fmovq\000"
355 /* 3027 */ "stbar\000"
356 /* 3033 */ "br\000"
357 /* 3036 */ "movr\000"
358 /* 3041 */ "fmovrs\000"
359 /* 3048 */ "fmovs\000"
360 /* 3054 */ "t\000"
361 /* 3056 */ "mov\000"
362 /* 3060 */ "flushw\000"
363 /* 3067 */ "normalw\000"
364 /* 3075 */ "invalw\000"
365 /* 3082 */ "otherw\000"
366 /* 3089 */ "retry\000"
367};
368#ifdef __GNUC__
369#pragma GCC diagnostic pop
370#endif
371
372 static const uint32_t OpInfo0[] = {
373 0U, // PHI
374 0U, // INLINEASM
375 0U, // INLINEASM_BR
376 0U, // CFI_INSTRUCTION
377 0U, // EH_LABEL
378 0U, // GC_LABEL
379 0U, // ANNOTATION_LABEL
380 0U, // KILL
381 0U, // EXTRACT_SUBREG
382 0U, // INSERT_SUBREG
383 0U, // IMPLICIT_DEF
384 0U, // INIT_UNDEF
385 0U, // SUBREG_TO_REG
386 0U, // COPY_TO_REGCLASS
387 2607U, // DBG_VALUE
388 2664U, // DBG_VALUE_LIST
389 2617U, // DBG_INSTR_REF
390 2631U, // DBG_PHI
391 2639U, // DBG_LABEL
392 0U, // REG_SEQUENCE
393 0U, // COPY
394 2591U, // BUNDLE
395 2649U, // LIFETIME_START
396 2565U, // LIFETIME_END
397 2578U, // PSEUDO_PROBE
398 0U, // ARITH_FENCE
399 0U, // STACKMAP
400 2979U, // FENTRY_CALL
401 0U, // PATCHPOINT
402 0U, // LOAD_STACK_GUARD
403 0U, // PREALLOCATED_SETUP
404 0U, // PREALLOCATED_ARG
405 0U, // STATEPOINT
406 0U, // LOCAL_ESCAPE
407 0U, // FAULTING_OP
408 0U, // PATCHABLE_OP
409 2472U, // PATCHABLE_FUNCTION_ENTER
410 2392U, // PATCHABLE_RET
411 2518U, // PATCHABLE_FUNCTION_EXIT
412 2495U, // PATCHABLE_TAIL_CALL
413 2447U, // PATCHABLE_EVENT_CALL
414 2423U, // PATCHABLE_TYPED_EVENT_CALL
415 0U, // ICALL_BRANCH_FUNNEL
416 2598U, // FAKE_USE
417 0U, // MEMBARRIER
418 0U, // JUMP_TABLE_DEBUG_INFO
419 0U, // CONVERGENCECTRL_ENTRY
420 0U, // CONVERGENCECTRL_ANCHOR
421 0U, // CONVERGENCECTRL_LOOP
422 0U, // CONVERGENCECTRL_GLUE
423 0U, // G_ASSERT_SEXT
424 0U, // G_ASSERT_ZEXT
425 0U, // G_ASSERT_ALIGN
426 0U, // G_ADD
427 0U, // G_SUB
428 0U, // G_MUL
429 0U, // G_SDIV
430 0U, // G_UDIV
431 0U, // G_SREM
432 0U, // G_UREM
433 0U, // G_SDIVREM
434 0U, // G_UDIVREM
435 0U, // G_AND
436 0U, // G_OR
437 0U, // G_XOR
438 0U, // G_ABDS
439 0U, // G_ABDU
440 0U, // G_IMPLICIT_DEF
441 0U, // G_PHI
442 0U, // G_FRAME_INDEX
443 0U, // G_GLOBAL_VALUE
444 0U, // G_PTRAUTH_GLOBAL_VALUE
445 0U, // G_CONSTANT_POOL
446 0U, // G_EXTRACT
447 0U, // G_UNMERGE_VALUES
448 0U, // G_INSERT
449 0U, // G_MERGE_VALUES
450 0U, // G_BUILD_VECTOR
451 0U, // G_BUILD_VECTOR_TRUNC
452 0U, // G_CONCAT_VECTORS
453 0U, // G_PTRTOINT
454 0U, // G_INTTOPTR
455 0U, // G_BITCAST
456 0U, // G_FREEZE
457 0U, // G_CONSTANT_FOLD_BARRIER
458 0U, // G_INTRINSIC_FPTRUNC_ROUND
459 0U, // G_INTRINSIC_TRUNC
460 0U, // G_INTRINSIC_ROUND
461 0U, // G_INTRINSIC_LRINT
462 0U, // G_INTRINSIC_LLRINT
463 0U, // G_INTRINSIC_ROUNDEVEN
464 0U, // G_READCYCLECOUNTER
465 0U, // G_READSTEADYCOUNTER
466 0U, // G_LOAD
467 0U, // G_SEXTLOAD
468 0U, // G_ZEXTLOAD
469 0U, // G_INDEXED_LOAD
470 0U, // G_INDEXED_SEXTLOAD
471 0U, // G_INDEXED_ZEXTLOAD
472 0U, // G_STORE
473 0U, // G_INDEXED_STORE
474 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
475 0U, // G_ATOMIC_CMPXCHG
476 0U, // G_ATOMICRMW_XCHG
477 0U, // G_ATOMICRMW_ADD
478 0U, // G_ATOMICRMW_SUB
479 0U, // G_ATOMICRMW_AND
480 0U, // G_ATOMICRMW_NAND
481 0U, // G_ATOMICRMW_OR
482 0U, // G_ATOMICRMW_XOR
483 0U, // G_ATOMICRMW_MAX
484 0U, // G_ATOMICRMW_MIN
485 0U, // G_ATOMICRMW_UMAX
486 0U, // G_ATOMICRMW_UMIN
487 0U, // G_ATOMICRMW_FADD
488 0U, // G_ATOMICRMW_FSUB
489 0U, // G_ATOMICRMW_FMAX
490 0U, // G_ATOMICRMW_FMIN
491 0U, // G_ATOMICRMW_FMAXIMUM
492 0U, // G_ATOMICRMW_FMINIMUM
493 0U, // G_ATOMICRMW_UINC_WRAP
494 0U, // G_ATOMICRMW_UDEC_WRAP
495 0U, // G_ATOMICRMW_USUB_COND
496 0U, // G_ATOMICRMW_USUB_SAT
497 0U, // G_FENCE
498 0U, // G_PREFETCH
499 0U, // G_BRCOND
500 0U, // G_BRINDIRECT
501 0U, // G_INVOKE_REGION_START
502 0U, // G_INTRINSIC
503 0U, // G_INTRINSIC_W_SIDE_EFFECTS
504 0U, // G_INTRINSIC_CONVERGENT
505 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
506 0U, // G_ANYEXT
507 0U, // G_TRUNC
508 0U, // G_CONSTANT
509 0U, // G_FCONSTANT
510 0U, // G_VASTART
511 0U, // G_VAARG
512 0U, // G_SEXT
513 0U, // G_SEXT_INREG
514 0U, // G_ZEXT
515 0U, // G_SHL
516 0U, // G_LSHR
517 0U, // G_ASHR
518 0U, // G_FSHL
519 0U, // G_FSHR
520 0U, // G_ROTR
521 0U, // G_ROTL
522 0U, // G_ICMP
523 0U, // G_FCMP
524 0U, // G_SCMP
525 0U, // G_UCMP
526 0U, // G_SELECT
527 0U, // G_UADDO
528 0U, // G_UADDE
529 0U, // G_USUBO
530 0U, // G_USUBE
531 0U, // G_SADDO
532 0U, // G_SADDE
533 0U, // G_SSUBO
534 0U, // G_SSUBE
535 0U, // G_UMULO
536 0U, // G_SMULO
537 0U, // G_UMULH
538 0U, // G_SMULH
539 0U, // G_UADDSAT
540 0U, // G_SADDSAT
541 0U, // G_USUBSAT
542 0U, // G_SSUBSAT
543 0U, // G_USHLSAT
544 0U, // G_SSHLSAT
545 0U, // G_SMULFIX
546 0U, // G_UMULFIX
547 0U, // G_SMULFIXSAT
548 0U, // G_UMULFIXSAT
549 0U, // G_SDIVFIX
550 0U, // G_UDIVFIX
551 0U, // G_SDIVFIXSAT
552 0U, // G_UDIVFIXSAT
553 0U, // G_FADD
554 0U, // G_FSUB
555 0U, // G_FMUL
556 0U, // G_FMA
557 0U, // G_FMAD
558 0U, // G_FDIV
559 0U, // G_FREM
560 0U, // G_FPOW
561 0U, // G_FPOWI
562 0U, // G_FEXP
563 0U, // G_FEXP2
564 0U, // G_FEXP10
565 0U, // G_FLOG
566 0U, // G_FLOG2
567 0U, // G_FLOG10
568 0U, // G_FLDEXP
569 0U, // G_FFREXP
570 0U, // G_FNEG
571 0U, // G_FPEXT
572 0U, // G_FPTRUNC
573 0U, // G_FPTOSI
574 0U, // G_FPTOUI
575 0U, // G_SITOFP
576 0U, // G_UITOFP
577 0U, // G_FPTOSI_SAT
578 0U, // G_FPTOUI_SAT
579 0U, // G_FABS
580 0U, // G_FCOPYSIGN
581 0U, // G_IS_FPCLASS
582 0U, // G_FCANONICALIZE
583 0U, // G_FMINNUM
584 0U, // G_FMAXNUM
585 0U, // G_FMINNUM_IEEE
586 0U, // G_FMAXNUM_IEEE
587 0U, // G_FMINIMUM
588 0U, // G_FMAXIMUM
589 0U, // G_FMINIMUMNUM
590 0U, // G_FMAXIMUMNUM
591 0U, // G_GET_FPENV
592 0U, // G_SET_FPENV
593 0U, // G_RESET_FPENV
594 0U, // G_GET_FPMODE
595 0U, // G_SET_FPMODE
596 0U, // G_RESET_FPMODE
597 0U, // G_PTR_ADD
598 0U, // G_PTRMASK
599 0U, // G_SMIN
600 0U, // G_SMAX
601 0U, // G_UMIN
602 0U, // G_UMAX
603 0U, // G_ABS
604 0U, // G_LROUND
605 0U, // G_LLROUND
606 0U, // G_BR
607 0U, // G_BRJT
608 0U, // G_VSCALE
609 0U, // G_INSERT_SUBVECTOR
610 0U, // G_EXTRACT_SUBVECTOR
611 0U, // G_INSERT_VECTOR_ELT
612 0U, // G_EXTRACT_VECTOR_ELT
613 0U, // G_SHUFFLE_VECTOR
614 0U, // G_SPLAT_VECTOR
615 0U, // G_STEP_VECTOR
616 0U, // G_VECTOR_COMPRESS
617 0U, // G_CTTZ
618 0U, // G_CTTZ_ZERO_UNDEF
619 0U, // G_CTLZ
620 0U, // G_CTLZ_ZERO_UNDEF
621 0U, // G_CTPOP
622 0U, // G_BSWAP
623 0U, // G_BITREVERSE
624 0U, // G_FCEIL
625 0U, // G_FCOS
626 0U, // G_FSIN
627 0U, // G_FSINCOS
628 0U, // G_FTAN
629 0U, // G_FACOS
630 0U, // G_FASIN
631 0U, // G_FATAN
632 0U, // G_FATAN2
633 0U, // G_FCOSH
634 0U, // G_FSINH
635 0U, // G_FTANH
636 0U, // G_FSQRT
637 0U, // G_FFLOOR
638 0U, // G_FRINT
639 0U, // G_FNEARBYINT
640 0U, // G_ADDRSPACE_CAST
641 0U, // G_BLOCK_ADDR
642 0U, // G_JUMP_TABLE
643 0U, // G_DYN_STACKALLOC
644 0U, // G_STACKSAVE
645 0U, // G_STACKRESTORE
646 0U, // G_STRICT_FADD
647 0U, // G_STRICT_FSUB
648 0U, // G_STRICT_FMUL
649 0U, // G_STRICT_FDIV
650 0U, // G_STRICT_FREM
651 0U, // G_STRICT_FMA
652 0U, // G_STRICT_FSQRT
653 0U, // G_STRICT_FLDEXP
654 0U, // G_READ_REGISTER
655 0U, // G_WRITE_REGISTER
656 0U, // G_MEMCPY
657 0U, // G_MEMCPY_INLINE
658 0U, // G_MEMMOVE
659 0U, // G_MEMSET
660 0U, // G_BZERO
661 0U, // G_TRAP
662 0U, // G_DEBUGTRAP
663 0U, // G_UBSANTRAP
664 0U, // G_VECREDUCE_SEQ_FADD
665 0U, // G_VECREDUCE_SEQ_FMUL
666 0U, // G_VECREDUCE_FADD
667 0U, // G_VECREDUCE_FMUL
668 0U, // G_VECREDUCE_FMAX
669 0U, // G_VECREDUCE_FMIN
670 0U, // G_VECREDUCE_FMAXIMUM
671 0U, // G_VECREDUCE_FMINIMUM
672 0U, // G_VECREDUCE_ADD
673 0U, // G_VECREDUCE_MUL
674 0U, // G_VECREDUCE_AND
675 0U, // G_VECREDUCE_OR
676 0U, // G_VECREDUCE_XOR
677 0U, // G_VECREDUCE_SMAX
678 0U, // G_VECREDUCE_SMIN
679 0U, // G_VECREDUCE_UMAX
680 0U, // G_VECREDUCE_UMIN
681 0U, // G_SBFX
682 0U, // G_UBFX
683 4609U, // ADJCALLSTACKDOWN
684 70164U, // ADJCALLSTACKUP
685 8206U, // GETPCX
686 2041U, // SELECT_CC_DFP_FCC
687 2152U, // SELECT_CC_DFP_ICC
688 2263U, // SELECT_CC_DFP_XCC
689 2097U, // SELECT_CC_FP_FCC
690 2208U, // SELECT_CC_FP_ICC
691 2319U, // SELECT_CC_FP_XCC
692 2124U, // SELECT_CC_Int_FCC
693 2235U, // SELECT_CC_Int_ICC
694 2346U, // SELECT_CC_Int_XCC
695 2069U, // SELECT_CC_QFP_FCC
696 2180U, // SELECT_CC_QFP_ICC
697 2291U, // SELECT_CC_QFP_XCC
698 2111280U, // SET
699 2111359U, // SETSW
700 20985824U, // SETX
701 20984449U, // ADDCCri
702 20984449U, // ADDCCrr
703 20985759U, // ADDCri
704 20985759U, // ADDCrr
705 20984541U, // ADDEri
706 20984541U, // ADDErr
707 20984555U, // ADDXC
708 20984439U, // ADDXCCC
709 20984594U, // ADDri
710 20984594U, // ADDrr
711 20985227U, // ALIGNADDR
712 20984978U, // ALIGNADDRL
713 2993U, // ALLCLEAN
714 20984456U, // ANDCCri
715 20984456U, // ANDCCrr
716 20984479U, // ANDNCCri
717 20984479U, // ANDNCCrr
718 20985039U, // ANDNri
719 20985039U, // ANDNrr
720 20984696U, // ANDri
721 20984696U, // ANDrr
722 20984289U, // ARRAY16
723 20984042U, // ARRAY32
724 20984313U, // ARRAY8
725 82471U, // BA
726 6445941U, // BCOND
727 6511477U, // BCONDA
728 91405U, // BINDri
729 91405U, // BINDrr
730 20984916U, // BMASK
731 155343735U, // BPFCC
732 155409271U, // BPFCCA
733 285559U, // BPFCCANT
734 351095U, // BPFCCNT
735 6708085U, // BPICC
736 482165U, // BPICCA
737 547701U, // BPICCANT
738 613237U, // BPICCNT
739 155343834U, // BPR
740 155409370U, // BPRA
741 285658U, // BPRANT
742 351194U, // BPRNT
743 6970229U, // BPXCC
744 744309U, // BPXCCA
745 809845U, // BPXCCANT
746 875381U, // BPXCCNT
747 20984816U, // BSHUFFLE
748 83073U, // CALL
749 17537U, // CALLi
750 91265U, // CALLri
751 4220033U, // CALLrii
752 91265U, // CALLrr
753 4220033U, // CALLrri
754 21904129U, // CASAri
755 9386753U, // CASArr
756 21904151U, // CASXAri
757 9386775U, // CASXArr
758 69980U, // CMASK16
759 69812U, // CMASK32
760 70129U, // CMASK8
761 6445940U, // CPBCOND
762 6511476U, // CPBCONDA
763 826432378U, // CWBCONDri
764 826432378U, // CWBCONDrr
765 826432382U, // CXBCONDri
766 826432382U, // CXBCONDrr
767 2974U, // DONE
768 20984119U, // EDGE16
769 20984932U, // EDGE16L
770 20985055U, // EDGE16LN
771 20985022U, // EDGE16N
772 20983951U, // EDGE32
773 20984923U, // EDGE32L
774 20985045U, // EDGE32LN
775 20985013U, // EDGE32N
776 20984298U, // EDGE8
777 20984941U, // EDGE8L
778 20985065U, // EDGE8LN
779 20985031U, // EDGE8N
780 2110405U, // FABSD
781 2110817U, // FABSQ
782 2111251U, // FABSS
783 20984599U, // FADDD
784 20985113U, // FADDQ
785 20985430U, // FADDS
786 20984386U, // FALIGNADATA
787 20984695U, // FAND
788 20983899U, // FANDNOT1
789 20985292U, // FANDNOT1S
790 20984058U, // FANDNOT2
791 20985349U, // FANDNOT2S
792 20985479U, // FANDS
793 6445943U, // FBCOND
794 6511479U, // FBCONDA
795 1071991U, // FBCONDA_V9
796 7428983U, // FBCOND_V9
797 20984181U, // FCHKSM16
798 5042U, // FCMPD
799 4097U, // FCMPD_V9
800 20984200U, // FCMPEQ16
801 20984013U, // FCMPEQ32
802 20984219U, // FCMPGT16
803 20984032U, // FCMPGT32
804 20984127U, // FCMPLE16
805 20983959U, // FCMPLE32
806 20984137U, // FCMPNE16
807 20983969U, // FCMPNE32
808 5466U, // FCMPQ
809 4111U, // FCMPQ_V9
810 5864U, // FCMPS
811 4125U, // FCMPS_V9
812 20984793U, // FDIVD
813 20985205U, // FDIVQ
814 20985634U, // FDIVS
815 20985135U, // FDMULQ
816 2110527U, // FDTOI
817 2110782U, // FDTOQ
818 2111171U, // FDTOS
819 2111426U, // FDTOX
820 2110340U, // FEXPAND
821 20984606U, // FHADDD
822 20985437U, // FHADDS
823 20984569U, // FHSUBD
824 20985405U, // FHSUBS
825 2110349U, // FITOD
826 2110789U, // FITOQ
827 2111178U, // FITOS
828 419435449U, // FLCMPD
829 419436271U, // FLCMPS
830 2540U, // FLUSH
831 3061U, // FLUSHW
832 91151U, // FLUSHri
833 91151U, // FLUSHrr
834 1900032815U, // FMADDD
835 1900033646U, // FMADDS
836 20984191U, // FMEAN16
837 2110432U, // FMOVD
838 17922968U, // FMOVD_FCC
839 17202072U, // FMOVD_ICC
840 17464216U, // FMOVD_XCC
841 2110844U, // FMOVQ
842 17923022U, // FMOVQ_FCC
843 17202126U, // FMOVQ_ICC
844 17464270U, // FMOVQ_XCC
845 35729U, // FMOVRD
846 35783U, // FMOVRQ
847 35810U, // FMOVRS
848 2111273U, // FMOVS
849 17923049U, // FMOVS_FCC
850 17202153U, // FMOVS_ICC
851 17464297U, // FMOVS_XCC
852 1900032769U, // FMSUBD
853 1900033605U, // FMSUBS
854 20984277U, // FMUL8SUX16
855 20984252U, // FMUL8ULX16
856 20984229U, // FMUL8X16
857 20984949U, // FMUL8X16AL
858 20985673U, // FMUL8X16AU
859 20984663U, // FMULD
860 20984264U, // FMULD8SUX16
861 20984239U, // FMULD8ULX16
862 20985143U, // FMULQ
863 20985516U, // FMULS
864 20984640U, // FNADDD
865 20985471U, // FNADDS
866 20984701U, // FNAND
867 20985486U, // FNANDS
868 2110288U, // FNEGD
869 2110760U, // FNEGQ
870 2111141U, // FNEGS
871 20984614U, // FNHADDD
872 20985445U, // FNHADDS
873 1900032823U, // FNMADDD
874 1900033654U, // FNMADDS
875 1900032777U, // FNMSUBD
876 1900033613U, // FNMSUBS
877 20984670U, // FNMULD
878 20985523U, // FNMULS
879 20985248U, // FNOR
880 20985597U, // FNORS
881 2109541U, // FNOT1
882 2110935U, // FNOT1S
883 2109700U, // FNOT2
884 2110992U, // FNOT2S
885 20984686U, // FNSMULD
886 70650U, // FONE
887 71318U, // FONES
888 20985243U, // FOR
889 20983916U, // FORNOT1
890 20985311U, // FORNOT1S
891 20984075U, // FORNOT2
892 20985368U, // FORNOT2S
893 20985591U, // FORS
894 2109779U, // FPACK16
895 20983979U, // FPACK32
896 2111397U, // FPACKFIX
897 20984110U, // FPADD16
898 20985388U, // FPADD16S
899 20983942U, // FPADD32
900 20985331U, // FPADD32S
901 20984084U, // FPADD64
902 1900033948U, // FPMADDX
903 1900033058U, // FPMADDXHI
904 20984807U, // FPMERGE
905 20984101U, // FPSUB16
906 20985378U, // FPSUB16S
907 20983933U, // FPSUB32
908 20985321U, // FPSUB32S
909 2110356U, // FQTOD
910 2110534U, // FQTOI
911 2111185U, // FQTOS
912 2111442U, // FQTOX
913 20984210U, // FSLAS16
914 20984023U, // FSLAS32
915 20984165U, // FSLL16
916 20983997U, // FSLL32
917 20984678U, // FSMULD
918 2110412U, // FSQRTD
919 2110824U, // FSQRTQ
920 2111258U, // FSQRTS
921 20984093U, // FSRA16
922 20983925U, // FSRA32
923 2109524U, // FSRC1
924 2110916U, // FSRC1S
925 2109683U, // FSRC2
926 2110973U, // FSRC2S
927 20984173U, // FSRL16
928 20984005U, // FSRL32
929 2110363U, // FSTOD
930 2110541U, // FSTOI
931 2110796U, // FSTOQ
932 2111449U, // FSTOX
933 20984562U, // FSUBD
934 20985106U, // FSUBQ
935 20985398U, // FSUBS
936 20985254U, // FXNOR
937 20985604U, // FXNORS
938 20985261U, // FXOR
939 20985612U, // FXORS
940 2110370U, // FXTOD
941 2110803U, // FXTOQ
942 2111201U, // FXTOS
943 70911U, // FZERO
944 71355U, // FZEROS
945 288529262U, // GDOP_LDXrr
946 288529212U, // GDOP_LDrr
947 3076U, // INVALW
948 2135180U, // JMPLri
949 2135180U, // JMPLrr
950 3054288U, // LDAri
951 28285648U, // LDArr
952 1272636U, // LDCSRri
953 1272636U, // LDCSRrr
954 3316540U, // LDCri
955 3316540U, // LDCrr
956 3054281U, // LDDAri
957 28285641U, // LDDArr
958 3316534U, // LDDCri
959 3316534U, // LDDCrr
960 3054281U, // LDDFAri
961 28285641U, // LDDFArr
962 3316534U, // LDDFri
963 3316534U, // LDDFrr
964 3316534U, // LDDri
965 3316534U, // LDDrr
966 3054288U, // LDFAri
967 28285648U, // LDFArr
968 1338172U, // LDFSRri
969 1338172U, // LDFSRrr
970 3316540U, // LDFri
971 3316540U, // LDFrr
972 3054330U, // LDQFAri
973 28285690U, // LDQFArr
974 3316577U, // LDQFri
975 3316577U, // LDQFrr
976 3054255U, // LDSBAri
977 28285615U, // LDSBArr
978 3316511U, // LDSBri
979 3316511U, // LDSBrr
980 3054306U, // LDSHAri
981 28285666U, // LDSHArr
982 3316556U, // LDSHri
983 3316556U, // LDSHrr
984 3054271U, // LDSTUBAri
985 28285631U, // LDSTUBArr
986 3316525U, // LDSTUBri
987 3316525U, // LDSTUBrr
988 3054344U, // LDSWAri
989 28285704U, // LDSWArr
990 3316583U, // LDSWri
991 3316583U, // LDSWrr
992 3054263U, // LDUBAri
993 28285623U, // LDUBArr
994 3316518U, // LDUBri
995 3316518U, // LDUBrr
996 3054314U, // LDUHAri
997 28285674U, // LDUHArr
998 3316563U, // LDUHri
999 3316563U, // LDUHrr
1000 3054352U, // LDXAri
1001 28285712U, // LDXArr
1002 1338222U, // LDXFSRri
1003 1338222U, // LDXFSRrr
1004 3316590U, // LDXri
1005 3316590U, // LDXrr
1006 3316540U, // LDri
1007 3316540U, // LDrr
1008 2111285U, // LZCNT
1009 42371U, // MEMBARi
1010 2111433U, // MOVDTOX
1011 17923057U, // MOVFCCri
1012 17923057U, // MOVFCCrr
1013 17202161U, // MOVICCri
1014 17202161U, // MOVICCrr
1015 35805U, // MOVRri
1016 35805U, // MOVRrr
1017 2111349U, // MOVSTOSW
1018 2111366U, // MOVSTOUW
1019 2111192U, // MOVWTOS
1020 17464305U, // MOVXCCri
1021 17464305U, // MOVXCCrr
1022 2110377U, // MOVXTOD
1023 20984509U, // MULSCCri
1024 20984509U, // MULSCCrr
1025 20985788U, // MULXri
1026 20985788U, // MULXrr
1027 3011U, // NOP
1028 3068U, // NORMALW
1029 20984496U, // ORCCri
1030 20984496U, // ORCCrr
1031 20984487U, // ORNCCri
1032 20984487U, // ORNCCrr
1033 20985074U, // ORNri
1034 20985074U, // ORNrr
1035 20985244U, // ORri
1036 20985244U, // ORrr
1037 3083U, // OTHERW
1038 20985660U, // PDIST
1039 20985079U, // PDISTN
1040 2110181U, // POPCrr
1041 13527766U, // PREFETCHAi
1042 15690454U, // PREFETCHAr
1043 13790017U, // PREFETCHi
1044 13790017U, // PREFETCHr
1045 33559999U, // PWRPSRri
1046 33559999U, // PWRPSRrr
1047 2110401U, // RDASR
1048 69685U, // RDFQ
1049 2110899U, // RDPR
1050 69706U, // RDPSR
1051 69696U, // RDTBR
1052 69675U, // RDWIM
1053 2946U, // RESTORED
1054 20984832U, // RESTOREri
1055 20984832U, // RESTORErr
1056 72006U, // RET
1057 72015U, // RETL
1058 3090U, // RETRY
1059 91971U, // RETTri
1060 91971U, // RETTrr
1061 2955U, // SAVED
1062 20984841U, // SAVEri
1063 20984841U, // SAVErr
1064 20984517U, // SDIVCCri
1065 20984517U, // SDIVCCrr
1066 20985835U, // SDIVXri
1067 20985835U, // SDIVXrr
1068 20985685U, // SDIVri
1069 20985685U, // SDIVrr
1070 2110491U, // SETHIi
1071 3002U, // SHUTDOWN
1072 70831U, // SIAM
1073 71062U, // SIR
1074 20985775U, // SLLXri
1075 20985775U, // SLLXrr
1076 20984967U, // SLLri
1077 20984967U, // SLLrr
1078 20984419U, // SMACri
1079 20984419U, // SMACrr
1080 20984463U, // SMULCCri
1081 20984463U, // SMULCCrr
1082 20984995U, // SMULri
1083 20984995U, // SMULrr
1084 20985744U, // SRAXri
1085 20985744U, // SRAXrr
1086 20984381U, // SRAri
1087 20984381U, // SRArr
1088 20985781U, // SRLXri
1089 20985781U, // SRLXrr
1090 20984990U, // SRLri
1091 20984990U, // SRLrr
1092 1421902U, // STAri
1093 11514446U, // STArr
1094 3028U, // STBAR
1095 1421861U, // STBAri
1096 11514405U, // STBArr
1097 1487449U, // STBri
1098 1487449U, // STBrr
1099 1469069U, // STCSRri
1100 1469069U, // STCSRrr
1101 1488703U, // STCri
1102 1488703U, // STCrr
1103 1421867U, // STDAri
1104 11514411U, // STDArr
1105 1469047U, // STDCQri
1106 1469047U, // STDCQrr
1107 1487828U, // STDCri
1108 1487828U, // STDCrr
1109 1421867U, // STDFAri
1110 11514411U, // STDFArr
1111 1469058U, // STDFQri
1112 1469058U, // STDFQrr
1113 1487828U, // STDFri
1114 1487828U, // STDFrr
1115 1487828U, // STDri
1116 1487828U, // STDrr
1117 1421902U, // STFAri
1118 11514446U, // STFArr
1119 1469080U, // STFSRri
1120 1469080U, // STFSRrr
1121 1488703U, // STFri
1122 1488703U, // STFrr
1123 1421873U, // STHAri
1124 11514417U, // STHArr
1125 1487894U, // STHri
1126 1487894U, // STHrr
1127 1421879U, // STQFAri
1128 11514423U, // STQFArr
1129 1488240U, // STQFri
1130 1488240U, // STQFrr
1131 1421907U, // STXAri
1132 11514451U, // STXArr
1133 1469091U, // STXFSRri
1134 1469091U, // STXFSRrr
1135 1488870U, // STXri
1136 1488870U, // STXrr
1137 1488703U, // STri
1138 1488703U, // STrr
1139 20984432U, // SUBCCri
1140 20984432U, // SUBCCrr
1141 20985750U, // SUBCri
1142 20985750U, // SUBCrr
1143 20984533U, // SUBEri
1144 20984533U, // SUBErr
1145 20984414U, // SUBri
1146 20984414U, // SUBrr
1147 3054322U, // SWAPAri
1148 28285682U, // SWAPArr
1149 3316570U, // SWAPri
1150 3316570U, // SWAPrr
1151 2550U, // TA1
1152 2555U, // TA3
1153 2560U, // TA5
1154 20985707U, // TADDCCTVri
1155 20985707U, // TADDCCTVrr
1156 20984448U, // TADDCCri
1157 20984448U, // TADDCCrr
1158 83073U, // TAIL_CALL
1159 91405U, // TAIL_CALLri
1160 52874223U, // TICCri
1161 52874223U, // TICCrr
1162 2705339154U, // TLS_ADDrr
1163 17537U, // TLS_CALL
1164 288529262U, // TLS_LDXrr
1165 288529212U, // TLS_LDrr
1166 52612079U, // TRAPri
1167 52612079U, // TRAPrr
1168 20985697U, // TSUBCCTVri
1169 20985697U, // TSUBCCTVrr
1170 20984431U, // TSUBCCri
1171 20984431U, // TSUBCCrr
1172 53136367U, // TXCCri
1173 53136367U, // TXCCrr
1174 20984525U, // UDIVCCri
1175 20984525U, // UDIVCCrr
1176 20985842U, // UDIVXri
1177 20985842U, // UDIVXrr
1178 20985691U, // UDIVri
1179 20985691U, // UDIVrr
1180 20984425U, // UMACri
1181 20984425U, // UMACrr
1182 20984471U, // UMULCCri
1183 20984471U, // UMULCCrr
1184 20984877U, // UMULXHI
1185 20985001U, // UMULri
1186 20985001U, // UMULrr
1187 70918U, // UNIMP
1188 419435442U, // V9FCMPD
1189 419435336U, // V9FCMPED
1190 419435808U, // V9FCMPEQ
1191 419436189U, // V9FCMPES
1192 419435866U, // V9FCMPQ
1193 419436264U, // V9FCMPS
1194 35736U, // V9FMOVD_FCC
1195 35790U, // V9FMOVQ_FCC
1196 35817U, // V9FMOVS_FCC
1197 35825U, // V9MOVFCCri
1198 35825U, // V9MOVFCCrr
1199 20985280U, // WRASRri
1200 20985280U, // WRASRrr
1201 20985273U, // WRPRri
1202 20985273U, // WRPRrr
1203 33560000U, // WRPSRri
1204 33560000U, // WRPSRrr
1205 67114432U, // WRTBRri
1206 67114432U, // WRTBRrr
1207 83891648U, // WRWIMri
1208 83891648U, // WRWIMrr
1209 20985787U, // XMULX
1210 20984886U, // XMULXHI
1211 20984494U, // XNORCCri
1212 20984494U, // XNORCCrr
1213 20985255U, // XNORri
1214 20985255U, // XNORrr
1215 20984502U, // XORCCri
1216 20984502U, // XORCCrr
1217 20985262U, // XORri
1218 20985262U, // XORrr
1219 };
1220
1221 // Emit the opcode for the instruction.
1222 uint32_t Bits = 0;
1223 Bits |= OpInfo0[MI.getOpcode()] << 0;
1224 if (Bits == 0)
1225 return {nullptr, Bits};
1226 return {AsmStrs+(Bits & 4095)-1, Bits};
1227
1228}
1229/// printInstruction - This method is automatically generated by tablegen
1230/// from the instruction set description.
1231LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
1232void SparcInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
1233 O << "\t";
1234
1235 auto MnemonicInfo = getMnemonic(MI: *MI);
1236
1237 O << MnemonicInfo.first;
1238
1239 uint32_t Bits = MnemonicInfo.second;
1240 assert(Bits != 0 && "Cannot print this instruction.");
1241
1242 // Fragment 0 encoded into 4 bits for 13 unique commands.
1243 switch ((Bits >> 12) & 15) {
1244 default: llvm_unreachable("Invalid command number.");
1245 case 0:
1246 // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
1247 return;
1248 break;
1249 case 1:
1250 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CMASK16, CMASK32, CMASK8, FCMPD, FCM...
1251 printOperand(MI, opNum: 0, STI, OS&: O);
1252 break;
1253 case 2:
1254 // GETPCX
1255 printGetPCX(MI, OpNo: 0, STI, OS&: O);
1256 return;
1257 break;
1258 case 3:
1259 // SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, AD...
1260 printOperand(MI, opNum: 1, STI, OS&: O);
1261 break;
1262 case 4:
1263 // BA, CALL, CALLi, TAIL_CALL, TLS_CALL
1264 printCTILabel(MI, Address, OpNum: 0, STI, O);
1265 break;
1266 case 5:
1267 // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
1268 printCCOperand(MI, opNum: 1, STI, OS&: O);
1269 break;
1270 case 6:
1271 // BINDri, BINDrr, CALLri, CALLrii, CALLrr, CALLrri, FLUSHri, FLUSHrr, LD...
1272 printMemOperand(MI, opNum: 0, STI, OS&: O);
1273 break;
1274 case 7:
1275 // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
1276 printCCOperand(MI, opNum: 3, STI, OS&: O);
1277 break;
1278 case 8:
1279 // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
1280 printCCOperand(MI, opNum: 4, STI, OS&: O);
1281 O << ' ';
1282 printOperand(MI, opNum: 1, STI, OS&: O);
1283 O << ", ";
1284 printOperand(MI, opNum: 2, STI, OS&: O);
1285 O << ", ";
1286 printOperand(MI, opNum: 0, STI, OS&: O);
1287 return;
1288 break;
1289 case 9:
1290 // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
1291 printMemOperand(MI, opNum: 1, STI, OS&: O);
1292 break;
1293 case 10:
1294 // MEMBARi
1295 printMembarTag(MI, opNum: 0, STI, O);
1296 return;
1297 break;
1298 case 11:
1299 // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
1300 printOperand(MI, opNum: 2, STI, OS&: O);
1301 O << ", [";
1302 printMemOperand(MI, opNum: 0, STI, OS&: O);
1303 break;
1304 case 12:
1305 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1306 printCCOperand(MI, opNum: 2, STI, OS&: O);
1307 break;
1308 }
1309
1310
1311 // Fragment 1 encoded into 5 bits for 23 unique commands.
1312 switch ((Bits >> 16) & 31) {
1313 default: llvm_unreachable("Invalid command number.");
1314 case 0:
1315 // ADJCALLSTACKDOWN, SET, SETSW, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ...
1316 O << ", ";
1317 break;
1318 case 1:
1319 // ADJCALLSTACKUP, BA, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMA...
1320 return;
1321 break;
1322 case 2:
1323 // BCOND, BPFCC, BPR, CPBCOND, CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr...
1324 O << ' ';
1325 break;
1326 case 3:
1327 // BCONDA, BPFCCA, BPRA, CPBCONDA, FBCONDA
1328 O << ",a ";
1329 break;
1330 case 4:
1331 // BPFCCANT, BPRANT
1332 O << ",a,pn ";
1333 printOperand(MI, opNum: 2, STI, OS&: O);
1334 O << ", ";
1335 printCTILabel(MI, Address, OpNum: 0, STI, O);
1336 return;
1337 break;
1338 case 5:
1339 // BPFCCNT, BPRNT
1340 O << ",pn ";
1341 printOperand(MI, opNum: 2, STI, OS&: O);
1342 O << ", ";
1343 printCTILabel(MI, Address, OpNum: 0, STI, O);
1344 return;
1345 break;
1346 case 6:
1347 // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
1348 O << " %icc, ";
1349 break;
1350 case 7:
1351 // BPICCA
1352 O << ",a %icc, ";
1353 printCTILabel(MI, Address, OpNum: 0, STI, O);
1354 return;
1355 break;
1356 case 8:
1357 // BPICCANT
1358 O << ",a,pn %icc, ";
1359 printCTILabel(MI, Address, OpNum: 0, STI, O);
1360 return;
1361 break;
1362 case 9:
1363 // BPICCNT
1364 O << ",pn %icc, ";
1365 printCTILabel(MI, Address, OpNum: 0, STI, O);
1366 return;
1367 break;
1368 case 10:
1369 // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
1370 O << " %xcc, ";
1371 break;
1372 case 11:
1373 // BPXCCA
1374 O << ",a %xcc, ";
1375 printCTILabel(MI, Address, OpNum: 0, STI, O);
1376 return;
1377 break;
1378 case 12:
1379 // BPXCCANT
1380 O << ",a,pn %xcc, ";
1381 printCTILabel(MI, Address, OpNum: 0, STI, O);
1382 return;
1383 break;
1384 case 13:
1385 // BPXCCNT
1386 O << ",pn %xcc, ";
1387 printCTILabel(MI, Address, OpNum: 0, STI, O);
1388 return;
1389 break;
1390 case 14:
1391 // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
1392 O << "] %asi, ";
1393 break;
1394 case 15:
1395 // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
1396 O << "] ";
1397 break;
1398 case 16:
1399 // FBCONDA_V9
1400 O << ",a %fcc0, ";
1401 printCTILabel(MI, Address, OpNum: 0, STI, O);
1402 return;
1403 break;
1404 case 17:
1405 // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1406 O << " %fcc0, ";
1407 break;
1408 case 18:
1409 // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
1410 O << "], ";
1411 break;
1412 case 19:
1413 // LDCSRri, LDCSRrr
1414 O << "], %csr";
1415 return;
1416 break;
1417 case 20:
1418 // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
1419 O << "], %fsr";
1420 return;
1421 break;
1422 case 21:
1423 // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
1424 O << "] %asi";
1425 return;
1426 break;
1427 case 22:
1428 // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
1429 O << ']';
1430 return;
1431 break;
1432 }
1433
1434
1435 // Fragment 2 encoded into 3 bits for 8 unique commands.
1436 switch ((Bits >> 21) & 7) {
1437 default: llvm_unreachable("Invalid command number.");
1438 case 0:
1439 // ADJCALLSTACKDOWN, CALLi, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMP...
1440 printOperand(MI, opNum: 1, STI, OS&: O);
1441 break;
1442 case 1:
1443 // SET, SETSW, FABSD, FABSQ, FABSS, FDTOI, FDTOQ, FDTOS, FDTOX, FEXPAND, ...
1444 printOperand(MI, opNum: 0, STI, OS&: O);
1445 break;
1446 case 2:
1447 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1448 printOperand(MI, opNum: 2, STI, OS&: O);
1449 break;
1450 case 3:
1451 // BCOND, BCONDA, BPICC, BPXCC, CPBCOND, CPBCONDA, FBCOND, FBCONDA, FBCON...
1452 printCTILabel(MI, Address, OpNum: 0, STI, O);
1453 return;
1454 break;
1455 case 4:
1456 // CASArr, CASXArr
1457 printASITag(MI, opNum: 4, STI, O);
1458 O << ", ";
1459 printOperand(MI, opNum: 2, STI, OS&: O);
1460 O << ", ";
1461 printOperand(MI, opNum: 0, STI, OS&: O);
1462 return;
1463 break;
1464 case 5:
1465 // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
1466 printASITag(MI, opNum: 3, STI, O);
1467 break;
1468 case 6:
1469 // PREFETCHAi, PREFETCHi, PREFETCHr
1470 printPrefetchTag(MI, opNum: 2, STI, O);
1471 return;
1472 break;
1473 case 7:
1474 // PREFETCHAr
1475 printASITag(MI, opNum: 2, STI, O);
1476 O << ", ";
1477 printPrefetchTag(MI, opNum: 3, STI, O);
1478 return;
1479 break;
1480 }
1481
1482
1483 // Fragment 3 encoded into 3 bits for 6 unique commands.
1484 switch ((Bits >> 24) & 7) {
1485 default: llvm_unreachable("Invalid command number.");
1486 case 0:
1487 // ADJCALLSTACKDOWN, SET, SETSW, CALLi, CALLrii, CALLrri, FABSD, FABSQ, F...
1488 return;
1489 break;
1490 case 1:
1491 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1492 O << ", ";
1493 break;
1494 case 2:
1495 // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
1496 O << ", %psr";
1497 return;
1498 break;
1499 case 3:
1500 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1501 O << " + ";
1502 printOperand(MI, opNum: 1, STI, OS&: O);
1503 return;
1504 break;
1505 case 4:
1506 // WRTBRri, WRTBRrr
1507 O << ", %tbr";
1508 return;
1509 break;
1510 case 5:
1511 // WRWIMri, WRWIMrr
1512 O << ", %wim";
1513 return;
1514 break;
1515 }
1516
1517
1518 // Fragment 4 encoded into 2 bits for 4 unique commands.
1519 switch ((Bits >> 27) & 3) {
1520 default: llvm_unreachable("Invalid command number.");
1521 case 0:
1522 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1523 printOperand(MI, opNum: 0, STI, OS&: O);
1524 break;
1525 case 1:
1526 // BPFCC, BPFCCA, BPR, BPRA
1527 printCTILabel(MI, Address, OpNum: 0, STI, O);
1528 return;
1529 break;
1530 case 2:
1531 // CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr, FMADDD, FMADDS, FMSUBD, FM...
1532 printOperand(MI, opNum: 3, STI, OS&: O);
1533 break;
1534 case 3:
1535 // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1536 printOperand(MI, opNum: 2, STI, OS&: O);
1537 return;
1538 break;
1539 }
1540
1541
1542 // Fragment 5 encoded into 1 bits for 2 unique commands.
1543 if ((Bits >> 29) & 1) {
1544 // CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr, FMADDD, FMADDS, FMSUBD, FM...
1545 O << ", ";
1546 } else {
1547 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1548 return;
1549 }
1550
1551
1552 // Fragment 6 encoded into 2 bits for 3 unique commands.
1553 switch ((Bits >> 30) & 3) {
1554 default: llvm_unreachable("Invalid command number.");
1555 case 0:
1556 // CWBCONDri, CWBCONDrr, CXBCONDri, CXBCONDrr
1557 printCTILabel(MI, Address, OpNum: 0, STI, O);
1558 return;
1559 break;
1560 case 1:
1561 // FMADDD, FMADDS, FMSUBD, FMSUBS, FNMADDD, FNMADDS, FNMSUBD, FNMSUBS, FP...
1562 printOperand(MI, opNum: 0, STI, OS&: O);
1563 return;
1564 break;
1565 case 2:
1566 // TLS_ADDrr
1567 printOperand(MI, opNum: 3, STI, OS&: O);
1568 return;
1569 break;
1570 }
1571
1572}
1573
1574
1575/// getRegisterName - This method is automatically generated by tblgen
1576/// from the register set description. This returns the assembler name
1577/// for the specified register.
1578const char *SparcInstPrinter::
1579getRegisterName(MCRegister Reg, unsigned AltIdx) {
1580 unsigned RegNo = Reg.id();
1581 assert(RegNo && RegNo < 238 && "Invalid register number!");
1582
1583
1584#ifdef __GNUC__
1585#pragma GCC diagnostic push
1586#pragma GCC diagnostic ignored "-Woverlength-strings"
1587#endif
1588 static const char AsmStrsNoRegAltName[] = {
1589 /* 0 */ "c10\000"
1590 /* 4 */ "f10\000"
1591 /* 8 */ "asr10\000"
1592 /* 14 */ "c20\000"
1593 /* 18 */ "f20\000"
1594 /* 22 */ "asr20\000"
1595 /* 28 */ "c30\000"
1596 /* 32 */ "f30\000"
1597 /* 36 */ "asr30\000"
1598 /* 42 */ "f40\000"
1599 /* 46 */ "f50\000"
1600 /* 50 */ "f60\000"
1601 /* 54 */ "fcc0\000"
1602 /* 59 */ "f0\000"
1603 /* 62 */ "g0\000"
1604 /* 65 */ "i0\000"
1605 /* 68 */ "l0\000"
1606 /* 71 */ "o0\000"
1607 /* 74 */ "c11\000"
1608 /* 78 */ "f11\000"
1609 /* 82 */ "asr11\000"
1610 /* 88 */ "c21\000"
1611 /* 92 */ "f21\000"
1612 /* 96 */ "asr21\000"
1613 /* 102 */ "c31\000"
1614 /* 106 */ "f31\000"
1615 /* 110 */ "asr31\000"
1616 /* 116 */ "fcc1\000"
1617 /* 121 */ "f1\000"
1618 /* 124 */ "g1\000"
1619 /* 127 */ "i1\000"
1620 /* 130 */ "l1\000"
1621 /* 133 */ "o1\000"
1622 /* 136 */ "asr1\000"
1623 /* 141 */ "c12\000"
1624 /* 145 */ "f12\000"
1625 /* 149 */ "asr12\000"
1626 /* 155 */ "c22\000"
1627 /* 159 */ "f22\000"
1628 /* 163 */ "asr22\000"
1629 /* 169 */ "f32\000"
1630 /* 173 */ "f42\000"
1631 /* 177 */ "f52\000"
1632 /* 181 */ "f62\000"
1633 /* 185 */ "fcc2\000"
1634 /* 190 */ "f2\000"
1635 /* 193 */ "g2\000"
1636 /* 196 */ "i2\000"
1637 /* 199 */ "l2\000"
1638 /* 202 */ "o2\000"
1639 /* 205 */ "asr2\000"
1640 /* 210 */ "c13\000"
1641 /* 214 */ "f13\000"
1642 /* 218 */ "asr13\000"
1643 /* 224 */ "c23\000"
1644 /* 228 */ "f23\000"
1645 /* 232 */ "asr23\000"
1646 /* 238 */ "fcc3\000"
1647 /* 243 */ "f3\000"
1648 /* 246 */ "g3\000"
1649 /* 249 */ "i3\000"
1650 /* 252 */ "l3\000"
1651 /* 255 */ "o3\000"
1652 /* 258 */ "asr3\000"
1653 /* 263 */ "c14\000"
1654 /* 267 */ "f14\000"
1655 /* 271 */ "asr14\000"
1656 /* 277 */ "c24\000"
1657 /* 281 */ "f24\000"
1658 /* 285 */ "asr24\000"
1659 /* 291 */ "f34\000"
1660 /* 295 */ "f44\000"
1661 /* 299 */ "f54\000"
1662 /* 303 */ "c4\000"
1663 /* 306 */ "f4\000"
1664 /* 309 */ "g4\000"
1665 /* 312 */ "i4\000"
1666 /* 315 */ "l4\000"
1667 /* 318 */ "o4\000"
1668 /* 321 */ "asr4\000"
1669 /* 326 */ "c15\000"
1670 /* 330 */ "f15\000"
1671 /* 334 */ "asr15\000"
1672 /* 340 */ "c25\000"
1673 /* 344 */ "f25\000"
1674 /* 348 */ "asr25\000"
1675 /* 354 */ "c5\000"
1676 /* 357 */ "f5\000"
1677 /* 360 */ "g5\000"
1678 /* 363 */ "i5\000"
1679 /* 366 */ "l5\000"
1680 /* 369 */ "o5\000"
1681 /* 372 */ "asr5\000"
1682 /* 377 */ "c16\000"
1683 /* 381 */ "f16\000"
1684 /* 385 */ "asr16\000"
1685 /* 391 */ "c26\000"
1686 /* 395 */ "f26\000"
1687 /* 399 */ "asr26\000"
1688 /* 405 */ "f36\000"
1689 /* 409 */ "f46\000"
1690 /* 413 */ "f56\000"
1691 /* 417 */ "c6\000"
1692 /* 420 */ "f6\000"
1693 /* 423 */ "g6\000"
1694 /* 426 */ "i6\000"
1695 /* 429 */ "l6\000"
1696 /* 432 */ "o6\000"
1697 /* 435 */ "asr6\000"
1698 /* 440 */ "c17\000"
1699 /* 444 */ "f17\000"
1700 /* 448 */ "asr17\000"
1701 /* 454 */ "c27\000"
1702 /* 458 */ "f27\000"
1703 /* 462 */ "asr27\000"
1704 /* 468 */ "c7\000"
1705 /* 471 */ "f7\000"
1706 /* 474 */ "g7\000"
1707 /* 477 */ "i7\000"
1708 /* 480 */ "l7\000"
1709 /* 483 */ "o7\000"
1710 /* 486 */ "asr7\000"
1711 /* 491 */ "c18\000"
1712 /* 495 */ "f18\000"
1713 /* 499 */ "asr18\000"
1714 /* 505 */ "c28\000"
1715 /* 509 */ "f28\000"
1716 /* 513 */ "asr28\000"
1717 /* 519 */ "f38\000"
1718 /* 523 */ "f48\000"
1719 /* 527 */ "f58\000"
1720 /* 531 */ "c8\000"
1721 /* 534 */ "f8\000"
1722 /* 537 */ "asr8\000"
1723 /* 542 */ "c19\000"
1724 /* 546 */ "f19\000"
1725 /* 550 */ "asr19\000"
1726 /* 556 */ "c29\000"
1727 /* 560 */ "f29\000"
1728 /* 564 */ "asr29\000"
1729 /* 570 */ "c9\000"
1730 /* 573 */ "f9\000"
1731 /* 576 */ "asr9\000"
1732 /* 581 */ "tba\000"
1733 /* 585 */ "icc\000"
1734 /* 589 */ "tnpc\000"
1735 /* 594 */ "tpc\000"
1736 /* 598 */ "canrestore\000"
1737 /* 609 */ "pstate\000"
1738 /* 616 */ "tstate\000"
1739 /* 623 */ "wstate\000"
1740 /* 630 */ "cansave\000"
1741 /* 638 */ "tick\000"
1742 /* 643 */ "gl\000"
1743 /* 646 */ "pil\000"
1744 /* 650 */ "tl\000"
1745 /* 653 */ "wim\000"
1746 /* 657 */ "cleanwin\000"
1747 /* 666 */ "otherwin\000"
1748 /* 675 */ "fp\000"
1749 /* 678 */ "sp\000"
1750 /* 681 */ "cwp\000"
1751 /* 685 */ "cq\000"
1752 /* 688 */ "fq\000"
1753 /* 691 */ "tbr\000"
1754 /* 695 */ "ver\000"
1755 /* 699 */ "csr\000"
1756 /* 703 */ "fsr\000"
1757 /* 707 */ "psr\000"
1758 /* 711 */ "tt\000"
1759 /* 714 */ "y\000"
1760};
1761#ifdef __GNUC__
1762#pragma GCC diagnostic pop
1763#endif
1764
1765 static const uint16_t RegAsmOffsetNoRegAltName[] = {
1766 598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609,
1767 581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205,
1768 258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385,
1769 448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36,
1770 110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141,
1771 210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391,
1772 454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381,
1773 495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295,
1774 409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306,
1775 357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495,
1776 546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54,
1777 116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196,
1778 249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71,
1779 133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281,
1780 509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531,
1781 0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309,
1782 423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432,
1783 };
1784
1785
1786#ifdef __GNUC__
1787#pragma GCC diagnostic push
1788#pragma GCC diagnostic ignored "-Woverlength-strings"
1789#endif
1790 static const char AsmStrsRegNamesStateReg[] = {
1791 /* 0 */ "pc\000"
1792 /* 3 */ "asi\000"
1793 /* 7 */ "tick\000"
1794 /* 12 */ "ccr\000"
1795 /* 16 */ "fprs\000"
1796};
1797#ifdef __GNUC__
1798#pragma GCC diagnostic pop
1799#endif
1800
1801 static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
1802 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1803 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12,
1804 3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1805 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1806 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1807 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1808 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1809 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1810 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1811 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1812 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1813 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1814 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1815 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1816 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1817 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1818 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1819 };
1820
1821 switch(AltIdx) {
1822 default: llvm_unreachable("Invalid register alt name index!");
1823 case SP::NoRegAltName:
1824 assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1825 "Invalid alt name index for register!");
1826 return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1827 case SP::RegNamesStateReg:
1828 if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
1829 return getRegisterName(Reg: RegNo, AltIdx: SP::NoRegAltName);
1830 return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
1831 }
1832}
1833
1834#ifdef PRINT_ALIAS_INSTR
1835#undef PRINT_ALIAS_INSTR
1836
1837bool SparcInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
1838 static const PatternsForOpcode OpToPatterns[] = {
1839 {.Opcode: SP::BCOND, .PatternStart: 0, .NumPatterns: 16 },
1840 {.Opcode: SP::BCONDA, .PatternStart: 16, .NumPatterns: 16 },
1841 {.Opcode: SP::BPFCCANT, .PatternStart: 32, .NumPatterns: 16 },
1842 {.Opcode: SP::BPFCCNT, .PatternStart: 48, .NumPatterns: 16 },
1843 {.Opcode: SP::BPICCANT, .PatternStart: 64, .NumPatterns: 16 },
1844 {.Opcode: SP::BPICCNT, .PatternStart: 80, .NumPatterns: 16 },
1845 {.Opcode: SP::BPRANT, .PatternStart: 96, .NumPatterns: 4 },
1846 {.Opcode: SP::BPRNT, .PatternStart: 100, .NumPatterns: 4 },
1847 {.Opcode: SP::BPXCCANT, .PatternStart: 104, .NumPatterns: 16 },
1848 {.Opcode: SP::BPXCCNT, .PatternStart: 120, .NumPatterns: 16 },
1849 {.Opcode: SP::CASArr, .PatternStart: 136, .NumPatterns: 2 },
1850 {.Opcode: SP::CASXArr, .PatternStart: 138, .NumPatterns: 2 },
1851 {.Opcode: SP::CWBCONDri, .PatternStart: 140, .NumPatterns: 14 },
1852 {.Opcode: SP::CWBCONDrr, .PatternStart: 154, .NumPatterns: 14 },
1853 {.Opcode: SP::CXBCONDri, .PatternStart: 168, .NumPatterns: 14 },
1854 {.Opcode: SP::CXBCONDrr, .PatternStart: 182, .NumPatterns: 14 },
1855 {.Opcode: SP::FMOVD_ICC, .PatternStart: 196, .NumPatterns: 16 },
1856 {.Opcode: SP::FMOVD_XCC, .PatternStart: 212, .NumPatterns: 16 },
1857 {.Opcode: SP::FMOVQ_ICC, .PatternStart: 228, .NumPatterns: 16 },
1858 {.Opcode: SP::FMOVQ_XCC, .PatternStart: 244, .NumPatterns: 16 },
1859 {.Opcode: SP::FMOVRD, .PatternStart: 260, .NumPatterns: 4 },
1860 {.Opcode: SP::FMOVRQ, .PatternStart: 264, .NumPatterns: 4 },
1861 {.Opcode: SP::FMOVRS, .PatternStart: 268, .NumPatterns: 4 },
1862 {.Opcode: SP::FMOVS_ICC, .PatternStart: 272, .NumPatterns: 16 },
1863 {.Opcode: SP::FMOVS_XCC, .PatternStart: 288, .NumPatterns: 16 },
1864 {.Opcode: SP::MOVICCri, .PatternStart: 304, .NumPatterns: 16 },
1865 {.Opcode: SP::MOVICCrr, .PatternStart: 320, .NumPatterns: 16 },
1866 {.Opcode: SP::MOVRri, .PatternStart: 336, .NumPatterns: 4 },
1867 {.Opcode: SP::MOVRrr, .PatternStart: 340, .NumPatterns: 4 },
1868 {.Opcode: SP::MOVXCCri, .PatternStart: 344, .NumPatterns: 16 },
1869 {.Opcode: SP::MOVXCCrr, .PatternStart: 360, .NumPatterns: 16 },
1870 {.Opcode: SP::ORCCrr, .PatternStart: 376, .NumPatterns: 1 },
1871 {.Opcode: SP::ORri, .PatternStart: 377, .NumPatterns: 1 },
1872 {.Opcode: SP::ORrr, .PatternStart: 378, .NumPatterns: 1 },
1873 {.Opcode: SP::RESTORErr, .PatternStart: 379, .NumPatterns: 1 },
1874 {.Opcode: SP::RET, .PatternStart: 380, .NumPatterns: 1 },
1875 {.Opcode: SP::RETL, .PatternStart: 381, .NumPatterns: 1 },
1876 {.Opcode: SP::SAVErr, .PatternStart: 382, .NumPatterns: 1 },
1877 {.Opcode: SP::SUBCCri, .PatternStart: 383, .NumPatterns: 1 },
1878 {.Opcode: SP::SUBCCrr, .PatternStart: 384, .NumPatterns: 1 },
1879 {.Opcode: SP::TICCri, .PatternStart: 385, .NumPatterns: 32 },
1880 {.Opcode: SP::TICCrr, .PatternStart: 417, .NumPatterns: 32 },
1881 {.Opcode: SP::TRAPri, .PatternStart: 449, .NumPatterns: 32 },
1882 {.Opcode: SP::TRAPrr, .PatternStart: 481, .NumPatterns: 32 },
1883 {.Opcode: SP::TXCCri, .PatternStart: 513, .NumPatterns: 32 },
1884 {.Opcode: SP::TXCCrr, .PatternStart: 545, .NumPatterns: 32 },
1885 {.Opcode: SP::V9FCMPD, .PatternStart: 577, .NumPatterns: 1 },
1886 {.Opcode: SP::V9FCMPED, .PatternStart: 578, .NumPatterns: 1 },
1887 {.Opcode: SP::V9FCMPEQ, .PatternStart: 579, .NumPatterns: 1 },
1888 {.Opcode: SP::V9FCMPES, .PatternStart: 580, .NumPatterns: 1 },
1889 {.Opcode: SP::V9FCMPQ, .PatternStart: 581, .NumPatterns: 1 },
1890 {.Opcode: SP::V9FCMPS, .PatternStart: 582, .NumPatterns: 1 },
1891 {.Opcode: SP::V9FMOVD_FCC, .PatternStart: 583, .NumPatterns: 16 },
1892 {.Opcode: SP::V9FMOVQ_FCC, .PatternStart: 599, .NumPatterns: 16 },
1893 {.Opcode: SP::V9FMOVS_FCC, .PatternStart: 615, .NumPatterns: 16 },
1894 {.Opcode: SP::V9MOVFCCri, .PatternStart: 631, .NumPatterns: 16 },
1895 {.Opcode: SP::V9MOVFCCrr, .PatternStart: 647, .NumPatterns: 16 },
1896 {.Opcode: SP::WRASRri, .PatternStart: 663, .NumPatterns: 1 },
1897 {.Opcode: SP::WRASRrr, .PatternStart: 664, .NumPatterns: 1 },
1898 };
1899
1900 static const AliasPattern Patterns[] = {
1901 // SP::BCOND - 0
1902 {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 2, .NumConds: 2 },
1903 {.AsmStrOffset: 8, .AliasCondStart: 2, .NumOperands: 2, .NumConds: 2 },
1904 {.AsmStrOffset: 16, .AliasCondStart: 4, .NumOperands: 2, .NumConds: 2 },
1905 {.AsmStrOffset: 25, .AliasCondStart: 6, .NumOperands: 2, .NumConds: 2 },
1906 {.AsmStrOffset: 33, .AliasCondStart: 8, .NumOperands: 2, .NumConds: 2 },
1907 {.AsmStrOffset: 41, .AliasCondStart: 10, .NumOperands: 2, .NumConds: 2 },
1908 {.AsmStrOffset: 50, .AliasCondStart: 12, .NumOperands: 2, .NumConds: 2 },
1909 {.AsmStrOffset: 59, .AliasCondStart: 14, .NumOperands: 2, .NumConds: 2 },
1910 {.AsmStrOffset: 67, .AliasCondStart: 16, .NumOperands: 2, .NumConds: 2 },
1911 {.AsmStrOffset: 76, .AliasCondStart: 18, .NumOperands: 2, .NumConds: 2 },
1912 {.AsmStrOffset: 86, .AliasCondStart: 20, .NumOperands: 2, .NumConds: 2 },
1913 {.AsmStrOffset: 95, .AliasCondStart: 22, .NumOperands: 2, .NumConds: 2 },
1914 {.AsmStrOffset: 104, .AliasCondStart: 24, .NumOperands: 2, .NumConds: 2 },
1915 {.AsmStrOffset: 114, .AliasCondStart: 26, .NumOperands: 2, .NumConds: 2 },
1916 {.AsmStrOffset: 124, .AliasCondStart: 28, .NumOperands: 2, .NumConds: 2 },
1917 {.AsmStrOffset: 133, .AliasCondStart: 30, .NumOperands: 2, .NumConds: 2 },
1918 // SP::BCONDA - 16
1919 {.AsmStrOffset: 142, .AliasCondStart: 32, .NumOperands: 2, .NumConds: 2 },
1920 {.AsmStrOffset: 152, .AliasCondStart: 34, .NumOperands: 2, .NumConds: 2 },
1921 {.AsmStrOffset: 162, .AliasCondStart: 36, .NumOperands: 2, .NumConds: 2 },
1922 {.AsmStrOffset: 173, .AliasCondStart: 38, .NumOperands: 2, .NumConds: 2 },
1923 {.AsmStrOffset: 183, .AliasCondStart: 40, .NumOperands: 2, .NumConds: 2 },
1924 {.AsmStrOffset: 193, .AliasCondStart: 42, .NumOperands: 2, .NumConds: 2 },
1925 {.AsmStrOffset: 204, .AliasCondStart: 44, .NumOperands: 2, .NumConds: 2 },
1926 {.AsmStrOffset: 215, .AliasCondStart: 46, .NumOperands: 2, .NumConds: 2 },
1927 {.AsmStrOffset: 225, .AliasCondStart: 48, .NumOperands: 2, .NumConds: 2 },
1928 {.AsmStrOffset: 236, .AliasCondStart: 50, .NumOperands: 2, .NumConds: 2 },
1929 {.AsmStrOffset: 248, .AliasCondStart: 52, .NumOperands: 2, .NumConds: 2 },
1930 {.AsmStrOffset: 259, .AliasCondStart: 54, .NumOperands: 2, .NumConds: 2 },
1931 {.AsmStrOffset: 270, .AliasCondStart: 56, .NumOperands: 2, .NumConds: 2 },
1932 {.AsmStrOffset: 282, .AliasCondStart: 58, .NumOperands: 2, .NumConds: 2 },
1933 {.AsmStrOffset: 294, .AliasCondStart: 60, .NumOperands: 2, .NumConds: 2 },
1934 {.AsmStrOffset: 305, .AliasCondStart: 62, .NumOperands: 2, .NumConds: 2 },
1935 // SP::BPFCCANT - 32
1936 {.AsmStrOffset: 316, .AliasCondStart: 64, .NumOperands: 3, .NumConds: 4 },
1937 {.AsmStrOffset: 334, .AliasCondStart: 68, .NumOperands: 3, .NumConds: 4 },
1938 {.AsmStrOffset: 352, .AliasCondStart: 72, .NumOperands: 3, .NumConds: 4 },
1939 {.AsmStrOffset: 370, .AliasCondStart: 76, .NumOperands: 3, .NumConds: 4 },
1940 {.AsmStrOffset: 388, .AliasCondStart: 80, .NumOperands: 3, .NumConds: 4 },
1941 {.AsmStrOffset: 407, .AliasCondStart: 84, .NumOperands: 3, .NumConds: 4 },
1942 {.AsmStrOffset: 425, .AliasCondStart: 88, .NumOperands: 3, .NumConds: 4 },
1943 {.AsmStrOffset: 444, .AliasCondStart: 92, .NumOperands: 3, .NumConds: 4 },
1944 {.AsmStrOffset: 463, .AliasCondStart: 96, .NumOperands: 3, .NumConds: 4 },
1945 {.AsmStrOffset: 482, .AliasCondStart: 100, .NumOperands: 3, .NumConds: 4 },
1946 {.AsmStrOffset: 500, .AliasCondStart: 104, .NumOperands: 3, .NumConds: 4 },
1947 {.AsmStrOffset: 519, .AliasCondStart: 108, .NumOperands: 3, .NumConds: 4 },
1948 {.AsmStrOffset: 538, .AliasCondStart: 112, .NumOperands: 3, .NumConds: 4 },
1949 {.AsmStrOffset: 558, .AliasCondStart: 116, .NumOperands: 3, .NumConds: 4 },
1950 {.AsmStrOffset: 577, .AliasCondStart: 120, .NumOperands: 3, .NumConds: 4 },
1951 {.AsmStrOffset: 597, .AliasCondStart: 124, .NumOperands: 3, .NumConds: 4 },
1952 // SP::BPFCCNT - 48
1953 {.AsmStrOffset: 615, .AliasCondStart: 128, .NumOperands: 3, .NumConds: 4 },
1954 {.AsmStrOffset: 631, .AliasCondStart: 132, .NumOperands: 3, .NumConds: 4 },
1955 {.AsmStrOffset: 647, .AliasCondStart: 136, .NumOperands: 3, .NumConds: 4 },
1956 {.AsmStrOffset: 663, .AliasCondStart: 140, .NumOperands: 3, .NumConds: 4 },
1957 {.AsmStrOffset: 679, .AliasCondStart: 144, .NumOperands: 3, .NumConds: 4 },
1958 {.AsmStrOffset: 696, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 4 },
1959 {.AsmStrOffset: 712, .AliasCondStart: 152, .NumOperands: 3, .NumConds: 4 },
1960 {.AsmStrOffset: 729, .AliasCondStart: 156, .NumOperands: 3, .NumConds: 4 },
1961 {.AsmStrOffset: 746, .AliasCondStart: 160, .NumOperands: 3, .NumConds: 4 },
1962 {.AsmStrOffset: 763, .AliasCondStart: 164, .NumOperands: 3, .NumConds: 4 },
1963 {.AsmStrOffset: 779, .AliasCondStart: 168, .NumOperands: 3, .NumConds: 4 },
1964 {.AsmStrOffset: 796, .AliasCondStart: 172, .NumOperands: 3, .NumConds: 4 },
1965 {.AsmStrOffset: 813, .AliasCondStart: 176, .NumOperands: 3, .NumConds: 4 },
1966 {.AsmStrOffset: 831, .AliasCondStart: 180, .NumOperands: 3, .NumConds: 4 },
1967 {.AsmStrOffset: 848, .AliasCondStart: 184, .NumOperands: 3, .NumConds: 4 },
1968 {.AsmStrOffset: 866, .AliasCondStart: 188, .NumOperands: 3, .NumConds: 4 },
1969 // SP::BPICCANT - 64
1970 {.AsmStrOffset: 882, .AliasCondStart: 192, .NumOperands: 2, .NumConds: 3 },
1971 {.AsmStrOffset: 901, .AliasCondStart: 195, .NumOperands: 2, .NumConds: 3 },
1972 {.AsmStrOffset: 920, .AliasCondStart: 198, .NumOperands: 2, .NumConds: 3 },
1973 {.AsmStrOffset: 940, .AliasCondStart: 201, .NumOperands: 2, .NumConds: 3 },
1974 {.AsmStrOffset: 959, .AliasCondStart: 204, .NumOperands: 2, .NumConds: 3 },
1975 {.AsmStrOffset: 978, .AliasCondStart: 207, .NumOperands: 2, .NumConds: 3 },
1976 {.AsmStrOffset: 998, .AliasCondStart: 210, .NumOperands: 2, .NumConds: 3 },
1977 {.AsmStrOffset: 1018, .AliasCondStart: 213, .NumOperands: 2, .NumConds: 3 },
1978 {.AsmStrOffset: 1037, .AliasCondStart: 216, .NumOperands: 2, .NumConds: 3 },
1979 {.AsmStrOffset: 1057, .AliasCondStart: 219, .NumOperands: 2, .NumConds: 3 },
1980 {.AsmStrOffset: 1078, .AliasCondStart: 222, .NumOperands: 2, .NumConds: 3 },
1981 {.AsmStrOffset: 1098, .AliasCondStart: 225, .NumOperands: 2, .NumConds: 3 },
1982 {.AsmStrOffset: 1118, .AliasCondStart: 228, .NumOperands: 2, .NumConds: 3 },
1983 {.AsmStrOffset: 1139, .AliasCondStart: 231, .NumOperands: 2, .NumConds: 3 },
1984 {.AsmStrOffset: 1160, .AliasCondStart: 234, .NumOperands: 2, .NumConds: 3 },
1985 {.AsmStrOffset: 1180, .AliasCondStart: 237, .NumOperands: 2, .NumConds: 3 },
1986 // SP::BPICCNT - 80
1987 {.AsmStrOffset: 1200, .AliasCondStart: 240, .NumOperands: 2, .NumConds: 3 },
1988 {.AsmStrOffset: 1217, .AliasCondStart: 243, .NumOperands: 2, .NumConds: 3 },
1989 {.AsmStrOffset: 1234, .AliasCondStart: 246, .NumOperands: 2, .NumConds: 3 },
1990 {.AsmStrOffset: 1252, .AliasCondStart: 249, .NumOperands: 2, .NumConds: 3 },
1991 {.AsmStrOffset: 1269, .AliasCondStart: 252, .NumOperands: 2, .NumConds: 3 },
1992 {.AsmStrOffset: 1286, .AliasCondStart: 255, .NumOperands: 2, .NumConds: 3 },
1993 {.AsmStrOffset: 1304, .AliasCondStart: 258, .NumOperands: 2, .NumConds: 3 },
1994 {.AsmStrOffset: 1322, .AliasCondStart: 261, .NumOperands: 2, .NumConds: 3 },
1995 {.AsmStrOffset: 1339, .AliasCondStart: 264, .NumOperands: 2, .NumConds: 3 },
1996 {.AsmStrOffset: 1357, .AliasCondStart: 267, .NumOperands: 2, .NumConds: 3 },
1997 {.AsmStrOffset: 1376, .AliasCondStart: 270, .NumOperands: 2, .NumConds: 3 },
1998 {.AsmStrOffset: 1394, .AliasCondStart: 273, .NumOperands: 2, .NumConds: 3 },
1999 {.AsmStrOffset: 1412, .AliasCondStart: 276, .NumOperands: 2, .NumConds: 3 },
2000 {.AsmStrOffset: 1431, .AliasCondStart: 279, .NumOperands: 2, .NumConds: 3 },
2001 {.AsmStrOffset: 1450, .AliasCondStart: 282, .NumOperands: 2, .NumConds: 3 },
2002 {.AsmStrOffset: 1468, .AliasCondStart: 285, .NumOperands: 2, .NumConds: 3 },
2003 // SP::BPRANT - 96
2004 {.AsmStrOffset: 1486, .AliasCondStart: 288, .NumOperands: 3, .NumConds: 4 },
2005 {.AsmStrOffset: 1506, .AliasCondStart: 292, .NumOperands: 3, .NumConds: 4 },
2006 {.AsmStrOffset: 1525, .AliasCondStart: 296, .NumOperands: 3, .NumConds: 4 },
2007 {.AsmStrOffset: 1544, .AliasCondStart: 300, .NumOperands: 3, .NumConds: 4 },
2008 // SP::BPRNT - 100
2009 {.AsmStrOffset: 1564, .AliasCondStart: 304, .NumOperands: 3, .NumConds: 4 },
2010 {.AsmStrOffset: 1582, .AliasCondStart: 308, .NumOperands: 3, .NumConds: 4 },
2011 {.AsmStrOffset: 1599, .AliasCondStart: 312, .NumOperands: 3, .NumConds: 4 },
2012 {.AsmStrOffset: 1616, .AliasCondStart: 316, .NumOperands: 3, .NumConds: 4 },
2013 // SP::BPXCCANT - 104
2014 {.AsmStrOffset: 1634, .AliasCondStart: 320, .NumOperands: 2, .NumConds: 3 },
2015 {.AsmStrOffset: 1653, .AliasCondStart: 323, .NumOperands: 2, .NumConds: 3 },
2016 {.AsmStrOffset: 1672, .AliasCondStart: 326, .NumOperands: 2, .NumConds: 3 },
2017 {.AsmStrOffset: 1692, .AliasCondStart: 329, .NumOperands: 2, .NumConds: 3 },
2018 {.AsmStrOffset: 1711, .AliasCondStart: 332, .NumOperands: 2, .NumConds: 3 },
2019 {.AsmStrOffset: 1730, .AliasCondStart: 335, .NumOperands: 2, .NumConds: 3 },
2020 {.AsmStrOffset: 1750, .AliasCondStart: 338, .NumOperands: 2, .NumConds: 3 },
2021 {.AsmStrOffset: 1770, .AliasCondStart: 341, .NumOperands: 2, .NumConds: 3 },
2022 {.AsmStrOffset: 1789, .AliasCondStart: 344, .NumOperands: 2, .NumConds: 3 },
2023 {.AsmStrOffset: 1809, .AliasCondStart: 347, .NumOperands: 2, .NumConds: 3 },
2024 {.AsmStrOffset: 1830, .AliasCondStart: 350, .NumOperands: 2, .NumConds: 3 },
2025 {.AsmStrOffset: 1850, .AliasCondStart: 353, .NumOperands: 2, .NumConds: 3 },
2026 {.AsmStrOffset: 1870, .AliasCondStart: 356, .NumOperands: 2, .NumConds: 3 },
2027 {.AsmStrOffset: 1891, .AliasCondStart: 359, .NumOperands: 2, .NumConds: 3 },
2028 {.AsmStrOffset: 1912, .AliasCondStart: 362, .NumOperands: 2, .NumConds: 3 },
2029 {.AsmStrOffset: 1932, .AliasCondStart: 365, .NumOperands: 2, .NumConds: 3 },
2030 // SP::BPXCCNT - 120
2031 {.AsmStrOffset: 1952, .AliasCondStart: 368, .NumOperands: 2, .NumConds: 3 },
2032 {.AsmStrOffset: 1969, .AliasCondStart: 371, .NumOperands: 2, .NumConds: 3 },
2033 {.AsmStrOffset: 1986, .AliasCondStart: 374, .NumOperands: 2, .NumConds: 3 },
2034 {.AsmStrOffset: 2004, .AliasCondStart: 377, .NumOperands: 2, .NumConds: 3 },
2035 {.AsmStrOffset: 2021, .AliasCondStart: 380, .NumOperands: 2, .NumConds: 3 },
2036 {.AsmStrOffset: 2038, .AliasCondStart: 383, .NumOperands: 2, .NumConds: 3 },
2037 {.AsmStrOffset: 2056, .AliasCondStart: 386, .NumOperands: 2, .NumConds: 3 },
2038 {.AsmStrOffset: 2074, .AliasCondStart: 389, .NumOperands: 2, .NumConds: 3 },
2039 {.AsmStrOffset: 2091, .AliasCondStart: 392, .NumOperands: 2, .NumConds: 3 },
2040 {.AsmStrOffset: 2109, .AliasCondStart: 395, .NumOperands: 2, .NumConds: 3 },
2041 {.AsmStrOffset: 2128, .AliasCondStart: 398, .NumOperands: 2, .NumConds: 3 },
2042 {.AsmStrOffset: 2146, .AliasCondStart: 401, .NumOperands: 2, .NumConds: 3 },
2043 {.AsmStrOffset: 2164, .AliasCondStart: 404, .NumOperands: 2, .NumConds: 3 },
2044 {.AsmStrOffset: 2183, .AliasCondStart: 407, .NumOperands: 2, .NumConds: 3 },
2045 {.AsmStrOffset: 2202, .AliasCondStart: 410, .NumOperands: 2, .NumConds: 3 },
2046 {.AsmStrOffset: 2220, .AliasCondStart: 413, .NumOperands: 2, .NumConds: 3 },
2047 // SP::CASArr - 136
2048 {.AsmStrOffset: 2238, .AliasCondStart: 416, .NumOperands: 5, .NumConds: 6 },
2049 {.AsmStrOffset: 2255, .AliasCondStart: 422, .NumOperands: 5, .NumConds: 6 },
2050 // SP::CASXArr - 138
2051 {.AsmStrOffset: 2273, .AliasCondStart: 428, .NumOperands: 5, .NumConds: 6 },
2052 {.AsmStrOffset: 2291, .AliasCondStart: 434, .NumOperands: 5, .NumConds: 6 },
2053 // SP::CWBCONDri - 140
2054 {.AsmStrOffset: 2310, .AliasCondStart: 440, .NumOperands: 4, .NumConds: 4 },
2055 {.AsmStrOffset: 2329, .AliasCondStart: 444, .NumOperands: 4, .NumConds: 4 },
2056 {.AsmStrOffset: 2347, .AliasCondStart: 448, .NumOperands: 4, .NumConds: 4 },
2057 {.AsmStrOffset: 2365, .AliasCondStart: 452, .NumOperands: 4, .NumConds: 4 },
2058 {.AsmStrOffset: 2384, .AliasCondStart: 456, .NumOperands: 4, .NumConds: 4 },
2059 {.AsmStrOffset: 2403, .AliasCondStart: 460, .NumOperands: 4, .NumConds: 4 },
2060 {.AsmStrOffset: 2421, .AliasCondStart: 464, .NumOperands: 4, .NumConds: 4 },
2061 {.AsmStrOffset: 2440, .AliasCondStart: 468, .NumOperands: 4, .NumConds: 4 },
2062 {.AsmStrOffset: 2460, .AliasCondStart: 472, .NumOperands: 4, .NumConds: 4 },
2063 {.AsmStrOffset: 2479, .AliasCondStart: 476, .NumOperands: 4, .NumConds: 4 },
2064 {.AsmStrOffset: 2498, .AliasCondStart: 480, .NumOperands: 4, .NumConds: 4 },
2065 {.AsmStrOffset: 2518, .AliasCondStart: 484, .NumOperands: 4, .NumConds: 4 },
2066 {.AsmStrOffset: 2538, .AliasCondStart: 488, .NumOperands: 4, .NumConds: 4 },
2067 {.AsmStrOffset: 2557, .AliasCondStart: 492, .NumOperands: 4, .NumConds: 4 },
2068 // SP::CWBCONDrr - 154
2069 {.AsmStrOffset: 2310, .AliasCondStart: 496, .NumOperands: 4, .NumConds: 5 },
2070 {.AsmStrOffset: 2329, .AliasCondStart: 501, .NumOperands: 4, .NumConds: 5 },
2071 {.AsmStrOffset: 2347, .AliasCondStart: 506, .NumOperands: 4, .NumConds: 5 },
2072 {.AsmStrOffset: 2365, .AliasCondStart: 511, .NumOperands: 4, .NumConds: 5 },
2073 {.AsmStrOffset: 2384, .AliasCondStart: 516, .NumOperands: 4, .NumConds: 5 },
2074 {.AsmStrOffset: 2403, .AliasCondStart: 521, .NumOperands: 4, .NumConds: 5 },
2075 {.AsmStrOffset: 2421, .AliasCondStart: 526, .NumOperands: 4, .NumConds: 5 },
2076 {.AsmStrOffset: 2440, .AliasCondStart: 531, .NumOperands: 4, .NumConds: 5 },
2077 {.AsmStrOffset: 2460, .AliasCondStart: 536, .NumOperands: 4, .NumConds: 5 },
2078 {.AsmStrOffset: 2479, .AliasCondStart: 541, .NumOperands: 4, .NumConds: 5 },
2079 {.AsmStrOffset: 2498, .AliasCondStart: 546, .NumOperands: 4, .NumConds: 5 },
2080 {.AsmStrOffset: 2518, .AliasCondStart: 551, .NumOperands: 4, .NumConds: 5 },
2081 {.AsmStrOffset: 2538, .AliasCondStart: 556, .NumOperands: 4, .NumConds: 5 },
2082 {.AsmStrOffset: 2557, .AliasCondStart: 561, .NumOperands: 4, .NumConds: 5 },
2083 // SP::CXBCONDri - 168
2084 {.AsmStrOffset: 2576, .AliasCondStart: 566, .NumOperands: 4, .NumConds: 4 },
2085 {.AsmStrOffset: 2595, .AliasCondStart: 570, .NumOperands: 4, .NumConds: 4 },
2086 {.AsmStrOffset: 2613, .AliasCondStart: 574, .NumOperands: 4, .NumConds: 4 },
2087 {.AsmStrOffset: 2631, .AliasCondStart: 578, .NumOperands: 4, .NumConds: 4 },
2088 {.AsmStrOffset: 2650, .AliasCondStart: 582, .NumOperands: 4, .NumConds: 4 },
2089 {.AsmStrOffset: 2669, .AliasCondStart: 586, .NumOperands: 4, .NumConds: 4 },
2090 {.AsmStrOffset: 2687, .AliasCondStart: 590, .NumOperands: 4, .NumConds: 4 },
2091 {.AsmStrOffset: 2706, .AliasCondStart: 594, .NumOperands: 4, .NumConds: 4 },
2092 {.AsmStrOffset: 2726, .AliasCondStart: 598, .NumOperands: 4, .NumConds: 4 },
2093 {.AsmStrOffset: 2745, .AliasCondStart: 602, .NumOperands: 4, .NumConds: 4 },
2094 {.AsmStrOffset: 2764, .AliasCondStart: 606, .NumOperands: 4, .NumConds: 4 },
2095 {.AsmStrOffset: 2784, .AliasCondStart: 610, .NumOperands: 4, .NumConds: 4 },
2096 {.AsmStrOffset: 2804, .AliasCondStart: 614, .NumOperands: 4, .NumConds: 4 },
2097 {.AsmStrOffset: 2823, .AliasCondStart: 618, .NumOperands: 4, .NumConds: 4 },
2098 // SP::CXBCONDrr - 182
2099 {.AsmStrOffset: 2576, .AliasCondStart: 622, .NumOperands: 4, .NumConds: 5 },
2100 {.AsmStrOffset: 2595, .AliasCondStart: 627, .NumOperands: 4, .NumConds: 5 },
2101 {.AsmStrOffset: 2613, .AliasCondStart: 632, .NumOperands: 4, .NumConds: 5 },
2102 {.AsmStrOffset: 2631, .AliasCondStart: 637, .NumOperands: 4, .NumConds: 5 },
2103 {.AsmStrOffset: 2650, .AliasCondStart: 642, .NumOperands: 4, .NumConds: 5 },
2104 {.AsmStrOffset: 2669, .AliasCondStart: 647, .NumOperands: 4, .NumConds: 5 },
2105 {.AsmStrOffset: 2687, .AliasCondStart: 652, .NumOperands: 4, .NumConds: 5 },
2106 {.AsmStrOffset: 2706, .AliasCondStart: 657, .NumOperands: 4, .NumConds: 5 },
2107 {.AsmStrOffset: 2726, .AliasCondStart: 662, .NumOperands: 4, .NumConds: 5 },
2108 {.AsmStrOffset: 2745, .AliasCondStart: 667, .NumOperands: 4, .NumConds: 5 },
2109 {.AsmStrOffset: 2764, .AliasCondStart: 672, .NumOperands: 4, .NumConds: 5 },
2110 {.AsmStrOffset: 2784, .AliasCondStart: 677, .NumOperands: 4, .NumConds: 5 },
2111 {.AsmStrOffset: 2804, .AliasCondStart: 682, .NumOperands: 4, .NumConds: 5 },
2112 {.AsmStrOffset: 2823, .AliasCondStart: 687, .NumOperands: 4, .NumConds: 5 },
2113 // SP::FMOVD_ICC - 196
2114 {.AsmStrOffset: 2842, .AliasCondStart: 692, .NumOperands: 4, .NumConds: 5 },
2115 {.AsmStrOffset: 2862, .AliasCondStart: 697, .NumOperands: 4, .NumConds: 5 },
2116 {.AsmStrOffset: 2882, .AliasCondStart: 702, .NumOperands: 4, .NumConds: 5 },
2117 {.AsmStrOffset: 2903, .AliasCondStart: 707, .NumOperands: 4, .NumConds: 5 },
2118 {.AsmStrOffset: 2923, .AliasCondStart: 712, .NumOperands: 4, .NumConds: 5 },
2119 {.AsmStrOffset: 2943, .AliasCondStart: 717, .NumOperands: 4, .NumConds: 5 },
2120 {.AsmStrOffset: 2964, .AliasCondStart: 722, .NumOperands: 4, .NumConds: 5 },
2121 {.AsmStrOffset: 2985, .AliasCondStart: 727, .NumOperands: 4, .NumConds: 5 },
2122 {.AsmStrOffset: 3005, .AliasCondStart: 732, .NumOperands: 4, .NumConds: 5 },
2123 {.AsmStrOffset: 3026, .AliasCondStart: 737, .NumOperands: 4, .NumConds: 5 },
2124 {.AsmStrOffset: 3048, .AliasCondStart: 742, .NumOperands: 4, .NumConds: 5 },
2125 {.AsmStrOffset: 3069, .AliasCondStart: 747, .NumOperands: 4, .NumConds: 5 },
2126 {.AsmStrOffset: 3090, .AliasCondStart: 752, .NumOperands: 4, .NumConds: 5 },
2127 {.AsmStrOffset: 3112, .AliasCondStart: 757, .NumOperands: 4, .NumConds: 5 },
2128 {.AsmStrOffset: 3134, .AliasCondStart: 762, .NumOperands: 4, .NumConds: 5 },
2129 {.AsmStrOffset: 3155, .AliasCondStart: 767, .NumOperands: 4, .NumConds: 5 },
2130 // SP::FMOVD_XCC - 212
2131 {.AsmStrOffset: 3176, .AliasCondStart: 772, .NumOperands: 4, .NumConds: 5 },
2132 {.AsmStrOffset: 3196, .AliasCondStart: 777, .NumOperands: 4, .NumConds: 5 },
2133 {.AsmStrOffset: 3216, .AliasCondStart: 782, .NumOperands: 4, .NumConds: 5 },
2134 {.AsmStrOffset: 3237, .AliasCondStart: 787, .NumOperands: 4, .NumConds: 5 },
2135 {.AsmStrOffset: 3257, .AliasCondStart: 792, .NumOperands: 4, .NumConds: 5 },
2136 {.AsmStrOffset: 3277, .AliasCondStart: 797, .NumOperands: 4, .NumConds: 5 },
2137 {.AsmStrOffset: 3298, .AliasCondStart: 802, .NumOperands: 4, .NumConds: 5 },
2138 {.AsmStrOffset: 3319, .AliasCondStart: 807, .NumOperands: 4, .NumConds: 5 },
2139 {.AsmStrOffset: 3339, .AliasCondStart: 812, .NumOperands: 4, .NumConds: 5 },
2140 {.AsmStrOffset: 3360, .AliasCondStart: 817, .NumOperands: 4, .NumConds: 5 },
2141 {.AsmStrOffset: 3382, .AliasCondStart: 822, .NumOperands: 4, .NumConds: 5 },
2142 {.AsmStrOffset: 3403, .AliasCondStart: 827, .NumOperands: 4, .NumConds: 5 },
2143 {.AsmStrOffset: 3424, .AliasCondStart: 832, .NumOperands: 4, .NumConds: 5 },
2144 {.AsmStrOffset: 3446, .AliasCondStart: 837, .NumOperands: 4, .NumConds: 5 },
2145 {.AsmStrOffset: 3468, .AliasCondStart: 842, .NumOperands: 4, .NumConds: 5 },
2146 {.AsmStrOffset: 3489, .AliasCondStart: 847, .NumOperands: 4, .NumConds: 5 },
2147 // SP::FMOVQ_ICC - 228
2148 {.AsmStrOffset: 3510, .AliasCondStart: 852, .NumOperands: 4, .NumConds: 5 },
2149 {.AsmStrOffset: 3530, .AliasCondStart: 857, .NumOperands: 4, .NumConds: 5 },
2150 {.AsmStrOffset: 3550, .AliasCondStart: 862, .NumOperands: 4, .NumConds: 5 },
2151 {.AsmStrOffset: 3571, .AliasCondStart: 867, .NumOperands: 4, .NumConds: 5 },
2152 {.AsmStrOffset: 3591, .AliasCondStart: 872, .NumOperands: 4, .NumConds: 5 },
2153 {.AsmStrOffset: 3611, .AliasCondStart: 877, .NumOperands: 4, .NumConds: 5 },
2154 {.AsmStrOffset: 3632, .AliasCondStart: 882, .NumOperands: 4, .NumConds: 5 },
2155 {.AsmStrOffset: 3653, .AliasCondStart: 887, .NumOperands: 4, .NumConds: 5 },
2156 {.AsmStrOffset: 3673, .AliasCondStart: 892, .NumOperands: 4, .NumConds: 5 },
2157 {.AsmStrOffset: 3694, .AliasCondStart: 897, .NumOperands: 4, .NumConds: 5 },
2158 {.AsmStrOffset: 3716, .AliasCondStart: 902, .NumOperands: 4, .NumConds: 5 },
2159 {.AsmStrOffset: 3737, .AliasCondStart: 907, .NumOperands: 4, .NumConds: 5 },
2160 {.AsmStrOffset: 3758, .AliasCondStart: 912, .NumOperands: 4, .NumConds: 5 },
2161 {.AsmStrOffset: 3780, .AliasCondStart: 917, .NumOperands: 4, .NumConds: 5 },
2162 {.AsmStrOffset: 3802, .AliasCondStart: 922, .NumOperands: 4, .NumConds: 5 },
2163 {.AsmStrOffset: 3823, .AliasCondStart: 927, .NumOperands: 4, .NumConds: 5 },
2164 // SP::FMOVQ_XCC - 244
2165 {.AsmStrOffset: 3844, .AliasCondStart: 932, .NumOperands: 4, .NumConds: 5 },
2166 {.AsmStrOffset: 3864, .AliasCondStart: 937, .NumOperands: 4, .NumConds: 5 },
2167 {.AsmStrOffset: 3884, .AliasCondStart: 942, .NumOperands: 4, .NumConds: 5 },
2168 {.AsmStrOffset: 3905, .AliasCondStart: 947, .NumOperands: 4, .NumConds: 5 },
2169 {.AsmStrOffset: 3925, .AliasCondStart: 952, .NumOperands: 4, .NumConds: 5 },
2170 {.AsmStrOffset: 3945, .AliasCondStart: 957, .NumOperands: 4, .NumConds: 5 },
2171 {.AsmStrOffset: 3966, .AliasCondStart: 962, .NumOperands: 4, .NumConds: 5 },
2172 {.AsmStrOffset: 3987, .AliasCondStart: 967, .NumOperands: 4, .NumConds: 5 },
2173 {.AsmStrOffset: 4007, .AliasCondStart: 972, .NumOperands: 4, .NumConds: 5 },
2174 {.AsmStrOffset: 4028, .AliasCondStart: 977, .NumOperands: 4, .NumConds: 5 },
2175 {.AsmStrOffset: 4050, .AliasCondStart: 982, .NumOperands: 4, .NumConds: 5 },
2176 {.AsmStrOffset: 4071, .AliasCondStart: 987, .NumOperands: 4, .NumConds: 5 },
2177 {.AsmStrOffset: 4092, .AliasCondStart: 992, .NumOperands: 4, .NumConds: 5 },
2178 {.AsmStrOffset: 4114, .AliasCondStart: 997, .NumOperands: 4, .NumConds: 5 },
2179 {.AsmStrOffset: 4136, .AliasCondStart: 1002, .NumOperands: 4, .NumConds: 5 },
2180 {.AsmStrOffset: 4157, .AliasCondStart: 1007, .NumOperands: 4, .NumConds: 5 },
2181 // SP::FMOVRD - 260
2182 {.AsmStrOffset: 4178, .AliasCondStart: 1012, .NumOperands: 5, .NumConds: 6 },
2183 {.AsmStrOffset: 4199, .AliasCondStart: 1018, .NumOperands: 5, .NumConds: 6 },
2184 {.AsmStrOffset: 4219, .AliasCondStart: 1024, .NumOperands: 5, .NumConds: 6 },
2185 {.AsmStrOffset: 4239, .AliasCondStart: 1030, .NumOperands: 5, .NumConds: 6 },
2186 // SP::FMOVRQ - 264
2187 {.AsmStrOffset: 4260, .AliasCondStart: 1036, .NumOperands: 5, .NumConds: 6 },
2188 {.AsmStrOffset: 4281, .AliasCondStart: 1042, .NumOperands: 5, .NumConds: 6 },
2189 {.AsmStrOffset: 4301, .AliasCondStart: 1048, .NumOperands: 5, .NumConds: 6 },
2190 {.AsmStrOffset: 4321, .AliasCondStart: 1054, .NumOperands: 5, .NumConds: 6 },
2191 // SP::FMOVRS - 268
2192 {.AsmStrOffset: 4342, .AliasCondStart: 1060, .NumOperands: 5, .NumConds: 6 },
2193 {.AsmStrOffset: 4363, .AliasCondStart: 1066, .NumOperands: 5, .NumConds: 6 },
2194 {.AsmStrOffset: 4383, .AliasCondStart: 1072, .NumOperands: 5, .NumConds: 6 },
2195 {.AsmStrOffset: 4403, .AliasCondStart: 1078, .NumOperands: 5, .NumConds: 6 },
2196 // SP::FMOVS_ICC - 272
2197 {.AsmStrOffset: 4424, .AliasCondStart: 1084, .NumOperands: 4, .NumConds: 5 },
2198 {.AsmStrOffset: 4444, .AliasCondStart: 1089, .NumOperands: 4, .NumConds: 5 },
2199 {.AsmStrOffset: 4464, .AliasCondStart: 1094, .NumOperands: 4, .NumConds: 5 },
2200 {.AsmStrOffset: 4485, .AliasCondStart: 1099, .NumOperands: 4, .NumConds: 5 },
2201 {.AsmStrOffset: 4505, .AliasCondStart: 1104, .NumOperands: 4, .NumConds: 5 },
2202 {.AsmStrOffset: 4525, .AliasCondStart: 1109, .NumOperands: 4, .NumConds: 5 },
2203 {.AsmStrOffset: 4546, .AliasCondStart: 1114, .NumOperands: 4, .NumConds: 5 },
2204 {.AsmStrOffset: 4567, .AliasCondStart: 1119, .NumOperands: 4, .NumConds: 5 },
2205 {.AsmStrOffset: 4587, .AliasCondStart: 1124, .NumOperands: 4, .NumConds: 5 },
2206 {.AsmStrOffset: 4608, .AliasCondStart: 1129, .NumOperands: 4, .NumConds: 5 },
2207 {.AsmStrOffset: 4630, .AliasCondStart: 1134, .NumOperands: 4, .NumConds: 5 },
2208 {.AsmStrOffset: 4651, .AliasCondStart: 1139, .NumOperands: 4, .NumConds: 5 },
2209 {.AsmStrOffset: 4672, .AliasCondStart: 1144, .NumOperands: 4, .NumConds: 5 },
2210 {.AsmStrOffset: 4694, .AliasCondStart: 1149, .NumOperands: 4, .NumConds: 5 },
2211 {.AsmStrOffset: 4716, .AliasCondStart: 1154, .NumOperands: 4, .NumConds: 5 },
2212 {.AsmStrOffset: 4737, .AliasCondStart: 1159, .NumOperands: 4, .NumConds: 5 },
2213 // SP::FMOVS_XCC - 288
2214 {.AsmStrOffset: 4758, .AliasCondStart: 1164, .NumOperands: 4, .NumConds: 5 },
2215 {.AsmStrOffset: 4778, .AliasCondStart: 1169, .NumOperands: 4, .NumConds: 5 },
2216 {.AsmStrOffset: 4798, .AliasCondStart: 1174, .NumOperands: 4, .NumConds: 5 },
2217 {.AsmStrOffset: 4819, .AliasCondStart: 1179, .NumOperands: 4, .NumConds: 5 },
2218 {.AsmStrOffset: 4839, .AliasCondStart: 1184, .NumOperands: 4, .NumConds: 5 },
2219 {.AsmStrOffset: 4859, .AliasCondStart: 1189, .NumOperands: 4, .NumConds: 5 },
2220 {.AsmStrOffset: 4880, .AliasCondStart: 1194, .NumOperands: 4, .NumConds: 5 },
2221 {.AsmStrOffset: 4901, .AliasCondStart: 1199, .NumOperands: 4, .NumConds: 5 },
2222 {.AsmStrOffset: 4921, .AliasCondStart: 1204, .NumOperands: 4, .NumConds: 5 },
2223 {.AsmStrOffset: 4942, .AliasCondStart: 1209, .NumOperands: 4, .NumConds: 5 },
2224 {.AsmStrOffset: 4964, .AliasCondStart: 1214, .NumOperands: 4, .NumConds: 5 },
2225 {.AsmStrOffset: 4985, .AliasCondStart: 1219, .NumOperands: 4, .NumConds: 5 },
2226 {.AsmStrOffset: 5006, .AliasCondStart: 1224, .NumOperands: 4, .NumConds: 5 },
2227 {.AsmStrOffset: 5028, .AliasCondStart: 1229, .NumOperands: 4, .NumConds: 5 },
2228 {.AsmStrOffset: 5050, .AliasCondStart: 1234, .NumOperands: 4, .NumConds: 5 },
2229 {.AsmStrOffset: 5071, .AliasCondStart: 1239, .NumOperands: 4, .NumConds: 5 },
2230 // SP::MOVICCri - 304
2231 {.AsmStrOffset: 5092, .AliasCondStart: 1244, .NumOperands: 4, .NumConds: 5 },
2232 {.AsmStrOffset: 5110, .AliasCondStart: 1249, .NumOperands: 4, .NumConds: 5 },
2233 {.AsmStrOffset: 5128, .AliasCondStart: 1254, .NumOperands: 4, .NumConds: 5 },
2234 {.AsmStrOffset: 5147, .AliasCondStart: 1259, .NumOperands: 4, .NumConds: 5 },
2235 {.AsmStrOffset: 5165, .AliasCondStart: 1264, .NumOperands: 4, .NumConds: 5 },
2236 {.AsmStrOffset: 5183, .AliasCondStart: 1269, .NumOperands: 4, .NumConds: 5 },
2237 {.AsmStrOffset: 5202, .AliasCondStart: 1274, .NumOperands: 4, .NumConds: 5 },
2238 {.AsmStrOffset: 5221, .AliasCondStart: 1279, .NumOperands: 4, .NumConds: 5 },
2239 {.AsmStrOffset: 5239, .AliasCondStart: 1284, .NumOperands: 4, .NumConds: 5 },
2240 {.AsmStrOffset: 5258, .AliasCondStart: 1289, .NumOperands: 4, .NumConds: 5 },
2241 {.AsmStrOffset: 5278, .AliasCondStart: 1294, .NumOperands: 4, .NumConds: 5 },
2242 {.AsmStrOffset: 5297, .AliasCondStart: 1299, .NumOperands: 4, .NumConds: 5 },
2243 {.AsmStrOffset: 5316, .AliasCondStart: 1304, .NumOperands: 4, .NumConds: 5 },
2244 {.AsmStrOffset: 5336, .AliasCondStart: 1309, .NumOperands: 4, .NumConds: 5 },
2245 {.AsmStrOffset: 5356, .AliasCondStart: 1314, .NumOperands: 4, .NumConds: 5 },
2246 {.AsmStrOffset: 5375, .AliasCondStart: 1319, .NumOperands: 4, .NumConds: 5 },
2247 // SP::MOVICCrr - 320
2248 {.AsmStrOffset: 5092, .AliasCondStart: 1324, .NumOperands: 4, .NumConds: 5 },
2249 {.AsmStrOffset: 5110, .AliasCondStart: 1329, .NumOperands: 4, .NumConds: 5 },
2250 {.AsmStrOffset: 5128, .AliasCondStart: 1334, .NumOperands: 4, .NumConds: 5 },
2251 {.AsmStrOffset: 5147, .AliasCondStart: 1339, .NumOperands: 4, .NumConds: 5 },
2252 {.AsmStrOffset: 5165, .AliasCondStart: 1344, .NumOperands: 4, .NumConds: 5 },
2253 {.AsmStrOffset: 5183, .AliasCondStart: 1349, .NumOperands: 4, .NumConds: 5 },
2254 {.AsmStrOffset: 5202, .AliasCondStart: 1354, .NumOperands: 4, .NumConds: 5 },
2255 {.AsmStrOffset: 5221, .AliasCondStart: 1359, .NumOperands: 4, .NumConds: 5 },
2256 {.AsmStrOffset: 5239, .AliasCondStart: 1364, .NumOperands: 4, .NumConds: 5 },
2257 {.AsmStrOffset: 5258, .AliasCondStart: 1369, .NumOperands: 4, .NumConds: 5 },
2258 {.AsmStrOffset: 5278, .AliasCondStart: 1374, .NumOperands: 4, .NumConds: 5 },
2259 {.AsmStrOffset: 5297, .AliasCondStart: 1379, .NumOperands: 4, .NumConds: 5 },
2260 {.AsmStrOffset: 5316, .AliasCondStart: 1384, .NumOperands: 4, .NumConds: 5 },
2261 {.AsmStrOffset: 5336, .AliasCondStart: 1389, .NumOperands: 4, .NumConds: 5 },
2262 {.AsmStrOffset: 5356, .AliasCondStart: 1394, .NumOperands: 4, .NumConds: 5 },
2263 {.AsmStrOffset: 5375, .AliasCondStart: 1399, .NumOperands: 4, .NumConds: 5 },
2264 // SP::MOVRri - 336
2265 {.AsmStrOffset: 5394, .AliasCondStart: 1404, .NumOperands: 5, .NumConds: 6 },
2266 {.AsmStrOffset: 5413, .AliasCondStart: 1410, .NumOperands: 5, .NumConds: 6 },
2267 {.AsmStrOffset: 5431, .AliasCondStart: 1416, .NumOperands: 5, .NumConds: 6 },
2268 {.AsmStrOffset: 5449, .AliasCondStart: 1422, .NumOperands: 5, .NumConds: 6 },
2269 // SP::MOVRrr - 340
2270 {.AsmStrOffset: 5394, .AliasCondStart: 1428, .NumOperands: 5, .NumConds: 6 },
2271 {.AsmStrOffset: 5413, .AliasCondStart: 1434, .NumOperands: 5, .NumConds: 6 },
2272 {.AsmStrOffset: 5431, .AliasCondStart: 1440, .NumOperands: 5, .NumConds: 6 },
2273 {.AsmStrOffset: 5449, .AliasCondStart: 1446, .NumOperands: 5, .NumConds: 6 },
2274 // SP::MOVXCCri - 344
2275 {.AsmStrOffset: 5468, .AliasCondStart: 1452, .NumOperands: 4, .NumConds: 5 },
2276 {.AsmStrOffset: 5486, .AliasCondStart: 1457, .NumOperands: 4, .NumConds: 5 },
2277 {.AsmStrOffset: 5504, .AliasCondStart: 1462, .NumOperands: 4, .NumConds: 5 },
2278 {.AsmStrOffset: 5523, .AliasCondStart: 1467, .NumOperands: 4, .NumConds: 5 },
2279 {.AsmStrOffset: 5541, .AliasCondStart: 1472, .NumOperands: 4, .NumConds: 5 },
2280 {.AsmStrOffset: 5559, .AliasCondStart: 1477, .NumOperands: 4, .NumConds: 5 },
2281 {.AsmStrOffset: 5578, .AliasCondStart: 1482, .NumOperands: 4, .NumConds: 5 },
2282 {.AsmStrOffset: 5597, .AliasCondStart: 1487, .NumOperands: 4, .NumConds: 5 },
2283 {.AsmStrOffset: 5615, .AliasCondStart: 1492, .NumOperands: 4, .NumConds: 5 },
2284 {.AsmStrOffset: 5634, .AliasCondStart: 1497, .NumOperands: 4, .NumConds: 5 },
2285 {.AsmStrOffset: 5654, .AliasCondStart: 1502, .NumOperands: 4, .NumConds: 5 },
2286 {.AsmStrOffset: 5673, .AliasCondStart: 1507, .NumOperands: 4, .NumConds: 5 },
2287 {.AsmStrOffset: 5692, .AliasCondStart: 1512, .NumOperands: 4, .NumConds: 5 },
2288 {.AsmStrOffset: 5712, .AliasCondStart: 1517, .NumOperands: 4, .NumConds: 5 },
2289 {.AsmStrOffset: 5732, .AliasCondStart: 1522, .NumOperands: 4, .NumConds: 5 },
2290 {.AsmStrOffset: 5751, .AliasCondStart: 1527, .NumOperands: 4, .NumConds: 5 },
2291 // SP::MOVXCCrr - 360
2292 {.AsmStrOffset: 5468, .AliasCondStart: 1532, .NumOperands: 4, .NumConds: 5 },
2293 {.AsmStrOffset: 5486, .AliasCondStart: 1537, .NumOperands: 4, .NumConds: 5 },
2294 {.AsmStrOffset: 5504, .AliasCondStart: 1542, .NumOperands: 4, .NumConds: 5 },
2295 {.AsmStrOffset: 5523, .AliasCondStart: 1547, .NumOperands: 4, .NumConds: 5 },
2296 {.AsmStrOffset: 5541, .AliasCondStart: 1552, .NumOperands: 4, .NumConds: 5 },
2297 {.AsmStrOffset: 5559, .AliasCondStart: 1557, .NumOperands: 4, .NumConds: 5 },
2298 {.AsmStrOffset: 5578, .AliasCondStart: 1562, .NumOperands: 4, .NumConds: 5 },
2299 {.AsmStrOffset: 5597, .AliasCondStart: 1567, .NumOperands: 4, .NumConds: 5 },
2300 {.AsmStrOffset: 5615, .AliasCondStart: 1572, .NumOperands: 4, .NumConds: 5 },
2301 {.AsmStrOffset: 5634, .AliasCondStart: 1577, .NumOperands: 4, .NumConds: 5 },
2302 {.AsmStrOffset: 5654, .AliasCondStart: 1582, .NumOperands: 4, .NumConds: 5 },
2303 {.AsmStrOffset: 5673, .AliasCondStart: 1587, .NumOperands: 4, .NumConds: 5 },
2304 {.AsmStrOffset: 5692, .AliasCondStart: 1592, .NumOperands: 4, .NumConds: 5 },
2305 {.AsmStrOffset: 5712, .AliasCondStart: 1597, .NumOperands: 4, .NumConds: 5 },
2306 {.AsmStrOffset: 5732, .AliasCondStart: 1602, .NumOperands: 4, .NumConds: 5 },
2307 {.AsmStrOffset: 5751, .AliasCondStart: 1607, .NumOperands: 4, .NumConds: 5 },
2308 // SP::ORCCrr - 376
2309 {.AsmStrOffset: 5770, .AliasCondStart: 1612, .NumOperands: 3, .NumConds: 3 },
2310 // SP::ORri - 377
2311 {.AsmStrOffset: 5777, .AliasCondStart: 1615, .NumOperands: 3, .NumConds: 2 },
2312 // SP::ORrr - 378
2313 {.AsmStrOffset: 5777, .AliasCondStart: 1617, .NumOperands: 3, .NumConds: 3 },
2314 // SP::RESTORErr - 379
2315 {.AsmStrOffset: 5788, .AliasCondStart: 1620, .NumOperands: 3, .NumConds: 3 },
2316 // SP::RET - 380
2317 {.AsmStrOffset: 5796, .AliasCondStart: 1623, .NumOperands: 1, .NumConds: 1 },
2318 // SP::RETL - 381
2319 {.AsmStrOffset: 5800, .AliasCondStart: 1624, .NumOperands: 1, .NumConds: 1 },
2320 // SP::SAVErr - 382
2321 {.AsmStrOffset: 5805, .AliasCondStart: 1625, .NumOperands: 3, .NumConds: 3 },
2322 // SP::SUBCCri - 383
2323 {.AsmStrOffset: 5810, .AliasCondStart: 1628, .NumOperands: 3, .NumConds: 2 },
2324 // SP::SUBCCrr - 384
2325 {.AsmStrOffset: 5810, .AliasCondStart: 1630, .NumOperands: 3, .NumConds: 3 },
2326 // SP::TICCri - 385
2327 {.AsmStrOffset: 5821, .AliasCondStart: 1633, .NumOperands: 3, .NumConds: 4 },
2328 {.AsmStrOffset: 5833, .AliasCondStart: 1637, .NumOperands: 3, .NumConds: 4 },
2329 {.AsmStrOffset: 5850, .AliasCondStart: 1641, .NumOperands: 3, .NumConds: 4 },
2330 {.AsmStrOffset: 5862, .AliasCondStart: 1645, .NumOperands: 3, .NumConds: 4 },
2331 {.AsmStrOffset: 5879, .AliasCondStart: 1649, .NumOperands: 3, .NumConds: 4 },
2332 {.AsmStrOffset: 5892, .AliasCondStart: 1653, .NumOperands: 3, .NumConds: 4 },
2333 {.AsmStrOffset: 5910, .AliasCondStart: 1657, .NumOperands: 3, .NumConds: 4 },
2334 {.AsmStrOffset: 5922, .AliasCondStart: 1661, .NumOperands: 3, .NumConds: 4 },
2335 {.AsmStrOffset: 5939, .AliasCondStart: 1665, .NumOperands: 3, .NumConds: 4 },
2336 {.AsmStrOffset: 5951, .AliasCondStart: 1669, .NumOperands: 3, .NumConds: 4 },
2337 {.AsmStrOffset: 5968, .AliasCondStart: 1673, .NumOperands: 3, .NumConds: 4 },
2338 {.AsmStrOffset: 5981, .AliasCondStart: 1677, .NumOperands: 3, .NumConds: 4 },
2339 {.AsmStrOffset: 5999, .AliasCondStart: 1681, .NumOperands: 3, .NumConds: 4 },
2340 {.AsmStrOffset: 6012, .AliasCondStart: 1685, .NumOperands: 3, .NumConds: 4 },
2341 {.AsmStrOffset: 6030, .AliasCondStart: 1689, .NumOperands: 3, .NumConds: 4 },
2342 {.AsmStrOffset: 6042, .AliasCondStart: 1693, .NumOperands: 3, .NumConds: 4 },
2343 {.AsmStrOffset: 6059, .AliasCondStart: 1697, .NumOperands: 3, .NumConds: 4 },
2344 {.AsmStrOffset: 6072, .AliasCondStart: 1701, .NumOperands: 3, .NumConds: 4 },
2345 {.AsmStrOffset: 6090, .AliasCondStart: 1705, .NumOperands: 3, .NumConds: 4 },
2346 {.AsmStrOffset: 6104, .AliasCondStart: 1709, .NumOperands: 3, .NumConds: 4 },
2347 {.AsmStrOffset: 6123, .AliasCondStart: 1713, .NumOperands: 3, .NumConds: 4 },
2348 {.AsmStrOffset: 6136, .AliasCondStart: 1717, .NumOperands: 3, .NumConds: 4 },
2349 {.AsmStrOffset: 6154, .AliasCondStart: 1721, .NumOperands: 3, .NumConds: 4 },
2350 {.AsmStrOffset: 6167, .AliasCondStart: 1725, .NumOperands: 3, .NumConds: 4 },
2351 {.AsmStrOffset: 6185, .AliasCondStart: 1729, .NumOperands: 3, .NumConds: 4 },
2352 {.AsmStrOffset: 6199, .AliasCondStart: 1733, .NumOperands: 3, .NumConds: 4 },
2353 {.AsmStrOffset: 6218, .AliasCondStart: 1737, .NumOperands: 3, .NumConds: 4 },
2354 {.AsmStrOffset: 6232, .AliasCondStart: 1741, .NumOperands: 3, .NumConds: 4 },
2355 {.AsmStrOffset: 6251, .AliasCondStart: 1745, .NumOperands: 3, .NumConds: 4 },
2356 {.AsmStrOffset: 6264, .AliasCondStart: 1749, .NumOperands: 3, .NumConds: 4 },
2357 {.AsmStrOffset: 6282, .AliasCondStart: 1753, .NumOperands: 3, .NumConds: 4 },
2358 {.AsmStrOffset: 6295, .AliasCondStart: 1757, .NumOperands: 3, .NumConds: 4 },
2359 // SP::TICCrr - 417
2360 {.AsmStrOffset: 5821, .AliasCondStart: 1761, .NumOperands: 3, .NumConds: 4 },
2361 {.AsmStrOffset: 5833, .AliasCondStart: 1765, .NumOperands: 3, .NumConds: 4 },
2362 {.AsmStrOffset: 5850, .AliasCondStart: 1769, .NumOperands: 3, .NumConds: 4 },
2363 {.AsmStrOffset: 5862, .AliasCondStart: 1773, .NumOperands: 3, .NumConds: 4 },
2364 {.AsmStrOffset: 5879, .AliasCondStart: 1777, .NumOperands: 3, .NumConds: 4 },
2365 {.AsmStrOffset: 5892, .AliasCondStart: 1781, .NumOperands: 3, .NumConds: 4 },
2366 {.AsmStrOffset: 5910, .AliasCondStart: 1785, .NumOperands: 3, .NumConds: 4 },
2367 {.AsmStrOffset: 5922, .AliasCondStart: 1789, .NumOperands: 3, .NumConds: 4 },
2368 {.AsmStrOffset: 5939, .AliasCondStart: 1793, .NumOperands: 3, .NumConds: 4 },
2369 {.AsmStrOffset: 5951, .AliasCondStart: 1797, .NumOperands: 3, .NumConds: 4 },
2370 {.AsmStrOffset: 5968, .AliasCondStart: 1801, .NumOperands: 3, .NumConds: 4 },
2371 {.AsmStrOffset: 5981, .AliasCondStart: 1805, .NumOperands: 3, .NumConds: 4 },
2372 {.AsmStrOffset: 5999, .AliasCondStart: 1809, .NumOperands: 3, .NumConds: 4 },
2373 {.AsmStrOffset: 6012, .AliasCondStart: 1813, .NumOperands: 3, .NumConds: 4 },
2374 {.AsmStrOffset: 6030, .AliasCondStart: 1817, .NumOperands: 3, .NumConds: 4 },
2375 {.AsmStrOffset: 6042, .AliasCondStart: 1821, .NumOperands: 3, .NumConds: 4 },
2376 {.AsmStrOffset: 6059, .AliasCondStart: 1825, .NumOperands: 3, .NumConds: 4 },
2377 {.AsmStrOffset: 6072, .AliasCondStart: 1829, .NumOperands: 3, .NumConds: 4 },
2378 {.AsmStrOffset: 6090, .AliasCondStart: 1833, .NumOperands: 3, .NumConds: 4 },
2379 {.AsmStrOffset: 6104, .AliasCondStart: 1837, .NumOperands: 3, .NumConds: 4 },
2380 {.AsmStrOffset: 6123, .AliasCondStart: 1841, .NumOperands: 3, .NumConds: 4 },
2381 {.AsmStrOffset: 6136, .AliasCondStart: 1845, .NumOperands: 3, .NumConds: 4 },
2382 {.AsmStrOffset: 6154, .AliasCondStart: 1849, .NumOperands: 3, .NumConds: 4 },
2383 {.AsmStrOffset: 6167, .AliasCondStart: 1853, .NumOperands: 3, .NumConds: 4 },
2384 {.AsmStrOffset: 6185, .AliasCondStart: 1857, .NumOperands: 3, .NumConds: 4 },
2385 {.AsmStrOffset: 6199, .AliasCondStart: 1861, .NumOperands: 3, .NumConds: 4 },
2386 {.AsmStrOffset: 6218, .AliasCondStart: 1865, .NumOperands: 3, .NumConds: 4 },
2387 {.AsmStrOffset: 6232, .AliasCondStart: 1869, .NumOperands: 3, .NumConds: 4 },
2388 {.AsmStrOffset: 6251, .AliasCondStart: 1873, .NumOperands: 3, .NumConds: 4 },
2389 {.AsmStrOffset: 6264, .AliasCondStart: 1877, .NumOperands: 3, .NumConds: 4 },
2390 {.AsmStrOffset: 6282, .AliasCondStart: 1881, .NumOperands: 3, .NumConds: 4 },
2391 {.AsmStrOffset: 6295, .AliasCondStart: 1885, .NumOperands: 3, .NumConds: 4 },
2392 // SP::TRAPri - 449
2393 {.AsmStrOffset: 6313, .AliasCondStart: 1889, .NumOperands: 3, .NumConds: 3 },
2394 {.AsmStrOffset: 6319, .AliasCondStart: 1892, .NumOperands: 3, .NumConds: 3 },
2395 {.AsmStrOffset: 6330, .AliasCondStart: 1895, .NumOperands: 3, .NumConds: 3 },
2396 {.AsmStrOffset: 6336, .AliasCondStart: 1898, .NumOperands: 3, .NumConds: 3 },
2397 {.AsmStrOffset: 6347, .AliasCondStart: 1901, .NumOperands: 3, .NumConds: 3 },
2398 {.AsmStrOffset: 6354, .AliasCondStart: 1904, .NumOperands: 3, .NumConds: 3 },
2399 {.AsmStrOffset: 6366, .AliasCondStart: 1907, .NumOperands: 3, .NumConds: 3 },
2400 {.AsmStrOffset: 6372, .AliasCondStart: 1910, .NumOperands: 3, .NumConds: 3 },
2401 {.AsmStrOffset: 6383, .AliasCondStart: 1913, .NumOperands: 3, .NumConds: 3 },
2402 {.AsmStrOffset: 6389, .AliasCondStart: 1916, .NumOperands: 3, .NumConds: 3 },
2403 {.AsmStrOffset: 6400, .AliasCondStart: 1919, .NumOperands: 3, .NumConds: 3 },
2404 {.AsmStrOffset: 6407, .AliasCondStart: 1922, .NumOperands: 3, .NumConds: 3 },
2405 {.AsmStrOffset: 6419, .AliasCondStart: 1925, .NumOperands: 3, .NumConds: 3 },
2406 {.AsmStrOffset: 6426, .AliasCondStart: 1928, .NumOperands: 3, .NumConds: 3 },
2407 {.AsmStrOffset: 6438, .AliasCondStart: 1931, .NumOperands: 3, .NumConds: 3 },
2408 {.AsmStrOffset: 6444, .AliasCondStart: 1934, .NumOperands: 3, .NumConds: 3 },
2409 {.AsmStrOffset: 6455, .AliasCondStart: 1937, .NumOperands: 3, .NumConds: 3 },
2410 {.AsmStrOffset: 6462, .AliasCondStart: 1940, .NumOperands: 3, .NumConds: 3 },
2411 {.AsmStrOffset: 6474, .AliasCondStart: 1943, .NumOperands: 3, .NumConds: 3 },
2412 {.AsmStrOffset: 6482, .AliasCondStart: 1946, .NumOperands: 3, .NumConds: 3 },
2413 {.AsmStrOffset: 6495, .AliasCondStart: 1949, .NumOperands: 3, .NumConds: 3 },
2414 {.AsmStrOffset: 6502, .AliasCondStart: 1952, .NumOperands: 3, .NumConds: 3 },
2415 {.AsmStrOffset: 6514, .AliasCondStart: 1955, .NumOperands: 3, .NumConds: 3 },
2416 {.AsmStrOffset: 6521, .AliasCondStart: 1958, .NumOperands: 3, .NumConds: 3 },
2417 {.AsmStrOffset: 6533, .AliasCondStart: 1961, .NumOperands: 3, .NumConds: 3 },
2418 {.AsmStrOffset: 6541, .AliasCondStart: 1964, .NumOperands: 3, .NumConds: 3 },
2419 {.AsmStrOffset: 6554, .AliasCondStart: 1967, .NumOperands: 3, .NumConds: 3 },
2420 {.AsmStrOffset: 6562, .AliasCondStart: 1970, .NumOperands: 3, .NumConds: 3 },
2421 {.AsmStrOffset: 6575, .AliasCondStart: 1973, .NumOperands: 3, .NumConds: 3 },
2422 {.AsmStrOffset: 6582, .AliasCondStart: 1976, .NumOperands: 3, .NumConds: 3 },
2423 {.AsmStrOffset: 6594, .AliasCondStart: 1979, .NumOperands: 3, .NumConds: 3 },
2424 {.AsmStrOffset: 6601, .AliasCondStart: 1982, .NumOperands: 3, .NumConds: 3 },
2425 // SP::TRAPrr - 481
2426 {.AsmStrOffset: 6313, .AliasCondStart: 1985, .NumOperands: 3, .NumConds: 3 },
2427 {.AsmStrOffset: 6319, .AliasCondStart: 1988, .NumOperands: 3, .NumConds: 3 },
2428 {.AsmStrOffset: 6330, .AliasCondStart: 1991, .NumOperands: 3, .NumConds: 3 },
2429 {.AsmStrOffset: 6336, .AliasCondStart: 1994, .NumOperands: 3, .NumConds: 3 },
2430 {.AsmStrOffset: 6347, .AliasCondStart: 1997, .NumOperands: 3, .NumConds: 3 },
2431 {.AsmStrOffset: 6354, .AliasCondStart: 2000, .NumOperands: 3, .NumConds: 3 },
2432 {.AsmStrOffset: 6366, .AliasCondStart: 2003, .NumOperands: 3, .NumConds: 3 },
2433 {.AsmStrOffset: 6372, .AliasCondStart: 2006, .NumOperands: 3, .NumConds: 3 },
2434 {.AsmStrOffset: 6383, .AliasCondStart: 2009, .NumOperands: 3, .NumConds: 3 },
2435 {.AsmStrOffset: 6389, .AliasCondStart: 2012, .NumOperands: 3, .NumConds: 3 },
2436 {.AsmStrOffset: 6400, .AliasCondStart: 2015, .NumOperands: 3, .NumConds: 3 },
2437 {.AsmStrOffset: 6407, .AliasCondStart: 2018, .NumOperands: 3, .NumConds: 3 },
2438 {.AsmStrOffset: 6419, .AliasCondStart: 2021, .NumOperands: 3, .NumConds: 3 },
2439 {.AsmStrOffset: 6426, .AliasCondStart: 2024, .NumOperands: 3, .NumConds: 3 },
2440 {.AsmStrOffset: 6438, .AliasCondStart: 2027, .NumOperands: 3, .NumConds: 3 },
2441 {.AsmStrOffset: 6444, .AliasCondStart: 2030, .NumOperands: 3, .NumConds: 3 },
2442 {.AsmStrOffset: 6455, .AliasCondStart: 2033, .NumOperands: 3, .NumConds: 3 },
2443 {.AsmStrOffset: 6462, .AliasCondStart: 2036, .NumOperands: 3, .NumConds: 3 },
2444 {.AsmStrOffset: 6474, .AliasCondStart: 2039, .NumOperands: 3, .NumConds: 3 },
2445 {.AsmStrOffset: 6482, .AliasCondStart: 2042, .NumOperands: 3, .NumConds: 3 },
2446 {.AsmStrOffset: 6495, .AliasCondStart: 2045, .NumOperands: 3, .NumConds: 3 },
2447 {.AsmStrOffset: 6502, .AliasCondStart: 2048, .NumOperands: 3, .NumConds: 3 },
2448 {.AsmStrOffset: 6514, .AliasCondStart: 2051, .NumOperands: 3, .NumConds: 3 },
2449 {.AsmStrOffset: 6521, .AliasCondStart: 2054, .NumOperands: 3, .NumConds: 3 },
2450 {.AsmStrOffset: 6533, .AliasCondStart: 2057, .NumOperands: 3, .NumConds: 3 },
2451 {.AsmStrOffset: 6541, .AliasCondStart: 2060, .NumOperands: 3, .NumConds: 3 },
2452 {.AsmStrOffset: 6554, .AliasCondStart: 2063, .NumOperands: 3, .NumConds: 3 },
2453 {.AsmStrOffset: 6562, .AliasCondStart: 2066, .NumOperands: 3, .NumConds: 3 },
2454 {.AsmStrOffset: 6575, .AliasCondStart: 2069, .NumOperands: 3, .NumConds: 3 },
2455 {.AsmStrOffset: 6582, .AliasCondStart: 2072, .NumOperands: 3, .NumConds: 3 },
2456 {.AsmStrOffset: 6594, .AliasCondStart: 2075, .NumOperands: 3, .NumConds: 3 },
2457 {.AsmStrOffset: 6601, .AliasCondStart: 2078, .NumOperands: 3, .NumConds: 3 },
2458 // SP::TXCCri - 513
2459 {.AsmStrOffset: 6613, .AliasCondStart: 2081, .NumOperands: 3, .NumConds: 4 },
2460 {.AsmStrOffset: 6625, .AliasCondStart: 2085, .NumOperands: 3, .NumConds: 4 },
2461 {.AsmStrOffset: 6642, .AliasCondStart: 2089, .NumOperands: 3, .NumConds: 4 },
2462 {.AsmStrOffset: 6654, .AliasCondStart: 2093, .NumOperands: 3, .NumConds: 4 },
2463 {.AsmStrOffset: 6671, .AliasCondStart: 2097, .NumOperands: 3, .NumConds: 4 },
2464 {.AsmStrOffset: 6684, .AliasCondStart: 2101, .NumOperands: 3, .NumConds: 4 },
2465 {.AsmStrOffset: 6702, .AliasCondStart: 2105, .NumOperands: 3, .NumConds: 4 },
2466 {.AsmStrOffset: 6714, .AliasCondStart: 2109, .NumOperands: 3, .NumConds: 4 },
2467 {.AsmStrOffset: 6731, .AliasCondStart: 2113, .NumOperands: 3, .NumConds: 4 },
2468 {.AsmStrOffset: 6743, .AliasCondStart: 2117, .NumOperands: 3, .NumConds: 4 },
2469 {.AsmStrOffset: 6760, .AliasCondStart: 2121, .NumOperands: 3, .NumConds: 4 },
2470 {.AsmStrOffset: 6773, .AliasCondStart: 2125, .NumOperands: 3, .NumConds: 4 },
2471 {.AsmStrOffset: 6791, .AliasCondStart: 2129, .NumOperands: 3, .NumConds: 4 },
2472 {.AsmStrOffset: 6804, .AliasCondStart: 2133, .NumOperands: 3, .NumConds: 4 },
2473 {.AsmStrOffset: 6822, .AliasCondStart: 2137, .NumOperands: 3, .NumConds: 4 },
2474 {.AsmStrOffset: 6834, .AliasCondStart: 2141, .NumOperands: 3, .NumConds: 4 },
2475 {.AsmStrOffset: 6851, .AliasCondStart: 2145, .NumOperands: 3, .NumConds: 4 },
2476 {.AsmStrOffset: 6864, .AliasCondStart: 2149, .NumOperands: 3, .NumConds: 4 },
2477 {.AsmStrOffset: 6882, .AliasCondStart: 2153, .NumOperands: 3, .NumConds: 4 },
2478 {.AsmStrOffset: 6896, .AliasCondStart: 2157, .NumOperands: 3, .NumConds: 4 },
2479 {.AsmStrOffset: 6915, .AliasCondStart: 2161, .NumOperands: 3, .NumConds: 4 },
2480 {.AsmStrOffset: 6928, .AliasCondStart: 2165, .NumOperands: 3, .NumConds: 4 },
2481 {.AsmStrOffset: 6946, .AliasCondStart: 2169, .NumOperands: 3, .NumConds: 4 },
2482 {.AsmStrOffset: 6959, .AliasCondStart: 2173, .NumOperands: 3, .NumConds: 4 },
2483 {.AsmStrOffset: 6977, .AliasCondStart: 2177, .NumOperands: 3, .NumConds: 4 },
2484 {.AsmStrOffset: 6991, .AliasCondStart: 2181, .NumOperands: 3, .NumConds: 4 },
2485 {.AsmStrOffset: 7010, .AliasCondStart: 2185, .NumOperands: 3, .NumConds: 4 },
2486 {.AsmStrOffset: 7024, .AliasCondStart: 2189, .NumOperands: 3, .NumConds: 4 },
2487 {.AsmStrOffset: 7043, .AliasCondStart: 2193, .NumOperands: 3, .NumConds: 4 },
2488 {.AsmStrOffset: 7056, .AliasCondStart: 2197, .NumOperands: 3, .NumConds: 4 },
2489 {.AsmStrOffset: 7074, .AliasCondStart: 2201, .NumOperands: 3, .NumConds: 4 },
2490 {.AsmStrOffset: 7087, .AliasCondStart: 2205, .NumOperands: 3, .NumConds: 4 },
2491 // SP::TXCCrr - 545
2492 {.AsmStrOffset: 6613, .AliasCondStart: 2209, .NumOperands: 3, .NumConds: 4 },
2493 {.AsmStrOffset: 6625, .AliasCondStart: 2213, .NumOperands: 3, .NumConds: 4 },
2494 {.AsmStrOffset: 6642, .AliasCondStart: 2217, .NumOperands: 3, .NumConds: 4 },
2495 {.AsmStrOffset: 6654, .AliasCondStart: 2221, .NumOperands: 3, .NumConds: 4 },
2496 {.AsmStrOffset: 6671, .AliasCondStart: 2225, .NumOperands: 3, .NumConds: 4 },
2497 {.AsmStrOffset: 6684, .AliasCondStart: 2229, .NumOperands: 3, .NumConds: 4 },
2498 {.AsmStrOffset: 6702, .AliasCondStart: 2233, .NumOperands: 3, .NumConds: 4 },
2499 {.AsmStrOffset: 6714, .AliasCondStart: 2237, .NumOperands: 3, .NumConds: 4 },
2500 {.AsmStrOffset: 6731, .AliasCondStart: 2241, .NumOperands: 3, .NumConds: 4 },
2501 {.AsmStrOffset: 6743, .AliasCondStart: 2245, .NumOperands: 3, .NumConds: 4 },
2502 {.AsmStrOffset: 6760, .AliasCondStart: 2249, .NumOperands: 3, .NumConds: 4 },
2503 {.AsmStrOffset: 6773, .AliasCondStart: 2253, .NumOperands: 3, .NumConds: 4 },
2504 {.AsmStrOffset: 6791, .AliasCondStart: 2257, .NumOperands: 3, .NumConds: 4 },
2505 {.AsmStrOffset: 6804, .AliasCondStart: 2261, .NumOperands: 3, .NumConds: 4 },
2506 {.AsmStrOffset: 6822, .AliasCondStart: 2265, .NumOperands: 3, .NumConds: 4 },
2507 {.AsmStrOffset: 6834, .AliasCondStart: 2269, .NumOperands: 3, .NumConds: 4 },
2508 {.AsmStrOffset: 6851, .AliasCondStart: 2273, .NumOperands: 3, .NumConds: 4 },
2509 {.AsmStrOffset: 6864, .AliasCondStart: 2277, .NumOperands: 3, .NumConds: 4 },
2510 {.AsmStrOffset: 6882, .AliasCondStart: 2281, .NumOperands: 3, .NumConds: 4 },
2511 {.AsmStrOffset: 6896, .AliasCondStart: 2285, .NumOperands: 3, .NumConds: 4 },
2512 {.AsmStrOffset: 6915, .AliasCondStart: 2289, .NumOperands: 3, .NumConds: 4 },
2513 {.AsmStrOffset: 6928, .AliasCondStart: 2293, .NumOperands: 3, .NumConds: 4 },
2514 {.AsmStrOffset: 6946, .AliasCondStart: 2297, .NumOperands: 3, .NumConds: 4 },
2515 {.AsmStrOffset: 6959, .AliasCondStart: 2301, .NumOperands: 3, .NumConds: 4 },
2516 {.AsmStrOffset: 6977, .AliasCondStart: 2305, .NumOperands: 3, .NumConds: 4 },
2517 {.AsmStrOffset: 6991, .AliasCondStart: 2309, .NumOperands: 3, .NumConds: 4 },
2518 {.AsmStrOffset: 7010, .AliasCondStart: 2313, .NumOperands: 3, .NumConds: 4 },
2519 {.AsmStrOffset: 7024, .AliasCondStart: 2317, .NumOperands: 3, .NumConds: 4 },
2520 {.AsmStrOffset: 7043, .AliasCondStart: 2321, .NumOperands: 3, .NumConds: 4 },
2521 {.AsmStrOffset: 7056, .AliasCondStart: 2325, .NumOperands: 3, .NumConds: 4 },
2522 {.AsmStrOffset: 7074, .AliasCondStart: 2329, .NumOperands: 3, .NumConds: 4 },
2523 {.AsmStrOffset: 7087, .AliasCondStart: 2333, .NumOperands: 3, .NumConds: 4 },
2524 // SP::V9FCMPD - 577
2525 {.AsmStrOffset: 7105, .AliasCondStart: 2337, .NumOperands: 3, .NumConds: 3 },
2526 // SP::V9FCMPED - 578
2527 {.AsmStrOffset: 7118, .AliasCondStart: 2340, .NumOperands: 3, .NumConds: 3 },
2528 // SP::V9FCMPEQ - 579
2529 {.AsmStrOffset: 7132, .AliasCondStart: 2343, .NumOperands: 3, .NumConds: 3 },
2530 // SP::V9FCMPES - 580
2531 {.AsmStrOffset: 7146, .AliasCondStart: 2346, .NumOperands: 3, .NumConds: 3 },
2532 // SP::V9FCMPQ - 581
2533 {.AsmStrOffset: 7160, .AliasCondStart: 2349, .NumOperands: 3, .NumConds: 3 },
2534 // SP::V9FCMPS - 582
2535 {.AsmStrOffset: 7173, .AliasCondStart: 2352, .NumOperands: 3, .NumConds: 3 },
2536 // SP::V9FMOVD_FCC - 583
2537 {.AsmStrOffset: 7186, .AliasCondStart: 2355, .NumOperands: 5, .NumConds: 6 },
2538 {.AsmStrOffset: 7204, .AliasCondStart: 2361, .NumOperands: 5, .NumConds: 6 },
2539 {.AsmStrOffset: 7222, .AliasCondStart: 2367, .NumOperands: 5, .NumConds: 6 },
2540 {.AsmStrOffset: 7240, .AliasCondStart: 2373, .NumOperands: 5, .NumConds: 6 },
2541 {.AsmStrOffset: 7258, .AliasCondStart: 2379, .NumOperands: 5, .NumConds: 6 },
2542 {.AsmStrOffset: 7277, .AliasCondStart: 2385, .NumOperands: 5, .NumConds: 6 },
2543 {.AsmStrOffset: 7295, .AliasCondStart: 2391, .NumOperands: 5, .NumConds: 6 },
2544 {.AsmStrOffset: 7314, .AliasCondStart: 2397, .NumOperands: 5, .NumConds: 6 },
2545 {.AsmStrOffset: 7333, .AliasCondStart: 2403, .NumOperands: 5, .NumConds: 6 },
2546 {.AsmStrOffset: 7352, .AliasCondStart: 2409, .NumOperands: 5, .NumConds: 6 },
2547 {.AsmStrOffset: 7370, .AliasCondStart: 2415, .NumOperands: 5, .NumConds: 6 },
2548 {.AsmStrOffset: 7389, .AliasCondStart: 2421, .NumOperands: 5, .NumConds: 6 },
2549 {.AsmStrOffset: 7408, .AliasCondStart: 2427, .NumOperands: 5, .NumConds: 6 },
2550 {.AsmStrOffset: 7428, .AliasCondStart: 2433, .NumOperands: 5, .NumConds: 6 },
2551 {.AsmStrOffset: 7447, .AliasCondStart: 2439, .NumOperands: 5, .NumConds: 6 },
2552 {.AsmStrOffset: 7467, .AliasCondStart: 2445, .NumOperands: 5, .NumConds: 6 },
2553 // SP::V9FMOVQ_FCC - 599
2554 {.AsmStrOffset: 7485, .AliasCondStart: 2451, .NumOperands: 5, .NumConds: 6 },
2555 {.AsmStrOffset: 7503, .AliasCondStart: 2457, .NumOperands: 5, .NumConds: 6 },
2556 {.AsmStrOffset: 7521, .AliasCondStart: 2463, .NumOperands: 5, .NumConds: 6 },
2557 {.AsmStrOffset: 7539, .AliasCondStart: 2469, .NumOperands: 5, .NumConds: 6 },
2558 {.AsmStrOffset: 7557, .AliasCondStart: 2475, .NumOperands: 5, .NumConds: 6 },
2559 {.AsmStrOffset: 7576, .AliasCondStart: 2481, .NumOperands: 5, .NumConds: 6 },
2560 {.AsmStrOffset: 7594, .AliasCondStart: 2487, .NumOperands: 5, .NumConds: 6 },
2561 {.AsmStrOffset: 7613, .AliasCondStart: 2493, .NumOperands: 5, .NumConds: 6 },
2562 {.AsmStrOffset: 7632, .AliasCondStart: 2499, .NumOperands: 5, .NumConds: 6 },
2563 {.AsmStrOffset: 7651, .AliasCondStart: 2505, .NumOperands: 5, .NumConds: 6 },
2564 {.AsmStrOffset: 7669, .AliasCondStart: 2511, .NumOperands: 5, .NumConds: 6 },
2565 {.AsmStrOffset: 7688, .AliasCondStart: 2517, .NumOperands: 5, .NumConds: 6 },
2566 {.AsmStrOffset: 7707, .AliasCondStart: 2523, .NumOperands: 5, .NumConds: 6 },
2567 {.AsmStrOffset: 7727, .AliasCondStart: 2529, .NumOperands: 5, .NumConds: 6 },
2568 {.AsmStrOffset: 7746, .AliasCondStart: 2535, .NumOperands: 5, .NumConds: 6 },
2569 {.AsmStrOffset: 7766, .AliasCondStart: 2541, .NumOperands: 5, .NumConds: 6 },
2570 // SP::V9FMOVS_FCC - 615
2571 {.AsmStrOffset: 7784, .AliasCondStart: 2547, .NumOperands: 5, .NumConds: 6 },
2572 {.AsmStrOffset: 7802, .AliasCondStart: 2553, .NumOperands: 5, .NumConds: 6 },
2573 {.AsmStrOffset: 7820, .AliasCondStart: 2559, .NumOperands: 5, .NumConds: 6 },
2574 {.AsmStrOffset: 7838, .AliasCondStart: 2565, .NumOperands: 5, .NumConds: 6 },
2575 {.AsmStrOffset: 7856, .AliasCondStart: 2571, .NumOperands: 5, .NumConds: 6 },
2576 {.AsmStrOffset: 7875, .AliasCondStart: 2577, .NumOperands: 5, .NumConds: 6 },
2577 {.AsmStrOffset: 7893, .AliasCondStart: 2583, .NumOperands: 5, .NumConds: 6 },
2578 {.AsmStrOffset: 7912, .AliasCondStart: 2589, .NumOperands: 5, .NumConds: 6 },
2579 {.AsmStrOffset: 7931, .AliasCondStart: 2595, .NumOperands: 5, .NumConds: 6 },
2580 {.AsmStrOffset: 7950, .AliasCondStart: 2601, .NumOperands: 5, .NumConds: 6 },
2581 {.AsmStrOffset: 7968, .AliasCondStart: 2607, .NumOperands: 5, .NumConds: 6 },
2582 {.AsmStrOffset: 7987, .AliasCondStart: 2613, .NumOperands: 5, .NumConds: 6 },
2583 {.AsmStrOffset: 8006, .AliasCondStart: 2619, .NumOperands: 5, .NumConds: 6 },
2584 {.AsmStrOffset: 8026, .AliasCondStart: 2625, .NumOperands: 5, .NumConds: 6 },
2585 {.AsmStrOffset: 8045, .AliasCondStart: 2631, .NumOperands: 5, .NumConds: 6 },
2586 {.AsmStrOffset: 8065, .AliasCondStart: 2637, .NumOperands: 5, .NumConds: 6 },
2587 // SP::V9MOVFCCri - 631
2588 {.AsmStrOffset: 8083, .AliasCondStart: 2643, .NumOperands: 5, .NumConds: 6 },
2589 {.AsmStrOffset: 8099, .AliasCondStart: 2649, .NumOperands: 5, .NumConds: 6 },
2590 {.AsmStrOffset: 8115, .AliasCondStart: 2655, .NumOperands: 5, .NumConds: 6 },
2591 {.AsmStrOffset: 8131, .AliasCondStart: 2661, .NumOperands: 5, .NumConds: 6 },
2592 {.AsmStrOffset: 8147, .AliasCondStart: 2667, .NumOperands: 5, .NumConds: 6 },
2593 {.AsmStrOffset: 8164, .AliasCondStart: 2673, .NumOperands: 5, .NumConds: 6 },
2594 {.AsmStrOffset: 8180, .AliasCondStart: 2679, .NumOperands: 5, .NumConds: 6 },
2595 {.AsmStrOffset: 8197, .AliasCondStart: 2685, .NumOperands: 5, .NumConds: 6 },
2596 {.AsmStrOffset: 8214, .AliasCondStart: 2691, .NumOperands: 5, .NumConds: 6 },
2597 {.AsmStrOffset: 8231, .AliasCondStart: 2697, .NumOperands: 5, .NumConds: 6 },
2598 {.AsmStrOffset: 8247, .AliasCondStart: 2703, .NumOperands: 5, .NumConds: 6 },
2599 {.AsmStrOffset: 8264, .AliasCondStart: 2709, .NumOperands: 5, .NumConds: 6 },
2600 {.AsmStrOffset: 8281, .AliasCondStart: 2715, .NumOperands: 5, .NumConds: 6 },
2601 {.AsmStrOffset: 8299, .AliasCondStart: 2721, .NumOperands: 5, .NumConds: 6 },
2602 {.AsmStrOffset: 8316, .AliasCondStart: 2727, .NumOperands: 5, .NumConds: 6 },
2603 {.AsmStrOffset: 8334, .AliasCondStart: 2733, .NumOperands: 5, .NumConds: 6 },
2604 // SP::V9MOVFCCrr - 647
2605 {.AsmStrOffset: 8083, .AliasCondStart: 2739, .NumOperands: 5, .NumConds: 6 },
2606 {.AsmStrOffset: 8099, .AliasCondStart: 2745, .NumOperands: 5, .NumConds: 6 },
2607 {.AsmStrOffset: 8115, .AliasCondStart: 2751, .NumOperands: 5, .NumConds: 6 },
2608 {.AsmStrOffset: 8131, .AliasCondStart: 2757, .NumOperands: 5, .NumConds: 6 },
2609 {.AsmStrOffset: 8147, .AliasCondStart: 2763, .NumOperands: 5, .NumConds: 6 },
2610 {.AsmStrOffset: 8164, .AliasCondStart: 2769, .NumOperands: 5, .NumConds: 6 },
2611 {.AsmStrOffset: 8180, .AliasCondStart: 2775, .NumOperands: 5, .NumConds: 6 },
2612 {.AsmStrOffset: 8197, .AliasCondStart: 2781, .NumOperands: 5, .NumConds: 6 },
2613 {.AsmStrOffset: 8214, .AliasCondStart: 2787, .NumOperands: 5, .NumConds: 6 },
2614 {.AsmStrOffset: 8231, .AliasCondStart: 2793, .NumOperands: 5, .NumConds: 6 },
2615 {.AsmStrOffset: 8247, .AliasCondStart: 2799, .NumOperands: 5, .NumConds: 6 },
2616 {.AsmStrOffset: 8264, .AliasCondStart: 2805, .NumOperands: 5, .NumConds: 6 },
2617 {.AsmStrOffset: 8281, .AliasCondStart: 2811, .NumOperands: 5, .NumConds: 6 },
2618 {.AsmStrOffset: 8299, .AliasCondStart: 2817, .NumOperands: 5, .NumConds: 6 },
2619 {.AsmStrOffset: 8316, .AliasCondStart: 2823, .NumOperands: 5, .NumConds: 6 },
2620 {.AsmStrOffset: 8334, .AliasCondStart: 2829, .NumOperands: 5, .NumConds: 6 },
2621 // SP::WRASRri - 663
2622 {.AsmStrOffset: 8350, .AliasCondStart: 2835, .NumOperands: 3, .NumConds: 3 },
2623 // SP::WRASRrr - 664
2624 {.AsmStrOffset: 8350, .AliasCondStart: 2838, .NumOperands: 3, .NumConds: 4 },
2625 };
2626
2627 static const AliasPatternCond Conds[] = {
2628 // (BCOND brtarget:$imm, 8) - 0
2629 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2630 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2631 // (BCOND brtarget:$imm, 0) - 2
2632 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2633 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2634 // (BCOND brtarget:$imm, 9) - 4
2635 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2636 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2637 // (BCOND brtarget:$imm, 1) - 6
2638 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2639 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2640 // (BCOND brtarget:$imm, 10) - 8
2641 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2642 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2643 // (BCOND brtarget:$imm, 2) - 10
2644 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2645 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2646 // (BCOND brtarget:$imm, 11) - 12
2647 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2648 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2649 // (BCOND brtarget:$imm, 3) - 14
2650 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2651 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2652 // (BCOND brtarget:$imm, 12) - 16
2653 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2654 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2655 // (BCOND brtarget:$imm, 4) - 18
2656 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2657 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2658 // (BCOND brtarget:$imm, 13) - 20
2659 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2660 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2661 // (BCOND brtarget:$imm, 5) - 22
2662 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2663 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2664 // (BCOND brtarget:$imm, 14) - 24
2665 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2666 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2667 // (BCOND brtarget:$imm, 6) - 26
2668 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2669 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2670 // (BCOND brtarget:$imm, 15) - 28
2671 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2672 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2673 // (BCOND brtarget:$imm, 7) - 30
2674 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2675 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2676 // (BCONDA brtarget:$imm, 8) - 32
2677 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2678 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2679 // (BCONDA brtarget:$imm, 0) - 34
2680 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2681 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2682 // (BCONDA brtarget:$imm, 9) - 36
2683 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2684 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2685 // (BCONDA brtarget:$imm, 1) - 38
2686 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2687 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2688 // (BCONDA brtarget:$imm, 10) - 40
2689 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2690 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2691 // (BCONDA brtarget:$imm, 2) - 42
2692 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2693 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2694 // (BCONDA brtarget:$imm, 11) - 44
2695 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2696 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2697 // (BCONDA brtarget:$imm, 3) - 46
2698 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2699 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2700 // (BCONDA brtarget:$imm, 12) - 48
2701 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2702 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2703 // (BCONDA brtarget:$imm, 4) - 50
2704 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2705 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2706 // (BCONDA brtarget:$imm, 13) - 52
2707 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2708 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2709 // (BCONDA brtarget:$imm, 5) - 54
2710 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2711 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2712 // (BCONDA brtarget:$imm, 14) - 56
2713 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2714 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2715 // (BCONDA brtarget:$imm, 6) - 58
2716 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2717 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2718 // (BCONDA brtarget:$imm, 15) - 60
2719 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2720 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2721 // (BCONDA brtarget:$imm, 7) - 62
2722 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2723 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2724 // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
2725 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2726 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2727 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2728 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2729 // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
2730 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2731 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2732 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2733 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2734 // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
2735 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2736 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2738 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2739 // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
2740 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2741 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2742 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2743 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2744 // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
2745 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2746 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2747 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2748 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2749 // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
2750 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2751 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2752 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2753 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2754 // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
2755 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2756 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2757 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2758 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2759 // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
2760 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2761 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2762 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2763 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2764 // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
2765 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2766 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2767 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2768 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2769 // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
2770 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2771 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2772 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2773 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2774 // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
2775 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2776 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2777 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2778 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2779 // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
2780 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2781 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2782 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2783 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2784 // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
2785 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2786 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2788 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2789 // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
2790 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2791 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2792 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2793 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2794 // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
2795 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2796 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2797 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2798 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2799 // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
2800 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2801 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2802 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2803 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2804 // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
2805 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2806 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2807 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2808 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2809 // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
2810 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2811 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2813 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2814 // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
2815 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2816 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2817 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2818 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2819 // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
2820 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2821 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2822 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2823 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2824 // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
2825 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2826 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2828 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2829 // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
2830 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2831 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2833 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2834 // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
2835 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2836 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2837 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2838 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2839 // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
2840 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2841 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2842 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2843 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2844 // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
2845 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2846 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2847 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2848 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2849 // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
2850 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2851 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2853 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2854 // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
2855 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2857 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2858 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2859 // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
2860 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2861 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2862 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2863 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2864 // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
2865 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2866 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2867 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2868 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2869 // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
2870 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2871 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2873 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2874 // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
2875 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2876 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2877 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2878 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2879 // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
2880 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2881 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2882 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2883 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2884 // (BPICCANT brtarget:$imm, 8) - 192
2885 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2887 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2888 // (BPICCANT brtarget:$imm, 0) - 195
2889 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2890 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2891 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2892 // (BPICCANT brtarget:$imm, 9) - 198
2893 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2894 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2895 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2896 // (BPICCANT brtarget:$imm, 1) - 201
2897 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2898 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2899 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2900 // (BPICCANT brtarget:$imm, 10) - 204
2901 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2902 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2903 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2904 // (BPICCANT brtarget:$imm, 2) - 207
2905 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2906 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2907 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2908 // (BPICCANT brtarget:$imm, 11) - 210
2909 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2910 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2911 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2912 // (BPICCANT brtarget:$imm, 3) - 213
2913 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2914 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2915 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2916 // (BPICCANT brtarget:$imm, 12) - 216
2917 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2918 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2919 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2920 // (BPICCANT brtarget:$imm, 4) - 219
2921 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2922 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2923 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2924 // (BPICCANT brtarget:$imm, 13) - 222
2925 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2926 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2927 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2928 // (BPICCANT brtarget:$imm, 5) - 225
2929 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2930 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2931 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2932 // (BPICCANT brtarget:$imm, 14) - 228
2933 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2934 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2935 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2936 // (BPICCANT brtarget:$imm, 6) - 231
2937 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2938 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2939 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2940 // (BPICCANT brtarget:$imm, 15) - 234
2941 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2942 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2943 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2944 // (BPICCANT brtarget:$imm, 7) - 237
2945 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2946 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2947 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2948 // (BPICCNT brtarget:$imm, 8) - 240
2949 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2950 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2951 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2952 // (BPICCNT brtarget:$imm, 0) - 243
2953 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2954 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2955 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2956 // (BPICCNT brtarget:$imm, 9) - 246
2957 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2958 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2959 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2960 // (BPICCNT brtarget:$imm, 1) - 249
2961 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2962 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2963 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2964 // (BPICCNT brtarget:$imm, 10) - 252
2965 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2966 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2967 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2968 // (BPICCNT brtarget:$imm, 2) - 255
2969 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2970 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2971 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2972 // (BPICCNT brtarget:$imm, 11) - 258
2973 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2974 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2975 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2976 // (BPICCNT brtarget:$imm, 3) - 261
2977 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2978 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2979 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2980 // (BPICCNT brtarget:$imm, 12) - 264
2981 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2982 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2983 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2984 // (BPICCNT brtarget:$imm, 4) - 267
2985 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2986 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2987 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2988 // (BPICCNT brtarget:$imm, 13) - 270
2989 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2990 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2991 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2992 // (BPICCNT brtarget:$imm, 5) - 273
2993 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2994 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2995 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2996 // (BPICCNT brtarget:$imm, 14) - 276
2997 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2998 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2999 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3000 // (BPICCNT brtarget:$imm, 6) - 279
3001 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3002 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3003 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3004 // (BPICCNT brtarget:$imm, 15) - 282
3005 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3006 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3007 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3008 // (BPICCNT brtarget:$imm, 7) - 285
3009 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3010 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3011 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3012 // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 288
3013 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3014 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3015 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3016 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3017 // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 292
3018 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3019 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3020 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3021 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3022 // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 296
3023 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3024 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3025 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3026 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3027 // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 300
3028 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3029 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3030 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3031 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3032 // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 304
3033 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3034 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3035 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3036 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3037 // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 308
3038 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3039 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3040 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3041 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3042 // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 312
3043 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3044 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3045 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3046 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3047 // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 316
3048 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3049 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3050 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3051 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3052 // (BPXCCANT brtarget:$imm, 8) - 320
3053 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3054 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3055 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3056 // (BPXCCANT brtarget:$imm, 0) - 323
3057 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3058 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3059 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3060 // (BPXCCANT brtarget:$imm, 9) - 326
3061 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3062 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3063 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3064 // (BPXCCANT brtarget:$imm, 1) - 329
3065 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3066 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3067 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3068 // (BPXCCANT brtarget:$imm, 10) - 332
3069 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3070 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3071 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3072 // (BPXCCANT brtarget:$imm, 2) - 335
3073 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3074 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3075 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3076 // (BPXCCANT brtarget:$imm, 11) - 338
3077 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3078 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3079 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3080 // (BPXCCANT brtarget:$imm, 3) - 341
3081 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3082 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3083 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3084 // (BPXCCANT brtarget:$imm, 12) - 344
3085 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3086 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3087 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3088 // (BPXCCANT brtarget:$imm, 4) - 347
3089 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3090 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3091 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3092 // (BPXCCANT brtarget:$imm, 13) - 350
3093 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3094 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3095 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3096 // (BPXCCANT brtarget:$imm, 5) - 353
3097 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3098 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3099 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3100 // (BPXCCANT brtarget:$imm, 14) - 356
3101 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3102 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3103 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3104 // (BPXCCANT brtarget:$imm, 6) - 359
3105 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3106 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3107 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3108 // (BPXCCANT brtarget:$imm, 15) - 362
3109 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3110 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3111 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3112 // (BPXCCANT brtarget:$imm, 7) - 365
3113 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3114 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3115 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3116 // (BPXCCNT brtarget:$imm, 8) - 368
3117 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3118 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3119 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3120 // (BPXCCNT brtarget:$imm, 0) - 371
3121 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3122 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3123 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3124 // (BPXCCNT brtarget:$imm, 9) - 374
3125 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3126 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3127 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3128 // (BPXCCNT brtarget:$imm, 1) - 377
3129 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3130 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3131 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3132 // (BPXCCNT brtarget:$imm, 10) - 380
3133 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3134 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3135 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3136 // (BPXCCNT brtarget:$imm, 2) - 383
3137 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3138 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3139 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3140 // (BPXCCNT brtarget:$imm, 11) - 386
3141 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3142 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3143 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3144 // (BPXCCNT brtarget:$imm, 3) - 389
3145 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3146 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3147 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3148 // (BPXCCNT brtarget:$imm, 12) - 392
3149 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3150 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3152 // (BPXCCNT brtarget:$imm, 4) - 395
3153 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3154 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3155 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3156 // (BPXCCNT brtarget:$imm, 13) - 398
3157 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3158 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3159 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3160 // (BPXCCNT brtarget:$imm, 5) - 401
3161 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3162 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3163 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3164 // (BPXCCNT brtarget:$imm, 14) - 404
3165 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3166 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3167 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3168 // (BPXCCNT brtarget:$imm, 6) - 407
3169 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3170 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3171 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3172 // (BPXCCNT brtarget:$imm, 15) - 410
3173 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3174 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3175 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3176 // (BPXCCNT brtarget:$imm, 7) - 413
3177 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3178 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3179 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3180 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 416
3181 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3182 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3183 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3184 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3185 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3186 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3187 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 422
3188 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3189 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3190 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3191 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3192 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3193 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3194 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 428
3195 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3196 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3197 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3198 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3199 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
3200 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3201 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 434
3202 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3203 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3204 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3205 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3206 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
3207 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3208 // (CWBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 440
3209 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3210 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3211 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3212 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3213 // (CWBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 444
3214 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3215 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3216 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3217 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3218 // (CWBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 448
3219 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3220 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3221 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3222 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3223 // (CWBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 452
3224 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3225 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3226 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3227 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3228 // (CWBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 456
3229 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3230 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3231 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3232 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3233 // (CWBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 460
3234 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3235 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3236 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3237 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3238 // (CWBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 464
3239 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3240 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3241 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3242 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3243 // (CWBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 468
3244 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3245 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3246 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3247 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3248 // (CWBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 472
3249 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3250 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3251 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3252 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3253 // (CWBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 476
3254 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3255 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3256 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3257 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3258 // (CWBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 480
3259 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3260 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3261 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3262 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3263 // (CWBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 484
3264 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3265 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3266 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3267 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3268 // (CWBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 488
3269 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3270 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3271 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3272 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3273 // (CWBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 492
3274 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3275 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3276 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3277 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3278 // (CWBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 496
3279 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3280 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3281 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3282 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3283 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3284 // (CWBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 501
3285 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3286 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3287 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3288 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3289 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3290 // (CWBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 506
3291 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3292 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3293 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3294 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3295 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3296 // (CWBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 511
3297 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3298 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3299 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3300 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3301 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3302 // (CWBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 516
3303 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3304 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3305 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3306 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3307 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3308 // (CWBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 521
3309 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3310 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3311 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3312 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3313 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3314 // (CWBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 526
3315 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3316 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3317 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3318 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3319 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3320 // (CWBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 531
3321 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3322 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3323 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3324 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3325 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3326 // (CWBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 536
3327 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3328 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3329 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3330 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3331 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3332 // (CWBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 541
3333 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3334 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3335 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3336 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3337 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3338 // (CWBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 546
3339 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3340 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3341 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3342 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3343 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3344 // (CWBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 551
3345 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3346 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3347 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3348 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3349 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3350 // (CWBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 556
3351 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3352 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3353 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3354 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3355 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3356 // (CWBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 561
3357 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3358 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3359 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3360 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3361 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3362 // (CXBCONDri cbtarget:$imm, 9, IntRegs:$rs1, simm5Op:$simm5) - 566
3363 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3364 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3365 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3366 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3367 // (CXBCONDri cbtarget:$imm, 1, IntRegs:$rs1, simm5Op:$simm5) - 570
3368 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3369 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3370 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3371 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3372 // (CXBCONDri cbtarget:$imm, 10, IntRegs:$rs1, simm5Op:$simm5) - 574
3373 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3374 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3375 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3376 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3377 // (CXBCONDri cbtarget:$imm, 2, IntRegs:$rs1, simm5Op:$simm5) - 578
3378 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3379 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3380 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3381 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3382 // (CXBCONDri cbtarget:$imm, 11, IntRegs:$rs1, simm5Op:$simm5) - 582
3383 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3384 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3385 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3386 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3387 // (CXBCONDri cbtarget:$imm, 3, IntRegs:$rs1, simm5Op:$simm5) - 586
3388 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3389 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3390 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3391 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3392 // (CXBCONDri cbtarget:$imm, 12, IntRegs:$rs1, simm5Op:$simm5) - 590
3393 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3394 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3395 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3396 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3397 // (CXBCONDri cbtarget:$imm, 4, IntRegs:$rs1, simm5Op:$simm5) - 594
3398 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3399 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3400 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3401 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3402 // (CXBCONDri cbtarget:$imm, 13, IntRegs:$rs1, simm5Op:$simm5) - 598
3403 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3404 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3405 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3406 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3407 // (CXBCONDri cbtarget:$imm, 5, IntRegs:$rs1, simm5Op:$simm5) - 602
3408 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3409 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3410 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3411 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3412 // (CXBCONDri cbtarget:$imm, 14, IntRegs:$rs1, simm5Op:$simm5) - 606
3413 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3414 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3415 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3416 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3417 // (CXBCONDri cbtarget:$imm, 6, IntRegs:$rs1, simm5Op:$simm5) - 610
3418 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3419 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3420 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3421 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3422 // (CXBCONDri cbtarget:$imm, 15, IntRegs:$rs1, simm5Op:$simm5) - 614
3423 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3424 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3425 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3426 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3427 // (CXBCONDri cbtarget:$imm, 7, IntRegs:$rs1, simm5Op:$simm5) - 618
3428 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3429 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3430 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3431 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3432 // (CXBCONDrr cbtarget:$imm, 9, IntRegs:$rs1, IntRegs:$rs2) - 622
3433 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3434 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3435 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3436 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3437 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3438 // (CXBCONDrr cbtarget:$imm, 1, IntRegs:$rs1, IntRegs:$rs2) - 627
3439 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3440 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3441 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3442 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3443 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3444 // (CXBCONDrr cbtarget:$imm, 10, IntRegs:$rs1, IntRegs:$rs2) - 632
3445 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3446 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3447 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3448 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3449 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3450 // (CXBCONDrr cbtarget:$imm, 2, IntRegs:$rs1, IntRegs:$rs2) - 637
3451 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3452 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3453 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3454 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3455 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3456 // (CXBCONDrr cbtarget:$imm, 11, IntRegs:$rs1, IntRegs:$rs2) - 642
3457 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3458 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3459 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3460 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3461 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3462 // (CXBCONDrr cbtarget:$imm, 3, IntRegs:$rs1, IntRegs:$rs2) - 647
3463 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3464 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3465 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3466 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3467 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3468 // (CXBCONDrr cbtarget:$imm, 12, IntRegs:$rs1, IntRegs:$rs2) - 652
3469 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3470 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3471 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3472 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3473 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3474 // (CXBCONDrr cbtarget:$imm, 4, IntRegs:$rs1, IntRegs:$rs2) - 657
3475 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3476 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3477 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3478 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3479 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3480 // (CXBCONDrr cbtarget:$imm, 13, IntRegs:$rs1, IntRegs:$rs2) - 662
3481 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3482 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3483 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3484 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3485 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3486 // (CXBCONDrr cbtarget:$imm, 5, IntRegs:$rs1, IntRegs:$rs2) - 667
3487 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3488 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3490 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3491 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3492 // (CXBCONDrr cbtarget:$imm, 14, IntRegs:$rs1, IntRegs:$rs2) - 672
3493 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3494 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3496 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3497 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3498 // (CXBCONDrr cbtarget:$imm, 6, IntRegs:$rs1, IntRegs:$rs2) - 677
3499 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3500 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3502 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3503 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3504 // (CXBCONDrr cbtarget:$imm, 15, IntRegs:$rs1, IntRegs:$rs2) - 682
3505 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3506 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3507 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3508 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3509 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3510 // (CXBCONDrr cbtarget:$imm, 7, IntRegs:$rs1, IntRegs:$rs2) - 687
3511 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3512 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3513 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3514 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3515 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
3516 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 692
3517 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3519 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3520 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3521 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3522 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 697
3523 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3524 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3525 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3526 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3527 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3528 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 702
3529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3530 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3531 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3532 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3533 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3534 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 707
3535 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3536 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3537 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3538 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3539 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3540 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 712
3541 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3542 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3543 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3544 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3545 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3546 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 717
3547 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3548 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3549 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3550 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3551 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3552 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 722
3553 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3554 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3555 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3556 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3557 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3558 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 727
3559 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3561 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3562 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3563 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3564 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 732
3565 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3566 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3567 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3568 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3569 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3570 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 737
3571 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3572 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3573 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3574 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3575 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3576 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 742
3577 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3578 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3579 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3580 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3581 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3582 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 747
3583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3585 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3586 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3587 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3588 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 752
3589 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3590 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3591 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3592 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3593 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3594 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 757
3595 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3596 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3597 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3598 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3599 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3600 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 762
3601 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3602 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3603 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3604 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3605 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3606 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 767
3607 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3608 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3609 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3610 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3611 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3612 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) - 772
3613 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3614 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3615 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3616 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3617 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3618 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) - 777
3619 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3620 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3621 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3622 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3623 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3624 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) - 782
3625 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3626 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3627 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3628 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3629 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3630 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) - 787
3631 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3632 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3633 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3634 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3635 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3636 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) - 792
3637 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3638 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3639 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3640 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3641 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3642 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) - 797
3643 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3644 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3645 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3646 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3647 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3648 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) - 802
3649 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3650 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3651 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3652 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3653 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3654 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) - 807
3655 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3656 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3657 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3658 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3659 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3660 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) - 812
3661 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3662 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3663 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3664 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3665 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3666 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) - 817
3667 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3668 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3669 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3670 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3671 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3672 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) - 822
3673 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3674 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3675 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3676 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3677 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3678 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) - 827
3679 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3680 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3681 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3682 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3683 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3684 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) - 832
3685 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3686 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3687 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3688 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3689 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3690 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) - 837
3691 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3692 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3693 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3694 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3695 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3696 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) - 842
3697 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3698 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3699 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3700 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3701 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3702 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) - 847
3703 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3704 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3705 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3706 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3707 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3708 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 852
3709 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3710 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3711 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3712 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3713 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3714 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 857
3715 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3716 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3717 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3718 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3719 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3720 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 862
3721 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3722 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3723 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3724 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3725 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3726 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 867
3727 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3728 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3729 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3730 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3731 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3732 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 872
3733 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3734 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3735 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3736 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3737 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3738 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 877
3739 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3740 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3741 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3742 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3743 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3744 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 882
3745 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3746 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3747 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3748 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3749 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3750 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 887
3751 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3752 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3753 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3754 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3755 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3756 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 892
3757 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3758 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3759 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3760 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3761 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3762 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 897
3763 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3764 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3765 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3766 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3767 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3768 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 902
3769 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3770 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3771 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3772 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3773 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3774 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 907
3775 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3776 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3777 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3778 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3779 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3780 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 912
3781 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3782 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3783 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3784 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3785 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3786 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 917
3787 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3788 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3789 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3790 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3791 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3792 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 922
3793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3794 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3795 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3796 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3797 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3798 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 927
3799 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3801 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3802 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3803 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3804 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) - 932
3805 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3806 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3807 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3808 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3809 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3810 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) - 937
3811 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3813 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3814 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3815 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3816 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) - 942
3817 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3818 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3819 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3820 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3821 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3822 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) - 947
3823 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3824 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3825 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3826 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3827 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3828 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) - 952
3829 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3830 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3831 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3832 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3833 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3834 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) - 957
3835 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3836 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3837 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3838 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3839 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3840 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) - 962
3841 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3842 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3843 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3844 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3845 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3846 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) - 967
3847 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3849 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3850 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3851 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3852 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) - 972
3853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3854 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3855 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3857 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3858 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) - 977
3859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3860 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3861 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3862 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3863 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3864 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) - 982
3865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3866 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3867 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3868 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3869 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3870 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) - 987
3871 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3873 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3874 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3875 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3876 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) - 992
3877 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3878 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3879 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3880 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3881 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3882 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) - 997
3883 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3884 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3885 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3887 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3888 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) - 1002
3889 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3890 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3891 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3892 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3893 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3894 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) - 1007
3895 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3896 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3897 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3898 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3899 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3900 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 1012
3901 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3902 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3904 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3905 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3906 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3907 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 1018
3908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3909 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3910 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3911 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3912 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3913 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3914 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 1024
3915 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3916 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3917 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3918 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3919 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3920 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3921 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 1030
3922 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3924 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3925 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3926 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3927 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3928 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 1036
3929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3930 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3931 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3932 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3933 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3934 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3935 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 1042
3936 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3937 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3939 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3940 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3941 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3942 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 1048
3943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3944 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3945 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3946 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3947 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3948 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3949 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 1054
3950 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3951 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3952 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3953 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3954 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3955 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3956 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 1060
3957 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3958 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3959 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3960 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3961 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3962 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3963 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 1066
3964 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3965 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3966 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3967 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3968 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3969 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3970 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 1072
3971 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3972 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3973 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3974 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3975 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3976 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3977 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 1078
3978 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3979 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3980 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3981 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3982 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3983 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3984 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 1084
3985 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3986 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3987 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3988 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3989 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3990 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 1089
3991 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3992 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3993 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3994 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3995 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3996 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 1094
3997 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3998 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3999 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4000 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4001 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4002 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 1099
4003 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4004 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4005 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4006 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4007 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4008 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 1104
4009 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4010 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4011 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4012 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4013 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4014 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 1109
4015 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4016 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4017 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4018 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4019 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4020 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 1114
4021 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4022 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4023 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4024 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4025 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4026 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 1119
4027 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4028 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4029 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4030 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4031 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4032 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 1124
4033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4034 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4035 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4036 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4037 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4038 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 1129
4039 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4040 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4041 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4042 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4043 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4044 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 1134
4045 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4046 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4047 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4048 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4049 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4050 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 1139
4051 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4052 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4053 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4054 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4055 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4056 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 1144
4057 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4058 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4059 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4060 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4061 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4062 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 1149
4063 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4064 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4065 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4066 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4067 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4068 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 1154
4069 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4070 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4071 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4072 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4073 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4074 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 1159
4075 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4076 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4077 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4078 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4079 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4080 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) - 1164
4081 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4082 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4083 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4084 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4085 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4086 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) - 1169
4087 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4088 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4089 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4090 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4091 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4092 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) - 1174
4093 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4094 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4095 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4096 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4097 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4098 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) - 1179
4099 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4100 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4101 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4102 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4103 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4104 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) - 1184
4105 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4106 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4107 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4108 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4109 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4110 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) - 1189
4111 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4112 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4113 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4114 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4115 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4116 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) - 1194
4117 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4118 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4119 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4120 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4121 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4122 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) - 1199
4123 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4124 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4125 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4126 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4127 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4128 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) - 1204
4129 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4130 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4131 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4132 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4133 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4134 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) - 1209
4135 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4136 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4137 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4138 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4139 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4140 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) - 1214
4141 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4142 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4143 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4144 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4145 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4146 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) - 1219
4147 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4148 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4149 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4150 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4152 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) - 1224
4153 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4154 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4155 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4156 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4157 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4158 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) - 1229
4159 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4160 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4161 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4162 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4163 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4164 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) - 1234
4165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4166 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4167 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4168 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4169 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4170 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) - 1239
4171 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4172 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4173 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4174 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4175 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4176 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1244
4177 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4178 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4179 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4180 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4181 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4182 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1249
4183 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4184 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4185 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4186 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4187 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4188 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1254
4189 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4190 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4191 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4192 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4193 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4194 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1259
4195 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4196 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4197 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4198 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4199 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4200 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1264
4201 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4202 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4203 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4204 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4205 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4206 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1269
4207 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4208 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4209 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4210 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4211 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4212 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1274
4213 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4214 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4215 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4216 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4217 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4218 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1279
4219 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4220 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4221 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4222 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4223 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4224 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1284
4225 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4226 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4227 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4228 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4229 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4230 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1289
4231 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4232 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4233 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4234 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4235 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4236 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1294
4237 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4238 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4239 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4240 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4241 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4242 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1299
4243 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4244 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4245 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4246 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4247 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4248 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1304
4249 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4250 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4251 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4252 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4253 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4254 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1309
4255 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4256 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4257 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4258 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4259 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4260 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1314
4261 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4262 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4263 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4264 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4265 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4266 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1319
4267 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4268 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4269 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4270 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4271 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4272 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1324
4273 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4274 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4275 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4276 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4277 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4278 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1329
4279 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4280 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4281 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4282 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4283 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4284 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1334
4285 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4286 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4287 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4288 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4289 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4290 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1339
4291 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4292 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4293 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4294 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4295 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4296 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1344
4297 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4298 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4299 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4300 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4301 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4302 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1349
4303 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4304 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4305 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4306 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4307 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4308 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1354
4309 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4310 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4311 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4312 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4313 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4314 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1359
4315 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4316 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4317 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4318 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4319 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4320 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1364
4321 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4322 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4323 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4324 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4325 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4326 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1369
4327 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4328 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4329 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4330 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4331 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4332 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1374
4333 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4334 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4335 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4336 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4337 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4338 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1379
4339 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4340 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4341 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4342 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4343 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4344 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1384
4345 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4346 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4347 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4348 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4349 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4350 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1389
4351 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4352 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4353 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4354 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4355 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4356 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1394
4357 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4358 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4359 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4360 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4361 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4362 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1399
4363 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4364 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4365 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4366 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4367 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4368 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1404
4369 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4370 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4371 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4372 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4373 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4374 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4375 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1410
4376 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4377 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4378 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4379 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4380 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4381 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4382 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1416
4383 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4384 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4385 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4386 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4387 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4388 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4389 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1422
4390 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4391 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4392 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4393 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4394 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4395 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4396 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1428
4397 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4398 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4399 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4400 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4401 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4402 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4403 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1434
4404 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4405 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4406 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4407 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4408 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4409 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4410 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1440
4411 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4413 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4414 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4415 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4416 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4417 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1446
4418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4419 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
4420 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4421 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4422 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4423 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4424 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) - 1452
4425 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4426 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4427 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4428 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4429 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4430 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) - 1457
4431 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4432 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4433 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4434 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4435 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4436 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) - 1462
4437 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4438 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4439 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4440 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4441 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4442 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) - 1467
4443 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4444 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4445 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4446 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4447 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4448 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) - 1472
4449 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4450 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4451 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4452 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4453 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4454 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) - 1477
4455 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4456 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4457 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4458 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4459 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4460 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) - 1482
4461 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4462 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4463 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4464 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4465 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4466 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) - 1487
4467 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4468 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4469 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4470 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4471 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4472 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) - 1492
4473 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4474 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4475 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4476 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4477 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4478 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) - 1497
4479 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4480 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4481 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4482 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4483 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4484 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) - 1502
4485 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4486 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4487 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4488 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4489 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4490 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) - 1507
4491 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4492 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4493 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4494 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4495 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4496 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) - 1512
4497 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4498 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4499 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4500 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4501 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4502 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) - 1517
4503 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4504 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4505 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4506 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4507 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4508 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) - 1522
4509 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4510 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4511 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4512 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4513 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4514 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) - 1527
4515 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4516 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4517 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4518 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4519 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4520 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1532
4521 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4522 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4523 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4524 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4525 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4526 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1537
4527 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4529 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4530 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4531 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4532 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1542
4533 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4534 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4535 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4536 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4537 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4538 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1547
4539 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4540 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4541 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4542 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4543 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4544 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1552
4545 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4546 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4547 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4548 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4549 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4550 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1557
4551 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4552 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4553 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4554 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4555 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4556 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1562
4557 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4558 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4559 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4560 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4561 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4562 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1567
4563 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4564 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4565 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4566 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4567 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4568 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1572
4569 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4570 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4571 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4572 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4573 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4574 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1577
4575 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4576 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4577 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4578 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4579 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4580 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1582
4581 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4582 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4583 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4584 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4585 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4586 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1587
4587 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4588 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4589 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4590 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4591 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4592 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1592
4593 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4594 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4595 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4596 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4597 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4598 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1597
4599 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4600 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4601 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4602 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4603 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4604 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1602
4605 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4606 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4607 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4608 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4609 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4610 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1607
4611 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4612 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4613 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4614 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4615 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4616 // (ORCCrr G0, IntRegs:$rs2, G0) - 1612
4617 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4618 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4619 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4620 // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1615
4621 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4622 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4623 // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1617
4624 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4625 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4626 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4627 // (RESTORErr G0, G0, G0) - 1620
4628 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4629 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4630 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4631 // (RET 8) - 1623
4632 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4633 // (RETL 8) - 1624
4634 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4635 // (SAVErr G0, G0, G0) - 1625
4636 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4637 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4638 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4639 // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1628
4640 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4641 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4642 // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1630
4643 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4644 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4645 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4646 // (TICCri G0, i32imm:$imm, 8) - 1633
4647 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4648 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4649 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4650 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4651 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1637
4652 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4653 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4654 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4655 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4656 // (TICCri G0, i32imm:$imm, 0) - 1641
4657 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4658 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4659 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4660 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4661 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1645
4662 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4663 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4664 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4665 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4666 // (TICCri G0, i32imm:$imm, 9) - 1649
4667 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4668 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4669 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4670 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4671 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1653
4672 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4673 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4674 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4675 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4676 // (TICCri G0, i32imm:$imm, 1) - 1657
4677 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4678 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4679 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4680 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4681 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1661
4682 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4683 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4684 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4685 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4686 // (TICCri G0, i32imm:$imm, 10) - 1665
4687 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4688 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4689 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4690 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4691 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1669
4692 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4693 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4694 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4695 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4696 // (TICCri G0, i32imm:$imm, 2) - 1673
4697 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4698 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4699 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4700 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4701 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1677
4702 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4703 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4704 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4705 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4706 // (TICCri G0, i32imm:$imm, 11) - 1681
4707 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4708 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4709 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4710 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4711 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1685
4712 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4713 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4714 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4715 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4716 // (TICCri G0, i32imm:$imm, 3) - 1689
4717 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4718 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4719 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4720 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4721 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1693
4722 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4723 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4724 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4725 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4726 // (TICCri G0, i32imm:$imm, 12) - 1697
4727 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4728 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4729 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4730 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4731 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1701
4732 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4733 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4734 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4735 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4736 // (TICCri G0, i32imm:$imm, 4) - 1705
4737 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4738 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4739 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4740 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4741 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1709
4742 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4743 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4744 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4745 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4746 // (TICCri G0, i32imm:$imm, 13) - 1713
4747 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4748 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4749 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4750 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4751 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1717
4752 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4753 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4754 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4755 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4756 // (TICCri G0, i32imm:$imm, 5) - 1721
4757 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4758 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4759 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4760 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4761 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1725
4762 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4763 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4764 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4765 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4766 // (TICCri G0, i32imm:$imm, 14) - 1729
4767 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4768 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4769 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4770 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4771 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1733
4772 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4773 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4774 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4775 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4776 // (TICCri G0, i32imm:$imm, 6) - 1737
4777 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4778 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4779 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4780 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4781 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1741
4782 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4783 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4784 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4785 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4786 // (TICCri G0, i32imm:$imm, 15) - 1745
4787 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4788 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4789 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4790 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4791 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 1749
4792 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4793 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4794 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4795 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4796 // (TICCri G0, i32imm:$imm, 7) - 1753
4797 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4798 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4799 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4800 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4801 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 1757
4802 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4803 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4804 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4805 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4806 // (TICCrr G0, IntRegs:$rs2, 8) - 1761
4807 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4809 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4810 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4811 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1765
4812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4813 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4814 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4815 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4816 // (TICCrr G0, IntRegs:$rs2, 0) - 1769
4817 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4818 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4819 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4820 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4821 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1773
4822 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4823 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4824 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4825 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4826 // (TICCrr G0, IntRegs:$rs2, 9) - 1777
4827 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4829 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4830 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4831 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1781
4832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4834 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4835 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4836 // (TICCrr G0, IntRegs:$rs2, 1) - 1785
4837 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4838 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4839 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4840 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4841 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1789
4842 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4843 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4844 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4845 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4846 // (TICCrr G0, IntRegs:$rs2, 10) - 1793
4847 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4849 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4850 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4851 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1797
4852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4854 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4855 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4856 // (TICCrr G0, IntRegs:$rs2, 2) - 1801
4857 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4858 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4859 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4860 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4861 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1805
4862 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4863 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4864 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4865 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4866 // (TICCrr G0, IntRegs:$rs2, 11) - 1809
4867 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4868 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4869 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4870 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4871 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1813
4872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4874 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4875 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4876 // (TICCrr G0, IntRegs:$rs2, 3) - 1817
4877 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4878 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4879 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4880 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4881 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1821
4882 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4883 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4884 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4885 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4886 // (TICCrr G0, IntRegs:$rs2, 12) - 1825
4887 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4888 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4889 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4890 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4891 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1829
4892 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4893 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4894 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4895 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4896 // (TICCrr G0, IntRegs:$rs2, 4) - 1833
4897 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4898 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4899 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4900 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4901 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1837
4902 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4904 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4905 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4906 // (TICCrr G0, IntRegs:$rs2, 13) - 1841
4907 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4909 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4910 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4911 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1845
4912 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4913 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4914 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4915 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4916 // (TICCrr G0, IntRegs:$rs2, 5) - 1849
4917 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4918 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4919 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4920 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4921 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1853
4922 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4924 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4925 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4926 // (TICCrr G0, IntRegs:$rs2, 14) - 1857
4927 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4928 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4929 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4930 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4931 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1861
4932 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4933 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4934 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4935 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4936 // (TICCrr G0, IntRegs:$rs2, 6) - 1865
4937 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4939 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4940 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4941 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1869
4942 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4944 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4945 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4946 // (TICCrr G0, IntRegs:$rs2, 15) - 1873
4947 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4949 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4950 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4951 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1877
4952 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4953 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4954 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4955 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4956 // (TICCrr G0, IntRegs:$rs2, 7) - 1881
4957 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4958 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4959 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4960 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4961 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1885
4962 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4964 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4965 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4966 // (TRAPri G0, i32imm:$imm, 8) - 1889
4967 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4968 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4969 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4970 // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 1892
4971 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4972 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4973 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4974 // (TRAPri G0, i32imm:$imm, 0) - 1895
4975 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4976 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4977 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4978 // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 1898
4979 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4980 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4981 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4982 // (TRAPri G0, i32imm:$imm, 9) - 1901
4983 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4984 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4985 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4986 // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 1904
4987 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4988 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4989 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4990 // (TRAPri G0, i32imm:$imm, 1) - 1907
4991 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4992 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4993 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4994 // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 1910
4995 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4996 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4997 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4998 // (TRAPri G0, i32imm:$imm, 10) - 1913
4999 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5000 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5001 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5002 // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 1916
5003 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5004 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5005 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5006 // (TRAPri G0, i32imm:$imm, 2) - 1919
5007 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5008 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5009 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5010 // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 1922
5011 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5012 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5013 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5014 // (TRAPri G0, i32imm:$imm, 11) - 1925
5015 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5016 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5017 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5018 // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 1928
5019 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5020 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5021 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5022 // (TRAPri G0, i32imm:$imm, 3) - 1931
5023 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5024 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5025 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5026 // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 1934
5027 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5028 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5029 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5030 // (TRAPri G0, i32imm:$imm, 12) - 1937
5031 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5032 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5033 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5034 // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 1940
5035 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5036 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5037 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5038 // (TRAPri G0, i32imm:$imm, 4) - 1943
5039 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5040 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5041 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5042 // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 1946
5043 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5044 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5045 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5046 // (TRAPri G0, i32imm:$imm, 13) - 1949
5047 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5048 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5049 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5050 // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 1952
5051 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5052 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5053 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5054 // (TRAPri G0, i32imm:$imm, 5) - 1955
5055 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5056 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5057 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5058 // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 1958
5059 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5060 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5061 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5062 // (TRAPri G0, i32imm:$imm, 14) - 1961
5063 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5064 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5065 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5066 // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 1964
5067 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5068 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5069 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5070 // (TRAPri G0, i32imm:$imm, 6) - 1967
5071 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5072 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5073 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5074 // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 1970
5075 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5076 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5077 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5078 // (TRAPri G0, i32imm:$imm, 15) - 1973
5079 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5080 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5081 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5082 // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 1976
5083 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5084 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5085 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5086 // (TRAPri G0, i32imm:$imm, 7) - 1979
5087 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5088 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5089 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5090 // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 1982
5091 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5092 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5093 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5094 // (TRAPrr G0, IntRegs:$rs1, 8) - 1985
5095 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5096 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5097 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5098 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1988
5099 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5100 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5101 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5102 // (TRAPrr G0, IntRegs:$rs1, 0) - 1991
5103 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5104 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5105 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5106 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1994
5107 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5108 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5109 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5110 // (TRAPrr G0, IntRegs:$rs1, 9) - 1997
5111 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5112 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5113 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5114 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2000
5115 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5116 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5117 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5118 // (TRAPrr G0, IntRegs:$rs1, 1) - 2003
5119 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5120 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5121 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5122 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2006
5123 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5124 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5125 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5126 // (TRAPrr G0, IntRegs:$rs1, 10) - 2009
5127 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5128 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5129 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5130 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2012
5131 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5132 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5133 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5134 // (TRAPrr G0, IntRegs:$rs1, 2) - 2015
5135 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5136 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5137 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5138 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2018
5139 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5140 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5141 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5142 // (TRAPrr G0, IntRegs:$rs1, 11) - 2021
5143 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5144 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5145 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5146 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2024
5147 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5148 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5149 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5150 // (TRAPrr G0, IntRegs:$rs1, 3) - 2027
5151 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5152 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5153 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5154 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2030
5155 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5156 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5157 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5158 // (TRAPrr G0, IntRegs:$rs1, 12) - 2033
5159 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5160 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5161 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5162 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2036
5163 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5164 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5165 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5166 // (TRAPrr G0, IntRegs:$rs1, 4) - 2039
5167 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5168 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5169 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5170 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2042
5171 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5172 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5173 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5174 // (TRAPrr G0, IntRegs:$rs1, 13) - 2045
5175 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5176 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5177 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5178 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2048
5179 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5180 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5181 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5182 // (TRAPrr G0, IntRegs:$rs1, 5) - 2051
5183 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5184 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5185 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5186 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2054
5187 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5188 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5189 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5190 // (TRAPrr G0, IntRegs:$rs1, 14) - 2057
5191 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5192 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5193 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5194 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2060
5195 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5196 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5197 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5198 // (TRAPrr G0, IntRegs:$rs1, 6) - 2063
5199 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5200 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5201 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5202 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2066
5203 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5204 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5205 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5206 // (TRAPrr G0, IntRegs:$rs1, 15) - 2069
5207 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5208 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5209 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5210 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2072
5211 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5212 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5213 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5214 // (TRAPrr G0, IntRegs:$rs1, 7) - 2075
5215 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5216 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5217 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5218 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2078
5219 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5220 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5221 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5222 // (TXCCri G0, i32imm:$imm, 8) - 2081
5223 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5224 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5225 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5226 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5227 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 2085
5228 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5229 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5230 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5231 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5232 // (TXCCri G0, i32imm:$imm, 0) - 2089
5233 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5234 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5235 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5236 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5237 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 2093
5238 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5239 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5240 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5241 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5242 // (TXCCri G0, i32imm:$imm, 9) - 2097
5243 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5244 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5245 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5246 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5247 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 2101
5248 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5249 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5250 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5251 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5252 // (TXCCri G0, i32imm:$imm, 1) - 2105
5253 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5254 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5255 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5256 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5257 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 2109
5258 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5259 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5260 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5261 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5262 // (TXCCri G0, i32imm:$imm, 10) - 2113
5263 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5264 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5265 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5266 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5267 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 2117
5268 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5269 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5270 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5271 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5272 // (TXCCri G0, i32imm:$imm, 2) - 2121
5273 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5274 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5275 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5276 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5277 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 2125
5278 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5279 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5280 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5281 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5282 // (TXCCri G0, i32imm:$imm, 11) - 2129
5283 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5284 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5285 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5286 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5287 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 2133
5288 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5289 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5290 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5291 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5292 // (TXCCri G0, i32imm:$imm, 3) - 2137
5293 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5294 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5295 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5296 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5297 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 2141
5298 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5299 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5300 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5301 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5302 // (TXCCri G0, i32imm:$imm, 12) - 2145
5303 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5304 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5305 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5306 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5307 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 2149
5308 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5309 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5310 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5311 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5312 // (TXCCri G0, i32imm:$imm, 4) - 2153
5313 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5314 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5315 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5316 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5317 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 2157
5318 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5319 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5320 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5321 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5322 // (TXCCri G0, i32imm:$imm, 13) - 2161
5323 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5324 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5325 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5326 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5327 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 2165
5328 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5329 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5330 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5331 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5332 // (TXCCri G0, i32imm:$imm, 5) - 2169
5333 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5334 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5335 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5336 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5337 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 2173
5338 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5339 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5340 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5341 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5342 // (TXCCri G0, i32imm:$imm, 14) - 2177
5343 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5344 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5345 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5346 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5347 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2181
5348 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5349 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5350 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5351 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5352 // (TXCCri G0, i32imm:$imm, 6) - 2185
5353 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5354 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5355 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5356 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5357 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2189
5358 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5359 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5360 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5361 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5362 // (TXCCri G0, i32imm:$imm, 15) - 2193
5363 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5364 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5365 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5366 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5367 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2197
5368 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5369 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5370 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5371 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5372 // (TXCCri G0, i32imm:$imm, 7) - 2201
5373 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5374 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5375 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5376 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5377 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2205
5378 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5379 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5380 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5381 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5382 // (TXCCrr G0, IntRegs:$rs2, 8) - 2209
5383 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5384 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5385 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5386 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5387 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2213
5388 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5389 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5390 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5391 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5392 // (TXCCrr G0, IntRegs:$rs2, 0) - 2217
5393 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5394 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5395 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5396 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5397 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2221
5398 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5399 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5400 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5401 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5402 // (TXCCrr G0, IntRegs:$rs2, 9) - 2225
5403 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5404 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5405 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5406 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5407 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2229
5408 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5409 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5410 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5411 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5412 // (TXCCrr G0, IntRegs:$rs2, 1) - 2233
5413 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5414 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5415 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5416 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5417 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2237
5418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5419 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5420 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5421 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5422 // (TXCCrr G0, IntRegs:$rs2, 10) - 2241
5423 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5424 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5425 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5426 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5427 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2245
5428 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5430 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5431 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5432 // (TXCCrr G0, IntRegs:$rs2, 2) - 2249
5433 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5434 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5435 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5436 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5437 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2253
5438 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5439 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5440 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5441 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5442 // (TXCCrr G0, IntRegs:$rs2, 11) - 2257
5443 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5444 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5445 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5446 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5447 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2261
5448 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5449 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5450 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5451 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5452 // (TXCCrr G0, IntRegs:$rs2, 3) - 2265
5453 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5454 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5455 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5456 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5457 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2269
5458 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5459 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5460 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5461 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5462 // (TXCCrr G0, IntRegs:$rs2, 12) - 2273
5463 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5464 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5465 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5466 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5467 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2277
5468 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5469 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5470 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5471 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5472 // (TXCCrr G0, IntRegs:$rs2, 4) - 2281
5473 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5474 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5475 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5476 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5477 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2285
5478 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5479 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5480 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5481 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5482 // (TXCCrr G0, IntRegs:$rs2, 13) - 2289
5483 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5484 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5485 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5486 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5487 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2293
5488 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5490 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5491 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5492 // (TXCCrr G0, IntRegs:$rs2, 5) - 2297
5493 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5494 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5495 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5496 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5497 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2301
5498 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5499 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5500 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5501 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5502 // (TXCCrr G0, IntRegs:$rs2, 14) - 2305
5503 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5504 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5505 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5506 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5507 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2309
5508 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5509 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5510 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5511 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5512 // (TXCCrr G0, IntRegs:$rs2, 6) - 2313
5513 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5514 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5515 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5516 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5517 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2317
5518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5519 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5520 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5521 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5522 // (TXCCrr G0, IntRegs:$rs2, 15) - 2321
5523 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5524 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5525 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5526 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5527 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2325
5528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5530 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5531 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5532 // (TXCCrr G0, IntRegs:$rs2, 7) - 2329
5533 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
5534 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5535 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5536 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5537 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2333
5538 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5539 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5540 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5541 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5542 // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2337
5543 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
5544 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5545 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5546 // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2340
5547 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
5548 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5549 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5550 // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2343
5551 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
5552 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5553 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5554 // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2346
5555 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
5556 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5557 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5558 // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2349
5559 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
5560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5562 // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2352
5563 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
5564 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5565 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5566 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 2355
5567 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5568 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5569 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5570 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5571 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5572 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5573 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 2361
5574 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5575 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5576 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5577 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5578 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5579 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5580 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 2367
5581 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5582 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5584 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5585 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5586 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5587 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 2373
5588 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5589 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5590 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5591 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5592 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5593 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5594 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 2379
5595 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5596 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5597 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5598 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5599 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5600 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5601 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 2385
5602 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5603 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5604 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5605 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5606 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5607 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5608 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 2391
5609 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5610 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5611 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5612 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5613 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5614 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5615 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 2397
5616 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5617 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5618 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5619 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5620 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5621 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5622 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 2403
5623 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5624 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5625 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5626 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5627 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5628 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5629 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 2409
5630 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5631 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5632 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5633 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5634 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5635 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5636 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 2415
5637 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5638 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5639 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5640 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5641 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5642 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5643 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 2421
5644 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5645 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5646 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5647 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5648 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5649 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5650 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 2427
5651 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5652 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5653 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5654 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5655 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5656 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5657 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 2433
5658 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5659 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5660 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5661 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5662 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5663 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5664 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 2439
5665 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5666 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5667 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5668 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5669 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5670 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5671 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 2445
5672 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5673 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5674 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5675 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5676 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5677 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5678 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 2451
5679 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5680 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5681 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5682 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5683 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5684 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5685 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 2457
5686 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5687 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5688 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5689 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5690 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5691 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5692 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 2463
5693 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5694 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5695 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5696 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5697 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5698 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5699 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 2469
5700 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5701 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5702 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5703 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5704 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5705 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5706 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 2475
5707 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5708 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5709 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5710 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5711 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5712 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5713 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 2481
5714 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5715 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5716 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5717 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5718 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5719 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5720 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 2487
5721 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5722 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5723 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5724 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5725 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5726 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5727 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 2493
5728 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5729 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5730 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5731 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5732 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5733 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5734 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 2499
5735 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5736 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5738 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5739 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5740 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5741 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 2505
5742 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5743 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5744 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5745 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5746 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5747 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5748 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 2511
5749 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5750 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5751 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5752 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5753 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5754 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5755 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 2517
5756 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5757 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5758 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5759 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5760 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5761 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5762 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 2523
5763 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5764 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5765 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5766 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5767 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5768 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5769 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 2529
5770 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5771 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5772 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5773 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5774 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5775 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5776 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 2535
5777 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5778 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5779 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5780 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5781 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5782 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5783 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 2541
5784 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5785 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5786 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5787 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5788 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5789 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5790 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 2547
5791 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5792 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5793 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5794 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5795 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5796 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5797 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 2553
5798 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5799 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5801 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5802 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5803 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5804 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 2559
5805 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5806 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5807 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5808 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5809 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5810 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5811 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 2565
5812 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5813 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5814 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5815 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5816 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5817 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5818 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 2571
5819 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5822 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5823 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5824 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5825 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 2577
5826 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5829 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5830 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5831 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5832 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 2583
5833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5834 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5835 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5836 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5837 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5838 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5839 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 2589
5840 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5841 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5842 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5843 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5844 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5845 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5846 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 2595
5847 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5849 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5850 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5851 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5852 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5853 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 2601
5854 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5855 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5856 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5857 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5858 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5859 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5860 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 2607
5861 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5862 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5863 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5864 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5865 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5866 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5867 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 2613
5868 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5869 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5870 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5871 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5872 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5873 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5874 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 2619
5875 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5876 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5877 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5878 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5879 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5880 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5881 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 2625
5882 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5883 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5884 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5885 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5887 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5888 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 2631
5889 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5890 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5891 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5892 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5893 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5894 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5895 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 2637
5896 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5897 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5898 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5899 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5900 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5901 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5902 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 2643
5903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5904 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5905 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5906 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5907 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5908 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5909 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 2649
5910 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5911 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5912 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5913 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5914 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5915 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5916 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 2655
5917 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5918 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5919 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5920 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5921 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5922 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5923 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 2661
5924 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5925 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5926 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5927 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5928 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5929 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5930 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 2667
5931 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5932 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5933 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5934 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5935 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5936 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5937 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 2673
5938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5939 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5940 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5941 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5942 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5943 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5944 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 2679
5945 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5946 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5947 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5948 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5949 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5950 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5951 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 2685
5952 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5953 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5954 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5955 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5956 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5957 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5958 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 2691
5959 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5960 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5961 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5962 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5963 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5964 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5965 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 2697
5966 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5967 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5968 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5969 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5970 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5971 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5972 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 2703
5973 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5974 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5975 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5976 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5977 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5978 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5979 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 2709
5980 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5981 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5982 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5983 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5984 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5985 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5986 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 2715
5987 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5988 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5989 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5990 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5991 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5992 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5993 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 2721
5994 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5995 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5996 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5997 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5998 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5999 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6000 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 2727
6001 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6002 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6003 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6004 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6005 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6006 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6007 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 2733
6008 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6009 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6010 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6011 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6012 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6013 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6014 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 2739
6015 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6016 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6017 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6018 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6019 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
6020 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6021 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 2745
6022 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6023 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6024 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6025 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6026 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
6027 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6028 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 2751
6029 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6030 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6031 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6032 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6033 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
6034 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6035 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 2757
6036 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6037 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6038 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6039 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6040 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
6041 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6042 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 2763
6043 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6044 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6045 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6046 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6047 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
6048 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6049 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 2769
6050 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6051 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6052 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6053 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6054 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
6055 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6056 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 2775
6057 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6058 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6059 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6060 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6061 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
6062 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6063 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 2781
6064 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6065 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6066 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6067 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6068 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
6069 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6070 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 2787
6071 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6072 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6073 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6074 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6075 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
6076 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6077 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 2793
6078 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6079 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6080 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6081 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6082 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
6083 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6084 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 2799
6085 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6086 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6087 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6088 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6089 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
6090 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6091 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 2805
6092 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6093 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6094 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6095 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6096 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
6097 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6098 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 2811
6099 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6100 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6101 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6102 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6103 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
6104 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6105 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 2817
6106 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6107 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6108 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6109 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6110 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
6111 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6112 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 2823
6113 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6114 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6115 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6116 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6117 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
6118 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6119 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 2829
6120 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6121 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
6122 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6123 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
6124 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
6125 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
6126 // (WRASRri ASR27, G0, simm13Op:$simm13) - 2835
6127 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
6128 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6129 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
6130 // (WRASRrr ASR27, G0, IntRegs:$rs2) - 2838
6131 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::ASR27},
6132 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
6133 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
6134 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureOSA2011},
6135 };
6136
6137 static const char AsmStrings[] =
6138 /* 0 */ "ba $\xFF\x01\x01\0"
6139 /* 8 */ "bn $\xFF\x01\x01\0"
6140 /* 16 */ "bne $\xFF\x01\x01\0"
6141 /* 25 */ "be $\xFF\x01\x01\0"
6142 /* 33 */ "bg $\xFF\x01\x01\0"
6143 /* 41 */ "ble $\xFF\x01\x01\0"
6144 /* 50 */ "bge $\xFF\x01\x01\0"
6145 /* 59 */ "bl $\xFF\x01\x01\0"
6146 /* 67 */ "bgu $\xFF\x01\x01\0"
6147 /* 76 */ "bleu $\xFF\x01\x01\0"
6148 /* 86 */ "bcc $\xFF\x01\x01\0"
6149 /* 95 */ "bcs $\xFF\x01\x01\0"
6150 /* 104 */ "bpos $\xFF\x01\x01\0"
6151 /* 114 */ "bneg $\xFF\x01\x01\0"
6152 /* 124 */ "bvc $\xFF\x01\x01\0"
6153 /* 133 */ "bvs $\xFF\x01\x01\0"
6154 /* 142 */ "ba,a $\xFF\x01\x01\0"
6155 /* 152 */ "bn,a $\xFF\x01\x01\0"
6156 /* 162 */ "bne,a $\xFF\x01\x01\0"
6157 /* 173 */ "be,a $\xFF\x01\x01\0"
6158 /* 183 */ "bg,a $\xFF\x01\x01\0"
6159 /* 193 */ "ble,a $\xFF\x01\x01\0"
6160 /* 204 */ "bge,a $\xFF\x01\x01\0"
6161 /* 215 */ "bl,a $\xFF\x01\x01\0"
6162 /* 225 */ "bgu,a $\xFF\x01\x01\0"
6163 /* 236 */ "bleu,a $\xFF\x01\x01\0"
6164 /* 248 */ "bcc,a $\xFF\x01\x01\0"
6165 /* 259 */ "bcs,a $\xFF\x01\x01\0"
6166 /* 270 */ "bpos,a $\xFF\x01\x01\0"
6167 /* 282 */ "bneg,a $\xFF\x01\x01\0"
6168 /* 294 */ "bvc,a $\xFF\x01\x01\0"
6169 /* 305 */ "bvs,a $\xFF\x01\x01\0"
6170 /* 316 */ "fba,a,pn $\x03, $\xFF\x01\x01\0"
6171 /* 334 */ "fbn,a,pn $\x03, $\xFF\x01\x01\0"
6172 /* 352 */ "fbu,a,pn $\x03, $\xFF\x01\x01\0"
6173 /* 370 */ "fbg,a,pn $\x03, $\xFF\x01\x01\0"
6174 /* 388 */ "fbug,a,pn $\x03, $\xFF\x01\x01\0"
6175 /* 407 */ "fbl,a,pn $\x03, $\xFF\x01\x01\0"
6176 /* 425 */ "fbul,a,pn $\x03, $\xFF\x01\x01\0"
6177 /* 444 */ "fblg,a,pn $\x03, $\xFF\x01\x01\0"
6178 /* 463 */ "fbne,a,pn $\x03, $\xFF\x01\x01\0"
6179 /* 482 */ "fbe,a,pn $\x03, $\xFF\x01\x01\0"
6180 /* 500 */ "fbue,a,pn $\x03, $\xFF\x01\x01\0"
6181 /* 519 */ "fbge,a,pn $\x03, $\xFF\x01\x01\0"
6182 /* 538 */ "fbuge,a,pn $\x03, $\xFF\x01\x01\0"
6183 /* 558 */ "fble,a,pn $\x03, $\xFF\x01\x01\0"
6184 /* 577 */ "fbule,a,pn $\x03, $\xFF\x01\x01\0"
6185 /* 597 */ "fbo,a,pn $\x03, $\xFF\x01\x01\0"
6186 /* 615 */ "fba,pn $\x03, $\xFF\x01\x01\0"
6187 /* 631 */ "fbn,pn $\x03, $\xFF\x01\x01\0"
6188 /* 647 */ "fbu,pn $\x03, $\xFF\x01\x01\0"
6189 /* 663 */ "fbg,pn $\x03, $\xFF\x01\x01\0"
6190 /* 679 */ "fbug,pn $\x03, $\xFF\x01\x01\0"
6191 /* 696 */ "fbl,pn $\x03, $\xFF\x01\x01\0"
6192 /* 712 */ "fbul,pn $\x03, $\xFF\x01\x01\0"
6193 /* 729 */ "fblg,pn $\x03, $\xFF\x01\x01\0"
6194 /* 746 */ "fbne,pn $\x03, $\xFF\x01\x01\0"
6195 /* 763 */ "fbe,pn $\x03, $\xFF\x01\x01\0"
6196 /* 779 */ "fbue,pn $\x03, $\xFF\x01\x01\0"
6197 /* 796 */ "fbge,pn $\x03, $\xFF\x01\x01\0"
6198 /* 813 */ "fbuge,pn $\x03, $\xFF\x01\x01\0"
6199 /* 831 */ "fble,pn $\x03, $\xFF\x01\x01\0"
6200 /* 848 */ "fbule,pn $\x03, $\xFF\x01\x01\0"
6201 /* 866 */ "fbo,pn $\x03, $\xFF\x01\x01\0"
6202 /* 882 */ "ba,a,pn %icc, $\xFF\x01\x01\0"
6203 /* 901 */ "bn,a,pn %icc, $\xFF\x01\x01\0"
6204 /* 920 */ "bne,a,pn %icc, $\xFF\x01\x01\0"
6205 /* 940 */ "be,a,pn %icc, $\xFF\x01\x01\0"
6206 /* 959 */ "bg,a,pn %icc, $\xFF\x01\x01\0"
6207 /* 978 */ "ble,a,pn %icc, $\xFF\x01\x01\0"
6208 /* 998 */ "bge,a,pn %icc, $\xFF\x01\x01\0"
6209 /* 1018 */ "bl,a,pn %icc, $\xFF\x01\x01\0"
6210 /* 1037 */ "bgu,a,pn %icc, $\xFF\x01\x01\0"
6211 /* 1057 */ "bleu,a,pn %icc, $\xFF\x01\x01\0"
6212 /* 1078 */ "bcc,a,pn %icc, $\xFF\x01\x01\0"
6213 /* 1098 */ "bcs,a,pn %icc, $\xFF\x01\x01\0"
6214 /* 1118 */ "bpos,a,pn %icc, $\xFF\x01\x01\0"
6215 /* 1139 */ "bneg,a,pn %icc, $\xFF\x01\x01\0"
6216 /* 1160 */ "bvc,a,pn %icc, $\xFF\x01\x01\0"
6217 /* 1180 */ "bvs,a,pn %icc, $\xFF\x01\x01\0"
6218 /* 1200 */ "ba,pn %icc, $\xFF\x01\x01\0"
6219 /* 1217 */ "bn,pn %icc, $\xFF\x01\x01\0"
6220 /* 1234 */ "bne,pn %icc, $\xFF\x01\x01\0"
6221 /* 1252 */ "be,pn %icc, $\xFF\x01\x01\0"
6222 /* 1269 */ "bg,pn %icc, $\xFF\x01\x01\0"
6223 /* 1286 */ "ble,pn %icc, $\xFF\x01\x01\0"
6224 /* 1304 */ "bge,pn %icc, $\xFF\x01\x01\0"
6225 /* 1322 */ "bl,pn %icc, $\xFF\x01\x01\0"
6226 /* 1339 */ "bgu,pn %icc, $\xFF\x01\x01\0"
6227 /* 1357 */ "bleu,pn %icc, $\xFF\x01\x01\0"
6228 /* 1376 */ "bcc,pn %icc, $\xFF\x01\x01\0"
6229 /* 1394 */ "bcs,pn %icc, $\xFF\x01\x01\0"
6230 /* 1412 */ "bpos,pn %icc, $\xFF\x01\x01\0"
6231 /* 1431 */ "bneg,pn %icc, $\xFF\x01\x01\0"
6232 /* 1450 */ "bvc,pn %icc, $\xFF\x01\x01\0"
6233 /* 1468 */ "bvs,pn %icc, $\xFF\x01\x01\0"
6234 /* 1486 */ "brlez,a,pn $\x03, $\xFF\x01\x01\0"
6235 /* 1506 */ "brlz,a,pn $\x03, $\xFF\x01\x01\0"
6236 /* 1525 */ "brgz,a,pn $\x03, $\xFF\x01\x01\0"
6237 /* 1544 */ "brgez,a,pn $\x03, $\xFF\x01\x01\0"
6238 /* 1564 */ "brlez,pn $\x03, $\xFF\x01\x01\0"
6239 /* 1582 */ "brlz,pn $\x03, $\xFF\x01\x01\0"
6240 /* 1599 */ "brgz,pn $\x03, $\xFF\x01\x01\0"
6241 /* 1616 */ "brgez,pn $\x03, $\xFF\x01\x01\0"
6242 /* 1634 */ "ba,a,pn %xcc, $\xFF\x01\x01\0"
6243 /* 1653 */ "bn,a,pn %xcc, $\xFF\x01\x01\0"
6244 /* 1672 */ "bne,a,pn %xcc, $\xFF\x01\x01\0"
6245 /* 1692 */ "be,a,pn %xcc, $\xFF\x01\x01\0"
6246 /* 1711 */ "bg,a,pn %xcc, $\xFF\x01\x01\0"
6247 /* 1730 */ "ble,a,pn %xcc, $\xFF\x01\x01\0"
6248 /* 1750 */ "bge,a,pn %xcc, $\xFF\x01\x01\0"
6249 /* 1770 */ "bl,a,pn %xcc, $\xFF\x01\x01\0"
6250 /* 1789 */ "bgu,a,pn %xcc, $\xFF\x01\x01\0"
6251 /* 1809 */ "bleu,a,pn %xcc, $\xFF\x01\x01\0"
6252 /* 1830 */ "bcc,a,pn %xcc, $\xFF\x01\x01\0"
6253 /* 1850 */ "bcs,a,pn %xcc, $\xFF\x01\x01\0"
6254 /* 1870 */ "bpos,a,pn %xcc, $\xFF\x01\x01\0"
6255 /* 1891 */ "bneg,a,pn %xcc, $\xFF\x01\x01\0"
6256 /* 1912 */ "bvc,a,pn %xcc, $\xFF\x01\x01\0"
6257 /* 1932 */ "bvs,a,pn %xcc, $\xFF\x01\x01\0"
6258 /* 1952 */ "ba,pn %xcc, $\xFF\x01\x01\0"
6259 /* 1969 */ "bn,pn %xcc, $\xFF\x01\x01\0"
6260 /* 1986 */ "bne,pn %xcc, $\xFF\x01\x01\0"
6261 /* 2004 */ "be,pn %xcc, $\xFF\x01\x01\0"
6262 /* 2021 */ "bg,pn %xcc, $\xFF\x01\x01\0"
6263 /* 2038 */ "ble,pn %xcc, $\xFF\x01\x01\0"
6264 /* 2056 */ "bge,pn %xcc, $\xFF\x01\x01\0"
6265 /* 2074 */ "bl,pn %xcc, $\xFF\x01\x01\0"
6266 /* 2091 */ "bgu,pn %xcc, $\xFF\x01\x01\0"
6267 /* 2109 */ "bleu,pn %xcc, $\xFF\x01\x01\0"
6268 /* 2128 */ "bcc,pn %xcc, $\xFF\x01\x01\0"
6269 /* 2146 */ "bcs,pn %xcc, $\xFF\x01\x01\0"
6270 /* 2164 */ "bpos,pn %xcc, $\xFF\x01\x01\0"
6271 /* 2183 */ "bneg,pn %xcc, $\xFF\x01\x01\0"
6272 /* 2202 */ "bvc,pn %xcc, $\xFF\x01\x01\0"
6273 /* 2220 */ "bvs,pn %xcc, $\xFF\x01\x01\0"
6274 /* 2238 */ "cas [$\x02], $\x03, $\x01\0"
6275 /* 2255 */ "casl [$\x02], $\x03, $\x01\0"
6276 /* 2273 */ "casx [$\x02], $\x03, $\x01\0"
6277 /* 2291 */ "casxl [$\x02], $\x03, $\x01\0"
6278 /* 2310 */ "cwbne $\x03, $\x04, $\xFF\x01\x01\0"
6279 /* 2329 */ "cwbe $\x03, $\x04, $\xFF\x01\x01\0"
6280 /* 2347 */ "cwbg $\x03, $\x04, $\xFF\x01\x01\0"
6281 /* 2365 */ "cwble $\x03, $\x04, $\xFF\x01\x01\0"
6282 /* 2384 */ "cwbge $\x03, $\x04, $\xFF\x01\x01\0"
6283 /* 2403 */ "cwbl $\x03, $\x04, $\xFF\x01\x01\0"
6284 /* 2421 */ "cwbgu $\x03, $\x04, $\xFF\x01\x01\0"
6285 /* 2440 */ "cwbleu $\x03, $\x04, $\xFF\x01\x01\0"
6286 /* 2460 */ "cwbcc $\x03, $\x04, $\xFF\x01\x01\0"
6287 /* 2479 */ "cwbcs $\x03, $\x04, $\xFF\x01\x01\0"
6288 /* 2498 */ "cwbpos $\x03, $\x04, $\xFF\x01\x01\0"
6289 /* 2518 */ "cwbneg $\x03, $\x04, $\xFF\x01\x01\0"
6290 /* 2538 */ "cwbvc $\x03, $\x04, $\xFF\x01\x01\0"
6291 /* 2557 */ "cwbvs $\x03, $\x04, $\xFF\x01\x01\0"
6292 /* 2576 */ "cxbne $\x03, $\x04, $\xFF\x01\x01\0"
6293 /* 2595 */ "cxbe $\x03, $\x04, $\xFF\x01\x01\0"
6294 /* 2613 */ "cxbg $\x03, $\x04, $\xFF\x01\x01\0"
6295 /* 2631 */ "cxble $\x03, $\x04, $\xFF\x01\x01\0"
6296 /* 2650 */ "cxbge $\x03, $\x04, $\xFF\x01\x01\0"
6297 /* 2669 */ "cxbl $\x03, $\x04, $\xFF\x01\x01\0"
6298 /* 2687 */ "cxbgu $\x03, $\x04, $\xFF\x01\x01\0"
6299 /* 2706 */ "cxbleu $\x03, $\x04, $\xFF\x01\x01\0"
6300 /* 2726 */ "cxbcc $\x03, $\x04, $\xFF\x01\x01\0"
6301 /* 2745 */ "cxbcs $\x03, $\x04, $\xFF\x01\x01\0"
6302 /* 2764 */ "cxbpos $\x03, $\x04, $\xFF\x01\x01\0"
6303 /* 2784 */ "cxbneg $\x03, $\x04, $\xFF\x01\x01\0"
6304 /* 2804 */ "cxbvc $\x03, $\x04, $\xFF\x01\x01\0"
6305 /* 2823 */ "cxbvs $\x03, $\x04, $\xFF\x01\x01\0"
6306 /* 2842 */ "fmovda %icc, $\x02, $\x01\0"
6307 /* 2862 */ "fmovdn %icc, $\x02, $\x01\0"
6308 /* 2882 */ "fmovdne %icc, $\x02, $\x01\0"
6309 /* 2903 */ "fmovde %icc, $\x02, $\x01\0"
6310 /* 2923 */ "fmovdg %icc, $\x02, $\x01\0"
6311 /* 2943 */ "fmovdle %icc, $\x02, $\x01\0"
6312 /* 2964 */ "fmovdge %icc, $\x02, $\x01\0"
6313 /* 2985 */ "fmovdl %icc, $\x02, $\x01\0"
6314 /* 3005 */ "fmovdgu %icc, $\x02, $\x01\0"
6315 /* 3026 */ "fmovdleu %icc, $\x02, $\x01\0"
6316 /* 3048 */ "fmovdcc %icc, $\x02, $\x01\0"
6317 /* 3069 */ "fmovdcs %icc, $\x02, $\x01\0"
6318 /* 3090 */ "fmovdpos %icc, $\x02, $\x01\0"
6319 /* 3112 */ "fmovdneg %icc, $\x02, $\x01\0"
6320 /* 3134 */ "fmovdvc %icc, $\x02, $\x01\0"
6321 /* 3155 */ "fmovdvs %icc, $\x02, $\x01\0"
6322 /* 3176 */ "fmovda %xcc, $\x02, $\x01\0"
6323 /* 3196 */ "fmovdn %xcc, $\x02, $\x01\0"
6324 /* 3216 */ "fmovdne %xcc, $\x02, $\x01\0"
6325 /* 3237 */ "fmovde %xcc, $\x02, $\x01\0"
6326 /* 3257 */ "fmovdg %xcc, $\x02, $\x01\0"
6327 /* 3277 */ "fmovdle %xcc, $\x02, $\x01\0"
6328 /* 3298 */ "fmovdge %xcc, $\x02, $\x01\0"
6329 /* 3319 */ "fmovdl %xcc, $\x02, $\x01\0"
6330 /* 3339 */ "fmovdgu %xcc, $\x02, $\x01\0"
6331 /* 3360 */ "fmovdleu %xcc, $\x02, $\x01\0"
6332 /* 3382 */ "fmovdcc %xcc, $\x02, $\x01\0"
6333 /* 3403 */ "fmovdcs %xcc, $\x02, $\x01\0"
6334 /* 3424 */ "fmovdpos %xcc, $\x02, $\x01\0"
6335 /* 3446 */ "fmovdneg %xcc, $\x02, $\x01\0"
6336 /* 3468 */ "fmovdvc %xcc, $\x02, $\x01\0"
6337 /* 3489 */ "fmovdvs %xcc, $\x02, $\x01\0"
6338 /* 3510 */ "fmovqa %icc, $\x02, $\x01\0"
6339 /* 3530 */ "fmovqn %icc, $\x02, $\x01\0"
6340 /* 3550 */ "fmovqne %icc, $\x02, $\x01\0"
6341 /* 3571 */ "fmovqe %icc, $\x02, $\x01\0"
6342 /* 3591 */ "fmovqg %icc, $\x02, $\x01\0"
6343 /* 3611 */ "fmovqle %icc, $\x02, $\x01\0"
6344 /* 3632 */ "fmovqge %icc, $\x02, $\x01\0"
6345 /* 3653 */ "fmovql %icc, $\x02, $\x01\0"
6346 /* 3673 */ "fmovqgu %icc, $\x02, $\x01\0"
6347 /* 3694 */ "fmovqleu %icc, $\x02, $\x01\0"
6348 /* 3716 */ "fmovqcc %icc, $\x02, $\x01\0"
6349 /* 3737 */ "fmovqcs %icc, $\x02, $\x01\0"
6350 /* 3758 */ "fmovqpos %icc, $\x02, $\x01\0"
6351 /* 3780 */ "fmovqneg %icc, $\x02, $\x01\0"
6352 /* 3802 */ "fmovqvc %icc, $\x02, $\x01\0"
6353 /* 3823 */ "fmovqvs %icc, $\x02, $\x01\0"
6354 /* 3844 */ "fmovqa %xcc, $\x02, $\x01\0"
6355 /* 3864 */ "fmovqn %xcc, $\x02, $\x01\0"
6356 /* 3884 */ "fmovqne %xcc, $\x02, $\x01\0"
6357 /* 3905 */ "fmovqe %xcc, $\x02, $\x01\0"
6358 /* 3925 */ "fmovqg %xcc, $\x02, $\x01\0"
6359 /* 3945 */ "fmovqle %xcc, $\x02, $\x01\0"
6360 /* 3966 */ "fmovqge %xcc, $\x02, $\x01\0"
6361 /* 3987 */ "fmovql %xcc, $\x02, $\x01\0"
6362 /* 4007 */ "fmovqgu %xcc, $\x02, $\x01\0"
6363 /* 4028 */ "fmovqleu %xcc, $\x02, $\x01\0"
6364 /* 4050 */ "fmovqcc %xcc, $\x02, $\x01\0"
6365 /* 4071 */ "fmovqcs %xcc, $\x02, $\x01\0"
6366 /* 4092 */ "fmovqpos %xcc, $\x02, $\x01\0"
6367 /* 4114 */ "fmovqneg %xcc, $\x02, $\x01\0"
6368 /* 4136 */ "fmovqvc %xcc, $\x02, $\x01\0"
6369 /* 4157 */ "fmovqvs %xcc, $\x02, $\x01\0"
6370 /* 4178 */ "fmovrdlez $\x02, $\x03, $\x01\0"
6371 /* 4199 */ "fmovrdlz $\x02, $\x03, $\x01\0"
6372 /* 4219 */ "fmovrdgz $\x02, $\x03, $\x01\0"
6373 /* 4239 */ "fmovrdgez $\x02, $\x03, $\x01\0"
6374 /* 4260 */ "fmovrqlez $\x02, $\x03, $\x01\0"
6375 /* 4281 */ "fmovrqlz $\x02, $\x03, $\x01\0"
6376 /* 4301 */ "fmovrqgz $\x02, $\x03, $\x01\0"
6377 /* 4321 */ "fmovrqgez $\x02, $\x03, $\x01\0"
6378 /* 4342 */ "fmovrslez $\x02, $\x03, $\x01\0"
6379 /* 4363 */ "fmovrslz $\x02, $\x03, $\x01\0"
6380 /* 4383 */ "fmovrsgz $\x02, $\x03, $\x01\0"
6381 /* 4403 */ "fmovrsgez $\x02, $\x03, $\x01\0"
6382 /* 4424 */ "fmovsa %icc, $\x02, $\x01\0"
6383 /* 4444 */ "fmovsn %icc, $\x02, $\x01\0"
6384 /* 4464 */ "fmovsne %icc, $\x02, $\x01\0"
6385 /* 4485 */ "fmovse %icc, $\x02, $\x01\0"
6386 /* 4505 */ "fmovsg %icc, $\x02, $\x01\0"
6387 /* 4525 */ "fmovsle %icc, $\x02, $\x01\0"
6388 /* 4546 */ "fmovsge %icc, $\x02, $\x01\0"
6389 /* 4567 */ "fmovsl %icc, $\x02, $\x01\0"
6390 /* 4587 */ "fmovsgu %icc, $\x02, $\x01\0"
6391 /* 4608 */ "fmovsleu %icc, $\x02, $\x01\0"
6392 /* 4630 */ "fmovscc %icc, $\x02, $\x01\0"
6393 /* 4651 */ "fmovscs %icc, $\x02, $\x01\0"
6394 /* 4672 */ "fmovspos %icc, $\x02, $\x01\0"
6395 /* 4694 */ "fmovsneg %icc, $\x02, $\x01\0"
6396 /* 4716 */ "fmovsvc %icc, $\x02, $\x01\0"
6397 /* 4737 */ "fmovsvs %icc, $\x02, $\x01\0"
6398 /* 4758 */ "fmovsa %xcc, $\x02, $\x01\0"
6399 /* 4778 */ "fmovsn %xcc, $\x02, $\x01\0"
6400 /* 4798 */ "fmovsne %xcc, $\x02, $\x01\0"
6401 /* 4819 */ "fmovse %xcc, $\x02, $\x01\0"
6402 /* 4839 */ "fmovsg %xcc, $\x02, $\x01\0"
6403 /* 4859 */ "fmovsle %xcc, $\x02, $\x01\0"
6404 /* 4880 */ "fmovsge %xcc, $\x02, $\x01\0"
6405 /* 4901 */ "fmovsl %xcc, $\x02, $\x01\0"
6406 /* 4921 */ "fmovsgu %xcc, $\x02, $\x01\0"
6407 /* 4942 */ "fmovsleu %xcc, $\x02, $\x01\0"
6408 /* 4964 */ "fmovscc %xcc, $\x02, $\x01\0"
6409 /* 4985 */ "fmovscs %xcc, $\x02, $\x01\0"
6410 /* 5006 */ "fmovspos %xcc, $\x02, $\x01\0"
6411 /* 5028 */ "fmovsneg %xcc, $\x02, $\x01\0"
6412 /* 5050 */ "fmovsvc %xcc, $\x02, $\x01\0"
6413 /* 5071 */ "fmovsvs %xcc, $\x02, $\x01\0"
6414 /* 5092 */ "mova %icc, $\x02, $\x01\0"
6415 /* 5110 */ "movn %icc, $\x02, $\x01\0"
6416 /* 5128 */ "movne %icc, $\x02, $\x01\0"
6417 /* 5147 */ "move %icc, $\x02, $\x01\0"
6418 /* 5165 */ "movg %icc, $\x02, $\x01\0"
6419 /* 5183 */ "movle %icc, $\x02, $\x01\0"
6420 /* 5202 */ "movge %icc, $\x02, $\x01\0"
6421 /* 5221 */ "movl %icc, $\x02, $\x01\0"
6422 /* 5239 */ "movgu %icc, $\x02, $\x01\0"
6423 /* 5258 */ "movleu %icc, $\x02, $\x01\0"
6424 /* 5278 */ "movcc %icc, $\x02, $\x01\0"
6425 /* 5297 */ "movcs %icc, $\x02, $\x01\0"
6426 /* 5316 */ "movpos %icc, $\x02, $\x01\0"
6427 /* 5336 */ "movneg %icc, $\x02, $\x01\0"
6428 /* 5356 */ "movvc %icc, $\x02, $\x01\0"
6429 /* 5375 */ "movvs %icc, $\x02, $\x01\0"
6430 /* 5394 */ "movrlez $\x02, $\x03, $\x01\0"
6431 /* 5413 */ "movrlz $\x02, $\x03, $\x01\0"
6432 /* 5431 */ "movrgz $\x02, $\x03, $\x01\0"
6433 /* 5449 */ "movrgez $\x02, $\x03, $\x01\0"
6434 /* 5468 */ "mova %xcc, $\x02, $\x01\0"
6435 /* 5486 */ "movn %xcc, $\x02, $\x01\0"
6436 /* 5504 */ "movne %xcc, $\x02, $\x01\0"
6437 /* 5523 */ "move %xcc, $\x02, $\x01\0"
6438 /* 5541 */ "movg %xcc, $\x02, $\x01\0"
6439 /* 5559 */ "movle %xcc, $\x02, $\x01\0"
6440 /* 5578 */ "movge %xcc, $\x02, $\x01\0"
6441 /* 5597 */ "movl %xcc, $\x02, $\x01\0"
6442 /* 5615 */ "movgu %xcc, $\x02, $\x01\0"
6443 /* 5634 */ "movleu %xcc, $\x02, $\x01\0"
6444 /* 5654 */ "movcc %xcc, $\x02, $\x01\0"
6445 /* 5673 */ "movcs %xcc, $\x02, $\x01\0"
6446 /* 5692 */ "movpos %xcc, $\x02, $\x01\0"
6447 /* 5712 */ "movneg %xcc, $\x02, $\x01\0"
6448 /* 5732 */ "movvc %xcc, $\x02, $\x01\0"
6449 /* 5751 */ "movvs %xcc, $\x02, $\x01\0"
6450 /* 5770 */ "tst $\x02\0"
6451 /* 5777 */ "mov $\x03, $\x01\0"
6452 /* 5788 */ "restore\0"
6453 /* 5796 */ "ret\0"
6454 /* 5800 */ "retl\0"
6455 /* 5805 */ "save\0"
6456 /* 5810 */ "cmp $\x02, $\x03\0"
6457 /* 5821 */ "ta %icc, $\x02\0"
6458 /* 5833 */ "ta %icc, $\x01 + $\x02\0"
6459 /* 5850 */ "tn %icc, $\x02\0"
6460 /* 5862 */ "tn %icc, $\x01 + $\x02\0"
6461 /* 5879 */ "tne %icc, $\x02\0"
6462 /* 5892 */ "tne %icc, $\x01 + $\x02\0"
6463 /* 5910 */ "te %icc, $\x02\0"
6464 /* 5922 */ "te %icc, $\x01 + $\x02\0"
6465 /* 5939 */ "tg %icc, $\x02\0"
6466 /* 5951 */ "tg %icc, $\x01 + $\x02\0"
6467 /* 5968 */ "tle %icc, $\x02\0"
6468 /* 5981 */ "tle %icc, $\x01 + $\x02\0"
6469 /* 5999 */ "tge %icc, $\x02\0"
6470 /* 6012 */ "tge %icc, $\x01 + $\x02\0"
6471 /* 6030 */ "tl %icc, $\x02\0"
6472 /* 6042 */ "tl %icc, $\x01 + $\x02\0"
6473 /* 6059 */ "tgu %icc, $\x02\0"
6474 /* 6072 */ "tgu %icc, $\x01 + $\x02\0"
6475 /* 6090 */ "tleu %icc, $\x02\0"
6476 /* 6104 */ "tleu %icc, $\x01 + $\x02\0"
6477 /* 6123 */ "tcc %icc, $\x02\0"
6478 /* 6136 */ "tcc %icc, $\x01 + $\x02\0"
6479 /* 6154 */ "tcs %icc, $\x02\0"
6480 /* 6167 */ "tcs %icc, $\x01 + $\x02\0"
6481 /* 6185 */ "tpos %icc, $\x02\0"
6482 /* 6199 */ "tpos %icc, $\x01 + $\x02\0"
6483 /* 6218 */ "tneg %icc, $\x02\0"
6484 /* 6232 */ "tneg %icc, $\x01 + $\x02\0"
6485 /* 6251 */ "tvc %icc, $\x02\0"
6486 /* 6264 */ "tvc %icc, $\x01 + $\x02\0"
6487 /* 6282 */ "tvs %icc, $\x02\0"
6488 /* 6295 */ "tvs %icc, $\x01 + $\x02\0"
6489 /* 6313 */ "ta $\x02\0"
6490 /* 6319 */ "ta $\x01 + $\x02\0"
6491 /* 6330 */ "tn $\x02\0"
6492 /* 6336 */ "tn $\x01 + $\x02\0"
6493 /* 6347 */ "tne $\x02\0"
6494 /* 6354 */ "tne $\x01 + $\x02\0"
6495 /* 6366 */ "te $\x02\0"
6496 /* 6372 */ "te $\x01 + $\x02\0"
6497 /* 6383 */ "tg $\x02\0"
6498 /* 6389 */ "tg $\x01 + $\x02\0"
6499 /* 6400 */ "tle $\x02\0"
6500 /* 6407 */ "tle $\x01 + $\x02\0"
6501 /* 6419 */ "tge $\x02\0"
6502 /* 6426 */ "tge $\x01 + $\x02\0"
6503 /* 6438 */ "tl $\x02\0"
6504 /* 6444 */ "tl $\x01 + $\x02\0"
6505 /* 6455 */ "tgu $\x02\0"
6506 /* 6462 */ "tgu $\x01 + $\x02\0"
6507 /* 6474 */ "tleu $\x02\0"
6508 /* 6482 */ "tleu $\x01 + $\x02\0"
6509 /* 6495 */ "tcc $\x02\0"
6510 /* 6502 */ "tcc $\x01 + $\x02\0"
6511 /* 6514 */ "tcs $\x02\0"
6512 /* 6521 */ "tcs $\x01 + $\x02\0"
6513 /* 6533 */ "tpos $\x02\0"
6514 /* 6541 */ "tpos $\x01 + $\x02\0"
6515 /* 6554 */ "tneg $\x02\0"
6516 /* 6562 */ "tneg $\x01 + $\x02\0"
6517 /* 6575 */ "tvc $\x02\0"
6518 /* 6582 */ "tvc $\x01 + $\x02\0"
6519 /* 6594 */ "tvs $\x02\0"
6520 /* 6601 */ "tvs $\x01 + $\x02\0"
6521 /* 6613 */ "ta %xcc, $\x02\0"
6522 /* 6625 */ "ta %xcc, $\x01 + $\x02\0"
6523 /* 6642 */ "tn %xcc, $\x02\0"
6524 /* 6654 */ "tn %xcc, $\x01 + $\x02\0"
6525 /* 6671 */ "tne %xcc, $\x02\0"
6526 /* 6684 */ "tne %xcc, $\x01 + $\x02\0"
6527 /* 6702 */ "te %xcc, $\x02\0"
6528 /* 6714 */ "te %xcc, $\x01 + $\x02\0"
6529 /* 6731 */ "tg %xcc, $\x02\0"
6530 /* 6743 */ "tg %xcc, $\x01 + $\x02\0"
6531 /* 6760 */ "tle %xcc, $\x02\0"
6532 /* 6773 */ "tle %xcc, $\x01 + $\x02\0"
6533 /* 6791 */ "tge %xcc, $\x02\0"
6534 /* 6804 */ "tge %xcc, $\x01 + $\x02\0"
6535 /* 6822 */ "tl %xcc, $\x02\0"
6536 /* 6834 */ "tl %xcc, $\x01 + $\x02\0"
6537 /* 6851 */ "tgu %xcc, $\x02\0"
6538 /* 6864 */ "tgu %xcc, $\x01 + $\x02\0"
6539 /* 6882 */ "tleu %xcc, $\x02\0"
6540 /* 6896 */ "tleu %xcc, $\x01 + $\x02\0"
6541 /* 6915 */ "tcc %xcc, $\x02\0"
6542 /* 6928 */ "tcc %xcc, $\x01 + $\x02\0"
6543 /* 6946 */ "tcs %xcc, $\x02\0"
6544 /* 6959 */ "tcs %xcc, $\x01 + $\x02\0"
6545 /* 6977 */ "tpos %xcc, $\x02\0"
6546 /* 6991 */ "tpos %xcc, $\x01 + $\x02\0"
6547 /* 7010 */ "tneg %xcc, $\x02\0"
6548 /* 7024 */ "tneg %xcc, $\x01 + $\x02\0"
6549 /* 7043 */ "tvc %xcc, $\x02\0"
6550 /* 7056 */ "tvc %xcc, $\x01 + $\x02\0"
6551 /* 7074 */ "tvs %xcc, $\x02\0"
6552 /* 7087 */ "tvs %xcc, $\x01 + $\x02\0"
6553 /* 7105 */ "fcmpd $\x02, $\x03\0"
6554 /* 7118 */ "fcmped $\x02, $\x03\0"
6555 /* 7132 */ "fcmpeq $\x02, $\x03\0"
6556 /* 7146 */ "fcmpes $\x02, $\x03\0"
6557 /* 7160 */ "fcmpq $\x02, $\x03\0"
6558 /* 7173 */ "fcmps $\x02, $\x03\0"
6559 /* 7186 */ "fmovda $\x02, $\x03, $\x01\0"
6560 /* 7204 */ "fmovdn $\x02, $\x03, $\x01\0"
6561 /* 7222 */ "fmovdu $\x02, $\x03, $\x01\0"
6562 /* 7240 */ "fmovdg $\x02, $\x03, $\x01\0"
6563 /* 7258 */ "fmovdug $\x02, $\x03, $\x01\0"
6564 /* 7277 */ "fmovdl $\x02, $\x03, $\x01\0"
6565 /* 7295 */ "fmovdul $\x02, $\x03, $\x01\0"
6566 /* 7314 */ "fmovdlg $\x02, $\x03, $\x01\0"
6567 /* 7333 */ "fmovdne $\x02, $\x03, $\x01\0"
6568 /* 7352 */ "fmovde $\x02, $\x03, $\x01\0"
6569 /* 7370 */ "fmovdue $\x02, $\x03, $\x01\0"
6570 /* 7389 */ "fmovdge $\x02, $\x03, $\x01\0"
6571 /* 7408 */ "fmovduge $\x02, $\x03, $\x01\0"
6572 /* 7428 */ "fmovdle $\x02, $\x03, $\x01\0"
6573 /* 7447 */ "fmovdule $\x02, $\x03, $\x01\0"
6574 /* 7467 */ "fmovdo $\x02, $\x03, $\x01\0"
6575 /* 7485 */ "fmovqa $\x02, $\x03, $\x01\0"
6576 /* 7503 */ "fmovqn $\x02, $\x03, $\x01\0"
6577 /* 7521 */ "fmovqu $\x02, $\x03, $\x01\0"
6578 /* 7539 */ "fmovqg $\x02, $\x03, $\x01\0"
6579 /* 7557 */ "fmovqug $\x02, $\x03, $\x01\0"
6580 /* 7576 */ "fmovql $\x02, $\x03, $\x01\0"
6581 /* 7594 */ "fmovqul $\x02, $\x03, $\x01\0"
6582 /* 7613 */ "fmovqlg $\x02, $\x03, $\x01\0"
6583 /* 7632 */ "fmovqne $\x02, $\x03, $\x01\0"
6584 /* 7651 */ "fmovqe $\x02, $\x03, $\x01\0"
6585 /* 7669 */ "fmovque $\x02, $\x03, $\x01\0"
6586 /* 7688 */ "fmovqge $\x02, $\x03, $\x01\0"
6587 /* 7707 */ "fmovquge $\x02, $\x03, $\x01\0"
6588 /* 7727 */ "fmovqle $\x02, $\x03, $\x01\0"
6589 /* 7746 */ "fmovqule $\x02, $\x03, $\x01\0"
6590 /* 7766 */ "fmovqo $\x02, $\x03, $\x01\0"
6591 /* 7784 */ "fmovsa $\x02, $\x03, $\x01\0"
6592 /* 7802 */ "fmovsn $\x02, $\x03, $\x01\0"
6593 /* 7820 */ "fmovsu $\x02, $\x03, $\x01\0"
6594 /* 7838 */ "fmovsg $\x02, $\x03, $\x01\0"
6595 /* 7856 */ "fmovsug $\x02, $\x03, $\x01\0"
6596 /* 7875 */ "fmovsl $\x02, $\x03, $\x01\0"
6597 /* 7893 */ "fmovsul $\x02, $\x03, $\x01\0"
6598 /* 7912 */ "fmovslg $\x02, $\x03, $\x01\0"
6599 /* 7931 */ "fmovsne $\x02, $\x03, $\x01\0"
6600 /* 7950 */ "fmovse $\x02, $\x03, $\x01\0"
6601 /* 7968 */ "fmovsue $\x02, $\x03, $\x01\0"
6602 /* 7987 */ "fmovsge $\x02, $\x03, $\x01\0"
6603 /* 8006 */ "fmovsuge $\x02, $\x03, $\x01\0"
6604 /* 8026 */ "fmovsle $\x02, $\x03, $\x01\0"
6605 /* 8045 */ "fmovsule $\x02, $\x03, $\x01\0"
6606 /* 8065 */ "fmovso $\x02, $\x03, $\x01\0"
6607 /* 8083 */ "mova $\x02, $\x03, $\x01\0"
6608 /* 8099 */ "movn $\x02, $\x03, $\x01\0"
6609 /* 8115 */ "movu $\x02, $\x03, $\x01\0"
6610 /* 8131 */ "movg $\x02, $\x03, $\x01\0"
6611 /* 8147 */ "movug $\x02, $\x03, $\x01\0"
6612 /* 8164 */ "movl $\x02, $\x03, $\x01\0"
6613 /* 8180 */ "movul $\x02, $\x03, $\x01\0"
6614 /* 8197 */ "movlg $\x02, $\x03, $\x01\0"
6615 /* 8214 */ "movne $\x02, $\x03, $\x01\0"
6616 /* 8231 */ "move $\x02, $\x03, $\x01\0"
6617 /* 8247 */ "movue $\x02, $\x03, $\x01\0"
6618 /* 8264 */ "movge $\x02, $\x03, $\x01\0"
6619 /* 8281 */ "movuge $\x02, $\x03, $\x01\0"
6620 /* 8299 */ "movle $\x02, $\x03, $\x01\0"
6621 /* 8316 */ "movule $\x02, $\x03, $\x01\0"
6622 /* 8334 */ "movo $\x02, $\x03, $\x01\0"
6623 /* 8350 */ "pause $\x03\0"
6624 ;
6625
6626#ifndef NDEBUG
6627 static struct SortCheck {
6628 SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
6629 assert(std::is_sorted(
6630 OpToPatterns.begin(), OpToPatterns.end(),
6631 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
6632 return L.Opcode < R.Opcode;
6633 }) &&
6634 "tablegen failed to sort opcode patterns");
6635 }
6636 } sortCheckVar(OpToPatterns);
6637#endif
6638
6639 AliasMatchingData M {
6640 .OpToPatterns: ArrayRef(OpToPatterns),
6641 .Patterns: ArrayRef(Patterns),
6642 .PatternConds: ArrayRef(Conds),
6643 .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)),
6644 .ValidateMCOperand: nullptr,
6645 };
6646 const char *AsmString = matchAliasPatterns(MI, STI: &STI, M);
6647 if (!AsmString) return false;
6648
6649 unsigned I = 0;
6650 while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
6651 AsmString[I] != '$' && AsmString[I] != '\0')
6652 ++I;
6653 OS << '\t' << StringRef(AsmString, I);
6654 if (AsmString[I] != '\0') {
6655 if (AsmString[I] == ' ' || AsmString[I] == '\t') {
6656 OS << '\t';
6657 ++I;
6658 }
6659 do {
6660 if (AsmString[I] == '$') {
6661 ++I;
6662 if (AsmString[I] == (char)0xff) {
6663 ++I;
6664 int OpIdx = AsmString[I++] - 1;
6665 int PrintMethodIdx = AsmString[I++] - 1;
6666 printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS);
6667 } else
6668 printOperand(MI, opNum: unsigned(AsmString[I++]) - 1, STI, OS);
6669 } else {
6670 OS << AsmString[I++];
6671 }
6672 } while (AsmString[I] != '\0');
6673 }
6674
6675 return true;
6676}
6677
6678void SparcInstPrinter::printCustomAliasOperand(
6679 const MCInst *MI, uint64_t Address, unsigned OpIdx,
6680 unsigned PrintMethodIdx,
6681 const MCSubtargetInfo &STI,
6682 raw_ostream &OS) {
6683 switch (PrintMethodIdx) {
6684 default:
6685 llvm_unreachable("Unknown PrintMethod kind");
6686 break;
6687 case 0:
6688 printCTILabel(MI, Address, OpNum: OpIdx, STI, O&: OS);
6689 break;
6690 }
6691}
6692
6693#endif // PRINT_ALIAS_INSTR
6694