1//===- PhiElimination.cpp - Eliminate PHI nodes by inserting copies -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass eliminates machine instruction PHI nodes by inserting copy
10// instructions. This destroys SSA information, but is the desired input for
11// some register allocators.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/PHIElimination.h"
16#include "PHIEliminationUtils.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/SmallPtrSet.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/Analysis/LoopInfo.h"
21#include "llvm/CodeGen/LiveInterval.h"
22#include "llvm/CodeGen/LiveIntervals.h"
23#include "llvm/CodeGen/LiveVariables.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineDomTreeUpdater.h"
26#include "llvm/CodeGen/MachineDominators.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineInstr.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineLoopInfo.h"
32#include "llvm/CodeGen/MachineOperand.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/CodeGen/SlotIndexes.h"
35#include "llvm/CodeGen/TargetInstrInfo.h"
36#include "llvm/CodeGen/TargetOpcodes.h"
37#include "llvm/CodeGen/TargetRegisterInfo.h"
38#include "llvm/CodeGen/TargetSubtargetInfo.h"
39#include "llvm/Pass.h"
40#include "llvm/Support/CommandLine.h"
41#include "llvm/Support/Debug.h"
42#include "llvm/Support/raw_ostream.h"
43#include <cassert>
44#include <iterator>
45#include <utility>
46
47using namespace llvm;
48
49#define DEBUG_TYPE "phi-node-elimination"
50
51static cl::opt<bool>
52 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(Val: false),
53 cl::Hidden,
54 cl::desc("Disable critical edge splitting "
55 "during PHI elimination"));
56
57static cl::opt<bool>
58 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(Val: false),
59 cl::Hidden,
60 cl::desc("Split all critical edges during "
61 "PHI elimination"));
62
63static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
64 "no-phi-elim-live-out-early-exit", cl::init(Val: false), cl::Hidden,
65 cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
66
67namespace {
68
69class PHIEliminationImpl {
70 MachineRegisterInfo *MRI = nullptr; // Machine register information
71 LiveVariables *LV = nullptr;
72 LiveIntervals *LIS = nullptr;
73 MachineLoopInfo *MLI = nullptr;
74 MachineDominatorTree *MDT = nullptr;
75
76 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
77 /// in predecessor basic blocks.
78 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
79
80 void LowerPHINode(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator LastPHIIt,
82 bool AllEdgesCritical);
83
84 /// analyzePHINodes - Gather information about the PHI nodes in
85 /// here. In particular, we want to map the number of uses of a virtual
86 /// register which is used in a PHI node. We map that to the BB the
87 /// vreg is coming from. This is used later to determine when the vreg
88 /// is killed in the BB.
89 void analyzePHINodes(const MachineFunction &MF);
90
91 /// Split critical edges where necessary for good coalescer performance.
92 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
93 MachineLoopInfo *MLI,
94 std::vector<SparseBitVector<>> *LiveInSets,
95 MachineDomTreeUpdater &MDTU);
96
97 // These functions are temporary abstractions around LiveVariables and
98 // LiveIntervals, so they can go away when LiveVariables does.
99 bool isLiveIn(Register Reg, const MachineBasicBlock *MBB);
100 bool isLiveOutPastPHIs(Register Reg, const MachineBasicBlock *MBB);
101
102 using BBVRegPair = std::pair<unsigned, Register>;
103 using VRegPHIUse = DenseMap<BBVRegPair, unsigned>;
104
105 // Count the number of non-undef PHI uses of each register in each BB.
106 VRegPHIUse VRegPHIUseCount;
107
108 // Defs of PHI sources which are implicit_def.
109 SmallPtrSet<MachineInstr *, 4> ImpDefs;
110
111 // Map reusable lowered PHI node -> incoming join register.
112 using LoweredPHIMap =
113 DenseMap<MachineInstr *, Register, MachineInstrExpressionTrait>;
114 LoweredPHIMap LoweredPHIs;
115
116 MachineFunctionPass *P = nullptr;
117 MachineFunctionAnalysisManager *MFAM = nullptr;
118
119public:
120 PHIEliminationImpl(MachineFunctionPass *P) : P(P) {
121 auto *LVWrapper = P->getAnalysisIfAvailable<LiveVariablesWrapperPass>();
122 auto *LISWrapper = P->getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
123 auto *MLIWrapper = P->getAnalysisIfAvailable<MachineLoopInfoWrapperPass>();
124 auto *MDTWrapper =
125 P->getAnalysisIfAvailable<MachineDominatorTreeWrapperPass>();
126 LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
127 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
128 MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;
129 MDT = MDTWrapper ? &MDTWrapper->getDomTree() : nullptr;
130 }
131
132 PHIEliminationImpl(MachineFunction &MF, MachineFunctionAnalysisManager &AM)
133 : LV(AM.getCachedResult<LiveVariablesAnalysis>(IR&: MF)),
134 LIS(AM.getCachedResult<LiveIntervalsAnalysis>(IR&: MF)),
135 MLI(AM.getCachedResult<MachineLoopAnalysis>(IR&: MF)),
136 MDT(AM.getCachedResult<MachineDominatorTreeAnalysis>(IR&: MF)), MFAM(&AM) {}
137
138 bool run(MachineFunction &MF);
139};
140
141class PHIElimination : public MachineFunctionPass {
142public:
143 static char ID; // Pass identification, replacement for typeid
144
145 PHIElimination() : MachineFunctionPass(ID) {
146 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
147 }
148
149 bool runOnMachineFunction(MachineFunction &MF) override {
150 PHIEliminationImpl Impl(this);
151 return Impl.run(MF);
152 }
153
154 MachineFunctionProperties getSetProperties() const override {
155 return MachineFunctionProperties().setNoPHIs();
156 }
157
158 void getAnalysisUsage(AnalysisUsage &AU) const override;
159};
160
161} // end anonymous namespace
162
163PreservedAnalyses
164PHIEliminationPass::run(MachineFunction &MF,
165 MachineFunctionAnalysisManager &MFAM) {
166 PHIEliminationImpl Impl(MF, MFAM);
167 bool Changed = Impl.run(MF);
168 if (!Changed)
169 return PreservedAnalyses::all();
170 auto PA = getMachineFunctionPassPreservedAnalyses();
171 PA.preserve<LiveIntervalsAnalysis>();
172 PA.preserve<LiveVariablesAnalysis>();
173 PA.preserve<SlotIndexesAnalysis>();
174 PA.preserve<MachineDominatorTreeAnalysis>();
175 PA.preserve<MachineLoopAnalysis>();
176 return PA;
177}
178
179STATISTIC(NumLowered, "Number of phis lowered");
180STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
181STATISTIC(NumReused, "Number of reused lowered phis");
182
183char PHIElimination::ID = 0;
184
185char &llvm::PHIEliminationID = PHIElimination::ID;
186
187INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE,
188 "Eliminate PHI nodes for register allocation", false,
189 false)
190INITIALIZE_PASS_DEPENDENCY(LiveVariablesWrapperPass)
191INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE,
192 "Eliminate PHI nodes for register allocation", false, false)
193
194void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
195 AU.addUsedIfAvailable<LiveVariablesWrapperPass>();
196 AU.addPreserved<LiveVariablesWrapperPass>();
197 AU.addPreserved<SlotIndexesWrapperPass>();
198 AU.addPreserved<LiveIntervalsWrapperPass>();
199 AU.addPreserved<MachineDominatorTreeWrapperPass>();
200 AU.addPreserved<MachineLoopInfoWrapperPass>();
201 MachineFunctionPass::getAnalysisUsage(AU);
202}
203
204bool PHIEliminationImpl::run(MachineFunction &MF) {
205 MRI = &MF.getRegInfo();
206
207 MachineDominatorTree *MDT = nullptr;
208 if (P) {
209 auto *MDTWrapper =
210 P->getAnalysisIfAvailable<MachineDominatorTreeWrapperPass>();
211 MDT = MDTWrapper ? &MDTWrapper->getDomTree() : nullptr;
212 } else {
213 MDT = MFAM->getCachedResult<MachineDominatorTreeAnalysis>(IR&: MF);
214 }
215 MachineDomTreeUpdater MDTU(MDT, MachineDomTreeUpdater::UpdateStrategy::Lazy);
216
217 bool Changed = false;
218
219 // Split critical edges to help the coalescer.
220 if (!DisableEdgeSplitting && (LV || LIS)) {
221 // A set of live-in regs for each MBB which is used to update LV
222 // efficiently also with large functions.
223 std::vector<SparseBitVector<>> LiveInSets;
224 if (LV) {
225 LiveInSets.resize(new_size: MF.size());
226 for (unsigned Index = 0, e = MRI->getNumVirtRegs(); Index != e; ++Index) {
227 // Set the bit for this register for each MBB where it is
228 // live-through or live-in (killed).
229 Register VirtReg = Register::index2VirtReg(Index);
230 MachineInstr *DefMI = MRI->getVRegDef(Reg: VirtReg);
231 if (!DefMI)
232 continue;
233 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg: VirtReg);
234 SparseBitVector<>::iterator AliveBlockItr = VI.AliveBlocks.begin();
235 SparseBitVector<>::iterator EndItr = VI.AliveBlocks.end();
236 while (AliveBlockItr != EndItr) {
237 unsigned BlockNum = *(AliveBlockItr++);
238 LiveInSets[BlockNum].set(Index);
239 }
240 // The register is live into an MBB in which it is killed but not
241 // defined. See comment for VarInfo in LiveVariables.h.
242 MachineBasicBlock *DefMBB = DefMI->getParent();
243 if (VI.Kills.size() > 1 ||
244 (!VI.Kills.empty() && VI.Kills.front()->getParent() != DefMBB))
245 for (auto *MI : VI.Kills)
246 LiveInSets[MI->getParent()->getNumber()].set(Index);
247 }
248 }
249
250 for (auto &MBB : MF)
251 Changed |=
252 SplitPHIEdges(MF, MBB, MLI, LiveInSets: (LV ? &LiveInSets : nullptr), MDTU);
253 }
254
255 // This pass takes the function out of SSA form.
256 MRI->leaveSSA();
257
258 // Populate VRegPHIUseCount
259 if (LV || LIS)
260 analyzePHINodes(MF);
261
262 // Eliminate PHI instructions by inserting copies into predecessor blocks.
263 for (auto &MBB : MF)
264 Changed |= EliminatePHINodes(MF, MBB);
265
266 // Remove dead IMPLICIT_DEF instructions.
267 for (MachineInstr *DefMI : ImpDefs) {
268 Register DefReg = DefMI->getOperand(i: 0).getReg();
269 if (MRI->use_nodbg_empty(RegNo: DefReg)) {
270 if (LIS)
271 LIS->RemoveMachineInstrFromMaps(MI&: *DefMI);
272 DefMI->eraseFromParent();
273 }
274 }
275
276 // Clean up the lowered PHI instructions.
277 for (auto &I : LoweredPHIs) {
278 if (LIS)
279 LIS->RemoveMachineInstrFromMaps(MI&: *I.first);
280 MF.deleteMachineInstr(MI: I.first);
281 }
282
283 LoweredPHIs.clear();
284 ImpDefs.clear();
285 VRegPHIUseCount.clear();
286
287 MF.getProperties().setNoPHIs();
288
289 return Changed;
290}
291
292/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
293/// predecessor basic blocks.
294bool PHIEliminationImpl::EliminatePHINodes(MachineFunction &MF,
295 MachineBasicBlock &MBB) {
296 if (MBB.empty() || !MBB.front().isPHI())
297 return false; // Quick exit for basic blocks without PHIs.
298
299 // Get an iterator to the last PHI node.
300 MachineBasicBlock::iterator LastPHIIt =
301 std::prev(x: MBB.SkipPHIsAndLabels(I: MBB.begin()));
302
303 // If all incoming edges are critical, we try to deduplicate identical PHIs so
304 // that we generate fewer copies. If at any edge is non-critical, we either
305 // have less than two predecessors (=> no PHIs) or a predecessor has only us
306 // as a successor (=> identical PHI node can't occur in different block).
307 bool AllEdgesCritical = MBB.pred_size() >= 2;
308 for (MachineBasicBlock *Pred : MBB.predecessors()) {
309 if (Pred->succ_size() < 2) {
310 AllEdgesCritical = false;
311 break;
312 }
313 }
314
315 while (MBB.front().isPHI())
316 LowerPHINode(MBB, LastPHIIt, AllEdgesCritical);
317
318 return true;
319}
320
321/// Return true if all defs of VirtReg are implicit-defs.
322/// This includes registers with no defs.
323static bool isImplicitlyDefined(Register VirtReg,
324 const MachineRegisterInfo &MRI) {
325 for (MachineInstr &DI : MRI.def_instructions(Reg: VirtReg))
326 if (!DI.isImplicitDef())
327 return false;
328 return true;
329}
330
331/// Return true if all sources of the phi node are implicit_def's, or undef's.
332static bool allPhiOperandsUndefined(const MachineInstr &MPhi,
333 const MachineRegisterInfo &MRI) {
334 for (unsigned I = 1, E = MPhi.getNumOperands(); I != E; I += 2) {
335 const MachineOperand &MO = MPhi.getOperand(i: I);
336 if (!isImplicitlyDefined(VirtReg: MO.getReg(), MRI) && !MO.isUndef())
337 return false;
338 }
339 return true;
340}
341/// LowerPHINode - Lower the PHI node at the top of the specified block.
342void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
343 MachineBasicBlock::iterator LastPHIIt,
344 bool AllEdgesCritical) {
345 ++NumLowered;
346
347 MachineBasicBlock::iterator AfterPHIsIt = std::next(x: LastPHIIt);
348
349 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
350 MachineInstr *MPhi = MBB.remove(I: &*MBB.begin());
351
352 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
353 Register DestReg = MPhi->getOperand(i: 0).getReg();
354 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
355 bool isDead = MPhi->getOperand(i: 0).isDead();
356
357 // Create a new register for the incoming PHI arguments.
358 MachineFunction &MF = *MBB.getParent();
359 Register IncomingReg;
360 bool EliminateNow = true; // delay elimination of nodes in LoweredPHIs
361 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
362
363 // Insert a register to register copy at the top of the current block (but
364 // after any remaining phi nodes) which copies the new incoming register
365 // into the phi node destination.
366 MachineInstr *PHICopy = nullptr;
367 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
368 if (allPhiOperandsUndefined(MPhi: *MPhi, MRI: *MRI))
369 // If all sources of a PHI node are implicit_def or undef uses, just emit an
370 // implicit_def instead of a copy.
371 PHICopy = BuildMI(BB&: MBB, I: AfterPHIsIt, MIMD: MPhi->getDebugLoc(),
372 MCID: TII->get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg);
373 else {
374 // Can we reuse an earlier PHI node? This only happens for critical edges,
375 // typically those created by tail duplication. Typically, an identical PHI
376 // node can't occur, so avoid hashing/storing such PHIs, which is somewhat
377 // expensive.
378 Register *Entry = nullptr;
379 if (AllEdgesCritical)
380 Entry = &LoweredPHIs[MPhi];
381 if (Entry && *Entry) {
382 // An identical PHI node was already lowered. Reuse the incoming register.
383 IncomingReg = *Entry;
384 reusedIncoming = true;
385 ++NumReused;
386 LLVM_DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for "
387 << *MPhi);
388 } else {
389 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg: DestReg);
390 IncomingReg = MF.getRegInfo().createVirtualRegister(RegClass: RC);
391 if (Entry) {
392 EliminateNow = false;
393 *Entry = IncomingReg;
394 }
395 }
396
397 // Give the target possiblity to handle special cases fallthrough otherwise
398 PHICopy = TII->createPHIDestinationCopy(
399 MBB, InsPt: AfterPHIsIt, DL: MPhi->getDebugLoc(), Src: IncomingReg, Dst: DestReg);
400 }
401
402 if (MPhi->peekDebugInstrNum()) {
403 // If referred to by debug-info, store where this PHI was.
404 MachineFunction *MF = MBB.getParent();
405 unsigned ID = MPhi->peekDebugInstrNum();
406 auto P = MachineFunction::DebugPHIRegallocPos(&MBB, IncomingReg, 0);
407 auto Res = MF->DebugPHIPositions.insert(KV: {ID, P});
408 assert(Res.second);
409 (void)Res;
410 }
411
412 // Update live variable information if there is any.
413 if (LV) {
414 if (IncomingReg) {
415 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg: IncomingReg);
416
417 MachineInstr *OldKill = nullptr;
418 bool IsPHICopyAfterOldKill = false;
419
420 if (reusedIncoming && (OldKill = VI.findKill(MBB: &MBB))) {
421 // Calculate whether the PHICopy is after the OldKill.
422 // In general, the PHICopy is inserted as the first non-phi instruction
423 // by default, so it's before the OldKill. But some Target hooks for
424 // createPHIDestinationCopy() may modify the default insert position of
425 // PHICopy.
426 for (auto I = MBB.SkipPHIsAndLabels(I: MBB.begin()), E = MBB.end(); I != E;
427 ++I) {
428 if (I == PHICopy)
429 break;
430
431 if (I == OldKill) {
432 IsPHICopyAfterOldKill = true;
433 break;
434 }
435 }
436 }
437
438 // When we are reusing the incoming register and it has been marked killed
439 // by OldKill, if the PHICopy is after the OldKill, we should remove the
440 // killed flag from OldKill.
441 if (IsPHICopyAfterOldKill) {
442 LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill);
443 LV->removeVirtualRegisterKilled(Reg: IncomingReg, MI&: *OldKill);
444 LLVM_DEBUG(MBB.dump());
445 }
446
447 // Add information to LiveVariables to know that the first used incoming
448 // value or the resued incoming value whose PHICopy is after the OldKIll
449 // is killed. Note that because the value is defined in several places
450 // (once each for each incoming block), the "def" block and instruction
451 // fields for the VarInfo is not filled in.
452 if (!OldKill || IsPHICopyAfterOldKill)
453 LV->addVirtualRegisterKilled(IncomingReg, MI&: *PHICopy);
454 }
455
456 // Since we are going to be deleting the PHI node, if it is the last use of
457 // any registers, or if the value itself is dead, we need to move this
458 // information over to the new copy we just inserted.
459 LV->removeVirtualRegistersKilled(MI&: *MPhi);
460
461 // If the result is dead, update LV.
462 if (isDead) {
463 LV->addVirtualRegisterDead(IncomingReg: DestReg, MI&: *PHICopy);
464 LV->removeVirtualRegisterDead(Reg: DestReg, MI&: *MPhi);
465 }
466 }
467
468 // Update LiveIntervals for the new copy or implicit def.
469 if (LIS) {
470 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(MI&: *PHICopy);
471
472 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(mbb: &MBB);
473 if (IncomingReg) {
474 // Add the region from the beginning of MBB to the copy instruction to
475 // IncomingReg's live interval.
476 LiveInterval &IncomingLI = LIS->getOrCreateEmptyInterval(Reg: IncomingReg);
477 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(Idx: MBBStartIndex);
478 if (!IncomingVNI)
479 IncomingVNI =
480 IncomingLI.getNextValue(Def: MBBStartIndex, VNInfoAllocator&: LIS->getVNInfoAllocator());
481 IncomingLI.addSegment(S: LiveInterval::Segment(
482 MBBStartIndex, DestCopyIndex.getRegSlot(), IncomingVNI));
483 }
484
485 LiveInterval &DestLI = LIS->getInterval(Reg: DestReg);
486 assert(!DestLI.empty() && "PHIs should have non-empty LiveIntervals.");
487
488 SlotIndex NewStart = DestCopyIndex.getRegSlot();
489
490 SmallVector<LiveRange *> ToUpdate({&DestLI});
491 for (auto &SR : DestLI.subranges())
492 ToUpdate.push_back(Elt: &SR);
493
494 for (auto LR : ToUpdate) {
495 auto DestSegment = LR->find(Pos: MBBStartIndex);
496 assert(DestSegment != LR->end() &&
497 "PHI destination must be live in block");
498
499 if (LR->endIndex().isDead()) {
500 // A dead PHI's live range begins and ends at the start of the MBB, but
501 // the lowered copy, which will still be dead, needs to begin and end at
502 // the copy instruction.
503 VNInfo *OrigDestVNI = LR->getVNInfoAt(Idx: DestSegment->start);
504 assert(OrigDestVNI && "PHI destination should be live at block entry.");
505 LR->removeSegment(Start: DestSegment->start, End: DestSegment->start.getDeadSlot());
506 LR->createDeadDef(Def: NewStart, VNIAlloc&: LIS->getVNInfoAllocator());
507 LR->removeValNo(ValNo: OrigDestVNI);
508 continue;
509 }
510
511 // Destination copies are not inserted in the same order as the PHI nodes
512 // they replace. Hence the start of the live range may need to be adjusted
513 // to match the actual slot index of the copy.
514 if (DestSegment->start > NewStart) {
515 VNInfo *VNI = LR->getVNInfoAt(Idx: DestSegment->start);
516 assert(VNI && "value should be defined for known segment");
517 LR->addSegment(
518 S: LiveInterval::Segment(NewStart, DestSegment->start, VNI));
519 } else if (DestSegment->start < NewStart) {
520 assert(DestSegment->start >= MBBStartIndex);
521 assert(DestSegment->end >= DestCopyIndex.getRegSlot());
522 LR->removeSegment(Start: DestSegment->start, End: NewStart);
523 }
524 VNInfo *DestVNI = LR->getVNInfoAt(Idx: NewStart);
525 assert(DestVNI && "PHI destination should be live at its definition.");
526 DestVNI->def = NewStart;
527 }
528 }
529
530 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
531 if (LV || LIS) {
532 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
533 if (!MPhi->getOperand(i).isUndef()) {
534 --VRegPHIUseCount[BBVRegPair(
535 MPhi->getOperand(i: i + 1).getMBB()->getNumber(),
536 MPhi->getOperand(i).getReg())];
537 }
538 }
539 }
540
541 // Now loop over all of the incoming arguments, changing them to copy into the
542 // IncomingReg register in the corresponding predecessor basic block.
543 SmallPtrSet<MachineBasicBlock *, 8> MBBsInsertedInto;
544 for (int i = NumSrcs - 1; i >= 0; --i) {
545 Register SrcReg = MPhi->getOperand(i: i * 2 + 1).getReg();
546 unsigned SrcSubReg = MPhi->getOperand(i: i * 2 + 1).getSubReg();
547 bool SrcUndef = MPhi->getOperand(i: i * 2 + 1).isUndef() ||
548 isImplicitlyDefined(VirtReg: SrcReg, MRI: *MRI);
549 assert(SrcReg.isVirtual() &&
550 "Machine PHI Operands must all be virtual registers!");
551
552 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
553 // path the PHI.
554 MachineBasicBlock &opBlock = *MPhi->getOperand(i: i * 2 + 2).getMBB();
555
556 // Check to make sure we haven't already emitted the copy for this block.
557 // This can happen because PHI nodes may have multiple entries for the same
558 // basic block.
559 if (!MBBsInsertedInto.insert(Ptr: &opBlock).second)
560 continue; // If the copy has already been emitted, we're done.
561
562 MachineInstr *SrcRegDef = MRI->getVRegDef(Reg: SrcReg);
563 if (SrcRegDef && TII->isUnspillableTerminator(MI: SrcRegDef)) {
564 assert(SrcRegDef->getOperand(0).isReg() &&
565 SrcRegDef->getOperand(0).isDef() &&
566 "Expected operand 0 to be a reg def!");
567 // Now that the PHI's use has been removed (as the instruction was
568 // removed) there should be no other uses of the SrcReg.
569 assert(MRI->use_empty(SrcReg) &&
570 "Expected a single use from UnspillableTerminator");
571 SrcRegDef->getOperand(i: 0).setReg(IncomingReg);
572
573 // Update LiveVariables.
574 if (LV) {
575 LiveVariables::VarInfo &SrcVI = LV->getVarInfo(Reg: SrcReg);
576 LiveVariables::VarInfo &IncomingVI = LV->getVarInfo(Reg: IncomingReg);
577 IncomingVI.AliveBlocks = std::move(SrcVI.AliveBlocks);
578 SrcVI.AliveBlocks.clear();
579 }
580
581 continue;
582 }
583
584 // Find a safe location to insert the copy, this may be the first terminator
585 // in the block (or end()).
586 MachineBasicBlock::iterator InsertPos =
587 findPHICopyInsertPoint(MBB: &opBlock, SuccMBB: &MBB, SrcReg);
588
589 // Insert the copy.
590 MachineInstr *NewSrcInstr = nullptr;
591 if (!reusedIncoming && IncomingReg) {
592 if (SrcUndef) {
593 // The source register is undefined, so there is no need for a real
594 // COPY, but we still need to ensure joint dominance by defs.
595 // Insert an IMPLICIT_DEF instruction.
596 NewSrcInstr =
597 BuildMI(BB&: opBlock, I: InsertPos, MIMD: MPhi->getDebugLoc(),
598 MCID: TII->get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: IncomingReg);
599
600 // Clean up the old implicit-def, if there even was one.
601 if (MachineInstr *DefMI = MRI->getVRegDef(Reg: SrcReg))
602 if (DefMI->isImplicitDef())
603 ImpDefs.insert(Ptr: DefMI);
604 } else {
605 // Delete the debug location, since the copy is inserted into a
606 // different basic block.
607 NewSrcInstr = TII->createPHISourceCopy(MBB&: opBlock, InsPt: InsertPos, DL: nullptr,
608 Src: SrcReg, SrcSubReg, Dst: IncomingReg);
609 }
610 }
611
612 // We only need to update the LiveVariables kill of SrcReg if this was the
613 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
614 // out of the predecessor. We can also ignore undef sources.
615 if (LV && !SrcUndef &&
616 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
617 !LV->isLiveOut(Reg: SrcReg, MBB: opBlock)) {
618 // We want to be able to insert a kill of the register if this PHI (aka,
619 // the copy we just inserted) is the last use of the source value. Live
620 // variable analysis conservatively handles this by saying that the value
621 // is live until the end of the block the PHI entry lives in. If the value
622 // really is dead at the PHI copy, there will be no successor blocks which
623 // have the value live-in.
624
625 // Okay, if we now know that the value is not live out of the block, we
626 // can add a kill marker in this block saying that it kills the incoming
627 // value!
628
629 // In our final twist, we have to decide which instruction kills the
630 // register. In most cases this is the copy, however, terminator
631 // instructions at the end of the block may also use the value. In this
632 // case, we should mark the last such terminator as being the killing
633 // block, not the copy.
634 MachineBasicBlock::iterator KillInst = opBlock.end();
635 for (MachineBasicBlock::iterator Term = InsertPos; Term != opBlock.end();
636 ++Term) {
637 if (Term->readsRegister(Reg: SrcReg, /*TRI=*/nullptr))
638 KillInst = Term;
639 }
640
641 if (KillInst == opBlock.end()) {
642 // No terminator uses the register.
643
644 if (reusedIncoming || !IncomingReg) {
645 // We may have to rewind a bit if we didn't insert a copy this time.
646 KillInst = InsertPos;
647 while (KillInst != opBlock.begin()) {
648 --KillInst;
649 if (KillInst->isDebugInstr())
650 continue;
651 if (KillInst->readsRegister(Reg: SrcReg, /*TRI=*/nullptr))
652 break;
653 }
654 } else {
655 // We just inserted this copy.
656 KillInst = NewSrcInstr;
657 }
658 }
659 assert(KillInst->readsRegister(SrcReg, /*TRI=*/nullptr) &&
660 "Cannot find kill instruction");
661
662 // Finally, mark it killed.
663 LV->addVirtualRegisterKilled(IncomingReg: SrcReg, MI&: *KillInst);
664
665 // This vreg no longer lives all of the way through opBlock.
666 unsigned opBlockNum = opBlock.getNumber();
667 LV->getVarInfo(Reg: SrcReg).AliveBlocks.reset(Idx: opBlockNum);
668 }
669
670 if (LIS) {
671 if (NewSrcInstr) {
672 LIS->InsertMachineInstrInMaps(MI&: *NewSrcInstr);
673 LIS->addSegmentToEndOfBlock(Reg: IncomingReg, startInst&: *NewSrcInstr);
674 }
675
676 if (!SrcUndef &&
677 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
678 LiveInterval &SrcLI = LIS->getInterval(Reg: SrcReg);
679
680 bool isLiveOut = false;
681 for (MachineBasicBlock *Succ : opBlock.successors()) {
682 SlotIndex startIdx = LIS->getMBBStartIdx(mbb: Succ);
683 VNInfo *VNI = SrcLI.getVNInfoAt(Idx: startIdx);
684
685 // Definitions by other PHIs are not truly live-in for our purposes.
686 if (VNI && VNI->def != startIdx) {
687 isLiveOut = true;
688 break;
689 }
690 }
691
692 if (!isLiveOut) {
693 MachineBasicBlock::iterator KillInst = opBlock.end();
694 for (MachineBasicBlock::iterator Term = InsertPos;
695 Term != opBlock.end(); ++Term) {
696 if (Term->readsRegister(Reg: SrcReg, /*TRI=*/nullptr))
697 KillInst = Term;
698 }
699
700 if (KillInst == opBlock.end()) {
701 // No terminator uses the register.
702
703 if (reusedIncoming || !IncomingReg) {
704 // We may have to rewind a bit if we didn't just insert a copy.
705 KillInst = InsertPos;
706 while (KillInst != opBlock.begin()) {
707 --KillInst;
708 if (KillInst->isDebugInstr())
709 continue;
710 if (KillInst->readsRegister(Reg: SrcReg, /*TRI=*/nullptr))
711 break;
712 }
713 } else {
714 // We just inserted this copy.
715 KillInst = std::prev(x: InsertPos);
716 }
717 }
718 assert(KillInst->readsRegister(SrcReg, /*TRI=*/nullptr) &&
719 "Cannot find kill instruction");
720
721 SlotIndex LastUseIndex = LIS->getInstructionIndex(Instr: *KillInst);
722 SrcLI.removeSegment(Start: LastUseIndex.getRegSlot(),
723 End: LIS->getMBBEndIdx(mbb: &opBlock));
724 for (auto &SR : SrcLI.subranges()) {
725 SR.removeSegment(Start: LastUseIndex.getRegSlot(),
726 End: LIS->getMBBEndIdx(mbb: &opBlock));
727 }
728 }
729 }
730 }
731 }
732
733 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
734 if (EliminateNow) {
735 if (LIS)
736 LIS->RemoveMachineInstrFromMaps(MI&: *MPhi);
737 MF.deleteMachineInstr(MI: MPhi);
738 }
739}
740
741/// analyzePHINodes - Gather information about the PHI nodes in here. In
742/// particular, we want to map the number of uses of a virtual register which is
743/// used in a PHI node. We map that to the BB the vreg is coming from. This is
744/// used later to determine when the vreg is killed in the BB.
745void PHIEliminationImpl::analyzePHINodes(const MachineFunction &MF) {
746 for (const auto &MBB : MF) {
747 for (const auto &BBI : MBB) {
748 if (!BBI.isPHI())
749 break;
750 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
751 if (!BBI.getOperand(i).isUndef()) {
752 ++VRegPHIUseCount[BBVRegPair(
753 BBI.getOperand(i: i + 1).getMBB()->getNumber(),
754 BBI.getOperand(i).getReg())];
755 }
756 }
757 }
758 }
759}
760
761bool PHIEliminationImpl::SplitPHIEdges(
762 MachineFunction &MF, MachineBasicBlock &MBB, MachineLoopInfo *MLI,
763 std::vector<SparseBitVector<>> *LiveInSets, MachineDomTreeUpdater &MDTU) {
764 if (MBB.empty() || !MBB.front().isPHI() || MBB.isEHPad())
765 return false; // Quick exit for basic blocks without PHIs.
766
767 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(BB: &MBB) : nullptr;
768 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
769
770 bool Changed = false;
771 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
772 BBI != BBE && BBI->isPHI(); ++BBI) {
773 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
774 Register Reg = BBI->getOperand(i).getReg();
775 MachineBasicBlock *PreMBB = BBI->getOperand(i: i + 1).getMBB();
776 // Is there a critical edge from PreMBB to MBB?
777 if (PreMBB->succ_size() == 1)
778 continue;
779
780 // Avoid splitting backedges of loops. It would introduce small
781 // out-of-line blocks into the loop which is very bad for code placement.
782 if (PreMBB == &MBB && !SplitAllCriticalEdges)
783 continue;
784 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(BB: PreMBB) : nullptr;
785 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
786 continue;
787
788 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
789 // when the source register is live-out for some other reason than a phi
790 // use. That means the copy we will insert in PreMBB won't be a kill, and
791 // there is a risk it may not be coalesced away.
792 //
793 // If the copy would be a kill, there is no need to split the edge.
794 bool ShouldSplit = isLiveOutPastPHIs(Reg, MBB: PreMBB);
795 if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
796 continue;
797 if (ShouldSplit) {
798 LLVM_DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
799 << printMBBReference(*PreMBB) << " -> "
800 << printMBBReference(MBB) << ": " << *BBI);
801 }
802
803 // If Reg is not live-in to MBB, it means it must be live-in to some
804 // other PreMBB successor, and we can avoid the interference by splitting
805 // the edge.
806 //
807 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
808 // is likely to be left after coalescing. If we are looking at a loop
809 // exiting edge, split it so we won't insert code in the loop, otherwise
810 // don't bother.
811 ShouldSplit = ShouldSplit && !isLiveIn(Reg, MBB: &MBB);
812
813 // Check for a loop exiting edge.
814 if (!ShouldSplit && CurLoop != PreLoop) {
815 LLVM_DEBUG({
816 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
817 if (PreLoop)
818 dbgs() << "PreLoop: " << *PreLoop;
819 if (CurLoop)
820 dbgs() << "CurLoop: " << *CurLoop;
821 });
822 // This edge could be entering a loop, exiting a loop, or it could be
823 // both: Jumping directly form one loop to the header of a sibling
824 // loop.
825 // Split unless this edge is entering CurLoop from an outer loop.
826 ShouldSplit = PreLoop && !PreLoop->contains(L: CurLoop);
827 }
828 if (!ShouldSplit && !SplitAllCriticalEdges)
829 continue;
830 if (!(P ? PreMBB->SplitCriticalEdge(Succ: &MBB, P&: *P, LiveInSets, MDTU: &MDTU)
831 : PreMBB->SplitCriticalEdge(Succ: &MBB, MFAM&: *MFAM, LiveInSets, MDTU: &MDTU))) {
832 LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n");
833 continue;
834 }
835 Changed = true;
836 ++NumCriticalEdgesSplit;
837 }
838 }
839 return Changed;
840}
841
842bool PHIEliminationImpl::isLiveIn(Register Reg, const MachineBasicBlock *MBB) {
843 assert((LV || LIS) &&
844 "isLiveIn() requires either LiveVariables or LiveIntervals");
845 if (LIS)
846 return LIS->isLiveInToMBB(LR: LIS->getInterval(Reg), mbb: MBB);
847 else
848 return LV->isLiveIn(Reg, MBB: *MBB);
849}
850
851bool PHIEliminationImpl::isLiveOutPastPHIs(Register Reg,
852 const MachineBasicBlock *MBB) {
853 assert((LV || LIS) &&
854 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
855 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
856 // so that a register used only in a PHI is not live out of the block. In
857 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather
858 // than in the predecessor basic block, so that a register used only in a PHI
859 // is live out of the block.
860 if (LIS) {
861 const LiveInterval &LI = LIS->getInterval(Reg);
862 for (const MachineBasicBlock *SI : MBB->successors())
863 if (LI.liveAt(index: LIS->getMBBStartIdx(mbb: SI)))
864 return true;
865 return false;
866 } else {
867 return LV->isLiveOut(Reg, MBB: *MBB);
868 }
869}
870