1//===- RegAllocBase.h - basic regalloc interface and driver -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the RegAllocBase class, which is the skeleton of a basic
10// register allocation algorithm and interface for extending it. It provides the
11// building blocks on which to construct other experimental allocators and test
12// the validity of two principles:
13//
14// - If virtual and physical register liveness is modeled using intervals, then
15// on-the-fly interference checking is cheap. Furthermore, interferences can be
16// lazily cached and reused.
17//
18// - Register allocation complexity, and generated code performance is
19// determined by the effectiveness of live range splitting rather than optimal
20// coloring.
21//
22// Following the first principle, interfering checking revolves around the
23// LiveIntervalUnion data structure.
24//
25// To fulfill the second principle, the basic allocator provides a driver for
26// incremental splitting. It essentially punts on the problem of register
27// coloring, instead driving the assignment of virtual to physical registers by
28// the cost of splitting. The basic allocator allows for heuristic reassignment
29// of registers, if a more sophisticated allocator chooses to do that.
30//
31// This framework provides a way to engineer the compile time vs. code
32// quality trade-off without relying on a particular theoretical solver.
33//
34//===----------------------------------------------------------------------===//
35
36#ifndef LLVM_LIB_CODEGEN_REGALLOCBASE_H
37#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
38
39#include "llvm/ADT/SmallPtrSet.h"
40#include "llvm/ADT/SmallSet.h"
41#include "llvm/CodeGen/MachineRegisterInfo.h"
42#include "llvm/CodeGen/RegAllocCommon.h"
43#include "llvm/CodeGen/RegisterClassInfo.h"
44
45namespace llvm {
46
47class LiveInterval;
48class LiveIntervals;
49class LiveRegMatrix;
50class MachineInstr;
51class MachineRegisterInfo;
52template<typename T> class SmallVectorImpl;
53class Spiller;
54class TargetRegisterInfo;
55class VirtRegMap;
56
57/// RegAllocBase provides the register allocation driver and interface that can
58/// be extended to add interesting heuristics.
59///
60/// Register allocators must override the selectOrSplit() method to implement
61/// live range splitting. They must also override enqueue/dequeue to provide an
62/// assignment order.
63class RegAllocBase {
64 virtual void anchor();
65
66protected:
67 const TargetRegisterInfo *TRI = nullptr;
68 MachineRegisterInfo *MRI = nullptr;
69 VirtRegMap *VRM = nullptr;
70 LiveIntervals *LIS = nullptr;
71 LiveRegMatrix *Matrix = nullptr;
72 RegisterClassInfo RegClassInfo;
73
74private:
75 /// Private, callees should go through shouldAllocateRegister
76 const RegAllocFilterFunc shouldAllocateRegisterImpl;
77
78protected:
79 /// Inst which is a def of an original reg and whose defs are already all
80 /// dead after remat is saved in DeadRemats. The deletion of such inst is
81 /// postponed till all the allocations are done, so its remat expr is
82 /// always available for the remat of all the siblings of the original reg.
83 SmallPtrSet<MachineInstr *, 32> DeadRemats;
84
85 SmallSet<Register, 2> FailedVRegs;
86 RegAllocBase(const RegAllocFilterFunc F = nullptr)
87 : shouldAllocateRegisterImpl(F) {}
88
89 virtual ~RegAllocBase() = default;
90
91 // A RegAlloc pass should call this before allocatePhysRegs.
92 void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
93
94 /// Get whether a given register should be allocated
95 bool shouldAllocateRegister(Register Reg) {
96 if (!shouldAllocateRegisterImpl)
97 return true;
98 return shouldAllocateRegisterImpl(*TRI, *MRI, Reg);
99 }
100
101 // The top-level driver. The output is a VirtRegMap that us updated with
102 // physical register assignments.
103 void allocatePhysRegs();
104
105 // Include spiller post optimization and removing dead defs left because of
106 // rematerialization.
107 virtual void postOptimization();
108
109 /// Perform cleanups on registers that failed to allocate. This hacks on the
110 /// liveness in order to avoid spurious verifier errors in later passes.
111 void cleanupFailedVReg(Register FailedVReg, MCRegister PhysReg,
112 SmallVectorImpl<Register> &SplitRegs);
113
114 // Get a temporary reference to a Spiller instance.
115 virtual Spiller &spiller() = 0;
116
117 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
118 virtual void enqueueImpl(const LiveInterval *LI) = 0;
119
120 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
121 void enqueue(const LiveInterval *LI);
122
123 /// dequeue - Return the next unassigned register, or NULL.
124 virtual const LiveInterval *dequeue() = 0;
125
126 // A RegAlloc pass should override this to provide the allocation heuristics.
127 // Each call must guarantee forward progess by returning an available PhysReg
128 // or new set of split live virtual registers. It is up to the splitter to
129 // converge quickly toward fully spilled live ranges.
130 virtual MCRegister selectOrSplit(const LiveInterval &VirtReg,
131 SmallVectorImpl<Register> &splitLVRs) = 0;
132
133 /// Query a physical register to use as a filler in contexts where the
134 /// allocation has failed. This will raise an error, but not abort the
135 /// compilation.
136 MCPhysReg getErrorAssignment(const TargetRegisterClass &RC,
137 const MachineInstr *CtxMI = nullptr);
138
139 // Use this group name for NamedRegionTimer.
140 static const char TimerGroupName[];
141 static const char TimerGroupDescription[];
142
143 /// Method called when the allocator is about to remove a LiveInterval.
144 virtual void aboutToRemoveInterval(const LiveInterval &LI) {}
145
146public:
147 /// VerifyEnabled - True when -verify-regalloc is given.
148 static bool VerifyEnabled;
149
150private:
151 void seedLiveRegs();
152};
153
154} // end namespace llvm
155
156#endif // LLVM_LIB_CODEGEN_REGALLOCBASE_H
157