1//===- TwoAddressInstructionPass.cpp - Two-Address instruction pass -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the TwoAddress instruction pass which is used
10// by most register allocators. Two-Address instructions are rewritten
11// from:
12//
13// A = B op C
14//
15// to:
16//
17// A = B
18// A op= C
19//
20// Note that if a register allocator chooses to use this pass, that it
21// has to be capable of handling the non-SSA nature of these rewritten
22// virtual registers.
23//
24// It is also worth noting that the duplicate operand of the two
25// address instruction is removed.
26//
27//===----------------------------------------------------------------------===//
28
29#include "llvm/CodeGen/TwoAddressInstructionPass.h"
30#include "llvm/ADT/DenseMap.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/ADT/iterator_range.h"
35#include "llvm/Analysis/AliasAnalysis.h"
36#include "llvm/CodeGen/LiveInterval.h"
37#include "llvm/CodeGen/LiveIntervals.h"
38#include "llvm/CodeGen/LiveVariables.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineDominators.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineFunctionPass.h"
43#include "llvm/CodeGen/MachineInstr.h"
44#include "llvm/CodeGen/MachineInstrBuilder.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineOperand.h"
47#include "llvm/CodeGen/MachineRegisterInfo.h"
48#include "llvm/CodeGen/Passes.h"
49#include "llvm/CodeGen/SlotIndexes.h"
50#include "llvm/CodeGen/TargetInstrInfo.h"
51#include "llvm/CodeGen/TargetOpcodes.h"
52#include "llvm/CodeGen/TargetRegisterInfo.h"
53#include "llvm/CodeGen/TargetSubtargetInfo.h"
54#include "llvm/MC/MCInstrDesc.h"
55#include "llvm/Pass.h"
56#include "llvm/Support/CodeGen.h"
57#include "llvm/Support/CommandLine.h"
58#include "llvm/Support/Debug.h"
59#include "llvm/Support/ErrorHandling.h"
60#include "llvm/Support/raw_ostream.h"
61#include "llvm/Target/TargetMachine.h"
62#include <cassert>
63#include <iterator>
64#include <utility>
65
66using namespace llvm;
67
68#define DEBUG_TYPE "twoaddressinstruction"
69
70STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
71STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
72STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
73STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
74STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
75STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
76
77// Temporary flag to disable rescheduling.
78static cl::opt<bool>
79EnableRescheduling("twoaddr-reschedule",
80 cl::desc("Coalesce copies by rescheduling (default=true)"),
81 cl::init(Val: true), cl::Hidden);
82
83// Limit the number of dataflow edges to traverse when evaluating the benefit
84// of commuting operands.
85static cl::opt<unsigned> MaxDataFlowEdge(
86 "dataflow-edge-limit", cl::Hidden, cl::init(Val: 3),
87 cl::desc("Maximum number of dataflow edges to traverse when evaluating "
88 "the benefit of commuting operands"));
89
90namespace {
91
92class TwoAddressInstructionImpl {
93 MachineFunction *MF = nullptr;
94 const TargetInstrInfo *TII = nullptr;
95 const TargetRegisterInfo *TRI = nullptr;
96 const InstrItineraryData *InstrItins = nullptr;
97 MachineRegisterInfo *MRI = nullptr;
98 LiveVariables *LV = nullptr;
99 LiveIntervals *LIS = nullptr;
100 AliasAnalysis *AA = nullptr;
101 CodeGenOptLevel OptLevel = CodeGenOptLevel::None;
102
103 // The current basic block being processed.
104 MachineBasicBlock *MBB = nullptr;
105
106 // Keep track the distance of a MI from the start of the current basic block.
107 DenseMap<MachineInstr*, unsigned> DistanceMap;
108
109 // Set of already processed instructions in the current block.
110 SmallPtrSet<MachineInstr*, 8> Processed;
111
112 // A map from virtual registers to physical registers which are likely targets
113 // to be coalesced to due to copies from physical registers to virtual
114 // registers. e.g. v1024 = move r0.
115 DenseMap<Register, Register> SrcRegMap;
116
117 // A map from virtual registers to physical registers which are likely targets
118 // to be coalesced to due to copies to physical registers from virtual
119 // registers. e.g. r1 = move v1024.
120 DenseMap<Register, Register> DstRegMap;
121
122 MachineInstr *getSingleDef(Register Reg, MachineBasicBlock *BB) const;
123
124 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
125
126 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);
127
128 bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg,
129 bool &IsSrcPhys, bool &IsDstPhys) const;
130
131 bool isPlainlyKilled(const MachineInstr *MI, LiveRange &LR) const;
132 bool isPlainlyKilled(const MachineInstr *MI, Register Reg) const;
133 bool isPlainlyKilled(const MachineOperand &MO) const;
134
135 bool isKilled(MachineInstr &MI, Register Reg, bool allowFalsePositives) const;
136
137 MachineInstr *findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
138 bool &IsCopy, Register &DstReg,
139 bool &IsDstPhys) const;
140
141 bool regsAreCompatible(Register RegA, Register RegB) const;
142
143 void removeMapRegEntry(const MachineOperand &MO,
144 DenseMap<Register, Register> &RegMap) const;
145
146 void removeClobberedSrcRegMap(MachineInstr *MI);
147
148 bool regOverlapsSet(const SmallVectorImpl<Register> &Set, Register Reg) const;
149
150 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
151 MachineInstr *MI, unsigned Dist);
152
153 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
154 unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);
155
156 bool isProfitableToConv3Addr(Register RegA, Register RegB);
157
158 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
159 MachineBasicBlock::iterator &nmi, Register RegA,
160 Register RegB, unsigned &Dist);
161
162 bool isDefTooClose(Register Reg, unsigned Dist, MachineInstr *MI);
163
164 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
165 MachineBasicBlock::iterator &nmi, Register Reg);
166 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
167 MachineBasicBlock::iterator &nmi, Register Reg);
168
169 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
170 MachineBasicBlock::iterator &nmi,
171 unsigned SrcIdx, unsigned DstIdx,
172 unsigned &Dist, bool shouldOnlyCommute);
173
174 bool tryInstructionCommute(MachineInstr *MI,
175 unsigned DstOpIdx,
176 unsigned BaseOpIdx,
177 bool BaseOpKilled,
178 unsigned Dist);
179 void scanUses(Register DstReg);
180
181 void processCopy(MachineInstr *MI);
182
183 using TiedPairList = SmallVector<std::pair<unsigned, unsigned>, 4>;
184 using TiedOperandMap = SmallDenseMap<Register, TiedPairList>;
185
186 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
187 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
188 void eliminateRegSequence(MachineBasicBlock::iterator&);
189 bool processStatepoint(MachineInstr *MI, TiedOperandMap &TiedOperands);
190
191public:
192 TwoAddressInstructionImpl(MachineFunction &MF, MachineFunctionPass *P);
193 TwoAddressInstructionImpl(MachineFunction &MF,
194 MachineFunctionAnalysisManager &MFAM);
195 void setOptLevel(CodeGenOptLevel Level) { OptLevel = Level; }
196 bool run();
197};
198
199class TwoAddressInstructionLegacyPass : public MachineFunctionPass {
200public:
201 static char ID; // Pass identification, replacement for typeid
202
203 TwoAddressInstructionLegacyPass() : MachineFunctionPass(ID) {
204 initializeTwoAddressInstructionLegacyPassPass(
205 *PassRegistry::getPassRegistry());
206 }
207
208 /// Pass entry point.
209 bool runOnMachineFunction(MachineFunction &MF) override {
210 TwoAddressInstructionImpl Impl(MF, this);
211 // Disable optimizations if requested. We cannot skip the whole pass as some
212 // fixups are necessary for correctness.
213 if (skipFunction(F: MF.getFunction()))
214 Impl.setOptLevel(CodeGenOptLevel::None);
215 return Impl.run();
216 }
217
218 void getAnalysisUsage(AnalysisUsage &AU) const override {
219 AU.setPreservesCFG();
220 AU.addUsedIfAvailable<AAResultsWrapperPass>();
221 AU.addUsedIfAvailable<LiveVariablesWrapperPass>();
222 AU.addPreserved<LiveVariablesWrapperPass>();
223 AU.addPreserved<SlotIndexesWrapperPass>();
224 AU.addPreserved<LiveIntervalsWrapperPass>();
225 AU.addPreservedID(ID&: MachineLoopInfoID);
226 AU.addPreservedID(ID&: MachineDominatorsID);
227 MachineFunctionPass::getAnalysisUsage(AU);
228 }
229};
230
231} // end anonymous namespace
232
233PreservedAnalyses
234TwoAddressInstructionPass::run(MachineFunction &MF,
235 MachineFunctionAnalysisManager &MFAM) {
236 // Disable optimizations if requested. We cannot skip the whole pass as some
237 // fixups are necessary for correctness.
238 TwoAddressInstructionImpl Impl(MF, MFAM);
239 if (MF.getFunction().hasOptNone())
240 Impl.setOptLevel(CodeGenOptLevel::None);
241
242 MFPropsModifier _(*this, MF);
243 bool Changed = Impl.run();
244 if (!Changed)
245 return PreservedAnalyses::all();
246 auto PA = getMachineFunctionPassPreservedAnalyses();
247 PA.preserve<LiveIntervalsAnalysis>();
248 PA.preserve<LiveVariablesAnalysis>();
249 PA.preserve<MachineDominatorTreeAnalysis>();
250 PA.preserve<MachineLoopAnalysis>();
251 PA.preserve<SlotIndexesAnalysis>();
252 PA.preserveSet<CFGAnalyses>();
253 return PA;
254}
255
256char TwoAddressInstructionLegacyPass::ID = 0;
257
258char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionLegacyPass::ID;
259
260INITIALIZE_PASS_BEGIN(TwoAddressInstructionLegacyPass, DEBUG_TYPE,
261 "Two-Address instruction pass", false, false)
262INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
263INITIALIZE_PASS_END(TwoAddressInstructionLegacyPass, DEBUG_TYPE,
264 "Two-Address instruction pass", false, false)
265
266TwoAddressInstructionImpl::TwoAddressInstructionImpl(
267 MachineFunction &Func, MachineFunctionAnalysisManager &MFAM)
268 : MF(&Func), TII(Func.getSubtarget().getInstrInfo()),
269 TRI(Func.getSubtarget().getRegisterInfo()),
270 InstrItins(Func.getSubtarget().getInstrItineraryData()),
271 MRI(&Func.getRegInfo()),
272 LV(MFAM.getCachedResult<LiveVariablesAnalysis>(IR&: Func)),
273 LIS(MFAM.getCachedResult<LiveIntervalsAnalysis>(IR&: Func)),
274 OptLevel(Func.getTarget().getOptLevel()) {
275 auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(IR&: Func)
276 .getManager();
277 AA = FAM.getCachedResult<AAManager>(IR&: Func.getFunction());
278}
279
280TwoAddressInstructionImpl::TwoAddressInstructionImpl(MachineFunction &Func,
281 MachineFunctionPass *P)
282 : MF(&Func), TII(Func.getSubtarget().getInstrInfo()),
283 TRI(Func.getSubtarget().getRegisterInfo()),
284 InstrItins(Func.getSubtarget().getInstrItineraryData()),
285 MRI(&Func.getRegInfo()), OptLevel(Func.getTarget().getOptLevel()) {
286 auto *LVWrapper = P->getAnalysisIfAvailable<LiveVariablesWrapperPass>();
287 LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
288 auto *LISWrapper = P->getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
289 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
290 if (auto *AAPass = P->getAnalysisIfAvailable<AAResultsWrapperPass>())
291 AA = &AAPass->getAAResults();
292 else
293 AA = nullptr;
294}
295
296/// Return the MachineInstr* if it is the single def of the Reg in current BB.
297MachineInstr *
298TwoAddressInstructionImpl::getSingleDef(Register Reg,
299 MachineBasicBlock *BB) const {
300 MachineInstr *Ret = nullptr;
301 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
302 if (DefMI.getParent() != BB || DefMI.isDebugValue())
303 continue;
304 if (!Ret)
305 Ret = &DefMI;
306 else if (Ret != &DefMI)
307 return nullptr;
308 }
309 return Ret;
310}
311
312/// Check if there is a reversed copy chain from FromReg to ToReg:
313/// %Tmp1 = copy %Tmp2;
314/// %FromReg = copy %Tmp1;
315/// %ToReg = add %FromReg ...
316/// %Tmp2 = copy %ToReg;
317/// MaxLen specifies the maximum length of the copy chain the func
318/// can walk through.
319bool TwoAddressInstructionImpl::isRevCopyChain(Register FromReg, Register ToReg,
320 int Maxlen) {
321 Register TmpReg = FromReg;
322 for (int i = 0; i < Maxlen; i++) {
323 MachineInstr *Def = getSingleDef(Reg: TmpReg, BB: MBB);
324 if (!Def || !Def->isCopy())
325 return false;
326
327 TmpReg = Def->getOperand(i: 1).getReg();
328
329 if (TmpReg == ToReg)
330 return true;
331 }
332 return false;
333}
334
335/// Return true if there are no intervening uses between the last instruction
336/// in the MBB that defines the specified register and the two-address
337/// instruction which is being processed. It also returns the last def location
338/// by reference.
339bool TwoAddressInstructionImpl::noUseAfterLastDef(Register Reg, unsigned Dist,
340 unsigned &LastDef) {
341 LastDef = 0;
342 unsigned LastUse = Dist;
343 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
344 MachineInstr *MI = MO.getParent();
345 if (MI->getParent() != MBB || MI->isDebugValue())
346 continue;
347 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(Val: MI);
348 if (DI == DistanceMap.end())
349 continue;
350 if (MO.isUse() && DI->second < LastUse)
351 LastUse = DI->second;
352 if (MO.isDef() && DI->second > LastDef)
353 LastDef = DI->second;
354 }
355
356 return !(LastUse > LastDef && LastUse < Dist);
357}
358
359/// Return true if the specified MI is a copy instruction or an extract_subreg
360/// instruction. It also returns the source and destination registers and
361/// whether they are physical registers by reference.
362bool TwoAddressInstructionImpl::isCopyToReg(MachineInstr &MI, Register &SrcReg,
363 Register &DstReg, bool &IsSrcPhys,
364 bool &IsDstPhys) const {
365 SrcReg = 0;
366 DstReg = 0;
367 if (MI.isCopy()) {
368 DstReg = MI.getOperand(i: 0).getReg();
369 SrcReg = MI.getOperand(i: 1).getReg();
370 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
371 DstReg = MI.getOperand(i: 0).getReg();
372 SrcReg = MI.getOperand(i: 2).getReg();
373 } else {
374 return false;
375 }
376
377 IsSrcPhys = SrcReg.isPhysical();
378 IsDstPhys = DstReg.isPhysical();
379 return true;
380}
381
382bool TwoAddressInstructionImpl::isPlainlyKilled(const MachineInstr *MI,
383 LiveRange &LR) const {
384 // This is to match the kill flag version where undefs don't have kill flags.
385 if (!LR.hasAtLeastOneValue())
386 return false;
387
388 SlotIndex useIdx = LIS->getInstructionIndex(Instr: *MI);
389 LiveInterval::const_iterator I = LR.find(Pos: useIdx);
390 assert(I != LR.end() && "Reg must be live-in to use.");
391 return !I->end.isBlock() && SlotIndex::isSameInstr(A: I->end, B: useIdx);
392}
393
394/// Test if the given register value, which is used by the
395/// given instruction, is killed by the given instruction.
396bool TwoAddressInstructionImpl::isPlainlyKilled(const MachineInstr *MI,
397 Register Reg) const {
398 // FIXME: Sometimes tryInstructionTransform() will add instructions and
399 // test whether they can be folded before keeping them. In this case it
400 // sets a kill before recursively calling tryInstructionTransform() again.
401 // If there is no interval available, we assume that this instruction is
402 // one of those. A kill flag is manually inserted on the operand so the
403 // check below will handle it.
404 if (LIS && !LIS->isNotInMIMap(Instr: *MI)) {
405 if (Reg.isVirtual())
406 return isPlainlyKilled(MI, LR&: LIS->getInterval(Reg));
407 // Reserved registers are considered always live.
408 if (MRI->isReserved(PhysReg: Reg))
409 return false;
410 return all_of(Range: TRI->regunits(Reg), P: [&](MCRegUnit U) {
411 return isPlainlyKilled(MI, LR&: LIS->getRegUnit(Unit: U));
412 });
413 }
414
415 return MI->killsRegister(Reg, /*TRI=*/nullptr);
416}
417
418/// Test if the register used by the given operand is killed by the operand's
419/// instruction.
420bool TwoAddressInstructionImpl::isPlainlyKilled(
421 const MachineOperand &MO) const {
422 return MO.isKill() || isPlainlyKilled(MI: MO.getParent(), Reg: MO.getReg());
423}
424
425/// Test if the given register value, which is used by the given
426/// instruction, is killed by the given instruction. This looks through
427/// coalescable copies to see if the original value is potentially not killed.
428///
429/// For example, in this code:
430///
431/// %reg1034 = copy %reg1024
432/// %reg1035 = copy killed %reg1025
433/// %reg1036 = add killed %reg1034, killed %reg1035
434///
435/// %reg1034 is not considered to be killed, since it is copied from a
436/// register which is not killed. Treating it as not killed lets the
437/// normal heuristics commute the (two-address) add, which lets
438/// coalescing eliminate the extra copy.
439///
440/// If allowFalsePositives is true then likely kills are treated as kills even
441/// if it can't be proven that they are kills.
442bool TwoAddressInstructionImpl::isKilled(MachineInstr &MI, Register Reg,
443 bool allowFalsePositives) const {
444 MachineInstr *DefMI = &MI;
445 while (true) {
446 // All uses of physical registers are likely to be kills.
447 if (Reg.isPhysical() && (allowFalsePositives || MRI->hasOneUse(RegNo: Reg)))
448 return true;
449 if (!isPlainlyKilled(MI: DefMI, Reg))
450 return false;
451 if (Reg.isPhysical())
452 return true;
453 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(RegNo: Reg);
454 // If there are multiple defs, we can't do a simple analysis, so just
455 // go with what the kill flag says.
456 if (std::next(x: Begin) != MRI->def_end())
457 return true;
458 DefMI = Begin->getParent();
459 bool IsSrcPhys, IsDstPhys;
460 Register SrcReg, DstReg;
461 // If the def is something other than a copy, then it isn't going to
462 // be coalesced, so follow the kill flag.
463 if (!isCopyToReg(MI&: *DefMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
464 return true;
465 Reg = SrcReg;
466 }
467}
468
469/// Return true if the specified MI uses the specified register as a two-address
470/// use. If so, return the destination register by reference.
471static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg) {
472 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
473 const MachineOperand &MO = MI.getOperand(i);
474 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
475 continue;
476 unsigned ti;
477 if (MI.isRegTiedToDefOperand(UseOpIdx: i, DefOpIdx: &ti)) {
478 DstReg = MI.getOperand(i: ti).getReg();
479 return true;
480 }
481 }
482 return false;
483}
484
485/// Given a register, if all its uses are in the same basic block, return the
486/// last use instruction if it's a copy or a two-address use.
487MachineInstr *TwoAddressInstructionImpl::findOnlyInterestingUse(
488 Register Reg, MachineBasicBlock *MBB, bool &IsCopy, Register &DstReg,
489 bool &IsDstPhys) const {
490 MachineOperand *UseOp = nullptr;
491 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
492 if (MO.isUndef())
493 continue;
494
495 MachineInstr *MI = MO.getParent();
496 if (MI->getParent() != MBB)
497 return nullptr;
498 if (isPlainlyKilled(MI, Reg))
499 UseOp = &MO;
500 }
501 if (!UseOp)
502 return nullptr;
503 MachineInstr &UseMI = *UseOp->getParent();
504
505 Register SrcReg;
506 bool IsSrcPhys;
507 if (isCopyToReg(MI&: UseMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
508 IsCopy = true;
509 return &UseMI;
510 }
511 IsDstPhys = false;
512 if (isTwoAddrUse(MI&: UseMI, Reg, DstReg)) {
513 IsDstPhys = DstReg.isPhysical();
514 return &UseMI;
515 }
516 if (UseMI.isCommutable()) {
517 unsigned Src1 = TargetInstrInfo::CommuteAnyOperandIndex;
518 unsigned Src2 = UseOp->getOperandNo();
519 if (TII->findCommutedOpIndices(MI: UseMI, SrcOpIdx1&: Src1, SrcOpIdx2&: Src2)) {
520 MachineOperand &MO = UseMI.getOperand(i: Src1);
521 if (MO.isReg() && MO.isUse() &&
522 isTwoAddrUse(MI&: UseMI, Reg: MO.getReg(), DstReg)) {
523 IsDstPhys = DstReg.isPhysical();
524 return &UseMI;
525 }
526 }
527 }
528 return nullptr;
529}
530
531/// Return the physical register the specified virtual register might be mapped
532/// to.
533static MCRegister getMappedReg(Register Reg,
534 DenseMap<Register, Register> &RegMap) {
535 while (Reg.isVirtual()) {
536 DenseMap<Register, Register>::iterator SI = RegMap.find(Val: Reg);
537 if (SI == RegMap.end())
538 return 0;
539 Reg = SI->second;
540 }
541 if (Reg.isPhysical())
542 return Reg;
543 return 0;
544}
545
546/// Return true if the two registers are equal or aliased.
547bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA,
548 Register RegB) const {
549 if (RegA == RegB)
550 return true;
551 if (!RegA || !RegB)
552 return false;
553 return TRI->regsOverlap(RegA, RegB);
554}
555
556/// From RegMap remove entries mapped to a physical register which overlaps MO.
557void TwoAddressInstructionImpl::removeMapRegEntry(
558 const MachineOperand &MO, DenseMap<Register, Register> &RegMap) const {
559 assert(
560 (MO.isReg() || MO.isRegMask()) &&
561 "removeMapRegEntry must be called with a register or regmask operand.");
562
563 SmallVector<Register, 2> Srcs;
564 for (auto SI : RegMap) {
565 Register ToReg = SI.second;
566 if (ToReg.isVirtual())
567 continue;
568
569 if (MO.isReg()) {
570 Register Reg = MO.getReg();
571 if (TRI->regsOverlap(RegA: ToReg, RegB: Reg))
572 Srcs.push_back(Elt: SI.first);
573 } else if (MO.clobbersPhysReg(PhysReg: ToReg))
574 Srcs.push_back(Elt: SI.first);
575 }
576
577 for (auto SrcReg : Srcs)
578 RegMap.erase(Val: SrcReg);
579}
580
581/// If a physical register is clobbered, old entries mapped to it should be
582/// deleted. For example
583///
584/// %2:gr64 = COPY killed $rdx
585/// MUL64r %3:gr64, implicit-def $rax, implicit-def $rdx
586///
587/// After the MUL instruction, $rdx contains different value than in the COPY
588/// instruction. So %2 should not map to $rdx after MUL.
589void TwoAddressInstructionImpl::removeClobberedSrcRegMap(MachineInstr *MI) {
590 if (MI->isCopy()) {
591 // If a virtual register is copied to its mapped physical register, it
592 // doesn't change the potential coalescing between them, so we don't remove
593 // entries mapped to the physical register. For example
594 //
595 // %100 = COPY $r8
596 // ...
597 // $r8 = COPY %100
598 //
599 // The first copy constructs SrcRegMap[%100] = $r8, the second copy doesn't
600 // destroy the content of $r8, and should not impact SrcRegMap.
601 Register Dst = MI->getOperand(i: 0).getReg();
602 if (!Dst || Dst.isVirtual())
603 return;
604
605 Register Src = MI->getOperand(i: 1).getReg();
606 if (regsAreCompatible(RegA: Dst, RegB: getMappedReg(Reg: Src, RegMap&: SrcRegMap)))
607 return;
608 }
609
610 for (const MachineOperand &MO : MI->operands()) {
611 if (MO.isRegMask()) {
612 removeMapRegEntry(MO, RegMap&: SrcRegMap);
613 continue;
614 }
615 if (!MO.isReg() || !MO.isDef())
616 continue;
617 Register Reg = MO.getReg();
618 if (!Reg || Reg.isVirtual())
619 continue;
620 removeMapRegEntry(MO, RegMap&: SrcRegMap);
621 }
622}
623
624// Returns true if Reg is equal or aliased to at least one register in Set.
625bool TwoAddressInstructionImpl::regOverlapsSet(
626 const SmallVectorImpl<Register> &Set, Register Reg) const {
627 for (Register R : Set)
628 if (TRI->regsOverlap(RegA: R, RegB: Reg))
629 return true;
630
631 return false;
632}
633
634/// Return true if it's potentially profitable to commute the two-address
635/// instruction that's being processed.
636bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA,
637 Register RegB,
638 Register RegC,
639 MachineInstr *MI,
640 unsigned Dist) {
641 if (OptLevel == CodeGenOptLevel::None)
642 return false;
643
644 // Determine if it's profitable to commute this two address instruction. In
645 // general, we want no uses between this instruction and the definition of
646 // the two-address register.
647 // e.g.
648 // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
649 // %reg1029 = COPY %reg1028
650 // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
651 // insert => %reg1030 = COPY %reg1028
652 // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
653 // In this case, it might not be possible to coalesce the second COPY
654 // instruction if the first one is coalesced. So it would be profitable to
655 // commute it:
656 // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
657 // %reg1029 = COPY %reg1028
658 // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
659 // insert => %reg1030 = COPY %reg1029
660 // %reg1030 = ADD8rr killed %reg1029, killed %reg1028, implicit dead %eflags
661
662 if (!isPlainlyKilled(MI, Reg: RegC))
663 return false;
664
665 // Ok, we have something like:
666 // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
667 // let's see if it's worth commuting it.
668
669 // Look for situations like this:
670 // %reg1024 = MOV r1
671 // %reg1025 = MOV r0
672 // %reg1026 = ADD %reg1024, %reg1025
673 // r0 = MOV %reg1026
674 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
675 MCRegister ToRegA = getMappedReg(Reg: RegA, RegMap&: DstRegMap);
676 if (ToRegA) {
677 MCRegister FromRegB = getMappedReg(Reg: RegB, RegMap&: SrcRegMap);
678 MCRegister FromRegC = getMappedReg(Reg: RegC, RegMap&: SrcRegMap);
679 bool CompB = FromRegB && regsAreCompatible(RegA: FromRegB, RegB: ToRegA);
680 bool CompC = FromRegC && regsAreCompatible(RegA: FromRegC, RegB: ToRegA);
681
682 // Compute if any of the following are true:
683 // -RegB is not tied to a register and RegC is compatible with RegA.
684 // -RegB is tied to the wrong physical register, but RegC is.
685 // -RegB is tied to the wrong physical register, and RegC isn't tied.
686 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
687 return true;
688 // Don't compute if any of the following are true:
689 // -RegC is not tied to a register and RegB is compatible with RegA.
690 // -RegC is tied to the wrong physical register, but RegB is.
691 // -RegC is tied to the wrong physical register, and RegB isn't tied.
692 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
693 return false;
694 }
695
696 // If there is a use of RegC between its last def (could be livein) and this
697 // instruction, then bail.
698 unsigned LastDefC = 0;
699 if (!noUseAfterLastDef(Reg: RegC, Dist, LastDef&: LastDefC))
700 return false;
701
702 // If there is a use of RegB between its last def (could be livein) and this
703 // instruction, then go ahead and make this transformation.
704 unsigned LastDefB = 0;
705 if (!noUseAfterLastDef(Reg: RegB, Dist, LastDef&: LastDefB))
706 return true;
707
708 // Look for situation like this:
709 // %reg101 = MOV %reg100
710 // %reg102 = ...
711 // %reg103 = ADD %reg102, %reg101
712 // ... = %reg103 ...
713 // %reg100 = MOV %reg103
714 // If there is a reversed copy chain from reg101 to reg103, commute the ADD
715 // to eliminate an otherwise unavoidable copy.
716 // FIXME:
717 // We can extend the logic further: If an pair of operands in an insn has
718 // been merged, the insn could be regarded as a virtual copy, and the virtual
719 // copy could also be used to construct a copy chain.
720 // To more generally minimize register copies, ideally the logic of two addr
721 // instruction pass should be integrated with register allocation pass where
722 // interference graph is available.
723 if (isRevCopyChain(FromReg: RegC, ToReg: RegA, Maxlen: MaxDataFlowEdge))
724 return true;
725
726 if (isRevCopyChain(FromReg: RegB, ToReg: RegA, Maxlen: MaxDataFlowEdge))
727 return false;
728
729 // Look for other target specific commute preference.
730 bool Commute;
731 if (TII->hasCommutePreference(MI&: *MI, Commute))
732 return Commute;
733
734 // Since there are no intervening uses for both registers, then commute
735 // if the def of RegC is closer. Its live interval is shorter.
736 return LastDefB && LastDefC && LastDefC > LastDefB;
737}
738
739/// Commute a two-address instruction and update the basic block, distance map,
740/// and live variables if needed. Return true if it is successful.
741bool TwoAddressInstructionImpl::commuteInstruction(MachineInstr *MI,
742 unsigned DstIdx,
743 unsigned RegBIdx,
744 unsigned RegCIdx,
745 unsigned Dist) {
746 Register RegC = MI->getOperand(i: RegCIdx).getReg();
747 LLVM_DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
748 MachineInstr *NewMI = TII->commuteInstruction(MI&: *MI, NewMI: false, OpIdx1: RegBIdx, OpIdx2: RegCIdx);
749
750 if (NewMI == nullptr) {
751 LLVM_DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
752 return false;
753 }
754
755 LLVM_DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
756 assert(NewMI == MI &&
757 "TargetInstrInfo::commuteInstruction() should not return a new "
758 "instruction unless it was requested.");
759
760 // Update source register map.
761 MCRegister FromRegC = getMappedReg(Reg: RegC, RegMap&: SrcRegMap);
762 if (FromRegC) {
763 Register RegA = MI->getOperand(i: DstIdx).getReg();
764 SrcRegMap[RegA] = FromRegC;
765 }
766
767 return true;
768}
769
770/// Return true if it is profitable to convert the given 2-address instruction
771/// to a 3-address one.
772bool TwoAddressInstructionImpl::isProfitableToConv3Addr(Register RegA,
773 Register RegB) {
774 // Look for situations like this:
775 // %reg1024 = MOV r1
776 // %reg1025 = MOV r0
777 // %reg1026 = ADD %reg1024, %reg1025
778 // r2 = MOV %reg1026
779 // Turn ADD into a 3-address instruction to avoid a copy.
780 MCRegister FromRegB = getMappedReg(Reg: RegB, RegMap&: SrcRegMap);
781 if (!FromRegB)
782 return false;
783 MCRegister ToRegA = getMappedReg(Reg: RegA, RegMap&: DstRegMap);
784 return (ToRegA && !regsAreCompatible(RegA: FromRegB, RegB: ToRegA));
785}
786
787/// Convert the specified two-address instruction into a three address one.
788/// Return true if this transformation was successful.
789bool TwoAddressInstructionImpl::convertInstTo3Addr(
790 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
791 Register RegA, Register RegB, unsigned &Dist) {
792 MachineInstrSpan MIS(mi, MBB);
793 MachineInstr *NewMI = TII->convertToThreeAddress(MI&: *mi, LV, LIS);
794 if (!NewMI)
795 return false;
796
797 LLVM_DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
798 LLVM_DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
799
800 // If the old instruction is debug value tracked, an update is required.
801 if (auto OldInstrNum = mi->peekDebugInstrNum()) {
802 assert(mi->getNumExplicitDefs() == 1);
803 assert(NewMI->getNumExplicitDefs() == 1);
804
805 // Find the old and new def location.
806 unsigned OldIdx = mi->defs().begin()->getOperandNo();
807 unsigned NewIdx = NewMI->defs().begin()->getOperandNo();
808
809 // Record that one def has been replaced by the other.
810 unsigned NewInstrNum = NewMI->getDebugInstrNum();
811 MF->makeDebugValueSubstitution(std::make_pair(x&: OldInstrNum, y&: OldIdx),
812 std::make_pair(x&: NewInstrNum, y&: NewIdx));
813 }
814
815 MBB->erase(I: mi); // Nuke the old inst.
816
817 for (MachineInstr &MI : MIS)
818 DistanceMap.insert(KV: std::make_pair(x: &MI, y: Dist++));
819 Dist--;
820 mi = NewMI;
821 nmi = std::next(x: mi);
822
823 // Update source and destination register maps.
824 SrcRegMap.erase(Val: RegA);
825 DstRegMap.erase(Val: RegB);
826 return true;
827}
828
829/// Scan forward recursively for only uses, update maps if the use is a copy or
830/// a two-address instruction.
831void TwoAddressInstructionImpl::scanUses(Register DstReg) {
832 SmallVector<Register, 4> VirtRegPairs;
833 bool IsDstPhys;
834 bool IsCopy = false;
835 Register NewReg;
836 Register Reg = DstReg;
837 while (MachineInstr *UseMI =
838 findOnlyInterestingUse(Reg, MBB, IsCopy, DstReg&: NewReg, IsDstPhys)) {
839 if (IsCopy && !Processed.insert(Ptr: UseMI).second)
840 break;
841
842 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(Val: UseMI);
843 if (DI != DistanceMap.end())
844 // Earlier in the same MBB.Reached via a back edge.
845 break;
846
847 if (IsDstPhys) {
848 VirtRegPairs.push_back(Elt: NewReg);
849 break;
850 }
851 SrcRegMap[NewReg] = Reg;
852 VirtRegPairs.push_back(Elt: NewReg);
853 Reg = NewReg;
854 }
855
856 if (!VirtRegPairs.empty()) {
857 Register ToReg = VirtRegPairs.pop_back_val();
858 while (!VirtRegPairs.empty()) {
859 Register FromReg = VirtRegPairs.pop_back_val();
860 bool isNew = DstRegMap.insert(KV: std::make_pair(x&: FromReg, y&: ToReg)).second;
861 if (!isNew)
862 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
863 ToReg = FromReg;
864 }
865 bool isNew = DstRegMap.insert(KV: std::make_pair(x&: DstReg, y&: ToReg)).second;
866 if (!isNew)
867 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
868 }
869}
870
871/// If the specified instruction is not yet processed, process it if it's a
872/// copy. For a copy instruction, we find the physical registers the
873/// source and destination registers might be mapped to. These are kept in
874/// point-to maps used to determine future optimizations. e.g.
875/// v1024 = mov r0
876/// v1025 = mov r1
877/// v1026 = add v1024, v1025
878/// r1 = mov r1026
879/// If 'add' is a two-address instruction, v1024, v1026 are both potentially
880/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
881/// potentially joined with r1 on the output side. It's worthwhile to commute
882/// 'add' to eliminate a copy.
883void TwoAddressInstructionImpl::processCopy(MachineInstr *MI) {
884 if (Processed.count(Ptr: MI))
885 return;
886
887 bool IsSrcPhys, IsDstPhys;
888 Register SrcReg, DstReg;
889 if (!isCopyToReg(MI&: *MI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
890 return;
891
892 if (IsDstPhys && !IsSrcPhys) {
893 DstRegMap.insert(KV: std::make_pair(x&: SrcReg, y&: DstReg));
894 } else if (!IsDstPhys && IsSrcPhys) {
895 bool isNew = SrcRegMap.insert(KV: std::make_pair(x&: DstReg, y&: SrcReg)).second;
896 if (!isNew)
897 assert(SrcRegMap[DstReg] == SrcReg &&
898 "Can't map to two src physical registers!");
899
900 scanUses(DstReg);
901 }
902
903 Processed.insert(Ptr: MI);
904}
905
906/// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
907/// consider moving the instruction below the kill instruction in order to
908/// eliminate the need for the copy.
909bool TwoAddressInstructionImpl::rescheduleMIBelowKill(
910 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
911 Register Reg) {
912 // Bail immediately if we don't have LV or LIS available. We use them to find
913 // kills efficiently.
914 if (!LV && !LIS)
915 return false;
916
917 MachineInstr *MI = &*mi;
918 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(Val: MI);
919 if (DI == DistanceMap.end())
920 // Must be created from unfolded load. Don't waste time trying this.
921 return false;
922
923 MachineInstr *KillMI = nullptr;
924 if (LIS) {
925 LiveInterval &LI = LIS->getInterval(Reg);
926 assert(LI.end() != LI.begin() &&
927 "Reg should not have empty live interval.");
928
929 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(mbb: MBB).getPrevSlot();
930 LiveInterval::const_iterator I = LI.find(Pos: MBBEndIdx);
931 if (I != LI.end() && I->start < MBBEndIdx)
932 return false;
933
934 --I;
935 KillMI = LIS->getInstructionFromIndex(index: I->end);
936 } else {
937 KillMI = LV->getVarInfo(Reg).findKill(MBB);
938 }
939 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
940 // Don't mess with copies, they may be coalesced later.
941 return false;
942
943 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
944 KillMI->isBranch() || KillMI->isTerminator())
945 // Don't move pass calls, etc.
946 return false;
947
948 Register DstReg;
949 if (isTwoAddrUse(MI&: *KillMI, Reg, DstReg))
950 return false;
951
952 bool SeenStore = true;
953 if (!MI->isSafeToMove(SawStore&: SeenStore))
954 return false;
955
956 if (TII->getInstrLatency(ItinData: InstrItins, MI: *MI) > 1)
957 // FIXME: Needs more sophisticated heuristics.
958 return false;
959
960 SmallVector<Register, 2> Uses;
961 SmallVector<Register, 2> Kills;
962 SmallVector<Register, 2> Defs;
963 for (const MachineOperand &MO : MI->operands()) {
964 if (!MO.isReg())
965 continue;
966 Register MOReg = MO.getReg();
967 if (!MOReg)
968 continue;
969 if (MO.isDef())
970 Defs.push_back(Elt: MOReg);
971 else {
972 Uses.push_back(Elt: MOReg);
973 if (MOReg != Reg && isPlainlyKilled(MO))
974 Kills.push_back(Elt: MOReg);
975 }
976 }
977
978 // Move the copies connected to MI down as well.
979 MachineBasicBlock::iterator Begin = MI;
980 MachineBasicBlock::iterator AfterMI = std::next(x: Begin);
981 MachineBasicBlock::iterator End = AfterMI;
982 while (End != MBB->end()) {
983 End = skipDebugInstructionsForward(It: End, End: MBB->end());
984 if (End->isCopy() && regOverlapsSet(Set: Defs, Reg: End->getOperand(i: 1).getReg()))
985 Defs.push_back(Elt: End->getOperand(i: 0).getReg());
986 else
987 break;
988 ++End;
989 }
990
991 // Check if the reschedule will not break dependencies.
992 unsigned NumVisited = 0;
993 MachineBasicBlock::iterator KillPos = KillMI;
994 ++KillPos;
995 for (MachineInstr &OtherMI : make_range(x: End, y: KillPos)) {
996 // Debug or pseudo instructions cannot be counted against the limit.
997 if (OtherMI.isDebugOrPseudoInstr())
998 continue;
999 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1000 return false;
1001 ++NumVisited;
1002 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1003 OtherMI.isBranch() || OtherMI.isTerminator())
1004 // Don't move pass calls, etc.
1005 return false;
1006 for (const MachineOperand &MO : OtherMI.operands()) {
1007 if (!MO.isReg())
1008 continue;
1009 Register MOReg = MO.getReg();
1010 if (!MOReg)
1011 continue;
1012 if (MO.isDef()) {
1013 if (regOverlapsSet(Set: Uses, Reg: MOReg))
1014 // Physical register use would be clobbered.
1015 return false;
1016 if (!MO.isDead() && regOverlapsSet(Set: Defs, Reg: MOReg))
1017 // May clobber a physical register def.
1018 // FIXME: This may be too conservative. It's ok if the instruction
1019 // is sunken completely below the use.
1020 return false;
1021 } else {
1022 if (regOverlapsSet(Set: Defs, Reg: MOReg))
1023 return false;
1024 bool isKill = isPlainlyKilled(MO);
1025 if (MOReg != Reg && ((isKill && regOverlapsSet(Set: Uses, Reg: MOReg)) ||
1026 regOverlapsSet(Set: Kills, Reg: MOReg)))
1027 // Don't want to extend other live ranges and update kills.
1028 return false;
1029 if (MOReg == Reg && !isKill)
1030 // We can't schedule across a use of the register in question.
1031 return false;
1032 // Ensure that if this is register in question, its the kill we expect.
1033 assert((MOReg != Reg || &OtherMI == KillMI) &&
1034 "Found multiple kills of a register in a basic block");
1035 }
1036 }
1037 }
1038
1039 // Move debug info as well.
1040 while (Begin != MBB->begin() && std::prev(x: Begin)->isDebugInstr())
1041 --Begin;
1042
1043 nmi = End;
1044 MachineBasicBlock::iterator InsertPos = KillPos;
1045 if (LIS) {
1046 // We have to move the copies (and any interleaved debug instructions)
1047 // first so that the MBB is still well-formed when calling handleMove().
1048 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
1049 auto CopyMI = MBBI++;
1050 MBB->splice(Where: InsertPos, Other: MBB, From: CopyMI);
1051 if (!CopyMI->isDebugOrPseudoInstr())
1052 LIS->handleMove(MI&: *CopyMI);
1053 InsertPos = CopyMI;
1054 }
1055 End = std::next(x: MachineBasicBlock::iterator(MI));
1056 }
1057
1058 // Copies following MI may have been moved as well.
1059 MBB->splice(Where: InsertPos, Other: MBB, From: Begin, To: End);
1060 DistanceMap.erase(I: DI);
1061
1062 // Update live variables
1063 if (LIS) {
1064 LIS->handleMove(MI&: *MI);
1065 } else {
1066 LV->removeVirtualRegisterKilled(Reg, MI&: *KillMI);
1067 LV->addVirtualRegisterKilled(IncomingReg: Reg, MI&: *MI);
1068 }
1069
1070 LLVM_DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
1071 return true;
1072}
1073
1074/// Return true if the re-scheduling will put the given instruction too close
1075/// to the defs of its register dependencies.
1076bool TwoAddressInstructionImpl::isDefTooClose(Register Reg, unsigned Dist,
1077 MachineInstr *MI) {
1078 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
1079 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
1080 continue;
1081 if (&DefMI == MI)
1082 return true; // MI is defining something KillMI uses
1083 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(Val: &DefMI);
1084 if (DDI == DistanceMap.end())
1085 return true; // Below MI
1086 unsigned DefDist = DDI->second;
1087 assert(Dist > DefDist && "Visited def already?");
1088 if (TII->getInstrLatency(ItinData: InstrItins, MI: DefMI) > (Dist - DefDist))
1089 return true;
1090 }
1091 return false;
1092}
1093
1094/// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
1095/// consider moving the kill instruction above the current two-address
1096/// instruction in order to eliminate the need for the copy.
1097bool TwoAddressInstructionImpl::rescheduleKillAboveMI(
1098 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
1099 Register Reg) {
1100 // Bail immediately if we don't have LV or LIS available. We use them to find
1101 // kills efficiently.
1102 if (!LV && !LIS)
1103 return false;
1104
1105 MachineInstr *MI = &*mi;
1106 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(Val: MI);
1107 if (DI == DistanceMap.end())
1108 // Must be created from unfolded load. Don't waste time trying this.
1109 return false;
1110
1111 MachineInstr *KillMI = nullptr;
1112 if (LIS) {
1113 LiveInterval &LI = LIS->getInterval(Reg);
1114 assert(LI.end() != LI.begin() &&
1115 "Reg should not have empty live interval.");
1116
1117 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(mbb: MBB).getPrevSlot();
1118 LiveInterval::const_iterator I = LI.find(Pos: MBBEndIdx);
1119 if (I != LI.end() && I->start < MBBEndIdx)
1120 return false;
1121
1122 --I;
1123 KillMI = LIS->getInstructionFromIndex(index: I->end);
1124 } else {
1125 KillMI = LV->getVarInfo(Reg).findKill(MBB);
1126 }
1127 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
1128 // Don't mess with copies, they may be coalesced later.
1129 return false;
1130
1131 Register DstReg;
1132 if (isTwoAddrUse(MI&: *KillMI, Reg, DstReg))
1133 return false;
1134
1135 bool SeenStore = true;
1136 if (!KillMI->isSafeToMove(SawStore&: SeenStore))
1137 return false;
1138
1139 SmallVector<Register, 2> Uses;
1140 SmallVector<Register, 2> Kills;
1141 SmallVector<Register, 2> Defs;
1142 SmallVector<Register, 2> LiveDefs;
1143 for (const MachineOperand &MO : KillMI->operands()) {
1144 if (!MO.isReg())
1145 continue;
1146 Register MOReg = MO.getReg();
1147 if (MO.isUse()) {
1148 if (!MOReg)
1149 continue;
1150 if (isDefTooClose(Reg: MOReg, Dist: DI->second, MI))
1151 return false;
1152 bool isKill = isPlainlyKilled(MO);
1153 if (MOReg == Reg && !isKill)
1154 return false;
1155 Uses.push_back(Elt: MOReg);
1156 if (isKill && MOReg != Reg)
1157 Kills.push_back(Elt: MOReg);
1158 } else if (MOReg.isPhysical()) {
1159 Defs.push_back(Elt: MOReg);
1160 if (!MO.isDead())
1161 LiveDefs.push_back(Elt: MOReg);
1162 }
1163 }
1164
1165 // Check if the reschedule will not break dependencies.
1166 unsigned NumVisited = 0;
1167 for (MachineInstr &OtherMI :
1168 make_range(x: mi, y: MachineBasicBlock::iterator(KillMI))) {
1169 // Debug or pseudo instructions cannot be counted against the limit.
1170 if (OtherMI.isDebugOrPseudoInstr())
1171 continue;
1172 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1173 return false;
1174 ++NumVisited;
1175 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1176 OtherMI.isBranch() || OtherMI.isTerminator())
1177 // Don't move pass calls, etc.
1178 return false;
1179 SmallVector<Register, 2> OtherDefs;
1180 for (const MachineOperand &MO : OtherMI.operands()) {
1181 if (!MO.isReg())
1182 continue;
1183 Register MOReg = MO.getReg();
1184 if (!MOReg)
1185 continue;
1186 if (MO.isUse()) {
1187 if (regOverlapsSet(Set: Defs, Reg: MOReg))
1188 // Moving KillMI can clobber the physical register if the def has
1189 // not been seen.
1190 return false;
1191 if (regOverlapsSet(Set: Kills, Reg: MOReg))
1192 // Don't want to extend other live ranges and update kills.
1193 return false;
1194 if (&OtherMI != MI && MOReg == Reg && !isPlainlyKilled(MO))
1195 // We can't schedule across a use of the register in question.
1196 return false;
1197 } else {
1198 OtherDefs.push_back(Elt: MOReg);
1199 }
1200 }
1201
1202 for (Register MOReg : OtherDefs) {
1203 if (regOverlapsSet(Set: Uses, Reg: MOReg))
1204 return false;
1205 if (MOReg.isPhysical() && regOverlapsSet(Set: LiveDefs, Reg: MOReg))
1206 return false;
1207 // Physical register def is seen.
1208 llvm::erase(C&: Defs, V: MOReg);
1209 }
1210 }
1211
1212 // Move the old kill above MI, don't forget to move debug info as well.
1213 MachineBasicBlock::iterator InsertPos = mi;
1214 while (InsertPos != MBB->begin() && std::prev(x: InsertPos)->isDebugInstr())
1215 --InsertPos;
1216 MachineBasicBlock::iterator From = KillMI;
1217 MachineBasicBlock::iterator To = std::next(x: From);
1218 while (std::prev(x: From)->isDebugInstr())
1219 --From;
1220 MBB->splice(Where: InsertPos, Other: MBB, From, To);
1221
1222 nmi = std::prev(x: InsertPos); // Backtrack so we process the moved instr.
1223 DistanceMap.erase(I: DI);
1224
1225 // Update live variables
1226 if (LIS) {
1227 LIS->handleMove(MI&: *KillMI);
1228 } else {
1229 LV->removeVirtualRegisterKilled(Reg, MI&: *KillMI);
1230 LV->addVirtualRegisterKilled(IncomingReg: Reg, MI&: *MI);
1231 }
1232
1233 LLVM_DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1234 return true;
1235}
1236
1237/// Tries to commute the operand 'BaseOpIdx' and some other operand in the
1238/// given machine instruction to improve opportunities for coalescing and
1239/// elimination of a register to register copy.
1240///
1241/// 'DstOpIdx' specifies the index of MI def operand.
1242/// 'BaseOpKilled' specifies if the register associated with 'BaseOpIdx'
1243/// operand is killed by the given instruction.
1244/// The 'Dist' arguments provides the distance of MI from the start of the
1245/// current basic block and it is used to determine if it is profitable
1246/// to commute operands in the instruction.
1247///
1248/// Returns true if the transformation happened. Otherwise, returns false.
1249bool TwoAddressInstructionImpl::tryInstructionCommute(MachineInstr *MI,
1250 unsigned DstOpIdx,
1251 unsigned BaseOpIdx,
1252 bool BaseOpKilled,
1253 unsigned Dist) {
1254 if (!MI->isCommutable())
1255 return false;
1256
1257 bool MadeChange = false;
1258 Register DstOpReg = MI->getOperand(i: DstOpIdx).getReg();
1259 Register BaseOpReg = MI->getOperand(i: BaseOpIdx).getReg();
1260 unsigned OpsNum = MI->getDesc().getNumOperands();
1261 unsigned OtherOpIdx = MI->getDesc().getNumDefs();
1262 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1263 // The call of findCommutedOpIndices below only checks if BaseOpIdx
1264 // and OtherOpIdx are commutable, it does not really search for
1265 // other commutable operands and does not change the values of passed
1266 // variables.
1267 if (OtherOpIdx == BaseOpIdx || !MI->getOperand(i: OtherOpIdx).isReg() ||
1268 !TII->findCommutedOpIndices(MI: *MI, SrcOpIdx1&: BaseOpIdx, SrcOpIdx2&: OtherOpIdx))
1269 continue;
1270
1271 Register OtherOpReg = MI->getOperand(i: OtherOpIdx).getReg();
1272 bool AggressiveCommute = false;
1273
1274 // If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
1275 // operands. This makes the live ranges of DstOp and OtherOp joinable.
1276 bool OtherOpKilled = isKilled(MI&: *MI, Reg: OtherOpReg, allowFalsePositives: false);
1277 bool DoCommute = !BaseOpKilled && OtherOpKilled;
1278
1279 if (!DoCommute &&
1280 isProfitableToCommute(RegA: DstOpReg, RegB: BaseOpReg, RegC: OtherOpReg, MI, Dist)) {
1281 DoCommute = true;
1282 AggressiveCommute = true;
1283 }
1284
1285 // If it's profitable to commute, try to do so.
1286 if (DoCommute && commuteInstruction(MI, DstIdx: DstOpIdx, RegBIdx: BaseOpIdx, RegCIdx: OtherOpIdx,
1287 Dist)) {
1288 MadeChange = true;
1289 ++NumCommuted;
1290 if (AggressiveCommute)
1291 ++NumAggrCommuted;
1292
1293 // There might be more than two commutable operands, update BaseOp and
1294 // continue scanning.
1295 // FIXME: This assumes that the new instruction's operands are in the
1296 // same positions and were simply swapped.
1297 BaseOpReg = OtherOpReg;
1298 BaseOpKilled = OtherOpKilled;
1299 // Resamples OpsNum in case the number of operands was reduced. This
1300 // happens with X86.
1301 OpsNum = MI->getDesc().getNumOperands();
1302 }
1303 }
1304 return MadeChange;
1305}
1306
1307/// For the case where an instruction has a single pair of tied register
1308/// operands, attempt some transformations that may either eliminate the tied
1309/// operands or improve the opportunities for coalescing away the register copy.
1310/// Returns true if no copy needs to be inserted to untie mi's operands
1311/// (either because they were untied, or because mi was rescheduled, and will
1312/// be visited again later). If the shouldOnlyCommute flag is true, only
1313/// instruction commutation is attempted.
1314bool TwoAddressInstructionImpl::tryInstructionTransform(
1315 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
1316 unsigned SrcIdx, unsigned DstIdx, unsigned &Dist, bool shouldOnlyCommute) {
1317 if (OptLevel == CodeGenOptLevel::None)
1318 return false;
1319
1320 MachineInstr &MI = *mi;
1321 Register regA = MI.getOperand(i: DstIdx).getReg();
1322 Register regB = MI.getOperand(i: SrcIdx).getReg();
1323
1324 assert(regB.isVirtual() && "cannot make instruction into two-address form");
1325 bool regBKilled = isKilled(MI, Reg: regB, allowFalsePositives: true);
1326
1327 if (regA.isVirtual())
1328 scanUses(DstReg: regA);
1329
1330 bool Commuted = tryInstructionCommute(MI: &MI, DstOpIdx: DstIdx, BaseOpIdx: SrcIdx, BaseOpKilled: regBKilled, Dist);
1331
1332 // If the instruction is convertible to 3 Addr, instead
1333 // of returning try 3 Addr transformation aggressively and
1334 // use this variable to check later. Because it might be better.
1335 // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
1336 // instead of the following code.
1337 // addl %esi, %edi
1338 // movl %edi, %eax
1339 // ret
1340 if (Commuted && !MI.isConvertibleTo3Addr())
1341 return false;
1342
1343 if (shouldOnlyCommute)
1344 return false;
1345
1346 // If there is one more use of regB later in the same MBB, consider
1347 // re-schedule this MI below it.
1348 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, Reg: regB)) {
1349 ++NumReSchedDowns;
1350 return true;
1351 }
1352
1353 // If we commuted, regB may have changed so we should re-sample it to avoid
1354 // confusing the three address conversion below.
1355 if (Commuted) {
1356 regB = MI.getOperand(i: SrcIdx).getReg();
1357 regBKilled = isKilled(MI, Reg: regB, allowFalsePositives: true);
1358 }
1359
1360 if (MI.isConvertibleTo3Addr()) {
1361 // This instruction is potentially convertible to a true
1362 // three-address instruction. Check if it is profitable.
1363 if (!regBKilled || isProfitableToConv3Addr(RegA: regA, RegB: regB)) {
1364 // Try to convert it.
1365 if (convertInstTo3Addr(mi, nmi, RegA: regA, RegB: regB, Dist)) {
1366 ++NumConvertedTo3Addr;
1367 return true; // Done with this instruction.
1368 }
1369 }
1370 }
1371
1372 // Return if it is commuted but 3 addr conversion is failed.
1373 if (Commuted)
1374 return false;
1375
1376 // If there is one more use of regB later in the same MBB, consider
1377 // re-schedule it before this MI if it's legal.
1378 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, Reg: regB)) {
1379 ++NumReSchedUps;
1380 return true;
1381 }
1382
1383 // If this is an instruction with a load folded into it, try unfolding
1384 // the load, e.g. avoid this:
1385 // movq %rdx, %rcx
1386 // addq (%rax), %rcx
1387 // in favor of this:
1388 // movq (%rax), %rcx
1389 // addq %rdx, %rcx
1390 // because it's preferable to schedule a load than a register copy.
1391 if (MI.mayLoad() && !regBKilled) {
1392 // Determine if a load can be unfolded.
1393 unsigned LoadRegIndex;
1394 unsigned NewOpc =
1395 TII->getOpcodeAfterMemoryUnfold(Opc: MI.getOpcode(),
1396 /*UnfoldLoad=*/true,
1397 /*UnfoldStore=*/false,
1398 LoadRegIndex: &LoadRegIndex);
1399 if (NewOpc != 0) {
1400 const MCInstrDesc &UnfoldMCID = TII->get(Opcode: NewOpc);
1401 if (UnfoldMCID.getNumDefs() == 1) {
1402 // Unfold the load.
1403 LLVM_DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1404 const TargetRegisterClass *RC =
1405 TRI->getAllocatableClass(
1406 RC: TII->getRegClass(MCID: UnfoldMCID, OpNum: LoadRegIndex, TRI, MF: *MF));
1407 Register Reg = MRI->createVirtualRegister(RegClass: RC);
1408 SmallVector<MachineInstr *, 2> NewMIs;
1409 if (!TII->unfoldMemoryOperand(MF&: *MF, MI, Reg,
1410 /*UnfoldLoad=*/true,
1411 /*UnfoldStore=*/false, NewMIs)) {
1412 LLVM_DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1413 return false;
1414 }
1415 assert(NewMIs.size() == 2 &&
1416 "Unfolded a load into multiple instructions!");
1417 // The load was previously folded, so this is the only use.
1418 NewMIs[1]->addRegisterKilled(IncomingReg: Reg, RegInfo: TRI);
1419
1420 // Tentatively insert the instructions into the block so that they
1421 // look "normal" to the transformation logic.
1422 MBB->insert(I: mi, MI: NewMIs[0]);
1423 MBB->insert(I: mi, MI: NewMIs[1]);
1424 DistanceMap.insert(KV: std::make_pair(x&: NewMIs[0], y: Dist++));
1425 DistanceMap.insert(KV: std::make_pair(x&: NewMIs[1], y&: Dist));
1426
1427 LLVM_DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1428 << "2addr: NEW INST: " << *NewMIs[1]);
1429
1430 // Transform the instruction, now that it no longer has a load.
1431 unsigned NewDstIdx =
1432 NewMIs[1]->findRegisterDefOperandIdx(Reg: regA, /*TRI=*/nullptr);
1433 unsigned NewSrcIdx =
1434 NewMIs[1]->findRegisterUseOperandIdx(Reg: regB, /*TRI=*/nullptr);
1435 MachineBasicBlock::iterator NewMI = NewMIs[1];
1436 bool TransformResult =
1437 tryInstructionTransform(mi&: NewMI, nmi&: mi, SrcIdx: NewSrcIdx, DstIdx: NewDstIdx, Dist, shouldOnlyCommute: true);
1438 (void)TransformResult;
1439 assert(!TransformResult &&
1440 "tryInstructionTransform() should return false.");
1441 if (NewMIs[1]->getOperand(i: NewSrcIdx).isKill()) {
1442 // Success, or at least we made an improvement. Keep the unfolded
1443 // instructions and discard the original.
1444 if (LV) {
1445 for (const MachineOperand &MO : MI.operands()) {
1446 if (MO.isReg() && MO.getReg().isVirtual()) {
1447 if (MO.isUse()) {
1448 if (MO.isKill()) {
1449 if (NewMIs[0]->killsRegister(Reg: MO.getReg(), /*TRI=*/nullptr))
1450 LV->replaceKillInstruction(Reg: MO.getReg(), OldMI&: MI, NewMI&: *NewMIs[0]);
1451 else {
1452 assert(NewMIs[1]->killsRegister(MO.getReg(),
1453 /*TRI=*/nullptr) &&
1454 "Kill missing after load unfold!");
1455 LV->replaceKillInstruction(Reg: MO.getReg(), OldMI&: MI, NewMI&: *NewMIs[1]);
1456 }
1457 }
1458 } else if (LV->removeVirtualRegisterDead(Reg: MO.getReg(), MI)) {
1459 if (NewMIs[1]->registerDefIsDead(Reg: MO.getReg(),
1460 /*TRI=*/nullptr))
1461 LV->addVirtualRegisterDead(IncomingReg: MO.getReg(), MI&: *NewMIs[1]);
1462 else {
1463 assert(NewMIs[0]->registerDefIsDead(MO.getReg(),
1464 /*TRI=*/nullptr) &&
1465 "Dead flag missing after load unfold!");
1466 LV->addVirtualRegisterDead(IncomingReg: MO.getReg(), MI&: *NewMIs[0]);
1467 }
1468 }
1469 }
1470 }
1471 LV->addVirtualRegisterKilled(IncomingReg: Reg, MI&: *NewMIs[1]);
1472 }
1473
1474 SmallVector<Register, 4> OrigRegs;
1475 if (LIS) {
1476 for (const MachineOperand &MO : MI.operands()) {
1477 if (MO.isReg())
1478 OrigRegs.push_back(Elt: MO.getReg());
1479 }
1480
1481 LIS->RemoveMachineInstrFromMaps(MI);
1482 }
1483
1484 MI.eraseFromParent();
1485 DistanceMap.erase(Val: &MI);
1486
1487 // Update LiveIntervals.
1488 if (LIS) {
1489 MachineBasicBlock::iterator Begin(NewMIs[0]);
1490 MachineBasicBlock::iterator End(NewMIs[1]);
1491 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1492 }
1493
1494 mi = NewMIs[1];
1495 } else {
1496 // Transforming didn't eliminate the tie and didn't lead to an
1497 // improvement. Clean up the unfolded instructions and keep the
1498 // original.
1499 LLVM_DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1500 NewMIs[0]->eraseFromParent();
1501 NewMIs[1]->eraseFromParent();
1502 DistanceMap.erase(Val: NewMIs[0]);
1503 DistanceMap.erase(Val: NewMIs[1]);
1504 Dist--;
1505 }
1506 }
1507 }
1508 }
1509
1510 return false;
1511}
1512
1513// Collect tied operands of MI that need to be handled.
1514// Rewrite trivial cases immediately.
1515// Return true if any tied operands where found, including the trivial ones.
1516bool TwoAddressInstructionImpl::collectTiedOperands(
1517 MachineInstr *MI, TiedOperandMap &TiedOperands) {
1518 bool AnyOps = false;
1519 unsigned NumOps = MI->getNumOperands();
1520
1521 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1522 unsigned DstIdx = 0;
1523 if (!MI->isRegTiedToDefOperand(UseOpIdx: SrcIdx, DefOpIdx: &DstIdx))
1524 continue;
1525 AnyOps = true;
1526 MachineOperand &SrcMO = MI->getOperand(i: SrcIdx);
1527 MachineOperand &DstMO = MI->getOperand(i: DstIdx);
1528 Register SrcReg = SrcMO.getReg();
1529 Register DstReg = DstMO.getReg();
1530 // Tied constraint already satisfied?
1531 if (SrcReg == DstReg)
1532 continue;
1533
1534 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1535
1536 // Deal with undef uses immediately - simply rewrite the src operand.
1537 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1538 // Constrain the DstReg register class if required.
1539 if (DstReg.isVirtual()) {
1540 const TargetRegisterClass *RC = MRI->getRegClass(Reg: SrcReg);
1541 MRI->constrainRegClass(Reg: DstReg, RC);
1542 }
1543 SrcMO.setReg(DstReg);
1544 SrcMO.setSubReg(0);
1545 LLVM_DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1546 continue;
1547 }
1548 TiedOperands[SrcReg].push_back(Elt: std::make_pair(x&: SrcIdx, y&: DstIdx));
1549 }
1550 return AnyOps;
1551}
1552
1553// Process a list of tied MI operands that all use the same source register.
1554// The tied pairs are of the form (SrcIdx, DstIdx).
1555void TwoAddressInstructionImpl::processTiedPairs(MachineInstr *MI,
1556 TiedPairList &TiedPairs,
1557 unsigned &Dist) {
1558 bool IsEarlyClobber = llvm::any_of(Range&: TiedPairs, P: [MI](auto const &TP) {
1559 return MI->getOperand(TP.second).isEarlyClobber();
1560 });
1561
1562 bool RemovedKillFlag = false;
1563 bool AllUsesCopied = true;
1564 Register LastCopiedReg;
1565 SlotIndex LastCopyIdx;
1566 Register RegB = 0;
1567 unsigned SubRegB = 0;
1568 for (auto &TP : TiedPairs) {
1569 unsigned SrcIdx = TP.first;
1570 unsigned DstIdx = TP.second;
1571
1572 const MachineOperand &DstMO = MI->getOperand(i: DstIdx);
1573 Register RegA = DstMO.getReg();
1574
1575 // Grab RegB from the instruction because it may have changed if the
1576 // instruction was commuted.
1577 RegB = MI->getOperand(i: SrcIdx).getReg();
1578 SubRegB = MI->getOperand(i: SrcIdx).getSubReg();
1579
1580 if (RegA == RegB) {
1581 // The register is tied to multiple destinations (or else we would
1582 // not have continued this far), but this use of the register
1583 // already matches the tied destination. Leave it.
1584 AllUsesCopied = false;
1585 continue;
1586 }
1587 LastCopiedReg = RegA;
1588
1589 assert(RegB.isVirtual() && "cannot make instruction into two-address form");
1590
1591#ifndef NDEBUG
1592 // First, verify that we don't have a use of "a" in the instruction
1593 // (a = b + a for example) because our transformation will not
1594 // work. This should never occur because we are in SSA form.
1595 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1596 assert(i == DstIdx ||
1597 !MI->getOperand(i).isReg() ||
1598 MI->getOperand(i).getReg() != RegA);
1599#endif
1600
1601 // Emit a copy.
1602 MachineInstrBuilder MIB = BuildMI(BB&: *MI->getParent(), I: MI, MIMD: MI->getDebugLoc(),
1603 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: RegA);
1604 // If this operand is folding a truncation, the truncation now moves to the
1605 // copy so that the register classes remain valid for the operands.
1606 MIB.addReg(RegNo: RegB, flags: 0, SubReg: SubRegB);
1607 const TargetRegisterClass *RC = MRI->getRegClass(Reg: RegB);
1608 if (SubRegB) {
1609 if (RegA.isVirtual()) {
1610 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1611 SubRegB) &&
1612 "tied subregister must be a truncation");
1613 // The superreg class will not be used to constrain the subreg class.
1614 RC = nullptr;
1615 } else {
1616 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1617 && "tied subregister must be a truncation");
1618 }
1619 }
1620
1621 // Update DistanceMap.
1622 MachineBasicBlock::iterator PrevMI = MI;
1623 --PrevMI;
1624 DistanceMap.insert(KV: std::make_pair(x: &*PrevMI, y&: Dist));
1625 DistanceMap[MI] = ++Dist;
1626
1627 if (LIS) {
1628 LastCopyIdx = LIS->InsertMachineInstrInMaps(MI&: *PrevMI).getRegSlot();
1629
1630 SlotIndex endIdx =
1631 LIS->getInstructionIndex(Instr: *MI).getRegSlot(EC: IsEarlyClobber);
1632 if (RegA.isVirtual()) {
1633 LiveInterval &LI = LIS->getInterval(Reg: RegA);
1634 VNInfo *VNI = LI.getNextValue(Def: LastCopyIdx, VNInfoAllocator&: LIS->getVNInfoAllocator());
1635 LI.addSegment(S: LiveRange::Segment(LastCopyIdx, endIdx, VNI));
1636 for (auto &S : LI.subranges()) {
1637 VNI = S.getNextValue(Def: LastCopyIdx, VNInfoAllocator&: LIS->getVNInfoAllocator());
1638 S.addSegment(S: LiveRange::Segment(LastCopyIdx, endIdx, VNI));
1639 }
1640 } else {
1641 for (MCRegUnit Unit : TRI->regunits(Reg: RegA)) {
1642 if (LiveRange *LR = LIS->getCachedRegUnit(Unit)) {
1643 VNInfo *VNI =
1644 LR->getNextValue(Def: LastCopyIdx, VNInfoAllocator&: LIS->getVNInfoAllocator());
1645 LR->addSegment(S: LiveRange::Segment(LastCopyIdx, endIdx, VNI));
1646 }
1647 }
1648 }
1649 }
1650
1651 LLVM_DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
1652
1653 MachineOperand &MO = MI->getOperand(i: SrcIdx);
1654 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1655 "inconsistent operand info for 2-reg pass");
1656 if (isPlainlyKilled(MO)) {
1657 MO.setIsKill(false);
1658 RemovedKillFlag = true;
1659 }
1660
1661 // Make sure regA is a legal regclass for the SrcIdx operand.
1662 if (RegA.isVirtual() && RegB.isVirtual())
1663 MRI->constrainRegClass(Reg: RegA, RC);
1664 MO.setReg(RegA);
1665 // The getMatchingSuper asserts guarantee that the register class projected
1666 // by SubRegB is compatible with RegA with no subregister. So regardless of
1667 // whether the dest oper writes a subreg, the source oper should not.
1668 MO.setSubReg(0);
1669 }
1670
1671 if (AllUsesCopied) {
1672 LaneBitmask RemainingUses = LaneBitmask::getNone();
1673 // Replace other (un-tied) uses of regB with LastCopiedReg.
1674 for (MachineOperand &MO : MI->all_uses()) {
1675 if (MO.getReg() == RegB) {
1676 if (MO.getSubReg() == SubRegB && !IsEarlyClobber) {
1677 if (isPlainlyKilled(MO)) {
1678 MO.setIsKill(false);
1679 RemovedKillFlag = true;
1680 }
1681 MO.setReg(LastCopiedReg);
1682 MO.setSubReg(0);
1683 } else {
1684 RemainingUses |= TRI->getSubRegIndexLaneMask(SubIdx: MO.getSubReg());
1685 }
1686 }
1687 }
1688
1689 // Update live variables for regB.
1690 if (RemovedKillFlag && RemainingUses.none() && LV &&
1691 LV->getVarInfo(Reg: RegB).removeKill(MI&: *MI)) {
1692 MachineBasicBlock::iterator PrevMI = MI;
1693 --PrevMI;
1694 LV->addVirtualRegisterKilled(IncomingReg: RegB, MI&: *PrevMI);
1695 }
1696
1697 if (RemovedKillFlag && RemainingUses.none())
1698 SrcRegMap[LastCopiedReg] = RegB;
1699
1700 // Update LiveIntervals.
1701 if (LIS) {
1702 SlotIndex UseIdx = LIS->getInstructionIndex(Instr: *MI);
1703 auto Shrink = [=](LiveRange &LR, LaneBitmask LaneMask) {
1704 LiveRange::Segment *S = LR.getSegmentContaining(Idx: LastCopyIdx);
1705 if (!S)
1706 return true;
1707 if ((LaneMask & RemainingUses).any())
1708 return false;
1709 if (S->end.getBaseIndex() != UseIdx)
1710 return false;
1711 S->end = LastCopyIdx;
1712 return true;
1713 };
1714
1715 LiveInterval &LI = LIS->getInterval(Reg: RegB);
1716 bool ShrinkLI = true;
1717 for (auto &S : LI.subranges())
1718 ShrinkLI &= Shrink(S, S.LaneMask);
1719 if (ShrinkLI)
1720 Shrink(LI, LaneBitmask::getAll());
1721 }
1722 } else if (RemovedKillFlag) {
1723 // Some tied uses of regB matched their destination registers, so
1724 // regB is still used in this instruction, but a kill flag was
1725 // removed from a different tied use of regB, so now we need to add
1726 // a kill flag to one of the remaining uses of regB.
1727 for (MachineOperand &MO : MI->all_uses()) {
1728 if (MO.getReg() == RegB) {
1729 MO.setIsKill(true);
1730 break;
1731 }
1732 }
1733 }
1734}
1735
1736// For every tied operand pair this function transforms statepoint from
1737// RegA = STATEPOINT ... RegB(tied-def N)
1738// to
1739// RegB = STATEPOINT ... RegB(tied-def N)
1740// and replaces all uses of RegA with RegB.
1741// No extra COPY instruction is necessary because tied use is killed at
1742// STATEPOINT.
1743bool TwoAddressInstructionImpl::processStatepoint(
1744 MachineInstr *MI, TiedOperandMap &TiedOperands) {
1745
1746 bool NeedCopy = false;
1747 for (auto &TO : TiedOperands) {
1748 Register RegB = TO.first;
1749 if (TO.second.size() != 1) {
1750 NeedCopy = true;
1751 continue;
1752 }
1753
1754 unsigned SrcIdx = TO.second[0].first;
1755 unsigned DstIdx = TO.second[0].second;
1756
1757 MachineOperand &DstMO = MI->getOperand(i: DstIdx);
1758 Register RegA = DstMO.getReg();
1759
1760 assert(RegB == MI->getOperand(SrcIdx).getReg());
1761
1762 if (RegA == RegB)
1763 continue;
1764
1765 // CodeGenPrepare can sink pointer compare past statepoint, which
1766 // breaks assumption that statepoint kills tied-use register when
1767 // in SSA form (see note in IR/SafepointIRVerifier.cpp). Fall back
1768 // to generic tied register handling to avoid assertion failures.
1769 // TODO: Recompute LIS/LV information for new range here.
1770 if (LIS) {
1771 const auto &UseLI = LIS->getInterval(Reg: RegB);
1772 const auto &DefLI = LIS->getInterval(Reg: RegA);
1773 if (DefLI.overlaps(other: UseLI)) {
1774 LLVM_DEBUG(dbgs() << "LIS: " << printReg(RegB, TRI, 0)
1775 << " UseLI overlaps with DefLI\n");
1776 NeedCopy = true;
1777 continue;
1778 }
1779 } else if (LV && LV->getVarInfo(Reg: RegB).findKill(MBB: MI->getParent()) != MI) {
1780 // Note that MachineOperand::isKill does not work here, because it
1781 // is set only on first register use in instruction and for statepoint
1782 // tied-use register will usually be found in preceeding deopt bundle.
1783 LLVM_DEBUG(dbgs() << "LV: " << printReg(RegB, TRI, 0)
1784 << " not killed by statepoint\n");
1785 NeedCopy = true;
1786 continue;
1787 }
1788
1789 if (!MRI->constrainRegClass(Reg: RegB, RC: MRI->getRegClass(Reg: RegA))) {
1790 LLVM_DEBUG(dbgs() << "MRI: couldn't constrain" << printReg(RegB, TRI, 0)
1791 << " to register class of " << printReg(RegA, TRI, 0)
1792 << '\n');
1793 NeedCopy = true;
1794 continue;
1795 }
1796 MRI->replaceRegWith(FromReg: RegA, ToReg: RegB);
1797
1798 if (LIS) {
1799 VNInfo::Allocator &A = LIS->getVNInfoAllocator();
1800 LiveInterval &LI = LIS->getInterval(Reg: RegB);
1801 LiveInterval &Other = LIS->getInterval(Reg: RegA);
1802 SmallVector<VNInfo *> NewVNIs;
1803 for (const VNInfo *VNI : Other.valnos) {
1804 assert(VNI->id == NewVNIs.size() && "assumed");
1805 NewVNIs.push_back(Elt: LI.createValueCopy(orig: VNI, VNInfoAllocator&: A));
1806 }
1807 for (auto &S : Other) {
1808 VNInfo *VNI = NewVNIs[S.valno->id];
1809 LiveRange::Segment NewSeg(S.start, S.end, VNI);
1810 LI.addSegment(S: NewSeg);
1811 }
1812 LIS->removeInterval(Reg: RegA);
1813 }
1814
1815 if (LV) {
1816 if (MI->getOperand(i: SrcIdx).isKill())
1817 LV->removeVirtualRegisterKilled(Reg: RegB, MI&: *MI);
1818 LiveVariables::VarInfo &SrcInfo = LV->getVarInfo(Reg: RegB);
1819 LiveVariables::VarInfo &DstInfo = LV->getVarInfo(Reg: RegA);
1820 SrcInfo.AliveBlocks |= DstInfo.AliveBlocks;
1821 DstInfo.AliveBlocks.clear();
1822 for (auto *KillMI : DstInfo.Kills)
1823 LV->addVirtualRegisterKilled(IncomingReg: RegB, MI&: *KillMI, AddIfNotFound: false);
1824 }
1825 }
1826 return !NeedCopy;
1827}
1828
1829/// Reduce two-address instructions to two operands.
1830bool TwoAddressInstructionImpl::run() {
1831 bool MadeChange = false;
1832
1833 LLVM_DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1834 LLVM_DEBUG(dbgs() << "********** Function: " << MF->getName() << '\n');
1835
1836 // This pass takes the function out of SSA form.
1837 MRI->leaveSSA();
1838
1839 // This pass will rewrite the tied-def to meet the RegConstraint.
1840 MF->getProperties().setTiedOpsRewritten();
1841
1842 TiedOperandMap TiedOperands;
1843 for (MachineBasicBlock &MBBI : *MF) {
1844 MBB = &MBBI;
1845 unsigned Dist = 0;
1846 DistanceMap.clear();
1847 SrcRegMap.clear();
1848 DstRegMap.clear();
1849 Processed.clear();
1850 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1851 mi != me; ) {
1852 MachineBasicBlock::iterator nmi = std::next(x: mi);
1853 // Skip debug instructions.
1854 if (mi->isDebugInstr()) {
1855 mi = nmi;
1856 continue;
1857 }
1858
1859 // Expand REG_SEQUENCE instructions. This will position mi at the first
1860 // expanded instruction.
1861 if (mi->isRegSequence())
1862 eliminateRegSequence(mi);
1863
1864 DistanceMap.insert(KV: std::make_pair(x: &*mi, y&: ++Dist));
1865
1866 processCopy(MI: &*mi);
1867
1868 // First scan through all the tied register uses in this instruction
1869 // and record a list of pairs of tied operands for each register.
1870 if (!collectTiedOperands(MI: &*mi, TiedOperands)) {
1871 removeClobberedSrcRegMap(MI: &*mi);
1872 mi = nmi;
1873 continue;
1874 }
1875
1876 ++NumTwoAddressInstrs;
1877 MadeChange = true;
1878 LLVM_DEBUG(dbgs() << '\t' << *mi);
1879
1880 // If the instruction has a single pair of tied operands, try some
1881 // transformations that may either eliminate the tied operands or
1882 // improve the opportunities for coalescing away the register copy.
1883 if (TiedOperands.size() == 1) {
1884 SmallVectorImpl<std::pair<unsigned, unsigned>> &TiedPairs
1885 = TiedOperands.begin()->second;
1886 if (TiedPairs.size() == 1) {
1887 unsigned SrcIdx = TiedPairs[0].first;
1888 unsigned DstIdx = TiedPairs[0].second;
1889 Register SrcReg = mi->getOperand(i: SrcIdx).getReg();
1890 Register DstReg = mi->getOperand(i: DstIdx).getReg();
1891 if (SrcReg != DstReg &&
1892 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, shouldOnlyCommute: false)) {
1893 // The tied operands have been eliminated or shifted further down
1894 // the block to ease elimination. Continue processing with 'nmi'.
1895 TiedOperands.clear();
1896 removeClobberedSrcRegMap(MI: &*mi);
1897 mi = nmi;
1898 continue;
1899 }
1900 }
1901 }
1902
1903 if (mi->getOpcode() == TargetOpcode::STATEPOINT &&
1904 processStatepoint(MI: &*mi, TiedOperands)) {
1905 TiedOperands.clear();
1906 LLVM_DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1907 mi = nmi;
1908 continue;
1909 }
1910
1911 // Now iterate over the information collected above.
1912 for (auto &TO : TiedOperands) {
1913 processTiedPairs(MI: &*mi, TiedPairs&: TO.second, Dist);
1914 LLVM_DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1915 }
1916
1917 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1918 if (mi->isInsertSubreg()) {
1919 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1920 // To %reg:subidx = COPY %subreg
1921 unsigned SubIdx = mi->getOperand(i: 3).getImm();
1922 mi->removeOperand(OpNo: 3);
1923 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1924 mi->getOperand(i: 0).setSubReg(SubIdx);
1925 mi->getOperand(i: 0).setIsUndef(mi->getOperand(i: 1).isUndef());
1926 mi->removeOperand(OpNo: 1);
1927 mi->setDesc(TII->get(Opcode: TargetOpcode::COPY));
1928 LLVM_DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1929
1930 // Update LiveIntervals.
1931 if (LIS) {
1932 Register Reg = mi->getOperand(i: 0).getReg();
1933 LiveInterval &LI = LIS->getInterval(Reg);
1934 if (LI.hasSubRanges()) {
1935 // The COPY no longer defines subregs of %reg except for
1936 // %reg.subidx.
1937 LaneBitmask LaneMask =
1938 TRI->getSubRegIndexLaneMask(SubIdx: mi->getOperand(i: 0).getSubReg());
1939 SlotIndex Idx = LIS->getInstructionIndex(Instr: *mi).getRegSlot();
1940 for (auto &S : LI.subranges()) {
1941 if ((S.LaneMask & LaneMask).none()) {
1942 LiveRange::iterator DefSeg = S.FindSegmentContaining(Idx);
1943 if (mi->getOperand(i: 0).isUndef()) {
1944 S.removeValNo(ValNo: DefSeg->valno);
1945 } else {
1946 LiveRange::iterator UseSeg = std::prev(x: DefSeg);
1947 S.MergeValueNumberInto(V1: DefSeg->valno, V2: UseSeg->valno);
1948 }
1949 }
1950 }
1951
1952 // The COPY no longer has a use of %reg.
1953 LIS->shrinkToUses(li: &LI);
1954 } else {
1955 // The live interval for Reg did not have subranges but now it needs
1956 // them because we have introduced a subreg def. Recompute it.
1957 LIS->removeInterval(Reg);
1958 LIS->createAndComputeVirtRegInterval(Reg);
1959 }
1960 }
1961 }
1962
1963 // Clear TiedOperands here instead of at the top of the loop
1964 // since most instructions do not have tied operands.
1965 TiedOperands.clear();
1966 removeClobberedSrcRegMap(MI: &*mi);
1967 mi = nmi;
1968 }
1969 }
1970
1971 return MadeChange;
1972}
1973
1974/// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1975///
1976/// The instruction is turned into a sequence of sub-register copies:
1977///
1978/// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1979///
1980/// Becomes:
1981///
1982/// undef %dst:ssub0 = COPY %v1
1983/// %dst:ssub1 = COPY %v2
1984void TwoAddressInstructionImpl::eliminateRegSequence(
1985 MachineBasicBlock::iterator &MBBI) {
1986 MachineInstr &MI = *MBBI;
1987 Register DstReg = MI.getOperand(i: 0).getReg();
1988
1989 SmallVector<Register, 4> OrigRegs;
1990 VNInfo *DefVN = nullptr;
1991 if (LIS) {
1992 OrigRegs.push_back(Elt: MI.getOperand(i: 0).getReg());
1993 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
1994 OrigRegs.push_back(Elt: MI.getOperand(i).getReg());
1995 if (LIS->hasInterval(Reg: DstReg)) {
1996 DefVN = LIS->getInterval(Reg: DstReg)
1997 .Query(Idx: LIS->getInstructionIndex(Instr: MI))
1998 .valueOut();
1999 }
2000 }
2001
2002 LaneBitmask UndefLanes = LaneBitmask::getNone();
2003 bool DefEmitted = false;
2004 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
2005 MachineOperand &UseMO = MI.getOperand(i);
2006 Register SrcReg = UseMO.getReg();
2007 unsigned SubIdx = MI.getOperand(i: i+1).getImm();
2008 // Nothing needs to be inserted for undef operands.
2009 if (UseMO.isUndef()) {
2010 UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx);
2011 continue;
2012 }
2013
2014 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
2015 // might insert a COPY that uses SrcReg after is was killed.
2016 bool isKill = UseMO.isKill();
2017 if (isKill)
2018 for (unsigned j = i + 2; j < e; j += 2)
2019 if (MI.getOperand(i: j).getReg() == SrcReg) {
2020 MI.getOperand(i: j).setIsKill();
2021 UseMO.setIsKill(false);
2022 isKill = false;
2023 break;
2024 }
2025
2026 // Insert the sub-register copy.
2027 MachineInstr *CopyMI = BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(),
2028 MCID: TII->get(Opcode: TargetOpcode::COPY))
2029 .addReg(RegNo: DstReg, flags: RegState::Define, SubReg: SubIdx)
2030 .add(MO: UseMO);
2031
2032 // The first def needs an undef flag because there is no live register
2033 // before it.
2034 if (!DefEmitted) {
2035 CopyMI->getOperand(i: 0).setIsUndef(true);
2036 // Return an iterator pointing to the first inserted instr.
2037 MBBI = CopyMI;
2038 }
2039 DefEmitted = true;
2040
2041 // Update LiveVariables' kill info.
2042 if (LV && isKill && !SrcReg.isPhysical())
2043 LV->replaceKillInstruction(Reg: SrcReg, OldMI&: MI, NewMI&: *CopyMI);
2044
2045 LLVM_DEBUG(dbgs() << "Inserted: " << *CopyMI);
2046 }
2047
2048 MachineBasicBlock::iterator EndMBBI =
2049 std::next(x: MachineBasicBlock::iterator(MI));
2050
2051 if (!DefEmitted) {
2052 LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
2053 MI.setDesc(TII->get(Opcode: TargetOpcode::IMPLICIT_DEF));
2054 for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
2055 MI.removeOperand(OpNo: j);
2056 } else {
2057 if (LIS) {
2058 // Force live interval recomputation if we moved to a partial definition
2059 // of the register. Undef flags must be propagate to uses of undefined
2060 // subregister for accurate interval computation.
2061 if (UndefLanes.any() && DefVN && MRI->shouldTrackSubRegLiveness(VReg: DstReg)) {
2062 auto &LI = LIS->getInterval(Reg: DstReg);
2063 for (MachineOperand &UseOp : MRI->use_operands(Reg: DstReg)) {
2064 unsigned SubReg = UseOp.getSubReg();
2065 if (UseOp.isUndef() || !SubReg)
2066 continue;
2067 auto *VN =
2068 LI.getVNInfoAt(Idx: LIS->getInstructionIndex(Instr: *UseOp.getParent()));
2069 if (DefVN != VN)
2070 continue;
2071 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubIdx: SubReg);
2072 if ((UndefLanes & LaneMask).any())
2073 UseOp.setIsUndef(true);
2074 }
2075 LIS->removeInterval(Reg: DstReg);
2076 }
2077 LIS->RemoveMachineInstrFromMaps(MI);
2078 }
2079
2080 LLVM_DEBUG(dbgs() << "Eliminated: " << MI);
2081 MI.eraseFromParent();
2082 }
2083
2084 // Udpate LiveIntervals.
2085 if (LIS)
2086 LIS->repairIntervalsInRange(MBB, Begin: MBBI, End: EndMBBI, OrigRegs);
2087}
2088