1//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides ARM specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMMCTargetDesc.h"
14#include "ARMAddressingModes.h"
15#include "ARMBaseInfo.h"
16#include "ARMInstPrinter.h"
17#include "ARMMCAsmInfo.h"
18#include "TargetInfo/ARMTargetInfo.h"
19#include "llvm/DebugInfo/CodeView/CodeView.h"
20#include "llvm/MC/MCAsmBackend.h"
21#include "llvm/MC/MCCodeEmitter.h"
22#include "llvm/MC/MCELFStreamer.h"
23#include "llvm/MC/MCInstrAnalysis.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCObjectWriter.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Support/Compiler.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/TargetParser/Triple.h"
33
34using namespace llvm;
35
36#define GET_REGINFO_MC_DESC
37#include "ARMGenRegisterInfo.inc"
38
39static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
40 std::string &Info) {
41 if (STI.hasFeature(Feature: llvm::ARM::HasV7Ops) &&
42 (MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 15) &&
43 (MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 0) &&
44 // Checks for the deprecated CP15ISB encoding:
45 // mcr p15, #0, rX, c7, c5, #4
46 (MI.getOperand(i: 3).isImm() && MI.getOperand(i: 3).getImm() == 7)) {
47 if ((MI.getOperand(i: 5).isImm() && MI.getOperand(i: 5).getImm() == 4)) {
48 if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 5) {
49 Info = "deprecated since v7, use 'isb'";
50 return true;
51 }
52
53 // Checks for the deprecated CP15DSB encoding:
54 // mcr p15, #0, rX, c7, c10, #4
55 if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 10) {
56 Info = "deprecated since v7, use 'dsb'";
57 return true;
58 }
59 }
60 // Checks for the deprecated CP15DMB encoding:
61 // mcr p15, #0, rX, c7, c10, #5
62 if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 10 &&
63 (MI.getOperand(i: 5).isImm() && MI.getOperand(i: 5).getImm() == 5)) {
64 Info = "deprecated since v7, use 'dmb'";
65 return true;
66 }
67 }
68 if (STI.hasFeature(Feature: llvm::ARM::HasV7Ops) &&
69 ((MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 10) ||
70 (MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 11))) {
71 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
72 "point instructions";
73 return true;
74 }
75 return false;
76}
77
78static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
79 std::string &Info) {
80 if (STI.hasFeature(Feature: llvm::ARM::HasV7Ops) &&
81 ((MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 10) ||
82 (MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 11))) {
83 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
84 "point instructions";
85 return true;
86 }
87 return false;
88}
89
90static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
91 std::string &Info) {
92 assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
93 "cannot predicate thumb instructions");
94
95 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
96 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
97 assert(MI.getOperand(OI).isReg() && "expected register");
98 if (MI.getOperand(i: OI).getReg() == ARM::PC) {
99 Info = "use of PC in the list is deprecated";
100 return true;
101 }
102 }
103 return false;
104}
105
106static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
107 std::string &Info) {
108 assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
109 "cannot predicate thumb instructions");
110
111 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
112 bool ListContainsPC = false, ListContainsLR = false;
113 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
114 assert(MI.getOperand(OI).isReg() && "expected register");
115 switch (MI.getOperand(i: OI).getReg().id()) {
116 default:
117 break;
118 case ARM::LR:
119 ListContainsLR = true;
120 break;
121 case ARM::PC:
122 ListContainsPC = true;
123 break;
124 }
125 }
126
127 if (ListContainsPC && ListContainsLR) {
128 Info = "use of LR and PC simultaneously in the list is deprecated";
129 return true;
130 }
131
132 return false;
133}
134
135#define GET_INSTRINFO_MC_DESC
136#define ENABLE_INSTR_PREDICATE_VERIFIER
137#include "ARMGenInstrInfo.inc"
138
139#define GET_SUBTARGETINFO_MC_DESC
140#include "ARMGenSubtargetInfo.inc"
141
142std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
143 std::string ARMArchFeature;
144
145 ARM::ArchKind ArchID = ARM::parseArch(Arch: TT.getArchName());
146 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
147 ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(AK: ArchID)).str();
148
149 if (TT.isThumb()) {
150 if (!ARMArchFeature.empty())
151 ARMArchFeature += ",";
152 ARMArchFeature += "+thumb-mode,+v4t";
153 }
154
155 if (TT.isOSNaCl()) {
156 if (!ARMArchFeature.empty())
157 ARMArchFeature += ",";
158 ARMArchFeature += "+nacl-trap";
159 }
160
161 if (TT.isOSWindows()) {
162 if (!ARMArchFeature.empty())
163 ARMArchFeature += ",";
164 ARMArchFeature += "+noarm";
165 }
166
167 return ARMArchFeature;
168}
169
170bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
171 const MCInstrDesc &Desc = MCII->get(Opcode: MI.getOpcode());
172 int PredOpIdx = Desc.findFirstPredOperandIdx();
173 return PredOpIdx != -1 && MI.getOperand(i: PredOpIdx).getImm() != ARMCC::AL;
174}
175
176bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
177 const MCInstrDesc &Desc = MCII->get(Opcode: MI.getOpcode());
178 for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
179 const MCOperand &MO = MI.getOperand(i: I);
180 if (MO.isReg() && MO.getReg() == ARM::CPSR &&
181 Desc.operands()[I].isOptionalDef())
182 return true;
183 }
184 return false;
185}
186
187uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc,
188 uint64_t Addr, int64_t Imm) {
189 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
190 // is 4 bytes.
191 uint64_t Offset =
192 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8;
193
194 // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
195 // which is 32-bit aligned. The target address for the case is calculated as
196 // targetAddress = Align(PC,4) + imm32;
197 // where
198 // Align(x, y) = y * (x DIV y);
199 if (InstDesc.getOpcode() == ARM::tBLXi)
200 Addr &= ~0x3;
201
202 return Addr + Imm + Offset;
203}
204
205MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
206 StringRef CPU, StringRef FS) {
207 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
208 if (!FS.empty()) {
209 if (!ArchFS.empty())
210 ArchFS = (Twine(ArchFS) + "," + FS).str();
211 else
212 ArchFS = std::string(FS);
213 }
214
215 return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS: ArchFS);
216}
217
218static MCInstrInfo *createARMMCInstrInfo() {
219 MCInstrInfo *X = new MCInstrInfo();
220 InitARMMCInstrInfo(II: X);
221 return X;
222}
223
224void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
225 // Mapping from CodeView to MC register id.
226 static const struct {
227 codeview::RegisterId CVReg;
228 MCPhysReg Reg;
229 } RegMap[] = {
230 {.CVReg: codeview::RegisterId::ARM_R0, .Reg: ARM::R0},
231 {.CVReg: codeview::RegisterId::ARM_R1, .Reg: ARM::R1},
232 {.CVReg: codeview::RegisterId::ARM_R2, .Reg: ARM::R2},
233 {.CVReg: codeview::RegisterId::ARM_R3, .Reg: ARM::R3},
234 {.CVReg: codeview::RegisterId::ARM_R4, .Reg: ARM::R4},
235 {.CVReg: codeview::RegisterId::ARM_R5, .Reg: ARM::R5},
236 {.CVReg: codeview::RegisterId::ARM_R6, .Reg: ARM::R6},
237 {.CVReg: codeview::RegisterId::ARM_R7, .Reg: ARM::R7},
238 {.CVReg: codeview::RegisterId::ARM_R8, .Reg: ARM::R8},
239 {.CVReg: codeview::RegisterId::ARM_R9, .Reg: ARM::R9},
240 {.CVReg: codeview::RegisterId::ARM_R10, .Reg: ARM::R10},
241 {.CVReg: codeview::RegisterId::ARM_R11, .Reg: ARM::R11},
242 {.CVReg: codeview::RegisterId::ARM_R12, .Reg: ARM::R12},
243 {.CVReg: codeview::RegisterId::ARM_SP, .Reg: ARM::SP},
244 {.CVReg: codeview::RegisterId::ARM_LR, .Reg: ARM::LR},
245 {.CVReg: codeview::RegisterId::ARM_PC, .Reg: ARM::PC},
246 {.CVReg: codeview::RegisterId::ARM_CPSR, .Reg: ARM::CPSR},
247 {.CVReg: codeview::RegisterId::ARM_FPSCR, .Reg: ARM::FPSCR},
248 {.CVReg: codeview::RegisterId::ARM_FPEXC, .Reg: ARM::FPEXC},
249 {.CVReg: codeview::RegisterId::ARM_FS0, .Reg: ARM::S0},
250 {.CVReg: codeview::RegisterId::ARM_FS1, .Reg: ARM::S1},
251 {.CVReg: codeview::RegisterId::ARM_FS2, .Reg: ARM::S2},
252 {.CVReg: codeview::RegisterId::ARM_FS3, .Reg: ARM::S3},
253 {.CVReg: codeview::RegisterId::ARM_FS4, .Reg: ARM::S4},
254 {.CVReg: codeview::RegisterId::ARM_FS5, .Reg: ARM::S5},
255 {.CVReg: codeview::RegisterId::ARM_FS6, .Reg: ARM::S6},
256 {.CVReg: codeview::RegisterId::ARM_FS7, .Reg: ARM::S7},
257 {.CVReg: codeview::RegisterId::ARM_FS8, .Reg: ARM::S8},
258 {.CVReg: codeview::RegisterId::ARM_FS9, .Reg: ARM::S9},
259 {.CVReg: codeview::RegisterId::ARM_FS10, .Reg: ARM::S10},
260 {.CVReg: codeview::RegisterId::ARM_FS11, .Reg: ARM::S11},
261 {.CVReg: codeview::RegisterId::ARM_FS12, .Reg: ARM::S12},
262 {.CVReg: codeview::RegisterId::ARM_FS13, .Reg: ARM::S13},
263 {.CVReg: codeview::RegisterId::ARM_FS14, .Reg: ARM::S14},
264 {.CVReg: codeview::RegisterId::ARM_FS15, .Reg: ARM::S15},
265 {.CVReg: codeview::RegisterId::ARM_FS16, .Reg: ARM::S16},
266 {.CVReg: codeview::RegisterId::ARM_FS17, .Reg: ARM::S17},
267 {.CVReg: codeview::RegisterId::ARM_FS18, .Reg: ARM::S18},
268 {.CVReg: codeview::RegisterId::ARM_FS19, .Reg: ARM::S19},
269 {.CVReg: codeview::RegisterId::ARM_FS20, .Reg: ARM::S20},
270 {.CVReg: codeview::RegisterId::ARM_FS21, .Reg: ARM::S21},
271 {.CVReg: codeview::RegisterId::ARM_FS22, .Reg: ARM::S22},
272 {.CVReg: codeview::RegisterId::ARM_FS23, .Reg: ARM::S23},
273 {.CVReg: codeview::RegisterId::ARM_FS24, .Reg: ARM::S24},
274 {.CVReg: codeview::RegisterId::ARM_FS25, .Reg: ARM::S25},
275 {.CVReg: codeview::RegisterId::ARM_FS26, .Reg: ARM::S26},
276 {.CVReg: codeview::RegisterId::ARM_FS27, .Reg: ARM::S27},
277 {.CVReg: codeview::RegisterId::ARM_FS28, .Reg: ARM::S28},
278 {.CVReg: codeview::RegisterId::ARM_FS29, .Reg: ARM::S29},
279 {.CVReg: codeview::RegisterId::ARM_FS30, .Reg: ARM::S30},
280 {.CVReg: codeview::RegisterId::ARM_FS31, .Reg: ARM::S31},
281 {.CVReg: codeview::RegisterId::ARM_ND0, .Reg: ARM::D0},
282 {.CVReg: codeview::RegisterId::ARM_ND1, .Reg: ARM::D1},
283 {.CVReg: codeview::RegisterId::ARM_ND2, .Reg: ARM::D2},
284 {.CVReg: codeview::RegisterId::ARM_ND3, .Reg: ARM::D3},
285 {.CVReg: codeview::RegisterId::ARM_ND4, .Reg: ARM::D4},
286 {.CVReg: codeview::RegisterId::ARM_ND5, .Reg: ARM::D5},
287 {.CVReg: codeview::RegisterId::ARM_ND6, .Reg: ARM::D6},
288 {.CVReg: codeview::RegisterId::ARM_ND7, .Reg: ARM::D7},
289 {.CVReg: codeview::RegisterId::ARM_ND8, .Reg: ARM::D8},
290 {.CVReg: codeview::RegisterId::ARM_ND9, .Reg: ARM::D9},
291 {.CVReg: codeview::RegisterId::ARM_ND10, .Reg: ARM::D10},
292 {.CVReg: codeview::RegisterId::ARM_ND11, .Reg: ARM::D11},
293 {.CVReg: codeview::RegisterId::ARM_ND12, .Reg: ARM::D12},
294 {.CVReg: codeview::RegisterId::ARM_ND13, .Reg: ARM::D13},
295 {.CVReg: codeview::RegisterId::ARM_ND14, .Reg: ARM::D14},
296 {.CVReg: codeview::RegisterId::ARM_ND15, .Reg: ARM::D15},
297 {.CVReg: codeview::RegisterId::ARM_ND16, .Reg: ARM::D16},
298 {.CVReg: codeview::RegisterId::ARM_ND17, .Reg: ARM::D17},
299 {.CVReg: codeview::RegisterId::ARM_ND18, .Reg: ARM::D18},
300 {.CVReg: codeview::RegisterId::ARM_ND19, .Reg: ARM::D19},
301 {.CVReg: codeview::RegisterId::ARM_ND20, .Reg: ARM::D20},
302 {.CVReg: codeview::RegisterId::ARM_ND21, .Reg: ARM::D21},
303 {.CVReg: codeview::RegisterId::ARM_ND22, .Reg: ARM::D22},
304 {.CVReg: codeview::RegisterId::ARM_ND23, .Reg: ARM::D23},
305 {.CVReg: codeview::RegisterId::ARM_ND24, .Reg: ARM::D24},
306 {.CVReg: codeview::RegisterId::ARM_ND25, .Reg: ARM::D25},
307 {.CVReg: codeview::RegisterId::ARM_ND26, .Reg: ARM::D26},
308 {.CVReg: codeview::RegisterId::ARM_ND27, .Reg: ARM::D27},
309 {.CVReg: codeview::RegisterId::ARM_ND28, .Reg: ARM::D28},
310 {.CVReg: codeview::RegisterId::ARM_ND29, .Reg: ARM::D29},
311 {.CVReg: codeview::RegisterId::ARM_ND30, .Reg: ARM::D30},
312 {.CVReg: codeview::RegisterId::ARM_ND31, .Reg: ARM::D31},
313 {.CVReg: codeview::RegisterId::ARM_NQ0, .Reg: ARM::Q0},
314 {.CVReg: codeview::RegisterId::ARM_NQ1, .Reg: ARM::Q1},
315 {.CVReg: codeview::RegisterId::ARM_NQ2, .Reg: ARM::Q2},
316 {.CVReg: codeview::RegisterId::ARM_NQ3, .Reg: ARM::Q3},
317 {.CVReg: codeview::RegisterId::ARM_NQ4, .Reg: ARM::Q4},
318 {.CVReg: codeview::RegisterId::ARM_NQ5, .Reg: ARM::Q5},
319 {.CVReg: codeview::RegisterId::ARM_NQ6, .Reg: ARM::Q6},
320 {.CVReg: codeview::RegisterId::ARM_NQ7, .Reg: ARM::Q7},
321 {.CVReg: codeview::RegisterId::ARM_NQ8, .Reg: ARM::Q8},
322 {.CVReg: codeview::RegisterId::ARM_NQ9, .Reg: ARM::Q9},
323 {.CVReg: codeview::RegisterId::ARM_NQ10, .Reg: ARM::Q10},
324 {.CVReg: codeview::RegisterId::ARM_NQ11, .Reg: ARM::Q11},
325 {.CVReg: codeview::RegisterId::ARM_NQ12, .Reg: ARM::Q12},
326 {.CVReg: codeview::RegisterId::ARM_NQ13, .Reg: ARM::Q13},
327 {.CVReg: codeview::RegisterId::ARM_NQ14, .Reg: ARM::Q14},
328 {.CVReg: codeview::RegisterId::ARM_NQ15, .Reg: ARM::Q15},
329 };
330 for (const auto &I : RegMap)
331 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
332}
333
334static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
335 MCRegisterInfo *X = new MCRegisterInfo();
336 InitARMMCRegisterInfo(RI: X, RA: ARM::LR, DwarfFlavour: 0, EHFlavour: 0, PC: ARM::PC);
337 ARM_MC::initLLVMToCVRegMapping(MRI: X);
338 return X;
339}
340
341static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
342 const Triple &TheTriple,
343 const MCTargetOptions &Options) {
344 MCAsmInfo *MAI;
345 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
346 MAI = new ARMMCAsmInfoDarwin(TheTriple);
347 else if (TheTriple.isWindowsMSVCEnvironment())
348 MAI = new ARMCOFFMCAsmInfoMicrosoft();
349 else if (TheTriple.isOSWindows())
350 MAI = new ARMCOFFMCAsmInfoGNU();
351 else
352 MAI = new ARMELFMCAsmInfo(TheTriple);
353
354 unsigned Reg = MRI.getDwarfRegNum(RegNum: ARM::SP, isEH: true);
355 MAI->addInitialFrameState(Inst: MCCFIInstruction::cfiDefCfa(L: nullptr, Register: Reg, Offset: 0));
356
357 return MAI;
358}
359
360static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
361 std::unique_ptr<MCAsmBackend> &&MAB,
362 std::unique_ptr<MCObjectWriter> &&OW,
363 std::unique_ptr<MCCodeEmitter> &&Emitter) {
364 return createARMELFStreamer(
365 Context&: Ctx, TAB: std::move(MAB), OW: std::move(OW), Emitter: std::move(Emitter),
366 IsThumb: (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
367 IsAndroid: T.isAndroid());
368}
369
370static MCStreamer *
371createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
372 std::unique_ptr<MCObjectWriter> &&OW,
373 std::unique_ptr<MCCodeEmitter> &&Emitter) {
374 return createMachOStreamer(Ctx, TAB: std::move(MAB), OW: std::move(OW),
375 CE: std::move(Emitter), DWARFMustBeAtTheEnd: false);
376}
377
378static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
379 unsigned SyntaxVariant,
380 const MCAsmInfo &MAI,
381 const MCInstrInfo &MII,
382 const MCRegisterInfo &MRI) {
383 if (SyntaxVariant == 0)
384 return new ARMInstPrinter(MAI, MII, MRI);
385 return nullptr;
386}
387
388static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
389 MCContext &Ctx) {
390 if (TT.isOSBinFormatMachO())
391 return createARMMachORelocationInfo(Ctx);
392 // Default to the stock relocation info.
393 return llvm::createMCRelocationInfo(TT, Ctx);
394}
395
396namespace {
397
398class ARMMCInstrAnalysis : public MCInstrAnalysis {
399public:
400 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
401
402 bool isUnconditionalBranch(const MCInst &Inst) const override {
403 // BCCs with the "always" predicate are unconditional branches.
404 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(i: 1).getImm()==ARMCC::AL)
405 return true;
406 return MCInstrAnalysis::isUnconditionalBranch(Inst);
407 }
408
409 bool isConditionalBranch(const MCInst &Inst) const override {
410 // BCCs with the "always" predicate are unconditional branches.
411 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(i: 1).getImm()==ARMCC::AL)
412 return false;
413 return MCInstrAnalysis::isConditionalBranch(Inst);
414 }
415
416 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
417 uint64_t &Target) const override {
418 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
419
420 // Find the PC-relative immediate operand in the instruction.
421 for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) {
422 if (Inst.getOperand(i: OpNum).isImm() &&
423 Desc.operands()[OpNum].OperandType == MCOI::OPERAND_PCREL) {
424 int64_t Imm = Inst.getOperand(i: OpNum).getImm();
425 Target = ARM_MC::evaluateBranchTarget(InstDesc: Desc, Addr, Imm);
426 return true;
427 }
428 }
429 return false;
430 }
431
432 std::optional<uint64_t>
433 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
434 uint64_t Addr, uint64_t Size) const override;
435
436 std::vector<std::pair<uint64_t, uint64_t>>
437 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
438 const MCSubtargetInfo &STI) const override;
439};
440
441} // namespace
442
443static std::optional<uint64_t>
444// NOLINTNEXTLINE(readability-identifier-naming)
445evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc,
446 unsigned MemOpIndex, uint64_t Addr) {
447 if (MemOpIndex + 1 >= Desc.getNumOperands())
448 return std::nullopt;
449
450 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
451 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
452 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
453 return std::nullopt;
454
455 int32_t OffImm = (int32_t)MO2.getImm();
456 // Special value for #-0. All others are normal.
457 if (OffImm == INT32_MIN)
458 OffImm = 0;
459 return Addr + OffImm;
460}
461
462static std::optional<uint64_t>
463evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc,
464 unsigned MemOpIndex, uint64_t Addr) {
465 if (MemOpIndex + 2 >= Desc.getNumOperands())
466 return std::nullopt;
467
468 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
469 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
470 const MCOperand &MO3 = Inst.getOperand(i: MemOpIndex + 2);
471 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm())
472 return std::nullopt;
473
474 unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc: MO3.getImm());
475 ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(AM3Opc: MO3.getImm());
476
477 if (Op == ARM_AM::sub)
478 return Addr - ImmOffs;
479 return Addr + ImmOffs;
480}
481
482static std::optional<uint64_t>
483evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc,
484 unsigned MemOpIndex, uint64_t Addr) {
485 if (MemOpIndex + 1 >= Desc.getNumOperands())
486 return std::nullopt;
487
488 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
489 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
490 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
491 return std::nullopt;
492
493 unsigned ImmOffs = ARM_AM::getAM5Offset(AM5Opc: MO2.getImm());
494 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(AM5Opc: MO2.getImm());
495
496 if (Op == ARM_AM::sub)
497 return Addr - ImmOffs * 4;
498 return Addr + ImmOffs * 4;
499}
500
501static std::optional<uint64_t>
502evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc,
503 unsigned MemOpIndex, uint64_t Addr) {
504 if (MemOpIndex + 1 >= Desc.getNumOperands())
505 return std::nullopt;
506
507 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
508 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
509 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
510 return std::nullopt;
511
512 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(AM5Opc: MO2.getImm());
513 ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(AM5Opc: MO2.getImm());
514
515 if (Op == ARM_AM::sub)
516 return Addr - ImmOffs * 2;
517 return Addr + ImmOffs * 2;
518}
519
520static std::optional<uint64_t>
521// NOLINTNEXTLINE(readability-identifier-naming)
522evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc,
523 unsigned MemOpIndex, uint64_t Addr) {
524 if (MemOpIndex + 1 >= Desc.getNumOperands())
525 return std::nullopt;
526
527 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
528 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
529 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
530 return std::nullopt;
531
532 int32_t OffImm = (int32_t)MO2.getImm();
533 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
534
535 // Special value for #-0. All others are normal.
536 if (OffImm == INT32_MIN)
537 OffImm = 0;
538 return Addr + OffImm;
539}
540
541static std::optional<uint64_t>
542// NOLINTNEXTLINE(readability-identifier-naming)
543evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc,
544 unsigned MemOpIndex, uint64_t Addr) {
545 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
546 if (!MO1.isImm())
547 return std::nullopt;
548
549 int32_t OffImm = (int32_t)MO1.getImm();
550
551 // Special value for #-0. All others are normal.
552 if (OffImm == INT32_MIN)
553 OffImm = 0;
554 return Addr + OffImm;
555}
556
557static std::optional<uint64_t>
558// NOLINTNEXTLINE(readability-identifier-naming)
559evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc,
560 unsigned MemOpIndex, uint64_t Addr) {
561 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr);
562}
563
564std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
565 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
566 uint64_t Size) const {
567 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
568
569 // Only load instructions can have PC-relative memory addressing.
570 if (!Desc.mayLoad())
571 return std::nullopt;
572
573 // PC-relative addressing does not update the base register.
574 uint64_t TSFlags = Desc.TSFlags;
575 unsigned IndexMode =
576 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
577 if (IndexMode != ARMII::IndexModeNone)
578 return std::nullopt;
579
580 // Find the memory addressing operand in the instruction.
581 unsigned OpIndex = Desc.NumDefs;
582 while (OpIndex < Desc.getNumOperands() &&
583 Desc.operands()[OpIndex].OperandType != MCOI::OPERAND_MEMORY)
584 ++OpIndex;
585 if (OpIndex == Desc.getNumOperands())
586 return std::nullopt;
587
588 // Base address for PC-relative addressing is always 32-bit aligned.
589 Addr &= ~0x3;
590
591 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
592 // is 4 bytes.
593 switch (Desc.TSFlags & ARMII::FormMask) {
594 default:
595 Addr += 8;
596 break;
597 case ARMII::ThumbFrm:
598 Addr += 4;
599 break;
600 // VLDR* instructions share the same opcode (and thus the same form) for Arm
601 // and Thumb. Use a bit longer route through STI in that case.
602 case ARMII::VFPLdStFrm:
603 Addr += STI->hasFeature(Feature: ARM::ModeThumb) ? 4 : 8;
604 break;
605 }
606
607 // Eveluate the address depending on the addressing mode
608 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
609 switch (AddrMode) {
610 default:
611 return std::nullopt;
612 case ARMII::AddrMode_i12:
613 return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, MemOpIndex: OpIndex, Addr);
614 case ARMII::AddrMode3:
615 return evaluateMemOpAddrForAddrMode3(Inst, Desc, MemOpIndex: OpIndex, Addr);
616 case ARMII::AddrMode5:
617 return evaluateMemOpAddrForAddrMode5(Inst, Desc, MemOpIndex: OpIndex, Addr);
618 case ARMII::AddrMode5FP16:
619 return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, MemOpIndex: OpIndex, Addr);
620 case ARMII::AddrModeT2_i8s4:
621 return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, MemOpIndex: OpIndex, Addr);
622 case ARMII::AddrModeT2_pc:
623 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex: OpIndex, Addr);
624 case ARMII::AddrModeT1_s:
625 return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, MemOpIndex: OpIndex, Addr);
626 }
627}
628
629template <typename T, size_t N>
630static bool instructionsMatch(const T (&Insns)[N], const uint8_t *Buf,
631 llvm::endianness E) {
632 for (size_t I = 0; I < N; ++I) {
633 T Val = support::endian::read<T>(Buf + I * sizeof(T), E);
634 if (Val != Insns[I])
635 return false;
636 }
637 return true;
638}
639
640std::vector<std::pair<uint64_t, uint64_t>>
641ARMMCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,
642 ArrayRef<uint8_t> PltContents,
643 const MCSubtargetInfo &STI) const {
644 llvm::endianness DataEndianness = STI.getTargetTriple().isLittleEndian()
645 ? endianness::little
646 : endianness::big;
647 llvm::endianness InstrEndianness =
648 STI.checkFeatures(FS: "+big-endian-instructions") ? endianness::big
649 : endianness::little;
650
651 // Do a lightweight parsing of PLT entries.
652 std::vector<std::pair<uint64_t, uint64_t>> Result;
653 if (STI.checkFeatures(FS: "+thumb-mode")) {
654 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 12 < End;
655 Byte += 16) {
656 // Expected instruction sequence:
657 //
658 // movw ip, #lower16
659 // movt ip, #upper16
660 // add ip, pc
661 // ldr.w pc, [ip]
662 // b . -4
663
664 uint32_t MovwPart1 =
665 support::endian::read16(P: PltContents.data() + Byte, E: InstrEndianness);
666 if ((MovwPart1 & 0xffb0) != 0xf200)
667 continue;
668
669 uint32_t MovwPart2 = support::endian::read16(
670 P: PltContents.data() + Byte + 2, E: InstrEndianness);
671 if ((MovwPart2 & 0x8f00) != 0xc00)
672 continue;
673
674 uint64_t OffsetLower = (MovwPart2 & 0xff) + ((MovwPart2 & 0x7000) >> 4) +
675 ((MovwPart1 & 0x400) << 1) +
676 ((MovwPart1 & 0xf) << 12);
677
678 uint32_t MovtPart1 = support::endian::read16(
679 P: PltContents.data() + Byte + 4, E: InstrEndianness);
680 if ((MovtPart1 & 0xfbf0) != 0xf2c0)
681 continue;
682
683 uint32_t MovtPart2 = support::endian::read16(
684 P: PltContents.data() + Byte + 6, E: InstrEndianness);
685 if ((MovtPart2 & 0x8f00) != 0xc00)
686 continue;
687
688 uint64_t OffsetHigher =
689 ((MovtPart2 & 0xff) << 16) + ((MovtPart2 & 0x7000) << 12) +
690 ((MovtPart1 & 0x400) << 17) + ((MovtPart1 & 0xf) << 28);
691
692 const uint16_t Insns[] = {
693 0x44fc, // add ip, pc
694 0xf8dc, 0xf000, // ldr.w pc, [ip]
695 0xe7fc, // b . -4
696 };
697
698 if (!instructionsMatch(Insns, Buf: PltContents.data() + Byte + 8,
699 E: InstrEndianness))
700 continue;
701
702 // add ip, pc at Byte + 8 + thumb-pc-bias = 12
703 uint64_t Offset = (PltSectionVA + Byte + 12) + OffsetLower + OffsetHigher;
704 Result.emplace_back(args: PltSectionVA + Byte, args&: Offset);
705 }
706 } else {
707 const uint32_t LongEntryInsns[] = {
708 0xe59fc004, // ldr ip, L2
709 0xe08cc00f, // L1: add ip, ip, pc
710 0xe59cf000, // ldr pc, [ip]
711 };
712
713 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 12 < End;
714 Byte += 4) {
715 // Is it a long entry?
716 if (instructionsMatch(Insns: LongEntryInsns, Buf: PltContents.data() + Byte,
717 E: InstrEndianness)) {
718 // Expected instruction sequence:
719 //
720 // ldr ip, L2
721 // L1: add ip, ip, pc
722 // ldr pc, [ip]
723 // L2: .word Offset(&(.got.plt) - L1 - 8
724
725 uint64_t Offset = (PltSectionVA + Byte + 12) +
726 support::endian::read32(
727 P: PltContents.data() + Byte + 12, E: DataEndianness);
728 Result.emplace_back(args: PltSectionVA + Byte, args&: Offset);
729 Byte += 12;
730 } else {
731 // Expected instruction sequence:
732 //
733 // L1: add ip, pc, #0x0NN00000 Offset(&(.got.plt) - L1 - 8
734 // add ip, ip, #0x000NN000 Offset(&(.got.plt) - L1 - 8
735 // ldr pc, [ip, #0x00000NNN] Offset(&(.got.plt) - L1 - 8
736
737 uint32_t Add1 =
738 support::endian::read32(P: PltContents.data() + Byte, E: InstrEndianness);
739 if ((Add1 & 0xe28fc600) != 0xe28fc600)
740 continue;
741 uint32_t Add2 = support::endian::read32(P: PltContents.data() + Byte + 4,
742 E: InstrEndianness);
743 if ((Add2 & 0xe28cca00) != 0xe28cca00)
744 continue;
745 uint32_t Ldr = support::endian::read32(P: PltContents.data() + Byte + 8,
746 E: InstrEndianness);
747 if ((Ldr & 0xe5bcf000) != 0xe5bcf000)
748 continue;
749
750 // add ip, pc, #offset at Byte + 0 + arm-pc-bias = 8
751 uint64_t Offset = (PltSectionVA + Byte + 8) + ((Add1 & 0xff) << 20) +
752 ((Add2 & 0xff) << 12) + (Ldr & 0xfff);
753 Result.emplace_back(args: PltSectionVA + Byte, args&: Offset);
754 Byte += 8;
755 }
756 }
757 }
758 return Result;
759}
760
761static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
762 return new ARMMCInstrAnalysis(Info);
763}
764
765bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
766 // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
767 // to rely on feature bits.
768 if (Coproc >= 8)
769 return false;
770 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
771}
772
773// Force static initialization.
774extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() {
775 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
776 &getTheThumbLETarget(), &getTheThumbBETarget()}) {
777 // Register the MC asm info.
778 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
779
780 // Register the MC instruction info.
781 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createARMMCInstrInfo);
782
783 // Register the MC register info.
784 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createARMMCRegisterInfo);
785
786 // Register the MC subtarget info.
787 TargetRegistry::RegisterMCSubtargetInfo(T&: *T,
788 Fn: ARM_MC::createARMMCSubtargetInfo);
789
790 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createELFStreamer);
791 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createARMWinCOFFStreamer);
792 TargetRegistry::RegisterMachOStreamer(T&: *T, Fn: createARMMachOStreamer);
793
794 // Register the obj target streamer.
795 TargetRegistry::RegisterObjectTargetStreamer(T&: *T,
796 Fn: createARMObjectTargetStreamer);
797
798 // Register the asm streamer.
799 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createARMTargetAsmStreamer);
800
801 // Register the null TargetStreamer.
802 TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createARMNullTargetStreamer);
803
804 // Register the MCInstPrinter.
805 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createARMMCInstPrinter);
806
807 // Register the MC relocation info.
808 TargetRegistry::RegisterMCRelocationInfo(T&: *T, Fn: createARMMCRelocationInfo);
809 }
810
811 // Register the MC instruction analyzer.
812 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
813 &getTheThumbLETarget(), &getTheThumbBETarget()})
814 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createARMMCInstrAnalysis);
815
816 for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
817 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createARMLEMCCodeEmitter);
818 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createARMLEAsmBackend);
819 }
820 for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
821 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createARMBEMCCodeEmitter);
822 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createARMBEAsmBackend);
823 }
824}
825