1//===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the BPFMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/BPFMCFixups.h"
14#include "MCTargetDesc/BPFMCTargetDesc.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/MC/MCCodeEmitter.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCFixup.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/EndianStream.h"
25#include <cassert>
26#include <cstdint>
27
28using namespace llvm;
29
30#define DEBUG_TYPE "mccodeemitter"
31
32namespace {
33
34class BPFMCCodeEmitter : public MCCodeEmitter {
35 const MCRegisterInfo &MRI;
36 bool IsLittleEndian;
37 MCContext &Ctx;
38
39public:
40 BPFMCCodeEmitter(const MCInstrInfo &, const MCRegisterInfo &mri,
41 bool IsLittleEndian, MCContext &ctx)
42 : MRI(mri), IsLittleEndian(IsLittleEndian), Ctx(ctx) {}
43 BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete;
44 void operator=(const BPFMCCodeEmitter &) = delete;
45 ~BPFMCCodeEmitter() override = default;
46
47 // getBinaryCodeForInstr - TableGen'erated function for getting the
48 // binary encoding for an instruction.
49 uint64_t getBinaryCodeForInstr(const MCInst &MI,
50 SmallVectorImpl<MCFixup> &Fixups,
51 const MCSubtargetInfo &STI) const;
52
53 // getMachineOpValue - Return binary encoding of operand. If the machin
54 // operand requires relocation, record the relocation and return zero.
55 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
56 SmallVectorImpl<MCFixup> &Fixups,
57 const MCSubtargetInfo &STI) const;
58
59 uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
60 SmallVectorImpl<MCFixup> &Fixups,
61 const MCSubtargetInfo &STI) const;
62
63 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
64 SmallVectorImpl<MCFixup> &Fixups,
65 const MCSubtargetInfo &STI) const override;
66};
67
68} // end anonymous namespace
69
70MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII,
71 MCContext &Ctx) {
72 return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), true, Ctx);
73}
74
75MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
76 MCContext &Ctx) {
77 return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), false, Ctx);
78}
79
80unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
81 const MCOperand &MO,
82 SmallVectorImpl<MCFixup> &Fixups,
83 const MCSubtargetInfo &STI) const {
84 if (MO.isReg())
85 return MRI.getEncodingValue(Reg: MO.getReg());
86 if (MO.isImm()) {
87 uint64_t Imm = MO.getImm();
88 uint64_t High32Bits = Imm >> 32, High33Bits = Imm >> 31;
89 if (MI.getOpcode() != BPF::LD_imm64 && High32Bits != 0 &&
90 High33Bits != 0x1FFFFFFFFULL) {
91 Ctx.reportWarning(L: MI.getLoc(),
92 Msg: "immediate out of range, shall fit in 32 bits");
93 }
94 return static_cast<unsigned>(Imm);
95 }
96
97 assert(MO.isExpr());
98
99 const MCExpr *Expr = MO.getExpr();
100
101 assert(Expr->getKind() == MCExpr::SymbolRef);
102
103 if (MI.getOpcode() == BPF::JAL)
104 // func call name
105 Fixups.push_back(Elt: MCFixup::create(Offset: 0, Value: Expr, Kind: FK_PCRel_4));
106 else if (MI.getOpcode() == BPF::LD_imm64)
107 Fixups.push_back(Elt: MCFixup::create(Offset: 0, Value: Expr, Kind: FK_SecRel_8));
108 else if (MI.getOpcode() == BPF::JMPL)
109 Fixups.push_back(Elt: MCFixup::create(Offset: 0, Value: Expr, Kind: (MCFixupKind)BPF::FK_BPF_PCRel_4));
110 else
111 // bb label
112 Fixups.push_back(Elt: MCFixup::create(Offset: 0, Value: Expr, Kind: FK_PCRel_2));
113
114 return 0;
115}
116
117static uint8_t SwapBits(uint8_t Val)
118{
119 return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
120}
121
122void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI,
123 SmallVectorImpl<char> &CB,
124 SmallVectorImpl<MCFixup> &Fixups,
125 const MCSubtargetInfo &STI) const {
126 unsigned Opcode = MI.getOpcode();
127 raw_svector_ostream OS(CB);
128 support::endian::Writer OSE(OS, IsLittleEndian ? llvm::endianness::little
129 : llvm::endianness::big);
130
131 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
132 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
133 CB.push_back(Elt: Value >> 56);
134 if (IsLittleEndian)
135 CB.push_back(Elt: (Value >> 48) & 0xff);
136 else
137 CB.push_back(Elt: SwapBits(Val: (Value >> 48) & 0xff));
138 OSE.write<uint16_t>(Val: 0);
139 OSE.write<uint32_t>(Val: Value & 0xffffFFFF);
140
141 const MCOperand &MO = MI.getOperand(i: 1);
142 uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
143 OSE.write<uint8_t>(Val: 0);
144 OSE.write<uint8_t>(Val: 0);
145 OSE.write<uint16_t>(Val: 0);
146 OSE.write<uint32_t>(Val: Imm >> 32);
147 } else {
148 // Get instruction encoding and emit it
149 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
150 CB.push_back(Elt: Value >> 56);
151 if (IsLittleEndian)
152 CB.push_back(Elt: char((Value >> 48) & 0xff));
153 else
154 CB.push_back(Elt: SwapBits(Val: (Value >> 48) & 0xff));
155 OSE.write<uint16_t>(Val: (Value >> 32) & 0xffff);
156 OSE.write<uint32_t>(Val: Value & 0xffffFFFF);
157 }
158}
159
160// Encode BPF Memory Operand
161uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
162 SmallVectorImpl<MCFixup> &Fixups,
163 const MCSubtargetInfo &STI) const {
164 // For CMPXCHG instructions, output is implicitly in R0/W0,
165 // so memory operand starts from operand 0.
166 int MemOpStartIndex = 1, Opcode = MI.getOpcode();
167 if (Opcode == BPF::CMPXCHGW32 || Opcode == BPF::CMPXCHGD)
168 MemOpStartIndex = 0;
169
170 uint64_t Encoding;
171 const MCOperand Op1 = MI.getOperand(i: MemOpStartIndex);
172 assert(Op1.isReg() && "First operand is not register.");
173 Encoding = MRI.getEncodingValue(Reg: Op1.getReg());
174 Encoding <<= 16;
175 MCOperand Op2 = MI.getOperand(i: MemOpStartIndex + 1);
176 assert(Op2.isImm() && "Second operand is not immediate.");
177 Encoding |= Op2.getImm() & 0xffff;
178 return Encoding;
179}
180
181#include "BPFGenMCCodeEmitter.inc"
182