1//===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the NVPTX implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
14#define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
15
16#include "NVPTX.h"
17#include "NVPTXRegisterInfo.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "NVPTXGenInstrInfo.inc"
22
23namespace llvm {
24
25class NVPTXInstrInfo : public NVPTXGenInstrInfo {
26 const NVPTXRegisterInfo RegInfo;
27 virtual void anchor();
28public:
29 explicit NVPTXInstrInfo();
30
31 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
32
33 /* The following virtual functions are used in register allocation.
34 * They are not implemented because the existing interface and the logic
35 * at the caller side do not work for the elementized vector load and store.
36 *
37 * virtual Register isLoadFromStackSlot(const MachineInstr *MI,
38 * int &FrameIndex) const;
39 * virtual Register isStoreToStackSlot(const MachineInstr *MI,
40 * int &FrameIndex) const;
41 * virtual void storeRegToStackSlot(
42 * MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
43 * unsigned SrcReg, bool isKill, int FrameIndex,
44 * const TargetRegisterClass *RC, Register VReg,
45 * MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const;
46 * virtual void loadRegFromStackSlot(
47 * MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 * unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC,
49 * const TargetRegisterInfo *TRI, Register VReg,
50 * MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const;
51 */
52
53 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
54 const DebugLoc &DL, Register DestReg, Register SrcReg,
55 bool KillSrc, bool RenamableDest = false,
56 bool RenamableSrc = false) const override;
57
58 // Branch analysis.
59 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
60 MachineBasicBlock *&FBB,
61 SmallVectorImpl<MachineOperand> &Cond,
62 bool AllowModify) const override;
63 unsigned removeBranch(MachineBasicBlock &MBB,
64 int *BytesRemoved = nullptr) const override;
65 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
66 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
67 const DebugLoc &DL,
68 int *BytesAdded = nullptr) const override;
69};
70
71} // namespace llvm
72
73#endif
74