1//===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISC-V specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVSubtarget.h"
14#include "GISel/RISCVCallLowering.h"
15#include "GISel/RISCVLegalizerInfo.h"
16#include "RISCV.h"
17#include "RISCVFrameLowering.h"
18#include "RISCVSelectionDAGInfo.h"
19#include "RISCVTargetMachine.h"
20#include "llvm/MC/TargetRegistry.h"
21#include "llvm/Support/ErrorHandling.h"
22
23using namespace llvm;
24
25#define DEBUG_TYPE "riscv-subtarget"
26
27#define GET_SUBTARGETINFO_TARGET_DESC
28#define GET_SUBTARGETINFO_CTOR
29#include "RISCVGenSubtargetInfo.inc"
30
31#define GET_RISCV_MACRO_FUSION_PRED_IMPL
32#include "RISCVGenMacroFusion.inc"
33
34namespace llvm::RISCVTuneInfoTable {
35
36#define GET_RISCVTuneInfoTable_IMPL
37#include "RISCVGenSearchableTables.inc"
38} // namespace llvm::RISCVTuneInfoTable
39
40static cl::opt<unsigned> RVVVectorLMULMax(
41 "riscv-v-fixed-length-vector-lmul-max",
42 cl::desc("The maximum LMUL value to use for fixed length vectors. "
43 "Fractional LMUL values are not supported."),
44 cl::init(Val: 8), cl::Hidden);
45
46static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
47 "riscv-disable-using-constant-pool-for-large-ints",
48 cl::desc("Disable using constant pool for large integers."),
49 cl::init(Val: false), cl::Hidden);
50
51static cl::opt<unsigned> RISCVMaxBuildIntsCost(
52 "riscv-max-build-ints-cost",
53 cl::desc("The maximum cost used for building integers."), cl::init(Val: 0),
54 cl::Hidden);
55
56static cl::opt<bool> UseAA("riscv-use-aa", cl::init(Val: true),
57 cl::desc("Enable the use of AA during codegen."));
58
59static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
60 "riscv-min-jump-table-entries", cl::Hidden,
61 cl::desc("Set minimum number of entries to use a jump table on RISCV"));
62
63static cl::opt<bool> UseMIPSLoadStorePairsOpt(
64 "use-riscv-mips-load-store-pairs",
65 cl::desc("Enable the load/store pair optimization pass"), cl::init(Val: false),
66 cl::Hidden);
67
68static cl::opt<bool> UseCCMovInsn("use-riscv-ccmov",
69 cl::desc("Use 'mips.ccmov' instruction"),
70 cl::init(Val: true), cl::Hidden);
71
72void RISCVSubtarget::anchor() {}
73
74RISCVSubtarget &
75RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
76 StringRef TuneCPU, StringRef FS,
77 StringRef ABIName) {
78 // Determine default and user-specified characteristics
79 bool Is64Bit = TT.isArch64Bit();
80 if (CPU.empty() || CPU == "generic")
81 CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
82
83 if (TuneCPU.empty())
84 TuneCPU = CPU;
85
86 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(Name: TuneCPU);
87 // If there is no TuneInfo for this CPU, we fail back to generic.
88 if (!TuneInfo)
89 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(Name: "generic");
90 assert(TuneInfo && "TuneInfo shouldn't be nullptr!");
91
92 ParseSubtargetFeatures(CPU, TuneCPU, FS);
93 TargetABI = RISCVABI::computeTargetABI(TT, FeatureBits: getFeatureBits(), ABIName);
94 RISCVFeatures::validate(TT, FeatureBits: getFeatureBits());
95 return *this;
96}
97
98RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
99 StringRef TuneCPU, StringRef FS,
100 StringRef ABIName, unsigned RVVVectorBitsMin,
101 unsigned RVVVectorBitsMax,
102 const TargetMachine &TM)
103 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
104 RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
105 FrameLowering(
106 initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
107 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
108 TSInfo = std::make_unique<RISCVSelectionDAGInfo>();
109}
110
111RISCVSubtarget::~RISCVSubtarget() = default;
112
113const SelectionDAGTargetInfo *RISCVSubtarget::getSelectionDAGInfo() const {
114 return TSInfo.get();
115}
116
117const CallLowering *RISCVSubtarget::getCallLowering() const {
118 if (!CallLoweringInfo)
119 CallLoweringInfo.reset(p: new RISCVCallLowering(*getTargetLowering()));
120 return CallLoweringInfo.get();
121}
122
123InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
124 if (!InstSelector) {
125 InstSelector.reset(p: createRISCVInstructionSelector(
126 *static_cast<const RISCVTargetMachine *>(&TLInfo.getTargetMachine()),
127 *this, *getRegBankInfo()));
128 }
129 return InstSelector.get();
130}
131
132const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
133 if (!Legalizer)
134 Legalizer.reset(p: new RISCVLegalizerInfo(*this));
135 return Legalizer.get();
136}
137
138const RISCVRegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
139 if (!RegBankInfo)
140 RegBankInfo.reset(p: new RISCVRegisterBankInfo(getHwMode()));
141 return RegBankInfo.get();
142}
143
144bool RISCVSubtarget::useConstantPoolForLargeInts() const {
145 return !RISCVDisableUsingConstantPoolForLargeInts;
146}
147
148unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
149 // Loading integer from constant pool needs two instructions (the reason why
150 // the minimum cost is 2): an address calculation instruction and a load
151 // instruction. Usually, address calculation and instructions used for
152 // building integers (addi, slli, etc.) can be done in one cycle, so here we
153 // set the default cost to (LoadLatency + 1) if no threshold is provided.
154 return RISCVMaxBuildIntsCost == 0
155 ? getSchedModel().LoadLatency + 1
156 : std::max<unsigned>(a: 2, b: RISCVMaxBuildIntsCost);
157}
158
159unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
160 assert(hasVInstructions() &&
161 "Tried to get vector length without Zve or V extension support!");
162
163 // ZvlLen specifies the minimum required vlen. The upper bound provided by
164 // riscv-v-vector-bits-max should be no less than it.
165 if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
166 report_fatal_error(reason: "riscv-v-vector-bits-max specified is lower "
167 "than the Zvl*b limitation");
168
169 return RVVVectorBitsMax;
170}
171
172unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
173 assert(hasVInstructions() &&
174 "Tried to get vector length without Zve or V extension support!");
175
176 if (RVVVectorBitsMin == -1U)
177 return ZvlLen;
178
179 // ZvlLen specifies the minimum required vlen. The lower bound provided by
180 // riscv-v-vector-bits-min should be no less than it.
181 if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
182 report_fatal_error(reason: "riscv-v-vector-bits-min specified is lower "
183 "than the Zvl*b limitation");
184
185 return RVVVectorBitsMin;
186}
187
188unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
189 assert(hasVInstructions() &&
190 "Tried to get vector length without Zve or V extension support!");
191 assert(RVVVectorLMULMax <= 8 &&
192 llvm::has_single_bit<uint32_t>(RVVVectorLMULMax) &&
193 "V extension requires a LMUL to be at most 8 and a power of 2!");
194 return llvm::bit_floor(Value: std::clamp<unsigned>(val: RVVVectorLMULMax, lo: 1, hi: 8));
195}
196
197bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
198 return hasVInstructions() &&
199 getMinRVVVectorSizeInBits() >= RISCV::RVVBitsPerBlock;
200}
201
202bool RISCVSubtarget::enableSubRegLiveness() const { return true; }
203
204bool RISCVSubtarget::enableMachinePipeliner() const {
205 return getSchedModel().hasInstrSchedModel();
206}
207
208 /// Enable use of alias analysis during code generation (during MI
209 /// scheduling, DAGCombine, etc.).
210bool RISCVSubtarget::useAA() const { return UseAA; }
211
212unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
213 return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
214 ? RISCVMinimumJumpTableEntries
215 : TuneInfo->MinimumJumpTableEntries;
216}
217
218void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
219 unsigned NumRegionInstrs) const {
220 // Do bidirectional scheduling since it provides a more balanced scheduling
221 // leading to better performance. This will increase compile time.
222 Policy.OnlyTopDown = false;
223 Policy.OnlyBottomUp = false;
224
225 // Disabling the latency heuristic can reduce the number of spills/reloads but
226 // will cause some regressions on some cores.
227 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
228
229 // Spilling is generally expensive on all RISC-V cores, so always enable
230 // register-pressure tracking. This will increase compile time.
231 Policy.ShouldTrackPressure = true;
232}
233
234void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
235 unsigned NumRegionInstrs) const {
236 MISched::Direction PostRASchedDirection = getPostRASchedDirection();
237 if (PostRASchedDirection == MISched::TopDown) {
238 Policy.OnlyTopDown = true;
239 Policy.OnlyBottomUp = false;
240 } else if (PostRASchedDirection == MISched::BottomUp) {
241 Policy.OnlyTopDown = false;
242 Policy.OnlyBottomUp = true;
243 } else if (PostRASchedDirection == MISched::Bidirectional) {
244 Policy.OnlyTopDown = false;
245 Policy.OnlyBottomUp = false;
246 }
247}
248
249bool RISCVSubtarget::useLoadStorePairs() const {
250 return UseMIPSLoadStorePairsOpt && HasVendorXMIPSLSP;
251}
252
253bool RISCVSubtarget::useCCMovInsn() const {
254 return UseCCMovInsn && HasVendorXMIPSCMov;
255}
256