1//===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Sparc implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
14#define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
15
16#include "SparcRegisterInfo.h"
17#include "llvm/CodeGen/TargetInstrInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "SparcGenInstrInfo.inc"
21
22namespace llvm {
23
24class SparcSubtarget;
25
26/// SPII - This namespace holds all of the target specific flags that
27/// instruction info tracks.
28///
29namespace SPII {
30 enum {
31 Pseudo = (1<<0),
32 Load = (1<<1),
33 Store = (1<<2),
34 DelaySlot = (1<<3)
35 };
36}
37
38class SparcInstrInfo : public SparcGenInstrInfo {
39 const SparcRegisterInfo RI;
40 const SparcSubtarget& Subtarget;
41 virtual void anchor();
42public:
43 explicit SparcInstrInfo(SparcSubtarget &ST);
44
45 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
46 /// such, whenever a client has an instance of instruction info, it should
47 /// always be able to get register info as well (through this method).
48 ///
49 const SparcRegisterInfo &getRegisterInfo() const { return RI; }
50
51 /// isLoadFromStackSlot - If the specified machine instruction is a direct
52 /// load from a stack slot, return the virtual or physical register number of
53 /// the destination along with the FrameIndex of the loaded stack slot. If
54 /// not, return 0. This predicate must return 0 if the instruction has
55 /// any side effects other than loading from the stack slot.
56 Register isLoadFromStackSlot(const MachineInstr &MI,
57 int &FrameIndex) const override;
58
59 /// isStoreToStackSlot - If the specified machine instruction is a direct
60 /// store to a stack slot, return the virtual or physical register number of
61 /// the source reg along with the FrameIndex of the loaded stack slot. If
62 /// not, return 0. This predicate must return 0 if the instruction has
63 /// any side effects other than storing to the stack slot.
64 Register isStoreToStackSlot(const MachineInstr &MI,
65 int &FrameIndex) const override;
66
67 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
68
69 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
70 MachineBasicBlock *&FBB,
71 SmallVectorImpl<MachineOperand> &Cond,
72 bool AllowModify = false) const override;
73
74 unsigned removeBranch(MachineBasicBlock &MBB,
75 int *BytesRemoved = nullptr) const override;
76
77 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
78 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
79 const DebugLoc &DL,
80 int *BytesAdded = nullptr) const override;
81
82 bool
83 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
84
85 /// Determine if the branch target is in range.
86 bool isBranchOffsetInRange(unsigned BranchOpc, int64_t Offset) const override;
87
88 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
89 const DebugLoc &DL, Register DestReg, Register SrcReg,
90 bool KillSrc, bool RenamableDest = false,
91 bool RenamableSrc = false) const override;
92
93 void storeRegToStackSlot(
94 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
95 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
96 const TargetRegisterInfo *TRI, Register VReg,
97 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
98
99 void loadRegFromStackSlot(
100 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
101 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
102 const TargetRegisterInfo *TRI, Register VReg,
103 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
104
105 Register getGlobalBaseReg(MachineFunction *MF) const;
106
107 /// GetInstSize - Return the number of bytes of code the specified
108 /// instruction may be. This returns the maximum number of bytes.
109 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
110
111 // Lower pseudo instructions after register allocation.
112 bool expandPostRAPseudo(MachineInstr &MI) const override;
113};
114
115}
116
117#endif
118