1//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "SparcTargetMachine.h"
13#include "LeonPasses.h"
14#include "Sparc.h"
15#include "SparcMachineFunctionInfo.h"
16#include "SparcTargetObjectFile.h"
17#include "TargetInfo/SparcTargetInfo.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/CodeGen/TargetPassConfig.h"
20#include "llvm/MC/TargetRegistry.h"
21#include "llvm/Support/Compiler.h"
22#include <optional>
23using namespace llvm;
24
25extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() {
26 // Register the target.
27 RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
28 RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
29 RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
30
31 PassRegistry &PR = *PassRegistry::getPassRegistry();
32 initializeSparcAsmPrinterPass(PR);
33 initializeSparcDAGToDAGISelLegacyPass(PR);
34 initializeErrataWorkaroundPass(PR);
35}
36
37static cl::opt<bool>
38 BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(Val: true),
39 cl::desc("Relax out of range conditional branches"));
40
41static std::string computeDataLayout(const Triple &T, bool is64Bit) {
42 // Sparc is typically big endian, but some are little.
43 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
44 Ret += "-m:e";
45
46 // Some ABIs have 32bit pointers.
47 if (!is64Bit)
48 Ret += "-p:32:32";
49
50 // Alignments for 64 bit integers.
51 Ret += "-i64:64";
52
53 // Alignments for 128 bit integers.
54 // This is not specified in the ABI document but is the de facto standard.
55 Ret += "-i128:128";
56
57 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
58 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
59 if (is64Bit)
60 Ret += "-n32:64";
61 else
62 Ret += "-f128:64-n32";
63
64 if (is64Bit)
65 Ret += "-S128";
66 else
67 Ret += "-S64";
68
69 return Ret;
70}
71
72static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
73 return RM.value_or(u: Reloc::Static);
74}
75
76// Code models. Some only make sense for 64-bit code.
77//
78// SunCC Reloc CodeModel Constraints
79// abs32 Static Small text+data+bss linked below 2^32 bytes
80// abs44 Static Medium text+data+bss linked below 2^44 bytes
81// abs64 Static Large text smaller than 2^31 bytes
82// pic13 PIC_ Small GOT < 2^13 bytes
83// pic32 PIC_ Medium GOT < 2^32 bytes
84//
85// All code models require that the text segment is smaller than 2GB.
86static CodeModel::Model
87getEffectiveSparcCodeModel(std::optional<CodeModel::Model> CM, Reloc::Model RM,
88 bool Is64Bit, bool JIT) {
89 if (CM) {
90 if (*CM == CodeModel::Tiny)
91 report_fatal_error(reason: "Target does not support the tiny CodeModel", gen_crash_diag: false);
92 if (*CM == CodeModel::Kernel)
93 report_fatal_error(reason: "Target does not support the kernel CodeModel", gen_crash_diag: false);
94 return *CM;
95 }
96 if (Is64Bit) {
97 if (JIT)
98 return CodeModel::Large;
99 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
100 }
101 return CodeModel::Small;
102}
103
104/// Create an ILP32 architecture model
105SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
106 StringRef CPU, StringRef FS,
107 const TargetOptions &Options,
108 std::optional<Reloc::Model> RM,
109 std::optional<CodeModel::Model> CM,
110 CodeGenOptLevel OL, bool JIT,
111 bool is64bit)
112 : CodeGenTargetMachineImpl(
113 T, computeDataLayout(T: TT, is64Bit: is64bit), TT, CPU, FS, Options,
114 getEffectiveRelocModel(RM),
115 getEffectiveSparcCodeModel(CM, RM: getEffectiveRelocModel(RM), Is64Bit: is64bit,
116 JIT),
117 OL),
118 TLOF(std::make_unique<SparcELFTargetObjectFile>()), is64Bit(is64bit) {
119 initAsmInfo();
120}
121
122SparcTargetMachine::~SparcTargetMachine() = default;
123
124const SparcSubtarget *
125SparcTargetMachine::getSubtargetImpl(const Function &F) const {
126 Attribute CPUAttr = F.getFnAttribute(Kind: "target-cpu");
127 Attribute TuneAttr = F.getFnAttribute(Kind: "tune-cpu");
128 Attribute FSAttr = F.getFnAttribute(Kind: "target-features");
129
130 std::string CPU =
131 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
132 std::string TuneCPU =
133 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
134 std::string FS =
135 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
136
137 // FIXME: This is related to the code below to reset the target options,
138 // we need to know whether or not the soft float flag is set on the
139 // function, so we can enable it as a subtarget feature.
140 bool softFloat = F.getFnAttribute(Kind: "use-soft-float").getValueAsBool();
141
142 if (softFloat)
143 FS += FS.empty() ? "+soft-float" : ",+soft-float";
144
145 auto &I = SubtargetMap[CPU + FS];
146 if (!I) {
147 // This needs to be done before we create a new subtarget since any
148 // creation will depend on the TM and the code generation flags on the
149 // function that reside in TargetOptions.
150 resetTargetOptions(F);
151 I = std::make_unique<SparcSubtarget>(args&: CPU, args&: TuneCPU, args&: FS, args: *this,
152 args: this->is64Bit);
153 }
154 return I.get();
155}
156
157MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
158 BumpPtrAllocator &Allocator, const Function &F,
159 const TargetSubtargetInfo *STI) const {
160 return SparcMachineFunctionInfo::create<SparcMachineFunctionInfo>(Allocator,
161 F, STI);
162}
163
164namespace {
165/// Sparc Code Generator Pass Configuration Options.
166class SparcPassConfig : public TargetPassConfig {
167public:
168 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
169 : TargetPassConfig(TM, PM) {}
170
171 SparcTargetMachine &getSparcTargetMachine() const {
172 return getTM<SparcTargetMachine>();
173 }
174
175 void addIRPasses() override;
176 bool addInstSelector() override;
177 void addPreEmitPass() override;
178};
179} // namespace
180
181TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
182 return new SparcPassConfig(*this, PM);
183}
184
185void SparcPassConfig::addIRPasses() {
186 addPass(P: createAtomicExpandLegacyPass());
187
188 TargetPassConfig::addIRPasses();
189}
190
191bool SparcPassConfig::addInstSelector() {
192 addPass(P: createSparcISelDag(TM&: getSparcTargetMachine()));
193 return false;
194}
195
196void SparcPassConfig::addPreEmitPass(){
197 if (BranchRelaxation)
198 addPass(PassID: &BranchRelaxationPassID);
199
200 addPass(P: createSparcDelaySlotFillerPass());
201 addPass(P: new InsertNOPLoad());
202 addPass(P: new DetectRoundChange());
203 addPass(P: new FixAllFDIVSQRT());
204 addPass(P: new ErrataWorkaround());
205}
206
207void SparcV8TargetMachine::anchor() { }
208
209SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
210 StringRef CPU, StringRef FS,
211 const TargetOptions &Options,
212 std::optional<Reloc::Model> RM,
213 std::optional<CodeModel::Model> CM,
214 CodeGenOptLevel OL, bool JIT)
215 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
216
217void SparcV9TargetMachine::anchor() { }
218
219SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
220 StringRef CPU, StringRef FS,
221 const TargetOptions &Options,
222 std::optional<Reloc::Model> RM,
223 std::optional<CodeModel::Model> CM,
224 CodeGenOptLevel OL, bool JIT)
225 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
226
227void SparcelTargetMachine::anchor() {}
228
229SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
230 StringRef CPU, StringRef FS,
231 const TargetOptions &Options,
232 std::optional<Reloc::Model> RM,
233 std::optional<CodeModel::Model> CM,
234 CodeGenOptLevel OL, bool JIT)
235 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
236