1//===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Streams SystemZ assembly language and associated data, in the form of
10// MCInsts and MCExprs respectively.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZAsmPrinter.h"
15#include "MCTargetDesc/SystemZGNUInstPrinter.h"
16#include "MCTargetDesc/SystemZHLASMInstPrinter.h"
17#include "MCTargetDesc/SystemZMCAsmInfo.h"
18#include "MCTargetDesc/SystemZMCTargetDesc.h"
19#include "SystemZConstantPoolValue.h"
20#include "SystemZMCInstLower.h"
21#include "TargetInfo/SystemZTargetInfo.h"
22#include "llvm/ADT/StringExtras.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/BinaryFormat/GOFF.h"
25#include "llvm/CodeGen/MachineModuleInfoImpls.h"
26#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27#include "llvm/IR/Mangler.h"
28#include "llvm/IR/Module.h"
29#include "llvm/MC/MCExpr.h"
30#include "llvm/MC/MCInstBuilder.h"
31#include "llvm/MC/MCSectionELF.h"
32#include "llvm/MC/MCStreamer.h"
33#include "llvm/MC/TargetRegistry.h"
34#include "llvm/Support/Chrono.h"
35#include "llvm/Support/Compiler.h"
36#include "llvm/Support/ConvertEBCDIC.h"
37#include "llvm/Support/FormatVariadic.h"
38
39using namespace llvm;
40
41// Return an RI instruction like MI with opcode Opcode, but with the
42// GR64 register operands turned into GR32s.
43static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
44 if (MI->isCompare())
45 return MCInstBuilder(Opcode)
46 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 0).getReg()))
47 .addImm(Val: MI->getOperand(i: 1).getImm());
48 else
49 return MCInstBuilder(Opcode)
50 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 0).getReg()))
51 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 1).getReg()))
52 .addImm(Val: MI->getOperand(i: 2).getImm());
53}
54
55// Return an RI instruction like MI with opcode Opcode, but with the
56// GR64 register operands turned into GRH32s.
57static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
58 if (MI->isCompare())
59 return MCInstBuilder(Opcode)
60 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 0).getReg()))
61 .addImm(Val: MI->getOperand(i: 1).getImm());
62 else
63 return MCInstBuilder(Opcode)
64 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 0).getReg()))
65 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 1).getReg()))
66 .addImm(Val: MI->getOperand(i: 2).getImm());
67}
68
69// Return an RI instruction like MI with opcode Opcode, but with the
70// R2 register turned into a GR64.
71static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
72 return MCInstBuilder(Opcode)
73 .addReg(Reg: MI->getOperand(i: 0).getReg())
74 .addReg(Reg: MI->getOperand(i: 1).getReg())
75 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 2).getReg()))
76 .addImm(Val: MI->getOperand(i: 3).getImm())
77 .addImm(Val: MI->getOperand(i: 4).getImm())
78 .addImm(Val: MI->getOperand(i: 5).getImm());
79}
80
81static const MCSymbolRefExpr *getTLSGetOffset(MCContext &Context) {
82 StringRef Name = "__tls_get_offset";
83 return MCSymbolRefExpr::create(Symbol: Context.getOrCreateSymbol(Name),
84 specifier: SystemZ::S_PLT, Ctx&: Context);
85}
86
87static const MCSymbolRefExpr *getGlobalOffsetTable(MCContext &Context) {
88 StringRef Name = "_GLOBAL_OFFSET_TABLE_";
89 return MCSymbolRefExpr::create(Symbol: Context.getOrCreateSymbol(Name),
90 Ctx&: Context);
91}
92
93// MI is an instruction that accepts an optional alignment hint,
94// and which was already lowered to LoweredMI. If the alignment
95// of the original memory operand is known, update LoweredMI to
96// an instruction with the corresponding hint set.
97static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI,
98 unsigned Opcode) {
99 if (MI->memoperands_empty())
100 return;
101
102 Align Alignment = Align(16);
103 for (MachineInstr::mmo_iterator MMOI = MI->memoperands_begin(),
104 EE = MI->memoperands_end(); MMOI != EE; ++MMOI)
105 if ((*MMOI)->getAlign() < Alignment)
106 Alignment = (*MMOI)->getAlign();
107
108 unsigned AlignmentHint = 0;
109 if (Alignment >= Align(16))
110 AlignmentHint = 4;
111 else if (Alignment >= Align(8))
112 AlignmentHint = 3;
113 if (AlignmentHint == 0)
114 return;
115
116 LoweredMI.setOpcode(Opcode);
117 LoweredMI.addOperand(Op: MCOperand::createImm(Val: AlignmentHint));
118}
119
120// MI loads the high part of a vector from memory. Return an instruction
121// that uses replicating vector load Opcode to do the same thing.
122static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
123 return MCInstBuilder(Opcode)
124 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
125 .addReg(Reg: MI->getOperand(i: 1).getReg())
126 .addImm(Val: MI->getOperand(i: 2).getImm())
127 .addReg(Reg: MI->getOperand(i: 3).getReg());
128}
129
130// MI stores the high part of a vector to memory. Return an instruction
131// that uses elemental vector store Opcode to do the same thing.
132static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
133 return MCInstBuilder(Opcode)
134 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
135 .addReg(Reg: MI->getOperand(i: 1).getReg())
136 .addImm(Val: MI->getOperand(i: 2).getImm())
137 .addReg(Reg: MI->getOperand(i: 3).getReg())
138 .addImm(Val: 0);
139}
140
141// MI extracts the first element of the source vector.
142static MCInst lowerVecEltExtraction(const MachineInstr *MI, unsigned Opcode) {
143 return MCInstBuilder(Opcode)
144 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 0).getReg()))
145 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 1).getReg()))
146 .addReg(Reg: 0)
147 .addImm(Val: 0);
148}
149
150// MI inserts value into the first element of the destination vector.
151static MCInst lowerVecEltInsertion(const MachineInstr *MI, unsigned Opcode) {
152 return MCInstBuilder(Opcode)
153 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
154 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
155 .addReg(Reg: MI->getOperand(i: 1).getReg())
156 .addReg(Reg: 0)
157 .addImm(Val: 0);
158}
159
160// The XPLINK ABI requires that a no-op encoding the call type is emitted after
161// each call to a subroutine. This information can be used by the called
162// function to determine its entry point, e.g. for generating a backtrace. The
163// call type is encoded as a register number in the bcr instruction. See
164// enumeration CallType for the possible values.
165void SystemZAsmPrinter::emitCallInformation(CallType CT) {
166 EmitToStreamer(S&: *OutStreamer,
167 Inst: MCInstBuilder(SystemZ::BCRAsm)
168 .addImm(Val: 0)
169 .addReg(Reg: SystemZMC::GR64Regs[static_cast<unsigned>(CT)]));
170}
171
172uint32_t SystemZAsmPrinter::AssociatedDataAreaTable::insert(const MCSymbol *Sym,
173 unsigned SlotKind) {
174 auto Key = std::make_pair(x&: Sym, y&: SlotKind);
175 auto It = Displacements.find(Key);
176
177 if (It != Displacements.end())
178 return (*It).second;
179
180 // Determine length of descriptor.
181 uint32_t Length;
182 switch (SlotKind) {
183 case SystemZII::MO_ADA_DIRECT_FUNC_DESC:
184 Length = 2 * PointerSize;
185 break;
186 default:
187 Length = PointerSize;
188 break;
189 }
190
191 uint32_t Displacement = NextDisplacement;
192 Displacements[std::make_pair(x&: Sym, y&: SlotKind)] = NextDisplacement;
193 NextDisplacement += Length;
194
195 return Displacement;
196}
197
198uint32_t
199SystemZAsmPrinter::AssociatedDataAreaTable::insert(const MachineOperand MO) {
200 MCSymbol *Sym;
201 if (MO.getType() == MachineOperand::MO_GlobalAddress) {
202 const GlobalValue *GV = MO.getGlobal();
203 Sym = MO.getParent()->getMF()->getTarget().getSymbol(GV);
204 assert(Sym && "No symbol");
205 } else if (MO.getType() == MachineOperand::MO_ExternalSymbol) {
206 const char *SymName = MO.getSymbolName();
207 Sym = MO.getParent()->getMF()->getContext().getOrCreateSymbol(Name: SymName);
208 assert(Sym && "No symbol");
209 } else
210 llvm_unreachable("Unexpected operand type");
211
212 unsigned ADAslotType = MO.getTargetFlags();
213 return insert(Sym, SlotKind: ADAslotType);
214}
215
216void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
217 SystemZ_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(),
218 Features: getSubtargetInfo().getFeatureBits());
219
220 SystemZMCInstLower Lower(MF->getContext(), *this);
221 MCInst LoweredMI;
222 switch (MI->getOpcode()) {
223 case SystemZ::Return:
224 LoweredMI = MCInstBuilder(SystemZ::BR)
225 .addReg(Reg: SystemZ::R14D);
226 break;
227
228 case SystemZ::Return_XPLINK:
229 LoweredMI = MCInstBuilder(SystemZ::B)
230 .addReg(Reg: SystemZ::R7D)
231 .addImm(Val: 2)
232 .addReg(Reg: 0);
233 break;
234
235 case SystemZ::CondReturn:
236 LoweredMI = MCInstBuilder(SystemZ::BCR)
237 .addImm(Val: MI->getOperand(i: 0).getImm())
238 .addImm(Val: MI->getOperand(i: 1).getImm())
239 .addReg(Reg: SystemZ::R14D);
240 break;
241
242 case SystemZ::CondReturn_XPLINK:
243 LoweredMI = MCInstBuilder(SystemZ::BC)
244 .addImm(Val: MI->getOperand(i: 0).getImm())
245 .addImm(Val: MI->getOperand(i: 1).getImm())
246 .addReg(Reg: SystemZ::R7D)
247 .addImm(Val: 2)
248 .addReg(Reg: 0);
249 break;
250
251 case SystemZ::CRBReturn:
252 LoweredMI = MCInstBuilder(SystemZ::CRB)
253 .addReg(Reg: MI->getOperand(i: 0).getReg())
254 .addReg(Reg: MI->getOperand(i: 1).getReg())
255 .addImm(Val: MI->getOperand(i: 2).getImm())
256 .addReg(Reg: SystemZ::R14D)
257 .addImm(Val: 0);
258 break;
259
260 case SystemZ::CGRBReturn:
261 LoweredMI = MCInstBuilder(SystemZ::CGRB)
262 .addReg(Reg: MI->getOperand(i: 0).getReg())
263 .addReg(Reg: MI->getOperand(i: 1).getReg())
264 .addImm(Val: MI->getOperand(i: 2).getImm())
265 .addReg(Reg: SystemZ::R14D)
266 .addImm(Val: 0);
267 break;
268
269 case SystemZ::CIBReturn:
270 LoweredMI = MCInstBuilder(SystemZ::CIB)
271 .addReg(Reg: MI->getOperand(i: 0).getReg())
272 .addImm(Val: MI->getOperand(i: 1).getImm())
273 .addImm(Val: MI->getOperand(i: 2).getImm())
274 .addReg(Reg: SystemZ::R14D)
275 .addImm(Val: 0);
276 break;
277
278 case SystemZ::CGIBReturn:
279 LoweredMI = MCInstBuilder(SystemZ::CGIB)
280 .addReg(Reg: MI->getOperand(i: 0).getReg())
281 .addImm(Val: MI->getOperand(i: 1).getImm())
282 .addImm(Val: MI->getOperand(i: 2).getImm())
283 .addReg(Reg: SystemZ::R14D)
284 .addImm(Val: 0);
285 break;
286
287 case SystemZ::CLRBReturn:
288 LoweredMI = MCInstBuilder(SystemZ::CLRB)
289 .addReg(Reg: MI->getOperand(i: 0).getReg())
290 .addReg(Reg: MI->getOperand(i: 1).getReg())
291 .addImm(Val: MI->getOperand(i: 2).getImm())
292 .addReg(Reg: SystemZ::R14D)
293 .addImm(Val: 0);
294 break;
295
296 case SystemZ::CLGRBReturn:
297 LoweredMI = MCInstBuilder(SystemZ::CLGRB)
298 .addReg(Reg: MI->getOperand(i: 0).getReg())
299 .addReg(Reg: MI->getOperand(i: 1).getReg())
300 .addImm(Val: MI->getOperand(i: 2).getImm())
301 .addReg(Reg: SystemZ::R14D)
302 .addImm(Val: 0);
303 break;
304
305 case SystemZ::CLIBReturn:
306 LoweredMI = MCInstBuilder(SystemZ::CLIB)
307 .addReg(Reg: MI->getOperand(i: 0).getReg())
308 .addImm(Val: MI->getOperand(i: 1).getImm())
309 .addImm(Val: MI->getOperand(i: 2).getImm())
310 .addReg(Reg: SystemZ::R14D)
311 .addImm(Val: 0);
312 break;
313
314 case SystemZ::CLGIBReturn:
315 LoweredMI = MCInstBuilder(SystemZ::CLGIB)
316 .addReg(Reg: MI->getOperand(i: 0).getReg())
317 .addImm(Val: MI->getOperand(i: 1).getImm())
318 .addImm(Val: MI->getOperand(i: 2).getImm())
319 .addReg(Reg: SystemZ::R14D)
320 .addImm(Val: 0);
321 break;
322
323 case SystemZ::CallBRASL_XPLINK64:
324 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRASL)
325 .addReg(Reg: SystemZ::R7D)
326 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0),
327 SystemZ::S_PLT)));
328 emitCallInformation(CT: CallType::BRASL7);
329 return;
330
331 case SystemZ::CallBASR_XPLINK64:
332 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BASR)
333 .addReg(Reg: SystemZ::R7D)
334 .addReg(Reg: MI->getOperand(i: 0).getReg()));
335 emitCallInformation(CT: CallType::BASR76);
336 return;
337
338 case SystemZ::CallBASR_STACKEXT:
339 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BASR)
340 .addReg(Reg: SystemZ::R3D)
341 .addReg(Reg: MI->getOperand(i: 0).getReg()));
342 emitCallInformation(CT: CallType::BASR33);
343 return;
344
345 case SystemZ::ADA_ENTRY_VALUE:
346 case SystemZ::ADA_ENTRY: {
347 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
348 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
349 uint32_t Disp = ADATable.insert(MO: MI->getOperand(i: 1));
350 Register TargetReg = MI->getOperand(i: 0).getReg();
351
352 Register ADAReg = MI->getOperand(i: 2).getReg();
353 Disp += MI->getOperand(i: 3).getImm();
354 bool LoadAddr = MI->getOpcode() == SystemZ::ADA_ENTRY;
355
356 unsigned Op0 = LoadAddr ? SystemZ::LA : SystemZ::LG;
357 unsigned Op = TII->getOpcodeForOffset(Opcode: Op0, Offset: Disp);
358
359 Register IndexReg = 0;
360 if (!Op) {
361 if (TargetReg != ADAReg) {
362 IndexReg = TargetReg;
363 // Use TargetReg to store displacement.
364 EmitToStreamer(
365 S&: *OutStreamer,
366 Inst: MCInstBuilder(SystemZ::LLILF).addReg(Reg: TargetReg).addImm(Val: Disp));
367 } else
368 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::ALGFI)
369 .addReg(Reg: TargetReg)
370 .addReg(Reg: TargetReg)
371 .addImm(Val: Disp));
372 Disp = 0;
373 Op = Op0;
374 }
375 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Op)
376 .addReg(Reg: TargetReg)
377 .addReg(Reg: ADAReg)
378 .addImm(Val: Disp)
379 .addReg(Reg: IndexReg));
380
381 return;
382 }
383 case SystemZ::CallBRASL:
384 LoweredMI = MCInstBuilder(SystemZ::BRASL)
385 .addReg(Reg: SystemZ::R14D)
386 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_PLT));
387 break;
388
389 case SystemZ::CallBASR:
390 LoweredMI = MCInstBuilder(SystemZ::BASR)
391 .addReg(Reg: SystemZ::R14D)
392 .addReg(Reg: MI->getOperand(i: 0).getReg());
393 break;
394
395 case SystemZ::CallJG:
396 LoweredMI = MCInstBuilder(SystemZ::JG)
397 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_PLT));
398 break;
399
400 case SystemZ::CallBRCL:
401 LoweredMI = MCInstBuilder(SystemZ::BRCL)
402 .addImm(Val: MI->getOperand(i: 0).getImm())
403 .addImm(Val: MI->getOperand(i: 1).getImm())
404 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 2), SystemZ::S_PLT));
405 break;
406
407 case SystemZ::CallBR:
408 LoweredMI = MCInstBuilder(SystemZ::BR)
409 .addReg(Reg: MI->getOperand(i: 0).getReg());
410 break;
411
412 case SystemZ::CallBCR:
413 LoweredMI = MCInstBuilder(SystemZ::BCR)
414 .addImm(Val: MI->getOperand(i: 0).getImm())
415 .addImm(Val: MI->getOperand(i: 1).getImm())
416 .addReg(Reg: MI->getOperand(i: 2).getReg());
417 break;
418
419 case SystemZ::CRBCall:
420 LoweredMI = MCInstBuilder(SystemZ::CRB)
421 .addReg(Reg: MI->getOperand(i: 0).getReg())
422 .addReg(Reg: MI->getOperand(i: 1).getReg())
423 .addImm(Val: MI->getOperand(i: 2).getImm())
424 .addReg(Reg: MI->getOperand(i: 3).getReg())
425 .addImm(Val: 0);
426 break;
427
428 case SystemZ::CGRBCall:
429 LoweredMI = MCInstBuilder(SystemZ::CGRB)
430 .addReg(Reg: MI->getOperand(i: 0).getReg())
431 .addReg(Reg: MI->getOperand(i: 1).getReg())
432 .addImm(Val: MI->getOperand(i: 2).getImm())
433 .addReg(Reg: MI->getOperand(i: 3).getReg())
434 .addImm(Val: 0);
435 break;
436
437 case SystemZ::CIBCall:
438 LoweredMI = MCInstBuilder(SystemZ::CIB)
439 .addReg(Reg: MI->getOperand(i: 0).getReg())
440 .addImm(Val: MI->getOperand(i: 1).getImm())
441 .addImm(Val: MI->getOperand(i: 2).getImm())
442 .addReg(Reg: MI->getOperand(i: 3).getReg())
443 .addImm(Val: 0);
444 break;
445
446 case SystemZ::CGIBCall:
447 LoweredMI = MCInstBuilder(SystemZ::CGIB)
448 .addReg(Reg: MI->getOperand(i: 0).getReg())
449 .addImm(Val: MI->getOperand(i: 1).getImm())
450 .addImm(Val: MI->getOperand(i: 2).getImm())
451 .addReg(Reg: MI->getOperand(i: 3).getReg())
452 .addImm(Val: 0);
453 break;
454
455 case SystemZ::CLRBCall:
456 LoweredMI = MCInstBuilder(SystemZ::CLRB)
457 .addReg(Reg: MI->getOperand(i: 0).getReg())
458 .addReg(Reg: MI->getOperand(i: 1).getReg())
459 .addImm(Val: MI->getOperand(i: 2).getImm())
460 .addReg(Reg: MI->getOperand(i: 3).getReg())
461 .addImm(Val: 0);
462 break;
463
464 case SystemZ::CLGRBCall:
465 LoweredMI = MCInstBuilder(SystemZ::CLGRB)
466 .addReg(Reg: MI->getOperand(i: 0).getReg())
467 .addReg(Reg: MI->getOperand(i: 1).getReg())
468 .addImm(Val: MI->getOperand(i: 2).getImm())
469 .addReg(Reg: MI->getOperand(i: 3).getReg())
470 .addImm(Val: 0);
471 break;
472
473 case SystemZ::CLIBCall:
474 LoweredMI = MCInstBuilder(SystemZ::CLIB)
475 .addReg(Reg: MI->getOperand(i: 0).getReg())
476 .addImm(Val: MI->getOperand(i: 1).getImm())
477 .addImm(Val: MI->getOperand(i: 2).getImm())
478 .addReg(Reg: MI->getOperand(i: 3).getReg())
479 .addImm(Val: 0);
480 break;
481
482 case SystemZ::CLGIBCall:
483 LoweredMI = MCInstBuilder(SystemZ::CLGIB)
484 .addReg(Reg: MI->getOperand(i: 0).getReg())
485 .addImm(Val: MI->getOperand(i: 1).getImm())
486 .addImm(Val: MI->getOperand(i: 2).getImm())
487 .addReg(Reg: MI->getOperand(i: 3).getReg())
488 .addImm(Val: 0);
489 break;
490
491 case SystemZ::TLS_GDCALL:
492 LoweredMI =
493 MCInstBuilder(SystemZ::BRASL)
494 .addReg(Reg: SystemZ::R14D)
495 .addExpr(Val: getTLSGetOffset(Context&: MF->getContext()))
496 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_TLSGD));
497 break;
498
499 case SystemZ::TLS_LDCALL:
500 LoweredMI =
501 MCInstBuilder(SystemZ::BRASL)
502 .addReg(Reg: SystemZ::R14D)
503 .addExpr(Val: getTLSGetOffset(Context&: MF->getContext()))
504 .addExpr(Val: Lower.getExpr(MO: MI->getOperand(i: 0), SystemZ::S_TLSLDM));
505 break;
506
507 case SystemZ::GOT:
508 LoweredMI = MCInstBuilder(SystemZ::LARL)
509 .addReg(Reg: MI->getOperand(i: 0).getReg())
510 .addExpr(Val: getGlobalOffsetTable(Context&: MF->getContext()));
511 break;
512
513 case SystemZ::IILF64:
514 LoweredMI = MCInstBuilder(SystemZ::IILF)
515 .addReg(Reg: SystemZMC::getRegAsGR32(Reg: MI->getOperand(i: 0).getReg()))
516 .addImm(Val: MI->getOperand(i: 2).getImm());
517 break;
518
519 case SystemZ::IIHF64:
520 LoweredMI = MCInstBuilder(SystemZ::IIHF)
521 .addReg(Reg: SystemZMC::getRegAsGRH32(Reg: MI->getOperand(i: 0).getReg()))
522 .addImm(Val: MI->getOperand(i: 2).getImm());
523 break;
524
525 case SystemZ::RISBHH:
526 case SystemZ::RISBHL:
527 LoweredMI = lowerRIEfLow(MI, Opcode: SystemZ::RISBHG);
528 break;
529
530 case SystemZ::RISBLH:
531 case SystemZ::RISBLL:
532 LoweredMI = lowerRIEfLow(MI, Opcode: SystemZ::RISBLG);
533 break;
534
535 case SystemZ::VLVGP32:
536 LoweredMI = MCInstBuilder(SystemZ::VLVGP)
537 .addReg(Reg: MI->getOperand(i: 0).getReg())
538 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 1).getReg()))
539 .addReg(Reg: SystemZMC::getRegAsGR64(Reg: MI->getOperand(i: 2).getReg()));
540 break;
541
542 case SystemZ::VLR32:
543 case SystemZ::VLR64:
544 LoweredMI = MCInstBuilder(SystemZ::VLR)
545 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 0).getReg()))
546 .addReg(Reg: SystemZMC::getRegAsVR128(Reg: MI->getOperand(i: 1).getReg()));
547 break;
548
549 case SystemZ::VL:
550 Lower.lower(MI, OutMI&: LoweredMI);
551 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VLAlign);
552 break;
553
554 case SystemZ::VST:
555 Lower.lower(MI, OutMI&: LoweredMI);
556 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VSTAlign);
557 break;
558
559 case SystemZ::VLM:
560 Lower.lower(MI, OutMI&: LoweredMI);
561 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VLMAlign);
562 break;
563
564 case SystemZ::VSTM:
565 Lower.lower(MI, OutMI&: LoweredMI);
566 lowerAlignmentHint(MI, LoweredMI, Opcode: SystemZ::VSTMAlign);
567 break;
568
569 case SystemZ::VL16:
570 LoweredMI = lowerSubvectorLoad(MI, Opcode: SystemZ::VLREPH);
571 break;
572
573 case SystemZ::VL32:
574 LoweredMI = lowerSubvectorLoad(MI, Opcode: SystemZ::VLREPF);
575 break;
576
577 case SystemZ::VL64:
578 LoweredMI = lowerSubvectorLoad(MI, Opcode: SystemZ::VLREPG);
579 break;
580
581 case SystemZ::VST16:
582 LoweredMI = lowerSubvectorStore(MI, Opcode: SystemZ::VSTEH);
583 break;
584
585 case SystemZ::VST32:
586 LoweredMI = lowerSubvectorStore(MI, Opcode: SystemZ::VSTEF);
587 break;
588
589 case SystemZ::VST64:
590 LoweredMI = lowerSubvectorStore(MI, Opcode: SystemZ::VSTEG);
591 break;
592
593 case SystemZ::LFER:
594 LoweredMI = lowerVecEltExtraction(MI, Opcode: SystemZ::VLGVF);
595 break;
596
597 case SystemZ::LFER_16:
598 LoweredMI = lowerVecEltExtraction(MI, Opcode: SystemZ::VLGVH);
599 break;
600
601 case SystemZ::LEFR:
602 LoweredMI = lowerVecEltInsertion(MI, Opcode: SystemZ::VLVGF);
603 break;
604
605 case SystemZ::LEFR_16:
606 LoweredMI = lowerVecEltInsertion(MI, Opcode: SystemZ::VLVGH);
607 break;
608
609#define LOWER_LOW(NAME) \
610 case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
611
612 LOWER_LOW(IILL);
613 LOWER_LOW(IILH);
614 LOWER_LOW(TMLL);
615 LOWER_LOW(TMLH);
616 LOWER_LOW(NILL);
617 LOWER_LOW(NILH);
618 LOWER_LOW(NILF);
619 LOWER_LOW(OILL);
620 LOWER_LOW(OILH);
621 LOWER_LOW(OILF);
622 LOWER_LOW(XILF);
623
624#undef LOWER_LOW
625
626#define LOWER_HIGH(NAME) \
627 case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
628
629 LOWER_HIGH(IIHL);
630 LOWER_HIGH(IIHH);
631 LOWER_HIGH(TMHL);
632 LOWER_HIGH(TMHH);
633 LOWER_HIGH(NIHL);
634 LOWER_HIGH(NIHH);
635 LOWER_HIGH(NIHF);
636 LOWER_HIGH(OIHL);
637 LOWER_HIGH(OIHH);
638 LOWER_HIGH(OIHF);
639 LOWER_HIGH(XIHF);
640
641#undef LOWER_HIGH
642
643 case SystemZ::Serialize:
644 if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization())
645 LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
646 .addImm(Val: 14).addReg(Reg: SystemZ::R0D);
647 else
648 LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
649 .addImm(Val: 15).addReg(Reg: SystemZ::R0D);
650 break;
651
652 // We want to emit "j .+2" for traps, jumping to the relative immediate field
653 // of the jump instruction, which is an illegal instruction. We cannot emit a
654 // "." symbol, so create and emit a temp label before the instruction and use
655 // that instead.
656 case SystemZ::Trap: {
657 MCSymbol *DotSym = OutContext.createTempSymbol();
658 OutStreamer->emitLabel(Symbol: DotSym);
659
660 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
661 const MCConstantExpr *ConstExpr = MCConstantExpr::create(Value: 2, Ctx&: OutContext);
662 LoweredMI = MCInstBuilder(SystemZ::J)
663 .addExpr(Val: MCBinaryExpr::createAdd(LHS: Expr, RHS: ConstExpr, Ctx&: OutContext));
664 }
665 break;
666
667 // Conditional traps will create a branch on condition instruction that jumps
668 // to the relative immediate field of the jump instruction. (eg. "jo .+2")
669 case SystemZ::CondTrap: {
670 MCSymbol *DotSym = OutContext.createTempSymbol();
671 OutStreamer->emitLabel(Symbol: DotSym);
672
673 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
674 const MCConstantExpr *ConstExpr = MCConstantExpr::create(Value: 2, Ctx&: OutContext);
675 LoweredMI = MCInstBuilder(SystemZ::BRC)
676 .addImm(Val: MI->getOperand(i: 0).getImm())
677 .addImm(Val: MI->getOperand(i: 1).getImm())
678 .addExpr(Val: MCBinaryExpr::createAdd(LHS: Expr, RHS: ConstExpr, Ctx&: OutContext));
679 }
680 break;
681
682 case TargetOpcode::FENTRY_CALL:
683 LowerFENTRY_CALL(MI: *MI, MCIL&: Lower);
684 return;
685
686 case TargetOpcode::STACKMAP:
687 LowerSTACKMAP(MI: *MI);
688 return;
689
690 case TargetOpcode::PATCHPOINT:
691 LowerPATCHPOINT(MI: *MI, Lower);
692 return;
693
694 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
695 LowerPATCHABLE_FUNCTION_ENTER(MI: *MI, Lower);
696 return;
697
698 case TargetOpcode::PATCHABLE_RET:
699 LowerPATCHABLE_RET(MI: *MI, Lower);
700 return;
701
702 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
703 llvm_unreachable("PATCHABLE_FUNCTION_EXIT should never be emitted");
704
705 case TargetOpcode::PATCHABLE_TAIL_CALL:
706 // TODO: Define a trampoline `__xray_FunctionTailExit` and differentiate a
707 // normal function exit from a tail exit.
708 llvm_unreachable("Tail call is handled in the normal case. See comments "
709 "around this assert.");
710
711 case SystemZ::EXRL_Pseudo: {
712 unsigned TargetInsOpc = MI->getOperand(i: 0).getImm();
713 Register LenMinus1Reg = MI->getOperand(i: 1).getReg();
714 Register DestReg = MI->getOperand(i: 2).getReg();
715 int64_t DestDisp = MI->getOperand(i: 3).getImm();
716 Register SrcReg = MI->getOperand(i: 4).getReg();
717 int64_t SrcDisp = MI->getOperand(i: 5).getImm();
718
719 SystemZTargetStreamer *TS = getTargetStreamer();
720 MCInst ET = MCInstBuilder(TargetInsOpc)
721 .addReg(Reg: DestReg)
722 .addImm(Val: DestDisp)
723 .addImm(Val: 1)
724 .addReg(Reg: SrcReg)
725 .addImm(Val: SrcDisp);
726 SystemZTargetStreamer::MCInstSTIPair ET_STI(ET, &MF->getSubtarget());
727 auto [It, Inserted] = TS->EXRLTargets2Sym.try_emplace(k: ET_STI);
728 if (Inserted)
729 It->second = OutContext.createTempSymbol();
730 MCSymbol *DotSym = It->second;
731 const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
732 EmitToStreamer(
733 S&: *OutStreamer,
734 Inst: MCInstBuilder(SystemZ::EXRL).addReg(Reg: LenMinus1Reg).addExpr(Val: Dot));
735 return;
736 }
737
738 // EH_SjLj_Setup is a dummy terminator instruction of size 0.
739 // It is used to handle the clobber register for builtin setjmp.
740 case SystemZ::EH_SjLj_Setup:
741 return;
742
743 default:
744 Lower.lower(MI, OutMI&: LoweredMI);
745 break;
746 }
747 EmitToStreamer(S&: *OutStreamer, Inst: LoweredMI);
748}
749
750// Emit the largest nop instruction smaller than or equal to NumBytes
751// bytes. Return the size of nop emitted.
752static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer,
753 unsigned NumBytes, const MCSubtargetInfo &STI) {
754 if (NumBytes < 2) {
755 llvm_unreachable("Zero nops?");
756 return 0;
757 }
758 else if (NumBytes < 4) {
759 OutStreamer.emitInstruction(
760 Inst: MCInstBuilder(SystemZ::BCRAsm).addImm(Val: 0).addReg(Reg: SystemZ::R0D), STI);
761 return 2;
762 }
763 else if (NumBytes < 6) {
764 OutStreamer.emitInstruction(
765 Inst: MCInstBuilder(SystemZ::BCAsm).addImm(Val: 0).addReg(Reg: 0).addImm(Val: 0).addReg(Reg: 0),
766 STI);
767 return 4;
768 }
769 else {
770 MCSymbol *DotSym = OutContext.createTempSymbol();
771 const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
772 OutStreamer.emitLabel(Symbol: DotSym);
773 OutStreamer.emitInstruction(
774 Inst: MCInstBuilder(SystemZ::BRCLAsm).addImm(Val: 0).addExpr(Val: Dot), STI);
775 return 6;
776 }
777}
778
779void SystemZAsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
780 SystemZMCInstLower &Lower) {
781 MCContext &Ctx = MF->getContext();
782 if (MF->getFunction().hasFnAttribute(Kind: "mrecord-mcount")) {
783 MCSymbol *DotSym = OutContext.createTempSymbol();
784 OutStreamer->pushSection();
785 OutStreamer->switchSection(
786 Section: Ctx.getELFSection(Section: "__mcount_loc", Type: ELF::SHT_PROGBITS, Flags: ELF::SHF_ALLOC));
787 OutStreamer->emitSymbolValue(Sym: DotSym, Size: 8);
788 OutStreamer->popSection();
789 OutStreamer->emitLabel(Symbol: DotSym);
790 }
791
792 if (MF->getFunction().hasFnAttribute(Kind: "mnop-mcount")) {
793 EmitNop(OutContext&: Ctx, OutStreamer&: *OutStreamer, NumBytes: 6, STI: getSubtargetInfo());
794 return;
795 }
796
797 MCSymbol *fentry = Ctx.getOrCreateSymbol(Name: "__fentry__");
798 const MCSymbolRefExpr *Op =
799 MCSymbolRefExpr::create(Symbol: fentry, specifier: SystemZ::S_PLT, Ctx);
800 OutStreamer->emitInstruction(
801 Inst: MCInstBuilder(SystemZ::BRASL).addReg(Reg: SystemZ::R0D).addExpr(Val: Op),
802 STI: getSubtargetInfo());
803}
804
805void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
806 auto *TII = MF->getSubtarget<SystemZSubtarget>().getInstrInfo();
807
808 unsigned NumNOPBytes = MI.getOperand(i: 1).getImm();
809
810 auto &Ctx = OutStreamer->getContext();
811 MCSymbol *MILabel = Ctx.createTempSymbol();
812 OutStreamer->emitLabel(Symbol: MILabel);
813
814 SM.recordStackMap(L: *MILabel, MI);
815 assert(NumNOPBytes % 2 == 0 && "Invalid number of NOP bytes requested!");
816
817 // Scan ahead to trim the shadow.
818 unsigned ShadowBytes = 0;
819 const MachineBasicBlock &MBB = *MI.getParent();
820 MachineBasicBlock::const_iterator MII(MI);
821 ++MII;
822 while (ShadowBytes < NumNOPBytes) {
823 if (MII == MBB.end() ||
824 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
825 MII->getOpcode() == TargetOpcode::STACKMAP)
826 break;
827 ShadowBytes += TII->getInstSizeInBytes(MI: *MII);
828 if (MII->isCall())
829 break;
830 ++MII;
831 }
832
833 // Emit nops.
834 while (ShadowBytes < NumNOPBytes)
835 ShadowBytes += EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: NumNOPBytes - ShadowBytes,
836 STI: getSubtargetInfo());
837}
838
839// Lower a patchpoint of the form:
840// [<def>], <id>, <numBytes>, <target>, <numArgs>
841void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
842 SystemZMCInstLower &Lower) {
843 auto &Ctx = OutStreamer->getContext();
844 MCSymbol *MILabel = Ctx.createTempSymbol();
845 OutStreamer->emitLabel(Symbol: MILabel);
846
847 SM.recordPatchPoint(L: *MILabel, MI);
848 PatchPointOpers Opers(&MI);
849
850 unsigned EncodedBytes = 0;
851 const MachineOperand &CalleeMO = Opers.getCallTarget();
852
853 if (CalleeMO.isImm()) {
854 uint64_t CallTarget = CalleeMO.getImm();
855 if (CallTarget) {
856 unsigned ScratchIdx = -1;
857 unsigned ScratchReg = 0;
858 do {
859 ScratchIdx = Opers.getNextScratchIdx(StartIdx: ScratchIdx + 1);
860 ScratchReg = MI.getOperand(i: ScratchIdx).getReg();
861 } while (ScratchReg == SystemZ::R0D);
862
863 // Materialize the call target address
864 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::LLILF)
865 .addReg(Reg: ScratchReg)
866 .addImm(Val: CallTarget & 0xFFFFFFFF));
867 EncodedBytes += 6;
868 if (CallTarget >> 32) {
869 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::IIHF)
870 .addReg(Reg: ScratchReg)
871 .addImm(Val: CallTarget >> 32));
872 EncodedBytes += 6;
873 }
874
875 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BASR)
876 .addReg(Reg: SystemZ::R14D)
877 .addReg(Reg: ScratchReg));
878 EncodedBytes += 2;
879 }
880 } else if (CalleeMO.isGlobal()) {
881 const MCExpr *Expr = Lower.getExpr(MO: CalleeMO, SystemZ::S_PLT);
882 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRASL)
883 .addReg(Reg: SystemZ::R14D)
884 .addExpr(Val: Expr));
885 EncodedBytes += 6;
886 }
887
888 // Emit padding.
889 unsigned NumBytes = Opers.getNumPatchBytes();
890 assert(NumBytes >= EncodedBytes &&
891 "Patchpoint can't request size less than the length of a call.");
892 assert((NumBytes - EncodedBytes) % 2 == 0 &&
893 "Invalid number of NOP bytes requested!");
894 while (EncodedBytes < NumBytes)
895 EncodedBytes += EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: NumBytes - EncodedBytes,
896 STI: getSubtargetInfo());
897}
898
899void SystemZAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
900 const MachineInstr &MI, SystemZMCInstLower &Lower) {
901 // .begin:
902 // j .end # -> stmg %r2, %r15, 16(%r15)
903 // nop
904 // llilf %2, FuncID
905 // brasl %r14, __xray_FunctionEntry@GOT
906 // .end:
907 //
908 // Update compiler-rt/lib/xray/xray_s390x.cpp accordingly when number
909 // of instructions change.
910 bool HasVectorFeature =
911 TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureVector) &&
912 !TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureSoftFloat);
913 MCSymbol *FuncEntry = OutContext.getOrCreateSymbol(
914 Name: HasVectorFeature ? "__xray_FunctionEntryVec" : "__xray_FunctionEntry");
915 MCSymbol *BeginOfSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
916 MCSymbol *EndOfSled = OutContext.createTempSymbol();
917 OutStreamer->emitLabel(Symbol: BeginOfSled);
918 EmitToStreamer(S&: *OutStreamer,
919 Inst: MCInstBuilder(SystemZ::J)
920 .addExpr(Val: MCSymbolRefExpr::create(Symbol: EndOfSled, Ctx&: OutContext)));
921 EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: 2, STI: getSubtargetInfo());
922 EmitToStreamer(S&: *OutStreamer,
923 Inst: MCInstBuilder(SystemZ::LLILF).addReg(Reg: SystemZ::R2D).addImm(Val: 0));
924 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRASL)
925 .addReg(Reg: SystemZ::R14D)
926 .addExpr(Val: MCSymbolRefExpr::create(
927 Symbol: FuncEntry, specifier: SystemZ::S_PLT, Ctx&: OutContext)));
928 OutStreamer->emitLabel(Symbol: EndOfSled);
929 recordSled(Sled: BeginOfSled, MI, Kind: SledKind::FUNCTION_ENTER, Version: 2);
930}
931
932void SystemZAsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
933 SystemZMCInstLower &Lower) {
934 unsigned OpCode = MI.getOperand(i: 0).getImm();
935 MCSymbol *FallthroughLabel = nullptr;
936 if (OpCode == SystemZ::CondReturn) {
937 FallthroughLabel = OutContext.createTempSymbol();
938 int64_t Cond0 = MI.getOperand(i: 1).getImm();
939 int64_t Cond1 = MI.getOperand(i: 2).getImm();
940 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::BRC)
941 .addImm(Val: Cond0)
942 .addImm(Val: Cond1 ^ Cond0)
943 .addExpr(Val: MCSymbolRefExpr::create(
944 Symbol: FallthroughLabel, Ctx&: OutContext)));
945 }
946 // .begin:
947 // br %r14 # -> stmg %r2, %r15, 24(%r15)
948 // nop
949 // nop
950 // llilf %2,FuncID
951 // j __xray_FunctionExit@GOT
952 //
953 // Update compiler-rt/lib/xray/xray_s390x.cpp accordingly when number
954 // of instructions change.
955 bool HasVectorFeature =
956 TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureVector) &&
957 !TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureSoftFloat);
958 MCSymbol *FuncExit = OutContext.getOrCreateSymbol(
959 Name: HasVectorFeature ? "__xray_FunctionExitVec" : "__xray_FunctionExit");
960 MCSymbol *BeginOfSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
961 OutStreamer->emitLabel(Symbol: BeginOfSled);
962 EmitToStreamer(S&: *OutStreamer,
963 Inst: MCInstBuilder(SystemZ::BR).addReg(Reg: SystemZ::R14D));
964 EmitNop(OutContext, OutStreamer&: *OutStreamer, NumBytes: 4, STI: getSubtargetInfo());
965 EmitToStreamer(S&: *OutStreamer,
966 Inst: MCInstBuilder(SystemZ::LLILF).addReg(Reg: SystemZ::R2D).addImm(Val: 0));
967 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(SystemZ::J)
968 .addExpr(Val: MCSymbolRefExpr::create(
969 Symbol: FuncExit, specifier: SystemZ::S_PLT, Ctx&: OutContext)));
970 if (FallthroughLabel)
971 OutStreamer->emitLabel(Symbol: FallthroughLabel);
972 recordSled(Sled: BeginOfSled, MI, Kind: SledKind::FUNCTION_EXIT, Version: 2);
973}
974
975// The *alignment* of 128-bit vector types is different between the software
976// and hardware vector ABIs. If the there is an externally visible use of a
977// vector type in the module it should be annotated with an attribute.
978void SystemZAsmPrinter::emitAttributes(Module &M) {
979 if (M.getModuleFlag(Key: "s390x-visible-vector-ABI")) {
980 bool HasVectorFeature =
981 TM.getMCSubtargetInfo()->hasFeature(Feature: SystemZ::FeatureVector);
982 OutStreamer->emitGNUAttribute(Tag: 8, Value: HasVectorFeature ? 2 : 1);
983 }
984}
985
986// Convert a SystemZ-specific constant pool modifier into the associated
987// specifier.
988static uint8_t getSpecifierFromModifier(SystemZCP::SystemZCPModifier Modifier) {
989 switch (Modifier) {
990 case SystemZCP::TLSGD:
991 return SystemZ::S_TLSGD;
992 case SystemZCP::TLSLDM:
993 return SystemZ::S_TLSLDM;
994 case SystemZCP::DTPOFF:
995 return SystemZ::S_DTPOFF;
996 case SystemZCP::NTPOFF:
997 return SystemZ::S_NTPOFF;
998 }
999 llvm_unreachable("Invalid SystemCPModifier!");
1000}
1001
1002void SystemZAsmPrinter::emitMachineConstantPoolValue(
1003 MachineConstantPoolValue *MCPV) {
1004 auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);
1005
1006 const MCExpr *Expr = MCSymbolRefExpr::create(
1007 Symbol: getSymbol(GV: ZCPV->getGlobalValue()),
1008 specifier: getSpecifierFromModifier(Modifier: ZCPV->getModifier()), Ctx&: OutContext);
1009 uint64_t Size = getDataLayout().getTypeAllocSize(Ty: ZCPV->getType());
1010
1011 OutStreamer->emitValue(Value: Expr, Size);
1012}
1013
1014static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo,
1015 raw_ostream &OS) {
1016 const char *RegName;
1017 if (MAI->getAssemblerDialect() == AD_HLASM) {
1018 RegName = SystemZHLASMInstPrinter::getRegisterName(Reg: RegNo);
1019 // Skip register prefix so that only register number is left
1020 assert(isalpha(RegName[0]) && isdigit(RegName[1]));
1021 OS << (RegName + 1);
1022 } else {
1023 RegName = SystemZGNUInstPrinter::getRegisterName(Reg: RegNo);
1024 OS << '%' << RegName;
1025 }
1026}
1027
1028static void printReg(unsigned Reg, const MCAsmInfo *MAI, raw_ostream &OS) {
1029 if (!Reg)
1030 OS << '0';
1031 else
1032 printFormattedRegName(MAI, RegNo: Reg, OS);
1033}
1034
1035static void printOperand(const MCOperand &MCOp, const MCAsmInfo *MAI,
1036 raw_ostream &OS) {
1037 if (MCOp.isReg())
1038 printReg(Reg: MCOp.getReg(), MAI, OS);
1039 else if (MCOp.isImm())
1040 OS << MCOp.getImm();
1041 else if (MCOp.isExpr())
1042 MAI->printExpr(OS, *MCOp.getExpr());
1043 else
1044 llvm_unreachable("Invalid operand");
1045}
1046
1047static void printAddress(const MCAsmInfo *MAI, unsigned Base,
1048 const MCOperand &DispMO, unsigned Index,
1049 raw_ostream &OS) {
1050 printOperand(MCOp: DispMO, MAI, OS);
1051 if (Base || Index) {
1052 OS << '(';
1053 if (Index) {
1054 printFormattedRegName(MAI, RegNo: Index, OS);
1055 if (Base)
1056 OS << ',';
1057 }
1058 if (Base)
1059 printFormattedRegName(MAI, RegNo: Base, OS);
1060 OS << ')';
1061 }
1062}
1063
1064bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1065 const char *ExtraCode,
1066 raw_ostream &OS) {
1067 const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();
1068 const MachineOperand &MO = MI->getOperand(i: OpNo);
1069 MCOperand MCOp;
1070 if (ExtraCode) {
1071 if (ExtraCode[0] == 'N' && !ExtraCode[1] && MO.isReg() &&
1072 SystemZ::GR128BitRegClass.contains(Reg: MO.getReg()))
1073 MCOp =
1074 MCOperand::createReg(Reg: MRI.getSubReg(Reg: MO.getReg(), Idx: SystemZ::subreg_l64));
1075 else
1076 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
1077 } else {
1078 SystemZMCInstLower Lower(MF->getContext(), *this);
1079 MCOp = Lower.lowerOperand(MO);
1080 }
1081 printOperand(MCOp, MAI, OS);
1082 return false;
1083}
1084
1085bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1086 unsigned OpNo,
1087 const char *ExtraCode,
1088 raw_ostream &OS) {
1089 if (ExtraCode && ExtraCode[0] && !ExtraCode[1]) {
1090 switch (ExtraCode[0]) {
1091 case 'A':
1092 // Unlike EmitMachineNode(), EmitSpecialNode(INLINEASM) does not call
1093 // setMemRefs(), so MI->memoperands() is empty and the alignment
1094 // information is not available.
1095 return false;
1096 case 'O':
1097 OS << MI->getOperand(i: OpNo + 1).getImm();
1098 return false;
1099 case 'R':
1100 ::printReg(Reg: MI->getOperand(i: OpNo).getReg(), MAI, OS);
1101 return false;
1102 }
1103 }
1104 printAddress(MAI, Base: MI->getOperand(i: OpNo).getReg(),
1105 DispMO: MCOperand::createImm(Val: MI->getOperand(i: OpNo + 1).getImm()),
1106 Index: MI->getOperand(i: OpNo + 2).getReg(), OS);
1107 return false;
1108}
1109
1110void SystemZAsmPrinter::emitEndOfAsmFile(Module &M) {
1111 auto TT = OutContext.getTargetTriple();
1112 if (TT.isOSzOS()) {
1113 emitADASection();
1114 emitIDRLSection(M);
1115 }
1116 emitAttributes(M);
1117 // Emit the END instruction in case of HLASM output. This must be the last
1118 // instruction in the source file.
1119 getTargetStreamer()->emitEnd();
1120}
1121
1122void SystemZAsmPrinter::emitADASection() {
1123 OutStreamer->pushSection();
1124
1125 const unsigned PointerSize = getDataLayout().getPointerSize();
1126 OutStreamer->switchSection(Section: getObjFileLowering().getADASection());
1127
1128 unsigned EmittedBytes = 0;
1129 for (auto &Entry : ADATable.getTable()) {
1130 const MCSymbol *Sym;
1131 unsigned SlotKind;
1132 std::tie(args&: Sym, args&: SlotKind) = Entry.first;
1133 unsigned Offset = Entry.second;
1134 assert(Offset == EmittedBytes && "Offset not as expected");
1135 (void)EmittedBytes;
1136#define EMIT_COMMENT(Str) \
1137 OutStreamer->AddComment(Twine("Offset ") \
1138 .concat(utostr(Offset)) \
1139 .concat(" " Str " ") \
1140 .concat(Sym->getName()));
1141 switch (SlotKind) {
1142 case SystemZII::MO_ADA_DIRECT_FUNC_DESC:
1143 // Language Environment DLL logic requires function descriptors, for
1144 // imported functions, that are placed in the ADA to be 8 byte aligned.
1145 EMIT_COMMENT("function descriptor of");
1146 OutStreamer->emitValue(
1147 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1148 S: SystemZ::S_RCon, Ctx&: OutContext),
1149 Size: PointerSize);
1150 OutStreamer->emitValue(
1151 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1152 S: SystemZ::S_VCon, Ctx&: OutContext),
1153 Size: PointerSize);
1154 EmittedBytes += PointerSize * 2;
1155 break;
1156 case SystemZII::MO_ADA_DATA_SYMBOL_ADDR:
1157 EMIT_COMMENT("pointer to data symbol");
1158 OutStreamer->emitValue(
1159 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext),
1160 S: SystemZ::S_None, Ctx&: OutContext),
1161 Size: PointerSize);
1162 EmittedBytes += PointerSize;
1163 break;
1164 case SystemZII::MO_ADA_INDIRECT_FUNC_DESC: {
1165 MCSymbol *Alias = OutContext.createTempSymbol(
1166 Name: Twine(Sym->getName()).concat(Suffix: "@indirect"));
1167 OutStreamer->emitAssignment(Symbol: Alias,
1168 Value: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext));
1169 OutStreamer->emitSymbolAttribute(Symbol: Alias, Attribute: MCSA_IndirectSymbol);
1170
1171 EMIT_COMMENT("pointer to function descriptor");
1172 OutStreamer->emitValue(
1173 Value: MCSpecifierExpr::create(Expr: MCSymbolRefExpr::create(Symbol: Alias, Ctx&: OutContext),
1174 S: SystemZ::S_VCon, Ctx&: OutContext),
1175 Size: PointerSize);
1176 EmittedBytes += PointerSize;
1177 break;
1178 }
1179 default:
1180 llvm_unreachable("Unexpected slot kind");
1181 }
1182#undef EMIT_COMMENT
1183 }
1184 OutStreamer->popSection();
1185}
1186
1187static std::string getProductID(Module &M) {
1188 std::string ProductID;
1189 if (auto *MD = M.getModuleFlag(Key: "zos_product_id"))
1190 ProductID = cast<MDString>(Val: MD)->getString().str();
1191 if (ProductID.empty())
1192 ProductID = "LLVM";
1193 return ProductID;
1194}
1195
1196static uint32_t getProductVersion(Module &M) {
1197 if (auto *VersionVal = mdconst::extract_or_null<ConstantInt>(
1198 MD: M.getModuleFlag(Key: "zos_product_major_version")))
1199 return VersionVal->getZExtValue();
1200 return LLVM_VERSION_MAJOR;
1201}
1202
1203static uint32_t getProductRelease(Module &M) {
1204 if (auto *ReleaseVal = mdconst::extract_or_null<ConstantInt>(
1205 MD: M.getModuleFlag(Key: "zos_product_minor_version")))
1206 return ReleaseVal->getZExtValue();
1207 return LLVM_VERSION_MINOR;
1208}
1209
1210static uint32_t getProductPatch(Module &M) {
1211 if (auto *PatchVal = mdconst::extract_or_null<ConstantInt>(
1212 MD: M.getModuleFlag(Key: "zos_product_patchlevel")))
1213 return PatchVal->getZExtValue();
1214 return LLVM_VERSION_PATCH;
1215}
1216
1217static time_t getTranslationTime(Module &M) {
1218 std::time_t Time = 0;
1219 if (auto *Val = mdconst::extract_or_null<ConstantInt>(
1220 MD: M.getModuleFlag(Key: "zos_translation_time"))) {
1221 long SecondsSinceEpoch = Val->getSExtValue();
1222 Time = static_cast<time_t>(SecondsSinceEpoch);
1223 }
1224 return Time;
1225}
1226
1227void SystemZAsmPrinter::emitIDRLSection(Module &M) {
1228 OutStreamer->pushSection();
1229 OutStreamer->switchSection(Section: getObjFileLowering().getIDRLSection());
1230 constexpr unsigned IDRLDataLength = 30;
1231 std::time_t Time = getTranslationTime(M);
1232
1233 uint32_t ProductVersion = getProductVersion(M);
1234 uint32_t ProductRelease = getProductRelease(M);
1235
1236 std::string ProductID = getProductID(M);
1237
1238 SmallString<IDRLDataLength + 1> TempStr;
1239 raw_svector_ostream O(TempStr);
1240 O << formatv(Fmt: "{0,-10}{1,0-2:d}{2,0-2:d}{3:%Y%m%d%H%M%S}{4,0-2}",
1241 Vals: ProductID.substr(pos: 0, n: 10).c_str(), Vals&: ProductVersion, Vals&: ProductRelease,
1242 Vals: llvm::sys::toUtcTime(T: Time), Vals: "0");
1243 SmallString<IDRLDataLength> Data;
1244 ConverterEBCDIC::convertToEBCDIC(Source: TempStr, Result&: Data);
1245
1246 OutStreamer->emitInt8(Value: 0); // Reserved.
1247 OutStreamer->emitInt8(Value: 3); // Format.
1248 OutStreamer->emitInt16(Value: IDRLDataLength); // Length.
1249 OutStreamer->emitBytes(Data: Data.str());
1250 OutStreamer->popSection();
1251}
1252
1253void SystemZAsmPrinter::emitFunctionBodyEnd() {
1254 if (TM.getTargetTriple().isOSzOS()) {
1255 // Emit symbol for the end of function if the z/OS target streamer
1256 // is used. This is needed to calculate the size of the function.
1257 MCSymbol *FnEndSym = createTempSymbol(Name: "func_end");
1258 OutStreamer->emitLabel(Symbol: FnEndSym);
1259
1260 OutStreamer->pushSection();
1261 OutStreamer->switchSection(Section: getObjFileLowering().getTextSection(),
1262 Subsec: GOFF::SK_PPA1);
1263 emitPPA1(FnEndSym);
1264 OutStreamer->popSection();
1265
1266 CurrentFnPPA1Sym = nullptr;
1267 CurrentFnEPMarkerSym = nullptr;
1268 }
1269}
1270
1271static void emitPPA1Flags(std::unique_ptr<MCStreamer> &OutStreamer, bool VarArg,
1272 bool StackProtector, bool FPRMask, bool VRMask,
1273 bool EHBlock, bool HasName) {
1274 enum class PPA1Flag1 : uint8_t {
1275 DSA64Bit = (0x80 >> 0),
1276 VarArg = (0x80 >> 7),
1277 LLVM_MARK_AS_BITMASK_ENUM(DSA64Bit)
1278 };
1279 enum class PPA1Flag2 : uint8_t {
1280 ExternalProcedure = (0x80 >> 0),
1281 STACKPROTECTOR = (0x80 >> 3),
1282 LLVM_MARK_AS_BITMASK_ENUM(ExternalProcedure)
1283 };
1284 enum class PPA1Flag3 : uint8_t {
1285 FPRMask = (0x80 >> 2),
1286 LLVM_MARK_AS_BITMASK_ENUM(FPRMask)
1287 };
1288 enum class PPA1Flag4 : uint8_t {
1289 EPMOffsetPresent = (0x80 >> 0),
1290 VRMask = (0x80 >> 2),
1291 EHBlock = (0x80 >> 3),
1292 ProcedureNamePresent = (0x80 >> 7),
1293 LLVM_MARK_AS_BITMASK_ENUM(EPMOffsetPresent)
1294 };
1295
1296 // Declare optional section flags that can be modified.
1297 auto Flags1 = PPA1Flag1(0);
1298 auto Flags2 = PPA1Flag2::ExternalProcedure;
1299 auto Flags3 = PPA1Flag3(0);
1300 auto Flags4 = PPA1Flag4::EPMOffsetPresent;
1301
1302 Flags1 |= PPA1Flag1::DSA64Bit;
1303
1304 if (VarArg)
1305 Flags1 |= PPA1Flag1::VarArg;
1306
1307 if (StackProtector)
1308 Flags2 |= PPA1Flag2::STACKPROTECTOR;
1309
1310 // SavedGPRMask, SavedFPRMask, and SavedVRMask are precomputed in.
1311 if (FPRMask)
1312 Flags3 |= PPA1Flag3::FPRMask; // Add emit FPR mask flag.
1313
1314 if (VRMask)
1315 Flags4 |= PPA1Flag4::VRMask; // Add emit VR mask flag.
1316
1317 if (EHBlock)
1318 Flags4 |= PPA1Flag4::EHBlock; // Add optional EH block.
1319
1320 if (HasName)
1321 Flags4 |= PPA1Flag4::ProcedureNamePresent; // Add optional name block.
1322
1323 OutStreamer->AddComment(T: "PPA1 Flags 1");
1324 if ((Flags1 & PPA1Flag1::DSA64Bit) == PPA1Flag1::DSA64Bit)
1325 OutStreamer->AddComment(T: " Bit 0: 1 = 64-bit DSA");
1326 else
1327 OutStreamer->AddComment(T: " Bit 0: 0 = 32-bit DSA");
1328 if ((Flags1 & PPA1Flag1::VarArg) == PPA1Flag1::VarArg)
1329 OutStreamer->AddComment(T: " Bit 7: 1 = Vararg function");
1330 OutStreamer->emitInt8(Value: static_cast<uint8_t>(Flags1)); // Flags 1.
1331
1332 OutStreamer->AddComment(T: "PPA1 Flags 2");
1333 if ((Flags2 & PPA1Flag2::ExternalProcedure) == PPA1Flag2::ExternalProcedure)
1334 OutStreamer->AddComment(T: " Bit 0: 1 = External procedure");
1335 if ((Flags2 & PPA1Flag2::STACKPROTECTOR) == PPA1Flag2::STACKPROTECTOR)
1336 OutStreamer->AddComment(T: " Bit 3: 1 = STACKPROTECT is enabled");
1337 else
1338 OutStreamer->AddComment(T: " Bit 3: 0 = STACKPROTECT is not enabled");
1339 OutStreamer->emitInt8(Value: static_cast<uint8_t>(Flags2)); // Flags 2.
1340
1341 OutStreamer->AddComment(T: "PPA1 Flags 3");
1342 if ((Flags3 & PPA1Flag3::FPRMask) == PPA1Flag3::FPRMask)
1343 OutStreamer->AddComment(T: " Bit 2: 1 = FP Reg Mask is in optional area");
1344 OutStreamer->emitInt8(
1345 Value: static_cast<uint8_t>(Flags3)); // Flags 3 (optional sections).
1346
1347 OutStreamer->AddComment(T: "PPA1 Flags 4");
1348 if ((Flags4 & PPA1Flag4::VRMask) == PPA1Flag4::VRMask)
1349 OutStreamer->AddComment(T: " Bit 2: 1 = Vector Reg Mask is in optional area");
1350 if ((Flags4 & PPA1Flag4::EHBlock) == PPA1Flag4::EHBlock)
1351 OutStreamer->AddComment(T: " Bit 3: 1 = C++ EH block");
1352 if ((Flags4 & PPA1Flag4::ProcedureNamePresent) ==
1353 PPA1Flag4::ProcedureNamePresent)
1354 OutStreamer->AddComment(T: " Bit 7: 1 = Name Length and Name");
1355 OutStreamer->emitInt8(Value: static_cast<uint8_t>(
1356 Flags4)); // Flags 4 (optional sections, always emit these).
1357}
1358
1359static void emitPPA1Name(std::unique_ptr<MCStreamer> &OutStreamer,
1360 StringRef OutName) {
1361 size_t NameSize = OutName.size();
1362 uint16_t OutSize;
1363 if (NameSize < UINT16_MAX) {
1364 OutSize = static_cast<uint16_t>(NameSize);
1365 } else {
1366 OutName = OutName.substr(Start: 0, UINT16_MAX);
1367 OutSize = UINT16_MAX;
1368 }
1369 // Emit padding to ensure that the next optional field word-aligned.
1370 uint8_t ExtraZeros = 4 - ((2 + OutSize) % 4);
1371
1372 SmallString<512> OutnameConv;
1373 ConverterEBCDIC::convertToEBCDIC(Source: OutName, Result&: OutnameConv);
1374 OutName = OutnameConv.str();
1375
1376 OutStreamer->AddComment(T: "Length of Name");
1377 OutStreamer->emitInt16(Value: OutSize);
1378 OutStreamer->AddComment(T: "Name of Function");
1379 OutStreamer->emitBytes(Data: OutName);
1380 OutStreamer->emitZeros(NumBytes: ExtraZeros);
1381}
1382
1383void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) {
1384 assert(PPA2Sym != nullptr && "PPA2 Symbol not defined");
1385
1386 const TargetRegisterInfo *TRI = MF->getRegInfo().getTargetRegisterInfo();
1387 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
1388 const auto TargetHasVector = Subtarget.hasVector();
1389
1390 const SystemZMachineFunctionInfo *ZFI =
1391 MF->getInfo<SystemZMachineFunctionInfo>();
1392 const auto *ZFL = static_cast<const SystemZXPLINKFrameLowering *>(
1393 Subtarget.getFrameLowering());
1394 const MachineFrameInfo &MFFrame = MF->getFrameInfo();
1395
1396 // Get saved GPR/FPR/VPR masks.
1397 const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
1398 uint16_t SavedGPRMask = 0;
1399 uint16_t SavedFPRMask = 0;
1400 uint8_t SavedVRMask = 0;
1401 int64_t OffsetFPR = 0;
1402 int64_t OffsetVR = 0;
1403 const int64_t TopOfStack =
1404 MFFrame.getOffsetAdjustment() + MFFrame.getStackSize();
1405
1406 // Loop over the spilled registers. The CalleeSavedInfo can't be used because
1407 // it does not contain all spilled registers.
1408 for (unsigned I = ZFI->getSpillGPRRegs().LowGPR,
1409 E = ZFI->getSpillGPRRegs().HighGPR;
1410 I && E && I <= E; ++I) {
1411 unsigned V = TRI->getEncodingValue(Reg: (Register)I);
1412 assert(V < 16 && "GPR index out of range");
1413 SavedGPRMask |= 1 << (15 - V);
1414 }
1415
1416 for (auto &CS : CSI) {
1417 unsigned Reg = CS.getReg();
1418 unsigned I = TRI->getEncodingValue(Reg);
1419
1420 if (SystemZ::FP64BitRegClass.contains(Reg)) {
1421 assert(I < 16 && "FPR index out of range");
1422 SavedFPRMask |= 1 << (15 - I);
1423 int64_t Temp = MFFrame.getObjectOffset(ObjectIdx: CS.getFrameIdx());
1424 if (Temp < OffsetFPR)
1425 OffsetFPR = Temp;
1426 } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
1427 assert(I >= 16 && I <= 23 && "VPR index out of range");
1428 unsigned BitNum = I - 16;
1429 SavedVRMask |= 1 << (7 - BitNum);
1430 int64_t Temp = MFFrame.getObjectOffset(ObjectIdx: CS.getFrameIdx());
1431 if (Temp < OffsetVR)
1432 OffsetVR = Temp;
1433 }
1434 }
1435
1436 // Adjust the offset.
1437 OffsetFPR += (OffsetFPR < 0) ? TopOfStack : 0;
1438 OffsetVR += (OffsetVR < 0) ? TopOfStack : 0;
1439
1440 // Get alloca register.
1441 uint8_t FrameReg = TRI->getEncodingValue(Reg: TRI->getFrameRegister(MF: *MF));
1442 uint8_t AllocaReg = ZFL->hasFP(MF: *MF) ? FrameReg : 0;
1443 assert(AllocaReg < 16 && "Can't have alloca register larger than 15");
1444 (void)AllocaReg;
1445
1446 // Build FPR save area offset.
1447 uint32_t FrameAndFPROffset = 0;
1448 if (SavedFPRMask) {
1449 uint64_t FPRSaveAreaOffset = OffsetFPR;
1450 assert(FPRSaveAreaOffset < 0x10000000 && "Offset out of range");
1451
1452 FrameAndFPROffset = FPRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.
1453 FrameAndFPROffset |= FrameReg << 28; // Put into top 4 bits.
1454 }
1455
1456 // Build VR save area offset.
1457 uint32_t FrameAndVROffset = 0;
1458 if (TargetHasVector && SavedVRMask) {
1459 uint64_t VRSaveAreaOffset = OffsetVR;
1460 assert(VRSaveAreaOffset < 0x10000000 && "Offset out of range");
1461
1462 FrameAndVROffset = VRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.
1463 FrameAndVROffset |= FrameReg << 28; // Put into top 4 bits.
1464 }
1465
1466 // Emit PPA1 section.
1467 OutStreamer->AddComment(T: "PPA1");
1468 OutStreamer->emitLabel(Symbol: CurrentFnPPA1Sym);
1469 OutStreamer->AddComment(T: "Version");
1470 OutStreamer->emitInt8(Value: 0x02); // Version.
1471 OutStreamer->AddComment(T: "LE Signature X'CE'");
1472 OutStreamer->emitInt8(Value: 0xCE); // CEL signature.
1473 OutStreamer->AddComment(T: "Saved GPR Mask");
1474 OutStreamer->emitInt16(Value: SavedGPRMask);
1475 OutStreamer->AddComment(T: "Offset to PPA2");
1476 OutStreamer->emitAbsoluteSymbolDiff(Hi: PPA2Sym, Lo: CurrentFnPPA1Sym, Size: 4);
1477
1478 bool NeedEmitEHBlock = !MF->getLandingPads().empty();
1479
1480 bool HasName =
1481 MF->getFunction().hasName() && MF->getFunction().getName().size() > 0;
1482
1483 emitPPA1Flags(OutStreamer, VarArg: MF->getFunction().isVarArg(),
1484 StackProtector: MFFrame.hasStackProtectorIndex(), FPRMask: SavedFPRMask != 0,
1485 VRMask: TargetHasVector && SavedVRMask != 0, EHBlock: NeedEmitEHBlock, HasName);
1486
1487 OutStreamer->AddComment(T: "Length/4 of Parms");
1488 OutStreamer->emitInt16(
1489 Value: static_cast<uint16_t>(ZFI->getSizeOfFnParams() / 4)); // Parms/4.
1490 OutStreamer->AddComment(T: "Length of Code");
1491 OutStreamer->emitAbsoluteSymbolDiff(Hi: FnEndSym, Lo: CurrentFnEPMarkerSym, Size: 4);
1492
1493 // Emit saved FPR mask and offset to FPR save area (0x20 of flags 3).
1494 if (SavedFPRMask) {
1495 OutStreamer->AddComment(T: "FPR mask");
1496 OutStreamer->emitInt16(Value: SavedFPRMask);
1497 OutStreamer->AddComment(T: "AR mask");
1498 OutStreamer->emitInt16(Value: 0); // AR Mask, unused currently.
1499 OutStreamer->AddComment(T: "FPR Save Area Locator");
1500 OutStreamer->AddComment(T: Twine(" Bit 0-3: Register R")
1501 .concat(Suffix: utostr(X: FrameAndFPROffset >> 28))
1502 .str());
1503 OutStreamer->AddComment(T: Twine(" Bit 4-31: Offset ")
1504 .concat(Suffix: utostr(X: FrameAndFPROffset & 0x0FFFFFFF))
1505 .str());
1506 OutStreamer->emitInt32(Value: FrameAndFPROffset); // Offset to FPR save area with
1507 // register to add value to
1508 // (alloca reg).
1509 }
1510
1511 // Emit saved VR mask to VR save area.
1512 if (TargetHasVector && SavedVRMask) {
1513 OutStreamer->AddComment(T: "VR mask");
1514 OutStreamer->emitInt8(Value: SavedVRMask);
1515 OutStreamer->emitInt8(Value: 0); // Reserved.
1516 OutStreamer->emitInt16(Value: 0); // Also reserved.
1517 OutStreamer->AddComment(T: "VR Save Area Locator");
1518 OutStreamer->AddComment(T: Twine(" Bit 0-3: Register R")
1519 .concat(Suffix: utostr(X: FrameAndVROffset >> 28))
1520 .str());
1521 OutStreamer->AddComment(T: Twine(" Bit 4-31: Offset ")
1522 .concat(Suffix: utostr(X: FrameAndVROffset & 0x0FFFFFFF))
1523 .str());
1524 OutStreamer->emitInt32(Value: FrameAndVROffset);
1525 }
1526
1527 // Emit C++ EH information block
1528 const Function *Per = nullptr;
1529 if (NeedEmitEHBlock) {
1530 Per = dyn_cast<Function>(
1531 Val: MF->getFunction().getPersonalityFn()->stripPointerCasts());
1532 MCSymbol *PersonalityRoutine =
1533 Per ? MF->getTarget().getSymbol(GV: Per) : nullptr;
1534 assert(PersonalityRoutine && "Missing personality routine");
1535
1536 OutStreamer->AddComment(T: "Version");
1537 OutStreamer->emitInt32(Value: 1);
1538 OutStreamer->AddComment(T: "Flags");
1539 OutStreamer->emitInt32(Value: 0); // LSDA field is a WAS offset
1540 OutStreamer->AddComment(T: "Personality routine");
1541 OutStreamer->emitInt64(Value: ADATable.insert(
1542 Sym: PersonalityRoutine, SlotKind: SystemZII::MO_ADA_INDIRECT_FUNC_DESC));
1543 OutStreamer->AddComment(T: "LSDA location");
1544 MCSymbol *GCCEH = MF->getContext().getOrCreateSymbol(
1545 Name: Twine("GCC_except_table") + Twine(MF->getFunctionNumber()));
1546 OutStreamer->emitInt64(
1547 Value: ADATable.insert(Sym: GCCEH, SlotKind: SystemZII::MO_ADA_DATA_SYMBOL_ADDR));
1548 }
1549
1550 // Emit name length and name optional section (0x01 of flags 4)
1551 if (HasName)
1552 emitPPA1Name(OutStreamer, OutName: MF->getFunction().getName());
1553
1554 // Emit offset to entry point optional section (0x80 of flags 4).
1555 OutStreamer->emitAbsoluteSymbolDiff(Hi: CurrentFnEPMarkerSym, Lo: CurrentFnPPA1Sym,
1556 Size: 4);
1557}
1558
1559void SystemZAsmPrinter::emitStartOfAsmFile(Module &M) {
1560 if (TM.getTargetTriple().isOSzOS())
1561 emitPPA2(M);
1562 AsmPrinter::emitStartOfAsmFile(M);
1563}
1564
1565void SystemZAsmPrinter::emitPPA2(Module &M) {
1566 OutStreamer->pushSection();
1567 OutStreamer->switchSection(Section: getObjFileLowering().getTextSection(),
1568 Subsec: GOFF::SK_PPA2);
1569 MCContext &OutContext = OutStreamer->getContext();
1570 // Make CELQSTRT symbol.
1571 const char *StartSymbolName = "CELQSTRT";
1572 MCSymbol *CELQSTRT = OutContext.getOrCreateSymbol(Name: StartSymbolName);
1573
1574 // Create symbol and assign to class field for use in PPA1.
1575 PPA2Sym = OutContext.createTempSymbol(Name: "PPA2", AlwaysAddSuffix: false);
1576 MCSymbol *DateVersionSym = OutContext.createTempSymbol(Name: "DVS", AlwaysAddSuffix: false);
1577
1578 std::time_t Time = getTranslationTime(M);
1579 SmallString<15> CompilationTime; // 14 + null
1580 raw_svector_ostream O(CompilationTime);
1581 O << formatv(Fmt: "{0:%Y%m%d%H%M%S}", Vals: llvm::sys::toUtcTime(T: Time));
1582
1583 uint32_t ProductVersion = getProductVersion(M),
1584 ProductRelease = getProductRelease(M),
1585 ProductPatch = getProductPatch(M);
1586
1587 SmallString<7> Version; // 6 + null
1588 raw_svector_ostream ostr(Version);
1589 ostr << formatv(Fmt: "{0,0-2:d}{1,0-2:d}{2,0-2:d}", Vals&: ProductVersion, Vals&: ProductRelease,
1590 Vals&: ProductPatch);
1591
1592 // Drop 0 during conversion.
1593 SmallString<sizeof(CompilationTime) - 1> CompilationTimeStr;
1594 SmallString<sizeof(Version) - 1> VersionStr;
1595
1596 ConverterEBCDIC::convertToEBCDIC(Source: CompilationTime, Result&: CompilationTimeStr);
1597 ConverterEBCDIC::convertToEBCDIC(Source: Version, Result&: VersionStr);
1598
1599 enum class PPA2MemberId : uint8_t {
1600 // See z/OS Language Environment Vendor Interfaces v2r5, p.23, for
1601 // complete list. Only the C runtime is supported by this backend.
1602 LE_C_Runtime = 3,
1603 };
1604 enum class PPA2MemberSubId : uint8_t {
1605 // List of languages using the LE C runtime implementation.
1606 C = 0x00,
1607 CXX = 0x01,
1608 Swift = 0x03,
1609 Go = 0x60,
1610 LLVMBasedLang = 0xe7,
1611 };
1612 // PPA2 Flags
1613 enum class PPA2Flags : uint8_t {
1614 CompileForBinaryFloatingPoint = 0x80,
1615 CompiledWithXPLink = 0x01,
1616 CompiledUnitASCII = 0x04,
1617 HasServiceInfo = 0x20,
1618 };
1619
1620 PPA2MemberSubId MemberSubId = PPA2MemberSubId::LLVMBasedLang;
1621 if (auto *MD = M.getModuleFlag(Key: "zos_cu_language")) {
1622 StringRef Language = cast<MDString>(Val: MD)->getString();
1623 MemberSubId = StringSwitch<PPA2MemberSubId>(Language)
1624 .Case(S: "C", Value: PPA2MemberSubId::C)
1625 .Case(S: "C++", Value: PPA2MemberSubId::CXX)
1626 .Case(S: "Swift", Value: PPA2MemberSubId::Swift)
1627 .Case(S: "Go", Value: PPA2MemberSubId::Go)
1628 .Default(Value: PPA2MemberSubId::LLVMBasedLang);
1629 }
1630
1631 // Emit PPA2 section.
1632 OutStreamer->emitLabel(Symbol: PPA2Sym);
1633 OutStreamer->emitInt8(Value: static_cast<uint8_t>(PPA2MemberId::LE_C_Runtime));
1634 OutStreamer->emitInt8(Value: static_cast<uint8_t>(MemberSubId));
1635 OutStreamer->emitInt8(Value: 0x22); // Member defined, c370_plist+c370_env
1636 OutStreamer->emitInt8(Value: 0x04); // Control level 4 (XPLink)
1637 OutStreamer->emitAbsoluteSymbolDiff(Hi: CELQSTRT, Lo: PPA2Sym, Size: 4);
1638 OutStreamer->emitInt32(Value: 0x00000000);
1639 OutStreamer->emitAbsoluteSymbolDiff(Hi: DateVersionSym, Lo: PPA2Sym, Size: 4);
1640 OutStreamer->emitInt32(
1641 Value: 0x00000000); // Offset to main entry point, always 0 (so says TR).
1642 uint8_t Flgs = static_cast<uint8_t>(PPA2Flags::CompileForBinaryFloatingPoint);
1643 Flgs |= static_cast<uint8_t>(PPA2Flags::CompiledWithXPLink);
1644
1645 if (auto *MD = M.getModuleFlag(Key: "zos_le_char_mode")) {
1646 const StringRef &CharMode = cast<MDString>(Val: MD)->getString();
1647 if (CharMode == "ascii") {
1648 Flgs |= static_cast<uint8_t>(
1649 PPA2Flags::CompiledUnitASCII); // Setting bit for ASCII char. mode.
1650 } else if (CharMode != "ebcdic") {
1651 report_fatal_error(
1652 reason: "Only ascii or ebcdic are valid values for zos_le_char_mode "
1653 "metadata");
1654 }
1655 }
1656
1657 OutStreamer->emitInt8(Value: Flgs);
1658 OutStreamer->emitInt8(Value: 0x00); // Reserved.
1659 // No MD5 signature before timestamp.
1660 // No FLOAT(AFP(VOLATILE)).
1661 // Remaining 5 flag bits reserved.
1662 OutStreamer->emitInt16(Value: 0x0000); // 16 Reserved flag bits.
1663
1664 // Emit date and version section.
1665 OutStreamer->emitLabel(Symbol: DateVersionSym);
1666 OutStreamer->emitBytes(Data: CompilationTimeStr.str());
1667 OutStreamer->emitBytes(Data: VersionStr.str());
1668
1669 OutStreamer->emitInt16(Value: 0x0000); // Service level string length.
1670
1671 // The binder requires that the offset to the PPA2 be emitted in a different,
1672 // specially-named section.
1673 OutStreamer->switchSection(Section: getObjFileLowering().getPPA2ListSection());
1674 // Emit 8 byte alignment.
1675 // Emit pointer to PPA2 label.
1676 OutStreamer->AddComment(T: "A(PPA2-CELQSTRT)");
1677 OutStreamer->emitAbsoluteSymbolDiff(Hi: PPA2Sym, Lo: CELQSTRT, Size: 8);
1678 OutStreamer->popSection();
1679}
1680
1681void SystemZAsmPrinter::emitFunctionEntryLabel() {
1682 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
1683
1684 if (Subtarget.getTargetTriple().isOSzOS()) {
1685 MCContext &OutContext = OutStreamer->getContext();
1686
1687 // Save information for later use.
1688 std::string N(MF->getFunction().hasName()
1689 ? Twine(MF->getFunction().getName()).concat(Suffix: "_").str()
1690 : "");
1691
1692 CurrentFnEPMarkerSym =
1693 OutContext.createTempSymbol(Name: Twine("EPM_").concat(Suffix: N).str(), AlwaysAddSuffix: true);
1694 CurrentFnPPA1Sym =
1695 OutContext.createTempSymbol(Name: Twine("PPA1_").concat(Suffix: N).str(), AlwaysAddSuffix: true);
1696
1697 // EntryPoint Marker
1698 const MachineFrameInfo &MFFrame = MF->getFrameInfo();
1699 bool IsUsingAlloca = MFFrame.hasVarSizedObjects();
1700 uint32_t DSASize = MFFrame.getStackSize();
1701 bool IsLeaf = DSASize == 0 && MFFrame.getCalleeSavedInfo().empty();
1702
1703 // Set Flags.
1704 uint8_t Flags = 0;
1705 if (IsLeaf)
1706 Flags |= 0x08;
1707 if (IsUsingAlloca)
1708 Flags |= 0x04;
1709
1710 // Combine into top 27 bits of DSASize and bottom 5 bits of Flags.
1711 uint32_t DSAAndFlags = DSASize & 0xFFFFFFE0; // (x/32) << 5
1712 DSAAndFlags |= Flags;
1713
1714 // Emit entry point marker section.
1715 OutStreamer->AddComment(T: "XPLINK Routine Layout Entry");
1716 OutStreamer->emitLabel(Symbol: CurrentFnEPMarkerSym);
1717 OutStreamer->AddComment(T: "Eyecatcher 0x00C300C500C500");
1718 OutStreamer->emitIntValueInHex(Value: 0x00C300C500C500, Size: 7); // Eyecatcher.
1719 OutStreamer->AddComment(T: "Mark Type C'1'");
1720 OutStreamer->emitInt8(Value: 0xF1); // Mark Type.
1721 OutStreamer->AddComment(T: "Offset to PPA1");
1722 OutStreamer->emitAbsoluteSymbolDiff(Hi: CurrentFnPPA1Sym, Lo: CurrentFnEPMarkerSym,
1723 Size: 4);
1724 if (OutStreamer->isVerboseAsm()) {
1725 OutStreamer->AddComment(T: "DSA Size 0x" + Twine::utohexstr(Val: DSASize));
1726 OutStreamer->AddComment(T: "Entry Flags");
1727 if (Flags & 0x08)
1728 OutStreamer->AddComment(T: " Bit 1: 1 = Leaf function");
1729 else
1730 OutStreamer->AddComment(T: " Bit 1: 0 = Non-leaf function");
1731 if (Flags & 0x04)
1732 OutStreamer->AddComment(T: " Bit 2: 1 = Uses alloca");
1733 else
1734 OutStreamer->AddComment(T: " Bit 2: 0 = Does not use alloca");
1735 }
1736 OutStreamer->emitInt32(Value: DSAAndFlags);
1737 }
1738
1739 AsmPrinter::emitFunctionEntryLabel();
1740}
1741
1742char SystemZAsmPrinter::ID = 0;
1743
1744INITIALIZE_PASS(SystemZAsmPrinter, "systemz-asm-printer",
1745 "SystemZ Assembly Printer", false, false)
1746
1747// Force static initialization.
1748extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
1749LLVMInitializeSystemZAsmPrinter() {
1750 RegisterAsmPrinter<SystemZAsmPrinter> X(getTheSystemZTarget());
1751}
1752