1//===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the WebAssembly-specific subclass of
11/// TargetSubtarget.
12///
13//===----------------------------------------------------------------------===//
14
15#include "WebAssemblySubtarget.h"
16#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17#include "WebAssemblyInstrInfo.h"
18#include "llvm/MC/TargetRegistry.h"
19using namespace llvm;
20
21#define DEBUG_TYPE "wasm-subtarget"
22
23#define GET_SUBTARGETINFO_CTOR
24#define GET_SUBTARGETINFO_TARGET_DESC
25#include "WebAssemblyGenSubtargetInfo.inc"
26
27WebAssemblySubtarget &
28WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
29 StringRef FS) {
30 // Determine default and user-specified characteristics
31 LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");
32
33 if (CPU.empty())
34 CPU = "generic";
35
36 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
37
38 FeatureBitset Bits = getFeatureBits();
39
40 // bulk-memory implies bulk-memory-opt
41 if (HasBulkMemory) {
42 HasBulkMemoryOpt = true;
43 Bits.set(WebAssembly::FeatureBulkMemoryOpt);
44 }
45
46 // reference-types implies call-indirect-overlong
47 if (HasReferenceTypes) {
48 HasCallIndirectOverlong = true;
49 Bits.set(WebAssembly::FeatureCallIndirectOverlong);
50 }
51
52 // In case we changed any bits, update `MCSubtargetInfo`'s `FeatureBitset`.
53 setFeatureBits(Bits);
54
55 return *this;
56}
57
58WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
59 const std::string &CPU,
60 const std::string &FS,
61 const TargetMachine &TM)
62 : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
63 TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
64 TLInfo(TM, *this) {}
65
66bool WebAssemblySubtarget::enableAtomicExpand() const {
67 // If atomics are disabled, atomic ops are lowered instead of expanded
68 return hasAtomics();
69}
70
71bool WebAssemblySubtarget::enableMachineScheduler() const {
72 // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
73 // enableMachineSchedDefaultSched overridden, it appears to have an overall
74 // negative effect for the kinds of register optimizations we're doing.
75 return false;
76}
77
78bool WebAssemblySubtarget::useAA() const { return true; }
79