1//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file includes code for rendering MCInst instances as AT&T-style
10// assembly.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86ATTInstPrinter.h"
15#include "X86BaseInfo.h"
16#include "X86InstComments.h"
17#include "llvm/MC/MCAsmInfo.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrAnalysis.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/Format.h"
25#include "llvm/Support/raw_ostream.h"
26#include <cassert>
27#include <cinttypes>
28#include <cstdint>
29
30using namespace llvm;
31
32#define DEBUG_TYPE "asm-printer"
33
34// Include the auto-generated portion of the assembly writer.
35#define PRINT_ALIAS_INSTR
36#include "X86GenAsmWriter.inc"
37
38void X86ATTInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) {
39 markup(OS, M: Markup::Register) << '%' << getRegisterName(Reg);
40}
41
42void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
43 StringRef Annot, const MCSubtargetInfo &STI,
44 raw_ostream &OS) {
45 // If verbose assembly is enabled, we can print some informative comments.
46 if (CommentStream)
47 HasCustomInstComment = EmitAnyX86InstComments(MI, OS&: *CommentStream, MCII: MII);
48
49 printInstFlags(MI, O&: OS, STI);
50
51 // Output CALLpcrel32 as "callq" in 64-bit mode.
52 // In Intel annotation it's always emitted as "call".
53 //
54 // TODO: Probably this hack should be redesigned via InstAlias in
55 // InstrInfo.td as soon as Requires clause is supported properly
56 // for InstAlias.
57 if (MI->getOpcode() == X86::CALLpcrel32 &&
58 (STI.hasFeature(Feature: X86::Is64Bit))) {
59 OS << "\tcallq\t";
60 printPCRelImm(MI, Address, OpNo: 0, O&: OS);
61 }
62 // data16 and data32 both have the same encoding of 0x66. While data32 is
63 // valid only in 16 bit systems, data16 is valid in the rest.
64 // There seems to be some lack of support of the Requires clause that causes
65 // 0x66 to be interpreted as "data16" by the asm printer.
66 // Thus we add an adjustment here in order to print the "right" instruction.
67 else if (MI->getOpcode() == X86::DATA16_PREFIX &&
68 STI.hasFeature(Feature: X86::Is16Bit)) {
69 OS << "\tdata32";
70 }
71 // Try to print any aliases first.
72 else if (!printAliasInstr(MI, Address, OS) && !printVecCompareInstr(MI, OS))
73 printInstruction(MI, Address, O&: OS);
74
75 // Next always print the annotation.
76 printAnnotation(OS, Annot);
77}
78
79bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
80 raw_ostream &OS) {
81 if (MI->getNumOperands() == 0 ||
82 !MI->getOperand(i: MI->getNumOperands() - 1).isImm())
83 return false;
84
85 int64_t Imm = MI->getOperand(i: MI->getNumOperands() - 1).getImm();
86
87 const MCInstrDesc &Desc = MII.get(Opcode: MI->getOpcode());
88
89 // Custom print the vector compare instructions to get the immediate
90 // translated into the mnemonic.
91 switch (MI->getOpcode()) {
92 case X86::CMPPDrmi: case X86::CMPPDrri:
93 case X86::CMPPSrmi: case X86::CMPPSrri:
94 case X86::CMPSDrmi: case X86::CMPSDrri:
95 case X86::CMPSDrmi_Int: case X86::CMPSDrri_Int:
96 case X86::CMPSSrmi: case X86::CMPSSrri:
97 case X86::CMPSSrmi_Int: case X86::CMPSSrri_Int:
98 if (Imm >= 0 && Imm <= 7) {
99 OS << '\t';
100 printCMPMnemonic(MI, /*IsVCMP*/IsVCmp: false, OS);
101
102 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
103 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
104 printdwordmem(MI, OpNo: 2, O&: OS);
105 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
106 printqwordmem(MI, OpNo: 2, O&: OS);
107 else
108 printxmmwordmem(MI, OpNo: 2, O&: OS);
109 } else
110 printOperand(MI, OpNo: 2, OS);
111
112 // Skip operand 1 as its tied to the dest.
113
114 OS << ", ";
115 printOperand(MI, OpNo: 0, OS);
116 return true;
117 }
118 break;
119
120 case X86::VCMPPDrmi: case X86::VCMPPDrri:
121 case X86::VCMPPDYrmi: case X86::VCMPPDYrri:
122 case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri:
123 case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri:
124 case X86::VCMPPDZrmi: case X86::VCMPPDZrri:
125 case X86::VCMPPSrmi: case X86::VCMPPSrri:
126 case X86::VCMPPSYrmi: case X86::VCMPPSYrri:
127 case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri:
128 case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri:
129 case X86::VCMPPSZrmi: case X86::VCMPPSZrri:
130 case X86::VCMPSDrmi: case X86::VCMPSDrri:
131 case X86::VCMPSDZrmi: case X86::VCMPSDZrri:
132 case X86::VCMPSDrmi_Int: case X86::VCMPSDrri_Int:
133 case X86::VCMPSDZrmi_Int: case X86::VCMPSDZrri_Int:
134 case X86::VCMPSSrmi: case X86::VCMPSSrri:
135 case X86::VCMPSSZrmi: case X86::VCMPSSZrri:
136 case X86::VCMPSSrmi_Int: case X86::VCMPSSrri_Int:
137 case X86::VCMPSSZrmi_Int: case X86::VCMPSSZrri_Int:
138 case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
139 case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
140 case X86::VCMPPDZrmik: case X86::VCMPPDZrrik:
141 case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
142 case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
143 case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
144 case X86::VCMPSDZrmik_Int: case X86::VCMPSDZrrik_Int:
145 case X86::VCMPSSZrmik_Int: case X86::VCMPSSZrrik_Int:
146 case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
147 case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
148 case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
149 case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
150 case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
151 case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
152 case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
153 case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
154 case X86::VCMPSDZrrib_Int: case X86::VCMPSDZrribk_Int:
155 case X86::VCMPSSZrrib_Int: case X86::VCMPSSZrribk_Int:
156 case X86::VCMPPHZ128rmi: case X86::VCMPPHZ128rri:
157 case X86::VCMPPHZ256rmi: case X86::VCMPPHZ256rri:
158 case X86::VCMPPHZrmi: case X86::VCMPPHZrri:
159 case X86::VCMPSHZrmi: case X86::VCMPSHZrri:
160 case X86::VCMPSHZrmi_Int: case X86::VCMPSHZrri_Int:
161 case X86::VCMPPHZ128rmik: case X86::VCMPPHZ128rrik:
162 case X86::VCMPPHZ256rmik: case X86::VCMPPHZ256rrik:
163 case X86::VCMPPHZrmik: case X86::VCMPPHZrrik:
164 case X86::VCMPSHZrmik_Int: case X86::VCMPSHZrrik_Int:
165 case X86::VCMPPHZ128rmbi: case X86::VCMPPHZ128rmbik:
166 case X86::VCMPPHZ256rmbi: case X86::VCMPPHZ256rmbik:
167 case X86::VCMPPHZrmbi: case X86::VCMPPHZrmbik:
168 case X86::VCMPPHZrrib: case X86::VCMPPHZrribk:
169 case X86::VCMPSHZrrib_Int: case X86::VCMPSHZrribk_Int:
170 case X86::VCMPBF16Z128rmi: case X86::VCMPBF16Z128rri:
171 case X86::VCMPBF16Z256rmi: case X86::VCMPBF16Z256rri:
172 case X86::VCMPBF16Zrmi: case X86::VCMPBF16Zrri:
173 case X86::VCMPBF16Z128rmik: case X86::VCMPBF16Z128rrik:
174 case X86::VCMPBF16Z256rmik: case X86::VCMPBF16Z256rrik:
175 case X86::VCMPBF16Zrmik: case X86::VCMPBF16Zrrik:
176 case X86::VCMPBF16Z128rmbi: case X86::VCMPBF16Z128rmbik:
177 case X86::VCMPBF16Z256rmbi: case X86::VCMPBF16Z256rmbik:
178 case X86::VCMPBF16Zrmbi: case X86::VCMPBF16Zrmbik:
179 if (Imm >= 0 && Imm <= 31) {
180 OS << '\t';
181 printCMPMnemonic(MI, /*IsVCMP*/IsVCmp: true, OS);
182
183 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
184
185 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
186 if (Desc.TSFlags & X86II::EVEX_B) {
187 // Broadcast form.
188 // Load size is word for TA map. Otherwise it is based on W-bit.
189 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) {
190 assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!");
191 printwordmem(MI, OpNo: CurOp--, O&: OS);
192 } else if (Desc.TSFlags & X86II::REX_W) {
193 printqwordmem(MI, OpNo: CurOp--, O&: OS);
194 } else {
195 printdwordmem(MI, OpNo: CurOp--, O&: OS);
196 }
197
198 // Print the number of elements broadcasted.
199 unsigned NumElts;
200 if (Desc.TSFlags & X86II::EVEX_L2)
201 NumElts = (Desc.TSFlags & X86II::REX_W) ? 8 : 16;
202 else if (Desc.TSFlags & X86II::VEX_L)
203 NumElts = (Desc.TSFlags & X86II::REX_W) ? 4 : 8;
204 else
205 NumElts = (Desc.TSFlags & X86II::REX_W) ? 2 : 4;
206 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) {
207 assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!");
208 NumElts *= 2;
209 }
210 OS << "{1to" << NumElts << "}";
211 } else {
212 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) {
213 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA)
214 printwordmem(MI, OpNo: CurOp--, O&: OS);
215 else
216 printdwordmem(MI, OpNo: CurOp--, O&: OS);
217 } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD &&
218 (Desc.TSFlags & X86II::OpMapMask) != X86II::TA) {
219 printqwordmem(MI, OpNo: CurOp--, O&: OS);
220 } else if (Desc.TSFlags & X86II::EVEX_L2) {
221 printzmmwordmem(MI, OpNo: CurOp--, O&: OS);
222 } else if (Desc.TSFlags & X86II::VEX_L) {
223 printymmwordmem(MI, OpNo: CurOp--, O&: OS);
224 } else {
225 printxmmwordmem(MI, OpNo: CurOp--, O&: OS);
226 }
227 }
228 } else {
229 if (Desc.TSFlags & X86II::EVEX_B)
230 OS << "{sae}, ";
231 printOperand(MI, OpNo: CurOp--, OS);
232 }
233
234 OS << ", ";
235 printOperand(MI, OpNo: CurOp--, OS);
236 OS << ", ";
237 printOperand(MI, OpNo: 0, OS);
238 if (CurOp > 0) {
239 // Print mask operand.
240 OS << " {";
241 printOperand(MI, OpNo: CurOp--, OS);
242 OS << "}";
243 }
244
245 return true;
246 }
247 break;
248
249 case X86::VPCOMBmi: case X86::VPCOMBri:
250 case X86::VPCOMDmi: case X86::VPCOMDri:
251 case X86::VPCOMQmi: case X86::VPCOMQri:
252 case X86::VPCOMUBmi: case X86::VPCOMUBri:
253 case X86::VPCOMUDmi: case X86::VPCOMUDri:
254 case X86::VPCOMUQmi: case X86::VPCOMUQri:
255 case X86::VPCOMUWmi: case X86::VPCOMUWri:
256 case X86::VPCOMWmi: case X86::VPCOMWri:
257 if (Imm >= 0 && Imm <= 7) {
258 OS << '\t';
259 printVPCOMMnemonic(MI, OS);
260
261 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem)
262 printxmmwordmem(MI, OpNo: 2, O&: OS);
263 else
264 printOperand(MI, OpNo: 2, OS);
265
266 OS << ", ";
267 printOperand(MI, OpNo: 1, OS);
268 OS << ", ";
269 printOperand(MI, OpNo: 0, OS);
270 return true;
271 }
272 break;
273
274 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri:
275 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri:
276 case X86::VPCMPBZrmi: case X86::VPCMPBZrri:
277 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri:
278 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri:
279 case X86::VPCMPDZrmi: case X86::VPCMPDZrri:
280 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri:
281 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri:
282 case X86::VPCMPQZrmi: case X86::VPCMPQZrri:
283 case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri:
284 case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri:
285 case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri:
286 case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri:
287 case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri:
288 case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri:
289 case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri:
290 case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri:
291 case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri:
292 case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri:
293 case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri:
294 case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri:
295 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri:
296 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri:
297 case X86::VPCMPWZrmi: case X86::VPCMPWZrri:
298 case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik:
299 case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik:
300 case X86::VPCMPBZrmik: case X86::VPCMPBZrrik:
301 case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik:
302 case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik:
303 case X86::VPCMPDZrmik: case X86::VPCMPDZrrik:
304 case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik:
305 case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik:
306 case X86::VPCMPQZrmik: case X86::VPCMPQZrrik:
307 case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
308 case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
309 case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik:
310 case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
311 case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
312 case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik:
313 case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
314 case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
315 case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik:
316 case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
317 case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik:
318 case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik:
319 case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik:
320 case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik:
321 case X86::VPCMPWZrmik: case X86::VPCMPWZrrik:
322 case X86::VPCMPDZ128rmbi: case X86::VPCMPDZ128rmbik:
323 case X86::VPCMPDZ256rmbi: case X86::VPCMPDZ256rmbik:
324 case X86::VPCMPDZrmbi: case X86::VPCMPDZrmbik:
325 case X86::VPCMPQZ128rmbi: case X86::VPCMPQZ128rmbik:
326 case X86::VPCMPQZ256rmbi: case X86::VPCMPQZ256rmbik:
327 case X86::VPCMPQZrmbi: case X86::VPCMPQZrmbik:
328 case X86::VPCMPUDZ128rmbi: case X86::VPCMPUDZ128rmbik:
329 case X86::VPCMPUDZ256rmbi: case X86::VPCMPUDZ256rmbik:
330 case X86::VPCMPUDZrmbi: case X86::VPCMPUDZrmbik:
331 case X86::VPCMPUQZ128rmbi: case X86::VPCMPUQZ128rmbik:
332 case X86::VPCMPUQZ256rmbi: case X86::VPCMPUQZ256rmbik:
333 case X86::VPCMPUQZrmbi: case X86::VPCMPUQZrmbik:
334 if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) {
335 OS << '\t';
336 printVPCMPMnemonic(MI, OS);
337
338 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
339
340 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
341 if (Desc.TSFlags & X86II::EVEX_B) {
342 // Broadcast form.
343 // Load size is based on W-bit as only D and Q are supported.
344 if (Desc.TSFlags & X86II::REX_W)
345 printqwordmem(MI, OpNo: CurOp--, O&: OS);
346 else
347 printdwordmem(MI, OpNo: CurOp--, O&: OS);
348
349 // Print the number of elements broadcasted.
350 unsigned NumElts;
351 if (Desc.TSFlags & X86II::EVEX_L2)
352 NumElts = (Desc.TSFlags & X86II::REX_W) ? 8 : 16;
353 else if (Desc.TSFlags & X86II::VEX_L)
354 NumElts = (Desc.TSFlags & X86II::REX_W) ? 4 : 8;
355 else
356 NumElts = (Desc.TSFlags & X86II::REX_W) ? 2 : 4;
357 OS << "{1to" << NumElts << "}";
358 } else {
359 if (Desc.TSFlags & X86II::EVEX_L2)
360 printzmmwordmem(MI, OpNo: CurOp--, O&: OS);
361 else if (Desc.TSFlags & X86II::VEX_L)
362 printymmwordmem(MI, OpNo: CurOp--, O&: OS);
363 else
364 printxmmwordmem(MI, OpNo: CurOp--, O&: OS);
365 }
366 } else {
367 printOperand(MI, OpNo: CurOp--, OS);
368 }
369
370 OS << ", ";
371 printOperand(MI, OpNo: CurOp--, OS);
372 OS << ", ";
373 printOperand(MI, OpNo: 0, OS);
374 if (CurOp > 0) {
375 // Print mask operand.
376 OS << " {";
377 printOperand(MI, OpNo: CurOp--, OS);
378 OS << "}";
379 }
380
381 return true;
382 }
383 break;
384 }
385
386 return false;
387}
388
389void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
390 raw_ostream &O) {
391 const MCOperand &Op = MI->getOperand(i: OpNo);
392 if (Op.isReg()) {
393 printRegName(OS&: O, Reg: Op.getReg());
394 } else if (Op.isImm()) {
395 // Print immediates as signed values.
396 int64_t Imm = Op.getImm();
397 markup(OS&: O, M: Markup::Immediate) << '$' << formatImm(Value: Imm);
398
399 // TODO: This should be in a helper function in the base class, so it can
400 // be used by other printers.
401
402 // If there are no instruction-specific comments, add a comment clarifying
403 // the hex value of the immediate operand when it isn't in the range
404 // [-256,255].
405 if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
406 // Don't print unnecessary hex sign bits.
407 if (Imm == (int16_t)(Imm))
408 *CommentStream << format(Fmt: "imm = 0x%" PRIX16 "\n", Vals: (uint16_t)Imm);
409 else if (Imm == (int32_t)(Imm))
410 *CommentStream << format(Fmt: "imm = 0x%" PRIX32 "\n", Vals: (uint32_t)Imm);
411 else
412 *CommentStream << format(Fmt: "imm = 0x%" PRIX64 "\n", Vals: (uint64_t)Imm);
413 }
414 } else {
415 assert(Op.isExpr() && "unknown operand kind in printOperand");
416 WithMarkup M = markup(OS&: O, M: Markup::Immediate);
417 O << '$';
418 MAI.printExpr(O, *Op.getExpr());
419 }
420}
421
422void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
423 raw_ostream &O) {
424 // Do not print the exact form of the memory operand if it references a known
425 // binary object.
426 if (SymbolizeOperands && MIA) {
427 uint64_t Target;
428 if (MIA->evaluateBranch(Inst: *MI, Addr: 0, Size: 0, Target))
429 return;
430 if (MIA->evaluateMemoryOperandAddress(Inst: *MI, /*STI=*/nullptr, Addr: 0, Size: 0))
431 return;
432 }
433
434 const MCOperand &BaseReg = MI->getOperand(i: Op + X86::AddrBaseReg);
435 const MCOperand &IndexReg = MI->getOperand(i: Op + X86::AddrIndexReg);
436 const MCOperand &DispSpec = MI->getOperand(i: Op + X86::AddrDisp);
437
438 WithMarkup M = markup(OS&: O, M: Markup::Memory);
439
440 // If this has a segment register, print it.
441 printOptionalSegReg(MI, OpNo: Op + X86::AddrSegmentReg, O);
442
443 if (DispSpec.isImm()) {
444 int64_t DispVal = DispSpec.getImm();
445 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
446 O << formatImm(Value: DispVal);
447 } else {
448 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
449 MAI.printExpr(O, *DispSpec.getExpr());
450 }
451
452 if (IndexReg.getReg() || BaseReg.getReg()) {
453 O << '(';
454 if (BaseReg.getReg())
455 printOperand(MI, OpNo: Op + X86::AddrBaseReg, O);
456
457 if (IndexReg.getReg()) {
458 O << ',';
459 printOperand(MI, OpNo: Op + X86::AddrIndexReg, O);
460 unsigned ScaleVal = MI->getOperand(i: Op + X86::AddrScaleAmt).getImm();
461 if (ScaleVal != 1) {
462 O << ',';
463 markup(OS&: O, M: Markup::Immediate) << ScaleVal; // never printed in hex.
464 }
465 }
466 O << ')';
467 }
468}
469
470void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
471 raw_ostream &O) {
472 WithMarkup M = markup(OS&: O, M: Markup::Memory);
473
474 // If this has a segment register, print it.
475 printOptionalSegReg(MI, OpNo: Op + 1, O);
476
477 O << "(";
478 printOperand(MI, OpNo: Op, O);
479 O << ")";
480}
481
482void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
483 raw_ostream &O) {
484 WithMarkup M = markup(OS&: O, M: Markup::Memory);
485
486 O << "%es:(";
487 printOperand(MI, OpNo: Op, O);
488 O << ")";
489}
490
491void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
492 raw_ostream &O) {
493 const MCOperand &DispSpec = MI->getOperand(i: Op);
494
495 WithMarkup M = markup(OS&: O, M: Markup::Memory);
496
497 // If this has a segment register, print it.
498 printOptionalSegReg(MI, OpNo: Op + 1, O);
499
500 if (DispSpec.isImm()) {
501 O << formatImm(Value: DispSpec.getImm());
502 } else {
503 assert(DispSpec.isExpr() && "non-immediate displacement?");
504 MAI.printExpr(O, *DispSpec.getExpr());
505 }
506}
507
508void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
509 raw_ostream &O) {
510 if (MI->getOperand(i: Op).isExpr())
511 return printOperand(MI, OpNo: Op, O);
512
513 markup(OS&: O, M: Markup::Immediate)
514 << '$' << formatImm(Value: MI->getOperand(i: Op).getImm() & 0xff);
515}
516
517void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
518 raw_ostream &OS) {
519 MCRegister Reg = MI->getOperand(i: OpNo).getReg();
520 // Override the default printing to print st(0) instead st.
521 if (Reg == X86::ST0)
522 markup(OS, M: Markup::Register) << "%st(0)";
523 else
524 printRegName(OS, Reg);
525}
526