1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Sparc.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10/// getMnemonic - This method is automatically generated by tablegen
11/// from the instruction set description.
12std::pair<const char *, uint64_t> SparcInstPrinter::getMnemonic(const MCInst *MI) {
13
14#ifdef __GNUC__
15#pragma GCC diagnostic push
16#pragma GCC diagnostic ignored "-Woverlength-strings"
17#endif
18 static const char AsmStrs[] = {
19 /* 0 */ "fcmpd %fcc0, \0"
20 /* 14 */ "fcmpq %fcc0, \0"
21 /* 28 */ "fcmps %fcc0, \0"
22 /* 42 */ "rd %wim, \0"
23 /* 52 */ "rdpr %fq, \0"
24 /* 63 */ "rd %tbr, \0"
25 /* 73 */ "rd %psr, \0"
26 /* 83 */ "fsrc1 \0"
27 /* 90 */ "fandnot1 \0"
28 /* 100 */ "fnot1 \0"
29 /* 107 */ "fornot1 \0"
30 /* 116 */ "fsra32 \0"
31 /* 124 */ "fpsub32 \0"
32 /* 133 */ "fpadd32 \0"
33 /* 142 */ "edge32 \0"
34 /* 150 */ "fcmple32 \0"
35 /* 160 */ "fcmpne32 \0"
36 /* 170 */ "fpack32 \0"
37 /* 179 */ "cmask32 \0"
38 /* 188 */ "fsll32 \0"
39 /* 196 */ "fsrl32 \0"
40 /* 204 */ "fcmpeq32 \0"
41 /* 214 */ "fslas32 \0"
42 /* 223 */ "fcmpgt32 \0"
43 /* 233 */ "array32 \0"
44 /* 242 */ "fsrc2 \0"
45 /* 249 */ "fandnot2 \0"
46 /* 259 */ "fnot2 \0"
47 /* 266 */ "fornot2 \0"
48 /* 275 */ "fpadd64 \0"
49 /* 284 */ "fsra16 \0"
50 /* 292 */ "fpsub16 \0"
51 /* 301 */ "fpadd16 \0"
52 /* 310 */ "edge16 \0"
53 /* 318 */ "fcmple16 \0"
54 /* 328 */ "fcmpne16 \0"
55 /* 338 */ "fpack16 \0"
56 /* 347 */ "cmask16 \0"
57 /* 356 */ "fsll16 \0"
58 /* 364 */ "fsrl16 \0"
59 /* 372 */ "fchksm16 \0"
60 /* 382 */ "fmean16 \0"
61 /* 391 */ "fcmpeq16 \0"
62 /* 401 */ "fslas16 \0"
63 /* 410 */ "fcmpgt16 \0"
64 /* 420 */ "fmul8x16 \0"
65 /* 430 */ "fmuld8ulx16 \0"
66 /* 443 */ "fmul8ulx16 \0"
67 /* 455 */ "fmuld8sux16 \0"
68 /* 468 */ "fmul8sux16 \0"
69 /* 480 */ "array16 \0"
70 /* 489 */ "edge8 \0"
71 /* 496 */ "cmask8 \0"
72 /* 504 */ "array8 \0"
73 /* 512 */ "!ADJCALLSTACKDOWN \0"
74 /* 531 */ "!ADJCALLSTACKUP \0"
75 /* 548 */ "fpsub32S \0"
76 /* 558 */ "fpsub16S \0"
77 /* 568 */ "stba \0"
78 /* 574 */ "stda \0"
79 /* 580 */ "stha \0"
80 /* 586 */ "stqa \0"
81 /* 592 */ "sra \0"
82 /* 597 */ "faligndata \0"
83 /* 609 */ "sta \0"
84 /* 614 */ "stxa \0"
85 /* 620 */ "stb \0"
86 /* 625 */ "sub \0"
87 /* 630 */ "smac \0"
88 /* 636 */ "umac \0"
89 /* 642 */ "tsubcc \0"
90 /* 650 */ "addxccc \0"
91 /* 659 */ "taddcc \0"
92 /* 667 */ "andcc \0"
93 /* 674 */ "smulcc \0"
94 /* 682 */ "umulcc \0"
95 /* 690 */ "andncc \0"
96 /* 698 */ "orncc \0"
97 /* 705 */ "xnorcc \0"
98 /* 713 */ "xorcc \0"
99 /* 720 */ "mulscc \0"
100 /* 728 */ "sdivcc \0"
101 /* 736 */ "udivcc \0"
102 /* 744 */ "subxcc \0"
103 /* 752 */ "addxcc \0"
104 /* 760 */ "popc \0"
105 /* 766 */ "addxc \0"
106 /* 773 */ "fsubd \0"
107 /* 780 */ "fhsubd \0"
108 /* 788 */ "add \0"
109 /* 793 */ "faddd \0"
110 /* 800 */ "fhaddd \0"
111 /* 808 */ "fnhaddd \0"
112 /* 817 */ "fnaddd \0"
113 /* 825 */ "fcmped \0"
114 /* 833 */ "fnegd \0"
115 /* 840 */ "fmuld \0"
116 /* 847 */ "fsmuld \0"
117 /* 855 */ "fand \0"
118 /* 861 */ "fnand \0"
119 /* 868 */ "fexpand \0"
120 /* 877 */ "fitod \0"
121 /* 884 */ "fqtod \0"
122 /* 891 */ "fstod \0"
123 /* 898 */ "fxtod \0"
124 /* 905 */ "fcmpd \0"
125 /* 912 */ "flcmpd \0"
126 /* 920 */ "rd \0"
127 /* 924 */ "fabsd \0"
128 /* 931 */ "fsqrtd \0"
129 /* 939 */ "std \0"
130 /* 944 */ "fdivd \0"
131 /* 951 */ "fmovd \0"
132 /* 958 */ "fpmerge \0"
133 /* 967 */ "bshuffle \0"
134 /* 977 */ "fone \0"
135 /* 983 */ "restore \0"
136 /* 992 */ "save \0"
137 /* 998 */ "flush \0"
138 /* 1005 */ "sth \0"
139 /* 1010 */ "sethi \0"
140 /* 1017 */ "umulxhi \0"
141 /* 1026 */ "xmulxhi \0"
142 /* 1035 */ "fdtoi \0"
143 /* 1042 */ "fqtoi \0"
144 /* 1049 */ "fstoi \0"
145 /* 1056 */ "bmask \0"
146 /* 1063 */ "edge32l \0"
147 /* 1072 */ "edge16l \0"
148 /* 1081 */ "edge8l \0"
149 /* 1089 */ "fmul8x16al \0"
150 /* 1101 */ "call \0"
151 /* 1107 */ "sll \0"
152 /* 1112 */ "jmpl \0"
153 /* 1118 */ "alignaddrl \0"
154 /* 1130 */ "srl \0"
155 /* 1135 */ "smul \0"
156 /* 1141 */ "umul \0"
157 /* 1147 */ "edge32n \0"
158 /* 1156 */ "edge16n \0"
159 /* 1165 */ "edge8n \0"
160 /* 1173 */ "andn \0"
161 /* 1179 */ "edge32ln \0"
162 /* 1189 */ "edge16ln \0"
163 /* 1199 */ "edge8ln \0"
164 /* 1208 */ "orn \0"
165 /* 1213 */ "pdistn \0"
166 /* 1221 */ "fzero \0"
167 /* 1228 */ "unimp \0"
168 /* 1235 */ "jmp \0"
169 /* 1240 */ "fsubq \0"
170 /* 1247 */ "faddq \0"
171 /* 1254 */ "fcmpeq \0"
172 /* 1262 */ "fnegq \0"
173 /* 1269 */ "fdmulq \0"
174 /* 1277 */ "fmulq \0"
175 /* 1284 */ "fdtoq \0"
176 /* 1291 */ "fitoq \0"
177 /* 1298 */ "fstoq \0"
178 /* 1305 */ "fxtoq \0"
179 /* 1312 */ "fcmpq \0"
180 /* 1319 */ "fabsq \0"
181 /* 1326 */ "fsqrtq \0"
182 /* 1334 */ "stq \0"
183 /* 1339 */ "fdivq \0"
184 /* 1346 */ "fmovq \0"
185 /* 1353 */ "membar \0"
186 /* 1361 */ "alignaddr \0"
187 /* 1372 */ "sir \0"
188 /* 1377 */ "for \0"
189 /* 1382 */ "fnor \0"
190 /* 1388 */ "fxnor \0"
191 /* 1395 */ "fxor \0"
192 /* 1401 */ "rdpr \0"
193 /* 1407 */ "wrpr \0"
194 /* 1413 */ "pwr \0"
195 /* 1418 */ "fsrc1s \0"
196 /* 1426 */ "fandnot1s \0"
197 /* 1437 */ "fnot1s \0"
198 /* 1445 */ "fornot1s \0"
199 /* 1455 */ "fpadd32s \0"
200 /* 1465 */ "fsrc2s \0"
201 /* 1473 */ "fandnot2s \0"
202 /* 1484 */ "fnot2s \0"
203 /* 1492 */ "fornot2s \0"
204 /* 1502 */ "fpadd16s \0"
205 /* 1512 */ "fsubs \0"
206 /* 1519 */ "fhsubs \0"
207 /* 1527 */ "fadds \0"
208 /* 1534 */ "fhadds \0"
209 /* 1542 */ "fnhadds \0"
210 /* 1551 */ "fnadds \0"
211 /* 1559 */ "fands \0"
212 /* 1566 */ "fnands \0"
213 /* 1574 */ "fones \0"
214 /* 1581 */ "fcmpes \0"
215 /* 1589 */ "fnegs \0"
216 /* 1596 */ "fmuls \0"
217 /* 1603 */ "fzeros \0"
218 /* 1611 */ "fdtos \0"
219 /* 1618 */ "fitos \0"
220 /* 1625 */ "fqtos \0"
221 /* 1632 */ "fxtos \0"
222 /* 1639 */ "fcmps \0"
223 /* 1646 */ "flcmps \0"
224 /* 1654 */ "fors \0"
225 /* 1660 */ "fnors \0"
226 /* 1667 */ "fxnors \0"
227 /* 1675 */ "fxors \0"
228 /* 1682 */ "fabss \0"
229 /* 1689 */ "fsqrts \0"
230 /* 1697 */ "fdivs \0"
231 /* 1704 */ "fmovs \0"
232 /* 1711 */ "set \0"
233 /* 1716 */ "lzcnt \0"
234 /* 1723 */ "pdist \0"
235 /* 1730 */ "rett \0"
236 /* 1736 */ "fmul8x16au \0"
237 /* 1748 */ "sdiv \0"
238 /* 1754 */ "udiv \0"
239 /* 1760 */ "tsubcctv \0"
240 /* 1770 */ "taddcctv \0"
241 /* 1780 */ "movstosw \0"
242 /* 1790 */ "movstouw \0"
243 /* 1800 */ "srax \0"
244 /* 1806 */ "subx \0"
245 /* 1812 */ "addx \0"
246 /* 1818 */ "fpackfix \0"
247 /* 1828 */ "sllx \0"
248 /* 1834 */ "srlx \0"
249 /* 1840 */ "xmulx \0"
250 /* 1847 */ "fdtox \0"
251 /* 1854 */ "movdtox \0"
252 /* 1863 */ "fqtox \0"
253 /* 1870 */ "fstox \0"
254 /* 1877 */ "setx \0"
255 /* 1883 */ "stx \0"
256 /* 1888 */ "sdivx \0"
257 /* 1895 */ "udivx \0"
258 /* 1902 */ "; SELECT_CC_DFP_FCC PSEUDO!\0"
259 /* 1930 */ "; SELECT_CC_QFP_FCC PSEUDO!\0"
260 /* 1958 */ "; SELECT_CC_FP_FCC PSEUDO!\0"
261 /* 1985 */ "; SELECT_CC_Int_FCC PSEUDO!\0"
262 /* 2013 */ "; SELECT_CC_DFP_ICC PSEUDO!\0"
263 /* 2041 */ "; SELECT_CC_QFP_ICC PSEUDO!\0"
264 /* 2069 */ "; SELECT_CC_FP_ICC PSEUDO!\0"
265 /* 2096 */ "; SELECT_CC_Int_ICC PSEUDO!\0"
266 /* 2124 */ "; SELECT_CC_DFP_XCC PSEUDO!\0"
267 /* 2152 */ "; SELECT_CC_QFP_XCC PSEUDO!\0"
268 /* 2180 */ "; SELECT_CC_FP_XCC PSEUDO!\0"
269 /* 2207 */ "; SELECT_CC_Int_XCC PSEUDO!\0"
270 /* 2235 */ "jmp %i7+\0"
271 /* 2244 */ "jmp %o7+\0"
272 /* 2253 */ "# XRay Function Patchable RET.\0"
273 /* 2284 */ "# XRay Typed Event Log.\0"
274 /* 2308 */ "# XRay Custom Event Log.\0"
275 /* 2333 */ "# XRay Function Enter.\0"
276 /* 2356 */ "# XRay Tail Call Exit.\0"
277 /* 2379 */ "# XRay Function Exit.\0"
278 /* 2401 */ "flush %g0\0"
279 /* 2411 */ "ta 1\0"
280 /* 2416 */ "ta 3\0"
281 /* 2421 */ "ta 5\0"
282 /* 2426 */ "LIFETIME_END\0"
283 /* 2439 */ "PSEUDO_PROBE\0"
284 /* 2452 */ "BUNDLE\0"
285 /* 2459 */ "DBG_VALUE\0"
286 /* 2469 */ "DBG_INSTR_REF\0"
287 /* 2483 */ "DBG_PHI\0"
288 /* 2491 */ "DBG_LABEL\0"
289 /* 2501 */ "LIFETIME_START\0"
290 /* 2516 */ "DBG_VALUE_LIST\0"
291 /* 2531 */ "std %cq, [\0"
292 /* 2542 */ "std %fq, [\0"
293 /* 2553 */ "st %csr, [\0"
294 /* 2564 */ "st %fsr, [\0"
295 /* 2575 */ "stx %fsr, [\0"
296 /* 2587 */ "ldsba [\0"
297 /* 2595 */ "lduba [\0"
298 /* 2603 */ "ldstuba [\0"
299 /* 2613 */ "ldda [\0"
300 /* 2620 */ "lda [\0"
301 /* 2626 */ "prefetcha [\0"
302 /* 2638 */ "ldsha [\0"
303 /* 2646 */ "lduha [\0"
304 /* 2654 */ "swapa [\0"
305 /* 2662 */ "ldqa [\0"
306 /* 2669 */ "casa [\0"
307 /* 2676 */ "ldswa [\0"
308 /* 2684 */ "ldxa [\0"
309 /* 2691 */ "casxa [\0"
310 /* 2699 */ "ldsb [\0"
311 /* 2706 */ "ldub [\0"
312 /* 2713 */ "ldstub [\0"
313 /* 2722 */ "ldd [\0"
314 /* 2728 */ "ld [\0"
315 /* 2733 */ "prefetch [\0"
316 /* 2744 */ "ldsh [\0"
317 /* 2751 */ "lduh [\0"
318 /* 2758 */ "swap [\0"
319 /* 2765 */ "ldq [\0"
320 /* 2771 */ "ldsw [\0"
321 /* 2778 */ "ldx [\0"
322 /* 2784 */ "cb\0"
323 /* 2787 */ "fb\0"
324 /* 2790 */ "restored\0"
325 /* 2799 */ "saved\0"
326 /* 2805 */ "fmovrd\0"
327 /* 2812 */ "fmovd\0"
328 /* 2818 */ "done\0"
329 /* 2823 */ "# FEntry call\0"
330 /* 2837 */ "siam\0"
331 /* 2842 */ "shutdown\0"
332 /* 2851 */ "nop\0"
333 /* 2855 */ "fmovrq\0"
334 /* 2862 */ "fmovq\0"
335 /* 2868 */ "stbar\0"
336 /* 2874 */ "br\0"
337 /* 2877 */ "movr\0"
338 /* 2882 */ "fmovrs\0"
339 /* 2889 */ "fmovs\0"
340 /* 2895 */ "t\0"
341 /* 2897 */ "mov\0"
342 /* 2901 */ "flushw\0"
343 /* 2908 */ "retry\0"
344};
345#ifdef __GNUC__
346#pragma GCC diagnostic pop
347#endif
348
349 static const uint32_t OpInfo0[] = {
350 0U, // PHI
351 0U, // INLINEASM
352 0U, // INLINEASM_BR
353 0U, // CFI_INSTRUCTION
354 0U, // EH_LABEL
355 0U, // GC_LABEL
356 0U, // ANNOTATION_LABEL
357 0U, // KILL
358 0U, // EXTRACT_SUBREG
359 0U, // INSERT_SUBREG
360 0U, // IMPLICIT_DEF
361 0U, // SUBREG_TO_REG
362 0U, // COPY_TO_REGCLASS
363 2460U, // DBG_VALUE
364 2517U, // DBG_VALUE_LIST
365 2470U, // DBG_INSTR_REF
366 2484U, // DBG_PHI
367 2492U, // DBG_LABEL
368 0U, // REG_SEQUENCE
369 0U, // COPY
370 2453U, // BUNDLE
371 2502U, // LIFETIME_START
372 2427U, // LIFETIME_END
373 2440U, // PSEUDO_PROBE
374 0U, // ARITH_FENCE
375 0U, // STACKMAP
376 2824U, // FENTRY_CALL
377 0U, // PATCHPOINT
378 0U, // LOAD_STACK_GUARD
379 0U, // PREALLOCATED_SETUP
380 0U, // PREALLOCATED_ARG
381 0U, // STATEPOINT
382 0U, // LOCAL_ESCAPE
383 0U, // FAULTING_OP
384 0U, // PATCHABLE_OP
385 2334U, // PATCHABLE_FUNCTION_ENTER
386 2254U, // PATCHABLE_RET
387 2380U, // PATCHABLE_FUNCTION_EXIT
388 2357U, // PATCHABLE_TAIL_CALL
389 2309U, // PATCHABLE_EVENT_CALL
390 2285U, // PATCHABLE_TYPED_EVENT_CALL
391 0U, // ICALL_BRANCH_FUNNEL
392 0U, // MEMBARRIER
393 0U, // JUMP_TABLE_DEBUG_INFO
394 0U, // CONVERGENCECTRL_ENTRY
395 0U, // CONVERGENCECTRL_ANCHOR
396 0U, // CONVERGENCECTRL_LOOP
397 0U, // CONVERGENCECTRL_GLUE
398 0U, // G_ASSERT_SEXT
399 0U, // G_ASSERT_ZEXT
400 0U, // G_ASSERT_ALIGN
401 0U, // G_ADD
402 0U, // G_SUB
403 0U, // G_MUL
404 0U, // G_SDIV
405 0U, // G_UDIV
406 0U, // G_SREM
407 0U, // G_UREM
408 0U, // G_SDIVREM
409 0U, // G_UDIVREM
410 0U, // G_AND
411 0U, // G_OR
412 0U, // G_XOR
413 0U, // G_IMPLICIT_DEF
414 0U, // G_PHI
415 0U, // G_FRAME_INDEX
416 0U, // G_GLOBAL_VALUE
417 0U, // G_PTRAUTH_GLOBAL_VALUE
418 0U, // G_CONSTANT_POOL
419 0U, // G_EXTRACT
420 0U, // G_UNMERGE_VALUES
421 0U, // G_INSERT
422 0U, // G_MERGE_VALUES
423 0U, // G_BUILD_VECTOR
424 0U, // G_BUILD_VECTOR_TRUNC
425 0U, // G_CONCAT_VECTORS
426 0U, // G_PTRTOINT
427 0U, // G_INTTOPTR
428 0U, // G_BITCAST
429 0U, // G_FREEZE
430 0U, // G_CONSTANT_FOLD_BARRIER
431 0U, // G_INTRINSIC_FPTRUNC_ROUND
432 0U, // G_INTRINSIC_TRUNC
433 0U, // G_INTRINSIC_ROUND
434 0U, // G_INTRINSIC_LRINT
435 0U, // G_INTRINSIC_LLRINT
436 0U, // G_INTRINSIC_ROUNDEVEN
437 0U, // G_READCYCLECOUNTER
438 0U, // G_READSTEADYCOUNTER
439 0U, // G_LOAD
440 0U, // G_SEXTLOAD
441 0U, // G_ZEXTLOAD
442 0U, // G_INDEXED_LOAD
443 0U, // G_INDEXED_SEXTLOAD
444 0U, // G_INDEXED_ZEXTLOAD
445 0U, // G_STORE
446 0U, // G_INDEXED_STORE
447 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
448 0U, // G_ATOMIC_CMPXCHG
449 0U, // G_ATOMICRMW_XCHG
450 0U, // G_ATOMICRMW_ADD
451 0U, // G_ATOMICRMW_SUB
452 0U, // G_ATOMICRMW_AND
453 0U, // G_ATOMICRMW_NAND
454 0U, // G_ATOMICRMW_OR
455 0U, // G_ATOMICRMW_XOR
456 0U, // G_ATOMICRMW_MAX
457 0U, // G_ATOMICRMW_MIN
458 0U, // G_ATOMICRMW_UMAX
459 0U, // G_ATOMICRMW_UMIN
460 0U, // G_ATOMICRMW_FADD
461 0U, // G_ATOMICRMW_FSUB
462 0U, // G_ATOMICRMW_FMAX
463 0U, // G_ATOMICRMW_FMIN
464 0U, // G_ATOMICRMW_UINC_WRAP
465 0U, // G_ATOMICRMW_UDEC_WRAP
466 0U, // G_FENCE
467 0U, // G_PREFETCH
468 0U, // G_BRCOND
469 0U, // G_BRINDIRECT
470 0U, // G_INVOKE_REGION_START
471 0U, // G_INTRINSIC
472 0U, // G_INTRINSIC_W_SIDE_EFFECTS
473 0U, // G_INTRINSIC_CONVERGENT
474 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
475 0U, // G_ANYEXT
476 0U, // G_TRUNC
477 0U, // G_CONSTANT
478 0U, // G_FCONSTANT
479 0U, // G_VASTART
480 0U, // G_VAARG
481 0U, // G_SEXT
482 0U, // G_SEXT_INREG
483 0U, // G_ZEXT
484 0U, // G_SHL
485 0U, // G_LSHR
486 0U, // G_ASHR
487 0U, // G_FSHL
488 0U, // G_FSHR
489 0U, // G_ROTR
490 0U, // G_ROTL
491 0U, // G_ICMP
492 0U, // G_FCMP
493 0U, // G_SCMP
494 0U, // G_UCMP
495 0U, // G_SELECT
496 0U, // G_UADDO
497 0U, // G_UADDE
498 0U, // G_USUBO
499 0U, // G_USUBE
500 0U, // G_SADDO
501 0U, // G_SADDE
502 0U, // G_SSUBO
503 0U, // G_SSUBE
504 0U, // G_UMULO
505 0U, // G_SMULO
506 0U, // G_UMULH
507 0U, // G_SMULH
508 0U, // G_UADDSAT
509 0U, // G_SADDSAT
510 0U, // G_USUBSAT
511 0U, // G_SSUBSAT
512 0U, // G_USHLSAT
513 0U, // G_SSHLSAT
514 0U, // G_SMULFIX
515 0U, // G_UMULFIX
516 0U, // G_SMULFIXSAT
517 0U, // G_UMULFIXSAT
518 0U, // G_SDIVFIX
519 0U, // G_UDIVFIX
520 0U, // G_SDIVFIXSAT
521 0U, // G_UDIVFIXSAT
522 0U, // G_FADD
523 0U, // G_FSUB
524 0U, // G_FMUL
525 0U, // G_FMA
526 0U, // G_FMAD
527 0U, // G_FDIV
528 0U, // G_FREM
529 0U, // G_FPOW
530 0U, // G_FPOWI
531 0U, // G_FEXP
532 0U, // G_FEXP2
533 0U, // G_FEXP10
534 0U, // G_FLOG
535 0U, // G_FLOG2
536 0U, // G_FLOG10
537 0U, // G_FLDEXP
538 0U, // G_FFREXP
539 0U, // G_FNEG
540 0U, // G_FPEXT
541 0U, // G_FPTRUNC
542 0U, // G_FPTOSI
543 0U, // G_FPTOUI
544 0U, // G_SITOFP
545 0U, // G_UITOFP
546 0U, // G_FABS
547 0U, // G_FCOPYSIGN
548 0U, // G_IS_FPCLASS
549 0U, // G_FCANONICALIZE
550 0U, // G_FMINNUM
551 0U, // G_FMAXNUM
552 0U, // G_FMINNUM_IEEE
553 0U, // G_FMAXNUM_IEEE
554 0U, // G_FMINIMUM
555 0U, // G_FMAXIMUM
556 0U, // G_GET_FPENV
557 0U, // G_SET_FPENV
558 0U, // G_RESET_FPENV
559 0U, // G_GET_FPMODE
560 0U, // G_SET_FPMODE
561 0U, // G_RESET_FPMODE
562 0U, // G_PTR_ADD
563 0U, // G_PTRMASK
564 0U, // G_SMIN
565 0U, // G_SMAX
566 0U, // G_UMIN
567 0U, // G_UMAX
568 0U, // G_ABS
569 0U, // G_LROUND
570 0U, // G_LLROUND
571 0U, // G_BR
572 0U, // G_BRJT
573 0U, // G_VSCALE
574 0U, // G_INSERT_SUBVECTOR
575 0U, // G_EXTRACT_SUBVECTOR
576 0U, // G_INSERT_VECTOR_ELT
577 0U, // G_EXTRACT_VECTOR_ELT
578 0U, // G_SHUFFLE_VECTOR
579 0U, // G_SPLAT_VECTOR
580 0U, // G_VECTOR_COMPRESS
581 0U, // G_CTTZ
582 0U, // G_CTTZ_ZERO_UNDEF
583 0U, // G_CTLZ
584 0U, // G_CTLZ_ZERO_UNDEF
585 0U, // G_CTPOP
586 0U, // G_BSWAP
587 0U, // G_BITREVERSE
588 0U, // G_FCEIL
589 0U, // G_FCOS
590 0U, // G_FSIN
591 0U, // G_FTAN
592 0U, // G_FACOS
593 0U, // G_FASIN
594 0U, // G_FATAN
595 0U, // G_FCOSH
596 0U, // G_FSINH
597 0U, // G_FTANH
598 0U, // G_FSQRT
599 0U, // G_FFLOOR
600 0U, // G_FRINT
601 0U, // G_FNEARBYINT
602 0U, // G_ADDRSPACE_CAST
603 0U, // G_BLOCK_ADDR
604 0U, // G_JUMP_TABLE
605 0U, // G_DYN_STACKALLOC
606 0U, // G_STACKSAVE
607 0U, // G_STACKRESTORE
608 0U, // G_STRICT_FADD
609 0U, // G_STRICT_FSUB
610 0U, // G_STRICT_FMUL
611 0U, // G_STRICT_FDIV
612 0U, // G_STRICT_FREM
613 0U, // G_STRICT_FMA
614 0U, // G_STRICT_FSQRT
615 0U, // G_STRICT_FLDEXP
616 0U, // G_READ_REGISTER
617 0U, // G_WRITE_REGISTER
618 0U, // G_MEMCPY
619 0U, // G_MEMCPY_INLINE
620 0U, // G_MEMMOVE
621 0U, // G_MEMSET
622 0U, // G_BZERO
623 0U, // G_TRAP
624 0U, // G_DEBUGTRAP
625 0U, // G_UBSANTRAP
626 0U, // G_VECREDUCE_SEQ_FADD
627 0U, // G_VECREDUCE_SEQ_FMUL
628 0U, // G_VECREDUCE_FADD
629 0U, // G_VECREDUCE_FMUL
630 0U, // G_VECREDUCE_FMAX
631 0U, // G_VECREDUCE_FMIN
632 0U, // G_VECREDUCE_FMAXIMUM
633 0U, // G_VECREDUCE_FMINIMUM
634 0U, // G_VECREDUCE_ADD
635 0U, // G_VECREDUCE_MUL
636 0U, // G_VECREDUCE_AND
637 0U, // G_VECREDUCE_OR
638 0U, // G_VECREDUCE_XOR
639 0U, // G_VECREDUCE_SMAX
640 0U, // G_VECREDUCE_SMIN
641 0U, // G_VECREDUCE_UMAX
642 0U, // G_VECREDUCE_UMIN
643 0U, // G_SBFX
644 0U, // G_UBFX
645 4609U, // ADJCALLSTACKDOWN
646 70164U, // ADJCALLSTACKUP
647 8206U, // GETPCX
648 1903U, // SELECT_CC_DFP_FCC
649 2014U, // SELECT_CC_DFP_ICC
650 2125U, // SELECT_CC_DFP_XCC
651 1959U, // SELECT_CC_FP_FCC
652 2070U, // SELECT_CC_FP_ICC
653 2181U, // SELECT_CC_FP_XCC
654 1986U, // SELECT_CC_Int_FCC
655 2097U, // SELECT_CC_Int_ICC
656 2208U, // SELECT_CC_Int_XCC
657 1931U, // SELECT_CC_QFP_FCC
658 2042U, // SELECT_CC_QFP_ICC
659 2153U, // SELECT_CC_QFP_XCC
660 2111152U, // SET
661 4208470U, // SETX
662 4207253U, // ADDCCri
663 4207253U, // ADDCCrr
664 4208405U, // ADDCri
665 4208405U, // ADDCrr
666 4207345U, // ADDEri
667 4207345U, // ADDErr
668 4207359U, // ADDXC
669 4207243U, // ADDXCCC
670 4207381U, // ADDri
671 4207381U, // ADDrr
672 4207954U, // ALIGNADDR
673 4207711U, // ALIGNADDRL
674 4207260U, // ANDCCri
675 4207260U, // ANDCCrr
676 4207283U, // ANDNCCri
677 4207283U, // ANDNCCrr
678 4207766U, // ANDNri
679 4207766U, // ANDNrr
680 4207449U, // ANDri
681 4207449U, // ANDrr
682 4207073U, // ARRAY16
683 4206826U, // ARRAY32
684 4207097U, // ARRAY8
685 70203U, // BA
686 2247394U, // BCOND
687 2312930U, // BCONDA
688 87252U, // BINDri
689 87252U, // BINDrr
690 4207649U, // BMASK
691 4344548U, // BPFCC
692 4410084U, // BPFCCA
693 281316U, // BPFCCANT
694 346852U, // BPFCCNT
695 2509538U, // BPICC
696 477922U, // BPICCA
697 543458U, // BPICCANT
698 608994U, // BPICCNT
699 4344635U, // BPR
700 4410171U, // BPRA
701 281403U, // BPRANT
702 346939U, // BPRNT
703 2771682U, // BPXCC
704 740066U, // BPXCCA
705 805602U, // BPXCCANT
706 871138U, // BPXCCNT
707 4207560U, // BSHUFFLE
708 70734U, // CALL
709 87118U, // CALLri
710 87118U, // CALLrr
711 5126766U, // CASAri
712 7289454U, // CASArr
713 5126788U, // CASXAri
714 7289476U, // CASXArr
715 2247393U, // CBCOND
716 2312929U, // CBCONDA
717 69980U, // CMASK16
718 69812U, // CMASK32
719 70129U, // CMASK8
720 2819U, // DONE
721 4206903U, // EDGE16
722 4207665U, // EDGE16L
723 4207782U, // EDGE16LN
724 4207749U, // EDGE16N
725 4206735U, // EDGE32
726 4207656U, // EDGE32L
727 4207772U, // EDGE32LN
728 4207740U, // EDGE32N
729 4207082U, // EDGE8
730 4207674U, // EDGE8L
731 4207792U, // EDGE8LN
732 4207758U, // EDGE8N
733 2110365U, // FABSD
734 2110760U, // FABSQ
735 2111123U, // FABSS
736 4207386U, // FADDD
737 4207840U, // FADDQ
738 4208120U, // FADDS
739 4207190U, // FALIGNADATA
740 4207448U, // FAND
741 4206683U, // FANDNOT1
742 4208019U, // FANDNOT1S
743 4206842U, // FANDNOT2
744 4208066U, // FANDNOT2S
745 4208152U, // FANDS
746 2247396U, // FBCOND
747 2312932U, // FBCONDA
748 1067748U, // FBCONDA_V9
749 3230436U, // FBCOND_V9
750 4206965U, // FCHKSM16
751 5002U, // FCMPD
752 4097U, // FCMPD_V9
753 4206984U, // FCMPEQ16
754 4206797U, // FCMPEQ32
755 4207003U, // FCMPGT16
756 4206816U, // FCMPGT32
757 4206911U, // FCMPLE16
758 4206743U, // FCMPLE32
759 4206921U, // FCMPNE16
760 4206753U, // FCMPNE32
761 5409U, // FCMPQ
762 4111U, // FCMPQ_V9
763 5736U, // FCMPS
764 4125U, // FCMPS_V9
765 4207537U, // FDIVD
766 4207932U, // FDIVQ
767 4208290U, // FDIVS
768 4207862U, // FDMULQ
769 2110476U, // FDTOI
770 2110725U, // FDTOQ
771 2111052U, // FDTOS
772 2111288U, // FDTOX
773 2110309U, // FEXPAND
774 4207393U, // FHADDD
775 4208127U, // FHADDS
776 4207373U, // FHSUBD
777 4208112U, // FHSUBS
778 2110318U, // FITOD
779 2110732U, // FITOQ
780 2111059U, // FITOS
781 16782225U, // FLCMPD
782 16782959U, // FLCMPS
783 2402U, // FLUSH
784 2902U, // FLUSHW
785 87015U, // FLUSHri
786 87015U, // FLUSHrr
787 4206975U, // FMEAN16
788 2110392U, // FMOVD
789 152136445U, // FMOVD_FCC
790 151415549U, // FMOVD_ICC
791 151677693U, // FMOVD_XCC
792 2110787U, // FMOVQ
793 152136495U, // FMOVQ_FCC
794 151415599U, // FMOVQ_ICC
795 151677743U, // FMOVQ_XCC
796 31478U, // FMOVRD
797 31528U, // FMOVRQ
798 31555U, // FMOVRS
799 2111145U, // FMOVS
800 152136522U, // FMOVS_FCC
801 151415626U, // FMOVS_ICC
802 151677770U, // FMOVS_XCC
803 4207061U, // FMUL8SUX16
804 4207036U, // FMUL8ULX16
805 4207013U, // FMUL8X16
806 4207682U, // FMUL8X16AL
807 4208329U, // FMUL8X16AU
808 4207433U, // FMULD
809 4207048U, // FMULD8SUX16
810 4207023U, // FMULD8ULX16
811 4207870U, // FMULQ
812 4208189U, // FMULS
813 4207410U, // FNADDD
814 4208144U, // FNADDS
815 4207454U, // FNAND
816 4208159U, // FNANDS
817 2110274U, // FNEGD
818 2110703U, // FNEGQ
819 2111030U, // FNEGS
820 4207401U, // FNHADDD
821 4208135U, // FNHADDS
822 4207401U, // FNMULD
823 4208135U, // FNMULS
824 4207975U, // FNOR
825 4208253U, // FNORS
826 2109541U, // FNOT1
827 2110878U, // FNOT1S
828 2109700U, // FNOT2
829 2110925U, // FNOT2S
830 4208135U, // FNSMULD
831 70610U, // FONE
832 71207U, // FONES
833 4207970U, // FOR
834 4206700U, // FORNOT1
835 4208038U, // FORNOT1S
836 4206859U, // FORNOT2
837 4208085U, // FORNOT2S
838 4208247U, // FORS
839 2109779U, // FPACK16
840 4206763U, // FPACK32
841 2111259U, // FPACKFIX
842 4206894U, // FPADD16
843 4208095U, // FPADD16S
844 4206726U, // FPADD32
845 4208048U, // FPADD32S
846 4206868U, // FPADD64
847 4207551U, // FPMERGE
848 4206885U, // FPSUB16
849 4207151U, // FPSUB16S
850 4206717U, // FPSUB32
851 4207141U, // FPSUB32S
852 2110325U, // FQTOD
853 2110483U, // FQTOI
854 2111066U, // FQTOS
855 2111304U, // FQTOX
856 4206994U, // FSLAS16
857 4206807U, // FSLAS32
858 4206949U, // FSLL16
859 4206781U, // FSLL32
860 4207440U, // FSMULD
861 2110372U, // FSQRTD
862 2110767U, // FSQRTQ
863 2111130U, // FSQRTS
864 4206877U, // FSRA16
865 4206709U, // FSRA32
866 2109524U, // FSRC1
867 2110859U, // FSRC1S
868 2109683U, // FSRC2
869 2110906U, // FSRC2S
870 4206957U, // FSRL16
871 4206789U, // FSRL32
872 2110332U, // FSTOD
873 2110490U, // FSTOI
874 2110739U, // FSTOQ
875 2111311U, // FSTOX
876 4207366U, // FSUBD
877 4207833U, // FSUBQ
878 4208105U, // FSUBS
879 4207981U, // FXNOR
880 4208260U, // FXNORS
881 4207988U, // FXOR
882 4208268U, // FXORS
883 2110339U, // FXTOD
884 2110746U, // FXTOQ
885 2111073U, // FXTOS
886 70854U, // FZERO
887 71236U, // FZEROS
888 288525019U, // GDOP_LDXrr
889 288524969U, // GDOP_LDrr
890 2131033U, // JMPLri
891 2131033U, // JMPLrr
892 3050045U, // LDAri
893 160401981U, // LDArr
894 1268393U, // LDCSRri
895 1268393U, // LDCSRrr
896 3312297U, // LDCri
897 3312297U, // LDCrr
898 3050038U, // LDDAri
899 160401974U, // LDDArr
900 3312291U, // LDDCri
901 3312291U, // LDDCrr
902 3050038U, // LDDFAri
903 160401974U, // LDDFArr
904 3312291U, // LDDFri
905 3312291U, // LDDFrr
906 3312291U, // LDDri
907 3312291U, // LDDrr
908 3050045U, // LDFAri
909 160401981U, // LDFArr
910 1333929U, // LDFSRri
911 1333929U, // LDFSRrr
912 3312297U, // LDFri
913 3312297U, // LDFrr
914 3050087U, // LDQFAri
915 160402023U, // LDQFArr
916 3312334U, // LDQFri
917 3312334U, // LDQFrr
918 3050012U, // LDSBAri
919 160401948U, // LDSBArr
920 3312268U, // LDSBri
921 3312268U, // LDSBrr
922 3050063U, // LDSHAri
923 160401999U, // LDSHArr
924 3312313U, // LDSHri
925 3312313U, // LDSHrr
926 3050028U, // LDSTUBAri
927 160401964U, // LDSTUBArr
928 3312282U, // LDSTUBri
929 3312282U, // LDSTUBrr
930 3050101U, // LDSWAri
931 160402037U, // LDSWArr
932 3312340U, // LDSWri
933 3312340U, // LDSWrr
934 3050020U, // LDUBAri
935 160401956U, // LDUBArr
936 3312275U, // LDUBri
937 3312275U, // LDUBrr
938 3050071U, // LDUHAri
939 160402007U, // LDUHArr
940 3312320U, // LDUHri
941 3312320U, // LDUHrr
942 3050109U, // LDXAri
943 160402045U, // LDXArr
944 1333979U, // LDXFSRri
945 1333979U, // LDXFSRrr
946 3312347U, // LDXri
947 3312347U, // LDXrr
948 3312297U, // LDri
949 3312297U, // LDrr
950 2111157U, // LZCNT
951 38218U, // MEMBARi
952 2111295U, // MOVDTOX
953 152136530U, // MOVFCCri
954 152136530U, // MOVFCCrr
955 151415634U, // MOVICCri
956 151415634U, // MOVICCrr
957 31550U, // MOVRri
958 31550U, // MOVRrr
959 2111221U, // MOVSTOSW
960 2111231U, // MOVSTOUW
961 2111295U, // MOVWTOS
962 151677778U, // MOVXCCri
963 151677778U, // MOVXCCrr
964 2111295U, // MOVXTOD
965 4207313U, // MULSCCri
966 4207313U, // MULSCCrr
967 4208434U, // MULXri
968 4208434U, // MULXrr
969 2852U, // NOP
970 4207300U, // ORCCri
971 4207300U, // ORCCrr
972 4207291U, // ORNCCri
973 4207291U, // ORNCCrr
974 4207801U, // ORNri
975 4207801U, // ORNrr
976 4207971U, // ORri
977 4207971U, // ORrr
978 4208316U, // PDIST
979 4207806U, // PDISTN
980 2110201U, // POPCrr
981 11426371U, // PREFETCHAi
982 13589059U, // PREFETCHAr
983 11688622U, // PREFETCHi
984 11688622U, // PREFETCHr
985 33559942U, // PWRPSRri
986 33559942U, // PWRPSRrr
987 2110361U, // RDASR
988 69685U, // RDFQ
989 2110842U, // RDPR
990 69706U, // RDPSR
991 69696U, // RDTBR
992 69675U, // RDWIM
993 2791U, // RESTORED
994 4207576U, // RESTOREri
995 4207576U, // RESTORErr
996 71868U, // RET
997 71877U, // RETL
998 2909U, // RETRY
999 87747U, // RETTri
1000 87747U, // RETTrr
1001 2800U, // SAVED
1002 4207585U, // SAVEri
1003 4207585U, // SAVErr
1004 4207321U, // SDIVCCri
1005 4207321U, // SDIVCCrr
1006 4208481U, // SDIVXri
1007 4208481U, // SDIVXrr
1008 4208341U, // SDIVri
1009 4208341U, // SDIVrr
1010 2110451U, // SETHIi
1011 2843U, // SHUTDOWN
1012 2838U, // SIAM
1013 71005U, // SIR
1014 4208421U, // SLLXri
1015 4208421U, // SLLXrr
1016 4207700U, // SLLri
1017 4207700U, // SLLrr
1018 4207223U, // SMACri
1019 4207223U, // SMACrr
1020 4207267U, // SMULCCri
1021 4207267U, // SMULCCrr
1022 4207728U, // SMULri
1023 4207728U, // SMULrr
1024 4208393U, // SRAXri
1025 4208393U, // SRAXrr
1026 4207185U, // SRAri
1027 4207185U, // SRArr
1028 4208427U, // SRLXri
1029 4208427U, // SRLXrr
1030 4207723U, // SRLri
1031 4207723U, // SRLrr
1032 1417826U, // STAri
1033 9413218U, // STArr
1034 2869U, // STBAR
1035 1417785U, // STBAri
1036 9413177U, // STBArr
1037 1483373U, // STBri
1038 1483373U, // STBrr
1039 1464826U, // STCSRri
1040 1464826U, // STCSRrr
1041 1484479U, // STCri
1042 1484479U, // STCrr
1043 1417791U, // STDAri
1044 9413183U, // STDArr
1045 1464804U, // STDCQri
1046 1464804U, // STDCQrr
1047 1483692U, // STDCri
1048 1483692U, // STDCrr
1049 1417791U, // STDFAri
1050 9413183U, // STDFArr
1051 1464815U, // STDFQri
1052 1464815U, // STDFQrr
1053 1483692U, // STDFri
1054 1483692U, // STDFrr
1055 1483692U, // STDri
1056 1483692U, // STDrr
1057 1417826U, // STFAri
1058 9413218U, // STFArr
1059 1464837U, // STFSRri
1060 1464837U, // STFSRrr
1061 1484479U, // STFri
1062 1484479U, // STFrr
1063 1417797U, // STHAri
1064 9413189U, // STHArr
1065 1483758U, // STHri
1066 1483758U, // STHrr
1067 1417803U, // STQFAri
1068 9413195U, // STQFArr
1069 1484087U, // STQFri
1070 1484087U, // STQFrr
1071 1417831U, // STXAri
1072 9413223U, // STXArr
1073 1464848U, // STXFSRri
1074 1464848U, // STXFSRrr
1075 1484636U, // STXri
1076 1484636U, // STXrr
1077 1484479U, // STri
1078 1484479U, // STrr
1079 4207236U, // SUBCCri
1080 4207236U, // SUBCCrr
1081 4208399U, // SUBCri
1082 4208399U, // SUBCrr
1083 4207337U, // SUBEri
1084 4207337U, // SUBErr
1085 4207218U, // SUBri
1086 4207218U, // SUBrr
1087 3050079U, // SWAPAri
1088 160402015U, // SWAPArr
1089 3312327U, // SWAPri
1090 3312327U, // SWAPrr
1091 2412U, // TA1
1092 2417U, // TA3
1093 2422U, // TA5
1094 4208363U, // TADDCCTVri
1095 4208363U, // TADDCCTVrr
1096 4207252U, // TADDCCri
1097 4207252U, // TADDCCrr
1098 70734U, // TAIL_CALL
1099 87252U, // TAIL_CALLri
1100 52869968U, // TICCri
1101 52869968U, // TICCrr
1102 289420053U, // TLS_ADDrr
1103 5198U, // TLS_CALL
1104 288525019U, // TLS_LDXrr
1105 288524969U, // TLS_LDrr
1106 52607824U, // TRAPri
1107 52607824U, // TRAPrr
1108 4208353U, // TSUBCCTVri
1109 4208353U, // TSUBCCTVrr
1110 4207235U, // TSUBCCri
1111 4207235U, // TSUBCCrr
1112 53132112U, // TXCCri
1113 53132112U, // TXCCrr
1114 4207329U, // UDIVCCri
1115 4207329U, // UDIVCCrr
1116 4208488U, // UDIVXri
1117 4208488U, // UDIVXrr
1118 4208347U, // UDIVri
1119 4208347U, // UDIVrr
1120 4207229U, // UMACri
1121 4207229U, // UMACrr
1122 4207275U, // UMULCCri
1123 4207275U, // UMULCCrr
1124 4207610U, // UMULXHI
1125 4207734U, // UMULri
1126 4207734U, // UMULrr
1127 70861U, // UNIMP
1128 16782218U, // V9FCMPD
1129 16782138U, // V9FCMPED
1130 16782567U, // V9FCMPEQ
1131 16782894U, // V9FCMPES
1132 16782625U, // V9FCMPQ
1133 16782952U, // V9FCMPS
1134 31485U, // V9FMOVD_FCC
1135 31535U, // V9FMOVQ_FCC
1136 31562U, // V9FMOVS_FCC
1137 31570U, // V9MOVFCCri
1138 31570U, // V9MOVFCCrr
1139 4208007U, // WRASRri
1140 4208007U, // WRASRrr
1141 4208000U, // WRPRri
1142 4208000U, // WRPRrr
1143 33559943U, // WRPSRri
1144 33559943U, // WRPSRrr
1145 67114375U, // WRTBRri
1146 67114375U, // WRTBRrr
1147 83891591U, // WRWIMri
1148 83891591U, // WRWIMrr
1149 4208433U, // XMULX
1150 4207619U, // XMULXHI
1151 4207298U, // XNORCCri
1152 4207298U, // XNORCCrr
1153 4207982U, // XNORri
1154 4207982U, // XNORrr
1155 4207306U, // XORCCri
1156 4207306U, // XORCCrr
1157 4207989U, // XORri
1158 4207989U, // XORrr
1159 };
1160
1161 // Emit the opcode for the instruction.
1162 uint32_t Bits = 0;
1163 Bits |= OpInfo0[MI->getOpcode()] << 0;
1164 if (Bits == 0)
1165 return {nullptr, Bits};
1166 return {AsmStrs+(Bits & 4095)-1, Bits};
1167
1168}
1169/// printInstruction - This method is automatically generated by tablegen
1170/// from the instruction set description.
1171LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
1172void SparcInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
1173 O << "\t";
1174
1175 auto MnemonicInfo = getMnemonic(MI);
1176
1177 O << MnemonicInfo.first;
1178
1179 uint32_t Bits = MnemonicInfo.second;
1180 assert(Bits != 0 && "Cannot print this instruction.");
1181
1182 // Fragment 0 encoded into 4 bits for 12 unique commands.
1183 switch ((Bits >> 12) & 15) {
1184 default: llvm_unreachable("Invalid command number.");
1185 case 0:
1186 // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
1187 return;
1188 break;
1189 case 1:
1190 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
1191 printOperand(MI, opNum: 0, STI, OS&: O);
1192 break;
1193 case 2:
1194 // GETPCX
1195 printGetPCX(MI, OpNo: 0, STI, OS&: O);
1196 return;
1197 break;
1198 case 3:
1199 // SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, AD...
1200 printOperand(MI, opNum: 1, STI, OS&: O);
1201 break;
1202 case 4:
1203 // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
1204 printCCOperand(MI, opNum: 1, STI, OS&: O);
1205 break;
1206 case 5:
1207 // BINDri, BINDrr, CALLri, CALLrr, FLUSHri, FLUSHrr, LDCSRri, LDCSRrr, LD...
1208 printMemOperand(MI, opNum: 0, STI, OS&: O);
1209 break;
1210 case 6:
1211 // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
1212 printCCOperand(MI, opNum: 3, STI, OS&: O);
1213 break;
1214 case 7:
1215 // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
1216 printCCOperand(MI, opNum: 4, STI, OS&: O);
1217 O << ' ';
1218 printOperand(MI, opNum: 1, STI, OS&: O);
1219 O << ", ";
1220 printOperand(MI, opNum: 2, STI, OS&: O);
1221 O << ", ";
1222 printOperand(MI, opNum: 0, STI, OS&: O);
1223 return;
1224 break;
1225 case 8:
1226 // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
1227 printMemOperand(MI, opNum: 1, STI, OS&: O);
1228 break;
1229 case 9:
1230 // MEMBARi
1231 printMembarTag(MI, opNum: 0, STI, O);
1232 return;
1233 break;
1234 case 10:
1235 // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
1236 printOperand(MI, opNum: 2, STI, OS&: O);
1237 O << ", [";
1238 printMemOperand(MI, opNum: 0, STI, OS&: O);
1239 break;
1240 case 11:
1241 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1242 printCCOperand(MI, opNum: 2, STI, OS&: O);
1243 break;
1244 }
1245
1246
1247 // Fragment 1 encoded into 5 bits for 23 unique commands.
1248 switch ((Bits >> 16) & 31) {
1249 default: llvm_unreachable("Invalid command number.");
1250 case 0:
1251 // ADJCALLSTACKDOWN, SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri,...
1252 O << ", ";
1253 break;
1254 case 1:
1255 // ADJCALLSTACKUP, BA, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMA...
1256 return;
1257 break;
1258 case 2:
1259 // BCOND, BPFCC, BPR, CBCOND, FBCOND, TRAPri, TRAPrr
1260 O << ' ';
1261 break;
1262 case 3:
1263 // BCONDA, BPFCCA, BPRA, CBCONDA, FBCONDA
1264 O << ",a ";
1265 break;
1266 case 4:
1267 // BPFCCANT, BPRANT
1268 O << ",a,pn ";
1269 printOperand(MI, opNum: 2, STI, OS&: O);
1270 O << ", ";
1271 printOperand(MI, opNum: 0, STI, OS&: O);
1272 return;
1273 break;
1274 case 5:
1275 // BPFCCNT, BPRNT
1276 O << ",pn ";
1277 printOperand(MI, opNum: 2, STI, OS&: O);
1278 O << ", ";
1279 printOperand(MI, opNum: 0, STI, OS&: O);
1280 return;
1281 break;
1282 case 6:
1283 // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
1284 O << " %icc, ";
1285 break;
1286 case 7:
1287 // BPICCA
1288 O << ",a %icc, ";
1289 printOperand(MI, opNum: 0, STI, OS&: O);
1290 return;
1291 break;
1292 case 8:
1293 // BPICCANT
1294 O << ",a,pn %icc, ";
1295 printOperand(MI, opNum: 0, STI, OS&: O);
1296 return;
1297 break;
1298 case 9:
1299 // BPICCNT
1300 O << ",pn %icc, ";
1301 printOperand(MI, opNum: 0, STI, OS&: O);
1302 return;
1303 break;
1304 case 10:
1305 // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
1306 O << " %xcc, ";
1307 break;
1308 case 11:
1309 // BPXCCA
1310 O << ",a %xcc, ";
1311 printOperand(MI, opNum: 0, STI, OS&: O);
1312 return;
1313 break;
1314 case 12:
1315 // BPXCCANT
1316 O << ",a,pn %xcc, ";
1317 printOperand(MI, opNum: 0, STI, OS&: O);
1318 return;
1319 break;
1320 case 13:
1321 // BPXCCNT
1322 O << ",pn %xcc, ";
1323 printOperand(MI, opNum: 0, STI, OS&: O);
1324 return;
1325 break;
1326 case 14:
1327 // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
1328 O << "] %asi, ";
1329 break;
1330 case 15:
1331 // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
1332 O << "] ";
1333 break;
1334 case 16:
1335 // FBCONDA_V9
1336 O << ",a %fcc0, ";
1337 printOperand(MI, opNum: 0, STI, OS&: O);
1338 return;
1339 break;
1340 case 17:
1341 // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1342 O << " %fcc0, ";
1343 break;
1344 case 18:
1345 // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
1346 O << "], ";
1347 break;
1348 case 19:
1349 // LDCSRri, LDCSRrr
1350 O << "], %csr";
1351 return;
1352 break;
1353 case 20:
1354 // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
1355 O << "], %fsr";
1356 return;
1357 break;
1358 case 21:
1359 // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
1360 O << "] %asi";
1361 return;
1362 break;
1363 case 22:
1364 // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
1365 O << ']';
1366 return;
1367 break;
1368 }
1369
1370
1371 // Fragment 2 encoded into 3 bits for 7 unique commands.
1372 switch ((Bits >> 21) & 7) {
1373 default: llvm_unreachable("Invalid command number.");
1374 case 0:
1375 // ADJCALLSTACKDOWN, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMPS_V9, F...
1376 printOperand(MI, opNum: 1, STI, OS&: O);
1377 break;
1378 case 1:
1379 // SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, FABSD, FABSQ, FABSS...
1380 printOperand(MI, opNum: 0, STI, OS&: O);
1381 break;
1382 case 2:
1383 // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
1384 printOperand(MI, opNum: 2, STI, OS&: O);
1385 O << ", ";
1386 printOperand(MI, opNum: 0, STI, OS&: O);
1387 break;
1388 case 3:
1389 // CASArr, CASXArr
1390 printASITag(MI, opNum: 4, STI, O);
1391 O << ", ";
1392 printOperand(MI, opNum: 2, STI, OS&: O);
1393 O << ", ";
1394 printOperand(MI, opNum: 0, STI, OS&: O);
1395 return;
1396 break;
1397 case 4:
1398 // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
1399 printASITag(MI, opNum: 3, STI, O);
1400 break;
1401 case 5:
1402 // PREFETCHAi, PREFETCHi, PREFETCHr
1403 printPrefetchTag(MI, opNum: 2, STI, O);
1404 return;
1405 break;
1406 case 6:
1407 // PREFETCHAr
1408 printASITag(MI, opNum: 2, STI, O);
1409 O << ", ";
1410 printPrefetchTag(MI, opNum: 3, STI, O);
1411 return;
1412 break;
1413 }
1414
1415
1416 // Fragment 3 encoded into 3 bits for 6 unique commands.
1417 switch ((Bits >> 24) & 7) {
1418 default: llvm_unreachable("Invalid command number.");
1419 case 0:
1420 // ADJCALLSTACKDOWN, SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri,...
1421 return;
1422 break;
1423 case 1:
1424 // FLCMPD, FLCMPS, FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC,...
1425 O << ", ";
1426 break;
1427 case 2:
1428 // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
1429 O << ", %psr";
1430 return;
1431 break;
1432 case 3:
1433 // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
1434 O << " + ";
1435 printOperand(MI, opNum: 1, STI, OS&: O);
1436 return;
1437 break;
1438 case 4:
1439 // WRTBRri, WRTBRrr
1440 O << ", %tbr";
1441 return;
1442 break;
1443 case 5:
1444 // WRWIMri, WRWIMrr
1445 O << ", %wim";
1446 return;
1447 break;
1448 }
1449
1450
1451 // Fragment 4 encoded into 2 bits for 3 unique commands.
1452 switch ((Bits >> 27) & 3) {
1453 default: llvm_unreachable("Invalid command number.");
1454 case 0:
1455 // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1456 printOperand(MI, opNum: 2, STI, OS&: O);
1457 return;
1458 break;
1459 case 1:
1460 // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
1461 printOperand(MI, opNum: 0, STI, OS&: O);
1462 return;
1463 break;
1464 case 2:
1465 // GDOP_LDXrr, GDOP_LDrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1466 printOperand(MI, opNum: 3, STI, OS&: O);
1467 return;
1468 break;
1469 }
1470
1471}
1472
1473
1474/// getRegisterName - This method is automatically generated by tblgen
1475/// from the register set description. This returns the assembler name
1476/// for the specified register.
1477const char *SparcInstPrinter::
1478getRegisterName(MCRegister Reg, unsigned AltIdx) {
1479 unsigned RegNo = Reg.id();
1480 assert(RegNo && RegNo < 238 && "Invalid register number!");
1481
1482
1483#ifdef __GNUC__
1484#pragma GCC diagnostic push
1485#pragma GCC diagnostic ignored "-Woverlength-strings"
1486#endif
1487 static const char AsmStrsNoRegAltName[] = {
1488 /* 0 */ "c10\0"
1489 /* 4 */ "f10\0"
1490 /* 8 */ "asr10\0"
1491 /* 14 */ "c20\0"
1492 /* 18 */ "f20\0"
1493 /* 22 */ "asr20\0"
1494 /* 28 */ "c30\0"
1495 /* 32 */ "f30\0"
1496 /* 36 */ "asr30\0"
1497 /* 42 */ "f40\0"
1498 /* 46 */ "f50\0"
1499 /* 50 */ "f60\0"
1500 /* 54 */ "fcc0\0"
1501 /* 59 */ "f0\0"
1502 /* 62 */ "g0\0"
1503 /* 65 */ "i0\0"
1504 /* 68 */ "l0\0"
1505 /* 71 */ "o0\0"
1506 /* 74 */ "c11\0"
1507 /* 78 */ "f11\0"
1508 /* 82 */ "asr11\0"
1509 /* 88 */ "c21\0"
1510 /* 92 */ "f21\0"
1511 /* 96 */ "asr21\0"
1512 /* 102 */ "c31\0"
1513 /* 106 */ "f31\0"
1514 /* 110 */ "asr31\0"
1515 /* 116 */ "fcc1\0"
1516 /* 121 */ "f1\0"
1517 /* 124 */ "g1\0"
1518 /* 127 */ "i1\0"
1519 /* 130 */ "l1\0"
1520 /* 133 */ "o1\0"
1521 /* 136 */ "asr1\0"
1522 /* 141 */ "c12\0"
1523 /* 145 */ "f12\0"
1524 /* 149 */ "asr12\0"
1525 /* 155 */ "c22\0"
1526 /* 159 */ "f22\0"
1527 /* 163 */ "asr22\0"
1528 /* 169 */ "f32\0"
1529 /* 173 */ "f42\0"
1530 /* 177 */ "f52\0"
1531 /* 181 */ "f62\0"
1532 /* 185 */ "fcc2\0"
1533 /* 190 */ "f2\0"
1534 /* 193 */ "g2\0"
1535 /* 196 */ "i2\0"
1536 /* 199 */ "l2\0"
1537 /* 202 */ "o2\0"
1538 /* 205 */ "asr2\0"
1539 /* 210 */ "c13\0"
1540 /* 214 */ "f13\0"
1541 /* 218 */ "asr13\0"
1542 /* 224 */ "c23\0"
1543 /* 228 */ "f23\0"
1544 /* 232 */ "asr23\0"
1545 /* 238 */ "fcc3\0"
1546 /* 243 */ "f3\0"
1547 /* 246 */ "g3\0"
1548 /* 249 */ "i3\0"
1549 /* 252 */ "l3\0"
1550 /* 255 */ "o3\0"
1551 /* 258 */ "asr3\0"
1552 /* 263 */ "c14\0"
1553 /* 267 */ "f14\0"
1554 /* 271 */ "asr14\0"
1555 /* 277 */ "c24\0"
1556 /* 281 */ "f24\0"
1557 /* 285 */ "asr24\0"
1558 /* 291 */ "f34\0"
1559 /* 295 */ "f44\0"
1560 /* 299 */ "f54\0"
1561 /* 303 */ "c4\0"
1562 /* 306 */ "f4\0"
1563 /* 309 */ "g4\0"
1564 /* 312 */ "i4\0"
1565 /* 315 */ "l4\0"
1566 /* 318 */ "o4\0"
1567 /* 321 */ "asr4\0"
1568 /* 326 */ "c15\0"
1569 /* 330 */ "f15\0"
1570 /* 334 */ "asr15\0"
1571 /* 340 */ "c25\0"
1572 /* 344 */ "f25\0"
1573 /* 348 */ "asr25\0"
1574 /* 354 */ "c5\0"
1575 /* 357 */ "f5\0"
1576 /* 360 */ "g5\0"
1577 /* 363 */ "i5\0"
1578 /* 366 */ "l5\0"
1579 /* 369 */ "o5\0"
1580 /* 372 */ "asr5\0"
1581 /* 377 */ "c16\0"
1582 /* 381 */ "f16\0"
1583 /* 385 */ "asr16\0"
1584 /* 391 */ "c26\0"
1585 /* 395 */ "f26\0"
1586 /* 399 */ "asr26\0"
1587 /* 405 */ "f36\0"
1588 /* 409 */ "f46\0"
1589 /* 413 */ "f56\0"
1590 /* 417 */ "c6\0"
1591 /* 420 */ "f6\0"
1592 /* 423 */ "g6\0"
1593 /* 426 */ "i6\0"
1594 /* 429 */ "l6\0"
1595 /* 432 */ "o6\0"
1596 /* 435 */ "asr6\0"
1597 /* 440 */ "c17\0"
1598 /* 444 */ "f17\0"
1599 /* 448 */ "asr17\0"
1600 /* 454 */ "c27\0"
1601 /* 458 */ "f27\0"
1602 /* 462 */ "asr27\0"
1603 /* 468 */ "c7\0"
1604 /* 471 */ "f7\0"
1605 /* 474 */ "g7\0"
1606 /* 477 */ "i7\0"
1607 /* 480 */ "l7\0"
1608 /* 483 */ "o7\0"
1609 /* 486 */ "asr7\0"
1610 /* 491 */ "c18\0"
1611 /* 495 */ "f18\0"
1612 /* 499 */ "asr18\0"
1613 /* 505 */ "c28\0"
1614 /* 509 */ "f28\0"
1615 /* 513 */ "asr28\0"
1616 /* 519 */ "f38\0"
1617 /* 523 */ "f48\0"
1618 /* 527 */ "f58\0"
1619 /* 531 */ "c8\0"
1620 /* 534 */ "f8\0"
1621 /* 537 */ "asr8\0"
1622 /* 542 */ "c19\0"
1623 /* 546 */ "f19\0"
1624 /* 550 */ "asr19\0"
1625 /* 556 */ "c29\0"
1626 /* 560 */ "f29\0"
1627 /* 564 */ "asr29\0"
1628 /* 570 */ "c9\0"
1629 /* 573 */ "f9\0"
1630 /* 576 */ "asr9\0"
1631 /* 581 */ "tba\0"
1632 /* 585 */ "icc\0"
1633 /* 589 */ "tnpc\0"
1634 /* 594 */ "tpc\0"
1635 /* 598 */ "canrestore\0"
1636 /* 609 */ "pstate\0"
1637 /* 616 */ "tstate\0"
1638 /* 623 */ "wstate\0"
1639 /* 630 */ "cansave\0"
1640 /* 638 */ "tick\0"
1641 /* 643 */ "gl\0"
1642 /* 646 */ "pil\0"
1643 /* 650 */ "tl\0"
1644 /* 653 */ "wim\0"
1645 /* 657 */ "cleanwin\0"
1646 /* 666 */ "otherwin\0"
1647 /* 675 */ "fp\0"
1648 /* 678 */ "sp\0"
1649 /* 681 */ "cwp\0"
1650 /* 685 */ "cq\0"
1651 /* 688 */ "fq\0"
1652 /* 691 */ "tbr\0"
1653 /* 695 */ "ver\0"
1654 /* 699 */ "csr\0"
1655 /* 703 */ "fsr\0"
1656 /* 707 */ "psr\0"
1657 /* 711 */ "tt\0"
1658 /* 714 */ "y\0"
1659};
1660#ifdef __GNUC__
1661#pragma GCC diagnostic pop
1662#endif
1663
1664 static const uint16_t RegAsmOffsetNoRegAltName[] = {
1665 598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609,
1666 581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205,
1667 258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385,
1668 448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36,
1669 110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141,
1670 210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391,
1671 454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381,
1672 495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295,
1673 409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306,
1674 357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495,
1675 546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54,
1676 116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196,
1677 249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71,
1678 133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281,
1679 509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531,
1680 0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309,
1681 423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432,
1682 };
1683
1684
1685#ifdef __GNUC__
1686#pragma GCC diagnostic push
1687#pragma GCC diagnostic ignored "-Woverlength-strings"
1688#endif
1689 static const char AsmStrsRegNamesStateReg[] = {
1690 /* 0 */ "pc\0"
1691 /* 3 */ "asi\0"
1692 /* 7 */ "tick\0"
1693 /* 12 */ "ccr\0"
1694 /* 16 */ "fprs\0"
1695};
1696#ifdef __GNUC__
1697#pragma GCC diagnostic pop
1698#endif
1699
1700 static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
1701 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1702 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12,
1703 3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1704 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1705 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1706 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1707 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1708 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1709 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1710 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1711 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1712 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1713 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1714 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1715 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1716 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1717 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1718 };
1719
1720 switch(AltIdx) {
1721 default: llvm_unreachable("Invalid register alt name index!");
1722 case SP::NoRegAltName:
1723 assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1724 "Invalid alt name index for register!");
1725 return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1726 case SP::RegNamesStateReg:
1727 if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
1728 return getRegisterName(Reg: RegNo, AltIdx: SP::NoRegAltName);
1729 return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
1730 }
1731}
1732
1733#ifdef PRINT_ALIAS_INSTR
1734#undef PRINT_ALIAS_INSTR
1735
1736bool SparcInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
1737 static const PatternsForOpcode OpToPatterns[] = {
1738 {.Opcode: SP::BCOND, .PatternStart: 0, .NumPatterns: 16 },
1739 {.Opcode: SP::BCONDA, .PatternStart: 16, .NumPatterns: 16 },
1740 {.Opcode: SP::BPFCCANT, .PatternStart: 32, .NumPatterns: 16 },
1741 {.Opcode: SP::BPFCCNT, .PatternStart: 48, .NumPatterns: 16 },
1742 {.Opcode: SP::BPICCANT, .PatternStart: 64, .NumPatterns: 16 },
1743 {.Opcode: SP::BPICCNT, .PatternStart: 80, .NumPatterns: 16 },
1744 {.Opcode: SP::BPRANT, .PatternStart: 96, .NumPatterns: 4 },
1745 {.Opcode: SP::BPRNT, .PatternStart: 100, .NumPatterns: 4 },
1746 {.Opcode: SP::BPXCCANT, .PatternStart: 104, .NumPatterns: 16 },
1747 {.Opcode: SP::BPXCCNT, .PatternStart: 120, .NumPatterns: 16 },
1748 {.Opcode: SP::CASArr, .PatternStart: 136, .NumPatterns: 2 },
1749 {.Opcode: SP::CASXArr, .PatternStart: 138, .NumPatterns: 2 },
1750 {.Opcode: SP::FMOVD_ICC, .PatternStart: 140, .NumPatterns: 16 },
1751 {.Opcode: SP::FMOVD_XCC, .PatternStart: 156, .NumPatterns: 16 },
1752 {.Opcode: SP::FMOVQ_ICC, .PatternStart: 172, .NumPatterns: 16 },
1753 {.Opcode: SP::FMOVQ_XCC, .PatternStart: 188, .NumPatterns: 16 },
1754 {.Opcode: SP::FMOVRD, .PatternStart: 204, .NumPatterns: 4 },
1755 {.Opcode: SP::FMOVRQ, .PatternStart: 208, .NumPatterns: 4 },
1756 {.Opcode: SP::FMOVRS, .PatternStart: 212, .NumPatterns: 4 },
1757 {.Opcode: SP::FMOVS_ICC, .PatternStart: 216, .NumPatterns: 16 },
1758 {.Opcode: SP::FMOVS_XCC, .PatternStart: 232, .NumPatterns: 16 },
1759 {.Opcode: SP::MOVICCri, .PatternStart: 248, .NumPatterns: 16 },
1760 {.Opcode: SP::MOVICCrr, .PatternStart: 264, .NumPatterns: 16 },
1761 {.Opcode: SP::MOVRri, .PatternStart: 280, .NumPatterns: 4 },
1762 {.Opcode: SP::MOVRrr, .PatternStart: 284, .NumPatterns: 4 },
1763 {.Opcode: SP::MOVXCCri, .PatternStart: 288, .NumPatterns: 16 },
1764 {.Opcode: SP::MOVXCCrr, .PatternStart: 304, .NumPatterns: 16 },
1765 {.Opcode: SP::ORCCrr, .PatternStart: 320, .NumPatterns: 1 },
1766 {.Opcode: SP::ORri, .PatternStart: 321, .NumPatterns: 1 },
1767 {.Opcode: SP::ORrr, .PatternStart: 322, .NumPatterns: 1 },
1768 {.Opcode: SP::RESTORErr, .PatternStart: 323, .NumPatterns: 1 },
1769 {.Opcode: SP::RET, .PatternStart: 324, .NumPatterns: 1 },
1770 {.Opcode: SP::RETL, .PatternStart: 325, .NumPatterns: 1 },
1771 {.Opcode: SP::SAVErr, .PatternStart: 326, .NumPatterns: 1 },
1772 {.Opcode: SP::SUBCCri, .PatternStart: 327, .NumPatterns: 1 },
1773 {.Opcode: SP::SUBCCrr, .PatternStart: 328, .NumPatterns: 1 },
1774 {.Opcode: SP::TICCri, .PatternStart: 329, .NumPatterns: 32 },
1775 {.Opcode: SP::TICCrr, .PatternStart: 361, .NumPatterns: 32 },
1776 {.Opcode: SP::TRAPri, .PatternStart: 393, .NumPatterns: 32 },
1777 {.Opcode: SP::TRAPrr, .PatternStart: 425, .NumPatterns: 32 },
1778 {.Opcode: SP::TXCCri, .PatternStart: 457, .NumPatterns: 32 },
1779 {.Opcode: SP::TXCCrr, .PatternStart: 489, .NumPatterns: 32 },
1780 {.Opcode: SP::V9FCMPD, .PatternStart: 521, .NumPatterns: 1 },
1781 {.Opcode: SP::V9FCMPED, .PatternStart: 522, .NumPatterns: 1 },
1782 {.Opcode: SP::V9FCMPEQ, .PatternStart: 523, .NumPatterns: 1 },
1783 {.Opcode: SP::V9FCMPES, .PatternStart: 524, .NumPatterns: 1 },
1784 {.Opcode: SP::V9FCMPQ, .PatternStart: 525, .NumPatterns: 1 },
1785 {.Opcode: SP::V9FCMPS, .PatternStart: 526, .NumPatterns: 1 },
1786 {.Opcode: SP::V9FMOVD_FCC, .PatternStart: 527, .NumPatterns: 16 },
1787 {.Opcode: SP::V9FMOVQ_FCC, .PatternStart: 543, .NumPatterns: 16 },
1788 {.Opcode: SP::V9FMOVS_FCC, .PatternStart: 559, .NumPatterns: 16 },
1789 {.Opcode: SP::V9MOVFCCri, .PatternStart: 575, .NumPatterns: 16 },
1790 {.Opcode: SP::V9MOVFCCrr, .PatternStart: 591, .NumPatterns: 16 },
1791 };
1792
1793 static const AliasPattern Patterns[] = {
1794 // SP::BCOND - 0
1795 {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 2, .NumConds: 2 },
1796 {.AsmStrOffset: 6, .AliasCondStart: 2, .NumOperands: 2, .NumConds: 2 },
1797 {.AsmStrOffset: 12, .AliasCondStart: 4, .NumOperands: 2, .NumConds: 2 },
1798 {.AsmStrOffset: 19, .AliasCondStart: 6, .NumOperands: 2, .NumConds: 2 },
1799 {.AsmStrOffset: 25, .AliasCondStart: 8, .NumOperands: 2, .NumConds: 2 },
1800 {.AsmStrOffset: 31, .AliasCondStart: 10, .NumOperands: 2, .NumConds: 2 },
1801 {.AsmStrOffset: 38, .AliasCondStart: 12, .NumOperands: 2, .NumConds: 2 },
1802 {.AsmStrOffset: 45, .AliasCondStart: 14, .NumOperands: 2, .NumConds: 2 },
1803 {.AsmStrOffset: 51, .AliasCondStart: 16, .NumOperands: 2, .NumConds: 2 },
1804 {.AsmStrOffset: 58, .AliasCondStart: 18, .NumOperands: 2, .NumConds: 2 },
1805 {.AsmStrOffset: 66, .AliasCondStart: 20, .NumOperands: 2, .NumConds: 2 },
1806 {.AsmStrOffset: 73, .AliasCondStart: 22, .NumOperands: 2, .NumConds: 2 },
1807 {.AsmStrOffset: 80, .AliasCondStart: 24, .NumOperands: 2, .NumConds: 2 },
1808 {.AsmStrOffset: 88, .AliasCondStart: 26, .NumOperands: 2, .NumConds: 2 },
1809 {.AsmStrOffset: 96, .AliasCondStart: 28, .NumOperands: 2, .NumConds: 2 },
1810 {.AsmStrOffset: 103, .AliasCondStart: 30, .NumOperands: 2, .NumConds: 2 },
1811 // SP::BCONDA - 16
1812 {.AsmStrOffset: 110, .AliasCondStart: 32, .NumOperands: 2, .NumConds: 2 },
1813 {.AsmStrOffset: 118, .AliasCondStart: 34, .NumOperands: 2, .NumConds: 2 },
1814 {.AsmStrOffset: 126, .AliasCondStart: 36, .NumOperands: 2, .NumConds: 2 },
1815 {.AsmStrOffset: 135, .AliasCondStart: 38, .NumOperands: 2, .NumConds: 2 },
1816 {.AsmStrOffset: 143, .AliasCondStart: 40, .NumOperands: 2, .NumConds: 2 },
1817 {.AsmStrOffset: 151, .AliasCondStart: 42, .NumOperands: 2, .NumConds: 2 },
1818 {.AsmStrOffset: 160, .AliasCondStart: 44, .NumOperands: 2, .NumConds: 2 },
1819 {.AsmStrOffset: 169, .AliasCondStart: 46, .NumOperands: 2, .NumConds: 2 },
1820 {.AsmStrOffset: 177, .AliasCondStart: 48, .NumOperands: 2, .NumConds: 2 },
1821 {.AsmStrOffset: 186, .AliasCondStart: 50, .NumOperands: 2, .NumConds: 2 },
1822 {.AsmStrOffset: 196, .AliasCondStart: 52, .NumOperands: 2, .NumConds: 2 },
1823 {.AsmStrOffset: 205, .AliasCondStart: 54, .NumOperands: 2, .NumConds: 2 },
1824 {.AsmStrOffset: 214, .AliasCondStart: 56, .NumOperands: 2, .NumConds: 2 },
1825 {.AsmStrOffset: 224, .AliasCondStart: 58, .NumOperands: 2, .NumConds: 2 },
1826 {.AsmStrOffset: 234, .AliasCondStart: 60, .NumOperands: 2, .NumConds: 2 },
1827 {.AsmStrOffset: 243, .AliasCondStart: 62, .NumOperands: 2, .NumConds: 2 },
1828 // SP::BPFCCANT - 32
1829 {.AsmStrOffset: 252, .AliasCondStart: 64, .NumOperands: 3, .NumConds: 4 },
1830 {.AsmStrOffset: 268, .AliasCondStart: 68, .NumOperands: 3, .NumConds: 4 },
1831 {.AsmStrOffset: 284, .AliasCondStart: 72, .NumOperands: 3, .NumConds: 4 },
1832 {.AsmStrOffset: 300, .AliasCondStart: 76, .NumOperands: 3, .NumConds: 4 },
1833 {.AsmStrOffset: 316, .AliasCondStart: 80, .NumOperands: 3, .NumConds: 4 },
1834 {.AsmStrOffset: 333, .AliasCondStart: 84, .NumOperands: 3, .NumConds: 4 },
1835 {.AsmStrOffset: 349, .AliasCondStart: 88, .NumOperands: 3, .NumConds: 4 },
1836 {.AsmStrOffset: 366, .AliasCondStart: 92, .NumOperands: 3, .NumConds: 4 },
1837 {.AsmStrOffset: 383, .AliasCondStart: 96, .NumOperands: 3, .NumConds: 4 },
1838 {.AsmStrOffset: 400, .AliasCondStart: 100, .NumOperands: 3, .NumConds: 4 },
1839 {.AsmStrOffset: 416, .AliasCondStart: 104, .NumOperands: 3, .NumConds: 4 },
1840 {.AsmStrOffset: 433, .AliasCondStart: 108, .NumOperands: 3, .NumConds: 4 },
1841 {.AsmStrOffset: 450, .AliasCondStart: 112, .NumOperands: 3, .NumConds: 4 },
1842 {.AsmStrOffset: 468, .AliasCondStart: 116, .NumOperands: 3, .NumConds: 4 },
1843 {.AsmStrOffset: 485, .AliasCondStart: 120, .NumOperands: 3, .NumConds: 4 },
1844 {.AsmStrOffset: 503, .AliasCondStart: 124, .NumOperands: 3, .NumConds: 4 },
1845 // SP::BPFCCNT - 48
1846 {.AsmStrOffset: 519, .AliasCondStart: 128, .NumOperands: 3, .NumConds: 4 },
1847 {.AsmStrOffset: 533, .AliasCondStart: 132, .NumOperands: 3, .NumConds: 4 },
1848 {.AsmStrOffset: 547, .AliasCondStart: 136, .NumOperands: 3, .NumConds: 4 },
1849 {.AsmStrOffset: 561, .AliasCondStart: 140, .NumOperands: 3, .NumConds: 4 },
1850 {.AsmStrOffset: 575, .AliasCondStart: 144, .NumOperands: 3, .NumConds: 4 },
1851 {.AsmStrOffset: 590, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 4 },
1852 {.AsmStrOffset: 604, .AliasCondStart: 152, .NumOperands: 3, .NumConds: 4 },
1853 {.AsmStrOffset: 619, .AliasCondStart: 156, .NumOperands: 3, .NumConds: 4 },
1854 {.AsmStrOffset: 634, .AliasCondStart: 160, .NumOperands: 3, .NumConds: 4 },
1855 {.AsmStrOffset: 649, .AliasCondStart: 164, .NumOperands: 3, .NumConds: 4 },
1856 {.AsmStrOffset: 663, .AliasCondStart: 168, .NumOperands: 3, .NumConds: 4 },
1857 {.AsmStrOffset: 678, .AliasCondStart: 172, .NumOperands: 3, .NumConds: 4 },
1858 {.AsmStrOffset: 693, .AliasCondStart: 176, .NumOperands: 3, .NumConds: 4 },
1859 {.AsmStrOffset: 709, .AliasCondStart: 180, .NumOperands: 3, .NumConds: 4 },
1860 {.AsmStrOffset: 724, .AliasCondStart: 184, .NumOperands: 3, .NumConds: 4 },
1861 {.AsmStrOffset: 740, .AliasCondStart: 188, .NumOperands: 3, .NumConds: 4 },
1862 // SP::BPICCANT - 64
1863 {.AsmStrOffset: 754, .AliasCondStart: 192, .NumOperands: 2, .NumConds: 3 },
1864 {.AsmStrOffset: 771, .AliasCondStart: 195, .NumOperands: 2, .NumConds: 3 },
1865 {.AsmStrOffset: 788, .AliasCondStart: 198, .NumOperands: 2, .NumConds: 3 },
1866 {.AsmStrOffset: 806, .AliasCondStart: 201, .NumOperands: 2, .NumConds: 3 },
1867 {.AsmStrOffset: 823, .AliasCondStart: 204, .NumOperands: 2, .NumConds: 3 },
1868 {.AsmStrOffset: 840, .AliasCondStart: 207, .NumOperands: 2, .NumConds: 3 },
1869 {.AsmStrOffset: 858, .AliasCondStart: 210, .NumOperands: 2, .NumConds: 3 },
1870 {.AsmStrOffset: 876, .AliasCondStart: 213, .NumOperands: 2, .NumConds: 3 },
1871 {.AsmStrOffset: 893, .AliasCondStart: 216, .NumOperands: 2, .NumConds: 3 },
1872 {.AsmStrOffset: 911, .AliasCondStart: 219, .NumOperands: 2, .NumConds: 3 },
1873 {.AsmStrOffset: 930, .AliasCondStart: 222, .NumOperands: 2, .NumConds: 3 },
1874 {.AsmStrOffset: 948, .AliasCondStart: 225, .NumOperands: 2, .NumConds: 3 },
1875 {.AsmStrOffset: 966, .AliasCondStart: 228, .NumOperands: 2, .NumConds: 3 },
1876 {.AsmStrOffset: 985, .AliasCondStart: 231, .NumOperands: 2, .NumConds: 3 },
1877 {.AsmStrOffset: 1004, .AliasCondStart: 234, .NumOperands: 2, .NumConds: 3 },
1878 {.AsmStrOffset: 1022, .AliasCondStart: 237, .NumOperands: 2, .NumConds: 3 },
1879 // SP::BPICCNT - 80
1880 {.AsmStrOffset: 1040, .AliasCondStart: 240, .NumOperands: 2, .NumConds: 3 },
1881 {.AsmStrOffset: 1055, .AliasCondStart: 243, .NumOperands: 2, .NumConds: 3 },
1882 {.AsmStrOffset: 1070, .AliasCondStart: 246, .NumOperands: 2, .NumConds: 3 },
1883 {.AsmStrOffset: 1086, .AliasCondStart: 249, .NumOperands: 2, .NumConds: 3 },
1884 {.AsmStrOffset: 1101, .AliasCondStart: 252, .NumOperands: 2, .NumConds: 3 },
1885 {.AsmStrOffset: 1116, .AliasCondStart: 255, .NumOperands: 2, .NumConds: 3 },
1886 {.AsmStrOffset: 1132, .AliasCondStart: 258, .NumOperands: 2, .NumConds: 3 },
1887 {.AsmStrOffset: 1148, .AliasCondStart: 261, .NumOperands: 2, .NumConds: 3 },
1888 {.AsmStrOffset: 1163, .AliasCondStart: 264, .NumOperands: 2, .NumConds: 3 },
1889 {.AsmStrOffset: 1179, .AliasCondStart: 267, .NumOperands: 2, .NumConds: 3 },
1890 {.AsmStrOffset: 1196, .AliasCondStart: 270, .NumOperands: 2, .NumConds: 3 },
1891 {.AsmStrOffset: 1212, .AliasCondStart: 273, .NumOperands: 2, .NumConds: 3 },
1892 {.AsmStrOffset: 1228, .AliasCondStart: 276, .NumOperands: 2, .NumConds: 3 },
1893 {.AsmStrOffset: 1245, .AliasCondStart: 279, .NumOperands: 2, .NumConds: 3 },
1894 {.AsmStrOffset: 1262, .AliasCondStart: 282, .NumOperands: 2, .NumConds: 3 },
1895 {.AsmStrOffset: 1278, .AliasCondStart: 285, .NumOperands: 2, .NumConds: 3 },
1896 // SP::BPRANT - 96
1897 {.AsmStrOffset: 1294, .AliasCondStart: 288, .NumOperands: 3, .NumConds: 3 },
1898 {.AsmStrOffset: 1312, .AliasCondStart: 291, .NumOperands: 3, .NumConds: 3 },
1899 {.AsmStrOffset: 1329, .AliasCondStart: 294, .NumOperands: 3, .NumConds: 3 },
1900 {.AsmStrOffset: 1346, .AliasCondStart: 297, .NumOperands: 3, .NumConds: 3 },
1901 // SP::BPRNT - 100
1902 {.AsmStrOffset: 1364, .AliasCondStart: 300, .NumOperands: 3, .NumConds: 3 },
1903 {.AsmStrOffset: 1380, .AliasCondStart: 303, .NumOperands: 3, .NumConds: 3 },
1904 {.AsmStrOffset: 1395, .AliasCondStart: 306, .NumOperands: 3, .NumConds: 3 },
1905 {.AsmStrOffset: 1410, .AliasCondStart: 309, .NumOperands: 3, .NumConds: 3 },
1906 // SP::BPXCCANT - 104
1907 {.AsmStrOffset: 1426, .AliasCondStart: 312, .NumOperands: 2, .NumConds: 2 },
1908 {.AsmStrOffset: 1443, .AliasCondStart: 314, .NumOperands: 2, .NumConds: 2 },
1909 {.AsmStrOffset: 1460, .AliasCondStart: 316, .NumOperands: 2, .NumConds: 2 },
1910 {.AsmStrOffset: 1478, .AliasCondStart: 318, .NumOperands: 2, .NumConds: 2 },
1911 {.AsmStrOffset: 1495, .AliasCondStart: 320, .NumOperands: 2, .NumConds: 2 },
1912 {.AsmStrOffset: 1512, .AliasCondStart: 322, .NumOperands: 2, .NumConds: 2 },
1913 {.AsmStrOffset: 1530, .AliasCondStart: 324, .NumOperands: 2, .NumConds: 2 },
1914 {.AsmStrOffset: 1548, .AliasCondStart: 326, .NumOperands: 2, .NumConds: 2 },
1915 {.AsmStrOffset: 1565, .AliasCondStart: 328, .NumOperands: 2, .NumConds: 2 },
1916 {.AsmStrOffset: 1583, .AliasCondStart: 330, .NumOperands: 2, .NumConds: 2 },
1917 {.AsmStrOffset: 1602, .AliasCondStart: 332, .NumOperands: 2, .NumConds: 2 },
1918 {.AsmStrOffset: 1620, .AliasCondStart: 334, .NumOperands: 2, .NumConds: 2 },
1919 {.AsmStrOffset: 1638, .AliasCondStart: 336, .NumOperands: 2, .NumConds: 2 },
1920 {.AsmStrOffset: 1657, .AliasCondStart: 338, .NumOperands: 2, .NumConds: 2 },
1921 {.AsmStrOffset: 1676, .AliasCondStart: 340, .NumOperands: 2, .NumConds: 2 },
1922 {.AsmStrOffset: 1694, .AliasCondStart: 342, .NumOperands: 2, .NumConds: 2 },
1923 // SP::BPXCCNT - 120
1924 {.AsmStrOffset: 1712, .AliasCondStart: 344, .NumOperands: 2, .NumConds: 2 },
1925 {.AsmStrOffset: 1727, .AliasCondStart: 346, .NumOperands: 2, .NumConds: 2 },
1926 {.AsmStrOffset: 1742, .AliasCondStart: 348, .NumOperands: 2, .NumConds: 2 },
1927 {.AsmStrOffset: 1758, .AliasCondStart: 350, .NumOperands: 2, .NumConds: 2 },
1928 {.AsmStrOffset: 1773, .AliasCondStart: 352, .NumOperands: 2, .NumConds: 2 },
1929 {.AsmStrOffset: 1788, .AliasCondStart: 354, .NumOperands: 2, .NumConds: 2 },
1930 {.AsmStrOffset: 1804, .AliasCondStart: 356, .NumOperands: 2, .NumConds: 2 },
1931 {.AsmStrOffset: 1820, .AliasCondStart: 358, .NumOperands: 2, .NumConds: 2 },
1932 {.AsmStrOffset: 1835, .AliasCondStart: 360, .NumOperands: 2, .NumConds: 2 },
1933 {.AsmStrOffset: 1851, .AliasCondStart: 362, .NumOperands: 2, .NumConds: 2 },
1934 {.AsmStrOffset: 1868, .AliasCondStart: 364, .NumOperands: 2, .NumConds: 2 },
1935 {.AsmStrOffset: 1884, .AliasCondStart: 366, .NumOperands: 2, .NumConds: 2 },
1936 {.AsmStrOffset: 1900, .AliasCondStart: 368, .NumOperands: 2, .NumConds: 2 },
1937 {.AsmStrOffset: 1917, .AliasCondStart: 370, .NumOperands: 2, .NumConds: 2 },
1938 {.AsmStrOffset: 1934, .AliasCondStart: 372, .NumOperands: 2, .NumConds: 2 },
1939 {.AsmStrOffset: 1950, .AliasCondStart: 374, .NumOperands: 2, .NumConds: 2 },
1940 // SP::CASArr - 136
1941 {.AsmStrOffset: 1966, .AliasCondStart: 376, .NumOperands: 5, .NumConds: 6 },
1942 {.AsmStrOffset: 1983, .AliasCondStart: 382, .NumOperands: 5, .NumConds: 6 },
1943 // SP::CASXArr - 138
1944 {.AsmStrOffset: 2001, .AliasCondStart: 388, .NumOperands: 5, .NumConds: 6 },
1945 {.AsmStrOffset: 2019, .AliasCondStart: 394, .NumOperands: 5, .NumConds: 6 },
1946 // SP::FMOVD_ICC - 140
1947 {.AsmStrOffset: 2038, .AliasCondStart: 400, .NumOperands: 4, .NumConds: 5 },
1948 {.AsmStrOffset: 2058, .AliasCondStart: 405, .NumOperands: 4, .NumConds: 5 },
1949 {.AsmStrOffset: 2078, .AliasCondStart: 410, .NumOperands: 4, .NumConds: 5 },
1950 {.AsmStrOffset: 2099, .AliasCondStart: 415, .NumOperands: 4, .NumConds: 5 },
1951 {.AsmStrOffset: 2119, .AliasCondStart: 420, .NumOperands: 4, .NumConds: 5 },
1952 {.AsmStrOffset: 2139, .AliasCondStart: 425, .NumOperands: 4, .NumConds: 5 },
1953 {.AsmStrOffset: 2160, .AliasCondStart: 430, .NumOperands: 4, .NumConds: 5 },
1954 {.AsmStrOffset: 2181, .AliasCondStart: 435, .NumOperands: 4, .NumConds: 5 },
1955 {.AsmStrOffset: 2201, .AliasCondStart: 440, .NumOperands: 4, .NumConds: 5 },
1956 {.AsmStrOffset: 2222, .AliasCondStart: 445, .NumOperands: 4, .NumConds: 5 },
1957 {.AsmStrOffset: 2244, .AliasCondStart: 450, .NumOperands: 4, .NumConds: 5 },
1958 {.AsmStrOffset: 2265, .AliasCondStart: 455, .NumOperands: 4, .NumConds: 5 },
1959 {.AsmStrOffset: 2286, .AliasCondStart: 460, .NumOperands: 4, .NumConds: 5 },
1960 {.AsmStrOffset: 2308, .AliasCondStart: 465, .NumOperands: 4, .NumConds: 5 },
1961 {.AsmStrOffset: 2330, .AliasCondStart: 470, .NumOperands: 4, .NumConds: 5 },
1962 {.AsmStrOffset: 2351, .AliasCondStart: 475, .NumOperands: 4, .NumConds: 5 },
1963 // SP::FMOVD_XCC - 156
1964 {.AsmStrOffset: 2372, .AliasCondStart: 480, .NumOperands: 4, .NumConds: 4 },
1965 {.AsmStrOffset: 2392, .AliasCondStart: 484, .NumOperands: 4, .NumConds: 4 },
1966 {.AsmStrOffset: 2412, .AliasCondStart: 488, .NumOperands: 4, .NumConds: 4 },
1967 {.AsmStrOffset: 2433, .AliasCondStart: 492, .NumOperands: 4, .NumConds: 4 },
1968 {.AsmStrOffset: 2453, .AliasCondStart: 496, .NumOperands: 4, .NumConds: 4 },
1969 {.AsmStrOffset: 2473, .AliasCondStart: 500, .NumOperands: 4, .NumConds: 4 },
1970 {.AsmStrOffset: 2494, .AliasCondStart: 504, .NumOperands: 4, .NumConds: 4 },
1971 {.AsmStrOffset: 2515, .AliasCondStart: 508, .NumOperands: 4, .NumConds: 4 },
1972 {.AsmStrOffset: 2535, .AliasCondStart: 512, .NumOperands: 4, .NumConds: 4 },
1973 {.AsmStrOffset: 2556, .AliasCondStart: 516, .NumOperands: 4, .NumConds: 4 },
1974 {.AsmStrOffset: 2578, .AliasCondStart: 520, .NumOperands: 4, .NumConds: 4 },
1975 {.AsmStrOffset: 2599, .AliasCondStart: 524, .NumOperands: 4, .NumConds: 4 },
1976 {.AsmStrOffset: 2620, .AliasCondStart: 528, .NumOperands: 4, .NumConds: 4 },
1977 {.AsmStrOffset: 2642, .AliasCondStart: 532, .NumOperands: 4, .NumConds: 4 },
1978 {.AsmStrOffset: 2664, .AliasCondStart: 536, .NumOperands: 4, .NumConds: 4 },
1979 {.AsmStrOffset: 2685, .AliasCondStart: 540, .NumOperands: 4, .NumConds: 4 },
1980 // SP::FMOVQ_ICC - 172
1981 {.AsmStrOffset: 2706, .AliasCondStart: 544, .NumOperands: 4, .NumConds: 5 },
1982 {.AsmStrOffset: 2726, .AliasCondStart: 549, .NumOperands: 4, .NumConds: 5 },
1983 {.AsmStrOffset: 2746, .AliasCondStart: 554, .NumOperands: 4, .NumConds: 5 },
1984 {.AsmStrOffset: 2767, .AliasCondStart: 559, .NumOperands: 4, .NumConds: 5 },
1985 {.AsmStrOffset: 2787, .AliasCondStart: 564, .NumOperands: 4, .NumConds: 5 },
1986 {.AsmStrOffset: 2807, .AliasCondStart: 569, .NumOperands: 4, .NumConds: 5 },
1987 {.AsmStrOffset: 2828, .AliasCondStart: 574, .NumOperands: 4, .NumConds: 5 },
1988 {.AsmStrOffset: 2849, .AliasCondStart: 579, .NumOperands: 4, .NumConds: 5 },
1989 {.AsmStrOffset: 2869, .AliasCondStart: 584, .NumOperands: 4, .NumConds: 5 },
1990 {.AsmStrOffset: 2890, .AliasCondStart: 589, .NumOperands: 4, .NumConds: 5 },
1991 {.AsmStrOffset: 2912, .AliasCondStart: 594, .NumOperands: 4, .NumConds: 5 },
1992 {.AsmStrOffset: 2933, .AliasCondStart: 599, .NumOperands: 4, .NumConds: 5 },
1993 {.AsmStrOffset: 2954, .AliasCondStart: 604, .NumOperands: 4, .NumConds: 5 },
1994 {.AsmStrOffset: 2976, .AliasCondStart: 609, .NumOperands: 4, .NumConds: 5 },
1995 {.AsmStrOffset: 2998, .AliasCondStart: 614, .NumOperands: 4, .NumConds: 5 },
1996 {.AsmStrOffset: 3019, .AliasCondStart: 619, .NumOperands: 4, .NumConds: 5 },
1997 // SP::FMOVQ_XCC - 188
1998 {.AsmStrOffset: 3040, .AliasCondStart: 624, .NumOperands: 4, .NumConds: 4 },
1999 {.AsmStrOffset: 3060, .AliasCondStart: 628, .NumOperands: 4, .NumConds: 4 },
2000 {.AsmStrOffset: 3080, .AliasCondStart: 632, .NumOperands: 4, .NumConds: 4 },
2001 {.AsmStrOffset: 3101, .AliasCondStart: 636, .NumOperands: 4, .NumConds: 4 },
2002 {.AsmStrOffset: 3121, .AliasCondStart: 640, .NumOperands: 4, .NumConds: 4 },
2003 {.AsmStrOffset: 3141, .AliasCondStart: 644, .NumOperands: 4, .NumConds: 4 },
2004 {.AsmStrOffset: 3162, .AliasCondStart: 648, .NumOperands: 4, .NumConds: 4 },
2005 {.AsmStrOffset: 3183, .AliasCondStart: 652, .NumOperands: 4, .NumConds: 4 },
2006 {.AsmStrOffset: 3203, .AliasCondStart: 656, .NumOperands: 4, .NumConds: 4 },
2007 {.AsmStrOffset: 3224, .AliasCondStart: 660, .NumOperands: 4, .NumConds: 4 },
2008 {.AsmStrOffset: 3246, .AliasCondStart: 664, .NumOperands: 4, .NumConds: 4 },
2009 {.AsmStrOffset: 3267, .AliasCondStart: 668, .NumOperands: 4, .NumConds: 4 },
2010 {.AsmStrOffset: 3288, .AliasCondStart: 672, .NumOperands: 4, .NumConds: 4 },
2011 {.AsmStrOffset: 3310, .AliasCondStart: 676, .NumOperands: 4, .NumConds: 4 },
2012 {.AsmStrOffset: 3332, .AliasCondStart: 680, .NumOperands: 4, .NumConds: 4 },
2013 {.AsmStrOffset: 3353, .AliasCondStart: 684, .NumOperands: 4, .NumConds: 4 },
2014 // SP::FMOVRD - 204
2015 {.AsmStrOffset: 3374, .AliasCondStart: 688, .NumOperands: 5, .NumConds: 5 },
2016 {.AsmStrOffset: 3395, .AliasCondStart: 693, .NumOperands: 5, .NumConds: 5 },
2017 {.AsmStrOffset: 3415, .AliasCondStart: 698, .NumOperands: 5, .NumConds: 5 },
2018 {.AsmStrOffset: 3435, .AliasCondStart: 703, .NumOperands: 5, .NumConds: 5 },
2019 // SP::FMOVRQ - 208
2020 {.AsmStrOffset: 3456, .AliasCondStart: 708, .NumOperands: 5, .NumConds: 5 },
2021 {.AsmStrOffset: 3477, .AliasCondStart: 713, .NumOperands: 5, .NumConds: 5 },
2022 {.AsmStrOffset: 3497, .AliasCondStart: 718, .NumOperands: 5, .NumConds: 5 },
2023 {.AsmStrOffset: 3517, .AliasCondStart: 723, .NumOperands: 5, .NumConds: 5 },
2024 // SP::FMOVRS - 212
2025 {.AsmStrOffset: 3538, .AliasCondStart: 728, .NumOperands: 5, .NumConds: 5 },
2026 {.AsmStrOffset: 3559, .AliasCondStart: 733, .NumOperands: 5, .NumConds: 5 },
2027 {.AsmStrOffset: 3579, .AliasCondStart: 738, .NumOperands: 5, .NumConds: 5 },
2028 {.AsmStrOffset: 3599, .AliasCondStart: 743, .NumOperands: 5, .NumConds: 5 },
2029 // SP::FMOVS_ICC - 216
2030 {.AsmStrOffset: 3620, .AliasCondStart: 748, .NumOperands: 4, .NumConds: 5 },
2031 {.AsmStrOffset: 3640, .AliasCondStart: 753, .NumOperands: 4, .NumConds: 5 },
2032 {.AsmStrOffset: 3660, .AliasCondStart: 758, .NumOperands: 4, .NumConds: 5 },
2033 {.AsmStrOffset: 3681, .AliasCondStart: 763, .NumOperands: 4, .NumConds: 5 },
2034 {.AsmStrOffset: 3701, .AliasCondStart: 768, .NumOperands: 4, .NumConds: 5 },
2035 {.AsmStrOffset: 3721, .AliasCondStart: 773, .NumOperands: 4, .NumConds: 5 },
2036 {.AsmStrOffset: 3742, .AliasCondStart: 778, .NumOperands: 4, .NumConds: 5 },
2037 {.AsmStrOffset: 3763, .AliasCondStart: 783, .NumOperands: 4, .NumConds: 5 },
2038 {.AsmStrOffset: 3783, .AliasCondStart: 788, .NumOperands: 4, .NumConds: 5 },
2039 {.AsmStrOffset: 3804, .AliasCondStart: 793, .NumOperands: 4, .NumConds: 5 },
2040 {.AsmStrOffset: 3826, .AliasCondStart: 798, .NumOperands: 4, .NumConds: 5 },
2041 {.AsmStrOffset: 3847, .AliasCondStart: 803, .NumOperands: 4, .NumConds: 5 },
2042 {.AsmStrOffset: 3868, .AliasCondStart: 808, .NumOperands: 4, .NumConds: 5 },
2043 {.AsmStrOffset: 3890, .AliasCondStart: 813, .NumOperands: 4, .NumConds: 5 },
2044 {.AsmStrOffset: 3912, .AliasCondStart: 818, .NumOperands: 4, .NumConds: 5 },
2045 {.AsmStrOffset: 3933, .AliasCondStart: 823, .NumOperands: 4, .NumConds: 5 },
2046 // SP::FMOVS_XCC - 232
2047 {.AsmStrOffset: 3954, .AliasCondStart: 828, .NumOperands: 4, .NumConds: 4 },
2048 {.AsmStrOffset: 3974, .AliasCondStart: 832, .NumOperands: 4, .NumConds: 4 },
2049 {.AsmStrOffset: 3994, .AliasCondStart: 836, .NumOperands: 4, .NumConds: 4 },
2050 {.AsmStrOffset: 4015, .AliasCondStart: 840, .NumOperands: 4, .NumConds: 4 },
2051 {.AsmStrOffset: 4035, .AliasCondStart: 844, .NumOperands: 4, .NumConds: 4 },
2052 {.AsmStrOffset: 4055, .AliasCondStart: 848, .NumOperands: 4, .NumConds: 4 },
2053 {.AsmStrOffset: 4076, .AliasCondStart: 852, .NumOperands: 4, .NumConds: 4 },
2054 {.AsmStrOffset: 4097, .AliasCondStart: 856, .NumOperands: 4, .NumConds: 4 },
2055 {.AsmStrOffset: 4117, .AliasCondStart: 860, .NumOperands: 4, .NumConds: 4 },
2056 {.AsmStrOffset: 4138, .AliasCondStart: 864, .NumOperands: 4, .NumConds: 4 },
2057 {.AsmStrOffset: 4160, .AliasCondStart: 868, .NumOperands: 4, .NumConds: 4 },
2058 {.AsmStrOffset: 4181, .AliasCondStart: 872, .NumOperands: 4, .NumConds: 4 },
2059 {.AsmStrOffset: 4202, .AliasCondStart: 876, .NumOperands: 4, .NumConds: 4 },
2060 {.AsmStrOffset: 4224, .AliasCondStart: 880, .NumOperands: 4, .NumConds: 4 },
2061 {.AsmStrOffset: 4246, .AliasCondStart: 884, .NumOperands: 4, .NumConds: 4 },
2062 {.AsmStrOffset: 4267, .AliasCondStart: 888, .NumOperands: 4, .NumConds: 4 },
2063 // SP::MOVICCri - 248
2064 {.AsmStrOffset: 4288, .AliasCondStart: 892, .NumOperands: 4, .NumConds: 5 },
2065 {.AsmStrOffset: 4306, .AliasCondStart: 897, .NumOperands: 4, .NumConds: 5 },
2066 {.AsmStrOffset: 4324, .AliasCondStart: 902, .NumOperands: 4, .NumConds: 5 },
2067 {.AsmStrOffset: 4343, .AliasCondStart: 907, .NumOperands: 4, .NumConds: 5 },
2068 {.AsmStrOffset: 4361, .AliasCondStart: 912, .NumOperands: 4, .NumConds: 5 },
2069 {.AsmStrOffset: 4379, .AliasCondStart: 917, .NumOperands: 4, .NumConds: 5 },
2070 {.AsmStrOffset: 4398, .AliasCondStart: 922, .NumOperands: 4, .NumConds: 5 },
2071 {.AsmStrOffset: 4417, .AliasCondStart: 927, .NumOperands: 4, .NumConds: 5 },
2072 {.AsmStrOffset: 4435, .AliasCondStart: 932, .NumOperands: 4, .NumConds: 5 },
2073 {.AsmStrOffset: 4454, .AliasCondStart: 937, .NumOperands: 4, .NumConds: 5 },
2074 {.AsmStrOffset: 4474, .AliasCondStart: 942, .NumOperands: 4, .NumConds: 5 },
2075 {.AsmStrOffset: 4493, .AliasCondStart: 947, .NumOperands: 4, .NumConds: 5 },
2076 {.AsmStrOffset: 4512, .AliasCondStart: 952, .NumOperands: 4, .NumConds: 5 },
2077 {.AsmStrOffset: 4532, .AliasCondStart: 957, .NumOperands: 4, .NumConds: 5 },
2078 {.AsmStrOffset: 4552, .AliasCondStart: 962, .NumOperands: 4, .NumConds: 5 },
2079 {.AsmStrOffset: 4571, .AliasCondStart: 967, .NumOperands: 4, .NumConds: 5 },
2080 // SP::MOVICCrr - 264
2081 {.AsmStrOffset: 4288, .AliasCondStart: 972, .NumOperands: 4, .NumConds: 5 },
2082 {.AsmStrOffset: 4306, .AliasCondStart: 977, .NumOperands: 4, .NumConds: 5 },
2083 {.AsmStrOffset: 4324, .AliasCondStart: 982, .NumOperands: 4, .NumConds: 5 },
2084 {.AsmStrOffset: 4343, .AliasCondStart: 987, .NumOperands: 4, .NumConds: 5 },
2085 {.AsmStrOffset: 4361, .AliasCondStart: 992, .NumOperands: 4, .NumConds: 5 },
2086 {.AsmStrOffset: 4379, .AliasCondStart: 997, .NumOperands: 4, .NumConds: 5 },
2087 {.AsmStrOffset: 4398, .AliasCondStart: 1002, .NumOperands: 4, .NumConds: 5 },
2088 {.AsmStrOffset: 4417, .AliasCondStart: 1007, .NumOperands: 4, .NumConds: 5 },
2089 {.AsmStrOffset: 4435, .AliasCondStart: 1012, .NumOperands: 4, .NumConds: 5 },
2090 {.AsmStrOffset: 4454, .AliasCondStart: 1017, .NumOperands: 4, .NumConds: 5 },
2091 {.AsmStrOffset: 4474, .AliasCondStart: 1022, .NumOperands: 4, .NumConds: 5 },
2092 {.AsmStrOffset: 4493, .AliasCondStart: 1027, .NumOperands: 4, .NumConds: 5 },
2093 {.AsmStrOffset: 4512, .AliasCondStart: 1032, .NumOperands: 4, .NumConds: 5 },
2094 {.AsmStrOffset: 4532, .AliasCondStart: 1037, .NumOperands: 4, .NumConds: 5 },
2095 {.AsmStrOffset: 4552, .AliasCondStart: 1042, .NumOperands: 4, .NumConds: 5 },
2096 {.AsmStrOffset: 4571, .AliasCondStart: 1047, .NumOperands: 4, .NumConds: 5 },
2097 // SP::MOVRri - 280
2098 {.AsmStrOffset: 4590, .AliasCondStart: 1052, .NumOperands: 5, .NumConds: 5 },
2099 {.AsmStrOffset: 4609, .AliasCondStart: 1057, .NumOperands: 5, .NumConds: 5 },
2100 {.AsmStrOffset: 4627, .AliasCondStart: 1062, .NumOperands: 5, .NumConds: 5 },
2101 {.AsmStrOffset: 4645, .AliasCondStart: 1067, .NumOperands: 5, .NumConds: 5 },
2102 // SP::MOVRrr - 284
2103 {.AsmStrOffset: 4590, .AliasCondStart: 1072, .NumOperands: 5, .NumConds: 5 },
2104 {.AsmStrOffset: 4609, .AliasCondStart: 1077, .NumOperands: 5, .NumConds: 5 },
2105 {.AsmStrOffset: 4627, .AliasCondStart: 1082, .NumOperands: 5, .NumConds: 5 },
2106 {.AsmStrOffset: 4645, .AliasCondStart: 1087, .NumOperands: 5, .NumConds: 5 },
2107 // SP::MOVXCCri - 288
2108 {.AsmStrOffset: 4664, .AliasCondStart: 1092, .NumOperands: 4, .NumConds: 4 },
2109 {.AsmStrOffset: 4682, .AliasCondStart: 1096, .NumOperands: 4, .NumConds: 4 },
2110 {.AsmStrOffset: 4700, .AliasCondStart: 1100, .NumOperands: 4, .NumConds: 4 },
2111 {.AsmStrOffset: 4719, .AliasCondStart: 1104, .NumOperands: 4, .NumConds: 4 },
2112 {.AsmStrOffset: 4737, .AliasCondStart: 1108, .NumOperands: 4, .NumConds: 4 },
2113 {.AsmStrOffset: 4755, .AliasCondStart: 1112, .NumOperands: 4, .NumConds: 4 },
2114 {.AsmStrOffset: 4774, .AliasCondStart: 1116, .NumOperands: 4, .NumConds: 4 },
2115 {.AsmStrOffset: 4793, .AliasCondStart: 1120, .NumOperands: 4, .NumConds: 4 },
2116 {.AsmStrOffset: 4811, .AliasCondStart: 1124, .NumOperands: 4, .NumConds: 4 },
2117 {.AsmStrOffset: 4830, .AliasCondStart: 1128, .NumOperands: 4, .NumConds: 4 },
2118 {.AsmStrOffset: 4850, .AliasCondStart: 1132, .NumOperands: 4, .NumConds: 4 },
2119 {.AsmStrOffset: 4869, .AliasCondStart: 1136, .NumOperands: 4, .NumConds: 4 },
2120 {.AsmStrOffset: 4888, .AliasCondStart: 1140, .NumOperands: 4, .NumConds: 4 },
2121 {.AsmStrOffset: 4908, .AliasCondStart: 1144, .NumOperands: 4, .NumConds: 4 },
2122 {.AsmStrOffset: 4928, .AliasCondStart: 1148, .NumOperands: 4, .NumConds: 4 },
2123 {.AsmStrOffset: 4947, .AliasCondStart: 1152, .NumOperands: 4, .NumConds: 4 },
2124 // SP::MOVXCCrr - 304
2125 {.AsmStrOffset: 4664, .AliasCondStart: 1156, .NumOperands: 4, .NumConds: 4 },
2126 {.AsmStrOffset: 4682, .AliasCondStart: 1160, .NumOperands: 4, .NumConds: 4 },
2127 {.AsmStrOffset: 4700, .AliasCondStart: 1164, .NumOperands: 4, .NumConds: 4 },
2128 {.AsmStrOffset: 4719, .AliasCondStart: 1168, .NumOperands: 4, .NumConds: 4 },
2129 {.AsmStrOffset: 4737, .AliasCondStart: 1172, .NumOperands: 4, .NumConds: 4 },
2130 {.AsmStrOffset: 4755, .AliasCondStart: 1176, .NumOperands: 4, .NumConds: 4 },
2131 {.AsmStrOffset: 4774, .AliasCondStart: 1180, .NumOperands: 4, .NumConds: 4 },
2132 {.AsmStrOffset: 4793, .AliasCondStart: 1184, .NumOperands: 4, .NumConds: 4 },
2133 {.AsmStrOffset: 4811, .AliasCondStart: 1188, .NumOperands: 4, .NumConds: 4 },
2134 {.AsmStrOffset: 4830, .AliasCondStart: 1192, .NumOperands: 4, .NumConds: 4 },
2135 {.AsmStrOffset: 4850, .AliasCondStart: 1196, .NumOperands: 4, .NumConds: 4 },
2136 {.AsmStrOffset: 4869, .AliasCondStart: 1200, .NumOperands: 4, .NumConds: 4 },
2137 {.AsmStrOffset: 4888, .AliasCondStart: 1204, .NumOperands: 4, .NumConds: 4 },
2138 {.AsmStrOffset: 4908, .AliasCondStart: 1208, .NumOperands: 4, .NumConds: 4 },
2139 {.AsmStrOffset: 4928, .AliasCondStart: 1212, .NumOperands: 4, .NumConds: 4 },
2140 {.AsmStrOffset: 4947, .AliasCondStart: 1216, .NumOperands: 4, .NumConds: 4 },
2141 // SP::ORCCrr - 320
2142 {.AsmStrOffset: 4966, .AliasCondStart: 1220, .NumOperands: 3, .NumConds: 3 },
2143 // SP::ORri - 321
2144 {.AsmStrOffset: 4973, .AliasCondStart: 1223, .NumOperands: 3, .NumConds: 2 },
2145 // SP::ORrr - 322
2146 {.AsmStrOffset: 4973, .AliasCondStart: 1225, .NumOperands: 3, .NumConds: 3 },
2147 // SP::RESTORErr - 323
2148 {.AsmStrOffset: 4984, .AliasCondStart: 1228, .NumOperands: 3, .NumConds: 3 },
2149 // SP::RET - 324
2150 {.AsmStrOffset: 4992, .AliasCondStart: 1231, .NumOperands: 1, .NumConds: 1 },
2151 // SP::RETL - 325
2152 {.AsmStrOffset: 4996, .AliasCondStart: 1232, .NumOperands: 1, .NumConds: 1 },
2153 // SP::SAVErr - 326
2154 {.AsmStrOffset: 5001, .AliasCondStart: 1233, .NumOperands: 3, .NumConds: 3 },
2155 // SP::SUBCCri - 327
2156 {.AsmStrOffset: 5006, .AliasCondStart: 1236, .NumOperands: 3, .NumConds: 2 },
2157 // SP::SUBCCrr - 328
2158 {.AsmStrOffset: 5006, .AliasCondStart: 1238, .NumOperands: 3, .NumConds: 3 },
2159 // SP::TICCri - 329
2160 {.AsmStrOffset: 5017, .AliasCondStart: 1241, .NumOperands: 3, .NumConds: 4 },
2161 {.AsmStrOffset: 5029, .AliasCondStart: 1245, .NumOperands: 3, .NumConds: 4 },
2162 {.AsmStrOffset: 5046, .AliasCondStart: 1249, .NumOperands: 3, .NumConds: 4 },
2163 {.AsmStrOffset: 5058, .AliasCondStart: 1253, .NumOperands: 3, .NumConds: 4 },
2164 {.AsmStrOffset: 5075, .AliasCondStart: 1257, .NumOperands: 3, .NumConds: 4 },
2165 {.AsmStrOffset: 5088, .AliasCondStart: 1261, .NumOperands: 3, .NumConds: 4 },
2166 {.AsmStrOffset: 5106, .AliasCondStart: 1265, .NumOperands: 3, .NumConds: 4 },
2167 {.AsmStrOffset: 5118, .AliasCondStart: 1269, .NumOperands: 3, .NumConds: 4 },
2168 {.AsmStrOffset: 5135, .AliasCondStart: 1273, .NumOperands: 3, .NumConds: 4 },
2169 {.AsmStrOffset: 5147, .AliasCondStart: 1277, .NumOperands: 3, .NumConds: 4 },
2170 {.AsmStrOffset: 5164, .AliasCondStart: 1281, .NumOperands: 3, .NumConds: 4 },
2171 {.AsmStrOffset: 5177, .AliasCondStart: 1285, .NumOperands: 3, .NumConds: 4 },
2172 {.AsmStrOffset: 5195, .AliasCondStart: 1289, .NumOperands: 3, .NumConds: 4 },
2173 {.AsmStrOffset: 5208, .AliasCondStart: 1293, .NumOperands: 3, .NumConds: 4 },
2174 {.AsmStrOffset: 5226, .AliasCondStart: 1297, .NumOperands: 3, .NumConds: 4 },
2175 {.AsmStrOffset: 5238, .AliasCondStart: 1301, .NumOperands: 3, .NumConds: 4 },
2176 {.AsmStrOffset: 5255, .AliasCondStart: 1305, .NumOperands: 3, .NumConds: 4 },
2177 {.AsmStrOffset: 5268, .AliasCondStart: 1309, .NumOperands: 3, .NumConds: 4 },
2178 {.AsmStrOffset: 5286, .AliasCondStart: 1313, .NumOperands: 3, .NumConds: 4 },
2179 {.AsmStrOffset: 5300, .AliasCondStart: 1317, .NumOperands: 3, .NumConds: 4 },
2180 {.AsmStrOffset: 5319, .AliasCondStart: 1321, .NumOperands: 3, .NumConds: 4 },
2181 {.AsmStrOffset: 5332, .AliasCondStart: 1325, .NumOperands: 3, .NumConds: 4 },
2182 {.AsmStrOffset: 5350, .AliasCondStart: 1329, .NumOperands: 3, .NumConds: 4 },
2183 {.AsmStrOffset: 5363, .AliasCondStart: 1333, .NumOperands: 3, .NumConds: 4 },
2184 {.AsmStrOffset: 5381, .AliasCondStart: 1337, .NumOperands: 3, .NumConds: 4 },
2185 {.AsmStrOffset: 5395, .AliasCondStart: 1341, .NumOperands: 3, .NumConds: 4 },
2186 {.AsmStrOffset: 5414, .AliasCondStart: 1345, .NumOperands: 3, .NumConds: 4 },
2187 {.AsmStrOffset: 5428, .AliasCondStart: 1349, .NumOperands: 3, .NumConds: 4 },
2188 {.AsmStrOffset: 5447, .AliasCondStart: 1353, .NumOperands: 3, .NumConds: 4 },
2189 {.AsmStrOffset: 5460, .AliasCondStart: 1357, .NumOperands: 3, .NumConds: 4 },
2190 {.AsmStrOffset: 5478, .AliasCondStart: 1361, .NumOperands: 3, .NumConds: 4 },
2191 {.AsmStrOffset: 5491, .AliasCondStart: 1365, .NumOperands: 3, .NumConds: 4 },
2192 // SP::TICCrr - 361
2193 {.AsmStrOffset: 5017, .AliasCondStart: 1369, .NumOperands: 3, .NumConds: 4 },
2194 {.AsmStrOffset: 5029, .AliasCondStart: 1373, .NumOperands: 3, .NumConds: 4 },
2195 {.AsmStrOffset: 5046, .AliasCondStart: 1377, .NumOperands: 3, .NumConds: 4 },
2196 {.AsmStrOffset: 5058, .AliasCondStart: 1381, .NumOperands: 3, .NumConds: 4 },
2197 {.AsmStrOffset: 5075, .AliasCondStart: 1385, .NumOperands: 3, .NumConds: 4 },
2198 {.AsmStrOffset: 5088, .AliasCondStart: 1389, .NumOperands: 3, .NumConds: 4 },
2199 {.AsmStrOffset: 5106, .AliasCondStart: 1393, .NumOperands: 3, .NumConds: 4 },
2200 {.AsmStrOffset: 5118, .AliasCondStart: 1397, .NumOperands: 3, .NumConds: 4 },
2201 {.AsmStrOffset: 5135, .AliasCondStart: 1401, .NumOperands: 3, .NumConds: 4 },
2202 {.AsmStrOffset: 5147, .AliasCondStart: 1405, .NumOperands: 3, .NumConds: 4 },
2203 {.AsmStrOffset: 5164, .AliasCondStart: 1409, .NumOperands: 3, .NumConds: 4 },
2204 {.AsmStrOffset: 5177, .AliasCondStart: 1413, .NumOperands: 3, .NumConds: 4 },
2205 {.AsmStrOffset: 5195, .AliasCondStart: 1417, .NumOperands: 3, .NumConds: 4 },
2206 {.AsmStrOffset: 5208, .AliasCondStart: 1421, .NumOperands: 3, .NumConds: 4 },
2207 {.AsmStrOffset: 5226, .AliasCondStart: 1425, .NumOperands: 3, .NumConds: 4 },
2208 {.AsmStrOffset: 5238, .AliasCondStart: 1429, .NumOperands: 3, .NumConds: 4 },
2209 {.AsmStrOffset: 5255, .AliasCondStart: 1433, .NumOperands: 3, .NumConds: 4 },
2210 {.AsmStrOffset: 5268, .AliasCondStart: 1437, .NumOperands: 3, .NumConds: 4 },
2211 {.AsmStrOffset: 5286, .AliasCondStart: 1441, .NumOperands: 3, .NumConds: 4 },
2212 {.AsmStrOffset: 5300, .AliasCondStart: 1445, .NumOperands: 3, .NumConds: 4 },
2213 {.AsmStrOffset: 5319, .AliasCondStart: 1449, .NumOperands: 3, .NumConds: 4 },
2214 {.AsmStrOffset: 5332, .AliasCondStart: 1453, .NumOperands: 3, .NumConds: 4 },
2215 {.AsmStrOffset: 5350, .AliasCondStart: 1457, .NumOperands: 3, .NumConds: 4 },
2216 {.AsmStrOffset: 5363, .AliasCondStart: 1461, .NumOperands: 3, .NumConds: 4 },
2217 {.AsmStrOffset: 5381, .AliasCondStart: 1465, .NumOperands: 3, .NumConds: 4 },
2218 {.AsmStrOffset: 5395, .AliasCondStart: 1469, .NumOperands: 3, .NumConds: 4 },
2219 {.AsmStrOffset: 5414, .AliasCondStart: 1473, .NumOperands: 3, .NumConds: 4 },
2220 {.AsmStrOffset: 5428, .AliasCondStart: 1477, .NumOperands: 3, .NumConds: 4 },
2221 {.AsmStrOffset: 5447, .AliasCondStart: 1481, .NumOperands: 3, .NumConds: 4 },
2222 {.AsmStrOffset: 5460, .AliasCondStart: 1485, .NumOperands: 3, .NumConds: 4 },
2223 {.AsmStrOffset: 5478, .AliasCondStart: 1489, .NumOperands: 3, .NumConds: 4 },
2224 {.AsmStrOffset: 5491, .AliasCondStart: 1493, .NumOperands: 3, .NumConds: 4 },
2225 // SP::TRAPri - 393
2226 {.AsmStrOffset: 5509, .AliasCondStart: 1497, .NumOperands: 3, .NumConds: 3 },
2227 {.AsmStrOffset: 5515, .AliasCondStart: 1500, .NumOperands: 3, .NumConds: 3 },
2228 {.AsmStrOffset: 5526, .AliasCondStart: 1503, .NumOperands: 3, .NumConds: 3 },
2229 {.AsmStrOffset: 5532, .AliasCondStart: 1506, .NumOperands: 3, .NumConds: 3 },
2230 {.AsmStrOffset: 5543, .AliasCondStart: 1509, .NumOperands: 3, .NumConds: 3 },
2231 {.AsmStrOffset: 5550, .AliasCondStart: 1512, .NumOperands: 3, .NumConds: 3 },
2232 {.AsmStrOffset: 5562, .AliasCondStart: 1515, .NumOperands: 3, .NumConds: 3 },
2233 {.AsmStrOffset: 5568, .AliasCondStart: 1518, .NumOperands: 3, .NumConds: 3 },
2234 {.AsmStrOffset: 5579, .AliasCondStart: 1521, .NumOperands: 3, .NumConds: 3 },
2235 {.AsmStrOffset: 5585, .AliasCondStart: 1524, .NumOperands: 3, .NumConds: 3 },
2236 {.AsmStrOffset: 5596, .AliasCondStart: 1527, .NumOperands: 3, .NumConds: 3 },
2237 {.AsmStrOffset: 5603, .AliasCondStart: 1530, .NumOperands: 3, .NumConds: 3 },
2238 {.AsmStrOffset: 5615, .AliasCondStart: 1533, .NumOperands: 3, .NumConds: 3 },
2239 {.AsmStrOffset: 5622, .AliasCondStart: 1536, .NumOperands: 3, .NumConds: 3 },
2240 {.AsmStrOffset: 5634, .AliasCondStart: 1539, .NumOperands: 3, .NumConds: 3 },
2241 {.AsmStrOffset: 5640, .AliasCondStart: 1542, .NumOperands: 3, .NumConds: 3 },
2242 {.AsmStrOffset: 5651, .AliasCondStart: 1545, .NumOperands: 3, .NumConds: 3 },
2243 {.AsmStrOffset: 5658, .AliasCondStart: 1548, .NumOperands: 3, .NumConds: 3 },
2244 {.AsmStrOffset: 5670, .AliasCondStart: 1551, .NumOperands: 3, .NumConds: 3 },
2245 {.AsmStrOffset: 5678, .AliasCondStart: 1554, .NumOperands: 3, .NumConds: 3 },
2246 {.AsmStrOffset: 5691, .AliasCondStart: 1557, .NumOperands: 3, .NumConds: 3 },
2247 {.AsmStrOffset: 5698, .AliasCondStart: 1560, .NumOperands: 3, .NumConds: 3 },
2248 {.AsmStrOffset: 5710, .AliasCondStart: 1563, .NumOperands: 3, .NumConds: 3 },
2249 {.AsmStrOffset: 5717, .AliasCondStart: 1566, .NumOperands: 3, .NumConds: 3 },
2250 {.AsmStrOffset: 5729, .AliasCondStart: 1569, .NumOperands: 3, .NumConds: 3 },
2251 {.AsmStrOffset: 5737, .AliasCondStart: 1572, .NumOperands: 3, .NumConds: 3 },
2252 {.AsmStrOffset: 5750, .AliasCondStart: 1575, .NumOperands: 3, .NumConds: 3 },
2253 {.AsmStrOffset: 5758, .AliasCondStart: 1578, .NumOperands: 3, .NumConds: 3 },
2254 {.AsmStrOffset: 5771, .AliasCondStart: 1581, .NumOperands: 3, .NumConds: 3 },
2255 {.AsmStrOffset: 5778, .AliasCondStart: 1584, .NumOperands: 3, .NumConds: 3 },
2256 {.AsmStrOffset: 5790, .AliasCondStart: 1587, .NumOperands: 3, .NumConds: 3 },
2257 {.AsmStrOffset: 5797, .AliasCondStart: 1590, .NumOperands: 3, .NumConds: 3 },
2258 // SP::TRAPrr - 425
2259 {.AsmStrOffset: 5509, .AliasCondStart: 1593, .NumOperands: 3, .NumConds: 3 },
2260 {.AsmStrOffset: 5515, .AliasCondStart: 1596, .NumOperands: 3, .NumConds: 3 },
2261 {.AsmStrOffset: 5526, .AliasCondStart: 1599, .NumOperands: 3, .NumConds: 3 },
2262 {.AsmStrOffset: 5532, .AliasCondStart: 1602, .NumOperands: 3, .NumConds: 3 },
2263 {.AsmStrOffset: 5543, .AliasCondStart: 1605, .NumOperands: 3, .NumConds: 3 },
2264 {.AsmStrOffset: 5550, .AliasCondStart: 1608, .NumOperands: 3, .NumConds: 3 },
2265 {.AsmStrOffset: 5562, .AliasCondStart: 1611, .NumOperands: 3, .NumConds: 3 },
2266 {.AsmStrOffset: 5568, .AliasCondStart: 1614, .NumOperands: 3, .NumConds: 3 },
2267 {.AsmStrOffset: 5579, .AliasCondStart: 1617, .NumOperands: 3, .NumConds: 3 },
2268 {.AsmStrOffset: 5585, .AliasCondStart: 1620, .NumOperands: 3, .NumConds: 3 },
2269 {.AsmStrOffset: 5596, .AliasCondStart: 1623, .NumOperands: 3, .NumConds: 3 },
2270 {.AsmStrOffset: 5603, .AliasCondStart: 1626, .NumOperands: 3, .NumConds: 3 },
2271 {.AsmStrOffset: 5615, .AliasCondStart: 1629, .NumOperands: 3, .NumConds: 3 },
2272 {.AsmStrOffset: 5622, .AliasCondStart: 1632, .NumOperands: 3, .NumConds: 3 },
2273 {.AsmStrOffset: 5634, .AliasCondStart: 1635, .NumOperands: 3, .NumConds: 3 },
2274 {.AsmStrOffset: 5640, .AliasCondStart: 1638, .NumOperands: 3, .NumConds: 3 },
2275 {.AsmStrOffset: 5651, .AliasCondStart: 1641, .NumOperands: 3, .NumConds: 3 },
2276 {.AsmStrOffset: 5658, .AliasCondStart: 1644, .NumOperands: 3, .NumConds: 3 },
2277 {.AsmStrOffset: 5670, .AliasCondStart: 1647, .NumOperands: 3, .NumConds: 3 },
2278 {.AsmStrOffset: 5678, .AliasCondStart: 1650, .NumOperands: 3, .NumConds: 3 },
2279 {.AsmStrOffset: 5691, .AliasCondStart: 1653, .NumOperands: 3, .NumConds: 3 },
2280 {.AsmStrOffset: 5698, .AliasCondStart: 1656, .NumOperands: 3, .NumConds: 3 },
2281 {.AsmStrOffset: 5710, .AliasCondStart: 1659, .NumOperands: 3, .NumConds: 3 },
2282 {.AsmStrOffset: 5717, .AliasCondStart: 1662, .NumOperands: 3, .NumConds: 3 },
2283 {.AsmStrOffset: 5729, .AliasCondStart: 1665, .NumOperands: 3, .NumConds: 3 },
2284 {.AsmStrOffset: 5737, .AliasCondStart: 1668, .NumOperands: 3, .NumConds: 3 },
2285 {.AsmStrOffset: 5750, .AliasCondStart: 1671, .NumOperands: 3, .NumConds: 3 },
2286 {.AsmStrOffset: 5758, .AliasCondStart: 1674, .NumOperands: 3, .NumConds: 3 },
2287 {.AsmStrOffset: 5771, .AliasCondStart: 1677, .NumOperands: 3, .NumConds: 3 },
2288 {.AsmStrOffset: 5778, .AliasCondStart: 1680, .NumOperands: 3, .NumConds: 3 },
2289 {.AsmStrOffset: 5790, .AliasCondStart: 1683, .NumOperands: 3, .NumConds: 3 },
2290 {.AsmStrOffset: 5797, .AliasCondStart: 1686, .NumOperands: 3, .NumConds: 3 },
2291 // SP::TXCCri - 457
2292 {.AsmStrOffset: 5809, .AliasCondStart: 1689, .NumOperands: 3, .NumConds: 4 },
2293 {.AsmStrOffset: 5821, .AliasCondStart: 1693, .NumOperands: 3, .NumConds: 4 },
2294 {.AsmStrOffset: 5838, .AliasCondStart: 1697, .NumOperands: 3, .NumConds: 4 },
2295 {.AsmStrOffset: 5850, .AliasCondStart: 1701, .NumOperands: 3, .NumConds: 4 },
2296 {.AsmStrOffset: 5867, .AliasCondStart: 1705, .NumOperands: 3, .NumConds: 4 },
2297 {.AsmStrOffset: 5880, .AliasCondStart: 1709, .NumOperands: 3, .NumConds: 4 },
2298 {.AsmStrOffset: 5898, .AliasCondStart: 1713, .NumOperands: 3, .NumConds: 4 },
2299 {.AsmStrOffset: 5910, .AliasCondStart: 1717, .NumOperands: 3, .NumConds: 4 },
2300 {.AsmStrOffset: 5927, .AliasCondStart: 1721, .NumOperands: 3, .NumConds: 4 },
2301 {.AsmStrOffset: 5939, .AliasCondStart: 1725, .NumOperands: 3, .NumConds: 4 },
2302 {.AsmStrOffset: 5956, .AliasCondStart: 1729, .NumOperands: 3, .NumConds: 4 },
2303 {.AsmStrOffset: 5969, .AliasCondStart: 1733, .NumOperands: 3, .NumConds: 4 },
2304 {.AsmStrOffset: 5987, .AliasCondStart: 1737, .NumOperands: 3, .NumConds: 4 },
2305 {.AsmStrOffset: 6000, .AliasCondStart: 1741, .NumOperands: 3, .NumConds: 4 },
2306 {.AsmStrOffset: 6018, .AliasCondStart: 1745, .NumOperands: 3, .NumConds: 4 },
2307 {.AsmStrOffset: 6030, .AliasCondStart: 1749, .NumOperands: 3, .NumConds: 4 },
2308 {.AsmStrOffset: 6047, .AliasCondStart: 1753, .NumOperands: 3, .NumConds: 4 },
2309 {.AsmStrOffset: 6060, .AliasCondStart: 1757, .NumOperands: 3, .NumConds: 4 },
2310 {.AsmStrOffset: 6078, .AliasCondStart: 1761, .NumOperands: 3, .NumConds: 4 },
2311 {.AsmStrOffset: 6092, .AliasCondStart: 1765, .NumOperands: 3, .NumConds: 4 },
2312 {.AsmStrOffset: 6111, .AliasCondStart: 1769, .NumOperands: 3, .NumConds: 4 },
2313 {.AsmStrOffset: 6124, .AliasCondStart: 1773, .NumOperands: 3, .NumConds: 4 },
2314 {.AsmStrOffset: 6142, .AliasCondStart: 1777, .NumOperands: 3, .NumConds: 4 },
2315 {.AsmStrOffset: 6155, .AliasCondStart: 1781, .NumOperands: 3, .NumConds: 4 },
2316 {.AsmStrOffset: 6173, .AliasCondStart: 1785, .NumOperands: 3, .NumConds: 4 },
2317 {.AsmStrOffset: 6187, .AliasCondStart: 1789, .NumOperands: 3, .NumConds: 4 },
2318 {.AsmStrOffset: 6206, .AliasCondStart: 1793, .NumOperands: 3, .NumConds: 4 },
2319 {.AsmStrOffset: 6220, .AliasCondStart: 1797, .NumOperands: 3, .NumConds: 4 },
2320 {.AsmStrOffset: 6239, .AliasCondStart: 1801, .NumOperands: 3, .NumConds: 4 },
2321 {.AsmStrOffset: 6252, .AliasCondStart: 1805, .NumOperands: 3, .NumConds: 4 },
2322 {.AsmStrOffset: 6270, .AliasCondStart: 1809, .NumOperands: 3, .NumConds: 4 },
2323 {.AsmStrOffset: 6283, .AliasCondStart: 1813, .NumOperands: 3, .NumConds: 4 },
2324 // SP::TXCCrr - 489
2325 {.AsmStrOffset: 5809, .AliasCondStart: 1817, .NumOperands: 3, .NumConds: 4 },
2326 {.AsmStrOffset: 5821, .AliasCondStart: 1821, .NumOperands: 3, .NumConds: 4 },
2327 {.AsmStrOffset: 5838, .AliasCondStart: 1825, .NumOperands: 3, .NumConds: 4 },
2328 {.AsmStrOffset: 5850, .AliasCondStart: 1829, .NumOperands: 3, .NumConds: 4 },
2329 {.AsmStrOffset: 5867, .AliasCondStart: 1833, .NumOperands: 3, .NumConds: 4 },
2330 {.AsmStrOffset: 5880, .AliasCondStart: 1837, .NumOperands: 3, .NumConds: 4 },
2331 {.AsmStrOffset: 5898, .AliasCondStart: 1841, .NumOperands: 3, .NumConds: 4 },
2332 {.AsmStrOffset: 5910, .AliasCondStart: 1845, .NumOperands: 3, .NumConds: 4 },
2333 {.AsmStrOffset: 5927, .AliasCondStart: 1849, .NumOperands: 3, .NumConds: 4 },
2334 {.AsmStrOffset: 5939, .AliasCondStart: 1853, .NumOperands: 3, .NumConds: 4 },
2335 {.AsmStrOffset: 5956, .AliasCondStart: 1857, .NumOperands: 3, .NumConds: 4 },
2336 {.AsmStrOffset: 5969, .AliasCondStart: 1861, .NumOperands: 3, .NumConds: 4 },
2337 {.AsmStrOffset: 5987, .AliasCondStart: 1865, .NumOperands: 3, .NumConds: 4 },
2338 {.AsmStrOffset: 6000, .AliasCondStart: 1869, .NumOperands: 3, .NumConds: 4 },
2339 {.AsmStrOffset: 6018, .AliasCondStart: 1873, .NumOperands: 3, .NumConds: 4 },
2340 {.AsmStrOffset: 6030, .AliasCondStart: 1877, .NumOperands: 3, .NumConds: 4 },
2341 {.AsmStrOffset: 6047, .AliasCondStart: 1881, .NumOperands: 3, .NumConds: 4 },
2342 {.AsmStrOffset: 6060, .AliasCondStart: 1885, .NumOperands: 3, .NumConds: 4 },
2343 {.AsmStrOffset: 6078, .AliasCondStart: 1889, .NumOperands: 3, .NumConds: 4 },
2344 {.AsmStrOffset: 6092, .AliasCondStart: 1893, .NumOperands: 3, .NumConds: 4 },
2345 {.AsmStrOffset: 6111, .AliasCondStart: 1897, .NumOperands: 3, .NumConds: 4 },
2346 {.AsmStrOffset: 6124, .AliasCondStart: 1901, .NumOperands: 3, .NumConds: 4 },
2347 {.AsmStrOffset: 6142, .AliasCondStart: 1905, .NumOperands: 3, .NumConds: 4 },
2348 {.AsmStrOffset: 6155, .AliasCondStart: 1909, .NumOperands: 3, .NumConds: 4 },
2349 {.AsmStrOffset: 6173, .AliasCondStart: 1913, .NumOperands: 3, .NumConds: 4 },
2350 {.AsmStrOffset: 6187, .AliasCondStart: 1917, .NumOperands: 3, .NumConds: 4 },
2351 {.AsmStrOffset: 6206, .AliasCondStart: 1921, .NumOperands: 3, .NumConds: 4 },
2352 {.AsmStrOffset: 6220, .AliasCondStart: 1925, .NumOperands: 3, .NumConds: 4 },
2353 {.AsmStrOffset: 6239, .AliasCondStart: 1929, .NumOperands: 3, .NumConds: 4 },
2354 {.AsmStrOffset: 6252, .AliasCondStart: 1933, .NumOperands: 3, .NumConds: 4 },
2355 {.AsmStrOffset: 6270, .AliasCondStart: 1937, .NumOperands: 3, .NumConds: 4 },
2356 {.AsmStrOffset: 6283, .AliasCondStart: 1941, .NumOperands: 3, .NumConds: 4 },
2357 // SP::V9FCMPD - 521
2358 {.AsmStrOffset: 6301, .AliasCondStart: 1945, .NumOperands: 3, .NumConds: 3 },
2359 // SP::V9FCMPED - 522
2360 {.AsmStrOffset: 6314, .AliasCondStart: 1948, .NumOperands: 3, .NumConds: 3 },
2361 // SP::V9FCMPEQ - 523
2362 {.AsmStrOffset: 6328, .AliasCondStart: 1951, .NumOperands: 3, .NumConds: 3 },
2363 // SP::V9FCMPES - 524
2364 {.AsmStrOffset: 6342, .AliasCondStart: 1954, .NumOperands: 3, .NumConds: 3 },
2365 // SP::V9FCMPQ - 525
2366 {.AsmStrOffset: 6356, .AliasCondStart: 1957, .NumOperands: 3, .NumConds: 3 },
2367 // SP::V9FCMPS - 526
2368 {.AsmStrOffset: 6369, .AliasCondStart: 1960, .NumOperands: 3, .NumConds: 3 },
2369 // SP::V9FMOVD_FCC - 527
2370 {.AsmStrOffset: 6382, .AliasCondStart: 1963, .NumOperands: 5, .NumConds: 6 },
2371 {.AsmStrOffset: 6400, .AliasCondStart: 1969, .NumOperands: 5, .NumConds: 6 },
2372 {.AsmStrOffset: 6418, .AliasCondStart: 1975, .NumOperands: 5, .NumConds: 6 },
2373 {.AsmStrOffset: 6436, .AliasCondStart: 1981, .NumOperands: 5, .NumConds: 6 },
2374 {.AsmStrOffset: 6454, .AliasCondStart: 1987, .NumOperands: 5, .NumConds: 6 },
2375 {.AsmStrOffset: 6473, .AliasCondStart: 1993, .NumOperands: 5, .NumConds: 6 },
2376 {.AsmStrOffset: 6491, .AliasCondStart: 1999, .NumOperands: 5, .NumConds: 6 },
2377 {.AsmStrOffset: 6510, .AliasCondStart: 2005, .NumOperands: 5, .NumConds: 6 },
2378 {.AsmStrOffset: 6529, .AliasCondStart: 2011, .NumOperands: 5, .NumConds: 6 },
2379 {.AsmStrOffset: 6548, .AliasCondStart: 2017, .NumOperands: 5, .NumConds: 6 },
2380 {.AsmStrOffset: 6566, .AliasCondStart: 2023, .NumOperands: 5, .NumConds: 6 },
2381 {.AsmStrOffset: 6585, .AliasCondStart: 2029, .NumOperands: 5, .NumConds: 6 },
2382 {.AsmStrOffset: 6604, .AliasCondStart: 2035, .NumOperands: 5, .NumConds: 6 },
2383 {.AsmStrOffset: 6624, .AliasCondStart: 2041, .NumOperands: 5, .NumConds: 6 },
2384 {.AsmStrOffset: 6643, .AliasCondStart: 2047, .NumOperands: 5, .NumConds: 6 },
2385 {.AsmStrOffset: 6663, .AliasCondStart: 2053, .NumOperands: 5, .NumConds: 6 },
2386 // SP::V9FMOVQ_FCC - 543
2387 {.AsmStrOffset: 6681, .AliasCondStart: 2059, .NumOperands: 5, .NumConds: 6 },
2388 {.AsmStrOffset: 6699, .AliasCondStart: 2065, .NumOperands: 5, .NumConds: 6 },
2389 {.AsmStrOffset: 6717, .AliasCondStart: 2071, .NumOperands: 5, .NumConds: 6 },
2390 {.AsmStrOffset: 6735, .AliasCondStart: 2077, .NumOperands: 5, .NumConds: 6 },
2391 {.AsmStrOffset: 6753, .AliasCondStart: 2083, .NumOperands: 5, .NumConds: 6 },
2392 {.AsmStrOffset: 6772, .AliasCondStart: 2089, .NumOperands: 5, .NumConds: 6 },
2393 {.AsmStrOffset: 6790, .AliasCondStart: 2095, .NumOperands: 5, .NumConds: 6 },
2394 {.AsmStrOffset: 6809, .AliasCondStart: 2101, .NumOperands: 5, .NumConds: 6 },
2395 {.AsmStrOffset: 6828, .AliasCondStart: 2107, .NumOperands: 5, .NumConds: 6 },
2396 {.AsmStrOffset: 6847, .AliasCondStart: 2113, .NumOperands: 5, .NumConds: 6 },
2397 {.AsmStrOffset: 6865, .AliasCondStart: 2119, .NumOperands: 5, .NumConds: 6 },
2398 {.AsmStrOffset: 6884, .AliasCondStart: 2125, .NumOperands: 5, .NumConds: 6 },
2399 {.AsmStrOffset: 6903, .AliasCondStart: 2131, .NumOperands: 5, .NumConds: 6 },
2400 {.AsmStrOffset: 6923, .AliasCondStart: 2137, .NumOperands: 5, .NumConds: 6 },
2401 {.AsmStrOffset: 6942, .AliasCondStart: 2143, .NumOperands: 5, .NumConds: 6 },
2402 {.AsmStrOffset: 6962, .AliasCondStart: 2149, .NumOperands: 5, .NumConds: 6 },
2403 // SP::V9FMOVS_FCC - 559
2404 {.AsmStrOffset: 6980, .AliasCondStart: 2155, .NumOperands: 5, .NumConds: 6 },
2405 {.AsmStrOffset: 6998, .AliasCondStart: 2161, .NumOperands: 5, .NumConds: 6 },
2406 {.AsmStrOffset: 7016, .AliasCondStart: 2167, .NumOperands: 5, .NumConds: 6 },
2407 {.AsmStrOffset: 7034, .AliasCondStart: 2173, .NumOperands: 5, .NumConds: 6 },
2408 {.AsmStrOffset: 7052, .AliasCondStart: 2179, .NumOperands: 5, .NumConds: 6 },
2409 {.AsmStrOffset: 7071, .AliasCondStart: 2185, .NumOperands: 5, .NumConds: 6 },
2410 {.AsmStrOffset: 7089, .AliasCondStart: 2191, .NumOperands: 5, .NumConds: 6 },
2411 {.AsmStrOffset: 7108, .AliasCondStart: 2197, .NumOperands: 5, .NumConds: 6 },
2412 {.AsmStrOffset: 7127, .AliasCondStart: 2203, .NumOperands: 5, .NumConds: 6 },
2413 {.AsmStrOffset: 7146, .AliasCondStart: 2209, .NumOperands: 5, .NumConds: 6 },
2414 {.AsmStrOffset: 7164, .AliasCondStart: 2215, .NumOperands: 5, .NumConds: 6 },
2415 {.AsmStrOffset: 7183, .AliasCondStart: 2221, .NumOperands: 5, .NumConds: 6 },
2416 {.AsmStrOffset: 7202, .AliasCondStart: 2227, .NumOperands: 5, .NumConds: 6 },
2417 {.AsmStrOffset: 7222, .AliasCondStart: 2233, .NumOperands: 5, .NumConds: 6 },
2418 {.AsmStrOffset: 7241, .AliasCondStart: 2239, .NumOperands: 5, .NumConds: 6 },
2419 {.AsmStrOffset: 7261, .AliasCondStart: 2245, .NumOperands: 5, .NumConds: 6 },
2420 // SP::V9MOVFCCri - 575
2421 {.AsmStrOffset: 7279, .AliasCondStart: 2251, .NumOperands: 5, .NumConds: 6 },
2422 {.AsmStrOffset: 7295, .AliasCondStart: 2257, .NumOperands: 5, .NumConds: 6 },
2423 {.AsmStrOffset: 7311, .AliasCondStart: 2263, .NumOperands: 5, .NumConds: 6 },
2424 {.AsmStrOffset: 7327, .AliasCondStart: 2269, .NumOperands: 5, .NumConds: 6 },
2425 {.AsmStrOffset: 7343, .AliasCondStart: 2275, .NumOperands: 5, .NumConds: 6 },
2426 {.AsmStrOffset: 7360, .AliasCondStart: 2281, .NumOperands: 5, .NumConds: 6 },
2427 {.AsmStrOffset: 7376, .AliasCondStart: 2287, .NumOperands: 5, .NumConds: 6 },
2428 {.AsmStrOffset: 7393, .AliasCondStart: 2293, .NumOperands: 5, .NumConds: 6 },
2429 {.AsmStrOffset: 7410, .AliasCondStart: 2299, .NumOperands: 5, .NumConds: 6 },
2430 {.AsmStrOffset: 7427, .AliasCondStart: 2305, .NumOperands: 5, .NumConds: 6 },
2431 {.AsmStrOffset: 7443, .AliasCondStart: 2311, .NumOperands: 5, .NumConds: 6 },
2432 {.AsmStrOffset: 7460, .AliasCondStart: 2317, .NumOperands: 5, .NumConds: 6 },
2433 {.AsmStrOffset: 7477, .AliasCondStart: 2323, .NumOperands: 5, .NumConds: 6 },
2434 {.AsmStrOffset: 7495, .AliasCondStart: 2329, .NumOperands: 5, .NumConds: 6 },
2435 {.AsmStrOffset: 7512, .AliasCondStart: 2335, .NumOperands: 5, .NumConds: 6 },
2436 {.AsmStrOffset: 7530, .AliasCondStart: 2341, .NumOperands: 5, .NumConds: 6 },
2437 // SP::V9MOVFCCrr - 591
2438 {.AsmStrOffset: 7279, .AliasCondStart: 2347, .NumOperands: 5, .NumConds: 6 },
2439 {.AsmStrOffset: 7295, .AliasCondStart: 2353, .NumOperands: 5, .NumConds: 6 },
2440 {.AsmStrOffset: 7311, .AliasCondStart: 2359, .NumOperands: 5, .NumConds: 6 },
2441 {.AsmStrOffset: 7327, .AliasCondStart: 2365, .NumOperands: 5, .NumConds: 6 },
2442 {.AsmStrOffset: 7343, .AliasCondStart: 2371, .NumOperands: 5, .NumConds: 6 },
2443 {.AsmStrOffset: 7360, .AliasCondStart: 2377, .NumOperands: 5, .NumConds: 6 },
2444 {.AsmStrOffset: 7376, .AliasCondStart: 2383, .NumOperands: 5, .NumConds: 6 },
2445 {.AsmStrOffset: 7393, .AliasCondStart: 2389, .NumOperands: 5, .NumConds: 6 },
2446 {.AsmStrOffset: 7410, .AliasCondStart: 2395, .NumOperands: 5, .NumConds: 6 },
2447 {.AsmStrOffset: 7427, .AliasCondStart: 2401, .NumOperands: 5, .NumConds: 6 },
2448 {.AsmStrOffset: 7443, .AliasCondStart: 2407, .NumOperands: 5, .NumConds: 6 },
2449 {.AsmStrOffset: 7460, .AliasCondStart: 2413, .NumOperands: 5, .NumConds: 6 },
2450 {.AsmStrOffset: 7477, .AliasCondStart: 2419, .NumOperands: 5, .NumConds: 6 },
2451 {.AsmStrOffset: 7495, .AliasCondStart: 2425, .NumOperands: 5, .NumConds: 6 },
2452 {.AsmStrOffset: 7512, .AliasCondStart: 2431, .NumOperands: 5, .NumConds: 6 },
2453 {.AsmStrOffset: 7530, .AliasCondStart: 2437, .NumOperands: 5, .NumConds: 6 },
2454 };
2455
2456 static const AliasPatternCond Conds[] = {
2457 // (BCOND brtarget:$imm, 8) - 0
2458 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2459 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2460 // (BCOND brtarget:$imm, 0) - 2
2461 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2462 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2463 // (BCOND brtarget:$imm, 9) - 4
2464 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2465 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2466 // (BCOND brtarget:$imm, 1) - 6
2467 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2468 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2469 // (BCOND brtarget:$imm, 10) - 8
2470 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2471 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2472 // (BCOND brtarget:$imm, 2) - 10
2473 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2474 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2475 // (BCOND brtarget:$imm, 11) - 12
2476 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2477 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2478 // (BCOND brtarget:$imm, 3) - 14
2479 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2480 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2481 // (BCOND brtarget:$imm, 12) - 16
2482 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2483 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2484 // (BCOND brtarget:$imm, 4) - 18
2485 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2486 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2487 // (BCOND brtarget:$imm, 13) - 20
2488 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2489 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2490 // (BCOND brtarget:$imm, 5) - 22
2491 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2492 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2493 // (BCOND brtarget:$imm, 14) - 24
2494 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2495 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2496 // (BCOND brtarget:$imm, 6) - 26
2497 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2498 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2499 // (BCOND brtarget:$imm, 15) - 28
2500 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2501 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2502 // (BCOND brtarget:$imm, 7) - 30
2503 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2504 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2505 // (BCONDA brtarget:$imm, 8) - 32
2506 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2507 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2508 // (BCONDA brtarget:$imm, 0) - 34
2509 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2510 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2511 // (BCONDA brtarget:$imm, 9) - 36
2512 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2513 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2514 // (BCONDA brtarget:$imm, 1) - 38
2515 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2516 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2517 // (BCONDA brtarget:$imm, 10) - 40
2518 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2519 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2520 // (BCONDA brtarget:$imm, 2) - 42
2521 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2522 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2523 // (BCONDA brtarget:$imm, 11) - 44
2524 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2525 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2526 // (BCONDA brtarget:$imm, 3) - 46
2527 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2528 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2529 // (BCONDA brtarget:$imm, 12) - 48
2530 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2531 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2532 // (BCONDA brtarget:$imm, 4) - 50
2533 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2534 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2535 // (BCONDA brtarget:$imm, 13) - 52
2536 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2537 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2538 // (BCONDA brtarget:$imm, 5) - 54
2539 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2540 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2541 // (BCONDA brtarget:$imm, 14) - 56
2542 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2543 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2544 // (BCONDA brtarget:$imm, 6) - 58
2545 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2546 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2547 // (BCONDA brtarget:$imm, 15) - 60
2548 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2549 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2550 // (BCONDA brtarget:$imm, 7) - 62
2551 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2552 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2553 // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
2554 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2555 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2556 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2557 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2558 // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
2559 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2560 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2562 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2563 // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
2564 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2565 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2566 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2567 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2568 // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
2569 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2570 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2571 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2572 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2573 // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
2574 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2575 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2576 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2577 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2578 // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
2579 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2580 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2581 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2582 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2583 // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
2584 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2585 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2586 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2587 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2588 // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
2589 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2590 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2591 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2592 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2593 // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
2594 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2595 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2596 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2597 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2598 // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
2599 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2600 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2601 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2602 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2603 // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
2604 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2605 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2606 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2607 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2608 // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
2609 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2610 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2611 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2612 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2613 // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
2614 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2615 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2616 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2617 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2618 // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
2619 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2620 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2621 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2622 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2623 // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
2624 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2625 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2626 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2627 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2628 // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
2629 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2630 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2631 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2632 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2633 // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
2634 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2635 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2636 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2637 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2638 // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
2639 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2640 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2641 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2642 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2643 // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
2644 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2645 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2646 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2647 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2648 // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
2649 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2650 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2651 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2652 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2653 // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
2654 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2655 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2656 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2657 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2658 // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
2659 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2660 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2661 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2662 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2663 // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
2664 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2665 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2666 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2667 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2668 // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
2669 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2670 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2671 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2672 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2673 // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
2674 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2675 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2676 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2677 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2678 // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
2679 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2680 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2681 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2682 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2683 // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
2684 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2685 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2686 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2687 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2688 // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
2689 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2690 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2691 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2692 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2693 // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
2694 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2695 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2696 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2697 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2698 // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
2699 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2700 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2701 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2702 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2703 // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
2704 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2705 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2706 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2707 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2708 // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
2709 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2710 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2711 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
2712 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2713 // (BPICCANT brtarget:$imm, 8) - 192
2714 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2715 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2716 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2717 // (BPICCANT brtarget:$imm, 0) - 195
2718 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2719 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2720 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2721 // (BPICCANT brtarget:$imm, 9) - 198
2722 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2723 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2724 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2725 // (BPICCANT brtarget:$imm, 1) - 201
2726 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2727 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2728 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2729 // (BPICCANT brtarget:$imm, 10) - 204
2730 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2731 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2732 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2733 // (BPICCANT brtarget:$imm, 2) - 207
2734 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2735 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2736 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2737 // (BPICCANT brtarget:$imm, 11) - 210
2738 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2739 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2740 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2741 // (BPICCANT brtarget:$imm, 3) - 213
2742 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2743 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2744 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2745 // (BPICCANT brtarget:$imm, 12) - 216
2746 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2747 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2748 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2749 // (BPICCANT brtarget:$imm, 4) - 219
2750 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2751 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2752 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2753 // (BPICCANT brtarget:$imm, 13) - 222
2754 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2755 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2756 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2757 // (BPICCANT brtarget:$imm, 5) - 225
2758 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2759 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2760 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2761 // (BPICCANT brtarget:$imm, 14) - 228
2762 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2763 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2764 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2765 // (BPICCANT brtarget:$imm, 6) - 231
2766 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2767 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2768 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2769 // (BPICCANT brtarget:$imm, 15) - 234
2770 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2771 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2772 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2773 // (BPICCANT brtarget:$imm, 7) - 237
2774 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2775 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2776 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2777 // (BPICCNT brtarget:$imm, 8) - 240
2778 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2779 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2780 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2781 // (BPICCNT brtarget:$imm, 0) - 243
2782 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2783 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2784 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2785 // (BPICCNT brtarget:$imm, 9) - 246
2786 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2787 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2788 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2789 // (BPICCNT brtarget:$imm, 1) - 249
2790 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2791 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2792 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2793 // (BPICCNT brtarget:$imm, 10) - 252
2794 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2795 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2796 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2797 // (BPICCNT brtarget:$imm, 2) - 255
2798 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2799 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2800 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2801 // (BPICCNT brtarget:$imm, 11) - 258
2802 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2803 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2804 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2805 // (BPICCNT brtarget:$imm, 3) - 261
2806 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2807 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2808 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2809 // (BPICCNT brtarget:$imm, 12) - 264
2810 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2811 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2812 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2813 // (BPICCNT brtarget:$imm, 4) - 267
2814 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2815 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2816 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2817 // (BPICCNT brtarget:$imm, 13) - 270
2818 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2819 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2820 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2821 // (BPICCNT brtarget:$imm, 5) - 273
2822 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2823 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2824 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2825 // (BPICCNT brtarget:$imm, 14) - 276
2826 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2827 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2828 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2829 // (BPICCNT brtarget:$imm, 6) - 279
2830 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2831 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2832 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2833 // (BPICCNT brtarget:$imm, 15) - 282
2834 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2835 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2836 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2837 // (BPICCNT brtarget:$imm, 7) - 285
2838 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2839 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2840 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2841 // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 288
2842 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2843 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2844 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2845 // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 291
2846 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2847 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2849 // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 294
2850 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2851 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2852 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2853 // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 297
2854 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2855 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2856 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2857 // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 300
2858 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2859 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2860 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2861 // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 303
2862 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2863 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2864 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2865 // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 306
2866 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2867 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2868 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2869 // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 309
2870 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2871 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2872 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2873 // (BPXCCANT brtarget:$imm, 8) - 312
2874 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2875 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2876 // (BPXCCANT brtarget:$imm, 0) - 314
2877 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2878 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2879 // (BPXCCANT brtarget:$imm, 9) - 316
2880 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2881 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2882 // (BPXCCANT brtarget:$imm, 1) - 318
2883 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2884 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2885 // (BPXCCANT brtarget:$imm, 10) - 320
2886 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2887 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2888 // (BPXCCANT brtarget:$imm, 2) - 322
2889 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2890 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2891 // (BPXCCANT brtarget:$imm, 11) - 324
2892 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2893 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2894 // (BPXCCANT brtarget:$imm, 3) - 326
2895 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2896 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2897 // (BPXCCANT brtarget:$imm, 12) - 328
2898 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2899 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2900 // (BPXCCANT brtarget:$imm, 4) - 330
2901 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2902 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2903 // (BPXCCANT brtarget:$imm, 13) - 332
2904 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2905 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2906 // (BPXCCANT brtarget:$imm, 5) - 334
2907 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2908 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2909 // (BPXCCANT brtarget:$imm, 14) - 336
2910 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2911 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2912 // (BPXCCANT brtarget:$imm, 6) - 338
2913 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2914 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2915 // (BPXCCANT brtarget:$imm, 15) - 340
2916 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2917 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2918 // (BPXCCANT brtarget:$imm, 7) - 342
2919 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2920 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2921 // (BPXCCNT brtarget:$imm, 8) - 344
2922 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2923 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
2924 // (BPXCCNT brtarget:$imm, 0) - 346
2925 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2926 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
2927 // (BPXCCNT brtarget:$imm, 9) - 348
2928 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2929 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
2930 // (BPXCCNT brtarget:$imm, 1) - 350
2931 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2932 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
2933 // (BPXCCNT brtarget:$imm, 10) - 352
2934 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2935 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
2936 // (BPXCCNT brtarget:$imm, 2) - 354
2937 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2938 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
2939 // (BPXCCNT brtarget:$imm, 11) - 356
2940 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2941 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
2942 // (BPXCCNT brtarget:$imm, 3) - 358
2943 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2944 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
2945 // (BPXCCNT brtarget:$imm, 12) - 360
2946 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2947 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
2948 // (BPXCCNT brtarget:$imm, 4) - 362
2949 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2950 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
2951 // (BPXCCNT brtarget:$imm, 13) - 364
2952 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2953 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
2954 // (BPXCCNT brtarget:$imm, 5) - 366
2955 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2956 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
2957 // (BPXCCNT brtarget:$imm, 14) - 368
2958 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2959 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
2960 // (BPXCCNT brtarget:$imm, 6) - 370
2961 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2962 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
2963 // (BPXCCNT brtarget:$imm, 15) - 372
2964 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2965 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
2966 // (BPXCCNT brtarget:$imm, 7) - 374
2967 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2968 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
2969 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 376
2970 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
2971 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
2972 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
2973 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2974 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
2975 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2976 // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 382
2977 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
2978 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
2979 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
2980 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2981 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
2982 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2983 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 388
2984 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2985 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2986 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2987 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2988 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(128)},
2989 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2990 // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 394
2991 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2992 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2993 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
2994 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
2995 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)},
2996 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
2997 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 400
2998 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
2999 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3000 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3001 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3002 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3003 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 405
3004 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3005 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3006 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3007 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3008 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3009 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 410
3010 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3011 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3012 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3013 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3014 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3015 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 415
3016 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3017 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3018 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3019 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3020 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3021 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 420
3022 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3023 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3024 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3025 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3026 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3027 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 425
3028 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3029 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3030 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3031 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3032 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3033 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 430
3034 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3035 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3036 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3037 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3038 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3039 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 435
3040 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3041 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3042 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3043 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3044 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3045 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 440
3046 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3047 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3048 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3049 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3050 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3051 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 445
3052 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3054 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3055 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3056 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3057 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 450
3058 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3059 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3060 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3061 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3062 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3063 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 455
3064 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3065 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3066 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3067 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3068 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3069 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 460
3070 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3071 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3072 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3073 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3074 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3075 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 465
3076 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3077 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3078 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3079 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3080 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3081 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 470
3082 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3083 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3084 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3085 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3086 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3087 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 475
3088 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3089 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3090 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3091 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3092 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3093 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) - 480
3094 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3095 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3096 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3097 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3098 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) - 484
3099 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3100 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3101 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3102 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3103 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) - 488
3104 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3105 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3106 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3107 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3108 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) - 492
3109 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3110 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3111 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3112 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3113 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) - 496
3114 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3115 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3116 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3117 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3118 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) - 500
3119 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3120 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3121 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3122 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3123 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) - 504
3124 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3125 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3126 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3127 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3128 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) - 508
3129 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3130 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3131 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3132 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3133 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) - 512
3134 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3135 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3136 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3137 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3138 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) - 516
3139 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3140 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3141 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3142 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3143 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) - 520
3144 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3145 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3146 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3147 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3148 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) - 524
3149 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3150 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3151 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3152 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3153 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) - 528
3154 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3155 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3156 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3157 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3158 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) - 532
3159 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3160 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3161 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3162 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3163 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) - 536
3164 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3166 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3167 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3168 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) - 540
3169 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3170 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3171 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3172 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3173 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 544
3174 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3175 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3176 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3177 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3178 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3179 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 549
3180 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3181 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3182 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3183 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3184 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3185 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 554
3186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3187 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3188 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3189 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3190 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3191 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 559
3192 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3194 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3195 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3196 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3197 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 564
3198 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3199 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3200 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3201 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3202 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3203 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 569
3204 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3205 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3206 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3207 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3208 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3209 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 574
3210 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3211 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3212 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3213 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3214 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3215 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 579
3216 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3217 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3218 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3219 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3220 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3221 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 584
3222 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3223 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3224 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3225 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3226 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3227 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 589
3228 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3229 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3230 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3231 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3232 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3233 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 594
3234 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3235 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3236 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3237 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3238 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3239 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 599
3240 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3241 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3242 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3243 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3244 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3245 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 604
3246 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3247 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3248 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3249 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3250 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3251 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 609
3252 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3253 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3254 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3255 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3256 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3257 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 614
3258 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3259 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3260 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3261 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3262 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3263 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 619
3264 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3265 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3266 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3267 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3268 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3269 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) - 624
3270 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3271 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3272 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3273 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3274 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) - 628
3275 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3276 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3277 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3278 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3279 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) - 632
3280 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3281 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3282 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3283 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3284 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) - 636
3285 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3286 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3287 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3288 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3289 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) - 640
3290 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3291 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3292 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3293 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3294 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) - 644
3295 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3296 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3297 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3298 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3299 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) - 648
3300 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3301 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3302 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3303 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3304 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) - 652
3305 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3306 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3307 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3308 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3309 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) - 656
3310 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3311 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3312 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3313 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3314 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) - 660
3315 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3316 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3317 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3318 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3319 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) - 664
3320 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3321 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3322 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3323 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3324 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) - 668
3325 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3326 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3327 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3328 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3329 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) - 672
3330 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3331 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3332 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3333 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3334 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) - 676
3335 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3336 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3337 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3338 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3339 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) - 680
3340 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3341 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3342 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3343 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3344 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) - 684
3345 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3346 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3347 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3348 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3349 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 688
3350 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3351 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3352 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3353 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3354 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3355 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 693
3356 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3357 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3358 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3359 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3360 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3361 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 698
3362 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3363 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3364 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3365 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3366 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3367 // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 703
3368 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3369 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3370 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
3371 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3372 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3373 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 708
3374 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3375 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3376 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3377 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3378 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3379 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 713
3380 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3381 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3382 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3383 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3384 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3385 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 718
3386 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3387 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3388 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3389 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3390 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3391 // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 723
3392 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3393 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3394 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
3395 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3396 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3397 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 728
3398 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3399 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3400 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3401 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3402 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3403 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 733
3404 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3405 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3406 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3407 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3408 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3409 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 738
3410 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3411 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3413 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3414 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3415 // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 743
3416 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3417 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3419 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3420 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3421 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 748
3422 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3423 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3424 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3425 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3426 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3427 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 753
3428 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3429 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3430 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3431 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3432 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3433 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 758
3434 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3435 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3436 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3437 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3438 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3439 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 763
3440 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3441 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3442 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3443 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3444 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3445 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 768
3446 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3447 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3448 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3449 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3450 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3451 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 773
3452 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3453 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3454 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3455 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3456 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3457 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 778
3458 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3459 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3460 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3461 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3462 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3463 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 783
3464 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3465 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3466 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3467 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3468 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3469 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 788
3470 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3471 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3472 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3473 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3474 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3475 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 793
3476 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3477 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3478 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3479 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3480 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3481 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 798
3482 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3483 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3484 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3485 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3486 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3487 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 803
3488 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3490 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3491 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3492 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3493 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 808
3494 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3496 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3497 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3498 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3499 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 813
3500 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3502 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3503 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3504 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3505 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 818
3506 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3507 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3508 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3509 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3510 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3511 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 823
3512 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3513 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3514 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3515 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3516 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3517 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) - 828
3518 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3519 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3520 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3521 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3522 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) - 832
3523 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3524 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3525 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3526 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3527 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) - 836
3528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3530 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3531 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3532 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) - 840
3533 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3534 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3535 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3536 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3537 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) - 844
3538 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3539 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3540 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3541 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3542 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) - 848
3543 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3544 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3545 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3546 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3547 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) - 852
3548 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3549 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3550 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3551 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3552 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) - 856
3553 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3554 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3555 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3556 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3557 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) - 860
3558 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3559 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3560 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3561 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3562 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) - 864
3563 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3564 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3565 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3566 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3567 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) - 868
3568 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3569 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3570 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3571 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3572 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) - 872
3573 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3574 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3575 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3576 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3577 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) - 876
3578 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3579 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3580 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3581 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3582 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) - 880
3583 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3585 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3586 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3587 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) - 884
3588 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3589 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3590 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3591 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3592 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) - 888
3593 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3594 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
3595 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3596 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3597 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 892
3598 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3599 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3600 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3601 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3602 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3603 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 897
3604 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3605 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3606 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3607 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3608 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3609 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 902
3610 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3611 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3612 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3613 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3614 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3615 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 907
3616 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3617 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3618 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3619 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3620 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3621 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 912
3622 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3623 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3624 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3625 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3626 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3627 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 917
3628 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3629 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3630 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3631 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3632 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3633 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 922
3634 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3635 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3636 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3637 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3638 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3639 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 927
3640 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3641 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3642 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3643 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3644 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3645 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 932
3646 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3647 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3648 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3649 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3650 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3651 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 937
3652 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3653 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3654 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3655 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3656 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3657 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 942
3658 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3659 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3660 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3661 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3662 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3663 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 947
3664 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3665 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3666 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3667 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3668 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3669 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 952
3670 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3671 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3672 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3673 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3674 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3675 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 957
3676 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3677 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3678 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3679 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3680 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3681 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 962
3682 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3683 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3684 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3685 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3686 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3687 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 967
3688 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3689 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3690 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3691 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3692 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3693 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 972
3694 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3695 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3696 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3697 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3698 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3699 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 977
3700 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3701 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3702 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3703 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3704 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3705 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 982
3706 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3707 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3708 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3709 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3710 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3711 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 987
3712 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3713 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3714 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3715 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3716 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3717 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 992
3718 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3719 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3720 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3721 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3722 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3723 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 997
3724 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3725 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3726 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3727 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3728 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3729 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1002
3730 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3731 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3732 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3733 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3734 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3735 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1007
3736 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3737 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3738 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3739 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3740 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3741 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1012
3742 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3743 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3744 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3745 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3746 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3747 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1017
3748 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3749 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3750 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3751 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3752 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3753 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1022
3754 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3755 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3756 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3757 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3758 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3759 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1027
3760 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3761 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3762 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3763 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3764 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3765 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1032
3766 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3767 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3768 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3769 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3770 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3771 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1037
3772 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3773 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3774 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3775 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3776 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3777 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1042
3778 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3779 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3780 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3781 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3782 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3783 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1047
3784 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3785 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3786 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3787 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3788 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
3789 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1052
3790 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3791 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3792 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3793 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3794 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3795 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1057
3796 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3797 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3798 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3799 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3800 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3801 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1062
3802 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3803 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3804 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3805 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3806 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3807 // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1067
3808 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3809 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3810 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3811 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3812 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3813 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1072
3814 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3815 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3816 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3817 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3818 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3819 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1077
3820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3821 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3822 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3823 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3824 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3825 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1082
3826 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3827 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3828 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3829 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3830 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3831 // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1087
3832 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3833 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::I64RegsRegClassID},
3834 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3835 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3836 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3837 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) - 1092
3838 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3839 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3840 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3841 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3842 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) - 1096
3843 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3844 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3845 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3846 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3847 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) - 1100
3848 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3849 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3850 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3851 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3852 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) - 1104
3853 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3854 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3855 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3857 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) - 1108
3858 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3859 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3860 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3861 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3862 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) - 1112
3863 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3864 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3865 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3866 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3867 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) - 1116
3868 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3869 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3870 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3871 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3872 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) - 1120
3873 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3874 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3875 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3876 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3877 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) - 1124
3878 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3879 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3880 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3881 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3882 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) - 1128
3883 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3884 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3885 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3887 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) - 1132
3888 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3889 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3890 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3891 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3892 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) - 1136
3893 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3894 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3895 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3896 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3897 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) - 1140
3898 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3899 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3900 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3901 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3902 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) - 1144
3903 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3904 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3905 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3906 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3907 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) - 1148
3908 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3909 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3910 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3911 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3912 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) - 1152
3913 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3914 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3915 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3916 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3917 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1156
3918 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3919 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3920 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3921 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
3922 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1160
3923 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3924 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3925 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3926 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
3927 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1164
3928 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3930 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3931 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
3932 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1168
3933 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3934 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3935 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3936 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
3937 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1172
3938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3939 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3940 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3941 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
3942 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1176
3943 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3944 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3945 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3946 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
3947 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1180
3948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3950 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3951 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
3952 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1184
3953 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3954 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3955 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3956 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
3957 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1188
3958 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3959 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3960 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3961 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
3962 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1192
3963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3964 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3965 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3966 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
3967 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1196
3968 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3969 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3970 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3971 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
3972 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1200
3973 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3974 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3975 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3976 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
3977 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1204
3978 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3979 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3980 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3981 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
3982 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1208
3983 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3984 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3985 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3986 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
3987 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1212
3988 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3989 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3990 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3991 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
3992 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1216
3993 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3994 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
3995 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
3996 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
3997 // (ORCCrr G0, IntRegs:$rs2, G0) - 1220
3998 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
3999 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4000 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4001 // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1223
4002 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4003 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4004 // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1225
4005 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4006 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4007 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4008 // (RESTORErr G0, G0, G0) - 1228
4009 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4010 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4011 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4012 // (RET 8) - 1231
4013 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4014 // (RETL 8) - 1232
4015 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4016 // (SAVErr G0, G0, G0) - 1233
4017 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4018 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4019 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4020 // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1236
4021 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4022 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4023 // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1238
4024 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4025 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4026 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4027 // (TICCri G0, i32imm:$imm, 8) - 1241
4028 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4029 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4030 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4031 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4032 // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1245
4033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4034 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4035 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4036 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4037 // (TICCri G0, i32imm:$imm, 0) - 1249
4038 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4039 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4040 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4041 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4042 // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1253
4043 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4044 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4045 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4046 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4047 // (TICCri G0, i32imm:$imm, 9) - 1257
4048 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4049 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4050 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4051 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4052 // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1261
4053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4054 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4055 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4056 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4057 // (TICCri G0, i32imm:$imm, 1) - 1265
4058 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4059 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4060 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4061 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4062 // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1269
4063 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4064 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4065 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4066 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4067 // (TICCri G0, i32imm:$imm, 10) - 1273
4068 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4069 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4070 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4071 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4072 // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1277
4073 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4074 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4075 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4076 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4077 // (TICCri G0, i32imm:$imm, 2) - 1281
4078 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4079 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4080 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4081 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4082 // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1285
4083 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4084 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4085 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4086 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4087 // (TICCri G0, i32imm:$imm, 11) - 1289
4088 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4089 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4090 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4091 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4092 // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1293
4093 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4094 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4095 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4096 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4097 // (TICCri G0, i32imm:$imm, 3) - 1297
4098 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4099 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4100 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4101 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4102 // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1301
4103 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4104 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4105 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4106 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4107 // (TICCri G0, i32imm:$imm, 12) - 1305
4108 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4109 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4110 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4111 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4112 // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1309
4113 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4114 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4115 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4116 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4117 // (TICCri G0, i32imm:$imm, 4) - 1313
4118 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4119 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4120 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4121 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4122 // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1317
4123 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4124 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4125 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4126 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4127 // (TICCri G0, i32imm:$imm, 13) - 1321
4128 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4129 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4130 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4131 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4132 // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1325
4133 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4134 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4135 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4136 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4137 // (TICCri G0, i32imm:$imm, 5) - 1329
4138 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4139 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4140 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4141 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4142 // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1333
4143 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4144 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4145 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4146 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4147 // (TICCri G0, i32imm:$imm, 14) - 1337
4148 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4149 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4150 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4151 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4152 // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1341
4153 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4154 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4155 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4156 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4157 // (TICCri G0, i32imm:$imm, 6) - 1345
4158 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4159 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4160 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4161 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4162 // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1349
4163 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4164 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4165 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4166 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4167 // (TICCri G0, i32imm:$imm, 15) - 1353
4168 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4169 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4170 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4171 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4172 // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 1357
4173 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4174 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4175 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4176 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4177 // (TICCri G0, i32imm:$imm, 7) - 1361
4178 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4179 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4180 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4181 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4182 // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 1365
4183 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4184 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4185 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4186 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4187 // (TICCrr G0, IntRegs:$rs2, 8) - 1369
4188 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4189 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4190 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4191 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4192 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1373
4193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4194 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4195 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4196 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4197 // (TICCrr G0, IntRegs:$rs2, 0) - 1377
4198 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4199 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4200 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4201 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4202 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1381
4203 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4204 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4205 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4206 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4207 // (TICCrr G0, IntRegs:$rs2, 9) - 1385
4208 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4209 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4210 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4211 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4212 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1389
4213 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4214 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4215 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4216 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4217 // (TICCrr G0, IntRegs:$rs2, 1) - 1393
4218 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4219 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4220 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4221 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4222 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1397
4223 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4224 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4225 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4226 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4227 // (TICCrr G0, IntRegs:$rs2, 10) - 1401
4228 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4229 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4230 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4231 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4232 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1405
4233 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4234 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4235 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4236 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4237 // (TICCrr G0, IntRegs:$rs2, 2) - 1409
4238 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4239 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4240 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4241 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4242 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1413
4243 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4244 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4245 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4246 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4247 // (TICCrr G0, IntRegs:$rs2, 11) - 1417
4248 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4249 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4250 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4251 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4252 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1421
4253 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4254 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4255 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4256 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4257 // (TICCrr G0, IntRegs:$rs2, 3) - 1425
4258 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4259 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4260 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4261 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4262 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1429
4263 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4264 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4265 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4266 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4267 // (TICCrr G0, IntRegs:$rs2, 12) - 1433
4268 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4269 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4270 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4271 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4272 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1437
4273 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4274 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4275 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4276 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4277 // (TICCrr G0, IntRegs:$rs2, 4) - 1441
4278 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4279 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4280 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4281 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4282 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1445
4283 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4284 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4285 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4286 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4287 // (TICCrr G0, IntRegs:$rs2, 13) - 1449
4288 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4289 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4290 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4291 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4292 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1453
4293 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4294 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4295 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4296 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4297 // (TICCrr G0, IntRegs:$rs2, 5) - 1457
4298 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4299 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4300 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4301 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4302 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1461
4303 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4304 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4305 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4306 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4307 // (TICCrr G0, IntRegs:$rs2, 14) - 1465
4308 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4309 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4310 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4311 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4312 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1469
4313 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4314 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4315 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4316 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4317 // (TICCrr G0, IntRegs:$rs2, 6) - 1473
4318 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4319 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4320 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4321 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4322 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1477
4323 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4324 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4325 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4326 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4327 // (TICCrr G0, IntRegs:$rs2, 15) - 1481
4328 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4329 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4330 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4331 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4332 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1485
4333 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4334 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4335 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4336 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4337 // (TICCrr G0, IntRegs:$rs2, 7) - 1489
4338 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4339 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4340 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4341 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4342 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1493
4343 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4344 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4345 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4346 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4347 // (TRAPri G0, i32imm:$imm, 8) - 1497
4348 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4349 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4350 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4351 // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 1500
4352 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4353 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4354 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4355 // (TRAPri G0, i32imm:$imm, 0) - 1503
4356 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4357 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4358 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4359 // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 1506
4360 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4361 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4362 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4363 // (TRAPri G0, i32imm:$imm, 9) - 1509
4364 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4365 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4366 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4367 // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 1512
4368 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4369 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4370 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4371 // (TRAPri G0, i32imm:$imm, 1) - 1515
4372 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4373 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4374 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4375 // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 1518
4376 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4377 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4378 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4379 // (TRAPri G0, i32imm:$imm, 10) - 1521
4380 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4381 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4382 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4383 // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 1524
4384 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4385 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4386 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4387 // (TRAPri G0, i32imm:$imm, 2) - 1527
4388 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4389 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4390 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4391 // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 1530
4392 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4393 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4394 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4395 // (TRAPri G0, i32imm:$imm, 11) - 1533
4396 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4397 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4398 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4399 // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 1536
4400 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4401 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4402 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4403 // (TRAPri G0, i32imm:$imm, 3) - 1539
4404 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4405 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4406 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4407 // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 1542
4408 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4409 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4410 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4411 // (TRAPri G0, i32imm:$imm, 12) - 1545
4412 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4413 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4414 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4415 // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 1548
4416 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4417 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4418 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4419 // (TRAPri G0, i32imm:$imm, 4) - 1551
4420 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4421 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4422 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4423 // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 1554
4424 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4425 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4426 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4427 // (TRAPri G0, i32imm:$imm, 13) - 1557
4428 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4429 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4430 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4431 // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 1560
4432 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4433 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4434 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4435 // (TRAPri G0, i32imm:$imm, 5) - 1563
4436 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4437 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4438 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4439 // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 1566
4440 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4441 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4442 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4443 // (TRAPri G0, i32imm:$imm, 14) - 1569
4444 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4445 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4446 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4447 // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 1572
4448 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4449 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4450 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4451 // (TRAPri G0, i32imm:$imm, 6) - 1575
4452 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4453 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4454 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4455 // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 1578
4456 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4457 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4458 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4459 // (TRAPri G0, i32imm:$imm, 15) - 1581
4460 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4461 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4462 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4463 // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 1584
4464 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4465 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4466 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4467 // (TRAPri G0, i32imm:$imm, 7) - 1587
4468 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4469 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4470 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4471 // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 1590
4472 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4473 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4474 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4475 // (TRAPrr G0, IntRegs:$rs1, 8) - 1593
4476 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4477 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4478 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4479 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1596
4480 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4481 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4482 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4483 // (TRAPrr G0, IntRegs:$rs1, 0) - 1599
4484 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4485 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4486 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4487 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1602
4488 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4490 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4491 // (TRAPrr G0, IntRegs:$rs1, 9) - 1605
4492 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4493 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4494 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4495 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1608
4496 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4497 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4498 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4499 // (TRAPrr G0, IntRegs:$rs1, 1) - 1611
4500 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4502 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4503 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1614
4504 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4505 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4506 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4507 // (TRAPrr G0, IntRegs:$rs1, 10) - 1617
4508 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4509 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4510 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4511 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1620
4512 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4513 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4514 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4515 // (TRAPrr G0, IntRegs:$rs1, 2) - 1623
4516 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4517 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4518 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4519 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1626
4520 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4521 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4522 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4523 // (TRAPrr G0, IntRegs:$rs1, 11) - 1629
4524 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4525 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4526 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4527 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1632
4528 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4529 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4530 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4531 // (TRAPrr G0, IntRegs:$rs1, 3) - 1635
4532 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4533 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4534 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4535 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1638
4536 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4537 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4538 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4539 // (TRAPrr G0, IntRegs:$rs1, 12) - 1641
4540 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4541 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4542 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4543 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1644
4544 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4545 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4546 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4547 // (TRAPrr G0, IntRegs:$rs1, 4) - 1647
4548 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4549 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4550 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4551 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1650
4552 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4553 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4554 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4555 // (TRAPrr G0, IntRegs:$rs1, 13) - 1653
4556 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4557 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4558 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4559 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1656
4560 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4561 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4562 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4563 // (TRAPrr G0, IntRegs:$rs1, 5) - 1659
4564 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4565 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4566 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4567 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1662
4568 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4569 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4570 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4571 // (TRAPrr G0, IntRegs:$rs1, 14) - 1665
4572 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4573 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4574 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4575 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1668
4576 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4577 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4578 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4579 // (TRAPrr G0, IntRegs:$rs1, 6) - 1671
4580 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4581 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4582 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4583 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1674
4584 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4585 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4586 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4587 // (TRAPrr G0, IntRegs:$rs1, 15) - 1677
4588 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4589 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4590 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4591 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1680
4592 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4593 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4594 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4595 // (TRAPrr G0, IntRegs:$rs1, 7) - 1683
4596 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4597 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4598 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4599 // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1686
4600 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4601 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4602 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4603 // (TXCCri G0, i32imm:$imm, 8) - 1689
4604 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4605 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4606 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4607 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4608 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 1693
4609 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4610 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4611 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4612 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4613 // (TXCCri G0, i32imm:$imm, 0) - 1697
4614 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4615 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4616 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4617 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4618 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 1701
4619 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4620 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4621 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4622 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4623 // (TXCCri G0, i32imm:$imm, 9) - 1705
4624 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4625 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4626 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4627 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4628 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 1709
4629 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4630 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4631 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4632 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4633 // (TXCCri G0, i32imm:$imm, 1) - 1713
4634 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4635 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4636 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4637 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4638 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 1717
4639 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4640 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4641 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4642 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4643 // (TXCCri G0, i32imm:$imm, 10) - 1721
4644 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4645 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4646 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4647 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4648 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 1725
4649 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4650 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4651 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4652 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4653 // (TXCCri G0, i32imm:$imm, 2) - 1729
4654 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4655 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4656 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4657 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4658 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 1733
4659 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4660 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4661 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4662 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4663 // (TXCCri G0, i32imm:$imm, 11) - 1737
4664 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4665 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4666 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4667 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4668 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 1741
4669 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4670 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4671 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4672 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4673 // (TXCCri G0, i32imm:$imm, 3) - 1745
4674 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4675 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4676 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4677 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4678 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 1749
4679 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4680 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4681 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4682 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4683 // (TXCCri G0, i32imm:$imm, 12) - 1753
4684 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4685 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4686 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4687 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4688 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 1757
4689 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4690 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4691 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4692 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4693 // (TXCCri G0, i32imm:$imm, 4) - 1761
4694 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4695 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4696 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4697 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4698 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 1765
4699 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4700 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4701 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4702 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4703 // (TXCCri G0, i32imm:$imm, 13) - 1769
4704 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4705 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4706 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4707 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4708 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 1773
4709 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4710 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4711 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4712 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4713 // (TXCCri G0, i32imm:$imm, 5) - 1777
4714 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4715 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4716 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4717 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4718 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 1781
4719 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4720 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4721 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4722 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4723 // (TXCCri G0, i32imm:$imm, 14) - 1785
4724 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4725 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4726 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4727 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4728 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 1789
4729 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4730 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4731 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4732 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4733 // (TXCCri G0, i32imm:$imm, 6) - 1793
4734 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4735 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4736 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4737 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4738 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 1797
4739 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4740 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4741 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4742 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4743 // (TXCCri G0, i32imm:$imm, 15) - 1801
4744 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4745 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4746 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4747 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4748 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 1805
4749 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4750 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4751 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4752 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4753 // (TXCCri G0, i32imm:$imm, 7) - 1809
4754 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4755 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4756 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4757 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4758 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 1813
4759 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4760 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4761 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4762 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4763 // (TXCCrr G0, IntRegs:$rs2, 8) - 1817
4764 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4765 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4766 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4767 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4768 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1821
4769 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4770 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4771 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4772 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4773 // (TXCCrr G0, IntRegs:$rs2, 0) - 1825
4774 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4775 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4776 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4777 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4778 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1829
4779 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4780 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4781 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4782 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4783 // (TXCCrr G0, IntRegs:$rs2, 9) - 1833
4784 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4785 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4786 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4787 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4788 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1837
4789 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4790 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4791 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
4792 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4793 // (TXCCrr G0, IntRegs:$rs2, 1) - 1841
4794 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4795 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4796 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4797 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4798 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1845
4799 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4800 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4801 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
4802 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4803 // (TXCCrr G0, IntRegs:$rs2, 10) - 1849
4804 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4805 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4806 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4807 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4808 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1853
4809 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4810 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4811 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
4812 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4813 // (TXCCrr G0, IntRegs:$rs2, 2) - 1857
4814 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4815 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4816 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4817 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4818 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1861
4819 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4820 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4821 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
4822 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4823 // (TXCCrr G0, IntRegs:$rs2, 11) - 1865
4824 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4825 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4826 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4827 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4828 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1869
4829 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4830 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4831 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
4832 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4833 // (TXCCrr G0, IntRegs:$rs2, 3) - 1873
4834 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4835 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4836 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4837 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4838 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1877
4839 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4840 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4841 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4842 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4843 // (TXCCrr G0, IntRegs:$rs2, 12) - 1881
4844 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4845 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4846 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4847 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4848 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1885
4849 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4850 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4851 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
4852 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4853 // (TXCCrr G0, IntRegs:$rs2, 4) - 1889
4854 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4855 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4856 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4857 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4858 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1893
4859 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4860 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4861 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4862 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4863 // (TXCCrr G0, IntRegs:$rs2, 13) - 1897
4864 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4865 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4866 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4867 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4868 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1901
4869 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4870 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4871 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
4872 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4873 // (TXCCrr G0, IntRegs:$rs2, 5) - 1905
4874 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4875 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4876 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4877 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4878 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1909
4879 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4880 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4881 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4882 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4883 // (TXCCrr G0, IntRegs:$rs2, 14) - 1913
4884 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4885 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4886 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4887 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4888 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1917
4889 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4890 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4891 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
4892 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4893 // (TXCCrr G0, IntRegs:$rs2, 6) - 1921
4894 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4895 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4896 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4897 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4898 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1925
4899 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4900 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4901 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4902 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4903 // (TXCCrr G0, IntRegs:$rs2, 15) - 1929
4904 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4905 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4906 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4907 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4908 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1933
4909 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4910 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4911 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
4912 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4913 // (TXCCrr G0, IntRegs:$rs2, 7) - 1937
4914 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::G0},
4915 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4916 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4917 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4918 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1941
4919 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4920 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
4921 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4922 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4923 // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 1945
4924 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
4925 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4926 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4927 // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 1948
4928 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
4929 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4930 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4931 // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 1951
4932 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
4933 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4934 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4935 // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 1954
4936 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
4937 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4938 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4939 // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 1957
4940 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
4941 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4942 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
4943 // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 1960
4944 {.Kind: AliasPatternCond::K_Reg, .Value: Sparc::FCC0},
4945 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4946 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
4947 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 1963
4948 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4949 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
4950 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4951 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4952 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
4953 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4954 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 1969
4955 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4956 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
4957 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4958 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4959 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
4960 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4961 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 1975
4962 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4963 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
4964 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4965 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4966 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
4967 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4968 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 1981
4969 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4970 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
4971 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4972 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4973 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
4974 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4975 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 1987
4976 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4977 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
4978 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4979 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4980 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
4981 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4982 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 1993
4983 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4984 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
4985 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4986 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4987 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
4988 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4989 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 1999
4990 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4991 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
4992 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4993 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
4994 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
4995 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
4996 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 2005
4997 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
4998 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
4999 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5000 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5001 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5002 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5003 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 2011
5004 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5005 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5006 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5007 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5008 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5009 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5010 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 2017
5011 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5012 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5013 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5014 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5015 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5016 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5017 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 2023
5018 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5019 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5020 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5021 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5022 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5023 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5024 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 2029
5025 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5026 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5027 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5028 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5029 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5030 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5031 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 2035
5032 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5033 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5034 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5035 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5036 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5037 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5038 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 2041
5039 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5040 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5041 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5042 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5043 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5044 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5045 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 2047
5046 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5047 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5048 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5049 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5050 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5051 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5052 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 2053
5053 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5054 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5055 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::DFPRegsRegClassID},
5056 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5057 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5058 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5059 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 2059
5060 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5061 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5062 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5063 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5064 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5065 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5066 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 2065
5067 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5068 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5069 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5070 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5071 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5072 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5073 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 2071
5074 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5075 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5076 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5077 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5078 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5079 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5080 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 2077
5081 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5082 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5083 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5084 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5085 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5086 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5087 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 2083
5088 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5089 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5090 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5091 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5092 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5093 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5094 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 2089
5095 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5096 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5097 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5098 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5099 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5100 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5101 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 2095
5102 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5103 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5104 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5105 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5106 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5107 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5108 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 2101
5109 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5110 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5111 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5112 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5113 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5114 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5115 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 2107
5116 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5117 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5118 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5119 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5120 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5121 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5122 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 2113
5123 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5124 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5125 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5126 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5127 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5128 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5129 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 2119
5130 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5131 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5132 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5133 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5134 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5135 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5136 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 2125
5137 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5138 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5139 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5140 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5141 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5142 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5143 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 2131
5144 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5145 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5146 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5147 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5148 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5149 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5150 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 2137
5151 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5152 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5153 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5154 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5155 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5156 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5157 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 2143
5158 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5159 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5160 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5161 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5162 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5163 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5164 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 2149
5165 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5166 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5167 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::QFPRegsRegClassID},
5168 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5169 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5170 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5171 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 2155
5172 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5173 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5174 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5175 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5176 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5177 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5178 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 2161
5179 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5180 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5181 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5182 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5183 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5184 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5185 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 2167
5186 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5187 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5188 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5189 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5190 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5191 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5192 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 2173
5193 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5194 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5195 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5196 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5197 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5198 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5199 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 2179
5200 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5201 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5202 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5203 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5204 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5205 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5206 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 2185
5207 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5208 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5209 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5210 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5211 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5212 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5213 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 2191
5214 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5215 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5216 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5217 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5218 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5219 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5220 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 2197
5221 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5222 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5223 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5224 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5225 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5226 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5227 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 2203
5228 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5229 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5230 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5231 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5232 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5233 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5234 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 2209
5235 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5236 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5237 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5238 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5239 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5240 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5241 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 2215
5242 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5243 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5244 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5245 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5246 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5247 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5248 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 2221
5249 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5250 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5251 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5252 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5253 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5254 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5255 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 2227
5256 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5257 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5258 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5259 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5260 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5261 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5262 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 2233
5263 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5264 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5265 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5266 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5267 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5268 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5269 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 2239
5270 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5271 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5272 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5273 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5274 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5275 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5276 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 2245
5277 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5278 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5279 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FPRegsRegClassID},
5280 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5281 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5282 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5283 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 2251
5284 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5285 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5286 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5287 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5288 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5289 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5290 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 2257
5291 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5292 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5293 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5294 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5295 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5296 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5297 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 2263
5298 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5299 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5300 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5301 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5302 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5303 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5304 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 2269
5305 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5306 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5307 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5308 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5309 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5310 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5311 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 2275
5312 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5313 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5314 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5315 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5316 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5317 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5318 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 2281
5319 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5320 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5321 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5322 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5323 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5324 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5325 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 2287
5326 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5327 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5328 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5329 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5330 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5331 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5332 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 2293
5333 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5334 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5335 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5336 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5337 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5338 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5339 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 2299
5340 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5341 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5342 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5343 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5344 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5345 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5346 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 2305
5347 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5348 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5349 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5350 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5351 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5352 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5353 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 2311
5354 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5355 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5356 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5357 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5358 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5359 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5360 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 2317
5361 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5362 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5363 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5364 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5365 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5366 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5367 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 2323
5368 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5369 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5370 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5371 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5372 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5373 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5374 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 2329
5375 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5376 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5377 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5378 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5379 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5380 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5381 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 2335
5382 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5383 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5384 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5385 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5386 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5387 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5388 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 2341
5389 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5390 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5391 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5392 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5393 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5394 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5395 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 2347
5396 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5397 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5398 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5399 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5400 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(8)},
5401 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5402 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 2353
5403 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5404 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5405 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5406 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5407 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)},
5408 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5409 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 2359
5410 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5411 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5412 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5413 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5414 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)},
5415 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5416 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 2365
5417 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5418 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5419 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5420 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5421 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)},
5422 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5423 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 2371
5424 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5425 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5426 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5427 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5428 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)},
5429 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5430 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 2377
5431 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5432 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5433 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5434 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5435 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)},
5436 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5437 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 2383
5438 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5439 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5440 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5441 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5442 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)},
5443 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5444 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 2389
5445 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5446 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5447 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5448 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5449 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)},
5450 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5451 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 2395
5452 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5453 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5454 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5455 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5456 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)},
5457 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5458 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 2401
5459 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5460 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5461 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5462 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5463 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(9)},
5464 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5465 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 2407
5466 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5467 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5468 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5469 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5470 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(10)},
5471 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5472 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 2413
5473 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5474 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5475 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5476 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5477 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(11)},
5478 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5479 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 2419
5480 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5481 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5482 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5483 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5484 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)},
5485 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5486 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 2425
5487 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5488 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5489 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5490 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5491 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(13)},
5492 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5493 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 2431
5494 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5495 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5496 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5497 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5498 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(14)},
5499 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5500 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 2437
5501 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5502 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::FCCRegsRegClassID},
5503 {.Kind: AliasPatternCond::K_RegClass, .Value: Sparc::IntRegsRegClassID},
5504 {.Kind: AliasPatternCond::K_Ignore, .Value: 0},
5505 {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)},
5506 {.Kind: AliasPatternCond::K_Feature, .Value: Sparc::FeatureV9},
5507 };
5508
5509 static const char AsmStrings[] =
5510 /* 0 */ "ba $\x01\0"
5511 /* 6 */ "bn $\x01\0"
5512 /* 12 */ "bne $\x01\0"
5513 /* 19 */ "be $\x01\0"
5514 /* 25 */ "bg $\x01\0"
5515 /* 31 */ "ble $\x01\0"
5516 /* 38 */ "bge $\x01\0"
5517 /* 45 */ "bl $\x01\0"
5518 /* 51 */ "bgu $\x01\0"
5519 /* 58 */ "bleu $\x01\0"
5520 /* 66 */ "bcc $\x01\0"
5521 /* 73 */ "bcs $\x01\0"
5522 /* 80 */ "bpos $\x01\0"
5523 /* 88 */ "bneg $\x01\0"
5524 /* 96 */ "bvc $\x01\0"
5525 /* 103 */ "bvs $\x01\0"
5526 /* 110 */ "ba,a $\x01\0"
5527 /* 118 */ "bn,a $\x01\0"
5528 /* 126 */ "bne,a $\x01\0"
5529 /* 135 */ "be,a $\x01\0"
5530 /* 143 */ "bg,a $\x01\0"
5531 /* 151 */ "ble,a $\x01\0"
5532 /* 160 */ "bge,a $\x01\0"
5533 /* 169 */ "bl,a $\x01\0"
5534 /* 177 */ "bgu,a $\x01\0"
5535 /* 186 */ "bleu,a $\x01\0"
5536 /* 196 */ "bcc,a $\x01\0"
5537 /* 205 */ "bcs,a $\x01\0"
5538 /* 214 */ "bpos,a $\x01\0"
5539 /* 224 */ "bneg,a $\x01\0"
5540 /* 234 */ "bvc,a $\x01\0"
5541 /* 243 */ "bvs,a $\x01\0"
5542 /* 252 */ "fba,a,pn $\x03, $\x01\0"
5543 /* 268 */ "fbn,a,pn $\x03, $\x01\0"
5544 /* 284 */ "fbu,a,pn $\x03, $\x01\0"
5545 /* 300 */ "fbg,a,pn $\x03, $\x01\0"
5546 /* 316 */ "fbug,a,pn $\x03, $\x01\0"
5547 /* 333 */ "fbl,a,pn $\x03, $\x01\0"
5548 /* 349 */ "fbul,a,pn $\x03, $\x01\0"
5549 /* 366 */ "fblg,a,pn $\x03, $\x01\0"
5550 /* 383 */ "fbne,a,pn $\x03, $\x01\0"
5551 /* 400 */ "fbe,a,pn $\x03, $\x01\0"
5552 /* 416 */ "fbue,a,pn $\x03, $\x01\0"
5553 /* 433 */ "fbge,a,pn $\x03, $\x01\0"
5554 /* 450 */ "fbuge,a,pn $\x03, $\x01\0"
5555 /* 468 */ "fble,a,pn $\x03, $\x01\0"
5556 /* 485 */ "fbule,a,pn $\x03, $\x01\0"
5557 /* 503 */ "fbo,a,pn $\x03, $\x01\0"
5558 /* 519 */ "fba,pn $\x03, $\x01\0"
5559 /* 533 */ "fbn,pn $\x03, $\x01\0"
5560 /* 547 */ "fbu,pn $\x03, $\x01\0"
5561 /* 561 */ "fbg,pn $\x03, $\x01\0"
5562 /* 575 */ "fbug,pn $\x03, $\x01\0"
5563 /* 590 */ "fbl,pn $\x03, $\x01\0"
5564 /* 604 */ "fbul,pn $\x03, $\x01\0"
5565 /* 619 */ "fblg,pn $\x03, $\x01\0"
5566 /* 634 */ "fbne,pn $\x03, $\x01\0"
5567 /* 649 */ "fbe,pn $\x03, $\x01\0"
5568 /* 663 */ "fbue,pn $\x03, $\x01\0"
5569 /* 678 */ "fbge,pn $\x03, $\x01\0"
5570 /* 693 */ "fbuge,pn $\x03, $\x01\0"
5571 /* 709 */ "fble,pn $\x03, $\x01\0"
5572 /* 724 */ "fbule,pn $\x03, $\x01\0"
5573 /* 740 */ "fbo,pn $\x03, $\x01\0"
5574 /* 754 */ "ba,a,pn %icc, $\x01\0"
5575 /* 771 */ "bn,a,pn %icc, $\x01\0"
5576 /* 788 */ "bne,a,pn %icc, $\x01\0"
5577 /* 806 */ "be,a,pn %icc, $\x01\0"
5578 /* 823 */ "bg,a,pn %icc, $\x01\0"
5579 /* 840 */ "ble,a,pn %icc, $\x01\0"
5580 /* 858 */ "bge,a,pn %icc, $\x01\0"
5581 /* 876 */ "bl,a,pn %icc, $\x01\0"
5582 /* 893 */ "bgu,a,pn %icc, $\x01\0"
5583 /* 911 */ "bleu,a,pn %icc, $\x01\0"
5584 /* 930 */ "bcc,a,pn %icc, $\x01\0"
5585 /* 948 */ "bcs,a,pn %icc, $\x01\0"
5586 /* 966 */ "bpos,a,pn %icc, $\x01\0"
5587 /* 985 */ "bneg,a,pn %icc, $\x01\0"
5588 /* 1004 */ "bvc,a,pn %icc, $\x01\0"
5589 /* 1022 */ "bvs,a,pn %icc, $\x01\0"
5590 /* 1040 */ "ba,pn %icc, $\x01\0"
5591 /* 1055 */ "bn,pn %icc, $\x01\0"
5592 /* 1070 */ "bne,pn %icc, $\x01\0"
5593 /* 1086 */ "be,pn %icc, $\x01\0"
5594 /* 1101 */ "bg,pn %icc, $\x01\0"
5595 /* 1116 */ "ble,pn %icc, $\x01\0"
5596 /* 1132 */ "bge,pn %icc, $\x01\0"
5597 /* 1148 */ "bl,pn %icc, $\x01\0"
5598 /* 1163 */ "bgu,pn %icc, $\x01\0"
5599 /* 1179 */ "bleu,pn %icc, $\x01\0"
5600 /* 1196 */ "bcc,pn %icc, $\x01\0"
5601 /* 1212 */ "bcs,pn %icc, $\x01\0"
5602 /* 1228 */ "bpos,pn %icc, $\x01\0"
5603 /* 1245 */ "bneg,pn %icc, $\x01\0"
5604 /* 1262 */ "bvc,pn %icc, $\x01\0"
5605 /* 1278 */ "bvs,pn %icc, $\x01\0"
5606 /* 1294 */ "brlez,a,pn $\x03, $\x01\0"
5607 /* 1312 */ "brlz,a,pn $\x03, $\x01\0"
5608 /* 1329 */ "brgz,a,pn $\x03, $\x01\0"
5609 /* 1346 */ "brgez,a,pn $\x03, $\x01\0"
5610 /* 1364 */ "brlez,pn $\x03, $\x01\0"
5611 /* 1380 */ "brlz,pn $\x03, $\x01\0"
5612 /* 1395 */ "brgz,pn $\x03, $\x01\0"
5613 /* 1410 */ "brgez,pn $\x03, $\x01\0"
5614 /* 1426 */ "ba,a,pn %xcc, $\x01\0"
5615 /* 1443 */ "bn,a,pn %xcc, $\x01\0"
5616 /* 1460 */ "bne,a,pn %xcc, $\x01\0"
5617 /* 1478 */ "be,a,pn %xcc, $\x01\0"
5618 /* 1495 */ "bg,a,pn %xcc, $\x01\0"
5619 /* 1512 */ "ble,a,pn %xcc, $\x01\0"
5620 /* 1530 */ "bge,a,pn %xcc, $\x01\0"
5621 /* 1548 */ "bl,a,pn %xcc, $\x01\0"
5622 /* 1565 */ "bgu,a,pn %xcc, $\x01\0"
5623 /* 1583 */ "bleu,a,pn %xcc, $\x01\0"
5624 /* 1602 */ "bcc,a,pn %xcc, $\x01\0"
5625 /* 1620 */ "bcs,a,pn %xcc, $\x01\0"
5626 /* 1638 */ "bpos,a,pn %xcc, $\x01\0"
5627 /* 1657 */ "bneg,a,pn %xcc, $\x01\0"
5628 /* 1676 */ "bvc,a,pn %xcc, $\x01\0"
5629 /* 1694 */ "bvs,a,pn %xcc, $\x01\0"
5630 /* 1712 */ "ba,pn %xcc, $\x01\0"
5631 /* 1727 */ "bn,pn %xcc, $\x01\0"
5632 /* 1742 */ "bne,pn %xcc, $\x01\0"
5633 /* 1758 */ "be,pn %xcc, $\x01\0"
5634 /* 1773 */ "bg,pn %xcc, $\x01\0"
5635 /* 1788 */ "ble,pn %xcc, $\x01\0"
5636 /* 1804 */ "bge,pn %xcc, $\x01\0"
5637 /* 1820 */ "bl,pn %xcc, $\x01\0"
5638 /* 1835 */ "bgu,pn %xcc, $\x01\0"
5639 /* 1851 */ "bleu,pn %xcc, $\x01\0"
5640 /* 1868 */ "bcc,pn %xcc, $\x01\0"
5641 /* 1884 */ "bcs,pn %xcc, $\x01\0"
5642 /* 1900 */ "bpos,pn %xcc, $\x01\0"
5643 /* 1917 */ "bneg,pn %xcc, $\x01\0"
5644 /* 1934 */ "bvc,pn %xcc, $\x01\0"
5645 /* 1950 */ "bvs,pn %xcc, $\x01\0"
5646 /* 1966 */ "cas [$\x02], $\x03, $\x01\0"
5647 /* 1983 */ "casl [$\x02], $\x03, $\x01\0"
5648 /* 2001 */ "casx [$\x02], $\x03, $\x01\0"
5649 /* 2019 */ "casxl [$\x02], $\x03, $\x01\0"
5650 /* 2038 */ "fmovda %icc, $\x02, $\x01\0"
5651 /* 2058 */ "fmovdn %icc, $\x02, $\x01\0"
5652 /* 2078 */ "fmovdne %icc, $\x02, $\x01\0"
5653 /* 2099 */ "fmovde %icc, $\x02, $\x01\0"
5654 /* 2119 */ "fmovdg %icc, $\x02, $\x01\0"
5655 /* 2139 */ "fmovdle %icc, $\x02, $\x01\0"
5656 /* 2160 */ "fmovdge %icc, $\x02, $\x01\0"
5657 /* 2181 */ "fmovdl %icc, $\x02, $\x01\0"
5658 /* 2201 */ "fmovdgu %icc, $\x02, $\x01\0"
5659 /* 2222 */ "fmovdleu %icc, $\x02, $\x01\0"
5660 /* 2244 */ "fmovdcc %icc, $\x02, $\x01\0"
5661 /* 2265 */ "fmovdcs %icc, $\x02, $\x01\0"
5662 /* 2286 */ "fmovdpos %icc, $\x02, $\x01\0"
5663 /* 2308 */ "fmovdneg %icc, $\x02, $\x01\0"
5664 /* 2330 */ "fmovdvc %icc, $\x02, $\x01\0"
5665 /* 2351 */ "fmovdvs %icc, $\x02, $\x01\0"
5666 /* 2372 */ "fmovda %xcc, $\x02, $\x01\0"
5667 /* 2392 */ "fmovdn %xcc, $\x02, $\x01\0"
5668 /* 2412 */ "fmovdne %xcc, $\x02, $\x01\0"
5669 /* 2433 */ "fmovde %xcc, $\x02, $\x01\0"
5670 /* 2453 */ "fmovdg %xcc, $\x02, $\x01\0"
5671 /* 2473 */ "fmovdle %xcc, $\x02, $\x01\0"
5672 /* 2494 */ "fmovdge %xcc, $\x02, $\x01\0"
5673 /* 2515 */ "fmovdl %xcc, $\x02, $\x01\0"
5674 /* 2535 */ "fmovdgu %xcc, $\x02, $\x01\0"
5675 /* 2556 */ "fmovdleu %xcc, $\x02, $\x01\0"
5676 /* 2578 */ "fmovdcc %xcc, $\x02, $\x01\0"
5677 /* 2599 */ "fmovdcs %xcc, $\x02, $\x01\0"
5678 /* 2620 */ "fmovdpos %xcc, $\x02, $\x01\0"
5679 /* 2642 */ "fmovdneg %xcc, $\x02, $\x01\0"
5680 /* 2664 */ "fmovdvc %xcc, $\x02, $\x01\0"
5681 /* 2685 */ "fmovdvs %xcc, $\x02, $\x01\0"
5682 /* 2706 */ "fmovqa %icc, $\x02, $\x01\0"
5683 /* 2726 */ "fmovqn %icc, $\x02, $\x01\0"
5684 /* 2746 */ "fmovqne %icc, $\x02, $\x01\0"
5685 /* 2767 */ "fmovqe %icc, $\x02, $\x01\0"
5686 /* 2787 */ "fmovqg %icc, $\x02, $\x01\0"
5687 /* 2807 */ "fmovqle %icc, $\x02, $\x01\0"
5688 /* 2828 */ "fmovqge %icc, $\x02, $\x01\0"
5689 /* 2849 */ "fmovql %icc, $\x02, $\x01\0"
5690 /* 2869 */ "fmovqgu %icc, $\x02, $\x01\0"
5691 /* 2890 */ "fmovqleu %icc, $\x02, $\x01\0"
5692 /* 2912 */ "fmovqcc %icc, $\x02, $\x01\0"
5693 /* 2933 */ "fmovqcs %icc, $\x02, $\x01\0"
5694 /* 2954 */ "fmovqpos %icc, $\x02, $\x01\0"
5695 /* 2976 */ "fmovqneg %icc, $\x02, $\x01\0"
5696 /* 2998 */ "fmovqvc %icc, $\x02, $\x01\0"
5697 /* 3019 */ "fmovqvs %icc, $\x02, $\x01\0"
5698 /* 3040 */ "fmovqa %xcc, $\x02, $\x01\0"
5699 /* 3060 */ "fmovqn %xcc, $\x02, $\x01\0"
5700 /* 3080 */ "fmovqne %xcc, $\x02, $\x01\0"
5701 /* 3101 */ "fmovqe %xcc, $\x02, $\x01\0"
5702 /* 3121 */ "fmovqg %xcc, $\x02, $\x01\0"
5703 /* 3141 */ "fmovqle %xcc, $\x02, $\x01\0"
5704 /* 3162 */ "fmovqge %xcc, $\x02, $\x01\0"
5705 /* 3183 */ "fmovql %xcc, $\x02, $\x01\0"
5706 /* 3203 */ "fmovqgu %xcc, $\x02, $\x01\0"
5707 /* 3224 */ "fmovqleu %xcc, $\x02, $\x01\0"
5708 /* 3246 */ "fmovqcc %xcc, $\x02, $\x01\0"
5709 /* 3267 */ "fmovqcs %xcc, $\x02, $\x01\0"
5710 /* 3288 */ "fmovqpos %xcc, $\x02, $\x01\0"
5711 /* 3310 */ "fmovqneg %xcc, $\x02, $\x01\0"
5712 /* 3332 */ "fmovqvc %xcc, $\x02, $\x01\0"
5713 /* 3353 */ "fmovqvs %xcc, $\x02, $\x01\0"
5714 /* 3374 */ "fmovrdlez $\x02, $\x03, $\x01\0"
5715 /* 3395 */ "fmovrdlz $\x02, $\x03, $\x01\0"
5716 /* 3415 */ "fmovrdgz $\x02, $\x03, $\x01\0"
5717 /* 3435 */ "fmovrdgez $\x02, $\x03, $\x01\0"
5718 /* 3456 */ "fmovrqlez $\x02, $\x03, $\x01\0"
5719 /* 3477 */ "fmovrqlz $\x02, $\x03, $\x01\0"
5720 /* 3497 */ "fmovrqgz $\x02, $\x03, $\x01\0"
5721 /* 3517 */ "fmovrqgez $\x02, $\x03, $\x01\0"
5722 /* 3538 */ "fmovrslez $\x02, $\x03, $\x01\0"
5723 /* 3559 */ "fmovrslz $\x02, $\x03, $\x01\0"
5724 /* 3579 */ "fmovrsgz $\x02, $\x03, $\x01\0"
5725 /* 3599 */ "fmovrsgez $\x02, $\x03, $\x01\0"
5726 /* 3620 */ "fmovsa %icc, $\x02, $\x01\0"
5727 /* 3640 */ "fmovsn %icc, $\x02, $\x01\0"
5728 /* 3660 */ "fmovsne %icc, $\x02, $\x01\0"
5729 /* 3681 */ "fmovse %icc, $\x02, $\x01\0"
5730 /* 3701 */ "fmovsg %icc, $\x02, $\x01\0"
5731 /* 3721 */ "fmovsle %icc, $\x02, $\x01\0"
5732 /* 3742 */ "fmovsge %icc, $\x02, $\x01\0"
5733 /* 3763 */ "fmovsl %icc, $\x02, $\x01\0"
5734 /* 3783 */ "fmovsgu %icc, $\x02, $\x01\0"
5735 /* 3804 */ "fmovsleu %icc, $\x02, $\x01\0"
5736 /* 3826 */ "fmovscc %icc, $\x02, $\x01\0"
5737 /* 3847 */ "fmovscs %icc, $\x02, $\x01\0"
5738 /* 3868 */ "fmovspos %icc, $\x02, $\x01\0"
5739 /* 3890 */ "fmovsneg %icc, $\x02, $\x01\0"
5740 /* 3912 */ "fmovsvc %icc, $\x02, $\x01\0"
5741 /* 3933 */ "fmovsvs %icc, $\x02, $\x01\0"
5742 /* 3954 */ "fmovsa %xcc, $\x02, $\x01\0"
5743 /* 3974 */ "fmovsn %xcc, $\x02, $\x01\0"
5744 /* 3994 */ "fmovsne %xcc, $\x02, $\x01\0"
5745 /* 4015 */ "fmovse %xcc, $\x02, $\x01\0"
5746 /* 4035 */ "fmovsg %xcc, $\x02, $\x01\0"
5747 /* 4055 */ "fmovsle %xcc, $\x02, $\x01\0"
5748 /* 4076 */ "fmovsge %xcc, $\x02, $\x01\0"
5749 /* 4097 */ "fmovsl %xcc, $\x02, $\x01\0"
5750 /* 4117 */ "fmovsgu %xcc, $\x02, $\x01\0"
5751 /* 4138 */ "fmovsleu %xcc, $\x02, $\x01\0"
5752 /* 4160 */ "fmovscc %xcc, $\x02, $\x01\0"
5753 /* 4181 */ "fmovscs %xcc, $\x02, $\x01\0"
5754 /* 4202 */ "fmovspos %xcc, $\x02, $\x01\0"
5755 /* 4224 */ "fmovsneg %xcc, $\x02, $\x01\0"
5756 /* 4246 */ "fmovsvc %xcc, $\x02, $\x01\0"
5757 /* 4267 */ "fmovsvs %xcc, $\x02, $\x01\0"
5758 /* 4288 */ "mova %icc, $\x02, $\x01\0"
5759 /* 4306 */ "movn %icc, $\x02, $\x01\0"
5760 /* 4324 */ "movne %icc, $\x02, $\x01\0"
5761 /* 4343 */ "move %icc, $\x02, $\x01\0"
5762 /* 4361 */ "movg %icc, $\x02, $\x01\0"
5763 /* 4379 */ "movle %icc, $\x02, $\x01\0"
5764 /* 4398 */ "movge %icc, $\x02, $\x01\0"
5765 /* 4417 */ "movl %icc, $\x02, $\x01\0"
5766 /* 4435 */ "movgu %icc, $\x02, $\x01\0"
5767 /* 4454 */ "movleu %icc, $\x02, $\x01\0"
5768 /* 4474 */ "movcc %icc, $\x02, $\x01\0"
5769 /* 4493 */ "movcs %icc, $\x02, $\x01\0"
5770 /* 4512 */ "movpos %icc, $\x02, $\x01\0"
5771 /* 4532 */ "movneg %icc, $\x02, $\x01\0"
5772 /* 4552 */ "movvc %icc, $\x02, $\x01\0"
5773 /* 4571 */ "movvs %icc, $\x02, $\x01\0"
5774 /* 4590 */ "movrlez $\x02, $\x03, $\x01\0"
5775 /* 4609 */ "movrlz $\x02, $\x03, $\x01\0"
5776 /* 4627 */ "movrgz $\x02, $\x03, $\x01\0"
5777 /* 4645 */ "movrgez $\x02, $\x03, $\x01\0"
5778 /* 4664 */ "mova %xcc, $\x02, $\x01\0"
5779 /* 4682 */ "movn %xcc, $\x02, $\x01\0"
5780 /* 4700 */ "movne %xcc, $\x02, $\x01\0"
5781 /* 4719 */ "move %xcc, $\x02, $\x01\0"
5782 /* 4737 */ "movg %xcc, $\x02, $\x01\0"
5783 /* 4755 */ "movle %xcc, $\x02, $\x01\0"
5784 /* 4774 */ "movge %xcc, $\x02, $\x01\0"
5785 /* 4793 */ "movl %xcc, $\x02, $\x01\0"
5786 /* 4811 */ "movgu %xcc, $\x02, $\x01\0"
5787 /* 4830 */ "movleu %xcc, $\x02, $\x01\0"
5788 /* 4850 */ "movcc %xcc, $\x02, $\x01\0"
5789 /* 4869 */ "movcs %xcc, $\x02, $\x01\0"
5790 /* 4888 */ "movpos %xcc, $\x02, $\x01\0"
5791 /* 4908 */ "movneg %xcc, $\x02, $\x01\0"
5792 /* 4928 */ "movvc %xcc, $\x02, $\x01\0"
5793 /* 4947 */ "movvs %xcc, $\x02, $\x01\0"
5794 /* 4966 */ "tst $\x02\0"
5795 /* 4973 */ "mov $\x03, $\x01\0"
5796 /* 4984 */ "restore\0"
5797 /* 4992 */ "ret\0"
5798 /* 4996 */ "retl\0"
5799 /* 5001 */ "save\0"
5800 /* 5006 */ "cmp $\x02, $\x03\0"
5801 /* 5017 */ "ta %icc, $\x02\0"
5802 /* 5029 */ "ta %icc, $\x01 + $\x02\0"
5803 /* 5046 */ "tn %icc, $\x02\0"
5804 /* 5058 */ "tn %icc, $\x01 + $\x02\0"
5805 /* 5075 */ "tne %icc, $\x02\0"
5806 /* 5088 */ "tne %icc, $\x01 + $\x02\0"
5807 /* 5106 */ "te %icc, $\x02\0"
5808 /* 5118 */ "te %icc, $\x01 + $\x02\0"
5809 /* 5135 */ "tg %icc, $\x02\0"
5810 /* 5147 */ "tg %icc, $\x01 + $\x02\0"
5811 /* 5164 */ "tle %icc, $\x02\0"
5812 /* 5177 */ "tle %icc, $\x01 + $\x02\0"
5813 /* 5195 */ "tge %icc, $\x02\0"
5814 /* 5208 */ "tge %icc, $\x01 + $\x02\0"
5815 /* 5226 */ "tl %icc, $\x02\0"
5816 /* 5238 */ "tl %icc, $\x01 + $\x02\0"
5817 /* 5255 */ "tgu %icc, $\x02\0"
5818 /* 5268 */ "tgu %icc, $\x01 + $\x02\0"
5819 /* 5286 */ "tleu %icc, $\x02\0"
5820 /* 5300 */ "tleu %icc, $\x01 + $\x02\0"
5821 /* 5319 */ "tcc %icc, $\x02\0"
5822 /* 5332 */ "tcc %icc, $\x01 + $\x02\0"
5823 /* 5350 */ "tcs %icc, $\x02\0"
5824 /* 5363 */ "tcs %icc, $\x01 + $\x02\0"
5825 /* 5381 */ "tpos %icc, $\x02\0"
5826 /* 5395 */ "tpos %icc, $\x01 + $\x02\0"
5827 /* 5414 */ "tneg %icc, $\x02\0"
5828 /* 5428 */ "tneg %icc, $\x01 + $\x02\0"
5829 /* 5447 */ "tvc %icc, $\x02\0"
5830 /* 5460 */ "tvc %icc, $\x01 + $\x02\0"
5831 /* 5478 */ "tvs %icc, $\x02\0"
5832 /* 5491 */ "tvs %icc, $\x01 + $\x02\0"
5833 /* 5509 */ "ta $\x02\0"
5834 /* 5515 */ "ta $\x01 + $\x02\0"
5835 /* 5526 */ "tn $\x02\0"
5836 /* 5532 */ "tn $\x01 + $\x02\0"
5837 /* 5543 */ "tne $\x02\0"
5838 /* 5550 */ "tne $\x01 + $\x02\0"
5839 /* 5562 */ "te $\x02\0"
5840 /* 5568 */ "te $\x01 + $\x02\0"
5841 /* 5579 */ "tg $\x02\0"
5842 /* 5585 */ "tg $\x01 + $\x02\0"
5843 /* 5596 */ "tle $\x02\0"
5844 /* 5603 */ "tle $\x01 + $\x02\0"
5845 /* 5615 */ "tge $\x02\0"
5846 /* 5622 */ "tge $\x01 + $\x02\0"
5847 /* 5634 */ "tl $\x02\0"
5848 /* 5640 */ "tl $\x01 + $\x02\0"
5849 /* 5651 */ "tgu $\x02\0"
5850 /* 5658 */ "tgu $\x01 + $\x02\0"
5851 /* 5670 */ "tleu $\x02\0"
5852 /* 5678 */ "tleu $\x01 + $\x02\0"
5853 /* 5691 */ "tcc $\x02\0"
5854 /* 5698 */ "tcc $\x01 + $\x02\0"
5855 /* 5710 */ "tcs $\x02\0"
5856 /* 5717 */ "tcs $\x01 + $\x02\0"
5857 /* 5729 */ "tpos $\x02\0"
5858 /* 5737 */ "tpos $\x01 + $\x02\0"
5859 /* 5750 */ "tneg $\x02\0"
5860 /* 5758 */ "tneg $\x01 + $\x02\0"
5861 /* 5771 */ "tvc $\x02\0"
5862 /* 5778 */ "tvc $\x01 + $\x02\0"
5863 /* 5790 */ "tvs $\x02\0"
5864 /* 5797 */ "tvs $\x01 + $\x02\0"
5865 /* 5809 */ "ta %xcc, $\x02\0"
5866 /* 5821 */ "ta %xcc, $\x01 + $\x02\0"
5867 /* 5838 */ "tn %xcc, $\x02\0"
5868 /* 5850 */ "tn %xcc, $\x01 + $\x02\0"
5869 /* 5867 */ "tne %xcc, $\x02\0"
5870 /* 5880 */ "tne %xcc, $\x01 + $\x02\0"
5871 /* 5898 */ "te %xcc, $\x02\0"
5872 /* 5910 */ "te %xcc, $\x01 + $\x02\0"
5873 /* 5927 */ "tg %xcc, $\x02\0"
5874 /* 5939 */ "tg %xcc, $\x01 + $\x02\0"
5875 /* 5956 */ "tle %xcc, $\x02\0"
5876 /* 5969 */ "tle %xcc, $\x01 + $\x02\0"
5877 /* 5987 */ "tge %xcc, $\x02\0"
5878 /* 6000 */ "tge %xcc, $\x01 + $\x02\0"
5879 /* 6018 */ "tl %xcc, $\x02\0"
5880 /* 6030 */ "tl %xcc, $\x01 + $\x02\0"
5881 /* 6047 */ "tgu %xcc, $\x02\0"
5882 /* 6060 */ "tgu %xcc, $\x01 + $\x02\0"
5883 /* 6078 */ "tleu %xcc, $\x02\0"
5884 /* 6092 */ "tleu %xcc, $\x01 + $\x02\0"
5885 /* 6111 */ "tcc %xcc, $\x02\0"
5886 /* 6124 */ "tcc %xcc, $\x01 + $\x02\0"
5887 /* 6142 */ "tcs %xcc, $\x02\0"
5888 /* 6155 */ "tcs %xcc, $\x01 + $\x02\0"
5889 /* 6173 */ "tpos %xcc, $\x02\0"
5890 /* 6187 */ "tpos %xcc, $\x01 + $\x02\0"
5891 /* 6206 */ "tneg %xcc, $\x02\0"
5892 /* 6220 */ "tneg %xcc, $\x01 + $\x02\0"
5893 /* 6239 */ "tvc %xcc, $\x02\0"
5894 /* 6252 */ "tvc %xcc, $\x01 + $\x02\0"
5895 /* 6270 */ "tvs %xcc, $\x02\0"
5896 /* 6283 */ "tvs %xcc, $\x01 + $\x02\0"
5897 /* 6301 */ "fcmpd $\x02, $\x03\0"
5898 /* 6314 */ "fcmped $\x02, $\x03\0"
5899 /* 6328 */ "fcmpeq $\x02, $\x03\0"
5900 /* 6342 */ "fcmpes $\x02, $\x03\0"
5901 /* 6356 */ "fcmpq $\x02, $\x03\0"
5902 /* 6369 */ "fcmps $\x02, $\x03\0"
5903 /* 6382 */ "fmovda $\x02, $\x03, $\x01\0"
5904 /* 6400 */ "fmovdn $\x02, $\x03, $\x01\0"
5905 /* 6418 */ "fmovdu $\x02, $\x03, $\x01\0"
5906 /* 6436 */ "fmovdg $\x02, $\x03, $\x01\0"
5907 /* 6454 */ "fmovdug $\x02, $\x03, $\x01\0"
5908 /* 6473 */ "fmovdl $\x02, $\x03, $\x01\0"
5909 /* 6491 */ "fmovdul $\x02, $\x03, $\x01\0"
5910 /* 6510 */ "fmovdlg $\x02, $\x03, $\x01\0"
5911 /* 6529 */ "fmovdne $\x02, $\x03, $\x01\0"
5912 /* 6548 */ "fmovde $\x02, $\x03, $\x01\0"
5913 /* 6566 */ "fmovdue $\x02, $\x03, $\x01\0"
5914 /* 6585 */ "fmovdge $\x02, $\x03, $\x01\0"
5915 /* 6604 */ "fmovduge $\x02, $\x03, $\x01\0"
5916 /* 6624 */ "fmovdle $\x02, $\x03, $\x01\0"
5917 /* 6643 */ "fmovdule $\x02, $\x03, $\x01\0"
5918 /* 6663 */ "fmovdo $\x02, $\x03, $\x01\0"
5919 /* 6681 */ "fmovqa $\x02, $\x03, $\x01\0"
5920 /* 6699 */ "fmovqn $\x02, $\x03, $\x01\0"
5921 /* 6717 */ "fmovqu $\x02, $\x03, $\x01\0"
5922 /* 6735 */ "fmovqg $\x02, $\x03, $\x01\0"
5923 /* 6753 */ "fmovqug $\x02, $\x03, $\x01\0"
5924 /* 6772 */ "fmovql $\x02, $\x03, $\x01\0"
5925 /* 6790 */ "fmovqul $\x02, $\x03, $\x01\0"
5926 /* 6809 */ "fmovqlg $\x02, $\x03, $\x01\0"
5927 /* 6828 */ "fmovqne $\x02, $\x03, $\x01\0"
5928 /* 6847 */ "fmovqe $\x02, $\x03, $\x01\0"
5929 /* 6865 */ "fmovque $\x02, $\x03, $\x01\0"
5930 /* 6884 */ "fmovqge $\x02, $\x03, $\x01\0"
5931 /* 6903 */ "fmovquge $\x02, $\x03, $\x01\0"
5932 /* 6923 */ "fmovqle $\x02, $\x03, $\x01\0"
5933 /* 6942 */ "fmovqule $\x02, $\x03, $\x01\0"
5934 /* 6962 */ "fmovqo $\x02, $\x03, $\x01\0"
5935 /* 6980 */ "fmovsa $\x02, $\x03, $\x01\0"
5936 /* 6998 */ "fmovsn $\x02, $\x03, $\x01\0"
5937 /* 7016 */ "fmovsu $\x02, $\x03, $\x01\0"
5938 /* 7034 */ "fmovsg $\x02, $\x03, $\x01\0"
5939 /* 7052 */ "fmovsug $\x02, $\x03, $\x01\0"
5940 /* 7071 */ "fmovsl $\x02, $\x03, $\x01\0"
5941 /* 7089 */ "fmovsul $\x02, $\x03, $\x01\0"
5942 /* 7108 */ "fmovslg $\x02, $\x03, $\x01\0"
5943 /* 7127 */ "fmovsne $\x02, $\x03, $\x01\0"
5944 /* 7146 */ "fmovse $\x02, $\x03, $\x01\0"
5945 /* 7164 */ "fmovsue $\x02, $\x03, $\x01\0"
5946 /* 7183 */ "fmovsge $\x02, $\x03, $\x01\0"
5947 /* 7202 */ "fmovsuge $\x02, $\x03, $\x01\0"
5948 /* 7222 */ "fmovsle $\x02, $\x03, $\x01\0"
5949 /* 7241 */ "fmovsule $\x02, $\x03, $\x01\0"
5950 /* 7261 */ "fmovso $\x02, $\x03, $\x01\0"
5951 /* 7279 */ "mova $\x02, $\x03, $\x01\0"
5952 /* 7295 */ "movn $\x02, $\x03, $\x01\0"
5953 /* 7311 */ "movu $\x02, $\x03, $\x01\0"
5954 /* 7327 */ "movg $\x02, $\x03, $\x01\0"
5955 /* 7343 */ "movug $\x02, $\x03, $\x01\0"
5956 /* 7360 */ "movl $\x02, $\x03, $\x01\0"
5957 /* 7376 */ "movul $\x02, $\x03, $\x01\0"
5958 /* 7393 */ "movlg $\x02, $\x03, $\x01\0"
5959 /* 7410 */ "movne $\x02, $\x03, $\x01\0"
5960 /* 7427 */ "move $\x02, $\x03, $\x01\0"
5961 /* 7443 */ "movue $\x02, $\x03, $\x01\0"
5962 /* 7460 */ "movge $\x02, $\x03, $\x01\0"
5963 /* 7477 */ "movuge $\x02, $\x03, $\x01\0"
5964 /* 7495 */ "movle $\x02, $\x03, $\x01\0"
5965 /* 7512 */ "movule $\x02, $\x03, $\x01\0"
5966 /* 7530 */ "movo $\x02, $\x03, $\x01\0"
5967 ;
5968
5969#ifndef NDEBUG
5970 static struct SortCheck {
5971 SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
5972 assert(std::is_sorted(
5973 OpToPatterns.begin(), OpToPatterns.end(),
5974 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
5975 return L.Opcode < R.Opcode;
5976 }) &&
5977 "tablegen failed to sort opcode patterns");
5978 }
5979 } sortCheckVar(OpToPatterns);
5980#endif
5981
5982 AliasMatchingData M {
5983 .OpToPatterns: ArrayRef(OpToPatterns),
5984 .Patterns: ArrayRef(Patterns),
5985 .PatternConds: ArrayRef(Conds),
5986 .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)),
5987 .ValidateMCOperand: nullptr,
5988 };
5989 const char *AsmString = matchAliasPatterns(MI, STI: &STI, M);
5990 if (!AsmString) return false;
5991
5992 unsigned I = 0;
5993 while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
5994 AsmString[I] != '$' && AsmString[I] != '\0')
5995 ++I;
5996 OS << '\t' << StringRef(AsmString, I);
5997 if (AsmString[I] != '\0') {
5998 if (AsmString[I] == ' ' || AsmString[I] == '\t') {
5999 OS << '\t';
6000 ++I;
6001 }
6002 do {
6003 if (AsmString[I] == '$') {
6004 ++I;
6005 if (AsmString[I] == (char)0xff) {
6006 ++I;
6007 int OpIdx = AsmString[I++] - 1;
6008 int PrintMethodIdx = AsmString[I++] - 1;
6009 printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS);
6010 } else
6011 printOperand(MI, opNum: unsigned(AsmString[I++]) - 1, STI, OS);
6012 } else {
6013 OS << AsmString[I++];
6014 }
6015 } while (AsmString[I] != '\0');
6016 }
6017
6018 return true;
6019}
6020
6021void SparcInstPrinter::printCustomAliasOperand(
6022 const MCInst *MI, uint64_t Address, unsigned OpIdx,
6023 unsigned PrintMethodIdx,
6024 const MCSubtargetInfo &STI,
6025 raw_ostream &OS) {
6026 llvm_unreachable("Unknown PrintMethod kind");
6027}
6028
6029#endif // PRINT_ALIAS_INSTR
6030