1 | //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file provides ARM specific target descriptions. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #include "ARMMCTargetDesc.h" |
14 | #include "ARMAddressingModes.h" |
15 | #include "ARMBaseInfo.h" |
16 | #include "ARMInstPrinter.h" |
17 | #include "ARMMCAsmInfo.h" |
18 | #include "TargetInfo/ARMTargetInfo.h" |
19 | #include "llvm/DebugInfo/CodeView/CodeView.h" |
20 | #include "llvm/MC/MCAsmBackend.h" |
21 | #include "llvm/MC/MCCodeEmitter.h" |
22 | #include "llvm/MC/MCELFStreamer.h" |
23 | #include "llvm/MC/MCInstrAnalysis.h" |
24 | #include "llvm/MC/MCInstrInfo.h" |
25 | #include "llvm/MC/MCObjectWriter.h" |
26 | #include "llvm/MC/MCRegisterInfo.h" |
27 | #include "llvm/MC/MCStreamer.h" |
28 | #include "llvm/MC/MCSubtargetInfo.h" |
29 | #include "llvm/MC/TargetRegistry.h" |
30 | #include "llvm/Support/ErrorHandling.h" |
31 | #include "llvm/TargetParser/Triple.h" |
32 | |
33 | using namespace llvm; |
34 | |
35 | #define GET_REGINFO_MC_DESC |
36 | #include "ARMGenRegisterInfo.inc" |
37 | |
38 | static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, |
39 | std::string &Info) { |
40 | if (STI.hasFeature(Feature: llvm::ARM::HasV7Ops) && |
41 | (MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 15) && |
42 | (MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 0) && |
43 | // Checks for the deprecated CP15ISB encoding: |
44 | // mcr p15, #0, rX, c7, c5, #4 |
45 | (MI.getOperand(i: 3).isImm() && MI.getOperand(i: 3).getImm() == 7)) { |
46 | if ((MI.getOperand(i: 5).isImm() && MI.getOperand(i: 5).getImm() == 4)) { |
47 | if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 5) { |
48 | Info = "deprecated since v7, use 'isb'" ; |
49 | return true; |
50 | } |
51 | |
52 | // Checks for the deprecated CP15DSB encoding: |
53 | // mcr p15, #0, rX, c7, c10, #4 |
54 | if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 10) { |
55 | Info = "deprecated since v7, use 'dsb'" ; |
56 | return true; |
57 | } |
58 | } |
59 | // Checks for the deprecated CP15DMB encoding: |
60 | // mcr p15, #0, rX, c7, c10, #5 |
61 | if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 10 && |
62 | (MI.getOperand(i: 5).isImm() && MI.getOperand(i: 5).getImm() == 5)) { |
63 | Info = "deprecated since v7, use 'dmb'" ; |
64 | return true; |
65 | } |
66 | } |
67 | if (STI.hasFeature(Feature: llvm::ARM::HasV7Ops) && |
68 | ((MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 10) || |
69 | (MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 11))) { |
70 | Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating " |
71 | "point instructions" ; |
72 | return true; |
73 | } |
74 | return false; |
75 | } |
76 | |
77 | static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, |
78 | std::string &Info) { |
79 | if (STI.hasFeature(Feature: llvm::ARM::HasV7Ops) && |
80 | ((MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 10) || |
81 | (MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 11))) { |
82 | Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating " |
83 | "point instructions" ; |
84 | return true; |
85 | } |
86 | return false; |
87 | } |
88 | |
89 | static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, |
90 | std::string &Info) { |
91 | assert(!STI.hasFeature(llvm::ARM::ModeThumb) && |
92 | "cannot predicate thumb instructions" ); |
93 | |
94 | assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments" ); |
95 | for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { |
96 | assert(MI.getOperand(OI).isReg() && "expected register" ); |
97 | if (MI.getOperand(i: OI).getReg() == ARM::PC) { |
98 | Info = "use of PC in the list is deprecated" ; |
99 | return true; |
100 | } |
101 | } |
102 | return false; |
103 | } |
104 | |
105 | static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, |
106 | std::string &Info) { |
107 | assert(!STI.hasFeature(llvm::ARM::ModeThumb) && |
108 | "cannot predicate thumb instructions" ); |
109 | |
110 | assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments" ); |
111 | bool ListContainsPC = false, ListContainsLR = false; |
112 | for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { |
113 | assert(MI.getOperand(OI).isReg() && "expected register" ); |
114 | switch (MI.getOperand(i: OI).getReg()) { |
115 | default: |
116 | break; |
117 | case ARM::LR: |
118 | ListContainsLR = true; |
119 | break; |
120 | case ARM::PC: |
121 | ListContainsPC = true; |
122 | break; |
123 | } |
124 | } |
125 | |
126 | if (ListContainsPC && ListContainsLR) { |
127 | Info = "use of LR and PC simultaneously in the list is deprecated" ; |
128 | return true; |
129 | } |
130 | |
131 | return false; |
132 | } |
133 | |
134 | #define GET_INSTRINFO_MC_DESC |
135 | #define ENABLE_INSTR_PREDICATE_VERIFIER |
136 | #include "ARMGenInstrInfo.inc" |
137 | |
138 | #define GET_SUBTARGETINFO_MC_DESC |
139 | #include "ARMGenSubtargetInfo.inc" |
140 | |
141 | std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { |
142 | std::string ARMArchFeature; |
143 | |
144 | ARM::ArchKind ArchID = ARM::parseArch(Arch: TT.getArchName()); |
145 | if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic" )) |
146 | ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(AK: ArchID)).str(); |
147 | |
148 | if (TT.isThumb()) { |
149 | if (!ARMArchFeature.empty()) |
150 | ARMArchFeature += "," ; |
151 | ARMArchFeature += "+thumb-mode,+v4t" ; |
152 | } |
153 | |
154 | if (TT.isOSNaCl()) { |
155 | if (!ARMArchFeature.empty()) |
156 | ARMArchFeature += "," ; |
157 | ARMArchFeature += "+nacl-trap" ; |
158 | } |
159 | |
160 | if (TT.isOSWindows()) { |
161 | if (!ARMArchFeature.empty()) |
162 | ARMArchFeature += "," ; |
163 | ARMArchFeature += "+noarm" ; |
164 | } |
165 | |
166 | return ARMArchFeature; |
167 | } |
168 | |
169 | bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) { |
170 | const MCInstrDesc &Desc = MCII->get(Opcode: MI.getOpcode()); |
171 | int PredOpIdx = Desc.findFirstPredOperandIdx(); |
172 | return PredOpIdx != -1 && MI.getOperand(i: PredOpIdx).getImm() != ARMCC::AL; |
173 | } |
174 | |
175 | bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) { |
176 | const MCInstrDesc &Desc = MCII->get(Opcode: MI.getOpcode()); |
177 | for (unsigned I = 0; I < MI.getNumOperands(); ++I) { |
178 | const MCOperand &MO = MI.getOperand(i: I); |
179 | if (MO.isReg() && MO.getReg() == ARM::CPSR && |
180 | Desc.operands()[I].isOptionalDef()) |
181 | return true; |
182 | } |
183 | return false; |
184 | } |
185 | |
186 | uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, |
187 | uint64_t Addr, int64_t Imm) { |
188 | // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it |
189 | // is 4 bytes. |
190 | uint64_t Offset = |
191 | ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8; |
192 | |
193 | // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code |
194 | // which is 32-bit aligned. The target address for the case is calculated as |
195 | // targetAddress = Align(PC,4) + imm32; |
196 | // where |
197 | // Align(x, y) = y * (x DIV y); |
198 | if (InstDesc.getOpcode() == ARM::tBLXi) |
199 | Addr &= ~0x3; |
200 | |
201 | return Addr + Imm + Offset; |
202 | } |
203 | |
204 | MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT, |
205 | StringRef CPU, StringRef FS) { |
206 | std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); |
207 | if (!FS.empty()) { |
208 | if (!ArchFS.empty()) |
209 | ArchFS = (Twine(ArchFS) + "," + FS).str(); |
210 | else |
211 | ArchFS = std::string(FS); |
212 | } |
213 | |
214 | return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS: ArchFS); |
215 | } |
216 | |
217 | static MCInstrInfo *createARMMCInstrInfo() { |
218 | MCInstrInfo *X = new MCInstrInfo(); |
219 | InitARMMCInstrInfo(II: X); |
220 | return X; |
221 | } |
222 | |
223 | void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { |
224 | // Mapping from CodeView to MC register id. |
225 | static const struct { |
226 | codeview::RegisterId CVReg; |
227 | MCPhysReg Reg; |
228 | } RegMap[] = { |
229 | {.CVReg: codeview::RegisterId::ARM_R0, .Reg: ARM::R0}, |
230 | {.CVReg: codeview::RegisterId::ARM_R1, .Reg: ARM::R1}, |
231 | {.CVReg: codeview::RegisterId::ARM_R2, .Reg: ARM::R2}, |
232 | {.CVReg: codeview::RegisterId::ARM_R3, .Reg: ARM::R3}, |
233 | {.CVReg: codeview::RegisterId::ARM_R4, .Reg: ARM::R4}, |
234 | {.CVReg: codeview::RegisterId::ARM_R5, .Reg: ARM::R5}, |
235 | {.CVReg: codeview::RegisterId::ARM_R6, .Reg: ARM::R6}, |
236 | {.CVReg: codeview::RegisterId::ARM_R7, .Reg: ARM::R7}, |
237 | {.CVReg: codeview::RegisterId::ARM_R8, .Reg: ARM::R8}, |
238 | {.CVReg: codeview::RegisterId::ARM_R9, .Reg: ARM::R9}, |
239 | {.CVReg: codeview::RegisterId::ARM_R10, .Reg: ARM::R10}, |
240 | {.CVReg: codeview::RegisterId::ARM_R11, .Reg: ARM::R11}, |
241 | {.CVReg: codeview::RegisterId::ARM_R12, .Reg: ARM::R12}, |
242 | {.CVReg: codeview::RegisterId::ARM_SP, .Reg: ARM::SP}, |
243 | {.CVReg: codeview::RegisterId::ARM_LR, .Reg: ARM::LR}, |
244 | {.CVReg: codeview::RegisterId::ARM_PC, .Reg: ARM::PC}, |
245 | {.CVReg: codeview::RegisterId::ARM_CPSR, .Reg: ARM::CPSR}, |
246 | {.CVReg: codeview::RegisterId::ARM_FPSCR, .Reg: ARM::FPSCR}, |
247 | {.CVReg: codeview::RegisterId::ARM_FPEXC, .Reg: ARM::FPEXC}, |
248 | {.CVReg: codeview::RegisterId::ARM_FS0, .Reg: ARM::S0}, |
249 | {.CVReg: codeview::RegisterId::ARM_FS1, .Reg: ARM::S1}, |
250 | {.CVReg: codeview::RegisterId::ARM_FS2, .Reg: ARM::S2}, |
251 | {.CVReg: codeview::RegisterId::ARM_FS3, .Reg: ARM::S3}, |
252 | {.CVReg: codeview::RegisterId::ARM_FS4, .Reg: ARM::S4}, |
253 | {.CVReg: codeview::RegisterId::ARM_FS5, .Reg: ARM::S5}, |
254 | {.CVReg: codeview::RegisterId::ARM_FS6, .Reg: ARM::S6}, |
255 | {.CVReg: codeview::RegisterId::ARM_FS7, .Reg: ARM::S7}, |
256 | {.CVReg: codeview::RegisterId::ARM_FS8, .Reg: ARM::S8}, |
257 | {.CVReg: codeview::RegisterId::ARM_FS9, .Reg: ARM::S9}, |
258 | {.CVReg: codeview::RegisterId::ARM_FS10, .Reg: ARM::S10}, |
259 | {.CVReg: codeview::RegisterId::ARM_FS11, .Reg: ARM::S11}, |
260 | {.CVReg: codeview::RegisterId::ARM_FS12, .Reg: ARM::S12}, |
261 | {.CVReg: codeview::RegisterId::ARM_FS13, .Reg: ARM::S13}, |
262 | {.CVReg: codeview::RegisterId::ARM_FS14, .Reg: ARM::S14}, |
263 | {.CVReg: codeview::RegisterId::ARM_FS15, .Reg: ARM::S15}, |
264 | {.CVReg: codeview::RegisterId::ARM_FS16, .Reg: ARM::S16}, |
265 | {.CVReg: codeview::RegisterId::ARM_FS17, .Reg: ARM::S17}, |
266 | {.CVReg: codeview::RegisterId::ARM_FS18, .Reg: ARM::S18}, |
267 | {.CVReg: codeview::RegisterId::ARM_FS19, .Reg: ARM::S19}, |
268 | {.CVReg: codeview::RegisterId::ARM_FS20, .Reg: ARM::S20}, |
269 | {.CVReg: codeview::RegisterId::ARM_FS21, .Reg: ARM::S21}, |
270 | {.CVReg: codeview::RegisterId::ARM_FS22, .Reg: ARM::S22}, |
271 | {.CVReg: codeview::RegisterId::ARM_FS23, .Reg: ARM::S23}, |
272 | {.CVReg: codeview::RegisterId::ARM_FS24, .Reg: ARM::S24}, |
273 | {.CVReg: codeview::RegisterId::ARM_FS25, .Reg: ARM::S25}, |
274 | {.CVReg: codeview::RegisterId::ARM_FS26, .Reg: ARM::S26}, |
275 | {.CVReg: codeview::RegisterId::ARM_FS27, .Reg: ARM::S27}, |
276 | {.CVReg: codeview::RegisterId::ARM_FS28, .Reg: ARM::S28}, |
277 | {.CVReg: codeview::RegisterId::ARM_FS29, .Reg: ARM::S29}, |
278 | {.CVReg: codeview::RegisterId::ARM_FS30, .Reg: ARM::S30}, |
279 | {.CVReg: codeview::RegisterId::ARM_FS31, .Reg: ARM::S31}, |
280 | {.CVReg: codeview::RegisterId::ARM_ND0, .Reg: ARM::D0}, |
281 | {.CVReg: codeview::RegisterId::ARM_ND1, .Reg: ARM::D1}, |
282 | {.CVReg: codeview::RegisterId::ARM_ND2, .Reg: ARM::D2}, |
283 | {.CVReg: codeview::RegisterId::ARM_ND3, .Reg: ARM::D3}, |
284 | {.CVReg: codeview::RegisterId::ARM_ND4, .Reg: ARM::D4}, |
285 | {.CVReg: codeview::RegisterId::ARM_ND5, .Reg: ARM::D5}, |
286 | {.CVReg: codeview::RegisterId::ARM_ND6, .Reg: ARM::D6}, |
287 | {.CVReg: codeview::RegisterId::ARM_ND7, .Reg: ARM::D7}, |
288 | {.CVReg: codeview::RegisterId::ARM_ND8, .Reg: ARM::D8}, |
289 | {.CVReg: codeview::RegisterId::ARM_ND9, .Reg: ARM::D9}, |
290 | {.CVReg: codeview::RegisterId::ARM_ND10, .Reg: ARM::D10}, |
291 | {.CVReg: codeview::RegisterId::ARM_ND11, .Reg: ARM::D11}, |
292 | {.CVReg: codeview::RegisterId::ARM_ND12, .Reg: ARM::D12}, |
293 | {.CVReg: codeview::RegisterId::ARM_ND13, .Reg: ARM::D13}, |
294 | {.CVReg: codeview::RegisterId::ARM_ND14, .Reg: ARM::D14}, |
295 | {.CVReg: codeview::RegisterId::ARM_ND15, .Reg: ARM::D15}, |
296 | {.CVReg: codeview::RegisterId::ARM_ND16, .Reg: ARM::D16}, |
297 | {.CVReg: codeview::RegisterId::ARM_ND17, .Reg: ARM::D17}, |
298 | {.CVReg: codeview::RegisterId::ARM_ND18, .Reg: ARM::D18}, |
299 | {.CVReg: codeview::RegisterId::ARM_ND19, .Reg: ARM::D19}, |
300 | {.CVReg: codeview::RegisterId::ARM_ND20, .Reg: ARM::D20}, |
301 | {.CVReg: codeview::RegisterId::ARM_ND21, .Reg: ARM::D21}, |
302 | {.CVReg: codeview::RegisterId::ARM_ND22, .Reg: ARM::D22}, |
303 | {.CVReg: codeview::RegisterId::ARM_ND23, .Reg: ARM::D23}, |
304 | {.CVReg: codeview::RegisterId::ARM_ND24, .Reg: ARM::D24}, |
305 | {.CVReg: codeview::RegisterId::ARM_ND25, .Reg: ARM::D25}, |
306 | {.CVReg: codeview::RegisterId::ARM_ND26, .Reg: ARM::D26}, |
307 | {.CVReg: codeview::RegisterId::ARM_ND27, .Reg: ARM::D27}, |
308 | {.CVReg: codeview::RegisterId::ARM_ND28, .Reg: ARM::D28}, |
309 | {.CVReg: codeview::RegisterId::ARM_ND29, .Reg: ARM::D29}, |
310 | {.CVReg: codeview::RegisterId::ARM_ND30, .Reg: ARM::D30}, |
311 | {.CVReg: codeview::RegisterId::ARM_ND31, .Reg: ARM::D31}, |
312 | {.CVReg: codeview::RegisterId::ARM_NQ0, .Reg: ARM::Q0}, |
313 | {.CVReg: codeview::RegisterId::ARM_NQ1, .Reg: ARM::Q1}, |
314 | {.CVReg: codeview::RegisterId::ARM_NQ2, .Reg: ARM::Q2}, |
315 | {.CVReg: codeview::RegisterId::ARM_NQ3, .Reg: ARM::Q3}, |
316 | {.CVReg: codeview::RegisterId::ARM_NQ4, .Reg: ARM::Q4}, |
317 | {.CVReg: codeview::RegisterId::ARM_NQ5, .Reg: ARM::Q5}, |
318 | {.CVReg: codeview::RegisterId::ARM_NQ6, .Reg: ARM::Q6}, |
319 | {.CVReg: codeview::RegisterId::ARM_NQ7, .Reg: ARM::Q7}, |
320 | {.CVReg: codeview::RegisterId::ARM_NQ8, .Reg: ARM::Q8}, |
321 | {.CVReg: codeview::RegisterId::ARM_NQ9, .Reg: ARM::Q9}, |
322 | {.CVReg: codeview::RegisterId::ARM_NQ10, .Reg: ARM::Q10}, |
323 | {.CVReg: codeview::RegisterId::ARM_NQ11, .Reg: ARM::Q11}, |
324 | {.CVReg: codeview::RegisterId::ARM_NQ12, .Reg: ARM::Q12}, |
325 | {.CVReg: codeview::RegisterId::ARM_NQ13, .Reg: ARM::Q13}, |
326 | {.CVReg: codeview::RegisterId::ARM_NQ14, .Reg: ARM::Q14}, |
327 | {.CVReg: codeview::RegisterId::ARM_NQ15, .Reg: ARM::Q15}, |
328 | }; |
329 | for (const auto &I : RegMap) |
330 | MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg)); |
331 | } |
332 | |
333 | static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) { |
334 | MCRegisterInfo *X = new MCRegisterInfo(); |
335 | InitARMMCRegisterInfo(RI: X, RA: ARM::LR, DwarfFlavour: 0, EHFlavour: 0, PC: ARM::PC); |
336 | ARM_MC::initLLVMToCVRegMapping(MRI: X); |
337 | return X; |
338 | } |
339 | |
340 | static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, |
341 | const Triple &TheTriple, |
342 | const MCTargetOptions &Options) { |
343 | MCAsmInfo *MAI; |
344 | if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) |
345 | MAI = new ARMMCAsmInfoDarwin(TheTriple); |
346 | else if (TheTriple.isWindowsMSVCEnvironment()) |
347 | MAI = new ARMCOFFMCAsmInfoMicrosoft(); |
348 | else if (TheTriple.isOSWindows()) |
349 | MAI = new ARMCOFFMCAsmInfoGNU(); |
350 | else |
351 | MAI = new ARMELFMCAsmInfo(TheTriple); |
352 | |
353 | unsigned Reg = MRI.getDwarfRegNum(RegNum: ARM::SP, isEH: true); |
354 | MAI->addInitialFrameState(Inst: MCCFIInstruction::cfiDefCfa(L: nullptr, Register: Reg, Offset: 0)); |
355 | |
356 | return MAI; |
357 | } |
358 | |
359 | static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, |
360 | std::unique_ptr<MCAsmBackend> &&MAB, |
361 | std::unique_ptr<MCObjectWriter> &&OW, |
362 | std::unique_ptr<MCCodeEmitter> &&Emitter) { |
363 | return createARMELFStreamer( |
364 | Context&: Ctx, TAB: std::move(MAB), OW: std::move(OW), Emitter: std::move(Emitter), |
365 | IsThumb: (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb), |
366 | IsAndroid: T.isAndroid()); |
367 | } |
368 | |
369 | static MCStreamer * |
370 | createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB, |
371 | std::unique_ptr<MCObjectWriter> &&OW, |
372 | std::unique_ptr<MCCodeEmitter> &&Emitter) { |
373 | return createMachOStreamer(Ctx, TAB: std::move(MAB), OW: std::move(OW), |
374 | CE: std::move(Emitter), DWARFMustBeAtTheEnd: false); |
375 | } |
376 | |
377 | static MCInstPrinter *createARMMCInstPrinter(const Triple &T, |
378 | unsigned SyntaxVariant, |
379 | const MCAsmInfo &MAI, |
380 | const MCInstrInfo &MII, |
381 | const MCRegisterInfo &MRI) { |
382 | if (SyntaxVariant == 0) |
383 | return new ARMInstPrinter(MAI, MII, MRI); |
384 | return nullptr; |
385 | } |
386 | |
387 | static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT, |
388 | MCContext &Ctx) { |
389 | if (TT.isOSBinFormatMachO()) |
390 | return createARMMachORelocationInfo(Ctx); |
391 | // Default to the stock relocation info. |
392 | return llvm::createMCRelocationInfo(TT, Ctx); |
393 | } |
394 | |
395 | namespace { |
396 | |
397 | class ARMMCInstrAnalysis : public MCInstrAnalysis { |
398 | public: |
399 | ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} |
400 | |
401 | bool isUnconditionalBranch(const MCInst &Inst) const override { |
402 | // BCCs with the "always" predicate are unconditional branches. |
403 | if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(i: 1).getImm()==ARMCC::AL) |
404 | return true; |
405 | return MCInstrAnalysis::isUnconditionalBranch(Inst); |
406 | } |
407 | |
408 | bool isConditionalBranch(const MCInst &Inst) const override { |
409 | // BCCs with the "always" predicate are unconditional branches. |
410 | if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(i: 1).getImm()==ARMCC::AL) |
411 | return false; |
412 | return MCInstrAnalysis::isConditionalBranch(Inst); |
413 | } |
414 | |
415 | bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, |
416 | uint64_t &Target) const override { |
417 | const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode()); |
418 | |
419 | // Find the PC-relative immediate operand in the instruction. |
420 | for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) { |
421 | if (Inst.getOperand(i: OpNum).isImm() && |
422 | Desc.operands()[OpNum].OperandType == MCOI::OPERAND_PCREL) { |
423 | int64_t Imm = Inst.getOperand(i: OpNum).getImm(); |
424 | Target = ARM_MC::evaluateBranchTarget(InstDesc: Desc, Addr, Imm); |
425 | return true; |
426 | } |
427 | } |
428 | return false; |
429 | } |
430 | |
431 | std::optional<uint64_t> |
432 | evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, |
433 | uint64_t Addr, uint64_t Size) const override; |
434 | }; |
435 | |
436 | } // namespace |
437 | |
438 | static std::optional<uint64_t> |
439 | // NOLINTNEXTLINE(readability-identifier-naming) |
440 | evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, |
441 | unsigned MemOpIndex, uint64_t Addr) { |
442 | if (MemOpIndex + 1 >= Desc.getNumOperands()) |
443 | return std::nullopt; |
444 | |
445 | const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex); |
446 | const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1); |
447 | if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) |
448 | return std::nullopt; |
449 | |
450 | int32_t OffImm = (int32_t)MO2.getImm(); |
451 | // Special value for #-0. All others are normal. |
452 | if (OffImm == INT32_MIN) |
453 | OffImm = 0; |
454 | return Addr + OffImm; |
455 | } |
456 | |
457 | static std::optional<uint64_t> |
458 | evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, |
459 | unsigned MemOpIndex, uint64_t Addr) { |
460 | if (MemOpIndex + 2 >= Desc.getNumOperands()) |
461 | return std::nullopt; |
462 | |
463 | const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex); |
464 | const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1); |
465 | const MCOperand &MO3 = Inst.getOperand(i: MemOpIndex + 2); |
466 | if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm()) |
467 | return std::nullopt; |
468 | |
469 | unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc: MO3.getImm()); |
470 | ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(AM3Opc: MO3.getImm()); |
471 | |
472 | if (Op == ARM_AM::sub) |
473 | return Addr - ImmOffs; |
474 | return Addr + ImmOffs; |
475 | } |
476 | |
477 | static std::optional<uint64_t> |
478 | evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, |
479 | unsigned MemOpIndex, uint64_t Addr) { |
480 | if (MemOpIndex + 1 >= Desc.getNumOperands()) |
481 | return std::nullopt; |
482 | |
483 | const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex); |
484 | const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1); |
485 | if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) |
486 | return std::nullopt; |
487 | |
488 | unsigned ImmOffs = ARM_AM::getAM5Offset(AM5Opc: MO2.getImm()); |
489 | ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(AM5Opc: MO2.getImm()); |
490 | |
491 | if (Op == ARM_AM::sub) |
492 | return Addr - ImmOffs * 4; |
493 | return Addr + ImmOffs * 4; |
494 | } |
495 | |
496 | static std::optional<uint64_t> |
497 | evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, |
498 | unsigned MemOpIndex, uint64_t Addr) { |
499 | if (MemOpIndex + 1 >= Desc.getNumOperands()) |
500 | return std::nullopt; |
501 | |
502 | const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex); |
503 | const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1); |
504 | if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) |
505 | return std::nullopt; |
506 | |
507 | unsigned ImmOffs = ARM_AM::getAM5FP16Offset(AM5Opc: MO2.getImm()); |
508 | ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(AM5Opc: MO2.getImm()); |
509 | |
510 | if (Op == ARM_AM::sub) |
511 | return Addr - ImmOffs * 2; |
512 | return Addr + ImmOffs * 2; |
513 | } |
514 | |
515 | static std::optional<uint64_t> |
516 | // NOLINTNEXTLINE(readability-identifier-naming) |
517 | evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, |
518 | unsigned MemOpIndex, uint64_t Addr) { |
519 | if (MemOpIndex + 1 >= Desc.getNumOperands()) |
520 | return std::nullopt; |
521 | |
522 | const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex); |
523 | const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1); |
524 | if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) |
525 | return std::nullopt; |
526 | |
527 | int32_t OffImm = (int32_t)MO2.getImm(); |
528 | assert(((OffImm & 0x3) == 0) && "Not a valid immediate!" ); |
529 | |
530 | // Special value for #-0. All others are normal. |
531 | if (OffImm == INT32_MIN) |
532 | OffImm = 0; |
533 | return Addr + OffImm; |
534 | } |
535 | |
536 | static std::optional<uint64_t> |
537 | // NOLINTNEXTLINE(readability-identifier-naming) |
538 | evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, |
539 | unsigned MemOpIndex, uint64_t Addr) { |
540 | const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex); |
541 | if (!MO1.isImm()) |
542 | return std::nullopt; |
543 | |
544 | int32_t OffImm = (int32_t)MO1.getImm(); |
545 | |
546 | // Special value for #-0. All others are normal. |
547 | if (OffImm == INT32_MIN) |
548 | OffImm = 0; |
549 | return Addr + OffImm; |
550 | } |
551 | |
552 | static std::optional<uint64_t> |
553 | // NOLINTNEXTLINE(readability-identifier-naming) |
554 | evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, |
555 | unsigned MemOpIndex, uint64_t Addr) { |
556 | return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr); |
557 | } |
558 | |
559 | std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress( |
560 | const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, |
561 | uint64_t Size) const { |
562 | const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode()); |
563 | |
564 | // Only load instructions can have PC-relative memory addressing. |
565 | if (!Desc.mayLoad()) |
566 | return std::nullopt; |
567 | |
568 | // PC-relative addressing does not update the base register. |
569 | uint64_t TSFlags = Desc.TSFlags; |
570 | unsigned IndexMode = |
571 | (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; |
572 | if (IndexMode != ARMII::IndexModeNone) |
573 | return std::nullopt; |
574 | |
575 | // Find the memory addressing operand in the instruction. |
576 | unsigned OpIndex = Desc.NumDefs; |
577 | while (OpIndex < Desc.getNumOperands() && |
578 | Desc.operands()[OpIndex].OperandType != MCOI::OPERAND_MEMORY) |
579 | ++OpIndex; |
580 | if (OpIndex == Desc.getNumOperands()) |
581 | return std::nullopt; |
582 | |
583 | // Base address for PC-relative addressing is always 32-bit aligned. |
584 | Addr &= ~0x3; |
585 | |
586 | // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it |
587 | // is 4 bytes. |
588 | switch (Desc.TSFlags & ARMII::FormMask) { |
589 | default: |
590 | Addr += 8; |
591 | break; |
592 | case ARMII::ThumbFrm: |
593 | Addr += 4; |
594 | break; |
595 | // VLDR* instructions share the same opcode (and thus the same form) for Arm |
596 | // and Thumb. Use a bit longer route through STI in that case. |
597 | case ARMII::VFPLdStFrm: |
598 | Addr += STI->hasFeature(Feature: ARM::ModeThumb) ? 4 : 8; |
599 | break; |
600 | } |
601 | |
602 | // Eveluate the address depending on the addressing mode |
603 | unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); |
604 | switch (AddrMode) { |
605 | default: |
606 | return std::nullopt; |
607 | case ARMII::AddrMode_i12: |
608 | return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, MemOpIndex: OpIndex, Addr); |
609 | case ARMII::AddrMode3: |
610 | return evaluateMemOpAddrForAddrMode3(Inst, Desc, MemOpIndex: OpIndex, Addr); |
611 | case ARMII::AddrMode5: |
612 | return evaluateMemOpAddrForAddrMode5(Inst, Desc, MemOpIndex: OpIndex, Addr); |
613 | case ARMII::AddrMode5FP16: |
614 | return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, MemOpIndex: OpIndex, Addr); |
615 | case ARMII::AddrModeT2_i8s4: |
616 | return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, MemOpIndex: OpIndex, Addr); |
617 | case ARMII::AddrModeT2_pc: |
618 | return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex: OpIndex, Addr); |
619 | case ARMII::AddrModeT1_s: |
620 | return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, MemOpIndex: OpIndex, Addr); |
621 | } |
622 | } |
623 | |
624 | static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) { |
625 | return new ARMMCInstrAnalysis(Info); |
626 | } |
627 | |
628 | bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) { |
629 | // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have |
630 | // to rely on feature bits. |
631 | if (Coproc >= 8) |
632 | return false; |
633 | return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc]; |
634 | } |
635 | |
636 | // Force static initialization. |
637 | extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() { |
638 | for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(), |
639 | &getTheThumbLETarget(), &getTheThumbBETarget()}) { |
640 | // Register the MC asm info. |
641 | RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); |
642 | |
643 | // Register the MC instruction info. |
644 | TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createARMMCInstrInfo); |
645 | |
646 | // Register the MC register info. |
647 | TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createARMMCRegisterInfo); |
648 | |
649 | // Register the MC subtarget info. |
650 | TargetRegistry::RegisterMCSubtargetInfo(T&: *T, |
651 | Fn: ARM_MC::createARMMCSubtargetInfo); |
652 | |
653 | TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createELFStreamer); |
654 | TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createARMWinCOFFStreamer); |
655 | TargetRegistry::RegisterMachOStreamer(T&: *T, Fn: createARMMachOStreamer); |
656 | |
657 | // Register the obj target streamer. |
658 | TargetRegistry::RegisterObjectTargetStreamer(T&: *T, |
659 | Fn: createARMObjectTargetStreamer); |
660 | |
661 | // Register the asm streamer. |
662 | TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createARMTargetAsmStreamer); |
663 | |
664 | // Register the null TargetStreamer. |
665 | TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createARMNullTargetStreamer); |
666 | |
667 | // Register the MCInstPrinter. |
668 | TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createARMMCInstPrinter); |
669 | |
670 | // Register the MC relocation info. |
671 | TargetRegistry::RegisterMCRelocationInfo(T&: *T, Fn: createARMMCRelocationInfo); |
672 | } |
673 | |
674 | // Register the MC instruction analyzer. |
675 | for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(), |
676 | &getTheThumbLETarget(), &getTheThumbBETarget()}) |
677 | TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createARMMCInstrAnalysis); |
678 | |
679 | for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) { |
680 | TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createARMLEMCCodeEmitter); |
681 | TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createARMLEAsmBackend); |
682 | } |
683 | for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) { |
684 | TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createARMBEMCCodeEmitter); |
685 | TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createARMBEAsmBackend); |
686 | } |
687 | } |
688 | |