1//===- HexagonBitTracker.cpp ----------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "HexagonBitTracker.h"
10#include "Hexagon.h"
11#include "HexagonInstrInfo.h"
12#include "HexagonRegisterInfo.h"
13#include "HexagonSubtarget.h"
14#include "llvm/CodeGen/MachineFrameInfo.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/CodeGen/MachineInstr.h"
17#include "llvm/CodeGen/MachineOperand.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/TargetRegisterInfo.h"
20#include "llvm/IR/Argument.h"
21#include "llvm/IR/Attributes.h"
22#include "llvm/IR/Function.h"
23#include "llvm/IR/Type.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstddef>
31#include <cstdint>
32#include <cstdlib>
33#include <utility>
34#include <vector>
35
36using namespace llvm;
37
38using BT = BitTracker;
39
40HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
41 MachineRegisterInfo &mri,
42 const HexagonInstrInfo &tii,
43 MachineFunction &mf)
44 : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
45 // Populate the VRX map (VR to extension-type).
46 // Go over all the formal parameters of the function. If a given parameter
47 // P is sign- or zero-extended, locate the virtual register holding that
48 // parameter and create an entry in the VRX map indicating the type of ex-
49 // tension (and the source type).
50 // This is a bit complicated to do accurately, since the memory layout in-
51 // formation is necessary to precisely determine whether an aggregate para-
52 // meter will be passed in a register or in memory. What is given in MRI
53 // is the association between the physical register that is live-in (i.e.
54 // holds an argument), and the virtual register that this value will be
55 // copied into. This, by itself, is not sufficient to map back the virtual
56 // register to a formal parameter from Function (since consecutive live-ins
57 // from MRI may not correspond to consecutive formal parameters from Func-
58 // tion). To avoid the complications with in-memory arguments, only consi-
59 // der the initial sequence of formal parameters that are known to be
60 // passed via registers.
61 unsigned InVirtReg, InPhysReg = 0;
62
63 for (const Argument &Arg : MF.getFunction().args()) {
64 Type *ATy = Arg.getType();
65 unsigned Width = 0;
66 if (ATy->isIntegerTy())
67 Width = ATy->getIntegerBitWidth();
68 else if (ATy->isPointerTy())
69 Width = 32;
70 // If pointer size is not set through target data, it will default to
71 // Module::AnyPointerSize.
72 if (Width == 0 || Width > 64)
73 break;
74 if (Arg.hasAttribute(Kind: Attribute::ByVal))
75 continue;
76 InPhysReg = getNextPhysReg(PReg: InPhysReg, Width);
77 if (!InPhysReg)
78 break;
79 InVirtReg = getVirtRegFor(PReg: InPhysReg);
80 if (!InVirtReg)
81 continue;
82 if (Arg.hasAttribute(Kind: Attribute::SExt))
83 VRX.insert(KV: std::make_pair(x&: InVirtReg, y: ExtType(ExtType::SExt, Width)));
84 else if (Arg.hasAttribute(Kind: Attribute::ZExt))
85 VRX.insert(KV: std::make_pair(x&: InVirtReg, y: ExtType(ExtType::ZExt, Width)));
86 }
87}
88
89BT::BitMask HexagonEvaluator::mask(Register Reg, unsigned Sub) const {
90 if (Sub == 0)
91 return MachineEvaluator::mask(Reg, Sub: 0);
92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
93 unsigned ID = RC.getID();
94 uint16_t RW = getRegBitWidth(RR: RegisterRef(Reg, Sub));
95 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
96 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, GenIdx: Hexagon::ps_sub_lo));
97 switch (ID) {
98 case Hexagon::DoubleRegsRegClassID:
99 case Hexagon::HvxWRRegClassID:
100 case Hexagon::HvxVQRRegClassID:
101 return IsSubLo ? BT::BitMask(0, RW-1)
102 : BT::BitMask(RW, 2*RW-1);
103 default:
104 break;
105 }
106#ifndef NDEBUG
107 dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
108 << TRI.getRegClassName(&RC) << '\n';
109#endif
110 llvm_unreachable("Unexpected register/subregister");
111}
112
113uint16_t HexagonEvaluator::getPhysRegBitWidth(MCRegister Reg) const {
114 using namespace Hexagon;
115 const auto &HST = MF.getSubtarget<HexagonSubtarget>();
116 if (HST.useHVXOps()) {
117 for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
118 HvxVQRRegClass})
119 if (RC.contains(Reg))
120 return TRI.getRegSizeInBits(RC);
121 }
122 // Default treatment for other physical registers.
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
124 return TRI.getRegSizeInBits(RC: *RC);
125
126 llvm_unreachable(
127 (Twine("Unhandled physical register") + TRI.getName(Reg)).str().c_str());
128}
129
130const TargetRegisterClass &HexagonEvaluator::composeWithSubRegIndex(
131 const TargetRegisterClass &RC, unsigned Idx) const {
132 if (Idx == 0)
133 return RC;
134
135#ifndef NDEBUG
136 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
137 bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
138 bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
139 assert(IsSubLo != IsSubHi && "Must refer to either low or high subreg");
140#endif
141
142 switch (RC.getID()) {
143 case Hexagon::DoubleRegsRegClassID:
144 return Hexagon::IntRegsRegClass;
145 case Hexagon::HvxWRRegClassID:
146 return Hexagon::HvxVRRegClass;
147 case Hexagon::HvxVQRRegClassID:
148 return Hexagon::HvxWRRegClass;
149 default:
150 break;
151 }
152#ifndef NDEBUG
153 dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
154#endif
155 llvm_unreachable("Unimplemented combination of reg class/subreg idx");
156}
157
158namespace {
159
160class RegisterRefs {
161 std::vector<BT::RegisterRef> Vector;
162
163public:
164 RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
165 for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
166 const MachineOperand &MO = MI.getOperand(i);
167 if (MO.isReg())
168 Vector[i] = BT::RegisterRef(MO);
169 // For indices that don't correspond to registers, the entry will
170 // remain constructed via the default constructor.
171 }
172 }
173
174 size_t size() const { return Vector.size(); }
175
176 const BT::RegisterRef &operator[](unsigned n) const {
177 // The main purpose of this operator is to assert with bad argument.
178 assert(n < Vector.size());
179 return Vector[n];
180 }
181};
182
183} // end anonymous namespace
184
185bool HexagonEvaluator::evaluate(const MachineInstr &MI,
186 const CellMapType &Inputs,
187 CellMapType &Outputs) const {
188 using namespace Hexagon;
189
190 unsigned NumDefs = 0;
191
192 // Basic correctness check: there should not be any defs with subregisters.
193 for (const MachineOperand &MO : MI.operands()) {
194 if (!MO.isReg() || !MO.isDef())
195 continue;
196 NumDefs++;
197 assert(MO.getSubReg() == 0);
198 }
199
200 if (NumDefs == 0)
201 return false;
202
203 unsigned Opc = MI.getOpcode();
204
205 if (MI.mayLoad()) {
206 switch (Opc) {
207 // These instructions may be marked as mayLoad, but they are generating
208 // immediate values, so skip them.
209 case CONST32:
210 case CONST64:
211 break;
212 default:
213 return evaluateLoad(MI, Inputs, Outputs);
214 }
215 }
216
217 // Check COPY instructions that copy formal parameters into virtual
218 // registers. Such parameters can be sign- or zero-extended at the
219 // call site, and we should take advantage of this knowledge. The MRI
220 // keeps a list of pairs of live-in physical and virtual registers,
221 // which provides information about which virtual registers will hold
222 // the argument values. The function will still contain instructions
223 // defining those virtual registers, and in practice those are COPY
224 // instructions from a physical to a virtual register. In such cases,
225 // applying the argument extension to the virtual register can be seen
226 // as simply mirroring the extension that had already been applied to
227 // the physical register at the call site. If the defining instruction
228 // was not a COPY, it would not be clear how to mirror that extension
229 // on the callee's side. For that reason, only check COPY instructions
230 // for potential extensions.
231 if (MI.isCopy()) {
232 if (evaluateFormalCopy(MI, Inputs, Outputs))
233 return true;
234 }
235
236 // Beyond this point, if any operand is a global, skip that instruction.
237 // The reason is that certain instructions that can take an immediate
238 // operand can also have a global symbol in that operand. To avoid
239 // checking what kind of operand a given instruction has individually
240 // for each instruction, do it here. Global symbols as operands gene-
241 // rally do not provide any useful information.
242 for (const MachineOperand &MO : MI.operands()) {
243 if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
244 MO.isCPI())
245 return false;
246 }
247
248 RegisterRefs Reg(MI);
249#define op(i) MI.getOperand(i)
250#define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
251#define im(i) MI.getOperand(i).getImm()
252
253 // If the instruction has no register operands, skip it.
254 if (Reg.size() == 0)
255 return false;
256
257 // Record result for register in operand 0.
258 auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
259 -> bool {
260 putCell(RR: Reg[0], RC: Val, M&: Outputs);
261 return true;
262 };
263 // Get the cell corresponding to the N-th operand.
264 auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
265 uint16_t W) -> BT::RegisterCell {
266 const MachineOperand &Op = MI.getOperand(i: N);
267 if (Op.isImm())
268 return eIMM(V: Op.getImm(), W);
269 if (!Op.isReg())
270 return RegisterCell::self(Reg: 0, Width: W);
271 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
272 return rc(N);
273 };
274 // Extract RW low bits of the cell.
275 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
276 -> BT::RegisterCell {
277 assert(RW <= RC.width());
278 return eXTR(A1: RC, B: 0, E: RW);
279 };
280 // Extract RW high bits of the cell.
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
282 -> BT::RegisterCell {
283 uint16_t W = RC.width();
284 assert(RW <= W);
285 return eXTR(A1: RC, B: W-RW, E: W);
286 };
287 // Extract N-th halfword (counting from the least significant position).
288 auto half = [this] (const BT::RegisterCell &RC, unsigned N)
289 -> BT::RegisterCell {
290 assert(N*16+16 <= RC.width());
291 return eXTR(A1: RC, B: N*16, E: N*16+16);
292 };
293 // Shuffle bits (pick even/odd from cells and merge into result).
294 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
295 uint16_t BW, bool Odd) -> BT::RegisterCell {
296 uint16_t I = Odd, Ws = Rs.width();
297 assert(Ws == Rt.width());
298 RegisterCell RC = eXTR(A1: Rt, B: I*BW, E: I*BW+BW).cat(RC: eXTR(A1: Rs, B: I*BW, E: I*BW+BW));
299 I += 2;
300 while (I*BW < Ws) {
301 RC.cat(RC: eXTR(A1: Rt, B: I*BW, E: I*BW+BW)).cat(RC: eXTR(A1: Rs, B: I*BW, E: I*BW+BW));
302 I += 2;
303 }
304 return RC;
305 };
306
307 // The bitwidth of the 0th operand. In most (if not all) of the
308 // instructions below, the 0th operand is the defined register.
309 // Pre-compute the bitwidth here, because it is needed in many cases
310 // cases below.
311 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(RR: Reg[0]) : 0;
312
313 // Register id of the 0th operand. It can be 0.
314 unsigned Reg0 = Reg[0].Reg;
315
316 switch (Opc) {
317 // Transfer immediate:
318
319 case A2_tfrsi:
320 case A2_tfrpi:
321 case CONST32:
322 case CONST64:
323 return rr0(eIMM(im(1), W: W0), Outputs);
324 case PS_false:
325 return rr0(RegisterCell(W0).fill(B: 0, E: W0, V: BT::BitValue::Zero), Outputs);
326 case PS_true:
327 return rr0(RegisterCell(W0).fill(B: 0, E: W0, V: BT::BitValue::One), Outputs);
328 case PS_fi: {
329 int FI = op(1).getIndex();
330 int Off = op(2).getImm();
331 unsigned A = MFI.getObjectAlign(ObjectIdx: FI).value() + std::abs(x: Off);
332 unsigned L = llvm::countr_zero(Val: A);
333 RegisterCell RC = RegisterCell::self(Reg: Reg[0].Reg, Width: W0);
334 RC.fill(B: 0, E: L, V: BT::BitValue::Zero);
335 return rr0(RC, Outputs);
336 }
337
338 // Transfer register:
339
340 case A2_tfr:
341 case A2_tfrp:
342 case C2_pxfer_map:
343 return rr0(rc(1), Outputs);
344 case C2_tfrpr: {
345 uint16_t RW = W0;
346 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
347 assert(PW <= RW);
348 RegisterCell PC = eXTR(rc(1), B: 0, E: PW);
349 RegisterCell RC = RegisterCell(RW).insert(RC: PC, M: BT::BitMask(0, PW-1));
350 RC.fill(B: PW, E: RW, V: BT::BitValue::Zero);
351 return rr0(RC, Outputs);
352 }
353 case C2_tfrrp: {
354 uint16_t RW = W0;
355 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
356 RegisterCell RC = RegisterCell::self(Reg: Reg[0].Reg, Width: RW);
357 RC.fill(B: PW, E: RW, V: BT::BitValue::Zero);
358 return rr0(eINS(A1: RC, A2: eXTR(rc(1), B: 0, E: PW), AtN: 0), Outputs);
359 }
360
361 // Arithmetic:
362
363 case A2_abs:
364 case A2_absp:
365 // TODO
366 break;
367
368 case A2_addsp: {
369 uint16_t W1 = getRegBitWidth(RR: Reg[1]);
370 assert(W0 == 64 && W1 == 32);
371 RegisterCell CW = RegisterCell(W0).insert(rc(1), M: BT::BitMask(0, W1-1));
372 RegisterCell RC = eADD(A1: eSXT(A1: CW, FromN: W1), rc(2));
373 return rr0(RC, Outputs);
374 }
375 case A2_add:
376 case A2_addp:
377 return rr0(eADD(rc(1), rc(2)), Outputs);
378 case A2_addi:
379 return rr0(eADD(rc(1), A2: eIMM(im(2), W: W0)), Outputs);
380 case S4_addi_asl_ri: {
381 RegisterCell RC = eADD(A1: eIMM(im(1), W: W0), A2: eASL(rc(2), im(3)));
382 return rr0(RC, Outputs);
383 }
384 case S4_addi_lsr_ri: {
385 RegisterCell RC = eADD(A1: eIMM(im(1), W: W0), A2: eLSR(rc(2), im(3)));
386 return rr0(RC, Outputs);
387 }
388 case S4_addaddi: {
389 RegisterCell RC = eADD(rc(1), A2: eADD(rc(2), A2: eIMM(im(3), W: W0)));
390 return rr0(RC, Outputs);
391 }
392 case M4_mpyri_addi: {
393 RegisterCell M = eMLS(rc(2), A2: eIMM(im(3), W: W0));
394 RegisterCell RC = eADD(A1: eIMM(im(1), W: W0), A2: lo(M, W0));
395 return rr0(RC, Outputs);
396 }
397 case M4_mpyrr_addi: {
398 RegisterCell M = eMLS(rc(2), rc(3));
399 RegisterCell RC = eADD(A1: eIMM(im(1), W: W0), A2: lo(M, W0));
400 return rr0(RC, Outputs);
401 }
402 case M4_mpyri_addr_u2: {
403 RegisterCell M = eMLS(A1: eIMM(im(2), W: W0), rc(3));
404 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
405 return rr0(RC, Outputs);
406 }
407 case M4_mpyri_addr: {
408 RegisterCell M = eMLS(rc(2), A2: eIMM(im(3), W: W0));
409 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
410 return rr0(RC, Outputs);
411 }
412 case M4_mpyrr_addr: {
413 RegisterCell M = eMLS(rc(2), rc(3));
414 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
415 return rr0(RC, Outputs);
416 }
417 case S4_subaddi: {
418 RegisterCell RC = eADD(rc(1), A2: eSUB(A1: eIMM(im(2), W: W0), rc(3)));
419 return rr0(RC, Outputs);
420 }
421 case M2_accii: {
422 RegisterCell RC = eADD(rc(1), A2: eADD(rc(2), A2: eIMM(im(3), W: W0)));
423 return rr0(RC, Outputs);
424 }
425 case M2_acci: {
426 RegisterCell RC = eADD(rc(1), A2: eADD(rc(2), rc(3)));
427 return rr0(RC, Outputs);
428 }
429 case M2_subacc: {
430 RegisterCell RC = eADD(rc(1), A2: eSUB(rc(2), rc(3)));
431 return rr0(RC, Outputs);
432 }
433 case S2_addasl_rrri: {
434 RegisterCell RC = eADD(rc(1), A2: eASL(rc(2), im(3)));
435 return rr0(RC, Outputs);
436 }
437 case C4_addipc: {
438 RegisterCell RPC = RegisterCell::self(Reg: Reg[0].Reg, Width: W0);
439 RPC.fill(B: 0, E: 2, V: BT::BitValue::Zero);
440 return rr0(eADD(A1: RPC, A2: eIMM(im(2), W: W0)), Outputs);
441 }
442 case A2_sub:
443 case A2_subp:
444 return rr0(eSUB(rc(1), rc(2)), Outputs);
445 case A2_subri:
446 return rr0(eSUB(A1: eIMM(im(1), W: W0), rc(2)), Outputs);
447 case S4_subi_asl_ri: {
448 RegisterCell RC = eSUB(A1: eIMM(im(1), W: W0), A2: eASL(rc(2), im(3)));
449 return rr0(RC, Outputs);
450 }
451 case S4_subi_lsr_ri: {
452 RegisterCell RC = eSUB(A1: eIMM(im(1), W: W0), A2: eLSR(rc(2), im(3)));
453 return rr0(RC, Outputs);
454 }
455 case M2_naccii: {
456 RegisterCell RC = eSUB(rc(1), A2: eADD(rc(2), A2: eIMM(im(3), W: W0)));
457 return rr0(RC, Outputs);
458 }
459 case M2_nacci: {
460 RegisterCell RC = eSUB(rc(1), A2: eADD(rc(2), rc(3)));
461 return rr0(RC, Outputs);
462 }
463 // 32-bit negation is done by "Rd = A2_subri 0, Rs"
464 case A2_negp:
465 return rr0(eSUB(A1: eIMM(V: 0, W: W0), rc(1)), Outputs);
466
467 case M2_mpy_up: {
468 RegisterCell M = eMLS(rc(1), rc(2));
469 return rr0(hi(M, W0), Outputs);
470 }
471 case M2_dpmpyss_s0:
472 return rr0(eMLS(rc(1), rc(2)), Outputs);
473 case M2_dpmpyss_acc_s0:
474 return rr0(eADD(rc(1), A2: eMLS(rc(2), rc(3))), Outputs);
475 case M2_dpmpyss_nac_s0:
476 return rr0(eSUB(rc(1), A2: eMLS(rc(2), rc(3))), Outputs);
477 case M2_mpyi: {
478 RegisterCell M = eMLS(rc(1), rc(2));
479 return rr0(lo(M, W0), Outputs);
480 }
481 case M2_macsip: {
482 RegisterCell M = eMLS(rc(2), A2: eIMM(im(3), W: W0));
483 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
484 return rr0(RC, Outputs);
485 }
486 case M2_macsin: {
487 RegisterCell M = eMLS(rc(2), A2: eIMM(im(3), W: W0));
488 RegisterCell RC = eSUB(rc(1), A2: lo(M, W0));
489 return rr0(RC, Outputs);
490 }
491 case M2_maci: {
492 RegisterCell M = eMLS(rc(2), rc(3));
493 RegisterCell RC = eADD(rc(1), A2: lo(M, W0));
494 return rr0(RC, Outputs);
495 }
496 case M2_mnaci: {
497 RegisterCell M = eMLS(rc(2), rc(3));
498 RegisterCell RC = eSUB(rc(1), A2: lo(M, W0));
499 return rr0(RC, Outputs);
500 }
501 case M2_mpysmi: {
502 RegisterCell M = eMLS(rc(1), A2: eIMM(im(2), W: W0));
503 return rr0(lo(M, 32), Outputs);
504 }
505 case M2_mpysin: {
506 RegisterCell M = eMLS(rc(1), A2: eIMM(V: -im(2), W: W0));
507 return rr0(lo(M, 32), Outputs);
508 }
509 case M2_mpysip: {
510 RegisterCell M = eMLS(rc(1), A2: eIMM(im(2), W: W0));
511 return rr0(lo(M, 32), Outputs);
512 }
513 case M2_mpyu_up: {
514 RegisterCell M = eMLU(rc(1), rc(2));
515 return rr0(hi(M, W0), Outputs);
516 }
517 case M2_dpmpyuu_s0:
518 return rr0(eMLU(rc(1), rc(2)), Outputs);
519 case M2_dpmpyuu_acc_s0:
520 return rr0(eADD(rc(1), A2: eMLU(rc(2), rc(3))), Outputs);
521 case M2_dpmpyuu_nac_s0:
522 return rr0(eSUB(rc(1), A2: eMLU(rc(2), rc(3))), Outputs);
523 //case M2_mpysu_up:
524
525 // Logical/bitwise:
526
527 case A2_andir:
528 return rr0(eAND(rc(1), A2: eIMM(im(2), W: W0)), Outputs);
529 case A2_and:
530 case A2_andp:
531 return rr0(eAND(rc(1), rc(2)), Outputs);
532 case A4_andn:
533 case A4_andnp:
534 return rr0(eAND(rc(1), A2: eNOT(rc(2))), Outputs);
535 case S4_andi_asl_ri: {
536 RegisterCell RC = eAND(A1: eIMM(im(1), W: W0), A2: eASL(rc(2), im(3)));
537 return rr0(RC, Outputs);
538 }
539 case S4_andi_lsr_ri: {
540 RegisterCell RC = eAND(A1: eIMM(im(1), W: W0), A2: eLSR(rc(2), im(3)));
541 return rr0(RC, Outputs);
542 }
543 case M4_and_and:
544 return rr0(eAND(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
545 case M4_and_andn:
546 return rr0(eAND(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
547 case M4_and_or:
548 return rr0(eAND(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
549 case M4_and_xor:
550 return rr0(eAND(rc(1), A2: eXOR(rc(2), rc(3))), Outputs);
551 case A2_orir:
552 return rr0(eORL(rc(1), A2: eIMM(im(2), W: W0)), Outputs);
553 case A2_or:
554 case A2_orp:
555 return rr0(eORL(rc(1), rc(2)), Outputs);
556 case A4_orn:
557 case A4_ornp:
558 return rr0(eORL(rc(1), A2: eNOT(rc(2))), Outputs);
559 case S4_ori_asl_ri: {
560 RegisterCell RC = eORL(A1: eIMM(im(1), W: W0), A2: eASL(rc(2), im(3)));
561 return rr0(RC, Outputs);
562 }
563 case S4_ori_lsr_ri: {
564 RegisterCell RC = eORL(A1: eIMM(im(1), W: W0), A2: eLSR(rc(2), im(3)));
565 return rr0(RC, Outputs);
566 }
567 case M4_or_and:
568 return rr0(eORL(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
569 case M4_or_andn:
570 return rr0(eORL(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
571 case S4_or_andi:
572 case S4_or_andix: {
573 RegisterCell RC = eORL(rc(1), A2: eAND(rc(2), A2: eIMM(im(3), W: W0)));
574 return rr0(RC, Outputs);
575 }
576 case S4_or_ori: {
577 RegisterCell RC = eORL(rc(1), A2: eORL(rc(2), A2: eIMM(im(3), W: W0)));
578 return rr0(RC, Outputs);
579 }
580 case M4_or_or:
581 return rr0(eORL(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
582 case M4_or_xor:
583 return rr0(eORL(rc(1), A2: eXOR(rc(2), rc(3))), Outputs);
584 case A2_xor:
585 case A2_xorp:
586 return rr0(eXOR(rc(1), rc(2)), Outputs);
587 case M4_xor_and:
588 return rr0(eXOR(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
589 case M4_xor_andn:
590 return rr0(eXOR(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
591 case M4_xor_or:
592 return rr0(eXOR(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
593 case M4_xor_xacc:
594 return rr0(eXOR(rc(1), A2: eXOR(rc(2), rc(3))), Outputs);
595 case A2_not:
596 case A2_notp:
597 return rr0(eNOT(rc(1)), Outputs);
598
599 case S2_asl_i_r:
600 case S2_asl_i_p:
601 return rr0(eASL(rc(1), im(2)), Outputs);
602 case A2_aslh:
603 return rr0(eASL(rc(1), Sh: 16), Outputs);
604 case S2_asl_i_r_acc:
605 case S2_asl_i_p_acc:
606 return rr0(eADD(rc(1), A2: eASL(rc(2), im(3))), Outputs);
607 case S2_asl_i_r_nac:
608 case S2_asl_i_p_nac:
609 return rr0(eSUB(rc(1), A2: eASL(rc(2), im(3))), Outputs);
610 case S2_asl_i_r_and:
611 case S2_asl_i_p_and:
612 return rr0(eAND(rc(1), A2: eASL(rc(2), im(3))), Outputs);
613 case S2_asl_i_r_or:
614 case S2_asl_i_p_or:
615 return rr0(eORL(rc(1), A2: eASL(rc(2), im(3))), Outputs);
616 case S2_asl_i_r_xacc:
617 case S2_asl_i_p_xacc:
618 return rr0(eXOR(rc(1), A2: eASL(rc(2), im(3))), Outputs);
619 case S2_asl_i_vh:
620 case S2_asl_i_vw:
621 // TODO
622 break;
623
624 case S2_asr_i_r:
625 case S2_asr_i_p:
626 return rr0(eASR(rc(1), im(2)), Outputs);
627 case A2_asrh:
628 return rr0(eASR(rc(1), Sh: 16), Outputs);
629 case S2_asr_i_r_acc:
630 case S2_asr_i_p_acc:
631 return rr0(eADD(rc(1), A2: eASR(rc(2), im(3))), Outputs);
632 case S2_asr_i_r_nac:
633 case S2_asr_i_p_nac:
634 return rr0(eSUB(rc(1), A2: eASR(rc(2), im(3))), Outputs);
635 case S2_asr_i_r_and:
636 case S2_asr_i_p_and:
637 return rr0(eAND(rc(1), A2: eASR(rc(2), im(3))), Outputs);
638 case S2_asr_i_r_or:
639 case S2_asr_i_p_or:
640 return rr0(eORL(rc(1), A2: eASR(rc(2), im(3))), Outputs);
641 case S2_asr_i_r_rnd: {
642 // The input is first sign-extended to 64 bits, then the output
643 // is truncated back to 32 bits.
644 assert(W0 == 32);
645 RegisterCell XC = eSXT(rc(1).cat(RC: eIMM(V: 0, W: W0)), FromN: W0);
646 RegisterCell RC = eASR(A1: eADD(A1: eASR(A1: XC, im(2)), A2: eIMM(V: 1, W: 2*W0)), Sh: 1);
647 return rr0(eXTR(A1: RC, B: 0, E: W0), Outputs);
648 }
649 case S2_asr_i_r_rnd_goodsyntax: {
650 int64_t S = im(2);
651 if (S == 0)
652 return rr0(rc(1), Outputs);
653 // Result: S2_asr_i_r_rnd Rs, u5-1
654 RegisterCell XC = eSXT(rc(1).cat(RC: eIMM(V: 0, W: W0)), FromN: W0);
655 RegisterCell RC = eLSR(A1: eADD(A1: eASR(A1: XC, Sh: S-1), A2: eIMM(V: 1, W: 2*W0)), Sh: 1);
656 return rr0(eXTR(A1: RC, B: 0, E: W0), Outputs);
657 }
658 case S2_asr_r_vh:
659 case S2_asr_i_vw:
660 case S2_asr_i_svw_trun:
661 // TODO
662 break;
663
664 case S2_lsr_i_r:
665 case S2_lsr_i_p:
666 return rr0(eLSR(rc(1), im(2)), Outputs);
667 case S2_lsr_i_r_acc:
668 case S2_lsr_i_p_acc:
669 return rr0(eADD(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
670 case S2_lsr_i_r_nac:
671 case S2_lsr_i_p_nac:
672 return rr0(eSUB(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
673 case S2_lsr_i_r_and:
674 case S2_lsr_i_p_and:
675 return rr0(eAND(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
676 case S2_lsr_i_r_or:
677 case S2_lsr_i_p_or:
678 return rr0(eORL(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
679 case S2_lsr_i_r_xacc:
680 case S2_lsr_i_p_xacc:
681 return rr0(eXOR(rc(1), A2: eLSR(rc(2), im(3))), Outputs);
682
683 case S2_clrbit_i: {
684 RegisterCell RC = rc(1);
685 RC[im(2)] = BT::BitValue::Zero;
686 return rr0(RC, Outputs);
687 }
688 case S2_setbit_i: {
689 RegisterCell RC = rc(1);
690 RC[im(2)] = BT::BitValue::One;
691 return rr0(RC, Outputs);
692 }
693 case S2_togglebit_i: {
694 RegisterCell RC = rc(1);
695 uint16_t BX = im(2);
696 RC[BX] = RC[BX].is(T: 0) ? BT::BitValue::One
697 : RC[BX].is(T: 1) ? BT::BitValue::Zero
698 : BT::BitValue::self();
699 return rr0(RC, Outputs);
700 }
701
702 case A4_bitspliti: {
703 uint16_t W1 = getRegBitWidth(RR: Reg[1]);
704 uint16_t BX = im(2);
705 // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
706 const BT::BitValue Zero = BT::BitValue::Zero;
707 RegisterCell RZ = RegisterCell(W0).fill(B: BX, E: W1, V: Zero)
708 .fill(B: W1+(W1-BX), E: W0, V: Zero);
709 RegisterCell BF1 = eXTR(rc(1), B: 0, E: BX), BF2 = eXTR(rc(1), B: BX, E: W1);
710 RegisterCell RC = eINS(A1: eINS(A1: RZ, A2: BF1, AtN: 0), A2: BF2, AtN: W1);
711 return rr0(RC, Outputs);
712 }
713 case S4_extract:
714 case S4_extractp:
715 case S2_extractu:
716 case S2_extractup: {
717 uint16_t Wd = im(2), Of = im(3);
718 assert(Wd <= W0);
719 if (Wd == 0)
720 return rr0(eIMM(V: 0, W: W0), Outputs);
721 // If the width extends beyond the register size, pad the register
722 // with 0 bits.
723 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(RC: eIMM(V: 0, W: Wd+Of-W0)) : rc(1);
724 RegisterCell Ext = eXTR(A1: Pad, B: Of, E: Wd+Of);
725 // Ext is short, need to extend it with 0s or sign bit.
726 RegisterCell RC = RegisterCell(W0).insert(RC: Ext, M: BT::BitMask(0, Wd-1));
727 if (Opc == S2_extractu || Opc == S2_extractup)
728 return rr0(eZXT(A1: RC, FromN: Wd), Outputs);
729 return rr0(eSXT(A1: RC, FromN: Wd), Outputs);
730 }
731 case S2_insert:
732 case S2_insertp: {
733 uint16_t Wd = im(3), Of = im(4);
734 assert(Wd < W0 && Of < W0);
735 // If Wd+Of exceeds W0, the inserted bits are truncated.
736 if (Wd+Of > W0)
737 Wd = W0-Of;
738 if (Wd == 0)
739 return rr0(rc(1), Outputs);
740 return rr0(eINS(rc(1), A2: eXTR(rc(2), B: 0, E: Wd), AtN: Of), Outputs);
741 }
742
743 // Bit permutations:
744
745 case A2_combineii:
746 case A4_combineii:
747 case A4_combineir:
748 case A4_combineri:
749 case A2_combinew:
750 case V6_vcombine:
751 assert(W0 % 2 == 0);
752 return rr0(cop(2, W0/2).cat(RC: cop(1, W0/2)), Outputs);
753 case A2_combine_ll:
754 case A2_combine_lh:
755 case A2_combine_hl:
756 case A2_combine_hh: {
757 assert(W0 == 32);
758 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
759 // Low half in the output is 0 for _ll and _hl, 1 otherwise:
760 unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
761 // High half in the output is 0 for _ll and _lh, 1 otherwise:
762 unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
763 RegisterCell R1 = rc(1);
764 RegisterCell R2 = rc(2);
765 RegisterCell RC = half(R2, LoH).cat(RC: half(R1, HiH));
766 return rr0(RC, Outputs);
767 }
768 case S2_packhl: {
769 assert(W0 == 64);
770 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
771 RegisterCell R1 = rc(1);
772 RegisterCell R2 = rc(2);
773 RegisterCell RC = half(R2, 0).cat(RC: half(R1, 0)).cat(RC: half(R2, 1))
774 .cat(RC: half(R1, 1));
775 return rr0(RC, Outputs);
776 }
777 case S2_shuffeb: {
778 RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
779 return rr0(RC, Outputs);
780 }
781 case S2_shuffeh: {
782 RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
783 return rr0(RC, Outputs);
784 }
785 case S2_shuffob: {
786 RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
787 return rr0(RC, Outputs);
788 }
789 case S2_shuffoh: {
790 RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
791 return rr0(RC, Outputs);
792 }
793 case C2_mask: {
794 uint16_t WR = W0;
795 uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
796 assert(WR == 64 && WP == 8);
797 RegisterCell R1 = rc(1);
798 RegisterCell RC(WR);
799 for (uint16_t i = 0; i < WP; ++i) {
800 const BT::BitValue &V = R1[i];
801 BT::BitValue F = (V.is(T: 0) || V.is(T: 1)) ? V : BT::BitValue::self();
802 RC.fill(B: i*8, E: i*8+8, V: F);
803 }
804 return rr0(RC, Outputs);
805 }
806
807 // Mux:
808
809 case C2_muxii:
810 case C2_muxir:
811 case C2_muxri:
812 case C2_mux: {
813 BT::BitValue PC0 = rc(1)[0];
814 RegisterCell R2 = cop(2, W0);
815 RegisterCell R3 = cop(3, W0);
816 if (PC0.is(T: 0) || PC0.is(T: 1))
817 return rr0(RegisterCell::ref(C: PC0 ? R2 : R3), Outputs);
818 R2.meet(RC: R3, SelfR: Reg[0].Reg);
819 return rr0(R2, Outputs);
820 }
821 case C2_vmux:
822 // TODO
823 break;
824
825 // Sign- and zero-extension:
826
827 case A2_sxtb:
828 return rr0(eSXT(rc(1), FromN: 8), Outputs);
829 case A2_sxth:
830 return rr0(eSXT(rc(1), FromN: 16), Outputs);
831 case A2_sxtw: {
832 uint16_t W1 = getRegBitWidth(RR: Reg[1]);
833 assert(W0 == 64 && W1 == 32);
834 RegisterCell RC = eSXT(rc(1).cat(RC: eIMM(V: 0, W: W1)), FromN: W1);
835 return rr0(RC, Outputs);
836 }
837 case A2_zxtb:
838 return rr0(eZXT(rc(1), FromN: 8), Outputs);
839 case A2_zxth:
840 return rr0(eZXT(rc(1), FromN: 16), Outputs);
841
842 // Saturations
843
844 case A2_satb:
845 return rr0(eSXT(A1: RegisterCell::self(Reg: 0, Width: W0).regify(R: Reg0), FromN: 8), Outputs);
846 case A2_sath:
847 return rr0(eSXT(A1: RegisterCell::self(Reg: 0, Width: W0).regify(R: Reg0), FromN: 16), Outputs);
848 case A2_satub:
849 return rr0(eZXT(A1: RegisterCell::self(Reg: 0, Width: W0).regify(R: Reg0), FromN: 8), Outputs);
850 case A2_satuh:
851 return rr0(eZXT(A1: RegisterCell::self(Reg: 0, Width: W0).regify(R: Reg0), FromN: 16), Outputs);
852
853 // Bit count:
854
855 case S2_cl0:
856 case S2_cl0p:
857 // Always produce a 32-bit result.
858 return rr0(eCLB(rc(1), B: false/*bit*/, W: 32), Outputs);
859 case S2_cl1:
860 case S2_cl1p:
861 return rr0(eCLB(rc(1), B: true/*bit*/, W: 32), Outputs);
862 case S2_clb:
863 case S2_clbp: {
864 uint16_t W1 = getRegBitWidth(RR: Reg[1]);
865 RegisterCell R1 = rc(1);
866 BT::BitValue TV = R1[W1-1];
867 if (TV.is(T: 0) || TV.is(T: 1))
868 return rr0(eCLB(A1: R1, B: TV, W: 32), Outputs);
869 break;
870 }
871 case S2_ct0:
872 case S2_ct0p:
873 return rr0(eCTB(rc(1), B: false/*bit*/, W: 32), Outputs);
874 case S2_ct1:
875 case S2_ct1p:
876 return rr0(eCTB(rc(1), B: true/*bit*/, W: 32), Outputs);
877 case S5_popcountp:
878 // TODO
879 break;
880
881 case C2_all8: {
882 RegisterCell P1 = rc(1);
883 bool Has0 = false, All1 = true;
884 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
885 if (!P1[i].is(T: 1))
886 All1 = false;
887 if (!P1[i].is(T: 0))
888 continue;
889 Has0 = true;
890 break;
891 }
892 if (!Has0 && !All1)
893 break;
894 RegisterCell RC(W0);
895 RC.fill(B: 0, E: W0, V: (All1 ? BT::BitValue::One : BT::BitValue::Zero));
896 return rr0(RC, Outputs);
897 }
898 case C2_any8: {
899 RegisterCell P1 = rc(1);
900 bool Has1 = false, All0 = true;
901 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
902 if (!P1[i].is(T: 0))
903 All0 = false;
904 if (!P1[i].is(T: 1))
905 continue;
906 Has1 = true;
907 break;
908 }
909 if (!Has1 && !All0)
910 break;
911 RegisterCell RC(W0);
912 RC.fill(B: 0, E: W0, V: (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
913 return rr0(RC, Outputs);
914 }
915 case C2_and:
916 return rr0(eAND(rc(1), rc(2)), Outputs);
917 case C2_andn:
918 return rr0(eAND(rc(1), A2: eNOT(rc(2))), Outputs);
919 case C2_not:
920 return rr0(eNOT(rc(1)), Outputs);
921 case C2_or:
922 return rr0(eORL(rc(1), rc(2)), Outputs);
923 case C2_orn:
924 return rr0(eORL(rc(1), A2: eNOT(rc(2))), Outputs);
925 case C2_xor:
926 return rr0(eXOR(rc(1), rc(2)), Outputs);
927 case C4_and_and:
928 return rr0(eAND(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
929 case C4_and_andn:
930 return rr0(eAND(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
931 case C4_and_or:
932 return rr0(eAND(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
933 case C4_and_orn:
934 return rr0(eAND(rc(1), A2: eORL(rc(2), A2: eNOT(rc(3)))), Outputs);
935 case C4_or_and:
936 return rr0(eORL(rc(1), A2: eAND(rc(2), rc(3))), Outputs);
937 case C4_or_andn:
938 return rr0(eORL(rc(1), A2: eAND(rc(2), A2: eNOT(rc(3)))), Outputs);
939 case C4_or_or:
940 return rr0(eORL(rc(1), A2: eORL(rc(2), rc(3))), Outputs);
941 case C4_or_orn:
942 return rr0(eORL(rc(1), A2: eORL(rc(2), A2: eNOT(rc(3)))), Outputs);
943 case C2_bitsclr:
944 case C2_bitsclri:
945 case C2_bitsset:
946 case C4_nbitsclr:
947 case C4_nbitsclri:
948 case C4_nbitsset:
949 // TODO
950 break;
951 case S2_tstbit_i:
952 case S4_ntstbit_i: {
953 BT::BitValue V = rc(1)[im(2)];
954 if (V.is(T: 0) || V.is(T: 1)) {
955 // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
956 bool TV = (Opc == S2_tstbit_i);
957 BT::BitValue F = V.is(T: TV) ? BT::BitValue::One : BT::BitValue::Zero;
958 return rr0(RegisterCell(W0).fill(B: 0, E: W0, V: F), Outputs);
959 }
960 break;
961 }
962
963 default:
964 // For instructions that define a single predicate registers, store
965 // the low 8 bits of the register only.
966 if (unsigned DefR = getUniqueDefVReg(MI)) {
967 if (MRI.getRegClass(Reg: DefR) == &Hexagon::PredRegsRegClass) {
968 BT::RegisterRef PD(DefR, 0);
969 uint16_t RW = getRegBitWidth(RR: PD);
970 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
971 RegisterCell RC = RegisterCell::self(Reg: DefR, Width: RW);
972 RC.fill(B: PW, E: RW, V: BT::BitValue::Zero);
973 putCell(RR: PD, RC, M&: Outputs);
974 return true;
975 }
976 }
977 return MachineEvaluator::evaluate(MI, Inputs, Outputs);
978 }
979 #undef im
980 #undef rc
981 #undef op
982 return false;
983}
984
985bool HexagonEvaluator::evaluate(const MachineInstr &BI,
986 const CellMapType &Inputs,
987 BranchTargetList &Targets,
988 bool &FallsThru) const {
989 // We need to evaluate one branch at a time. TII::analyzeBranch checks
990 // all the branches in a basic block at once, so we cannot use it.
991 unsigned Opc = BI.getOpcode();
992 bool SimpleBranch = false;
993 bool Negated = false;
994 switch (Opc) {
995 case Hexagon::J2_jumpf:
996 case Hexagon::J2_jumpfpt:
997 case Hexagon::J2_jumpfnew:
998 case Hexagon::J2_jumpfnewpt:
999 Negated = true;
1000 [[fallthrough]];
1001 case Hexagon::J2_jumpt:
1002 case Hexagon::J2_jumptpt:
1003 case Hexagon::J2_jumptnew:
1004 case Hexagon::J2_jumptnewpt:
1005 // Simple branch: if([!]Pn) jump ...
1006 // i.e. Op0 = predicate, Op1 = branch target.
1007 SimpleBranch = true;
1008 break;
1009 case Hexagon::J2_jump:
1010 Targets.insert(X: BI.getOperand(i: 0).getMBB());
1011 FallsThru = false;
1012 return true;
1013 default:
1014 // If the branch is of unknown type, assume that all successors are
1015 // executable.
1016 return false;
1017 }
1018
1019 if (!SimpleBranch)
1020 return false;
1021
1022 // BI is a conditional branch if we got here.
1023 RegisterRef PR = BI.getOperand(i: 0);
1024 RegisterCell PC = getCell(RR: PR, M: Inputs);
1025 const BT::BitValue &Test = PC[0];
1026
1027 // If the condition is neither true nor false, then it's unknown.
1028 if (!Test.is(T: 0) && !Test.is(T: 1))
1029 return false;
1030
1031 // "Test.is(!Negated)" means "branch condition is true".
1032 if (!Test.is(T: !Negated)) {
1033 // Condition known to be false.
1034 FallsThru = true;
1035 return true;
1036 }
1037
1038 Targets.insert(X: BI.getOperand(i: 1).getMBB());
1039 FallsThru = false;
1040 return true;
1041}
1042
1043unsigned HexagonEvaluator::getUniqueDefVReg(const MachineInstr &MI) const {
1044 unsigned DefReg = 0;
1045 for (const MachineOperand &Op : MI.operands()) {
1046 if (!Op.isReg() || !Op.isDef())
1047 continue;
1048 Register R = Op.getReg();
1049 if (!R.isVirtual())
1050 continue;
1051 if (DefReg != 0)
1052 return 0;
1053 DefReg = R;
1054 }
1055 return DefReg;
1056}
1057
1058bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
1059 const CellMapType &Inputs,
1060 CellMapType &Outputs) const {
1061 using namespace Hexagon;
1062
1063 if (TII.isPredicated(MI))
1064 return false;
1065 assert(MI.mayLoad() && "A load that mayn't?");
1066 unsigned Opc = MI.getOpcode();
1067
1068 uint16_t BitNum;
1069 bool SignEx;
1070
1071 switch (Opc) {
1072 default:
1073 return false;
1074
1075#if 0
1076 // memb_fifo
1077 case L2_loadalignb_pbr:
1078 case L2_loadalignb_pcr:
1079 case L2_loadalignb_pi:
1080 // memh_fifo
1081 case L2_loadalignh_pbr:
1082 case L2_loadalignh_pcr:
1083 case L2_loadalignh_pi:
1084 // membh
1085 case L2_loadbsw2_pbr:
1086 case L2_loadbsw2_pci:
1087 case L2_loadbsw2_pcr:
1088 case L2_loadbsw2_pi:
1089 case L2_loadbsw4_pbr:
1090 case L2_loadbsw4_pci:
1091 case L2_loadbsw4_pcr:
1092 case L2_loadbsw4_pi:
1093 // memubh
1094 case L2_loadbzw2_pbr:
1095 case L2_loadbzw2_pci:
1096 case L2_loadbzw2_pcr:
1097 case L2_loadbzw2_pi:
1098 case L2_loadbzw4_pbr:
1099 case L2_loadbzw4_pci:
1100 case L2_loadbzw4_pcr:
1101 case L2_loadbzw4_pi:
1102#endif
1103
1104 case L2_loadrbgp:
1105 case L2_loadrb_io:
1106 case L2_loadrb_pbr:
1107 case L2_loadrb_pci:
1108 case L2_loadrb_pcr:
1109 case L2_loadrb_pi:
1110 case PS_loadrbabs:
1111 case L4_loadrb_ap:
1112 case L4_loadrb_rr:
1113 case L4_loadrb_ur:
1114 BitNum = 8;
1115 SignEx = true;
1116 break;
1117
1118 case L2_loadrubgp:
1119 case L2_loadrub_io:
1120 case L2_loadrub_pbr:
1121 case L2_loadrub_pci:
1122 case L2_loadrub_pcr:
1123 case L2_loadrub_pi:
1124 case PS_loadrubabs:
1125 case L4_loadrub_ap:
1126 case L4_loadrub_rr:
1127 case L4_loadrub_ur:
1128 BitNum = 8;
1129 SignEx = false;
1130 break;
1131
1132 case L2_loadrhgp:
1133 case L2_loadrh_io:
1134 case L2_loadrh_pbr:
1135 case L2_loadrh_pci:
1136 case L2_loadrh_pcr:
1137 case L2_loadrh_pi:
1138 case PS_loadrhabs:
1139 case L4_loadrh_ap:
1140 case L4_loadrh_rr:
1141 case L4_loadrh_ur:
1142 BitNum = 16;
1143 SignEx = true;
1144 break;
1145
1146 case L2_loadruhgp:
1147 case L2_loadruh_io:
1148 case L2_loadruh_pbr:
1149 case L2_loadruh_pci:
1150 case L2_loadruh_pcr:
1151 case L2_loadruh_pi:
1152 case L4_loadruh_rr:
1153 case PS_loadruhabs:
1154 case L4_loadruh_ap:
1155 case L4_loadruh_ur:
1156 BitNum = 16;
1157 SignEx = false;
1158 break;
1159
1160 case L2_loadrigp:
1161 case L2_loadri_io:
1162 case L2_loadri_pbr:
1163 case L2_loadri_pci:
1164 case L2_loadri_pcr:
1165 case L2_loadri_pi:
1166 case L2_loadw_locked:
1167 case PS_loadriabs:
1168 case L4_loadri_ap:
1169 case L4_loadri_rr:
1170 case L4_loadri_ur:
1171 case LDriw_pred:
1172 BitNum = 32;
1173 SignEx = true;
1174 break;
1175
1176 case L2_loadrdgp:
1177 case L2_loadrd_io:
1178 case L2_loadrd_pbr:
1179 case L2_loadrd_pci:
1180 case L2_loadrd_pcr:
1181 case L2_loadrd_pi:
1182 case L4_loadd_locked:
1183 case PS_loadrdabs:
1184 case L4_loadrd_ap:
1185 case L4_loadrd_rr:
1186 case L4_loadrd_ur:
1187 BitNum = 64;
1188 SignEx = true;
1189 break;
1190 }
1191
1192 const MachineOperand &MD = MI.getOperand(i: 0);
1193 assert(MD.isReg() && MD.isDef());
1194 RegisterRef RD = MD;
1195
1196 uint16_t W = getRegBitWidth(RR: RD);
1197 assert(W >= BitNum && BitNum > 0);
1198 RegisterCell Res(W);
1199
1200 for (uint16_t i = 0; i < BitNum; ++i)
1201 Res[i] = BT::BitValue::self(Self: BT::BitRef(RD.Reg, i));
1202
1203 if (SignEx) {
1204 const BT::BitValue &Sign = Res[BitNum-1];
1205 for (uint16_t i = BitNum; i < W; ++i)
1206 Res[i] = BT::BitValue::ref(V: Sign);
1207 } else {
1208 for (uint16_t i = BitNum; i < W; ++i)
1209 Res[i] = BT::BitValue::Zero;
1210 }
1211
1212 putCell(RR: RD, RC: Res, M&: Outputs);
1213 return true;
1214}
1215
1216bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1217 const CellMapType &Inputs,
1218 CellMapType &Outputs) const {
1219 // If MI defines a formal parameter, but is not a copy (loads are handled
1220 // in evaluateLoad), then it's not clear what to do.
1221 assert(MI.isCopy());
1222
1223 RegisterRef RD = MI.getOperand(i: 0);
1224 RegisterRef RS = MI.getOperand(i: 1);
1225 assert(RD.Sub == 0);
1226 if (!RS.Reg.isPhysical())
1227 return false;
1228 RegExtMap::const_iterator F = VRX.find(Val: RD.Reg);
1229 if (F == VRX.end())
1230 return false;
1231
1232 uint16_t EW = F->second.Width;
1233 // Store RD's cell into the map. This will associate the cell with a virtual
1234 // register, and make zero-/sign-extends possible (otherwise we would be ex-
1235 // tending "self" bit values, which will have no effect, since "self" values
1236 // cannot be references to anything).
1237 putCell(RR: RD, RC: getCell(RR: RS, M: Inputs), M&: Outputs);
1238
1239 RegisterCell Res;
1240 // Read RD's cell from the outputs instead of RS's cell from the inputs:
1241 if (F->second.Type == ExtType::SExt)
1242 Res = eSXT(A1: getCell(RR: RD, M: Outputs), FromN: EW);
1243 else if (F->second.Type == ExtType::ZExt)
1244 Res = eZXT(A1: getCell(RR: RD, M: Outputs), FromN: EW);
1245
1246 putCell(RR: RD, RC: Res, M&: Outputs);
1247 return true;
1248}
1249
1250unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1251 using namespace Hexagon;
1252
1253 bool Is64 = DoubleRegsRegClass.contains(Reg: PReg);
1254 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1255
1256 static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1257 static const unsigned Phys64[] = { D0, D1, D2 };
1258 const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1259 const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1260
1261 // Return the first parameter register of the required width.
1262 if (PReg == 0)
1263 return (Width <= 32) ? Phys32[0] : Phys64[0];
1264
1265 // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1266 // next register.
1267 unsigned Idx32 = 0, Idx64 = 0;
1268 if (!Is64) {
1269 while (Idx32 < Num32) {
1270 if (Phys32[Idx32] == PReg)
1271 break;
1272 Idx32++;
1273 }
1274 Idx64 = Idx32/2;
1275 } else {
1276 while (Idx64 < Num64) {
1277 if (Phys64[Idx64] == PReg)
1278 break;
1279 Idx64++;
1280 }
1281 Idx32 = Idx64*2+1;
1282 }
1283
1284 if (Width <= 32)
1285 return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1286 return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1287}
1288
1289unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1290 for (std::pair<unsigned,unsigned> P : MRI.liveins())
1291 if (P.first == PReg)
1292 return P.second;
1293 return 0;
1294}
1295