1//===-- PPCBranchSelector.cpp - Emit long conditional branches ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that scans a machine function to determine which
10// conditional branches need more than 16 bits of displacement to reach their
11// target basic block. It does this in two passes; a calculation of basic block
12// positions pass, and a branch pseudo op to machine branch opcode pass. This
13// pass should be run last, just before the assembly printer.
14//
15//===----------------------------------------------------------------------===//
16
17#include "MCTargetDesc/PPCPredicates.h"
18#include "PPC.h"
19#include "PPCInstrBuilder.h"
20#include "PPCInstrInfo.h"
21#include "PPCSubtarget.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/Support/MathExtras.h"
27#include "llvm/Target/TargetMachine.h"
28#include <algorithm>
29using namespace llvm;
30
31#define DEBUG_TYPE "ppc-branch-select"
32
33STATISTIC(NumExpanded, "Number of branches expanded to long format");
34STATISTIC(NumPrefixed, "Number of prefixed instructions");
35STATISTIC(NumPrefixedAligned,
36 "Number of prefixed instructions that have been aligned");
37
38namespace {
39 struct PPCBSel : public MachineFunctionPass {
40 static char ID;
41 PPCBSel() : MachineFunctionPass(ID) {
42 initializePPCBSelPass(*PassRegistry::getPassRegistry());
43 }
44
45 // The sizes of the basic blocks in the function (the first
46 // element of the pair); the second element of the pair is the amount of the
47 // size that is due to potential padding.
48 std::vector<std::pair<unsigned, unsigned>> BlockSizes;
49
50 // The first block number which has imprecise instruction address.
51 int FirstImpreciseBlock = -1;
52
53 unsigned GetAlignmentAdjustment(MachineBasicBlock &MBB, unsigned Offset);
54 unsigned ComputeBlockSizes(MachineFunction &Fn);
55 void modifyAdjustment(MachineFunction &Fn);
56 int computeBranchSize(MachineFunction &Fn,
57 const MachineBasicBlock *Src,
58 const MachineBasicBlock *Dest,
59 unsigned BrOffset);
60
61 bool runOnMachineFunction(MachineFunction &Fn) override;
62
63 MachineFunctionProperties getRequiredProperties() const override {
64 return MachineFunctionProperties().set(
65 MachineFunctionProperties::Property::NoVRegs);
66 }
67
68 StringRef getPassName() const override { return "PowerPC Branch Selector"; }
69 };
70 char PPCBSel::ID = 0;
71}
72
73INITIALIZE_PASS(PPCBSel, "ppc-branch-select", "PowerPC Branch Selector",
74 false, false)
75
76/// createPPCBranchSelectionPass - returns an instance of the Branch Selection
77/// Pass
78///
79FunctionPass *llvm::createPPCBranchSelectionPass() {
80 return new PPCBSel();
81}
82
83/// In order to make MBB aligned, we need to add an adjustment value to the
84/// original Offset.
85unsigned PPCBSel::GetAlignmentAdjustment(MachineBasicBlock &MBB,
86 unsigned Offset) {
87 const Align Alignment = MBB.getAlignment();
88 if (Alignment == Align(1))
89 return 0;
90
91 const Align ParentAlign = MBB.getParent()->getAlignment();
92
93 if (Alignment <= ParentAlign)
94 return offsetToAlignment(Value: Offset, Alignment);
95
96 // The alignment of this MBB is larger than the function's alignment, so we
97 // can't tell whether or not it will insert nops. Assume that it will.
98 if (FirstImpreciseBlock < 0)
99 FirstImpreciseBlock = MBB.getNumber();
100 return Alignment.value() + offsetToAlignment(Value: Offset, Alignment);
101}
102
103/// We need to be careful about the offset of the first block in the function
104/// because it might not have the function's alignment. This happens because,
105/// under the ELFv2 ABI, for functions which require a TOC pointer, we add a
106/// two-instruction sequence to the start of the function.
107/// Note: This needs to be synchronized with the check in
108/// PPCLinuxAsmPrinter::EmitFunctionBodyStart.
109static inline unsigned GetInitialOffset(MachineFunction &Fn) {
110 unsigned InitialOffset = 0;
111 if (Fn.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
112 !Fn.getRegInfo().use_empty(RegNo: PPC::X2))
113 InitialOffset = 8;
114 return InitialOffset;
115}
116
117/// Measure each MBB and compute a size for the entire function.
118unsigned PPCBSel::ComputeBlockSizes(MachineFunction &Fn) {
119 const PPCInstrInfo *TII =
120 static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
121 unsigned FuncSize = GetInitialOffset(Fn);
122
123 for (MachineBasicBlock &MBB : Fn) {
124 // The end of the previous block may have extra nops if this block has an
125 // alignment requirement.
126 if (MBB.getNumber() > 0) {
127 unsigned AlignExtra = GetAlignmentAdjustment(MBB, Offset: FuncSize);
128
129 auto &BS = BlockSizes[MBB.getNumber()-1];
130 BS.first += AlignExtra;
131 BS.second = AlignExtra;
132
133 FuncSize += AlignExtra;
134 }
135
136 unsigned BlockSize = 0;
137 unsigned UnalignedBytesRemaining = 0;
138 for (MachineInstr &MI : MBB) {
139 unsigned MINumBytes = TII->getInstSizeInBytes(MI);
140 if (MI.isInlineAsm() && (FirstImpreciseBlock < 0))
141 FirstImpreciseBlock = MBB.getNumber();
142 if (TII->isPrefixed(Opcode: MI.getOpcode())) {
143 NumPrefixed++;
144
145 // All 8 byte instructions may require alignment. Each 8 byte
146 // instruction may be aligned by another 4 bytes.
147 // This means that an 8 byte instruction may require 12 bytes
148 // (8 for the instruction itself and 4 for the alignment nop).
149 // This will happen if an 8 byte instruction can be aligned to 64 bytes
150 // by only adding a 4 byte nop.
151 // We don't know the alignment at this point in the code so we have to
152 // adopt a more pessimistic approach. If an instruction may need
153 // alignment we assume that it does need alignment and add 4 bytes to
154 // it. As a result we may end up with more long branches than before
155 // but we are in the safe position where if we need a long branch we
156 // have one.
157 // The if statement checks to make sure that two 8 byte instructions
158 // are at least 64 bytes away from each other. It is not possible for
159 // two instructions that both need alignment to be within 64 bytes of
160 // each other.
161 if (!UnalignedBytesRemaining) {
162 BlockSize += 4;
163 UnalignedBytesRemaining = 60;
164 NumPrefixedAligned++;
165 }
166 }
167 UnalignedBytesRemaining -= std::min(a: UnalignedBytesRemaining, b: MINumBytes);
168 BlockSize += MINumBytes;
169 }
170
171 BlockSizes[MBB.getNumber()].first = BlockSize;
172 FuncSize += BlockSize;
173 }
174
175 return FuncSize;
176}
177
178/// Modify the basic block align adjustment.
179void PPCBSel::modifyAdjustment(MachineFunction &Fn) {
180 unsigned Offset = GetInitialOffset(Fn);
181 for (MachineBasicBlock &MBB : Fn) {
182 if (MBB.getNumber() > 0) {
183 auto &BS = BlockSizes[MBB.getNumber()-1];
184 BS.first -= BS.second;
185 Offset -= BS.second;
186
187 unsigned AlignExtra = GetAlignmentAdjustment(MBB, Offset);
188
189 BS.first += AlignExtra;
190 BS.second = AlignExtra;
191
192 Offset += AlignExtra;
193 }
194
195 Offset += BlockSizes[MBB.getNumber()].first;
196 }
197}
198
199/// Determine the offset from the branch in Src block to the Dest block.
200/// BrOffset is the offset of the branch instruction inside Src block.
201int PPCBSel::computeBranchSize(MachineFunction &Fn,
202 const MachineBasicBlock *Src,
203 const MachineBasicBlock *Dest,
204 unsigned BrOffset) {
205 int BranchSize;
206 Align MaxAlign = Align(4);
207 bool NeedExtraAdjustment = false;
208 if (Dest->getNumber() <= Src->getNumber()) {
209 // If this is a backwards branch, the delta is the offset from the
210 // start of this block to this branch, plus the sizes of all blocks
211 // from this block to the dest.
212 BranchSize = BrOffset;
213 MaxAlign = std::max(a: MaxAlign, b: Src->getAlignment());
214
215 int DestBlock = Dest->getNumber();
216 BranchSize += BlockSizes[DestBlock].first;
217 for (unsigned i = DestBlock+1, e = Src->getNumber(); i < e; ++i) {
218 BranchSize += BlockSizes[i].first;
219 MaxAlign = std::max(a: MaxAlign, b: Fn.getBlockNumbered(N: i)->getAlignment());
220 }
221
222 NeedExtraAdjustment = (FirstImpreciseBlock >= 0) &&
223 (DestBlock >= FirstImpreciseBlock);
224 } else {
225 // Otherwise, add the size of the blocks between this block and the
226 // dest to the number of bytes left in this block.
227 unsigned StartBlock = Src->getNumber();
228 BranchSize = BlockSizes[StartBlock].first - BrOffset;
229
230 MaxAlign = std::max(a: MaxAlign, b: Dest->getAlignment());
231 for (unsigned i = StartBlock+1, e = Dest->getNumber(); i != e; ++i) {
232 BranchSize += BlockSizes[i].first;
233 MaxAlign = std::max(a: MaxAlign, b: Fn.getBlockNumbered(N: i)->getAlignment());
234 }
235
236 NeedExtraAdjustment = (FirstImpreciseBlock >= 0) &&
237 (Src->getNumber() >= FirstImpreciseBlock);
238 }
239
240 // We tend to over estimate code size due to large alignment and
241 // inline assembly. Usually it causes larger computed branch offset.
242 // But sometimes it may also causes smaller computed branch offset
243 // than actual branch offset. If the offset is close to the limit of
244 // encoding, it may cause problem at run time.
245 // Following is a simplified example.
246 //
247 // actual estimated
248 // address address
249 // ...
250 // bne Far 100 10c
251 // .p2align 4
252 // Near: 110 110
253 // ...
254 // Far: 8108 8108
255 //
256 // Actual offset: 0x8108 - 0x100 = 0x8008
257 // Computed offset: 0x8108 - 0x10c = 0x7ffc
258 //
259 // This example also shows when we can get the largest gap between
260 // estimated offset and actual offset. If there is an aligned block
261 // ABB between branch and target, assume its alignment is <align>
262 // bits. Now consider the accumulated function size FSIZE till the end
263 // of previous block PBB. If the estimated FSIZE is multiple of
264 // 2^<align>, we don't need any padding for the estimated address of
265 // ABB. If actual FSIZE at the end of PBB is 4 bytes more than
266 // multiple of 2^<align>, then we need (2^<align> - 4) bytes of
267 // padding. It also means the actual branch offset is (2^<align> - 4)
268 // larger than computed offset. Other actual FSIZE needs less padding
269 // bytes, so causes smaller gap between actual and computed offset.
270 //
271 // On the other hand, if the inline asm or large alignment occurs
272 // between the branch block and destination block, the estimated address
273 // can be <delta> larger than actual address. If padding bytes are
274 // needed for a later aligned block, the actual number of padding bytes
275 // is at most <delta> more than estimated padding bytes. So the actual
276 // aligned block address is less than or equal to the estimated aligned
277 // block address. So the actual branch offset is less than or equal to
278 // computed branch offset.
279 //
280 // The computed offset is at most ((1 << alignment) - 4) bytes smaller
281 // than actual offset. So we add this number to the offset for safety.
282 if (NeedExtraAdjustment)
283 BranchSize += MaxAlign.value() - 4;
284
285 return BranchSize;
286}
287
288bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
289 const PPCInstrInfo *TII =
290 static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
291 // Give the blocks of the function a dense, in-order, numbering.
292 Fn.RenumberBlocks();
293 BlockSizes.resize(new_size: Fn.getNumBlockIDs());
294 FirstImpreciseBlock = -1;
295
296 // Measure each MBB and compute a size for the entire function.
297 unsigned FuncSize = ComputeBlockSizes(Fn);
298
299 // If the entire function is smaller than the displacement of a branch field,
300 // we know we don't need to shrink any branches in this function. This is a
301 // common case.
302 if (FuncSize < (1 << 15)) {
303 BlockSizes.clear();
304 return false;
305 }
306
307 // For each conditional branch, if the offset to its destination is larger
308 // than the offset field allows, transform it into a long branch sequence
309 // like this:
310 // short branch:
311 // bCC MBB
312 // long branch:
313 // b!CC $PC+8
314 // b MBB
315 //
316 bool MadeChange = true;
317 bool EverMadeChange = false;
318 while (MadeChange) {
319 // Iteratively expand branches until we reach a fixed point.
320 MadeChange = false;
321
322 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
323 ++MFI) {
324 MachineBasicBlock &MBB = *MFI;
325 unsigned MBBStartOffset = 0;
326 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
327 I != E; ++I) {
328 MachineBasicBlock *Dest = nullptr;
329 if (I->getOpcode() == PPC::BCC && !I->getOperand(i: 2).isImm())
330 Dest = I->getOperand(i: 2).getMBB();
331 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) &&
332 !I->getOperand(i: 1).isImm())
333 Dest = I->getOperand(i: 1).getMBB();
334 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
335 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &&
336 !I->getOperand(i: 0).isImm())
337 Dest = I->getOperand(i: 0).getMBB();
338
339 if (!Dest) {
340 MBBStartOffset += TII->getInstSizeInBytes(MI: *I);
341 continue;
342 }
343
344 // Determine the offset from the current branch to the destination
345 // block.
346 int BranchSize = computeBranchSize(Fn, Src: &MBB, Dest, BrOffset: MBBStartOffset);
347
348 // If this branch is in range, ignore it.
349 if (isInt<16>(x: BranchSize)) {
350 MBBStartOffset += 4;
351 continue;
352 }
353
354 // Otherwise, we have to expand it to a long branch.
355 MachineInstr &OldBranch = *I;
356 DebugLoc dl = OldBranch.getDebugLoc();
357
358 if (I->getOpcode() == PPC::BCC) {
359 // The BCC operands are:
360 // 0. PPC branch predicate
361 // 1. CR register
362 // 2. Target MBB
363 PPC::Predicate Pred = (PPC::Predicate)I->getOperand(i: 0).getImm();
364 Register CRReg = I->getOperand(i: 1).getReg();
365
366 // Jump over the uncond branch inst (i.e. $PC+8) on opposite condition.
367 BuildMI(BB&: MBB, I, MIMD: dl, MCID: TII->get(Opcode: PPC::BCC))
368 .addImm(Val: PPC::InvertPredicate(Opcode: Pred)).addReg(RegNo: CRReg).addImm(Val: 2);
369 } else if (I->getOpcode() == PPC::BC) {
370 Register CRBit = I->getOperand(i: 0).getReg();
371 BuildMI(BB&: MBB, I, MIMD: dl, MCID: TII->get(Opcode: PPC::BCn)).addReg(RegNo: CRBit).addImm(Val: 2);
372 } else if (I->getOpcode() == PPC::BCn) {
373 Register CRBit = I->getOperand(i: 0).getReg();
374 BuildMI(BB&: MBB, I, MIMD: dl, MCID: TII->get(Opcode: PPC::BC)).addReg(RegNo: CRBit).addImm(Val: 2);
375 } else if (I->getOpcode() == PPC::BDNZ) {
376 BuildMI(BB&: MBB, I, MIMD: dl, MCID: TII->get(Opcode: PPC::BDZ)).addImm(Val: 2);
377 } else if (I->getOpcode() == PPC::BDNZ8) {
378 BuildMI(BB&: MBB, I, MIMD: dl, MCID: TII->get(Opcode: PPC::BDZ8)).addImm(Val: 2);
379 } else if (I->getOpcode() == PPC::BDZ) {
380 BuildMI(BB&: MBB, I, MIMD: dl, MCID: TII->get(Opcode: PPC::BDNZ)).addImm(Val: 2);
381 } else if (I->getOpcode() == PPC::BDZ8) {
382 BuildMI(BB&: MBB, I, MIMD: dl, MCID: TII->get(Opcode: PPC::BDNZ8)).addImm(Val: 2);
383 } else {
384 llvm_unreachable("Unhandled branch type!");
385 }
386
387 // Uncond branch to the real destination.
388 I = BuildMI(BB&: MBB, I, MIMD: dl, MCID: TII->get(Opcode: PPC::B)).addMBB(MBB: Dest);
389
390 // Remove the old branch from the function.
391 OldBranch.eraseFromParent();
392
393 // Remember that this instruction is 8-bytes, increase the size of the
394 // block by 4, remember to iterate.
395 BlockSizes[MBB.getNumber()].first += 4;
396 MBBStartOffset += 8;
397 ++NumExpanded;
398 MadeChange = true;
399 }
400 }
401
402 if (MadeChange) {
403 // If we're going to iterate again, make sure we've updated our
404 // padding-based contributions to the block sizes.
405 modifyAdjustment(Fn);
406 }
407
408 EverMadeChange |= MadeChange;
409 }
410
411 BlockSizes.clear();
412 return EverMadeChange;
413}
414