1//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15#define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16
17#include "MCTargetDesc/PPCMCTargetDesc.h"
18#include "llvm/ADT/DenseMap.h"
19
20#define GET_REGINFO_HEADER
21#include "PPCGenRegisterInfo.inc"
22
23namespace llvm {
24class PPCTargetMachine;
25
26inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27 unsigned Reg = 0;
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30 Reg = PPC::CR0;
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33 Reg = PPC::CR1;
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36 Reg = PPC::CR2;
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39 Reg = PPC::CR3;
40 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42 Reg = PPC::CR4;
43 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45 Reg = PPC::CR5;
46 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48 Reg = PPC::CR6;
49 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51 Reg = PPC::CR7;
52
53 assert(Reg != 0 && "Invalid CR bit register");
54 return Reg;
55}
56
57class PPCRegisterInfo : public PPCGenRegisterInfo {
58 DenseMap<unsigned, unsigned> ImmToIdxMap;
59 const PPCTargetMachine &TM;
60
61public:
62 PPCRegisterInfo(const PPCTargetMachine &TM);
63
64 /// getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode
65 /// for a given imm form load/store opcode \p ImmFormOpcode.
66 /// FIXME: move this to PPCInstrInfo class.
67 unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const {
68 if (!ImmToIdxMap.count(Val: ImmOpcode))
69 return PPC::INSTRUCTION_LIST_END;
70 return ImmToIdxMap.find(Val: ImmOpcode)->second;
71 }
72
73 /// getPointerRegClass - Return the register class to use to hold pointers.
74 /// This is used for addressing modes.
75 const TargetRegisterClass *
76 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
77
78 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
79 MachineFunction &MF) const override;
80
81 const TargetRegisterClass *
82 getLargestLegalSuperClass(const TargetRegisterClass *RC,
83 const MachineFunction &MF) const override;
84
85 /// Code Generation virtual methods...
86 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
87 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
88 CallingConv::ID CC) const override;
89 const uint32_t *getNoPreservedMask() const override;
90
91 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
92
93 BitVector getReservedRegs(const MachineFunction &MF) const override;
94 bool isAsmClobberable(const MachineFunction &MF,
95 MCRegister PhysReg) const override;
96 bool isCallerPreservedPhysReg(MCRegister PhysReg,
97 const MachineFunction &MF) const override;
98
99 // Provide hints to the register allocator for allocating subregisters
100 // of primed and unprimed accumulators. For example, if accumulator
101 // ACC5 is assigned, we also want to assign UACC5 to the input.
102 // Similarly if UACC5 is assigned, we want to assign VSRp10, VSRp11
103 // to its inputs.
104 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
105 SmallVectorImpl<MCPhysReg> &Hints,
106 const MachineFunction &MF, const VirtRegMap *VRM,
107 const LiveRegMatrix *Matrix) const override;
108
109 /// We require the register scavenger.
110 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
111 return true;
112 }
113
114 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
115
116 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
117
118 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
119 void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const;
120 void prepareDynamicAlloca(MachineBasicBlock::iterator II,
121 Register &NegSizeReg, bool &KillNegSizeReg,
122 Register &FramePointer) const;
123 void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const;
124 void lowerCRSpilling(MachineBasicBlock::iterator II,
125 unsigned FrameIndex) const;
126 void lowerCRRestore(MachineBasicBlock::iterator II,
127 unsigned FrameIndex) const;
128 void lowerCRBitSpilling(MachineBasicBlock::iterator II,
129 unsigned FrameIndex) const;
130 void lowerCRBitRestore(MachineBasicBlock::iterator II,
131 unsigned FrameIndex) const;
132
133 void lowerOctWordSpilling(MachineBasicBlock::iterator II,
134 unsigned FrameIndex) const;
135 void lowerACCSpilling(MachineBasicBlock::iterator II,
136 unsigned FrameIndex) const;
137 void lowerACCRestore(MachineBasicBlock::iterator II,
138 unsigned FrameIndex) const;
139
140 void lowerWACCSpilling(MachineBasicBlock::iterator II,
141 unsigned FrameIndex) const;
142 void lowerWACCRestore(MachineBasicBlock::iterator II,
143 unsigned FrameIndex) const;
144
145 void lowerQuadwordSpilling(MachineBasicBlock::iterator II,
146 unsigned FrameIndex) const;
147 void lowerQuadwordRestore(MachineBasicBlock::iterator II,
148 unsigned FrameIndex) const;
149
150 static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg,
151 MCRegister SrcReg);
152
153 bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
154 int &FrameIdx) const override;
155 bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
156 unsigned FIOperandNum,
157 RegScavenger *RS = nullptr) const override;
158
159 // Support for virtual base registers.
160 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
161 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
162 int64_t Offset) const override;
163 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
164 int64_t Offset) const override;
165 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
166 int64_t Offset) const override;
167
168 // Debug information queries.
169 Register getFrameRegister(const MachineFunction &MF) const override;
170
171 // Base pointer (stack realignment) support.
172 Register getBaseRegister(const MachineFunction &MF) const;
173 bool hasBasePointer(const MachineFunction &MF) const;
174
175 bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override {
176 return Reg == PPC::LR || Reg == PPC::LR8;
177 }
178};
179
180} // end namespace llvm
181
182#endif
183