| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Assembly Writer Source Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* From: AArch64.td *| |
| 7 | |* *| |
| 8 | \*===----------------------------------------------------------------------===*/ |
| 9 | |
| 10 | /// getMnemonic - This method is automatically generated by tablegen |
| 11 | /// from the instruction set description. |
| 12 | std::pair<const char *, uint64_t> |
| 13 | AArch64InstPrinter::getMnemonic(const MCInst &MI) const { |
| 14 | |
| 15 | #ifdef __GNUC__ |
| 16 | #pragma GCC diagnostic push |
| 17 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 18 | #endif |
| 19 | static const char AsmStrs[] = { |
| 20 | /* 0 */ "sha1su0\t\000" |
| 21 | /* 9 */ "sha512su0\t\000" |
| 22 | /* 20 */ "sha256su0\t\000" |
| 23 | /* 31 */ "st64bv0\t\000" |
| 24 | /* 40 */ "ld1\t\000" |
| 25 | /* 45 */ "stl1\t\000" |
| 26 | /* 51 */ "trn1\t\000" |
| 27 | /* 57 */ "ldap1\t\000" |
| 28 | /* 64 */ "zip1\t\000" |
| 29 | /* 70 */ "uzp1\t\000" |
| 30 | /* 76 */ "zipq1\t\000" |
| 31 | /* 83 */ "uzpq1\t\000" |
| 32 | /* 90 */ "dcps1\t\000" |
| 33 | /* 97 */ "sm3ss1\t\000" |
| 34 | /* 105 */ "gcsss1\t\000" |
| 35 | /* 113 */ "st1\t\000" |
| 36 | /* 118 */ "sha1su1\t\000" |
| 37 | /* 127 */ "sha512su1\t\000" |
| 38 | /* 138 */ "sha256su1\t\000" |
| 39 | /* 149 */ "sm3partw1\t\000" |
| 40 | /* 160 */ "rax1\t\000" |
| 41 | /* 166 */ "rev32\t\000" |
| 42 | /* 173 */ "ld2\t\000" |
| 43 | /* 178 */ "sha512h2\t\000" |
| 44 | /* 188 */ "sha256h2\t\000" |
| 45 | /* 198 */ "luti2\t\000" |
| 46 | /* 205 */ "sabal2\t\000" |
| 47 | /* 213 */ "uabal2\t\000" |
| 48 | /* 221 */ "sqdmlal2\t\000" |
| 49 | /* 231 */ "fmlal2\t\000" |
| 50 | /* 239 */ "smlal2\t\000" |
| 51 | /* 247 */ "umlal2\t\000" |
| 52 | /* 255 */ "ssubl2\t\000" |
| 53 | /* 263 */ "usubl2\t\000" |
| 54 | /* 271 */ "sabdl2\t\000" |
| 55 | /* 279 */ "uabdl2\t\000" |
| 56 | /* 287 */ "saddl2\t\000" |
| 57 | /* 295 */ "uaddl2\t\000" |
| 58 | /* 303 */ "sshll2\t\000" |
| 59 | /* 311 */ "ushll2\t\000" |
| 60 | /* 319 */ "sqdmull2\t\000" |
| 61 | /* 329 */ "pmull2\t\000" |
| 62 | /* 337 */ "smull2\t\000" |
| 63 | /* 345 */ "umull2\t\000" |
| 64 | /* 353 */ "sqdmlsl2\t\000" |
| 65 | /* 363 */ "fmlsl2\t\000" |
| 66 | /* 371 */ "smlsl2\t\000" |
| 67 | /* 379 */ "umlsl2\t\000" |
| 68 | /* 387 */ "bf1cvtl2\t\000" |
| 69 | /* 397 */ "bf2cvtl2\t\000" |
| 70 | /* 407 */ "fcvtl2\t\000" |
| 71 | /* 415 */ "rsubhn2\t\000" |
| 72 | /* 424 */ "raddhn2\t\000" |
| 73 | /* 433 */ "sqshrn2\t\000" |
| 74 | /* 442 */ "uqshrn2\t\000" |
| 75 | /* 451 */ "sqrshrn2\t\000" |
| 76 | /* 461 */ "uqrshrn2\t\000" |
| 77 | /* 471 */ "trn2\t\000" |
| 78 | /* 477 */ "bfcvtn2\t\000" |
| 79 | /* 486 */ "sqxtn2\t\000" |
| 80 | /* 494 */ "uqxtn2\t\000" |
| 81 | /* 502 */ "sqshrun2\t\000" |
| 82 | /* 512 */ "sqrshrun2\t\000" |
| 83 | /* 523 */ "sqxtun2\t\000" |
| 84 | /* 532 */ "fcvtxn2\t\000" |
| 85 | /* 541 */ "zip2\t\000" |
| 86 | /* 547 */ "uzp2\t\000" |
| 87 | /* 553 */ "zipq2\t\000" |
| 88 | /* 560 */ "uzpq2\t\000" |
| 89 | /* 567 */ "dcps2\t\000" |
| 90 | /* 574 */ "gcsss2\t\000" |
| 91 | /* 582 */ "st2\t\000" |
| 92 | /* 587 */ "ssubw2\t\000" |
| 93 | /* 595 */ "usubw2\t\000" |
| 94 | /* 603 */ "saddw2\t\000" |
| 95 | /* 611 */ "uaddw2\t\000" |
| 96 | /* 619 */ "sm3partw2\t\000" |
| 97 | /* 630 */ "ld3\t\000" |
| 98 | /* 635 */ "eor3\t\000" |
| 99 | /* 641 */ "dcps3\t\000" |
| 100 | /* 648 */ "st3\t\000" |
| 101 | /* 653 */ "rev64\t\000" |
| 102 | /* 660 */ "ld4\t\000" |
| 103 | /* 665 */ "luti4\t\000" |
| 104 | /* 672 */ "st4\t\000" |
| 105 | /* 677 */ "setf16\t\000" |
| 106 | /* 685 */ "rev16\t\000" |
| 107 | /* 692 */ "luti6\t\000" |
| 108 | /* 699 */ "setf8\t\000" |
| 109 | /* 706 */ "sm3tt1a\t\000" |
| 110 | /* 715 */ "sm3tt2a\t\000" |
| 111 | /* 724 */ "bfmop4a\t\000" |
| 112 | /* 733 */ "usmop4a\t\000" |
| 113 | /* 742 */ "sumop4a\t\000" |
| 114 | /* 751 */ "braa\t\000" |
| 115 | /* 757 */ "ldraa\t\000" |
| 116 | /* 764 */ "blraa\t\000" |
| 117 | /* 771 */ "saba\t\000" |
| 118 | /* 777 */ "uaba\t\000" |
| 119 | /* 783 */ "pacda\t\000" |
| 120 | /* 790 */ "ldadda\t\000" |
| 121 | /* 798 */ "ldbfadda\t\000" |
| 122 | /* 808 */ "ldfadda\t\000" |
| 123 | /* 817 */ "ldtadda\t\000" |
| 124 | /* 826 */ "autda\t\000" |
| 125 | /* 833 */ "pacga\t\000" |
| 126 | /* 840 */ "addha\t\000" |
| 127 | /* 847 */ "pacia\t\000" |
| 128 | /* 854 */ "autia\t\000" |
| 129 | /* 861 */ "brka\t\000" |
| 130 | /* 867 */ "fcmla\t\000" |
| 131 | /* 874 */ "bfmla\t\000" |
| 132 | /* 881 */ "bfmmla\t\000" |
| 133 | /* 889 */ "usmmla\t\000" |
| 134 | /* 897 */ "ummla\t\000" |
| 135 | /* 904 */ "fnmla\t\000" |
| 136 | /* 911 */ "ldbfminnma\t\000" |
| 137 | /* 923 */ "ldfminnma\t\000" |
| 138 | /* 934 */ "ldbfmaxnma\t\000" |
| 139 | /* 946 */ "ldfmaxnma\t\000" |
| 140 | /* 957 */ "ldbfmina\t\000" |
| 141 | /* 967 */ "ldfmina\t\000" |
| 142 | /* 976 */ "ldsmina\t\000" |
| 143 | /* 985 */ "ldumina\t\000" |
| 144 | /* 994 */ "brkpa\t\000" |
| 145 | /* 1001 */ "bmopa\t\000" |
| 146 | /* 1008 */ "bfmopa\t\000" |
| 147 | /* 1016 */ "usmopa\t\000" |
| 148 | /* 1024 */ "bftmopa\t\000" |
| 149 | /* 1033 */ "ustmopa\t\000" |
| 150 | /* 1042 */ "sutmopa\t\000" |
| 151 | /* 1051 */ "sumopa\t\000" |
| 152 | /* 1059 */ "rcwsswppa\t\000" |
| 153 | /* 1070 */ "rcwswppa\t\000" |
| 154 | /* 1080 */ "ldclrpa\t\000" |
| 155 | /* 1089 */ "rcwsclrpa\t\000" |
| 156 | /* 1100 */ "rcwclrpa\t\000" |
| 157 | /* 1110 */ "rcwscaspa\t\000" |
| 158 | /* 1121 */ "rcwcaspa\t\000" |
| 159 | /* 1131 */ "ldsetpa\t\000" |
| 160 | /* 1140 */ "rcwssetpa\t\000" |
| 161 | /* 1151 */ "rcwsetpa\t\000" |
| 162 | /* 1161 */ "rcwsswpa\t\000" |
| 163 | /* 1171 */ "rcwswpa\t\000" |
| 164 | /* 1180 */ "fexpa\t\000" |
| 165 | /* 1187 */ "ldclra\t\000" |
| 166 | /* 1195 */ "rcwsclra\t\000" |
| 167 | /* 1205 */ "ldtclra\t\000" |
| 168 | /* 1214 */ "rcwclra\t\000" |
| 169 | /* 1223 */ "ldeora\t\000" |
| 170 | /* 1231 */ "srsra\t\000" |
| 171 | /* 1238 */ "ursra\t\000" |
| 172 | /* 1245 */ "ssra\t\000" |
| 173 | /* 1251 */ "usra\t\000" |
| 174 | /* 1257 */ "rcwscasa\t\000" |
| 175 | /* 1267 */ "rcwcasa\t\000" |
| 176 | /* 1276 */ "ldseta\t\000" |
| 177 | /* 1284 */ "rcwsseta\t\000" |
| 178 | /* 1294 */ "ldtseta\t\000" |
| 179 | /* 1303 */ "rcwseta\t\000" |
| 180 | /* 1312 */ "frinta\t\000" |
| 181 | /* 1320 */ "swpta\t\000" |
| 182 | /* 1327 */ "clasta\t\000" |
| 183 | /* 1335 */ "addva\t\000" |
| 184 | /* 1342 */ "mova\t\000" |
| 185 | /* 1348 */ "ldbfmaxa\t\000" |
| 186 | /* 1358 */ "ldfmaxa\t\000" |
| 187 | /* 1367 */ "ldsmaxa\t\000" |
| 188 | /* 1376 */ "ldumaxa\t\000" |
| 189 | /* 1385 */ "pacdza\t\000" |
| 190 | /* 1393 */ "autdza\t\000" |
| 191 | /* 1401 */ "paciza\t\000" |
| 192 | /* 1409 */ "autiza\t\000" |
| 193 | /* 1417 */ "ld1b\t\000" |
| 194 | /* 1423 */ "ldff1b\t\000" |
| 195 | /* 1431 */ "ldnf1b\t\000" |
| 196 | /* 1439 */ "ldnt1b\t\000" |
| 197 | /* 1447 */ "stnt1b\t\000" |
| 198 | /* 1455 */ "st1b\t\000" |
| 199 | /* 1461 */ "sm3tt1b\t\000" |
| 200 | /* 1470 */ "crc32b\t\000" |
| 201 | /* 1478 */ "ld2b\t\000" |
| 202 | /* 1484 */ "st2b\t\000" |
| 203 | /* 1490 */ "sm3tt2b\t\000" |
| 204 | /* 1499 */ "ld3b\t\000" |
| 205 | /* 1505 */ "st3b\t\000" |
| 206 | /* 1511 */ "ld64b\t\000" |
| 207 | /* 1518 */ "st64b\t\000" |
| 208 | /* 1525 */ "ld4b\t\000" |
| 209 | /* 1531 */ "st4b\t\000" |
| 210 | /* 1537 */ "ldaddab\t\000" |
| 211 | /* 1546 */ "ldsminab\t\000" |
| 212 | /* 1556 */ "lduminab\t\000" |
| 213 | /* 1566 */ "swpab\t\000" |
| 214 | /* 1573 */ "brab\t\000" |
| 215 | /* 1579 */ "ldrab\t\000" |
| 216 | /* 1586 */ "blrab\t\000" |
| 217 | /* 1593 */ "ldclrab\t\000" |
| 218 | /* 1602 */ "ldeorab\t\000" |
| 219 | /* 1611 */ "casab\t\000" |
| 220 | /* 1618 */ "ldsetab\t\000" |
| 221 | /* 1627 */ "ldsmaxab\t\000" |
| 222 | /* 1637 */ "ldumaxab\t\000" |
| 223 | /* 1647 */ "fmlallbb\t\000" |
| 224 | /* 1657 */ "crc32cb\t\000" |
| 225 | /* 1666 */ "sqdecb\t\000" |
| 226 | /* 1674 */ "uqdecb\t\000" |
| 227 | /* 1682 */ "sqincb\t\000" |
| 228 | /* 1690 */ "uqincb\t\000" |
| 229 | /* 1698 */ "pacdb\t\000" |
| 230 | /* 1705 */ "ldaddb\t\000" |
| 231 | /* 1713 */ "autdb\t\000" |
| 232 | /* 1720 */ "tchangeb\t\000" |
| 233 | /* 1730 */ "prfb\t\000" |
| 234 | /* 1736 */ "flogb\t\000" |
| 235 | /* 1743 */ "pacib\t\000" |
| 236 | /* 1750 */ "autib\t\000" |
| 237 | /* 1757 */ "brkb\t\000" |
| 238 | /* 1763 */ "sabalb\t\000" |
| 239 | /* 1771 */ "uabalb\t\000" |
| 240 | /* 1779 */ "ldaddalb\t\000" |
| 241 | /* 1789 */ "sqdmlalb\t\000" |
| 242 | /* 1799 */ "bfmlalb\t\000" |
| 243 | /* 1808 */ "smlalb\t\000" |
| 244 | /* 1816 */ "umlalb\t\000" |
| 245 | /* 1824 */ "ldsminalb\t\000" |
| 246 | /* 1835 */ "lduminalb\t\000" |
| 247 | /* 1846 */ "swpalb\t\000" |
| 248 | /* 1854 */ "ldclralb\t\000" |
| 249 | /* 1864 */ "ldeoralb\t\000" |
| 250 | /* 1874 */ "casalb\t\000" |
| 251 | /* 1882 */ "ldsetalb\t\000" |
| 252 | /* 1892 */ "ldsmaxalb\t\000" |
| 253 | /* 1903 */ "ldumaxalb\t\000" |
| 254 | /* 1914 */ "ssublb\t\000" |
| 255 | /* 1922 */ "usublb\t\000" |
| 256 | /* 1930 */ "sbclb\t\000" |
| 257 | /* 1937 */ "adclb\t\000" |
| 258 | /* 1944 */ "sabdlb\t\000" |
| 259 | /* 1952 */ "uabdlb\t\000" |
| 260 | /* 1960 */ "ldaddlb\t\000" |
| 261 | /* 1969 */ "saddlb\t\000" |
| 262 | /* 1977 */ "uaddlb\t\000" |
| 263 | /* 1985 */ "sshllb\t\000" |
| 264 | /* 1993 */ "ushllb\t\000" |
| 265 | /* 2001 */ "sqdmullb\t\000" |
| 266 | /* 2011 */ "pmullb\t\000" |
| 267 | /* 2019 */ "smullb\t\000" |
| 268 | /* 2027 */ "umullb\t\000" |
| 269 | /* 2035 */ "ldsminlb\t\000" |
| 270 | /* 2045 */ "lduminlb\t\000" |
| 271 | /* 2055 */ "swplb\t\000" |
| 272 | /* 2062 */ "ldclrlb\t\000" |
| 273 | /* 2071 */ "ldeorlb\t\000" |
| 274 | /* 2080 */ "caslb\t\000" |
| 275 | /* 2087 */ "sqdmlslb\t\000" |
| 276 | /* 2097 */ "bfmlslb\t\000" |
| 277 | /* 2106 */ "smlslb\t\000" |
| 278 | /* 2114 */ "umlslb\t\000" |
| 279 | /* 2122 */ "ldsetlb\t\000" |
| 280 | /* 2131 */ "ldsmaxlb\t\000" |
| 281 | /* 2141 */ "ldumaxlb\t\000" |
| 282 | /* 2151 */ "dmb\t\000" |
| 283 | /* 2156 */ "rsubhnb\t\000" |
| 284 | /* 2165 */ "raddhnb\t\000" |
| 285 | /* 2174 */ "ldsminb\t\000" |
| 286 | /* 2183 */ "lduminb\t\000" |
| 287 | /* 2192 */ "sqshrnb\t\000" |
| 288 | /* 2201 */ "uqshrnb\t\000" |
| 289 | /* 2210 */ "sqrshrnb\t\000" |
| 290 | /* 2220 */ "uqrshrnb\t\000" |
| 291 | /* 2230 */ "fcvtnb\t\000" |
| 292 | /* 2238 */ "sqxtnb\t\000" |
| 293 | /* 2246 */ "uqxtnb\t\000" |
| 294 | /* 2254 */ "sqshrunb\t\000" |
| 295 | /* 2264 */ "sqrshrunb\t\000" |
| 296 | /* 2275 */ "sqxtunb\t\000" |
| 297 | /* 2284 */ "ld1rob\t\000" |
| 298 | /* 2292 */ "brkpb\t\000" |
| 299 | /* 2299 */ "swpb\t\000" |
| 300 | /* 2305 */ "ld1rqb\t\000" |
| 301 | /* 2313 */ "ld1rb\t\000" |
| 302 | /* 2320 */ "ldarb\t\000" |
| 303 | /* 2327 */ "ldlarb\t\000" |
| 304 | /* 2335 */ "ldrb\t\000" |
| 305 | /* 2341 */ "ldclrb\t\000" |
| 306 | /* 2349 */ "stllrb\t\000" |
| 307 | /* 2357 */ "stlrb\t\000" |
| 308 | /* 2364 */ "ldeorb\t\000" |
| 309 | /* 2372 */ "ldaprb\t\000" |
| 310 | /* 2380 */ "ldtrb\t\000" |
| 311 | /* 2387 */ "strb\t\000" |
| 312 | /* 2393 */ "sttrb\t\000" |
| 313 | /* 2400 */ "ldurb\t\000" |
| 314 | /* 2407 */ "stlurb\t\000" |
| 315 | /* 2415 */ "ldapurb\t\000" |
| 316 | /* 2424 */ "sturb\t\000" |
| 317 | /* 2431 */ "ldaxrb\t\000" |
| 318 | /* 2439 */ "ldxrb\t\000" |
| 319 | /* 2446 */ "stlxrb\t\000" |
| 320 | /* 2454 */ "stxrb\t\000" |
| 321 | /* 2461 */ "ld1sb\t\000" |
| 322 | /* 2468 */ "ldff1sb\t\000" |
| 323 | /* 2477 */ "ldnf1sb\t\000" |
| 324 | /* 2486 */ "ldnt1sb\t\000" |
| 325 | /* 2495 */ "casb\t\000" |
| 326 | /* 2501 */ "dsb\t\000" |
| 327 | /* 2506 */ "isb\t\000" |
| 328 | /* 2511 */ "fmsb\t\000" |
| 329 | /* 2517 */ "fnmsb\t\000" |
| 330 | /* 2524 */ "ld1rsb\t\000" |
| 331 | /* 2532 */ "ldrsb\t\000" |
| 332 | /* 2539 */ "ldtrsb\t\000" |
| 333 | /* 2547 */ "ldursb\t\000" |
| 334 | /* 2555 */ "ldapursb\t\000" |
| 335 | /* 2565 */ "tsb\t\000" |
| 336 | /* 2570 */ "ldsetb\t\000" |
| 337 | /* 2578 */ "ssubltb\t\000" |
| 338 | /* 2587 */ "fmlalltb\t\000" |
| 339 | /* 2597 */ "cntb\t\000" |
| 340 | /* 2603 */ "fvdotb\t\000" |
| 341 | /* 2611 */ "eortb\t\000" |
| 342 | /* 2618 */ "clastb\t\000" |
| 343 | /* 2626 */ "sxtb\t\000" |
| 344 | /* 2632 */ "uxtb\t\000" |
| 345 | /* 2638 */ "bfsub\t\000" |
| 346 | /* 2645 */ "shsub\t\000" |
| 347 | /* 2652 */ "uhsub\t\000" |
| 348 | /* 2659 */ "fmsub\t\000" |
| 349 | /* 2666 */ "fnmsub\t\000" |
| 350 | /* 2674 */ "sqsub\t\000" |
| 351 | /* 2681 */ "uqsub\t\000" |
| 352 | /* 2688 */ "revb\t\000" |
| 353 | /* 2694 */ "ssubwb\t\000" |
| 354 | /* 2702 */ "usubwb\t\000" |
| 355 | /* 2710 */ "saddwb\t\000" |
| 356 | /* 2718 */ "uaddwb\t\000" |
| 357 | /* 2726 */ "ldsmaxb\t\000" |
| 358 | /* 2735 */ "ldumaxb\t\000" |
| 359 | /* 2744 */ "pacdzb\t\000" |
| 360 | /* 2752 */ "autdzb\t\000" |
| 361 | /* 2760 */ "pacizb\t\000" |
| 362 | /* 2768 */ "autizb\t\000" |
| 363 | /* 2776 */ "sha1c\t\000" |
| 364 | /* 2783 */ "sbc\t\000" |
| 365 | /* 2788 */ "adc\t\000" |
| 366 | /* 2793 */ "bic\t\000" |
| 367 | /* 2798 */ "aesemc\t\000" |
| 368 | /* 2806 */ "aesdimc\t\000" |
| 369 | /* 2815 */ "aesimc\t\000" |
| 370 | /* 2823 */ "aesmc\t\000" |
| 371 | /* 2830 */ "csinc\t\000" |
| 372 | /* 2837 */ "retaasppc\t\000" |
| 373 | /* 2848 */ "autiasppc\t\000" |
| 374 | /* 2859 */ "retabsppc\t\000" |
| 375 | /* 2870 */ "autibsppc\t\000" |
| 376 | /* 2881 */ "hvc\t\000" |
| 377 | /* 2886 */ "svc\t\000" |
| 378 | /* 2891 */ "ld1d\t\000" |
| 379 | /* 2897 */ "ldff1d\t\000" |
| 380 | /* 2905 */ "ldnf1d\t\000" |
| 381 | /* 2913 */ "ldnt1d\t\000" |
| 382 | /* 2921 */ "stnt1d\t\000" |
| 383 | /* 2929 */ "st1d\t\000" |
| 384 | /* 2935 */ "ld2d\t\000" |
| 385 | /* 2941 */ "st2d\t\000" |
| 386 | /* 2947 */ "ld3d\t\000" |
| 387 | /* 2953 */ "st3d\t\000" |
| 388 | /* 2959 */ "ld4d\t\000" |
| 389 | /* 2965 */ "st4d\t\000" |
| 390 | /* 2971 */ "fmad\t\000" |
| 391 | /* 2977 */ "fnmad\t\000" |
| 392 | /* 2984 */ "ftmad\t\000" |
| 393 | /* 2991 */ "fabd\t\000" |
| 394 | /* 2997 */ "sabd\t\000" |
| 395 | /* 3003 */ "uabd\t\000" |
| 396 | /* 3009 */ "xpacd\t\000" |
| 397 | /* 3016 */ "sqdecd\t\000" |
| 398 | /* 3024 */ "uqdecd\t\000" |
| 399 | /* 3032 */ "sqincd\t\000" |
| 400 | /* 3040 */ "uqincd\t\000" |
| 401 | /* 3048 */ "fcadd\t\000" |
| 402 | /* 3055 */ "sqcadd\t\000" |
| 403 | /* 3063 */ "ldadd\t\000" |
| 404 | /* 3070 */ "ldbfadd\t\000" |
| 405 | /* 3079 */ "stbfadd\t\000" |
| 406 | /* 3088 */ "ldfadd\t\000" |
| 407 | /* 3096 */ "stfadd\t\000" |
| 408 | /* 3104 */ "srhadd\t\000" |
| 409 | /* 3112 */ "urhadd\t\000" |
| 410 | /* 3120 */ "shadd\t\000" |
| 411 | /* 3127 */ "uhadd\t\000" |
| 412 | /* 3134 */ "fmadd\t\000" |
| 413 | /* 3141 */ "fnmadd\t\000" |
| 414 | /* 3149 */ "usqadd\t\000" |
| 415 | /* 3157 */ "suqadd\t\000" |
| 416 | /* 3165 */ "ldtadd\t\000" |
| 417 | /* 3173 */ "prfd\t\000" |
| 418 | /* 3179 */ "nand\t\000" |
| 419 | /* 3185 */ "expand\t\000" |
| 420 | /* 3193 */ "ld1rod\t\000" |
| 421 | /* 3201 */ "ld1rqd\t\000" |
| 422 | /* 3209 */ "ld1rd\t\000" |
| 423 | /* 3216 */ "asrd\t\000" |
| 424 | /* 3222 */ "aesd\t\000" |
| 425 | /* 3228 */ "cntd\t\000" |
| 426 | /* 3234 */ "revd\t\000" |
| 427 | /* 3240 */ "sm4e\t\000" |
| 428 | /* 3246 */ "splice\t\000" |
| 429 | /* 3254 */ "cbbge\t\000" |
| 430 | /* 3261 */ "cbge\t\000" |
| 431 | /* 3267 */ "facge\t\000" |
| 432 | /* 3274 */ "whilege\t\000" |
| 433 | /* 3283 */ "cbhge\t\000" |
| 434 | /* 3290 */ "fcmge\t\000" |
| 435 | /* 3297 */ "cmpge\t\000" |
| 436 | /* 3304 */ "bfscale\t\000" |
| 437 | /* 3313 */ "whilele\t\000" |
| 438 | /* 3322 */ "fcmle\t\000" |
| 439 | /* 3329 */ "cmple\t\000" |
| 440 | /* 3336 */ "cbbne\t\000" |
| 441 | /* 3343 */ "cbne\t\000" |
| 442 | /* 3349 */ "cbhne\t\000" |
| 443 | /* 3356 */ "fcmne\t\000" |
| 444 | /* 3363 */ "ctermne\t\000" |
| 445 | /* 3372 */ "cmpne\t\000" |
| 446 | /* 3379 */ "frecpe\t\000" |
| 447 | /* 3387 */ "urecpe\t\000" |
| 448 | /* 3395 */ "fccmpe\t\000" |
| 449 | /* 3403 */ "fcmpe\t\000" |
| 450 | /* 3410 */ "aese\t\000" |
| 451 | /* 3416 */ "pfalse\t\000" |
| 452 | /* 3424 */ "frsqrte\t\000" |
| 453 | /* 3433 */ "ursqrte\t\000" |
| 454 | /* 3442 */ "ptrue\t\000" |
| 455 | /* 3449 */ "udf\t\000" |
| 456 | /* 3454 */ "tchangef\t\000" |
| 457 | /* 3464 */ "bif\t\000" |
| 458 | /* 3469 */ "rmif\t\000" |
| 459 | /* 3475 */ "scvtf\t\000" |
| 460 | /* 3482 */ "ucvtf\t\000" |
| 461 | /* 3489 */ "st2g\t\000" |
| 462 | /* 3495 */ "stz2g\t\000" |
| 463 | /* 3502 */ "subg\t\000" |
| 464 | /* 3508 */ "addg\t\000" |
| 465 | /* 3514 */ "ldg\t\000" |
| 466 | /* 3519 */ "fneg\t\000" |
| 467 | /* 3525 */ "sqneg\t\000" |
| 468 | /* 3532 */ "csneg\t\000" |
| 469 | /* 3539 */ "histseg\t\000" |
| 470 | /* 3548 */ "irg\t\000" |
| 471 | /* 3553 */ "stg\t\000" |
| 472 | /* 3558 */ "stzg\t\000" |
| 473 | /* 3564 */ "sha1h\t\000" |
| 474 | /* 3571 */ "ld1h\t\000" |
| 475 | /* 3577 */ "ldff1h\t\000" |
| 476 | /* 3585 */ "ldnf1h\t\000" |
| 477 | /* 3593 */ "ldnt1h\t\000" |
| 478 | /* 3601 */ "stnt1h\t\000" |
| 479 | /* 3609 */ "st1h\t\000" |
| 480 | /* 3615 */ "sha512h\t\000" |
| 481 | /* 3624 */ "crc32h\t\000" |
| 482 | /* 3632 */ "ld2h\t\000" |
| 483 | /* 3638 */ "st2h\t\000" |
| 484 | /* 3644 */ "ld3h\t\000" |
| 485 | /* 3650 */ "st3h\t\000" |
| 486 | /* 3656 */ "ld4h\t\000" |
| 487 | /* 3662 */ "st4h\t\000" |
| 488 | /* 3668 */ "sha256h\t\000" |
| 489 | /* 3677 */ "ldaddah\t\000" |
| 490 | /* 3686 */ "sqrdcmlah\t\000" |
| 491 | /* 3697 */ "sqrdmlah\t\000" |
| 492 | /* 3707 */ "ldsminah\t\000" |
| 493 | /* 3717 */ "lduminah\t\000" |
| 494 | /* 3727 */ "swpah\t\000" |
| 495 | /* 3734 */ "ldclrah\t\000" |
| 496 | /* 3743 */ "ldeorah\t\000" |
| 497 | /* 3752 */ "casah\t\000" |
| 498 | /* 3759 */ "ldsetah\t\000" |
| 499 | /* 3768 */ "ldsmaxah\t\000" |
| 500 | /* 3778 */ "ldumaxah\t\000" |
| 501 | /* 3788 */ "crc32ch\t\000" |
| 502 | /* 3797 */ "sqdech\t\000" |
| 503 | /* 3805 */ "uqdech\t\000" |
| 504 | /* 3813 */ "sqinch\t\000" |
| 505 | /* 3821 */ "uqinch\t\000" |
| 506 | /* 3829 */ "nmatch\t\000" |
| 507 | /* 3837 */ "ldaddh\t\000" |
| 508 | /* 3845 */ "prfh\t\000" |
| 509 | /* 3851 */ "stshh\t\000" |
| 510 | /* 3858 */ "ldaddalh\t\000" |
| 511 | /* 3868 */ "ldsminalh\t\000" |
| 512 | /* 3879 */ "lduminalh\t\000" |
| 513 | /* 3890 */ "swpalh\t\000" |
| 514 | /* 3898 */ "ldclralh\t\000" |
| 515 | /* 3908 */ "ldeoralh\t\000" |
| 516 | /* 3918 */ "casalh\t\000" |
| 517 | /* 3926 */ "ldsetalh\t\000" |
| 518 | /* 3936 */ "ldsmaxalh\t\000" |
| 519 | /* 3947 */ "ldumaxalh\t\000" |
| 520 | /* 3958 */ "ldaddlh\t\000" |
| 521 | /* 3967 */ "ldsminlh\t\000" |
| 522 | /* 3977 */ "lduminlh\t\000" |
| 523 | /* 3987 */ "swplh\t\000" |
| 524 | /* 3994 */ "ldclrlh\t\000" |
| 525 | /* 4003 */ "ldeorlh\t\000" |
| 526 | /* 4012 */ "caslh\t\000" |
| 527 | /* 4019 */ "ldsetlh\t\000" |
| 528 | /* 4028 */ "sqdmulh\t\000" |
| 529 | /* 4037 */ "sqrdmulh\t\000" |
| 530 | /* 4047 */ "smulh\t\000" |
| 531 | /* 4054 */ "umulh\t\000" |
| 532 | /* 4061 */ "ldsmaxlh\t\000" |
| 533 | /* 4071 */ "ldumaxlh\t\000" |
| 534 | /* 4081 */ "ldsminh\t\000" |
| 535 | /* 4090 */ "lduminh\t\000" |
| 536 | /* 4099 */ "ld1roh\t\000" |
| 537 | /* 4107 */ "swph\t\000" |
| 538 | /* 4113 */ "ld1rqh\t\000" |
| 539 | /* 4121 */ "ld1rh\t\000" |
| 540 | /* 4128 */ "ldarh\t\000" |
| 541 | /* 4135 */ "ldlarh\t\000" |
| 542 | /* 4143 */ "ldrh\t\000" |
| 543 | /* 4149 */ "ldclrh\t\000" |
| 544 | /* 4157 */ "stllrh\t\000" |
| 545 | /* 4165 */ "stlrh\t\000" |
| 546 | /* 4172 */ "ldeorh\t\000" |
| 547 | /* 4180 */ "ldaprh\t\000" |
| 548 | /* 4188 */ "ldtrh\t\000" |
| 549 | /* 4195 */ "strh\t\000" |
| 550 | /* 4201 */ "sttrh\t\000" |
| 551 | /* 4208 */ "ldurh\t\000" |
| 552 | /* 4215 */ "stlurh\t\000" |
| 553 | /* 4223 */ "ldapurh\t\000" |
| 554 | /* 4232 */ "sturh\t\000" |
| 555 | /* 4239 */ "ldaxrh\t\000" |
| 556 | /* 4247 */ "ldxrh\t\000" |
| 557 | /* 4254 */ "stlxrh\t\000" |
| 558 | /* 4262 */ "stxrh\t\000" |
| 559 | /* 4269 */ "ld1sh\t\000" |
| 560 | /* 4276 */ "ldff1sh\t\000" |
| 561 | /* 4285 */ "ldnf1sh\t\000" |
| 562 | /* 4294 */ "ldnt1sh\t\000" |
| 563 | /* 4303 */ "cash\t\000" |
| 564 | /* 4309 */ "sqrdmlsh\t\000" |
| 565 | /* 4319 */ "ld1rsh\t\000" |
| 566 | /* 4327 */ "ldrsh\t\000" |
| 567 | /* 4334 */ "ldtrsh\t\000" |
| 568 | /* 4342 */ "ldursh\t\000" |
| 569 | /* 4350 */ "ldapursh\t\000" |
| 570 | /* 4360 */ "ldseth\t\000" |
| 571 | /* 4368 */ "cnth\t\000" |
| 572 | /* 4374 */ "sxth\t\000" |
| 573 | /* 4380 */ "uxth\t\000" |
| 574 | /* 4386 */ "shuh\t\000" |
| 575 | /* 4392 */ "revh\t\000" |
| 576 | /* 4398 */ "ldsmaxh\t\000" |
| 577 | /* 4407 */ "ldumaxh\t\000" |
| 578 | /* 4416 */ "xpaci\t\000" |
| 579 | /* 4423 */ "cbbhi\t\000" |
| 580 | /* 4430 */ "cbhi\t\000" |
| 581 | /* 4436 */ "whilehi\t\000" |
| 582 | /* 4445 */ "cbhhi\t\000" |
| 583 | /* 4452 */ "punpkhi\t\000" |
| 584 | /* 4461 */ "sunpkhi\t\000" |
| 585 | /* 4470 */ "uunpkhi\t\000" |
| 586 | /* 4479 */ "cmhi\t\000" |
| 587 | /* 4485 */ "cmphi\t\000" |
| 588 | /* 4492 */ "sli\t\000" |
| 589 | /* 4497 */ "gmi\t\000" |
| 590 | /* 4502 */ "mvni\t\000" |
| 591 | /* 4508 */ "sri\t\000" |
| 592 | /* 4513 */ "frinti\t\000" |
| 593 | /* 4521 */ "movi\t\000" |
| 594 | /* 4527 */ "sunpk\t\000" |
| 595 | /* 4534 */ "uunpk\t\000" |
| 596 | /* 4541 */ "brk\t\000" |
| 597 | /* 4546 */ "movk\t\000" |
| 598 | /* 4552 */ "sabal\t\000" |
| 599 | /* 4559 */ "uabal\t\000" |
| 600 | /* 4566 */ "ldaddal\t\000" |
| 601 | /* 4575 */ "ldbfaddal\t\000" |
| 602 | /* 4586 */ "ldfaddal\t\000" |
| 603 | /* 4596 */ "ldtaddal\t\000" |
| 604 | /* 4606 */ "sqdmlal\t\000" |
| 605 | /* 4615 */ "bfmlal\t\000" |
| 606 | /* 4623 */ "pmlal\t\000" |
| 607 | /* 4630 */ "smlal\t\000" |
| 608 | /* 4637 */ "umlal\t\000" |
| 609 | /* 4644 */ "ldbfminnmal\t\000" |
| 610 | /* 4657 */ "ldfminnmal\t\000" |
| 611 | /* 4669 */ "ldbfmaxnmal\t\000" |
| 612 | /* 4682 */ "ldfmaxnmal\t\000" |
| 613 | /* 4694 */ "ldbfminal\t\000" |
| 614 | /* 4705 */ "ldfminal\t\000" |
| 615 | /* 4715 */ "ldsminal\t\000" |
| 616 | /* 4725 */ "lduminal\t\000" |
| 617 | /* 4735 */ "rcwsswppal\t\000" |
| 618 | /* 4747 */ "rcwswppal\t\000" |
| 619 | /* 4758 */ "ldclrpal\t\000" |
| 620 | /* 4768 */ "rcwsclrpal\t\000" |
| 621 | /* 4780 */ "rcwclrpal\t\000" |
| 622 | /* 4791 */ "rcwscaspal\t\000" |
| 623 | /* 4803 */ "rcwcaspal\t\000" |
| 624 | /* 4814 */ "ldsetpal\t\000" |
| 625 | /* 4824 */ "rcwssetpal\t\000" |
| 626 | /* 4836 */ "rcwsetpal\t\000" |
| 627 | /* 4847 */ "rcwsswpal\t\000" |
| 628 | /* 4858 */ "rcwswpal\t\000" |
| 629 | /* 4868 */ "ldclral\t\000" |
| 630 | /* 4877 */ "rcwsclral\t\000" |
| 631 | /* 4888 */ "ldtclral\t\000" |
| 632 | /* 4898 */ "rcwclral\t\000" |
| 633 | /* 4908 */ "ldeoral\t\000" |
| 634 | /* 4917 */ "rcwscasal\t\000" |
| 635 | /* 4928 */ "rcwcasal\t\000" |
| 636 | /* 4938 */ "ldsetal\t\000" |
| 637 | /* 4947 */ "rcwssetal\t\000" |
| 638 | /* 4958 */ "ldtsetal\t\000" |
| 639 | /* 4968 */ "rcwsetal\t\000" |
| 640 | /* 4978 */ "swptal\t\000" |
| 641 | /* 4986 */ "ldbfmaxal\t\000" |
| 642 | /* 4997 */ "ldfmaxal\t\000" |
| 643 | /* 5007 */ "ldsmaxal\t\000" |
| 644 | /* 5017 */ "ldumaxal\t\000" |
| 645 | /* 5027 */ "tbl\t\000" |
| 646 | /* 5032 */ "smsubl\t\000" |
| 647 | /* 5040 */ "umsubl\t\000" |
| 648 | /* 5048 */ "ssubl\t\000" |
| 649 | /* 5055 */ "usubl\t\000" |
| 650 | /* 5062 */ "sabdl\t\000" |
| 651 | /* 5069 */ "uabdl\t\000" |
| 652 | /* 5076 */ "ldaddl\t\000" |
| 653 | /* 5084 */ "ldbfaddl\t\000" |
| 654 | /* 5094 */ "stbfaddl\t\000" |
| 655 | /* 5104 */ "ldfaddl\t\000" |
| 656 | /* 5113 */ "stfaddl\t\000" |
| 657 | /* 5122 */ "smaddl\t\000" |
| 658 | /* 5130 */ "umaddl\t\000" |
| 659 | /* 5138 */ "saddl\t\000" |
| 660 | /* 5145 */ "ldtaddl\t\000" |
| 661 | /* 5154 */ "uaddl\t\000" |
| 662 | /* 5161 */ "fcsel\t\000" |
| 663 | /* 5168 */ "psel\t\000" |
| 664 | /* 5174 */ "ftssel\t\000" |
| 665 | /* 5182 */ "sqshl\t\000" |
| 666 | /* 5189 */ "uqshl\t\000" |
| 667 | /* 5196 */ "sqrshl\t\000" |
| 668 | /* 5204 */ "uqrshl\t\000" |
| 669 | /* 5212 */ "srshl\t\000" |
| 670 | /* 5219 */ "urshl\t\000" |
| 671 | /* 5226 */ "sshl\t\000" |
| 672 | /* 5232 */ "ushl\t\000" |
| 673 | /* 5238 */ "fmlall\t\000" |
| 674 | /* 5246 */ "usmlall\t\000" |
| 675 | /* 5255 */ "sumlall\t\000" |
| 676 | /* 5264 */ "sshll\t\000" |
| 677 | /* 5271 */ "ushll\t\000" |
| 678 | /* 5278 */ "smlsll\t\000" |
| 679 | /* 5286 */ "umlsll\t\000" |
| 680 | /* 5294 */ "sqdmull\t\000" |
| 681 | /* 5303 */ "pmull\t\000" |
| 682 | /* 5310 */ "smull\t\000" |
| 683 | /* 5317 */ "umull\t\000" |
| 684 | /* 5324 */ "ldbfminnml\t\000" |
| 685 | /* 5336 */ "stbfminnml\t\000" |
| 686 | /* 5348 */ "ldfminnml\t\000" |
| 687 | /* 5359 */ "stfminnml\t\000" |
| 688 | /* 5370 */ "ldbfmaxnml\t\000" |
| 689 | /* 5382 */ "stbfmaxnml\t\000" |
| 690 | /* 5394 */ "ldfmaxnml\t\000" |
| 691 | /* 5405 */ "stfmaxnml\t\000" |
| 692 | /* 5416 */ "ldbfminl\t\000" |
| 693 | /* 5426 */ "stbfminl\t\000" |
| 694 | /* 5436 */ "ldfminl\t\000" |
| 695 | /* 5445 */ "stfminl\t\000" |
| 696 | /* 5454 */ "ldsminl\t\000" |
| 697 | /* 5463 */ "lduminl\t\000" |
| 698 | /* 5472 */ "addpl\t\000" |
| 699 | /* 5479 */ "rcwsswppl\t\000" |
| 700 | /* 5490 */ "rcwswppl\t\000" |
| 701 | /* 5500 */ "ldclrpl\t\000" |
| 702 | /* 5509 */ "rcwsclrpl\t\000" |
| 703 | /* 5520 */ "rcwclrpl\t\000" |
| 704 | /* 5530 */ "rcwscaspl\t\000" |
| 705 | /* 5541 */ "rcwcaspl\t\000" |
| 706 | /* 5551 */ "addspl\t\000" |
| 707 | /* 5559 */ "ldsetpl\t\000" |
| 708 | /* 5568 */ "rcwssetpl\t\000" |
| 709 | /* 5579 */ "rcwsetpl\t\000" |
| 710 | /* 5589 */ "rcwsswpl\t\000" |
| 711 | /* 5599 */ "rcwswpl\t\000" |
| 712 | /* 5608 */ "ldclrl\t\000" |
| 713 | /* 5616 */ "rcwsclrl\t\000" |
| 714 | /* 5626 */ "ldtclrl\t\000" |
| 715 | /* 5635 */ "rcwclrl\t\000" |
| 716 | /* 5644 */ "ldeorl\t\000" |
| 717 | /* 5652 */ "rcwscasl\t\000" |
| 718 | /* 5662 */ "rcwcasl\t\000" |
| 719 | /* 5671 */ "nbsl\t\000" |
| 720 | /* 5677 */ "sqdmlsl\t\000" |
| 721 | /* 5686 */ "bfmlsl\t\000" |
| 722 | /* 5694 */ "smlsl\t\000" |
| 723 | /* 5701 */ "umlsl\t\000" |
| 724 | /* 5708 */ "sysl\t\000" |
| 725 | /* 5714 */ "ldsetl\t\000" |
| 726 | /* 5722 */ "rcwssetl\t\000" |
| 727 | /* 5732 */ "ldtsetl\t\000" |
| 728 | /* 5741 */ "rcwsetl\t\000" |
| 729 | /* 5750 */ "swptl\t\000" |
| 730 | /* 5757 */ "bf1cvtl\t\000" |
| 731 | /* 5766 */ "bf2cvtl\t\000" |
| 732 | /* 5775 */ "fcvtl\t\000" |
| 733 | /* 5782 */ "bfmul\t\000" |
| 734 | /* 5789 */ "fnmul\t\000" |
| 735 | /* 5796 */ "pmul\t\000" |
| 736 | /* 5802 */ "ftsmul\t\000" |
| 737 | /* 5810 */ "addvl\t\000" |
| 738 | /* 5817 */ "rdvl\t\000" |
| 739 | /* 5823 */ "addsvl\t\000" |
| 740 | /* 5831 */ "rdsvl\t\000" |
| 741 | /* 5838 */ "ldbfmaxl\t\000" |
| 742 | /* 5848 */ "stbfmaxl\t\000" |
| 743 | /* 5858 */ "ldfmaxl\t\000" |
| 744 | /* 5867 */ "stfmaxl\t\000" |
| 745 | /* 5876 */ "ldsmaxl\t\000" |
| 746 | /* 5885 */ "ldumaxl\t\000" |
| 747 | /* 5894 */ "sha1m\t\000" |
| 748 | /* 5901 */ "sbfm\t\000" |
| 749 | /* 5907 */ "ubfm\t\000" |
| 750 | /* 5913 */ "rprfm\t\000" |
| 751 | /* 5920 */ "ldgm\t\000" |
| 752 | /* 5926 */ "stgm\t\000" |
| 753 | /* 5932 */ "stzgm\t\000" |
| 754 | /* 5939 */ "gcspushm\t\000" |
| 755 | /* 5949 */ "ldbfminnm\t\000" |
| 756 | /* 5960 */ "stbfminnm\t\000" |
| 757 | /* 5971 */ "ldfminnm\t\000" |
| 758 | /* 5981 */ "stfminnm\t\000" |
| 759 | /* 5991 */ "ldbfmaxnm\t\000" |
| 760 | /* 6002 */ "stbfmaxnm\t\000" |
| 761 | /* 6013 */ "ldfmaxnm\t\000" |
| 762 | /* 6023 */ "stfmaxnm\t\000" |
| 763 | /* 6033 */ "gcspopm\t\000" |
| 764 | /* 6042 */ "dupm\t\000" |
| 765 | /* 6048 */ "frintm\t\000" |
| 766 | /* 6056 */ "prfum\t\000" |
| 767 | /* 6063 */ "bsl1n\t\000" |
| 768 | /* 6070 */ "bsl2n\t\000" |
| 769 | /* 6077 */ "rsubhn\t\000" |
| 770 | /* 6085 */ "raddhn\t\000" |
| 771 | /* 6093 */ "famin\t\000" |
| 772 | /* 6100 */ "ldbfmin\t\000" |
| 773 | /* 6109 */ "stbfmin\t\000" |
| 774 | /* 6118 */ "ldfmin\t\000" |
| 775 | /* 6126 */ "stfmin\t\000" |
| 776 | /* 6134 */ "ldsmin\t\000" |
| 777 | /* 6142 */ "ldumin\t\000" |
| 778 | /* 6150 */ "brkn\t\000" |
| 779 | /* 6156 */ "ccmn\t\000" |
| 780 | /* 6162 */ "eon\t\000" |
| 781 | /* 6167 */ "sqshrn\t\000" |
| 782 | /* 6175 */ "uqshrn\t\000" |
| 783 | /* 6183 */ "sqrshrn\t\000" |
| 784 | /* 6192 */ "uqrshrn\t\000" |
| 785 | /* 6201 */ "orn\t\000" |
| 786 | /* 6206 */ "fcvtzsn\t\000" |
| 787 | /* 6215 */ "frintn\t\000" |
| 788 | /* 6223 */ "bfcvtn\t\000" |
| 789 | /* 6231 */ "sqcvtn\t\000" |
| 790 | /* 6239 */ "uqcvtn\t\000" |
| 791 | /* 6247 */ "sqxtn\t\000" |
| 792 | /* 6254 */ "uqxtn\t\000" |
| 793 | /* 6261 */ "sqshrun\t\000" |
| 794 | /* 6270 */ "sqrshrun\t\000" |
| 795 | /* 6280 */ "sqcvtun\t\000" |
| 796 | /* 6289 */ "sqxtun\t\000" |
| 797 | /* 6297 */ "fcvtzun\t\000" |
| 798 | /* 6306 */ "movn\t\000" |
| 799 | /* 6312 */ "fcvtxn\t\000" |
| 800 | /* 6320 */ "cblo\t\000" |
| 801 | /* 6326 */ "whilelo\t\000" |
| 802 | /* 6335 */ "punpklo\t\000" |
| 803 | /* 6344 */ "sunpklo\t\000" |
| 804 | /* 6353 */ "uunpklo\t\000" |
| 805 | /* 6362 */ "cmplo\t\000" |
| 806 | /* 6369 */ "zero\t\000" |
| 807 | /* 6375 */ "fcmuo\t\000" |
| 808 | /* 6382 */ "sha1p\t\000" |
| 809 | /* 6389 */ "ldap\t\000" |
| 810 | /* 6395 */ "addsubp\t\000" |
| 811 | /* 6404 */ "sqdecp\t\000" |
| 812 | /* 6412 */ "uqdecp\t\000" |
| 813 | /* 6420 */ "sqincp\t\000" |
| 814 | /* 6428 */ "uqincp\t\000" |
| 815 | /* 6436 */ "faddp\t\000" |
| 816 | /* 6443 */ "ldp\t\000" |
| 817 | /* 6448 */ "bdep\t\000" |
| 818 | /* 6454 */ "stgp\t\000" |
| 819 | /* 6460 */ "zip\t\000" |
| 820 | /* 6465 */ "sadalp\t\000" |
| 821 | /* 6473 */ "uadalp\t\000" |
| 822 | /* 6481 */ "saddlp\t\000" |
| 823 | /* 6489 */ "uaddlp\t\000" |
| 824 | /* 6497 */ "stilp\t\000" |
| 825 | /* 6504 */ "stlp\t\000" |
| 826 | /* 6510 */ "bfclamp\t\000" |
| 827 | /* 6519 */ "sclamp\t\000" |
| 828 | /* 6527 */ "uclamp\t\000" |
| 829 | /* 6535 */ "fccmp\t\000" |
| 830 | /* 6542 */ "fcmp\t\000" |
| 831 | /* 6548 */ "fminnmp\t\000" |
| 832 | /* 6557 */ "fmaxnmp\t\000" |
| 833 | /* 6566 */ "ldnp\t\000" |
| 834 | /* 6572 */ "fminp\t\000" |
| 835 | /* 6579 */ "sminp\t\000" |
| 836 | /* 6586 */ "uminp\t\000" |
| 837 | /* 6593 */ "ldtnp\t\000" |
| 838 | /* 6600 */ "stnp\t\000" |
| 839 | /* 6606 */ "sttnp\t\000" |
| 840 | /* 6613 */ "ldapp\t\000" |
| 841 | /* 6620 */ "ldiapp\t\000" |
| 842 | /* 6628 */ "rcwsswpp\t\000" |
| 843 | /* 6638 */ "rcwswpp\t\000" |
| 844 | /* 6647 */ "addqp\t\000" |
| 845 | /* 6654 */ "adrp\t\000" |
| 846 | /* 6660 */ "bgrp\t\000" |
| 847 | /* 6666 */ "ldclrp\t\000" |
| 848 | /* 6674 */ "rcwsclrp\t\000" |
| 849 | /* 6684 */ "rcwclrp\t\000" |
| 850 | /* 6693 */ "rcwscasp\t\000" |
| 851 | /* 6703 */ "rcwcasp\t\000" |
| 852 | /* 6712 */ "sysp\t\000" |
| 853 | /* 6718 */ "ldtp\t\000" |
| 854 | /* 6724 */ "ldsetp\t\000" |
| 855 | /* 6732 */ "rcwssetp\t\000" |
| 856 | /* 6742 */ "rcwsetp\t\000" |
| 857 | /* 6751 */ "cntp\t\000" |
| 858 | /* 6757 */ "frintp\t\000" |
| 859 | /* 6765 */ "lastp\t\000" |
| 860 | /* 6772 */ "firstp\t\000" |
| 861 | /* 6780 */ "sttp\t\000" |
| 862 | /* 6786 */ "fdup\t\000" |
| 863 | /* 6792 */ "rcwsswp\t\000" |
| 864 | /* 6801 */ "rcwswp\t\000" |
| 865 | /* 6809 */ "ldaxp\t\000" |
| 866 | /* 6816 */ "fmaxp\t\000" |
| 867 | /* 6823 */ "smaxp\t\000" |
| 868 | /* 6830 */ "umaxp\t\000" |
| 869 | /* 6837 */ "ldxp\t\000" |
| 870 | /* 6843 */ "stlxp\t\000" |
| 871 | /* 6850 */ "stxp\t\000" |
| 872 | /* 6856 */ "uzp\t\000" |
| 873 | /* 6861 */ "ld1q\t\000" |
| 874 | /* 6867 */ "st1q\t\000" |
| 875 | /* 6873 */ "ld2q\t\000" |
| 876 | /* 6879 */ "st2q\t\000" |
| 877 | /* 6885 */ "ld3q\t\000" |
| 878 | /* 6891 */ "st3q\t\000" |
| 879 | /* 6897 */ "ld4q\t\000" |
| 880 | /* 6903 */ "st4q\t\000" |
| 881 | /* 6909 */ "cbbeq\t\000" |
| 882 | /* 6916 */ "cbeq\t\000" |
| 883 | /* 6922 */ "cbheq\t\000" |
| 884 | /* 6929 */ "fcmeq\t\000" |
| 885 | /* 6936 */ "ctermeq\t\000" |
| 886 | /* 6945 */ "cmpeq\t\000" |
| 887 | /* 6952 */ "tblq\t\000" |
| 888 | /* 6958 */ "dupq\t\000" |
| 889 | /* 6964 */ "extq\t\000" |
| 890 | /* 6970 */ "tbxq\t\000" |
| 891 | /* 6976 */ "ld1r\t\000" |
| 892 | /* 6982 */ "ld2r\t\000" |
| 893 | /* 6988 */ "ld3r\t\000" |
| 894 | /* 6994 */ "ld4r\t\000" |
| 895 | /* 7000 */ "ldar\t\000" |
| 896 | /* 7006 */ "ldlar\t\000" |
| 897 | /* 7013 */ "xar\t\000" |
| 898 | /* 7018 */ "fsubr\t\000" |
| 899 | /* 7025 */ "shsubr\t\000" |
| 900 | /* 7033 */ "uhsubr\t\000" |
| 901 | /* 7041 */ "sqsubr\t\000" |
| 902 | /* 7049 */ "uqsubr\t\000" |
| 903 | /* 7057 */ "retaasppcr\t\000" |
| 904 | /* 7069 */ "autiasppcr\t\000" |
| 905 | /* 7081 */ "retabsppcr\t\000" |
| 906 | /* 7093 */ "autibsppcr\t\000" |
| 907 | /* 7105 */ "adr\t\000" |
| 908 | /* 7110 */ "ldr\t\000" |
| 909 | /* 7115 */ "tenter\t\000" |
| 910 | /* 7123 */ "rdffr\t\000" |
| 911 | /* 7130 */ "wrffr\t\000" |
| 912 | /* 7137 */ "sqrshr\t\000" |
| 913 | /* 7145 */ "uqrshr\t\000" |
| 914 | /* 7153 */ "srshr\t\000" |
| 915 | /* 7160 */ "urshr\t\000" |
| 916 | /* 7167 */ "sshr\t\000" |
| 917 | /* 7173 */ "ushr\t\000" |
| 918 | /* 7179 */ "blr\t\000" |
| 919 | /* 7184 */ "ldclr\t\000" |
| 920 | /* 7191 */ "rcwsclr\t\000" |
| 921 | /* 7200 */ "ldtclr\t\000" |
| 922 | /* 7208 */ "rcwclr\t\000" |
| 923 | /* 7216 */ "sqshlr\t\000" |
| 924 | /* 7224 */ "uqshlr\t\000" |
| 925 | /* 7232 */ "sqrshlr\t\000" |
| 926 | /* 7241 */ "uqrshlr\t\000" |
| 927 | /* 7250 */ "srshlr\t\000" |
| 928 | /* 7258 */ "urshlr\t\000" |
| 929 | /* 7266 */ "stllr\t\000" |
| 930 | /* 7273 */ "lslr\t\000" |
| 931 | /* 7279 */ "stlr\t\000" |
| 932 | /* 7285 */ "ldeor\t\000" |
| 933 | /* 7292 */ "nor\t\000" |
| 934 | /* 7297 */ "ror\t\000" |
| 935 | /* 7302 */ "ldapr\t\000" |
| 936 | /* 7309 */ "orr\t\000" |
| 937 | /* 7314 */ "asrr\t\000" |
| 938 | /* 7320 */ "lsrr\t\000" |
| 939 | /* 7326 */ "msrr\t\000" |
| 940 | /* 7332 */ "asr\t\000" |
| 941 | /* 7337 */ "lsr\t\000" |
| 942 | /* 7342 */ "msr\t\000" |
| 943 | /* 7347 */ "insr\t\000" |
| 944 | /* 7353 */ "ldtr\t\000" |
| 945 | /* 7359 */ "gcsstr\t\000" |
| 946 | /* 7367 */ "gcssttr\t\000" |
| 947 | /* 7376 */ "extr\t\000" |
| 948 | /* 7382 */ "ldur\t\000" |
| 949 | /* 7388 */ "stlur\t\000" |
| 950 | /* 7395 */ "ldapur\t\000" |
| 951 | /* 7403 */ "stur\t\000" |
| 952 | /* 7409 */ "fdivr\t\000" |
| 953 | /* 7416 */ "sdivr\t\000" |
| 954 | /* 7423 */ "udivr\t\000" |
| 955 | /* 7430 */ "whilewr\t\000" |
| 956 | /* 7439 */ "ldaxr\t\000" |
| 957 | /* 7446 */ "ldxr\t\000" |
| 958 | /* 7452 */ "stlxr\t\000" |
| 959 | /* 7459 */ "ldatxr\t\000" |
| 960 | /* 7467 */ "ldtxr\t\000" |
| 961 | /* 7474 */ "stltxr\t\000" |
| 962 | /* 7482 */ "stxr\t\000" |
| 963 | /* 7488 */ "sttxr\t\000" |
| 964 | /* 7495 */ "bfmop4s\t\000" |
| 965 | /* 7504 */ "usmop4s\t\000" |
| 966 | /* 7513 */ "sumop4s\t\000" |
| 967 | /* 7522 */ "rcwscas\t\000" |
| 968 | /* 7531 */ "rcwcas\t\000" |
| 969 | /* 7539 */ "brkas\t\000" |
| 970 | /* 7546 */ "apas\t\000" |
| 971 | /* 7552 */ "brkpas\t\000" |
| 972 | /* 7560 */ "fcvtas\t\000" |
| 973 | /* 7568 */ "fabs\t\000" |
| 974 | /* 7574 */ "sqabs\t\000" |
| 975 | /* 7581 */ "brkbs\t\000" |
| 976 | /* 7588 */ "brkpbs\t\000" |
| 977 | /* 7596 */ "subs\t\000" |
| 978 | /* 7602 */ "sbcs\t\000" |
| 979 | /* 7608 */ "adcs\t\000" |
| 980 | /* 7614 */ "bics\t\000" |
| 981 | /* 7620 */ "adds\t\000" |
| 982 | /* 7626 */ "nands\t\000" |
| 983 | /* 7633 */ "ptrues\t\000" |
| 984 | /* 7641 */ "cbbhs\t\000" |
| 985 | /* 7648 */ "cbhs\t\000" |
| 986 | /* 7654 */ "whilehs\t\000" |
| 987 | /* 7663 */ "cbhhs\t\000" |
| 988 | /* 7670 */ "cmhs\t\000" |
| 989 | /* 7676 */ "cmphs\t\000" |
| 990 | /* 7683 */ "cls\t\000" |
| 991 | /* 7688 */ "whilels\t\000" |
| 992 | /* 7697 */ "bfmls\t\000" |
| 993 | /* 7704 */ "fnmls\t\000" |
| 994 | /* 7711 */ "cmpls\t\000" |
| 995 | /* 7718 */ "fcvtms\t\000" |
| 996 | /* 7726 */ "ins\t\000" |
| 997 | /* 7731 */ "brkns\t\000" |
| 998 | /* 7738 */ "orns\t\000" |
| 999 | /* 7744 */ "fcvtns\t\000" |
| 1000 | /* 7752 */ "subps\t\000" |
| 1001 | /* 7759 */ "frecps\t\000" |
| 1002 | /* 7767 */ "bmops\t\000" |
| 1003 | /* 7774 */ "bfmops\t\000" |
| 1004 | /* 7782 */ "usmops\t\000" |
| 1005 | /* 7790 */ "sumops\t\000" |
| 1006 | /* 7798 */ "fcvtps\t\000" |
| 1007 | /* 7806 */ "rdffrs\t\000" |
| 1008 | /* 7814 */ "mrs\t\000" |
| 1009 | /* 7819 */ "eors\t\000" |
| 1010 | /* 7825 */ "nors\t\000" |
| 1011 | /* 7831 */ "mrrs\t\000" |
| 1012 | /* 7837 */ "orrs\t\000" |
| 1013 | /* 7843 */ "frsqrts\t\000" |
| 1014 | /* 7852 */ "sys\t\000" |
| 1015 | /* 7857 */ "fcvtzs\t\000" |
| 1016 | /* 7865 */ "fjcvtzs\t\000" |
| 1017 | /* 7874 */ "caspat\t\000" |
| 1018 | /* 7882 */ "casat\t\000" |
| 1019 | /* 7889 */ "sqdmlalbt\t\000" |
| 1020 | /* 7900 */ "ssublbt\t\000" |
| 1021 | /* 7909 */ "saddlbt\t\000" |
| 1022 | /* 7918 */ "fmlallbt\t\000" |
| 1023 | /* 7928 */ "sqdmlslbt\t\000" |
| 1024 | /* 7939 */ "eorbt\t\000" |
| 1025 | /* 7946 */ "compact\t\000" |
| 1026 | /* 7955 */ "wfet\t\000" |
| 1027 | /* 7961 */ "ret\t\000" |
| 1028 | /* 7966 */ "ldset\t\000" |
| 1029 | /* 7973 */ "rcwsset\t\000" |
| 1030 | /* 7982 */ "ldtset\t\000" |
| 1031 | /* 7990 */ "rcwset\t\000" |
| 1032 | /* 7998 */ "cbbgt\t\000" |
| 1033 | /* 8005 */ "cbgt\t\000" |
| 1034 | /* 8011 */ "facgt\t\000" |
| 1035 | /* 8018 */ "whilegt\t\000" |
| 1036 | /* 8027 */ "cbhgt\t\000" |
| 1037 | /* 8034 */ "fcmgt\t\000" |
| 1038 | /* 8041 */ "cmpgt\t\000" |
| 1039 | /* 8048 */ "rbit\t\000" |
| 1040 | /* 8054 */ "trcit\t\000" |
| 1041 | /* 8061 */ "wfit\t\000" |
| 1042 | /* 8067 */ "texit\t\000" |
| 1043 | /* 8074 */ "sabalt\t\000" |
| 1044 | /* 8082 */ "uabalt\t\000" |
| 1045 | /* 8090 */ "sqdmlalt\t\000" |
| 1046 | /* 8100 */ "bfmlalt\t\000" |
| 1047 | /* 8109 */ "smlalt\t\000" |
| 1048 | /* 8117 */ "umlalt\t\000" |
| 1049 | /* 8125 */ "caspalt\t\000" |
| 1050 | /* 8134 */ "casalt\t\000" |
| 1051 | /* 8142 */ "cblt\t\000" |
| 1052 | /* 8148 */ "ssublt\t\000" |
| 1053 | /* 8156 */ "usublt\t\000" |
| 1054 | /* 8164 */ "sbclt\t\000" |
| 1055 | /* 8171 */ "adclt\t\000" |
| 1056 | /* 8178 */ "sabdlt\t\000" |
| 1057 | /* 8186 */ "uabdlt\t\000" |
| 1058 | /* 8194 */ "saddlt\t\000" |
| 1059 | /* 8202 */ "uaddlt\t\000" |
| 1060 | /* 8210 */ "whilelt\t\000" |
| 1061 | /* 8219 */ "scvtflt\t\000" |
| 1062 | /* 8228 */ "ucvtflt\t\000" |
| 1063 | /* 8237 */ "hlt\t\000" |
| 1064 | /* 8242 */ "sshllt\t\000" |
| 1065 | /* 8250 */ "ushllt\t\000" |
| 1066 | /* 8258 */ "sqdmullt\t\000" |
| 1067 | /* 8268 */ "pmullt\t\000" |
| 1068 | /* 8276 */ "smullt\t\000" |
| 1069 | /* 8284 */ "umullt\t\000" |
| 1070 | /* 8292 */ "fcmlt\t\000" |
| 1071 | /* 8299 */ "cmplt\t\000" |
| 1072 | /* 8306 */ "casplt\t\000" |
| 1073 | /* 8314 */ "caslt\t\000" |
| 1074 | /* 8321 */ "sqdmlslt\t\000" |
| 1075 | /* 8331 */ "bfmlslt\t\000" |
| 1076 | /* 8340 */ "smlslt\t\000" |
| 1077 | /* 8348 */ "umlslt\t\000" |
| 1078 | /* 8356 */ "bf1cvtlt\t\000" |
| 1079 | /* 8366 */ "bf2cvtlt\t\000" |
| 1080 | /* 8376 */ "fcvtlt\t\000" |
| 1081 | /* 8384 */ "histcnt\t\000" |
| 1082 | /* 8393 */ "rsubhnt\t\000" |
| 1083 | /* 8402 */ "raddhnt\t\000" |
| 1084 | /* 8411 */ "hint\t\000" |
| 1085 | /* 8417 */ "sqshrnt\t\000" |
| 1086 | /* 8426 */ "uqshrnt\t\000" |
| 1087 | /* 8435 */ "sqrshrnt\t\000" |
| 1088 | /* 8445 */ "uqrshrnt\t\000" |
| 1089 | /* 8455 */ "bfcvtnt\t\000" |
| 1090 | /* 8464 */ "sqxtnt\t\000" |
| 1091 | /* 8472 */ "uqxtnt\t\000" |
| 1092 | /* 8480 */ "sqshrunt\t\000" |
| 1093 | /* 8490 */ "sqrshrunt\t\000" |
| 1094 | /* 8501 */ "sqxtunt\t\000" |
| 1095 | /* 8510 */ "fcvtxnt\t\000" |
| 1096 | /* 8519 */ "cdot\t\000" |
| 1097 | /* 8525 */ "bfdot\t\000" |
| 1098 | /* 8532 */ "usdot\t\000" |
| 1099 | /* 8539 */ "sudot\t\000" |
| 1100 | /* 8546 */ "bfvdot\t\000" |
| 1101 | /* 8554 */ "usvdot\t\000" |
| 1102 | /* 8562 */ "suvdot\t\000" |
| 1103 | /* 8570 */ "cnot\t\000" |
| 1104 | /* 8576 */ "mlapt\t\000" |
| 1105 | /* 8583 */ "msubpt\t\000" |
| 1106 | /* 8591 */ "madpt\t\000" |
| 1107 | /* 8598 */ "maddpt\t\000" |
| 1108 | /* 8606 */ "caspt\t\000" |
| 1109 | /* 8613 */ "swpt\t\000" |
| 1110 | /* 8619 */ "fsqrt\t\000" |
| 1111 | /* 8626 */ "cast\t\000" |
| 1112 | /* 8632 */ "ptest\t\000" |
| 1113 | /* 8639 */ "pfirst\t\000" |
| 1114 | /* 8647 */ "cmtst\t\000" |
| 1115 | /* 8654 */ "fmlalltt\t\000" |
| 1116 | /* 8664 */ "fvdott\t\000" |
| 1117 | /* 8672 */ "bf1cvt\t\000" |
| 1118 | /* 8680 */ "bf2cvt\t\000" |
| 1119 | /* 8688 */ "bfcvt\t\000" |
| 1120 | /* 8695 */ "sqcvt\t\000" |
| 1121 | /* 8702 */ "uqcvt\t\000" |
| 1122 | /* 8709 */ "movt\t\000" |
| 1123 | /* 8715 */ "ssubwt\t\000" |
| 1124 | /* 8723 */ "usubwt\t\000" |
| 1125 | /* 8731 */ "saddwt\t\000" |
| 1126 | /* 8739 */ "uaddwt\t\000" |
| 1127 | /* 8747 */ "bext\t\000" |
| 1128 | /* 8753 */ "pnext\t\000" |
| 1129 | /* 8760 */ "pext\t\000" |
| 1130 | /* 8766 */ "fcvtau\t\000" |
| 1131 | /* 8774 */ "sqshlu\t\000" |
| 1132 | /* 8782 */ "fcvtmu\t\000" |
| 1133 | /* 8790 */ "fcvtnu\t\000" |
| 1134 | /* 8798 */ "fcvtpu\t\000" |
| 1135 | /* 8806 */ "sqrshru\t\000" |
| 1136 | /* 8815 */ "sqcvtu\t\000" |
| 1137 | /* 8823 */ "fcvtzu\t\000" |
| 1138 | /* 8831 */ "st64bv\t\000" |
| 1139 | /* 8839 */ "faddv\t\000" |
| 1140 | /* 8846 */ "saddv\t\000" |
| 1141 | /* 8853 */ "uaddv\t\000" |
| 1142 | /* 8860 */ "andv\t\000" |
| 1143 | /* 8866 */ "rev\t\000" |
| 1144 | /* 8871 */ "fdiv\t\000" |
| 1145 | /* 8877 */ "sdiv\t\000" |
| 1146 | /* 8883 */ "udiv\t\000" |
| 1147 | /* 8889 */ "saddlv\t\000" |
| 1148 | /* 8897 */ "uaddlv\t\000" |
| 1149 | /* 8905 */ "fminnmv\t\000" |
| 1150 | /* 8914 */ "fmaxnmv\t\000" |
| 1151 | /* 8923 */ "fminv\t\000" |
| 1152 | /* 8930 */ "sminv\t\000" |
| 1153 | /* 8937 */ "uminv\t\000" |
| 1154 | /* 8944 */ "csinv\t\000" |
| 1155 | /* 8951 */ "fmov\t\000" |
| 1156 | /* 8957 */ "pmov\t\000" |
| 1157 | /* 8963 */ "smov\t\000" |
| 1158 | /* 8969 */ "umov\t\000" |
| 1159 | /* 8975 */ "faddqv\t\000" |
| 1160 | /* 8983 */ "andqv\t\000" |
| 1161 | /* 8990 */ "fminnmqv\t\000" |
| 1162 | /* 9000 */ "fmaxnmqv\t\000" |
| 1163 | /* 9010 */ "fminqv\t\000" |
| 1164 | /* 9018 */ "sminqv\t\000" |
| 1165 | /* 9026 */ "uminqv\t\000" |
| 1166 | /* 9034 */ "eorqv\t\000" |
| 1167 | /* 9041 */ "fmaxqv\t\000" |
| 1168 | /* 9049 */ "smaxqv\t\000" |
| 1169 | /* 9057 */ "umaxqv\t\000" |
| 1170 | /* 9065 */ "eorv\t\000" |
| 1171 | /* 9071 */ "fmaxv\t\000" |
| 1172 | /* 9078 */ "smaxv\t\000" |
| 1173 | /* 9085 */ "umaxv\t\000" |
| 1174 | /* 9092 */ "ld1w\t\000" |
| 1175 | /* 9098 */ "ldff1w\t\000" |
| 1176 | /* 9106 */ "ldnf1w\t\000" |
| 1177 | /* 9114 */ "ldnt1w\t\000" |
| 1178 | /* 9122 */ "stnt1w\t\000" |
| 1179 | /* 9130 */ "st1w\t\000" |
| 1180 | /* 9136 */ "crc32w\t\000" |
| 1181 | /* 9144 */ "ld2w\t\000" |
| 1182 | /* 9150 */ "st2w\t\000" |
| 1183 | /* 9156 */ "ld3w\t\000" |
| 1184 | /* 9162 */ "st3w\t\000" |
| 1185 | /* 9168 */ "ld4w\t\000" |
| 1186 | /* 9174 */ "st4w\t\000" |
| 1187 | /* 9180 */ "ssubw\t\000" |
| 1188 | /* 9187 */ "usubw\t\000" |
| 1189 | /* 9194 */ "crc32cw\t\000" |
| 1190 | /* 9203 */ "sqdecw\t\000" |
| 1191 | /* 9211 */ "uqdecw\t\000" |
| 1192 | /* 9219 */ "sqincw\t\000" |
| 1193 | /* 9227 */ "uqincw\t\000" |
| 1194 | /* 9235 */ "saddw\t\000" |
| 1195 | /* 9242 */ "uaddw\t\000" |
| 1196 | /* 9249 */ "prfw\t\000" |
| 1197 | /* 9255 */ "ld1row\t\000" |
| 1198 | /* 9263 */ "ld1rqw\t\000" |
| 1199 | /* 9271 */ "ld1rw\t\000" |
| 1200 | /* 9278 */ "whilerw\t\000" |
| 1201 | /* 9287 */ "ld1sw\t\000" |
| 1202 | /* 9294 */ "ldff1sw\t\000" |
| 1203 | /* 9303 */ "ldnf1sw\t\000" |
| 1204 | /* 9312 */ "ldnt1sw\t\000" |
| 1205 | /* 9321 */ "ldpsw\t\000" |
| 1206 | /* 9328 */ "ld1rsw\t\000" |
| 1207 | /* 9336 */ "ldrsw\t\000" |
| 1208 | /* 9343 */ "ldtrsw\t\000" |
| 1209 | /* 9351 */ "ldursw\t\000" |
| 1210 | /* 9359 */ "ldapursw\t\000" |
| 1211 | /* 9369 */ "cntw\t\000" |
| 1212 | /* 9375 */ "sxtw\t\000" |
| 1213 | /* 9381 */ "uxtw\t\000" |
| 1214 | /* 9387 */ "revw\t\000" |
| 1215 | /* 9393 */ "crc32x\t\000" |
| 1216 | /* 9401 */ "frint32x\t\000" |
| 1217 | /* 9411 */ "frint64x\t\000" |
| 1218 | /* 9421 */ "bcax\t\000" |
| 1219 | /* 9427 */ "famax\t\000" |
| 1220 | /* 9434 */ "ldbfmax\t\000" |
| 1221 | /* 9443 */ "stbfmax\t\000" |
| 1222 | /* 9452 */ "ldfmax\t\000" |
| 1223 | /* 9460 */ "stfmax\t\000" |
| 1224 | /* 9468 */ "ldsmax\t\000" |
| 1225 | /* 9476 */ "ldumax\t\000" |
| 1226 | /* 9484 */ "tbx\t\000" |
| 1227 | /* 9489 */ "crc32cx\t\000" |
| 1228 | /* 9498 */ "index\t\000" |
| 1229 | /* 9505 */ "clrex\t\000" |
| 1230 | /* 9512 */ "movprfx\t\000" |
| 1231 | /* 9521 */ "fmulx\t\000" |
| 1232 | /* 9528 */ "frecpx\t\000" |
| 1233 | /* 9536 */ "frintx\t\000" |
| 1234 | /* 9544 */ "fcvtx\t\000" |
| 1235 | /* 9551 */ "sm4ekey\t\000" |
| 1236 | /* 9560 */ "fcpy\t\000" |
| 1237 | /* 9566 */ "frint32z\t\000" |
| 1238 | /* 9576 */ "frint64z\t\000" |
| 1239 | /* 9586 */ "braaz\t\000" |
| 1240 | /* 9593 */ "blraaz\t\000" |
| 1241 | /* 9601 */ "movaz\t\000" |
| 1242 | /* 9608 */ "brabz\t\000" |
| 1243 | /* 9615 */ "blrabz\t\000" |
| 1244 | /* 9623 */ "cbz\t\000" |
| 1245 | /* 9628 */ "tbz\t\000" |
| 1246 | /* 9633 */ "clz\t\000" |
| 1247 | /* 9638 */ "cbnz\t\000" |
| 1248 | /* 9644 */ "tbnz\t\000" |
| 1249 | /* 9650 */ "ctz\t\000" |
| 1250 | /* 9655 */ "frintz\t\000" |
| 1251 | /* 9663 */ "movz\t\000" |
| 1252 | /* 9669 */ ".tlsdesccall \000" |
| 1253 | /* 9683 */ "zero\t{ \000" |
| 1254 | /* 9691 */ "# XRay Function Patchable RET.\000" |
| 1255 | /* 9722 */ "b.\000" |
| 1256 | /* 9725 */ "bc.\000" |
| 1257 | /* 9729 */ "# XRay Typed Event Log.\000" |
| 1258 | /* 9753 */ "# XRay Custom Event Log.\000" |
| 1259 | /* 9778 */ "# XRay Function Enter.\000" |
| 1260 | /* 9801 */ "# XRay Tail Call Exit.\000" |
| 1261 | /* 9824 */ "# XRay Function Exit.\000" |
| 1262 | /* 9846 */ "hint\t#0\000" |
| 1263 | /* 9854 */ "hint\t#10\000" |
| 1264 | /* 9863 */ "hint\t#30\000" |
| 1265 | /* 9872 */ "hint\t#40\000" |
| 1266 | /* 9881 */ "hint\t#31\000" |
| 1267 | /* 9890 */ "hint\t#12\000" |
| 1268 | /* 9899 */ "hint\t#14\000" |
| 1269 | /* 9908 */ "hint\t#24\000" |
| 1270 | /* 9917 */ "pacia171615\000" |
| 1271 | /* 9929 */ "autia171615\000" |
| 1272 | /* 9941 */ "pacib171615\000" |
| 1273 | /* 9953 */ "autib171615\000" |
| 1274 | /* 9965 */ "hint\t#25\000" |
| 1275 | /* 9974 */ "hint\t#26\000" |
| 1276 | /* 9983 */ "hint\t#7\000" |
| 1277 | /* 9991 */ "hint\t#27\000" |
| 1278 | /* 10000 */ "hint\t#8\000" |
| 1279 | /* 10008 */ "hint\t#28\000" |
| 1280 | /* 10017 */ "hint\t#29\000" |
| 1281 | /* 10026 */ "hint\t#39\000" |
| 1282 | /* 10035 */ "LIFETIME_END\000" |
| 1283 | /* 10048 */ "PSEUDO_PROBE\000" |
| 1284 | /* 10061 */ "BUNDLE\000" |
| 1285 | /* 10068 */ "FAKE_USE\000" |
| 1286 | /* 10077 */ "DBG_VALUE\000" |
| 1287 | /* 10087 */ "DBG_INSTR_REF\000" |
| 1288 | /* 10101 */ "DBG_PHI\000" |
| 1289 | /* 10109 */ "DBG_LABEL\000" |
| 1290 | /* 10119 */ "LIFETIME_START\000" |
| 1291 | /* 10134 */ "DBG_VALUE_LIST\000" |
| 1292 | /* 10149 */ "cpyfe\t[\000" |
| 1293 | /* 10157 */ "setge\t[\000" |
| 1294 | /* 10165 */ "setgoe\t[\000" |
| 1295 | /* 10174 */ "sete\t[\000" |
| 1296 | /* 10181 */ "cpye\t[\000" |
| 1297 | /* 10188 */ "cpyfm\t[\000" |
| 1298 | /* 10196 */ "setgm\t[\000" |
| 1299 | /* 10204 */ "setgom\t[\000" |
| 1300 | /* 10213 */ "setm\t[\000" |
| 1301 | /* 10220 */ "cpym\t[\000" |
| 1302 | /* 10227 */ "cpyfen\t[\000" |
| 1303 | /* 10236 */ "setgen\t[\000" |
| 1304 | /* 10245 */ "setgoen\t[\000" |
| 1305 | /* 10255 */ "seten\t[\000" |
| 1306 | /* 10263 */ "cpyen\t[\000" |
| 1307 | /* 10271 */ "cpyfmn\t[\000" |
| 1308 | /* 10280 */ "setgmn\t[\000" |
| 1309 | /* 10289 */ "setgomn\t[\000" |
| 1310 | /* 10299 */ "setmn\t[\000" |
| 1311 | /* 10307 */ "cpymn\t[\000" |
| 1312 | /* 10315 */ "cpyfpn\t[\000" |
| 1313 | /* 10324 */ "setgpn\t[\000" |
| 1314 | /* 10333 */ "setgopn\t[\000" |
| 1315 | /* 10343 */ "setpn\t[\000" |
| 1316 | /* 10351 */ "cpypn\t[\000" |
| 1317 | /* 10359 */ "cpyfern\t[\000" |
| 1318 | /* 10369 */ "cpyern\t[\000" |
| 1319 | /* 10378 */ "cpyfmrn\t[\000" |
| 1320 | /* 10388 */ "cpymrn\t[\000" |
| 1321 | /* 10397 */ "cpyfprn\t[\000" |
| 1322 | /* 10407 */ "cpyprn\t[\000" |
| 1323 | /* 10416 */ "cpyfetrn\t[\000" |
| 1324 | /* 10427 */ "cpyetrn\t[\000" |
| 1325 | /* 10437 */ "cpyfmtrn\t[\000" |
| 1326 | /* 10448 */ "cpymtrn\t[\000" |
| 1327 | /* 10458 */ "cpyfptrn\t[\000" |
| 1328 | /* 10469 */ "cpyptrn\t[\000" |
| 1329 | /* 10479 */ "cpyfertrn\t[\000" |
| 1330 | /* 10491 */ "cpyertrn\t[\000" |
| 1331 | /* 10502 */ "cpyfmrtrn\t[\000" |
| 1332 | /* 10514 */ "cpymrtrn\t[\000" |
| 1333 | /* 10525 */ "cpyfprtrn\t[\000" |
| 1334 | /* 10537 */ "cpyprtrn\t[\000" |
| 1335 | /* 10548 */ "cpyfewtrn\t[\000" |
| 1336 | /* 10560 */ "cpyewtrn\t[\000" |
| 1337 | /* 10571 */ "cpyfmwtrn\t[\000" |
| 1338 | /* 10583 */ "cpymwtrn\t[\000" |
| 1339 | /* 10594 */ "cpyfpwtrn\t[\000" |
| 1340 | /* 10606 */ "cpypwtrn\t[\000" |
| 1341 | /* 10617 */ "cpyfetn\t[\000" |
| 1342 | /* 10627 */ "setgetn\t[\000" |
| 1343 | /* 10637 */ "setgoetn\t[\000" |
| 1344 | /* 10648 */ "setetn\t[\000" |
| 1345 | /* 10657 */ "cpyetn\t[\000" |
| 1346 | /* 10666 */ "cpyfmtn\t[\000" |
| 1347 | /* 10676 */ "setgmtn\t[\000" |
| 1348 | /* 10686 */ "setgomtn\t[\000" |
| 1349 | /* 10697 */ "setmtn\t[\000" |
| 1350 | /* 10706 */ "cpymtn\t[\000" |
| 1351 | /* 10715 */ "cpyfptn\t[\000" |
| 1352 | /* 10725 */ "setgptn\t[\000" |
| 1353 | /* 10735 */ "setgoptn\t[\000" |
| 1354 | /* 10746 */ "setptn\t[\000" |
| 1355 | /* 10755 */ "cpyptn\t[\000" |
| 1356 | /* 10764 */ "cpyfertn\t[\000" |
| 1357 | /* 10775 */ "cpyertn\t[\000" |
| 1358 | /* 10785 */ "cpyfmrtn\t[\000" |
| 1359 | /* 10796 */ "cpymrtn\t[\000" |
| 1360 | /* 10806 */ "cpyfprtn\t[\000" |
| 1361 | /* 10817 */ "cpyprtn\t[\000" |
| 1362 | /* 10827 */ "cpyfewtn\t[\000" |
| 1363 | /* 10838 */ "cpyewtn\t[\000" |
| 1364 | /* 10848 */ "cpyfmwtn\t[\000" |
| 1365 | /* 10859 */ "cpymwtn\t[\000" |
| 1366 | /* 10869 */ "cpyfpwtn\t[\000" |
| 1367 | /* 10880 */ "cpypwtn\t[\000" |
| 1368 | /* 10890 */ "cpyfewn\t[\000" |
| 1369 | /* 10900 */ "cpyewn\t[\000" |
| 1370 | /* 10909 */ "cpyfmwn\t[\000" |
| 1371 | /* 10919 */ "cpymwn\t[\000" |
| 1372 | /* 10928 */ "cpyfpwn\t[\000" |
| 1373 | /* 10938 */ "cpypwn\t[\000" |
| 1374 | /* 10947 */ "cpyfetwn\t[\000" |
| 1375 | /* 10958 */ "cpyetwn\t[\000" |
| 1376 | /* 10968 */ "cpyfmtwn\t[\000" |
| 1377 | /* 10979 */ "cpymtwn\t[\000" |
| 1378 | /* 10989 */ "cpyfptwn\t[\000" |
| 1379 | /* 11000 */ "cpyptwn\t[\000" |
| 1380 | /* 11010 */ "cpyfertwn\t[\000" |
| 1381 | /* 11022 */ "cpyertwn\t[\000" |
| 1382 | /* 11033 */ "cpyfmrtwn\t[\000" |
| 1383 | /* 11045 */ "cpymrtwn\t[\000" |
| 1384 | /* 11056 */ "cpyfprtwn\t[\000" |
| 1385 | /* 11068 */ "cpyprtwn\t[\000" |
| 1386 | /* 11079 */ "cpyfewtwn\t[\000" |
| 1387 | /* 11091 */ "cpyewtwn\t[\000" |
| 1388 | /* 11102 */ "cpyfmwtwn\t[\000" |
| 1389 | /* 11114 */ "cpymwtwn\t[\000" |
| 1390 | /* 11125 */ "cpyfpwtwn\t[\000" |
| 1391 | /* 11137 */ "cpypwtwn\t[\000" |
| 1392 | /* 11148 */ "cpyfp\t[\000" |
| 1393 | /* 11156 */ "setgp\t[\000" |
| 1394 | /* 11164 */ "setgop\t[\000" |
| 1395 | /* 11173 */ "setp\t[\000" |
| 1396 | /* 11180 */ "cpyp\t[\000" |
| 1397 | /* 11187 */ "cpyfet\t[\000" |
| 1398 | /* 11196 */ "setget\t[\000" |
| 1399 | /* 11205 */ "setgoet\t[\000" |
| 1400 | /* 11215 */ "setet\t[\000" |
| 1401 | /* 11223 */ "cpyet\t[\000" |
| 1402 | /* 11231 */ "cpyfmt\t[\000" |
| 1403 | /* 11240 */ "setgmt\t[\000" |
| 1404 | /* 11249 */ "setgomt\t[\000" |
| 1405 | /* 11259 */ "setmt\t[\000" |
| 1406 | /* 11267 */ "cpymt\t[\000" |
| 1407 | /* 11275 */ "cpyfpt\t[\000" |
| 1408 | /* 11284 */ "setgpt\t[\000" |
| 1409 | /* 11293 */ "setgopt\t[\000" |
| 1410 | /* 11303 */ "setpt\t[\000" |
| 1411 | /* 11311 */ "cpypt\t[\000" |
| 1412 | /* 11319 */ "cpyfert\t[\000" |
| 1413 | /* 11329 */ "cpyert\t[\000" |
| 1414 | /* 11338 */ "cpyfmrt\t[\000" |
| 1415 | /* 11348 */ "cpymrt\t[\000" |
| 1416 | /* 11357 */ "cpyfprt\t[\000" |
| 1417 | /* 11367 */ "cpyprt\t[\000" |
| 1418 | /* 11376 */ "cpyfewt\t[\000" |
| 1419 | /* 11386 */ "cpyewt\t[\000" |
| 1420 | /* 11395 */ "cpyfmwt\t[\000" |
| 1421 | /* 11405 */ "cpymwt\t[\000" |
| 1422 | /* 11414 */ "cpyfpwt\t[\000" |
| 1423 | /* 11424 */ "cpypwt\t[\000" |
| 1424 | /* 11433 */ "eretaa\000" |
| 1425 | /* 11440 */ "eretab\000" |
| 1426 | /* 11447 */ "sb\000" |
| 1427 | /* 11450 */ "pacnbiasppc\000" |
| 1428 | /* 11462 */ "paciasppc\000" |
| 1429 | /* 11472 */ "pacnbibsppc\000" |
| 1430 | /* 11484 */ "pacibsppc\000" |
| 1431 | /* 11494 */ "xaflag\000" |
| 1432 | /* 11501 */ "axflag\000" |
| 1433 | /* 11508 */ "stcph\000" |
| 1434 | /* 11514 */ "brb\tinj\000" |
| 1435 | /* 11522 */ "# FEntry call\000" |
| 1436 | /* 11536 */ "brb\tiall\000" |
| 1437 | /* 11545 */ "setffr\000" |
| 1438 | /* 11552 */ "drps\000" |
| 1439 | /* 11557 */ "eret\000" |
| 1440 | /* 11562 */ "cfinv\000" |
| 1441 | /* 11568 */ "gcspopcx\000" |
| 1442 | /* 11577 */ "gcspushx\000" |
| 1443 | /* 11586 */ "gcspopx\000" |
| 1444 | /* 11594 */ "ld1b\t{\000" |
| 1445 | /* 11601 */ "st1b\t{\000" |
| 1446 | /* 11608 */ "ld1d\t{\000" |
| 1447 | /* 11615 */ "st1d\t{\000" |
| 1448 | /* 11622 */ "ld1h\t{\000" |
| 1449 | /* 11629 */ "st1h\t{\000" |
| 1450 | /* 11636 */ "ld1q\t{\000" |
| 1451 | /* 11643 */ "st1q\t{\000" |
| 1452 | /* 11650 */ "ld1w\t{\000" |
| 1453 | /* 11657 */ "st1w\t{\000" |
| 1454 | }; |
| 1455 | #ifdef __GNUC__ |
| 1456 | #pragma GCC diagnostic pop |
| 1457 | #endif |
| 1458 | |
| 1459 | static const uint32_t OpInfo0[] = { |
| 1460 | 0U, // PHI |
| 1461 | 0U, // INLINEASM |
| 1462 | 0U, // INLINEASM_BR |
| 1463 | 0U, // CFI_INSTRUCTION |
| 1464 | 0U, // EH_LABEL |
| 1465 | 0U, // GC_LABEL |
| 1466 | 0U, // ANNOTATION_LABEL |
| 1467 | 0U, // KILL |
| 1468 | 0U, // EXTRACT_SUBREG |
| 1469 | 0U, // INSERT_SUBREG |
| 1470 | 0U, // IMPLICIT_DEF |
| 1471 | 0U, // INIT_UNDEF |
| 1472 | 0U, // SUBREG_TO_REG |
| 1473 | 0U, // COPY_TO_REGCLASS |
| 1474 | 10078U, // DBG_VALUE |
| 1475 | 10135U, // DBG_VALUE_LIST |
| 1476 | 10088U, // DBG_INSTR_REF |
| 1477 | 10102U, // DBG_PHI |
| 1478 | 10110U, // DBG_LABEL |
| 1479 | 0U, // REG_SEQUENCE |
| 1480 | 0U, // COPY |
| 1481 | 0U, // COPY_LANEMASK |
| 1482 | 10062U, // BUNDLE |
| 1483 | 10120U, // LIFETIME_START |
| 1484 | 10036U, // LIFETIME_END |
| 1485 | 10049U, // PSEUDO_PROBE |
| 1486 | 0U, // ARITH_FENCE |
| 1487 | 0U, // STACKMAP |
| 1488 | 11523U, // FENTRY_CALL |
| 1489 | 0U, // PATCHPOINT |
| 1490 | 0U, // LOAD_STACK_GUARD |
| 1491 | 0U, // PREALLOCATED_SETUP |
| 1492 | 0U, // PREALLOCATED_ARG |
| 1493 | 0U, // STATEPOINT |
| 1494 | 0U, // LOCAL_ESCAPE |
| 1495 | 0U, // FAULTING_OP |
| 1496 | 0U, // PATCHABLE_OP |
| 1497 | 9779U, // PATCHABLE_FUNCTION_ENTER |
| 1498 | 9692U, // PATCHABLE_RET |
| 1499 | 9825U, // PATCHABLE_FUNCTION_EXIT |
| 1500 | 9802U, // PATCHABLE_TAIL_CALL |
| 1501 | 9754U, // PATCHABLE_EVENT_CALL |
| 1502 | 9730U, // PATCHABLE_TYPED_EVENT_CALL |
| 1503 | 0U, // ICALL_BRANCH_FUNNEL |
| 1504 | 10069U, // FAKE_USE |
| 1505 | 0U, // MEMBARRIER |
| 1506 | 0U, // JUMP_TABLE_DEBUG_INFO |
| 1507 | 0U, // RELOC_NONE |
| 1508 | 0U, // CONVERGENCECTRL_ENTRY |
| 1509 | 0U, // CONVERGENCECTRL_ANCHOR |
| 1510 | 0U, // CONVERGENCECTRL_LOOP |
| 1511 | 0U, // CONVERGENCECTRL_GLUE |
| 1512 | 0U, // G_ASSERT_SEXT |
| 1513 | 0U, // G_ASSERT_ZEXT |
| 1514 | 0U, // G_ASSERT_ALIGN |
| 1515 | 0U, // G_ADD |
| 1516 | 0U, // G_SUB |
| 1517 | 0U, // G_MUL |
| 1518 | 0U, // G_SDIV |
| 1519 | 0U, // G_UDIV |
| 1520 | 0U, // G_SREM |
| 1521 | 0U, // G_UREM |
| 1522 | 0U, // G_SDIVREM |
| 1523 | 0U, // G_UDIVREM |
| 1524 | 0U, // G_AND |
| 1525 | 0U, // G_OR |
| 1526 | 0U, // G_XOR |
| 1527 | 0U, // G_ABDS |
| 1528 | 0U, // G_ABDU |
| 1529 | 0U, // G_UAVGFLOOR |
| 1530 | 0U, // G_UAVGCEIL |
| 1531 | 0U, // G_SAVGFLOOR |
| 1532 | 0U, // G_SAVGCEIL |
| 1533 | 0U, // G_IMPLICIT_DEF |
| 1534 | 0U, // G_PHI |
| 1535 | 0U, // G_FRAME_INDEX |
| 1536 | 0U, // G_GLOBAL_VALUE |
| 1537 | 0U, // G_PTRAUTH_GLOBAL_VALUE |
| 1538 | 0U, // G_CONSTANT_POOL |
| 1539 | 0U, // G_EXTRACT |
| 1540 | 0U, // G_UNMERGE_VALUES |
| 1541 | 0U, // G_INSERT |
| 1542 | 0U, // G_MERGE_VALUES |
| 1543 | 0U, // G_BUILD_VECTOR |
| 1544 | 0U, // G_BUILD_VECTOR_TRUNC |
| 1545 | 0U, // G_CONCAT_VECTORS |
| 1546 | 0U, // G_PTRTOINT |
| 1547 | 0U, // G_INTTOPTR |
| 1548 | 0U, // G_BITCAST |
| 1549 | 0U, // G_FREEZE |
| 1550 | 0U, // G_CONSTANT_FOLD_BARRIER |
| 1551 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 1552 | 0U, // G_INTRINSIC_TRUNC |
| 1553 | 0U, // G_INTRINSIC_ROUND |
| 1554 | 0U, // G_INTRINSIC_LRINT |
| 1555 | 0U, // G_INTRINSIC_LLRINT |
| 1556 | 0U, // G_INTRINSIC_ROUNDEVEN |
| 1557 | 0U, // G_READCYCLECOUNTER |
| 1558 | 0U, // G_READSTEADYCOUNTER |
| 1559 | 0U, // G_LOAD |
| 1560 | 0U, // G_SEXTLOAD |
| 1561 | 0U, // G_ZEXTLOAD |
| 1562 | 0U, // G_INDEXED_LOAD |
| 1563 | 0U, // G_INDEXED_SEXTLOAD |
| 1564 | 0U, // G_INDEXED_ZEXTLOAD |
| 1565 | 0U, // G_STORE |
| 1566 | 0U, // G_INDEXED_STORE |
| 1567 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 1568 | 0U, // G_ATOMIC_CMPXCHG |
| 1569 | 0U, // G_ATOMICRMW_XCHG |
| 1570 | 0U, // G_ATOMICRMW_ADD |
| 1571 | 0U, // G_ATOMICRMW_SUB |
| 1572 | 0U, // G_ATOMICRMW_AND |
| 1573 | 0U, // G_ATOMICRMW_NAND |
| 1574 | 0U, // G_ATOMICRMW_OR |
| 1575 | 0U, // G_ATOMICRMW_XOR |
| 1576 | 0U, // G_ATOMICRMW_MAX |
| 1577 | 0U, // G_ATOMICRMW_MIN |
| 1578 | 0U, // G_ATOMICRMW_UMAX |
| 1579 | 0U, // G_ATOMICRMW_UMIN |
| 1580 | 0U, // G_ATOMICRMW_FADD |
| 1581 | 0U, // G_ATOMICRMW_FSUB |
| 1582 | 0U, // G_ATOMICRMW_FMAX |
| 1583 | 0U, // G_ATOMICRMW_FMIN |
| 1584 | 0U, // G_ATOMICRMW_FMAXIMUM |
| 1585 | 0U, // G_ATOMICRMW_FMINIMUM |
| 1586 | 0U, // G_ATOMICRMW_FMAXIMUMNUM |
| 1587 | 0U, // G_ATOMICRMW_FMINIMUMNUM |
| 1588 | 0U, // G_ATOMICRMW_UINC_WRAP |
| 1589 | 0U, // G_ATOMICRMW_UDEC_WRAP |
| 1590 | 0U, // G_ATOMICRMW_USUB_COND |
| 1591 | 0U, // G_ATOMICRMW_USUB_SAT |
| 1592 | 0U, // G_FENCE |
| 1593 | 0U, // G_PREFETCH |
| 1594 | 0U, // G_BRCOND |
| 1595 | 0U, // G_BRINDIRECT |
| 1596 | 0U, // G_INVOKE_REGION_START |
| 1597 | 0U, // G_INTRINSIC |
| 1598 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 1599 | 0U, // G_INTRINSIC_CONVERGENT |
| 1600 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 1601 | 0U, // G_ANYEXT |
| 1602 | 0U, // G_TRUNC |
| 1603 | 0U, // G_TRUNC_SSAT_S |
| 1604 | 0U, // G_TRUNC_SSAT_U |
| 1605 | 0U, // G_TRUNC_USAT_U |
| 1606 | 0U, // G_CONSTANT |
| 1607 | 0U, // G_FCONSTANT |
| 1608 | 0U, // G_VASTART |
| 1609 | 0U, // G_VAARG |
| 1610 | 0U, // G_SEXT |
| 1611 | 0U, // G_SEXT_INREG |
| 1612 | 0U, // G_ZEXT |
| 1613 | 0U, // G_SHL |
| 1614 | 0U, // G_LSHR |
| 1615 | 0U, // G_ASHR |
| 1616 | 0U, // G_FSHL |
| 1617 | 0U, // G_FSHR |
| 1618 | 0U, // G_ROTR |
| 1619 | 0U, // G_ROTL |
| 1620 | 0U, // G_ICMP |
| 1621 | 0U, // G_FCMP |
| 1622 | 0U, // G_SCMP |
| 1623 | 0U, // G_UCMP |
| 1624 | 0U, // G_SELECT |
| 1625 | 0U, // G_UADDO |
| 1626 | 0U, // G_UADDE |
| 1627 | 0U, // G_USUBO |
| 1628 | 0U, // G_USUBE |
| 1629 | 0U, // G_SADDO |
| 1630 | 0U, // G_SADDE |
| 1631 | 0U, // G_SSUBO |
| 1632 | 0U, // G_SSUBE |
| 1633 | 0U, // G_UMULO |
| 1634 | 0U, // G_SMULO |
| 1635 | 0U, // G_UMULH |
| 1636 | 0U, // G_SMULH |
| 1637 | 0U, // G_UADDSAT |
| 1638 | 0U, // G_SADDSAT |
| 1639 | 0U, // G_USUBSAT |
| 1640 | 0U, // G_SSUBSAT |
| 1641 | 0U, // G_USHLSAT |
| 1642 | 0U, // G_SSHLSAT |
| 1643 | 0U, // G_SMULFIX |
| 1644 | 0U, // G_UMULFIX |
| 1645 | 0U, // G_SMULFIXSAT |
| 1646 | 0U, // G_UMULFIXSAT |
| 1647 | 0U, // G_SDIVFIX |
| 1648 | 0U, // G_UDIVFIX |
| 1649 | 0U, // G_SDIVFIXSAT |
| 1650 | 0U, // G_UDIVFIXSAT |
| 1651 | 0U, // G_FADD |
| 1652 | 0U, // G_FSUB |
| 1653 | 0U, // G_FMUL |
| 1654 | 0U, // G_FMA |
| 1655 | 0U, // G_FMAD |
| 1656 | 0U, // G_FDIV |
| 1657 | 0U, // G_FREM |
| 1658 | 0U, // G_FMODF |
| 1659 | 0U, // G_FPOW |
| 1660 | 0U, // G_FPOWI |
| 1661 | 0U, // G_FEXP |
| 1662 | 0U, // G_FEXP2 |
| 1663 | 0U, // G_FEXP10 |
| 1664 | 0U, // G_FLOG |
| 1665 | 0U, // G_FLOG2 |
| 1666 | 0U, // G_FLOG10 |
| 1667 | 0U, // G_FLDEXP |
| 1668 | 0U, // G_FFREXP |
| 1669 | 0U, // G_FNEG |
| 1670 | 0U, // G_FPEXT |
| 1671 | 0U, // G_FPTRUNC |
| 1672 | 0U, // G_FPTOSI |
| 1673 | 0U, // G_FPTOUI |
| 1674 | 0U, // G_SITOFP |
| 1675 | 0U, // G_UITOFP |
| 1676 | 0U, // G_FPTOSI_SAT |
| 1677 | 0U, // G_FPTOUI_SAT |
| 1678 | 0U, // G_FABS |
| 1679 | 0U, // G_FCOPYSIGN |
| 1680 | 0U, // G_IS_FPCLASS |
| 1681 | 0U, // G_FCANONICALIZE |
| 1682 | 0U, // G_FMINNUM |
| 1683 | 0U, // G_FMAXNUM |
| 1684 | 0U, // G_FMINNUM_IEEE |
| 1685 | 0U, // G_FMAXNUM_IEEE |
| 1686 | 0U, // G_FMINIMUM |
| 1687 | 0U, // G_FMAXIMUM |
| 1688 | 0U, // G_FMINIMUMNUM |
| 1689 | 0U, // G_FMAXIMUMNUM |
| 1690 | 0U, // G_GET_FPENV |
| 1691 | 0U, // G_SET_FPENV |
| 1692 | 0U, // G_RESET_FPENV |
| 1693 | 0U, // G_GET_FPMODE |
| 1694 | 0U, // G_SET_FPMODE |
| 1695 | 0U, // G_RESET_FPMODE |
| 1696 | 0U, // G_GET_ROUNDING |
| 1697 | 0U, // G_SET_ROUNDING |
| 1698 | 0U, // G_PTR_ADD |
| 1699 | 0U, // G_PTRMASK |
| 1700 | 0U, // G_SMIN |
| 1701 | 0U, // G_SMAX |
| 1702 | 0U, // G_UMIN |
| 1703 | 0U, // G_UMAX |
| 1704 | 0U, // G_ABS |
| 1705 | 0U, // G_LROUND |
| 1706 | 0U, // G_LLROUND |
| 1707 | 0U, // G_BR |
| 1708 | 0U, // G_BRJT |
| 1709 | 0U, // G_VSCALE |
| 1710 | 0U, // G_INSERT_SUBVECTOR |
| 1711 | 0U, // G_EXTRACT_SUBVECTOR |
| 1712 | 0U, // G_INSERT_VECTOR_ELT |
| 1713 | 0U, // G_EXTRACT_VECTOR_ELT |
| 1714 | 0U, // G_SHUFFLE_VECTOR |
| 1715 | 0U, // G_SPLAT_VECTOR |
| 1716 | 0U, // G_STEP_VECTOR |
| 1717 | 0U, // G_VECTOR_COMPRESS |
| 1718 | 0U, // G_CTTZ |
| 1719 | 0U, // G_CTTZ_ZERO_UNDEF |
| 1720 | 0U, // G_CTLZ |
| 1721 | 0U, // G_CTLZ_ZERO_UNDEF |
| 1722 | 0U, // G_CTLS |
| 1723 | 0U, // G_CTPOP |
| 1724 | 0U, // G_BSWAP |
| 1725 | 0U, // G_BITREVERSE |
| 1726 | 0U, // G_FCEIL |
| 1727 | 0U, // G_FCOS |
| 1728 | 0U, // G_FSIN |
| 1729 | 0U, // G_FSINCOS |
| 1730 | 0U, // G_FTAN |
| 1731 | 0U, // G_FACOS |
| 1732 | 0U, // G_FASIN |
| 1733 | 0U, // G_FATAN |
| 1734 | 0U, // G_FATAN2 |
| 1735 | 0U, // G_FCOSH |
| 1736 | 0U, // G_FSINH |
| 1737 | 0U, // G_FTANH |
| 1738 | 0U, // G_FSQRT |
| 1739 | 0U, // G_FFLOOR |
| 1740 | 0U, // G_FRINT |
| 1741 | 0U, // G_FNEARBYINT |
| 1742 | 0U, // G_ADDRSPACE_CAST |
| 1743 | 0U, // G_BLOCK_ADDR |
| 1744 | 0U, // G_JUMP_TABLE |
| 1745 | 0U, // G_DYN_STACKALLOC |
| 1746 | 0U, // G_STACKSAVE |
| 1747 | 0U, // G_STACKRESTORE |
| 1748 | 0U, // G_STRICT_FADD |
| 1749 | 0U, // G_STRICT_FSUB |
| 1750 | 0U, // G_STRICT_FMUL |
| 1751 | 0U, // G_STRICT_FDIV |
| 1752 | 0U, // G_STRICT_FREM |
| 1753 | 0U, // G_STRICT_FMA |
| 1754 | 0U, // G_STRICT_FSQRT |
| 1755 | 0U, // G_STRICT_FLDEXP |
| 1756 | 0U, // G_READ_REGISTER |
| 1757 | 0U, // G_WRITE_REGISTER |
| 1758 | 0U, // G_MEMCPY |
| 1759 | 0U, // G_MEMCPY_INLINE |
| 1760 | 0U, // G_MEMMOVE |
| 1761 | 0U, // G_MEMSET |
| 1762 | 0U, // G_BZERO |
| 1763 | 0U, // G_TRAP |
| 1764 | 0U, // G_DEBUGTRAP |
| 1765 | 0U, // G_UBSANTRAP |
| 1766 | 0U, // G_VECREDUCE_SEQ_FADD |
| 1767 | 0U, // G_VECREDUCE_SEQ_FMUL |
| 1768 | 0U, // G_VECREDUCE_FADD |
| 1769 | 0U, // G_VECREDUCE_FMUL |
| 1770 | 0U, // G_VECREDUCE_FMAX |
| 1771 | 0U, // G_VECREDUCE_FMIN |
| 1772 | 0U, // G_VECREDUCE_FMAXIMUM |
| 1773 | 0U, // G_VECREDUCE_FMINIMUM |
| 1774 | 0U, // G_VECREDUCE_ADD |
| 1775 | 0U, // G_VECREDUCE_MUL |
| 1776 | 0U, // G_VECREDUCE_AND |
| 1777 | 0U, // G_VECREDUCE_OR |
| 1778 | 0U, // G_VECREDUCE_XOR |
| 1779 | 0U, // G_VECREDUCE_SMAX |
| 1780 | 0U, // G_VECREDUCE_SMIN |
| 1781 | 0U, // G_VECREDUCE_UMAX |
| 1782 | 0U, // G_VECREDUCE_UMIN |
| 1783 | 0U, // G_SBFX |
| 1784 | 0U, // G_UBFX |
| 1785 | 0U, // ABS_ZPmZ_B_UNDEF |
| 1786 | 0U, // ABS_ZPmZ_D_UNDEF |
| 1787 | 0U, // ABS_ZPmZ_H_UNDEF |
| 1788 | 0U, // ABS_ZPmZ_S_UNDEF |
| 1789 | 0U, // ADDHA_MPPZ_D_PSEUDO_D |
| 1790 | 0U, // ADDHA_MPPZ_S_PSEUDO_S |
| 1791 | 0U, // ADDSWrr |
| 1792 | 0U, // ADDSXrr |
| 1793 | 0U, // ADDVA_MPPZ_D_PSEUDO_D |
| 1794 | 0U, // ADDVA_MPPZ_S_PSEUDO_S |
| 1795 | 0U, // ADDWrr |
| 1796 | 0U, // ADDXrr |
| 1797 | 0U, // ADD_VG2_M2Z2Z_D_PSEUDO |
| 1798 | 0U, // ADD_VG2_M2Z2Z_S_PSEUDO |
| 1799 | 0U, // ADD_VG2_M2ZZ_D_PSEUDO |
| 1800 | 0U, // ADD_VG2_M2ZZ_S_PSEUDO |
| 1801 | 0U, // ADD_VG2_M2Z_D_PSEUDO |
| 1802 | 0U, // ADD_VG2_M2Z_S_PSEUDO |
| 1803 | 0U, // ADD_VG4_M4Z4Z_D_PSEUDO |
| 1804 | 0U, // ADD_VG4_M4Z4Z_S_PSEUDO |
| 1805 | 0U, // ADD_VG4_M4ZZ_D_PSEUDO |
| 1806 | 0U, // ADD_VG4_M4ZZ_S_PSEUDO |
| 1807 | 0U, // ADD_VG4_M4Z_D_PSEUDO |
| 1808 | 0U, // ADD_VG4_M4Z_S_PSEUDO |
| 1809 | 0U, // ADD_ZI_B_PSEUDO |
| 1810 | 0U, // ADD_ZI_D_PSEUDO |
| 1811 | 0U, // ADD_ZI_H_PSEUDO |
| 1812 | 0U, // ADD_ZI_S_PSEUDO |
| 1813 | 0U, // ADD_ZPZZ_B_ZERO |
| 1814 | 0U, // ADD_ZPZZ_D_ZERO |
| 1815 | 0U, // ADD_ZPZZ_H_ZERO |
| 1816 | 0U, // ADD_ZPZZ_S_ZERO |
| 1817 | 0U, // ADDlowTLS |
| 1818 | 0U, // ADJCALLSTACKDOWN |
| 1819 | 0U, // ADJCALLSTACKUP |
| 1820 | 0U, // AESIMCrrTied |
| 1821 | 0U, // AESMCrrTied |
| 1822 | 0U, // ANDSWrr |
| 1823 | 0U, // ANDSXrr |
| 1824 | 0U, // ANDWrr |
| 1825 | 0U, // ANDXrr |
| 1826 | 0U, // AND_ZPZZ_B_ZERO |
| 1827 | 0U, // AND_ZPZZ_D_ZERO |
| 1828 | 0U, // AND_ZPZZ_H_ZERO |
| 1829 | 0U, // AND_ZPZZ_S_ZERO |
| 1830 | 0U, // ASRD_ZPZI_B_ZERO |
| 1831 | 0U, // ASRD_ZPZI_D_ZERO |
| 1832 | 0U, // ASRD_ZPZI_H_ZERO |
| 1833 | 0U, // ASRD_ZPZI_S_ZERO |
| 1834 | 0U, // ASR_ZPZI_B_UNDEF |
| 1835 | 0U, // ASR_ZPZI_B_ZERO |
| 1836 | 0U, // ASR_ZPZI_D_UNDEF |
| 1837 | 0U, // ASR_ZPZI_D_ZERO |
| 1838 | 0U, // ASR_ZPZI_H_UNDEF |
| 1839 | 0U, // ASR_ZPZI_H_ZERO |
| 1840 | 0U, // ASR_ZPZI_S_UNDEF |
| 1841 | 0U, // ASR_ZPZI_S_ZERO |
| 1842 | 0U, // ASR_ZPZZ_B_UNDEF |
| 1843 | 0U, // ASR_ZPZZ_B_ZERO |
| 1844 | 0U, // ASR_ZPZZ_D_UNDEF |
| 1845 | 0U, // ASR_ZPZZ_D_ZERO |
| 1846 | 0U, // ASR_ZPZZ_H_UNDEF |
| 1847 | 0U, // ASR_ZPZZ_H_ZERO |
| 1848 | 0U, // ASR_ZPZZ_S_UNDEF |
| 1849 | 0U, // ASR_ZPZZ_S_ZERO |
| 1850 | 0U, // AUTH_TCRETURN |
| 1851 | 0U, // AUTH_TCRETURN_BTI |
| 1852 | 0U, // AUTPAC |
| 1853 | 0U, // AUTRELLOADPAC |
| 1854 | 0U, // AUTx16x17 |
| 1855 | 0U, // AUTxMxN |
| 1856 | 0U, // AllocateSMESaveBuffer |
| 1857 | 0U, // AllocateZABuffer |
| 1858 | 0U, // BFADD_VG2_M2Z_H_PSEUDO |
| 1859 | 0U, // BFADD_VG4_M4Z_H_PSEUDO |
| 1860 | 0U, // BFADD_ZPZZ_UNDEF |
| 1861 | 0U, // BFADD_ZPZZ_ZERO |
| 1862 | 0U, // BFDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 1863 | 0U, // BFDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 1864 | 0U, // BFDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 1865 | 0U, // BFDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 1866 | 0U, // BFDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 1867 | 0U, // BFDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 1868 | 0U, // BFMAXNM_ZPZZ_UNDEF |
| 1869 | 0U, // BFMAXNM_ZPZZ_ZERO |
| 1870 | 0U, // BFMAX_ZPZZ_UNDEF |
| 1871 | 0U, // BFMAX_ZPZZ_ZERO |
| 1872 | 0U, // BFMINNM_ZPZZ_UNDEF |
| 1873 | 0U, // BFMINNM_ZPZZ_ZERO |
| 1874 | 0U, // BFMIN_ZPZZ_UNDEF |
| 1875 | 0U, // BFMIN_ZPZZ_ZERO |
| 1876 | 0U, // BFMLAL_MZZI_HtoS_PSEUDO |
| 1877 | 0U, // BFMLAL_MZZ_HtoS_PSEUDO |
| 1878 | 0U, // BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 1879 | 0U, // BFMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 1880 | 0U, // BFMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 1881 | 0U, // BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 1882 | 0U, // BFMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 1883 | 0U, // BFMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 1884 | 0U, // BFMLA_VG2_M2Z2Z_PSEUDO |
| 1885 | 0U, // BFMLA_VG2_M2ZZI_PSEUDO |
| 1886 | 0U, // BFMLA_VG2_M2ZZ_PSEUDO |
| 1887 | 0U, // BFMLA_VG4_M4Z4Z_PSEUDO |
| 1888 | 0U, // BFMLA_VG4_M4ZZI_PSEUDO |
| 1889 | 0U, // BFMLA_VG4_M4ZZ_PSEUDO |
| 1890 | 0U, // BFMLA_ZPZZZ_UNDEF |
| 1891 | 0U, // BFMLSL_MZZI_HtoS_PSEUDO |
| 1892 | 0U, // BFMLSL_MZZ_HtoS_PSEUDO |
| 1893 | 0U, // BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 1894 | 0U, // BFMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 1895 | 0U, // BFMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 1896 | 0U, // BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 1897 | 0U, // BFMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 1898 | 0U, // BFMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 1899 | 0U, // BFMLS_VG2_M2Z2Z_PSEUDO |
| 1900 | 0U, // BFMLS_VG2_M2ZZI_PSEUDO |
| 1901 | 0U, // BFMLS_VG2_M2ZZ_PSEUDO |
| 1902 | 0U, // BFMLS_VG4_M4Z4Z_PSEUDO |
| 1903 | 0U, // BFMLS_VG4_M4ZZI_PSEUDO |
| 1904 | 0U, // BFMLS_VG4_M4ZZ_PSEUDO |
| 1905 | 0U, // BFMLS_ZPZZZ_UNDEF |
| 1906 | 0U, // BFMOP4A_M2Z2Z_H_PSEUDO |
| 1907 | 0U, // BFMOP4A_M2Z2Z_S_PSEUDO |
| 1908 | 0U, // BFMOP4A_M2ZZ_H_PSEUDO |
| 1909 | 0U, // BFMOP4A_M2ZZ_S_PSEUDO |
| 1910 | 0U, // BFMOP4A_MZ2Z_H_PSEUDO |
| 1911 | 0U, // BFMOP4A_MZ2Z_S_PSEUDO |
| 1912 | 0U, // BFMOP4A_MZZ_H_PSEUDO |
| 1913 | 0U, // BFMOP4A_MZZ_S_PSEUDO |
| 1914 | 0U, // BFMOP4S_M2Z2Z_H_PSEUDO |
| 1915 | 0U, // BFMOP4S_M2Z2Z_S_PSEUDO |
| 1916 | 0U, // BFMOP4S_M2ZZ_H_PSEUDO |
| 1917 | 0U, // BFMOP4S_M2ZZ_S_PSEUDO |
| 1918 | 0U, // BFMOP4S_MZ2Z_H_PSEUDO |
| 1919 | 0U, // BFMOP4S_MZ2Z_S_PSEUDO |
| 1920 | 0U, // BFMOP4S_MZZ_H_PSEUDO |
| 1921 | 0U, // BFMOP4S_MZZ_S_PSEUDO |
| 1922 | 0U, // BFMOPA_MPPZZ_H_PSEUDO |
| 1923 | 0U, // BFMOPA_MPPZZ_PSEUDO |
| 1924 | 0U, // BFMOPS_MPPZZ_H_PSEUDO |
| 1925 | 0U, // BFMOPS_MPPZZ_PSEUDO |
| 1926 | 0U, // BFMUL_ZPZZ_UNDEF |
| 1927 | 0U, // BFMUL_ZPZZ_ZERO |
| 1928 | 0U, // BFSUB_VG2_M2Z_H_PSEUDO |
| 1929 | 0U, // BFSUB_VG4_M4Z_H_PSEUDO |
| 1930 | 0U, // BFSUB_ZPZZ_UNDEF |
| 1931 | 0U, // BFSUB_ZPZZ_ZERO |
| 1932 | 0U, // BFTMOPA_M2ZZZI_HtoH_PSEUDO |
| 1933 | 0U, // BFTMOPA_M2ZZZI_HtoS_PSEUDO |
| 1934 | 0U, // BFVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 1935 | 0U, // BICSWrr |
| 1936 | 0U, // BICSXrr |
| 1937 | 0U, // BICWrr |
| 1938 | 0U, // BICXrr |
| 1939 | 0U, // BIC_ZPZZ_B_ZERO |
| 1940 | 0U, // BIC_ZPZZ_D_ZERO |
| 1941 | 0U, // BIC_ZPZZ_H_ZERO |
| 1942 | 0U, // BIC_ZPZZ_S_ZERO |
| 1943 | 0U, // BLRA |
| 1944 | 0U, // BLRA_RVMARKER |
| 1945 | 0U, // BLRNoIP |
| 1946 | 0U, // BLR_BTI |
| 1947 | 0U, // BLR_RVMARKER |
| 1948 | 0U, // BLR_X16 |
| 1949 | 0U, // BMOPA_MPPZZ_S_PSEUDO |
| 1950 | 0U, // BMOPS_MPPZZ_S_PSEUDO |
| 1951 | 0U, // BRA |
| 1952 | 0U, // BR_JumpTable |
| 1953 | 0U, // BSPv16i8 |
| 1954 | 0U, // BSPv8i8 |
| 1955 | 0U, // CATCHRET |
| 1956 | 0U, // CBBAssertExt |
| 1957 | 0U, // CBHAssertExt |
| 1958 | 0U, // CBWPri |
| 1959 | 0U, // CBWPrr |
| 1960 | 0U, // CBXPri |
| 1961 | 0U, // CBXPrr |
| 1962 | 0U, // CHECK_MATCHING_VL_PSEUDO |
| 1963 | 0U, // CLEANUPRET |
| 1964 | 0U, // CLS_ZPmZ_B_UNDEF |
| 1965 | 0U, // CLS_ZPmZ_D_UNDEF |
| 1966 | 0U, // CLS_ZPmZ_H_UNDEF |
| 1967 | 0U, // CLS_ZPmZ_S_UNDEF |
| 1968 | 0U, // CLZ_ZPmZ_B_UNDEF |
| 1969 | 0U, // CLZ_ZPmZ_D_UNDEF |
| 1970 | 0U, // CLZ_ZPmZ_H_UNDEF |
| 1971 | 0U, // CLZ_ZPmZ_S_UNDEF |
| 1972 | 0U, // CMP_SWAP_128 |
| 1973 | 0U, // CMP_SWAP_128_ACQUIRE |
| 1974 | 0U, // CMP_SWAP_128_MONOTONIC |
| 1975 | 0U, // CMP_SWAP_128_RELEASE |
| 1976 | 0U, // CMP_SWAP_16 |
| 1977 | 0U, // CMP_SWAP_32 |
| 1978 | 0U, // CMP_SWAP_64 |
| 1979 | 0U, // CMP_SWAP_8 |
| 1980 | 0U, // CNOT_ZPmZ_B_UNDEF |
| 1981 | 0U, // CNOT_ZPmZ_D_UNDEF |
| 1982 | 0U, // CNOT_ZPmZ_H_UNDEF |
| 1983 | 0U, // CNOT_ZPmZ_S_UNDEF |
| 1984 | 0U, // CNT_ZPmZ_B_UNDEF |
| 1985 | 0U, // CNT_ZPmZ_D_UNDEF |
| 1986 | 0U, // CNT_ZPmZ_H_UNDEF |
| 1987 | 0U, // CNT_ZPmZ_S_UNDEF |
| 1988 | 0U, // COALESCER_BARRIER_FPR128 |
| 1989 | 0U, // COALESCER_BARRIER_FPR16 |
| 1990 | 0U, // COALESCER_BARRIER_FPR32 |
| 1991 | 0U, // COALESCER_BARRIER_FPR64 |
| 1992 | 0U, // CommitZASavePseudo |
| 1993 | 0U, // EMITBKEY |
| 1994 | 0U, // EMITMTETAGGED |
| 1995 | 0U, // EONWrr |
| 1996 | 0U, // EONXrr |
| 1997 | 0U, // EON_ZZZ |
| 1998 | 0U, // EORWrr |
| 1999 | 0U, // EORXrr |
| 2000 | 0U, // EOR_ZPZZ_B_ZERO |
| 2001 | 0U, // EOR_ZPZZ_D_ZERO |
| 2002 | 0U, // EOR_ZPZZ_H_ZERO |
| 2003 | 0U, // EOR_ZPZZ_S_ZERO |
| 2004 | 0U, // EXT_ZZI_CONSTRUCTIVE |
| 2005 | 0U, // EntryPStateSM |
| 2006 | 0U, // F128CSEL |
| 2007 | 0U, // FABD_ZPZZ_D_UNDEF |
| 2008 | 0U, // FABD_ZPZZ_D_ZERO |
| 2009 | 0U, // FABD_ZPZZ_H_UNDEF |
| 2010 | 0U, // FABD_ZPZZ_H_ZERO |
| 2011 | 0U, // FABD_ZPZZ_S_UNDEF |
| 2012 | 0U, // FABD_ZPZZ_S_ZERO |
| 2013 | 0U, // FABS_ZPmZ_D_UNDEF |
| 2014 | 0U, // FABS_ZPmZ_H_UNDEF |
| 2015 | 0U, // FABS_ZPmZ_S_UNDEF |
| 2016 | 0U, // FADD_VG2_M2Z_D_PSEUDO |
| 2017 | 0U, // FADD_VG2_M2Z_H_PSEUDO |
| 2018 | 0U, // FADD_VG2_M2Z_S_PSEUDO |
| 2019 | 0U, // FADD_VG4_M4Z_D_PSEUDO |
| 2020 | 0U, // FADD_VG4_M4Z_H_PSEUDO |
| 2021 | 0U, // FADD_VG4_M4Z_S_PSEUDO |
| 2022 | 0U, // FADD_ZPZI_D_UNDEF |
| 2023 | 0U, // FADD_ZPZI_D_ZERO |
| 2024 | 0U, // FADD_ZPZI_H_UNDEF |
| 2025 | 0U, // FADD_ZPZI_H_ZERO |
| 2026 | 0U, // FADD_ZPZI_S_UNDEF |
| 2027 | 0U, // FADD_ZPZI_S_ZERO |
| 2028 | 0U, // FADD_ZPZZ_D_UNDEF |
| 2029 | 0U, // FADD_ZPZZ_D_ZERO |
| 2030 | 0U, // FADD_ZPZZ_H_UNDEF |
| 2031 | 0U, // FADD_ZPZZ_H_ZERO |
| 2032 | 0U, // FADD_ZPZZ_S_UNDEF |
| 2033 | 0U, // FADD_ZPZZ_S_ZERO |
| 2034 | 0U, // FAMAX_ZPZZ_D_UNDEF |
| 2035 | 0U, // FAMAX_ZPZZ_H_UNDEF |
| 2036 | 0U, // FAMAX_ZPZZ_S_UNDEF |
| 2037 | 0U, // FAMIN_ZPZZ_D_UNDEF |
| 2038 | 0U, // FAMIN_ZPZZ_H_UNDEF |
| 2039 | 0U, // FAMIN_ZPZZ_S_UNDEF |
| 2040 | 0U, // FCVTZS_ZPmZ_DtoD_UNDEF |
| 2041 | 0U, // FCVTZS_ZPmZ_DtoS_UNDEF |
| 2042 | 0U, // FCVTZS_ZPmZ_HtoD_UNDEF |
| 2043 | 0U, // FCVTZS_ZPmZ_HtoH_UNDEF |
| 2044 | 0U, // FCVTZS_ZPmZ_HtoS_UNDEF |
| 2045 | 0U, // FCVTZS_ZPmZ_StoD_UNDEF |
| 2046 | 0U, // FCVTZS_ZPmZ_StoS_UNDEF |
| 2047 | 0U, // FCVTZU_ZPmZ_DtoD_UNDEF |
| 2048 | 0U, // FCVTZU_ZPmZ_DtoS_UNDEF |
| 2049 | 0U, // FCVTZU_ZPmZ_HtoD_UNDEF |
| 2050 | 0U, // FCVTZU_ZPmZ_HtoH_UNDEF |
| 2051 | 0U, // FCVTZU_ZPmZ_HtoS_UNDEF |
| 2052 | 0U, // FCVTZU_ZPmZ_StoD_UNDEF |
| 2053 | 0U, // FCVTZU_ZPmZ_StoS_UNDEF |
| 2054 | 0U, // FCVT_ZPmZ_DtoH_UNDEF |
| 2055 | 0U, // FCVT_ZPmZ_DtoS_UNDEF |
| 2056 | 0U, // FCVT_ZPmZ_HtoD_UNDEF |
| 2057 | 0U, // FCVT_ZPmZ_HtoS_UNDEF |
| 2058 | 0U, // FCVT_ZPmZ_StoD_UNDEF |
| 2059 | 0U, // FCVT_ZPmZ_StoH_UNDEF |
| 2060 | 0U, // FDIVR_ZPZZ_D_ZERO |
| 2061 | 0U, // FDIVR_ZPZZ_H_ZERO |
| 2062 | 0U, // FDIVR_ZPZZ_S_ZERO |
| 2063 | 0U, // FDIV_ZPZZ_D_UNDEF |
| 2064 | 0U, // FDIV_ZPZZ_D_ZERO |
| 2065 | 0U, // FDIV_ZPZZ_H_UNDEF |
| 2066 | 0U, // FDIV_ZPZZ_H_ZERO |
| 2067 | 0U, // FDIV_ZPZZ_S_UNDEF |
| 2068 | 0U, // FDIV_ZPZZ_S_ZERO |
| 2069 | 0U, // FDOT_VG2_M2Z2Z_BtoH_PSEUDO |
| 2070 | 0U, // FDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 2071 | 0U, // FDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 2072 | 0U, // FDOT_VG2_M2ZZI_BtoH_PSEUDO |
| 2073 | 0U, // FDOT_VG2_M2ZZI_BtoS_PSEUDO |
| 2074 | 0U, // FDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 2075 | 0U, // FDOT_VG2_M2ZZ_BtoH_PSEUDO |
| 2076 | 0U, // FDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 2077 | 0U, // FDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 2078 | 0U, // FDOT_VG4_M4Z4Z_BtoH_PSEUDO |
| 2079 | 0U, // FDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 2080 | 0U, // FDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 2081 | 0U, // FDOT_VG4_M4ZZI_BtoH_PSEUDO |
| 2082 | 0U, // FDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 2083 | 0U, // FDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 2084 | 0U, // FDOT_VG4_M4ZZ_BtoH_PSEUDO |
| 2085 | 0U, // FDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 2086 | 0U, // FDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 2087 | 0U, // FLOGB_ZPZZ_D_ZERO |
| 2088 | 0U, // FLOGB_ZPZZ_H_ZERO |
| 2089 | 0U, // FLOGB_ZPZZ_S_ZERO |
| 2090 | 0U, // FMAXNM_ZPZI_D_UNDEF |
| 2091 | 0U, // FMAXNM_ZPZI_D_ZERO |
| 2092 | 0U, // FMAXNM_ZPZI_H_UNDEF |
| 2093 | 0U, // FMAXNM_ZPZI_H_ZERO |
| 2094 | 0U, // FMAXNM_ZPZI_S_UNDEF |
| 2095 | 0U, // FMAXNM_ZPZI_S_ZERO |
| 2096 | 0U, // FMAXNM_ZPZZ_D_UNDEF |
| 2097 | 0U, // FMAXNM_ZPZZ_D_ZERO |
| 2098 | 0U, // FMAXNM_ZPZZ_H_UNDEF |
| 2099 | 0U, // FMAXNM_ZPZZ_H_ZERO |
| 2100 | 0U, // FMAXNM_ZPZZ_S_UNDEF |
| 2101 | 0U, // FMAXNM_ZPZZ_S_ZERO |
| 2102 | 0U, // FMAX_ZPZI_D_UNDEF |
| 2103 | 0U, // FMAX_ZPZI_D_ZERO |
| 2104 | 0U, // FMAX_ZPZI_H_UNDEF |
| 2105 | 0U, // FMAX_ZPZI_H_ZERO |
| 2106 | 0U, // FMAX_ZPZI_S_UNDEF |
| 2107 | 0U, // FMAX_ZPZI_S_ZERO |
| 2108 | 0U, // FMAX_ZPZZ_D_UNDEF |
| 2109 | 0U, // FMAX_ZPZZ_D_ZERO |
| 2110 | 0U, // FMAX_ZPZZ_H_UNDEF |
| 2111 | 0U, // FMAX_ZPZZ_H_ZERO |
| 2112 | 0U, // FMAX_ZPZZ_S_UNDEF |
| 2113 | 0U, // FMAX_ZPZZ_S_ZERO |
| 2114 | 0U, // FMINNM_ZPZI_D_UNDEF |
| 2115 | 0U, // FMINNM_ZPZI_D_ZERO |
| 2116 | 0U, // FMINNM_ZPZI_H_UNDEF |
| 2117 | 0U, // FMINNM_ZPZI_H_ZERO |
| 2118 | 0U, // FMINNM_ZPZI_S_UNDEF |
| 2119 | 0U, // FMINNM_ZPZI_S_ZERO |
| 2120 | 0U, // FMINNM_ZPZZ_D_UNDEF |
| 2121 | 0U, // FMINNM_ZPZZ_D_ZERO |
| 2122 | 0U, // FMINNM_ZPZZ_H_UNDEF |
| 2123 | 0U, // FMINNM_ZPZZ_H_ZERO |
| 2124 | 0U, // FMINNM_ZPZZ_S_UNDEF |
| 2125 | 0U, // FMINNM_ZPZZ_S_ZERO |
| 2126 | 0U, // FMIN_ZPZI_D_UNDEF |
| 2127 | 0U, // FMIN_ZPZI_D_ZERO |
| 2128 | 0U, // FMIN_ZPZI_H_UNDEF |
| 2129 | 0U, // FMIN_ZPZI_H_ZERO |
| 2130 | 0U, // FMIN_ZPZI_S_UNDEF |
| 2131 | 0U, // FMIN_ZPZI_S_ZERO |
| 2132 | 0U, // FMIN_ZPZZ_D_UNDEF |
| 2133 | 0U, // FMIN_ZPZZ_D_ZERO |
| 2134 | 0U, // FMIN_ZPZZ_H_UNDEF |
| 2135 | 0U, // FMIN_ZPZZ_H_ZERO |
| 2136 | 0U, // FMIN_ZPZZ_S_UNDEF |
| 2137 | 0U, // FMIN_ZPZZ_S_ZERO |
| 2138 | 0U, // FMLALL_MZZI_BtoS_PSEUDO |
| 2139 | 0U, // FMLALL_MZZ_BtoS_PSEUDO |
| 2140 | 0U, // FMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 2141 | 0U, // FMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 2142 | 0U, // FMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 2143 | 0U, // FMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 2144 | 0U, // FMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 2145 | 0U, // FMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 2146 | 0U, // FMLAL_MZZI_BtoH_PSEUDO |
| 2147 | 0U, // FMLAL_MZZI_HtoS_PSEUDO |
| 2148 | 0U, // FMLAL_MZZ_HtoS_PSEUDO |
| 2149 | 0U, // FMLAL_VG2_M2Z2Z_BtoH_PSEUDO |
| 2150 | 0U, // FMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2151 | 0U, // FMLAL_VG2_M2ZZI_BtoH_PSEUDO |
| 2152 | 0U, // FMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 2153 | 0U, // FMLAL_VG2_M2ZZ_BtoH_PSEUDO |
| 2154 | 0U, // FMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 2155 | 0U, // FMLAL_VG2_MZZ_BtoH_PSEUDO |
| 2156 | 0U, // FMLAL_VG4_M4Z4Z_BtoH_PSEUDO |
| 2157 | 0U, // FMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2158 | 0U, // FMLAL_VG4_M4ZZI_BtoH_PSEUDO |
| 2159 | 0U, // FMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 2160 | 0U, // FMLAL_VG4_M4ZZ_BtoH_PSEUDO |
| 2161 | 0U, // FMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 2162 | 0U, // FMLA_VG2_M2Z2Z_D_PSEUDO |
| 2163 | 0U, // FMLA_VG2_M2Z2Z_H_PSEUDO |
| 2164 | 0U, // FMLA_VG2_M2Z2Z_S_PSEUDO |
| 2165 | 0U, // FMLA_VG2_M2ZZI_D_PSEUDO |
| 2166 | 0U, // FMLA_VG2_M2ZZI_H_PSEUDO |
| 2167 | 0U, // FMLA_VG2_M2ZZI_S_PSEUDO |
| 2168 | 0U, // FMLA_VG2_M2ZZ_D_PSEUDO |
| 2169 | 0U, // FMLA_VG2_M2ZZ_H_PSEUDO |
| 2170 | 0U, // FMLA_VG2_M2ZZ_S_PSEUDO |
| 2171 | 0U, // FMLA_VG4_M4Z4Z_D_PSEUDO |
| 2172 | 0U, // FMLA_VG4_M4Z4Z_H_PSEUDO |
| 2173 | 0U, // FMLA_VG4_M4Z4Z_S_PSEUDO |
| 2174 | 0U, // FMLA_VG4_M4ZZI_D_PSEUDO |
| 2175 | 0U, // FMLA_VG4_M4ZZI_H_PSEUDO |
| 2176 | 0U, // FMLA_VG4_M4ZZI_S_PSEUDO |
| 2177 | 0U, // FMLA_VG4_M4ZZ_D_PSEUDO |
| 2178 | 0U, // FMLA_VG4_M4ZZ_H_PSEUDO |
| 2179 | 0U, // FMLA_VG4_M4ZZ_S_PSEUDO |
| 2180 | 0U, // FMLA_ZPZZZ_D_UNDEF |
| 2181 | 0U, // FMLA_ZPZZZ_H_UNDEF |
| 2182 | 0U, // FMLA_ZPZZZ_S_UNDEF |
| 2183 | 0U, // FMLSL_MZZI_HtoS_PSEUDO |
| 2184 | 0U, // FMLSL_MZZ_HtoS_PSEUDO |
| 2185 | 0U, // FMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2186 | 0U, // FMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 2187 | 0U, // FMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 2188 | 0U, // FMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2189 | 0U, // FMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 2190 | 0U, // FMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 2191 | 0U, // FMLS_VG2_M2Z2Z_D_PSEUDO |
| 2192 | 0U, // FMLS_VG2_M2Z2Z_H_PSEUDO |
| 2193 | 0U, // FMLS_VG2_M2Z2Z_S_PSEUDO |
| 2194 | 0U, // FMLS_VG2_M2ZZI_D_PSEUDO |
| 2195 | 0U, // FMLS_VG2_M2ZZI_H_PSEUDO |
| 2196 | 0U, // FMLS_VG2_M2ZZI_S_PSEUDO |
| 2197 | 0U, // FMLS_VG2_M2ZZ_D_PSEUDO |
| 2198 | 0U, // FMLS_VG2_M2ZZ_H_PSEUDO |
| 2199 | 0U, // FMLS_VG2_M2ZZ_S_PSEUDO |
| 2200 | 0U, // FMLS_VG4_M4Z4Z_D_PSEUDO |
| 2201 | 0U, // FMLS_VG4_M4Z4Z_H_PSEUDO |
| 2202 | 0U, // FMLS_VG4_M4Z4Z_S_PSEUDO |
| 2203 | 0U, // FMLS_VG4_M4ZZI_D_PSEUDO |
| 2204 | 0U, // FMLS_VG4_M4ZZI_H_PSEUDO |
| 2205 | 0U, // FMLS_VG4_M4ZZI_S_PSEUDO |
| 2206 | 0U, // FMLS_VG4_M4ZZ_D_PSEUDO |
| 2207 | 0U, // FMLS_VG4_M4ZZ_H_PSEUDO |
| 2208 | 0U, // FMLS_VG4_M4ZZ_S_PSEUDO |
| 2209 | 0U, // FMLS_ZPZZZ_D_UNDEF |
| 2210 | 0U, // FMLS_ZPZZZ_H_UNDEF |
| 2211 | 0U, // FMLS_ZPZZZ_S_UNDEF |
| 2212 | 0U, // FMOP4A_M2Z2Z_BtoH_PSEUDO |
| 2213 | 0U, // FMOP4A_M2Z2Z_BtoS_PSEUDO |
| 2214 | 0U, // FMOP4A_M2Z2Z_D_PSEUDO |
| 2215 | 0U, // FMOP4A_M2Z2Z_H_PSEUDO |
| 2216 | 0U, // FMOP4A_M2Z2Z_HtoS_PSEUDO |
| 2217 | 0U, // FMOP4A_M2Z2Z_S_PSEUDO |
| 2218 | 0U, // FMOP4A_M2ZZ_BtoH_PSEUDO |
| 2219 | 0U, // FMOP4A_M2ZZ_BtoS_PSEUDO |
| 2220 | 0U, // FMOP4A_M2ZZ_D_PSEUDO |
| 2221 | 0U, // FMOP4A_M2ZZ_H_PSEUDO |
| 2222 | 0U, // FMOP4A_M2ZZ_HtoS_PSEUDO |
| 2223 | 0U, // FMOP4A_M2ZZ_S_PSEUDO |
| 2224 | 0U, // FMOP4A_MZ2Z_BtoH_PSEUDO |
| 2225 | 0U, // FMOP4A_MZ2Z_BtoS_PSEUDO |
| 2226 | 0U, // FMOP4A_MZ2Z_D_PSEUDO |
| 2227 | 0U, // FMOP4A_MZ2Z_H_PSEUDO |
| 2228 | 0U, // FMOP4A_MZ2Z_HtoS_PSEUDO |
| 2229 | 0U, // FMOP4A_MZ2Z_S_PSEUDO |
| 2230 | 0U, // FMOP4A_MZZ_BtoH_PSEUDO |
| 2231 | 0U, // FMOP4A_MZZ_BtoS_PSEUDO |
| 2232 | 0U, // FMOP4A_MZZ_D_PSEUDO |
| 2233 | 0U, // FMOP4A_MZZ_H_PSEUDO |
| 2234 | 0U, // FMOP4A_MZZ_HtoS_PSEUDO |
| 2235 | 0U, // FMOP4A_MZZ_S_PSEUDO |
| 2236 | 0U, // FMOP4S_M2Z2Z_D_PSEUDO |
| 2237 | 0U, // FMOP4S_M2Z2Z_H_PSEUDO |
| 2238 | 0U, // FMOP4S_M2Z2Z_HtoS_PSEUDO |
| 2239 | 0U, // FMOP4S_M2Z2Z_S_PSEUDO |
| 2240 | 0U, // FMOP4S_M2ZZ_D_PSEUDO |
| 2241 | 0U, // FMOP4S_M2ZZ_H_PSEUDO |
| 2242 | 0U, // FMOP4S_M2ZZ_HtoS_PSEUDO |
| 2243 | 0U, // FMOP4S_M2ZZ_S_PSEUDO |
| 2244 | 0U, // FMOP4S_MZ2Z_D_PSEUDO |
| 2245 | 0U, // FMOP4S_MZ2Z_H_PSEUDO |
| 2246 | 0U, // FMOP4S_MZ2Z_HtoS_PSEUDO |
| 2247 | 0U, // FMOP4S_MZ2Z_S_PSEUDO |
| 2248 | 0U, // FMOP4S_MZZ_D_PSEUDO |
| 2249 | 0U, // FMOP4S_MZZ_H_PSEUDO |
| 2250 | 0U, // FMOP4S_MZZ_HtoS_PSEUDO |
| 2251 | 0U, // FMOP4S_MZZ_S_PSEUDO |
| 2252 | 0U, // FMOPAL_MPPZZ_PSEUDO |
| 2253 | 0U, // FMOPA_MPPZZ_BtoH_PSEUDO |
| 2254 | 0U, // FMOPA_MPPZZ_BtoS_PSEUDO |
| 2255 | 0U, // FMOPA_MPPZZ_D_PSEUDO |
| 2256 | 0U, // FMOPA_MPPZZ_H_PSEUDO |
| 2257 | 0U, // FMOPA_MPPZZ_S_PSEUDO |
| 2258 | 0U, // FMOPSL_MPPZZ_PSEUDO |
| 2259 | 0U, // FMOPS_MPPZZ_D_PSEUDO |
| 2260 | 0U, // FMOPS_MPPZZ_H_PSEUDO |
| 2261 | 0U, // FMOPS_MPPZZ_S_PSEUDO |
| 2262 | 0U, // FMOVD0 |
| 2263 | 0U, // FMOVH0 |
| 2264 | 0U, // FMOVS0 |
| 2265 | 0U, // FMULX_ZPZZ_D_UNDEF |
| 2266 | 0U, // FMULX_ZPZZ_D_ZERO |
| 2267 | 0U, // FMULX_ZPZZ_H_UNDEF |
| 2268 | 0U, // FMULX_ZPZZ_H_ZERO |
| 2269 | 0U, // FMULX_ZPZZ_S_UNDEF |
| 2270 | 0U, // FMULX_ZPZZ_S_ZERO |
| 2271 | 0U, // FMUL_ZPZI_D_UNDEF |
| 2272 | 0U, // FMUL_ZPZI_D_ZERO |
| 2273 | 0U, // FMUL_ZPZI_H_UNDEF |
| 2274 | 0U, // FMUL_ZPZI_H_ZERO |
| 2275 | 0U, // FMUL_ZPZI_S_UNDEF |
| 2276 | 0U, // FMUL_ZPZI_S_ZERO |
| 2277 | 0U, // FMUL_ZPZZ_D_UNDEF |
| 2278 | 0U, // FMUL_ZPZZ_D_ZERO |
| 2279 | 0U, // FMUL_ZPZZ_H_UNDEF |
| 2280 | 0U, // FMUL_ZPZZ_H_ZERO |
| 2281 | 0U, // FMUL_ZPZZ_S_UNDEF |
| 2282 | 0U, // FMUL_ZPZZ_S_ZERO |
| 2283 | 0U, // FNEG_ZPmZ_D_UNDEF |
| 2284 | 0U, // FNEG_ZPmZ_H_UNDEF |
| 2285 | 0U, // FNEG_ZPmZ_S_UNDEF |
| 2286 | 0U, // FNMLA_ZPZZZ_D_UNDEF |
| 2287 | 0U, // FNMLA_ZPZZZ_H_UNDEF |
| 2288 | 0U, // FNMLA_ZPZZZ_S_UNDEF |
| 2289 | 0U, // FNMLS_ZPZZZ_D_UNDEF |
| 2290 | 0U, // FNMLS_ZPZZZ_H_UNDEF |
| 2291 | 0U, // FNMLS_ZPZZZ_S_UNDEF |
| 2292 | 0U, // FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO |
| 2293 | 0U, // FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO |
| 2294 | 0U, // FRECPX_ZPmZ_D_UNDEF |
| 2295 | 0U, // FRECPX_ZPmZ_H_UNDEF |
| 2296 | 0U, // FRECPX_ZPmZ_S_UNDEF |
| 2297 | 0U, // FRINT32X_ZPmZ_D_UNDEF |
| 2298 | 0U, // FRINT32X_ZPmZ_S_UNDEF |
| 2299 | 0U, // FRINT32Z_ZPmZ_D_UNDEF |
| 2300 | 0U, // FRINT32Z_ZPmZ_S_UNDEF |
| 2301 | 0U, // FRINT64X_ZPmZ_D_UNDEF |
| 2302 | 0U, // FRINT64X_ZPmZ_S_UNDEF |
| 2303 | 0U, // FRINT64Z_ZPmZ_D_UNDEF |
| 2304 | 0U, // FRINT64Z_ZPmZ_S_UNDEF |
| 2305 | 0U, // FRINTA_ZPmZ_D_UNDEF |
| 2306 | 0U, // FRINTA_ZPmZ_H_UNDEF |
| 2307 | 0U, // FRINTA_ZPmZ_S_UNDEF |
| 2308 | 0U, // FRINTI_ZPmZ_D_UNDEF |
| 2309 | 0U, // FRINTI_ZPmZ_H_UNDEF |
| 2310 | 0U, // FRINTI_ZPmZ_S_UNDEF |
| 2311 | 0U, // FRINTM_ZPmZ_D_UNDEF |
| 2312 | 0U, // FRINTM_ZPmZ_H_UNDEF |
| 2313 | 0U, // FRINTM_ZPmZ_S_UNDEF |
| 2314 | 0U, // FRINTN_ZPmZ_D_UNDEF |
| 2315 | 0U, // FRINTN_ZPmZ_H_UNDEF |
| 2316 | 0U, // FRINTN_ZPmZ_S_UNDEF |
| 2317 | 0U, // FRINTP_ZPmZ_D_UNDEF |
| 2318 | 0U, // FRINTP_ZPmZ_H_UNDEF |
| 2319 | 0U, // FRINTP_ZPmZ_S_UNDEF |
| 2320 | 0U, // FRINTX_ZPmZ_D_UNDEF |
| 2321 | 0U, // FRINTX_ZPmZ_H_UNDEF |
| 2322 | 0U, // FRINTX_ZPmZ_S_UNDEF |
| 2323 | 0U, // FRINTZ_ZPmZ_D_UNDEF |
| 2324 | 0U, // FRINTZ_ZPmZ_H_UNDEF |
| 2325 | 0U, // FRINTZ_ZPmZ_S_UNDEF |
| 2326 | 0U, // FSQRT_ZPmZ_D_UNDEF |
| 2327 | 0U, // FSQRT_ZPmZ_H_UNDEF |
| 2328 | 0U, // FSQRT_ZPmZ_S_UNDEF |
| 2329 | 0U, // FSUBR_ZPZI_D_UNDEF |
| 2330 | 0U, // FSUBR_ZPZI_D_ZERO |
| 2331 | 0U, // FSUBR_ZPZI_H_UNDEF |
| 2332 | 0U, // FSUBR_ZPZI_H_ZERO |
| 2333 | 0U, // FSUBR_ZPZI_S_UNDEF |
| 2334 | 0U, // FSUBR_ZPZI_S_ZERO |
| 2335 | 0U, // FSUBR_ZPZZ_D_ZERO |
| 2336 | 0U, // FSUBR_ZPZZ_H_ZERO |
| 2337 | 0U, // FSUBR_ZPZZ_S_ZERO |
| 2338 | 0U, // FSUB_VG2_M2Z_D_PSEUDO |
| 2339 | 0U, // FSUB_VG2_M2Z_H_PSEUDO |
| 2340 | 0U, // FSUB_VG2_M2Z_S_PSEUDO |
| 2341 | 0U, // FSUB_VG4_M4Z_D_PSEUDO |
| 2342 | 0U, // FSUB_VG4_M4Z_H_PSEUDO |
| 2343 | 0U, // FSUB_VG4_M4Z_S_PSEUDO |
| 2344 | 0U, // FSUB_ZPZI_D_UNDEF |
| 2345 | 0U, // FSUB_ZPZI_D_ZERO |
| 2346 | 0U, // FSUB_ZPZI_H_UNDEF |
| 2347 | 0U, // FSUB_ZPZI_H_ZERO |
| 2348 | 0U, // FSUB_ZPZI_S_UNDEF |
| 2349 | 0U, // FSUB_ZPZI_S_ZERO |
| 2350 | 0U, // FSUB_ZPZZ_D_UNDEF |
| 2351 | 0U, // FSUB_ZPZZ_D_ZERO |
| 2352 | 0U, // FSUB_ZPZZ_H_UNDEF |
| 2353 | 0U, // FSUB_ZPZZ_H_ZERO |
| 2354 | 0U, // FSUB_ZPZZ_S_UNDEF |
| 2355 | 0U, // FSUB_ZPZZ_S_ZERO |
| 2356 | 0U, // FTMOPA_M2ZZZI_BtoH_PSEUDO |
| 2357 | 0U, // FTMOPA_M2ZZZI_BtoS_PSEUDO |
| 2358 | 0U, // FTMOPA_M2ZZZI_HtoH_PSEUDO |
| 2359 | 0U, // FTMOPA_M2ZZZI_HtoS_PSEUDO |
| 2360 | 0U, // FTMOPA_M2ZZZI_StoS_PSEUDO |
| 2361 | 0U, // FVDOTB_VG4_M2ZZI_BtoS_PSEUDO |
| 2362 | 0U, // FVDOTT_VG4_M2ZZI_BtoS_PSEUDO |
| 2363 | 0U, // FVDOT_VG2_M2ZZI_BtoH_PSEUDO |
| 2364 | 0U, // FVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 2365 | 0U, // G_AARCH64_PREFETCH |
| 2366 | 0U, // G_AARCH64_RANGE_PREFETCH |
| 2367 | 0U, // G_ADD_LOW |
| 2368 | 0U, // G_BSP |
| 2369 | 0U, // G_DUP |
| 2370 | 0U, // G_DUPLANE16 |
| 2371 | 0U, // G_DUPLANE32 |
| 2372 | 0U, // G_DUPLANE64 |
| 2373 | 0U, // G_DUPLANE8 |
| 2374 | 0U, // G_EXT |
| 2375 | 0U, // G_FCMEQ |
| 2376 | 0U, // G_FCMGE |
| 2377 | 0U, // G_FCMGT |
| 2378 | 0U, // G_FPTRUNC_ODD |
| 2379 | 0U, // G_PMULL |
| 2380 | 0U, // G_REV32 |
| 2381 | 0U, // G_REV64 |
| 2382 | 0U, // G_SADDLP |
| 2383 | 0U, // G_SADDLV |
| 2384 | 0U, // G_SDOT |
| 2385 | 0U, // G_SITOF |
| 2386 | 0U, // G_SLI |
| 2387 | 0U, // G_SMULL |
| 2388 | 0U, // G_SQSHLU_I |
| 2389 | 0U, // G_SRI |
| 2390 | 0U, // G_SRSHR_I |
| 2391 | 0U, // G_TRN1 |
| 2392 | 0U, // G_TRN2 |
| 2393 | 0U, // G_UADDLP |
| 2394 | 0U, // G_UADDLV |
| 2395 | 0U, // G_UDOT |
| 2396 | 0U, // G_UITOF |
| 2397 | 0U, // G_UMULL |
| 2398 | 0U, // G_URSHR_I |
| 2399 | 0U, // G_USDOT |
| 2400 | 0U, // G_UZP1 |
| 2401 | 0U, // G_UZP2 |
| 2402 | 0U, // G_VASHR |
| 2403 | 0U, // G_VLSHR |
| 2404 | 0U, // G_ZIP1 |
| 2405 | 0U, // G_ZIP2 |
| 2406 | 0U, // GetSMESaveSize |
| 2407 | 0U, // HOM_Epilog |
| 2408 | 0U, // HOM_Prolog |
| 2409 | 0U, // HWASAN_CHECK_MEMACCESS |
| 2410 | 0U, // HWASAN_CHECK_MEMACCESS_FIXEDSHADOW |
| 2411 | 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| 2412 | 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW |
| 2413 | 0U, // INSERT_MXIPZ_H_PSEUDO_B |
| 2414 | 0U, // INSERT_MXIPZ_H_PSEUDO_D |
| 2415 | 0U, // INSERT_MXIPZ_H_PSEUDO_H |
| 2416 | 0U, // INSERT_MXIPZ_H_PSEUDO_Q |
| 2417 | 0U, // INSERT_MXIPZ_H_PSEUDO_S |
| 2418 | 0U, // INSERT_MXIPZ_V_PSEUDO_B |
| 2419 | 0U, // INSERT_MXIPZ_V_PSEUDO_D |
| 2420 | 0U, // INSERT_MXIPZ_V_PSEUDO_H |
| 2421 | 0U, // INSERT_MXIPZ_V_PSEUDO_Q |
| 2422 | 0U, // INSERT_MXIPZ_V_PSEUDO_S |
| 2423 | 0U, // IRGstack |
| 2424 | 0U, // InOutZAUsePseudo |
| 2425 | 0U, // InitTPIDR2Obj |
| 2426 | 0U, // JumpTableDest16 |
| 2427 | 0U, // JumpTableDest32 |
| 2428 | 0U, // JumpTableDest8 |
| 2429 | 0U, // KCFI_CHECK |
| 2430 | 0U, // LD1B_2Z_IMM_PSEUDO |
| 2431 | 0U, // LD1B_2Z_PSEUDO |
| 2432 | 0U, // LD1B_4Z_IMM_PSEUDO |
| 2433 | 0U, // LD1B_4Z_PSEUDO |
| 2434 | 0U, // LD1D_2Z_IMM_PSEUDO |
| 2435 | 0U, // LD1D_2Z_PSEUDO |
| 2436 | 0U, // LD1D_4Z_IMM_PSEUDO |
| 2437 | 0U, // LD1D_4Z_PSEUDO |
| 2438 | 0U, // LD1H_2Z_IMM_PSEUDO |
| 2439 | 0U, // LD1H_2Z_PSEUDO |
| 2440 | 0U, // LD1H_4Z_IMM_PSEUDO |
| 2441 | 0U, // LD1H_4Z_PSEUDO |
| 2442 | 0U, // LD1W_2Z_IMM_PSEUDO |
| 2443 | 0U, // LD1W_2Z_PSEUDO |
| 2444 | 0U, // LD1W_4Z_IMM_PSEUDO |
| 2445 | 0U, // LD1W_4Z_PSEUDO |
| 2446 | 0U, // LD1_MXIPXX_H_PSEUDO_B |
| 2447 | 0U, // LD1_MXIPXX_H_PSEUDO_D |
| 2448 | 0U, // LD1_MXIPXX_H_PSEUDO_H |
| 2449 | 0U, // LD1_MXIPXX_H_PSEUDO_Q |
| 2450 | 0U, // LD1_MXIPXX_H_PSEUDO_S |
| 2451 | 0U, // LD1_MXIPXX_V_PSEUDO_B |
| 2452 | 0U, // LD1_MXIPXX_V_PSEUDO_D |
| 2453 | 0U, // LD1_MXIPXX_V_PSEUDO_H |
| 2454 | 0U, // LD1_MXIPXX_V_PSEUDO_Q |
| 2455 | 0U, // LD1_MXIPXX_V_PSEUDO_S |
| 2456 | 0U, // LDNT1B_2Z_IMM_PSEUDO |
| 2457 | 0U, // LDNT1B_2Z_PSEUDO |
| 2458 | 0U, // LDNT1B_4Z_IMM_PSEUDO |
| 2459 | 0U, // LDNT1B_4Z_PSEUDO |
| 2460 | 0U, // LDNT1D_2Z_IMM_PSEUDO |
| 2461 | 0U, // LDNT1D_2Z_PSEUDO |
| 2462 | 0U, // LDNT1D_4Z_IMM_PSEUDO |
| 2463 | 0U, // LDNT1D_4Z_PSEUDO |
| 2464 | 0U, // LDNT1H_2Z_IMM_PSEUDO |
| 2465 | 0U, // LDNT1H_2Z_PSEUDO |
| 2466 | 0U, // LDNT1H_4Z_IMM_PSEUDO |
| 2467 | 0U, // LDNT1H_4Z_PSEUDO |
| 2468 | 0U, // LDNT1W_2Z_IMM_PSEUDO |
| 2469 | 0U, // LDNT1W_2Z_PSEUDO |
| 2470 | 0U, // LDNT1W_4Z_IMM_PSEUDO |
| 2471 | 0U, // LDNT1W_4Z_PSEUDO |
| 2472 | 0U, // LDR_PPXI |
| 2473 | 0U, // LDR_TX_PSEUDO |
| 2474 | 0U, // LDR_ZA_PSEUDO |
| 2475 | 0U, // LDR_ZZXI |
| 2476 | 0U, // LDR_ZZXI_STRIDED_CONTIGUOUS |
| 2477 | 0U, // LDR_ZZZXI |
| 2478 | 0U, // LDR_ZZZZXI |
| 2479 | 0U, // LDR_ZZZZXI_STRIDED_CONTIGUOUS |
| 2480 | 0U, // LOADauthptrstatic |
| 2481 | 0U, // LOADgot |
| 2482 | 0U, // LOADgotAUTH |
| 2483 | 0U, // LOADgotPAC |
| 2484 | 0U, // LSL_ZPZI_B_UNDEF |
| 2485 | 0U, // LSL_ZPZI_B_ZERO |
| 2486 | 0U, // LSL_ZPZI_D_UNDEF |
| 2487 | 0U, // LSL_ZPZI_D_ZERO |
| 2488 | 0U, // LSL_ZPZI_H_UNDEF |
| 2489 | 0U, // LSL_ZPZI_H_ZERO |
| 2490 | 0U, // LSL_ZPZI_S_UNDEF |
| 2491 | 0U, // LSL_ZPZI_S_ZERO |
| 2492 | 0U, // LSL_ZPZZ_B_UNDEF |
| 2493 | 0U, // LSL_ZPZZ_B_ZERO |
| 2494 | 0U, // LSL_ZPZZ_D_UNDEF |
| 2495 | 0U, // LSL_ZPZZ_D_ZERO |
| 2496 | 0U, // LSL_ZPZZ_H_UNDEF |
| 2497 | 0U, // LSL_ZPZZ_H_ZERO |
| 2498 | 0U, // LSL_ZPZZ_S_UNDEF |
| 2499 | 0U, // LSL_ZPZZ_S_ZERO |
| 2500 | 0U, // LSR_ZPZI_B_UNDEF |
| 2501 | 0U, // LSR_ZPZI_B_ZERO |
| 2502 | 0U, // LSR_ZPZI_D_UNDEF |
| 2503 | 0U, // LSR_ZPZI_D_ZERO |
| 2504 | 0U, // LSR_ZPZI_H_UNDEF |
| 2505 | 0U, // LSR_ZPZI_H_ZERO |
| 2506 | 0U, // LSR_ZPZI_S_UNDEF |
| 2507 | 0U, // LSR_ZPZI_S_ZERO |
| 2508 | 0U, // LSR_ZPZZ_B_UNDEF |
| 2509 | 0U, // LSR_ZPZZ_B_ZERO |
| 2510 | 0U, // LSR_ZPZZ_D_UNDEF |
| 2511 | 0U, // LSR_ZPZZ_D_ZERO |
| 2512 | 0U, // LSR_ZPZZ_H_UNDEF |
| 2513 | 0U, // LSR_ZPZZ_H_ZERO |
| 2514 | 0U, // LSR_ZPZZ_S_UNDEF |
| 2515 | 0U, // LSR_ZPZZ_S_ZERO |
| 2516 | 0U, // MLA_ZPZZZ_B_UNDEF |
| 2517 | 0U, // MLA_ZPZZZ_D_UNDEF |
| 2518 | 0U, // MLA_ZPZZZ_H_UNDEF |
| 2519 | 0U, // MLA_ZPZZZ_S_UNDEF |
| 2520 | 0U, // MLS_ZPZZZ_B_UNDEF |
| 2521 | 0U, // MLS_ZPZZZ_D_UNDEF |
| 2522 | 0U, // MLS_ZPZZZ_H_UNDEF |
| 2523 | 0U, // MLS_ZPZZZ_S_UNDEF |
| 2524 | 0U, // MOPSMemoryCopyPseudo |
| 2525 | 0U, // MOPSMemoryMovePseudo |
| 2526 | 0U, // MOPSMemorySetPseudo |
| 2527 | 0U, // MOPSMemorySetTaggingPseudo |
| 2528 | 0U, // MOVAZ_2ZMI_H_B_PSEUDO |
| 2529 | 0U, // MOVAZ_2ZMI_H_D_PSEUDO |
| 2530 | 0U, // MOVAZ_2ZMI_H_H_PSEUDO |
| 2531 | 0U, // MOVAZ_2ZMI_H_S_PSEUDO |
| 2532 | 0U, // MOVAZ_2ZMI_V_B_PSEUDO |
| 2533 | 0U, // MOVAZ_2ZMI_V_D_PSEUDO |
| 2534 | 0U, // MOVAZ_2ZMI_V_H_PSEUDO |
| 2535 | 0U, // MOVAZ_2ZMI_V_S_PSEUDO |
| 2536 | 0U, // MOVAZ_4ZMI_H_B_PSEUDO |
| 2537 | 0U, // MOVAZ_4ZMI_H_D_PSEUDO |
| 2538 | 0U, // MOVAZ_4ZMI_H_H_PSEUDO |
| 2539 | 0U, // MOVAZ_4ZMI_H_S_PSEUDO |
| 2540 | 0U, // MOVAZ_4ZMI_V_B_PSEUDO |
| 2541 | 0U, // MOVAZ_4ZMI_V_D_PSEUDO |
| 2542 | 0U, // MOVAZ_4ZMI_V_H_PSEUDO |
| 2543 | 0U, // MOVAZ_4ZMI_V_S_PSEUDO |
| 2544 | 0U, // MOVAZ_VG2_2ZMXI_PSEUDO |
| 2545 | 0U, // MOVAZ_VG4_4ZMXI_PSEUDO |
| 2546 | 0U, // MOVAZ_ZMI_H_B_PSEUDO |
| 2547 | 0U, // MOVAZ_ZMI_H_D_PSEUDO |
| 2548 | 0U, // MOVAZ_ZMI_H_H_PSEUDO |
| 2549 | 0U, // MOVAZ_ZMI_H_Q_PSEUDO |
| 2550 | 0U, // MOVAZ_ZMI_H_S_PSEUDO |
| 2551 | 0U, // MOVAZ_ZMI_V_B_PSEUDO |
| 2552 | 0U, // MOVAZ_ZMI_V_D_PSEUDO |
| 2553 | 0U, // MOVAZ_ZMI_V_H_PSEUDO |
| 2554 | 0U, // MOVAZ_ZMI_V_Q_PSEUDO |
| 2555 | 0U, // MOVAZ_ZMI_V_S_PSEUDO |
| 2556 | 0U, // MOVA_MXI2Z_H_B_PSEUDO |
| 2557 | 0U, // MOVA_MXI2Z_H_D_PSEUDO |
| 2558 | 0U, // MOVA_MXI2Z_H_H_PSEUDO |
| 2559 | 0U, // MOVA_MXI2Z_H_S_PSEUDO |
| 2560 | 0U, // MOVA_MXI2Z_V_B_PSEUDO |
| 2561 | 0U, // MOVA_MXI2Z_V_D_PSEUDO |
| 2562 | 0U, // MOVA_MXI2Z_V_H_PSEUDO |
| 2563 | 0U, // MOVA_MXI2Z_V_S_PSEUDO |
| 2564 | 0U, // MOVA_MXI4Z_H_B_PSEUDO |
| 2565 | 0U, // MOVA_MXI4Z_H_D_PSEUDO |
| 2566 | 0U, // MOVA_MXI4Z_H_H_PSEUDO |
| 2567 | 0U, // MOVA_MXI4Z_H_S_PSEUDO |
| 2568 | 0U, // MOVA_MXI4Z_V_B_PSEUDO |
| 2569 | 0U, // MOVA_MXI4Z_V_D_PSEUDO |
| 2570 | 0U, // MOVA_MXI4Z_V_H_PSEUDO |
| 2571 | 0U, // MOVA_MXI4Z_V_S_PSEUDO |
| 2572 | 0U, // MOVA_VG2_MXI2Z_PSEUDO |
| 2573 | 0U, // MOVA_VG4_MXI4Z_PSEUDO |
| 2574 | 0U, // MOVMCSym |
| 2575 | 0U, // MOVT_TIZ_PSEUDO |
| 2576 | 0U, // MOVaddr |
| 2577 | 0U, // MOVaddrBA |
| 2578 | 0U, // MOVaddrCP |
| 2579 | 0U, // MOVaddrEXT |
| 2580 | 0U, // MOVaddrJT |
| 2581 | 0U, // MOVaddrPAC |
| 2582 | 0U, // MOVaddrTLS |
| 2583 | 0U, // MOVbaseTLS |
| 2584 | 0U, // MOVi32imm |
| 2585 | 0U, // MOVi64imm |
| 2586 | 0U, // MRS_FPCR |
| 2587 | 0U, // MRS_FPSR |
| 2588 | 0U, // MSR_FPCR |
| 2589 | 0U, // MSR_FPMR |
| 2590 | 0U, // MSR_FPSR |
| 2591 | 0U, // MSRpstatePseudo |
| 2592 | 0U, // MUL_ZPZZ_B_UNDEF |
| 2593 | 0U, // MUL_ZPZZ_D_UNDEF |
| 2594 | 0U, // MUL_ZPZZ_H_UNDEF |
| 2595 | 0U, // MUL_ZPZZ_S_UNDEF |
| 2596 | 0U, // NAND_ZZZ |
| 2597 | 0U, // NEG_ZPmZ_B_UNDEF |
| 2598 | 0U, // NEG_ZPmZ_D_UNDEF |
| 2599 | 0U, // NEG_ZPmZ_H_UNDEF |
| 2600 | 0U, // NEG_ZPmZ_S_UNDEF |
| 2601 | 0U, // NOR_ZZZ |
| 2602 | 0U, // NOT_ZPmZ_B_UNDEF |
| 2603 | 0U, // NOT_ZPmZ_D_UNDEF |
| 2604 | 0U, // NOT_ZPmZ_H_UNDEF |
| 2605 | 0U, // NOT_ZPmZ_S_UNDEF |
| 2606 | 0U, // ORNWrr |
| 2607 | 0U, // ORNXrr |
| 2608 | 0U, // ORRWrr |
| 2609 | 0U, // ORRXrr |
| 2610 | 0U, // ORR_ZPZZ_B_ZERO |
| 2611 | 0U, // ORR_ZPZZ_D_ZERO |
| 2612 | 0U, // ORR_ZPZZ_H_ZERO |
| 2613 | 0U, // ORR_ZPZZ_S_ZERO |
| 2614 | 0U, // PAC |
| 2615 | 0U, // PAUTH_EPILOGUE |
| 2616 | 0U, // PAUTH_PROLOGUE |
| 2617 | 0U, // PROBED_STACKALLOC |
| 2618 | 0U, // PROBED_STACKALLOC_DYN |
| 2619 | 0U, // PROBED_STACKALLOC_VAR |
| 2620 | 0U, // PTEST_PP_ANY |
| 2621 | 0U, // PTEST_PP_FIRST |
| 2622 | 0U, // RET_ReallyLR |
| 2623 | 0U, // RequiresZASavePseudo |
| 2624 | 0U, // RequiresZT0SavePseudo |
| 2625 | 0U, // RestoreZAPseudo |
| 2626 | 0U, // SABD_ZPZZ_B_UNDEF |
| 2627 | 0U, // SABD_ZPZZ_D_UNDEF |
| 2628 | 0U, // SABD_ZPZZ_H_UNDEF |
| 2629 | 0U, // SABD_ZPZZ_S_UNDEF |
| 2630 | 0U, // SCVTF_ZPmZ_DtoD_UNDEF |
| 2631 | 0U, // SCVTF_ZPmZ_DtoH_UNDEF |
| 2632 | 0U, // SCVTF_ZPmZ_DtoS_UNDEF |
| 2633 | 0U, // SCVTF_ZPmZ_HtoH_UNDEF |
| 2634 | 0U, // SCVTF_ZPmZ_StoD_UNDEF |
| 2635 | 0U, // SCVTF_ZPmZ_StoH_UNDEF |
| 2636 | 0U, // SCVTF_ZPmZ_StoS_UNDEF |
| 2637 | 0U, // SDIV_ZPZZ_D_UNDEF |
| 2638 | 0U, // SDIV_ZPZZ_S_UNDEF |
| 2639 | 0U, // SDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 2640 | 0U, // SDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 2641 | 0U, // SDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 2642 | 0U, // SDOT_VG2_M2ZZI_BToS_PSEUDO |
| 2643 | 0U, // SDOT_VG2_M2ZZI_HToS_PSEUDO |
| 2644 | 0U, // SDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 2645 | 0U, // SDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 2646 | 0U, // SDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 2647 | 0U, // SDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 2648 | 0U, // SDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 2649 | 0U, // SDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 2650 | 0U, // SDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 2651 | 0U, // SDOT_VG4_M4ZZI_BToS_PSEUDO |
| 2652 | 0U, // SDOT_VG4_M4ZZI_HToS_PSEUDO |
| 2653 | 0U, // SDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 2654 | 0U, // SDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 2655 | 0U, // SDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 2656 | 0U, // SDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 2657 | 0U, // SEH_AddFP |
| 2658 | 0U, // SEH_AllocZ |
| 2659 | 0U, // SEH_EpilogEnd |
| 2660 | 0U, // SEH_EpilogStart |
| 2661 | 0U, // SEH_Nop |
| 2662 | 0U, // SEH_PACSignLR |
| 2663 | 0U, // SEH_PrologEnd |
| 2664 | 0U, // SEH_SaveAnyRegI |
| 2665 | 0U, // SEH_SaveAnyRegIP |
| 2666 | 0U, // SEH_SaveAnyRegQP |
| 2667 | 0U, // SEH_SaveAnyRegQPX |
| 2668 | 0U, // SEH_SaveFPLR |
| 2669 | 0U, // SEH_SaveFPLR_X |
| 2670 | 0U, // SEH_SaveFReg |
| 2671 | 0U, // SEH_SaveFRegP |
| 2672 | 0U, // SEH_SaveFRegP_X |
| 2673 | 0U, // SEH_SaveFReg_X |
| 2674 | 0U, // SEH_SavePReg |
| 2675 | 0U, // SEH_SaveReg |
| 2676 | 0U, // SEH_SaveRegP |
| 2677 | 0U, // SEH_SaveRegP_X |
| 2678 | 0U, // SEH_SaveReg_X |
| 2679 | 0U, // SEH_SaveZReg |
| 2680 | 0U, // SEH_SetFP |
| 2681 | 0U, // SEH_StackAlloc |
| 2682 | 0U, // SHSUB_ZPZZ_B_UNDEF |
| 2683 | 0U, // SHSUB_ZPZZ_D_UNDEF |
| 2684 | 0U, // SHSUB_ZPZZ_H_UNDEF |
| 2685 | 0U, // SHSUB_ZPZZ_S_UNDEF |
| 2686 | 0U, // SMAX_ZPZZ_B_UNDEF |
| 2687 | 0U, // SMAX_ZPZZ_D_UNDEF |
| 2688 | 0U, // SMAX_ZPZZ_H_UNDEF |
| 2689 | 0U, // SMAX_ZPZZ_S_UNDEF |
| 2690 | 0U, // SMEStateAllocPseudo |
| 2691 | 0U, // SMIN_ZPZZ_B_UNDEF |
| 2692 | 0U, // SMIN_ZPZZ_D_UNDEF |
| 2693 | 0U, // SMIN_ZPZZ_H_UNDEF |
| 2694 | 0U, // SMIN_ZPZZ_S_UNDEF |
| 2695 | 0U, // SMLALL_MZZI_BtoS_PSEUDO |
| 2696 | 0U, // SMLALL_MZZI_HtoD_PSEUDO |
| 2697 | 0U, // SMLALL_MZZ_BtoS_PSEUDO |
| 2698 | 0U, // SMLALL_MZZ_HtoD_PSEUDO |
| 2699 | 0U, // SMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 2700 | 0U, // SMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 2701 | 0U, // SMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 2702 | 0U, // SMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 2703 | 0U, // SMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 2704 | 0U, // SMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 2705 | 0U, // SMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 2706 | 0U, // SMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 2707 | 0U, // SMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 2708 | 0U, // SMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 2709 | 0U, // SMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 2710 | 0U, // SMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 2711 | 0U, // SMLAL_MZZI_HtoS_PSEUDO |
| 2712 | 0U, // SMLAL_MZZ_HtoS_PSEUDO |
| 2713 | 0U, // SMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2714 | 0U, // SMLAL_VG2_M2ZZI_S_PSEUDO |
| 2715 | 0U, // SMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 2716 | 0U, // SMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2717 | 0U, // SMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 2718 | 0U, // SMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 2719 | 0U, // SMLSLL_MZZI_BtoS_PSEUDO |
| 2720 | 0U, // SMLSLL_MZZI_HtoD_PSEUDO |
| 2721 | 0U, // SMLSLL_MZZ_BtoS_PSEUDO |
| 2722 | 0U, // SMLSLL_MZZ_HtoD_PSEUDO |
| 2723 | 0U, // SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 2724 | 0U, // SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 2725 | 0U, // SMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 2726 | 0U, // SMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 2727 | 0U, // SMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 2728 | 0U, // SMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 2729 | 0U, // SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 2730 | 0U, // SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 2731 | 0U, // SMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 2732 | 0U, // SMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 2733 | 0U, // SMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 2734 | 0U, // SMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 2735 | 0U, // SMLSL_MZZI_HtoS_PSEUDO |
| 2736 | 0U, // SMLSL_MZZ_HtoS_PSEUDO |
| 2737 | 0U, // SMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2738 | 0U, // SMLSL_VG2_M2ZZI_S_PSEUDO |
| 2739 | 0U, // SMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 2740 | 0U, // SMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2741 | 0U, // SMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 2742 | 0U, // SMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 2743 | 0U, // SMOP4A_M2Z2Z_BToS_PSEUDO |
| 2744 | 0U, // SMOP4A_M2Z2Z_HToS_PSEUDO |
| 2745 | 0U, // SMOP4A_M2Z2Z_HtoD_PSEUDO |
| 2746 | 0U, // SMOP4A_M2ZZ_BToS_PSEUDO |
| 2747 | 0U, // SMOP4A_M2ZZ_HToS_PSEUDO |
| 2748 | 0U, // SMOP4A_M2ZZ_HtoD_PSEUDO |
| 2749 | 0U, // SMOP4A_MZ2Z_BToS_PSEUDO |
| 2750 | 0U, // SMOP4A_MZ2Z_HToS_PSEUDO |
| 2751 | 0U, // SMOP4A_MZ2Z_HtoD_PSEUDO |
| 2752 | 0U, // SMOP4A_MZZ_BToS_PSEUDO |
| 2753 | 0U, // SMOP4A_MZZ_HToS_PSEUDO |
| 2754 | 0U, // SMOP4A_MZZ_HtoD_PSEUDO |
| 2755 | 0U, // SMOP4S_M2Z2Z_BToS_PSEUDO |
| 2756 | 0U, // SMOP4S_M2Z2Z_HToS_PSEUDO |
| 2757 | 0U, // SMOP4S_M2Z2Z_HtoD_PSEUDO |
| 2758 | 0U, // SMOP4S_M2ZZ_BToS_PSEUDO |
| 2759 | 0U, // SMOP4S_M2ZZ_HToS_PSEUDO |
| 2760 | 0U, // SMOP4S_M2ZZ_HtoD_PSEUDO |
| 2761 | 0U, // SMOP4S_MZ2Z_BToS_PSEUDO |
| 2762 | 0U, // SMOP4S_MZ2Z_HToS_PSEUDO |
| 2763 | 0U, // SMOP4S_MZ2Z_HtoD_PSEUDO |
| 2764 | 0U, // SMOP4S_MZZ_BToS_PSEUDO |
| 2765 | 0U, // SMOP4S_MZZ_HToS_PSEUDO |
| 2766 | 0U, // SMOP4S_MZZ_HtoD_PSEUDO |
| 2767 | 0U, // SMOPA_MPPZZ_D_PSEUDO |
| 2768 | 0U, // SMOPA_MPPZZ_HtoS_PSEUDO |
| 2769 | 0U, // SMOPA_MPPZZ_S_PSEUDO |
| 2770 | 0U, // SMOPS_MPPZZ_D_PSEUDO |
| 2771 | 0U, // SMOPS_MPPZZ_HtoS_PSEUDO |
| 2772 | 0U, // SMOPS_MPPZZ_S_PSEUDO |
| 2773 | 0U, // SMULH_ZPZZ_B_UNDEF |
| 2774 | 0U, // SMULH_ZPZZ_D_UNDEF |
| 2775 | 0U, // SMULH_ZPZZ_H_UNDEF |
| 2776 | 0U, // SMULH_ZPZZ_S_UNDEF |
| 2777 | 0U, // SPACE |
| 2778 | 0U, // SQABS_ZPmZ_B_UNDEF |
| 2779 | 0U, // SQABS_ZPmZ_D_UNDEF |
| 2780 | 0U, // SQABS_ZPmZ_H_UNDEF |
| 2781 | 0U, // SQABS_ZPmZ_S_UNDEF |
| 2782 | 0U, // SQADD_ZI_B_PSEUDO |
| 2783 | 0U, // SQADD_ZI_D_PSEUDO |
| 2784 | 0U, // SQADD_ZI_H_PSEUDO |
| 2785 | 0U, // SQADD_ZI_S_PSEUDO |
| 2786 | 0U, // SQNEG_ZPmZ_B_UNDEF |
| 2787 | 0U, // SQNEG_ZPmZ_D_UNDEF |
| 2788 | 0U, // SQNEG_ZPmZ_H_UNDEF |
| 2789 | 0U, // SQNEG_ZPmZ_S_UNDEF |
| 2790 | 0U, // SQRSHL_ZPZZ_B_UNDEF |
| 2791 | 0U, // SQRSHL_ZPZZ_D_UNDEF |
| 2792 | 0U, // SQRSHL_ZPZZ_H_UNDEF |
| 2793 | 0U, // SQRSHL_ZPZZ_S_UNDEF |
| 2794 | 0U, // SQSHLU_ZPZI_B_ZERO |
| 2795 | 0U, // SQSHLU_ZPZI_D_ZERO |
| 2796 | 0U, // SQSHLU_ZPZI_H_ZERO |
| 2797 | 0U, // SQSHLU_ZPZI_S_ZERO |
| 2798 | 0U, // SQSHL_ZPZI_B_UNDEF |
| 2799 | 0U, // SQSHL_ZPZI_B_ZERO |
| 2800 | 0U, // SQSHL_ZPZI_D_UNDEF |
| 2801 | 0U, // SQSHL_ZPZI_D_ZERO |
| 2802 | 0U, // SQSHL_ZPZI_H_UNDEF |
| 2803 | 0U, // SQSHL_ZPZI_H_ZERO |
| 2804 | 0U, // SQSHL_ZPZI_S_UNDEF |
| 2805 | 0U, // SQSHL_ZPZI_S_ZERO |
| 2806 | 0U, // SQSHL_ZPZZ_B_UNDEF |
| 2807 | 0U, // SQSHL_ZPZZ_D_UNDEF |
| 2808 | 0U, // SQSHL_ZPZZ_H_UNDEF |
| 2809 | 0U, // SQSHL_ZPZZ_S_UNDEF |
| 2810 | 0U, // SQSUB_ZI_B_PSEUDO |
| 2811 | 0U, // SQSUB_ZI_D_PSEUDO |
| 2812 | 0U, // SQSUB_ZI_H_PSEUDO |
| 2813 | 0U, // SQSUB_ZI_S_PSEUDO |
| 2814 | 0U, // SRSHL_ZPZZ_B_UNDEF |
| 2815 | 0U, // SRSHL_ZPZZ_D_UNDEF |
| 2816 | 0U, // SRSHL_ZPZZ_H_UNDEF |
| 2817 | 0U, // SRSHL_ZPZZ_S_UNDEF |
| 2818 | 0U, // SRSHR_ZPZI_B_ZERO |
| 2819 | 0U, // SRSHR_ZPZI_D_ZERO |
| 2820 | 0U, // SRSHR_ZPZI_H_ZERO |
| 2821 | 0U, // SRSHR_ZPZI_S_ZERO |
| 2822 | 0U, // STGloop |
| 2823 | 0U, // STGloop_wback |
| 2824 | 0U, // STMOPA_M2ZZZI_BtoS_PSEUDO |
| 2825 | 0U, // STMOPA_M2ZZZI_HtoS_PSEUDO |
| 2826 | 0U, // STR_PPXI |
| 2827 | 0U, // STR_TX_PSEUDO |
| 2828 | 0U, // STR_ZZXI |
| 2829 | 0U, // STR_ZZXI_STRIDED_CONTIGUOUS |
| 2830 | 0U, // STR_ZZZXI |
| 2831 | 0U, // STR_ZZZZXI |
| 2832 | 0U, // STR_ZZZZXI_STRIDED_CONTIGUOUS |
| 2833 | 0U, // STSHH_ATOMIC_STORE_SZ |
| 2834 | 0U, // STZGloop |
| 2835 | 0U, // STZGloop_wback |
| 2836 | 0U, // SUBR_ZI_B_PSEUDO |
| 2837 | 0U, // SUBR_ZI_D_PSEUDO |
| 2838 | 0U, // SUBR_ZI_H_PSEUDO |
| 2839 | 0U, // SUBR_ZI_S_PSEUDO |
| 2840 | 0U, // SUBR_ZPZZ_B_ZERO |
| 2841 | 0U, // SUBR_ZPZZ_D_ZERO |
| 2842 | 0U, // SUBR_ZPZZ_H_ZERO |
| 2843 | 0U, // SUBR_ZPZZ_S_ZERO |
| 2844 | 0U, // SUBSWrr |
| 2845 | 0U, // SUBSXrr |
| 2846 | 0U, // SUBWrr |
| 2847 | 0U, // SUBXrr |
| 2848 | 0U, // SUB_VG2_M2Z2Z_D_PSEUDO |
| 2849 | 0U, // SUB_VG2_M2Z2Z_S_PSEUDO |
| 2850 | 0U, // SUB_VG2_M2ZZ_D_PSEUDO |
| 2851 | 0U, // SUB_VG2_M2ZZ_S_PSEUDO |
| 2852 | 0U, // SUB_VG2_M2Z_D_PSEUDO |
| 2853 | 0U, // SUB_VG2_M2Z_S_PSEUDO |
| 2854 | 0U, // SUB_VG4_M4Z4Z_D_PSEUDO |
| 2855 | 0U, // SUB_VG4_M4Z4Z_S_PSEUDO |
| 2856 | 0U, // SUB_VG4_M4ZZ_D_PSEUDO |
| 2857 | 0U, // SUB_VG4_M4ZZ_S_PSEUDO |
| 2858 | 0U, // SUB_VG4_M4Z_D_PSEUDO |
| 2859 | 0U, // SUB_VG4_M4Z_S_PSEUDO |
| 2860 | 0U, // SUB_ZI_B_PSEUDO |
| 2861 | 0U, // SUB_ZI_D_PSEUDO |
| 2862 | 0U, // SUB_ZI_H_PSEUDO |
| 2863 | 0U, // SUB_ZI_S_PSEUDO |
| 2864 | 0U, // SUB_ZPZZ_B_ZERO |
| 2865 | 0U, // SUB_ZPZZ_D_ZERO |
| 2866 | 0U, // SUB_ZPZZ_H_ZERO |
| 2867 | 0U, // SUB_ZPZZ_S_ZERO |
| 2868 | 0U, // SUDOT_VG2_M2ZZI_BToS_PSEUDO |
| 2869 | 0U, // SUDOT_VG2_M2ZZ_BToS_PSEUDO |
| 2870 | 0U, // SUDOT_VG4_M4ZZI_BToS_PSEUDO |
| 2871 | 0U, // SUDOT_VG4_M4ZZ_BToS_PSEUDO |
| 2872 | 0U, // SUMLALL_MZZI_BtoS_PSEUDO |
| 2873 | 0U, // SUMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 2874 | 0U, // SUMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 2875 | 0U, // SUMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 2876 | 0U, // SUMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 2877 | 0U, // SUMOP4A_M2Z2Z_BToS_PSEUDO |
| 2878 | 0U, // SUMOP4A_M2Z2Z_HtoD_PSEUDO |
| 2879 | 0U, // SUMOP4A_M2ZZ_BToS_PSEUDO |
| 2880 | 0U, // SUMOP4A_M2ZZ_HtoD_PSEUDO |
| 2881 | 0U, // SUMOP4A_MZ2Z_BToS_PSEUDO |
| 2882 | 0U, // SUMOP4A_MZ2Z_HtoD_PSEUDO |
| 2883 | 0U, // SUMOP4A_MZZ_BToS_PSEUDO |
| 2884 | 0U, // SUMOP4A_MZZ_HtoD_PSEUDO |
| 2885 | 0U, // SUMOP4S_M2Z2Z_BToS_PSEUDO |
| 2886 | 0U, // SUMOP4S_M2Z2Z_HtoD_PSEUDO |
| 2887 | 0U, // SUMOP4S_M2ZZ_BToS_PSEUDO |
| 2888 | 0U, // SUMOP4S_M2ZZ_HtoD_PSEUDO |
| 2889 | 0U, // SUMOP4S_MZ2Z_BToS_PSEUDO |
| 2890 | 0U, // SUMOP4S_MZ2Z_HtoD_PSEUDO |
| 2891 | 0U, // SUMOP4S_MZZ_BToS_PSEUDO |
| 2892 | 0U, // SUMOP4S_MZZ_HtoD_PSEUDO |
| 2893 | 0U, // SUMOPA_MPPZZ_D_PSEUDO |
| 2894 | 0U, // SUMOPA_MPPZZ_S_PSEUDO |
| 2895 | 0U, // SUMOPS_MPPZZ_D_PSEUDO |
| 2896 | 0U, // SUMOPS_MPPZZ_S_PSEUDO |
| 2897 | 0U, // SUTMOPA_M2ZZZI_BtoS_PSEUDO |
| 2898 | 0U, // SUVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 2899 | 0U, // SVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 2900 | 0U, // SVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 2901 | 0U, // SVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 2902 | 0U, // SXTB_ZPmZ_D_UNDEF |
| 2903 | 0U, // SXTB_ZPmZ_H_UNDEF |
| 2904 | 0U, // SXTB_ZPmZ_S_UNDEF |
| 2905 | 0U, // SXTH_ZPmZ_D_UNDEF |
| 2906 | 0U, // SXTH_ZPmZ_S_UNDEF |
| 2907 | 0U, // SXTW_ZPmZ_D_UNDEF |
| 2908 | 0U, // SpeculationBarrierISBDSBEndBB |
| 2909 | 0U, // SpeculationBarrierSBEndBB |
| 2910 | 0U, // SpeculationSafeValueW |
| 2911 | 0U, // SpeculationSafeValueX |
| 2912 | 0U, // StoreSwiftAsyncContext |
| 2913 | 0U, // TAGPstack |
| 2914 | 0U, // TCRETURNdi |
| 2915 | 0U, // TCRETURNri |
| 2916 | 0U, // TCRETURNriALL |
| 2917 | 0U, // TCRETURNrinotx16 |
| 2918 | 0U, // TCRETURNrix16x17 |
| 2919 | 0U, // TCRETURNrix17 |
| 2920 | 26054U, // TLSDESCCALL |
| 2921 | 0U, // TLSDESC_AUTH_CALLSEQ |
| 2922 | 0U, // TLSDESC_CALLSEQ |
| 2923 | 0U, // UABD_ZPZZ_B_UNDEF |
| 2924 | 0U, // UABD_ZPZZ_D_UNDEF |
| 2925 | 0U, // UABD_ZPZZ_H_UNDEF |
| 2926 | 0U, // UABD_ZPZZ_S_UNDEF |
| 2927 | 0U, // UCVTF_ZPmZ_DtoD_UNDEF |
| 2928 | 0U, // UCVTF_ZPmZ_DtoH_UNDEF |
| 2929 | 0U, // UCVTF_ZPmZ_DtoS_UNDEF |
| 2930 | 0U, // UCVTF_ZPmZ_HtoH_UNDEF |
| 2931 | 0U, // UCVTF_ZPmZ_StoD_UNDEF |
| 2932 | 0U, // UCVTF_ZPmZ_StoH_UNDEF |
| 2933 | 0U, // UCVTF_ZPmZ_StoS_UNDEF |
| 2934 | 0U, // UDIV_ZPZZ_D_UNDEF |
| 2935 | 0U, // UDIV_ZPZZ_S_UNDEF |
| 2936 | 0U, // UDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 2937 | 0U, // UDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 2938 | 0U, // UDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 2939 | 0U, // UDOT_VG2_M2ZZI_BToS_PSEUDO |
| 2940 | 0U, // UDOT_VG2_M2ZZI_HToS_PSEUDO |
| 2941 | 0U, // UDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 2942 | 0U, // UDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 2943 | 0U, // UDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 2944 | 0U, // UDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 2945 | 0U, // UDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 2946 | 0U, // UDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 2947 | 0U, // UDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 2948 | 0U, // UDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 2949 | 0U, // UDOT_VG4_M4ZZI_HToS_PSEUDO |
| 2950 | 0U, // UDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 2951 | 0U, // UDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 2952 | 0U, // UDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 2953 | 0U, // UDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 2954 | 0U, // UHSUB_ZPZZ_B_UNDEF |
| 2955 | 0U, // UHSUB_ZPZZ_D_UNDEF |
| 2956 | 0U, // UHSUB_ZPZZ_H_UNDEF |
| 2957 | 0U, // UHSUB_ZPZZ_S_UNDEF |
| 2958 | 0U, // UMAX_ZPZZ_B_UNDEF |
| 2959 | 0U, // UMAX_ZPZZ_D_UNDEF |
| 2960 | 0U, // UMAX_ZPZZ_H_UNDEF |
| 2961 | 0U, // UMAX_ZPZZ_S_UNDEF |
| 2962 | 0U, // UMIN_ZPZZ_B_UNDEF |
| 2963 | 0U, // UMIN_ZPZZ_D_UNDEF |
| 2964 | 0U, // UMIN_ZPZZ_H_UNDEF |
| 2965 | 0U, // UMIN_ZPZZ_S_UNDEF |
| 2966 | 0U, // UMLALL_MZZI_BtoS_PSEUDO |
| 2967 | 0U, // UMLALL_MZZI_HtoD_PSEUDO |
| 2968 | 0U, // UMLALL_MZZ_BtoS_PSEUDO |
| 2969 | 0U, // UMLALL_MZZ_HtoD_PSEUDO |
| 2970 | 0U, // UMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 2971 | 0U, // UMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 2972 | 0U, // UMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 2973 | 0U, // UMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 2974 | 0U, // UMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 2975 | 0U, // UMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 2976 | 0U, // UMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 2977 | 0U, // UMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 2978 | 0U, // UMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 2979 | 0U, // UMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 2980 | 0U, // UMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 2981 | 0U, // UMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 2982 | 0U, // UMLAL_MZZI_HtoS_PSEUDO |
| 2983 | 0U, // UMLAL_MZZ_HtoS_PSEUDO |
| 2984 | 0U, // UMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2985 | 0U, // UMLAL_VG2_M2ZZI_S_PSEUDO |
| 2986 | 0U, // UMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 2987 | 0U, // UMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2988 | 0U, // UMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 2989 | 0U, // UMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 2990 | 0U, // UMLSLL_MZZI_BtoS_PSEUDO |
| 2991 | 0U, // UMLSLL_MZZI_HtoD_PSEUDO |
| 2992 | 0U, // UMLSLL_MZZ_BtoS_PSEUDO |
| 2993 | 0U, // UMLSLL_MZZ_HtoD_PSEUDO |
| 2994 | 0U, // UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 2995 | 0U, // UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 2996 | 0U, // UMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 2997 | 0U, // UMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 2998 | 0U, // UMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 2999 | 0U, // UMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 3000 | 0U, // UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3001 | 0U, // UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 3002 | 0U, // UMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 3003 | 0U, // UMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 3004 | 0U, // UMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 3005 | 0U, // UMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 3006 | 0U, // UMLSL_MZZI_HtoS_PSEUDO |
| 3007 | 0U, // UMLSL_MZZ_HtoS_PSEUDO |
| 3008 | 0U, // UMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 3009 | 0U, // UMLSL_VG2_M2ZZI_S_PSEUDO |
| 3010 | 0U, // UMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 3011 | 0U, // UMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 3012 | 0U, // UMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 3013 | 0U, // UMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 3014 | 0U, // UMOP4A_M2Z2Z_BToS_PSEUDO |
| 3015 | 0U, // UMOP4A_M2Z2Z_HToS_PSEUDO |
| 3016 | 0U, // UMOP4A_M2Z2Z_HtoD_PSEUDO |
| 3017 | 0U, // UMOP4A_M2ZZ_BToS_PSEUDO |
| 3018 | 0U, // UMOP4A_M2ZZ_HToS_PSEUDO |
| 3019 | 0U, // UMOP4A_M2ZZ_HtoD_PSEUDO |
| 3020 | 0U, // UMOP4A_MZ2Z_BToS_PSEUDO |
| 3021 | 0U, // UMOP4A_MZ2Z_HToS_PSEUDO |
| 3022 | 0U, // UMOP4A_MZ2Z_HtoD_PSEUDO |
| 3023 | 0U, // UMOP4A_MZZ_BToS_PSEUDO |
| 3024 | 0U, // UMOP4A_MZZ_HToS_PSEUDO |
| 3025 | 0U, // UMOP4A_MZZ_HtoD_PSEUDO |
| 3026 | 0U, // UMOP4S_M2Z2Z_BToS_PSEUDO |
| 3027 | 0U, // UMOP4S_M2Z2Z_HToS_PSEUDO |
| 3028 | 0U, // UMOP4S_M2Z2Z_HtoD_PSEUDO |
| 3029 | 0U, // UMOP4S_M2ZZ_BToS_PSEUDO |
| 3030 | 0U, // UMOP4S_M2ZZ_HToS_PSEUDO |
| 3031 | 0U, // UMOP4S_M2ZZ_HtoD_PSEUDO |
| 3032 | 0U, // UMOP4S_MZ2Z_BToS_PSEUDO |
| 3033 | 0U, // UMOP4S_MZ2Z_HToS_PSEUDO |
| 3034 | 0U, // UMOP4S_MZ2Z_HtoD_PSEUDO |
| 3035 | 0U, // UMOP4S_MZZ_BToS_PSEUDO |
| 3036 | 0U, // UMOP4S_MZZ_HToS_PSEUDO |
| 3037 | 0U, // UMOP4S_MZZ_HtoD_PSEUDO |
| 3038 | 0U, // UMOPA_MPPZZ_D_PSEUDO |
| 3039 | 0U, // UMOPA_MPPZZ_HtoS_PSEUDO |
| 3040 | 0U, // UMOPA_MPPZZ_S_PSEUDO |
| 3041 | 0U, // UMOPS_MPPZZ_D_PSEUDO |
| 3042 | 0U, // UMOPS_MPPZZ_HtoS_PSEUDO |
| 3043 | 0U, // UMOPS_MPPZZ_S_PSEUDO |
| 3044 | 0U, // UMULH_ZPZZ_B_UNDEF |
| 3045 | 0U, // UMULH_ZPZZ_D_UNDEF |
| 3046 | 0U, // UMULH_ZPZZ_H_UNDEF |
| 3047 | 0U, // UMULH_ZPZZ_S_UNDEF |
| 3048 | 0U, // UQADD_ZI_B_PSEUDO |
| 3049 | 0U, // UQADD_ZI_D_PSEUDO |
| 3050 | 0U, // UQADD_ZI_H_PSEUDO |
| 3051 | 0U, // UQADD_ZI_S_PSEUDO |
| 3052 | 0U, // UQRSHL_ZPZZ_B_UNDEF |
| 3053 | 0U, // UQRSHL_ZPZZ_D_UNDEF |
| 3054 | 0U, // UQRSHL_ZPZZ_H_UNDEF |
| 3055 | 0U, // UQRSHL_ZPZZ_S_UNDEF |
| 3056 | 0U, // UQSHL_ZPZI_B_UNDEF |
| 3057 | 0U, // UQSHL_ZPZI_B_ZERO |
| 3058 | 0U, // UQSHL_ZPZI_D_UNDEF |
| 3059 | 0U, // UQSHL_ZPZI_D_ZERO |
| 3060 | 0U, // UQSHL_ZPZI_H_UNDEF |
| 3061 | 0U, // UQSHL_ZPZI_H_ZERO |
| 3062 | 0U, // UQSHL_ZPZI_S_UNDEF |
| 3063 | 0U, // UQSHL_ZPZI_S_ZERO |
| 3064 | 0U, // UQSHL_ZPZZ_B_UNDEF |
| 3065 | 0U, // UQSHL_ZPZZ_D_UNDEF |
| 3066 | 0U, // UQSHL_ZPZZ_H_UNDEF |
| 3067 | 0U, // UQSHL_ZPZZ_S_UNDEF |
| 3068 | 0U, // UQSUB_ZI_B_PSEUDO |
| 3069 | 0U, // UQSUB_ZI_D_PSEUDO |
| 3070 | 0U, // UQSUB_ZI_H_PSEUDO |
| 3071 | 0U, // UQSUB_ZI_S_PSEUDO |
| 3072 | 0U, // URECPE_ZPmZ_S_UNDEF |
| 3073 | 0U, // URSHL_ZPZZ_B_UNDEF |
| 3074 | 0U, // URSHL_ZPZZ_D_UNDEF |
| 3075 | 0U, // URSHL_ZPZZ_H_UNDEF |
| 3076 | 0U, // URSHL_ZPZZ_S_UNDEF |
| 3077 | 0U, // URSHR_ZPZI_B_ZERO |
| 3078 | 0U, // URSHR_ZPZI_D_ZERO |
| 3079 | 0U, // URSHR_ZPZI_H_ZERO |
| 3080 | 0U, // URSHR_ZPZI_S_ZERO |
| 3081 | 0U, // URSQRTE_ZPmZ_S_UNDEF |
| 3082 | 0U, // USDOT_VG2_M2Z2Z_BToS_PSEUDO |
| 3083 | 0U, // USDOT_VG2_M2ZZI_BToS_PSEUDO |
| 3084 | 0U, // USDOT_VG2_M2ZZ_BToS_PSEUDO |
| 3085 | 0U, // USDOT_VG4_M4Z4Z_BToS_PSEUDO |
| 3086 | 0U, // USDOT_VG4_M4ZZI_BToS_PSEUDO |
| 3087 | 0U, // USDOT_VG4_M4ZZ_BToS_PSEUDO |
| 3088 | 0U, // USMLALL_MZZI_BtoS_PSEUDO |
| 3089 | 0U, // USMLALL_MZZ_BtoS_PSEUDO |
| 3090 | 0U, // USMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 3091 | 0U, // USMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 3092 | 0U, // USMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 3093 | 0U, // USMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3094 | 0U, // USMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 3095 | 0U, // USMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 3096 | 0U, // USMOP4A_M2Z2Z_BToS_PSEUDO |
| 3097 | 0U, // USMOP4A_M2Z2Z_HtoD_PSEUDO |
| 3098 | 0U, // USMOP4A_M2ZZ_BToS_PSEUDO |
| 3099 | 0U, // USMOP4A_M2ZZ_HtoD_PSEUDO |
| 3100 | 0U, // USMOP4A_MZ2Z_BToS_PSEUDO |
| 3101 | 0U, // USMOP4A_MZ2Z_HtoD_PSEUDO |
| 3102 | 0U, // USMOP4A_MZZ_BToS_PSEUDO |
| 3103 | 0U, // USMOP4A_MZZ_HtoD_PSEUDO |
| 3104 | 0U, // USMOP4S_M2Z2Z_BToS_PSEUDO |
| 3105 | 0U, // USMOP4S_M2Z2Z_HtoD_PSEUDO |
| 3106 | 0U, // USMOP4S_M2ZZ_BToS_PSEUDO |
| 3107 | 0U, // USMOP4S_M2ZZ_HtoD_PSEUDO |
| 3108 | 0U, // USMOP4S_MZ2Z_BToS_PSEUDO |
| 3109 | 0U, // USMOP4S_MZ2Z_HtoD_PSEUDO |
| 3110 | 0U, // USMOP4S_MZZ_BToS_PSEUDO |
| 3111 | 0U, // USMOP4S_MZZ_HtoD_PSEUDO |
| 3112 | 0U, // USMOPA_MPPZZ_D_PSEUDO |
| 3113 | 0U, // USMOPA_MPPZZ_S_PSEUDO |
| 3114 | 0U, // USMOPS_MPPZZ_D_PSEUDO |
| 3115 | 0U, // USMOPS_MPPZZ_S_PSEUDO |
| 3116 | 0U, // USTMOPA_M2ZZZI_BtoS_PSEUDO |
| 3117 | 0U, // USVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 3118 | 0U, // UTMOPA_M2ZZZI_BtoS_PSEUDO |
| 3119 | 0U, // UTMOPA_M2ZZZI_HtoS_PSEUDO |
| 3120 | 0U, // UVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 3121 | 0U, // UVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 3122 | 0U, // UVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 3123 | 0U, // UXTB_ZPmZ_D_UNDEF |
| 3124 | 0U, // UXTB_ZPmZ_H_UNDEF |
| 3125 | 0U, // UXTB_ZPmZ_S_UNDEF |
| 3126 | 0U, // UXTH_ZPmZ_D_UNDEF |
| 3127 | 0U, // UXTH_ZPmZ_S_UNDEF |
| 3128 | 0U, // UXTW_ZPmZ_D_UNDEF |
| 3129 | 0U, // ZERO_MXI_2Z_PSEUDO |
| 3130 | 0U, // ZERO_MXI_4Z_PSEUDO |
| 3131 | 0U, // ZERO_MXI_VG2_2Z_PSEUDO |
| 3132 | 0U, // ZERO_MXI_VG2_4Z_PSEUDO |
| 3133 | 0U, // ZERO_MXI_VG2_Z_PSEUDO |
| 3134 | 0U, // ZERO_MXI_VG4_2Z_PSEUDO |
| 3135 | 0U, // ZERO_MXI_VG4_4Z_PSEUDO |
| 3136 | 0U, // ZERO_MXI_VG4_Z_PSEUDO |
| 3137 | 0U, // ZERO_M_PSEUDO |
| 3138 | 0U, // ZERO_T_PSEUDO |
| 3139 | 2121106U, // ABSWr |
| 3140 | 2121106U, // ABSXr |
| 3141 | 270572946U, // ABS_ZPmZ_B |
| 3142 | 270589330U, // ABS_ZPmZ_D |
| 3143 | 541138322U, // ABS_ZPmZ_H |
| 3144 | 270622098U, // ABS_ZPmZ_S |
| 3145 | 807443858U, // ABS_ZPzZ_B |
| 3146 | 807460242U, // ABS_ZPzZ_D |
| 3147 | 1080106386U, // ABS_ZPzZ_H |
| 3148 | 807493010U, // ABS_ZPzZ_S |
| 3149 | 1350671762U, // ABSv16i8 |
| 3150 | 2121106U, // ABSv1i64 |
| 3151 | 1352768914U, // ABSv2i32 |
| 3152 | 1354866066U, // ABSv2i64 |
| 3153 | 1356963218U, // ABSv4i16 |
| 3154 | 1359060370U, // ABSv4i32 |
| 3155 | 1361157522U, // ABSv8i16 |
| 3156 | 1363254674U, // ABSv8i8 |
| 3157 | 1612760978U, // ADCLB_ZZZ_D |
| 3158 | 1881229202U, // ADCLB_ZZZ_S |
| 3159 | 1612767212U, // ADCLT_ZZZ_D |
| 3160 | 1881235436U, // ADCLT_ZZZ_S |
| 3161 | 2121145U, // ADCSWr |
| 3162 | 2121145U, // ADCSXr |
| 3163 | 2116325U, // ADCWr |
| 3164 | 2116325U, // ADCXr |
| 3165 | 2117045U, // ADDG |
| 3166 | 541180745U, // ADDHA_MPPZ_D |
| 3167 | 541180745U, // ADDHA_MPPZ_S |
| 3168 | 2149615735U, // ADDHNB_ZZZ_B |
| 3169 | 2439055479U, // ADDHNB_ZZZ_H |
| 3170 | 2686535799U, // ADDHNB_ZZZ_S |
| 3171 | 2954928340U, // ADDHNT_ZZZ_B |
| 3172 | 2441158868U, // ADDHNT_ZZZ_H |
| 3173 | 1612800212U, // ADDHNT_ZZZ_S |
| 3174 | 1352767431U, // ADDHNv2i64_v2i32 |
| 3175 | 3238134186U, // ADDHNv2i64_v4i32 |
| 3176 | 1356961735U, // ADDHNv4i32_v4i16 |
| 3177 | 3240231338U, // ADDHNv4i32_v8i16 |
| 3178 | 3229745578U, // ADDHNv8i16_v16i8 |
| 3179 | 1363253191U, // ADDHNv8i16_v8i8 |
| 3180 | 2119009U, // ADDPL_XXI |
| 3181 | 2122136U, // ADDPT_shift |
| 3182 | 807442726U, // ADDP_ZPmZ_B |
| 3183 | 807459110U, // ADDP_ZPmZ_D |
| 3184 | 543234342U, // ADDP_ZPmZ_H |
| 3185 | 807491878U, // ADDP_ZPmZ_S |
| 3186 | 1350670630U, // ADDPv16i8 |
| 3187 | 1352767782U, // ADDPv2i32 |
| 3188 | 1354864934U, // ADDPv2i64 |
| 3189 | 1344297254U, // ADDPv2i64p |
| 3190 | 1356962086U, // ADDPv4i16 |
| 3191 | 1359059238U, // ADDPv4i32 |
| 3192 | 1361156390U, // ADDPv8i16 |
| 3193 | 1363253542U, // ADDPv8i8 |
| 3194 | 3491797496U, // ADDQP_ZZZ_B |
| 3195 | 2686507512U, // ADDQP_ZZZ_D |
| 3196 | 2443254264U, // ADDQP_ZZZ_H |
| 3197 | 3760282104U, // ADDQP_ZZZ_S |
| 3198 | 813802257U, // ADDQV_VPZ_B |
| 3199 | 817996561U, // ADDQV_VPZ_D |
| 3200 | 824288017U, // ADDQV_VPZ_H |
| 3201 | 822190865U, // ADDQV_VPZ_S |
| 3202 | 2119088U, // ADDSPL_XXI |
| 3203 | 3491797244U, // ADDSUBP_ZZZ_B |
| 3204 | 2686507260U, // ADDSUBP_ZZZ_D |
| 3205 | 2443254012U, // ADDSUBP_ZZZ_H |
| 3206 | 3760281852U, // ADDSUBP_ZZZ_S |
| 3207 | 2119360U, // ADDSVL_XXI |
| 3208 | 2121157U, // ADDSWri |
| 3209 | 2121157U, // ADDSWrs |
| 3210 | 2121157U, // ADDSWrx |
| 3211 | 2121157U, // ADDSXri |
| 3212 | 2121157U, // ADDSXrs |
| 3213 | 2121157U, // ADDSXrx |
| 3214 | 2121157U, // ADDSXrx64 |
| 3215 | 541181240U, // ADDVA_MPPZ_D |
| 3216 | 541181240U, // ADDVA_MPPZ_S |
| 3217 | 2119347U, // ADDVL_XXI |
| 3218 | 1344299657U, // ADDVv16i8v |
| 3219 | 1344299657U, // ADDVv4i16v |
| 3220 | 1344299657U, // ADDVv4i32v |
| 3221 | 1344299657U, // ADDVv8i16v |
| 3222 | 1344299657U, // ADDVv8i8v |
| 3223 | 2116587U, // ADDWri |
| 3224 | 2116587U, // ADDWrs |
| 3225 | 2116587U, // ADDWrx |
| 3226 | 2116587U, // ADDXri |
| 3227 | 2116587U, // ADDXrs |
| 3228 | 2116587U, // ADDXrx |
| 3229 | 2116587U, // ADDXrx64 |
| 3230 | 2445429739U, // ADD_VG2_2ZZ_B |
| 3231 | 2447543275U, // ADD_VG2_2ZZ_D |
| 3232 | 2449656811U, // ADD_VG2_2ZZ_H |
| 3233 | 2451770347U, // ADD_VG2_2ZZ_S |
| 3234 | 4064496619U, // ADD_VG2_M2Z2Z_D |
| 3235 | 4064513003U, // ADD_VG2_M2Z2Z_S |
| 3236 | 4064496619U, // ADD_VG2_M2ZZ_D |
| 3237 | 4064513003U, // ADD_VG2_M2ZZ_S |
| 3238 | 4064496619U, // ADD_VG2_M2Z_D |
| 3239 | 4064513003U, // ADD_VG2_M2Z_S |
| 3240 | 2445429739U, // ADD_VG4_4ZZ_B |
| 3241 | 2447543275U, // ADD_VG4_4ZZ_D |
| 3242 | 2449656811U, // ADD_VG4_4ZZ_H |
| 3243 | 2451770347U, // ADD_VG4_4ZZ_S |
| 3244 | 37964779U, // ADD_VG4_M4Z4Z_D |
| 3245 | 37981163U, // ADD_VG4_M4Z4Z_S |
| 3246 | 37964779U, // ADD_VG4_M4ZZ_D |
| 3247 | 37981163U, // ADD_VG4_M4ZZ_S |
| 3248 | 37964779U, // ADD_VG4_M4Z_D |
| 3249 | 37981163U, // ADD_VG4_M4Z_S |
| 3250 | 3491793899U, // ADD_ZI_B |
| 3251 | 2686503915U, // ADD_ZI_D |
| 3252 | 2443250667U, // ADD_ZI_H |
| 3253 | 3760278507U, // ADD_ZI_S |
| 3254 | 807439339U, // ADD_ZPmZ_B |
| 3255 | 807461272U, // ADD_ZPmZ_CPA |
| 3256 | 807455723U, // ADD_ZPmZ_D |
| 3257 | 543230955U, // ADD_ZPmZ_H |
| 3258 | 807488491U, // ADD_ZPmZ_S |
| 3259 | 3491793899U, // ADD_ZZZ_B |
| 3260 | 2686509464U, // ADD_ZZZ_CPA |
| 3261 | 2686503915U, // ADD_ZZZ_D |
| 3262 | 2443250667U, // ADD_ZZZ_H |
| 3263 | 3760278507U, // ADD_ZZZ_S |
| 3264 | 1350667243U, // ADDv16i8 |
| 3265 | 2116587U, // ADDv1i64 |
| 3266 | 1352764395U, // ADDv2i32 |
| 3267 | 1354861547U, // ADDv2i64 |
| 3268 | 1356958699U, // ADDv4i16 |
| 3269 | 1359055851U, // ADDv4i32 |
| 3270 | 1361153003U, // ADDv8i16 |
| 3271 | 1363250155U, // ADDv8i8 |
| 3272 | 270556098U, // ADR |
| 3273 | 270555647U, // ADRP |
| 3274 | 2724256706U, // ADR_LSL_ZZZ_D_0 |
| 3275 | 2724256706U, // ADR_LSL_ZZZ_D_1 |
| 3276 | 2724256706U, // ADR_LSL_ZZZ_D_2 |
| 3277 | 2724256706U, // ADR_LSL_ZZZ_D_3 |
| 3278 | 3798031298U, // ADR_LSL_ZZZ_S_0 |
| 3279 | 3798031298U, // ADR_LSL_ZZZ_S_1 |
| 3280 | 3798031298U, // ADR_LSL_ZZZ_S_2 |
| 3281 | 3798031298U, // ADR_LSL_ZZZ_S_3 |
| 3282 | 2724256706U, // ADR_SXTW_ZZZ_D_0 |
| 3283 | 2724256706U, // ADR_SXTW_ZZZ_D_1 |
| 3284 | 2724256706U, // ADR_SXTW_ZZZ_D_2 |
| 3285 | 2724256706U, // ADR_SXTW_ZZZ_D_3 |
| 3286 | 2724256706U, // ADR_UXTW_ZZZ_D_0 |
| 3287 | 2724256706U, // ADR_UXTW_ZZZ_D_1 |
| 3288 | 2724256706U, // ADR_UXTW_ZZZ_D_2 |
| 3289 | 2724256706U, // ADR_UXTW_ZZZ_D_3 |
| 3290 | 2445429495U, // AESDIMC_2ZZI_B |
| 3291 | 2445429495U, // AESDIMC_4ZZI_B |
| 3292 | 2445429911U, // AESD_2ZZI_B |
| 3293 | 2445429911U, // AESD_4ZZI_B |
| 3294 | 3491794071U, // AESD_ZZZ_B |
| 3295 | 3229748375U, // AESDrr |
| 3296 | 2445429487U, // AESEMC_2ZZI_B |
| 3297 | 2445429487U, // AESEMC_4ZZI_B |
| 3298 | 2445430099U, // AESE_2ZZI_B |
| 3299 | 2445430099U, // AESE_4ZZI_B |
| 3300 | 3491794259U, // AESE_ZZZ_B |
| 3301 | 3229748563U, // AESErr |
| 3302 | 3491793664U, // AESIMC_ZZ_B |
| 3303 | 1350667008U, // AESIMCrr |
| 3304 | 3491793672U, // AESMC_ZZ_B |
| 3305 | 1350667016U, // AESMCrr |
| 3306 | 813802264U, // ANDQV_VPZ_B |
| 3307 | 817996568U, // ANDQV_VPZ_D |
| 3308 | 824288024U, // ANDQV_VPZ_H |
| 3309 | 822190872U, // ANDQV_VPZ_S |
| 3310 | 2121164U, // ANDSWri |
| 3311 | 2121164U, // ANDSWrs |
| 3312 | 2121164U, // ANDSXri |
| 3313 | 2121164U, // ANDSXrs |
| 3314 | 807443916U, // ANDS_PPzPP |
| 3315 | 254621U, // ANDV_VPZ_B |
| 3316 | 579084957U, // ANDV_VPZ_D |
| 3317 | 581198493U, // ANDV_VPZ_H |
| 3318 | 562340509U, // ANDV_VPZ_S |
| 3319 | 2116717U, // ANDWri |
| 3320 | 2116717U, // ANDWrs |
| 3321 | 2116717U, // ANDXri |
| 3322 | 2116717U, // ANDXrs |
| 3323 | 807439469U, // AND_PPzPP |
| 3324 | 2686504045U, // AND_ZI |
| 3325 | 807439469U, // AND_ZPmZ_B |
| 3326 | 807455853U, // AND_ZPmZ_D |
| 3327 | 543231085U, // AND_ZPmZ_H |
| 3328 | 807488621U, // AND_ZPmZ_S |
| 3329 | 2686504045U, // AND_ZZZ |
| 3330 | 1350667373U, // ANDv16i8 |
| 3331 | 1363250285U, // ANDv8i8 |
| 3332 | 23931U, // APAS |
| 3333 | 807439505U, // ASRD_ZPmI_B |
| 3334 | 807455889U, // ASRD_ZPmI_D |
| 3335 | 543231121U, // ASRD_ZPmI_H |
| 3336 | 807488657U, // ASRD_ZPmI_S |
| 3337 | 807443603U, // ASRR_ZPmZ_B |
| 3338 | 807459987U, // ASRR_ZPmZ_D |
| 3339 | 543235219U, // ASRR_ZPmZ_H |
| 3340 | 807492755U, // ASRR_ZPmZ_S |
| 3341 | 2120869U, // ASRVWr |
| 3342 | 2120869U, // ASRVXr |
| 3343 | 807443621U, // ASR_WIDE_ZPmZ_B |
| 3344 | 543235237U, // ASR_WIDE_ZPmZ_H |
| 3345 | 807492773U, // ASR_WIDE_ZPmZ_S |
| 3346 | 3491798181U, // ASR_WIDE_ZZZ_B |
| 3347 | 2443254949U, // ASR_WIDE_ZZZ_H |
| 3348 | 3760282789U, // ASR_WIDE_ZZZ_S |
| 3349 | 807443621U, // ASR_ZPmI_B |
| 3350 | 807460005U, // ASR_ZPmI_D |
| 3351 | 543235237U, // ASR_ZPmI_H |
| 3352 | 807492773U, // ASR_ZPmI_S |
| 3353 | 807443621U, // ASR_ZPmZ_B |
| 3354 | 807460005U, // ASR_ZPmZ_D |
| 3355 | 543235237U, // ASR_ZPmZ_H |
| 3356 | 807492773U, // ASR_ZPmZ_S |
| 3357 | 3491798181U, // ASR_ZZI_B |
| 3358 | 2686508197U, // ASR_ZZI_D |
| 3359 | 2443254949U, // ASR_ZZI_H |
| 3360 | 3760282789U, // ASR_ZZI_S |
| 3361 | 807715643U, // AUTDA |
| 3362 | 807716530U, // AUTDB |
| 3363 | 312690U, // AUTDZA |
| 3364 | 314049U, // AUTDZB |
| 3365 | 807715671U, // AUTIA |
| 3366 | 9891U, // AUTIA1716 |
| 3367 | 9930U, // AUTIA171615 |
| 3368 | 10018U, // AUTIASP |
| 3369 | 330529U, // AUTIASPPCi |
| 3370 | 23454U, // AUTIASPPCr |
| 3371 | 10009U, // AUTIAZ |
| 3372 | 807716567U, // AUTIB |
| 3373 | 9900U, // AUTIB1716 |
| 3374 | 9954U, // AUTIB171615 |
| 3375 | 9882U, // AUTIBSP |
| 3376 | 330551U, // AUTIBSPPCi |
| 3377 | 23478U, // AUTIBSPPCr |
| 3378 | 9864U, // AUTIBZ |
| 3379 | 312706U, // AUTIZA |
| 3380 | 314065U, // AUTIZB |
| 3381 | 11502U, // AXFLAG |
| 3382 | 329101U, // B |
| 3383 | 1350673614U, // BCAX |
| 3384 | 2686510286U, // BCAX_ZZZZ |
| 3385 | 353790U, // BCcc |
| 3386 | 3491797297U, // BDEP_ZZZ_B |
| 3387 | 2686507313U, // BDEP_ZZZ_D |
| 3388 | 2443254065U, // BDEP_ZZZ_H |
| 3389 | 3760281905U, // BDEP_ZZZ_S |
| 3390 | 3491799596U, // BEXT_ZZZ_B |
| 3391 | 2686509612U, // BEXT_ZZZ_D |
| 3392 | 2443256364U, // BEXT_ZZZ_H |
| 3393 | 3760284204U, // BEXT_ZZZ_S |
| 3394 | 3231850830U, // BF16DOTlanev4bf16 |
| 3395 | 3238142286U, // BF16DOTlanev8bf16 |
| 3396 | 1361155710U, // BF1CVTL |
| 3397 | 1361150340U, // BF1CVTL2 |
| 3398 | 583082149U, // BF1CVTLT_ZZ_BtoH |
| 3399 | 583194238U, // BF1CVTL_2ZZ_BtoH |
| 3400 | 583197153U, // BF1CVT_2ZZ_BtoH |
| 3401 | 583082465U, // BF1CVT_ZZ_BtoH |
| 3402 | 1361155719U, // BF2CVTL |
| 3403 | 1361150350U, // BF2CVTL2 |
| 3404 | 583082159U, // BF2CVTLT_ZZ_BtoH |
| 3405 | 583194247U, // BF2CVTL_2ZZ_BtoH |
| 3406 | 583197161U, // BF2CVT_2ZZ_BtoH |
| 3407 | 583082473U, // BF2CVT_ZZ_BtoH |
| 3408 | 4064644097U, // BFADD_VG2_M2Z_H |
| 3409 | 38112257U, // BFADD_VG4_M4Z_H |
| 3410 | 543230977U, // BFADD_ZPmZZ |
| 3411 | 2443250689U, // BFADD_ZZZ |
| 3412 | 2460146031U, // BFCLAMP_VG2_2ZZZ_H |
| 3413 | 2460146031U, // BFCLAMP_VG4_4ZZZ_H |
| 3414 | 2460031343U, // BFCLAMP_ZZZ |
| 3415 | 2122225U, // BFCVT |
| 3416 | 1356961872U, // BFCVTN |
| 3417 | 3240231390U, // BFCVTN2 |
| 3418 | 541139208U, // BFCVTNT_ZPmZ |
| 3419 | 1078010120U, // BFCVTNT_ZPzZ_StoH |
| 3420 | 1075877968U, // BFCVTN_Z2Z_HtoB |
| 3421 | 572594256U, // BFCVTN_Z2Z_StoH |
| 3422 | 1075880433U, // BFCVT_Z2Z_HtoB |
| 3423 | 572596721U, // BFCVT_Z2Z_StoH |
| 3424 | 541139441U, // BFCVT_ZPmZ |
| 3425 | 1080107505U, // BFCVT_ZPzZ_StoH |
| 3426 | 4064518478U, // BFDOT_VG2_M2Z2Z_HtoS |
| 3427 | 4064518478U, // BFDOT_VG2_M2ZZI_HtoS |
| 3428 | 4064518478U, // BFDOT_VG2_M2ZZ_HtoS |
| 3429 | 37986638U, // BFDOT_VG4_M4Z4Z_HtoS |
| 3430 | 37986638U, // BFDOT_VG4_M4ZZI_HtoS |
| 3431 | 37986638U, // BFDOT_VG4_M4ZZ_HtoS |
| 3432 | 2954977614U, // BFDOT_ZZI |
| 3433 | 2954977614U, // BFDOT_ZZZ |
| 3434 | 3231850830U, // BFDOTv4bf16 |
| 3435 | 3238142286U, // BFDOTv8bf16 |
| 3436 | 2449659754U, // BFMAXNM_VG2_2Z2Z_H |
| 3437 | 2449659754U, // BFMAXNM_VG2_2ZZ_H |
| 3438 | 2449659754U, // BFMAXNM_VG4_4Z2Z_H |
| 3439 | 2449659754U, // BFMAXNM_VG4_4ZZ_H |
| 3440 | 543233898U, // BFMAXNM_ZPmZZ |
| 3441 | 2449663197U, // BFMAX_VG2_2Z2Z_H |
| 3442 | 2449663197U, // BFMAX_VG2_2ZZ_H |
| 3443 | 2449663197U, // BFMAX_VG4_4Z2Z_H |
| 3444 | 2449663197U, // BFMAX_VG4_4ZZ_H |
| 3445 | 543237341U, // BFMAX_ZPmZZ |
| 3446 | 2449659712U, // BFMINNM_VG2_2Z2Z_H |
| 3447 | 2449659712U, // BFMINNM_VG2_2ZZ_H |
| 3448 | 2449659712U, // BFMINNM_VG4_4Z2Z_H |
| 3449 | 2449659712U, // BFMINNM_VG4_4ZZ_H |
| 3450 | 543233856U, // BFMINNM_ZPmZZ |
| 3451 | 2449659863U, // BFMIN_VG2_2Z2Z_H |
| 3452 | 2449659863U, // BFMIN_VG2_2ZZ_H |
| 3453 | 2449659863U, // BFMIN_VG4_4Z2Z_H |
| 3454 | 2449659863U, // BFMIN_VG4_4ZZ_H |
| 3455 | 543234007U, // BFMIN_ZPmZZ |
| 3456 | 3238135560U, // BFMLALB |
| 3457 | 3238135560U, // BFMLALBIdx |
| 3458 | 2954970888U, // BFMLALB_ZZZ |
| 3459 | 2954970888U, // BFMLALB_ZZZI |
| 3460 | 3238141861U, // BFMLALT |
| 3461 | 3238141861U, // BFMLALTIdx |
| 3462 | 2954977189U, // BFMLALT_ZZZ |
| 3463 | 2954977189U, // BFMLALT_ZZZI |
| 3464 | 1390645768U, // BFMLAL_MZZI_HtoS |
| 3465 | 1390645768U, // BFMLAL_MZZ_HtoS |
| 3466 | 4075000328U, // BFMLAL_VG2_M2Z2Z_HtoS |
| 3467 | 4075000328U, // BFMLAL_VG2_M2ZZI_HtoS |
| 3468 | 4075000328U, // BFMLAL_VG2_M2ZZ_HtoS |
| 3469 | 48468488U, // BFMLAL_VG4_M4Z4Z_HtoS |
| 3470 | 48468488U, // BFMLAL_VG4_M4ZZI_HtoS |
| 3471 | 48468488U, // BFMLAL_VG4_M4ZZ_HtoS |
| 3472 | 4064641899U, // BFMLA_VG2_M2Z2Z |
| 3473 | 4064641899U, // BFMLA_VG2_M2ZZ |
| 3474 | 4064641899U, // BFMLA_VG2_M2ZZI |
| 3475 | 38110059U, // BFMLA_VG4_M4Z4Z |
| 3476 | 38110059U, // BFMLA_VG4_M4ZZ |
| 3477 | 38110059U, // BFMLA_VG4_M4ZZI |
| 3478 | 543228779U, // BFMLA_ZPmZZ |
| 3479 | 2460025707U, // BFMLA_ZZZI |
| 3480 | 2954971186U, // BFMLSLB_ZZZI_S |
| 3481 | 2954971186U, // BFMLSLB_ZZZ_S |
| 3482 | 2954977420U, // BFMLSLT_ZZZI_S |
| 3483 | 2954977420U, // BFMLSLT_ZZZ_S |
| 3484 | 1390646839U, // BFMLSL_MZZI_HtoS |
| 3485 | 1390646839U, // BFMLSL_MZZ_HtoS |
| 3486 | 4075001399U, // BFMLSL_VG2_M2Z2Z_HtoS |
| 3487 | 4075001399U, // BFMLSL_VG2_M2ZZI_HtoS |
| 3488 | 4075001399U, // BFMLSL_VG2_M2ZZ_HtoS |
| 3489 | 48469559U, // BFMLSL_VG4_M4Z4Z_HtoS |
| 3490 | 48469559U, // BFMLSL_VG4_M4ZZI_HtoS |
| 3491 | 48469559U, // BFMLSL_VG4_M4ZZ_HtoS |
| 3492 | 4064648722U, // BFMLS_VG2_M2Z2Z |
| 3493 | 4064648722U, // BFMLS_VG2_M2ZZ |
| 3494 | 4064648722U, // BFMLS_VG2_M2ZZI |
| 3495 | 38116882U, // BFMLS_VG4_M4Z4Z |
| 3496 | 38116882U, // BFMLS_VG4_M4ZZ |
| 3497 | 38116882U, // BFMLS_VG4_M4ZZI |
| 3498 | 543235602U, // BFMLS_ZPmZZ |
| 3499 | 2460032530U, // BFMLS_ZZZI |
| 3500 | 3238134642U, // BFMMLA |
| 3501 | 2460025714U, // BFMMLA_ZZZ_H |
| 3502 | 2954969970U, // BFMMLA_ZZZ_HtoS |
| 3503 | 1661059797U, // BFMOP4A_M2Z2Z_H |
| 3504 | 1661059797U, // BFMOP4A_M2Z2Z_S |
| 3505 | 1929495253U, // BFMOP4A_M2ZZ_H |
| 3506 | 1929495253U, // BFMOP4A_M2ZZ_S |
| 3507 | 2460074709U, // BFMOP4A_MZ2Z_H |
| 3508 | 2460074709U, // BFMOP4A_MZ2Z_S |
| 3509 | 2460074709U, // BFMOP4A_MZZ_H |
| 3510 | 2460074709U, // BFMOP4A_MZZ_S |
| 3511 | 1661066568U, // BFMOP4S_M2Z2Z_H |
| 3512 | 1661066568U, // BFMOP4S_M2Z2Z_S |
| 3513 | 1929502024U, // BFMOP4S_M2ZZ_H |
| 3514 | 1929502024U, // BFMOP4S_M2ZZ_S |
| 3515 | 2460081480U, // BFMOP4S_MZ2Z_H |
| 3516 | 2460081480U, // BFMOP4S_MZ2Z_S |
| 3517 | 2460081480U, // BFMOP4S_MZZ_H |
| 3518 | 2460081480U, // BFMOP4S_MZZ_S |
| 3519 | 541180913U, // BFMOPA_MPPZZ |
| 3520 | 541180913U, // BFMOPA_MPPZZ_H |
| 3521 | 541187679U, // BFMOPS_MPPZZ |
| 3522 | 541187679U, // BFMOPS_MPPZZ_H |
| 3523 | 2449659543U, // BFMUL_2Z2Z |
| 3524 | 2449659543U, // BFMUL_2ZZ |
| 3525 | 2449659543U, // BFMUL_4Z4Z |
| 3526 | 2449659543U, // BFMUL_4ZZ |
| 3527 | 543233687U, // BFMUL_ZPmZZ |
| 3528 | 2443253399U, // BFMUL_ZZZ |
| 3529 | 2443253399U, // BFMUL_ZZZI |
| 3530 | 807425807U, // BFMWri |
| 3531 | 807425807U, // BFMXri |
| 3532 | 2449657065U, // BFSCALE_2Z2Z |
| 3533 | 2449657065U, // BFSCALE_2ZZ |
| 3534 | 2449657065U, // BFSCALE_4Z4Z |
| 3535 | 2449657065U, // BFSCALE_4ZZ |
| 3536 | 543231209U, // BFSCALE_ZPZZ_H |
| 3537 | 4064643663U, // BFSUB_VG2_M2Z_H |
| 3538 | 38111823U, // BFSUB_VG4_M4Z_H |
| 3539 | 543230543U, // BFSUB_ZPmZZ |
| 3540 | 2443250255U, // BFSUB_ZZZ |
| 3541 | 1929495553U, // BFTMOPA_M2ZZZI_HtoH |
| 3542 | 1929495553U, // BFTMOPA_M2ZZZI_HtoS |
| 3543 | 4064518499U, // BFVDOT_VG2_M2ZZI_HtoS |
| 3544 | 3491797509U, // BGRP_ZZZ_B |
| 3545 | 2686507525U, // BGRP_ZZZ_D |
| 3546 | 2443254277U, // BGRP_ZZZ_H |
| 3547 | 3760282117U, // BGRP_ZZZ_S |
| 3548 | 2121151U, // BICSWrs |
| 3549 | 2121151U, // BICSXrs |
| 3550 | 807443903U, // BICS_PPzPP |
| 3551 | 2116330U, // BICWrs |
| 3552 | 2116330U, // BICXrs |
| 3553 | 807439082U, // BIC_PPzPP |
| 3554 | 807439082U, // BIC_ZPmZ_B |
| 3555 | 807455466U, // BIC_ZPmZ_D |
| 3556 | 543230698U, // BIC_ZPmZ_H |
| 3557 | 807488234U, // BIC_ZPmZ_S |
| 3558 | 2686503658U, // BIC_ZZZ |
| 3559 | 1350666986U, // BICv16i8 |
| 3560 | 2158103274U, // BICv2i32 |
| 3561 | 2162297578U, // BICv4i16 |
| 3562 | 2164394730U, // BICv4i32 |
| 3563 | 2166491882U, // BICv8i16 |
| 3564 | 1363249898U, // BICv8i8 |
| 3565 | 3229748617U, // BIFv16i8 |
| 3566 | 3242331529U, // BIFv8i8 |
| 3567 | 3229753202U, // BITv16i8 |
| 3568 | 3242336114U, // BITv8i8 |
| 3569 | 332709U, // BL |
| 3570 | 23564U, // BLR |
| 3571 | 2114301U, // BLRAA |
| 3572 | 25978U, // BLRAAZ |
| 3573 | 2115123U, // BLRAB |
| 3574 | 26000U, // BLRABZ |
| 3575 | 541180906U, // BMOPA_MPPZZ_S |
| 3576 | 541187672U, // BMOPS_MPPZZ_S |
| 3577 | 23406U, // BR |
| 3578 | 2114288U, // BRAA |
| 3579 | 25971U, // BRAAZ |
| 3580 | 2115110U, // BRAB |
| 3581 | 25993U, // BRABZ |
| 3582 | 11537U, // BRB_IALL |
| 3583 | 11515U, // BRB_INJ |
| 3584 | 381374U, // BRK |
| 3585 | 807443828U, // BRKAS_PPzP |
| 3586 | 270566238U, // BRKA_PPmP |
| 3587 | 807437150U, // BRKA_PPzP |
| 3588 | 807443870U, // BRKBS_PPzP |
| 3589 | 270567134U, // BRKB_PPmP |
| 3590 | 807438046U, // BRKB_PPzP |
| 3591 | 807444020U, // BRKNS_PPzP |
| 3592 | 807442439U, // BRKN_PPzP |
| 3593 | 807443841U, // BRKPAS_PPzPP |
| 3594 | 807437283U, // BRKPA_PPzPP |
| 3595 | 807443877U, // BRKPBS_PPzPP |
| 3596 | 807438581U, // BRKPB_PPzPP |
| 3597 | 2686506928U, // BSL1N_ZZZZ |
| 3598 | 2686506935U, // BSL2N_ZZZZ |
| 3599 | 2686506537U, // BSL_ZZZZ |
| 3600 | 3229750825U, // BSLv16i8 |
| 3601 | 3242333737U, // BSLv8i8 |
| 3602 | 353787U, // Bcc |
| 3603 | 3491793898U, // CADD_ZZI_B |
| 3604 | 2686503914U, // CADD_ZZI_D |
| 3605 | 2443250666U, // CADD_ZZI_H |
| 3606 | 3760278506U, // CADD_ZZI_S |
| 3607 | 807716428U, // CASAB |
| 3608 | 807718569U, // CASAH |
| 3609 | 807716691U, // CASALB |
| 3610 | 807718735U, // CASALH |
| 3611 | 807722951U, // CASALTX |
| 3612 | 807719738U, // CASALW |
| 3613 | 807719738U, // CASALX |
| 3614 | 807722699U, // CASATX |
| 3615 | 807716078U, // CASAW |
| 3616 | 807716078U, // CASAX |
| 3617 | 807717312U, // CASB |
| 3618 | 807719120U, // CASH |
| 3619 | 807716897U, // CASLB |
| 3620 | 807718829U, // CASLH |
| 3621 | 807723131U, // CASLTX |
| 3622 | 807720473U, // CASLW |
| 3623 | 807720473U, // CASLX |
| 3624 | 401342U, // CASPALTX |
| 3625 | 414396U, // CASPALW |
| 3626 | 398012U, // CASPALX |
| 3627 | 401091U, // CASPATX |
| 3628 | 410715U, // CASPAW |
| 3629 | 394331U, // CASPAX |
| 3630 | 401523U, // CASPLTX |
| 3631 | 415135U, // CASPLW |
| 3632 | 398751U, // CASPLX |
| 3633 | 401823U, // CASPTX |
| 3634 | 416298U, // CASPW |
| 3635 | 399914U, // CASPX |
| 3636 | 807723443U, // CASTX |
| 3637 | 807722343U, // CASW |
| 3638 | 807722343U, // CASX |
| 3639 | 2120446U, // CBBEQWrr |
| 3640 | 2116791U, // CBBGEWrr |
| 3641 | 2121535U, // CBBGTWrr |
| 3642 | 2117960U, // CBBHIWrr |
| 3643 | 2121178U, // CBBHSWrr |
| 3644 | 2116873U, // CBBNEWrr |
| 3645 | 2120453U, // CBEQWri |
| 3646 | 2120453U, // CBEQWrr |
| 3647 | 2120453U, // CBEQXri |
| 3648 | 2120453U, // CBEQXrr |
| 3649 | 2116798U, // CBGEWrr |
| 3650 | 2116798U, // CBGEXrr |
| 3651 | 2121542U, // CBGTWri |
| 3652 | 2121542U, // CBGTWrr |
| 3653 | 2121542U, // CBGTXri |
| 3654 | 2121542U, // CBGTXrr |
| 3655 | 2120459U, // CBHEQWrr |
| 3656 | 2116820U, // CBHGEWrr |
| 3657 | 2121564U, // CBHGTWrr |
| 3658 | 2117982U, // CBHHIWrr |
| 3659 | 2121200U, // CBHHSWrr |
| 3660 | 2117967U, // CBHIWri |
| 3661 | 2117967U, // CBHIWrr |
| 3662 | 2117967U, // CBHIXri |
| 3663 | 2117967U, // CBHIXrr |
| 3664 | 2116886U, // CBHNEWrr |
| 3665 | 2121185U, // CBHSWrr |
| 3666 | 2121185U, // CBHSXrr |
| 3667 | 2119857U, // CBLOWri |
| 3668 | 2119857U, // CBLOXri |
| 3669 | 2121679U, // CBLTWri |
| 3670 | 2121679U, // CBLTXri |
| 3671 | 2116880U, // CBNEWri |
| 3672 | 2116880U, // CBNEWrr |
| 3673 | 2116880U, // CBNEXri |
| 3674 | 2116880U, // CBNEXrr |
| 3675 | 2418042279U, // CBNZW |
| 3676 | 2418042279U, // CBNZX |
| 3677 | 2418042264U, // CBZW |
| 3678 | 2418042264U, // CBZX |
| 3679 | 2119693U, // CCMNWi |
| 3680 | 2119693U, // CCMNWr |
| 3681 | 2119693U, // CCMNXi |
| 3682 | 2119693U, // CCMNXr |
| 3683 | 2120073U, // CCMPWi |
| 3684 | 2120073U, // CCMPWr |
| 3685 | 2120073U, // CCMPXi |
| 3686 | 2120073U, // CCMPXr |
| 3687 | 2954944840U, // CDOT_ZZZI_D |
| 3688 | 2686542152U, // CDOT_ZZZI_S |
| 3689 | 2954944840U, // CDOT_ZZZ_D |
| 3690 | 2686542152U, // CDOT_ZZZ_S |
| 3691 | 11563U, // CFINV |
| 3692 | 9873U, // CHKFEAT |
| 3693 | 807421232U, // CLASTA_RPZ_B |
| 3694 | 807421232U, // CLASTA_RPZ_D |
| 3695 | 807421232U, // CLASTA_RPZ_H |
| 3696 | 807421232U, // CLASTA_RPZ_S |
| 3697 | 807421232U, // CLASTA_VPZ_B |
| 3698 | 807421232U, // CLASTA_VPZ_D |
| 3699 | 807421232U, // CLASTA_VPZ_H |
| 3700 | 807421232U, // CLASTA_VPZ_S |
| 3701 | 807437616U, // CLASTA_ZPZ_B |
| 3702 | 807454000U, // CLASTA_ZPZ_D |
| 3703 | 2422277424U, // CLASTA_ZPZ_H |
| 3704 | 807486768U, // CLASTA_ZPZ_S |
| 3705 | 807422523U, // CLASTB_RPZ_B |
| 3706 | 807422523U, // CLASTB_RPZ_D |
| 3707 | 807422523U, // CLASTB_RPZ_H |
| 3708 | 807422523U, // CLASTB_RPZ_S |
| 3709 | 807422523U, // CLASTB_VPZ_B |
| 3710 | 807422523U, // CLASTB_VPZ_D |
| 3711 | 807422523U, // CLASTB_VPZ_H |
| 3712 | 807422523U, // CLASTB_VPZ_S |
| 3713 | 807438907U, // CLASTB_ZPZ_B |
| 3714 | 807455291U, // CLASTB_ZPZ_D |
| 3715 | 2422278715U, // CLASTB_ZPZ_H |
| 3716 | 807488059U, // CLASTB_ZPZ_S |
| 3717 | 25890U, // CLREX |
| 3718 | 2121220U, // CLSWr |
| 3719 | 2121220U, // CLSXr |
| 3720 | 270573060U, // CLS_ZPmZ_B |
| 3721 | 270589444U, // CLS_ZPmZ_D |
| 3722 | 541138436U, // CLS_ZPmZ_H |
| 3723 | 270622212U, // CLS_ZPmZ_S |
| 3724 | 807443972U, // CLS_ZPzZ_B |
| 3725 | 807460356U, // CLS_ZPzZ_D |
| 3726 | 1080106500U, // CLS_ZPzZ_H |
| 3727 | 807493124U, // CLS_ZPzZ_S |
| 3728 | 1350671876U, // CLSv16i8 |
| 3729 | 1352769028U, // CLSv2i32 |
| 3730 | 1356963332U, // CLSv4i16 |
| 3731 | 1359060484U, // CLSv4i32 |
| 3732 | 1361157636U, // CLSv8i16 |
| 3733 | 1363254788U, // CLSv8i8 |
| 3734 | 2123170U, // CLZWr |
| 3735 | 2123170U, // CLZXr |
| 3736 | 270575010U, // CLZ_ZPmZ_B |
| 3737 | 270591394U, // CLZ_ZPmZ_D |
| 3738 | 541140386U, // CLZ_ZPmZ_H |
| 3739 | 270624162U, // CLZ_ZPmZ_S |
| 3740 | 807445922U, // CLZ_ZPzZ_B |
| 3741 | 807462306U, // CLZ_ZPzZ_D |
| 3742 | 1080108450U, // CLZ_ZPzZ_H |
| 3743 | 807495074U, // CLZ_ZPzZ_S |
| 3744 | 1350673826U, // CLZv16i8 |
| 3745 | 1352770978U, // CLZv2i32 |
| 3746 | 1356965282U, // CLZv4i16 |
| 3747 | 1359062434U, // CLZv4i32 |
| 3748 | 1361159586U, // CLZv8i16 |
| 3749 | 1363256738U, // CLZv8i8 |
| 3750 | 1350671123U, // CMEQv16i8 |
| 3751 | 1350671123U, // CMEQv16i8rz |
| 3752 | 2120467U, // CMEQv1i64 |
| 3753 | 2120467U, // CMEQv1i64rz |
| 3754 | 1352768275U, // CMEQv2i32 |
| 3755 | 1352768275U, // CMEQv2i32rz |
| 3756 | 1354865427U, // CMEQv2i64 |
| 3757 | 1354865427U, // CMEQv2i64rz |
| 3758 | 1356962579U, // CMEQv4i16 |
| 3759 | 1356962579U, // CMEQv4i16rz |
| 3760 | 1359059731U, // CMEQv4i32 |
| 3761 | 1359059731U, // CMEQv4i32rz |
| 3762 | 1361156883U, // CMEQv8i16 |
| 3763 | 1361156883U, // CMEQv8i16rz |
| 3764 | 1363254035U, // CMEQv8i8 |
| 3765 | 1363254035U, // CMEQv8i8rz |
| 3766 | 1350667484U, // CMGEv16i8 |
| 3767 | 1350667484U, // CMGEv16i8rz |
| 3768 | 2116828U, // CMGEv1i64 |
| 3769 | 2116828U, // CMGEv1i64rz |
| 3770 | 1352764636U, // CMGEv2i32 |
| 3771 | 1352764636U, // CMGEv2i32rz |
| 3772 | 1354861788U, // CMGEv2i64 |
| 3773 | 1354861788U, // CMGEv2i64rz |
| 3774 | 1356958940U, // CMGEv4i16 |
| 3775 | 1356958940U, // CMGEv4i16rz |
| 3776 | 1359056092U, // CMGEv4i32 |
| 3777 | 1359056092U, // CMGEv4i32rz |
| 3778 | 1361153244U, // CMGEv8i16 |
| 3779 | 1361153244U, // CMGEv8i16rz |
| 3780 | 1363250396U, // CMGEv8i8 |
| 3781 | 1363250396U, // CMGEv8i8rz |
| 3782 | 1350672228U, // CMGTv16i8 |
| 3783 | 1350672228U, // CMGTv16i8rz |
| 3784 | 2121572U, // CMGTv1i64 |
| 3785 | 2121572U, // CMGTv1i64rz |
| 3786 | 1352769380U, // CMGTv2i32 |
| 3787 | 1352769380U, // CMGTv2i32rz |
| 3788 | 1354866532U, // CMGTv2i64 |
| 3789 | 1354866532U, // CMGTv2i64rz |
| 3790 | 1356963684U, // CMGTv4i16 |
| 3791 | 1356963684U, // CMGTv4i16rz |
| 3792 | 1359060836U, // CMGTv4i32 |
| 3793 | 1359060836U, // CMGTv4i32rz |
| 3794 | 1361157988U, // CMGTv8i16 |
| 3795 | 1361157988U, // CMGTv8i16rz |
| 3796 | 1363255140U, // CMGTv8i8 |
| 3797 | 1363255140U, // CMGTv8i8rz |
| 3798 | 1350668672U, // CMHIv16i8 |
| 3799 | 2118016U, // CMHIv1i64 |
| 3800 | 1352765824U, // CMHIv2i32 |
| 3801 | 1354862976U, // CMHIv2i64 |
| 3802 | 1356960128U, // CMHIv4i16 |
| 3803 | 1359057280U, // CMHIv4i32 |
| 3804 | 1361154432U, // CMHIv8i16 |
| 3805 | 1363251584U, // CMHIv8i8 |
| 3806 | 1350671863U, // CMHSv16i8 |
| 3807 | 2121207U, // CMHSv1i64 |
| 3808 | 1352769015U, // CMHSv2i32 |
| 3809 | 1354866167U, // CMHSv2i64 |
| 3810 | 1356963319U, // CMHSv4i16 |
| 3811 | 1359060471U, // CMHSv4i32 |
| 3812 | 1361157623U, // CMHSv8i16 |
| 3813 | 1363254775U, // CMHSv8i8 |
| 3814 | 2460025701U, // CMLA_ZZZI_H |
| 3815 | 1881228133U, // CMLA_ZZZI_S |
| 3816 | 2686485349U, // CMLA_ZZZ_B |
| 3817 | 1612759909U, // CMLA_ZZZ_D |
| 3818 | 2460025701U, // CMLA_ZZZ_H |
| 3819 | 1881228133U, // CMLA_ZZZ_S |
| 3820 | 1350667516U, // CMLEv16i8rz |
| 3821 | 2116860U, // CMLEv1i64rz |
| 3822 | 1352764668U, // CMLEv2i32rz |
| 3823 | 1354861820U, // CMLEv2i64rz |
| 3824 | 1356958972U, // CMLEv4i16rz |
| 3825 | 1359056124U, // CMLEv4i32rz |
| 3826 | 1361153276U, // CMLEv8i16rz |
| 3827 | 1363250428U, // CMLEv8i8rz |
| 3828 | 1350672486U, // CMLTv16i8rz |
| 3829 | 2121830U, // CMLTv1i64rz |
| 3830 | 1352769638U, // CMLTv2i32rz |
| 3831 | 1354866790U, // CMLTv2i64rz |
| 3832 | 1356963942U, // CMLTv4i16rz |
| 3833 | 1359061094U, // CMLTv4i32rz |
| 3834 | 1361158246U, // CMLTv8i16rz |
| 3835 | 1363255398U, // CMLTv8i8rz |
| 3836 | 807443234U, // CMPEQ_PPzZI_B |
| 3837 | 807459618U, // CMPEQ_PPzZI_D |
| 3838 | 1080105762U, // CMPEQ_PPzZI_H |
| 3839 | 807492386U, // CMPEQ_PPzZI_S |
| 3840 | 807443234U, // CMPEQ_PPzZZ_B |
| 3841 | 807459618U, // CMPEQ_PPzZZ_D |
| 3842 | 1080105762U, // CMPEQ_PPzZZ_H |
| 3843 | 807492386U, // CMPEQ_PPzZZ_S |
| 3844 | 807443234U, // CMPEQ_WIDE_PPzZZ_B |
| 3845 | 1080105762U, // CMPEQ_WIDE_PPzZZ_H |
| 3846 | 807492386U, // CMPEQ_WIDE_PPzZZ_S |
| 3847 | 807439586U, // CMPGE_PPzZI_B |
| 3848 | 807455970U, // CMPGE_PPzZI_D |
| 3849 | 1080102114U, // CMPGE_PPzZI_H |
| 3850 | 807488738U, // CMPGE_PPzZI_S |
| 3851 | 807439586U, // CMPGE_PPzZZ_B |
| 3852 | 807455970U, // CMPGE_PPzZZ_D |
| 3853 | 1080102114U, // CMPGE_PPzZZ_H |
| 3854 | 807488738U, // CMPGE_PPzZZ_S |
| 3855 | 807439586U, // CMPGE_WIDE_PPzZZ_B |
| 3856 | 1080102114U, // CMPGE_WIDE_PPzZZ_H |
| 3857 | 807488738U, // CMPGE_WIDE_PPzZZ_S |
| 3858 | 807444330U, // CMPGT_PPzZI_B |
| 3859 | 807460714U, // CMPGT_PPzZI_D |
| 3860 | 1080106858U, // CMPGT_PPzZI_H |
| 3861 | 807493482U, // CMPGT_PPzZI_S |
| 3862 | 807444330U, // CMPGT_PPzZZ_B |
| 3863 | 807460714U, // CMPGT_PPzZZ_D |
| 3864 | 1080106858U, // CMPGT_PPzZZ_H |
| 3865 | 807493482U, // CMPGT_PPzZZ_S |
| 3866 | 807444330U, // CMPGT_WIDE_PPzZZ_B |
| 3867 | 1080106858U, // CMPGT_WIDE_PPzZZ_H |
| 3868 | 807493482U, // CMPGT_WIDE_PPzZZ_S |
| 3869 | 807440774U, // CMPHI_PPzZI_B |
| 3870 | 807457158U, // CMPHI_PPzZI_D |
| 3871 | 1080103302U, // CMPHI_PPzZI_H |
| 3872 | 807489926U, // CMPHI_PPzZI_S |
| 3873 | 807440774U, // CMPHI_PPzZZ_B |
| 3874 | 807457158U, // CMPHI_PPzZZ_D |
| 3875 | 1080103302U, // CMPHI_PPzZZ_H |
| 3876 | 807489926U, // CMPHI_PPzZZ_S |
| 3877 | 807440774U, // CMPHI_WIDE_PPzZZ_B |
| 3878 | 1080103302U, // CMPHI_WIDE_PPzZZ_H |
| 3879 | 807489926U, // CMPHI_WIDE_PPzZZ_S |
| 3880 | 807443965U, // CMPHS_PPzZI_B |
| 3881 | 807460349U, // CMPHS_PPzZI_D |
| 3882 | 1080106493U, // CMPHS_PPzZI_H |
| 3883 | 807493117U, // CMPHS_PPzZI_S |
| 3884 | 807443965U, // CMPHS_PPzZZ_B |
| 3885 | 807460349U, // CMPHS_PPzZZ_D |
| 3886 | 1080106493U, // CMPHS_PPzZZ_H |
| 3887 | 807493117U, // CMPHS_PPzZZ_S |
| 3888 | 807443965U, // CMPHS_WIDE_PPzZZ_B |
| 3889 | 1080106493U, // CMPHS_WIDE_PPzZZ_H |
| 3890 | 807493117U, // CMPHS_WIDE_PPzZZ_S |
| 3891 | 807439618U, // CMPLE_PPzZI_B |
| 3892 | 807456002U, // CMPLE_PPzZI_D |
| 3893 | 1080102146U, // CMPLE_PPzZI_H |
| 3894 | 807488770U, // CMPLE_PPzZI_S |
| 3895 | 807439618U, // CMPLE_WIDE_PPzZZ_B |
| 3896 | 1080102146U, // CMPLE_WIDE_PPzZZ_H |
| 3897 | 807488770U, // CMPLE_WIDE_PPzZZ_S |
| 3898 | 807442651U, // CMPLO_PPzZI_B |
| 3899 | 807459035U, // CMPLO_PPzZI_D |
| 3900 | 1080105179U, // CMPLO_PPzZI_H |
| 3901 | 807491803U, // CMPLO_PPzZI_S |
| 3902 | 807442651U, // CMPLO_WIDE_PPzZZ_B |
| 3903 | 1080105179U, // CMPLO_WIDE_PPzZZ_H |
| 3904 | 807491803U, // CMPLO_WIDE_PPzZZ_S |
| 3905 | 807444000U, // CMPLS_PPzZI_B |
| 3906 | 807460384U, // CMPLS_PPzZI_D |
| 3907 | 1080106528U, // CMPLS_PPzZI_H |
| 3908 | 807493152U, // CMPLS_PPzZI_S |
| 3909 | 807444000U, // CMPLS_WIDE_PPzZZ_B |
| 3910 | 1080106528U, // CMPLS_WIDE_PPzZZ_H |
| 3911 | 807493152U, // CMPLS_WIDE_PPzZZ_S |
| 3912 | 807444588U, // CMPLT_PPzZI_B |
| 3913 | 807460972U, // CMPLT_PPzZI_D |
| 3914 | 1080107116U, // CMPLT_PPzZI_H |
| 3915 | 807493740U, // CMPLT_PPzZI_S |
| 3916 | 807444588U, // CMPLT_WIDE_PPzZZ_B |
| 3917 | 1080107116U, // CMPLT_WIDE_PPzZZ_H |
| 3918 | 807493740U, // CMPLT_WIDE_PPzZZ_S |
| 3919 | 807439661U, // CMPNE_PPzZI_B |
| 3920 | 807456045U, // CMPNE_PPzZI_D |
| 3921 | 1080102189U, // CMPNE_PPzZI_H |
| 3922 | 807488813U, // CMPNE_PPzZI_S |
| 3923 | 807439661U, // CMPNE_PPzZZ_B |
| 3924 | 807456045U, // CMPNE_PPzZZ_D |
| 3925 | 1080102189U, // CMPNE_PPzZZ_H |
| 3926 | 807488813U, // CMPNE_PPzZZ_S |
| 3927 | 807439661U, // CMPNE_WIDE_PPzZZ_B |
| 3928 | 1080102189U, // CMPNE_WIDE_PPzZZ_H |
| 3929 | 807488813U, // CMPNE_WIDE_PPzZZ_S |
| 3930 | 1350672840U, // CMTSTv16i8 |
| 3931 | 2122184U, // CMTSTv1i64 |
| 3932 | 1352769992U, // CMTSTv2i32 |
| 3933 | 1354867144U, // CMTSTv2i64 |
| 3934 | 1356964296U, // CMTSTv4i16 |
| 3935 | 1359061448U, // CMTSTv4i32 |
| 3936 | 1361158600U, // CMTSTv8i16 |
| 3937 | 1363255752U, // CMTSTv8i8 |
| 3938 | 270573947U, // CNOT_ZPmZ_B |
| 3939 | 270590331U, // CNOT_ZPmZ_D |
| 3940 | 541139323U, // CNOT_ZPmZ_H |
| 3941 | 270623099U, // CNOT_ZPmZ_S |
| 3942 | 807444859U, // CNOT_ZPzZ_B |
| 3943 | 807461243U, // CNOT_ZPzZ_D |
| 3944 | 1080107387U, // CNOT_ZPzZ_H |
| 3945 | 807494011U, // CNOT_ZPzZ_S |
| 3946 | 2954906150U, // CNTB_XPiI |
| 3947 | 2954906781U, // CNTD_XPiI |
| 3948 | 2954907921U, // CNTH_XPiI |
| 3949 | 3223345760U, // CNTP_XCI_B |
| 3950 | 3491781216U, // CNTP_XCI_D |
| 3951 | 3760216672U, // CNTP_XCI_H |
| 3952 | 4028652128U, // CNTP_XCI_S |
| 3953 | 807426656U, // CNTP_XPP_B |
| 3954 | 807426656U, // CNTP_XPP_D |
| 3955 | 807426656U, // CNTP_XPP_H |
| 3956 | 807426656U, // CNTP_XPP_S |
| 3957 | 2954912922U, // CNTW_XPiI |
| 3958 | 2121925U, // CNTWr |
| 3959 | 2121925U, // CNTXr |
| 3960 | 270573765U, // CNT_ZPmZ_B |
| 3961 | 270590149U, // CNT_ZPmZ_D |
| 3962 | 541139141U, // CNT_ZPmZ_H |
| 3963 | 270622917U, // CNT_ZPmZ_S |
| 3964 | 807444677U, // CNT_ZPzZ_B |
| 3965 | 807461061U, // CNT_ZPzZ_D |
| 3966 | 1080107205U, // CNT_ZPzZ_H |
| 3967 | 807493829U, // CNT_ZPzZ_S |
| 3968 | 1350672581U, // CNTv16i8 |
| 3969 | 1363255493U, // CNTv8i8 |
| 3970 | 807444235U, // COMPACT_ZPZ_B |
| 3971 | 807460619U, // COMPACT_ZPZ_D |
| 3972 | 2422284043U, // COMPACT_ZPZ_H |
| 3973 | 807493387U, // COMPACT_ZPZ_S |
| 3974 | 436166U, // CPYE |
| 3975 | 436248U, // CPYEN |
| 3976 | 436354U, // CPYERN |
| 3977 | 437314U, // CPYERT |
| 3978 | 436760U, // CPYERTN |
| 3979 | 436476U, // CPYERTRN |
| 3980 | 437007U, // CPYERTWN |
| 3981 | 437208U, // CPYET |
| 3982 | 436642U, // CPYETN |
| 3983 | 436412U, // CPYETRN |
| 3984 | 436943U, // CPYETWN |
| 3985 | 436885U, // CPYEWN |
| 3986 | 437371U, // CPYEWT |
| 3987 | 436823U, // CPYEWTN |
| 3988 | 436545U, // CPYEWTRN |
| 3989 | 437076U, // CPYEWTWN |
| 3990 | 436134U, // CPYFE |
| 3991 | 436212U, // CPYFEN |
| 3992 | 436344U, // CPYFERN |
| 3993 | 437304U, // CPYFERT |
| 3994 | 436749U, // CPYFERTN |
| 3995 | 436464U, // CPYFERTRN |
| 3996 | 436995U, // CPYFERTWN |
| 3997 | 437172U, // CPYFET |
| 3998 | 436602U, // CPYFETN |
| 3999 | 436401U, // CPYFETRN |
| 4000 | 436932U, // CPYFETWN |
| 4001 | 436875U, // CPYFEWN |
| 4002 | 437361U, // CPYFEWT |
| 4003 | 436812U, // CPYFEWTN |
| 4004 | 436533U, // CPYFEWTRN |
| 4005 | 437064U, // CPYFEWTWN |
| 4006 | 436173U, // CPYFM |
| 4007 | 436256U, // CPYFMN |
| 4008 | 436363U, // CPYFMRN |
| 4009 | 437323U, // CPYFMRT |
| 4010 | 436770U, // CPYFMRTN |
| 4011 | 436487U, // CPYFMRTRN |
| 4012 | 437018U, // CPYFMRTWN |
| 4013 | 437216U, // CPYFMT |
| 4014 | 436651U, // CPYFMTN |
| 4015 | 436422U, // CPYFMTRN |
| 4016 | 436953U, // CPYFMTWN |
| 4017 | 436894U, // CPYFMWN |
| 4018 | 437380U, // CPYFMWT |
| 4019 | 436833U, // CPYFMWTN |
| 4020 | 436556U, // CPYFMWTRN |
| 4021 | 437087U, // CPYFMWTWN |
| 4022 | 437133U, // CPYFP |
| 4023 | 436300U, // CPYFPN |
| 4024 | 436382U, // CPYFPRN |
| 4025 | 437342U, // CPYFPRT |
| 4026 | 436791U, // CPYFPRTN |
| 4027 | 436510U, // CPYFPRTRN |
| 4028 | 437041U, // CPYFPRTWN |
| 4029 | 437260U, // CPYFPT |
| 4030 | 436700U, // CPYFPTN |
| 4031 | 436443U, // CPYFPTRN |
| 4032 | 436974U, // CPYFPTWN |
| 4033 | 436913U, // CPYFPWN |
| 4034 | 437399U, // CPYFPWT |
| 4035 | 436854U, // CPYFPWTN |
| 4036 | 436579U, // CPYFPWTRN |
| 4037 | 437110U, // CPYFPWTWN |
| 4038 | 436205U, // CPYM |
| 4039 | 436292U, // CPYMN |
| 4040 | 436373U, // CPYMRN |
| 4041 | 437333U, // CPYMRT |
| 4042 | 436781U, // CPYMRTN |
| 4043 | 436499U, // CPYMRTRN |
| 4044 | 437030U, // CPYMRTWN |
| 4045 | 437252U, // CPYMT |
| 4046 | 436691U, // CPYMTN |
| 4047 | 436433U, // CPYMTRN |
| 4048 | 436964U, // CPYMTWN |
| 4049 | 436904U, // CPYMWN |
| 4050 | 437390U, // CPYMWT |
| 4051 | 436844U, // CPYMWTN |
| 4052 | 436568U, // CPYMWTRN |
| 4053 | 437099U, // CPYMWTWN |
| 4054 | 437165U, // CPYP |
| 4055 | 436336U, // CPYPN |
| 4056 | 436392U, // CPYPRN |
| 4057 | 437352U, // CPYPRT |
| 4058 | 436802U, // CPYPRTN |
| 4059 | 436522U, // CPYPRTRN |
| 4060 | 437053U, // CPYPRTWN |
| 4061 | 437296U, // CPYPT |
| 4062 | 436740U, // CPYPTN |
| 4063 | 436454U, // CPYPTRN |
| 4064 | 436985U, // CPYPTWN |
| 4065 | 436923U, // CPYPWN |
| 4066 | 437409U, // CPYPWT |
| 4067 | 436865U, // CPYPWTN |
| 4068 | 436591U, // CPYPWTRN |
| 4069 | 437122U, // CPYPWTWN |
| 4070 | 270574938U, // CPY_ZPmI_B |
| 4071 | 270591322U, // CPY_ZPmI_D |
| 4072 | 541140314U, // CPY_ZPmI_H |
| 4073 | 270624090U, // CPY_ZPmI_S |
| 4074 | 270574938U, // CPY_ZPmR_B |
| 4075 | 270591322U, // CPY_ZPmR_D |
| 4076 | 541140314U, // CPY_ZPmR_H |
| 4077 | 270624090U, // CPY_ZPmR_S |
| 4078 | 270574938U, // CPY_ZPmV_B |
| 4079 | 270591322U, // CPY_ZPmV_D |
| 4080 | 541140314U, // CPY_ZPmV_H |
| 4081 | 270624090U, // CPY_ZPmV_S |
| 4082 | 807445850U, // CPY_ZPzI_B |
| 4083 | 807462234U, // CPY_ZPzI_D |
| 4084 | 1080108378U, // CPY_ZPzI_H |
| 4085 | 807495002U, // CPY_ZPzI_S |
| 4086 | 2115007U, // CRC32Brr |
| 4087 | 2115194U, // CRC32CBrr |
| 4088 | 2117325U, // CRC32CHrr |
| 4089 | 2122731U, // CRC32CWrr |
| 4090 | 2123026U, // CRC32CXrr |
| 4091 | 2117161U, // CRC32Hrr |
| 4092 | 2122673U, // CRC32Wrr |
| 4093 | 2122930U, // CRC32Xrr |
| 4094 | 2118699U, // CSELWr |
| 4095 | 2118699U, // CSELXr |
| 4096 | 2116367U, // CSINCWr |
| 4097 | 2116367U, // CSINCXr |
| 4098 | 2122481U, // CSINVWr |
| 4099 | 2122481U, // CSINVXr |
| 4100 | 2117069U, // CSNEGWr |
| 4101 | 2117069U, // CSNEGXr |
| 4102 | 2120473U, // CTERMEQ_WW |
| 4103 | 2120473U, // CTERMEQ_XX |
| 4104 | 2116900U, // CTERMNE_WW |
| 4105 | 2116900U, // CTERMNE_XX |
| 4106 | 2123187U, // CTZWr |
| 4107 | 2123187U, // CTZXr |
| 4108 | 376923U, // DCPS1 |
| 4109 | 377400U, // DCPS2 |
| 4110 | 377474U, // DCPS3 |
| 4111 | 2115205U, // DECB_XPiI |
| 4112 | 2116555U, // DECD_XPiI |
| 4113 | 2149323U, // DECD_ZPiI |
| 4114 | 2117336U, // DECH_XPiI |
| 4115 | 52498136U, // DECH_ZPiI |
| 4116 | 3491780871U, // DECP_XP_B |
| 4117 | 2686474503U, // DECP_XP_D |
| 4118 | 2149603591U, // DECP_XP_H |
| 4119 | 3760216327U, // DECP_XP_S |
| 4120 | 1612765447U, // DECP_ZP_D |
| 4121 | 580983047U, // DECP_ZP_H |
| 4122 | 1881233671U, // DECP_ZP_S |
| 4123 | 2122742U, // DECW_XPiI |
| 4124 | 2188278U, // DECW_ZPiI |
| 4125 | 444520U, // DMB |
| 4126 | 11553U, // DRPS |
| 4127 | 444870U, // DSB |
| 4128 | 461254U, // DSBnXS |
| 4129 | 270587803U, // DUPM_ZI |
| 4130 | 3491797807U, // DUPQ_ZZI_B |
| 4131 | 2686507823U, // DUPQ_ZZI_D |
| 4132 | 564206383U, // DUPQ_ZZI_H |
| 4133 | 3760282415U, // DUPQ_ZZI_S |
| 4134 | 807443076U, // DUP_ZI_B |
| 4135 | 1075894916U, // DUP_ZI_D |
| 4136 | 54598276U, // DUP_ZI_H |
| 4137 | 1344363140U, // DUP_ZI_S |
| 4138 | 2136708U, // DUP_ZR_B |
| 4139 | 2153092U, // DUP_ZR_D |
| 4140 | 593566340U, // DUP_ZR_H |
| 4141 | 2185860U, // DUP_ZR_S |
| 4142 | 3491797636U, // DUP_ZZI_B |
| 4143 | 2686507652U, // DUP_ZZI_D |
| 4144 | 564206212U, // DUP_ZZI_H |
| 4145 | 596073092U, // DUP_ZZI_Q |
| 4146 | 3760282244U, // DUP_ZZI_S |
| 4147 | 1344299769U, // DUPi16 |
| 4148 | 1344299769U, // DUPi32 |
| 4149 | 1344299769U, // DUPi64 |
| 4150 | 1344299769U, // DUPi8 |
| 4151 | 8493700U, // DUPv16i8gpr |
| 4152 | 1350670980U, // DUPv16i8lane |
| 4153 | 10590852U, // DUPv2i32gpr |
| 4154 | 1352768132U, // DUPv2i32lane |
| 4155 | 12688004U, // DUPv2i64gpr |
| 4156 | 1354865284U, // DUPv2i64lane |
| 4157 | 14785156U, // DUPv4i16gpr |
| 4158 | 1356962436U, // DUPv4i16lane |
| 4159 | 16882308U, // DUPv4i32gpr |
| 4160 | 1359059588U, // DUPv4i32lane |
| 4161 | 18979460U, // DUPv8i16gpr |
| 4162 | 1361156740U, // DUPv8i16lane |
| 4163 | 21076612U, // DUPv8i8gpr |
| 4164 | 1363253892U, // DUPv8i8lane |
| 4165 | 2119699U, // EONWrs |
| 4166 | 2119699U, // EONXrs |
| 4167 | 1350664828U, // EOR3 |
| 4168 | 2686501500U, // EOR3_ZZZZ |
| 4169 | 2686492420U, // EORBT_ZZZ_B |
| 4170 | 1612766980U, // EORBT_ZZZ_D |
| 4171 | 2460032772U, // EORBT_ZZZ_H |
| 4172 | 1881235204U, // EORBT_ZZZ_S |
| 4173 | 813802315U, // EORQV_VPZ_B |
| 4174 | 817996619U, // EORQV_VPZ_D |
| 4175 | 824288075U, // EORQV_VPZ_H |
| 4176 | 822190923U, // EORQV_VPZ_S |
| 4177 | 807444108U, // EORS_PPzPP |
| 4178 | 2686487092U, // EORTB_ZZZ_B |
| 4179 | 1612761652U, // EORTB_ZZZ_D |
| 4180 | 2460027444U, // EORTB_ZZZ_H |
| 4181 | 1881229876U, // EORTB_ZZZ_S |
| 4182 | 254826U, // EORV_VPZ_B |
| 4183 | 579085162U, // EORV_VPZ_D |
| 4184 | 581198698U, // EORV_VPZ_H |
| 4185 | 562340714U, // EORV_VPZ_S |
| 4186 | 2120824U, // EORWri |
| 4187 | 2120824U, // EORWrs |
| 4188 | 2120824U, // EORXri |
| 4189 | 2120824U, // EORXrs |
| 4190 | 807443576U, // EOR_PPzPP |
| 4191 | 2686508152U, // EOR_ZI |
| 4192 | 807443576U, // EOR_ZPmZ_B |
| 4193 | 807459960U, // EOR_ZPmZ_D |
| 4194 | 543235192U, // EOR_ZPmZ_H |
| 4195 | 807492728U, // EOR_ZPmZ_S |
| 4196 | 2686508152U, // EOR_ZZZ |
| 4197 | 1350671480U, // EORv16i8 |
| 4198 | 1363254392U, // EORv8i8 |
| 4199 | 11558U, // ERET |
| 4200 | 11434U, // ERETAA |
| 4201 | 11441U, // ERETAB |
| 4202 | 807439474U, // EXPAND_ZPZ_B |
| 4203 | 807455858U, // EXPAND_ZPZ_D |
| 4204 | 2422279282U, // EXPAND_ZPZ_H |
| 4205 | 807488626U, // EXPAND_ZPZ_S |
| 4206 | 3491797813U, // EXTQ_ZZI |
| 4207 | 270566719U, // EXTRACT_ZPMXI_H_B |
| 4208 | 270583103U, // EXTRACT_ZPMXI_H_D |
| 4209 | 541132095U, // EXTRACT_ZPMXI_H_H |
| 4210 | 541541695U, // EXTRACT_ZPMXI_H_Q |
| 4211 | 270615871U, // EXTRACT_ZPMXI_H_S |
| 4212 | 270566719U, // EXTRACT_ZPMXI_V_B |
| 4213 | 270583103U, // EXTRACT_ZPMXI_V_D |
| 4214 | 541132095U, // EXTRACT_ZPMXI_V_H |
| 4215 | 541541695U, // EXTRACT_ZPMXI_V_Q |
| 4216 | 270615871U, // EXTRACT_ZPMXI_V_S |
| 4217 | 2120913U, // EXTRWrri |
| 4218 | 2120913U, // EXTRXrri |
| 4219 | 3491799597U, // EXT_ZZI |
| 4220 | 1612751405U, // EXT_ZZI_B |
| 4221 | 1350672941U, // EXTv16i8 |
| 4222 | 1363255853U, // EXTv8i8 |
| 4223 | 1361155711U, // F1CVTL |
| 4224 | 1361150341U, // F1CVTL2 |
| 4225 | 583082150U, // F1CVTLT_ZZ_BtoH |
| 4226 | 583194239U, // F1CVTL_2ZZ_BtoH |
| 4227 | 583197154U, // F1CVT_2ZZ_BtoH |
| 4228 | 583082466U, // F1CVT_ZZ_BtoH |
| 4229 | 1361155720U, // F2CVTL |
| 4230 | 1361150351U, // F2CVTL2 |
| 4231 | 583082160U, // F2CVTLT_ZZ_BtoH |
| 4232 | 583194248U, // F2CVTL_2ZZ_BtoH |
| 4233 | 583197162U, // F2CVT_2ZZ_BtoH |
| 4234 | 583082474U, // F2CVT_ZZ_BtoH |
| 4235 | 2116528U, // FABD16 |
| 4236 | 2116528U, // FABD32 |
| 4237 | 2116528U, // FABD64 |
| 4238 | 807455664U, // FABD_ZPmZ_D |
| 4239 | 543230896U, // FABD_ZPmZ_H |
| 4240 | 807488432U, // FABD_ZPmZ_S |
| 4241 | 1352764336U, // FABDv2f32 |
| 4242 | 1354861488U, // FABDv2f64 |
| 4243 | 1356958640U, // FABDv4f16 |
| 4244 | 1359055792U, // FABDv4f32 |
| 4245 | 1361152944U, // FABDv8f16 |
| 4246 | 2121105U, // FABSDr |
| 4247 | 2121105U, // FABSHr |
| 4248 | 2121105U, // FABSSr |
| 4249 | 270589329U, // FABS_ZPmZ_D |
| 4250 | 541138321U, // FABS_ZPmZ_H |
| 4251 | 270622097U, // FABS_ZPmZ_S |
| 4252 | 807460241U, // FABS_ZPzZ_D |
| 4253 | 1080106385U, // FABS_ZPzZ_H |
| 4254 | 807493009U, // FABS_ZPzZ_S |
| 4255 | 1352768913U, // FABSv2f32 |
| 4256 | 1354866065U, // FABSv2f64 |
| 4257 | 1356963217U, // FABSv4f16 |
| 4258 | 1359060369U, // FABSv4f32 |
| 4259 | 1361157521U, // FABSv8f16 |
| 4260 | 2116804U, // FACGE16 |
| 4261 | 2116804U, // FACGE32 |
| 4262 | 2116804U, // FACGE64 |
| 4263 | 807455940U, // FACGE_PPzZZ_D |
| 4264 | 1080102084U, // FACGE_PPzZZ_H |
| 4265 | 807488708U, // FACGE_PPzZZ_S |
| 4266 | 1352764612U, // FACGEv2f32 |
| 4267 | 1354861764U, // FACGEv2f64 |
| 4268 | 1356958916U, // FACGEv4f16 |
| 4269 | 1359056068U, // FACGEv4f32 |
| 4270 | 1361153220U, // FACGEv8f16 |
| 4271 | 2121548U, // FACGT16 |
| 4272 | 2121548U, // FACGT32 |
| 4273 | 2121548U, // FACGT64 |
| 4274 | 807460684U, // FACGT_PPzZZ_D |
| 4275 | 1080106828U, // FACGT_PPzZZ_H |
| 4276 | 807493452U, // FACGT_PPzZZ_S |
| 4277 | 1352769356U, // FACGTv2f32 |
| 4278 | 1354866508U, // FACGTv2f64 |
| 4279 | 1356963660U, // FACGTv4f16 |
| 4280 | 1359060812U, // FACGTv4f32 |
| 4281 | 1361157964U, // FACGTv8f16 |
| 4282 | 61080354U, // FADDA_VPZ_D |
| 4283 | 2479112994U, // FADDA_VPZ_H |
| 4284 | 65307426U, // FADDA_VPZ_S |
| 4285 | 2116610U, // FADDDrr |
| 4286 | 2116610U, // FADDHrr |
| 4287 | 807459109U, // FADDP_ZPmZZ_D |
| 4288 | 543234341U, // FADDP_ZPmZZ_H |
| 4289 | 807491877U, // FADDP_ZPmZZ_S |
| 4290 | 1352767781U, // FADDPv2f32 |
| 4291 | 1354864933U, // FADDPv2f64 |
| 4292 | 1344297253U, // FADDPv2i16p |
| 4293 | 1344297253U, // FADDPv2i32p |
| 4294 | 1344297253U, // FADDPv2i64p |
| 4295 | 1356962085U, // FADDPv4f16 |
| 4296 | 1359059237U, // FADDPv4f32 |
| 4297 | 1361156389U, // FADDPv8f16 |
| 4298 | 817996560U, // FADDQV_D |
| 4299 | 824288016U, // FADDQV_H |
| 4300 | 822190864U, // FADDQV_S |
| 4301 | 2116610U, // FADDSrr |
| 4302 | 579084936U, // FADDV_VPZ_D |
| 4303 | 581198472U, // FADDV_VPZ_H |
| 4304 | 562340488U, // FADDV_VPZ_S |
| 4305 | 4064496642U, // FADD_VG2_M2Z_D |
| 4306 | 4064644098U, // FADD_VG2_M2Z_H |
| 4307 | 4064513026U, // FADD_VG2_M2Z_S |
| 4308 | 37964802U, // FADD_VG4_M4Z_D |
| 4309 | 38112258U, // FADD_VG4_M4Z_H |
| 4310 | 37981186U, // FADD_VG4_M4Z_S |
| 4311 | 807455746U, // FADD_ZPmI_D |
| 4312 | 543230978U, // FADD_ZPmI_H |
| 4313 | 807488514U, // FADD_ZPmI_S |
| 4314 | 807455746U, // FADD_ZPmZ_D |
| 4315 | 543230978U, // FADD_ZPmZ_H |
| 4316 | 807488514U, // FADD_ZPmZ_S |
| 4317 | 2686503938U, // FADD_ZZZ_D |
| 4318 | 2443250690U, // FADD_ZZZ_H |
| 4319 | 3760278530U, // FADD_ZZZ_S |
| 4320 | 1352764418U, // FADDv2f32 |
| 4321 | 1354861570U, // FADDv2f64 |
| 4322 | 1356958722U, // FADDv4f16 |
| 4323 | 1359055874U, // FADDv4f32 |
| 4324 | 1361153026U, // FADDv8f16 |
| 4325 | 2447549652U, // FAMAX_2Z2Z_D |
| 4326 | 2449663188U, // FAMAX_2Z2Z_H |
| 4327 | 2451776724U, // FAMAX_2Z2Z_S |
| 4328 | 2447549652U, // FAMAX_4Z4Z_D |
| 4329 | 2449663188U, // FAMAX_4Z4Z_H |
| 4330 | 2451776724U, // FAMAX_4Z4Z_S |
| 4331 | 807462100U, // FAMAX_ZPmZ_D |
| 4332 | 543237332U, // FAMAX_ZPmZ_H |
| 4333 | 807494868U, // FAMAX_ZPmZ_S |
| 4334 | 1352770772U, // FAMAXv2f32 |
| 4335 | 1354867924U, // FAMAXv2f64 |
| 4336 | 1356965076U, // FAMAXv4f16 |
| 4337 | 1359062228U, // FAMAXv4f32 |
| 4338 | 1361159380U, // FAMAXv8f16 |
| 4339 | 2447546318U, // FAMIN_2Z2Z_D |
| 4340 | 2449659854U, // FAMIN_2Z2Z_H |
| 4341 | 2451773390U, // FAMIN_2Z2Z_S |
| 4342 | 2447546318U, // FAMIN_4Z4Z_D |
| 4343 | 2449659854U, // FAMIN_4Z4Z_H |
| 4344 | 2451773390U, // FAMIN_4Z4Z_S |
| 4345 | 807458766U, // FAMIN_ZPmZ_D |
| 4346 | 543233998U, // FAMIN_ZPmZ_H |
| 4347 | 807491534U, // FAMIN_ZPmZ_S |
| 4348 | 1352767438U, // FAMINv2f32 |
| 4349 | 1354864590U, // FAMINv2f64 |
| 4350 | 1356961742U, // FAMINv4f16 |
| 4351 | 1359058894U, // FAMINv4f32 |
| 4352 | 1361156046U, // FAMINv8f16 |
| 4353 | 807455721U, // FCADD_ZPmZ_D |
| 4354 | 543230953U, // FCADD_ZPmZ_H |
| 4355 | 807488489U, // FCADD_ZPmZ_S |
| 4356 | 1352764393U, // FCADDv2f32 |
| 4357 | 1354861545U, // FCADDv2f64 |
| 4358 | 1356958697U, // FCADDv4f16 |
| 4359 | 1359055849U, // FCADDv4f32 |
| 4360 | 1361153001U, // FCADDv8f16 |
| 4361 | 2120072U, // FCCMPDrr |
| 4362 | 2116932U, // FCCMPEDrr |
| 4363 | 2116932U, // FCCMPEHrr |
| 4364 | 2116932U, // FCCMPESrr |
| 4365 | 2120072U, // FCCMPHrr |
| 4366 | 2120072U, // FCCMPSrr |
| 4367 | 2458032496U, // FCLAMP_VG2_2Z2Z_D |
| 4368 | 2460146032U, // FCLAMP_VG2_2Z2Z_H |
| 4369 | 2441288048U, // FCLAMP_VG2_2Z2Z_S |
| 4370 | 2458032496U, // FCLAMP_VG4_4Z4Z_D |
| 4371 | 2460146032U, // FCLAMP_VG4_4Z4Z_H |
| 4372 | 2441288048U, // FCLAMP_VG4_4Z4Z_S |
| 4373 | 1612765552U, // FCLAMP_ZZZ_D |
| 4374 | 2460031344U, // FCLAMP_ZZZ_H |
| 4375 | 1881233776U, // FCLAMP_ZZZ_S |
| 4376 | 2120466U, // FCMEQ16 |
| 4377 | 2120466U, // FCMEQ32 |
| 4378 | 2120466U, // FCMEQ64 |
| 4379 | 807459602U, // FCMEQ_PPzZ0_D |
| 4380 | 1080105746U, // FCMEQ_PPzZ0_H |
| 4381 | 807492370U, // FCMEQ_PPzZ0_S |
| 4382 | 807459602U, // FCMEQ_PPzZZ_D |
| 4383 | 1080105746U, // FCMEQ_PPzZZ_H |
| 4384 | 807492370U, // FCMEQ_PPzZZ_S |
| 4385 | 2120466U, // FCMEQv1i16rz |
| 4386 | 2120466U, // FCMEQv1i32rz |
| 4387 | 2120466U, // FCMEQv1i64rz |
| 4388 | 1352768274U, // FCMEQv2f32 |
| 4389 | 1354865426U, // FCMEQv2f64 |
| 4390 | 1352768274U, // FCMEQv2i32rz |
| 4391 | 1354865426U, // FCMEQv2i64rz |
| 4392 | 1356962578U, // FCMEQv4f16 |
| 4393 | 1359059730U, // FCMEQv4f32 |
| 4394 | 1356962578U, // FCMEQv4i16rz |
| 4395 | 1359059730U, // FCMEQv4i32rz |
| 4396 | 1361156882U, // FCMEQv8f16 |
| 4397 | 1361156882U, // FCMEQv8i16rz |
| 4398 | 2116827U, // FCMGE16 |
| 4399 | 2116827U, // FCMGE32 |
| 4400 | 2116827U, // FCMGE64 |
| 4401 | 807455963U, // FCMGE_PPzZ0_D |
| 4402 | 1080102107U, // FCMGE_PPzZ0_H |
| 4403 | 807488731U, // FCMGE_PPzZ0_S |
| 4404 | 807455963U, // FCMGE_PPzZZ_D |
| 4405 | 1080102107U, // FCMGE_PPzZZ_H |
| 4406 | 807488731U, // FCMGE_PPzZZ_S |
| 4407 | 2116827U, // FCMGEv1i16rz |
| 4408 | 2116827U, // FCMGEv1i32rz |
| 4409 | 2116827U, // FCMGEv1i64rz |
| 4410 | 1352764635U, // FCMGEv2f32 |
| 4411 | 1354861787U, // FCMGEv2f64 |
| 4412 | 1352764635U, // FCMGEv2i32rz |
| 4413 | 1354861787U, // FCMGEv2i64rz |
| 4414 | 1356958939U, // FCMGEv4f16 |
| 4415 | 1359056091U, // FCMGEv4f32 |
| 4416 | 1356958939U, // FCMGEv4i16rz |
| 4417 | 1359056091U, // FCMGEv4i32rz |
| 4418 | 1361153243U, // FCMGEv8f16 |
| 4419 | 1361153243U, // FCMGEv8i16rz |
| 4420 | 2121571U, // FCMGT16 |
| 4421 | 2121571U, // FCMGT32 |
| 4422 | 2121571U, // FCMGT64 |
| 4423 | 807460707U, // FCMGT_PPzZ0_D |
| 4424 | 1080106851U, // FCMGT_PPzZ0_H |
| 4425 | 807493475U, // FCMGT_PPzZ0_S |
| 4426 | 807460707U, // FCMGT_PPzZZ_D |
| 4427 | 1080106851U, // FCMGT_PPzZZ_H |
| 4428 | 807493475U, // FCMGT_PPzZZ_S |
| 4429 | 2121571U, // FCMGTv1i16rz |
| 4430 | 2121571U, // FCMGTv1i32rz |
| 4431 | 2121571U, // FCMGTv1i64rz |
| 4432 | 1352769379U, // FCMGTv2f32 |
| 4433 | 1354866531U, // FCMGTv2f64 |
| 4434 | 1352769379U, // FCMGTv2i32rz |
| 4435 | 1354866531U, // FCMGTv2i64rz |
| 4436 | 1356963683U, // FCMGTv4f16 |
| 4437 | 1359060835U, // FCMGTv4f32 |
| 4438 | 1356963683U, // FCMGTv4i16rz |
| 4439 | 1359060835U, // FCMGTv4i32rz |
| 4440 | 1361157987U, // FCMGTv8f16 |
| 4441 | 1361157987U, // FCMGTv8i16rz |
| 4442 | 807453540U, // FCMLA_ZPmZZ_D |
| 4443 | 543228772U, // FCMLA_ZPmZZ_H |
| 4444 | 807486308U, // FCMLA_ZPmZZ_S |
| 4445 | 2460025700U, // FCMLA_ZZZI_H |
| 4446 | 1881228132U, // FCMLA_ZZZI_S |
| 4447 | 3231843172U, // FCMLAv2f32 |
| 4448 | 3233940324U, // FCMLAv2f64 |
| 4449 | 3236037476U, // FCMLAv4f16 |
| 4450 | 3236037476U, // FCMLAv4f16_indexed |
| 4451 | 3238134628U, // FCMLAv4f32 |
| 4452 | 3238134628U, // FCMLAv4f32_indexed |
| 4453 | 3240231780U, // FCMLAv8f16 |
| 4454 | 3240231780U, // FCMLAv8f16_indexed |
| 4455 | 807455995U, // FCMLE_PPzZ0_D |
| 4456 | 1080102139U, // FCMLE_PPzZ0_H |
| 4457 | 807488763U, // FCMLE_PPzZ0_S |
| 4458 | 2116859U, // FCMLEv1i16rz |
| 4459 | 2116859U, // FCMLEv1i32rz |
| 4460 | 2116859U, // FCMLEv1i64rz |
| 4461 | 1352764667U, // FCMLEv2i32rz |
| 4462 | 1354861819U, // FCMLEv2i64rz |
| 4463 | 1356958971U, // FCMLEv4i16rz |
| 4464 | 1359056123U, // FCMLEv4i32rz |
| 4465 | 1361153275U, // FCMLEv8i16rz |
| 4466 | 807460965U, // FCMLT_PPzZ0_D |
| 4467 | 1080107109U, // FCMLT_PPzZ0_H |
| 4468 | 807493733U, // FCMLT_PPzZ0_S |
| 4469 | 2121829U, // FCMLTv1i16rz |
| 4470 | 2121829U, // FCMLTv1i32rz |
| 4471 | 2121829U, // FCMLTv1i64rz |
| 4472 | 1352769637U, // FCMLTv2i32rz |
| 4473 | 1354866789U, // FCMLTv2i64rz |
| 4474 | 1356963941U, // FCMLTv4i16rz |
| 4475 | 1359061093U, // FCMLTv4i32rz |
| 4476 | 1361158245U, // FCMLTv8i16rz |
| 4477 | 807456029U, // FCMNE_PPzZ0_D |
| 4478 | 1080102173U, // FCMNE_PPzZ0_H |
| 4479 | 807488797U, // FCMNE_PPzZ0_S |
| 4480 | 807456029U, // FCMNE_PPzZZ_D |
| 4481 | 1080102173U, // FCMNE_PPzZZ_H |
| 4482 | 807488797U, // FCMNE_PPzZZ_S |
| 4483 | 67131791U, // FCMPDri |
| 4484 | 2120079U, // FCMPDrr |
| 4485 | 67128652U, // FCMPEDri |
| 4486 | 2116940U, // FCMPEDrr |
| 4487 | 67128652U, // FCMPEHri |
| 4488 | 2116940U, // FCMPEHrr |
| 4489 | 67128652U, // FCMPESri |
| 4490 | 2116940U, // FCMPESrr |
| 4491 | 67131791U, // FCMPHri |
| 4492 | 2120079U, // FCMPHrr |
| 4493 | 67131791U, // FCMPSri |
| 4494 | 2120079U, // FCMPSrr |
| 4495 | 807459048U, // FCMUO_PPzZZ_D |
| 4496 | 1080105192U, // FCMUO_PPzZZ_H |
| 4497 | 807491816U, // FCMUO_PPzZZ_S |
| 4498 | 270591321U, // FCPY_ZPmI_D |
| 4499 | 541140313U, // FCPY_ZPmI_H |
| 4500 | 270624089U, // FCPY_ZPmI_S |
| 4501 | 2118698U, // FCSELDrrr |
| 4502 | 2118698U, // FCSELHrrr |
| 4503 | 2118698U, // FCSELSrrr |
| 4504 | 2121097U, // FCVTASDHr |
| 4505 | 2121097U, // FCVTASDSr |
| 4506 | 2121097U, // FCVTASSDr |
| 4507 | 2121097U, // FCVTASSHr |
| 4508 | 2121097U, // FCVTASUWDr |
| 4509 | 2121097U, // FCVTASUWHr |
| 4510 | 2121097U, // FCVTASUWSr |
| 4511 | 2121097U, // FCVTASUXDr |
| 4512 | 2121097U, // FCVTASUXHr |
| 4513 | 2121097U, // FCVTASUXSr |
| 4514 | 2121097U, // FCVTASv1f16 |
| 4515 | 2121097U, // FCVTASv1i32 |
| 4516 | 2121097U, // FCVTASv1i64 |
| 4517 | 1352768905U, // FCVTASv2f32 |
| 4518 | 1354866057U, // FCVTASv2f64 |
| 4519 | 1356963209U, // FCVTASv4f16 |
| 4520 | 1359060361U, // FCVTASv4f32 |
| 4521 | 1361157513U, // FCVTASv8f16 |
| 4522 | 2122303U, // FCVTAUDHr |
| 4523 | 2122303U, // FCVTAUDSr |
| 4524 | 2122303U, // FCVTAUSDr |
| 4525 | 2122303U, // FCVTAUSHr |
| 4526 | 2122303U, // FCVTAUUWDr |
| 4527 | 2122303U, // FCVTAUUWHr |
| 4528 | 2122303U, // FCVTAUUWSr |
| 4529 | 2122303U, // FCVTAUUXDr |
| 4530 | 2122303U, // FCVTAUUXHr |
| 4531 | 2122303U, // FCVTAUUXSr |
| 4532 | 2122303U, // FCVTAUv1f16 |
| 4533 | 2122303U, // FCVTAUv1i32 |
| 4534 | 2122303U, // FCVTAUv1i64 |
| 4535 | 1352770111U, // FCVTAUv2f32 |
| 4536 | 1354867263U, // FCVTAUv2f64 |
| 4537 | 1356964415U, // FCVTAUv4f16 |
| 4538 | 1359061567U, // FCVTAUv4f32 |
| 4539 | 1361158719U, // FCVTAUv8f16 |
| 4540 | 2122226U, // FCVTDHr |
| 4541 | 2122226U, // FCVTDSr |
| 4542 | 2122226U, // FCVTHDr |
| 4543 | 2122226U, // FCVTHSr |
| 4544 | 270622905U, // FCVTLT_ZPmZ_HtoS |
| 4545 | 270590137U, // FCVTLT_ZPmZ_StoD |
| 4546 | 807493817U, // FCVTLT_ZPzZ_HtoS |
| 4547 | 807461049U, // FCVTLT_ZPzZ_StoD |
| 4548 | 564336272U, // FCVTL_2ZZ_H_S |
| 4549 | 1354864272U, // FCVTLv2i32 |
| 4550 | 1359058576U, // FCVTLv4i16 |
| 4551 | 1354858904U, // FCVTLv4i32 |
| 4552 | 1359053208U, // FCVTLv8i16 |
| 4553 | 2121255U, // FCVTMSDHr |
| 4554 | 2121255U, // FCVTMSDSr |
| 4555 | 2121255U, // FCVTMSSDr |
| 4556 | 2121255U, // FCVTMSSHr |
| 4557 | 2121255U, // FCVTMSUWDr |
| 4558 | 2121255U, // FCVTMSUWHr |
| 4559 | 2121255U, // FCVTMSUWSr |
| 4560 | 2121255U, // FCVTMSUXDr |
| 4561 | 2121255U, // FCVTMSUXHr |
| 4562 | 2121255U, // FCVTMSUXSr |
| 4563 | 2121255U, // FCVTMSv1f16 |
| 4564 | 2121255U, // FCVTMSv1i32 |
| 4565 | 2121255U, // FCVTMSv1i64 |
| 4566 | 1352769063U, // FCVTMSv2f32 |
| 4567 | 1354866215U, // FCVTMSv2f64 |
| 4568 | 1356963367U, // FCVTMSv4f16 |
| 4569 | 1359060519U, // FCVTMSv4f32 |
| 4570 | 1361157671U, // FCVTMSv8f16 |
| 4571 | 2122319U, // FCVTMUDHr |
| 4572 | 2122319U, // FCVTMUDSr |
| 4573 | 2122319U, // FCVTMUSDr |
| 4574 | 2122319U, // FCVTMUSHr |
| 4575 | 2122319U, // FCVTMUUWDr |
| 4576 | 2122319U, // FCVTMUUWHr |
| 4577 | 2122319U, // FCVTMUUWSr |
| 4578 | 2122319U, // FCVTMUUXDr |
| 4579 | 2122319U, // FCVTMUUXHr |
| 4580 | 2122319U, // FCVTMUUXSr |
| 4581 | 2122319U, // FCVTMUv1f16 |
| 4582 | 2122319U, // FCVTMUv1i32 |
| 4583 | 2122319U, // FCVTMUv1i64 |
| 4584 | 1352770127U, // FCVTMUv2f32 |
| 4585 | 1354867279U, // FCVTMUv2f64 |
| 4586 | 1356964431U, // FCVTMUv4f16 |
| 4587 | 1359061583U, // FCVTMUv4f32 |
| 4588 | 1361158735U, // FCVTMUv8f16 |
| 4589 | 1881180343U, // FCVTNB_Z2Z_StoB |
| 4590 | 2121281U, // FCVTNSDHr |
| 4591 | 2121281U, // FCVTNSDSr |
| 4592 | 2121281U, // FCVTNSSDr |
| 4593 | 2121281U, // FCVTNSSHr |
| 4594 | 2121281U, // FCVTNSUWDr |
| 4595 | 2121281U, // FCVTNSUWHr |
| 4596 | 2121281U, // FCVTNSUWSr |
| 4597 | 2121281U, // FCVTNSUXDr |
| 4598 | 2121281U, // FCVTNSUXHr |
| 4599 | 2121281U, // FCVTNSUXSr |
| 4600 | 2121281U, // FCVTNSv1f16 |
| 4601 | 2121281U, // FCVTNSv1i32 |
| 4602 | 2121281U, // FCVTNSv1i64 |
| 4603 | 1352769089U, // FCVTNSv2f32 |
| 4604 | 1354866241U, // FCVTNSv2f64 |
| 4605 | 1356963393U, // FCVTNSv4f16 |
| 4606 | 1359060545U, // FCVTNSv4f32 |
| 4607 | 1361157697U, // FCVTNSv8f16 |
| 4608 | 2149622025U, // FCVTNT_Z2Z_StoB |
| 4609 | 270622985U, // FCVTNT_ZPmZ_DtoS |
| 4610 | 541139209U, // FCVTNT_ZPmZ_StoH |
| 4611 | 270622985U, // FCVTNT_ZPzZ_DtoS |
| 4612 | 1078010121U, // FCVTNT_ZPzZ_StoH |
| 4613 | 2122327U, // FCVTNUDHr |
| 4614 | 2122327U, // FCVTNUDSr |
| 4615 | 2122327U, // FCVTNUSDr |
| 4616 | 2122327U, // FCVTNUSHr |
| 4617 | 2122327U, // FCVTNUUWDr |
| 4618 | 2122327U, // FCVTNUUWHr |
| 4619 | 2122327U, // FCVTNUUWSr |
| 4620 | 2122327U, // FCVTNUUXDr |
| 4621 | 2122327U, // FCVTNUUXHr |
| 4622 | 2122327U, // FCVTNUUXSr |
| 4623 | 2122327U, // FCVTNUv1f16 |
| 4624 | 2122327U, // FCVTNUv1i32 |
| 4625 | 2122327U, // FCVTNUv1i64 |
| 4626 | 1352770135U, // FCVTNUv2f32 |
| 4627 | 1354867287U, // FCVTNUv2f64 |
| 4628 | 1356964439U, // FCVTNUv4f16 |
| 4629 | 1359061591U, // FCVTNUv4f32 |
| 4630 | 1361158743U, // FCVTNUv8f16 |
| 4631 | 1350670417U, // FCVTN_F16v16f8 |
| 4632 | 1363253329U, // FCVTN_F16v8f8 |
| 4633 | 3229745631U, // FCVTN_F322v16f8 |
| 4634 | 1363253329U, // FCVTN_F32v8f8 |
| 4635 | 1075877969U, // FCVTN_Z2Z_HtoB |
| 4636 | 572594257U, // FCVTN_Z2Z_StoH |
| 4637 | 1881184337U, // FCVTN_Z4Z_StoB |
| 4638 | 1352767569U, // FCVTNv2i32 |
| 4639 | 1356961873U, // FCVTNv4i16 |
| 4640 | 3238134239U, // FCVTNv4i32 |
| 4641 | 3240231391U, // FCVTNv8i16 |
| 4642 | 2121335U, // FCVTPSDHr |
| 4643 | 2121335U, // FCVTPSDSr |
| 4644 | 2121335U, // FCVTPSSDr |
| 4645 | 2121335U, // FCVTPSSHr |
| 4646 | 2121335U, // FCVTPSUWDr |
| 4647 | 2121335U, // FCVTPSUWHr |
| 4648 | 2121335U, // FCVTPSUWSr |
| 4649 | 2121335U, // FCVTPSUXDr |
| 4650 | 2121335U, // FCVTPSUXHr |
| 4651 | 2121335U, // FCVTPSUXSr |
| 4652 | 2121335U, // FCVTPSv1f16 |
| 4653 | 2121335U, // FCVTPSv1i32 |
| 4654 | 2121335U, // FCVTPSv1i64 |
| 4655 | 1352769143U, // FCVTPSv2f32 |
| 4656 | 1354866295U, // FCVTPSv2f64 |
| 4657 | 1356963447U, // FCVTPSv4f16 |
| 4658 | 1359060599U, // FCVTPSv4f32 |
| 4659 | 1361157751U, // FCVTPSv8f16 |
| 4660 | 2122335U, // FCVTPUDHr |
| 4661 | 2122335U, // FCVTPUDSr |
| 4662 | 2122335U, // FCVTPUSDr |
| 4663 | 2122335U, // FCVTPUSHr |
| 4664 | 2122335U, // FCVTPUUWDr |
| 4665 | 2122335U, // FCVTPUUWHr |
| 4666 | 2122335U, // FCVTPUUWSr |
| 4667 | 2122335U, // FCVTPUUXDr |
| 4668 | 2122335U, // FCVTPUUXHr |
| 4669 | 2122335U, // FCVTPUUXSr |
| 4670 | 2122335U, // FCVTPUv1f16 |
| 4671 | 2122335U, // FCVTPUv1i32 |
| 4672 | 2122335U, // FCVTPUv1i64 |
| 4673 | 1352770143U, // FCVTPUv2f32 |
| 4674 | 1354867295U, // FCVTPUv2f64 |
| 4675 | 1356964447U, // FCVTPUv4f16 |
| 4676 | 1359061599U, // FCVTPUv4f32 |
| 4677 | 1361158751U, // FCVTPUv8f16 |
| 4678 | 2122226U, // FCVTSDr |
| 4679 | 2122226U, // FCVTSHr |
| 4680 | 270623039U, // FCVTXNT_ZPmZ_DtoS |
| 4681 | 270623039U, // FCVTXNT_ZPzZ_StoD |
| 4682 | 2119849U, // FCVTXNv1i64 |
| 4683 | 1352767657U, // FCVTXNv2f32 |
| 4684 | 3238134293U, // FCVTXNv4f32 |
| 4685 | 270624073U, // FCVTX_ZPmZ_DtoS |
| 4686 | 807494985U, // FCVTX_ZPzZ_DtoS |
| 4687 | 2121394U, // FCVTZSDHr |
| 4688 | 2121394U, // FCVTZSDSr |
| 4689 | 2418104383U, // FCVTZSN_Z2Z_DtoS |
| 4690 | 1075877951U, // FCVTZSN_Z2Z_HtoB |
| 4691 | 572594239U, // FCVTZSN_Z2Z_StoH |
| 4692 | 2121394U, // FCVTZSSDr |
| 4693 | 2121394U, // FCVTZSSHr |
| 4694 | 2121394U, // FCVTZSSWDri |
| 4695 | 2121394U, // FCVTZSSWHri |
| 4696 | 2121394U, // FCVTZSSWSri |
| 4697 | 2121394U, // FCVTZSSXDri |
| 4698 | 2121394U, // FCVTZSSXHri |
| 4699 | 2121394U, // FCVTZSSXSri |
| 4700 | 2121394U, // FCVTZSUWDr |
| 4701 | 2121394U, // FCVTZSUWHr |
| 4702 | 2121394U, // FCVTZSUWSr |
| 4703 | 2121394U, // FCVTZSUXDr |
| 4704 | 2121394U, // FCVTZSUXHr |
| 4705 | 2121394U, // FCVTZSUXSr |
| 4706 | 572726962U, // FCVTZS_2Z2Z_StoS |
| 4707 | 572726962U, // FCVTZS_4Z4Z_StoS |
| 4708 | 270589618U, // FCVTZS_ZPmZ_DtoD |
| 4709 | 270622386U, // FCVTZS_ZPmZ_DtoS |
| 4710 | 270589618U, // FCVTZS_ZPmZ_HtoD |
| 4711 | 541138610U, // FCVTZS_ZPmZ_HtoH |
| 4712 | 270622386U, // FCVTZS_ZPmZ_HtoS |
| 4713 | 270589618U, // FCVTZS_ZPmZ_StoD |
| 4714 | 270622386U, // FCVTZS_ZPmZ_StoS |
| 4715 | 807460530U, // FCVTZS_ZPzZ_DtoD |
| 4716 | 807493298U, // FCVTZS_ZPzZ_DtoS |
| 4717 | 807460530U, // FCVTZS_ZPzZ_HtoD |
| 4718 | 1080106674U, // FCVTZS_ZPzZ_HtoH |
| 4719 | 807493298U, // FCVTZS_ZPzZ_HtoS |
| 4720 | 807460530U, // FCVTZS_ZPzZ_StoD |
| 4721 | 807493298U, // FCVTZS_ZPzZ_StoS |
| 4722 | 2121394U, // FCVTZSd |
| 4723 | 2121394U, // FCVTZSh |
| 4724 | 2121394U, // FCVTZSs |
| 4725 | 2121394U, // FCVTZSv1f16 |
| 4726 | 2121394U, // FCVTZSv1i32 |
| 4727 | 2121394U, // FCVTZSv1i64 |
| 4728 | 1352769202U, // FCVTZSv2f32 |
| 4729 | 1354866354U, // FCVTZSv2f64 |
| 4730 | 1352769202U, // FCVTZSv2i32_shift |
| 4731 | 1354866354U, // FCVTZSv2i64_shift |
| 4732 | 1356963506U, // FCVTZSv4f16 |
| 4733 | 1359060658U, // FCVTZSv4f32 |
| 4734 | 1356963506U, // FCVTZSv4i16_shift |
| 4735 | 1359060658U, // FCVTZSv4i32_shift |
| 4736 | 1361157810U, // FCVTZSv8f16 |
| 4737 | 1361157810U, // FCVTZSv8i16_shift |
| 4738 | 2122360U, // FCVTZUDHr |
| 4739 | 2122360U, // FCVTZUDSr |
| 4740 | 2418104474U, // FCVTZUN_Z2Z_DtoS |
| 4741 | 1075878042U, // FCVTZUN_Z2Z_HtoB |
| 4742 | 572594330U, // FCVTZUN_Z2Z_StoH |
| 4743 | 2122360U, // FCVTZUSDr |
| 4744 | 2122360U, // FCVTZUSHr |
| 4745 | 2122360U, // FCVTZUSWDri |
| 4746 | 2122360U, // FCVTZUSWHri |
| 4747 | 2122360U, // FCVTZUSWSri |
| 4748 | 2122360U, // FCVTZUSXDri |
| 4749 | 2122360U, // FCVTZUSXHri |
| 4750 | 2122360U, // FCVTZUSXSri |
| 4751 | 2122360U, // FCVTZUUWDr |
| 4752 | 2122360U, // FCVTZUUWHr |
| 4753 | 2122360U, // FCVTZUUWSr |
| 4754 | 2122360U, // FCVTZUUXDr |
| 4755 | 2122360U, // FCVTZUUXHr |
| 4756 | 2122360U, // FCVTZUUXSr |
| 4757 | 572727928U, // FCVTZU_2Z2Z_StoS |
| 4758 | 572727928U, // FCVTZU_4Z4Z_StoS |
| 4759 | 270590584U, // FCVTZU_ZPmZ_DtoD |
| 4760 | 270623352U, // FCVTZU_ZPmZ_DtoS |
| 4761 | 270590584U, // FCVTZU_ZPmZ_HtoD |
| 4762 | 541139576U, // FCVTZU_ZPmZ_HtoH |
| 4763 | 270623352U, // FCVTZU_ZPmZ_HtoS |
| 4764 | 270590584U, // FCVTZU_ZPmZ_StoD |
| 4765 | 270623352U, // FCVTZU_ZPmZ_StoS |
| 4766 | 807461496U, // FCVTZU_ZPzZ_DtoD |
| 4767 | 807494264U, // FCVTZU_ZPzZ_DtoS |
| 4768 | 807461496U, // FCVTZU_ZPzZ_HtoD |
| 4769 | 1080107640U, // FCVTZU_ZPzZ_HtoH |
| 4770 | 807494264U, // FCVTZU_ZPzZ_HtoS |
| 4771 | 807461496U, // FCVTZU_ZPzZ_StoD |
| 4772 | 807494264U, // FCVTZU_ZPzZ_StoS |
| 4773 | 2122360U, // FCVTZUd |
| 4774 | 2122360U, // FCVTZUh |
| 4775 | 2122360U, // FCVTZUs |
| 4776 | 2122360U, // FCVTZUv1f16 |
| 4777 | 2122360U, // FCVTZUv1i32 |
| 4778 | 2122360U, // FCVTZUv1i64 |
| 4779 | 1352770168U, // FCVTZUv2f32 |
| 4780 | 1354867320U, // FCVTZUv2f64 |
| 4781 | 1352770168U, // FCVTZUv2i32_shift |
| 4782 | 1354867320U, // FCVTZUv2i64_shift |
| 4783 | 1356964472U, // FCVTZUv4f16 |
| 4784 | 1359061624U, // FCVTZUv4f32 |
| 4785 | 1356964472U, // FCVTZUv4i16_shift |
| 4786 | 1359061624U, // FCVTZUv4i32_shift |
| 4787 | 1361158776U, // FCVTZUv8f16 |
| 4788 | 1361158776U, // FCVTZUv8i16_shift |
| 4789 | 564339186U, // FCVT_2ZZ_H_S |
| 4790 | 1075880434U, // FCVT_Z2Z_HtoB |
| 4791 | 572596722U, // FCVT_Z2Z_StoH |
| 4792 | 1881186802U, // FCVT_Z4Z_StoB |
| 4793 | 541139442U, // FCVT_ZPmZ_DtoH |
| 4794 | 270623218U, // FCVT_ZPmZ_DtoS |
| 4795 | 270590450U, // FCVT_ZPmZ_HtoD |
| 4796 | 270623218U, // FCVT_ZPmZ_HtoS |
| 4797 | 270590450U, // FCVT_ZPmZ_StoD |
| 4798 | 541139442U, // FCVT_ZPmZ_StoH |
| 4799 | 1080107506U, // FCVT_ZPzZ_DtoH |
| 4800 | 807494130U, // FCVT_ZPzZ_DtoS |
| 4801 | 807461362U, // FCVT_ZPzZ_HtoD |
| 4802 | 807494130U, // FCVT_ZPzZ_HtoS |
| 4803 | 807461362U, // FCVT_ZPzZ_StoD |
| 4804 | 1080107506U, // FCVT_ZPzZ_StoH |
| 4805 | 2122408U, // FDIVDrr |
| 4806 | 2122408U, // FDIVHrr |
| 4807 | 807460082U, // FDIVR_ZPmZ_D |
| 4808 | 543235314U, // FDIVR_ZPmZ_H |
| 4809 | 807492850U, // FDIVR_ZPmZ_S |
| 4810 | 2122408U, // FDIVSrr |
| 4811 | 807461544U, // FDIV_ZPmZ_D |
| 4812 | 543236776U, // FDIV_ZPmZ_H |
| 4813 | 807494312U, // FDIV_ZPmZ_S |
| 4814 | 1352770216U, // FDIVv2f32 |
| 4815 | 1354867368U, // FDIVv2f64 |
| 4816 | 1356964520U, // FDIVv4f16 |
| 4817 | 1359061672U, // FDIVv4f32 |
| 4818 | 1361158824U, // FDIVv8f16 |
| 4819 | 4064649551U, // FDOT_VG2_M2Z2Z_BtoH |
| 4820 | 4064518479U, // FDOT_VG2_M2Z2Z_BtoS |
| 4821 | 4064518479U, // FDOT_VG2_M2Z2Z_HtoS |
| 4822 | 4064649551U, // FDOT_VG2_M2ZZI_BtoH |
| 4823 | 4064518479U, // FDOT_VG2_M2ZZI_BtoS |
| 4824 | 4064518479U, // FDOT_VG2_M2ZZI_HtoS |
| 4825 | 4064649551U, // FDOT_VG2_M2ZZ_BtoH |
| 4826 | 4064518479U, // FDOT_VG2_M2ZZ_BtoS |
| 4827 | 4064518479U, // FDOT_VG2_M2ZZ_HtoS |
| 4828 | 38117711U, // FDOT_VG4_M4Z4Z_BtoH |
| 4829 | 37986639U, // FDOT_VG4_M4Z4Z_BtoS |
| 4830 | 37986639U, // FDOT_VG4_M4Z4Z_HtoS |
| 4831 | 38117711U, // FDOT_VG4_M4ZZI_BtoH |
| 4832 | 37986639U, // FDOT_VG4_M4ZZI_BtoS |
| 4833 | 37986639U, // FDOT_VG4_M4ZZI_HtoS |
| 4834 | 38117711U, // FDOT_VG4_M4ZZ_BtoH |
| 4835 | 37986639U, // FDOT_VG4_M4ZZ_BtoS |
| 4836 | 37986639U, // FDOT_VG4_M4ZZ_HtoS |
| 4837 | 2485199183U, // FDOT_ZZZI_BtoH |
| 4838 | 2686542159U, // FDOT_ZZZI_BtoS |
| 4839 | 2954977615U, // FDOT_ZZZI_S |
| 4840 | 2485199183U, // FDOT_ZZZ_BtoH |
| 4841 | 2686542159U, // FDOT_ZZZ_BtoS |
| 4842 | 2954977615U, // FDOT_ZZZ_S |
| 4843 | 3231850831U, // FDOTlanev2f32 |
| 4844 | 3236045135U, // FDOTlanev4f16 |
| 4845 | 3231850831U, // FDOTlanev4f16_v2f32 |
| 4846 | 3238142287U, // FDOTlanev4f32 |
| 4847 | 3240239439U, // FDOTlanev8f16 |
| 4848 | 3238142287U, // FDOTlanev8f16_v4f32 |
| 4849 | 3231850831U, // FDOTv2f32 |
| 4850 | 3236045135U, // FDOTv4f16 |
| 4851 | 3231850831U, // FDOTv4f16_v2f32 |
| 4852 | 3238142287U, // FDOTv4f32 |
| 4853 | 3240239439U, // FDOTv8f16 |
| 4854 | 3238142287U, // FDOTv8f16_v4f32 |
| 4855 | 2686507651U, // FDUP_ZI_D |
| 4856 | 71375491U, // FDUP_ZI_H |
| 4857 | 2686540419U, // FDUP_ZI_S |
| 4858 | 2686502045U, // FEXPA_ZZ_D |
| 4859 | 564200605U, // FEXPA_ZZ_H |
| 4860 | 3760276637U, // FEXPA_ZZ_S |
| 4861 | 807426677U, // FIRSTP_XPP_B |
| 4862 | 807426677U, // FIRSTP_XPP_D |
| 4863 | 807426677U, // FIRSTP_XPP_H |
| 4864 | 807426677U, // FIRSTP_XPP_S |
| 4865 | 2121402U, // FJCVTZS |
| 4866 | 270583497U, // FLOGB_ZPmZ_D |
| 4867 | 541132489U, // FLOGB_ZPmZ_H |
| 4868 | 270616265U, // FLOGB_ZPmZ_S |
| 4869 | 807454409U, // FLOGB_ZPzZ_D |
| 4870 | 1080100553U, // FLOGB_ZPzZ_H |
| 4871 | 807487177U, // FLOGB_ZPzZ_S |
| 4872 | 2116671U, // FMADDDrrr |
| 4873 | 2116671U, // FMADDHrrr |
| 4874 | 2116671U, // FMADDSrrr |
| 4875 | 807455644U, // FMAD_ZPmZZ_D |
| 4876 | 543230876U, // FMAD_ZPmZZ_H |
| 4877 | 807488412U, // FMAD_ZPmZZ_S |
| 4878 | 2122974U, // FMAXDrr |
| 4879 | 2122974U, // FMAXHrr |
| 4880 | 2119531U, // FMAXNMDrr |
| 4881 | 2119531U, // FMAXNMHrr |
| 4882 | 807459230U, // FMAXNMP_ZPmZZ_D |
| 4883 | 543234462U, // FMAXNMP_ZPmZZ_H |
| 4884 | 807491998U, // FMAXNMP_ZPmZZ_S |
| 4885 | 1352767902U, // FMAXNMPv2f32 |
| 4886 | 1354865054U, // FMAXNMPv2f64 |
| 4887 | 1344297374U, // FMAXNMPv2i16p |
| 4888 | 1344297374U, // FMAXNMPv2i32p |
| 4889 | 1344297374U, // FMAXNMPv2i64p |
| 4890 | 1356962206U, // FMAXNMPv4f16 |
| 4891 | 1359059358U, // FMAXNMPv4f32 |
| 4892 | 1361156510U, // FMAXNMPv8f16 |
| 4893 | 817996585U, // FMAXNMQV_D |
| 4894 | 824288041U, // FMAXNMQV_H |
| 4895 | 822190889U, // FMAXNMQV_S |
| 4896 | 2119531U, // FMAXNMSrr |
| 4897 | 579085011U, // FMAXNMV_VPZ_D |
| 4898 | 581198547U, // FMAXNMV_VPZ_H |
| 4899 | 562340563U, // FMAXNMV_VPZ_S |
| 4900 | 1344299731U, // FMAXNMVv4i16v |
| 4901 | 1344299731U, // FMAXNMVv4i32v |
| 4902 | 1344299731U, // FMAXNMVv8i16v |
| 4903 | 2447546219U, // FMAXNM_VG2_2Z2Z_D |
| 4904 | 2449659755U, // FMAXNM_VG2_2Z2Z_H |
| 4905 | 2451773291U, // FMAXNM_VG2_2Z2Z_S |
| 4906 | 2447546219U, // FMAXNM_VG2_2ZZ_D |
| 4907 | 2449659755U, // FMAXNM_VG2_2ZZ_H |
| 4908 | 2451773291U, // FMAXNM_VG2_2ZZ_S |
| 4909 | 2447546219U, // FMAXNM_VG4_4Z4Z_D |
| 4910 | 2449659755U, // FMAXNM_VG4_4Z4Z_H |
| 4911 | 2451773291U, // FMAXNM_VG4_4Z4Z_S |
| 4912 | 2447546219U, // FMAXNM_VG4_4ZZ_D |
| 4913 | 2449659755U, // FMAXNM_VG4_4ZZ_H |
| 4914 | 2451773291U, // FMAXNM_VG4_4ZZ_S |
| 4915 | 807458667U, // FMAXNM_ZPmI_D |
| 4916 | 543233899U, // FMAXNM_ZPmI_H |
| 4917 | 807491435U, // FMAXNM_ZPmI_S |
| 4918 | 807458667U, // FMAXNM_ZPmZ_D |
| 4919 | 543233899U, // FMAXNM_ZPmZ_H |
| 4920 | 807491435U, // FMAXNM_ZPmZ_S |
| 4921 | 1352767339U, // FMAXNMv2f32 |
| 4922 | 1354864491U, // FMAXNMv2f64 |
| 4923 | 1356961643U, // FMAXNMv4f16 |
| 4924 | 1359058795U, // FMAXNMv4f32 |
| 4925 | 1361155947U, // FMAXNMv8f16 |
| 4926 | 807459489U, // FMAXP_ZPmZZ_D |
| 4927 | 543234721U, // FMAXP_ZPmZZ_H |
| 4928 | 807492257U, // FMAXP_ZPmZZ_S |
| 4929 | 1352768161U, // FMAXPv2f32 |
| 4930 | 1354865313U, // FMAXPv2f64 |
| 4931 | 1344297633U, // FMAXPv2i16p |
| 4932 | 1344297633U, // FMAXPv2i32p |
| 4933 | 1344297633U, // FMAXPv2i64p |
| 4934 | 1356962465U, // FMAXPv4f16 |
| 4935 | 1359059617U, // FMAXPv4f32 |
| 4936 | 1361156769U, // FMAXPv8f16 |
| 4937 | 817996626U, // FMAXQV_D |
| 4938 | 824288082U, // FMAXQV_H |
| 4939 | 822190930U, // FMAXQV_S |
| 4940 | 2122974U, // FMAXSrr |
| 4941 | 579085168U, // FMAXV_VPZ_D |
| 4942 | 581198704U, // FMAXV_VPZ_H |
| 4943 | 562340720U, // FMAXV_VPZ_S |
| 4944 | 1344299888U, // FMAXVv4i16v |
| 4945 | 1344299888U, // FMAXVv4i32v |
| 4946 | 1344299888U, // FMAXVv8i16v |
| 4947 | 2447549662U, // FMAX_VG2_2Z2Z_D |
| 4948 | 2449663198U, // FMAX_VG2_2Z2Z_H |
| 4949 | 2451776734U, // FMAX_VG2_2Z2Z_S |
| 4950 | 2447549662U, // FMAX_VG2_2ZZ_D |
| 4951 | 2449663198U, // FMAX_VG2_2ZZ_H |
| 4952 | 2451776734U, // FMAX_VG2_2ZZ_S |
| 4953 | 2447549662U, // FMAX_VG4_4Z4Z_D |
| 4954 | 2449663198U, // FMAX_VG4_4Z4Z_H |
| 4955 | 2451776734U, // FMAX_VG4_4Z4Z_S |
| 4956 | 2447549662U, // FMAX_VG4_4ZZ_D |
| 4957 | 2449663198U, // FMAX_VG4_4ZZ_H |
| 4958 | 2451776734U, // FMAX_VG4_4ZZ_S |
| 4959 | 807462110U, // FMAX_ZPmI_D |
| 4960 | 543237342U, // FMAX_ZPmI_H |
| 4961 | 807494878U, // FMAX_ZPmI_S |
| 4962 | 807462110U, // FMAX_ZPmZ_D |
| 4963 | 543237342U, // FMAX_ZPmZ_H |
| 4964 | 807494878U, // FMAX_ZPmZ_S |
| 4965 | 1352770782U, // FMAXv2f32 |
| 4966 | 1354867934U, // FMAXv2f64 |
| 4967 | 1356965086U, // FMAXv4f16 |
| 4968 | 1359062238U, // FMAXv4f32 |
| 4969 | 1361159390U, // FMAXv8f16 |
| 4970 | 2119640U, // FMINDrr |
| 4971 | 2119640U, // FMINHrr |
| 4972 | 2119489U, // FMINNMDrr |
| 4973 | 2119489U, // FMINNMHrr |
| 4974 | 807459221U, // FMINNMP_ZPmZZ_D |
| 4975 | 543234453U, // FMINNMP_ZPmZZ_H |
| 4976 | 807491989U, // FMINNMP_ZPmZZ_S |
| 4977 | 1352767893U, // FMINNMPv2f32 |
| 4978 | 1354865045U, // FMINNMPv2f64 |
| 4979 | 1344297365U, // FMINNMPv2i16p |
| 4980 | 1344297365U, // FMINNMPv2i32p |
| 4981 | 1344297365U, // FMINNMPv2i64p |
| 4982 | 1356962197U, // FMINNMPv4f16 |
| 4983 | 1359059349U, // FMINNMPv4f32 |
| 4984 | 1361156501U, // FMINNMPv8f16 |
| 4985 | 817996575U, // FMINNMQV_D |
| 4986 | 824288031U, // FMINNMQV_H |
| 4987 | 822190879U, // FMINNMQV_S |
| 4988 | 2119489U, // FMINNMSrr |
| 4989 | 579085002U, // FMINNMV_VPZ_D |
| 4990 | 581198538U, // FMINNMV_VPZ_H |
| 4991 | 562340554U, // FMINNMV_VPZ_S |
| 4992 | 1344299722U, // FMINNMVv4i16v |
| 4993 | 1344299722U, // FMINNMVv4i32v |
| 4994 | 1344299722U, // FMINNMVv8i16v |
| 4995 | 2447546177U, // FMINNM_VG2_2Z2Z_D |
| 4996 | 2449659713U, // FMINNM_VG2_2Z2Z_H |
| 4997 | 2451773249U, // FMINNM_VG2_2Z2Z_S |
| 4998 | 2447546177U, // FMINNM_VG2_2ZZ_D |
| 4999 | 2449659713U, // FMINNM_VG2_2ZZ_H |
| 5000 | 2451773249U, // FMINNM_VG2_2ZZ_S |
| 5001 | 2447546177U, // FMINNM_VG4_4Z4Z_D |
| 5002 | 2449659713U, // FMINNM_VG4_4Z4Z_H |
| 5003 | 2451773249U, // FMINNM_VG4_4Z4Z_S |
| 5004 | 2447546177U, // FMINNM_VG4_4ZZ_D |
| 5005 | 2449659713U, // FMINNM_VG4_4ZZ_H |
| 5006 | 2451773249U, // FMINNM_VG4_4ZZ_S |
| 5007 | 807458625U, // FMINNM_ZPmI_D |
| 5008 | 543233857U, // FMINNM_ZPmI_H |
| 5009 | 807491393U, // FMINNM_ZPmI_S |
| 5010 | 807458625U, // FMINNM_ZPmZ_D |
| 5011 | 543233857U, // FMINNM_ZPmZ_H |
| 5012 | 807491393U, // FMINNM_ZPmZ_S |
| 5013 | 1352767297U, // FMINNMv2f32 |
| 5014 | 1354864449U, // FMINNMv2f64 |
| 5015 | 1356961601U, // FMINNMv4f16 |
| 5016 | 1359058753U, // FMINNMv4f32 |
| 5017 | 1361155905U, // FMINNMv8f16 |
| 5018 | 807459245U, // FMINP_ZPmZZ_D |
| 5019 | 543234477U, // FMINP_ZPmZZ_H |
| 5020 | 807492013U, // FMINP_ZPmZZ_S |
| 5021 | 1352767917U, // FMINPv2f32 |
| 5022 | 1354865069U, // FMINPv2f64 |
| 5023 | 1344297389U, // FMINPv2i16p |
| 5024 | 1344297389U, // FMINPv2i32p |
| 5025 | 1344297389U, // FMINPv2i64p |
| 5026 | 1356962221U, // FMINPv4f16 |
| 5027 | 1359059373U, // FMINPv4f32 |
| 5028 | 1361156525U, // FMINPv8f16 |
| 5029 | 817996595U, // FMINQV_D |
| 5030 | 824288051U, // FMINQV_H |
| 5031 | 822190899U, // FMINQV_S |
| 5032 | 2119640U, // FMINSrr |
| 5033 | 579085020U, // FMINV_VPZ_D |
| 5034 | 581198556U, // FMINV_VPZ_H |
| 5035 | 562340572U, // FMINV_VPZ_S |
| 5036 | 1344299740U, // FMINVv4i16v |
| 5037 | 1344299740U, // FMINVv4i32v |
| 5038 | 1344299740U, // FMINVv8i16v |
| 5039 | 2447546328U, // FMIN_VG2_2Z2Z_D |
| 5040 | 2449659864U, // FMIN_VG2_2Z2Z_H |
| 5041 | 2451773400U, // FMIN_VG2_2Z2Z_S |
| 5042 | 2447546328U, // FMIN_VG2_2ZZ_D |
| 5043 | 2449659864U, // FMIN_VG2_2ZZ_H |
| 5044 | 2451773400U, // FMIN_VG2_2ZZ_S |
| 5045 | 2447546328U, // FMIN_VG4_4Z4Z_D |
| 5046 | 2449659864U, // FMIN_VG4_4Z4Z_H |
| 5047 | 2451773400U, // FMIN_VG4_4Z4Z_S |
| 5048 | 2447546328U, // FMIN_VG4_4ZZ_D |
| 5049 | 2449659864U, // FMIN_VG4_4ZZ_H |
| 5050 | 2451773400U, // FMIN_VG4_4ZZ_S |
| 5051 | 807458776U, // FMIN_ZPmI_D |
| 5052 | 543234008U, // FMIN_ZPmI_H |
| 5053 | 807491544U, // FMIN_ZPmI_S |
| 5054 | 807458776U, // FMIN_ZPmZ_D |
| 5055 | 543234008U, // FMIN_ZPmZ_H |
| 5056 | 807491544U, // FMIN_ZPmZ_S |
| 5057 | 1352767448U, // FMINv2f32 |
| 5058 | 1354864600U, // FMINv2f64 |
| 5059 | 1356961752U, // FMINv4f16 |
| 5060 | 1359058904U, // FMINv4f32 |
| 5061 | 1361156056U, // FMINv8f16 |
| 5062 | 3231842536U, // FMLAL2lanev4f16 |
| 5063 | 3238133992U, // FMLAL2lanev8f16 |
| 5064 | 3231842536U, // FMLAL2v4f16 |
| 5065 | 3238133992U, // FMLAL2v8f16 |
| 5066 | 2485192457U, // FMLALB_ZZZ |
| 5067 | 2485192457U, // FMLALB_ZZZI |
| 5068 | 2954970889U, // FMLALB_ZZZI_SHH |
| 5069 | 2954970889U, // FMLALB_ZZZ_SHH |
| 5070 | 3240232713U, // FMLALBlanev8f16 |
| 5071 | 3240232713U, // FMLALBv16i8_v8f16 |
| 5072 | 2686535280U, // FMLALLBB_ZZZ |
| 5073 | 2686535280U, // FMLALLBB_ZZZI |
| 5074 | 3238135408U, // FMLALLBBlanev4f32 |
| 5075 | 3238135408U, // FMLALLBBv4f32 |
| 5076 | 2686541551U, // FMLALLBT_ZZZ |
| 5077 | 2686541551U, // FMLALLBT_ZZZI |
| 5078 | 3238141679U, // FMLALLBTlanev4f32 |
| 5079 | 3238141679U, // FMLALLBTv4f32 |
| 5080 | 2686536220U, // FMLALLTB_ZZZ |
| 5081 | 2686536220U, // FMLALLTB_ZZZI |
| 5082 | 3238136348U, // FMLALLTBlanev4f32 |
| 5083 | 3238136348U, // FMLALLTBv4f32 |
| 5084 | 2686542287U, // FMLALLTT_ZZZ |
| 5085 | 2686542287U, // FMLALLTT_ZZZI |
| 5086 | 3238142415U, // FMLALLTTlanev4f32 |
| 5087 | 3238142415U, // FMLALLTTv4f32 |
| 5088 | 1415812215U, // FMLALL_MZZI_BtoS |
| 5089 | 1415812215U, // FMLALL_MZZ_BtoS |
| 5090 | 4100166775U, // FMLALL_VG2_M2Z2Z_BtoS |
| 5091 | 4100166775U, // FMLALL_VG2_M2ZZI_BtoS |
| 5092 | 3026424951U, // FMLALL_VG2_M2ZZ_BtoS |
| 5093 | 73634935U, // FMLALL_VG4_M4Z4Z_BtoS |
| 5094 | 73634935U, // FMLALL_VG4_M4ZZI_BtoS |
| 5095 | 3294860407U, // FMLALL_VG4_M4ZZ_BtoS |
| 5096 | 2485198758U, // FMLALT_ZZZ |
| 5097 | 2485198758U, // FMLALT_ZZZI |
| 5098 | 2954977190U, // FMLALT_ZZZI_SHH |
| 5099 | 2954977190U, // FMLALT_ZZZ_SHH |
| 5100 | 3240239014U, // FMLALTlanev8f16 |
| 5101 | 3240239014U, // FMLALTv16i8_v8f16 |
| 5102 | 1390776841U, // FMLAL_MZZI_BtoH |
| 5103 | 1390645769U, // FMLAL_MZZI_HtoS |
| 5104 | 1390645769U, // FMLAL_MZZ_HtoS |
| 5105 | 4075131401U, // FMLAL_VG2_M2Z2Z_BtoH |
| 5106 | 4075000329U, // FMLAL_VG2_M2Z2Z_HtoS |
| 5107 | 4075131401U, // FMLAL_VG2_M2ZZI_BtoH |
| 5108 | 4075000329U, // FMLAL_VG2_M2ZZI_HtoS |
| 5109 | 4075131401U, // FMLAL_VG2_M2ZZ_BtoH |
| 5110 | 4075000329U, // FMLAL_VG2_M2ZZ_HtoS |
| 5111 | 1390776841U, // FMLAL_VG2_MZZ_BtoH |
| 5112 | 48599561U, // FMLAL_VG4_M4Z4Z_BtoH |
| 5113 | 48468489U, // FMLAL_VG4_M4Z4Z_HtoS |
| 5114 | 48599561U, // FMLAL_VG4_M4ZZI_BtoH |
| 5115 | 48468489U, // FMLAL_VG4_M4ZZI_HtoS |
| 5116 | 48599561U, // FMLAL_VG4_M4ZZ_BtoH |
| 5117 | 48468489U, // FMLAL_VG4_M4ZZ_HtoS |
| 5118 | 3231846921U, // FMLALlanev4f16 |
| 5119 | 3238138377U, // FMLALlanev8f16 |
| 5120 | 3231846921U, // FMLALv4f16 |
| 5121 | 3238138377U, // FMLALv8f16 |
| 5122 | 4064494444U, // FMLA_VG2_M2Z2Z_D |
| 5123 | 4064641900U, // FMLA_VG2_M2Z2Z_H |
| 5124 | 4064510828U, // FMLA_VG2_M2Z2Z_S |
| 5125 | 4064494444U, // FMLA_VG2_M2ZZI_D |
| 5126 | 4064641900U, // FMLA_VG2_M2ZZI_H |
| 5127 | 4064510828U, // FMLA_VG2_M2ZZI_S |
| 5128 | 4064494444U, // FMLA_VG2_M2ZZ_D |
| 5129 | 4064641900U, // FMLA_VG2_M2ZZ_H |
| 5130 | 4064510828U, // FMLA_VG2_M2ZZ_S |
| 5131 | 37962604U, // FMLA_VG4_M4Z4Z_D |
| 5132 | 38110060U, // FMLA_VG4_M4Z4Z_H |
| 5133 | 37978988U, // FMLA_VG4_M4Z4Z_S |
| 5134 | 37962604U, // FMLA_VG4_M4ZZI_D |
| 5135 | 38110060U, // FMLA_VG4_M4ZZI_H |
| 5136 | 37978988U, // FMLA_VG4_M4ZZI_S |
| 5137 | 37962604U, // FMLA_VG4_M4ZZ_D |
| 5138 | 38110060U, // FMLA_VG4_M4ZZ_H |
| 5139 | 37978988U, // FMLA_VG4_M4ZZ_S |
| 5140 | 807453548U, // FMLA_ZPmZZ_D |
| 5141 | 543228780U, // FMLA_ZPmZZ_H |
| 5142 | 807486316U, // FMLA_ZPmZZ_S |
| 5143 | 1612759916U, // FMLA_ZZZI_D |
| 5144 | 2460025708U, // FMLA_ZZZI_H |
| 5145 | 1881228140U, // FMLA_ZZZI_S |
| 5146 | 807715692U, // FMLAv1i16_indexed |
| 5147 | 807715692U, // FMLAv1i32_indexed |
| 5148 | 807715692U, // FMLAv1i64_indexed |
| 5149 | 3231843180U, // FMLAv2f32 |
| 5150 | 3233940332U, // FMLAv2f64 |
| 5151 | 3231843180U, // FMLAv2i32_indexed |
| 5152 | 3233940332U, // FMLAv2i64_indexed |
| 5153 | 3236037484U, // FMLAv4f16 |
| 5154 | 3238134636U, // FMLAv4f32 |
| 5155 | 3236037484U, // FMLAv4i16_indexed |
| 5156 | 3238134636U, // FMLAv4i32_indexed |
| 5157 | 3240231788U, // FMLAv8f16 |
| 5158 | 3240231788U, // FMLAv8i16_indexed |
| 5159 | 2954969971U, // FMLLA_ZZZ_HtoS |
| 5160 | 3231842668U, // FMLSL2lanev4f16 |
| 5161 | 3238134124U, // FMLSL2lanev8f16 |
| 5162 | 3231842668U, // FMLSL2v4f16 |
| 5163 | 3238134124U, // FMLSL2v8f16 |
| 5164 | 2954971187U, // FMLSLB_ZZZI_SHH |
| 5165 | 2954971187U, // FMLSLB_ZZZ_SHH |
| 5166 | 2954977421U, // FMLSLT_ZZZI_SHH |
| 5167 | 2954977421U, // FMLSLT_ZZZ_SHH |
| 5168 | 1390646840U, // FMLSL_MZZI_HtoS |
| 5169 | 1390646840U, // FMLSL_MZZ_HtoS |
| 5170 | 4075001400U, // FMLSL_VG2_M2Z2Z_HtoS |
| 5171 | 4075001400U, // FMLSL_VG2_M2ZZI_HtoS |
| 5172 | 4075001400U, // FMLSL_VG2_M2ZZ_HtoS |
| 5173 | 48469560U, // FMLSL_VG4_M4Z4Z_HtoS |
| 5174 | 48469560U, // FMLSL_VG4_M4ZZI_HtoS |
| 5175 | 48469560U, // FMLSL_VG4_M4ZZ_HtoS |
| 5176 | 3231847992U, // FMLSLlanev4f16 |
| 5177 | 3238139448U, // FMLSLlanev8f16 |
| 5178 | 3231847992U, // FMLSLv4f16 |
| 5179 | 3238139448U, // FMLSLv8f16 |
| 5180 | 4064501267U, // FMLS_VG2_M2Z2Z_D |
| 5181 | 4064648723U, // FMLS_VG2_M2Z2Z_H |
| 5182 | 4064517651U, // FMLS_VG2_M2Z2Z_S |
| 5183 | 4064501267U, // FMLS_VG2_M2ZZI_D |
| 5184 | 4064648723U, // FMLS_VG2_M2ZZI_H |
| 5185 | 4064517651U, // FMLS_VG2_M2ZZI_S |
| 5186 | 4064501267U, // FMLS_VG2_M2ZZ_D |
| 5187 | 4064648723U, // FMLS_VG2_M2ZZ_H |
| 5188 | 4064517651U, // FMLS_VG2_M2ZZ_S |
| 5189 | 37969427U, // FMLS_VG4_M4Z4Z_D |
| 5190 | 38116883U, // FMLS_VG4_M4Z4Z_H |
| 5191 | 37985811U, // FMLS_VG4_M4Z4Z_S |
| 5192 | 37969427U, // FMLS_VG4_M4ZZI_D |
| 5193 | 38116883U, // FMLS_VG4_M4ZZI_H |
| 5194 | 37985811U, // FMLS_VG4_M4ZZI_S |
| 5195 | 37969427U, // FMLS_VG4_M4ZZ_D |
| 5196 | 38116883U, // FMLS_VG4_M4ZZ_H |
| 5197 | 37985811U, // FMLS_VG4_M4ZZ_S |
| 5198 | 807460371U, // FMLS_ZPmZZ_D |
| 5199 | 543235603U, // FMLS_ZPmZZ_H |
| 5200 | 807493139U, // FMLS_ZPmZZ_S |
| 5201 | 1612766739U, // FMLS_ZZZI_D |
| 5202 | 2460032531U, // FMLS_ZZZI_H |
| 5203 | 1881234963U, // FMLS_ZZZI_S |
| 5204 | 807722515U, // FMLSv1i16_indexed |
| 5205 | 807722515U, // FMLSv1i32_indexed |
| 5206 | 807722515U, // FMLSv1i64_indexed |
| 5207 | 3231850003U, // FMLSv2f32 |
| 5208 | 3233947155U, // FMLSv2f64 |
| 5209 | 3231850003U, // FMLSv2i32_indexed |
| 5210 | 3233947155U, // FMLSv2i64_indexed |
| 5211 | 3236044307U, // FMLSv4f16 |
| 5212 | 3238141459U, // FMLSv4f32 |
| 5213 | 3236044307U, // FMLSv4i16_indexed |
| 5214 | 3238141459U, // FMLSv4i32_indexed |
| 5215 | 3240238611U, // FMLSv8f16 |
| 5216 | 3240238611U, // FMLSv8i16_indexed |
| 5217 | 2485191539U, // FMMLA_ZZZ_BtoH |
| 5218 | 2686534515U, // FMMLA_ZZZ_BtoS |
| 5219 | 1612759923U, // FMMLA_ZZZ_D |
| 5220 | 2460025715U, // FMMLA_ZZZ_H |
| 5221 | 1881228147U, // FMMLA_ZZZ_S |
| 5222 | 3238134643U, // FMMLAv4f32 |
| 5223 | 3240231795U, // FMMLAv8f16 |
| 5224 | 3238134643U, // FMMLAv8f16_v4f32 |
| 5225 | 3240231795U, // FMMLAv8f16_v8f16 |
| 5226 | 3565273814U, // FMOP4A_M2Z2Z_BtoH |
| 5227 | 3565273814U, // FMOP4A_M2Z2Z_BtoS |
| 5228 | 3835806422U, // FMOP4A_M2Z2Z_D |
| 5229 | 1661059798U, // FMOP4A_M2Z2Z_H |
| 5230 | 1661059798U, // FMOP4A_M2Z2Z_HtoS |
| 5231 | 4106339030U, // FMOP4A_M2Z2Z_S |
| 5232 | 75612886U, // FMOP4A_M2ZZ_BtoH |
| 5233 | 75612886U, // FMOP4A_M2ZZ_BtoS |
| 5234 | 346145494U, // FMOP4A_M2ZZ_D |
| 5235 | 1929495254U, // FMOP4A_M2ZZ_H |
| 5236 | 1929495254U, // FMOP4A_M2ZZ_HtoS |
| 5237 | 616678102U, // FMOP4A_M2ZZ_S |
| 5238 | 2485240534U, // FMOP4A_MZ2Z_BtoH |
| 5239 | 2485240534U, // FMOP4A_MZ2Z_BtoS |
| 5240 | 2457977558U, // FMOP4A_MZ2Z_D |
| 5241 | 2460074710U, // FMOP4A_MZ2Z_H |
| 5242 | 2460074710U, // FMOP4A_MZ2Z_HtoS |
| 5243 | 2441200342U, // FMOP4A_MZ2Z_S |
| 5244 | 2485240534U, // FMOP4A_MZZ_BtoH |
| 5245 | 2485240534U, // FMOP4A_MZZ_BtoS |
| 5246 | 2457977558U, // FMOP4A_MZZ_D |
| 5247 | 2460074710U, // FMOP4A_MZZ_H |
| 5248 | 2460074710U, // FMOP4A_MZZ_HtoS |
| 5249 | 2441200342U, // FMOP4A_MZZ_S |
| 5250 | 3835813193U, // FMOP4S_M2Z2Z_D |
| 5251 | 1661066569U, // FMOP4S_M2Z2Z_H |
| 5252 | 1661066569U, // FMOP4S_M2Z2Z_HtoS |
| 5253 | 4106345801U, // FMOP4S_M2Z2Z_S |
| 5254 | 346152265U, // FMOP4S_M2ZZ_D |
| 5255 | 1929502025U, // FMOP4S_M2ZZ_H |
| 5256 | 1929502025U, // FMOP4S_M2ZZ_HtoS |
| 5257 | 616684873U, // FMOP4S_M2ZZ_S |
| 5258 | 2457984329U, // FMOP4S_MZ2Z_D |
| 5259 | 2460081481U, // FMOP4S_MZ2Z_H |
| 5260 | 2460081481U, // FMOP4S_MZ2Z_HtoS |
| 5261 | 2441207113U, // FMOP4S_MZ2Z_S |
| 5262 | 2457984329U, // FMOP4S_MZZ_D |
| 5263 | 2460081481U, // FMOP4S_MZZ_H |
| 5264 | 2460081481U, // FMOP4S_MZZ_HtoS |
| 5265 | 2441207113U, // FMOP4S_MZZ_S |
| 5266 | 541180914U, // FMOPAL_MPPZZ |
| 5267 | 541180914U, // FMOPA_MPPZZ_BtoH |
| 5268 | 541180914U, // FMOPA_MPPZZ_BtoS |
| 5269 | 541180914U, // FMOPA_MPPZZ_D |
| 5270 | 541180914U, // FMOPA_MPPZZ_H |
| 5271 | 541180914U, // FMOPA_MPPZZ_S |
| 5272 | 541187680U, // FMOPSL_MPPZZ |
| 5273 | 541187680U, // FMOPS_MPPZZ_D |
| 5274 | 541187680U, // FMOPS_MPPZZ_H |
| 5275 | 541187680U, // FMOPS_MPPZZ_S |
| 5276 | 1344299768U, // FMOVDXHighr |
| 5277 | 2122488U, // FMOVDXr |
| 5278 | 2686477048U, // FMOVDi |
| 5279 | 2122488U, // FMOVDr |
| 5280 | 2122488U, // FMOVHWr |
| 5281 | 2122488U, // FMOVHXr |
| 5282 | 2686477048U, // FMOVHi |
| 5283 | 2122488U, // FMOVHr |
| 5284 | 2122488U, // FMOVSWr |
| 5285 | 2686477048U, // FMOVSi |
| 5286 | 2122488U, // FMOVSr |
| 5287 | 2122488U, // FMOVWHr |
| 5288 | 2122488U, // FMOVWSr |
| 5289 | 81896184U, // FMOVXDHighr |
| 5290 | 2122488U, // FMOVXDr |
| 5291 | 2122488U, // FMOVXHr |
| 5292 | 2694947576U, // FMOVv2f32_ns |
| 5293 | 2697044728U, // FMOVv2f64_ns |
| 5294 | 2699141880U, // FMOVv4f16_ns |
| 5295 | 2701239032U, // FMOVv4f32_ns |
| 5296 | 2703336184U, // FMOVv8f16_ns |
| 5297 | 807455184U, // FMSB_ZPmZZ_D |
| 5298 | 543230416U, // FMSB_ZPmZZ_H |
| 5299 | 807487952U, // FMSB_ZPmZZ_S |
| 5300 | 2116196U, // FMSUBDrrr |
| 5301 | 2116196U, // FMSUBHrrr |
| 5302 | 2116196U, // FMSUBSrrr |
| 5303 | 2119320U, // FMULDrr |
| 5304 | 2119320U, // FMULHrr |
| 5305 | 2119320U, // FMULSrr |
| 5306 | 2123058U, // FMULX16 |
| 5307 | 2123058U, // FMULX32 |
| 5308 | 2123058U, // FMULX64 |
| 5309 | 807462194U, // FMULX_ZPmZ_D |
| 5310 | 543237426U, // FMULX_ZPmZ_H |
| 5311 | 807494962U, // FMULX_ZPmZ_S |
| 5312 | 2123058U, // FMULXv1i16_indexed |
| 5313 | 2123058U, // FMULXv1i32_indexed |
| 5314 | 2123058U, // FMULXv1i64_indexed |
| 5315 | 1352770866U, // FMULXv2f32 |
| 5316 | 1354868018U, // FMULXv2f64 |
| 5317 | 1352770866U, // FMULXv2i32_indexed |
| 5318 | 1354868018U, // FMULXv2i64_indexed |
| 5319 | 1356965170U, // FMULXv4f16 |
| 5320 | 1359062322U, // FMULXv4f32 |
| 5321 | 1356965170U, // FMULXv4i16_indexed |
| 5322 | 1359062322U, // FMULXv4i32_indexed |
| 5323 | 1361159474U, // FMULXv8f16 |
| 5324 | 1361159474U, // FMULXv8i16_indexed |
| 5325 | 2447546008U, // FMUL_2Z2Z_D |
| 5326 | 2449659544U, // FMUL_2Z2Z_H |
| 5327 | 2451773080U, // FMUL_2Z2Z_S |
| 5328 | 2447546008U, // FMUL_2ZZ_D |
| 5329 | 2449659544U, // FMUL_2ZZ_H |
| 5330 | 2451773080U, // FMUL_2ZZ_S |
| 5331 | 2447546008U, // FMUL_4Z4Z_D |
| 5332 | 2449659544U, // FMUL_4Z4Z_H |
| 5333 | 2451773080U, // FMUL_4Z4Z_S |
| 5334 | 2447546008U, // FMUL_4ZZ_D |
| 5335 | 2449659544U, // FMUL_4ZZ_H |
| 5336 | 2451773080U, // FMUL_4ZZ_S |
| 5337 | 807458456U, // FMUL_ZPmI_D |
| 5338 | 543233688U, // FMUL_ZPmI_H |
| 5339 | 807491224U, // FMUL_ZPmI_S |
| 5340 | 807458456U, // FMUL_ZPmZ_D |
| 5341 | 543233688U, // FMUL_ZPmZ_H |
| 5342 | 807491224U, // FMUL_ZPmZ_S |
| 5343 | 2686506648U, // FMUL_ZZZI_D |
| 5344 | 2443253400U, // FMUL_ZZZI_H |
| 5345 | 3760281240U, // FMUL_ZZZI_S |
| 5346 | 2686506648U, // FMUL_ZZZ_D |
| 5347 | 2443253400U, // FMUL_ZZZ_H |
| 5348 | 3760281240U, // FMUL_ZZZ_S |
| 5349 | 2119320U, // FMULv1i16_indexed |
| 5350 | 2119320U, // FMULv1i32_indexed |
| 5351 | 2119320U, // FMULv1i64_indexed |
| 5352 | 1352767128U, // FMULv2f32 |
| 5353 | 1354864280U, // FMULv2f64 |
| 5354 | 1352767128U, // FMULv2i32_indexed |
| 5355 | 1354864280U, // FMULv2i64_indexed |
| 5356 | 1356961432U, // FMULv4f16 |
| 5357 | 1359058584U, // FMULv4f32 |
| 5358 | 1356961432U, // FMULv4i16_indexed |
| 5359 | 1359058584U, // FMULv4i32_indexed |
| 5360 | 1361155736U, // FMULv8f16 |
| 5361 | 1361155736U, // FMULv8i16_indexed |
| 5362 | 2117056U, // FNEGDr |
| 5363 | 2117056U, // FNEGHr |
| 5364 | 2117056U, // FNEGSr |
| 5365 | 270585280U, // FNEG_ZPmZ_D |
| 5366 | 541134272U, // FNEG_ZPmZ_H |
| 5367 | 270618048U, // FNEG_ZPmZ_S |
| 5368 | 807456192U, // FNEG_ZPzZ_D |
| 5369 | 1080102336U, // FNEG_ZPzZ_H |
| 5370 | 807488960U, // FNEG_ZPzZ_S |
| 5371 | 1352764864U, // FNEGv2f32 |
| 5372 | 1354862016U, // FNEGv2f64 |
| 5373 | 1356959168U, // FNEGv4f16 |
| 5374 | 1359056320U, // FNEGv4f32 |
| 5375 | 1361153472U, // FNEGv8f16 |
| 5376 | 2116678U, // FNMADDDrrr |
| 5377 | 2116678U, // FNMADDHrrr |
| 5378 | 2116678U, // FNMADDSrrr |
| 5379 | 807455650U, // FNMAD_ZPmZZ_D |
| 5380 | 543230882U, // FNMAD_ZPmZZ_H |
| 5381 | 807488418U, // FNMAD_ZPmZZ_S |
| 5382 | 807453577U, // FNMLA_ZPmZZ_D |
| 5383 | 543228809U, // FNMLA_ZPmZZ_H |
| 5384 | 807486345U, // FNMLA_ZPmZZ_S |
| 5385 | 807460377U, // FNMLS_ZPmZZ_D |
| 5386 | 543235609U, // FNMLS_ZPmZZ_H |
| 5387 | 807493145U, // FNMLS_ZPmZZ_S |
| 5388 | 807455190U, // FNMSB_ZPmZZ_D |
| 5389 | 543230422U, // FNMSB_ZPmZZ_H |
| 5390 | 807487958U, // FNMSB_ZPmZZ_S |
| 5391 | 2116203U, // FNMSUBDrrr |
| 5392 | 2116203U, // FNMSUBHrrr |
| 5393 | 2116203U, // FNMSUBSrrr |
| 5394 | 2119326U, // FNMULDrr |
| 5395 | 2119326U, // FNMULHrr |
| 5396 | 2119326U, // FNMULSrr |
| 5397 | 2686504244U, // FRECPE_ZZ_D |
| 5398 | 564202804U, // FRECPE_ZZ_H |
| 5399 | 3760278836U, // FRECPE_ZZ_S |
| 5400 | 2116916U, // FRECPEv1f16 |
| 5401 | 2116916U, // FRECPEv1i32 |
| 5402 | 2116916U, // FRECPEv1i64 |
| 5403 | 1352764724U, // FRECPEv2f32 |
| 5404 | 1354861876U, // FRECPEv2f64 |
| 5405 | 1356959028U, // FRECPEv4f16 |
| 5406 | 1359056180U, // FRECPEv4f32 |
| 5407 | 1361153332U, // FRECPEv8f16 |
| 5408 | 2121296U, // FRECPS16 |
| 5409 | 2121296U, // FRECPS32 |
| 5410 | 2121296U, // FRECPS64 |
| 5411 | 2686508624U, // FRECPS_ZZZ_D |
| 5412 | 2443255376U, // FRECPS_ZZZ_H |
| 5413 | 3760283216U, // FRECPS_ZZZ_S |
| 5414 | 1352769104U, // FRECPSv2f32 |
| 5415 | 1354866256U, // FRECPSv2f64 |
| 5416 | 1356963408U, // FRECPSv4f16 |
| 5417 | 1359060560U, // FRECPSv4f32 |
| 5418 | 1361157712U, // FRECPSv8f16 |
| 5419 | 270591289U, // FRECPX_ZPmZ_D |
| 5420 | 541140281U, // FRECPX_ZPmZ_H |
| 5421 | 270624057U, // FRECPX_ZPmZ_S |
| 5422 | 807462201U, // FRECPX_ZPzZ_D |
| 5423 | 1080108345U, // FRECPX_ZPzZ_H |
| 5424 | 807494969U, // FRECPX_ZPzZ_S |
| 5425 | 2123065U, // FRECPXv1f16 |
| 5426 | 2123065U, // FRECPXv1i32 |
| 5427 | 2123065U, // FRECPXv1i64 |
| 5428 | 2122938U, // FRINT32XDr |
| 5429 | 2122938U, // FRINT32XSr |
| 5430 | 270591162U, // FRINT32X_ZPmZ_D |
| 5431 | 270623930U, // FRINT32X_ZPmZ_S |
| 5432 | 807462074U, // FRINT32X_ZPzZ_D |
| 5433 | 807494842U, // FRINT32X_ZPzZ_S |
| 5434 | 1352770746U, // FRINT32Xv2f32 |
| 5435 | 1354867898U, // FRINT32Xv2f64 |
| 5436 | 1359062202U, // FRINT32Xv4f32 |
| 5437 | 2123103U, // FRINT32ZDr |
| 5438 | 2123103U, // FRINT32ZSr |
| 5439 | 270591327U, // FRINT32Z_ZPmZ_D |
| 5440 | 270624095U, // FRINT32Z_ZPmZ_S |
| 5441 | 807462239U, // FRINT32Z_ZPzZ_D |
| 5442 | 807495007U, // FRINT32Z_ZPzZ_S |
| 5443 | 1352770911U, // FRINT32Zv2f32 |
| 5444 | 1354868063U, // FRINT32Zv2f64 |
| 5445 | 1359062367U, // FRINT32Zv4f32 |
| 5446 | 2122948U, // FRINT64XDr |
| 5447 | 2122948U, // FRINT64XSr |
| 5448 | 270591172U, // FRINT64X_ZPmZ_D |
| 5449 | 270623940U, // FRINT64X_ZPmZ_S |
| 5450 | 807462084U, // FRINT64X_ZPzZ_D |
| 5451 | 807494852U, // FRINT64X_ZPzZ_S |
| 5452 | 1352770756U, // FRINT64Xv2f32 |
| 5453 | 1354867908U, // FRINT64Xv2f64 |
| 5454 | 1359062212U, // FRINT64Xv4f32 |
| 5455 | 2123113U, // FRINT64ZDr |
| 5456 | 2123113U, // FRINT64ZSr |
| 5457 | 270591337U, // FRINT64Z_ZPmZ_D |
| 5458 | 270624105U, // FRINT64Z_ZPmZ_S |
| 5459 | 807462249U, // FRINT64Z_ZPzZ_D |
| 5460 | 807495017U, // FRINT64Z_ZPzZ_S |
| 5461 | 1352770921U, // FRINT64Zv2f32 |
| 5462 | 1354868073U, // FRINT64Zv2f64 |
| 5463 | 1359062377U, // FRINT64Zv4f32 |
| 5464 | 2114849U, // FRINTADr |
| 5465 | 2114849U, // FRINTAHr |
| 5466 | 2114849U, // FRINTASr |
| 5467 | 572720417U, // FRINTA_2Z2Z_S |
| 5468 | 572720417U, // FRINTA_4Z4Z_S |
| 5469 | 270583073U, // FRINTA_ZPmZ_D |
| 5470 | 541132065U, // FRINTA_ZPmZ_H |
| 5471 | 270615841U, // FRINTA_ZPmZ_S |
| 5472 | 807453985U, // FRINTA_ZPzZ_D |
| 5473 | 1080100129U, // FRINTA_ZPzZ_H |
| 5474 | 807486753U, // FRINTA_ZPzZ_S |
| 5475 | 1352762657U, // FRINTAv2f32 |
| 5476 | 1354859809U, // FRINTAv2f64 |
| 5477 | 1356956961U, // FRINTAv4f16 |
| 5478 | 1359054113U, // FRINTAv4f32 |
| 5479 | 1361151265U, // FRINTAv8f16 |
| 5480 | 2118050U, // FRINTIDr |
| 5481 | 2118050U, // FRINTIHr |
| 5482 | 2118050U, // FRINTISr |
| 5483 | 270586274U, // FRINTI_ZPmZ_D |
| 5484 | 541135266U, // FRINTI_ZPmZ_H |
| 5485 | 270619042U, // FRINTI_ZPmZ_S |
| 5486 | 807457186U, // FRINTI_ZPzZ_D |
| 5487 | 1080103330U, // FRINTI_ZPzZ_H |
| 5488 | 807489954U, // FRINTI_ZPzZ_S |
| 5489 | 1352765858U, // FRINTIv2f32 |
| 5490 | 1354863010U, // FRINTIv2f64 |
| 5491 | 1356960162U, // FRINTIv4f16 |
| 5492 | 1359057314U, // FRINTIv4f32 |
| 5493 | 1361154466U, // FRINTIv8f16 |
| 5494 | 2119585U, // FRINTMDr |
| 5495 | 2119585U, // FRINTMHr |
| 5496 | 2119585U, // FRINTMSr |
| 5497 | 572725153U, // FRINTM_2Z2Z_S |
| 5498 | 572725153U, // FRINTM_4Z4Z_S |
| 5499 | 270587809U, // FRINTM_ZPmZ_D |
| 5500 | 541136801U, // FRINTM_ZPmZ_H |
| 5501 | 270620577U, // FRINTM_ZPmZ_S |
| 5502 | 807458721U, // FRINTM_ZPzZ_D |
| 5503 | 1080104865U, // FRINTM_ZPzZ_H |
| 5504 | 807491489U, // FRINTM_ZPzZ_S |
| 5505 | 1352767393U, // FRINTMv2f32 |
| 5506 | 1354864545U, // FRINTMv2f64 |
| 5507 | 1356961697U, // FRINTMv4f16 |
| 5508 | 1359058849U, // FRINTMv4f32 |
| 5509 | 1361156001U, // FRINTMv8f16 |
| 5510 | 2119752U, // FRINTNDr |
| 5511 | 2119752U, // FRINTNHr |
| 5512 | 2119752U, // FRINTNSr |
| 5513 | 572725320U, // FRINTN_2Z2Z_S |
| 5514 | 572725320U, // FRINTN_4Z4Z_S |
| 5515 | 270587976U, // FRINTN_ZPmZ_D |
| 5516 | 541136968U, // FRINTN_ZPmZ_H |
| 5517 | 270620744U, // FRINTN_ZPmZ_S |
| 5518 | 807458888U, // FRINTN_ZPzZ_D |
| 5519 | 1080105032U, // FRINTN_ZPzZ_H |
| 5520 | 807491656U, // FRINTN_ZPzZ_S |
| 5521 | 1352767560U, // FRINTNv2f32 |
| 5522 | 1354864712U, // FRINTNv2f64 |
| 5523 | 1356961864U, // FRINTNv4f16 |
| 5524 | 1359059016U, // FRINTNv4f32 |
| 5525 | 1361156168U, // FRINTNv8f16 |
| 5526 | 2120294U, // FRINTPDr |
| 5527 | 2120294U, // FRINTPHr |
| 5528 | 2120294U, // FRINTPSr |
| 5529 | 572725862U, // FRINTP_2Z2Z_S |
| 5530 | 572725862U, // FRINTP_4Z4Z_S |
| 5531 | 270588518U, // FRINTP_ZPmZ_D |
| 5532 | 541137510U, // FRINTP_ZPmZ_H |
| 5533 | 270621286U, // FRINTP_ZPmZ_S |
| 5534 | 807459430U, // FRINTP_ZPzZ_D |
| 5535 | 1080105574U, // FRINTP_ZPzZ_H |
| 5536 | 807492198U, // FRINTP_ZPzZ_S |
| 5537 | 1352768102U, // FRINTPv2f32 |
| 5538 | 1354865254U, // FRINTPv2f64 |
| 5539 | 1356962406U, // FRINTPv4f16 |
| 5540 | 1359059558U, // FRINTPv4f32 |
| 5541 | 1361156710U, // FRINTPv8f16 |
| 5542 | 2123073U, // FRINTXDr |
| 5543 | 2123073U, // FRINTXHr |
| 5544 | 2123073U, // FRINTXSr |
| 5545 | 270591297U, // FRINTX_ZPmZ_D |
| 5546 | 541140289U, // FRINTX_ZPmZ_H |
| 5547 | 270624065U, // FRINTX_ZPmZ_S |
| 5548 | 807462209U, // FRINTX_ZPzZ_D |
| 5549 | 1080108353U, // FRINTX_ZPzZ_H |
| 5550 | 807494977U, // FRINTX_ZPzZ_S |
| 5551 | 1352770881U, // FRINTXv2f32 |
| 5552 | 1354868033U, // FRINTXv2f64 |
| 5553 | 1356965185U, // FRINTXv4f16 |
| 5554 | 1359062337U, // FRINTXv4f32 |
| 5555 | 1361159489U, // FRINTXv8f16 |
| 5556 | 2123192U, // FRINTZDr |
| 5557 | 2123192U, // FRINTZHr |
| 5558 | 2123192U, // FRINTZSr |
| 5559 | 270591416U, // FRINTZ_ZPmZ_D |
| 5560 | 541140408U, // FRINTZ_ZPmZ_H |
| 5561 | 270624184U, // FRINTZ_ZPmZ_S |
| 5562 | 807462328U, // FRINTZ_ZPzZ_D |
| 5563 | 1080108472U, // FRINTZ_ZPzZ_H |
| 5564 | 807495096U, // FRINTZ_ZPzZ_S |
| 5565 | 1352771000U, // FRINTZv2f32 |
| 5566 | 1354868152U, // FRINTZv2f64 |
| 5567 | 1356965304U, // FRINTZv4f16 |
| 5568 | 1359062456U, // FRINTZv4f32 |
| 5569 | 1361159608U, // FRINTZv8f16 |
| 5570 | 2686504289U, // FRSQRTE_ZZ_D |
| 5571 | 564202849U, // FRSQRTE_ZZ_H |
| 5572 | 3760278881U, // FRSQRTE_ZZ_S |
| 5573 | 2116961U, // FRSQRTEv1f16 |
| 5574 | 2116961U, // FRSQRTEv1i32 |
| 5575 | 2116961U, // FRSQRTEv1i64 |
| 5576 | 1352764769U, // FRSQRTEv2f32 |
| 5577 | 1354861921U, // FRSQRTEv2f64 |
| 5578 | 1356959073U, // FRSQRTEv4f16 |
| 5579 | 1359056225U, // FRSQRTEv4f32 |
| 5580 | 1361153377U, // FRSQRTEv8f16 |
| 5581 | 2121380U, // FRSQRTS16 |
| 5582 | 2121380U, // FRSQRTS32 |
| 5583 | 2121380U, // FRSQRTS64 |
| 5584 | 2686508708U, // FRSQRTS_ZZZ_D |
| 5585 | 2443255460U, // FRSQRTS_ZZZ_H |
| 5586 | 3760283300U, // FRSQRTS_ZZZ_S |
| 5587 | 1352769188U, // FRSQRTSv2f32 |
| 5588 | 1354866340U, // FRSQRTSv2f64 |
| 5589 | 1356963492U, // FRSQRTSv4f16 |
| 5590 | 1359060644U, // FRSQRTSv4f32 |
| 5591 | 1361157796U, // FRSQRTSv8f16 |
| 5592 | 2447543530U, // FSCALE_2Z2Z_D |
| 5593 | 2449657066U, // FSCALE_2Z2Z_H |
| 5594 | 2451770602U, // FSCALE_2Z2Z_S |
| 5595 | 2447543530U, // FSCALE_2ZZ_D |
| 5596 | 2449657066U, // FSCALE_2ZZ_H |
| 5597 | 2451770602U, // FSCALE_2ZZ_S |
| 5598 | 2447543530U, // FSCALE_4Z4Z_D |
| 5599 | 2449657066U, // FSCALE_4Z4Z_H |
| 5600 | 2451770602U, // FSCALE_4Z4Z_S |
| 5601 | 2447543530U, // FSCALE_4ZZ_D |
| 5602 | 2449657066U, // FSCALE_4ZZ_H |
| 5603 | 2451770602U, // FSCALE_4ZZ_S |
| 5604 | 807455978U, // FSCALE_ZPmZ_D |
| 5605 | 543231210U, // FSCALE_ZPmZ_H |
| 5606 | 807488746U, // FSCALE_ZPmZ_S |
| 5607 | 1352764650U, // FSCALEv2f32 |
| 5608 | 1354861802U, // FSCALEv2f64 |
| 5609 | 1356958954U, // FSCALEv4f16 |
| 5610 | 1359056106U, // FSCALEv4f32 |
| 5611 | 1361153258U, // FSCALEv8f16 |
| 5612 | 2122156U, // FSQRTDr |
| 5613 | 2122156U, // FSQRTHr |
| 5614 | 2122156U, // FSQRTSr |
| 5615 | 807461292U, // FSQRT_ZPZz_D |
| 5616 | 1080107436U, // FSQRT_ZPZz_H |
| 5617 | 807494060U, // FSQRT_ZPZz_S |
| 5618 | 270590380U, // FSQRT_ZPmZ_D |
| 5619 | 541139372U, // FSQRT_ZPmZ_H |
| 5620 | 270623148U, // FSQRT_ZPmZ_S |
| 5621 | 1352769964U, // FSQRTv2f32 |
| 5622 | 1354867116U, // FSQRTv2f64 |
| 5623 | 1356964268U, // FSQRTv4f16 |
| 5624 | 1359061420U, // FSQRTv4f32 |
| 5625 | 1361158572U, // FSQRTv8f16 |
| 5626 | 2116176U, // FSUBDrr |
| 5627 | 2116176U, // FSUBHrr |
| 5628 | 807459691U, // FSUBR_ZPmI_D |
| 5629 | 543234923U, // FSUBR_ZPmI_H |
| 5630 | 807492459U, // FSUBR_ZPmI_S |
| 5631 | 807459691U, // FSUBR_ZPmZ_D |
| 5632 | 543234923U, // FSUBR_ZPmZ_H |
| 5633 | 807492459U, // FSUBR_ZPmZ_S |
| 5634 | 2116176U, // FSUBSrr |
| 5635 | 4064496208U, // FSUB_VG2_M2Z_D |
| 5636 | 4064643664U, // FSUB_VG2_M2Z_H |
| 5637 | 4064512592U, // FSUB_VG2_M2Z_S |
| 5638 | 37964368U, // FSUB_VG4_M4Z_D |
| 5639 | 38111824U, // FSUB_VG4_M4Z_H |
| 5640 | 37980752U, // FSUB_VG4_M4Z_S |
| 5641 | 807455312U, // FSUB_ZPmI_D |
| 5642 | 543230544U, // FSUB_ZPmI_H |
| 5643 | 807488080U, // FSUB_ZPmI_S |
| 5644 | 807455312U, // FSUB_ZPmZ_D |
| 5645 | 543230544U, // FSUB_ZPmZ_H |
| 5646 | 807488080U, // FSUB_ZPmZ_S |
| 5647 | 2686503504U, // FSUB_ZZZ_D |
| 5648 | 2443250256U, // FSUB_ZZZ_H |
| 5649 | 3760278096U, // FSUB_ZZZ_S |
| 5650 | 1352763984U, // FSUBv2f32 |
| 5651 | 1354861136U, // FSUBv2f64 |
| 5652 | 1356958288U, // FSUBv4f16 |
| 5653 | 1359055440U, // FSUBv4f32 |
| 5654 | 1361152592U, // FSUBv8f16 |
| 5655 | 2686503849U, // FTMAD_ZZI_D |
| 5656 | 2443250601U, // FTMAD_ZZI_H |
| 5657 | 3760278441U, // FTMAD_ZZI_S |
| 5658 | 75613186U, // FTMOPA_M2ZZZI_BtoH |
| 5659 | 75613186U, // FTMOPA_M2ZZZI_BtoS |
| 5660 | 1929495554U, // FTMOPA_M2ZZZI_HtoH |
| 5661 | 1929495554U, // FTMOPA_M2ZZZI_HtoS |
| 5662 | 616678402U, // FTMOPA_M2ZZZI_StoS |
| 5663 | 2686506667U, // FTSMUL_ZZZ_D |
| 5664 | 2443253419U, // FTSMUL_ZZZ_H |
| 5665 | 3760281259U, // FTSMUL_ZZZ_S |
| 5666 | 2686506039U, // FTSSEL_ZZZ_D |
| 5667 | 2443252791U, // FTSSEL_ZZZ_H |
| 5668 | 3760280631U, // FTSSEL_ZZZ_S |
| 5669 | 37980716U, // FVDOTB_VG4_M2ZZI_BtoS |
| 5670 | 37986777U, // FVDOTT_VG4_M2ZZI_BtoS |
| 5671 | 4064649572U, // FVDOT_VG2_M2ZZI_BtoH |
| 5672 | 4064518500U, // FVDOT_VG2_M2ZZI_HtoS |
| 5673 | 11569U, // GCSPOPCX |
| 5674 | 22418U, // GCSPOPM |
| 5675 | 11587U, // GCSPOPX |
| 5676 | 22324U, // GCSPUSHM |
| 5677 | 11578U, // GCSPUSHX |
| 5678 | 16490U, // GCSSS1 |
| 5679 | 16959U, // GCSSS2 |
| 5680 | 39869632U, // GCSSTR |
| 5681 | 39869640U, // GCSSTTR |
| 5682 | 811763082U, // GLD1B_D |
| 5683 | 811763082U, // GLD1B_D_IMM |
| 5684 | 811763082U, // GLD1B_D_SXTW |
| 5685 | 811763082U, // GLD1B_D_UXTW |
| 5686 | 811795850U, // GLD1B_S_IMM |
| 5687 | 811795850U, // GLD1B_S_SXTW |
| 5688 | 811795850U, // GLD1B_S_UXTW |
| 5689 | 811764556U, // GLD1D |
| 5690 | 811764556U, // GLD1D_IMM |
| 5691 | 811764556U, // GLD1D_SCALED |
| 5692 | 811764556U, // GLD1D_SXTW |
| 5693 | 811764556U, // GLD1D_SXTW_SCALED |
| 5694 | 811764556U, // GLD1D_UXTW |
| 5695 | 811764556U, // GLD1D_UXTW_SCALED |
| 5696 | 811765236U, // GLD1H_D |
| 5697 | 811765236U, // GLD1H_D_IMM |
| 5698 | 811765236U, // GLD1H_D_SCALED |
| 5699 | 811765236U, // GLD1H_D_SXTW |
| 5700 | 811765236U, // GLD1H_D_SXTW_SCALED |
| 5701 | 811765236U, // GLD1H_D_UXTW |
| 5702 | 811765236U, // GLD1H_D_UXTW_SCALED |
| 5703 | 811798004U, // GLD1H_S_IMM |
| 5704 | 811798004U, // GLD1H_S_SXTW |
| 5705 | 811798004U, // GLD1H_S_SXTW_SCALED |
| 5706 | 811798004U, // GLD1H_S_UXTW |
| 5707 | 811798004U, // GLD1H_S_UXTW_SCALED |
| 5708 | 812096206U, // GLD1Q |
| 5709 | 811764126U, // GLD1SB_D |
| 5710 | 811764126U, // GLD1SB_D_IMM |
| 5711 | 811764126U, // GLD1SB_D_SXTW |
| 5712 | 811764126U, // GLD1SB_D_UXTW |
| 5713 | 811796894U, // GLD1SB_S_IMM |
| 5714 | 811796894U, // GLD1SB_S_SXTW |
| 5715 | 811796894U, // GLD1SB_S_UXTW |
| 5716 | 811765934U, // GLD1SH_D |
| 5717 | 811765934U, // GLD1SH_D_IMM |
| 5718 | 811765934U, // GLD1SH_D_SCALED |
| 5719 | 811765934U, // GLD1SH_D_SXTW |
| 5720 | 811765934U, // GLD1SH_D_SXTW_SCALED |
| 5721 | 811765934U, // GLD1SH_D_UXTW |
| 5722 | 811765934U, // GLD1SH_D_UXTW_SCALED |
| 5723 | 811798702U, // GLD1SH_S_IMM |
| 5724 | 811798702U, // GLD1SH_S_SXTW |
| 5725 | 811798702U, // GLD1SH_S_SXTW_SCALED |
| 5726 | 811798702U, // GLD1SH_S_UXTW |
| 5727 | 811798702U, // GLD1SH_S_UXTW_SCALED |
| 5728 | 811770952U, // GLD1SW_D |
| 5729 | 811770952U, // GLD1SW_D_IMM |
| 5730 | 811770952U, // GLD1SW_D_SCALED |
| 5731 | 811770952U, // GLD1SW_D_SXTW |
| 5732 | 811770952U, // GLD1SW_D_SXTW_SCALED |
| 5733 | 811770952U, // GLD1SW_D_UXTW |
| 5734 | 811770952U, // GLD1SW_D_UXTW_SCALED |
| 5735 | 811770757U, // GLD1W_D |
| 5736 | 811770757U, // GLD1W_D_IMM |
| 5737 | 811770757U, // GLD1W_D_SCALED |
| 5738 | 811770757U, // GLD1W_D_SXTW |
| 5739 | 811770757U, // GLD1W_D_SXTW_SCALED |
| 5740 | 811770757U, // GLD1W_D_UXTW |
| 5741 | 811770757U, // GLD1W_D_UXTW_SCALED |
| 5742 | 811803525U, // GLD1W_IMM |
| 5743 | 811803525U, // GLD1W_SXTW |
| 5744 | 811803525U, // GLD1W_SXTW_SCALED |
| 5745 | 811803525U, // GLD1W_UXTW |
| 5746 | 811803525U, // GLD1W_UXTW_SCALED |
| 5747 | 811763088U, // GLDFF1B_D |
| 5748 | 811763088U, // GLDFF1B_D_IMM |
| 5749 | 811763088U, // GLDFF1B_D_SXTW |
| 5750 | 811763088U, // GLDFF1B_D_UXTW |
| 5751 | 811795856U, // GLDFF1B_S_IMM |
| 5752 | 811795856U, // GLDFF1B_S_SXTW |
| 5753 | 811795856U, // GLDFF1B_S_UXTW |
| 5754 | 811764562U, // GLDFF1D |
| 5755 | 811764562U, // GLDFF1D_IMM |
| 5756 | 811764562U, // GLDFF1D_SCALED |
| 5757 | 811764562U, // GLDFF1D_SXTW |
| 5758 | 811764562U, // GLDFF1D_SXTW_SCALED |
| 5759 | 811764562U, // GLDFF1D_UXTW |
| 5760 | 811764562U, // GLDFF1D_UXTW_SCALED |
| 5761 | 811765242U, // GLDFF1H_D |
| 5762 | 811765242U, // GLDFF1H_D_IMM |
| 5763 | 811765242U, // GLDFF1H_D_SCALED |
| 5764 | 811765242U, // GLDFF1H_D_SXTW |
| 5765 | 811765242U, // GLDFF1H_D_SXTW_SCALED |
| 5766 | 811765242U, // GLDFF1H_D_UXTW |
| 5767 | 811765242U, // GLDFF1H_D_UXTW_SCALED |
| 5768 | 811798010U, // GLDFF1H_S_IMM |
| 5769 | 811798010U, // GLDFF1H_S_SXTW |
| 5770 | 811798010U, // GLDFF1H_S_SXTW_SCALED |
| 5771 | 811798010U, // GLDFF1H_S_UXTW |
| 5772 | 811798010U, // GLDFF1H_S_UXTW_SCALED |
| 5773 | 811764133U, // GLDFF1SB_D |
| 5774 | 811764133U, // GLDFF1SB_D_IMM |
| 5775 | 811764133U, // GLDFF1SB_D_SXTW |
| 5776 | 811764133U, // GLDFF1SB_D_UXTW |
| 5777 | 811796901U, // GLDFF1SB_S_IMM |
| 5778 | 811796901U, // GLDFF1SB_S_SXTW |
| 5779 | 811796901U, // GLDFF1SB_S_UXTW |
| 5780 | 811765941U, // GLDFF1SH_D |
| 5781 | 811765941U, // GLDFF1SH_D_IMM |
| 5782 | 811765941U, // GLDFF1SH_D_SCALED |
| 5783 | 811765941U, // GLDFF1SH_D_SXTW |
| 5784 | 811765941U, // GLDFF1SH_D_SXTW_SCALED |
| 5785 | 811765941U, // GLDFF1SH_D_UXTW |
| 5786 | 811765941U, // GLDFF1SH_D_UXTW_SCALED |
| 5787 | 811798709U, // GLDFF1SH_S_IMM |
| 5788 | 811798709U, // GLDFF1SH_S_SXTW |
| 5789 | 811798709U, // GLDFF1SH_S_SXTW_SCALED |
| 5790 | 811798709U, // GLDFF1SH_S_UXTW |
| 5791 | 811798709U, // GLDFF1SH_S_UXTW_SCALED |
| 5792 | 811770959U, // GLDFF1SW_D |
| 5793 | 811770959U, // GLDFF1SW_D_IMM |
| 5794 | 811770959U, // GLDFF1SW_D_SCALED |
| 5795 | 811770959U, // GLDFF1SW_D_SXTW |
| 5796 | 811770959U, // GLDFF1SW_D_SXTW_SCALED |
| 5797 | 811770959U, // GLDFF1SW_D_UXTW |
| 5798 | 811770959U, // GLDFF1SW_D_UXTW_SCALED |
| 5799 | 811770763U, // GLDFF1W_D |
| 5800 | 811770763U, // GLDFF1W_D_IMM |
| 5801 | 811770763U, // GLDFF1W_D_SCALED |
| 5802 | 811770763U, // GLDFF1W_D_SXTW |
| 5803 | 811770763U, // GLDFF1W_D_SXTW_SCALED |
| 5804 | 811770763U, // GLDFF1W_D_UXTW |
| 5805 | 811770763U, // GLDFF1W_D_UXTW_SCALED |
| 5806 | 811803531U, // GLDFF1W_IMM |
| 5807 | 811803531U, // GLDFF1W_SXTW |
| 5808 | 811803531U, // GLDFF1W_SXTW_SCALED |
| 5809 | 811803531U, // GLDFF1W_UXTW |
| 5810 | 811803531U, // GLDFF1W_UXTW_SCALED |
| 5811 | 2118034U, // GMI |
| 5812 | 516316U, // HINT |
| 5813 | 807461057U, // HISTCNT_ZPzZZ_D |
| 5814 | 807493825U, // HISTCNT_ZPzZZ_S |
| 5815 | 3491794388U, // HISTSEG_ZZZ |
| 5816 | 385070U, // HLT |
| 5817 | 379714U, // HVC |
| 5818 | 2115221U, // INCB_XPiI |
| 5819 | 2116571U, // INCD_XPiI |
| 5820 | 2149339U, // INCD_ZPiI |
| 5821 | 2117352U, // INCH_XPiI |
| 5822 | 52498152U, // INCH_ZPiI |
| 5823 | 3491780887U, // INCP_XP_B |
| 5824 | 2686474519U, // INCP_XP_D |
| 5825 | 2149603607U, // INCP_XP_H |
| 5826 | 3760216343U, // INCP_XP_S |
| 5827 | 1612765463U, // INCP_ZP_D |
| 5828 | 580983063U, // INCP_ZP_H |
| 5829 | 1881233687U, // INCP_ZP_S |
| 5830 | 2122758U, // INCW_XPiI |
| 5831 | 2188294U, // INCW_ZPiI |
| 5832 | 1075881243U, // INDEX_II_B |
| 5833 | 2155803U, // INDEX_II_D |
| 5834 | 1426138395U, // INDEX_II_H |
| 5835 | 2188571U, // INDEX_II_S |
| 5836 | 1075881243U, // INDEX_IR_B |
| 5837 | 2155803U, // INDEX_IR_D |
| 5838 | 889267483U, // INDEX_IR_H |
| 5839 | 2188571U, // INDEX_IR_S |
| 5840 | 2139419U, // INDEX_RI_B |
| 5841 | 2155803U, // INDEX_RI_D |
| 5842 | 2472617243U, // INDEX_RI_H |
| 5843 | 2188571U, // INDEX_RI_S |
| 5844 | 2139419U, // INDEX_RR_B |
| 5845 | 2155803U, // INDEX_RR_D |
| 5846 | 2472617243U, // INDEX_RR_H |
| 5847 | 2188571U, // INDEX_RR_S |
| 5848 | 2502427967U, // INSERT_MXIPZ_H_B |
| 5849 | 2502427967U, // INSERT_MXIPZ_H_D |
| 5850 | 2502427967U, // INSERT_MXIPZ_H_H |
| 5851 | 2502427967U, // INSERT_MXIPZ_H_Q |
| 5852 | 2502427967U, // INSERT_MXIPZ_H_S |
| 5853 | 2502444351U, // INSERT_MXIPZ_V_B |
| 5854 | 2502444351U, // INSERT_MXIPZ_V_D |
| 5855 | 2502444351U, // INSERT_MXIPZ_V_H |
| 5856 | 2502444351U, // INSERT_MXIPZ_V_Q |
| 5857 | 2502444351U, // INSERT_MXIPZ_V_S |
| 5858 | 807443636U, // INSR_ZR_B |
| 5859 | 807460020U, // INSR_ZR_D |
| 5860 | 622927028U, // INSR_ZR_H |
| 5861 | 807492788U, // INSR_ZR_S |
| 5862 | 1612750004U, // INSR_ZV_B |
| 5863 | 1881201844U, // INSR_ZV_D |
| 5864 | 599858356U, // INSR_ZV_H |
| 5865 | 2149670068U, // INSR_ZV_S |
| 5866 | 2504138287U, // INSvi16gpr |
| 5867 | 2772573743U, // INSvi16lane |
| 5868 | 2506235439U, // INSvi32gpr |
| 5869 | 2774670895U, // INSvi32lane |
| 5870 | 2497846831U, // INSvi64gpr |
| 5871 | 2766282287U, // INSvi64lane |
| 5872 | 2508332591U, // INSvi8gpr |
| 5873 | 2776768047U, // INSvi8lane |
| 5874 | 2117085U, // IRG |
| 5875 | 444875U, // ISB |
| 5876 | 807421233U, // LASTA_RPZ_B |
| 5877 | 807421233U, // LASTA_RPZ_D |
| 5878 | 807421233U, // LASTA_RPZ_H |
| 5879 | 807421233U, // LASTA_RPZ_S |
| 5880 | 807421233U, // LASTA_VPZ_B |
| 5881 | 807421233U, // LASTA_VPZ_D |
| 5882 | 807421233U, // LASTA_VPZ_H |
| 5883 | 807421233U, // LASTA_VPZ_S |
| 5884 | 807422524U, // LASTB_RPZ_B |
| 5885 | 807422524U, // LASTB_RPZ_D |
| 5886 | 807422524U, // LASTB_RPZ_H |
| 5887 | 807422524U, // LASTB_RPZ_S |
| 5888 | 807422524U, // LASTB_VPZ_B |
| 5889 | 807422524U, // LASTB_VPZ_D |
| 5890 | 807422524U, // LASTB_VPZ_H |
| 5891 | 807422524U, // LASTB_VPZ_S |
| 5892 | 807426670U, // LASTP_XPP_B |
| 5893 | 807426670U, // LASTP_XPP_D |
| 5894 | 807426670U, // LASTP_XPP_H |
| 5895 | 807426670U, // LASTP_XPP_S |
| 5896 | 811746698U, // LD1B |
| 5897 | 899827082U, // LD1B_2Z |
| 5898 | 899827082U, // LD1B_2Z_IMM |
| 5899 | 2955445642U, // LD1B_2Z_STRIDED |
| 5900 | 2955445642U, // LD1B_2Z_STRIDED_IMM |
| 5901 | 899827082U, // LD1B_4Z |
| 5902 | 899827082U, // LD1B_4Z_IMM |
| 5903 | 899827082U, // LD1B_4Z_STRIDED |
| 5904 | 899827082U, // LD1B_4Z_STRIDED_IMM |
| 5905 | 811763082U, // LD1B_D |
| 5906 | 811763082U, // LD1B_D_IMM |
| 5907 | 811779466U, // LD1B_H |
| 5908 | 811779466U, // LD1B_H_IMM |
| 5909 | 811746698U, // LD1B_IMM |
| 5910 | 811795850U, // LD1B_S |
| 5911 | 811795850U, // LD1B_S_IMM |
| 5912 | 811764556U, // LD1D |
| 5913 | 899844940U, // LD1D_2Z |
| 5914 | 899844940U, // LD1D_2Z_IMM |
| 5915 | 899844940U, // LD1D_2Z_STRIDED |
| 5916 | 899844940U, // LD1D_2Z_STRIDED_IMM |
| 5917 | 899844940U, // LD1D_4Z |
| 5918 | 899844940U, // LD1D_4Z_IMM |
| 5919 | 899844940U, // LD1D_4Z_STRIDED |
| 5920 | 899844940U, // LD1D_4Z_STRIDED_IMM |
| 5921 | 811764556U, // LD1D_IMM |
| 5922 | 812092236U, // LD1D_Q |
| 5923 | 812092236U, // LD1D_Q_IMM |
| 5924 | 573481U, // LD1Fourv16b |
| 5925 | 97058857U, // LD1Fourv16b_POST |
| 5926 | 606249U, // LD1Fourv1d |
| 5927 | 99188777U, // LD1Fourv1d_POST |
| 5928 | 639017U, // LD1Fourv2d |
| 5929 | 97124393U, // LD1Fourv2d_POST |
| 5930 | 671785U, // LD1Fourv2s |
| 5931 | 99254313U, // LD1Fourv2s_POST |
| 5932 | 704553U, // LD1Fourv4h |
| 5933 | 99287081U, // LD1Fourv4h_POST |
| 5934 | 737321U, // LD1Fourv4s |
| 5935 | 97222697U, // LD1Fourv4s_POST |
| 5936 | 770089U, // LD1Fourv8b |
| 5937 | 99352617U, // LD1Fourv8b_POST |
| 5938 | 802857U, // LD1Fourv8h |
| 5939 | 97288233U, // LD1Fourv8h_POST |
| 5940 | 811781620U, // LD1H |
| 5941 | 899862004U, // LD1H_2Z |
| 5942 | 899862004U, // LD1H_2Z_IMM |
| 5943 | 2955726324U, // LD1H_2Z_STRIDED |
| 5944 | 2955726324U, // LD1H_2Z_STRIDED_IMM |
| 5945 | 899862004U, // LD1H_4Z |
| 5946 | 899862004U, // LD1H_4Z_IMM |
| 5947 | 899862004U, // LD1H_4Z_STRIDED |
| 5948 | 899862004U, // LD1H_4Z_STRIDED_IMM |
| 5949 | 811765236U, // LD1H_D |
| 5950 | 811765236U, // LD1H_D_IMM |
| 5951 | 811781620U, // LD1H_IMM |
| 5952 | 811798004U, // LD1H_S |
| 5953 | 811798004U, // LD1H_S_IMM |
| 5954 | 573481U, // LD1Onev16b |
| 5955 | 101253161U, // LD1Onev16b_POST |
| 5956 | 606249U, // LD1Onev1d |
| 5957 | 103383081U, // LD1Onev1d_POST |
| 5958 | 639017U, // LD1Onev2d |
| 5959 | 101318697U, // LD1Onev2d_POST |
| 5960 | 671785U, // LD1Onev2s |
| 5961 | 103448617U, // LD1Onev2s_POST |
| 5962 | 704553U, // LD1Onev4h |
| 5963 | 103481385U, // LD1Onev4h_POST |
| 5964 | 737321U, // LD1Onev4s |
| 5965 | 101417001U, // LD1Onev4s_POST |
| 5966 | 770089U, // LD1Onev8b |
| 5967 | 103546921U, // LD1Onev8b_POST |
| 5968 | 802857U, // LD1Onev8h |
| 5969 | 101482537U, // LD1Onev8h_POST |
| 5970 | 811763978U, // LD1RB_D_IMM |
| 5971 | 811780362U, // LD1RB_H_IMM |
| 5972 | 811747594U, // LD1RB_IMM |
| 5973 | 811796746U, // LD1RB_S_IMM |
| 5974 | 811764874U, // LD1RD_IMM |
| 5975 | 811765786U, // LD1RH_D_IMM |
| 5976 | 811782170U, // LD1RH_IMM |
| 5977 | 811798554U, // LD1RH_S_IMM |
| 5978 | 811747565U, // LD1RO_B |
| 5979 | 811747565U, // LD1RO_B_IMM |
| 5980 | 811764858U, // LD1RO_D |
| 5981 | 811764858U, // LD1RO_D_IMM |
| 5982 | 811782148U, // LD1RO_H |
| 5983 | 811782148U, // LD1RO_H_IMM |
| 5984 | 811803688U, // LD1RO_W |
| 5985 | 811803688U, // LD1RO_W_IMM |
| 5986 | 811747586U, // LD1RQ_B |
| 5987 | 811747586U, // LD1RQ_B_IMM |
| 5988 | 811764866U, // LD1RQ_D |
| 5989 | 811764866U, // LD1RQ_D_IMM |
| 5990 | 811782162U, // LD1RQ_H |
| 5991 | 811782162U, // LD1RQ_H_IMM |
| 5992 | 811803696U, // LD1RQ_W |
| 5993 | 811803696U, // LD1RQ_W_IMM |
| 5994 | 811764189U, // LD1RSB_D_IMM |
| 5995 | 811780573U, // LD1RSB_H_IMM |
| 5996 | 811796957U, // LD1RSB_S_IMM |
| 5997 | 811765984U, // LD1RSH_D_IMM |
| 5998 | 811798752U, // LD1RSH_S_IMM |
| 5999 | 811770993U, // LD1RSW_IMM |
| 6000 | 811770936U, // LD1RW_D_IMM |
| 6001 | 811803704U, // LD1RW_IMM |
| 6002 | 580417U, // LD1Rv16b |
| 6003 | 105454401U, // LD1Rv16b_POST |
| 6004 | 613185U, // LD1Rv1d |
| 6005 | 103390017U, // LD1Rv1d_POST |
| 6006 | 645953U, // LD1Rv2d |
| 6007 | 103422785U, // LD1Rv2d_POST |
| 6008 | 678721U, // LD1Rv2s |
| 6009 | 107649857U, // LD1Rv2s_POST |
| 6010 | 711489U, // LD1Rv4h |
| 6011 | 109779777U, // LD1Rv4h_POST |
| 6012 | 744257U, // LD1Rv4s |
| 6013 | 107715393U, // LD1Rv4s_POST |
| 6014 | 777025U, // LD1Rv8b |
| 6015 | 105651009U, // LD1Rv8b_POST |
| 6016 | 809793U, // LD1Rv8h |
| 6017 | 109878081U, // LD1Rv8h_POST |
| 6018 | 811764126U, // LD1SB_D |
| 6019 | 811764126U, // LD1SB_D_IMM |
| 6020 | 811780510U, // LD1SB_H |
| 6021 | 811780510U, // LD1SB_H_IMM |
| 6022 | 811796894U, // LD1SB_S |
| 6023 | 811796894U, // LD1SB_S_IMM |
| 6024 | 811765934U, // LD1SH_D |
| 6025 | 811765934U, // LD1SH_D_IMM |
| 6026 | 811798702U, // LD1SH_S |
| 6027 | 811798702U, // LD1SH_S_IMM |
| 6028 | 811770952U, // LD1SW_D |
| 6029 | 811770952U, // LD1SW_D_IMM |
| 6030 | 573481U, // LD1Threev16b |
| 6031 | 111738921U, // LD1Threev16b_POST |
| 6032 | 606249U, // LD1Threev1d |
| 6033 | 113868841U, // LD1Threev1d_POST |
| 6034 | 639017U, // LD1Threev2d |
| 6035 | 111804457U, // LD1Threev2d_POST |
| 6036 | 671785U, // LD1Threev2s |
| 6037 | 113934377U, // LD1Threev2s_POST |
| 6038 | 704553U, // LD1Threev4h |
| 6039 | 113967145U, // LD1Threev4h_POST |
| 6040 | 737321U, // LD1Threev4s |
| 6041 | 111902761U, // LD1Threev4s_POST |
| 6042 | 770089U, // LD1Threev8b |
| 6043 | 114032681U, // LD1Threev8b_POST |
| 6044 | 802857U, // LD1Threev8h |
| 6045 | 111968297U, // LD1Threev8h_POST |
| 6046 | 573481U, // LD1Twov16b |
| 6047 | 99156009U, // LD1Twov16b_POST |
| 6048 | 606249U, // LD1Twov1d |
| 6049 | 101285929U, // LD1Twov1d_POST |
| 6050 | 639017U, // LD1Twov2d |
| 6051 | 99221545U, // LD1Twov2d_POST |
| 6052 | 671785U, // LD1Twov2s |
| 6053 | 101351465U, // LD1Twov2s_POST |
| 6054 | 704553U, // LD1Twov4h |
| 6055 | 101384233U, // LD1Twov4h_POST |
| 6056 | 737321U, // LD1Twov4s |
| 6057 | 99319849U, // LD1Twov4s_POST |
| 6058 | 770089U, // LD1Twov8b |
| 6059 | 101449769U, // LD1Twov8b_POST |
| 6060 | 802857U, // LD1Twov8h |
| 6061 | 99385385U, // LD1Twov8h_POST |
| 6062 | 811803525U, // LD1W |
| 6063 | 899883909U, // LD1W_2Z |
| 6064 | 899883909U, // LD1W_2Z_IMM |
| 6065 | 899883909U, // LD1W_2Z_STRIDED |
| 6066 | 899883909U, // LD1W_2Z_STRIDED_IMM |
| 6067 | 899883909U, // LD1W_4Z |
| 6068 | 899883909U, // LD1W_4Z_IMM |
| 6069 | 899883909U, // LD1W_4Z_STRIDED |
| 6070 | 899883909U, // LD1W_4Z_STRIDED_IMM |
| 6071 | 811770757U, // LD1W_D |
| 6072 | 811770757U, // LD1W_D_IMM |
| 6073 | 811803525U, // LD1W_IMM |
| 6074 | 812098437U, // LD1W_Q |
| 6075 | 812098437U, // LD1W_Q_IMM |
| 6076 | 2473078091U, // LD1_MXIPXX_H_B |
| 6077 | 2473078105U, // LD1_MXIPXX_H_D |
| 6078 | 2473078119U, // LD1_MXIPXX_H_H |
| 6079 | 2473078133U, // LD1_MXIPXX_H_Q |
| 6080 | 2473078147U, // LD1_MXIPXX_H_S |
| 6081 | 2473094475U, // LD1_MXIPXX_V_B |
| 6082 | 2473094489U, // LD1_MXIPXX_V_D |
| 6083 | 2473094503U, // LD1_MXIPXX_V_H |
| 6084 | 2473094517U, // LD1_MXIPXX_V_Q |
| 6085 | 2473094531U, // LD1_MXIPXX_V_S |
| 6086 | 116195369U, // LD1i16 |
| 6087 | 118308905U, // LD1i16_POST |
| 6088 | 116228137U, // LD1i32 |
| 6089 | 120438825U, // LD1i32_POST |
| 6090 | 116260905U, // LD1i64 |
| 6091 | 122568745U, // LD1i64_POST |
| 6092 | 116293673U, // LD1i8 |
| 6093 | 124698665U, // LD1i8_POST |
| 6094 | 811746759U, // LD2B |
| 6095 | 811746759U, // LD2B_IMM |
| 6096 | 811764600U, // LD2D |
| 6097 | 811764600U, // LD2D_IMM |
| 6098 | 811781681U, // LD2H |
| 6099 | 811781681U, // LD2H_IMM |
| 6100 | 812096218U, // LD2Q |
| 6101 | 812096218U, // LD2Q_IMM |
| 6102 | 580423U, // LD2Rv16b |
| 6103 | 109648711U, // LD2Rv16b_POST |
| 6104 | 613191U, // LD2Rv1d |
| 6105 | 101292871U, // LD2Rv1d_POST |
| 6106 | 645959U, // LD2Rv2d |
| 6107 | 101325639U, // LD2Rv2d_POST |
| 6108 | 678727U, // LD2Rv2s |
| 6109 | 103455559U, // LD2Rv2s_POST |
| 6110 | 711495U, // LD2Rv4h |
| 6111 | 107682631U, // LD2Rv4h_POST |
| 6112 | 744263U, // LD2Rv4s |
| 6113 | 103521095U, // LD2Rv4s_POST |
| 6114 | 777031U, // LD2Rv8b |
| 6115 | 109845319U, // LD2Rv8b_POST |
| 6116 | 809799U, // LD2Rv8h |
| 6117 | 107780935U, // LD2Rv8h_POST |
| 6118 | 573614U, // LD2Twov16b |
| 6119 | 99156142U, // LD2Twov16b_POST |
| 6120 | 639150U, // LD2Twov2d |
| 6121 | 99221678U, // LD2Twov2d_POST |
| 6122 | 671918U, // LD2Twov2s |
| 6123 | 101351598U, // LD2Twov2s_POST |
| 6124 | 704686U, // LD2Twov4h |
| 6125 | 101384366U, // LD2Twov4h_POST |
| 6126 | 737454U, // LD2Twov4s |
| 6127 | 99319982U, // LD2Twov4s_POST |
| 6128 | 770222U, // LD2Twov8b |
| 6129 | 101449902U, // LD2Twov8b_POST |
| 6130 | 802990U, // LD2Twov8h |
| 6131 | 99385518U, // LD2Twov8h_POST |
| 6132 | 811803577U, // LD2W |
| 6133 | 811803577U, // LD2W_IMM |
| 6134 | 116195502U, // LD2i16 |
| 6135 | 120406190U, // LD2i16_POST |
| 6136 | 116228270U, // LD2i32 |
| 6137 | 122536110U, // LD2i32_POST |
| 6138 | 116261038U, // LD2i64 |
| 6139 | 126763182U, // LD2i64_POST |
| 6140 | 116293806U, // LD2i8 |
| 6141 | 118407342U, // LD2i8_POST |
| 6142 | 811746780U, // LD3B |
| 6143 | 811746780U, // LD3B_IMM |
| 6144 | 811764612U, // LD3D |
| 6145 | 811764612U, // LD3D_IMM |
| 6146 | 811781693U, // LD3H |
| 6147 | 811781693U, // LD3H_IMM |
| 6148 | 812096230U, // LD3Q |
| 6149 | 812096230U, // LD3Q_IMM |
| 6150 | 580429U, // LD3Rv16b |
| 6151 | 128523085U, // LD3Rv16b_POST |
| 6152 | 613197U, // LD3Rv1d |
| 6153 | 113875789U, // LD3Rv1d_POST |
| 6154 | 645965U, // LD3Rv2d |
| 6155 | 113908557U, // LD3Rv2d_POST |
| 6156 | 678733U, // LD3Rv2s |
| 6157 | 130718541U, // LD3Rv2s_POST |
| 6158 | 711501U, // LD3Rv4h |
| 6159 | 132848461U, // LD3Rv4h_POST |
| 6160 | 744269U, // LD3Rv4s |
| 6161 | 130784077U, // LD3Rv4s_POST |
| 6162 | 777037U, // LD3Rv8b |
| 6163 | 128719693U, // LD3Rv8b_POST |
| 6164 | 809805U, // LD3Rv8h |
| 6165 | 132946765U, // LD3Rv8h_POST |
| 6166 | 574071U, // LD3Threev16b |
| 6167 | 111739511U, // LD3Threev16b_POST |
| 6168 | 639607U, // LD3Threev2d |
| 6169 | 111805047U, // LD3Threev2d_POST |
| 6170 | 672375U, // LD3Threev2s |
| 6171 | 113934967U, // LD3Threev2s_POST |
| 6172 | 705143U, // LD3Threev4h |
| 6173 | 113967735U, // LD3Threev4h_POST |
| 6174 | 737911U, // LD3Threev4s |
| 6175 | 111903351U, // LD3Threev4s_POST |
| 6176 | 770679U, // LD3Threev8b |
| 6177 | 114033271U, // LD3Threev8b_POST |
| 6178 | 803447U, // LD3Threev8h |
| 6179 | 111968887U, // LD3Threev8h_POST |
| 6180 | 811803589U, // LD3W |
| 6181 | 811803589U, // LD3W_IMM |
| 6182 | 116195959U, // LD3i16 |
| 6183 | 135086711U, // LD3i16_POST |
| 6184 | 116228727U, // LD3i32 |
| 6185 | 137216631U, // LD3i32_POST |
| 6186 | 116261495U, // LD3i64 |
| 6187 | 139346551U, // LD3i64_POST |
| 6188 | 116294263U, // LD3i8 |
| 6189 | 141476471U, // LD3i8_POST |
| 6190 | 811746806U, // LD4B |
| 6191 | 811746806U, // LD4B_IMM |
| 6192 | 811764624U, // LD4D |
| 6193 | 811764624U, // LD4D_IMM |
| 6194 | 574101U, // LD4Fourv16b |
| 6195 | 97059477U, // LD4Fourv16b_POST |
| 6196 | 639637U, // LD4Fourv2d |
| 6197 | 97125013U, // LD4Fourv2d_POST |
| 6198 | 672405U, // LD4Fourv2s |
| 6199 | 99254933U, // LD4Fourv2s_POST |
| 6200 | 705173U, // LD4Fourv4h |
| 6201 | 99287701U, // LD4Fourv4h_POST |
| 6202 | 737941U, // LD4Fourv4s |
| 6203 | 97223317U, // LD4Fourv4s_POST |
| 6204 | 770709U, // LD4Fourv8b |
| 6205 | 99353237U, // LD4Fourv8b_POST |
| 6206 | 803477U, // LD4Fourv8h |
| 6207 | 97288853U, // LD4Fourv8h_POST |
| 6208 | 811781705U, // LD4H |
| 6209 | 811781705U, // LD4H_IMM |
| 6210 | 812096242U, // LD4Q |
| 6211 | 812096242U, // LD4Q_IMM |
| 6212 | 580435U, // LD4Rv16b |
| 6213 | 107551571U, // LD4Rv16b_POST |
| 6214 | 613203U, // LD4Rv1d |
| 6215 | 99195731U, // LD4Rv1d_POST |
| 6216 | 645971U, // LD4Rv2d |
| 6217 | 99228499U, // LD4Rv2d_POST |
| 6218 | 678739U, // LD4Rv2s |
| 6219 | 101358419U, // LD4Rv2s_POST |
| 6220 | 711507U, // LD4Rv4h |
| 6221 | 103488339U, // LD4Rv4h_POST |
| 6222 | 744275U, // LD4Rv4s |
| 6223 | 101423955U, // LD4Rv4s_POST |
| 6224 | 777043U, // LD4Rv8b |
| 6225 | 107748179U, // LD4Rv8b_POST |
| 6226 | 809811U, // LD4Rv8h |
| 6227 | 103586643U, // LD4Rv8h_POST |
| 6228 | 811803601U, // LD4W |
| 6229 | 811803601U, // LD4W_IMM |
| 6230 | 116195989U, // LD4i16 |
| 6231 | 122503829U, // LD4i16_POST |
| 6232 | 116228757U, // LD4i32 |
| 6233 | 126730901U, // LD4i32_POST |
| 6234 | 116261525U, // LD4i64 |
| 6235 | 143540885U, // LD4i64_POST |
| 6236 | 116294293U, // LD4i8 |
| 6237 | 120504981U, // LD4i8_POST |
| 6238 | 984552U, // LD64B |
| 6239 | 3223635458U, // LDADDAB |
| 6240 | 3223637598U, // LDADDAH |
| 6241 | 3223635700U, // LDADDALB |
| 6242 | 3223637779U, // LDADDALH |
| 6243 | 3223638487U, // LDADDALW |
| 6244 | 3223638487U, // LDADDALX |
| 6245 | 3223634711U, // LDADDAW |
| 6246 | 3223634711U, // LDADDAX |
| 6247 | 3223635626U, // LDADDB |
| 6248 | 3223637758U, // LDADDH |
| 6249 | 3223635881U, // LDADDLB |
| 6250 | 3223637879U, // LDADDLH |
| 6251 | 3223638997U, // LDADDLW |
| 6252 | 3223638997U, // LDADDLX |
| 6253 | 3223636984U, // LDADDW |
| 6254 | 3223636984U, // LDADDX |
| 6255 | 116260922U, // LDAP1 |
| 6256 | 2120150U, // LDAPPi |
| 6257 | 39864645U, // LDAPRB |
| 6258 | 39866453U, // LDAPRH |
| 6259 | 39869575U, // LDAPRW |
| 6260 | 845470855U, // LDAPRWpost |
| 6261 | 39869575U, // LDAPRX |
| 6262 | 845470855U, // LDAPRXpost |
| 6263 | 39864688U, // LDAPURBi |
| 6264 | 39866496U, // LDAPURHi |
| 6265 | 39864828U, // LDAPURSBWi |
| 6266 | 39864828U, // LDAPURSBXi |
| 6267 | 39866623U, // LDAPURSHWi |
| 6268 | 39866623U, // LDAPURSHXi |
| 6269 | 39871632U, // LDAPURSWi |
| 6270 | 39869668U, // LDAPURXi |
| 6271 | 39869668U, // LDAPURbi |
| 6272 | 39869668U, // LDAPURdi |
| 6273 | 39869668U, // LDAPURhi |
| 6274 | 39869668U, // LDAPURi |
| 6275 | 39869668U, // LDAPURqi |
| 6276 | 39869668U, // LDAPURsi |
| 6277 | 2119926U, // LDAPi |
| 6278 | 39864593U, // LDARB |
| 6279 | 39866401U, // LDARH |
| 6280 | 39869273U, // LDARW |
| 6281 | 39869273U, // LDARX |
| 6282 | 39869732U, // LDATXRW |
| 6283 | 39869732U, // LDATXRX |
| 6284 | 2120346U, // LDAXPW |
| 6285 | 2120346U, // LDAXPX |
| 6286 | 39864704U, // LDAXRB |
| 6287 | 39866512U, // LDAXRH |
| 6288 | 39869712U, // LDAXRW |
| 6289 | 39869712U, // LDAXRX |
| 6290 | 3223636991U, // LDBFADD |
| 6291 | 3223634719U, // LDBFADDA |
| 6292 | 3223638496U, // LDBFADDAL |
| 6293 | 3223639005U, // LDBFADDL |
| 6294 | 3223643355U, // LDBFMAX |
| 6295 | 3223635269U, // LDBFMAXA |
| 6296 | 3223638907U, // LDBFMAXAL |
| 6297 | 3223639759U, // LDBFMAXL |
| 6298 | 3223639912U, // LDBFMAXNM |
| 6299 | 3223634855U, // LDBFMAXNMA |
| 6300 | 3223638590U, // LDBFMAXNMAL |
| 6301 | 3223639291U, // LDBFMAXNML |
| 6302 | 3223640021U, // LDBFMIN |
| 6303 | 3223634878U, // LDBFMINA |
| 6304 | 3223638615U, // LDBFMINAL |
| 6305 | 3223639337U, // LDBFMINL |
| 6306 | 3223639870U, // LDBFMINNM |
| 6307 | 3223634832U, // LDBFMINNMA |
| 6308 | 3223638565U, // LDBFMINNMAL |
| 6309 | 3223639245U, // LDBFMINNML |
| 6310 | 3223635514U, // LDCLRAB |
| 6311 | 3223637655U, // LDCLRAH |
| 6312 | 3223635775U, // LDCLRALB |
| 6313 | 3223637819U, // LDCLRALH |
| 6314 | 3223638789U, // LDCLRALW |
| 6315 | 3223638789U, // LDCLRALX |
| 6316 | 3223635108U, // LDCLRAW |
| 6317 | 3223635108U, // LDCLRAX |
| 6318 | 3223636262U, // LDCLRB |
| 6319 | 3223638070U, // LDCLRH |
| 6320 | 3223635983U, // LDCLRLB |
| 6321 | 3223637915U, // LDCLRLH |
| 6322 | 3223639529U, // LDCLRLW |
| 6323 | 3223639529U, // LDCLRLX |
| 6324 | 2419022347U, // LDCLRP |
| 6325 | 2419016761U, // LDCLRPA |
| 6326 | 2419020439U, // LDCLRPAL |
| 6327 | 2419021181U, // LDCLRPL |
| 6328 | 3223641105U, // LDCLRW |
| 6329 | 3223641105U, // LDCLRX |
| 6330 | 3223635523U, // LDEORAB |
| 6331 | 3223637664U, // LDEORAH |
| 6332 | 3223635785U, // LDEORALB |
| 6333 | 3223637829U, // LDEORALH |
| 6334 | 3223638829U, // LDEORALW |
| 6335 | 3223638829U, // LDEORALX |
| 6336 | 3223635144U, // LDEORAW |
| 6337 | 3223635144U, // LDEORAX |
| 6338 | 3223636285U, // LDEORB |
| 6339 | 3223638093U, // LDEORH |
| 6340 | 3223635992U, // LDEORLB |
| 6341 | 3223637924U, // LDEORLH |
| 6342 | 3223639565U, // LDEORLW |
| 6343 | 3223639565U, // LDEORLX |
| 6344 | 3223641206U, // LDEORW |
| 6345 | 3223641206U, // LDEORX |
| 6346 | 3223634729U, // LDFADDAD |
| 6347 | 3223634729U, // LDFADDAH |
| 6348 | 3223638507U, // LDFADDALD |
| 6349 | 3223638507U, // LDFADDALH |
| 6350 | 3223638507U, // LDFADDALS |
| 6351 | 3223634729U, // LDFADDAS |
| 6352 | 3223637009U, // LDFADDD |
| 6353 | 3223637009U, // LDFADDH |
| 6354 | 3223639025U, // LDFADDLD |
| 6355 | 3223639025U, // LDFADDLH |
| 6356 | 3223639025U, // LDFADDLS |
| 6357 | 3223637009U, // LDFADDS |
| 6358 | 811746704U, // LDFF1B |
| 6359 | 811763088U, // LDFF1B_D |
| 6360 | 811779472U, // LDFF1B_H |
| 6361 | 811795856U, // LDFF1B_S |
| 6362 | 811764562U, // LDFF1D |
| 6363 | 811781626U, // LDFF1H |
| 6364 | 811765242U, // LDFF1H_D |
| 6365 | 811798010U, // LDFF1H_S |
| 6366 | 811764133U, // LDFF1SB_D |
| 6367 | 811780517U, // LDFF1SB_H |
| 6368 | 811796901U, // LDFF1SB_S |
| 6369 | 811765941U, // LDFF1SH_D |
| 6370 | 811798709U, // LDFF1SH_S |
| 6371 | 811770959U, // LDFF1SW_D |
| 6372 | 811803531U, // LDFF1W |
| 6373 | 811770763U, // LDFF1W_D |
| 6374 | 3223635279U, // LDFMAXAD |
| 6375 | 3223635279U, // LDFMAXAH |
| 6376 | 3223638918U, // LDFMAXALD |
| 6377 | 3223638918U, // LDFMAXALH |
| 6378 | 3223638918U, // LDFMAXALS |
| 6379 | 3223635279U, // LDFMAXAS |
| 6380 | 3223643373U, // LDFMAXD |
| 6381 | 3223643373U, // LDFMAXH |
| 6382 | 3223639779U, // LDFMAXLD |
| 6383 | 3223639779U, // LDFMAXLH |
| 6384 | 3223639779U, // LDFMAXLS |
| 6385 | 3223634867U, // LDFMAXNMAD |
| 6386 | 3223634867U, // LDFMAXNMAH |
| 6387 | 3223638603U, // LDFMAXNMALD |
| 6388 | 3223638603U, // LDFMAXNMALH |
| 6389 | 3223638603U, // LDFMAXNMALS |
| 6390 | 3223634867U, // LDFMAXNMAS |
| 6391 | 3223639934U, // LDFMAXNMD |
| 6392 | 3223639934U, // LDFMAXNMH |
| 6393 | 3223639315U, // LDFMAXNMLD |
| 6394 | 3223639315U, // LDFMAXNMLH |
| 6395 | 3223639315U, // LDFMAXNMLS |
| 6396 | 3223639934U, // LDFMAXNMS |
| 6397 | 3223643373U, // LDFMAXS |
| 6398 | 3223634888U, // LDFMINAD |
| 6399 | 3223634888U, // LDFMINAH |
| 6400 | 3223638626U, // LDFMINALD |
| 6401 | 3223638626U, // LDFMINALH |
| 6402 | 3223638626U, // LDFMINALS |
| 6403 | 3223634888U, // LDFMINAS |
| 6404 | 3223640039U, // LDFMIND |
| 6405 | 3223640039U, // LDFMINH |
| 6406 | 3223639357U, // LDFMINLD |
| 6407 | 3223639357U, // LDFMINLH |
| 6408 | 3223639357U, // LDFMINLS |
| 6409 | 3223634844U, // LDFMINNMAD |
| 6410 | 3223634844U, // LDFMINNMAH |
| 6411 | 3223638578U, // LDFMINNMALD |
| 6412 | 3223638578U, // LDFMINNMALH |
| 6413 | 3223638578U, // LDFMINNMALS |
| 6414 | 3223634844U, // LDFMINNMAS |
| 6415 | 3223639892U, // LDFMINNMD |
| 6416 | 3223639892U, // LDFMINNMH |
| 6417 | 3223639269U, // LDFMINNMLD |
| 6418 | 3223639269U, // LDFMINNMLH |
| 6419 | 3223639269U, // LDFMINNMLS |
| 6420 | 3223639892U, // LDFMINNMS |
| 6421 | 3223640039U, // LDFMINS |
| 6422 | 845467067U, // LDG |
| 6423 | 39868193U, // LDGM |
| 6424 | 2120157U, // LDIAPPW |
| 6425 | 807721437U, // LDIAPPWpost |
| 6426 | 2120157U, // LDIAPPX |
| 6427 | 807721437U, // LDIAPPXpost |
| 6428 | 39864600U, // LDLARB |
| 6429 | 39866408U, // LDLARH |
| 6430 | 39869279U, // LDLARW |
| 6431 | 39869279U, // LDLARX |
| 6432 | 811763096U, // LDNF1B_D_IMM |
| 6433 | 811779480U, // LDNF1B_H_IMM |
| 6434 | 811746712U, // LDNF1B_IMM |
| 6435 | 811795864U, // LDNF1B_S_IMM |
| 6436 | 811764570U, // LDNF1D_IMM |
| 6437 | 811765250U, // LDNF1H_D_IMM |
| 6438 | 811781634U, // LDNF1H_IMM |
| 6439 | 811798018U, // LDNF1H_S_IMM |
| 6440 | 811764142U, // LDNF1SB_D_IMM |
| 6441 | 811780526U, // LDNF1SB_H_IMM |
| 6442 | 811796910U, // LDNF1SB_S_IMM |
| 6443 | 811765950U, // LDNF1SH_D_IMM |
| 6444 | 811798718U, // LDNF1SH_S_IMM |
| 6445 | 811770968U, // LDNF1SW_D_IMM |
| 6446 | 811770771U, // LDNF1W_D_IMM |
| 6447 | 811803539U, // LDNF1W_IMM |
| 6448 | 2120103U, // LDNPDi |
| 6449 | 2120103U, // LDNPQi |
| 6450 | 2120103U, // LDNPSi |
| 6451 | 2120103U, // LDNPWi |
| 6452 | 2120103U, // LDNPXi |
| 6453 | 899827104U, // LDNT1B_2Z |
| 6454 | 899827104U, // LDNT1B_2Z_IMM |
| 6455 | 2955445664U, // LDNT1B_2Z_STRIDED |
| 6456 | 2955445664U, // LDNT1B_2Z_STRIDED_IMM |
| 6457 | 899827104U, // LDNT1B_4Z |
| 6458 | 899827104U, // LDNT1B_4Z_IMM |
| 6459 | 899827104U, // LDNT1B_4Z_STRIDED |
| 6460 | 899827104U, // LDNT1B_4Z_STRIDED_IMM |
| 6461 | 811746720U, // LDNT1B_ZRI |
| 6462 | 811746720U, // LDNT1B_ZRR |
| 6463 | 811763104U, // LDNT1B_ZZR_D |
| 6464 | 811795872U, // LDNT1B_ZZR_S |
| 6465 | 899844962U, // LDNT1D_2Z |
| 6466 | 899844962U, // LDNT1D_2Z_IMM |
| 6467 | 899844962U, // LDNT1D_2Z_STRIDED |
| 6468 | 899844962U, // LDNT1D_2Z_STRIDED_IMM |
| 6469 | 899844962U, // LDNT1D_4Z |
| 6470 | 899844962U, // LDNT1D_4Z_IMM |
| 6471 | 899844962U, // LDNT1D_4Z_STRIDED |
| 6472 | 899844962U, // LDNT1D_4Z_STRIDED_IMM |
| 6473 | 811764578U, // LDNT1D_ZRI |
| 6474 | 811764578U, // LDNT1D_ZRR |
| 6475 | 811764578U, // LDNT1D_ZZR_D |
| 6476 | 899862026U, // LDNT1H_2Z |
| 6477 | 899862026U, // LDNT1H_2Z_IMM |
| 6478 | 2955726346U, // LDNT1H_2Z_STRIDED |
| 6479 | 2955726346U, // LDNT1H_2Z_STRIDED_IMM |
| 6480 | 899862026U, // LDNT1H_4Z |
| 6481 | 899862026U, // LDNT1H_4Z_IMM |
| 6482 | 899862026U, // LDNT1H_4Z_STRIDED |
| 6483 | 899862026U, // LDNT1H_4Z_STRIDED_IMM |
| 6484 | 811781642U, // LDNT1H_ZRI |
| 6485 | 811781642U, // LDNT1H_ZRR |
| 6486 | 811765258U, // LDNT1H_ZZR_D |
| 6487 | 811798026U, // LDNT1H_ZZR_S |
| 6488 | 811764151U, // LDNT1SB_ZZR_D |
| 6489 | 811796919U, // LDNT1SB_ZZR_S |
| 6490 | 811765959U, // LDNT1SH_ZZR_D |
| 6491 | 811798727U, // LDNT1SH_ZZR_S |
| 6492 | 811770977U, // LDNT1SW_ZZR_D |
| 6493 | 899883931U, // LDNT1W_2Z |
| 6494 | 899883931U, // LDNT1W_2Z_IMM |
| 6495 | 899883931U, // LDNT1W_2Z_STRIDED |
| 6496 | 899883931U, // LDNT1W_2Z_STRIDED_IMM |
| 6497 | 899883931U, // LDNT1W_4Z |
| 6498 | 899883931U, // LDNT1W_4Z_IMM |
| 6499 | 899883931U, // LDNT1W_4Z_STRIDED |
| 6500 | 899883931U, // LDNT1W_4Z_STRIDED_IMM |
| 6501 | 811803547U, // LDNT1W_ZRI |
| 6502 | 811803547U, // LDNT1W_ZRR |
| 6503 | 811770779U, // LDNT1W_ZZR_D |
| 6504 | 811803547U, // LDNT1W_ZZR_S |
| 6505 | 2119980U, // LDPDi |
| 6506 | 807721260U, // LDPDpost |
| 6507 | 807721260U, // LDPDpre |
| 6508 | 2119980U, // LDPQi |
| 6509 | 807721260U, // LDPQpost |
| 6510 | 807721260U, // LDPQpre |
| 6511 | 2122858U, // LDPSWi |
| 6512 | 807724138U, // LDPSWpost |
| 6513 | 807724138U, // LDPSWpre |
| 6514 | 2119980U, // LDPSi |
| 6515 | 807721260U, // LDPSpost |
| 6516 | 807721260U, // LDPSpre |
| 6517 | 2119980U, // LDPWi |
| 6518 | 807721260U, // LDPWpost |
| 6519 | 807721260U, // LDPWpre |
| 6520 | 2119980U, // LDPXi |
| 6521 | 807721260U, // LDPXpost |
| 6522 | 807721260U, // LDPXpre |
| 6523 | 39863030U, // LDRAAindexed |
| 6524 | 845464310U, // LDRAAwriteback |
| 6525 | 39863852U, // LDRABindexed |
| 6526 | 845465132U, // LDRABwriteback |
| 6527 | 845465888U, // LDRBBpost |
| 6528 | 845465888U, // LDRBBpre |
| 6529 | 39864608U, // LDRBBroW |
| 6530 | 39864608U, // LDRBBroX |
| 6531 | 39864608U, // LDRBBui |
| 6532 | 845470663U, // LDRBpost |
| 6533 | 845470663U, // LDRBpre |
| 6534 | 39869383U, // LDRBroW |
| 6535 | 39869383U, // LDRBroX |
| 6536 | 39869383U, // LDRBui |
| 6537 | 2418039751U, // LDRDl |
| 6538 | 845470663U, // LDRDpost |
| 6539 | 845470663U, // LDRDpre |
| 6540 | 39869383U, // LDRDroW |
| 6541 | 39869383U, // LDRDroX |
| 6542 | 39869383U, // LDRDui |
| 6543 | 845467696U, // LDRHHpost |
| 6544 | 845467696U, // LDRHHpre |
| 6545 | 39866416U, // LDRHHroW |
| 6546 | 39866416U, // LDRHHroX |
| 6547 | 39866416U, // LDRHHui |
| 6548 | 845470663U, // LDRHpost |
| 6549 | 845470663U, // LDRHpre |
| 6550 | 39869383U, // LDRHroW |
| 6551 | 39869383U, // LDRHroX |
| 6552 | 39869383U, // LDRHui |
| 6553 | 2418039751U, // LDRQl |
| 6554 | 845470663U, // LDRQpost |
| 6555 | 845470663U, // LDRQpre |
| 6556 | 39869383U, // LDRQroW |
| 6557 | 39869383U, // LDRQroX |
| 6558 | 39869383U, // LDRQui |
| 6559 | 845466085U, // LDRSBWpost |
| 6560 | 845466085U, // LDRSBWpre |
| 6561 | 39864805U, // LDRSBWroW |
| 6562 | 39864805U, // LDRSBWroX |
| 6563 | 39864805U, // LDRSBWui |
| 6564 | 845466085U, // LDRSBXpost |
| 6565 | 845466085U, // LDRSBXpre |
| 6566 | 39864805U, // LDRSBXroW |
| 6567 | 39864805U, // LDRSBXroX |
| 6568 | 39864805U, // LDRSBXui |
| 6569 | 845467880U, // LDRSHWpost |
| 6570 | 845467880U, // LDRSHWpre |
| 6571 | 39866600U, // LDRSHWroW |
| 6572 | 39866600U, // LDRSHWroX |
| 6573 | 39866600U, // LDRSHWui |
| 6574 | 845467880U, // LDRSHXpost |
| 6575 | 845467880U, // LDRSHXpre |
| 6576 | 39866600U, // LDRSHXroW |
| 6577 | 39866600U, // LDRSHXroX |
| 6578 | 39866600U, // LDRSHXui |
| 6579 | 2418041977U, // LDRSWl |
| 6580 | 845472889U, // LDRSWpost |
| 6581 | 845472889U, // LDRSWpre |
| 6582 | 39871609U, // LDRSWroW |
| 6583 | 39871609U, // LDRSWroX |
| 6584 | 39871609U, // LDRSWui |
| 6585 | 2418039751U, // LDRSl |
| 6586 | 845470663U, // LDRSpost |
| 6587 | 845470663U, // LDRSpre |
| 6588 | 39869383U, // LDRSroW |
| 6589 | 39869383U, // LDRSroX |
| 6590 | 39869383U, // LDRSui |
| 6591 | 2418039751U, // LDRWl |
| 6592 | 845470663U, // LDRWpost |
| 6593 | 845470663U, // LDRWpre |
| 6594 | 39869383U, // LDRWroW |
| 6595 | 39869383U, // LDRWroX |
| 6596 | 39869383U, // LDRWui |
| 6597 | 2418039751U, // LDRXl |
| 6598 | 845470663U, // LDRXpost |
| 6599 | 845470663U, // LDRXpre |
| 6600 | 39869383U, // LDRXroW |
| 6601 | 39869383U, // LDRXroX |
| 6602 | 39869383U, // LDRXui |
| 6603 | 40868807U, // LDR_PXI |
| 6604 | 39869383U, // LDR_TX |
| 6605 | 1039303U, // LDR_ZA |
| 6606 | 40868807U, // LDR_ZXI |
| 6607 | 3223635539U, // LDSETAB |
| 6608 | 3223637680U, // LDSETAH |
| 6609 | 3223635803U, // LDSETALB |
| 6610 | 3223637847U, // LDSETALH |
| 6611 | 3223638859U, // LDSETALW |
| 6612 | 3223638859U, // LDSETALX |
| 6613 | 3223635197U, // LDSETAW |
| 6614 | 3223635197U, // LDSETAX |
| 6615 | 3223636491U, // LDSETB |
| 6616 | 3223638281U, // LDSETH |
| 6617 | 3223636043U, // LDSETLB |
| 6618 | 3223637940U, // LDSETLH |
| 6619 | 3223639635U, // LDSETLW |
| 6620 | 3223639635U, // LDSETLX |
| 6621 | 2419022405U, // LDSETP |
| 6622 | 2419016812U, // LDSETPA |
| 6623 | 2419020495U, // LDSETPAL |
| 6624 | 2419021240U, // LDSETPL |
| 6625 | 3223641887U, // LDSETW |
| 6626 | 3223641887U, // LDSETX |
| 6627 | 3223635548U, // LDSMAXAB |
| 6628 | 3223637689U, // LDSMAXAH |
| 6629 | 3223635813U, // LDSMAXALB |
| 6630 | 3223637857U, // LDSMAXALH |
| 6631 | 3223638928U, // LDSMAXALW |
| 6632 | 3223638928U, // LDSMAXALX |
| 6633 | 3223635288U, // LDSMAXAW |
| 6634 | 3223635288U, // LDSMAXAX |
| 6635 | 3223636647U, // LDSMAXB |
| 6636 | 3223638319U, // LDSMAXH |
| 6637 | 3223636052U, // LDSMAXLB |
| 6638 | 3223637982U, // LDSMAXLH |
| 6639 | 3223639797U, // LDSMAXLW |
| 6640 | 3223639797U, // LDSMAXLX |
| 6641 | 3223643389U, // LDSMAXW |
| 6642 | 3223643389U, // LDSMAXX |
| 6643 | 3223635467U, // LDSMINAB |
| 6644 | 3223637628U, // LDSMINAH |
| 6645 | 3223635745U, // LDSMINALB |
| 6646 | 3223637789U, // LDSMINALH |
| 6647 | 3223638636U, // LDSMINALW |
| 6648 | 3223638636U, // LDSMINALX |
| 6649 | 3223634897U, // LDSMINAW |
| 6650 | 3223634897U, // LDSMINAX |
| 6651 | 3223636095U, // LDSMINB |
| 6652 | 3223638002U, // LDSMINH |
| 6653 | 3223635956U, // LDSMINLB |
| 6654 | 3223637888U, // LDSMINLH |
| 6655 | 3223639375U, // LDSMINLW |
| 6656 | 3223639375U, // LDSMINLX |
| 6657 | 3223640055U, // LDSMINW |
| 6658 | 3223640055U, // LDSMINX |
| 6659 | 3223638517U, // LDTADDALW |
| 6660 | 3223638517U, // LDTADDALX |
| 6661 | 3223634738U, // LDTADDAW |
| 6662 | 3223634738U, // LDTADDAX |
| 6663 | 3223639066U, // LDTADDLW |
| 6664 | 3223639066U, // LDTADDLX |
| 6665 | 3223637086U, // LDTADDW |
| 6666 | 3223637086U, // LDTADDX |
| 6667 | 3223638809U, // LDTCLRALW |
| 6668 | 3223638809U, // LDTCLRALX |
| 6669 | 3223635126U, // LDTCLRAW |
| 6670 | 3223635126U, // LDTCLRAX |
| 6671 | 3223639547U, // LDTCLRLW |
| 6672 | 3223639547U, // LDTCLRLX |
| 6673 | 3223641121U, // LDTCLRW |
| 6674 | 3223641121U, // LDTCLRX |
| 6675 | 2120130U, // LDTNPQi |
| 6676 | 2120130U, // LDTNPXi |
| 6677 | 2120255U, // LDTPQi |
| 6678 | 807721535U, // LDTPQpost |
| 6679 | 807721535U, // LDTPQpre |
| 6680 | 2120255U, // LDTPi |
| 6681 | 807721535U, // LDTPpost |
| 6682 | 807721535U, // LDTPpre |
| 6683 | 39864653U, // LDTRBi |
| 6684 | 39866461U, // LDTRHi |
| 6685 | 39864812U, // LDTRSBWi |
| 6686 | 39864812U, // LDTRSBXi |
| 6687 | 39866607U, // LDTRSHWi |
| 6688 | 39866607U, // LDTRSHXi |
| 6689 | 39871616U, // LDTRSWi |
| 6690 | 39869626U, // LDTRWi |
| 6691 | 39869626U, // LDTRXi |
| 6692 | 3223638879U, // LDTSETALW |
| 6693 | 3223638879U, // LDTSETALX |
| 6694 | 3223635215U, // LDTSETAW |
| 6695 | 3223635215U, // LDTSETAX |
| 6696 | 3223639653U, // LDTSETLW |
| 6697 | 3223639653U, // LDTSETLX |
| 6698 | 3223641903U, // LDTSETW |
| 6699 | 3223641903U, // LDTSETX |
| 6700 | 39869740U, // LDTXRWr |
| 6701 | 39869740U, // LDTXRXr |
| 6702 | 3223635558U, // LDUMAXAB |
| 6703 | 3223637699U, // LDUMAXAH |
| 6704 | 3223635824U, // LDUMAXALB |
| 6705 | 3223637868U, // LDUMAXALH |
| 6706 | 3223638938U, // LDUMAXALW |
| 6707 | 3223638938U, // LDUMAXALX |
| 6708 | 3223635297U, // LDUMAXAW |
| 6709 | 3223635297U, // LDUMAXAX |
| 6710 | 3223636656U, // LDUMAXB |
| 6711 | 3223638328U, // LDUMAXH |
| 6712 | 3223636062U, // LDUMAXLB |
| 6713 | 3223637992U, // LDUMAXLH |
| 6714 | 3223639806U, // LDUMAXLW |
| 6715 | 3223639806U, // LDUMAXLX |
| 6716 | 3223643397U, // LDUMAXW |
| 6717 | 3223643397U, // LDUMAXX |
| 6718 | 3223635477U, // LDUMINAB |
| 6719 | 3223637638U, // LDUMINAH |
| 6720 | 3223635756U, // LDUMINALB |
| 6721 | 3223637800U, // LDUMINALH |
| 6722 | 3223638646U, // LDUMINALW |
| 6723 | 3223638646U, // LDUMINALX |
| 6724 | 3223634906U, // LDUMINAW |
| 6725 | 3223634906U, // LDUMINAX |
| 6726 | 3223636104U, // LDUMINB |
| 6727 | 3223638011U, // LDUMINH |
| 6728 | 3223635966U, // LDUMINLB |
| 6729 | 3223637898U, // LDUMINLH |
| 6730 | 3223639384U, // LDUMINLW |
| 6731 | 3223639384U, // LDUMINLX |
| 6732 | 3223640063U, // LDUMINW |
| 6733 | 3223640063U, // LDUMINX |
| 6734 | 39864673U, // LDURBBi |
| 6735 | 39869655U, // LDURBi |
| 6736 | 39869655U, // LDURDi |
| 6737 | 39866481U, // LDURHHi |
| 6738 | 39869655U, // LDURHi |
| 6739 | 39869655U, // LDURQi |
| 6740 | 39864820U, // LDURSBWi |
| 6741 | 39864820U, // LDURSBXi |
| 6742 | 39866615U, // LDURSHWi |
| 6743 | 39866615U, // LDURSHXi |
| 6744 | 39871624U, // LDURSWi |
| 6745 | 39869655U, // LDURSi |
| 6746 | 39869655U, // LDURWi |
| 6747 | 39869655U, // LDURXi |
| 6748 | 2120374U, // LDXPW |
| 6749 | 2120374U, // LDXPX |
| 6750 | 39864712U, // LDXRB |
| 6751 | 39866520U, // LDXRH |
| 6752 | 39869719U, // LDXRW |
| 6753 | 39869719U, // LDXRX |
| 6754 | 807443562U, // LSLR_ZPmZ_B |
| 6755 | 807459946U, // LSLR_ZPmZ_D |
| 6756 | 543235178U, // LSLR_ZPmZ_H |
| 6757 | 807492714U, // LSLR_ZPmZ_S |
| 6758 | 2119218U, // LSLVWr |
| 6759 | 2119218U, // LSLVXr |
| 6760 | 807441970U, // LSL_WIDE_ZPmZ_B |
| 6761 | 543233586U, // LSL_WIDE_ZPmZ_H |
| 6762 | 807491122U, // LSL_WIDE_ZPmZ_S |
| 6763 | 3491796530U, // LSL_WIDE_ZZZ_B |
| 6764 | 2443253298U, // LSL_WIDE_ZZZ_H |
| 6765 | 3760281138U, // LSL_WIDE_ZZZ_S |
| 6766 | 807441970U, // LSL_ZPmI_B |
| 6767 | 807458354U, // LSL_ZPmI_D |
| 6768 | 543233586U, // LSL_ZPmI_H |
| 6769 | 807491122U, // LSL_ZPmI_S |
| 6770 | 807441970U, // LSL_ZPmZ_B |
| 6771 | 807458354U, // LSL_ZPmZ_D |
| 6772 | 543233586U, // LSL_ZPmZ_H |
| 6773 | 807491122U, // LSL_ZPmZ_S |
| 6774 | 3491796530U, // LSL_ZZI_B |
| 6775 | 2686506546U, // LSL_ZZI_D |
| 6776 | 2443253298U, // LSL_ZZI_H |
| 6777 | 3760281138U, // LSL_ZZI_S |
| 6778 | 807443609U, // LSRR_ZPmZ_B |
| 6779 | 807459993U, // LSRR_ZPmZ_D |
| 6780 | 543235225U, // LSRR_ZPmZ_H |
| 6781 | 807492761U, // LSRR_ZPmZ_S |
| 6782 | 2120874U, // LSRVWr |
| 6783 | 2120874U, // LSRVXr |
| 6784 | 807443626U, // LSR_WIDE_ZPmZ_B |
| 6785 | 543235242U, // LSR_WIDE_ZPmZ_H |
| 6786 | 807492778U, // LSR_WIDE_ZPmZ_S |
| 6787 | 3491798186U, // LSR_WIDE_ZZZ_B |
| 6788 | 2443254954U, // LSR_WIDE_ZZZ_H |
| 6789 | 3760282794U, // LSR_WIDE_ZZZ_S |
| 6790 | 807443626U, // LSR_ZPmI_B |
| 6791 | 807460010U, // LSR_ZPmI_D |
| 6792 | 543235242U, // LSR_ZPmI_H |
| 6793 | 807492778U, // LSR_ZPmI_S |
| 6794 | 807443626U, // LSR_ZPmZ_B |
| 6795 | 807460010U, // LSR_ZPmZ_D |
| 6796 | 543235242U, // LSR_ZPmZ_H |
| 6797 | 807492778U, // LSR_ZPmZ_S |
| 6798 | 3491798186U, // LSR_ZZI_B |
| 6799 | 2686508202U, // LSR_ZZI_D |
| 6800 | 2443254954U, // LSR_ZZI_H |
| 6801 | 3760282794U, // LSR_ZZI_S |
| 6802 | 3498148039U, // LUT2_B |
| 6803 | 3777069255U, // LUT2_H |
| 6804 | 3498148506U, // LUT4_B |
| 6805 | 3777069722U, // LUT4_H |
| 6806 | 2472689863U, // LUTI2_2ZTZI_B |
| 6807 | 2472722631U, // LUTI2_2ZTZI_H |
| 6808 | 2472739015U, // LUTI2_2ZTZI_S |
| 6809 | 2472689863U, // LUTI2_4ZTZI_B |
| 6810 | 2472722631U, // LUTI2_4ZTZI_H |
| 6811 | 2472739015U, // LUTI2_4ZTZI_S |
| 6812 | 2654407U, // LUTI2_S_2ZTZI_B |
| 6813 | 2932935U, // LUTI2_S_2ZTZI_H |
| 6814 | 2472689863U, // LUTI2_S_4ZTZI_B |
| 6815 | 2472722631U, // LUTI2_S_4ZTZI_H |
| 6816 | 2130119U, // LUTI2_ZTZI_B |
| 6817 | 2472607943U, // LUTI2_ZTZI_H |
| 6818 | 2179271U, // LUTI2_ZTZI_S |
| 6819 | 1612742855U, // LUTI2_ZZZI_B |
| 6820 | 2449539271U, // LUTI2_ZZZI_H |
| 6821 | 2472690330U, // LUTI4_2ZTZI_B |
| 6822 | 2472723098U, // LUTI4_2ZTZI_H |
| 6823 | 2472739482U, // LUTI4_2ZTZI_S |
| 6824 | 2472723098U, // LUTI4_4ZTZI_H |
| 6825 | 2472739482U, // LUTI4_4ZTZI_S |
| 6826 | 2472690330U, // LUTI4_4ZZT2Z |
| 6827 | 2654874U, // LUTI4_S_2ZTZI_B |
| 6828 | 2933402U, // LUTI4_S_2ZTZI_H |
| 6829 | 2472723098U, // LUTI4_S_4ZTZI_H |
| 6830 | 2472690330U, // LUTI4_S_4ZZT2Z |
| 6831 | 2449539738U, // LUTI4_Z2ZZI |
| 6832 | 2130586U, // LUTI4_ZTZI_B |
| 6833 | 2472608410U, // LUTI4_ZTZI_H |
| 6834 | 2179738U, // LUTI4_ZTZI_S |
| 6835 | 1612743322U, // LUTI4_ZZZI_B |
| 6836 | 2449539738U, // LUTI4_ZZZI_H |
| 6837 | 2449654453U, // LUTI6_4Z2Z2ZI |
| 6838 | 2472690357U, // LUTI6_4ZT3Z |
| 6839 | 2449654453U, // LUTI6_S_4Z2Z2ZI |
| 6840 | 2472690357U, // LUTI6_S_4ZT3Z |
| 6841 | 1612743349U, // LUTI6_Z2ZZ |
| 6842 | 2449539765U, // LUTI6_Z2ZZI_H |
| 6843 | 2130613U, // LUTI6_ZTZ |
| 6844 | 2122135U, // MADDPT |
| 6845 | 2116672U, // MADDWrrr |
| 6846 | 2116672U, // MADDXrrr |
| 6847 | 1612767632U, // MAD_CPA |
| 6848 | 807439261U, // MAD_ZPmZZ_B |
| 6849 | 807455645U, // MAD_ZPmZZ_D |
| 6850 | 543230877U, // MAD_ZPmZZ_H |
| 6851 | 807488413U, // MAD_ZPmZZ_S |
| 6852 | 807440119U, // MATCH_PPzZZ_B |
| 6853 | 1080102647U, // MATCH_PPzZZ_H |
| 6854 | 1612767617U, // MLA_CPA |
| 6855 | 807437158U, // MLA_ZPmZZ_B |
| 6856 | 807453542U, // MLA_ZPmZZ_D |
| 6857 | 543228774U, // MLA_ZPmZZ_H |
| 6858 | 807486310U, // MLA_ZPmZZ_S |
| 6859 | 1612759910U, // MLA_ZZZI_D |
| 6860 | 2460025702U, // MLA_ZZZI_H |
| 6861 | 1881228134U, // MLA_ZZZI_S |
| 6862 | 3229746022U, // MLAv16i8 |
| 6863 | 3231843174U, // MLAv2i32 |
| 6864 | 3231843174U, // MLAv2i32_indexed |
| 6865 | 3236037478U, // MLAv4i16 |
| 6866 | 3236037478U, // MLAv4i16_indexed |
| 6867 | 3238134630U, // MLAv4i32 |
| 6868 | 3238134630U, // MLAv4i32_indexed |
| 6869 | 3240231782U, // MLAv8i16 |
| 6870 | 3240231782U, // MLAv8i16_indexed |
| 6871 | 3242328934U, // MLAv8i8 |
| 6872 | 807443988U, // MLS_ZPmZZ_B |
| 6873 | 807460372U, // MLS_ZPmZZ_D |
| 6874 | 543235604U, // MLS_ZPmZZ_H |
| 6875 | 807493140U, // MLS_ZPmZZ_S |
| 6876 | 1612766740U, // MLS_ZZZI_D |
| 6877 | 2460032532U, // MLS_ZZZI_H |
| 6878 | 1881234964U, // MLS_ZZZI_S |
| 6879 | 3229752852U, // MLSv16i8 |
| 6880 | 3231850004U, // MLSv2i32 |
| 6881 | 3231850004U, // MLSv2i32_indexed |
| 6882 | 3236044308U, // MLSv4i16 |
| 6883 | 3236044308U, // MLSv4i16_indexed |
| 6884 | 3238141460U, // MLSv4i32 |
| 6885 | 3238141460U, // MLSv4i32_indexed |
| 6886 | 3240238612U, // MLSv8i16 |
| 6887 | 3240238612U, // MLSv8i16_indexed |
| 6888 | 3242335764U, // MLSv8i8 |
| 6889 | 4172244910U, // MOPSSETGE |
| 6890 | 4172244989U, // MOPSSETGEN |
| 6891 | 4172245949U, // MOPSSETGET |
| 6892 | 4172245380U, // MOPSSETGETN |
| 6893 | 146957698U, // MOVAZ_2ZMI_H_B |
| 6894 | 146974082U, // MOVAZ_2ZMI_H_D |
| 6895 | 146990466U, // MOVAZ_2ZMI_H_H |
| 6896 | 147006850U, // MOVAZ_2ZMI_H_S |
| 6897 | 149054850U, // MOVAZ_2ZMI_V_B |
| 6898 | 149071234U, // MOVAZ_2ZMI_V_D |
| 6899 | 149087618U, // MOVAZ_2ZMI_V_H |
| 6900 | 149104002U, // MOVAZ_2ZMI_V_S |
| 6901 | 415393154U, // MOVAZ_4ZMI_H_B |
| 6902 | 415409538U, // MOVAZ_4ZMI_H_D |
| 6903 | 415425922U, // MOVAZ_4ZMI_H_H |
| 6904 | 415442306U, // MOVAZ_4ZMI_H_S |
| 6905 | 417490306U, // MOVAZ_4ZMI_V_B |
| 6906 | 417506690U, // MOVAZ_4ZMI_V_D |
| 6907 | 417523074U, // MOVAZ_4ZMI_V_H |
| 6908 | 417539458U, // MOVAZ_4ZMI_V_S |
| 6909 | 688039298U, // MOVAZ_VG2_2ZMXI |
| 6910 | 956474754U, // MOVAZ_VG4_4ZMXI |
| 6911 | 1075881346U, // MOVAZ_ZMI_H_B |
| 6912 | 1075897730U, // MOVAZ_ZMI_H_D |
| 6913 | 2569086338U, // MOVAZ_ZMI_H_H |
| 6914 | 2569495938U, // MOVAZ_ZMI_H_Q |
| 6915 | 1075930498U, // MOVAZ_ZMI_H_S |
| 6916 | 1344316802U, // MOVAZ_ZMI_V_B |
| 6917 | 1344333186U, // MOVAZ_ZMI_V_D |
| 6918 | 2571183490U, // MOVAZ_ZMI_V_H |
| 6919 | 2571593090U, // MOVAZ_ZMI_V_Q |
| 6920 | 1344365954U, // MOVAZ_ZMI_V_S |
| 6921 | 958547263U, // MOVA_2ZMXI_H_B |
| 6922 | 958563647U, // MOVA_2ZMXI_H_D |
| 6923 | 958580031U, // MOVA_2ZMXI_H_H |
| 6924 | 958596415U, // MOVA_2ZMXI_H_S |
| 6925 | 960644415U, // MOVA_2ZMXI_V_B |
| 6926 | 960660799U, // MOVA_2ZMXI_V_D |
| 6927 | 960677183U, // MOVA_2ZMXI_V_H |
| 6928 | 960693567U, // MOVA_2ZMXI_V_S |
| 6929 | 958547263U, // MOVA_4ZMXI_H_B |
| 6930 | 958563647U, // MOVA_4ZMXI_H_D |
| 6931 | 958580031U, // MOVA_4ZMXI_H_H |
| 6932 | 958596415U, // MOVA_4ZMXI_H_S |
| 6933 | 960644415U, // MOVA_4ZMXI_V_B |
| 6934 | 960660799U, // MOVA_4ZMXI_V_D |
| 6935 | 960677183U, // MOVA_4ZMXI_V_H |
| 6936 | 960693567U, // MOVA_4ZMXI_V_S |
| 6937 | 2502427967U, // MOVA_MXI2Z_H_B |
| 6938 | 2502427967U, // MOVA_MXI2Z_H_D |
| 6939 | 2502427967U, // MOVA_MXI2Z_H_H |
| 6940 | 2502427967U, // MOVA_MXI2Z_H_S |
| 6941 | 2502444351U, // MOVA_MXI2Z_V_B |
| 6942 | 2502444351U, // MOVA_MXI2Z_V_D |
| 6943 | 2502444351U, // MOVA_MXI2Z_V_H |
| 6944 | 2502444351U, // MOVA_MXI2Z_V_S |
| 6945 | 2502427967U, // MOVA_MXI4Z_H_B |
| 6946 | 2502427967U, // MOVA_MXI4Z_H_D |
| 6947 | 2502427967U, // MOVA_MXI4Z_H_H |
| 6948 | 2502427967U, // MOVA_MXI4Z_H_S |
| 6949 | 2502444351U, // MOVA_MXI4Z_V_B |
| 6950 | 2502444351U, // MOVA_MXI4Z_V_D |
| 6951 | 2502444351U, // MOVA_MXI4Z_V_H |
| 6952 | 2502444351U, // MOVA_MXI4Z_V_S |
| 6953 | 694322495U, // MOVA_VG2_2ZMXI |
| 6954 | 4064494911U, // MOVA_VG2_MXI2Z |
| 6955 | 962757951U, // MOVA_VG4_4ZMXI |
| 6956 | 37963071U, // MOVA_VG4_MXI4Z |
| 6957 | 1612730794U, // MOVID |
| 6958 | 1887539626U, // MOVIv16b_ns |
| 6959 | 1623298474U, // MOVIv2d_ns |
| 6960 | 1889636778U, // MOVIv2i32 |
| 6961 | 1889636778U, // MOVIv2s_msl |
| 6962 | 1893831082U, // MOVIv4i16 |
| 6963 | 1895928234U, // MOVIv4i32 |
| 6964 | 1895928234U, // MOVIv4s_msl |
| 6965 | 1900122538U, // MOVIv8b_ns |
| 6966 | 1898025386U, // MOVIv8i16 |
| 6967 | 2149601731U, // MOVKWi |
| 6968 | 2149601731U, // MOVKXi |
| 6969 | 1881168035U, // MOVNWi |
| 6970 | 1881168035U, // MOVNXi |
| 6971 | 270574889U, // MOVPRFX_ZPmZ_B |
| 6972 | 270591273U, // MOVPRFX_ZPmZ_D |
| 6973 | 541140265U, // MOVPRFX_ZPmZ_H |
| 6974 | 270624041U, // MOVPRFX_ZPmZ_S |
| 6975 | 807445801U, // MOVPRFX_ZPzZ_B |
| 6976 | 807462185U, // MOVPRFX_ZPzZ_D |
| 6977 | 1080108329U, // MOVPRFX_ZPzZ_H |
| 6978 | 807494953U, // MOVPRFX_ZPzZ_S |
| 6979 | 808428841U, // MOVPRFX_ZZ |
| 6980 | 2306892294U, // MOVT_TIX |
| 6981 | 2575327750U, // MOVT_TIZ |
| 6982 | 2122246U, // MOVT_XTI |
| 6983 | 1881171392U, // MOVZWi |
| 6984 | 1881171392U, // MOVZXi |
| 6985 | 1056408U, // MRRS |
| 6986 | 2686475911U, // MRS |
| 6987 | 807438801U, // MSB_ZPmZZ_B |
| 6988 | 807455185U, // MSB_ZPmZZ_D |
| 6989 | 543230417U, // MSB_ZPmZZ_H |
| 6990 | 807487953U, // MSB_ZPmZZ_S |
| 6991 | 594566319U, // MSR |
| 6992 | 162552991U, // MSRR |
| 6993 | 1088687U, // MSRpstateImm1 |
| 6994 | 1088687U, // MSRpstateImm4 |
| 6995 | 1105071U, // MSRpstatesvcrImm1 |
| 6996 | 2122120U, // MSUBPT |
| 6997 | 2116197U, // MSUBWrrr |
| 6998 | 2116197U, // MSUBXrrr |
| 6999 | 3491796633U, // MUL_ZI_B |
| 7000 | 2686506649U, // MUL_ZI_D |
| 7001 | 2443253401U, // MUL_ZI_H |
| 7002 | 3760281241U, // MUL_ZI_S |
| 7003 | 807442073U, // MUL_ZPmZ_B |
| 7004 | 807458457U, // MUL_ZPmZ_D |
| 7005 | 543233689U, // MUL_ZPmZ_H |
| 7006 | 807491225U, // MUL_ZPmZ_S |
| 7007 | 2686506649U, // MUL_ZZZI_D |
| 7008 | 2443253401U, // MUL_ZZZI_H |
| 7009 | 3760281241U, // MUL_ZZZI_S |
| 7010 | 3491796633U, // MUL_ZZZ_B |
| 7011 | 2686506649U, // MUL_ZZZ_D |
| 7012 | 2443253401U, // MUL_ZZZ_H |
| 7013 | 3760281241U, // MUL_ZZZ_S |
| 7014 | 1350669977U, // MULv16i8 |
| 7015 | 1352767129U, // MULv2i32 |
| 7016 | 1352767129U, // MULv2i32_indexed |
| 7017 | 1356961433U, // MULv4i16 |
| 7018 | 1356961433U, // MULv4i16_indexed |
| 7019 | 1359058585U, // MULv4i32 |
| 7020 | 1359058585U, // MULv4i32_indexed |
| 7021 | 1361155737U, // MULv8i16 |
| 7022 | 1361155737U, // MULv8i16_indexed |
| 7023 | 1363252889U, // MULv8i8 |
| 7024 | 1889636759U, // MVNIv2i32 |
| 7025 | 1889636759U, // MVNIv2s_msl |
| 7026 | 1893831063U, // MVNIv4i16 |
| 7027 | 1895928215U, // MVNIv4i32 |
| 7028 | 1895928215U, // MVNIv4s_msl |
| 7029 | 1898025367U, // MVNIv8i16 |
| 7030 | 807443915U, // NANDS_PPzPP |
| 7031 | 807439468U, // NAND_PPzPP |
| 7032 | 2686506536U, // NBSL_ZZZZ |
| 7033 | 270568897U, // NEG_ZPmZ_B |
| 7034 | 270585281U, // NEG_ZPmZ_D |
| 7035 | 541134273U, // NEG_ZPmZ_H |
| 7036 | 270618049U, // NEG_ZPmZ_S |
| 7037 | 807439809U, // NEG_ZPzZ_B |
| 7038 | 807456193U, // NEG_ZPzZ_D |
| 7039 | 1080102337U, // NEG_ZPzZ_H |
| 7040 | 807488961U, // NEG_ZPzZ_S |
| 7041 | 1350667713U, // NEGv16i8 |
| 7042 | 2117057U, // NEGv1i64 |
| 7043 | 1352764865U, // NEGv2i32 |
| 7044 | 1354862017U, // NEGv2i64 |
| 7045 | 1356959169U, // NEGv4i16 |
| 7046 | 1359056321U, // NEGv4i32 |
| 7047 | 1361153473U, // NEGv8i16 |
| 7048 | 1363250625U, // NEGv8i8 |
| 7049 | 807440118U, // NMATCH_PPzZZ_B |
| 7050 | 1080102646U, // NMATCH_PPzZZ_H |
| 7051 | 9847U, // NOP |
| 7052 | 807444114U, // NORS_PPzPP |
| 7053 | 807443581U, // NOR_PPzPP |
| 7054 | 270573948U, // NOT_ZPmZ_B |
| 7055 | 270590332U, // NOT_ZPmZ_D |
| 7056 | 541139324U, // NOT_ZPmZ_H |
| 7057 | 270623100U, // NOT_ZPmZ_S |
| 7058 | 807444860U, // NOT_ZPzZ_B |
| 7059 | 807461244U, // NOT_ZPzZ_D |
| 7060 | 1080107388U, // NOT_ZPzZ_H |
| 7061 | 807494012U, // NOT_ZPzZ_S |
| 7062 | 1350672764U, // NOTv16i8 |
| 7063 | 1363255676U, // NOTv8i8 |
| 7064 | 807444027U, // ORNS_PPzPP |
| 7065 | 2119738U, // ORNWrs |
| 7066 | 2119738U, // ORNXrs |
| 7067 | 807442490U, // ORN_PPzPP |
| 7068 | 1350670394U, // ORNv16i8 |
| 7069 | 1363253306U, // ORNv8i8 |
| 7070 | 813802316U, // ORQV_VPZ_B |
| 7071 | 817996620U, // ORQV_VPZ_D |
| 7072 | 824288076U, // ORQV_VPZ_H |
| 7073 | 822190924U, // ORQV_VPZ_S |
| 7074 | 807444126U, // ORRS_PPzPP |
| 7075 | 2120846U, // ORRWri |
| 7076 | 2120846U, // ORRWrs |
| 7077 | 2120846U, // ORRXri |
| 7078 | 2120846U, // ORRXrs |
| 7079 | 807443598U, // ORR_PPzPP |
| 7080 | 2686508174U, // ORR_ZI |
| 7081 | 807443598U, // ORR_ZPmZ_B |
| 7082 | 807459982U, // ORR_ZPmZ_D |
| 7083 | 543235214U, // ORR_ZPmZ_H |
| 7084 | 807492750U, // ORR_ZPmZ_S |
| 7085 | 2686508174U, // ORR_ZZZ |
| 7086 | 1350671502U, // ORRv16i8 |
| 7087 | 2158107790U, // ORRv2i32 |
| 7088 | 2162302094U, // ORRv4i16 |
| 7089 | 2164399246U, // ORRv4i32 |
| 7090 | 2166496398U, // ORRv8i16 |
| 7091 | 1363254414U, // ORRv8i8 |
| 7092 | 254827U, // ORV_VPZ_B |
| 7093 | 579085163U, // ORV_VPZ_D |
| 7094 | 581198699U, // ORV_VPZ_H |
| 7095 | 562340715U, // ORV_VPZ_S |
| 7096 | 807715600U, // PACDA |
| 7097 | 807716515U, // PACDB |
| 7098 | 312682U, // PACDZA |
| 7099 | 314041U, // PACDZB |
| 7100 | 2114370U, // PACGA |
| 7101 | 807715664U, // PACIA |
| 7102 | 10001U, // PACIA1716 |
| 7103 | 9918U, // PACIA171615 |
| 7104 | 9966U, // PACIASP |
| 7105 | 11463U, // PACIASPPC |
| 7106 | 9909U, // PACIAZ |
| 7107 | 807716560U, // PACIB |
| 7108 | 9855U, // PACIB1716 |
| 7109 | 9942U, // PACIB171615 |
| 7110 | 9992U, // PACIBSP |
| 7111 | 11485U, // PACIBSPPC |
| 7112 | 9975U, // PACIBZ |
| 7113 | 312698U, // PACIZA |
| 7114 | 314057U, // PACIZB |
| 7115 | 10027U, // PACM |
| 7116 | 11451U, // PACNBIASPPC |
| 7117 | 11473U, // PACNBIBSPPC |
| 7118 | 631398969U, // PEXT_2PCI_B |
| 7119 | 631415353U, // PEXT_2PCI_D |
| 7120 | 631431737U, // PEXT_2PCI_H |
| 7121 | 631448121U, // PEXT_2PCI_S |
| 7122 | 2954928697U, // PEXT_PCI_B |
| 7123 | 2954945081U, // PEXT_PCI_D |
| 7124 | 631317049U, // PEXT_PCI_H |
| 7125 | 2954977849U, // PEXT_PCI_S |
| 7126 | 36185U, // PFALSE |
| 7127 | 807444928U, // PFIRST_B |
| 7128 | 2458358288U, // PMLAL_2ZZZ_Q |
| 7129 | 807445246U, // PMOV_PZI_B |
| 7130 | 807461630U, // PMOV_PZI_D |
| 7131 | 543236862U, // PMOV_PZI_H |
| 7132 | 807494398U, // PMOV_PZI_S |
| 7133 | 164602622U, // PMOV_ZIP_B |
| 7134 | 433038078U, // PMOV_ZIP_D |
| 7135 | 2043650814U, // PMOV_ZIP_H |
| 7136 | 701473534U, // PMOV_ZIP_S |
| 7137 | 3760244700U, // PMULLB_ZZZ_D |
| 7138 | 2462123996U, // PMULLB_ZZZ_H |
| 7139 | 166152156U, // PMULLB_ZZZ_Q |
| 7140 | 3760250957U, // PMULLT_ZZZ_D |
| 7141 | 2462130253U, // PMULLT_ZZZ_H |
| 7142 | 166158413U, // PMULLT_ZZZ_Q |
| 7143 | 166171832U, // PMULL_2ZZZ_Q |
| 7144 | 1361150282U, // PMULLv16i8 |
| 7145 | 3120665784U, // PMULLv1i64 |
| 7146 | 3389096266U, // PMULLv2i64 |
| 7147 | 1361155256U, // PMULLv8i8 |
| 7148 | 3491796645U, // PMUL_ZZZ_B |
| 7149 | 1350669989U, // PMULv16i8 |
| 7150 | 1363252901U, // PMULv8i8 |
| 7151 | 807445042U, // PNEXT_B |
| 7152 | 807461426U, // PNEXT_D |
| 7153 | 2422284850U, // PNEXT_H |
| 7154 | 807494194U, // PNEXT_S |
| 7155 | 2458977987U, // PRFB_D_PZI |
| 7156 | 2503018179U, // PRFB_D_SCALED |
| 7157 | 2503018179U, // PRFB_D_SXTW_SCALED |
| 7158 | 2503018179U, // PRFB_D_UXTW_SCALED |
| 7159 | 2503018179U, // PRFB_PRI |
| 7160 | 2503018179U, // PRFB_PRR |
| 7161 | 2442200771U, // PRFB_S_PZI |
| 7162 | 2503018179U, // PRFB_S_SXTW_SCALED |
| 7163 | 2503018179U, // PRFB_S_UXTW_SCALED |
| 7164 | 2458979430U, // PRFD_D_PZI |
| 7165 | 2503019622U, // PRFD_D_SCALED |
| 7166 | 2503019622U, // PRFD_D_SXTW_SCALED |
| 7167 | 2503019622U, // PRFD_D_UXTW_SCALED |
| 7168 | 2503019622U, // PRFD_PRI |
| 7169 | 2503019622U, // PRFD_PRR |
| 7170 | 2442202214U, // PRFD_S_PZI |
| 7171 | 2503019622U, // PRFD_S_SXTW_SCALED |
| 7172 | 2503019622U, // PRFD_S_UXTW_SCALED |
| 7173 | 2458980102U, // PRFH_D_PZI |
| 7174 | 2503020294U, // PRFH_D_SCALED |
| 7175 | 2503020294U, // PRFH_D_SXTW_SCALED |
| 7176 | 2503020294U, // PRFH_D_UXTW_SCALED |
| 7177 | 2503020294U, // PRFH_PRI |
| 7178 | 2503020294U, // PRFH_PRR |
| 7179 | 2442202886U, // PRFH_S_PZI |
| 7180 | 2503020294U, // PRFH_S_SXTW_SCALED |
| 7181 | 2503020294U, // PRFH_S_UXTW_SCALED |
| 7182 | 2419152667U, // PRFMl |
| 7183 | 40982299U, // PRFMroW |
| 7184 | 40982299U, // PRFMroX |
| 7185 | 40982299U, // PRFMui |
| 7186 | 40982441U, // PRFUMi |
| 7187 | 2458985506U, // PRFW_D_PZI |
| 7188 | 2503025698U, // PRFW_D_SCALED |
| 7189 | 2503025698U, // PRFW_D_SXTW_SCALED |
| 7190 | 2503025698U, // PRFW_D_UXTW_SCALED |
| 7191 | 2503025698U, // PRFW_PRI |
| 7192 | 2503025698U, // PRFW_PRR |
| 7193 | 2442208290U, // PRFW_S_PZI |
| 7194 | 2503025698U, // PRFW_S_SXTW_SCALED |
| 7195 | 2503025698U, // PRFW_S_UXTW_SCALED |
| 7196 | 808424497U, // PSEL_PPPRI_B |
| 7197 | 808424497U, // PSEL_PPPRI_D |
| 7198 | 808424497U, // PSEL_PPPRI_H |
| 7199 | 808424497U, // PSEL_PPPRI_S |
| 7200 | 3492782521U, // PTEST_PP |
| 7201 | 2954927570U, // PTRUES_B |
| 7202 | 2954943954U, // PTRUES_D |
| 7203 | 169942482U, // PTRUES_H |
| 7204 | 2954976722U, // PTRUES_S |
| 7205 | 2954923379U, // PTRUE_B |
| 7206 | 1150323U, // PTRUE_C_B |
| 7207 | 1166707U, // PTRUE_C_D |
| 7208 | 1183091U, // PTRUE_C_H |
| 7209 | 1199475U, // PTRUE_C_S |
| 7210 | 2954939763U, // PTRUE_D |
| 7211 | 169938291U, // PTRUE_H |
| 7212 | 2954972531U, // PTRUE_S |
| 7213 | 583078245U, // PUNPKHI_PP |
| 7214 | 583080128U, // PUNPKLO_PP |
| 7215 | 2149615734U, // RADDHNB_ZZZ_B |
| 7216 | 2439055478U, // RADDHNB_ZZZ_H |
| 7217 | 2686535798U, // RADDHNB_ZZZ_S |
| 7218 | 2954928339U, // RADDHNT_ZZZ_B |
| 7219 | 2441158867U, // RADDHNT_ZZZ_H |
| 7220 | 1612800211U, // RADDHNT_ZZZ_S |
| 7221 | 1352767430U, // RADDHNv2i64_v2i32 |
| 7222 | 3238134185U, // RADDHNv2i64_v4i32 |
| 7223 | 1356961734U, // RADDHNv4i32_v4i16 |
| 7224 | 3240231337U, // RADDHNv4i32_v8i16 |
| 7225 | 3229745577U, // RADDHNv8i16_v16i8 |
| 7226 | 1363253190U, // RADDHNv8i16_v8i8 |
| 7227 | 1354858657U, // RAX1 |
| 7228 | 2686501025U, // RAX1_ZZZ_D |
| 7229 | 2121585U, // RBITWr |
| 7230 | 2121585U, // RBITXr |
| 7231 | 270573425U, // RBIT_ZPmZ_B |
| 7232 | 270589809U, // RBIT_ZPmZ_D |
| 7233 | 541138801U, // RBIT_ZPmZ_H |
| 7234 | 270622577U, // RBIT_ZPmZ_S |
| 7235 | 807444337U, // RBIT_ZPzZ_B |
| 7236 | 807460721U, // RBIT_ZPzZ_D |
| 7237 | 1080106865U, // RBIT_ZPzZ_H |
| 7238 | 807493489U, // RBIT_ZPzZ_S |
| 7239 | 1350672241U, // RBITv16i8 |
| 7240 | 1363255153U, // RBITv8i8 |
| 7241 | 807722348U, // RCWCAS |
| 7242 | 807716084U, // RCWCASA |
| 7243 | 807719745U, // RCWCASAL |
| 7244 | 807720479U, // RCWCASL |
| 7245 | 399920U, // RCWCASP |
| 7246 | 394338U, // RCWCASPA |
| 7247 | 398020U, // RCWCASPAL |
| 7248 | 398758U, // RCWCASPL |
| 7249 | 3223641129U, // RCWCLR |
| 7250 | 3223635135U, // RCWCLRA |
| 7251 | 3223638819U, // RCWCLRAL |
| 7252 | 3223639556U, // RCWCLRL |
| 7253 | 2419022365U, // RCWCLRP |
| 7254 | 2419016781U, // RCWCLRPA |
| 7255 | 2419020461U, // RCWCLRPAL |
| 7256 | 2419021201U, // RCWCLRPL |
| 7257 | 3223641112U, // RCWCLRS |
| 7258 | 3223635116U, // RCWCLRSA |
| 7259 | 3223638798U, // RCWCLRSAL |
| 7260 | 3223639537U, // RCWCLRSL |
| 7261 | 2419022355U, // RCWCLRSP |
| 7262 | 2419016770U, // RCWCLRSPA |
| 7263 | 2419020449U, // RCWCLRSPAL |
| 7264 | 2419021190U, // RCWCLRSPL |
| 7265 | 807722339U, // RCWSCAS |
| 7266 | 807716074U, // RCWSCASA |
| 7267 | 807719734U, // RCWSCASAL |
| 7268 | 807720469U, // RCWSCASL |
| 7269 | 399910U, // RCWSCASP |
| 7270 | 394327U, // RCWSCASPA |
| 7271 | 398008U, // RCWSCASPAL |
| 7272 | 398747U, // RCWSCASPL |
| 7273 | 3223641911U, // RCWSET |
| 7274 | 3223635224U, // RCWSETA |
| 7275 | 3223638889U, // RCWSETAL |
| 7276 | 3223639662U, // RCWSETL |
| 7277 | 2419022423U, // RCWSETP |
| 7278 | 2419016832U, // RCWSETPA |
| 7279 | 2419020517U, // RCWSETPAL |
| 7280 | 2419021260U, // RCWSETPL |
| 7281 | 3223641894U, // RCWSETS |
| 7282 | 3223635205U, // RCWSETSA |
| 7283 | 3223638868U, // RCWSETSAL |
| 7284 | 3223639643U, // RCWSETSL |
| 7285 | 2419022413U, // RCWSETSP |
| 7286 | 2419016821U, // RCWSETSPA |
| 7287 | 2419020505U, // RCWSETSPAL |
| 7288 | 2419021249U, // RCWSETSPL |
| 7289 | 3223640722U, // RCWSWP |
| 7290 | 3223635092U, // RCWSWPA |
| 7291 | 3223638779U, // RCWSWPAL |
| 7292 | 3223639520U, // RCWSWPL |
| 7293 | 2419022319U, // RCWSWPP |
| 7294 | 2419016751U, // RCWSWPPA |
| 7295 | 2419020428U, // RCWSWPPAL |
| 7296 | 2419021171U, // RCWSWPPL |
| 7297 | 3223640713U, // RCWSWPS |
| 7298 | 3223635082U, // RCWSWPSA |
| 7299 | 3223638768U, // RCWSWPSAL |
| 7300 | 3223639510U, // RCWSWPSL |
| 7301 | 2419022309U, // RCWSWPSP |
| 7302 | 2419016740U, // RCWSWPSPA |
| 7303 | 2419020416U, // RCWSWPSPAL |
| 7304 | 2419021160U, // RCWSWPSPL |
| 7305 | 807444095U, // RDFFRS_PPz |
| 7306 | 39892U, // RDFFR_P |
| 7307 | 807443412U, // RDFFR_PPz |
| 7308 | 2119368U, // RDSVLI_XI |
| 7309 | 2119354U, // RDVLI_XI |
| 7310 | 24346U, // RET |
| 7311 | 11435U, // RETAA |
| 7312 | 330518U, // RETAASPPCi |
| 7313 | 23442U, // RETAASPPCr |
| 7314 | 11442U, // RETAB |
| 7315 | 330540U, // RETABSPPCi |
| 7316 | 23466U, // RETABSPPCr |
| 7317 | 2114222U, // REV16Wr |
| 7318 | 2114222U, // REV16Xr |
| 7319 | 1350664878U, // REV16v16i8 |
| 7320 | 1363247790U, // REV16v8i8 |
| 7321 | 2113703U, // REV32Xr |
| 7322 | 1350664359U, // REV32v16i8 |
| 7323 | 1356955815U, // REV32v4i16 |
| 7324 | 1361150119U, // REV32v8i16 |
| 7325 | 1363247271U, // REV32v8i8 |
| 7326 | 1350664846U, // REV64v16i8 |
| 7327 | 1352761998U, // REV64v2i32 |
| 7328 | 1356956302U, // REV64v4i16 |
| 7329 | 1359053454U, // REV64v4i32 |
| 7330 | 1361150606U, // REV64v8i16 |
| 7331 | 1363247758U, // REV64v8i8 |
| 7332 | 270584449U, // REVB_ZPmZ_D |
| 7333 | 541133441U, // REVB_ZPmZ_H |
| 7334 | 270617217U, // REVB_ZPmZ_S |
| 7335 | 807455361U, // REVB_ZPzZ_D |
| 7336 | 1080101505U, // REVB_ZPzZ_H |
| 7337 | 807488129U, // REVB_ZPzZ_S |
| 7338 | 541543587U, // REVD_ZPmZ |
| 7339 | 1080511651U, // REVD_ZPzZ |
| 7340 | 270586153U, // REVH_ZPmZ_D |
| 7341 | 270618921U, // REVH_ZPmZ_S |
| 7342 | 807457065U, // REVH_ZPzZ_D |
| 7343 | 807489833U, // REVH_ZPzZ_S |
| 7344 | 270591148U, // REVW_ZPmZ_D |
| 7345 | 807462060U, // REVW_ZPzZ_D |
| 7346 | 2122403U, // REVWr |
| 7347 | 2122403U, // REVXr |
| 7348 | 3491799715U, // REV_PP_B |
| 7349 | 2686509731U, // REV_PP_D |
| 7350 | 564208291U, // REV_PP_H |
| 7351 | 3760284323U, // REV_PP_S |
| 7352 | 3491799715U, // REV_ZZ_B |
| 7353 | 2686509731U, // REV_ZZ_D |
| 7354 | 564208291U, // REV_ZZ_H |
| 7355 | 3760284323U, // REV_ZZ_S |
| 7356 | 2117006U, // RMIF |
| 7357 | 2120834U, // RORVWr |
| 7358 | 2120834U, // RORVXr |
| 7359 | 1218330U, // RPRFM |
| 7360 | 2149615781U, // RSHRNB_ZZI_B |
| 7361 | 2439055525U, // RSHRNB_ZZI_H |
| 7362 | 2686535845U, // RSHRNB_ZZI_S |
| 7363 | 2954928374U, // RSHRNT_ZZI_B |
| 7364 | 2441158902U, // RSHRNT_ZZI_H |
| 7365 | 1612800246U, // RSHRNT_ZZI_S |
| 7366 | 3229745606U, // RSHRNv16i8_shift |
| 7367 | 1352767530U, // RSHRNv2i32_shift |
| 7368 | 1356961834U, // RSHRNv4i16_shift |
| 7369 | 3238134214U, // RSHRNv4i32_shift |
| 7370 | 3240231366U, // RSHRNv8i16_shift |
| 7371 | 1363253290U, // RSHRNv8i8_shift |
| 7372 | 2149615725U, // RSUBHNB_ZZZ_B |
| 7373 | 2439055469U, // RSUBHNB_ZZZ_H |
| 7374 | 2686535789U, // RSUBHNB_ZZZ_S |
| 7375 | 2954928330U, // RSUBHNT_ZZZ_B |
| 7376 | 2441158858U, // RSUBHNT_ZZZ_H |
| 7377 | 1612800202U, // RSUBHNT_ZZZ_S |
| 7378 | 1352767422U, // RSUBHNv2i64_v2i32 |
| 7379 | 3238134176U, // RSUBHNv2i64_v4i32 |
| 7380 | 1356961726U, // RSUBHNv4i32_v4i16 |
| 7381 | 3240231328U, // RSUBHNv4i32_v8i16 |
| 7382 | 3229745568U, // RSUBHNv8i16_v16i8 |
| 7383 | 1363253182U, // RSUBHNv8i16_v8i8 |
| 7384 | 1881196260U, // SABALB_ZZZ_D |
| 7385 | 2485192420U, // SABALB_ZZZ_H |
| 7386 | 2954970852U, // SABALB_ZZZ_S |
| 7387 | 1881202571U, // SABALT_ZZZ_D |
| 7388 | 2485198731U, // SABALT_ZZZ_H |
| 7389 | 2954977163U, // SABALT_ZZZ_S |
| 7390 | 2485195209U, // SABAL_ZZZ_BtoH |
| 7391 | 2954973641U, // SABAL_ZZZ_HtoS |
| 7392 | 1881199049U, // SABAL_ZZZ_StoD |
| 7393 | 3240231118U, // SABALv16i8_v8i16 |
| 7394 | 3233944009U, // SABALv2i32_v2i64 |
| 7395 | 3238138313U, // SABALv4i16_v4i32 |
| 7396 | 3233939662U, // SABALv4i32_v2i64 |
| 7397 | 3238133966U, // SABALv8i16_v4i32 |
| 7398 | 3240235465U, // SABALv8i8_v8i16 |
| 7399 | 2686485252U, // SABA_ZZZ_B |
| 7400 | 1612759812U, // SABA_ZZZ_D |
| 7401 | 2460025604U, // SABA_ZZZ_H |
| 7402 | 1881228036U, // SABA_ZZZ_S |
| 7403 | 3229745924U, // SABAv16i8 |
| 7404 | 3231843076U, // SABAv2i32 |
| 7405 | 3236037380U, // SABAv4i16 |
| 7406 | 3238134532U, // SABAv4i32 |
| 7407 | 3240231684U, // SABAv8i16 |
| 7408 | 3242328836U, // SABAv8i8 |
| 7409 | 3760244633U, // SABDLB_ZZZ_D |
| 7410 | 2462123929U, // SABDLB_ZZZ_H |
| 7411 | 2149664665U, // SABDLB_ZZZ_S |
| 7412 | 3760250867U, // SABDLT_ZZZ_D |
| 7413 | 2462130163U, // SABDLT_ZZZ_H |
| 7414 | 2149670899U, // SABDLT_ZZZ_S |
| 7415 | 1361150224U, // SABDLv16i8_v8i16 |
| 7416 | 1354863559U, // SABDLv2i32_v2i64 |
| 7417 | 1359057863U, // SABDLv4i16_v4i32 |
| 7418 | 1354858768U, // SABDLv4i32_v2i64 |
| 7419 | 1359053072U, // SABDLv8i16_v4i32 |
| 7420 | 1361155015U, // SABDLv8i8_v8i16 |
| 7421 | 807439286U, // SABD_ZPmZ_B |
| 7422 | 807455670U, // SABD_ZPmZ_D |
| 7423 | 543230902U, // SABD_ZPmZ_H |
| 7424 | 807488438U, // SABD_ZPmZ_S |
| 7425 | 1350667190U, // SABDv16i8 |
| 7426 | 1352764342U, // SABDv2i32 |
| 7427 | 1356958646U, // SABDv4i16 |
| 7428 | 1359055798U, // SABDv4i32 |
| 7429 | 1361152950U, // SABDv8i16 |
| 7430 | 1363250102U, // SABDv8i8 |
| 7431 | 807459138U, // SADALP_ZPmZ_D |
| 7432 | 543234370U, // SADALP_ZPmZ_H |
| 7433 | 807491906U, // SADALP_ZPmZ_S |
| 7434 | 3240237378U, // SADALPv16i8_v8i16 |
| 7435 | 3393329474U, // SADALPv2i32_v1i64 |
| 7436 | 3231848770U, // SADALPv4i16_v2i32 |
| 7437 | 3233945922U, // SADALPv4i32_v2i64 |
| 7438 | 3238140226U, // SADALPv8i16_v4i32 |
| 7439 | 3236043074U, // SADALPv8i8_v4i16 |
| 7440 | 3760250598U, // SADDLBT_ZZZ_D |
| 7441 | 2462129894U, // SADDLBT_ZZZ_H |
| 7442 | 2149670630U, // SADDLBT_ZZZ_S |
| 7443 | 3760244658U, // SADDLB_ZZZ_D |
| 7444 | 2462123954U, // SADDLB_ZZZ_H |
| 7445 | 2149664690U, // SADDLB_ZZZ_S |
| 7446 | 1361156434U, // SADDLPv16i8_v8i16 |
| 7447 | 1514248530U, // SADDLPv2i32_v1i64 |
| 7448 | 1352767826U, // SADDLPv4i16_v2i32 |
| 7449 | 1354864978U, // SADDLPv4i32_v2i64 |
| 7450 | 1359059282U, // SADDLPv8i16_v4i32 |
| 7451 | 1356962130U, // SADDLPv8i8_v4i16 |
| 7452 | 3760250883U, // SADDLT_ZZZ_D |
| 7453 | 2462130179U, // SADDLT_ZZZ_H |
| 7454 | 2149670915U, // SADDLT_ZZZ_S |
| 7455 | 1344299706U, // SADDLVv16i8v |
| 7456 | 1344299706U, // SADDLVv4i16v |
| 7457 | 1344299706U, // SADDLVv4i32v |
| 7458 | 1344299706U, // SADDLVv8i16v |
| 7459 | 1344299706U, // SADDLVv8i8v |
| 7460 | 1361150240U, // SADDLv16i8_v8i16 |
| 7461 | 1354863635U, // SADDLv2i32_v2i64 |
| 7462 | 1359057939U, // SADDLv4i16_v4i32 |
| 7463 | 1354858784U, // SADDLv4i32_v2i64 |
| 7464 | 1359053088U, // SADDLv8i16_v4i32 |
| 7465 | 1361155091U, // SADDLv8i8_v8i16 |
| 7466 | 606347919U, // SADDV_VPZ_B |
| 7467 | 581182095U, // SADDV_VPZ_H |
| 7468 | 562307727U, // SADDV_VPZ_S |
| 7469 | 2686503575U, // SADDWB_ZZZ_D |
| 7470 | 2443250327U, // SADDWB_ZZZ_H |
| 7471 | 3760278167U, // SADDWB_ZZZ_S |
| 7472 | 2686509596U, // SADDWT_ZZZ_D |
| 7473 | 2443256348U, // SADDWT_ZZZ_H |
| 7474 | 3760284188U, // SADDWT_ZZZ_S |
| 7475 | 1361150556U, // SADDWv16i8_v8i16 |
| 7476 | 1354867732U, // SADDWv2i32_v2i64 |
| 7477 | 1359062036U, // SADDWv4i16_v4i32 |
| 7478 | 1354859100U, // SADDWv4i32_v2i64 |
| 7479 | 1359053404U, // SADDWv8i16_v4i32 |
| 7480 | 1361159188U, // SADDWv8i8_v8i16 |
| 7481 | 11448U, // SB |
| 7482 | 1612760971U, // SBCLB_ZZZ_D |
| 7483 | 1881229195U, // SBCLB_ZZZ_S |
| 7484 | 1612767205U, // SBCLT_ZZZ_D |
| 7485 | 1881235429U, // SBCLT_ZZZ_S |
| 7486 | 2121139U, // SBCSWr |
| 7487 | 2121139U, // SBCSXr |
| 7488 | 2116320U, // SBCWr |
| 7489 | 2116320U, // SBCXr |
| 7490 | 2119438U, // SBFMWri |
| 7491 | 2119438U, // SBFMXri |
| 7492 | 2485279096U, // SCLAMP_VG2_2Z2Z_B |
| 7493 | 2458032504U, // SCLAMP_VG2_2Z2Z_D |
| 7494 | 2460146040U, // SCLAMP_VG2_2Z2Z_H |
| 7495 | 2441288056U, // SCLAMP_VG2_2Z2Z_S |
| 7496 | 2485279096U, // SCLAMP_VG4_4Z4Z_B |
| 7497 | 2458032504U, // SCLAMP_VG4_4Z4Z_D |
| 7498 | 2460146040U, // SCLAMP_VG4_4Z4Z_H |
| 7499 | 2441288056U, // SCLAMP_VG4_4Z4Z_S |
| 7500 | 2686491000U, // SCLAMP_ZZZ_B |
| 7501 | 1612765560U, // SCLAMP_ZZZ_D |
| 7502 | 2460031352U, // SCLAMP_ZZZ_H |
| 7503 | 1881233784U, // SCLAMP_ZZZ_S |
| 7504 | 2117012U, // SCVTFDSr |
| 7505 | 2117012U, // SCVTFHDr |
| 7506 | 2117012U, // SCVTFHSr |
| 7507 | 583082012U, // SCVTFLT_ZZ_BtoH |
| 7508 | 2149670940U, // SCVTFLT_ZZ_HtoS |
| 7509 | 3760250908U, // SCVTFLT_ZZ_StoD |
| 7510 | 2117012U, // SCVTFSDr |
| 7511 | 2117012U, // SCVTFSWDri |
| 7512 | 2117012U, // SCVTFSWHri |
| 7513 | 2117012U, // SCVTFSWSri |
| 7514 | 2117012U, // SCVTFSXDri |
| 7515 | 2117012U, // SCVTFSXHri |
| 7516 | 2117012U, // SCVTFSXSri |
| 7517 | 2117012U, // SCVTFUWDri |
| 7518 | 2117012U, // SCVTFUWHri |
| 7519 | 2117012U, // SCVTFUWSri |
| 7520 | 2117012U, // SCVTFUXDri |
| 7521 | 2117012U, // SCVTFUXHri |
| 7522 | 2117012U, // SCVTFUXSri |
| 7523 | 572722580U, // SCVTF_2Z2Z_StoS |
| 7524 | 572722580U, // SCVTF_4Z4Z_StoS |
| 7525 | 270585236U, // SCVTF_ZPmZ_DtoD |
| 7526 | 541134228U, // SCVTF_ZPmZ_DtoH |
| 7527 | 270618004U, // SCVTF_ZPmZ_DtoS |
| 7528 | 541134228U, // SCVTF_ZPmZ_HtoH |
| 7529 | 270585236U, // SCVTF_ZPmZ_StoD |
| 7530 | 541134228U, // SCVTF_ZPmZ_StoH |
| 7531 | 270618004U, // SCVTF_ZPmZ_StoS |
| 7532 | 807456148U, // SCVTF_ZPzZ_DtoD |
| 7533 | 1080102292U, // SCVTF_ZPzZ_DtoH |
| 7534 | 807488916U, // SCVTF_ZPzZ_DtoS |
| 7535 | 1080102292U, // SCVTF_ZPzZ_HtoH |
| 7536 | 807456148U, // SCVTF_ZPzZ_StoD |
| 7537 | 1080102292U, // SCVTF_ZPzZ_StoH |
| 7538 | 807488916U, // SCVTF_ZPzZ_StoS |
| 7539 | 583077268U, // SCVTF_ZZ_BtoH |
| 7540 | 2149666196U, // SCVTF_ZZ_HtoS |
| 7541 | 3760246164U, // SCVTF_ZZ_StoD |
| 7542 | 2117012U, // SCVTFd |
| 7543 | 2117012U, // SCVTFh |
| 7544 | 2117012U, // SCVTFs |
| 7545 | 2117012U, // SCVTFv1i16 |
| 7546 | 2117012U, // SCVTFv1i32 |
| 7547 | 2117012U, // SCVTFv1i64 |
| 7548 | 1352764820U, // SCVTFv2f32 |
| 7549 | 1354861972U, // SCVTFv2f64 |
| 7550 | 1352764820U, // SCVTFv2i32_shift |
| 7551 | 1354861972U, // SCVTFv2i64_shift |
| 7552 | 1356959124U, // SCVTFv4f16 |
| 7553 | 1359056276U, // SCVTFv4f32 |
| 7554 | 1356959124U, // SCVTFv4i16_shift |
| 7555 | 1359056276U, // SCVTFv4i32_shift |
| 7556 | 1361153428U, // SCVTFv8f16 |
| 7557 | 1361153428U, // SCVTFv8i16_shift |
| 7558 | 807460089U, // SDIVR_ZPmZ_D |
| 7559 | 807492857U, // SDIVR_ZPmZ_S |
| 7560 | 2122414U, // SDIVWr |
| 7561 | 2122414U, // SDIVXr |
| 7562 | 807461550U, // SDIV_ZPmZ_D |
| 7563 | 807494318U, // SDIV_ZPmZ_S |
| 7564 | 4064518486U, // SDOT_VG2_M2Z2Z_BtoS |
| 7565 | 4064502102U, // SDOT_VG2_M2Z2Z_HtoD |
| 7566 | 4064518486U, // SDOT_VG2_M2Z2Z_HtoS |
| 7567 | 4064518486U, // SDOT_VG2_M2ZZI_BToS |
| 7568 | 4064518486U, // SDOT_VG2_M2ZZI_HToS |
| 7569 | 4064502102U, // SDOT_VG2_M2ZZI_HtoD |
| 7570 | 4064518486U, // SDOT_VG2_M2ZZ_BtoS |
| 7571 | 4064502102U, // SDOT_VG2_M2ZZ_HtoD |
| 7572 | 4064518486U, // SDOT_VG2_M2ZZ_HtoS |
| 7573 | 37986646U, // SDOT_VG4_M4Z4Z_BtoS |
| 7574 | 37970262U, // SDOT_VG4_M4Z4Z_HtoD |
| 7575 | 37986646U, // SDOT_VG4_M4Z4Z_HtoS |
| 7576 | 37986646U, // SDOT_VG4_M4ZZI_BToS |
| 7577 | 37986646U, // SDOT_VG4_M4ZZI_HToS |
| 7578 | 37970262U, // SDOT_VG4_M4ZZI_HtoD |
| 7579 | 37986646U, // SDOT_VG4_M4ZZ_BtoS |
| 7580 | 37970262U, // SDOT_VG4_M4ZZ_HtoD |
| 7581 | 37986646U, // SDOT_VG4_M4ZZ_HtoS |
| 7582 | 2485199190U, // SDOT_ZZZI_BtoH |
| 7583 | 2686542166U, // SDOT_ZZZI_BtoS |
| 7584 | 2954944854U, // SDOT_ZZZI_HtoD |
| 7585 | 2954977622U, // SDOT_ZZZI_HtoS |
| 7586 | 2485199190U, // SDOT_ZZZ_BtoH |
| 7587 | 2686542166U, // SDOT_ZZZ_BtoS |
| 7588 | 2954944854U, // SDOT_ZZZ_HtoD |
| 7589 | 2954977622U, // SDOT_ZZZ_HtoS |
| 7590 | 3238142294U, // SDOTlanev16i8 |
| 7591 | 3231850838U, // SDOTlanev8i8 |
| 7592 | 3238142294U, // SDOTv16i8 |
| 7593 | 3231850838U, // SDOTv8i8 |
| 7594 | 807441452U, // SEL_PPPP |
| 7595 | 2510443564U, // SEL_VG2_2ZC2Z2Z_B |
| 7596 | 2510459948U, // SEL_VG2_2ZC2Z2Z_D |
| 7597 | 2510476332U, // SEL_VG2_2ZC2Z2Z_H |
| 7598 | 2510492716U, // SEL_VG2_2ZC2Z2Z_S |
| 7599 | 2510443564U, // SEL_VG4_4ZC4Z4Z_B |
| 7600 | 2510459948U, // SEL_VG4_4ZC4Z4Z_D |
| 7601 | 2510476332U, // SEL_VG4_4ZC4Z4Z_H |
| 7602 | 2510492716U, // SEL_VG4_4ZC4Z4Z_S |
| 7603 | 807441452U, // SEL_ZPZZ_B |
| 7604 | 807457836U, // SEL_ZPZZ_D |
| 7605 | 2422281260U, // SEL_ZPZZ_H |
| 7606 | 807490604U, // SEL_ZPZZ_S |
| 7607 | 4172244927U, // SETE |
| 7608 | 4172245008U, // SETEN |
| 7609 | 4172245968U, // SETET |
| 7610 | 4172245401U, // SETETN |
| 7611 | 17062U, // SETF16 |
| 7612 | 17084U, // SETF8 |
| 7613 | 11546U, // SETFFR |
| 7614 | 4172244949U, // SETGM |
| 7615 | 4172245033U, // SETGMN |
| 7616 | 4172245993U, // SETGMT |
| 7617 | 4172245429U, // SETGMTN |
| 7618 | 3635374006U, // SETGOE |
| 7619 | 3635374086U, // SETGOEN |
| 7620 | 3635375046U, // SETGOET |
| 7621 | 3635374478U, // SETGOETN |
| 7622 | 3635374045U, // SETGOM |
| 7623 | 3635374130U, // SETGOMN |
| 7624 | 3635375090U, // SETGOMT |
| 7625 | 3635374527U, // SETGOMTN |
| 7626 | 3635375005U, // SETGOP |
| 7627 | 3635374174U, // SETGOPN |
| 7628 | 3635375134U, // SETGOPT |
| 7629 | 3635374576U, // SETGOPTN |
| 7630 | 4172245909U, // SETGP |
| 7631 | 4172245077U, // SETGPN |
| 7632 | 4172246037U, // SETGPT |
| 7633 | 4172245478U, // SETGPTN |
| 7634 | 4172244966U, // SETM |
| 7635 | 4172245052U, // SETMN |
| 7636 | 4172246012U, // SETMT |
| 7637 | 4172245450U, // SETMTN |
| 7638 | 4172245926U, // SETP |
| 7639 | 4172245096U, // SETPN |
| 7640 | 4172246056U, // SETPT |
| 7641 | 4172245499U, // SETPTN |
| 7642 | 807717593U, // SHA1Crrr |
| 7643 | 2117101U, // SHA1Hrr |
| 7644 | 807720711U, // SHA1Mrrr |
| 7645 | 807721199U, // SHA1Prrr |
| 7646 | 3238133761U, // SHA1SU0rrr |
| 7647 | 3238133879U, // SHA1SU1rr |
| 7648 | 807715005U, // SHA256H2rrr |
| 7649 | 807718485U, // SHA256Hrrr |
| 7650 | 3238133781U, // SHA256SU0rr |
| 7651 | 3238133899U, // SHA256SU1rrr |
| 7652 | 807718432U, // SHA512H |
| 7653 | 807714995U, // SHA512H2 |
| 7654 | 3233939466U, // SHA512SU0 |
| 7655 | 3233939584U, // SHA512SU1 |
| 7656 | 807439409U, // SHADD_ZPmZ_B |
| 7657 | 807455793U, // SHADD_ZPmZ_D |
| 7658 | 543231025U, // SHADD_ZPmZ_H |
| 7659 | 807488561U, // SHADD_ZPmZ_S |
| 7660 | 1350667313U, // SHADDv16i8 |
| 7661 | 1352764465U, // SHADDv2i32 |
| 7662 | 1356958769U, // SHADDv4i16 |
| 7663 | 1359055921U, // SHADDv4i32 |
| 7664 | 1361153073U, // SHADDv8i16 |
| 7665 | 1363250225U, // SHADDv8i8 |
| 7666 | 1361150257U, // SHLLv16i8 |
| 7667 | 1354863762U, // SHLLv2i32 |
| 7668 | 1359058066U, // SHLLv4i16 |
| 7669 | 1354858801U, // SHLLv4i32 |
| 7670 | 1359053105U, // SHLLv8i16 |
| 7671 | 1361155218U, // SHLLv8i8 |
| 7672 | 2118721U, // SHLd |
| 7673 | 1350669377U, // SHLv16i8_shift |
| 7674 | 1352766529U, // SHLv2i32_shift |
| 7675 | 1354863681U, // SHLv2i64_shift |
| 7676 | 1356960833U, // SHLv4i16_shift |
| 7677 | 1359057985U, // SHLv4i32_shift |
| 7678 | 1361155137U, // SHLv8i16_shift |
| 7679 | 1363252289U, // SHLv8i8_shift |
| 7680 | 2149615763U, // SHRNB_ZZI_B |
| 7681 | 2439055507U, // SHRNB_ZZI_H |
| 7682 | 2686535827U, // SHRNB_ZZI_S |
| 7683 | 2954928356U, // SHRNT_ZZI_B |
| 7684 | 2441158884U, // SHRNT_ZZI_H |
| 7685 | 1612800228U, // SHRNT_ZZI_S |
| 7686 | 3229745588U, // SHRNv16i8_shift |
| 7687 | 1352767514U, // SHRNv2i32_shift |
| 7688 | 1356961818U, // SHRNv4i16_shift |
| 7689 | 3238134196U, // SHRNv4i32_shift |
| 7690 | 3240231348U, // SHRNv8i16_shift |
| 7691 | 1363253274U, // SHRNv8i8_shift |
| 7692 | 807443314U, // SHSUBR_ZPmZ_B |
| 7693 | 807459698U, // SHSUBR_ZPmZ_D |
| 7694 | 543234930U, // SHSUBR_ZPmZ_H |
| 7695 | 807492466U, // SHSUBR_ZPmZ_S |
| 7696 | 807438934U, // SHSUB_ZPmZ_B |
| 7697 | 807455318U, // SHSUB_ZPmZ_D |
| 7698 | 543230550U, // SHSUB_ZPmZ_H |
| 7699 | 807488086U, // SHSUB_ZPmZ_S |
| 7700 | 1350666838U, // SHSUBv16i8 |
| 7701 | 1352763990U, // SHSUBv2i32 |
| 7702 | 1356958294U, // SHSUBv4i16 |
| 7703 | 1359055446U, // SHSUBv4i32 |
| 7704 | 1361152598U, // SHSUBv8i16 |
| 7705 | 1363249750U, // SHSUBv8i8 |
| 7706 | 1233187U, // SHUH |
| 7707 | 2686488973U, // SLI_ZZI_B |
| 7708 | 1612763533U, // SLI_ZZI_D |
| 7709 | 2460029325U, // SLI_ZZI_H |
| 7710 | 1881231757U, // SLI_ZZI_S |
| 7711 | 807719309U, // SLId |
| 7712 | 3229749645U, // SLIv16i8_shift |
| 7713 | 3231846797U, // SLIv2i32_shift |
| 7714 | 3233943949U, // SLIv2i64_shift |
| 7715 | 3236041101U, // SLIv4i16_shift |
| 7716 | 3238138253U, // SLIv4i32_shift |
| 7717 | 3240235405U, // SLIv8i16_shift |
| 7718 | 3242332557U, // SLIv8i8_shift |
| 7719 | 3238133910U, // SM3PARTW1 |
| 7720 | 3238134380U, // SM3PARTW2 |
| 7721 | 1359052898U, // SM3SS1 |
| 7722 | 3238134467U, // SM3TT1A |
| 7723 | 3238135222U, // SM3TT1B |
| 7724 | 3238134476U, // SM3TT2A |
| 7725 | 3238135251U, // SM3TT2B |
| 7726 | 3238137001U, // SM4E |
| 7727 | 3760285008U, // SM4EKEY_ZZZ_S |
| 7728 | 1359062352U, // SM4ENCKEY |
| 7729 | 3760278697U, // SM4E_ZZZ_S |
| 7730 | 2118659U, // SMADDLrrr |
| 7731 | 807443112U, // SMAXP_ZPmZ_B |
| 7732 | 807459496U, // SMAXP_ZPmZ_D |
| 7733 | 543234728U, // SMAXP_ZPmZ_H |
| 7734 | 807492264U, // SMAXP_ZPmZ_S |
| 7735 | 1350671016U, // SMAXPv16i8 |
| 7736 | 1352768168U, // SMAXPv2i32 |
| 7737 | 1356962472U, // SMAXPv4i16 |
| 7738 | 1359059624U, // SMAXPv4i32 |
| 7739 | 1361156776U, // SMAXPv8i16 |
| 7740 | 1363253928U, // SMAXPv8i8 |
| 7741 | 813802330U, // SMAXQV_VPZ_B |
| 7742 | 817996634U, // SMAXQV_VPZ_D |
| 7743 | 824288090U, // SMAXQV_VPZ_H |
| 7744 | 822190938U, // SMAXQV_VPZ_S |
| 7745 | 254839U, // SMAXV_VPZ_B |
| 7746 | 579085175U, // SMAXV_VPZ_D |
| 7747 | 581198711U, // SMAXV_VPZ_H |
| 7748 | 562340727U, // SMAXV_VPZ_S |
| 7749 | 1344299895U, // SMAXVv16i8v |
| 7750 | 1344299895U, // SMAXVv4i16v |
| 7751 | 1344299895U, // SMAXVv4i32v |
| 7752 | 1344299895U, // SMAXVv8i16v |
| 7753 | 1344299895U, // SMAXVv8i8v |
| 7754 | 2123007U, // SMAXWri |
| 7755 | 2123007U, // SMAXWrr |
| 7756 | 2123007U, // SMAXXri |
| 7757 | 2123007U, // SMAXXrr |
| 7758 | 2445436159U, // SMAX_VG2_2Z2Z_B |
| 7759 | 2447549695U, // SMAX_VG2_2Z2Z_D |
| 7760 | 2449663231U, // SMAX_VG2_2Z2Z_H |
| 7761 | 2451776767U, // SMAX_VG2_2Z2Z_S |
| 7762 | 2445436159U, // SMAX_VG2_2ZZ_B |
| 7763 | 2447549695U, // SMAX_VG2_2ZZ_D |
| 7764 | 2449663231U, // SMAX_VG2_2ZZ_H |
| 7765 | 2451776767U, // SMAX_VG2_2ZZ_S |
| 7766 | 2445436159U, // SMAX_VG4_4Z4Z_B |
| 7767 | 2447549695U, // SMAX_VG4_4Z4Z_D |
| 7768 | 2449663231U, // SMAX_VG4_4Z4Z_H |
| 7769 | 2451776767U, // SMAX_VG4_4Z4Z_S |
| 7770 | 2445436159U, // SMAX_VG4_4ZZ_B |
| 7771 | 2447549695U, // SMAX_VG4_4ZZ_D |
| 7772 | 2449663231U, // SMAX_VG4_4ZZ_H |
| 7773 | 2451776767U, // SMAX_VG4_4ZZ_S |
| 7774 | 3491800319U, // SMAX_ZI_B |
| 7775 | 2686510335U, // SMAX_ZI_D |
| 7776 | 2443257087U, // SMAX_ZI_H |
| 7777 | 3760284927U, // SMAX_ZI_S |
| 7778 | 807445759U, // SMAX_ZPmZ_B |
| 7779 | 807462143U, // SMAX_ZPmZ_D |
| 7780 | 543237375U, // SMAX_ZPmZ_H |
| 7781 | 807494911U, // SMAX_ZPmZ_S |
| 7782 | 1350673663U, // SMAXv16i8 |
| 7783 | 1352770815U, // SMAXv2i32 |
| 7784 | 1356965119U, // SMAXv4i16 |
| 7785 | 1359062271U, // SMAXv4i32 |
| 7786 | 1361159423U, // SMAXv8i16 |
| 7787 | 1363256575U, // SMAXv8i8 |
| 7788 | 379658U, // SMC |
| 7789 | 807442868U, // SMINP_ZPmZ_B |
| 7790 | 807459252U, // SMINP_ZPmZ_D |
| 7791 | 543234484U, // SMINP_ZPmZ_H |
| 7792 | 807492020U, // SMINP_ZPmZ_S |
| 7793 | 1350670772U, // SMINPv16i8 |
| 7794 | 1352767924U, // SMINPv2i32 |
| 7795 | 1356962228U, // SMINPv4i16 |
| 7796 | 1359059380U, // SMINPv4i32 |
| 7797 | 1361156532U, // SMINPv8i16 |
| 7798 | 1363253684U, // SMINPv8i8 |
| 7799 | 813802299U, // SMINQV_VPZ_B |
| 7800 | 817996603U, // SMINQV_VPZ_D |
| 7801 | 824288059U, // SMINQV_VPZ_H |
| 7802 | 822190907U, // SMINQV_VPZ_S |
| 7803 | 254691U, // SMINV_VPZ_B |
| 7804 | 579085027U, // SMINV_VPZ_D |
| 7805 | 581198563U, // SMINV_VPZ_H |
| 7806 | 562340579U, // SMINV_VPZ_S |
| 7807 | 1344299747U, // SMINVv16i8v |
| 7808 | 1344299747U, // SMINVv4i16v |
| 7809 | 1344299747U, // SMINVv4i32v |
| 7810 | 1344299747U, // SMINVv8i16v |
| 7811 | 1344299747U, // SMINVv8i8v |
| 7812 | 2119673U, // SMINWri |
| 7813 | 2119673U, // SMINWrr |
| 7814 | 2119673U, // SMINXri |
| 7815 | 2119673U, // SMINXrr |
| 7816 | 2445432825U, // SMIN_VG2_2Z2Z_B |
| 7817 | 2447546361U, // SMIN_VG2_2Z2Z_D |
| 7818 | 2449659897U, // SMIN_VG2_2Z2Z_H |
| 7819 | 2451773433U, // SMIN_VG2_2Z2Z_S |
| 7820 | 2445432825U, // SMIN_VG2_2ZZ_B |
| 7821 | 2447546361U, // SMIN_VG2_2ZZ_D |
| 7822 | 2449659897U, // SMIN_VG2_2ZZ_H |
| 7823 | 2451773433U, // SMIN_VG2_2ZZ_S |
| 7824 | 2445432825U, // SMIN_VG4_4Z4Z_B |
| 7825 | 2447546361U, // SMIN_VG4_4Z4Z_D |
| 7826 | 2449659897U, // SMIN_VG4_4Z4Z_H |
| 7827 | 2451773433U, // SMIN_VG4_4Z4Z_S |
| 7828 | 2445432825U, // SMIN_VG4_4ZZ_B |
| 7829 | 2447546361U, // SMIN_VG4_4ZZ_D |
| 7830 | 2449659897U, // SMIN_VG4_4ZZ_H |
| 7831 | 2451773433U, // SMIN_VG4_4ZZ_S |
| 7832 | 3491796985U, // SMIN_ZI_B |
| 7833 | 2686507001U, // SMIN_ZI_D |
| 7834 | 2443253753U, // SMIN_ZI_H |
| 7835 | 3760281593U, // SMIN_ZI_S |
| 7836 | 807442425U, // SMIN_ZPmZ_B |
| 7837 | 807458809U, // SMIN_ZPmZ_D |
| 7838 | 543234041U, // SMIN_ZPmZ_H |
| 7839 | 807491577U, // SMIN_ZPmZ_S |
| 7840 | 1350670329U, // SMINv16i8 |
| 7841 | 1352767481U, // SMINv2i32 |
| 7842 | 1356961785U, // SMINv4i16 |
| 7843 | 1359058937U, // SMINv4i32 |
| 7844 | 1361156089U, // SMINv8i16 |
| 7845 | 1363253241U, // SMINv8i8 |
| 7846 | 1881196305U, // SMLALB_ZZZI_D |
| 7847 | 2954970897U, // SMLALB_ZZZI_S |
| 7848 | 1881196305U, // SMLALB_ZZZ_D |
| 7849 | 2485192465U, // SMLALB_ZZZ_H |
| 7850 | 2954970897U, // SMLALB_ZZZ_S |
| 7851 | 1415812224U, // SMLALL_MZZI_BtoS |
| 7852 | 1415795840U, // SMLALL_MZZI_HtoD |
| 7853 | 1415812224U, // SMLALL_MZZ_BtoS |
| 7854 | 1415795840U, // SMLALL_MZZ_HtoD |
| 7855 | 4100166784U, // SMLALL_VG2_M2Z2Z_BtoS |
| 7856 | 4100150400U, // SMLALL_VG2_M2Z2Z_HtoD |
| 7857 | 4100166784U, // SMLALL_VG2_M2ZZI_BtoS |
| 7858 | 4100150400U, // SMLALL_VG2_M2ZZI_HtoD |
| 7859 | 3026424960U, // SMLALL_VG2_M2ZZ_BtoS |
| 7860 | 3026408576U, // SMLALL_VG2_M2ZZ_HtoD |
| 7861 | 73634944U, // SMLALL_VG4_M4Z4Z_BtoS |
| 7862 | 73618560U, // SMLALL_VG4_M4Z4Z_HtoD |
| 7863 | 73634944U, // SMLALL_VG4_M4ZZI_BtoS |
| 7864 | 73618560U, // SMLALL_VG4_M4ZZI_HtoD |
| 7865 | 3294860416U, // SMLALL_VG4_M4ZZ_BtoS |
| 7866 | 3294844032U, // SMLALL_VG4_M4ZZ_HtoD |
| 7867 | 1881202606U, // SMLALT_ZZZI_D |
| 7868 | 2954977198U, // SMLALT_ZZZI_S |
| 7869 | 1881202606U, // SMLALT_ZZZ_D |
| 7870 | 2485198766U, // SMLALT_ZZZ_H |
| 7871 | 2954977198U, // SMLALT_ZZZ_S |
| 7872 | 1390645783U, // SMLAL_MZZI_HtoS |
| 7873 | 1390645783U, // SMLAL_MZZ_HtoS |
| 7874 | 4075000343U, // SMLAL_VG2_M2Z2Z_HtoS |
| 7875 | 4075000343U, // SMLAL_VG2_M2ZZI_S |
| 7876 | 4075000343U, // SMLAL_VG2_M2ZZ_HtoS |
| 7877 | 48468503U, // SMLAL_VG4_M4Z4Z_HtoS |
| 7878 | 48468503U, // SMLAL_VG4_M4ZZI_HtoS |
| 7879 | 48468503U, // SMLAL_VG4_M4ZZ_HtoS |
| 7880 | 3240231152U, // SMLALv16i8_v8i16 |
| 7881 | 3233944087U, // SMLALv2i32_indexed |
| 7882 | 3233944087U, // SMLALv2i32_v2i64 |
| 7883 | 3238138391U, // SMLALv4i16_indexed |
| 7884 | 3238138391U, // SMLALv4i16_v4i32 |
| 7885 | 3233939696U, // SMLALv4i32_indexed |
| 7886 | 3233939696U, // SMLALv4i32_v2i64 |
| 7887 | 3238134000U, // SMLALv8i16_indexed |
| 7888 | 3238134000U, // SMLALv8i16_v4i32 |
| 7889 | 3240235543U, // SMLALv8i8_v8i16 |
| 7890 | 1881196603U, // SMLSLB_ZZZI_D |
| 7891 | 2954971195U, // SMLSLB_ZZZI_S |
| 7892 | 1881196603U, // SMLSLB_ZZZ_D |
| 7893 | 2485192763U, // SMLSLB_ZZZ_H |
| 7894 | 2954971195U, // SMLSLB_ZZZ_S |
| 7895 | 1415812255U, // SMLSLL_MZZI_BtoS |
| 7896 | 1415795871U, // SMLSLL_MZZI_HtoD |
| 7897 | 1415812255U, // SMLSLL_MZZ_BtoS |
| 7898 | 1415795871U, // SMLSLL_MZZ_HtoD |
| 7899 | 4100166815U, // SMLSLL_VG2_M2Z2Z_BtoS |
| 7900 | 4100150431U, // SMLSLL_VG2_M2Z2Z_HtoD |
| 7901 | 4100166815U, // SMLSLL_VG2_M2ZZI_BtoS |
| 7902 | 4100150431U, // SMLSLL_VG2_M2ZZI_HtoD |
| 7903 | 3026424991U, // SMLSLL_VG2_M2ZZ_BtoS |
| 7904 | 3026408607U, // SMLSLL_VG2_M2ZZ_HtoD |
| 7905 | 73634975U, // SMLSLL_VG4_M4Z4Z_BtoS |
| 7906 | 73618591U, // SMLSLL_VG4_M4Z4Z_HtoD |
| 7907 | 73634975U, // SMLSLL_VG4_M4ZZI_BtoS |
| 7908 | 73618591U, // SMLSLL_VG4_M4ZZI_HtoD |
| 7909 | 3294860447U, // SMLSLL_VG4_M4ZZ_BtoS |
| 7910 | 3294844063U, // SMLSLL_VG4_M4ZZ_HtoD |
| 7911 | 1881202837U, // SMLSLT_ZZZI_D |
| 7912 | 2954977429U, // SMLSLT_ZZZI_S |
| 7913 | 1881202837U, // SMLSLT_ZZZ_D |
| 7914 | 2485198997U, // SMLSLT_ZZZ_H |
| 7915 | 2954977429U, // SMLSLT_ZZZ_S |
| 7916 | 1390646847U, // SMLSL_MZZI_HtoS |
| 7917 | 1390646847U, // SMLSL_MZZ_HtoS |
| 7918 | 4075001407U, // SMLSL_VG2_M2Z2Z_HtoS |
| 7919 | 4075001407U, // SMLSL_VG2_M2ZZI_S |
| 7920 | 4075001407U, // SMLSL_VG2_M2ZZ_HtoS |
| 7921 | 48469567U, // SMLSL_VG4_M4Z4Z_HtoS |
| 7922 | 48469567U, // SMLSL_VG4_M4ZZI_HtoS |
| 7923 | 48469567U, // SMLSL_VG4_M4ZZ_HtoS |
| 7924 | 3240231284U, // SMLSLv16i8_v8i16 |
| 7925 | 3233945151U, // SMLSLv2i32_indexed |
| 7926 | 3233945151U, // SMLSLv2i32_v2i64 |
| 7927 | 3238139455U, // SMLSLv4i16_indexed |
| 7928 | 3238139455U, // SMLSLv4i16_v4i32 |
| 7929 | 3233939828U, // SMLSLv4i32_indexed |
| 7930 | 3233939828U, // SMLSLv4i32_v2i64 |
| 7931 | 3238134132U, // SMLSLv8i16_indexed |
| 7932 | 3238134132U, // SMLSLv8i16_v4i32 |
| 7933 | 3240236607U, // SMLSLv8i8_v8i16 |
| 7934 | 3238134651U, // SMMLA |
| 7935 | 2686534523U, // SMMLA_ZZZ |
| 7936 | 3565273823U, // SMOP4A_M2Z2Z_BToS |
| 7937 | 1661059807U, // SMOP4A_M2Z2Z_HToS |
| 7938 | 1661059807U, // SMOP4A_M2Z2Z_HtoD |
| 7939 | 75612895U, // SMOP4A_M2ZZ_BToS |
| 7940 | 1929495263U, // SMOP4A_M2ZZ_HToS |
| 7941 | 1929495263U, // SMOP4A_M2ZZ_HtoD |
| 7942 | 2485240543U, // SMOP4A_MZ2Z_BToS |
| 7943 | 2460074719U, // SMOP4A_MZ2Z_HToS |
| 7944 | 2460074719U, // SMOP4A_MZ2Z_HtoD |
| 7945 | 2485240543U, // SMOP4A_MZZ_BToS |
| 7946 | 2460074719U, // SMOP4A_MZZ_HToS |
| 7947 | 2460074719U, // SMOP4A_MZZ_HtoD |
| 7948 | 3565280594U, // SMOP4S_M2Z2Z_BToS |
| 7949 | 1661066578U, // SMOP4S_M2Z2Z_HToS |
| 7950 | 1661066578U, // SMOP4S_M2Z2Z_HtoD |
| 7951 | 75619666U, // SMOP4S_M2ZZ_BToS |
| 7952 | 1929502034U, // SMOP4S_M2ZZ_HToS |
| 7953 | 1929502034U, // SMOP4S_M2ZZ_HtoD |
| 7954 | 2485247314U, // SMOP4S_MZ2Z_BToS |
| 7955 | 2460081490U, // SMOP4S_MZ2Z_HToS |
| 7956 | 2460081490U, // SMOP4S_MZ2Z_HtoD |
| 7957 | 2485247314U, // SMOP4S_MZZ_BToS |
| 7958 | 2460081490U, // SMOP4S_MZZ_HToS |
| 7959 | 2460081490U, // SMOP4S_MZZ_HtoD |
| 7960 | 541180922U, // SMOPA_MPPZZ_D |
| 7961 | 541180922U, // SMOPA_MPPZZ_HtoS |
| 7962 | 541180922U, // SMOPA_MPPZZ_S |
| 7963 | 541187688U, // SMOPS_MPPZZ_D |
| 7964 | 541187688U, // SMOPS_MPPZZ_HtoS |
| 7965 | 541187688U, // SMOPS_MPPZZ_S |
| 7966 | 1344299780U, // SMOVvi16to32 |
| 7967 | 1344299780U, // SMOVvi16to32_idx0 |
| 7968 | 1344299780U, // SMOVvi16to64 |
| 7969 | 1344299780U, // SMOVvi16to64_idx0 |
| 7970 | 1344299780U, // SMOVvi32to64 |
| 7971 | 1344299780U, // SMOVvi32to64_idx0 |
| 7972 | 1344299780U, // SMOVvi8to32 |
| 7973 | 1344299780U, // SMOVvi8to32_idx0 |
| 7974 | 1344299780U, // SMOVvi8to64 |
| 7975 | 1344299780U, // SMOVvi8to64_idx0 |
| 7976 | 2118569U, // SMSUBLrrr |
| 7977 | 807440336U, // SMULH_ZPmZ_B |
| 7978 | 807456720U, // SMULH_ZPmZ_D |
| 7979 | 543231952U, // SMULH_ZPmZ_H |
| 7980 | 807489488U, // SMULH_ZPmZ_S |
| 7981 | 3491794896U, // SMULH_ZZZ_B |
| 7982 | 2686504912U, // SMULH_ZZZ_D |
| 7983 | 2443251664U, // SMULH_ZZZ_H |
| 7984 | 3760279504U, // SMULH_ZZZ_S |
| 7985 | 2117584U, // SMULHrr |
| 7986 | 3760244708U, // SMULLB_ZZZI_D |
| 7987 | 2149664740U, // SMULLB_ZZZI_S |
| 7988 | 3760244708U, // SMULLB_ZZZ_D |
| 7989 | 2462124004U, // SMULLB_ZZZ_H |
| 7990 | 2149664740U, // SMULLB_ZZZ_S |
| 7991 | 3760250965U, // SMULLT_ZZZI_D |
| 7992 | 2149670997U, // SMULLT_ZZZI_S |
| 7993 | 3760250965U, // SMULLT_ZZZ_D |
| 7994 | 2462130261U, // SMULLT_ZZZ_H |
| 7995 | 2149670997U, // SMULLT_ZZZ_S |
| 7996 | 1361150290U, // SMULLv16i8_v8i16 |
| 7997 | 1354863807U, // SMULLv2i32_indexed |
| 7998 | 1354863807U, // SMULLv2i32_v2i64 |
| 7999 | 1359058111U, // SMULLv4i16_indexed |
| 8000 | 1359058111U, // SMULLv4i16_v4i32 |
| 8001 | 1354858834U, // SMULLv4i32_indexed |
| 8002 | 1354858834U, // SMULLv4i32_v2i64 |
| 8003 | 1359053138U, // SMULLv8i16_indexed |
| 8004 | 1359053138U, // SMULLv8i16_v4i32 |
| 8005 | 1361155263U, // SMULLv8i8_v8i16 |
| 8006 | 807439535U, // SPLICE_ZPZZ_B |
| 8007 | 807455919U, // SPLICE_ZPZZ_D |
| 8008 | 2422279343U, // SPLICE_ZPZZ_H |
| 8009 | 807488687U, // SPLICE_ZPZZ_S |
| 8010 | 807439535U, // SPLICE_ZPZ_B |
| 8011 | 807455919U, // SPLICE_ZPZ_D |
| 8012 | 2422279343U, // SPLICE_ZPZ_H |
| 8013 | 807488687U, // SPLICE_ZPZ_S |
| 8014 | 270572951U, // SQABS_ZPmZ_B |
| 8015 | 270589335U, // SQABS_ZPmZ_D |
| 8016 | 541138327U, // SQABS_ZPmZ_H |
| 8017 | 270622103U, // SQABS_ZPmZ_S |
| 8018 | 807443863U, // SQABS_ZPzZ_B |
| 8019 | 807460247U, // SQABS_ZPzZ_D |
| 8020 | 1080106391U, // SQABS_ZPzZ_H |
| 8021 | 807493015U, // SQABS_ZPzZ_S |
| 8022 | 1350671767U, // SQABSv16i8 |
| 8023 | 2121111U, // SQABSv1i16 |
| 8024 | 2121111U, // SQABSv1i32 |
| 8025 | 2121111U, // SQABSv1i64 |
| 8026 | 2121111U, // SQABSv1i8 |
| 8027 | 1352768919U, // SQABSv2i32 |
| 8028 | 1354866071U, // SQABSv2i64 |
| 8029 | 1356963223U, // SQABSv4i16 |
| 8030 | 1359060375U, // SQABSv4i32 |
| 8031 | 1361157527U, // SQABSv8i16 |
| 8032 | 1363254679U, // SQABSv8i8 |
| 8033 | 3491793999U, // SQADD_ZI_B |
| 8034 | 2686504015U, // SQADD_ZI_D |
| 8035 | 2443250767U, // SQADD_ZI_H |
| 8036 | 3760278607U, // SQADD_ZI_S |
| 8037 | 807439439U, // SQADD_ZPmZ_B |
| 8038 | 807455823U, // SQADD_ZPmZ_D |
| 8039 | 543231055U, // SQADD_ZPmZ_H |
| 8040 | 807488591U, // SQADD_ZPmZ_S |
| 8041 | 3491793999U, // SQADD_ZZZ_B |
| 8042 | 2686504015U, // SQADD_ZZZ_D |
| 8043 | 2443250767U, // SQADD_ZZZ_H |
| 8044 | 3760278607U, // SQADD_ZZZ_S |
| 8045 | 1350667343U, // SQADDv16i8 |
| 8046 | 2116687U, // SQADDv1i16 |
| 8047 | 2116687U, // SQADDv1i32 |
| 8048 | 2116687U, // SQADDv1i64 |
| 8049 | 2116687U, // SQADDv1i8 |
| 8050 | 1352764495U, // SQADDv2i32 |
| 8051 | 1354861647U, // SQADDv2i64 |
| 8052 | 1356958799U, // SQADDv4i16 |
| 8053 | 1359055951U, // SQADDv4i32 |
| 8054 | 1361153103U, // SQADDv8i16 |
| 8055 | 1363250255U, // SQADDv8i8 |
| 8056 | 3491793904U, // SQCADD_ZZI_B |
| 8057 | 2686503920U, // SQCADD_ZZI_D |
| 8058 | 2443250672U, // SQCADD_ZZI_H |
| 8059 | 3760278512U, // SQCADD_ZZI_S |
| 8060 | 572594264U, // SQCVTN_Z2Z_StoH |
| 8061 | 568399960U, // SQCVTN_Z4Z_DtoH |
| 8062 | 1881184344U, // SQCVTN_Z4Z_StoB |
| 8063 | 572594313U, // SQCVTUN_Z2Z_StoH |
| 8064 | 568400009U, // SQCVTUN_Z4Z_DtoH |
| 8065 | 1881184393U, // SQCVTUN_Z4Z_StoB |
| 8066 | 572596848U, // SQCVTU_Z2Z_StoH |
| 8067 | 568402544U, // SQCVTU_Z4Z_DtoH |
| 8068 | 1881186928U, // SQCVTU_Z4Z_StoB |
| 8069 | 572596728U, // SQCVT_Z2Z_StoH |
| 8070 | 568402424U, // SQCVT_Z4Z_DtoH |
| 8071 | 1881186808U, // SQCVT_Z4Z_StoB |
| 8072 | 2115203U, // SQDECB_XPiI |
| 8073 | 3760211587U, // SQDECB_XPiWdI |
| 8074 | 2116553U, // SQDECD_XPiI |
| 8075 | 3760212937U, // SQDECD_XPiWdI |
| 8076 | 2149321U, // SQDECD_ZPiI |
| 8077 | 2117334U, // SQDECH_XPiI |
| 8078 | 3760213718U, // SQDECH_XPiWdI |
| 8079 | 52498134U, // SQDECH_ZPiI |
| 8080 | 3491780869U, // SQDECP_XPWd_B |
| 8081 | 2686474501U, // SQDECP_XPWd_D |
| 8082 | 2149603589U, // SQDECP_XPWd_H |
| 8083 | 3760216325U, // SQDECP_XPWd_S |
| 8084 | 3491780869U, // SQDECP_XP_B |
| 8085 | 2686474501U, // SQDECP_XP_D |
| 8086 | 2149603589U, // SQDECP_XP_H |
| 8087 | 3760216325U, // SQDECP_XP_S |
| 8088 | 1612765445U, // SQDECP_ZP_D |
| 8089 | 580983045U, // SQDECP_ZP_H |
| 8090 | 1881233669U, // SQDECP_ZP_S |
| 8091 | 2122740U, // SQDECW_XPiI |
| 8092 | 3760219124U, // SQDECW_XPiWdI |
| 8093 | 2188276U, // SQDECW_ZPiI |
| 8094 | 1881202386U, // SQDMLALBT_ZZZ_D |
| 8095 | 2485198546U, // SQDMLALBT_ZZZ_H |
| 8096 | 2954976978U, // SQDMLALBT_ZZZ_S |
| 8097 | 1881196286U, // SQDMLALB_ZZZI_D |
| 8098 | 2954970878U, // SQDMLALB_ZZZI_S |
| 8099 | 1881196286U, // SQDMLALB_ZZZ_D |
| 8100 | 2485192446U, // SQDMLALB_ZZZ_H |
| 8101 | 2954970878U, // SQDMLALB_ZZZ_S |
| 8102 | 1881202587U, // SQDMLALT_ZZZI_D |
| 8103 | 2954977179U, // SQDMLALT_ZZZI_S |
| 8104 | 1881202587U, // SQDMLALT_ZZZ_D |
| 8105 | 2485198747U, // SQDMLALT_ZZZ_H |
| 8106 | 2954977179U, // SQDMLALT_ZZZ_S |
| 8107 | 807719423U, // SQDMLALi16 |
| 8108 | 807719423U, // SQDMLALi32 |
| 8109 | 807719423U, // SQDMLALv1i32_indexed |
| 8110 | 807719423U, // SQDMLALv1i64_indexed |
| 8111 | 3233944063U, // SQDMLALv2i32_indexed |
| 8112 | 3233944063U, // SQDMLALv2i32_v2i64 |
| 8113 | 3238138367U, // SQDMLALv4i16_indexed |
| 8114 | 3238138367U, // SQDMLALv4i16_v4i32 |
| 8115 | 3233939678U, // SQDMLALv4i32_indexed |
| 8116 | 3233939678U, // SQDMLALv4i32_v2i64 |
| 8117 | 3238133982U, // SQDMLALv8i16_indexed |
| 8118 | 3238133982U, // SQDMLALv8i16_v4i32 |
| 8119 | 1881202425U, // SQDMLSLBT_ZZZ_D |
| 8120 | 2485198585U, // SQDMLSLBT_ZZZ_H |
| 8121 | 2954977017U, // SQDMLSLBT_ZZZ_S |
| 8122 | 1881196584U, // SQDMLSLB_ZZZI_D |
| 8123 | 2954971176U, // SQDMLSLB_ZZZI_S |
| 8124 | 1881196584U, // SQDMLSLB_ZZZ_D |
| 8125 | 2485192744U, // SQDMLSLB_ZZZ_H |
| 8126 | 2954971176U, // SQDMLSLB_ZZZ_S |
| 8127 | 1881202818U, // SQDMLSLT_ZZZI_D |
| 8128 | 2954977410U, // SQDMLSLT_ZZZI_S |
| 8129 | 1881202818U, // SQDMLSLT_ZZZ_D |
| 8130 | 2485198978U, // SQDMLSLT_ZZZ_H |
| 8131 | 2954977410U, // SQDMLSLT_ZZZ_S |
| 8132 | 807720494U, // SQDMLSLi16 |
| 8133 | 807720494U, // SQDMLSLi32 |
| 8134 | 807720494U, // SQDMLSLv1i32_indexed |
| 8135 | 807720494U, // SQDMLSLv1i64_indexed |
| 8136 | 3233945134U, // SQDMLSLv2i32_indexed |
| 8137 | 3233945134U, // SQDMLSLv2i32_v2i64 |
| 8138 | 3238139438U, // SQDMLSLv4i16_indexed |
| 8139 | 3238139438U, // SQDMLSLv4i16_v4i32 |
| 8140 | 3233939810U, // SQDMLSLv4i32_indexed |
| 8141 | 3233939810U, // SQDMLSLv4i32_v2i64 |
| 8142 | 3238134114U, // SQDMLSLv8i16_indexed |
| 8143 | 3238134114U, // SQDMLSLv8i16_v4i32 |
| 8144 | 2445430717U, // SQDMULH_VG2_2Z2Z_B |
| 8145 | 2447544253U, // SQDMULH_VG2_2Z2Z_D |
| 8146 | 2449657789U, // SQDMULH_VG2_2Z2Z_H |
| 8147 | 2451771325U, // SQDMULH_VG2_2Z2Z_S |
| 8148 | 2445430717U, // SQDMULH_VG2_2ZZ_B |
| 8149 | 2447544253U, // SQDMULH_VG2_2ZZ_D |
| 8150 | 2449657789U, // SQDMULH_VG2_2ZZ_H |
| 8151 | 2451771325U, // SQDMULH_VG2_2ZZ_S |
| 8152 | 2445430717U, // SQDMULH_VG4_4Z4Z_B |
| 8153 | 2447544253U, // SQDMULH_VG4_4Z4Z_D |
| 8154 | 2449657789U, // SQDMULH_VG4_4Z4Z_H |
| 8155 | 2451771325U, // SQDMULH_VG4_4Z4Z_S |
| 8156 | 2445430717U, // SQDMULH_VG4_4ZZ_B |
| 8157 | 2447544253U, // SQDMULH_VG4_4ZZ_D |
| 8158 | 2449657789U, // SQDMULH_VG4_4ZZ_H |
| 8159 | 2451771325U, // SQDMULH_VG4_4ZZ_S |
| 8160 | 2686504893U, // SQDMULH_ZZZI_D |
| 8161 | 2443251645U, // SQDMULH_ZZZI_H |
| 8162 | 3760279485U, // SQDMULH_ZZZI_S |
| 8163 | 3491794877U, // SQDMULH_ZZZ_B |
| 8164 | 2686504893U, // SQDMULH_ZZZ_D |
| 8165 | 2443251645U, // SQDMULH_ZZZ_H |
| 8166 | 3760279485U, // SQDMULH_ZZZ_S |
| 8167 | 2117565U, // SQDMULHv1i16 |
| 8168 | 2117565U, // SQDMULHv1i16_indexed |
| 8169 | 2117565U, // SQDMULHv1i32 |
| 8170 | 2117565U, // SQDMULHv1i32_indexed |
| 8171 | 1352765373U, // SQDMULHv2i32 |
| 8172 | 1352765373U, // SQDMULHv2i32_indexed |
| 8173 | 1356959677U, // SQDMULHv4i16 |
| 8174 | 1356959677U, // SQDMULHv4i16_indexed |
| 8175 | 1359056829U, // SQDMULHv4i32 |
| 8176 | 1359056829U, // SQDMULHv4i32_indexed |
| 8177 | 1361153981U, // SQDMULHv8i16 |
| 8178 | 1361153981U, // SQDMULHv8i16_indexed |
| 8179 | 3760244690U, // SQDMULLB_ZZZI_D |
| 8180 | 2149664722U, // SQDMULLB_ZZZI_S |
| 8181 | 3760244690U, // SQDMULLB_ZZZ_D |
| 8182 | 2462123986U, // SQDMULLB_ZZZ_H |
| 8183 | 2149664722U, // SQDMULLB_ZZZ_S |
| 8184 | 3760250947U, // SQDMULLT_ZZZI_D |
| 8185 | 2149670979U, // SQDMULLT_ZZZI_S |
| 8186 | 3760250947U, // SQDMULLT_ZZZ_D |
| 8187 | 2462130243U, // SQDMULLT_ZZZ_H |
| 8188 | 2149670979U, // SQDMULLT_ZZZ_S |
| 8189 | 2118831U, // SQDMULLi16 |
| 8190 | 2118831U, // SQDMULLi32 |
| 8191 | 2118831U, // SQDMULLv1i32_indexed |
| 8192 | 2118831U, // SQDMULLv1i64_indexed |
| 8193 | 1354863791U, // SQDMULLv2i32_indexed |
| 8194 | 1354863791U, // SQDMULLv2i32_v2i64 |
| 8195 | 1359058095U, // SQDMULLv4i16_indexed |
| 8196 | 1359058095U, // SQDMULLv4i16_v4i32 |
| 8197 | 1354858816U, // SQDMULLv4i32_indexed |
| 8198 | 1354858816U, // SQDMULLv4i32_v2i64 |
| 8199 | 1359053120U, // SQDMULLv8i16_indexed |
| 8200 | 1359053120U, // SQDMULLv8i16_v4i32 |
| 8201 | 2115219U, // SQINCB_XPiI |
| 8202 | 3760211603U, // SQINCB_XPiWdI |
| 8203 | 2116569U, // SQINCD_XPiI |
| 8204 | 3760212953U, // SQINCD_XPiWdI |
| 8205 | 2149337U, // SQINCD_ZPiI |
| 8206 | 2117350U, // SQINCH_XPiI |
| 8207 | 3760213734U, // SQINCH_XPiWdI |
| 8208 | 52498150U, // SQINCH_ZPiI |
| 8209 | 3491780885U, // SQINCP_XPWd_B |
| 8210 | 2686474517U, // SQINCP_XPWd_D |
| 8211 | 2149603605U, // SQINCP_XPWd_H |
| 8212 | 3760216341U, // SQINCP_XPWd_S |
| 8213 | 3491780885U, // SQINCP_XP_B |
| 8214 | 2686474517U, // SQINCP_XP_D |
| 8215 | 2149603605U, // SQINCP_XP_H |
| 8216 | 3760216341U, // SQINCP_XP_S |
| 8217 | 1612765461U, // SQINCP_ZP_D |
| 8218 | 580983061U, // SQINCP_ZP_H |
| 8219 | 1881233685U, // SQINCP_ZP_S |
| 8220 | 2122756U, // SQINCW_XPiI |
| 8221 | 3760219140U, // SQINCW_XPiWdI |
| 8222 | 2188292U, // SQINCW_ZPiI |
| 8223 | 270568902U, // SQNEG_ZPmZ_B |
| 8224 | 270585286U, // SQNEG_ZPmZ_D |
| 8225 | 541134278U, // SQNEG_ZPmZ_H |
| 8226 | 270618054U, // SQNEG_ZPmZ_S |
| 8227 | 807439814U, // SQNEG_ZPzZ_B |
| 8228 | 807456198U, // SQNEG_ZPzZ_D |
| 8229 | 1080102342U, // SQNEG_ZPzZ_H |
| 8230 | 807488966U, // SQNEG_ZPzZ_S |
| 8231 | 1350667718U, // SQNEGv16i8 |
| 8232 | 2117062U, // SQNEGv1i16 |
| 8233 | 2117062U, // SQNEGv1i32 |
| 8234 | 2117062U, // SQNEGv1i64 |
| 8235 | 2117062U, // SQNEGv1i8 |
| 8236 | 1352764870U, // SQNEGv2i32 |
| 8237 | 1354862022U, // SQNEGv2i64 |
| 8238 | 1356959174U, // SQNEGv4i16 |
| 8239 | 1359056326U, // SQNEGv4i32 |
| 8240 | 1361153478U, // SQNEGv8i16 |
| 8241 | 1363250630U, // SQNEGv8i8 |
| 8242 | 2460028519U, // SQRDCMLAH_ZZZI_H |
| 8243 | 1881230951U, // SQRDCMLAH_ZZZI_S |
| 8244 | 2686488167U, // SQRDCMLAH_ZZZ_B |
| 8245 | 1612762727U, // SQRDCMLAH_ZZZ_D |
| 8246 | 2460028519U, // SQRDCMLAH_ZZZ_H |
| 8247 | 1881230951U, // SQRDCMLAH_ZZZ_S |
| 8248 | 1612762738U, // SQRDMLAH_ZZZI_D |
| 8249 | 2460028530U, // SQRDMLAH_ZZZI_H |
| 8250 | 1881230962U, // SQRDMLAH_ZZZI_S |
| 8251 | 2686488178U, // SQRDMLAH_ZZZ_B |
| 8252 | 1612762738U, // SQRDMLAH_ZZZ_D |
| 8253 | 2460028530U, // SQRDMLAH_ZZZ_H |
| 8254 | 1881230962U, // SQRDMLAH_ZZZ_S |
| 8255 | 807718514U, // SQRDMLAHv1i16 |
| 8256 | 807718514U, // SQRDMLAHv1i16_indexed |
| 8257 | 807718514U, // SQRDMLAHv1i32 |
| 8258 | 807718514U, // SQRDMLAHv1i32_indexed |
| 8259 | 3231846002U, // SQRDMLAHv2i32 |
| 8260 | 3231846002U, // SQRDMLAHv2i32_indexed |
| 8261 | 3236040306U, // SQRDMLAHv4i16 |
| 8262 | 3236040306U, // SQRDMLAHv4i16_indexed |
| 8263 | 3238137458U, // SQRDMLAHv4i32 |
| 8264 | 3238137458U, // SQRDMLAHv4i32_indexed |
| 8265 | 3240234610U, // SQRDMLAHv8i16 |
| 8266 | 3240234610U, // SQRDMLAHv8i16_indexed |
| 8267 | 1612763350U, // SQRDMLSH_ZZZI_D |
| 8268 | 2460029142U, // SQRDMLSH_ZZZI_H |
| 8269 | 1881231574U, // SQRDMLSH_ZZZI_S |
| 8270 | 2686488790U, // SQRDMLSH_ZZZ_B |
| 8271 | 1612763350U, // SQRDMLSH_ZZZ_D |
| 8272 | 2460029142U, // SQRDMLSH_ZZZ_H |
| 8273 | 1881231574U, // SQRDMLSH_ZZZ_S |
| 8274 | 807719126U, // SQRDMLSHv1i16 |
| 8275 | 807719126U, // SQRDMLSHv1i16_indexed |
| 8276 | 807719126U, // SQRDMLSHv1i32 |
| 8277 | 807719126U, // SQRDMLSHv1i32_indexed |
| 8278 | 3231846614U, // SQRDMLSHv2i32 |
| 8279 | 3231846614U, // SQRDMLSHv2i32_indexed |
| 8280 | 3236040918U, // SQRDMLSHv4i16 |
| 8281 | 3236040918U, // SQRDMLSHv4i16_indexed |
| 8282 | 3238138070U, // SQRDMLSHv4i32 |
| 8283 | 3238138070U, // SQRDMLSHv4i32_indexed |
| 8284 | 3240235222U, // SQRDMLSHv8i16 |
| 8285 | 3240235222U, // SQRDMLSHv8i16_indexed |
| 8286 | 2686504902U, // SQRDMULH_ZZZI_D |
| 8287 | 2443251654U, // SQRDMULH_ZZZI_H |
| 8288 | 3760279494U, // SQRDMULH_ZZZI_S |
| 8289 | 3491794886U, // SQRDMULH_ZZZ_B |
| 8290 | 2686504902U, // SQRDMULH_ZZZ_D |
| 8291 | 2443251654U, // SQRDMULH_ZZZ_H |
| 8292 | 3760279494U, // SQRDMULH_ZZZ_S |
| 8293 | 2117574U, // SQRDMULHv1i16 |
| 8294 | 2117574U, // SQRDMULHv1i16_indexed |
| 8295 | 2117574U, // SQRDMULHv1i32 |
| 8296 | 2117574U, // SQRDMULHv1i32_indexed |
| 8297 | 1352765382U, // SQRDMULHv2i32 |
| 8298 | 1352765382U, // SQRDMULHv2i32_indexed |
| 8299 | 1356959686U, // SQRDMULHv4i16 |
| 8300 | 1356959686U, // SQRDMULHv4i16_indexed |
| 8301 | 1359056838U, // SQRDMULHv4i32 |
| 8302 | 1359056838U, // SQRDMULHv4i32_indexed |
| 8303 | 1361153990U, // SQRDMULHv8i16 |
| 8304 | 1361153990U, // SQRDMULHv8i16_indexed |
| 8305 | 807443521U, // SQRSHLR_ZPmZ_B |
| 8306 | 807459905U, // SQRSHLR_ZPmZ_D |
| 8307 | 543235137U, // SQRSHLR_ZPmZ_H |
| 8308 | 807492673U, // SQRSHLR_ZPmZ_S |
| 8309 | 807441485U, // SQRSHL_ZPmZ_B |
| 8310 | 807457869U, // SQRSHL_ZPmZ_D |
| 8311 | 543233101U, // SQRSHL_ZPmZ_H |
| 8312 | 807490637U, // SQRSHL_ZPmZ_S |
| 8313 | 1350669389U, // SQRSHLv16i8 |
| 8314 | 2118733U, // SQRSHLv1i16 |
| 8315 | 2118733U, // SQRSHLv1i32 |
| 8316 | 2118733U, // SQRSHLv1i64 |
| 8317 | 2118733U, // SQRSHLv1i8 |
| 8318 | 1352766541U, // SQRSHLv2i32 |
| 8319 | 1354863693U, // SQRSHLv2i64 |
| 8320 | 1356960845U, // SQRSHLv4i16 |
| 8321 | 1359057997U, // SQRSHLv4i32 |
| 8322 | 1361155149U, // SQRSHLv8i16 |
| 8323 | 1363252301U, // SQRSHLv8i8 |
| 8324 | 2149615779U, // SQRSHRNB_ZZI_B |
| 8325 | 2439055523U, // SQRSHRNB_ZZI_H |
| 8326 | 2686535843U, // SQRSHRNB_ZZI_S |
| 8327 | 2954928372U, // SQRSHRNT_ZZI_B |
| 8328 | 2441158900U, // SQRSHRNT_ZZI_H |
| 8329 | 1612800244U, // SQRSHRNT_ZZI_S |
| 8330 | 1881184296U, // SQRSHRN_VG4_Z4ZI_B |
| 8331 | 2447448104U, // SQRSHRN_VG4_Z4ZI_H |
| 8332 | 1075877928U, // SQRSHRN_Z2ZI_HtoB |
| 8333 | 2451642408U, // SQRSHRN_Z2ZI_StoH |
| 8334 | 2119720U, // SQRSHRNb |
| 8335 | 2119720U, // SQRSHRNh |
| 8336 | 2119720U, // SQRSHRNs |
| 8337 | 3229745604U, // SQRSHRNv16i8_shift |
| 8338 | 1352767528U, // SQRSHRNv2i32_shift |
| 8339 | 1356961832U, // SQRSHRNv4i16_shift |
| 8340 | 3238134212U, // SQRSHRNv4i32_shift |
| 8341 | 3240231364U, // SQRSHRNv8i16_shift |
| 8342 | 1363253288U, // SQRSHRNv8i8_shift |
| 8343 | 2149615833U, // SQRSHRUNB_ZZI_B |
| 8344 | 2439055577U, // SQRSHRUNB_ZZI_H |
| 8345 | 2686535897U, // SQRSHRUNB_ZZI_S |
| 8346 | 2954928427U, // SQRSHRUNT_ZZI_B |
| 8347 | 2441158955U, // SQRSHRUNT_ZZI_H |
| 8348 | 1612800299U, // SQRSHRUNT_ZZI_S |
| 8349 | 1881184383U, // SQRSHRUN_VG4_Z4ZI_B |
| 8350 | 2447448191U, // SQRSHRUN_VG4_Z4ZI_H |
| 8351 | 1075878015U, // SQRSHRUN_Z2ZI_HtoB |
| 8352 | 2451642495U, // SQRSHRUN_Z2ZI_StoH |
| 8353 | 2119807U, // SQRSHRUNb |
| 8354 | 2119807U, // SQRSHRUNh |
| 8355 | 2119807U, // SQRSHRUNs |
| 8356 | 3229745665U, // SQRSHRUNv16i8_shift |
| 8357 | 1352767615U, // SQRSHRUNv2i32_shift |
| 8358 | 1356961919U, // SQRSHRUNv4i16_shift |
| 8359 | 3238134273U, // SQRSHRUNv4i32_shift |
| 8360 | 3240231425U, // SQRSHRUNv8i16_shift |
| 8361 | 1363253375U, // SQRSHRUNv8i8_shift |
| 8362 | 2451645031U, // SQRSHRU_VG2_Z2ZI_H |
| 8363 | 1881186919U, // SQRSHRU_VG4_Z4ZI_B |
| 8364 | 2447450727U, // SQRSHRU_VG4_Z4ZI_H |
| 8365 | 2451643362U, // SQRSHR_VG2_Z2ZI_H |
| 8366 | 1881185250U, // SQRSHR_VG4_Z4ZI_B |
| 8367 | 2447449058U, // SQRSHR_VG4_Z4ZI_H |
| 8368 | 807443505U, // SQSHLR_ZPmZ_B |
| 8369 | 807459889U, // SQSHLR_ZPmZ_D |
| 8370 | 543235121U, // SQSHLR_ZPmZ_H |
| 8371 | 807492657U, // SQSHLR_ZPmZ_S |
| 8372 | 807445063U, // SQSHLU_ZPmI_B |
| 8373 | 807461447U, // SQSHLU_ZPmI_D |
| 8374 | 543236679U, // SQSHLU_ZPmI_H |
| 8375 | 807494215U, // SQSHLU_ZPmI_S |
| 8376 | 2122311U, // SQSHLUb |
| 8377 | 2122311U, // SQSHLUd |
| 8378 | 2122311U, // SQSHLUh |
| 8379 | 2122311U, // SQSHLUs |
| 8380 | 1350672967U, // SQSHLUv16i8_shift |
| 8381 | 1352770119U, // SQSHLUv2i32_shift |
| 8382 | 1354867271U, // SQSHLUv2i64_shift |
| 8383 | 1356964423U, // SQSHLUv4i16_shift |
| 8384 | 1359061575U, // SQSHLUv4i32_shift |
| 8385 | 1361158727U, // SQSHLUv8i16_shift |
| 8386 | 1363255879U, // SQSHLUv8i8_shift |
| 8387 | 807441471U, // SQSHL_ZPmI_B |
| 8388 | 807457855U, // SQSHL_ZPmI_D |
| 8389 | 543233087U, // SQSHL_ZPmI_H |
| 8390 | 807490623U, // SQSHL_ZPmI_S |
| 8391 | 807441471U, // SQSHL_ZPmZ_B |
| 8392 | 807457855U, // SQSHL_ZPmZ_D |
| 8393 | 543233087U, // SQSHL_ZPmZ_H |
| 8394 | 807490623U, // SQSHL_ZPmZ_S |
| 8395 | 2118719U, // SQSHLb |
| 8396 | 2118719U, // SQSHLd |
| 8397 | 2118719U, // SQSHLh |
| 8398 | 2118719U, // SQSHLs |
| 8399 | 1350669375U, // SQSHLv16i8 |
| 8400 | 1350669375U, // SQSHLv16i8_shift |
| 8401 | 2118719U, // SQSHLv1i16 |
| 8402 | 2118719U, // SQSHLv1i32 |
| 8403 | 2118719U, // SQSHLv1i64 |
| 8404 | 2118719U, // SQSHLv1i8 |
| 8405 | 1352766527U, // SQSHLv2i32 |
| 8406 | 1352766527U, // SQSHLv2i32_shift |
| 8407 | 1354863679U, // SQSHLv2i64 |
| 8408 | 1354863679U, // SQSHLv2i64_shift |
| 8409 | 1356960831U, // SQSHLv4i16 |
| 8410 | 1356960831U, // SQSHLv4i16_shift |
| 8411 | 1359057983U, // SQSHLv4i32 |
| 8412 | 1359057983U, // SQSHLv4i32_shift |
| 8413 | 1361155135U, // SQSHLv8i16 |
| 8414 | 1361155135U, // SQSHLv8i16_shift |
| 8415 | 1363252287U, // SQSHLv8i8 |
| 8416 | 1363252287U, // SQSHLv8i8_shift |
| 8417 | 2149615761U, // SQSHRNB_ZZI_B |
| 8418 | 2439055505U, // SQSHRNB_ZZI_H |
| 8419 | 2686535825U, // SQSHRNB_ZZI_S |
| 8420 | 2954928354U, // SQSHRNT_ZZI_B |
| 8421 | 2441158882U, // SQSHRNT_ZZI_H |
| 8422 | 1612800226U, // SQSHRNT_ZZI_S |
| 8423 | 1075877912U, // SQSHRN_Z2ZI_HtoB |
| 8424 | 2451642392U, // SQSHRN_Z2ZI_StoH |
| 8425 | 2119704U, // SQSHRNb |
| 8426 | 2119704U, // SQSHRNh |
| 8427 | 2119704U, // SQSHRNs |
| 8428 | 3229745586U, // SQSHRNv16i8_shift |
| 8429 | 1352767512U, // SQSHRNv2i32_shift |
| 8430 | 1356961816U, // SQSHRNv4i16_shift |
| 8431 | 3238134194U, // SQSHRNv4i32_shift |
| 8432 | 3240231346U, // SQSHRNv8i16_shift |
| 8433 | 1363253272U, // SQSHRNv8i8_shift |
| 8434 | 2149615823U, // SQSHRUNB_ZZI_B |
| 8435 | 2439055567U, // SQSHRUNB_ZZI_H |
| 8436 | 2686535887U, // SQSHRUNB_ZZI_S |
| 8437 | 2954928417U, // SQSHRUNT_ZZI_B |
| 8438 | 2441158945U, // SQSHRUNT_ZZI_H |
| 8439 | 1612800289U, // SQSHRUNT_ZZI_S |
| 8440 | 1075878006U, // SQSHRUN_Z2ZI_HtoB |
| 8441 | 2451642486U, // SQSHRUN_Z2ZI_StoH |
| 8442 | 2119798U, // SQSHRUNb |
| 8443 | 2119798U, // SQSHRUNh |
| 8444 | 2119798U, // SQSHRUNs |
| 8445 | 3229745655U, // SQSHRUNv16i8_shift |
| 8446 | 1352767606U, // SQSHRUNv2i32_shift |
| 8447 | 1356961910U, // SQSHRUNv4i16_shift |
| 8448 | 3238134263U, // SQSHRUNv4i32_shift |
| 8449 | 3240231415U, // SQSHRUNv8i16_shift |
| 8450 | 1363253366U, // SQSHRUNv8i8_shift |
| 8451 | 807443330U, // SQSUBR_ZPmZ_B |
| 8452 | 807459714U, // SQSUBR_ZPmZ_D |
| 8453 | 543234946U, // SQSUBR_ZPmZ_H |
| 8454 | 807492482U, // SQSUBR_ZPmZ_S |
| 8455 | 3491793523U, // SQSUB_ZI_B |
| 8456 | 2686503539U, // SQSUB_ZI_D |
| 8457 | 2443250291U, // SQSUB_ZI_H |
| 8458 | 3760278131U, // SQSUB_ZI_S |
| 8459 | 807438963U, // SQSUB_ZPmZ_B |
| 8460 | 807455347U, // SQSUB_ZPmZ_D |
| 8461 | 543230579U, // SQSUB_ZPmZ_H |
| 8462 | 807488115U, // SQSUB_ZPmZ_S |
| 8463 | 3491793523U, // SQSUB_ZZZ_B |
| 8464 | 2686503539U, // SQSUB_ZZZ_D |
| 8465 | 2443250291U, // SQSUB_ZZZ_H |
| 8466 | 3760278131U, // SQSUB_ZZZ_S |
| 8467 | 1350666867U, // SQSUBv16i8 |
| 8468 | 2116211U, // SQSUBv1i16 |
| 8469 | 2116211U, // SQSUBv1i32 |
| 8470 | 2116211U, // SQSUBv1i64 |
| 8471 | 2116211U, // SQSUBv1i8 |
| 8472 | 1352764019U, // SQSUBv2i32 |
| 8473 | 1354861171U, // SQSUBv2i64 |
| 8474 | 1356958323U, // SQSUBv4i16 |
| 8475 | 1359055475U, // SQSUBv4i32 |
| 8476 | 1361152627U, // SQSUBv8i16 |
| 8477 | 1363249779U, // SQSUBv8i8 |
| 8478 | 2149615807U, // SQXTNB_ZZ_B |
| 8479 | 560007359U, // SQXTNB_ZZ_H |
| 8480 | 2686535871U, // SQXTNB_ZZ_S |
| 8481 | 2954928401U, // SQXTNT_ZZ_B |
| 8482 | 562110737U, // SQXTNT_ZZ_H |
| 8483 | 1612800273U, // SQXTNT_ZZ_S |
| 8484 | 3229745639U, // SQXTNv16i8 |
| 8485 | 2119784U, // SQXTNv1i16 |
| 8486 | 2119784U, // SQXTNv1i32 |
| 8487 | 2119784U, // SQXTNv1i8 |
| 8488 | 1352767592U, // SQXTNv2i32 |
| 8489 | 1356961896U, // SQXTNv4i16 |
| 8490 | 3238134247U, // SQXTNv4i32 |
| 8491 | 3240231399U, // SQXTNv8i16 |
| 8492 | 1363253352U, // SQXTNv8i8 |
| 8493 | 2149615844U, // SQXTUNB_ZZ_B |
| 8494 | 560007396U, // SQXTUNB_ZZ_H |
| 8495 | 2686535908U, // SQXTUNB_ZZ_S |
| 8496 | 2954928438U, // SQXTUNT_ZZ_B |
| 8497 | 562110774U, // SQXTUNT_ZZ_H |
| 8498 | 1612800310U, // SQXTUNT_ZZ_S |
| 8499 | 3229745676U, // SQXTUNv16i8 |
| 8500 | 2119826U, // SQXTUNv1i16 |
| 8501 | 2119826U, // SQXTUNv1i32 |
| 8502 | 2119826U, // SQXTUNv1i8 |
| 8503 | 1352767634U, // SQXTUNv2i32 |
| 8504 | 1356961938U, // SQXTUNv4i16 |
| 8505 | 3238134284U, // SQXTUNv4i32 |
| 8506 | 3240231436U, // SQXTUNv8i16 |
| 8507 | 1363253394U, // SQXTUNv8i8 |
| 8508 | 807439393U, // SRHADD_ZPmZ_B |
| 8509 | 807455777U, // SRHADD_ZPmZ_D |
| 8510 | 543231009U, // SRHADD_ZPmZ_H |
| 8511 | 807488545U, // SRHADD_ZPmZ_S |
| 8512 | 1350667297U, // SRHADDv16i8 |
| 8513 | 1352764449U, // SRHADDv2i32 |
| 8514 | 1356958753U, // SRHADDv4i16 |
| 8515 | 1359055905U, // SRHADDv4i32 |
| 8516 | 1361153057U, // SRHADDv8i16 |
| 8517 | 1363250209U, // SRHADDv8i8 |
| 8518 | 2686488989U, // SRI_ZZI_B |
| 8519 | 1612763549U, // SRI_ZZI_D |
| 8520 | 2460029341U, // SRI_ZZI_H |
| 8521 | 1881231773U, // SRI_ZZI_S |
| 8522 | 807719325U, // SRId |
| 8523 | 3229749661U, // SRIv16i8_shift |
| 8524 | 3231846813U, // SRIv2i32_shift |
| 8525 | 3233943965U, // SRIv2i64_shift |
| 8526 | 3236041117U, // SRIv4i16_shift |
| 8527 | 3238138269U, // SRIv4i32_shift |
| 8528 | 3240235421U, // SRIv8i16_shift |
| 8529 | 3242332573U, // SRIv8i8_shift |
| 8530 | 807443539U, // SRSHLR_ZPmZ_B |
| 8531 | 807459923U, // SRSHLR_ZPmZ_D |
| 8532 | 543235155U, // SRSHLR_ZPmZ_H |
| 8533 | 807492691U, // SRSHLR_ZPmZ_S |
| 8534 | 2445431901U, // SRSHL_VG2_2Z2Z_B |
| 8535 | 2447545437U, // SRSHL_VG2_2Z2Z_D |
| 8536 | 2449658973U, // SRSHL_VG2_2Z2Z_H |
| 8537 | 2451772509U, // SRSHL_VG2_2Z2Z_S |
| 8538 | 2445431901U, // SRSHL_VG2_2ZZ_B |
| 8539 | 2447545437U, // SRSHL_VG2_2ZZ_D |
| 8540 | 2449658973U, // SRSHL_VG2_2ZZ_H |
| 8541 | 2451772509U, // SRSHL_VG2_2ZZ_S |
| 8542 | 2445431901U, // SRSHL_VG4_4Z4Z_B |
| 8543 | 2447545437U, // SRSHL_VG4_4Z4Z_D |
| 8544 | 2449658973U, // SRSHL_VG4_4Z4Z_H |
| 8545 | 2451772509U, // SRSHL_VG4_4Z4Z_S |
| 8546 | 2445431901U, // SRSHL_VG4_4ZZ_B |
| 8547 | 2447545437U, // SRSHL_VG4_4ZZ_D |
| 8548 | 2449658973U, // SRSHL_VG4_4ZZ_H |
| 8549 | 2451772509U, // SRSHL_VG4_4ZZ_S |
| 8550 | 807441501U, // SRSHL_ZPmZ_B |
| 8551 | 807457885U, // SRSHL_ZPmZ_D |
| 8552 | 543233117U, // SRSHL_ZPmZ_H |
| 8553 | 807490653U, // SRSHL_ZPmZ_S |
| 8554 | 1350669405U, // SRSHLv16i8 |
| 8555 | 2118749U, // SRSHLv1i64 |
| 8556 | 1352766557U, // SRSHLv2i32 |
| 8557 | 1354863709U, // SRSHLv2i64 |
| 8558 | 1356960861U, // SRSHLv4i16 |
| 8559 | 1359058013U, // SRSHLv4i32 |
| 8560 | 1361155165U, // SRSHLv8i16 |
| 8561 | 1363252317U, // SRSHLv8i8 |
| 8562 | 807443442U, // SRSHR_ZPmI_B |
| 8563 | 807459826U, // SRSHR_ZPmI_D |
| 8564 | 543235058U, // SRSHR_ZPmI_H |
| 8565 | 807492594U, // SRSHR_ZPmI_S |
| 8566 | 2120690U, // SRSHRd |
| 8567 | 1350671346U, // SRSHRv16i8_shift |
| 8568 | 1352768498U, // SRSHRv2i32_shift |
| 8569 | 1354865650U, // SRSHRv2i64_shift |
| 8570 | 1356962802U, // SRSHRv4i16_shift |
| 8571 | 1359059954U, // SRSHRv4i32_shift |
| 8572 | 1361157106U, // SRSHRv8i16_shift |
| 8573 | 1363254258U, // SRSHRv8i8_shift |
| 8574 | 2686485712U, // SRSRA_ZZI_B |
| 8575 | 1612760272U, // SRSRA_ZZI_D |
| 8576 | 2460026064U, // SRSRA_ZZI_H |
| 8577 | 1881228496U, // SRSRA_ZZI_S |
| 8578 | 807716048U, // SRSRAd |
| 8579 | 3229746384U, // SRSRAv16i8_shift |
| 8580 | 3231843536U, // SRSRAv2i32_shift |
| 8581 | 3233940688U, // SRSRAv2i64_shift |
| 8582 | 3236037840U, // SRSRAv4i16_shift |
| 8583 | 3238134992U, // SRSRAv4i32_shift |
| 8584 | 3240232144U, // SRSRAv8i16_shift |
| 8585 | 3242329296U, // SRSRAv8i8_shift |
| 8586 | 3760244674U, // SSHLLB_ZZI_D |
| 8587 | 2462123970U, // SSHLLB_ZZI_H |
| 8588 | 2149664706U, // SSHLLB_ZZI_S |
| 8589 | 3760250931U, // SSHLLT_ZZI_D |
| 8590 | 2462130227U, // SSHLLT_ZZI_H |
| 8591 | 2149670963U, // SSHLLT_ZZI_S |
| 8592 | 1361150256U, // SSHLLv16i8_shift |
| 8593 | 1354863761U, // SSHLLv2i32_shift |
| 8594 | 1359058065U, // SSHLLv4i16_shift |
| 8595 | 1354858800U, // SSHLLv4i32_shift |
| 8596 | 1359053104U, // SSHLLv8i16_shift |
| 8597 | 1361155217U, // SSHLLv8i8_shift |
| 8598 | 1350669419U, // SSHLv16i8 |
| 8599 | 2118763U, // SSHLv1i64 |
| 8600 | 1352766571U, // SSHLv2i32 |
| 8601 | 1354863723U, // SSHLv2i64 |
| 8602 | 1356960875U, // SSHLv4i16 |
| 8603 | 1359058027U, // SSHLv4i32 |
| 8604 | 1361155179U, // SSHLv8i16 |
| 8605 | 1363252331U, // SSHLv8i8 |
| 8606 | 2120704U, // SSHRd |
| 8607 | 1350671360U, // SSHRv16i8_shift |
| 8608 | 1352768512U, // SSHRv2i32_shift |
| 8609 | 1354865664U, // SSHRv2i64_shift |
| 8610 | 1356962816U, // SSHRv4i16_shift |
| 8611 | 1359059968U, // SSHRv4i32_shift |
| 8612 | 1361157120U, // SSHRv8i16_shift |
| 8613 | 1363254272U, // SSHRv8i8_shift |
| 8614 | 2686485726U, // SSRA_ZZI_B |
| 8615 | 1612760286U, // SSRA_ZZI_D |
| 8616 | 2460026078U, // SSRA_ZZI_H |
| 8617 | 1881228510U, // SSRA_ZZI_S |
| 8618 | 807716062U, // SSRAd |
| 8619 | 3229746398U, // SSRAv16i8_shift |
| 8620 | 3231843550U, // SSRAv2i32_shift |
| 8621 | 3233940702U, // SSRAv2i64_shift |
| 8622 | 3236037854U, // SSRAv4i16_shift |
| 8623 | 3238135006U, // SSRAv4i32_shift |
| 8624 | 3240232158U, // SSRAv8i16_shift |
| 8625 | 3242329310U, // SSRAv8i8_shift |
| 8626 | 4032988592U, // SST1B_D |
| 8627 | 4032988592U, // SST1B_D_IMM |
| 8628 | 4032988592U, // SST1B_D_SXTW |
| 8629 | 4032988592U, // SST1B_D_UXTW |
| 8630 | 4033021360U, // SST1B_S_IMM |
| 8631 | 4033021360U, // SST1B_S_SXTW |
| 8632 | 4033021360U, // SST1B_S_UXTW |
| 8633 | 4032990066U, // SST1D |
| 8634 | 4032990066U, // SST1D_IMM |
| 8635 | 4032990066U, // SST1D_SCALED |
| 8636 | 4032990066U, // SST1D_SXTW |
| 8637 | 4032990066U, // SST1D_SXTW_SCALED |
| 8638 | 4032990066U, // SST1D_UXTW |
| 8639 | 4032990066U, // SST1D_UXTW_SCALED |
| 8640 | 4032990746U, // SST1H_D |
| 8641 | 4032990746U, // SST1H_D_IMM |
| 8642 | 4032990746U, // SST1H_D_SCALED |
| 8643 | 4032990746U, // SST1H_D_SXTW |
| 8644 | 4032990746U, // SST1H_D_SXTW_SCALED |
| 8645 | 4032990746U, // SST1H_D_UXTW |
| 8646 | 4032990746U, // SST1H_D_UXTW_SCALED |
| 8647 | 4033023514U, // SST1H_S_IMM |
| 8648 | 4033023514U, // SST1H_S_SXTW |
| 8649 | 4033023514U, // SST1H_S_SXTW_SCALED |
| 8650 | 4033023514U, // SST1H_S_UXTW |
| 8651 | 4033023514U, // SST1H_S_UXTW_SCALED |
| 8652 | 4033321684U, // SST1Q |
| 8653 | 4032996267U, // SST1W_D |
| 8654 | 4032996267U, // SST1W_D_IMM |
| 8655 | 4032996267U, // SST1W_D_SCALED |
| 8656 | 4032996267U, // SST1W_D_SXTW |
| 8657 | 4032996267U, // SST1W_D_SXTW_SCALED |
| 8658 | 4032996267U, // SST1W_D_UXTW |
| 8659 | 4032996267U, // SST1W_D_UXTW_SCALED |
| 8660 | 4033029035U, // SST1W_IMM |
| 8661 | 4033029035U, // SST1W_SXTW |
| 8662 | 4033029035U, // SST1W_SXTW_SCALED |
| 8663 | 4033029035U, // SST1W_UXTW |
| 8664 | 4033029035U, // SST1W_UXTW_SCALED |
| 8665 | 3760250589U, // SSUBLBT_ZZZ_D |
| 8666 | 2462129885U, // SSUBLBT_ZZZ_H |
| 8667 | 2149670621U, // SSUBLBT_ZZZ_S |
| 8668 | 3760244603U, // SSUBLB_ZZZ_D |
| 8669 | 2462123899U, // SSUBLB_ZZZ_H |
| 8670 | 2149664635U, // SSUBLB_ZZZ_S |
| 8671 | 3760245267U, // SSUBLTB_ZZZ_D |
| 8672 | 2462124563U, // SSUBLTB_ZZZ_H |
| 8673 | 2149665299U, // SSUBLTB_ZZZ_S |
| 8674 | 3760250837U, // SSUBLT_ZZZ_D |
| 8675 | 2462130133U, // SSUBLT_ZZZ_H |
| 8676 | 2149670869U, // SSUBLT_ZZZ_S |
| 8677 | 1361150208U, // SSUBLv16i8_v8i16 |
| 8678 | 1354863545U, // SSUBLv2i32_v2i64 |
| 8679 | 1359057849U, // SSUBLv4i16_v4i32 |
| 8680 | 1354858752U, // SSUBLv4i32_v2i64 |
| 8681 | 1359053056U, // SSUBLv8i16_v4i32 |
| 8682 | 1361155001U, // SSUBLv8i8_v8i16 |
| 8683 | 2686503559U, // SSUBWB_ZZZ_D |
| 8684 | 2443250311U, // SSUBWB_ZZZ_H |
| 8685 | 3760278151U, // SSUBWB_ZZZ_S |
| 8686 | 2686509580U, // SSUBWT_ZZZ_D |
| 8687 | 2443256332U, // SSUBWT_ZZZ_H |
| 8688 | 3760284172U, // SSUBWT_ZZZ_S |
| 8689 | 1361150540U, // SSUBWv16i8_v8i16 |
| 8690 | 1354867677U, // SSUBWv2i32_v2i64 |
| 8691 | 1359061981U, // SSUBWv4i16_v4i32 |
| 8692 | 1354859084U, // SSUBWv4i32_v2i64 |
| 8693 | 1359053388U, // SSUBWv8i16_v4i32 |
| 8694 | 1361159133U, // SSUBWv8i8_v8i16 |
| 8695 | 4032972208U, // ST1B |
| 8696 | 4121052592U, // ST1B_2Z |
| 8697 | 4121052592U, // ST1B_2Z_IMM |
| 8698 | 2955445680U, // ST1B_2Z_STRIDED |
| 8699 | 2955445680U, // ST1B_2Z_STRIDED_IMM |
| 8700 | 4121052592U, // ST1B_4Z |
| 8701 | 4121052592U, // ST1B_4Z_IMM |
| 8702 | 4121052592U, // ST1B_4Z_STRIDED |
| 8703 | 4121052592U, // ST1B_4Z_STRIDED_IMM |
| 8704 | 4032988592U, // ST1B_D |
| 8705 | 4032988592U, // ST1B_D_IMM |
| 8706 | 4033004976U, // ST1B_H |
| 8707 | 4033004976U, // ST1B_H_IMM |
| 8708 | 4032972208U, // ST1B_IMM |
| 8709 | 4033021360U, // ST1B_S |
| 8710 | 4033021360U, // ST1B_S_IMM |
| 8711 | 4032990066U, // ST1D |
| 8712 | 4121070450U, // ST1D_2Z |
| 8713 | 4121070450U, // ST1D_2Z_IMM |
| 8714 | 4121070450U, // ST1D_2Z_STRIDED |
| 8715 | 4121070450U, // ST1D_2Z_STRIDED_IMM |
| 8716 | 4121070450U, // ST1D_4Z |
| 8717 | 4121070450U, // ST1D_4Z_IMM |
| 8718 | 4121070450U, // ST1D_4Z_STRIDED |
| 8719 | 4121070450U, // ST1D_4Z_STRIDED_IMM |
| 8720 | 4032990066U, // ST1D_IMM |
| 8721 | 4033317746U, // ST1D_Q |
| 8722 | 4033317746U, // ST1D_Q_IMM |
| 8723 | 573554U, // ST1Fourv16b |
| 8724 | 97058930U, // ST1Fourv16b_POST |
| 8725 | 606322U, // ST1Fourv1d |
| 8726 | 99188850U, // ST1Fourv1d_POST |
| 8727 | 639090U, // ST1Fourv2d |
| 8728 | 97124466U, // ST1Fourv2d_POST |
| 8729 | 671858U, // ST1Fourv2s |
| 8730 | 99254386U, // ST1Fourv2s_POST |
| 8731 | 704626U, // ST1Fourv4h |
| 8732 | 99287154U, // ST1Fourv4h_POST |
| 8733 | 737394U, // ST1Fourv4s |
| 8734 | 97222770U, // ST1Fourv4s_POST |
| 8735 | 770162U, // ST1Fourv8b |
| 8736 | 99352690U, // ST1Fourv8b_POST |
| 8737 | 802930U, // ST1Fourv8h |
| 8738 | 97288306U, // ST1Fourv8h_POST |
| 8739 | 4033007130U, // ST1H |
| 8740 | 4121087514U, // ST1H_2Z |
| 8741 | 4121087514U, // ST1H_2Z_IMM |
| 8742 | 2955726362U, // ST1H_2Z_STRIDED |
| 8743 | 2955726362U, // ST1H_2Z_STRIDED_IMM |
| 8744 | 4121087514U, // ST1H_4Z |
| 8745 | 4121087514U, // ST1H_4Z_IMM |
| 8746 | 4121087514U, // ST1H_4Z_STRIDED |
| 8747 | 4121087514U, // ST1H_4Z_STRIDED_IMM |
| 8748 | 4032990746U, // ST1H_D |
| 8749 | 4032990746U, // ST1H_D_IMM |
| 8750 | 4033007130U, // ST1H_IMM |
| 8751 | 4033023514U, // ST1H_S |
| 8752 | 4033023514U, // ST1H_S_IMM |
| 8753 | 573554U, // ST1Onev16b |
| 8754 | 101253234U, // ST1Onev16b_POST |
| 8755 | 606322U, // ST1Onev1d |
| 8756 | 103383154U, // ST1Onev1d_POST |
| 8757 | 639090U, // ST1Onev2d |
| 8758 | 101318770U, // ST1Onev2d_POST |
| 8759 | 671858U, // ST1Onev2s |
| 8760 | 103448690U, // ST1Onev2s_POST |
| 8761 | 704626U, // ST1Onev4h |
| 8762 | 103481458U, // ST1Onev4h_POST |
| 8763 | 737394U, // ST1Onev4s |
| 8764 | 101417074U, // ST1Onev4s_POST |
| 8765 | 770162U, // ST1Onev8b |
| 8766 | 103546994U, // ST1Onev8b_POST |
| 8767 | 802930U, // ST1Onev8h |
| 8768 | 101482610U, // ST1Onev8h_POST |
| 8769 | 573554U, // ST1Threev16b |
| 8770 | 111738994U, // ST1Threev16b_POST |
| 8771 | 606322U, // ST1Threev1d |
| 8772 | 113868914U, // ST1Threev1d_POST |
| 8773 | 639090U, // ST1Threev2d |
| 8774 | 111804530U, // ST1Threev2d_POST |
| 8775 | 671858U, // ST1Threev2s |
| 8776 | 113934450U, // ST1Threev2s_POST |
| 8777 | 704626U, // ST1Threev4h |
| 8778 | 113967218U, // ST1Threev4h_POST |
| 8779 | 737394U, // ST1Threev4s |
| 8780 | 111902834U, // ST1Threev4s_POST |
| 8781 | 770162U, // ST1Threev8b |
| 8782 | 114032754U, // ST1Threev8b_POST |
| 8783 | 802930U, // ST1Threev8h |
| 8784 | 111968370U, // ST1Threev8h_POST |
| 8785 | 573554U, // ST1Twov16b |
| 8786 | 99156082U, // ST1Twov16b_POST |
| 8787 | 606322U, // ST1Twov1d |
| 8788 | 101286002U, // ST1Twov1d_POST |
| 8789 | 639090U, // ST1Twov2d |
| 8790 | 99221618U, // ST1Twov2d_POST |
| 8791 | 671858U, // ST1Twov2s |
| 8792 | 101351538U, // ST1Twov2s_POST |
| 8793 | 704626U, // ST1Twov4h |
| 8794 | 101384306U, // ST1Twov4h_POST |
| 8795 | 737394U, // ST1Twov4s |
| 8796 | 99319922U, // ST1Twov4s_POST |
| 8797 | 770162U, // ST1Twov8b |
| 8798 | 101449842U, // ST1Twov8b_POST |
| 8799 | 802930U, // ST1Twov8h |
| 8800 | 99385458U, // ST1Twov8h_POST |
| 8801 | 4033029035U, // ST1W |
| 8802 | 4121109419U, // ST1W_2Z |
| 8803 | 4121109419U, // ST1W_2Z_IMM |
| 8804 | 4121109419U, // ST1W_2Z_STRIDED |
| 8805 | 4121109419U, // ST1W_2Z_STRIDED_IMM |
| 8806 | 4121109419U, // ST1W_4Z |
| 8807 | 4121109419U, // ST1W_4Z_IMM |
| 8808 | 4121109419U, // ST1W_4Z_STRIDED |
| 8809 | 4121109419U, // ST1W_4Z_STRIDED_IMM |
| 8810 | 4032996267U, // ST1W_D |
| 8811 | 4032996267U, // ST1W_D_IMM |
| 8812 | 4033029035U, // ST1W_IMM |
| 8813 | 4033323947U, // ST1W_Q |
| 8814 | 4033323947U, // ST1W_Q_IMM |
| 8815 | 2473078098U, // ST1_MXIPXX_H_B |
| 8816 | 2473078112U, // ST1_MXIPXX_H_D |
| 8817 | 2473078126U, // ST1_MXIPXX_H_H |
| 8818 | 2473078140U, // ST1_MXIPXX_H_Q |
| 8819 | 2473078154U, // ST1_MXIPXX_H_S |
| 8820 | 2473094482U, // ST1_MXIPXX_V_B |
| 8821 | 2473094496U, // ST1_MXIPXX_V_D |
| 8822 | 2473094510U, // ST1_MXIPXX_V_H |
| 8823 | 2473094524U, // ST1_MXIPXX_V_Q |
| 8824 | 2473094538U, // ST1_MXIPXX_V_S |
| 8825 | 174899314U, // ST1i16 |
| 8826 | 177012850U, // ST1i16_POST |
| 8827 | 1245298U, // ST1i32 |
| 8828 | 445481074U, // ST1i32_POST |
| 8829 | 1261682U, // ST1i64 |
| 8830 | 713949298U, // ST1i64_POST |
| 8831 | 174620786U, // ST1i8 |
| 8832 | 982417522U, // ST1i8_POST |
| 8833 | 4032972237U, // ST2B |
| 8834 | 4032972237U, // ST2B_IMM |
| 8835 | 4032990078U, // ST2D |
| 8836 | 4032990078U, // ST2D_IMM |
| 8837 | 845467042U, // ST2GPostIndex |
| 8838 | 845467042U, // ST2GPreIndex |
| 8839 | 39865762U, // ST2Gi |
| 8840 | 4033007159U, // ST2H |
| 8841 | 4033007159U, // ST2H_IMM |
| 8842 | 4033321696U, // ST2Q |
| 8843 | 4033321696U, // ST2Q_IMM |
| 8844 | 574023U, // ST2Twov16b |
| 8845 | 99156551U, // ST2Twov16b_POST |
| 8846 | 639559U, // ST2Twov2d |
| 8847 | 99222087U, // ST2Twov2d_POST |
| 8848 | 672327U, // ST2Twov2s |
| 8849 | 101352007U, // ST2Twov2s_POST |
| 8850 | 705095U, // ST2Twov4h |
| 8851 | 101384775U, // ST2Twov4h_POST |
| 8852 | 737863U, // ST2Twov4s |
| 8853 | 99320391U, // ST2Twov4s_POST |
| 8854 | 770631U, // ST2Twov8b |
| 8855 | 101450311U, // ST2Twov8b_POST |
| 8856 | 803399U, // ST2Twov8h |
| 8857 | 99385927U, // ST2Twov8h_POST |
| 8858 | 4033029055U, // ST2W |
| 8859 | 4033029055U, // ST2W_IMM |
| 8860 | 174899783U, // ST2i16 |
| 8861 | 445448775U, // ST2i16_POST |
| 8862 | 1245767U, // ST2i32 |
| 8863 | 713916999U, // ST2i32_POST |
| 8864 | 1262151U, // ST2i64 |
| 8865 | 1250820679U, // ST2i64_POST |
| 8866 | 174621255U, // ST2i8 |
| 8867 | 177111623U, // ST2i8_POST |
| 8868 | 4032972258U, // ST3B |
| 8869 | 4032972258U, // ST3B_IMM |
| 8870 | 4032990090U, // ST3D |
| 8871 | 4032990090U, // ST3D_IMM |
| 8872 | 4033007171U, // ST3H |
| 8873 | 4033007171U, // ST3H_IMM |
| 8874 | 4033321708U, // ST3Q |
| 8875 | 4033321708U, // ST3Q_IMM |
| 8876 | 574089U, // ST3Threev16b |
| 8877 | 111739529U, // ST3Threev16b_POST |
| 8878 | 639625U, // ST3Threev2d |
| 8879 | 111805065U, // ST3Threev2d_POST |
| 8880 | 672393U, // ST3Threev2s |
| 8881 | 113934985U, // ST3Threev2s_POST |
| 8882 | 705161U, // ST3Threev4h |
| 8883 | 113967753U, // ST3Threev4h_POST |
| 8884 | 737929U, // ST3Threev4s |
| 8885 | 111903369U, // ST3Threev4s_POST |
| 8886 | 770697U, // ST3Threev8b |
| 8887 | 114033289U, // ST3Threev8b_POST |
| 8888 | 803465U, // ST3Threev8h |
| 8889 | 111968905U, // ST3Threev8h_POST |
| 8890 | 4033029067U, // ST3W |
| 8891 | 4033029067U, // ST3W_IMM |
| 8892 | 174899849U, // ST3i16 |
| 8893 | 1519190665U, // ST3i16_POST |
| 8894 | 1245833U, // ST3i32 |
| 8895 | 1787658889U, // ST3i32_POST |
| 8896 | 1262217U, // ST3i64 |
| 8897 | 2056127113U, // ST3i64_POST |
| 8898 | 174621321U, // ST3i8 |
| 8899 | 2324595337U, // ST3i8_POST |
| 8900 | 4032972284U, // ST4B |
| 8901 | 4032972284U, // ST4B_IMM |
| 8902 | 4032990102U, // ST4D |
| 8903 | 4032990102U, // ST4D_IMM |
| 8904 | 574113U, // ST4Fourv16b |
| 8905 | 97059489U, // ST4Fourv16b_POST |
| 8906 | 639649U, // ST4Fourv2d |
| 8907 | 97125025U, // ST4Fourv2d_POST |
| 8908 | 672417U, // ST4Fourv2s |
| 8909 | 99254945U, // ST4Fourv2s_POST |
| 8910 | 705185U, // ST4Fourv4h |
| 8911 | 99287713U, // ST4Fourv4h_POST |
| 8912 | 737953U, // ST4Fourv4s |
| 8913 | 97223329U, // ST4Fourv4s_POST |
| 8914 | 770721U, // ST4Fourv8b |
| 8915 | 99353249U, // ST4Fourv8b_POST |
| 8916 | 803489U, // ST4Fourv8h |
| 8917 | 97288865U, // ST4Fourv8h_POST |
| 8918 | 4033007183U, // ST4H |
| 8919 | 4033007183U, // ST4H_IMM |
| 8920 | 4033321720U, // ST4Q |
| 8921 | 4033321720U, // ST4Q_IMM |
| 8922 | 4033029079U, // ST4W |
| 8923 | 4033029079U, // ST4W_IMM |
| 8924 | 174899873U, // ST4i16 |
| 8925 | 713884321U, // ST4i16_POST |
| 8926 | 1245857U, // ST4i32 |
| 8927 | 1250788001U, // ST4i32_POST |
| 8928 | 1262241U, // ST4i64 |
| 8929 | 2592998049U, // ST4i64_POST |
| 8930 | 174621345U, // ST4i8 |
| 8931 | 445547169U, // ST4i8_POST |
| 8932 | 984559U, // ST64B |
| 8933 | 2686476928U, // ST64BV |
| 8934 | 2686468128U, // ST64BV0 |
| 8935 | 178277384U, // STBFADD |
| 8936 | 178279399U, // STBFADDL |
| 8937 | 178283748U, // STBFMAX |
| 8938 | 178280153U, // STBFMAXL |
| 8939 | 178280307U, // STBFMAXNM |
| 8940 | 178279687U, // STBFMAXNML |
| 8941 | 178280414U, // STBFMIN |
| 8942 | 178279731U, // STBFMINL |
| 8943 | 178280265U, // STBFMINNM |
| 8944 | 178279641U, // STBFMINNML |
| 8945 | 11509U, // STCPH |
| 8946 | 178277401U, // STFADDD |
| 8947 | 178277401U, // STFADDH |
| 8948 | 178279418U, // STFADDLD |
| 8949 | 178279418U, // STFADDLH |
| 8950 | 178279418U, // STFADDLS |
| 8951 | 178277401U, // STFADDS |
| 8952 | 178283765U, // STFMAXD |
| 8953 | 178283765U, // STFMAXH |
| 8954 | 178280172U, // STFMAXLD |
| 8955 | 178280172U, // STFMAXLH |
| 8956 | 178280172U, // STFMAXLS |
| 8957 | 178280328U, // STFMAXNMD |
| 8958 | 178280328U, // STFMAXNMH |
| 8959 | 178279710U, // STFMAXNMLD |
| 8960 | 178279710U, // STFMAXNMLH |
| 8961 | 178279710U, // STFMAXNMLS |
| 8962 | 178280328U, // STFMAXNMS |
| 8963 | 178283765U, // STFMAXS |
| 8964 | 178280431U, // STFMIND |
| 8965 | 178280431U, // STFMINH |
| 8966 | 178279750U, // STFMINLD |
| 8967 | 178279750U, // STFMINLH |
| 8968 | 178279750U, // STFMINLS |
| 8969 | 178280286U, // STFMINNMD |
| 8970 | 178280286U, // STFMINNMH |
| 8971 | 178279664U, // STFMINNMLD |
| 8972 | 178279664U, // STFMINNMLH |
| 8973 | 178279664U, // STFMINNMLS |
| 8974 | 178280286U, // STFMINNMS |
| 8975 | 178280431U, // STFMINS |
| 8976 | 39868199U, // STGM |
| 8977 | 2119991U, // STGPi |
| 8978 | 845467106U, // STGPostIndex |
| 8979 | 807721271U, // STGPpost |
| 8980 | 807721271U, // STGPpre |
| 8981 | 845467106U, // STGPreIndex |
| 8982 | 39865826U, // STGi |
| 8983 | 2120034U, // STILPW |
| 8984 | 807721314U, // STILPWpre |
| 8985 | 2120034U, // STILPX |
| 8986 | 807721314U, // STILPXpre |
| 8987 | 1261614U, // STL1 |
| 8988 | 39864622U, // STLLRB |
| 8989 | 39866430U, // STLLRH |
| 8990 | 39869539U, // STLLRW |
| 8991 | 39869539U, // STLLRX |
| 8992 | 2120041U, // STLPi |
| 8993 | 39864630U, // STLRB |
| 8994 | 39866438U, // STLRH |
| 8995 | 39869552U, // STLRW |
| 8996 | 845470832U, // STLRWpre |
| 8997 | 39869552U, // STLRX |
| 8998 | 845470832U, // STLRXpre |
| 8999 | 2121011U, // STLTXRW |
| 9000 | 2121011U, // STLTXRX |
| 9001 | 39864680U, // STLURBi |
| 9002 | 39866488U, // STLURHi |
| 9003 | 39869661U, // STLURWi |
| 9004 | 39869661U, // STLURXi |
| 9005 | 39869661U, // STLURbi |
| 9006 | 39869661U, // STLURdi |
| 9007 | 39869661U, // STLURhi |
| 9008 | 39869661U, // STLURqi |
| 9009 | 39869661U, // STLURsi |
| 9010 | 2120380U, // STLXPW |
| 9011 | 2120380U, // STLXPX |
| 9012 | 2115983U, // STLXRB |
| 9013 | 2117791U, // STLXRH |
| 9014 | 2120989U, // STLXRW |
| 9015 | 2120989U, // STLXRX |
| 9016 | 75613195U, // STMOPA_M2ZZZI_BtoS |
| 9017 | 1929495563U, // STMOPA_M2ZZZI_HtoS |
| 9018 | 2120137U, // STNPDi |
| 9019 | 2120137U, // STNPQi |
| 9020 | 2120137U, // STNPSi |
| 9021 | 2120137U, // STNPWi |
| 9022 | 2120137U, // STNPXi |
| 9023 | 4121052584U, // STNT1B_2Z |
| 9024 | 4121052584U, // STNT1B_2Z_IMM |
| 9025 | 2955445672U, // STNT1B_2Z_STRIDED |
| 9026 | 2955445672U, // STNT1B_2Z_STRIDED_IMM |
| 9027 | 4121052584U, // STNT1B_4Z |
| 9028 | 4121052584U, // STNT1B_4Z_IMM |
| 9029 | 4121052584U, // STNT1B_4Z_STRIDED |
| 9030 | 4121052584U, // STNT1B_4Z_STRIDED_IMM |
| 9031 | 4032972200U, // STNT1B_ZRI |
| 9032 | 4032972200U, // STNT1B_ZRR |
| 9033 | 4032988584U, // STNT1B_ZZR_D |
| 9034 | 4033021352U, // STNT1B_ZZR_S |
| 9035 | 4121070442U, // STNT1D_2Z |
| 9036 | 4121070442U, // STNT1D_2Z_IMM |
| 9037 | 4121070442U, // STNT1D_2Z_STRIDED |
| 9038 | 4121070442U, // STNT1D_2Z_STRIDED_IMM |
| 9039 | 4121070442U, // STNT1D_4Z |
| 9040 | 4121070442U, // STNT1D_4Z_IMM |
| 9041 | 4121070442U, // STNT1D_4Z_STRIDED |
| 9042 | 4121070442U, // STNT1D_4Z_STRIDED_IMM |
| 9043 | 4032990058U, // STNT1D_ZRI |
| 9044 | 4032990058U, // STNT1D_ZRR |
| 9045 | 4032990058U, // STNT1D_ZZR_D |
| 9046 | 4121087506U, // STNT1H_2Z |
| 9047 | 4121087506U, // STNT1H_2Z_IMM |
| 9048 | 2955726354U, // STNT1H_2Z_STRIDED |
| 9049 | 2955726354U, // STNT1H_2Z_STRIDED_IMM |
| 9050 | 4121087506U, // STNT1H_4Z |
| 9051 | 4121087506U, // STNT1H_4Z_IMM |
| 9052 | 4121087506U, // STNT1H_4Z_STRIDED |
| 9053 | 4121087506U, // STNT1H_4Z_STRIDED_IMM |
| 9054 | 4033007122U, // STNT1H_ZRI |
| 9055 | 4033007122U, // STNT1H_ZRR |
| 9056 | 4032990738U, // STNT1H_ZZR_D |
| 9057 | 4033023506U, // STNT1H_ZZR_S |
| 9058 | 4121109411U, // STNT1W_2Z |
| 9059 | 4121109411U, // STNT1W_2Z_IMM |
| 9060 | 4121109411U, // STNT1W_2Z_STRIDED |
| 9061 | 4121109411U, // STNT1W_2Z_STRIDED_IMM |
| 9062 | 4121109411U, // STNT1W_4Z |
| 9063 | 4121109411U, // STNT1W_4Z_IMM |
| 9064 | 4121109411U, // STNT1W_4Z_STRIDED |
| 9065 | 4121109411U, // STNT1W_4Z_STRIDED_IMM |
| 9066 | 4033029027U, // STNT1W_ZRI |
| 9067 | 4033029027U, // STNT1W_ZRR |
| 9068 | 4032996259U, // STNT1W_ZZR_D |
| 9069 | 4033029027U, // STNT1W_ZZR_S |
| 9070 | 2120304U, // STPDi |
| 9071 | 807721584U, // STPDpost |
| 9072 | 807721584U, // STPDpre |
| 9073 | 2120304U, // STPQi |
| 9074 | 807721584U, // STPQpost |
| 9075 | 807721584U, // STPQpre |
| 9076 | 2120304U, // STPSi |
| 9077 | 807721584U, // STPSpost |
| 9078 | 807721584U, // STPSpre |
| 9079 | 2120304U, // STPWi |
| 9080 | 807721584U, // STPWpost |
| 9081 | 807721584U, // STPWpre |
| 9082 | 2120304U, // STPXi |
| 9083 | 807721584U, // STPXpost |
| 9084 | 807721584U, // STPXpre |
| 9085 | 845465940U, // STRBBpost |
| 9086 | 845465940U, // STRBBpre |
| 9087 | 39864660U, // STRBBroW |
| 9088 | 39864660U, // STRBBroX |
| 9089 | 39864660U, // STRBBui |
| 9090 | 845470915U, // STRBpost |
| 9091 | 845470915U, // STRBpre |
| 9092 | 39869635U, // STRBroW |
| 9093 | 39869635U, // STRBroX |
| 9094 | 39869635U, // STRBui |
| 9095 | 845470915U, // STRDpost |
| 9096 | 845470915U, // STRDpre |
| 9097 | 39869635U, // STRDroW |
| 9098 | 39869635U, // STRDroX |
| 9099 | 39869635U, // STRDui |
| 9100 | 845467748U, // STRHHpost |
| 9101 | 845467748U, // STRHHpre |
| 9102 | 39866468U, // STRHHroW |
| 9103 | 39866468U, // STRHHroX |
| 9104 | 39866468U, // STRHHui |
| 9105 | 845470915U, // STRHpost |
| 9106 | 845470915U, // STRHpre |
| 9107 | 39869635U, // STRHroW |
| 9108 | 39869635U, // STRHroX |
| 9109 | 39869635U, // STRHui |
| 9110 | 845470915U, // STRQpost |
| 9111 | 845470915U, // STRQpre |
| 9112 | 39869635U, // STRQroW |
| 9113 | 39869635U, // STRQroX |
| 9114 | 39869635U, // STRQui |
| 9115 | 845470915U, // STRSpost |
| 9116 | 845470915U, // STRSpre |
| 9117 | 39869635U, // STRSroW |
| 9118 | 39869635U, // STRSroX |
| 9119 | 39869635U, // STRSui |
| 9120 | 845470915U, // STRWpost |
| 9121 | 845470915U, // STRWpre |
| 9122 | 39869635U, // STRWroW |
| 9123 | 39869635U, // STRWroX |
| 9124 | 39869635U, // STRWui |
| 9125 | 845470915U, // STRXpost |
| 9126 | 845470915U, // STRXpre |
| 9127 | 39869635U, // STRXroW |
| 9128 | 39869635U, // STRXroX |
| 9129 | 39869635U, // STRXui |
| 9130 | 40869059U, // STR_PXI |
| 9131 | 39869635U, // STR_TX |
| 9132 | 1039555U, // STR_ZA |
| 9133 | 40869059U, // STR_ZXI |
| 9134 | 1281804U, // STSHH |
| 9135 | 2120143U, // STTNPQi |
| 9136 | 2120143U, // STTNPXi |
| 9137 | 2120317U, // STTPQi |
| 9138 | 807721597U, // STTPQpost |
| 9139 | 807721597U, // STTPQpre |
| 9140 | 2120317U, // STTPi |
| 9141 | 807721597U, // STTPpost |
| 9142 | 807721597U, // STTPpre |
| 9143 | 39864666U, // STTRBi |
| 9144 | 39866474U, // STTRHi |
| 9145 | 39869643U, // STTRWi |
| 9146 | 39869643U, // STTRXi |
| 9147 | 2121025U, // STTXRWr |
| 9148 | 2121025U, // STTXRXr |
| 9149 | 39864697U, // STURBBi |
| 9150 | 39869676U, // STURBi |
| 9151 | 39869676U, // STURDi |
| 9152 | 39866505U, // STURHHi |
| 9153 | 39869676U, // STURHi |
| 9154 | 39869676U, // STURQi |
| 9155 | 39869676U, // STURSi |
| 9156 | 39869676U, // STURWi |
| 9157 | 39869676U, // STURXi |
| 9158 | 2120387U, // STXPW |
| 9159 | 2120387U, // STXPX |
| 9160 | 2115991U, // STXRB |
| 9161 | 2117799U, // STXRH |
| 9162 | 2121019U, // STXRW |
| 9163 | 2121019U, // STXRX |
| 9164 | 845467048U, // STZ2GPostIndex |
| 9165 | 845467048U, // STZ2GPreIndex |
| 9166 | 39865768U, // STZ2Gi |
| 9167 | 39868205U, // STZGM |
| 9168 | 845467111U, // STZGPostIndex |
| 9169 | 845467111U, // STZGPreIndex |
| 9170 | 39865831U, // STZGi |
| 9171 | 2117039U, // SUBG |
| 9172 | 2149615726U, // SUBHNB_ZZZ_B |
| 9173 | 2439055470U, // SUBHNB_ZZZ_H |
| 9174 | 2686535790U, // SUBHNB_ZZZ_S |
| 9175 | 2954928331U, // SUBHNT_ZZZ_B |
| 9176 | 2441158859U, // SUBHNT_ZZZ_H |
| 9177 | 1612800203U, // SUBHNT_ZZZ_S |
| 9178 | 1352767423U, // SUBHNv2i64_v2i32 |
| 9179 | 3238134177U, // SUBHNv2i64_v4i32 |
| 9180 | 1356961727U, // SUBHNv4i32_v4i16 |
| 9181 | 3240231329U, // SUBHNv4i32_v8i16 |
| 9182 | 3229745569U, // SUBHNv8i16_v16i8 |
| 9183 | 1363253183U, // SUBHNv8i16_v8i8 |
| 9184 | 2119935U, // SUBP |
| 9185 | 2121289U, // SUBPS |
| 9186 | 2122121U, // SUBPT_shift |
| 9187 | 807442687U, // SUBP_ZPmZZ_B |
| 9188 | 807459071U, // SUBP_ZPmZZ_D |
| 9189 | 543234303U, // SUBP_ZPmZZ_H |
| 9190 | 807491839U, // SUBP_ZPmZZ_S |
| 9191 | 3491797868U, // SUBR_ZI_B |
| 9192 | 2686507884U, // SUBR_ZI_D |
| 9193 | 2443254636U, // SUBR_ZI_H |
| 9194 | 3760282476U, // SUBR_ZI_S |
| 9195 | 807443308U, // SUBR_ZPmZ_B |
| 9196 | 807459692U, // SUBR_ZPmZ_D |
| 9197 | 543234924U, // SUBR_ZPmZ_H |
| 9198 | 807492460U, // SUBR_ZPmZ_S |
| 9199 | 2121133U, // SUBSWri |
| 9200 | 2121133U, // SUBSWrs |
| 9201 | 2121133U, // SUBSWrx |
| 9202 | 2121133U, // SUBSXri |
| 9203 | 2121133U, // SUBSXrs |
| 9204 | 2121133U, // SUBSXrx |
| 9205 | 2121133U, // SUBSXrx64 |
| 9206 | 2116177U, // SUBWri |
| 9207 | 2116177U, // SUBWrs |
| 9208 | 2116177U, // SUBWrx |
| 9209 | 2116177U, // SUBXri |
| 9210 | 2116177U, // SUBXrs |
| 9211 | 2116177U, // SUBXrx |
| 9212 | 2116177U, // SUBXrx64 |
| 9213 | 4064496209U, // SUB_VG2_M2Z2Z_D |
| 9214 | 4064512593U, // SUB_VG2_M2Z2Z_S |
| 9215 | 4064496209U, // SUB_VG2_M2ZZ_D |
| 9216 | 4064512593U, // SUB_VG2_M2ZZ_S |
| 9217 | 4064496209U, // SUB_VG2_M2Z_D |
| 9218 | 4064512593U, // SUB_VG2_M2Z_S |
| 9219 | 37964369U, // SUB_VG4_M4Z4Z_D |
| 9220 | 37980753U, // SUB_VG4_M4Z4Z_S |
| 9221 | 37964369U, // SUB_VG4_M4ZZ_D |
| 9222 | 37980753U, // SUB_VG4_M4ZZ_S |
| 9223 | 37964369U, // SUB_VG4_M4Z_D |
| 9224 | 37980753U, // SUB_VG4_M4Z_S |
| 9225 | 3491793489U, // SUB_ZI_B |
| 9226 | 2686503505U, // SUB_ZI_D |
| 9227 | 2443250257U, // SUB_ZI_H |
| 9228 | 3760278097U, // SUB_ZI_S |
| 9229 | 807438929U, // SUB_ZPmZ_B |
| 9230 | 807461257U, // SUB_ZPmZ_CPA |
| 9231 | 807455313U, // SUB_ZPmZ_D |
| 9232 | 543230545U, // SUB_ZPmZ_H |
| 9233 | 807488081U, // SUB_ZPmZ_S |
| 9234 | 3491793489U, // SUB_ZZZ_B |
| 9235 | 2686509449U, // SUB_ZZZ_CPA |
| 9236 | 2686503505U, // SUB_ZZZ_D |
| 9237 | 2443250257U, // SUB_ZZZ_H |
| 9238 | 3760278097U, // SUB_ZZZ_S |
| 9239 | 1350666833U, // SUBv16i8 |
| 9240 | 2116177U, // SUBv1i64 |
| 9241 | 1352763985U, // SUBv2i32 |
| 9242 | 1354861137U, // SUBv2i64 |
| 9243 | 1356958289U, // SUBv4i16 |
| 9244 | 1359055441U, // SUBv4i32 |
| 9245 | 1361152593U, // SUBv8i16 |
| 9246 | 1363249745U, // SUBv8i8 |
| 9247 | 4064518492U, // SUDOT_VG2_M2ZZI_BToS |
| 9248 | 4064518492U, // SUDOT_VG2_M2ZZ_BToS |
| 9249 | 37986652U, // SUDOT_VG4_M4ZZI_BToS |
| 9250 | 37986652U, // SUDOT_VG4_M4ZZ_BToS |
| 9251 | 2686542172U, // SUDOT_ZZZI |
| 9252 | 3238142300U, // SUDOTlanev16i8 |
| 9253 | 3231850844U, // SUDOTlanev8i8 |
| 9254 | 1415812232U, // SUMLALL_MZZI_BtoS |
| 9255 | 4100166792U, // SUMLALL_VG2_M2ZZI_BtoS |
| 9256 | 3026424968U, // SUMLALL_VG2_M2ZZ_BtoS |
| 9257 | 73634952U, // SUMLALL_VG4_M4ZZI_BtoS |
| 9258 | 3294860424U, // SUMLALL_VG4_M4ZZ_BtoS |
| 9259 | 3565273831U, // SUMOP4A_M2Z2Z_BToS |
| 9260 | 1661059815U, // SUMOP4A_M2Z2Z_HtoD |
| 9261 | 75612903U, // SUMOP4A_M2ZZ_BToS |
| 9262 | 1929495271U, // SUMOP4A_M2ZZ_HtoD |
| 9263 | 2485240551U, // SUMOP4A_MZ2Z_BToS |
| 9264 | 2460074727U, // SUMOP4A_MZ2Z_HtoD |
| 9265 | 2485240551U, // SUMOP4A_MZZ_BToS |
| 9266 | 2460074727U, // SUMOP4A_MZZ_HtoD |
| 9267 | 3565280602U, // SUMOP4S_M2Z2Z_BToS |
| 9268 | 1661066586U, // SUMOP4S_M2Z2Z_HtoD |
| 9269 | 75619674U, // SUMOP4S_M2ZZ_BToS |
| 9270 | 1929502042U, // SUMOP4S_M2ZZ_HtoD |
| 9271 | 2485247322U, // SUMOP4S_MZ2Z_BToS |
| 9272 | 2460081498U, // SUMOP4S_MZ2Z_HtoD |
| 9273 | 2485247322U, // SUMOP4S_MZZ_BToS |
| 9274 | 2460081498U, // SUMOP4S_MZZ_HtoD |
| 9275 | 541180956U, // SUMOPA_MPPZZ_D |
| 9276 | 541180956U, // SUMOPA_MPPZZ_S |
| 9277 | 541187695U, // SUMOPS_MPPZZ_D |
| 9278 | 541187695U, // SUMOPS_MPPZZ_S |
| 9279 | 3760247150U, // SUNPKHI_ZZ_D |
| 9280 | 583078254U, // SUNPKHI_ZZ_H |
| 9281 | 2149667182U, // SUNPKHI_ZZ_S |
| 9282 | 3760249033U, // SUNPKLO_ZZ_D |
| 9283 | 583080137U, // SUNPKLO_ZZ_H |
| 9284 | 2149669065U, // SUNPKLO_ZZ_S |
| 9285 | 560107952U, // SUNPK_VG2_2ZZ_D |
| 9286 | 583193008U, // SUNPK_VG2_2ZZ_H |
| 9287 | 564335024U, // SUNPK_VG2_2ZZ_S |
| 9288 | 572690864U, // SUNPK_VG4_4Z2Z_D |
| 9289 | 566415792U, // SUNPK_VG4_4Z2Z_H |
| 9290 | 570626480U, // SUNPK_VG4_4Z2Z_S |
| 9291 | 807439446U, // SUQADD_ZPmZ_B |
| 9292 | 807455830U, // SUQADD_ZPmZ_D |
| 9293 | 543231062U, // SUQADD_ZPmZ_H |
| 9294 | 807488598U, // SUQADD_ZPmZ_S |
| 9295 | 3229748310U, // SUQADDv16i8 |
| 9296 | 807717974U, // SUQADDv1i16 |
| 9297 | 807717974U, // SUQADDv1i32 |
| 9298 | 807717974U, // SUQADDv1i64 |
| 9299 | 807717974U, // SUQADDv1i8 |
| 9300 | 3231845462U, // SUQADDv2i32 |
| 9301 | 3233942614U, // SUQADDv2i64 |
| 9302 | 3236039766U, // SUQADDv4i16 |
| 9303 | 3238136918U, // SUQADDv4i32 |
| 9304 | 3240234070U, // SUQADDv8i16 |
| 9305 | 3242331222U, // SUQADDv8i8 |
| 9306 | 75613203U, // SUTMOPA_M2ZZZI_BtoS |
| 9307 | 37986675U, // SUVDOT_VG4_M4ZZI_BToS |
| 9308 | 379719U, // SVC |
| 9309 | 4064518508U, // SVDOT_VG2_M2ZZI_HtoS |
| 9310 | 37986668U, // SVDOT_VG4_M4ZZI_BtoS |
| 9311 | 37970284U, // SVDOT_VG4_M4ZZI_HtoD |
| 9312 | 3223635487U, // SWPAB |
| 9313 | 3223637648U, // SWPAH |
| 9314 | 3223635767U, // SWPALB |
| 9315 | 3223637811U, // SWPALH |
| 9316 | 3223638772U, // SWPALW |
| 9317 | 3223638772U, // SWPALX |
| 9318 | 3223635086U, // SWPAW |
| 9319 | 3223635086U, // SWPAX |
| 9320 | 3223636220U, // SWPB |
| 9321 | 3223638028U, // SWPH |
| 9322 | 3223635976U, // SWPLB |
| 9323 | 3223637908U, // SWPLH |
| 9324 | 3223639514U, // SWPLW |
| 9325 | 3223639514U, // SWPLX |
| 9326 | 2419022313U, // SWPP |
| 9327 | 2419016744U, // SWPPA |
| 9328 | 2419020420U, // SWPPAL |
| 9329 | 2419021164U, // SWPPL |
| 9330 | 3223638899U, // SWPTALW |
| 9331 | 3223638899U, // SWPTALX |
| 9332 | 3223635241U, // SWPTAW |
| 9333 | 3223635241U, // SWPTAX |
| 9334 | 3223639671U, // SWPTLW |
| 9335 | 3223639671U, // SWPTLX |
| 9336 | 3223642534U, // SWPTW |
| 9337 | 3223642534U, // SWPTX |
| 9338 | 3223640717U, // SWPW |
| 9339 | 3223640717U, // SWPX |
| 9340 | 270584387U, // SXTB_ZPmZ_D |
| 9341 | 541133379U, // SXTB_ZPmZ_H |
| 9342 | 270617155U, // SXTB_ZPmZ_S |
| 9343 | 807455299U, // SXTB_ZPzZ_D |
| 9344 | 1080101443U, // SXTB_ZPzZ_H |
| 9345 | 807488067U, // SXTB_ZPzZ_S |
| 9346 | 270586135U, // SXTH_ZPmZ_D |
| 9347 | 270618903U, // SXTH_ZPmZ_S |
| 9348 | 807457047U, // SXTH_ZPzZ_D |
| 9349 | 807489815U, // SXTH_ZPzZ_S |
| 9350 | 270591136U, // SXTW_ZPmZ_D |
| 9351 | 807462048U, // SXTW_ZPzZ_D |
| 9352 | 2119245U, // SYSLxt |
| 9353 | 2954910265U, // SYSPxt |
| 9354 | 2954910265U, // SYSPxt_XZR |
| 9355 | 2954911405U, // SYSxt |
| 9356 | 1612749609U, // TBLQ_ZZZ_B |
| 9357 | 2418072361U, // TBLQ_ZZZ_D |
| 9358 | 2449546025U, // TBLQ_ZZZ_H |
| 9359 | 1881234217U, // TBLQ_ZZZ_S |
| 9360 | 1612747684U, // TBL_ZZZZ_B |
| 9361 | 2418070436U, // TBL_ZZZZ_D |
| 9362 | 2449544100U, // TBL_ZZZZ_H |
| 9363 | 1881232292U, // TBL_ZZZZ_S |
| 9364 | 1612747684U, // TBL_ZZZ_B |
| 9365 | 2418070436U, // TBL_ZZZ_D |
| 9366 | 2449544100U, // TBL_ZZZ_H |
| 9367 | 1881232292U, // TBL_ZZZ_S |
| 9368 | 3498152868U, // TBLv16i8Four |
| 9369 | 3498152868U, // TBLv16i8One |
| 9370 | 3498152868U, // TBLv16i8Three |
| 9371 | 3498152868U, // TBLv16i8Two |
| 9372 | 3510735780U, // TBLv8i8Four |
| 9373 | 3510735780U, // TBLv8i8One |
| 9374 | 3510735780U, // TBLv8i8Three |
| 9375 | 3510735780U, // TBLv8i8Two |
| 9376 | 2123181U, // TBNZW |
| 9377 | 2123181U, // TBNZX |
| 9378 | 2686491451U, // TBXQ_ZZZ_B |
| 9379 | 1612766011U, // TBXQ_ZZZ_D |
| 9380 | 2460031803U, // TBXQ_ZZZ_H |
| 9381 | 1881234235U, // TBXQ_ZZZ_S |
| 9382 | 2686493965U, // TBX_ZZZ_B |
| 9383 | 1612768525U, // TBX_ZZZ_D |
| 9384 | 2460034317U, // TBX_ZZZ_H |
| 9385 | 1881236749U, // TBX_ZZZ_S |
| 9386 | 3229754637U, // TBXv16i8Four |
| 9387 | 3229754637U, // TBXv16i8One |
| 9388 | 3229754637U, // TBXv16i8Three |
| 9389 | 3229754637U, // TBXv16i8Two |
| 9390 | 3242337549U, // TBXv8i8Four |
| 9391 | 3242337549U, // TBXv8i8One |
| 9392 | 3242337549U, // TBXv8i8Three |
| 9393 | 3242337549U, // TBXv8i8Two |
| 9394 | 2123165U, // TBZW |
| 9395 | 2123165U, // TBZX |
| 9396 | 1881163449U, // TCHANGEBri |
| 9397 | 2115257U, // TCHANGEBrr |
| 9398 | 1881165183U, // TCHANGEFri |
| 9399 | 2116991U, // TCHANGEFrr |
| 9400 | 3492273100U, // TENTER |
| 9401 | 1302404U, // TEXIT |
| 9402 | 24439U, // TRCIT |
| 9403 | 3491790900U, // TRN1_PPP_B |
| 9404 | 2686500916U, // TRN1_PPP_D |
| 9405 | 2443247668U, // TRN1_PPP_H |
| 9406 | 3760275508U, // TRN1_PPP_S |
| 9407 | 3491790900U, // TRN1_ZZZ_B |
| 9408 | 2686500916U, // TRN1_ZZZ_D |
| 9409 | 2443247668U, // TRN1_ZZZ_H |
| 9410 | 2475114548U, // TRN1_ZZZ_Q |
| 9411 | 3760275508U, // TRN1_ZZZ_S |
| 9412 | 1350664244U, // TRN1v16i8 |
| 9413 | 1352761396U, // TRN1v2i32 |
| 9414 | 1354858548U, // TRN1v2i64 |
| 9415 | 1356955700U, // TRN1v4i16 |
| 9416 | 1359052852U, // TRN1v4i32 |
| 9417 | 1361150004U, // TRN1v8i16 |
| 9418 | 1363247156U, // TRN1v8i8 |
| 9419 | 3491791320U, // TRN2_PPP_B |
| 9420 | 2686501336U, // TRN2_PPP_D |
| 9421 | 2443248088U, // TRN2_PPP_H |
| 9422 | 3760275928U, // TRN2_PPP_S |
| 9423 | 3491791320U, // TRN2_ZZZ_B |
| 9424 | 2686501336U, // TRN2_ZZZ_D |
| 9425 | 2443248088U, // TRN2_ZZZ_H |
| 9426 | 2475114968U, // TRN2_ZZZ_Q |
| 9427 | 3760275928U, // TRN2_ZZZ_S |
| 9428 | 1350664664U, // TRN2v16i8 |
| 9429 | 1352761816U, // TRN2v2i32 |
| 9430 | 1354858968U, // TRN2v2i64 |
| 9431 | 1356956120U, // TRN2v4i16 |
| 9432 | 1359053272U, // TRN2v4i32 |
| 9433 | 1361150424U, // TRN2v8i16 |
| 9434 | 1363247576U, // TRN2v8i8 |
| 9435 | 444934U, // TSB |
| 9436 | 1881196268U, // UABALB_ZZZ_D |
| 9437 | 2485192428U, // UABALB_ZZZ_H |
| 9438 | 2954970860U, // UABALB_ZZZ_S |
| 9439 | 1881202579U, // UABALT_ZZZ_D |
| 9440 | 2485198739U, // UABALT_ZZZ_H |
| 9441 | 2954977171U, // UABALT_ZZZ_S |
| 9442 | 2485195216U, // UABAL_ZZZ_BtoH |
| 9443 | 2954973648U, // UABAL_ZZZ_HtoS |
| 9444 | 1881199056U, // UABAL_ZZZ_StoD |
| 9445 | 3240231126U, // UABALv16i8_v8i16 |
| 9446 | 3233944016U, // UABALv2i32_v2i64 |
| 9447 | 3238138320U, // UABALv4i16_v4i32 |
| 9448 | 3233939670U, // UABALv4i32_v2i64 |
| 9449 | 3238133974U, // UABALv8i16_v4i32 |
| 9450 | 3240235472U, // UABALv8i8_v8i16 |
| 9451 | 2686485258U, // UABA_ZZZ_B |
| 9452 | 1612759818U, // UABA_ZZZ_D |
| 9453 | 2460025610U, // UABA_ZZZ_H |
| 9454 | 1881228042U, // UABA_ZZZ_S |
| 9455 | 3229745930U, // UABAv16i8 |
| 9456 | 3231843082U, // UABAv2i32 |
| 9457 | 3236037386U, // UABAv4i16 |
| 9458 | 3238134538U, // UABAv4i32 |
| 9459 | 3240231690U, // UABAv8i16 |
| 9460 | 3242328842U, // UABAv8i8 |
| 9461 | 3760244641U, // UABDLB_ZZZ_D |
| 9462 | 2462123937U, // UABDLB_ZZZ_H |
| 9463 | 2149664673U, // UABDLB_ZZZ_S |
| 9464 | 3760250875U, // UABDLT_ZZZ_D |
| 9465 | 2462130171U, // UABDLT_ZZZ_H |
| 9466 | 2149670907U, // UABDLT_ZZZ_S |
| 9467 | 1361150232U, // UABDLv16i8_v8i16 |
| 9468 | 1354863566U, // UABDLv2i32_v2i64 |
| 9469 | 1359057870U, // UABDLv4i16_v4i32 |
| 9470 | 1354858776U, // UABDLv4i32_v2i64 |
| 9471 | 1359053080U, // UABDLv8i16_v4i32 |
| 9472 | 1361155022U, // UABDLv8i8_v8i16 |
| 9473 | 807439292U, // UABD_ZPmZ_B |
| 9474 | 807455676U, // UABD_ZPmZ_D |
| 9475 | 543230908U, // UABD_ZPmZ_H |
| 9476 | 807488444U, // UABD_ZPmZ_S |
| 9477 | 1350667196U, // UABDv16i8 |
| 9478 | 1352764348U, // UABDv2i32 |
| 9479 | 1356958652U, // UABDv4i16 |
| 9480 | 1359055804U, // UABDv4i32 |
| 9481 | 1361152956U, // UABDv8i16 |
| 9482 | 1363250108U, // UABDv8i8 |
| 9483 | 807459146U, // UADALP_ZPmZ_D |
| 9484 | 543234378U, // UADALP_ZPmZ_H |
| 9485 | 807491914U, // UADALP_ZPmZ_S |
| 9486 | 3240237386U, // UADALPv16i8_v8i16 |
| 9487 | 3393329482U, // UADALPv2i32_v1i64 |
| 9488 | 3231848778U, // UADALPv4i16_v2i32 |
| 9489 | 3233945930U, // UADALPv4i32_v2i64 |
| 9490 | 3238140234U, // UADALPv8i16_v4i32 |
| 9491 | 3236043082U, // UADALPv8i8_v4i16 |
| 9492 | 3760244666U, // UADDLB_ZZZ_D |
| 9493 | 2462123962U, // UADDLB_ZZZ_H |
| 9494 | 2149664698U, // UADDLB_ZZZ_S |
| 9495 | 1361156442U, // UADDLPv16i8_v8i16 |
| 9496 | 1514248538U, // UADDLPv2i32_v1i64 |
| 9497 | 1352767834U, // UADDLPv4i16_v2i32 |
| 9498 | 1354864986U, // UADDLPv4i32_v2i64 |
| 9499 | 1359059290U, // UADDLPv8i16_v4i32 |
| 9500 | 1356962138U, // UADDLPv8i8_v4i16 |
| 9501 | 3760250891U, // UADDLT_ZZZ_D |
| 9502 | 2462130187U, // UADDLT_ZZZ_H |
| 9503 | 2149670923U, // UADDLT_ZZZ_S |
| 9504 | 1344299714U, // UADDLVv16i8v |
| 9505 | 1344299714U, // UADDLVv4i16v |
| 9506 | 1344299714U, // UADDLVv4i32v |
| 9507 | 1344299714U, // UADDLVv8i16v |
| 9508 | 1344299714U, // UADDLVv8i8v |
| 9509 | 1361150248U, // UADDLv16i8_v8i16 |
| 9510 | 1354863651U, // UADDLv2i32_v2i64 |
| 9511 | 1359057955U, // UADDLv4i16_v4i32 |
| 9512 | 1354858792U, // UADDLv4i32_v2i64 |
| 9513 | 1359053096U, // UADDLv8i16_v4i32 |
| 9514 | 1361155107U, // UADDLv8i8_v8i16 |
| 9515 | 606347926U, // UADDV_VPZ_B |
| 9516 | 579084950U, // UADDV_VPZ_D |
| 9517 | 581182102U, // UADDV_VPZ_H |
| 9518 | 562307734U, // UADDV_VPZ_S |
| 9519 | 2686503583U, // UADDWB_ZZZ_D |
| 9520 | 2443250335U, // UADDWB_ZZZ_H |
| 9521 | 3760278175U, // UADDWB_ZZZ_S |
| 9522 | 2686509604U, // UADDWT_ZZZ_D |
| 9523 | 2443256356U, // UADDWT_ZZZ_H |
| 9524 | 3760284196U, // UADDWT_ZZZ_S |
| 9525 | 1361150564U, // UADDWv16i8_v8i16 |
| 9526 | 1354867739U, // UADDWv2i32_v2i64 |
| 9527 | 1359062043U, // UADDWv4i16_v4i32 |
| 9528 | 1354859108U, // UADDWv4i32_v2i64 |
| 9529 | 1359053412U, // UADDWv8i16_v4i32 |
| 9530 | 1361159195U, // UADDWv8i8_v8i16 |
| 9531 | 2119444U, // UBFMWri |
| 9532 | 2119444U, // UBFMXri |
| 9533 | 2485279104U, // UCLAMP_VG2_2Z2Z_B |
| 9534 | 2458032512U, // UCLAMP_VG2_2Z2Z_D |
| 9535 | 2460146048U, // UCLAMP_VG2_2Z2Z_H |
| 9536 | 2441288064U, // UCLAMP_VG2_2Z2Z_S |
| 9537 | 2485279104U, // UCLAMP_VG4_4Z4Z_B |
| 9538 | 2458032512U, // UCLAMP_VG4_4Z4Z_D |
| 9539 | 2460146048U, // UCLAMP_VG4_4Z4Z_H |
| 9540 | 2441288064U, // UCLAMP_VG4_4Z4Z_S |
| 9541 | 2686491008U, // UCLAMP_ZZZ_B |
| 9542 | 1612765568U, // UCLAMP_ZZZ_D |
| 9543 | 2460031360U, // UCLAMP_ZZZ_H |
| 9544 | 1881233792U, // UCLAMP_ZZZ_S |
| 9545 | 2117019U, // UCVTFDSr |
| 9546 | 2117019U, // UCVTFHDr |
| 9547 | 2117019U, // UCVTFHSr |
| 9548 | 583082021U, // UCVTFLT_ZZ_BtoH |
| 9549 | 2149670949U, // UCVTFLT_ZZ_HtoS |
| 9550 | 3760250917U, // UCVTFLT_ZZ_StoD |
| 9551 | 2117019U, // UCVTFSDr |
| 9552 | 2117019U, // UCVTFSWDri |
| 9553 | 2117019U, // UCVTFSWHri |
| 9554 | 2117019U, // UCVTFSWSri |
| 9555 | 2117019U, // UCVTFSXDri |
| 9556 | 2117019U, // UCVTFSXHri |
| 9557 | 2117019U, // UCVTFSXSri |
| 9558 | 2117019U, // UCVTFUWDri |
| 9559 | 2117019U, // UCVTFUWHri |
| 9560 | 2117019U, // UCVTFUWSri |
| 9561 | 2117019U, // UCVTFUXDri |
| 9562 | 2117019U, // UCVTFUXHri |
| 9563 | 2117019U, // UCVTFUXSri |
| 9564 | 572722587U, // UCVTF_2Z2Z_StoS |
| 9565 | 572722587U, // UCVTF_4Z4Z_StoS |
| 9566 | 270585243U, // UCVTF_ZPmZ_DtoD |
| 9567 | 541134235U, // UCVTF_ZPmZ_DtoH |
| 9568 | 270618011U, // UCVTF_ZPmZ_DtoS |
| 9569 | 541134235U, // UCVTF_ZPmZ_HtoH |
| 9570 | 270585243U, // UCVTF_ZPmZ_StoD |
| 9571 | 541134235U, // UCVTF_ZPmZ_StoH |
| 9572 | 270618011U, // UCVTF_ZPmZ_StoS |
| 9573 | 807456155U, // UCVTF_ZPzZ_DtoD |
| 9574 | 1080102299U, // UCVTF_ZPzZ_DtoH |
| 9575 | 807488923U, // UCVTF_ZPzZ_DtoS |
| 9576 | 1080102299U, // UCVTF_ZPzZ_HtoH |
| 9577 | 807456155U, // UCVTF_ZPzZ_StoD |
| 9578 | 1080102299U, // UCVTF_ZPzZ_StoH |
| 9579 | 807488923U, // UCVTF_ZPzZ_StoS |
| 9580 | 583077275U, // UCVTF_ZZ_BtoH |
| 9581 | 2149666203U, // UCVTF_ZZ_HtoS |
| 9582 | 3760246171U, // UCVTF_ZZ_StoD |
| 9583 | 2117019U, // UCVTFd |
| 9584 | 2117019U, // UCVTFh |
| 9585 | 2117019U, // UCVTFs |
| 9586 | 2117019U, // UCVTFv1i16 |
| 9587 | 2117019U, // UCVTFv1i32 |
| 9588 | 2117019U, // UCVTFv1i64 |
| 9589 | 1352764827U, // UCVTFv2f32 |
| 9590 | 1354861979U, // UCVTFv2f64 |
| 9591 | 1352764827U, // UCVTFv2i32_shift |
| 9592 | 1354861979U, // UCVTFv2i64_shift |
| 9593 | 1356959131U, // UCVTFv4f16 |
| 9594 | 1359056283U, // UCVTFv4f32 |
| 9595 | 1356959131U, // UCVTFv4i16_shift |
| 9596 | 1359056283U, // UCVTFv4i32_shift |
| 9597 | 1361153435U, // UCVTFv8f16 |
| 9598 | 1361153435U, // UCVTFv8i16_shift |
| 9599 | 19834U, // UDF |
| 9600 | 807460096U, // UDIVR_ZPmZ_D |
| 9601 | 807492864U, // UDIVR_ZPmZ_S |
| 9602 | 2122420U, // UDIVWr |
| 9603 | 2122420U, // UDIVXr |
| 9604 | 807461556U, // UDIV_ZPmZ_D |
| 9605 | 807494324U, // UDIV_ZPmZ_S |
| 9606 | 4064518493U, // UDOT_VG2_M2Z2Z_BtoS |
| 9607 | 4064502109U, // UDOT_VG2_M2Z2Z_HtoD |
| 9608 | 4064518493U, // UDOT_VG2_M2Z2Z_HtoS |
| 9609 | 4064518493U, // UDOT_VG2_M2ZZI_BToS |
| 9610 | 4064518493U, // UDOT_VG2_M2ZZI_HToS |
| 9611 | 4064502109U, // UDOT_VG2_M2ZZI_HtoD |
| 9612 | 4064518493U, // UDOT_VG2_M2ZZ_BtoS |
| 9613 | 4064502109U, // UDOT_VG2_M2ZZ_HtoD |
| 9614 | 4064518493U, // UDOT_VG2_M2ZZ_HtoS |
| 9615 | 37986653U, // UDOT_VG4_M4Z4Z_BtoS |
| 9616 | 37970269U, // UDOT_VG4_M4Z4Z_HtoD |
| 9617 | 37986653U, // UDOT_VG4_M4Z4Z_HtoS |
| 9618 | 37986653U, // UDOT_VG4_M4ZZI_BtoS |
| 9619 | 37986653U, // UDOT_VG4_M4ZZI_HToS |
| 9620 | 37970269U, // UDOT_VG4_M4ZZI_HtoD |
| 9621 | 37986653U, // UDOT_VG4_M4ZZ_BtoS |
| 9622 | 37970269U, // UDOT_VG4_M4ZZ_HtoD |
| 9623 | 37986653U, // UDOT_VG4_M4ZZ_HtoS |
| 9624 | 2485199197U, // UDOT_ZZZI_BtoH |
| 9625 | 2686542173U, // UDOT_ZZZI_BtoS |
| 9626 | 2954944861U, // UDOT_ZZZI_HtoD |
| 9627 | 2954977629U, // UDOT_ZZZI_HtoS |
| 9628 | 2485199197U, // UDOT_ZZZ_BtoH |
| 9629 | 2686542173U, // UDOT_ZZZ_BtoS |
| 9630 | 2954944861U, // UDOT_ZZZ_HtoD |
| 9631 | 2954977629U, // UDOT_ZZZ_HtoS |
| 9632 | 3238142301U, // UDOTlanev16i8 |
| 9633 | 3231850845U, // UDOTlanev8i8 |
| 9634 | 3238142301U, // UDOTv16i8 |
| 9635 | 3231850845U, // UDOTv8i8 |
| 9636 | 807439416U, // UHADD_ZPmZ_B |
| 9637 | 807455800U, // UHADD_ZPmZ_D |
| 9638 | 543231032U, // UHADD_ZPmZ_H |
| 9639 | 807488568U, // UHADD_ZPmZ_S |
| 9640 | 1350667320U, // UHADDv16i8 |
| 9641 | 1352764472U, // UHADDv2i32 |
| 9642 | 1356958776U, // UHADDv4i16 |
| 9643 | 1359055928U, // UHADDv4i32 |
| 9644 | 1361153080U, // UHADDv8i16 |
| 9645 | 1363250232U, // UHADDv8i8 |
| 9646 | 807443322U, // UHSUBR_ZPmZ_B |
| 9647 | 807459706U, // UHSUBR_ZPmZ_D |
| 9648 | 543234938U, // UHSUBR_ZPmZ_H |
| 9649 | 807492474U, // UHSUBR_ZPmZ_S |
| 9650 | 807438941U, // UHSUB_ZPmZ_B |
| 9651 | 807455325U, // UHSUB_ZPmZ_D |
| 9652 | 543230557U, // UHSUB_ZPmZ_H |
| 9653 | 807488093U, // UHSUB_ZPmZ_S |
| 9654 | 1350666845U, // UHSUBv16i8 |
| 9655 | 1352763997U, // UHSUBv2i32 |
| 9656 | 1356958301U, // UHSUBv4i16 |
| 9657 | 1359055453U, // UHSUBv4i32 |
| 9658 | 1361152605U, // UHSUBv8i16 |
| 9659 | 1363249757U, // UHSUBv8i8 |
| 9660 | 2118667U, // UMADDLrrr |
| 9661 | 807443119U, // UMAXP_ZPmZ_B |
| 9662 | 807459503U, // UMAXP_ZPmZ_D |
| 9663 | 543234735U, // UMAXP_ZPmZ_H |
| 9664 | 807492271U, // UMAXP_ZPmZ_S |
| 9665 | 1350671023U, // UMAXPv16i8 |
| 9666 | 1352768175U, // UMAXPv2i32 |
| 9667 | 1356962479U, // UMAXPv4i16 |
| 9668 | 1359059631U, // UMAXPv4i32 |
| 9669 | 1361156783U, // UMAXPv8i16 |
| 9670 | 1363253935U, // UMAXPv8i8 |
| 9671 | 813802338U, // UMAXQV_VPZ_B |
| 9672 | 817996642U, // UMAXQV_VPZ_D |
| 9673 | 824288098U, // UMAXQV_VPZ_H |
| 9674 | 822190946U, // UMAXQV_VPZ_S |
| 9675 | 254846U, // UMAXV_VPZ_B |
| 9676 | 579085182U, // UMAXV_VPZ_D |
| 9677 | 581198718U, // UMAXV_VPZ_H |
| 9678 | 562340734U, // UMAXV_VPZ_S |
| 9679 | 1344299902U, // UMAXVv16i8v |
| 9680 | 1344299902U, // UMAXVv4i16v |
| 9681 | 1344299902U, // UMAXVv4i32v |
| 9682 | 1344299902U, // UMAXVv8i16v |
| 9683 | 1344299902U, // UMAXVv8i8v |
| 9684 | 2123015U, // UMAXWri |
| 9685 | 2123015U, // UMAXWrr |
| 9686 | 2123015U, // UMAXXri |
| 9687 | 2123015U, // UMAXXrr |
| 9688 | 2445436167U, // UMAX_VG2_2Z2Z_B |
| 9689 | 2447549703U, // UMAX_VG2_2Z2Z_D |
| 9690 | 2449663239U, // UMAX_VG2_2Z2Z_H |
| 9691 | 2451776775U, // UMAX_VG2_2Z2Z_S |
| 9692 | 2445436167U, // UMAX_VG2_2ZZ_B |
| 9693 | 2447549703U, // UMAX_VG2_2ZZ_D |
| 9694 | 2449663239U, // UMAX_VG2_2ZZ_H |
| 9695 | 2451776775U, // UMAX_VG2_2ZZ_S |
| 9696 | 2445436167U, // UMAX_VG4_4Z4Z_B |
| 9697 | 2447549703U, // UMAX_VG4_4Z4Z_D |
| 9698 | 2449663239U, // UMAX_VG4_4Z4Z_H |
| 9699 | 2451776775U, // UMAX_VG4_4Z4Z_S |
| 9700 | 2445436167U, // UMAX_VG4_4ZZ_B |
| 9701 | 2447549703U, // UMAX_VG4_4ZZ_D |
| 9702 | 2449663239U, // UMAX_VG4_4ZZ_H |
| 9703 | 2451776775U, // UMAX_VG4_4ZZ_S |
| 9704 | 3491800327U, // UMAX_ZI_B |
| 9705 | 2686510343U, // UMAX_ZI_D |
| 9706 | 2443257095U, // UMAX_ZI_H |
| 9707 | 3760284935U, // UMAX_ZI_S |
| 9708 | 807445767U, // UMAX_ZPmZ_B |
| 9709 | 807462151U, // UMAX_ZPmZ_D |
| 9710 | 543237383U, // UMAX_ZPmZ_H |
| 9711 | 807494919U, // UMAX_ZPmZ_S |
| 9712 | 1350673671U, // UMAXv16i8 |
| 9713 | 1352770823U, // UMAXv2i32 |
| 9714 | 1356965127U, // UMAXv4i16 |
| 9715 | 1359062279U, // UMAXv4i32 |
| 9716 | 1361159431U, // UMAXv8i16 |
| 9717 | 1363256583U, // UMAXv8i8 |
| 9718 | 807442875U, // UMINP_ZPmZ_B |
| 9719 | 807459259U, // UMINP_ZPmZ_D |
| 9720 | 543234491U, // UMINP_ZPmZ_H |
| 9721 | 807492027U, // UMINP_ZPmZ_S |
| 9722 | 1350670779U, // UMINPv16i8 |
| 9723 | 1352767931U, // UMINPv2i32 |
| 9724 | 1356962235U, // UMINPv4i16 |
| 9725 | 1359059387U, // UMINPv4i32 |
| 9726 | 1361156539U, // UMINPv8i16 |
| 9727 | 1363253691U, // UMINPv8i8 |
| 9728 | 813802307U, // UMINQV_VPZ_B |
| 9729 | 817996611U, // UMINQV_VPZ_D |
| 9730 | 824288067U, // UMINQV_VPZ_H |
| 9731 | 822190915U, // UMINQV_VPZ_S |
| 9732 | 254698U, // UMINV_VPZ_B |
| 9733 | 579085034U, // UMINV_VPZ_D |
| 9734 | 581198570U, // UMINV_VPZ_H |
| 9735 | 562340586U, // UMINV_VPZ_S |
| 9736 | 1344299754U, // UMINVv16i8v |
| 9737 | 1344299754U, // UMINVv4i16v |
| 9738 | 1344299754U, // UMINVv4i32v |
| 9739 | 1344299754U, // UMINVv8i16v |
| 9740 | 1344299754U, // UMINVv8i8v |
| 9741 | 2119681U, // UMINWri |
| 9742 | 2119681U, // UMINWrr |
| 9743 | 2119681U, // UMINXri |
| 9744 | 2119681U, // UMINXrr |
| 9745 | 2445432833U, // UMIN_VG2_2Z2Z_B |
| 9746 | 2447546369U, // UMIN_VG2_2Z2Z_D |
| 9747 | 2449659905U, // UMIN_VG2_2Z2Z_H |
| 9748 | 2451773441U, // UMIN_VG2_2Z2Z_S |
| 9749 | 2445432833U, // UMIN_VG2_2ZZ_B |
| 9750 | 2447546369U, // UMIN_VG2_2ZZ_D |
| 9751 | 2449659905U, // UMIN_VG2_2ZZ_H |
| 9752 | 2451773441U, // UMIN_VG2_2ZZ_S |
| 9753 | 2445432833U, // UMIN_VG4_4Z4Z_B |
| 9754 | 2447546369U, // UMIN_VG4_4Z4Z_D |
| 9755 | 2449659905U, // UMIN_VG4_4Z4Z_H |
| 9756 | 2451773441U, // UMIN_VG4_4Z4Z_S |
| 9757 | 2445432833U, // UMIN_VG4_4ZZ_B |
| 9758 | 2447546369U, // UMIN_VG4_4ZZ_D |
| 9759 | 2449659905U, // UMIN_VG4_4ZZ_H |
| 9760 | 2451773441U, // UMIN_VG4_4ZZ_S |
| 9761 | 3491796993U, // UMIN_ZI_B |
| 9762 | 2686507009U, // UMIN_ZI_D |
| 9763 | 2443253761U, // UMIN_ZI_H |
| 9764 | 3760281601U, // UMIN_ZI_S |
| 9765 | 807442433U, // UMIN_ZPmZ_B |
| 9766 | 807458817U, // UMIN_ZPmZ_D |
| 9767 | 543234049U, // UMIN_ZPmZ_H |
| 9768 | 807491585U, // UMIN_ZPmZ_S |
| 9769 | 1350670337U, // UMINv16i8 |
| 9770 | 1352767489U, // UMINv2i32 |
| 9771 | 1356961793U, // UMINv4i16 |
| 9772 | 1359058945U, // UMINv4i32 |
| 9773 | 1361156097U, // UMINv8i16 |
| 9774 | 1363253249U, // UMINv8i8 |
| 9775 | 1881196313U, // UMLALB_ZZZI_D |
| 9776 | 2954970905U, // UMLALB_ZZZI_S |
| 9777 | 1881196313U, // UMLALB_ZZZ_D |
| 9778 | 2485192473U, // UMLALB_ZZZ_H |
| 9779 | 2954970905U, // UMLALB_ZZZ_S |
| 9780 | 1415812233U, // UMLALL_MZZI_BtoS |
| 9781 | 1415795849U, // UMLALL_MZZI_HtoD |
| 9782 | 1415812233U, // UMLALL_MZZ_BtoS |
| 9783 | 1415795849U, // UMLALL_MZZ_HtoD |
| 9784 | 4100166793U, // UMLALL_VG2_M2Z2Z_BtoS |
| 9785 | 4100150409U, // UMLALL_VG2_M2Z2Z_HtoD |
| 9786 | 4100166793U, // UMLALL_VG2_M2ZZI_BtoS |
| 9787 | 4100150409U, // UMLALL_VG2_M2ZZI_HtoD |
| 9788 | 3026424969U, // UMLALL_VG2_M2ZZ_BtoS |
| 9789 | 3026408585U, // UMLALL_VG2_M2ZZ_HtoD |
| 9790 | 73634953U, // UMLALL_VG4_M4Z4Z_BtoS |
| 9791 | 73618569U, // UMLALL_VG4_M4Z4Z_HtoD |
| 9792 | 73634953U, // UMLALL_VG4_M4ZZI_BtoS |
| 9793 | 73618569U, // UMLALL_VG4_M4ZZI_HtoD |
| 9794 | 3294860425U, // UMLALL_VG4_M4ZZ_BtoS |
| 9795 | 3294844041U, // UMLALL_VG4_M4ZZ_HtoD |
| 9796 | 1881202614U, // UMLALT_ZZZI_D |
| 9797 | 2954977206U, // UMLALT_ZZZI_S |
| 9798 | 1881202614U, // UMLALT_ZZZ_D |
| 9799 | 2485198774U, // UMLALT_ZZZ_H |
| 9800 | 2954977206U, // UMLALT_ZZZ_S |
| 9801 | 1390645790U, // UMLAL_MZZI_HtoS |
| 9802 | 1390645790U, // UMLAL_MZZ_HtoS |
| 9803 | 4075000350U, // UMLAL_VG2_M2Z2Z_HtoS |
| 9804 | 4075000350U, // UMLAL_VG2_M2ZZI_S |
| 9805 | 4075000350U, // UMLAL_VG2_M2ZZ_HtoS |
| 9806 | 48468510U, // UMLAL_VG4_M4Z4Z_HtoS |
| 9807 | 48468510U, // UMLAL_VG4_M4ZZI_HtoS |
| 9808 | 48468510U, // UMLAL_VG4_M4ZZ_HtoS |
| 9809 | 3240231160U, // UMLALv16i8_v8i16 |
| 9810 | 3233944094U, // UMLALv2i32_indexed |
| 9811 | 3233944094U, // UMLALv2i32_v2i64 |
| 9812 | 3238138398U, // UMLALv4i16_indexed |
| 9813 | 3238138398U, // UMLALv4i16_v4i32 |
| 9814 | 3233939704U, // UMLALv4i32_indexed |
| 9815 | 3233939704U, // UMLALv4i32_v2i64 |
| 9816 | 3238134008U, // UMLALv8i16_indexed |
| 9817 | 3238134008U, // UMLALv8i16_v4i32 |
| 9818 | 3240235550U, // UMLALv8i8_v8i16 |
| 9819 | 1881196611U, // UMLSLB_ZZZI_D |
| 9820 | 2954971203U, // UMLSLB_ZZZI_S |
| 9821 | 1881196611U, // UMLSLB_ZZZ_D |
| 9822 | 2485192771U, // UMLSLB_ZZZ_H |
| 9823 | 2954971203U, // UMLSLB_ZZZ_S |
| 9824 | 1415812263U, // UMLSLL_MZZI_BtoS |
| 9825 | 1415795879U, // UMLSLL_MZZI_HtoD |
| 9826 | 1415812263U, // UMLSLL_MZZ_BtoS |
| 9827 | 1415795879U, // UMLSLL_MZZ_HtoD |
| 9828 | 4100166823U, // UMLSLL_VG2_M2Z2Z_BtoS |
| 9829 | 4100150439U, // UMLSLL_VG2_M2Z2Z_HtoD |
| 9830 | 4100166823U, // UMLSLL_VG2_M2ZZI_BtoS |
| 9831 | 4100150439U, // UMLSLL_VG2_M2ZZI_HtoD |
| 9832 | 3026424999U, // UMLSLL_VG2_M2ZZ_BtoS |
| 9833 | 3026408615U, // UMLSLL_VG2_M2ZZ_HtoD |
| 9834 | 73634983U, // UMLSLL_VG4_M4Z4Z_BtoS |
| 9835 | 73618599U, // UMLSLL_VG4_M4Z4Z_HtoD |
| 9836 | 73634983U, // UMLSLL_VG4_M4ZZI_BtoS |
| 9837 | 73618599U, // UMLSLL_VG4_M4ZZI_HtoD |
| 9838 | 3294860455U, // UMLSLL_VG4_M4ZZ_BtoS |
| 9839 | 3294844071U, // UMLSLL_VG4_M4ZZ_HtoD |
| 9840 | 1881202845U, // UMLSLT_ZZZI_D |
| 9841 | 2954977437U, // UMLSLT_ZZZI_S |
| 9842 | 1881202845U, // UMLSLT_ZZZ_D |
| 9843 | 2485199005U, // UMLSLT_ZZZ_H |
| 9844 | 2954977437U, // UMLSLT_ZZZ_S |
| 9845 | 1390646854U, // UMLSL_MZZI_HtoS |
| 9846 | 1390646854U, // UMLSL_MZZ_HtoS |
| 9847 | 4075001414U, // UMLSL_VG2_M2Z2Z_HtoS |
| 9848 | 4075001414U, // UMLSL_VG2_M2ZZI_S |
| 9849 | 4075001414U, // UMLSL_VG2_M2ZZ_HtoS |
| 9850 | 48469574U, // UMLSL_VG4_M4Z4Z_HtoS |
| 9851 | 48469574U, // UMLSL_VG4_M4ZZI_HtoS |
| 9852 | 48469574U, // UMLSL_VG4_M4ZZ_HtoS |
| 9853 | 3240231292U, // UMLSLv16i8_v8i16 |
| 9854 | 3233945158U, // UMLSLv2i32_indexed |
| 9855 | 3233945158U, // UMLSLv2i32_v2i64 |
| 9856 | 3238139462U, // UMLSLv4i16_indexed |
| 9857 | 3238139462U, // UMLSLv4i16_v4i32 |
| 9858 | 3233939836U, // UMLSLv4i32_indexed |
| 9859 | 3233939836U, // UMLSLv4i32_v2i64 |
| 9860 | 3238134140U, // UMLSLv8i16_indexed |
| 9861 | 3238134140U, // UMLSLv8i16_v4i32 |
| 9862 | 3240236614U, // UMLSLv8i8_v8i16 |
| 9863 | 3238134658U, // UMMLA |
| 9864 | 2686534530U, // UMMLA_ZZZ |
| 9865 | 3565273832U, // UMOP4A_M2Z2Z_BToS |
| 9866 | 1661059816U, // UMOP4A_M2Z2Z_HToS |
| 9867 | 1661059816U, // UMOP4A_M2Z2Z_HtoD |
| 9868 | 75612904U, // UMOP4A_M2ZZ_BToS |
| 9869 | 1929495272U, // UMOP4A_M2ZZ_HToS |
| 9870 | 1929495272U, // UMOP4A_M2ZZ_HtoD |
| 9871 | 2485240552U, // UMOP4A_MZ2Z_BToS |
| 9872 | 2460074728U, // UMOP4A_MZ2Z_HToS |
| 9873 | 2460074728U, // UMOP4A_MZ2Z_HtoD |
| 9874 | 2485240552U, // UMOP4A_MZZ_BToS |
| 9875 | 2460074728U, // UMOP4A_MZZ_HToS |
| 9876 | 2460074728U, // UMOP4A_MZZ_HtoD |
| 9877 | 3565280603U, // UMOP4S_M2Z2Z_BToS |
| 9878 | 1661066587U, // UMOP4S_M2Z2Z_HToS |
| 9879 | 1661066587U, // UMOP4S_M2Z2Z_HtoD |
| 9880 | 75619675U, // UMOP4S_M2ZZ_BToS |
| 9881 | 1929502043U, // UMOP4S_M2ZZ_HToS |
| 9882 | 1929502043U, // UMOP4S_M2ZZ_HtoD |
| 9883 | 2485247323U, // UMOP4S_MZ2Z_BToS |
| 9884 | 2460081499U, // UMOP4S_MZ2Z_HToS |
| 9885 | 2460081499U, // UMOP4S_MZ2Z_HtoD |
| 9886 | 2485247323U, // UMOP4S_MZZ_BToS |
| 9887 | 2460081499U, // UMOP4S_MZZ_HToS |
| 9888 | 2460081499U, // UMOP4S_MZZ_HtoD |
| 9889 | 541180957U, // UMOPA_MPPZZ_D |
| 9890 | 541180957U, // UMOPA_MPPZZ_HtoS |
| 9891 | 541180957U, // UMOPA_MPPZZ_S |
| 9892 | 541187696U, // UMOPS_MPPZZ_D |
| 9893 | 541187696U, // UMOPS_MPPZZ_HtoS |
| 9894 | 541187696U, // UMOPS_MPPZZ_S |
| 9895 | 1344299786U, // UMOVvi16 |
| 9896 | 1344299786U, // UMOVvi16_idx0 |
| 9897 | 1344299786U, // UMOVvi32 |
| 9898 | 1344299786U, // UMOVvi32_idx0 |
| 9899 | 1344299786U, // UMOVvi64 |
| 9900 | 1344299786U, // UMOVvi64_idx0 |
| 9901 | 1344299786U, // UMOVvi8 |
| 9902 | 1344299786U, // UMOVvi8_idx0 |
| 9903 | 2118577U, // UMSUBLrrr |
| 9904 | 807440343U, // UMULH_ZPmZ_B |
| 9905 | 807456727U, // UMULH_ZPmZ_D |
| 9906 | 543231959U, // UMULH_ZPmZ_H |
| 9907 | 807489495U, // UMULH_ZPmZ_S |
| 9908 | 3491794903U, // UMULH_ZZZ_B |
| 9909 | 2686504919U, // UMULH_ZZZ_D |
| 9910 | 2443251671U, // UMULH_ZZZ_H |
| 9911 | 3760279511U, // UMULH_ZZZ_S |
| 9912 | 2117591U, // UMULHrr |
| 9913 | 3760244716U, // UMULLB_ZZZI_D |
| 9914 | 2149664748U, // UMULLB_ZZZI_S |
| 9915 | 3760244716U, // UMULLB_ZZZ_D |
| 9916 | 2462124012U, // UMULLB_ZZZ_H |
| 9917 | 2149664748U, // UMULLB_ZZZ_S |
| 9918 | 3760250973U, // UMULLT_ZZZI_D |
| 9919 | 2149671005U, // UMULLT_ZZZI_S |
| 9920 | 3760250973U, // UMULLT_ZZZ_D |
| 9921 | 2462130269U, // UMULLT_ZZZ_H |
| 9922 | 2149671005U, // UMULLT_ZZZ_S |
| 9923 | 1361150298U, // UMULLv16i8_v8i16 |
| 9924 | 1354863814U, // UMULLv2i32_indexed |
| 9925 | 1354863814U, // UMULLv2i32_v2i64 |
| 9926 | 1359058118U, // UMULLv4i16_indexed |
| 9927 | 1359058118U, // UMULLv4i16_v4i32 |
| 9928 | 1354858842U, // UMULLv4i32_indexed |
| 9929 | 1354858842U, // UMULLv4i32_v2i64 |
| 9930 | 1359053146U, // UMULLv8i16_indexed |
| 9931 | 1359053146U, // UMULLv8i16_v4i32 |
| 9932 | 1361155270U, // UMULLv8i8_v8i16 |
| 9933 | 3491794007U, // UQADD_ZI_B |
| 9934 | 2686504023U, // UQADD_ZI_D |
| 9935 | 2443250775U, // UQADD_ZI_H |
| 9936 | 3760278615U, // UQADD_ZI_S |
| 9937 | 807439447U, // UQADD_ZPmZ_B |
| 9938 | 807455831U, // UQADD_ZPmZ_D |
| 9939 | 543231063U, // UQADD_ZPmZ_H |
| 9940 | 807488599U, // UQADD_ZPmZ_S |
| 9941 | 3491794007U, // UQADD_ZZZ_B |
| 9942 | 2686504023U, // UQADD_ZZZ_D |
| 9943 | 2443250775U, // UQADD_ZZZ_H |
| 9944 | 3760278615U, // UQADD_ZZZ_S |
| 9945 | 1350667351U, // UQADDv16i8 |
| 9946 | 2116695U, // UQADDv1i16 |
| 9947 | 2116695U, // UQADDv1i32 |
| 9948 | 2116695U, // UQADDv1i64 |
| 9949 | 2116695U, // UQADDv1i8 |
| 9950 | 1352764503U, // UQADDv2i32 |
| 9951 | 1354861655U, // UQADDv2i64 |
| 9952 | 1356958807U, // UQADDv4i16 |
| 9953 | 1359055959U, // UQADDv4i32 |
| 9954 | 1361153111U, // UQADDv8i16 |
| 9955 | 1363250263U, // UQADDv8i8 |
| 9956 | 572594272U, // UQCVTN_Z2Z_StoH |
| 9957 | 568399968U, // UQCVTN_Z4Z_DtoH |
| 9958 | 1881184352U, // UQCVTN_Z4Z_StoB |
| 9959 | 572596735U, // UQCVT_Z2Z_StoH |
| 9960 | 568402431U, // UQCVT_Z4Z_DtoH |
| 9961 | 1881186815U, // UQCVT_Z4Z_StoB |
| 9962 | 2115211U, // UQDECB_WPiI |
| 9963 | 2115211U, // UQDECB_XPiI |
| 9964 | 2116561U, // UQDECD_WPiI |
| 9965 | 2116561U, // UQDECD_XPiI |
| 9966 | 2149329U, // UQDECD_ZPiI |
| 9967 | 2117342U, // UQDECH_WPiI |
| 9968 | 2117342U, // UQDECH_XPiI |
| 9969 | 52498142U, // UQDECH_ZPiI |
| 9970 | 3491780877U, // UQDECP_WP_B |
| 9971 | 2686474509U, // UQDECP_WP_D |
| 9972 | 2149603597U, // UQDECP_WP_H |
| 9973 | 3760216333U, // UQDECP_WP_S |
| 9974 | 3491780877U, // UQDECP_XP_B |
| 9975 | 2686474509U, // UQDECP_XP_D |
| 9976 | 2149603597U, // UQDECP_XP_H |
| 9977 | 3760216333U, // UQDECP_XP_S |
| 9978 | 1612765453U, // UQDECP_ZP_D |
| 9979 | 580983053U, // UQDECP_ZP_H |
| 9980 | 1881233677U, // UQDECP_ZP_S |
| 9981 | 2122748U, // UQDECW_WPiI |
| 9982 | 2122748U, // UQDECW_XPiI |
| 9983 | 2188284U, // UQDECW_ZPiI |
| 9984 | 2115227U, // UQINCB_WPiI |
| 9985 | 2115227U, // UQINCB_XPiI |
| 9986 | 2116577U, // UQINCD_WPiI |
| 9987 | 2116577U, // UQINCD_XPiI |
| 9988 | 2149345U, // UQINCD_ZPiI |
| 9989 | 2117358U, // UQINCH_WPiI |
| 9990 | 2117358U, // UQINCH_XPiI |
| 9991 | 52498158U, // UQINCH_ZPiI |
| 9992 | 3491780893U, // UQINCP_WP_B |
| 9993 | 2686474525U, // UQINCP_WP_D |
| 9994 | 2149603613U, // UQINCP_WP_H |
| 9995 | 3760216349U, // UQINCP_WP_S |
| 9996 | 3491780893U, // UQINCP_XP_B |
| 9997 | 2686474525U, // UQINCP_XP_D |
| 9998 | 2149603613U, // UQINCP_XP_H |
| 9999 | 3760216349U, // UQINCP_XP_S |
| 10000 | 1612765469U, // UQINCP_ZP_D |
| 10001 | 580983069U, // UQINCP_ZP_H |
| 10002 | 1881233693U, // UQINCP_ZP_S |
| 10003 | 2122764U, // UQINCW_WPiI |
| 10004 | 2122764U, // UQINCW_XPiI |
| 10005 | 2188300U, // UQINCW_ZPiI |
| 10006 | 807443530U, // UQRSHLR_ZPmZ_B |
| 10007 | 807459914U, // UQRSHLR_ZPmZ_D |
| 10008 | 543235146U, // UQRSHLR_ZPmZ_H |
| 10009 | 807492682U, // UQRSHLR_ZPmZ_S |
| 10010 | 807441493U, // UQRSHL_ZPmZ_B |
| 10011 | 807457877U, // UQRSHL_ZPmZ_D |
| 10012 | 543233109U, // UQRSHL_ZPmZ_H |
| 10013 | 807490645U, // UQRSHL_ZPmZ_S |
| 10014 | 1350669397U, // UQRSHLv16i8 |
| 10015 | 2118741U, // UQRSHLv1i16 |
| 10016 | 2118741U, // UQRSHLv1i32 |
| 10017 | 2118741U, // UQRSHLv1i64 |
| 10018 | 2118741U, // UQRSHLv1i8 |
| 10019 | 1352766549U, // UQRSHLv2i32 |
| 10020 | 1354863701U, // UQRSHLv2i64 |
| 10021 | 1356960853U, // UQRSHLv4i16 |
| 10022 | 1359058005U, // UQRSHLv4i32 |
| 10023 | 1361155157U, // UQRSHLv8i16 |
| 10024 | 1363252309U, // UQRSHLv8i8 |
| 10025 | 2149615789U, // UQRSHRNB_ZZI_B |
| 10026 | 2439055533U, // UQRSHRNB_ZZI_H |
| 10027 | 2686535853U, // UQRSHRNB_ZZI_S |
| 10028 | 2954928382U, // UQRSHRNT_ZZI_B |
| 10029 | 2441158910U, // UQRSHRNT_ZZI_H |
| 10030 | 1612800254U, // UQRSHRNT_ZZI_S |
| 10031 | 1881184305U, // UQRSHRN_VG4_Z4ZI_B |
| 10032 | 2447448113U, // UQRSHRN_VG4_Z4ZI_H |
| 10033 | 1075877937U, // UQRSHRN_Z2ZI_HtoB |
| 10034 | 2451642417U, // UQRSHRN_Z2ZI_StoH |
| 10035 | 2119729U, // UQRSHRNb |
| 10036 | 2119729U, // UQRSHRNh |
| 10037 | 2119729U, // UQRSHRNs |
| 10038 | 3229745614U, // UQRSHRNv16i8_shift |
| 10039 | 1352767537U, // UQRSHRNv2i32_shift |
| 10040 | 1356961841U, // UQRSHRNv4i16_shift |
| 10041 | 3238134222U, // UQRSHRNv4i32_shift |
| 10042 | 3240231374U, // UQRSHRNv8i16_shift |
| 10043 | 1363253297U, // UQRSHRNv8i8_shift |
| 10044 | 2451643370U, // UQRSHR_VG2_Z2ZI_H |
| 10045 | 1881185258U, // UQRSHR_VG4_Z4ZI_B |
| 10046 | 2447449066U, // UQRSHR_VG4_Z4ZI_H |
| 10047 | 807443513U, // UQSHLR_ZPmZ_B |
| 10048 | 807459897U, // UQSHLR_ZPmZ_D |
| 10049 | 543235129U, // UQSHLR_ZPmZ_H |
| 10050 | 807492665U, // UQSHLR_ZPmZ_S |
| 10051 | 807441478U, // UQSHL_ZPmI_B |
| 10052 | 807457862U, // UQSHL_ZPmI_D |
| 10053 | 543233094U, // UQSHL_ZPmI_H |
| 10054 | 807490630U, // UQSHL_ZPmI_S |
| 10055 | 807441478U, // UQSHL_ZPmZ_B |
| 10056 | 807457862U, // UQSHL_ZPmZ_D |
| 10057 | 543233094U, // UQSHL_ZPmZ_H |
| 10058 | 807490630U, // UQSHL_ZPmZ_S |
| 10059 | 2118726U, // UQSHLb |
| 10060 | 2118726U, // UQSHLd |
| 10061 | 2118726U, // UQSHLh |
| 10062 | 2118726U, // UQSHLs |
| 10063 | 1350669382U, // UQSHLv16i8 |
| 10064 | 1350669382U, // UQSHLv16i8_shift |
| 10065 | 2118726U, // UQSHLv1i16 |
| 10066 | 2118726U, // UQSHLv1i32 |
| 10067 | 2118726U, // UQSHLv1i64 |
| 10068 | 2118726U, // UQSHLv1i8 |
| 10069 | 1352766534U, // UQSHLv2i32 |
| 10070 | 1352766534U, // UQSHLv2i32_shift |
| 10071 | 1354863686U, // UQSHLv2i64 |
| 10072 | 1354863686U, // UQSHLv2i64_shift |
| 10073 | 1356960838U, // UQSHLv4i16 |
| 10074 | 1356960838U, // UQSHLv4i16_shift |
| 10075 | 1359057990U, // UQSHLv4i32 |
| 10076 | 1359057990U, // UQSHLv4i32_shift |
| 10077 | 1361155142U, // UQSHLv8i16 |
| 10078 | 1361155142U, // UQSHLv8i16_shift |
| 10079 | 1363252294U, // UQSHLv8i8 |
| 10080 | 1363252294U, // UQSHLv8i8_shift |
| 10081 | 2149615770U, // UQSHRNB_ZZI_B |
| 10082 | 2439055514U, // UQSHRNB_ZZI_H |
| 10083 | 2686535834U, // UQSHRNB_ZZI_S |
| 10084 | 2954928363U, // UQSHRNT_ZZI_B |
| 10085 | 2441158891U, // UQSHRNT_ZZI_H |
| 10086 | 1612800235U, // UQSHRNT_ZZI_S |
| 10087 | 1075877920U, // UQSHRN_Z2ZI_HtoB |
| 10088 | 2451642400U, // UQSHRN_Z2ZI_StoH |
| 10089 | 2119712U, // UQSHRNb |
| 10090 | 2119712U, // UQSHRNh |
| 10091 | 2119712U, // UQSHRNs |
| 10092 | 3229745595U, // UQSHRNv16i8_shift |
| 10093 | 1352767520U, // UQSHRNv2i32_shift |
| 10094 | 1356961824U, // UQSHRNv4i16_shift |
| 10095 | 3238134203U, // UQSHRNv4i32_shift |
| 10096 | 3240231355U, // UQSHRNv8i16_shift |
| 10097 | 1363253280U, // UQSHRNv8i8_shift |
| 10098 | 807443338U, // UQSUBR_ZPmZ_B |
| 10099 | 807459722U, // UQSUBR_ZPmZ_D |
| 10100 | 543234954U, // UQSUBR_ZPmZ_H |
| 10101 | 807492490U, // UQSUBR_ZPmZ_S |
| 10102 | 3491793530U, // UQSUB_ZI_B |
| 10103 | 2686503546U, // UQSUB_ZI_D |
| 10104 | 2443250298U, // UQSUB_ZI_H |
| 10105 | 3760278138U, // UQSUB_ZI_S |
| 10106 | 807438970U, // UQSUB_ZPmZ_B |
| 10107 | 807455354U, // UQSUB_ZPmZ_D |
| 10108 | 543230586U, // UQSUB_ZPmZ_H |
| 10109 | 807488122U, // UQSUB_ZPmZ_S |
| 10110 | 3491793530U, // UQSUB_ZZZ_B |
| 10111 | 2686503546U, // UQSUB_ZZZ_D |
| 10112 | 2443250298U, // UQSUB_ZZZ_H |
| 10113 | 3760278138U, // UQSUB_ZZZ_S |
| 10114 | 1350666874U, // UQSUBv16i8 |
| 10115 | 2116218U, // UQSUBv1i16 |
| 10116 | 2116218U, // UQSUBv1i32 |
| 10117 | 2116218U, // UQSUBv1i64 |
| 10118 | 2116218U, // UQSUBv1i8 |
| 10119 | 1352764026U, // UQSUBv2i32 |
| 10120 | 1354861178U, // UQSUBv2i64 |
| 10121 | 1356958330U, // UQSUBv4i16 |
| 10122 | 1359055482U, // UQSUBv4i32 |
| 10123 | 1361152634U, // UQSUBv8i16 |
| 10124 | 1363249786U, // UQSUBv8i8 |
| 10125 | 2149615815U, // UQXTNB_ZZ_B |
| 10126 | 560007367U, // UQXTNB_ZZ_H |
| 10127 | 2686535879U, // UQXTNB_ZZ_S |
| 10128 | 2954928409U, // UQXTNT_ZZ_B |
| 10129 | 562110745U, // UQXTNT_ZZ_H |
| 10130 | 1612800281U, // UQXTNT_ZZ_S |
| 10131 | 3229745647U, // UQXTNv16i8 |
| 10132 | 2119791U, // UQXTNv1i16 |
| 10133 | 2119791U, // UQXTNv1i32 |
| 10134 | 2119791U, // UQXTNv1i8 |
| 10135 | 1352767599U, // UQXTNv2i32 |
| 10136 | 1356961903U, // UQXTNv4i16 |
| 10137 | 3238134255U, // UQXTNv4i32 |
| 10138 | 3240231407U, // UQXTNv8i16 |
| 10139 | 1363253359U, // UQXTNv8i8 |
| 10140 | 270617916U, // URECPE_ZPmZ_S |
| 10141 | 807488828U, // URECPE_ZPzZ_S |
| 10142 | 1352764732U, // URECPEv2i32 |
| 10143 | 1359056188U, // URECPEv4i32 |
| 10144 | 807439401U, // URHADD_ZPmZ_B |
| 10145 | 807455785U, // URHADD_ZPmZ_D |
| 10146 | 543231017U, // URHADD_ZPmZ_H |
| 10147 | 807488553U, // URHADD_ZPmZ_S |
| 10148 | 1350667305U, // URHADDv16i8 |
| 10149 | 1352764457U, // URHADDv2i32 |
| 10150 | 1356958761U, // URHADDv4i16 |
| 10151 | 1359055913U, // URHADDv4i32 |
| 10152 | 1361153065U, // URHADDv8i16 |
| 10153 | 1363250217U, // URHADDv8i8 |
| 10154 | 807443547U, // URSHLR_ZPmZ_B |
| 10155 | 807459931U, // URSHLR_ZPmZ_D |
| 10156 | 543235163U, // URSHLR_ZPmZ_H |
| 10157 | 807492699U, // URSHLR_ZPmZ_S |
| 10158 | 2445431908U, // URSHL_VG2_2Z2Z_B |
| 10159 | 2447545444U, // URSHL_VG2_2Z2Z_D |
| 10160 | 2449658980U, // URSHL_VG2_2Z2Z_H |
| 10161 | 2451772516U, // URSHL_VG2_2Z2Z_S |
| 10162 | 2445431908U, // URSHL_VG2_2ZZ_B |
| 10163 | 2447545444U, // URSHL_VG2_2ZZ_D |
| 10164 | 2449658980U, // URSHL_VG2_2ZZ_H |
| 10165 | 2451772516U, // URSHL_VG2_2ZZ_S |
| 10166 | 2445431908U, // URSHL_VG4_4Z4Z_B |
| 10167 | 2447545444U, // URSHL_VG4_4Z4Z_D |
| 10168 | 2449658980U, // URSHL_VG4_4Z4Z_H |
| 10169 | 2451772516U, // URSHL_VG4_4Z4Z_S |
| 10170 | 2445431908U, // URSHL_VG4_4ZZ_B |
| 10171 | 2447545444U, // URSHL_VG4_4ZZ_D |
| 10172 | 2449658980U, // URSHL_VG4_4ZZ_H |
| 10173 | 2451772516U, // URSHL_VG4_4ZZ_S |
| 10174 | 807441508U, // URSHL_ZPmZ_B |
| 10175 | 807457892U, // URSHL_ZPmZ_D |
| 10176 | 543233124U, // URSHL_ZPmZ_H |
| 10177 | 807490660U, // URSHL_ZPmZ_S |
| 10178 | 1350669412U, // URSHLv16i8 |
| 10179 | 2118756U, // URSHLv1i64 |
| 10180 | 1352766564U, // URSHLv2i32 |
| 10181 | 1354863716U, // URSHLv2i64 |
| 10182 | 1356960868U, // URSHLv4i16 |
| 10183 | 1359058020U, // URSHLv4i32 |
| 10184 | 1361155172U, // URSHLv8i16 |
| 10185 | 1363252324U, // URSHLv8i8 |
| 10186 | 807443449U, // URSHR_ZPmI_B |
| 10187 | 807459833U, // URSHR_ZPmI_D |
| 10188 | 543235065U, // URSHR_ZPmI_H |
| 10189 | 807492601U, // URSHR_ZPmI_S |
| 10190 | 2120697U, // URSHRd |
| 10191 | 1350671353U, // URSHRv16i8_shift |
| 10192 | 1352768505U, // URSHRv2i32_shift |
| 10193 | 1354865657U, // URSHRv2i64_shift |
| 10194 | 1356962809U, // URSHRv4i16_shift |
| 10195 | 1359059961U, // URSHRv4i32_shift |
| 10196 | 1361157113U, // URSHRv8i16_shift |
| 10197 | 1363254265U, // URSHRv8i8_shift |
| 10198 | 270617962U, // URSQRTE_ZPmZ_S |
| 10199 | 807488874U, // URSQRTE_ZPzZ_S |
| 10200 | 1352764778U, // URSQRTEv2i32 |
| 10201 | 1359056234U, // URSQRTEv4i32 |
| 10202 | 2686485719U, // URSRA_ZZI_B |
| 10203 | 1612760279U, // URSRA_ZZI_D |
| 10204 | 2460026071U, // URSRA_ZZI_H |
| 10205 | 1881228503U, // URSRA_ZZI_S |
| 10206 | 807716055U, // URSRAd |
| 10207 | 3229746391U, // URSRAv16i8_shift |
| 10208 | 3231843543U, // URSRAv2i32_shift |
| 10209 | 3233940695U, // URSRAv2i64_shift |
| 10210 | 3236037847U, // URSRAv4i16_shift |
| 10211 | 3238134999U, // URSRAv4i32_shift |
| 10212 | 3240232151U, // URSRAv8i16_shift |
| 10213 | 3242329303U, // URSRAv8i8_shift |
| 10214 | 4064518485U, // USDOT_VG2_M2Z2Z_BToS |
| 10215 | 4064518485U, // USDOT_VG2_M2ZZI_BToS |
| 10216 | 4064518485U, // USDOT_VG2_M2ZZ_BToS |
| 10217 | 37986645U, // USDOT_VG4_M4Z4Z_BToS |
| 10218 | 37986645U, // USDOT_VG4_M4ZZI_BToS |
| 10219 | 37986645U, // USDOT_VG4_M4ZZ_BToS |
| 10220 | 2686542165U, // USDOT_ZZZ |
| 10221 | 2686542165U, // USDOT_ZZZI |
| 10222 | 3238142293U, // USDOTlanev16i8 |
| 10223 | 3231850837U, // USDOTlanev8i8 |
| 10224 | 3238142293U, // USDOTv16i8 |
| 10225 | 3231850837U, // USDOTv8i8 |
| 10226 | 3760244682U, // USHLLB_ZZI_D |
| 10227 | 2462123978U, // USHLLB_ZZI_H |
| 10228 | 2149664714U, // USHLLB_ZZI_S |
| 10229 | 3760250939U, // USHLLT_ZZI_D |
| 10230 | 2462130235U, // USHLLT_ZZI_H |
| 10231 | 2149670971U, // USHLLT_ZZI_S |
| 10232 | 1361150264U, // USHLLv16i8_shift |
| 10233 | 1354863768U, // USHLLv2i32_shift |
| 10234 | 1359058072U, // USHLLv4i16_shift |
| 10235 | 1354858808U, // USHLLv4i32_shift |
| 10236 | 1359053112U, // USHLLv8i16_shift |
| 10237 | 1361155224U, // USHLLv8i8_shift |
| 10238 | 1350669425U, // USHLv16i8 |
| 10239 | 2118769U, // USHLv1i64 |
| 10240 | 1352766577U, // USHLv2i32 |
| 10241 | 1354863729U, // USHLv2i64 |
| 10242 | 1356960881U, // USHLv4i16 |
| 10243 | 1359058033U, // USHLv4i32 |
| 10244 | 1361155185U, // USHLv8i16 |
| 10245 | 1363252337U, // USHLv8i8 |
| 10246 | 2120710U, // USHRd |
| 10247 | 1350671366U, // USHRv16i8_shift |
| 10248 | 1352768518U, // USHRv2i32_shift |
| 10249 | 1354865670U, // USHRv2i64_shift |
| 10250 | 1356962822U, // USHRv4i16_shift |
| 10251 | 1359059974U, // USHRv4i32_shift |
| 10252 | 1361157126U, // USHRv8i16_shift |
| 10253 | 1363254278U, // USHRv8i8_shift |
| 10254 | 1415812223U, // USMLALL_MZZI_BtoS |
| 10255 | 1415812223U, // USMLALL_MZZ_BtoS |
| 10256 | 4100166783U, // USMLALL_VG2_M2Z2Z_BtoS |
| 10257 | 4100166783U, // USMLALL_VG2_M2ZZI_BtoS |
| 10258 | 3026424959U, // USMLALL_VG2_M2ZZ_BtoS |
| 10259 | 73634943U, // USMLALL_VG4_M4Z4Z_BtoS |
| 10260 | 73634943U, // USMLALL_VG4_M4ZZI_BtoS |
| 10261 | 3294860415U, // USMLALL_VG4_M4ZZ_BtoS |
| 10262 | 3238134650U, // USMMLA |
| 10263 | 2686534522U, // USMMLA_ZZZ |
| 10264 | 3565273822U, // USMOP4A_M2Z2Z_BToS |
| 10265 | 1661059806U, // USMOP4A_M2Z2Z_HtoD |
| 10266 | 75612894U, // USMOP4A_M2ZZ_BToS |
| 10267 | 1929495262U, // USMOP4A_M2ZZ_HtoD |
| 10268 | 2485240542U, // USMOP4A_MZ2Z_BToS |
| 10269 | 2460074718U, // USMOP4A_MZ2Z_HtoD |
| 10270 | 2485240542U, // USMOP4A_MZZ_BToS |
| 10271 | 2460074718U, // USMOP4A_MZZ_HtoD |
| 10272 | 3565280593U, // USMOP4S_M2Z2Z_BToS |
| 10273 | 1661066577U, // USMOP4S_M2Z2Z_HtoD |
| 10274 | 75619665U, // USMOP4S_M2ZZ_BToS |
| 10275 | 1929502033U, // USMOP4S_M2ZZ_HtoD |
| 10276 | 2485247313U, // USMOP4S_MZ2Z_BToS |
| 10277 | 2460081489U, // USMOP4S_MZ2Z_HtoD |
| 10278 | 2485247313U, // USMOP4S_MZZ_BToS |
| 10279 | 2460081489U, // USMOP4S_MZZ_HtoD |
| 10280 | 541180921U, // USMOPA_MPPZZ_D |
| 10281 | 541180921U, // USMOPA_MPPZZ_S |
| 10282 | 541187687U, // USMOPS_MPPZZ_D |
| 10283 | 541187687U, // USMOPS_MPPZZ_S |
| 10284 | 807439438U, // USQADD_ZPmZ_B |
| 10285 | 807455822U, // USQADD_ZPmZ_D |
| 10286 | 543231054U, // USQADD_ZPmZ_H |
| 10287 | 807488590U, // USQADD_ZPmZ_S |
| 10288 | 3229748302U, // USQADDv16i8 |
| 10289 | 807717966U, // USQADDv1i16 |
| 10290 | 807717966U, // USQADDv1i32 |
| 10291 | 807717966U, // USQADDv1i64 |
| 10292 | 807717966U, // USQADDv1i8 |
| 10293 | 3231845454U, // USQADDv2i32 |
| 10294 | 3233942606U, // USQADDv2i64 |
| 10295 | 3236039758U, // USQADDv4i16 |
| 10296 | 3238136910U, // USQADDv4i32 |
| 10297 | 3240234062U, // USQADDv8i16 |
| 10298 | 3242331214U, // USQADDv8i8 |
| 10299 | 2686485732U, // USRA_ZZI_B |
| 10300 | 1612760292U, // USRA_ZZI_D |
| 10301 | 2460026084U, // USRA_ZZI_H |
| 10302 | 1881228516U, // USRA_ZZI_S |
| 10303 | 807716068U, // USRAd |
| 10304 | 3229746404U, // USRAv16i8_shift |
| 10305 | 3231843556U, // USRAv2i32_shift |
| 10306 | 3233940708U, // USRAv2i64_shift |
| 10307 | 3236037860U, // USRAv4i16_shift |
| 10308 | 3238135012U, // USRAv4i32_shift |
| 10309 | 3240232164U, // USRAv8i16_shift |
| 10310 | 3242329316U, // USRAv8i8_shift |
| 10311 | 75613194U, // USTMOPA_M2ZZZI_BtoS |
| 10312 | 3760244611U, // USUBLB_ZZZ_D |
| 10313 | 2462123907U, // USUBLB_ZZZ_H |
| 10314 | 2149664643U, // USUBLB_ZZZ_S |
| 10315 | 3760250845U, // USUBLT_ZZZ_D |
| 10316 | 2462130141U, // USUBLT_ZZZ_H |
| 10317 | 2149670877U, // USUBLT_ZZZ_S |
| 10318 | 1361150216U, // USUBLv16i8_v8i16 |
| 10319 | 1354863552U, // USUBLv2i32_v2i64 |
| 10320 | 1359057856U, // USUBLv4i16_v4i32 |
| 10321 | 1354858760U, // USUBLv4i32_v2i64 |
| 10322 | 1359053064U, // USUBLv8i16_v4i32 |
| 10323 | 1361155008U, // USUBLv8i8_v8i16 |
| 10324 | 2686503567U, // USUBWB_ZZZ_D |
| 10325 | 2443250319U, // USUBWB_ZZZ_H |
| 10326 | 3760278159U, // USUBWB_ZZZ_S |
| 10327 | 2686509588U, // USUBWT_ZZZ_D |
| 10328 | 2443256340U, // USUBWT_ZZZ_H |
| 10329 | 3760284180U, // USUBWT_ZZZ_S |
| 10330 | 1361150548U, // USUBWv16i8_v8i16 |
| 10331 | 1354867684U, // USUBWv2i32_v2i64 |
| 10332 | 1359061988U, // USUBWv4i16_v4i32 |
| 10333 | 1354859092U, // USUBWv4i32_v2i64 |
| 10334 | 1359053396U, // USUBWv8i16_v4i32 |
| 10335 | 1361159140U, // USUBWv8i8_v8i16 |
| 10336 | 37986667U, // USVDOT_VG4_M4ZZI_BToS |
| 10337 | 75613204U, // UTMOPA_M2ZZZI_BtoS |
| 10338 | 1929495572U, // UTMOPA_M2ZZZI_HtoS |
| 10339 | 3760247159U, // UUNPKHI_ZZ_D |
| 10340 | 583078263U, // UUNPKHI_ZZ_H |
| 10341 | 2149667191U, // UUNPKHI_ZZ_S |
| 10342 | 3760249042U, // UUNPKLO_ZZ_D |
| 10343 | 583080146U, // UUNPKLO_ZZ_H |
| 10344 | 2149669074U, // UUNPKLO_ZZ_S |
| 10345 | 560107959U, // UUNPK_VG2_2ZZ_D |
| 10346 | 583193015U, // UUNPK_VG2_2ZZ_H |
| 10347 | 564335031U, // UUNPK_VG2_2ZZ_S |
| 10348 | 572690871U, // UUNPK_VG4_4Z2Z_D |
| 10349 | 566415799U, // UUNPK_VG4_4Z2Z_H |
| 10350 | 570626487U, // UUNPK_VG4_4Z2Z_S |
| 10351 | 4064518516U, // UVDOT_VG2_M2ZZI_HtoS |
| 10352 | 37986676U, // UVDOT_VG4_M4ZZI_BtoS |
| 10353 | 37970292U, // UVDOT_VG4_M4ZZI_HtoD |
| 10354 | 270584393U, // UXTB_ZPmZ_D |
| 10355 | 541133385U, // UXTB_ZPmZ_H |
| 10356 | 270617161U, // UXTB_ZPmZ_S |
| 10357 | 807455305U, // UXTB_ZPzZ_D |
| 10358 | 1080101449U, // UXTB_ZPzZ_H |
| 10359 | 807488073U, // UXTB_ZPzZ_S |
| 10360 | 270586141U, // UXTH_ZPmZ_D |
| 10361 | 270618909U, // UXTH_ZPmZ_S |
| 10362 | 807457053U, // UXTH_ZPzZ_D |
| 10363 | 807489821U, // UXTH_ZPzZ_S |
| 10364 | 270591142U, // UXTW_ZPmZ_D |
| 10365 | 807462054U, // UXTW_ZPzZ_D |
| 10366 | 3491790919U, // UZP1_PPP_B |
| 10367 | 2686500935U, // UZP1_PPP_D |
| 10368 | 2443247687U, // UZP1_PPP_H |
| 10369 | 3760275527U, // UZP1_PPP_S |
| 10370 | 3491790919U, // UZP1_ZZZ_B |
| 10371 | 2686500935U, // UZP1_ZZZ_D |
| 10372 | 2443247687U, // UZP1_ZZZ_H |
| 10373 | 2475114567U, // UZP1_ZZZ_Q |
| 10374 | 3760275527U, // UZP1_ZZZ_S |
| 10375 | 1350664263U, // UZP1v16i8 |
| 10376 | 1352761415U, // UZP1v2i32 |
| 10377 | 1354858567U, // UZP1v2i64 |
| 10378 | 1356955719U, // UZP1v4i16 |
| 10379 | 1359052871U, // UZP1v4i32 |
| 10380 | 1361150023U, // UZP1v8i16 |
| 10381 | 1363247175U, // UZP1v8i8 |
| 10382 | 3491791396U, // UZP2_PPP_B |
| 10383 | 2686501412U, // UZP2_PPP_D |
| 10384 | 2443248164U, // UZP2_PPP_H |
| 10385 | 3760276004U, // UZP2_PPP_S |
| 10386 | 3491791396U, // UZP2_ZZZ_B |
| 10387 | 2686501412U, // UZP2_ZZZ_D |
| 10388 | 2443248164U, // UZP2_ZZZ_H |
| 10389 | 2475115044U, // UZP2_ZZZ_Q |
| 10390 | 3760276004U, // UZP2_ZZZ_S |
| 10391 | 1350664740U, // UZP2v16i8 |
| 10392 | 1352761892U, // UZP2v2i32 |
| 10393 | 1354859044U, // UZP2v2i64 |
| 10394 | 1356956196U, // UZP2v4i16 |
| 10395 | 1359053348U, // UZP2v4i32 |
| 10396 | 1361150500U, // UZP2v8i16 |
| 10397 | 1363247652U, // UZP2v8i8 |
| 10398 | 3491790932U, // UZPQ1_ZZZ_B |
| 10399 | 2686500948U, // UZPQ1_ZZZ_D |
| 10400 | 2443247700U, // UZPQ1_ZZZ_H |
| 10401 | 3760275540U, // UZPQ1_ZZZ_S |
| 10402 | 3491791409U, // UZPQ2_ZZZ_B |
| 10403 | 2686501425U, // UZPQ2_ZZZ_D |
| 10404 | 2443248177U, // UZPQ2_ZZZ_H |
| 10405 | 3760276017U, // UZPQ2_ZZZ_S |
| 10406 | 2462210761U, // UZP_VG2_2ZZZ_B |
| 10407 | 165845705U, // UZP_VG2_2ZZZ_D |
| 10408 | 2443369161U, // UZP_VG2_2ZZZ_H |
| 10409 | 2475137737U, // UZP_VG2_2ZZZ_Q |
| 10410 | 2439191241U, // UZP_VG2_2ZZZ_S |
| 10411 | 566385353U, // UZP_VG4_4Z4Z_B |
| 10412 | 568498889U, // UZP_VG4_4Z4Z_D |
| 10413 | 570612425U, // UZP_VG4_4Z4Z_H |
| 10414 | 180853449U, // UZP_VG4_4Z4Z_Q |
| 10415 | 572725961U, // UZP_VG4_4Z4Z_S |
| 10416 | 24340U, // WFET |
| 10417 | 24446U, // WFIT |
| 10418 | 2472692939U, // WHILEGE_2PXX_B |
| 10419 | 2472709323U, // WHILEGE_2PXX_D |
| 10420 | 2472725707U, // WHILEGE_2PXX_H |
| 10421 | 2472742091U, // WHILEGE_2PXX_S |
| 10422 | 3247307U, // WHILEGE_CXX_B |
| 10423 | 3263691U, // WHILEGE_CXX_D |
| 10424 | 3280075U, // WHILEGE_CXX_H |
| 10425 | 3296459U, // WHILEGE_CXX_S |
| 10426 | 2133195U, // WHILEGE_PWW_B |
| 10427 | 2149579U, // WHILEGE_PWW_D |
| 10428 | 2472611019U, // WHILEGE_PWW_H |
| 10429 | 2182347U, // WHILEGE_PWW_S |
| 10430 | 2133195U, // WHILEGE_PXX_B |
| 10431 | 2149579U, // WHILEGE_PXX_D |
| 10432 | 2472611019U, // WHILEGE_PXX_H |
| 10433 | 2182347U, // WHILEGE_PXX_S |
| 10434 | 2472697683U, // WHILEGT_2PXX_B |
| 10435 | 2472714067U, // WHILEGT_2PXX_D |
| 10436 | 2472730451U, // WHILEGT_2PXX_H |
| 10437 | 2472746835U, // WHILEGT_2PXX_S |
| 10438 | 3252051U, // WHILEGT_CXX_B |
| 10439 | 3268435U, // WHILEGT_CXX_D |
| 10440 | 3284819U, // WHILEGT_CXX_H |
| 10441 | 3301203U, // WHILEGT_CXX_S |
| 10442 | 2137939U, // WHILEGT_PWW_B |
| 10443 | 2154323U, // WHILEGT_PWW_D |
| 10444 | 2472615763U, // WHILEGT_PWW_H |
| 10445 | 2187091U, // WHILEGT_PWW_S |
| 10446 | 2137939U, // WHILEGT_PXX_B |
| 10447 | 2154323U, // WHILEGT_PXX_D |
| 10448 | 2472615763U, // WHILEGT_PXX_H |
| 10449 | 2187091U, // WHILEGT_PXX_S |
| 10450 | 2472694101U, // WHILEHI_2PXX_B |
| 10451 | 2472710485U, // WHILEHI_2PXX_D |
| 10452 | 2472726869U, // WHILEHI_2PXX_H |
| 10453 | 2472743253U, // WHILEHI_2PXX_S |
| 10454 | 3248469U, // WHILEHI_CXX_B |
| 10455 | 3264853U, // WHILEHI_CXX_D |
| 10456 | 3281237U, // WHILEHI_CXX_H |
| 10457 | 3297621U, // WHILEHI_CXX_S |
| 10458 | 2134357U, // WHILEHI_PWW_B |
| 10459 | 2150741U, // WHILEHI_PWW_D |
| 10460 | 2472612181U, // WHILEHI_PWW_H |
| 10461 | 2183509U, // WHILEHI_PWW_S |
| 10462 | 2134357U, // WHILEHI_PXX_B |
| 10463 | 2150741U, // WHILEHI_PXX_D |
| 10464 | 2472612181U, // WHILEHI_PXX_H |
| 10465 | 2183509U, // WHILEHI_PXX_S |
| 10466 | 2472697319U, // WHILEHS_2PXX_B |
| 10467 | 2472713703U, // WHILEHS_2PXX_D |
| 10468 | 2472730087U, // WHILEHS_2PXX_H |
| 10469 | 2472746471U, // WHILEHS_2PXX_S |
| 10470 | 3251687U, // WHILEHS_CXX_B |
| 10471 | 3268071U, // WHILEHS_CXX_D |
| 10472 | 3284455U, // WHILEHS_CXX_H |
| 10473 | 3300839U, // WHILEHS_CXX_S |
| 10474 | 2137575U, // WHILEHS_PWW_B |
| 10475 | 2153959U, // WHILEHS_PWW_D |
| 10476 | 2472615399U, // WHILEHS_PWW_H |
| 10477 | 2186727U, // WHILEHS_PWW_S |
| 10478 | 2137575U, // WHILEHS_PXX_B |
| 10479 | 2153959U, // WHILEHS_PXX_D |
| 10480 | 2472615399U, // WHILEHS_PXX_H |
| 10481 | 2186727U, // WHILEHS_PXX_S |
| 10482 | 2472692978U, // WHILELE_2PXX_B |
| 10483 | 2472709362U, // WHILELE_2PXX_D |
| 10484 | 2472725746U, // WHILELE_2PXX_H |
| 10485 | 2472742130U, // WHILELE_2PXX_S |
| 10486 | 3247346U, // WHILELE_CXX_B |
| 10487 | 3263730U, // WHILELE_CXX_D |
| 10488 | 3280114U, // WHILELE_CXX_H |
| 10489 | 3296498U, // WHILELE_CXX_S |
| 10490 | 2133234U, // WHILELE_PWW_B |
| 10491 | 2149618U, // WHILELE_PWW_D |
| 10492 | 2472611058U, // WHILELE_PWW_H |
| 10493 | 2182386U, // WHILELE_PWW_S |
| 10494 | 2133234U, // WHILELE_PXX_B |
| 10495 | 2149618U, // WHILELE_PXX_D |
| 10496 | 2472611058U, // WHILELE_PXX_H |
| 10497 | 2182386U, // WHILELE_PXX_S |
| 10498 | 2472695991U, // WHILELO_2PXX_B |
| 10499 | 2472712375U, // WHILELO_2PXX_D |
| 10500 | 2472728759U, // WHILELO_2PXX_H |
| 10501 | 2472745143U, // WHILELO_2PXX_S |
| 10502 | 3250359U, // WHILELO_CXX_B |
| 10503 | 3266743U, // WHILELO_CXX_D |
| 10504 | 3283127U, // WHILELO_CXX_H |
| 10505 | 3299511U, // WHILELO_CXX_S |
| 10506 | 2136247U, // WHILELO_PWW_B |
| 10507 | 2152631U, // WHILELO_PWW_D |
| 10508 | 2472614071U, // WHILELO_PWW_H |
| 10509 | 2185399U, // WHILELO_PWW_S |
| 10510 | 2136247U, // WHILELO_PXX_B |
| 10511 | 2152631U, // WHILELO_PXX_D |
| 10512 | 2472614071U, // WHILELO_PXX_H |
| 10513 | 2185399U, // WHILELO_PXX_S |
| 10514 | 2472697353U, // WHILELS_2PXX_B |
| 10515 | 2472713737U, // WHILELS_2PXX_D |
| 10516 | 2472730121U, // WHILELS_2PXX_H |
| 10517 | 2472746505U, // WHILELS_2PXX_S |
| 10518 | 3251721U, // WHILELS_CXX_B |
| 10519 | 3268105U, // WHILELS_CXX_D |
| 10520 | 3284489U, // WHILELS_CXX_H |
| 10521 | 3300873U, // WHILELS_CXX_S |
| 10522 | 2137609U, // WHILELS_PWW_B |
| 10523 | 2153993U, // WHILELS_PWW_D |
| 10524 | 2472615433U, // WHILELS_PWW_H |
| 10525 | 2186761U, // WHILELS_PWW_S |
| 10526 | 2137609U, // WHILELS_PXX_B |
| 10527 | 2153993U, // WHILELS_PXX_D |
| 10528 | 2472615433U, // WHILELS_PXX_H |
| 10529 | 2186761U, // WHILELS_PXX_S |
| 10530 | 2472697875U, // WHILELT_2PXX_B |
| 10531 | 2472714259U, // WHILELT_2PXX_D |
| 10532 | 2472730643U, // WHILELT_2PXX_H |
| 10533 | 2472747027U, // WHILELT_2PXX_S |
| 10534 | 3252243U, // WHILELT_CXX_B |
| 10535 | 3268627U, // WHILELT_CXX_D |
| 10536 | 3285011U, // WHILELT_CXX_H |
| 10537 | 3301395U, // WHILELT_CXX_S |
| 10538 | 2138131U, // WHILELT_PWW_B |
| 10539 | 2154515U, // WHILELT_PWW_D |
| 10540 | 2472615955U, // WHILELT_PWW_H |
| 10541 | 2187283U, // WHILELT_PWW_S |
| 10542 | 2138131U, // WHILELT_PXX_B |
| 10543 | 2154515U, // WHILELT_PXX_D |
| 10544 | 2472615955U, // WHILELT_PXX_H |
| 10545 | 2187283U, // WHILELT_PXX_S |
| 10546 | 2139199U, // WHILERW_PXX_B |
| 10547 | 2155583U, // WHILERW_PXX_D |
| 10548 | 2472617023U, // WHILERW_PXX_H |
| 10549 | 2188351U, // WHILERW_PXX_S |
| 10550 | 2137351U, // WHILEWR_PXX_B |
| 10551 | 2153735U, // WHILEWR_PXX_D |
| 10552 | 2472615175U, // WHILEWR_PXX_H |
| 10553 | 2186503U, // WHILEWR_PXX_S |
| 10554 | 39899U, // WRFFR |
| 10555 | 11495U, // XAFLAG |
| 10556 | 1354865510U, // XAR |
| 10557 | 3491797862U, // XAR_ZZZI_B |
| 10558 | 2686507878U, // XAR_ZZZI_D |
| 10559 | 2443254630U, // XAR_ZZZI_H |
| 10560 | 3760282470U, // XAR_ZZZI_S |
| 10561 | 19394U, // XPACD |
| 10562 | 20801U, // XPACI |
| 10563 | 9984U, // XPACLRI |
| 10564 | 3229745641U, // XTNv16i8 |
| 10565 | 1352767594U, // XTNv2i32 |
| 10566 | 1356961898U, // XTNv4i16 |
| 10567 | 3238134249U, // XTNv4i32 |
| 10568 | 3240231401U, // XTNv8i16 |
| 10569 | 1363253354U, // XTNv8i8 |
| 10570 | 1317090U, // ZERO_M |
| 10571 | 3806550242U, // ZERO_MXI_2Z |
| 10572 | 3831716066U, // ZERO_MXI_4Z |
| 10573 | 585324770U, // ZERO_MXI_VG2_2Z |
| 10574 | 610490594U, // ZERO_MXI_VG2_4Z |
| 10575 | 574839010U, // ZERO_MXI_VG2_Z |
| 10576 | 853760226U, // ZERO_MXI_VG4_2Z |
| 10577 | 878926050U, // ZERO_MXI_VG4_4Z |
| 10578 | 843274466U, // ZERO_MXI_VG4_Z |
| 10579 | 182478292U, // ZERO_T |
| 10580 | 3491790913U, // ZIP1_PPP_B |
| 10581 | 2686500929U, // ZIP1_PPP_D |
| 10582 | 2443247681U, // ZIP1_PPP_H |
| 10583 | 3760275521U, // ZIP1_PPP_S |
| 10584 | 3491790913U, // ZIP1_ZZZ_B |
| 10585 | 2686500929U, // ZIP1_ZZZ_D |
| 10586 | 2443247681U, // ZIP1_ZZZ_H |
| 10587 | 2475114561U, // ZIP1_ZZZ_Q |
| 10588 | 3760275521U, // ZIP1_ZZZ_S |
| 10589 | 1350664257U, // ZIP1v16i8 |
| 10590 | 1352761409U, // ZIP1v2i32 |
| 10591 | 1354858561U, // ZIP1v2i64 |
| 10592 | 1356955713U, // ZIP1v4i16 |
| 10593 | 1359052865U, // ZIP1v4i32 |
| 10594 | 1361150017U, // ZIP1v8i16 |
| 10595 | 1363247169U, // ZIP1v8i8 |
| 10596 | 3491791390U, // ZIP2_PPP_B |
| 10597 | 2686501406U, // ZIP2_PPP_D |
| 10598 | 2443248158U, // ZIP2_PPP_H |
| 10599 | 3760275998U, // ZIP2_PPP_S |
| 10600 | 3491791390U, // ZIP2_ZZZ_B |
| 10601 | 2686501406U, // ZIP2_ZZZ_D |
| 10602 | 2443248158U, // ZIP2_ZZZ_H |
| 10603 | 2475115038U, // ZIP2_ZZZ_Q |
| 10604 | 3760275998U, // ZIP2_ZZZ_S |
| 10605 | 1350664734U, // ZIP2v16i8 |
| 10606 | 1352761886U, // ZIP2v2i32 |
| 10607 | 1354859038U, // ZIP2v2i64 |
| 10608 | 1356956190U, // ZIP2v4i16 |
| 10609 | 1359053342U, // ZIP2v4i32 |
| 10610 | 1361150494U, // ZIP2v8i16 |
| 10611 | 1363247646U, // ZIP2v8i8 |
| 10612 | 3491790925U, // ZIPQ1_ZZZ_B |
| 10613 | 2686500941U, // ZIPQ1_ZZZ_D |
| 10614 | 2443247693U, // ZIPQ1_ZZZ_H |
| 10615 | 3760275533U, // ZIPQ1_ZZZ_S |
| 10616 | 3491791402U, // ZIPQ2_ZZZ_B |
| 10617 | 2686501418U, // ZIPQ2_ZZZ_D |
| 10618 | 2443248170U, // ZIPQ2_ZZZ_H |
| 10619 | 3760276010U, // ZIPQ2_ZZZ_S |
| 10620 | 2462210365U, // ZIP_VG2_2ZZZ_B |
| 10621 | 165845309U, // ZIP_VG2_2ZZZ_D |
| 10622 | 2443368765U, // ZIP_VG2_2ZZZ_H |
| 10623 | 2475137341U, // ZIP_VG2_2ZZZ_Q |
| 10624 | 2439190845U, // ZIP_VG2_2ZZZ_S |
| 10625 | 566384957U, // ZIP_VG4_4Z4Z_B |
| 10626 | 568498493U, // ZIP_VG4_4Z4Z_D |
| 10627 | 570612029U, // ZIP_VG4_4Z4Z_H |
| 10628 | 180853053U, // ZIP_VG4_4Z4Z_Q |
| 10629 | 572725565U, // ZIP_VG4_4Z4Z_S |
| 10630 | }; |
| 10631 | |
| 10632 | static const uint32_t OpInfo1[] = { |
| 10633 | 0U, // PHI |
| 10634 | 0U, // INLINEASM |
| 10635 | 0U, // INLINEASM_BR |
| 10636 | 0U, // CFI_INSTRUCTION |
| 10637 | 0U, // EH_LABEL |
| 10638 | 0U, // GC_LABEL |
| 10639 | 0U, // ANNOTATION_LABEL |
| 10640 | 0U, // KILL |
| 10641 | 0U, // EXTRACT_SUBREG |
| 10642 | 0U, // INSERT_SUBREG |
| 10643 | 0U, // IMPLICIT_DEF |
| 10644 | 0U, // INIT_UNDEF |
| 10645 | 0U, // SUBREG_TO_REG |
| 10646 | 0U, // COPY_TO_REGCLASS |
| 10647 | 0U, // DBG_VALUE |
| 10648 | 0U, // DBG_VALUE_LIST |
| 10649 | 0U, // DBG_INSTR_REF |
| 10650 | 0U, // DBG_PHI |
| 10651 | 0U, // DBG_LABEL |
| 10652 | 0U, // REG_SEQUENCE |
| 10653 | 0U, // COPY |
| 10654 | 0U, // COPY_LANEMASK |
| 10655 | 0U, // BUNDLE |
| 10656 | 0U, // LIFETIME_START |
| 10657 | 0U, // LIFETIME_END |
| 10658 | 0U, // PSEUDO_PROBE |
| 10659 | 0U, // ARITH_FENCE |
| 10660 | 0U, // STACKMAP |
| 10661 | 0U, // FENTRY_CALL |
| 10662 | 0U, // PATCHPOINT |
| 10663 | 0U, // LOAD_STACK_GUARD |
| 10664 | 0U, // PREALLOCATED_SETUP |
| 10665 | 0U, // PREALLOCATED_ARG |
| 10666 | 0U, // STATEPOINT |
| 10667 | 0U, // LOCAL_ESCAPE |
| 10668 | 0U, // FAULTING_OP |
| 10669 | 0U, // PATCHABLE_OP |
| 10670 | 0U, // PATCHABLE_FUNCTION_ENTER |
| 10671 | 0U, // PATCHABLE_RET |
| 10672 | 0U, // PATCHABLE_FUNCTION_EXIT |
| 10673 | 0U, // PATCHABLE_TAIL_CALL |
| 10674 | 0U, // PATCHABLE_EVENT_CALL |
| 10675 | 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 10676 | 0U, // ICALL_BRANCH_FUNNEL |
| 10677 | 0U, // FAKE_USE |
| 10678 | 0U, // MEMBARRIER |
| 10679 | 0U, // JUMP_TABLE_DEBUG_INFO |
| 10680 | 0U, // RELOC_NONE |
| 10681 | 0U, // CONVERGENCECTRL_ENTRY |
| 10682 | 0U, // CONVERGENCECTRL_ANCHOR |
| 10683 | 0U, // CONVERGENCECTRL_LOOP |
| 10684 | 0U, // CONVERGENCECTRL_GLUE |
| 10685 | 0U, // G_ASSERT_SEXT |
| 10686 | 0U, // G_ASSERT_ZEXT |
| 10687 | 0U, // G_ASSERT_ALIGN |
| 10688 | 0U, // G_ADD |
| 10689 | 0U, // G_SUB |
| 10690 | 0U, // G_MUL |
| 10691 | 0U, // G_SDIV |
| 10692 | 0U, // G_UDIV |
| 10693 | 0U, // G_SREM |
| 10694 | 0U, // G_UREM |
| 10695 | 0U, // G_SDIVREM |
| 10696 | 0U, // G_UDIVREM |
| 10697 | 0U, // G_AND |
| 10698 | 0U, // G_OR |
| 10699 | 0U, // G_XOR |
| 10700 | 0U, // G_ABDS |
| 10701 | 0U, // G_ABDU |
| 10702 | 0U, // G_UAVGFLOOR |
| 10703 | 0U, // G_UAVGCEIL |
| 10704 | 0U, // G_SAVGFLOOR |
| 10705 | 0U, // G_SAVGCEIL |
| 10706 | 0U, // G_IMPLICIT_DEF |
| 10707 | 0U, // G_PHI |
| 10708 | 0U, // G_FRAME_INDEX |
| 10709 | 0U, // G_GLOBAL_VALUE |
| 10710 | 0U, // G_PTRAUTH_GLOBAL_VALUE |
| 10711 | 0U, // G_CONSTANT_POOL |
| 10712 | 0U, // G_EXTRACT |
| 10713 | 0U, // G_UNMERGE_VALUES |
| 10714 | 0U, // G_INSERT |
| 10715 | 0U, // G_MERGE_VALUES |
| 10716 | 0U, // G_BUILD_VECTOR |
| 10717 | 0U, // G_BUILD_VECTOR_TRUNC |
| 10718 | 0U, // G_CONCAT_VECTORS |
| 10719 | 0U, // G_PTRTOINT |
| 10720 | 0U, // G_INTTOPTR |
| 10721 | 0U, // G_BITCAST |
| 10722 | 0U, // G_FREEZE |
| 10723 | 0U, // G_CONSTANT_FOLD_BARRIER |
| 10724 | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 10725 | 0U, // G_INTRINSIC_TRUNC |
| 10726 | 0U, // G_INTRINSIC_ROUND |
| 10727 | 0U, // G_INTRINSIC_LRINT |
| 10728 | 0U, // G_INTRINSIC_LLRINT |
| 10729 | 0U, // G_INTRINSIC_ROUNDEVEN |
| 10730 | 0U, // G_READCYCLECOUNTER |
| 10731 | 0U, // G_READSTEADYCOUNTER |
| 10732 | 0U, // G_LOAD |
| 10733 | 0U, // G_SEXTLOAD |
| 10734 | 0U, // G_ZEXTLOAD |
| 10735 | 0U, // G_INDEXED_LOAD |
| 10736 | 0U, // G_INDEXED_SEXTLOAD |
| 10737 | 0U, // G_INDEXED_ZEXTLOAD |
| 10738 | 0U, // G_STORE |
| 10739 | 0U, // G_INDEXED_STORE |
| 10740 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 10741 | 0U, // G_ATOMIC_CMPXCHG |
| 10742 | 0U, // G_ATOMICRMW_XCHG |
| 10743 | 0U, // G_ATOMICRMW_ADD |
| 10744 | 0U, // G_ATOMICRMW_SUB |
| 10745 | 0U, // G_ATOMICRMW_AND |
| 10746 | 0U, // G_ATOMICRMW_NAND |
| 10747 | 0U, // G_ATOMICRMW_OR |
| 10748 | 0U, // G_ATOMICRMW_XOR |
| 10749 | 0U, // G_ATOMICRMW_MAX |
| 10750 | 0U, // G_ATOMICRMW_MIN |
| 10751 | 0U, // G_ATOMICRMW_UMAX |
| 10752 | 0U, // G_ATOMICRMW_UMIN |
| 10753 | 0U, // G_ATOMICRMW_FADD |
| 10754 | 0U, // G_ATOMICRMW_FSUB |
| 10755 | 0U, // G_ATOMICRMW_FMAX |
| 10756 | 0U, // G_ATOMICRMW_FMIN |
| 10757 | 0U, // G_ATOMICRMW_FMAXIMUM |
| 10758 | 0U, // G_ATOMICRMW_FMINIMUM |
| 10759 | 0U, // G_ATOMICRMW_FMAXIMUMNUM |
| 10760 | 0U, // G_ATOMICRMW_FMINIMUMNUM |
| 10761 | 0U, // G_ATOMICRMW_UINC_WRAP |
| 10762 | 0U, // G_ATOMICRMW_UDEC_WRAP |
| 10763 | 0U, // G_ATOMICRMW_USUB_COND |
| 10764 | 0U, // G_ATOMICRMW_USUB_SAT |
| 10765 | 0U, // G_FENCE |
| 10766 | 0U, // G_PREFETCH |
| 10767 | 0U, // G_BRCOND |
| 10768 | 0U, // G_BRINDIRECT |
| 10769 | 0U, // G_INVOKE_REGION_START |
| 10770 | 0U, // G_INTRINSIC |
| 10771 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 10772 | 0U, // G_INTRINSIC_CONVERGENT |
| 10773 | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 10774 | 0U, // G_ANYEXT |
| 10775 | 0U, // G_TRUNC |
| 10776 | 0U, // G_TRUNC_SSAT_S |
| 10777 | 0U, // G_TRUNC_SSAT_U |
| 10778 | 0U, // G_TRUNC_USAT_U |
| 10779 | 0U, // G_CONSTANT |
| 10780 | 0U, // G_FCONSTANT |
| 10781 | 0U, // G_VASTART |
| 10782 | 0U, // G_VAARG |
| 10783 | 0U, // G_SEXT |
| 10784 | 0U, // G_SEXT_INREG |
| 10785 | 0U, // G_ZEXT |
| 10786 | 0U, // G_SHL |
| 10787 | 0U, // G_LSHR |
| 10788 | 0U, // G_ASHR |
| 10789 | 0U, // G_FSHL |
| 10790 | 0U, // G_FSHR |
| 10791 | 0U, // G_ROTR |
| 10792 | 0U, // G_ROTL |
| 10793 | 0U, // G_ICMP |
| 10794 | 0U, // G_FCMP |
| 10795 | 0U, // G_SCMP |
| 10796 | 0U, // G_UCMP |
| 10797 | 0U, // G_SELECT |
| 10798 | 0U, // G_UADDO |
| 10799 | 0U, // G_UADDE |
| 10800 | 0U, // G_USUBO |
| 10801 | 0U, // G_USUBE |
| 10802 | 0U, // G_SADDO |
| 10803 | 0U, // G_SADDE |
| 10804 | 0U, // G_SSUBO |
| 10805 | 0U, // G_SSUBE |
| 10806 | 0U, // G_UMULO |
| 10807 | 0U, // G_SMULO |
| 10808 | 0U, // G_UMULH |
| 10809 | 0U, // G_SMULH |
| 10810 | 0U, // G_UADDSAT |
| 10811 | 0U, // G_SADDSAT |
| 10812 | 0U, // G_USUBSAT |
| 10813 | 0U, // G_SSUBSAT |
| 10814 | 0U, // G_USHLSAT |
| 10815 | 0U, // G_SSHLSAT |
| 10816 | 0U, // G_SMULFIX |
| 10817 | 0U, // G_UMULFIX |
| 10818 | 0U, // G_SMULFIXSAT |
| 10819 | 0U, // G_UMULFIXSAT |
| 10820 | 0U, // G_SDIVFIX |
| 10821 | 0U, // G_UDIVFIX |
| 10822 | 0U, // G_SDIVFIXSAT |
| 10823 | 0U, // G_UDIVFIXSAT |
| 10824 | 0U, // G_FADD |
| 10825 | 0U, // G_FSUB |
| 10826 | 0U, // G_FMUL |
| 10827 | 0U, // G_FMA |
| 10828 | 0U, // G_FMAD |
| 10829 | 0U, // G_FDIV |
| 10830 | 0U, // G_FREM |
| 10831 | 0U, // G_FMODF |
| 10832 | 0U, // G_FPOW |
| 10833 | 0U, // G_FPOWI |
| 10834 | 0U, // G_FEXP |
| 10835 | 0U, // G_FEXP2 |
| 10836 | 0U, // G_FEXP10 |
| 10837 | 0U, // G_FLOG |
| 10838 | 0U, // G_FLOG2 |
| 10839 | 0U, // G_FLOG10 |
| 10840 | 0U, // G_FLDEXP |
| 10841 | 0U, // G_FFREXP |
| 10842 | 0U, // G_FNEG |
| 10843 | 0U, // G_FPEXT |
| 10844 | 0U, // G_FPTRUNC |
| 10845 | 0U, // G_FPTOSI |
| 10846 | 0U, // G_FPTOUI |
| 10847 | 0U, // G_SITOFP |
| 10848 | 0U, // G_UITOFP |
| 10849 | 0U, // G_FPTOSI_SAT |
| 10850 | 0U, // G_FPTOUI_SAT |
| 10851 | 0U, // G_FABS |
| 10852 | 0U, // G_FCOPYSIGN |
| 10853 | 0U, // G_IS_FPCLASS |
| 10854 | 0U, // G_FCANONICALIZE |
| 10855 | 0U, // G_FMINNUM |
| 10856 | 0U, // G_FMAXNUM |
| 10857 | 0U, // G_FMINNUM_IEEE |
| 10858 | 0U, // G_FMAXNUM_IEEE |
| 10859 | 0U, // G_FMINIMUM |
| 10860 | 0U, // G_FMAXIMUM |
| 10861 | 0U, // G_FMINIMUMNUM |
| 10862 | 0U, // G_FMAXIMUMNUM |
| 10863 | 0U, // G_GET_FPENV |
| 10864 | 0U, // G_SET_FPENV |
| 10865 | 0U, // G_RESET_FPENV |
| 10866 | 0U, // G_GET_FPMODE |
| 10867 | 0U, // G_SET_FPMODE |
| 10868 | 0U, // G_RESET_FPMODE |
| 10869 | 0U, // G_GET_ROUNDING |
| 10870 | 0U, // G_SET_ROUNDING |
| 10871 | 0U, // G_PTR_ADD |
| 10872 | 0U, // G_PTRMASK |
| 10873 | 0U, // G_SMIN |
| 10874 | 0U, // G_SMAX |
| 10875 | 0U, // G_UMIN |
| 10876 | 0U, // G_UMAX |
| 10877 | 0U, // G_ABS |
| 10878 | 0U, // G_LROUND |
| 10879 | 0U, // G_LLROUND |
| 10880 | 0U, // G_BR |
| 10881 | 0U, // G_BRJT |
| 10882 | 0U, // G_VSCALE |
| 10883 | 0U, // G_INSERT_SUBVECTOR |
| 10884 | 0U, // G_EXTRACT_SUBVECTOR |
| 10885 | 0U, // G_INSERT_VECTOR_ELT |
| 10886 | 0U, // G_EXTRACT_VECTOR_ELT |
| 10887 | 0U, // G_SHUFFLE_VECTOR |
| 10888 | 0U, // G_SPLAT_VECTOR |
| 10889 | 0U, // G_STEP_VECTOR |
| 10890 | 0U, // G_VECTOR_COMPRESS |
| 10891 | 0U, // G_CTTZ |
| 10892 | 0U, // G_CTTZ_ZERO_UNDEF |
| 10893 | 0U, // G_CTLZ |
| 10894 | 0U, // G_CTLZ_ZERO_UNDEF |
| 10895 | 0U, // G_CTLS |
| 10896 | 0U, // G_CTPOP |
| 10897 | 0U, // G_BSWAP |
| 10898 | 0U, // G_BITREVERSE |
| 10899 | 0U, // G_FCEIL |
| 10900 | 0U, // G_FCOS |
| 10901 | 0U, // G_FSIN |
| 10902 | 0U, // G_FSINCOS |
| 10903 | 0U, // G_FTAN |
| 10904 | 0U, // G_FACOS |
| 10905 | 0U, // G_FASIN |
| 10906 | 0U, // G_FATAN |
| 10907 | 0U, // G_FATAN2 |
| 10908 | 0U, // G_FCOSH |
| 10909 | 0U, // G_FSINH |
| 10910 | 0U, // G_FTANH |
| 10911 | 0U, // G_FSQRT |
| 10912 | 0U, // G_FFLOOR |
| 10913 | 0U, // G_FRINT |
| 10914 | 0U, // G_FNEARBYINT |
| 10915 | 0U, // G_ADDRSPACE_CAST |
| 10916 | 0U, // G_BLOCK_ADDR |
| 10917 | 0U, // G_JUMP_TABLE |
| 10918 | 0U, // G_DYN_STACKALLOC |
| 10919 | 0U, // G_STACKSAVE |
| 10920 | 0U, // G_STACKRESTORE |
| 10921 | 0U, // G_STRICT_FADD |
| 10922 | 0U, // G_STRICT_FSUB |
| 10923 | 0U, // G_STRICT_FMUL |
| 10924 | 0U, // G_STRICT_FDIV |
| 10925 | 0U, // G_STRICT_FREM |
| 10926 | 0U, // G_STRICT_FMA |
| 10927 | 0U, // G_STRICT_FSQRT |
| 10928 | 0U, // G_STRICT_FLDEXP |
| 10929 | 0U, // G_READ_REGISTER |
| 10930 | 0U, // G_WRITE_REGISTER |
| 10931 | 0U, // G_MEMCPY |
| 10932 | 0U, // G_MEMCPY_INLINE |
| 10933 | 0U, // G_MEMMOVE |
| 10934 | 0U, // G_MEMSET |
| 10935 | 0U, // G_BZERO |
| 10936 | 0U, // G_TRAP |
| 10937 | 0U, // G_DEBUGTRAP |
| 10938 | 0U, // G_UBSANTRAP |
| 10939 | 0U, // G_VECREDUCE_SEQ_FADD |
| 10940 | 0U, // G_VECREDUCE_SEQ_FMUL |
| 10941 | 0U, // G_VECREDUCE_FADD |
| 10942 | 0U, // G_VECREDUCE_FMUL |
| 10943 | 0U, // G_VECREDUCE_FMAX |
| 10944 | 0U, // G_VECREDUCE_FMIN |
| 10945 | 0U, // G_VECREDUCE_FMAXIMUM |
| 10946 | 0U, // G_VECREDUCE_FMINIMUM |
| 10947 | 0U, // G_VECREDUCE_ADD |
| 10948 | 0U, // G_VECREDUCE_MUL |
| 10949 | 0U, // G_VECREDUCE_AND |
| 10950 | 0U, // G_VECREDUCE_OR |
| 10951 | 0U, // G_VECREDUCE_XOR |
| 10952 | 0U, // G_VECREDUCE_SMAX |
| 10953 | 0U, // G_VECREDUCE_SMIN |
| 10954 | 0U, // G_VECREDUCE_UMAX |
| 10955 | 0U, // G_VECREDUCE_UMIN |
| 10956 | 0U, // G_SBFX |
| 10957 | 0U, // G_UBFX |
| 10958 | 0U, // ABS_ZPmZ_B_UNDEF |
| 10959 | 0U, // ABS_ZPmZ_D_UNDEF |
| 10960 | 0U, // ABS_ZPmZ_H_UNDEF |
| 10961 | 0U, // ABS_ZPmZ_S_UNDEF |
| 10962 | 0U, // ADDHA_MPPZ_D_PSEUDO_D |
| 10963 | 0U, // ADDHA_MPPZ_S_PSEUDO_S |
| 10964 | 0U, // ADDSWrr |
| 10965 | 0U, // ADDSXrr |
| 10966 | 0U, // ADDVA_MPPZ_D_PSEUDO_D |
| 10967 | 0U, // ADDVA_MPPZ_S_PSEUDO_S |
| 10968 | 0U, // ADDWrr |
| 10969 | 0U, // ADDXrr |
| 10970 | 0U, // ADD_VG2_M2Z2Z_D_PSEUDO |
| 10971 | 0U, // ADD_VG2_M2Z2Z_S_PSEUDO |
| 10972 | 0U, // ADD_VG2_M2ZZ_D_PSEUDO |
| 10973 | 0U, // ADD_VG2_M2ZZ_S_PSEUDO |
| 10974 | 0U, // ADD_VG2_M2Z_D_PSEUDO |
| 10975 | 0U, // ADD_VG2_M2Z_S_PSEUDO |
| 10976 | 0U, // ADD_VG4_M4Z4Z_D_PSEUDO |
| 10977 | 0U, // ADD_VG4_M4Z4Z_S_PSEUDO |
| 10978 | 0U, // ADD_VG4_M4ZZ_D_PSEUDO |
| 10979 | 0U, // ADD_VG4_M4ZZ_S_PSEUDO |
| 10980 | 0U, // ADD_VG4_M4Z_D_PSEUDO |
| 10981 | 0U, // ADD_VG4_M4Z_S_PSEUDO |
| 10982 | 0U, // ADD_ZI_B_PSEUDO |
| 10983 | 0U, // ADD_ZI_D_PSEUDO |
| 10984 | 0U, // ADD_ZI_H_PSEUDO |
| 10985 | 0U, // ADD_ZI_S_PSEUDO |
| 10986 | 0U, // ADD_ZPZZ_B_ZERO |
| 10987 | 0U, // ADD_ZPZZ_D_ZERO |
| 10988 | 0U, // ADD_ZPZZ_H_ZERO |
| 10989 | 0U, // ADD_ZPZZ_S_ZERO |
| 10990 | 0U, // ADDlowTLS |
| 10991 | 0U, // ADJCALLSTACKDOWN |
| 10992 | 0U, // ADJCALLSTACKUP |
| 10993 | 0U, // AESIMCrrTied |
| 10994 | 0U, // AESMCrrTied |
| 10995 | 0U, // ANDSWrr |
| 10996 | 0U, // ANDSXrr |
| 10997 | 0U, // ANDWrr |
| 10998 | 0U, // ANDXrr |
| 10999 | 0U, // AND_ZPZZ_B_ZERO |
| 11000 | 0U, // AND_ZPZZ_D_ZERO |
| 11001 | 0U, // AND_ZPZZ_H_ZERO |
| 11002 | 0U, // AND_ZPZZ_S_ZERO |
| 11003 | 0U, // ASRD_ZPZI_B_ZERO |
| 11004 | 0U, // ASRD_ZPZI_D_ZERO |
| 11005 | 0U, // ASRD_ZPZI_H_ZERO |
| 11006 | 0U, // ASRD_ZPZI_S_ZERO |
| 11007 | 0U, // ASR_ZPZI_B_UNDEF |
| 11008 | 0U, // ASR_ZPZI_B_ZERO |
| 11009 | 0U, // ASR_ZPZI_D_UNDEF |
| 11010 | 0U, // ASR_ZPZI_D_ZERO |
| 11011 | 0U, // ASR_ZPZI_H_UNDEF |
| 11012 | 0U, // ASR_ZPZI_H_ZERO |
| 11013 | 0U, // ASR_ZPZI_S_UNDEF |
| 11014 | 0U, // ASR_ZPZI_S_ZERO |
| 11015 | 0U, // ASR_ZPZZ_B_UNDEF |
| 11016 | 0U, // ASR_ZPZZ_B_ZERO |
| 11017 | 0U, // ASR_ZPZZ_D_UNDEF |
| 11018 | 0U, // ASR_ZPZZ_D_ZERO |
| 11019 | 0U, // ASR_ZPZZ_H_UNDEF |
| 11020 | 0U, // ASR_ZPZZ_H_ZERO |
| 11021 | 0U, // ASR_ZPZZ_S_UNDEF |
| 11022 | 0U, // ASR_ZPZZ_S_ZERO |
| 11023 | 0U, // AUTH_TCRETURN |
| 11024 | 0U, // AUTH_TCRETURN_BTI |
| 11025 | 0U, // AUTPAC |
| 11026 | 0U, // AUTRELLOADPAC |
| 11027 | 0U, // AUTx16x17 |
| 11028 | 0U, // AUTxMxN |
| 11029 | 0U, // AllocateSMESaveBuffer |
| 11030 | 0U, // AllocateZABuffer |
| 11031 | 0U, // BFADD_VG2_M2Z_H_PSEUDO |
| 11032 | 0U, // BFADD_VG4_M4Z_H_PSEUDO |
| 11033 | 0U, // BFADD_ZPZZ_UNDEF |
| 11034 | 0U, // BFADD_ZPZZ_ZERO |
| 11035 | 0U, // BFDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 11036 | 0U, // BFDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 11037 | 0U, // BFDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 11038 | 0U, // BFDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 11039 | 0U, // BFDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 11040 | 0U, // BFDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 11041 | 0U, // BFMAXNM_ZPZZ_UNDEF |
| 11042 | 0U, // BFMAXNM_ZPZZ_ZERO |
| 11043 | 0U, // BFMAX_ZPZZ_UNDEF |
| 11044 | 0U, // BFMAX_ZPZZ_ZERO |
| 11045 | 0U, // BFMINNM_ZPZZ_UNDEF |
| 11046 | 0U, // BFMINNM_ZPZZ_ZERO |
| 11047 | 0U, // BFMIN_ZPZZ_UNDEF |
| 11048 | 0U, // BFMIN_ZPZZ_ZERO |
| 11049 | 0U, // BFMLAL_MZZI_HtoS_PSEUDO |
| 11050 | 0U, // BFMLAL_MZZ_HtoS_PSEUDO |
| 11051 | 0U, // BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11052 | 0U, // BFMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 11053 | 0U, // BFMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 11054 | 0U, // BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11055 | 0U, // BFMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 11056 | 0U, // BFMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 11057 | 0U, // BFMLA_VG2_M2Z2Z_PSEUDO |
| 11058 | 0U, // BFMLA_VG2_M2ZZI_PSEUDO |
| 11059 | 0U, // BFMLA_VG2_M2ZZ_PSEUDO |
| 11060 | 0U, // BFMLA_VG4_M4Z4Z_PSEUDO |
| 11061 | 0U, // BFMLA_VG4_M4ZZI_PSEUDO |
| 11062 | 0U, // BFMLA_VG4_M4ZZ_PSEUDO |
| 11063 | 0U, // BFMLA_ZPZZZ_UNDEF |
| 11064 | 0U, // BFMLSL_MZZI_HtoS_PSEUDO |
| 11065 | 0U, // BFMLSL_MZZ_HtoS_PSEUDO |
| 11066 | 0U, // BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11067 | 0U, // BFMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 11068 | 0U, // BFMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 11069 | 0U, // BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11070 | 0U, // BFMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 11071 | 0U, // BFMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 11072 | 0U, // BFMLS_VG2_M2Z2Z_PSEUDO |
| 11073 | 0U, // BFMLS_VG2_M2ZZI_PSEUDO |
| 11074 | 0U, // BFMLS_VG2_M2ZZ_PSEUDO |
| 11075 | 0U, // BFMLS_VG4_M4Z4Z_PSEUDO |
| 11076 | 0U, // BFMLS_VG4_M4ZZI_PSEUDO |
| 11077 | 0U, // BFMLS_VG4_M4ZZ_PSEUDO |
| 11078 | 0U, // BFMLS_ZPZZZ_UNDEF |
| 11079 | 0U, // BFMOP4A_M2Z2Z_H_PSEUDO |
| 11080 | 0U, // BFMOP4A_M2Z2Z_S_PSEUDO |
| 11081 | 0U, // BFMOP4A_M2ZZ_H_PSEUDO |
| 11082 | 0U, // BFMOP4A_M2ZZ_S_PSEUDO |
| 11083 | 0U, // BFMOP4A_MZ2Z_H_PSEUDO |
| 11084 | 0U, // BFMOP4A_MZ2Z_S_PSEUDO |
| 11085 | 0U, // BFMOP4A_MZZ_H_PSEUDO |
| 11086 | 0U, // BFMOP4A_MZZ_S_PSEUDO |
| 11087 | 0U, // BFMOP4S_M2Z2Z_H_PSEUDO |
| 11088 | 0U, // BFMOP4S_M2Z2Z_S_PSEUDO |
| 11089 | 0U, // BFMOP4S_M2ZZ_H_PSEUDO |
| 11090 | 0U, // BFMOP4S_M2ZZ_S_PSEUDO |
| 11091 | 0U, // BFMOP4S_MZ2Z_H_PSEUDO |
| 11092 | 0U, // BFMOP4S_MZ2Z_S_PSEUDO |
| 11093 | 0U, // BFMOP4S_MZZ_H_PSEUDO |
| 11094 | 0U, // BFMOP4S_MZZ_S_PSEUDO |
| 11095 | 0U, // BFMOPA_MPPZZ_H_PSEUDO |
| 11096 | 0U, // BFMOPA_MPPZZ_PSEUDO |
| 11097 | 0U, // BFMOPS_MPPZZ_H_PSEUDO |
| 11098 | 0U, // BFMOPS_MPPZZ_PSEUDO |
| 11099 | 0U, // BFMUL_ZPZZ_UNDEF |
| 11100 | 0U, // BFMUL_ZPZZ_ZERO |
| 11101 | 0U, // BFSUB_VG2_M2Z_H_PSEUDO |
| 11102 | 0U, // BFSUB_VG4_M4Z_H_PSEUDO |
| 11103 | 0U, // BFSUB_ZPZZ_UNDEF |
| 11104 | 0U, // BFSUB_ZPZZ_ZERO |
| 11105 | 0U, // BFTMOPA_M2ZZZI_HtoH_PSEUDO |
| 11106 | 0U, // BFTMOPA_M2ZZZI_HtoS_PSEUDO |
| 11107 | 0U, // BFVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 11108 | 0U, // BICSWrr |
| 11109 | 0U, // BICSXrr |
| 11110 | 0U, // BICWrr |
| 11111 | 0U, // BICXrr |
| 11112 | 0U, // BIC_ZPZZ_B_ZERO |
| 11113 | 0U, // BIC_ZPZZ_D_ZERO |
| 11114 | 0U, // BIC_ZPZZ_H_ZERO |
| 11115 | 0U, // BIC_ZPZZ_S_ZERO |
| 11116 | 0U, // BLRA |
| 11117 | 0U, // BLRA_RVMARKER |
| 11118 | 0U, // BLRNoIP |
| 11119 | 0U, // BLR_BTI |
| 11120 | 0U, // BLR_RVMARKER |
| 11121 | 0U, // BLR_X16 |
| 11122 | 0U, // BMOPA_MPPZZ_S_PSEUDO |
| 11123 | 0U, // BMOPS_MPPZZ_S_PSEUDO |
| 11124 | 0U, // BRA |
| 11125 | 0U, // BR_JumpTable |
| 11126 | 0U, // BSPv16i8 |
| 11127 | 0U, // BSPv8i8 |
| 11128 | 0U, // CATCHRET |
| 11129 | 0U, // CBBAssertExt |
| 11130 | 0U, // CBHAssertExt |
| 11131 | 0U, // CBWPri |
| 11132 | 0U, // CBWPrr |
| 11133 | 0U, // CBXPri |
| 11134 | 0U, // CBXPrr |
| 11135 | 0U, // CHECK_MATCHING_VL_PSEUDO |
| 11136 | 0U, // CLEANUPRET |
| 11137 | 0U, // CLS_ZPmZ_B_UNDEF |
| 11138 | 0U, // CLS_ZPmZ_D_UNDEF |
| 11139 | 0U, // CLS_ZPmZ_H_UNDEF |
| 11140 | 0U, // CLS_ZPmZ_S_UNDEF |
| 11141 | 0U, // CLZ_ZPmZ_B_UNDEF |
| 11142 | 0U, // CLZ_ZPmZ_D_UNDEF |
| 11143 | 0U, // CLZ_ZPmZ_H_UNDEF |
| 11144 | 0U, // CLZ_ZPmZ_S_UNDEF |
| 11145 | 0U, // CMP_SWAP_128 |
| 11146 | 0U, // CMP_SWAP_128_ACQUIRE |
| 11147 | 0U, // CMP_SWAP_128_MONOTONIC |
| 11148 | 0U, // CMP_SWAP_128_RELEASE |
| 11149 | 0U, // CMP_SWAP_16 |
| 11150 | 0U, // CMP_SWAP_32 |
| 11151 | 0U, // CMP_SWAP_64 |
| 11152 | 0U, // CMP_SWAP_8 |
| 11153 | 0U, // CNOT_ZPmZ_B_UNDEF |
| 11154 | 0U, // CNOT_ZPmZ_D_UNDEF |
| 11155 | 0U, // CNOT_ZPmZ_H_UNDEF |
| 11156 | 0U, // CNOT_ZPmZ_S_UNDEF |
| 11157 | 0U, // CNT_ZPmZ_B_UNDEF |
| 11158 | 0U, // CNT_ZPmZ_D_UNDEF |
| 11159 | 0U, // CNT_ZPmZ_H_UNDEF |
| 11160 | 0U, // CNT_ZPmZ_S_UNDEF |
| 11161 | 0U, // COALESCER_BARRIER_FPR128 |
| 11162 | 0U, // COALESCER_BARRIER_FPR16 |
| 11163 | 0U, // COALESCER_BARRIER_FPR32 |
| 11164 | 0U, // COALESCER_BARRIER_FPR64 |
| 11165 | 0U, // CommitZASavePseudo |
| 11166 | 0U, // EMITBKEY |
| 11167 | 0U, // EMITMTETAGGED |
| 11168 | 0U, // EONWrr |
| 11169 | 0U, // EONXrr |
| 11170 | 0U, // EON_ZZZ |
| 11171 | 0U, // EORWrr |
| 11172 | 0U, // EORXrr |
| 11173 | 0U, // EOR_ZPZZ_B_ZERO |
| 11174 | 0U, // EOR_ZPZZ_D_ZERO |
| 11175 | 0U, // EOR_ZPZZ_H_ZERO |
| 11176 | 0U, // EOR_ZPZZ_S_ZERO |
| 11177 | 0U, // EXT_ZZI_CONSTRUCTIVE |
| 11178 | 0U, // EntryPStateSM |
| 11179 | 0U, // F128CSEL |
| 11180 | 0U, // FABD_ZPZZ_D_UNDEF |
| 11181 | 0U, // FABD_ZPZZ_D_ZERO |
| 11182 | 0U, // FABD_ZPZZ_H_UNDEF |
| 11183 | 0U, // FABD_ZPZZ_H_ZERO |
| 11184 | 0U, // FABD_ZPZZ_S_UNDEF |
| 11185 | 0U, // FABD_ZPZZ_S_ZERO |
| 11186 | 0U, // FABS_ZPmZ_D_UNDEF |
| 11187 | 0U, // FABS_ZPmZ_H_UNDEF |
| 11188 | 0U, // FABS_ZPmZ_S_UNDEF |
| 11189 | 0U, // FADD_VG2_M2Z_D_PSEUDO |
| 11190 | 0U, // FADD_VG2_M2Z_H_PSEUDO |
| 11191 | 0U, // FADD_VG2_M2Z_S_PSEUDO |
| 11192 | 0U, // FADD_VG4_M4Z_D_PSEUDO |
| 11193 | 0U, // FADD_VG4_M4Z_H_PSEUDO |
| 11194 | 0U, // FADD_VG4_M4Z_S_PSEUDO |
| 11195 | 0U, // FADD_ZPZI_D_UNDEF |
| 11196 | 0U, // FADD_ZPZI_D_ZERO |
| 11197 | 0U, // FADD_ZPZI_H_UNDEF |
| 11198 | 0U, // FADD_ZPZI_H_ZERO |
| 11199 | 0U, // FADD_ZPZI_S_UNDEF |
| 11200 | 0U, // FADD_ZPZI_S_ZERO |
| 11201 | 0U, // FADD_ZPZZ_D_UNDEF |
| 11202 | 0U, // FADD_ZPZZ_D_ZERO |
| 11203 | 0U, // FADD_ZPZZ_H_UNDEF |
| 11204 | 0U, // FADD_ZPZZ_H_ZERO |
| 11205 | 0U, // FADD_ZPZZ_S_UNDEF |
| 11206 | 0U, // FADD_ZPZZ_S_ZERO |
| 11207 | 0U, // FAMAX_ZPZZ_D_UNDEF |
| 11208 | 0U, // FAMAX_ZPZZ_H_UNDEF |
| 11209 | 0U, // FAMAX_ZPZZ_S_UNDEF |
| 11210 | 0U, // FAMIN_ZPZZ_D_UNDEF |
| 11211 | 0U, // FAMIN_ZPZZ_H_UNDEF |
| 11212 | 0U, // FAMIN_ZPZZ_S_UNDEF |
| 11213 | 0U, // FCVTZS_ZPmZ_DtoD_UNDEF |
| 11214 | 0U, // FCVTZS_ZPmZ_DtoS_UNDEF |
| 11215 | 0U, // FCVTZS_ZPmZ_HtoD_UNDEF |
| 11216 | 0U, // FCVTZS_ZPmZ_HtoH_UNDEF |
| 11217 | 0U, // FCVTZS_ZPmZ_HtoS_UNDEF |
| 11218 | 0U, // FCVTZS_ZPmZ_StoD_UNDEF |
| 11219 | 0U, // FCVTZS_ZPmZ_StoS_UNDEF |
| 11220 | 0U, // FCVTZU_ZPmZ_DtoD_UNDEF |
| 11221 | 0U, // FCVTZU_ZPmZ_DtoS_UNDEF |
| 11222 | 0U, // FCVTZU_ZPmZ_HtoD_UNDEF |
| 11223 | 0U, // FCVTZU_ZPmZ_HtoH_UNDEF |
| 11224 | 0U, // FCVTZU_ZPmZ_HtoS_UNDEF |
| 11225 | 0U, // FCVTZU_ZPmZ_StoD_UNDEF |
| 11226 | 0U, // FCVTZU_ZPmZ_StoS_UNDEF |
| 11227 | 0U, // FCVT_ZPmZ_DtoH_UNDEF |
| 11228 | 0U, // FCVT_ZPmZ_DtoS_UNDEF |
| 11229 | 0U, // FCVT_ZPmZ_HtoD_UNDEF |
| 11230 | 0U, // FCVT_ZPmZ_HtoS_UNDEF |
| 11231 | 0U, // FCVT_ZPmZ_StoD_UNDEF |
| 11232 | 0U, // FCVT_ZPmZ_StoH_UNDEF |
| 11233 | 0U, // FDIVR_ZPZZ_D_ZERO |
| 11234 | 0U, // FDIVR_ZPZZ_H_ZERO |
| 11235 | 0U, // FDIVR_ZPZZ_S_ZERO |
| 11236 | 0U, // FDIV_ZPZZ_D_UNDEF |
| 11237 | 0U, // FDIV_ZPZZ_D_ZERO |
| 11238 | 0U, // FDIV_ZPZZ_H_UNDEF |
| 11239 | 0U, // FDIV_ZPZZ_H_ZERO |
| 11240 | 0U, // FDIV_ZPZZ_S_UNDEF |
| 11241 | 0U, // FDIV_ZPZZ_S_ZERO |
| 11242 | 0U, // FDOT_VG2_M2Z2Z_BtoH_PSEUDO |
| 11243 | 0U, // FDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 11244 | 0U, // FDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 11245 | 0U, // FDOT_VG2_M2ZZI_BtoH_PSEUDO |
| 11246 | 0U, // FDOT_VG2_M2ZZI_BtoS_PSEUDO |
| 11247 | 0U, // FDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 11248 | 0U, // FDOT_VG2_M2ZZ_BtoH_PSEUDO |
| 11249 | 0U, // FDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 11250 | 0U, // FDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 11251 | 0U, // FDOT_VG4_M4Z4Z_BtoH_PSEUDO |
| 11252 | 0U, // FDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 11253 | 0U, // FDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 11254 | 0U, // FDOT_VG4_M4ZZI_BtoH_PSEUDO |
| 11255 | 0U, // FDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 11256 | 0U, // FDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 11257 | 0U, // FDOT_VG4_M4ZZ_BtoH_PSEUDO |
| 11258 | 0U, // FDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 11259 | 0U, // FDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 11260 | 0U, // FLOGB_ZPZZ_D_ZERO |
| 11261 | 0U, // FLOGB_ZPZZ_H_ZERO |
| 11262 | 0U, // FLOGB_ZPZZ_S_ZERO |
| 11263 | 0U, // FMAXNM_ZPZI_D_UNDEF |
| 11264 | 0U, // FMAXNM_ZPZI_D_ZERO |
| 11265 | 0U, // FMAXNM_ZPZI_H_UNDEF |
| 11266 | 0U, // FMAXNM_ZPZI_H_ZERO |
| 11267 | 0U, // FMAXNM_ZPZI_S_UNDEF |
| 11268 | 0U, // FMAXNM_ZPZI_S_ZERO |
| 11269 | 0U, // FMAXNM_ZPZZ_D_UNDEF |
| 11270 | 0U, // FMAXNM_ZPZZ_D_ZERO |
| 11271 | 0U, // FMAXNM_ZPZZ_H_UNDEF |
| 11272 | 0U, // FMAXNM_ZPZZ_H_ZERO |
| 11273 | 0U, // FMAXNM_ZPZZ_S_UNDEF |
| 11274 | 0U, // FMAXNM_ZPZZ_S_ZERO |
| 11275 | 0U, // FMAX_ZPZI_D_UNDEF |
| 11276 | 0U, // FMAX_ZPZI_D_ZERO |
| 11277 | 0U, // FMAX_ZPZI_H_UNDEF |
| 11278 | 0U, // FMAX_ZPZI_H_ZERO |
| 11279 | 0U, // FMAX_ZPZI_S_UNDEF |
| 11280 | 0U, // FMAX_ZPZI_S_ZERO |
| 11281 | 0U, // FMAX_ZPZZ_D_UNDEF |
| 11282 | 0U, // FMAX_ZPZZ_D_ZERO |
| 11283 | 0U, // FMAX_ZPZZ_H_UNDEF |
| 11284 | 0U, // FMAX_ZPZZ_H_ZERO |
| 11285 | 0U, // FMAX_ZPZZ_S_UNDEF |
| 11286 | 0U, // FMAX_ZPZZ_S_ZERO |
| 11287 | 0U, // FMINNM_ZPZI_D_UNDEF |
| 11288 | 0U, // FMINNM_ZPZI_D_ZERO |
| 11289 | 0U, // FMINNM_ZPZI_H_UNDEF |
| 11290 | 0U, // FMINNM_ZPZI_H_ZERO |
| 11291 | 0U, // FMINNM_ZPZI_S_UNDEF |
| 11292 | 0U, // FMINNM_ZPZI_S_ZERO |
| 11293 | 0U, // FMINNM_ZPZZ_D_UNDEF |
| 11294 | 0U, // FMINNM_ZPZZ_D_ZERO |
| 11295 | 0U, // FMINNM_ZPZZ_H_UNDEF |
| 11296 | 0U, // FMINNM_ZPZZ_H_ZERO |
| 11297 | 0U, // FMINNM_ZPZZ_S_UNDEF |
| 11298 | 0U, // FMINNM_ZPZZ_S_ZERO |
| 11299 | 0U, // FMIN_ZPZI_D_UNDEF |
| 11300 | 0U, // FMIN_ZPZI_D_ZERO |
| 11301 | 0U, // FMIN_ZPZI_H_UNDEF |
| 11302 | 0U, // FMIN_ZPZI_H_ZERO |
| 11303 | 0U, // FMIN_ZPZI_S_UNDEF |
| 11304 | 0U, // FMIN_ZPZI_S_ZERO |
| 11305 | 0U, // FMIN_ZPZZ_D_UNDEF |
| 11306 | 0U, // FMIN_ZPZZ_D_ZERO |
| 11307 | 0U, // FMIN_ZPZZ_H_UNDEF |
| 11308 | 0U, // FMIN_ZPZZ_H_ZERO |
| 11309 | 0U, // FMIN_ZPZZ_S_UNDEF |
| 11310 | 0U, // FMIN_ZPZZ_S_ZERO |
| 11311 | 0U, // FMLALL_MZZI_BtoS_PSEUDO |
| 11312 | 0U, // FMLALL_MZZ_BtoS_PSEUDO |
| 11313 | 0U, // FMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 11314 | 0U, // FMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 11315 | 0U, // FMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 11316 | 0U, // FMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 11317 | 0U, // FMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 11318 | 0U, // FMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 11319 | 0U, // FMLAL_MZZI_BtoH_PSEUDO |
| 11320 | 0U, // FMLAL_MZZI_HtoS_PSEUDO |
| 11321 | 0U, // FMLAL_MZZ_HtoS_PSEUDO |
| 11322 | 0U, // FMLAL_VG2_M2Z2Z_BtoH_PSEUDO |
| 11323 | 0U, // FMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11324 | 0U, // FMLAL_VG2_M2ZZI_BtoH_PSEUDO |
| 11325 | 0U, // FMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 11326 | 0U, // FMLAL_VG2_M2ZZ_BtoH_PSEUDO |
| 11327 | 0U, // FMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 11328 | 0U, // FMLAL_VG2_MZZ_BtoH_PSEUDO |
| 11329 | 0U, // FMLAL_VG4_M4Z4Z_BtoH_PSEUDO |
| 11330 | 0U, // FMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11331 | 0U, // FMLAL_VG4_M4ZZI_BtoH_PSEUDO |
| 11332 | 0U, // FMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 11333 | 0U, // FMLAL_VG4_M4ZZ_BtoH_PSEUDO |
| 11334 | 0U, // FMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 11335 | 0U, // FMLA_VG2_M2Z2Z_D_PSEUDO |
| 11336 | 0U, // FMLA_VG2_M2Z2Z_H_PSEUDO |
| 11337 | 0U, // FMLA_VG2_M2Z2Z_S_PSEUDO |
| 11338 | 0U, // FMLA_VG2_M2ZZI_D_PSEUDO |
| 11339 | 0U, // FMLA_VG2_M2ZZI_H_PSEUDO |
| 11340 | 0U, // FMLA_VG2_M2ZZI_S_PSEUDO |
| 11341 | 0U, // FMLA_VG2_M2ZZ_D_PSEUDO |
| 11342 | 0U, // FMLA_VG2_M2ZZ_H_PSEUDO |
| 11343 | 0U, // FMLA_VG2_M2ZZ_S_PSEUDO |
| 11344 | 0U, // FMLA_VG4_M4Z4Z_D_PSEUDO |
| 11345 | 0U, // FMLA_VG4_M4Z4Z_H_PSEUDO |
| 11346 | 0U, // FMLA_VG4_M4Z4Z_S_PSEUDO |
| 11347 | 0U, // FMLA_VG4_M4ZZI_D_PSEUDO |
| 11348 | 0U, // FMLA_VG4_M4ZZI_H_PSEUDO |
| 11349 | 0U, // FMLA_VG4_M4ZZI_S_PSEUDO |
| 11350 | 0U, // FMLA_VG4_M4ZZ_D_PSEUDO |
| 11351 | 0U, // FMLA_VG4_M4ZZ_H_PSEUDO |
| 11352 | 0U, // FMLA_VG4_M4ZZ_S_PSEUDO |
| 11353 | 0U, // FMLA_ZPZZZ_D_UNDEF |
| 11354 | 0U, // FMLA_ZPZZZ_H_UNDEF |
| 11355 | 0U, // FMLA_ZPZZZ_S_UNDEF |
| 11356 | 0U, // FMLSL_MZZI_HtoS_PSEUDO |
| 11357 | 0U, // FMLSL_MZZ_HtoS_PSEUDO |
| 11358 | 0U, // FMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11359 | 0U, // FMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 11360 | 0U, // FMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 11361 | 0U, // FMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11362 | 0U, // FMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 11363 | 0U, // FMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 11364 | 0U, // FMLS_VG2_M2Z2Z_D_PSEUDO |
| 11365 | 0U, // FMLS_VG2_M2Z2Z_H_PSEUDO |
| 11366 | 0U, // FMLS_VG2_M2Z2Z_S_PSEUDO |
| 11367 | 0U, // FMLS_VG2_M2ZZI_D_PSEUDO |
| 11368 | 0U, // FMLS_VG2_M2ZZI_H_PSEUDO |
| 11369 | 0U, // FMLS_VG2_M2ZZI_S_PSEUDO |
| 11370 | 0U, // FMLS_VG2_M2ZZ_D_PSEUDO |
| 11371 | 0U, // FMLS_VG2_M2ZZ_H_PSEUDO |
| 11372 | 0U, // FMLS_VG2_M2ZZ_S_PSEUDO |
| 11373 | 0U, // FMLS_VG4_M4Z4Z_D_PSEUDO |
| 11374 | 0U, // FMLS_VG4_M4Z4Z_H_PSEUDO |
| 11375 | 0U, // FMLS_VG4_M4Z4Z_S_PSEUDO |
| 11376 | 0U, // FMLS_VG4_M4ZZI_D_PSEUDO |
| 11377 | 0U, // FMLS_VG4_M4ZZI_H_PSEUDO |
| 11378 | 0U, // FMLS_VG4_M4ZZI_S_PSEUDO |
| 11379 | 0U, // FMLS_VG4_M4ZZ_D_PSEUDO |
| 11380 | 0U, // FMLS_VG4_M4ZZ_H_PSEUDO |
| 11381 | 0U, // FMLS_VG4_M4ZZ_S_PSEUDO |
| 11382 | 0U, // FMLS_ZPZZZ_D_UNDEF |
| 11383 | 0U, // FMLS_ZPZZZ_H_UNDEF |
| 11384 | 0U, // FMLS_ZPZZZ_S_UNDEF |
| 11385 | 0U, // FMOP4A_M2Z2Z_BtoH_PSEUDO |
| 11386 | 0U, // FMOP4A_M2Z2Z_BtoS_PSEUDO |
| 11387 | 0U, // FMOP4A_M2Z2Z_D_PSEUDO |
| 11388 | 0U, // FMOP4A_M2Z2Z_H_PSEUDO |
| 11389 | 0U, // FMOP4A_M2Z2Z_HtoS_PSEUDO |
| 11390 | 0U, // FMOP4A_M2Z2Z_S_PSEUDO |
| 11391 | 0U, // FMOP4A_M2ZZ_BtoH_PSEUDO |
| 11392 | 0U, // FMOP4A_M2ZZ_BtoS_PSEUDO |
| 11393 | 0U, // FMOP4A_M2ZZ_D_PSEUDO |
| 11394 | 0U, // FMOP4A_M2ZZ_H_PSEUDO |
| 11395 | 0U, // FMOP4A_M2ZZ_HtoS_PSEUDO |
| 11396 | 0U, // FMOP4A_M2ZZ_S_PSEUDO |
| 11397 | 0U, // FMOP4A_MZ2Z_BtoH_PSEUDO |
| 11398 | 0U, // FMOP4A_MZ2Z_BtoS_PSEUDO |
| 11399 | 0U, // FMOP4A_MZ2Z_D_PSEUDO |
| 11400 | 0U, // FMOP4A_MZ2Z_H_PSEUDO |
| 11401 | 0U, // FMOP4A_MZ2Z_HtoS_PSEUDO |
| 11402 | 0U, // FMOP4A_MZ2Z_S_PSEUDO |
| 11403 | 0U, // FMOP4A_MZZ_BtoH_PSEUDO |
| 11404 | 0U, // FMOP4A_MZZ_BtoS_PSEUDO |
| 11405 | 0U, // FMOP4A_MZZ_D_PSEUDO |
| 11406 | 0U, // FMOP4A_MZZ_H_PSEUDO |
| 11407 | 0U, // FMOP4A_MZZ_HtoS_PSEUDO |
| 11408 | 0U, // FMOP4A_MZZ_S_PSEUDO |
| 11409 | 0U, // FMOP4S_M2Z2Z_D_PSEUDO |
| 11410 | 0U, // FMOP4S_M2Z2Z_H_PSEUDO |
| 11411 | 0U, // FMOP4S_M2Z2Z_HtoS_PSEUDO |
| 11412 | 0U, // FMOP4S_M2Z2Z_S_PSEUDO |
| 11413 | 0U, // FMOP4S_M2ZZ_D_PSEUDO |
| 11414 | 0U, // FMOP4S_M2ZZ_H_PSEUDO |
| 11415 | 0U, // FMOP4S_M2ZZ_HtoS_PSEUDO |
| 11416 | 0U, // FMOP4S_M2ZZ_S_PSEUDO |
| 11417 | 0U, // FMOP4S_MZ2Z_D_PSEUDO |
| 11418 | 0U, // FMOP4S_MZ2Z_H_PSEUDO |
| 11419 | 0U, // FMOP4S_MZ2Z_HtoS_PSEUDO |
| 11420 | 0U, // FMOP4S_MZ2Z_S_PSEUDO |
| 11421 | 0U, // FMOP4S_MZZ_D_PSEUDO |
| 11422 | 0U, // FMOP4S_MZZ_H_PSEUDO |
| 11423 | 0U, // FMOP4S_MZZ_HtoS_PSEUDO |
| 11424 | 0U, // FMOP4S_MZZ_S_PSEUDO |
| 11425 | 0U, // FMOPAL_MPPZZ_PSEUDO |
| 11426 | 0U, // FMOPA_MPPZZ_BtoH_PSEUDO |
| 11427 | 0U, // FMOPA_MPPZZ_BtoS_PSEUDO |
| 11428 | 0U, // FMOPA_MPPZZ_D_PSEUDO |
| 11429 | 0U, // FMOPA_MPPZZ_H_PSEUDO |
| 11430 | 0U, // FMOPA_MPPZZ_S_PSEUDO |
| 11431 | 0U, // FMOPSL_MPPZZ_PSEUDO |
| 11432 | 0U, // FMOPS_MPPZZ_D_PSEUDO |
| 11433 | 0U, // FMOPS_MPPZZ_H_PSEUDO |
| 11434 | 0U, // FMOPS_MPPZZ_S_PSEUDO |
| 11435 | 0U, // FMOVD0 |
| 11436 | 0U, // FMOVH0 |
| 11437 | 0U, // FMOVS0 |
| 11438 | 0U, // FMULX_ZPZZ_D_UNDEF |
| 11439 | 0U, // FMULX_ZPZZ_D_ZERO |
| 11440 | 0U, // FMULX_ZPZZ_H_UNDEF |
| 11441 | 0U, // FMULX_ZPZZ_H_ZERO |
| 11442 | 0U, // FMULX_ZPZZ_S_UNDEF |
| 11443 | 0U, // FMULX_ZPZZ_S_ZERO |
| 11444 | 0U, // FMUL_ZPZI_D_UNDEF |
| 11445 | 0U, // FMUL_ZPZI_D_ZERO |
| 11446 | 0U, // FMUL_ZPZI_H_UNDEF |
| 11447 | 0U, // FMUL_ZPZI_H_ZERO |
| 11448 | 0U, // FMUL_ZPZI_S_UNDEF |
| 11449 | 0U, // FMUL_ZPZI_S_ZERO |
| 11450 | 0U, // FMUL_ZPZZ_D_UNDEF |
| 11451 | 0U, // FMUL_ZPZZ_D_ZERO |
| 11452 | 0U, // FMUL_ZPZZ_H_UNDEF |
| 11453 | 0U, // FMUL_ZPZZ_H_ZERO |
| 11454 | 0U, // FMUL_ZPZZ_S_UNDEF |
| 11455 | 0U, // FMUL_ZPZZ_S_ZERO |
| 11456 | 0U, // FNEG_ZPmZ_D_UNDEF |
| 11457 | 0U, // FNEG_ZPmZ_H_UNDEF |
| 11458 | 0U, // FNEG_ZPmZ_S_UNDEF |
| 11459 | 0U, // FNMLA_ZPZZZ_D_UNDEF |
| 11460 | 0U, // FNMLA_ZPZZZ_H_UNDEF |
| 11461 | 0U, // FNMLA_ZPZZZ_S_UNDEF |
| 11462 | 0U, // FNMLS_ZPZZZ_D_UNDEF |
| 11463 | 0U, // FNMLS_ZPZZZ_H_UNDEF |
| 11464 | 0U, // FNMLS_ZPZZZ_S_UNDEF |
| 11465 | 0U, // FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO |
| 11466 | 0U, // FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO |
| 11467 | 0U, // FRECPX_ZPmZ_D_UNDEF |
| 11468 | 0U, // FRECPX_ZPmZ_H_UNDEF |
| 11469 | 0U, // FRECPX_ZPmZ_S_UNDEF |
| 11470 | 0U, // FRINT32X_ZPmZ_D_UNDEF |
| 11471 | 0U, // FRINT32X_ZPmZ_S_UNDEF |
| 11472 | 0U, // FRINT32Z_ZPmZ_D_UNDEF |
| 11473 | 0U, // FRINT32Z_ZPmZ_S_UNDEF |
| 11474 | 0U, // FRINT64X_ZPmZ_D_UNDEF |
| 11475 | 0U, // FRINT64X_ZPmZ_S_UNDEF |
| 11476 | 0U, // FRINT64Z_ZPmZ_D_UNDEF |
| 11477 | 0U, // FRINT64Z_ZPmZ_S_UNDEF |
| 11478 | 0U, // FRINTA_ZPmZ_D_UNDEF |
| 11479 | 0U, // FRINTA_ZPmZ_H_UNDEF |
| 11480 | 0U, // FRINTA_ZPmZ_S_UNDEF |
| 11481 | 0U, // FRINTI_ZPmZ_D_UNDEF |
| 11482 | 0U, // FRINTI_ZPmZ_H_UNDEF |
| 11483 | 0U, // FRINTI_ZPmZ_S_UNDEF |
| 11484 | 0U, // FRINTM_ZPmZ_D_UNDEF |
| 11485 | 0U, // FRINTM_ZPmZ_H_UNDEF |
| 11486 | 0U, // FRINTM_ZPmZ_S_UNDEF |
| 11487 | 0U, // FRINTN_ZPmZ_D_UNDEF |
| 11488 | 0U, // FRINTN_ZPmZ_H_UNDEF |
| 11489 | 0U, // FRINTN_ZPmZ_S_UNDEF |
| 11490 | 0U, // FRINTP_ZPmZ_D_UNDEF |
| 11491 | 0U, // FRINTP_ZPmZ_H_UNDEF |
| 11492 | 0U, // FRINTP_ZPmZ_S_UNDEF |
| 11493 | 0U, // FRINTX_ZPmZ_D_UNDEF |
| 11494 | 0U, // FRINTX_ZPmZ_H_UNDEF |
| 11495 | 0U, // FRINTX_ZPmZ_S_UNDEF |
| 11496 | 0U, // FRINTZ_ZPmZ_D_UNDEF |
| 11497 | 0U, // FRINTZ_ZPmZ_H_UNDEF |
| 11498 | 0U, // FRINTZ_ZPmZ_S_UNDEF |
| 11499 | 0U, // FSQRT_ZPmZ_D_UNDEF |
| 11500 | 0U, // FSQRT_ZPmZ_H_UNDEF |
| 11501 | 0U, // FSQRT_ZPmZ_S_UNDEF |
| 11502 | 0U, // FSUBR_ZPZI_D_UNDEF |
| 11503 | 0U, // FSUBR_ZPZI_D_ZERO |
| 11504 | 0U, // FSUBR_ZPZI_H_UNDEF |
| 11505 | 0U, // FSUBR_ZPZI_H_ZERO |
| 11506 | 0U, // FSUBR_ZPZI_S_UNDEF |
| 11507 | 0U, // FSUBR_ZPZI_S_ZERO |
| 11508 | 0U, // FSUBR_ZPZZ_D_ZERO |
| 11509 | 0U, // FSUBR_ZPZZ_H_ZERO |
| 11510 | 0U, // FSUBR_ZPZZ_S_ZERO |
| 11511 | 0U, // FSUB_VG2_M2Z_D_PSEUDO |
| 11512 | 0U, // FSUB_VG2_M2Z_H_PSEUDO |
| 11513 | 0U, // FSUB_VG2_M2Z_S_PSEUDO |
| 11514 | 0U, // FSUB_VG4_M4Z_D_PSEUDO |
| 11515 | 0U, // FSUB_VG4_M4Z_H_PSEUDO |
| 11516 | 0U, // FSUB_VG4_M4Z_S_PSEUDO |
| 11517 | 0U, // FSUB_ZPZI_D_UNDEF |
| 11518 | 0U, // FSUB_ZPZI_D_ZERO |
| 11519 | 0U, // FSUB_ZPZI_H_UNDEF |
| 11520 | 0U, // FSUB_ZPZI_H_ZERO |
| 11521 | 0U, // FSUB_ZPZI_S_UNDEF |
| 11522 | 0U, // FSUB_ZPZI_S_ZERO |
| 11523 | 0U, // FSUB_ZPZZ_D_UNDEF |
| 11524 | 0U, // FSUB_ZPZZ_D_ZERO |
| 11525 | 0U, // FSUB_ZPZZ_H_UNDEF |
| 11526 | 0U, // FSUB_ZPZZ_H_ZERO |
| 11527 | 0U, // FSUB_ZPZZ_S_UNDEF |
| 11528 | 0U, // FSUB_ZPZZ_S_ZERO |
| 11529 | 0U, // FTMOPA_M2ZZZI_BtoH_PSEUDO |
| 11530 | 0U, // FTMOPA_M2ZZZI_BtoS_PSEUDO |
| 11531 | 0U, // FTMOPA_M2ZZZI_HtoH_PSEUDO |
| 11532 | 0U, // FTMOPA_M2ZZZI_HtoS_PSEUDO |
| 11533 | 0U, // FTMOPA_M2ZZZI_StoS_PSEUDO |
| 11534 | 0U, // FVDOTB_VG4_M2ZZI_BtoS_PSEUDO |
| 11535 | 0U, // FVDOTT_VG4_M2ZZI_BtoS_PSEUDO |
| 11536 | 0U, // FVDOT_VG2_M2ZZI_BtoH_PSEUDO |
| 11537 | 0U, // FVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 11538 | 0U, // G_AARCH64_PREFETCH |
| 11539 | 0U, // G_AARCH64_RANGE_PREFETCH |
| 11540 | 0U, // G_ADD_LOW |
| 11541 | 0U, // G_BSP |
| 11542 | 0U, // G_DUP |
| 11543 | 0U, // G_DUPLANE16 |
| 11544 | 0U, // G_DUPLANE32 |
| 11545 | 0U, // G_DUPLANE64 |
| 11546 | 0U, // G_DUPLANE8 |
| 11547 | 0U, // G_EXT |
| 11548 | 0U, // G_FCMEQ |
| 11549 | 0U, // G_FCMGE |
| 11550 | 0U, // G_FCMGT |
| 11551 | 0U, // G_FPTRUNC_ODD |
| 11552 | 0U, // G_PMULL |
| 11553 | 0U, // G_REV32 |
| 11554 | 0U, // G_REV64 |
| 11555 | 0U, // G_SADDLP |
| 11556 | 0U, // G_SADDLV |
| 11557 | 0U, // G_SDOT |
| 11558 | 0U, // G_SITOF |
| 11559 | 0U, // G_SLI |
| 11560 | 0U, // G_SMULL |
| 11561 | 0U, // G_SQSHLU_I |
| 11562 | 0U, // G_SRI |
| 11563 | 0U, // G_SRSHR_I |
| 11564 | 0U, // G_TRN1 |
| 11565 | 0U, // G_TRN2 |
| 11566 | 0U, // G_UADDLP |
| 11567 | 0U, // G_UADDLV |
| 11568 | 0U, // G_UDOT |
| 11569 | 0U, // G_UITOF |
| 11570 | 0U, // G_UMULL |
| 11571 | 0U, // G_URSHR_I |
| 11572 | 0U, // G_USDOT |
| 11573 | 0U, // G_UZP1 |
| 11574 | 0U, // G_UZP2 |
| 11575 | 0U, // G_VASHR |
| 11576 | 0U, // G_VLSHR |
| 11577 | 0U, // G_ZIP1 |
| 11578 | 0U, // G_ZIP2 |
| 11579 | 0U, // GetSMESaveSize |
| 11580 | 0U, // HOM_Epilog |
| 11581 | 0U, // HOM_Prolog |
| 11582 | 0U, // HWASAN_CHECK_MEMACCESS |
| 11583 | 0U, // HWASAN_CHECK_MEMACCESS_FIXEDSHADOW |
| 11584 | 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| 11585 | 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW |
| 11586 | 0U, // INSERT_MXIPZ_H_PSEUDO_B |
| 11587 | 0U, // INSERT_MXIPZ_H_PSEUDO_D |
| 11588 | 0U, // INSERT_MXIPZ_H_PSEUDO_H |
| 11589 | 0U, // INSERT_MXIPZ_H_PSEUDO_Q |
| 11590 | 0U, // INSERT_MXIPZ_H_PSEUDO_S |
| 11591 | 0U, // INSERT_MXIPZ_V_PSEUDO_B |
| 11592 | 0U, // INSERT_MXIPZ_V_PSEUDO_D |
| 11593 | 0U, // INSERT_MXIPZ_V_PSEUDO_H |
| 11594 | 0U, // INSERT_MXIPZ_V_PSEUDO_Q |
| 11595 | 0U, // INSERT_MXIPZ_V_PSEUDO_S |
| 11596 | 0U, // IRGstack |
| 11597 | 0U, // InOutZAUsePseudo |
| 11598 | 0U, // InitTPIDR2Obj |
| 11599 | 0U, // JumpTableDest16 |
| 11600 | 0U, // JumpTableDest32 |
| 11601 | 0U, // JumpTableDest8 |
| 11602 | 0U, // KCFI_CHECK |
| 11603 | 0U, // LD1B_2Z_IMM_PSEUDO |
| 11604 | 0U, // LD1B_2Z_PSEUDO |
| 11605 | 0U, // LD1B_4Z_IMM_PSEUDO |
| 11606 | 0U, // LD1B_4Z_PSEUDO |
| 11607 | 0U, // LD1D_2Z_IMM_PSEUDO |
| 11608 | 0U, // LD1D_2Z_PSEUDO |
| 11609 | 0U, // LD1D_4Z_IMM_PSEUDO |
| 11610 | 0U, // LD1D_4Z_PSEUDO |
| 11611 | 0U, // LD1H_2Z_IMM_PSEUDO |
| 11612 | 0U, // LD1H_2Z_PSEUDO |
| 11613 | 0U, // LD1H_4Z_IMM_PSEUDO |
| 11614 | 0U, // LD1H_4Z_PSEUDO |
| 11615 | 0U, // LD1W_2Z_IMM_PSEUDO |
| 11616 | 0U, // LD1W_2Z_PSEUDO |
| 11617 | 0U, // LD1W_4Z_IMM_PSEUDO |
| 11618 | 0U, // LD1W_4Z_PSEUDO |
| 11619 | 0U, // LD1_MXIPXX_H_PSEUDO_B |
| 11620 | 0U, // LD1_MXIPXX_H_PSEUDO_D |
| 11621 | 0U, // LD1_MXIPXX_H_PSEUDO_H |
| 11622 | 0U, // LD1_MXIPXX_H_PSEUDO_Q |
| 11623 | 0U, // LD1_MXIPXX_H_PSEUDO_S |
| 11624 | 0U, // LD1_MXIPXX_V_PSEUDO_B |
| 11625 | 0U, // LD1_MXIPXX_V_PSEUDO_D |
| 11626 | 0U, // LD1_MXIPXX_V_PSEUDO_H |
| 11627 | 0U, // LD1_MXIPXX_V_PSEUDO_Q |
| 11628 | 0U, // LD1_MXIPXX_V_PSEUDO_S |
| 11629 | 0U, // LDNT1B_2Z_IMM_PSEUDO |
| 11630 | 0U, // LDNT1B_2Z_PSEUDO |
| 11631 | 0U, // LDNT1B_4Z_IMM_PSEUDO |
| 11632 | 0U, // LDNT1B_4Z_PSEUDO |
| 11633 | 0U, // LDNT1D_2Z_IMM_PSEUDO |
| 11634 | 0U, // LDNT1D_2Z_PSEUDO |
| 11635 | 0U, // LDNT1D_4Z_IMM_PSEUDO |
| 11636 | 0U, // LDNT1D_4Z_PSEUDO |
| 11637 | 0U, // LDNT1H_2Z_IMM_PSEUDO |
| 11638 | 0U, // LDNT1H_2Z_PSEUDO |
| 11639 | 0U, // LDNT1H_4Z_IMM_PSEUDO |
| 11640 | 0U, // LDNT1H_4Z_PSEUDO |
| 11641 | 0U, // LDNT1W_2Z_IMM_PSEUDO |
| 11642 | 0U, // LDNT1W_2Z_PSEUDO |
| 11643 | 0U, // LDNT1W_4Z_IMM_PSEUDO |
| 11644 | 0U, // LDNT1W_4Z_PSEUDO |
| 11645 | 0U, // LDR_PPXI |
| 11646 | 0U, // LDR_TX_PSEUDO |
| 11647 | 0U, // LDR_ZA_PSEUDO |
| 11648 | 0U, // LDR_ZZXI |
| 11649 | 0U, // LDR_ZZXI_STRIDED_CONTIGUOUS |
| 11650 | 0U, // LDR_ZZZXI |
| 11651 | 0U, // LDR_ZZZZXI |
| 11652 | 0U, // LDR_ZZZZXI_STRIDED_CONTIGUOUS |
| 11653 | 0U, // LOADauthptrstatic |
| 11654 | 0U, // LOADgot |
| 11655 | 0U, // LOADgotAUTH |
| 11656 | 0U, // LOADgotPAC |
| 11657 | 0U, // LSL_ZPZI_B_UNDEF |
| 11658 | 0U, // LSL_ZPZI_B_ZERO |
| 11659 | 0U, // LSL_ZPZI_D_UNDEF |
| 11660 | 0U, // LSL_ZPZI_D_ZERO |
| 11661 | 0U, // LSL_ZPZI_H_UNDEF |
| 11662 | 0U, // LSL_ZPZI_H_ZERO |
| 11663 | 0U, // LSL_ZPZI_S_UNDEF |
| 11664 | 0U, // LSL_ZPZI_S_ZERO |
| 11665 | 0U, // LSL_ZPZZ_B_UNDEF |
| 11666 | 0U, // LSL_ZPZZ_B_ZERO |
| 11667 | 0U, // LSL_ZPZZ_D_UNDEF |
| 11668 | 0U, // LSL_ZPZZ_D_ZERO |
| 11669 | 0U, // LSL_ZPZZ_H_UNDEF |
| 11670 | 0U, // LSL_ZPZZ_H_ZERO |
| 11671 | 0U, // LSL_ZPZZ_S_UNDEF |
| 11672 | 0U, // LSL_ZPZZ_S_ZERO |
| 11673 | 0U, // LSR_ZPZI_B_UNDEF |
| 11674 | 0U, // LSR_ZPZI_B_ZERO |
| 11675 | 0U, // LSR_ZPZI_D_UNDEF |
| 11676 | 0U, // LSR_ZPZI_D_ZERO |
| 11677 | 0U, // LSR_ZPZI_H_UNDEF |
| 11678 | 0U, // LSR_ZPZI_H_ZERO |
| 11679 | 0U, // LSR_ZPZI_S_UNDEF |
| 11680 | 0U, // LSR_ZPZI_S_ZERO |
| 11681 | 0U, // LSR_ZPZZ_B_UNDEF |
| 11682 | 0U, // LSR_ZPZZ_B_ZERO |
| 11683 | 0U, // LSR_ZPZZ_D_UNDEF |
| 11684 | 0U, // LSR_ZPZZ_D_ZERO |
| 11685 | 0U, // LSR_ZPZZ_H_UNDEF |
| 11686 | 0U, // LSR_ZPZZ_H_ZERO |
| 11687 | 0U, // LSR_ZPZZ_S_UNDEF |
| 11688 | 0U, // LSR_ZPZZ_S_ZERO |
| 11689 | 0U, // MLA_ZPZZZ_B_UNDEF |
| 11690 | 0U, // MLA_ZPZZZ_D_UNDEF |
| 11691 | 0U, // MLA_ZPZZZ_H_UNDEF |
| 11692 | 0U, // MLA_ZPZZZ_S_UNDEF |
| 11693 | 0U, // MLS_ZPZZZ_B_UNDEF |
| 11694 | 0U, // MLS_ZPZZZ_D_UNDEF |
| 11695 | 0U, // MLS_ZPZZZ_H_UNDEF |
| 11696 | 0U, // MLS_ZPZZZ_S_UNDEF |
| 11697 | 0U, // MOPSMemoryCopyPseudo |
| 11698 | 0U, // MOPSMemoryMovePseudo |
| 11699 | 0U, // MOPSMemorySetPseudo |
| 11700 | 0U, // MOPSMemorySetTaggingPseudo |
| 11701 | 0U, // MOVAZ_2ZMI_H_B_PSEUDO |
| 11702 | 0U, // MOVAZ_2ZMI_H_D_PSEUDO |
| 11703 | 0U, // MOVAZ_2ZMI_H_H_PSEUDO |
| 11704 | 0U, // MOVAZ_2ZMI_H_S_PSEUDO |
| 11705 | 0U, // MOVAZ_2ZMI_V_B_PSEUDO |
| 11706 | 0U, // MOVAZ_2ZMI_V_D_PSEUDO |
| 11707 | 0U, // MOVAZ_2ZMI_V_H_PSEUDO |
| 11708 | 0U, // MOVAZ_2ZMI_V_S_PSEUDO |
| 11709 | 0U, // MOVAZ_4ZMI_H_B_PSEUDO |
| 11710 | 0U, // MOVAZ_4ZMI_H_D_PSEUDO |
| 11711 | 0U, // MOVAZ_4ZMI_H_H_PSEUDO |
| 11712 | 0U, // MOVAZ_4ZMI_H_S_PSEUDO |
| 11713 | 0U, // MOVAZ_4ZMI_V_B_PSEUDO |
| 11714 | 0U, // MOVAZ_4ZMI_V_D_PSEUDO |
| 11715 | 0U, // MOVAZ_4ZMI_V_H_PSEUDO |
| 11716 | 0U, // MOVAZ_4ZMI_V_S_PSEUDO |
| 11717 | 0U, // MOVAZ_VG2_2ZMXI_PSEUDO |
| 11718 | 0U, // MOVAZ_VG4_4ZMXI_PSEUDO |
| 11719 | 0U, // MOVAZ_ZMI_H_B_PSEUDO |
| 11720 | 0U, // MOVAZ_ZMI_H_D_PSEUDO |
| 11721 | 0U, // MOVAZ_ZMI_H_H_PSEUDO |
| 11722 | 0U, // MOVAZ_ZMI_H_Q_PSEUDO |
| 11723 | 0U, // MOVAZ_ZMI_H_S_PSEUDO |
| 11724 | 0U, // MOVAZ_ZMI_V_B_PSEUDO |
| 11725 | 0U, // MOVAZ_ZMI_V_D_PSEUDO |
| 11726 | 0U, // MOVAZ_ZMI_V_H_PSEUDO |
| 11727 | 0U, // MOVAZ_ZMI_V_Q_PSEUDO |
| 11728 | 0U, // MOVAZ_ZMI_V_S_PSEUDO |
| 11729 | 0U, // MOVA_MXI2Z_H_B_PSEUDO |
| 11730 | 0U, // MOVA_MXI2Z_H_D_PSEUDO |
| 11731 | 0U, // MOVA_MXI2Z_H_H_PSEUDO |
| 11732 | 0U, // MOVA_MXI2Z_H_S_PSEUDO |
| 11733 | 0U, // MOVA_MXI2Z_V_B_PSEUDO |
| 11734 | 0U, // MOVA_MXI2Z_V_D_PSEUDO |
| 11735 | 0U, // MOVA_MXI2Z_V_H_PSEUDO |
| 11736 | 0U, // MOVA_MXI2Z_V_S_PSEUDO |
| 11737 | 0U, // MOVA_MXI4Z_H_B_PSEUDO |
| 11738 | 0U, // MOVA_MXI4Z_H_D_PSEUDO |
| 11739 | 0U, // MOVA_MXI4Z_H_H_PSEUDO |
| 11740 | 0U, // MOVA_MXI4Z_H_S_PSEUDO |
| 11741 | 0U, // MOVA_MXI4Z_V_B_PSEUDO |
| 11742 | 0U, // MOVA_MXI4Z_V_D_PSEUDO |
| 11743 | 0U, // MOVA_MXI4Z_V_H_PSEUDO |
| 11744 | 0U, // MOVA_MXI4Z_V_S_PSEUDO |
| 11745 | 0U, // MOVA_VG2_MXI2Z_PSEUDO |
| 11746 | 0U, // MOVA_VG4_MXI4Z_PSEUDO |
| 11747 | 0U, // MOVMCSym |
| 11748 | 0U, // MOVT_TIZ_PSEUDO |
| 11749 | 0U, // MOVaddr |
| 11750 | 0U, // MOVaddrBA |
| 11751 | 0U, // MOVaddrCP |
| 11752 | 0U, // MOVaddrEXT |
| 11753 | 0U, // MOVaddrJT |
| 11754 | 0U, // MOVaddrPAC |
| 11755 | 0U, // MOVaddrTLS |
| 11756 | 0U, // MOVbaseTLS |
| 11757 | 0U, // MOVi32imm |
| 11758 | 0U, // MOVi64imm |
| 11759 | 0U, // MRS_FPCR |
| 11760 | 0U, // MRS_FPSR |
| 11761 | 0U, // MSR_FPCR |
| 11762 | 0U, // MSR_FPMR |
| 11763 | 0U, // MSR_FPSR |
| 11764 | 0U, // MSRpstatePseudo |
| 11765 | 0U, // MUL_ZPZZ_B_UNDEF |
| 11766 | 0U, // MUL_ZPZZ_D_UNDEF |
| 11767 | 0U, // MUL_ZPZZ_H_UNDEF |
| 11768 | 0U, // MUL_ZPZZ_S_UNDEF |
| 11769 | 0U, // NAND_ZZZ |
| 11770 | 0U, // NEG_ZPmZ_B_UNDEF |
| 11771 | 0U, // NEG_ZPmZ_D_UNDEF |
| 11772 | 0U, // NEG_ZPmZ_H_UNDEF |
| 11773 | 0U, // NEG_ZPmZ_S_UNDEF |
| 11774 | 0U, // NOR_ZZZ |
| 11775 | 0U, // NOT_ZPmZ_B_UNDEF |
| 11776 | 0U, // NOT_ZPmZ_D_UNDEF |
| 11777 | 0U, // NOT_ZPmZ_H_UNDEF |
| 11778 | 0U, // NOT_ZPmZ_S_UNDEF |
| 11779 | 0U, // ORNWrr |
| 11780 | 0U, // ORNXrr |
| 11781 | 0U, // ORRWrr |
| 11782 | 0U, // ORRXrr |
| 11783 | 0U, // ORR_ZPZZ_B_ZERO |
| 11784 | 0U, // ORR_ZPZZ_D_ZERO |
| 11785 | 0U, // ORR_ZPZZ_H_ZERO |
| 11786 | 0U, // ORR_ZPZZ_S_ZERO |
| 11787 | 0U, // PAC |
| 11788 | 0U, // PAUTH_EPILOGUE |
| 11789 | 0U, // PAUTH_PROLOGUE |
| 11790 | 0U, // PROBED_STACKALLOC |
| 11791 | 0U, // PROBED_STACKALLOC_DYN |
| 11792 | 0U, // PROBED_STACKALLOC_VAR |
| 11793 | 0U, // PTEST_PP_ANY |
| 11794 | 0U, // PTEST_PP_FIRST |
| 11795 | 0U, // RET_ReallyLR |
| 11796 | 0U, // RequiresZASavePseudo |
| 11797 | 0U, // RequiresZT0SavePseudo |
| 11798 | 0U, // RestoreZAPseudo |
| 11799 | 0U, // SABD_ZPZZ_B_UNDEF |
| 11800 | 0U, // SABD_ZPZZ_D_UNDEF |
| 11801 | 0U, // SABD_ZPZZ_H_UNDEF |
| 11802 | 0U, // SABD_ZPZZ_S_UNDEF |
| 11803 | 0U, // SCVTF_ZPmZ_DtoD_UNDEF |
| 11804 | 0U, // SCVTF_ZPmZ_DtoH_UNDEF |
| 11805 | 0U, // SCVTF_ZPmZ_DtoS_UNDEF |
| 11806 | 0U, // SCVTF_ZPmZ_HtoH_UNDEF |
| 11807 | 0U, // SCVTF_ZPmZ_StoD_UNDEF |
| 11808 | 0U, // SCVTF_ZPmZ_StoH_UNDEF |
| 11809 | 0U, // SCVTF_ZPmZ_StoS_UNDEF |
| 11810 | 0U, // SDIV_ZPZZ_D_UNDEF |
| 11811 | 0U, // SDIV_ZPZZ_S_UNDEF |
| 11812 | 0U, // SDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 11813 | 0U, // SDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 11814 | 0U, // SDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 11815 | 0U, // SDOT_VG2_M2ZZI_BToS_PSEUDO |
| 11816 | 0U, // SDOT_VG2_M2ZZI_HToS_PSEUDO |
| 11817 | 0U, // SDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 11818 | 0U, // SDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 11819 | 0U, // SDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 11820 | 0U, // SDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 11821 | 0U, // SDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 11822 | 0U, // SDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 11823 | 0U, // SDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 11824 | 0U, // SDOT_VG4_M4ZZI_BToS_PSEUDO |
| 11825 | 0U, // SDOT_VG4_M4ZZI_HToS_PSEUDO |
| 11826 | 0U, // SDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 11827 | 0U, // SDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 11828 | 0U, // SDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 11829 | 0U, // SDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 11830 | 0U, // SEH_AddFP |
| 11831 | 0U, // SEH_AllocZ |
| 11832 | 0U, // SEH_EpilogEnd |
| 11833 | 0U, // SEH_EpilogStart |
| 11834 | 0U, // SEH_Nop |
| 11835 | 0U, // SEH_PACSignLR |
| 11836 | 0U, // SEH_PrologEnd |
| 11837 | 0U, // SEH_SaveAnyRegI |
| 11838 | 0U, // SEH_SaveAnyRegIP |
| 11839 | 0U, // SEH_SaveAnyRegQP |
| 11840 | 0U, // SEH_SaveAnyRegQPX |
| 11841 | 0U, // SEH_SaveFPLR |
| 11842 | 0U, // SEH_SaveFPLR_X |
| 11843 | 0U, // SEH_SaveFReg |
| 11844 | 0U, // SEH_SaveFRegP |
| 11845 | 0U, // SEH_SaveFRegP_X |
| 11846 | 0U, // SEH_SaveFReg_X |
| 11847 | 0U, // SEH_SavePReg |
| 11848 | 0U, // SEH_SaveReg |
| 11849 | 0U, // SEH_SaveRegP |
| 11850 | 0U, // SEH_SaveRegP_X |
| 11851 | 0U, // SEH_SaveReg_X |
| 11852 | 0U, // SEH_SaveZReg |
| 11853 | 0U, // SEH_SetFP |
| 11854 | 0U, // SEH_StackAlloc |
| 11855 | 0U, // SHSUB_ZPZZ_B_UNDEF |
| 11856 | 0U, // SHSUB_ZPZZ_D_UNDEF |
| 11857 | 0U, // SHSUB_ZPZZ_H_UNDEF |
| 11858 | 0U, // SHSUB_ZPZZ_S_UNDEF |
| 11859 | 0U, // SMAX_ZPZZ_B_UNDEF |
| 11860 | 0U, // SMAX_ZPZZ_D_UNDEF |
| 11861 | 0U, // SMAX_ZPZZ_H_UNDEF |
| 11862 | 0U, // SMAX_ZPZZ_S_UNDEF |
| 11863 | 0U, // SMEStateAllocPseudo |
| 11864 | 0U, // SMIN_ZPZZ_B_UNDEF |
| 11865 | 0U, // SMIN_ZPZZ_D_UNDEF |
| 11866 | 0U, // SMIN_ZPZZ_H_UNDEF |
| 11867 | 0U, // SMIN_ZPZZ_S_UNDEF |
| 11868 | 0U, // SMLALL_MZZI_BtoS_PSEUDO |
| 11869 | 0U, // SMLALL_MZZI_HtoD_PSEUDO |
| 11870 | 0U, // SMLALL_MZZ_BtoS_PSEUDO |
| 11871 | 0U, // SMLALL_MZZ_HtoD_PSEUDO |
| 11872 | 0U, // SMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 11873 | 0U, // SMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 11874 | 0U, // SMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 11875 | 0U, // SMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 11876 | 0U, // SMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 11877 | 0U, // SMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 11878 | 0U, // SMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 11879 | 0U, // SMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 11880 | 0U, // SMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 11881 | 0U, // SMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 11882 | 0U, // SMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 11883 | 0U, // SMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 11884 | 0U, // SMLAL_MZZI_HtoS_PSEUDO |
| 11885 | 0U, // SMLAL_MZZ_HtoS_PSEUDO |
| 11886 | 0U, // SMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11887 | 0U, // SMLAL_VG2_M2ZZI_S_PSEUDO |
| 11888 | 0U, // SMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 11889 | 0U, // SMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11890 | 0U, // SMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 11891 | 0U, // SMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 11892 | 0U, // SMLSLL_MZZI_BtoS_PSEUDO |
| 11893 | 0U, // SMLSLL_MZZI_HtoD_PSEUDO |
| 11894 | 0U, // SMLSLL_MZZ_BtoS_PSEUDO |
| 11895 | 0U, // SMLSLL_MZZ_HtoD_PSEUDO |
| 11896 | 0U, // SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 11897 | 0U, // SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 11898 | 0U, // SMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 11899 | 0U, // SMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 11900 | 0U, // SMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 11901 | 0U, // SMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 11902 | 0U, // SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 11903 | 0U, // SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 11904 | 0U, // SMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 11905 | 0U, // SMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 11906 | 0U, // SMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 11907 | 0U, // SMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 11908 | 0U, // SMLSL_MZZI_HtoS_PSEUDO |
| 11909 | 0U, // SMLSL_MZZ_HtoS_PSEUDO |
| 11910 | 0U, // SMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 11911 | 0U, // SMLSL_VG2_M2ZZI_S_PSEUDO |
| 11912 | 0U, // SMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 11913 | 0U, // SMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 11914 | 0U, // SMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 11915 | 0U, // SMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 11916 | 0U, // SMOP4A_M2Z2Z_BToS_PSEUDO |
| 11917 | 0U, // SMOP4A_M2Z2Z_HToS_PSEUDO |
| 11918 | 0U, // SMOP4A_M2Z2Z_HtoD_PSEUDO |
| 11919 | 0U, // SMOP4A_M2ZZ_BToS_PSEUDO |
| 11920 | 0U, // SMOP4A_M2ZZ_HToS_PSEUDO |
| 11921 | 0U, // SMOP4A_M2ZZ_HtoD_PSEUDO |
| 11922 | 0U, // SMOP4A_MZ2Z_BToS_PSEUDO |
| 11923 | 0U, // SMOP4A_MZ2Z_HToS_PSEUDO |
| 11924 | 0U, // SMOP4A_MZ2Z_HtoD_PSEUDO |
| 11925 | 0U, // SMOP4A_MZZ_BToS_PSEUDO |
| 11926 | 0U, // SMOP4A_MZZ_HToS_PSEUDO |
| 11927 | 0U, // SMOP4A_MZZ_HtoD_PSEUDO |
| 11928 | 0U, // SMOP4S_M2Z2Z_BToS_PSEUDO |
| 11929 | 0U, // SMOP4S_M2Z2Z_HToS_PSEUDO |
| 11930 | 0U, // SMOP4S_M2Z2Z_HtoD_PSEUDO |
| 11931 | 0U, // SMOP4S_M2ZZ_BToS_PSEUDO |
| 11932 | 0U, // SMOP4S_M2ZZ_HToS_PSEUDO |
| 11933 | 0U, // SMOP4S_M2ZZ_HtoD_PSEUDO |
| 11934 | 0U, // SMOP4S_MZ2Z_BToS_PSEUDO |
| 11935 | 0U, // SMOP4S_MZ2Z_HToS_PSEUDO |
| 11936 | 0U, // SMOP4S_MZ2Z_HtoD_PSEUDO |
| 11937 | 0U, // SMOP4S_MZZ_BToS_PSEUDO |
| 11938 | 0U, // SMOP4S_MZZ_HToS_PSEUDO |
| 11939 | 0U, // SMOP4S_MZZ_HtoD_PSEUDO |
| 11940 | 0U, // SMOPA_MPPZZ_D_PSEUDO |
| 11941 | 0U, // SMOPA_MPPZZ_HtoS_PSEUDO |
| 11942 | 0U, // SMOPA_MPPZZ_S_PSEUDO |
| 11943 | 0U, // SMOPS_MPPZZ_D_PSEUDO |
| 11944 | 0U, // SMOPS_MPPZZ_HtoS_PSEUDO |
| 11945 | 0U, // SMOPS_MPPZZ_S_PSEUDO |
| 11946 | 0U, // SMULH_ZPZZ_B_UNDEF |
| 11947 | 0U, // SMULH_ZPZZ_D_UNDEF |
| 11948 | 0U, // SMULH_ZPZZ_H_UNDEF |
| 11949 | 0U, // SMULH_ZPZZ_S_UNDEF |
| 11950 | 0U, // SPACE |
| 11951 | 0U, // SQABS_ZPmZ_B_UNDEF |
| 11952 | 0U, // SQABS_ZPmZ_D_UNDEF |
| 11953 | 0U, // SQABS_ZPmZ_H_UNDEF |
| 11954 | 0U, // SQABS_ZPmZ_S_UNDEF |
| 11955 | 0U, // SQADD_ZI_B_PSEUDO |
| 11956 | 0U, // SQADD_ZI_D_PSEUDO |
| 11957 | 0U, // SQADD_ZI_H_PSEUDO |
| 11958 | 0U, // SQADD_ZI_S_PSEUDO |
| 11959 | 0U, // SQNEG_ZPmZ_B_UNDEF |
| 11960 | 0U, // SQNEG_ZPmZ_D_UNDEF |
| 11961 | 0U, // SQNEG_ZPmZ_H_UNDEF |
| 11962 | 0U, // SQNEG_ZPmZ_S_UNDEF |
| 11963 | 0U, // SQRSHL_ZPZZ_B_UNDEF |
| 11964 | 0U, // SQRSHL_ZPZZ_D_UNDEF |
| 11965 | 0U, // SQRSHL_ZPZZ_H_UNDEF |
| 11966 | 0U, // SQRSHL_ZPZZ_S_UNDEF |
| 11967 | 0U, // SQSHLU_ZPZI_B_ZERO |
| 11968 | 0U, // SQSHLU_ZPZI_D_ZERO |
| 11969 | 0U, // SQSHLU_ZPZI_H_ZERO |
| 11970 | 0U, // SQSHLU_ZPZI_S_ZERO |
| 11971 | 0U, // SQSHL_ZPZI_B_UNDEF |
| 11972 | 0U, // SQSHL_ZPZI_B_ZERO |
| 11973 | 0U, // SQSHL_ZPZI_D_UNDEF |
| 11974 | 0U, // SQSHL_ZPZI_D_ZERO |
| 11975 | 0U, // SQSHL_ZPZI_H_UNDEF |
| 11976 | 0U, // SQSHL_ZPZI_H_ZERO |
| 11977 | 0U, // SQSHL_ZPZI_S_UNDEF |
| 11978 | 0U, // SQSHL_ZPZI_S_ZERO |
| 11979 | 0U, // SQSHL_ZPZZ_B_UNDEF |
| 11980 | 0U, // SQSHL_ZPZZ_D_UNDEF |
| 11981 | 0U, // SQSHL_ZPZZ_H_UNDEF |
| 11982 | 0U, // SQSHL_ZPZZ_S_UNDEF |
| 11983 | 0U, // SQSUB_ZI_B_PSEUDO |
| 11984 | 0U, // SQSUB_ZI_D_PSEUDO |
| 11985 | 0U, // SQSUB_ZI_H_PSEUDO |
| 11986 | 0U, // SQSUB_ZI_S_PSEUDO |
| 11987 | 0U, // SRSHL_ZPZZ_B_UNDEF |
| 11988 | 0U, // SRSHL_ZPZZ_D_UNDEF |
| 11989 | 0U, // SRSHL_ZPZZ_H_UNDEF |
| 11990 | 0U, // SRSHL_ZPZZ_S_UNDEF |
| 11991 | 0U, // SRSHR_ZPZI_B_ZERO |
| 11992 | 0U, // SRSHR_ZPZI_D_ZERO |
| 11993 | 0U, // SRSHR_ZPZI_H_ZERO |
| 11994 | 0U, // SRSHR_ZPZI_S_ZERO |
| 11995 | 0U, // STGloop |
| 11996 | 0U, // STGloop_wback |
| 11997 | 0U, // STMOPA_M2ZZZI_BtoS_PSEUDO |
| 11998 | 0U, // STMOPA_M2ZZZI_HtoS_PSEUDO |
| 11999 | 0U, // STR_PPXI |
| 12000 | 0U, // STR_TX_PSEUDO |
| 12001 | 0U, // STR_ZZXI |
| 12002 | 0U, // STR_ZZXI_STRIDED_CONTIGUOUS |
| 12003 | 0U, // STR_ZZZXI |
| 12004 | 0U, // STR_ZZZZXI |
| 12005 | 0U, // STR_ZZZZXI_STRIDED_CONTIGUOUS |
| 12006 | 0U, // STSHH_ATOMIC_STORE_SZ |
| 12007 | 0U, // STZGloop |
| 12008 | 0U, // STZGloop_wback |
| 12009 | 0U, // SUBR_ZI_B_PSEUDO |
| 12010 | 0U, // SUBR_ZI_D_PSEUDO |
| 12011 | 0U, // SUBR_ZI_H_PSEUDO |
| 12012 | 0U, // SUBR_ZI_S_PSEUDO |
| 12013 | 0U, // SUBR_ZPZZ_B_ZERO |
| 12014 | 0U, // SUBR_ZPZZ_D_ZERO |
| 12015 | 0U, // SUBR_ZPZZ_H_ZERO |
| 12016 | 0U, // SUBR_ZPZZ_S_ZERO |
| 12017 | 0U, // SUBSWrr |
| 12018 | 0U, // SUBSXrr |
| 12019 | 0U, // SUBWrr |
| 12020 | 0U, // SUBXrr |
| 12021 | 0U, // SUB_VG2_M2Z2Z_D_PSEUDO |
| 12022 | 0U, // SUB_VG2_M2Z2Z_S_PSEUDO |
| 12023 | 0U, // SUB_VG2_M2ZZ_D_PSEUDO |
| 12024 | 0U, // SUB_VG2_M2ZZ_S_PSEUDO |
| 12025 | 0U, // SUB_VG2_M2Z_D_PSEUDO |
| 12026 | 0U, // SUB_VG2_M2Z_S_PSEUDO |
| 12027 | 0U, // SUB_VG4_M4Z4Z_D_PSEUDO |
| 12028 | 0U, // SUB_VG4_M4Z4Z_S_PSEUDO |
| 12029 | 0U, // SUB_VG4_M4ZZ_D_PSEUDO |
| 12030 | 0U, // SUB_VG4_M4ZZ_S_PSEUDO |
| 12031 | 0U, // SUB_VG4_M4Z_D_PSEUDO |
| 12032 | 0U, // SUB_VG4_M4Z_S_PSEUDO |
| 12033 | 0U, // SUB_ZI_B_PSEUDO |
| 12034 | 0U, // SUB_ZI_D_PSEUDO |
| 12035 | 0U, // SUB_ZI_H_PSEUDO |
| 12036 | 0U, // SUB_ZI_S_PSEUDO |
| 12037 | 0U, // SUB_ZPZZ_B_ZERO |
| 12038 | 0U, // SUB_ZPZZ_D_ZERO |
| 12039 | 0U, // SUB_ZPZZ_H_ZERO |
| 12040 | 0U, // SUB_ZPZZ_S_ZERO |
| 12041 | 0U, // SUDOT_VG2_M2ZZI_BToS_PSEUDO |
| 12042 | 0U, // SUDOT_VG2_M2ZZ_BToS_PSEUDO |
| 12043 | 0U, // SUDOT_VG4_M4ZZI_BToS_PSEUDO |
| 12044 | 0U, // SUDOT_VG4_M4ZZ_BToS_PSEUDO |
| 12045 | 0U, // SUMLALL_MZZI_BtoS_PSEUDO |
| 12046 | 0U, // SUMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 12047 | 0U, // SUMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 12048 | 0U, // SUMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 12049 | 0U, // SUMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 12050 | 0U, // SUMOP4A_M2Z2Z_BToS_PSEUDO |
| 12051 | 0U, // SUMOP4A_M2Z2Z_HtoD_PSEUDO |
| 12052 | 0U, // SUMOP4A_M2ZZ_BToS_PSEUDO |
| 12053 | 0U, // SUMOP4A_M2ZZ_HtoD_PSEUDO |
| 12054 | 0U, // SUMOP4A_MZ2Z_BToS_PSEUDO |
| 12055 | 0U, // SUMOP4A_MZ2Z_HtoD_PSEUDO |
| 12056 | 0U, // SUMOP4A_MZZ_BToS_PSEUDO |
| 12057 | 0U, // SUMOP4A_MZZ_HtoD_PSEUDO |
| 12058 | 0U, // SUMOP4S_M2Z2Z_BToS_PSEUDO |
| 12059 | 0U, // SUMOP4S_M2Z2Z_HtoD_PSEUDO |
| 12060 | 0U, // SUMOP4S_M2ZZ_BToS_PSEUDO |
| 12061 | 0U, // SUMOP4S_M2ZZ_HtoD_PSEUDO |
| 12062 | 0U, // SUMOP4S_MZ2Z_BToS_PSEUDO |
| 12063 | 0U, // SUMOP4S_MZ2Z_HtoD_PSEUDO |
| 12064 | 0U, // SUMOP4S_MZZ_BToS_PSEUDO |
| 12065 | 0U, // SUMOP4S_MZZ_HtoD_PSEUDO |
| 12066 | 0U, // SUMOPA_MPPZZ_D_PSEUDO |
| 12067 | 0U, // SUMOPA_MPPZZ_S_PSEUDO |
| 12068 | 0U, // SUMOPS_MPPZZ_D_PSEUDO |
| 12069 | 0U, // SUMOPS_MPPZZ_S_PSEUDO |
| 12070 | 0U, // SUTMOPA_M2ZZZI_BtoS_PSEUDO |
| 12071 | 0U, // SUVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 12072 | 0U, // SVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 12073 | 0U, // SVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 12074 | 0U, // SVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 12075 | 0U, // SXTB_ZPmZ_D_UNDEF |
| 12076 | 0U, // SXTB_ZPmZ_H_UNDEF |
| 12077 | 0U, // SXTB_ZPmZ_S_UNDEF |
| 12078 | 0U, // SXTH_ZPmZ_D_UNDEF |
| 12079 | 0U, // SXTH_ZPmZ_S_UNDEF |
| 12080 | 0U, // SXTW_ZPmZ_D_UNDEF |
| 12081 | 0U, // SpeculationBarrierISBDSBEndBB |
| 12082 | 0U, // SpeculationBarrierSBEndBB |
| 12083 | 0U, // SpeculationSafeValueW |
| 12084 | 0U, // SpeculationSafeValueX |
| 12085 | 0U, // StoreSwiftAsyncContext |
| 12086 | 0U, // TAGPstack |
| 12087 | 0U, // TCRETURNdi |
| 12088 | 0U, // TCRETURNri |
| 12089 | 0U, // TCRETURNriALL |
| 12090 | 0U, // TCRETURNrinotx16 |
| 12091 | 0U, // TCRETURNrix16x17 |
| 12092 | 0U, // TCRETURNrix17 |
| 12093 | 0U, // TLSDESCCALL |
| 12094 | 0U, // TLSDESC_AUTH_CALLSEQ |
| 12095 | 0U, // TLSDESC_CALLSEQ |
| 12096 | 0U, // UABD_ZPZZ_B_UNDEF |
| 12097 | 0U, // UABD_ZPZZ_D_UNDEF |
| 12098 | 0U, // UABD_ZPZZ_H_UNDEF |
| 12099 | 0U, // UABD_ZPZZ_S_UNDEF |
| 12100 | 0U, // UCVTF_ZPmZ_DtoD_UNDEF |
| 12101 | 0U, // UCVTF_ZPmZ_DtoH_UNDEF |
| 12102 | 0U, // UCVTF_ZPmZ_DtoS_UNDEF |
| 12103 | 0U, // UCVTF_ZPmZ_HtoH_UNDEF |
| 12104 | 0U, // UCVTF_ZPmZ_StoD_UNDEF |
| 12105 | 0U, // UCVTF_ZPmZ_StoH_UNDEF |
| 12106 | 0U, // UCVTF_ZPmZ_StoS_UNDEF |
| 12107 | 0U, // UDIV_ZPZZ_D_UNDEF |
| 12108 | 0U, // UDIV_ZPZZ_S_UNDEF |
| 12109 | 0U, // UDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 12110 | 0U, // UDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 12111 | 0U, // UDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 12112 | 0U, // UDOT_VG2_M2ZZI_BToS_PSEUDO |
| 12113 | 0U, // UDOT_VG2_M2ZZI_HToS_PSEUDO |
| 12114 | 0U, // UDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 12115 | 0U, // UDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 12116 | 0U, // UDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 12117 | 0U, // UDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 12118 | 0U, // UDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 12119 | 0U, // UDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 12120 | 0U, // UDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 12121 | 0U, // UDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 12122 | 0U, // UDOT_VG4_M4ZZI_HToS_PSEUDO |
| 12123 | 0U, // UDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 12124 | 0U, // UDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 12125 | 0U, // UDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 12126 | 0U, // UDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 12127 | 0U, // UHSUB_ZPZZ_B_UNDEF |
| 12128 | 0U, // UHSUB_ZPZZ_D_UNDEF |
| 12129 | 0U, // UHSUB_ZPZZ_H_UNDEF |
| 12130 | 0U, // UHSUB_ZPZZ_S_UNDEF |
| 12131 | 0U, // UMAX_ZPZZ_B_UNDEF |
| 12132 | 0U, // UMAX_ZPZZ_D_UNDEF |
| 12133 | 0U, // UMAX_ZPZZ_H_UNDEF |
| 12134 | 0U, // UMAX_ZPZZ_S_UNDEF |
| 12135 | 0U, // UMIN_ZPZZ_B_UNDEF |
| 12136 | 0U, // UMIN_ZPZZ_D_UNDEF |
| 12137 | 0U, // UMIN_ZPZZ_H_UNDEF |
| 12138 | 0U, // UMIN_ZPZZ_S_UNDEF |
| 12139 | 0U, // UMLALL_MZZI_BtoS_PSEUDO |
| 12140 | 0U, // UMLALL_MZZI_HtoD_PSEUDO |
| 12141 | 0U, // UMLALL_MZZ_BtoS_PSEUDO |
| 12142 | 0U, // UMLALL_MZZ_HtoD_PSEUDO |
| 12143 | 0U, // UMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 12144 | 0U, // UMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 12145 | 0U, // UMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 12146 | 0U, // UMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 12147 | 0U, // UMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 12148 | 0U, // UMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 12149 | 0U, // UMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 12150 | 0U, // UMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 12151 | 0U, // UMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 12152 | 0U, // UMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 12153 | 0U, // UMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 12154 | 0U, // UMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 12155 | 0U, // UMLAL_MZZI_HtoS_PSEUDO |
| 12156 | 0U, // UMLAL_MZZ_HtoS_PSEUDO |
| 12157 | 0U, // UMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 12158 | 0U, // UMLAL_VG2_M2ZZI_S_PSEUDO |
| 12159 | 0U, // UMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 12160 | 0U, // UMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 12161 | 0U, // UMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 12162 | 0U, // UMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 12163 | 0U, // UMLSLL_MZZI_BtoS_PSEUDO |
| 12164 | 0U, // UMLSLL_MZZI_HtoD_PSEUDO |
| 12165 | 0U, // UMLSLL_MZZ_BtoS_PSEUDO |
| 12166 | 0U, // UMLSLL_MZZ_HtoD_PSEUDO |
| 12167 | 0U, // UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 12168 | 0U, // UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 12169 | 0U, // UMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 12170 | 0U, // UMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 12171 | 0U, // UMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 12172 | 0U, // UMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 12173 | 0U, // UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 12174 | 0U, // UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 12175 | 0U, // UMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 12176 | 0U, // UMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 12177 | 0U, // UMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 12178 | 0U, // UMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 12179 | 0U, // UMLSL_MZZI_HtoS_PSEUDO |
| 12180 | 0U, // UMLSL_MZZ_HtoS_PSEUDO |
| 12181 | 0U, // UMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 12182 | 0U, // UMLSL_VG2_M2ZZI_S_PSEUDO |
| 12183 | 0U, // UMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 12184 | 0U, // UMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 12185 | 0U, // UMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 12186 | 0U, // UMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 12187 | 0U, // UMOP4A_M2Z2Z_BToS_PSEUDO |
| 12188 | 0U, // UMOP4A_M2Z2Z_HToS_PSEUDO |
| 12189 | 0U, // UMOP4A_M2Z2Z_HtoD_PSEUDO |
| 12190 | 0U, // UMOP4A_M2ZZ_BToS_PSEUDO |
| 12191 | 0U, // UMOP4A_M2ZZ_HToS_PSEUDO |
| 12192 | 0U, // UMOP4A_M2ZZ_HtoD_PSEUDO |
| 12193 | 0U, // UMOP4A_MZ2Z_BToS_PSEUDO |
| 12194 | 0U, // UMOP4A_MZ2Z_HToS_PSEUDO |
| 12195 | 0U, // UMOP4A_MZ2Z_HtoD_PSEUDO |
| 12196 | 0U, // UMOP4A_MZZ_BToS_PSEUDO |
| 12197 | 0U, // UMOP4A_MZZ_HToS_PSEUDO |
| 12198 | 0U, // UMOP4A_MZZ_HtoD_PSEUDO |
| 12199 | 0U, // UMOP4S_M2Z2Z_BToS_PSEUDO |
| 12200 | 0U, // UMOP4S_M2Z2Z_HToS_PSEUDO |
| 12201 | 0U, // UMOP4S_M2Z2Z_HtoD_PSEUDO |
| 12202 | 0U, // UMOP4S_M2ZZ_BToS_PSEUDO |
| 12203 | 0U, // UMOP4S_M2ZZ_HToS_PSEUDO |
| 12204 | 0U, // UMOP4S_M2ZZ_HtoD_PSEUDO |
| 12205 | 0U, // UMOP4S_MZ2Z_BToS_PSEUDO |
| 12206 | 0U, // UMOP4S_MZ2Z_HToS_PSEUDO |
| 12207 | 0U, // UMOP4S_MZ2Z_HtoD_PSEUDO |
| 12208 | 0U, // UMOP4S_MZZ_BToS_PSEUDO |
| 12209 | 0U, // UMOP4S_MZZ_HToS_PSEUDO |
| 12210 | 0U, // UMOP4S_MZZ_HtoD_PSEUDO |
| 12211 | 0U, // UMOPA_MPPZZ_D_PSEUDO |
| 12212 | 0U, // UMOPA_MPPZZ_HtoS_PSEUDO |
| 12213 | 0U, // UMOPA_MPPZZ_S_PSEUDO |
| 12214 | 0U, // UMOPS_MPPZZ_D_PSEUDO |
| 12215 | 0U, // UMOPS_MPPZZ_HtoS_PSEUDO |
| 12216 | 0U, // UMOPS_MPPZZ_S_PSEUDO |
| 12217 | 0U, // UMULH_ZPZZ_B_UNDEF |
| 12218 | 0U, // UMULH_ZPZZ_D_UNDEF |
| 12219 | 0U, // UMULH_ZPZZ_H_UNDEF |
| 12220 | 0U, // UMULH_ZPZZ_S_UNDEF |
| 12221 | 0U, // UQADD_ZI_B_PSEUDO |
| 12222 | 0U, // UQADD_ZI_D_PSEUDO |
| 12223 | 0U, // UQADD_ZI_H_PSEUDO |
| 12224 | 0U, // UQADD_ZI_S_PSEUDO |
| 12225 | 0U, // UQRSHL_ZPZZ_B_UNDEF |
| 12226 | 0U, // UQRSHL_ZPZZ_D_UNDEF |
| 12227 | 0U, // UQRSHL_ZPZZ_H_UNDEF |
| 12228 | 0U, // UQRSHL_ZPZZ_S_UNDEF |
| 12229 | 0U, // UQSHL_ZPZI_B_UNDEF |
| 12230 | 0U, // UQSHL_ZPZI_B_ZERO |
| 12231 | 0U, // UQSHL_ZPZI_D_UNDEF |
| 12232 | 0U, // UQSHL_ZPZI_D_ZERO |
| 12233 | 0U, // UQSHL_ZPZI_H_UNDEF |
| 12234 | 0U, // UQSHL_ZPZI_H_ZERO |
| 12235 | 0U, // UQSHL_ZPZI_S_UNDEF |
| 12236 | 0U, // UQSHL_ZPZI_S_ZERO |
| 12237 | 0U, // UQSHL_ZPZZ_B_UNDEF |
| 12238 | 0U, // UQSHL_ZPZZ_D_UNDEF |
| 12239 | 0U, // UQSHL_ZPZZ_H_UNDEF |
| 12240 | 0U, // UQSHL_ZPZZ_S_UNDEF |
| 12241 | 0U, // UQSUB_ZI_B_PSEUDO |
| 12242 | 0U, // UQSUB_ZI_D_PSEUDO |
| 12243 | 0U, // UQSUB_ZI_H_PSEUDO |
| 12244 | 0U, // UQSUB_ZI_S_PSEUDO |
| 12245 | 0U, // URECPE_ZPmZ_S_UNDEF |
| 12246 | 0U, // URSHL_ZPZZ_B_UNDEF |
| 12247 | 0U, // URSHL_ZPZZ_D_UNDEF |
| 12248 | 0U, // URSHL_ZPZZ_H_UNDEF |
| 12249 | 0U, // URSHL_ZPZZ_S_UNDEF |
| 12250 | 0U, // URSHR_ZPZI_B_ZERO |
| 12251 | 0U, // URSHR_ZPZI_D_ZERO |
| 12252 | 0U, // URSHR_ZPZI_H_ZERO |
| 12253 | 0U, // URSHR_ZPZI_S_ZERO |
| 12254 | 0U, // URSQRTE_ZPmZ_S_UNDEF |
| 12255 | 0U, // USDOT_VG2_M2Z2Z_BToS_PSEUDO |
| 12256 | 0U, // USDOT_VG2_M2ZZI_BToS_PSEUDO |
| 12257 | 0U, // USDOT_VG2_M2ZZ_BToS_PSEUDO |
| 12258 | 0U, // USDOT_VG4_M4Z4Z_BToS_PSEUDO |
| 12259 | 0U, // USDOT_VG4_M4ZZI_BToS_PSEUDO |
| 12260 | 0U, // USDOT_VG4_M4ZZ_BToS_PSEUDO |
| 12261 | 0U, // USMLALL_MZZI_BtoS_PSEUDO |
| 12262 | 0U, // USMLALL_MZZ_BtoS_PSEUDO |
| 12263 | 0U, // USMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 12264 | 0U, // USMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 12265 | 0U, // USMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 12266 | 0U, // USMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 12267 | 0U, // USMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 12268 | 0U, // USMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 12269 | 0U, // USMOP4A_M2Z2Z_BToS_PSEUDO |
| 12270 | 0U, // USMOP4A_M2Z2Z_HtoD_PSEUDO |
| 12271 | 0U, // USMOP4A_M2ZZ_BToS_PSEUDO |
| 12272 | 0U, // USMOP4A_M2ZZ_HtoD_PSEUDO |
| 12273 | 0U, // USMOP4A_MZ2Z_BToS_PSEUDO |
| 12274 | 0U, // USMOP4A_MZ2Z_HtoD_PSEUDO |
| 12275 | 0U, // USMOP4A_MZZ_BToS_PSEUDO |
| 12276 | 0U, // USMOP4A_MZZ_HtoD_PSEUDO |
| 12277 | 0U, // USMOP4S_M2Z2Z_BToS_PSEUDO |
| 12278 | 0U, // USMOP4S_M2Z2Z_HtoD_PSEUDO |
| 12279 | 0U, // USMOP4S_M2ZZ_BToS_PSEUDO |
| 12280 | 0U, // USMOP4S_M2ZZ_HtoD_PSEUDO |
| 12281 | 0U, // USMOP4S_MZ2Z_BToS_PSEUDO |
| 12282 | 0U, // USMOP4S_MZ2Z_HtoD_PSEUDO |
| 12283 | 0U, // USMOP4S_MZZ_BToS_PSEUDO |
| 12284 | 0U, // USMOP4S_MZZ_HtoD_PSEUDO |
| 12285 | 0U, // USMOPA_MPPZZ_D_PSEUDO |
| 12286 | 0U, // USMOPA_MPPZZ_S_PSEUDO |
| 12287 | 0U, // USMOPS_MPPZZ_D_PSEUDO |
| 12288 | 0U, // USMOPS_MPPZZ_S_PSEUDO |
| 12289 | 0U, // USTMOPA_M2ZZZI_BtoS_PSEUDO |
| 12290 | 0U, // USVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 12291 | 0U, // UTMOPA_M2ZZZI_BtoS_PSEUDO |
| 12292 | 0U, // UTMOPA_M2ZZZI_HtoS_PSEUDO |
| 12293 | 0U, // UVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 12294 | 0U, // UVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 12295 | 0U, // UVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 12296 | 0U, // UXTB_ZPmZ_D_UNDEF |
| 12297 | 0U, // UXTB_ZPmZ_H_UNDEF |
| 12298 | 0U, // UXTB_ZPmZ_S_UNDEF |
| 12299 | 0U, // UXTH_ZPmZ_D_UNDEF |
| 12300 | 0U, // UXTH_ZPmZ_S_UNDEF |
| 12301 | 0U, // UXTW_ZPmZ_D_UNDEF |
| 12302 | 0U, // ZERO_MXI_2Z_PSEUDO |
| 12303 | 0U, // ZERO_MXI_4Z_PSEUDO |
| 12304 | 0U, // ZERO_MXI_VG2_2Z_PSEUDO |
| 12305 | 0U, // ZERO_MXI_VG2_4Z_PSEUDO |
| 12306 | 0U, // ZERO_MXI_VG2_Z_PSEUDO |
| 12307 | 0U, // ZERO_MXI_VG4_2Z_PSEUDO |
| 12308 | 0U, // ZERO_MXI_VG4_4Z_PSEUDO |
| 12309 | 0U, // ZERO_MXI_VG4_Z_PSEUDO |
| 12310 | 0U, // ZERO_M_PSEUDO |
| 12311 | 0U, // ZERO_T_PSEUDO |
| 12312 | 0U, // ABSWr |
| 12313 | 0U, // ABSXr |
| 12314 | 8U, // ABS_ZPmZ_B |
| 12315 | 2056U, // ABS_ZPmZ_D |
| 12316 | 4112U, // ABS_ZPmZ_H |
| 12317 | 6152U, // ABS_ZPmZ_S |
| 12318 | 8216U, // ABS_ZPzZ_B |
| 12319 | 10264U, // ABS_ZPzZ_D |
| 12320 | 4128U, // ABS_ZPzZ_H |
| 12321 | 12312U, // ABS_ZPzZ_S |
| 12322 | 40U, // ABSv16i8 |
| 12323 | 0U, // ABSv1i64 |
| 12324 | 48U, // ABSv2i32 |
| 12325 | 56U, // ABSv2i64 |
| 12326 | 64U, // ABSv4i16 |
| 12327 | 72U, // ABSv4i32 |
| 12328 | 80U, // ABSv8i16 |
| 12329 | 88U, // ABSv8i8 |
| 12330 | 2144U, // ADCLB_ZZZ_D |
| 12331 | 6240U, // ADCLB_ZZZ_S |
| 12332 | 2144U, // ADCLT_ZZZ_D |
| 12333 | 6240U, // ADCLT_ZZZ_S |
| 12334 | 14432U, // ADCSWr |
| 12335 | 14432U, // ADCSXr |
| 12336 | 14432U, // ADCWr |
| 12337 | 14432U, // ADCXr |
| 12338 | 278624U, // ADDG |
| 12339 | 18536U, // ADDHA_MPPZ_D |
| 12340 | 20584U, // ADDHA_MPPZ_S |
| 12341 | 22624U, // ADDHNB_ZZZ_B |
| 12342 | 4208U, // ADDHNB_ZZZ_H |
| 12343 | 10336U, // ADDHNB_ZZZ_S |
| 12344 | 24672U, // ADDHNT_ZZZ_B |
| 12345 | 120U, // ADDHNT_ZZZ_H |
| 12346 | 2144U, // ADDHNT_ZZZ_S |
| 12347 | 551040U, // ADDHNv2i64_v2i32 |
| 12348 | 553088U, // ADDHNv2i64_v4i32 |
| 12349 | 813192U, // ADDHNv4i32_v4i16 |
| 12350 | 815240U, // ADDHNv4i32_v8i16 |
| 12351 | 1077392U, // ADDHNv8i16_v16i8 |
| 12352 | 1075344U, // ADDHNv8i16_v8i8 |
| 12353 | 14432U, // ADDPL_XXI |
| 12354 | 1325152U, // ADDPT_shift |
| 12355 | 33824776U, // ADDP_ZPmZ_B |
| 12356 | 67381256U, // ADDP_ZPmZ_D |
| 12357 | 102266912U, // ADDP_ZPmZ_H |
| 12358 | 134492168U, // ADDP_ZPmZ_S |
| 12359 | 1861784U, // ADDPv16i8 |
| 12360 | 2123936U, // ADDPv2i32 |
| 12361 | 551040U, // ADDPv2i64 |
| 12362 | 56U, // ADDPv2i64p |
| 12363 | 2386088U, // ADDPv4i16 |
| 12364 | 813192U, // ADDPv4i32 |
| 12365 | 1075344U, // ADDPv8i16 |
| 12366 | 2648240U, // ADDPv8i8 |
| 12367 | 8288U, // ADDQP_ZZZ_B |
| 12368 | 10336U, // ADDQP_ZZZ_D |
| 12369 | 4128U, // ADDQP_ZZZ_H |
| 12370 | 12384U, // ADDQP_ZZZ_S |
| 12371 | 8288U, // ADDQV_VPZ_B |
| 12372 | 10336U, // ADDQV_VPZ_D |
| 12373 | 22624U, // ADDQV_VPZ_H |
| 12374 | 12384U, // ADDQV_VPZ_S |
| 12375 | 14432U, // ADDSPL_XXI |
| 12376 | 8288U, // ADDSUBP_ZZZ_B |
| 12377 | 10336U, // ADDSUBP_ZZZ_D |
| 12378 | 4128U, // ADDSUBP_ZZZ_H |
| 12379 | 12384U, // ADDSUBP_ZZZ_S |
| 12380 | 14432U, // ADDSVL_XXI |
| 12381 | 32864U, // ADDSWri |
| 12382 | 34912U, // ADDSWrs |
| 12383 | 36960U, // ADDSWrx |
| 12384 | 32864U, // ADDSXri |
| 12385 | 34912U, // ADDSXrs |
| 12386 | 36960U, // ADDSXrx |
| 12387 | 2898016U, // ADDSXrx64 |
| 12388 | 18536U, // ADDVA_MPPZ_D |
| 12389 | 20584U, // ADDVA_MPPZ_S |
| 12390 | 14432U, // ADDVL_XXI |
| 12391 | 40U, // ADDVv16i8v |
| 12392 | 64U, // ADDVv4i16v |
| 12393 | 72U, // ADDVv4i32v |
| 12394 | 80U, // ADDVv8i16v |
| 12395 | 88U, // ADDVv8i8v |
| 12396 | 32864U, // ADDWri |
| 12397 | 34912U, // ADDWrs |
| 12398 | 36960U, // ADDWrx |
| 12399 | 32864U, // ADDXri |
| 12400 | 34912U, // ADDXrs |
| 12401 | 36960U, // ADDXrx |
| 12402 | 2898016U, // ADDXrx64 |
| 12403 | 184U, // ADD_VG2_2ZZ_B |
| 12404 | 4288U, // ADD_VG2_2ZZ_D |
| 12405 | 4128U, // ADD_VG2_2ZZ_H |
| 12406 | 4208U, // ADD_VG2_2ZZ_S |
| 12407 | 3176648U, // ADD_VG2_M2Z2Z_D |
| 12408 | 3438800U, // ADD_VG2_M2Z2Z_S |
| 12409 | 104364232U, // ADD_VG2_M2ZZ_D |
| 12410 | 104626384U, // ADD_VG2_M2ZZ_S |
| 12411 | 4296U, // ADD_VG2_M2Z_D |
| 12412 | 4304U, // ADD_VG2_M2Z_S |
| 12413 | 184U, // ADD_VG4_4ZZ_B |
| 12414 | 4288U, // ADD_VG4_4ZZ_D |
| 12415 | 4128U, // ADD_VG4_4ZZ_H |
| 12416 | 4208U, // ADD_VG4_4ZZ_S |
| 12417 | 3176649U, // ADD_VG4_M4Z4Z_D |
| 12418 | 3438801U, // ADD_VG4_M4Z4Z_S |
| 12419 | 104364233U, // ADD_VG4_M4ZZ_D |
| 12420 | 104626385U, // ADD_VG4_M4ZZ_S |
| 12421 | 4297U, // ADD_VG4_M4Z_D |
| 12422 | 4305U, // ADD_VG4_M4Z_S |
| 12423 | 39008U, // ADD_ZI_B |
| 12424 | 41056U, // ADD_ZI_D |
| 12425 | 216U, // ADD_ZI_H |
| 12426 | 43104U, // ADD_ZI_S |
| 12427 | 33824776U, // ADD_ZPmZ_B |
| 12428 | 67381256U, // ADD_ZPmZ_CPA |
| 12429 | 67381256U, // ADD_ZPmZ_D |
| 12430 | 102266912U, // ADD_ZPmZ_H |
| 12431 | 134492168U, // ADD_ZPmZ_S |
| 12432 | 8288U, // ADD_ZZZ_B |
| 12433 | 10336U, // ADD_ZZZ_CPA |
| 12434 | 10336U, // ADD_ZZZ_D |
| 12435 | 4128U, // ADD_ZZZ_H |
| 12436 | 12384U, // ADD_ZZZ_S |
| 12437 | 1861784U, // ADDv16i8 |
| 12438 | 14432U, // ADDv1i64 |
| 12439 | 2123936U, // ADDv2i32 |
| 12440 | 551040U, // ADDv2i64 |
| 12441 | 2386088U, // ADDv4i16 |
| 12442 | 813192U, // ADDv4i32 |
| 12443 | 1075344U, // ADDv8i16 |
| 12444 | 2648240U, // ADDv8i8 |
| 12445 | 1U, // ADR |
| 12446 | 1U, // ADRP |
| 12447 | 45152U, // ADR_LSL_ZZZ_D_0 |
| 12448 | 47200U, // ADR_LSL_ZZZ_D_1 |
| 12449 | 49248U, // ADR_LSL_ZZZ_D_2 |
| 12450 | 51296U, // ADR_LSL_ZZZ_D_3 |
| 12451 | 53344U, // ADR_LSL_ZZZ_S_0 |
| 12452 | 55392U, // ADR_LSL_ZZZ_S_1 |
| 12453 | 57440U, // ADR_LSL_ZZZ_S_2 |
| 12454 | 59488U, // ADR_LSL_ZZZ_S_3 |
| 12455 | 61536U, // ADR_SXTW_ZZZ_D_0 |
| 12456 | 63584U, // ADR_SXTW_ZZZ_D_1 |
| 12457 | 65632U, // ADR_SXTW_ZZZ_D_2 |
| 12458 | 67680U, // ADR_SXTW_ZZZ_D_3 |
| 12459 | 69728U, // ADR_UXTW_ZZZ_D_0 |
| 12460 | 71776U, // ADR_UXTW_ZZZ_D_1 |
| 12461 | 73824U, // ADR_UXTW_ZZZ_D_2 |
| 12462 | 75872U, // ADR_UXTW_ZZZ_D_3 |
| 12463 | 78048U, // AESDIMC_2ZZI_B |
| 12464 | 78048U, // AESDIMC_4ZZI_B |
| 12465 | 78048U, // AESD_2ZZI_B |
| 12466 | 78048U, // AESD_4ZZI_B |
| 12467 | 8288U, // AESD_ZZZ_B |
| 12468 | 40U, // AESDrr |
| 12469 | 78048U, // AESEMC_2ZZI_B |
| 12470 | 78048U, // AESEMC_4ZZI_B |
| 12471 | 78048U, // AESE_2ZZI_B |
| 12472 | 78048U, // AESE_4ZZI_B |
| 12473 | 8288U, // AESE_ZZZ_B |
| 12474 | 40U, // AESErr |
| 12475 | 0U, // AESIMC_ZZ_B |
| 12476 | 40U, // AESIMCrr |
| 12477 | 0U, // AESMC_ZZ_B |
| 12478 | 40U, // AESMCrr |
| 12479 | 8288U, // ANDQV_VPZ_B |
| 12480 | 10336U, // ANDQV_VPZ_D |
| 12481 | 22624U, // ANDQV_VPZ_H |
| 12482 | 12384U, // ANDQV_VPZ_S |
| 12483 | 79968U, // ANDSWri |
| 12484 | 34912U, // ANDSWrs |
| 12485 | 82016U, // ANDSXri |
| 12486 | 34912U, // ANDSXrs |
| 12487 | 33824792U, // ANDS_PPzPP |
| 12488 | 0U, // ANDV_VPZ_B |
| 12489 | 1U, // ANDV_VPZ_D |
| 12490 | 1U, // ANDV_VPZ_H |
| 12491 | 1U, // ANDV_VPZ_S |
| 12492 | 79968U, // ANDWri |
| 12493 | 34912U, // ANDWrs |
| 12494 | 82016U, // ANDXri |
| 12495 | 34912U, // ANDXrs |
| 12496 | 33824792U, // AND_PPzPP |
| 12497 | 82016U, // AND_ZI |
| 12498 | 33824776U, // AND_ZPmZ_B |
| 12499 | 67381256U, // AND_ZPmZ_D |
| 12500 | 102266912U, // AND_ZPmZ_H |
| 12501 | 134492168U, // AND_ZPmZ_S |
| 12502 | 10336U, // AND_ZZZ |
| 12503 | 1861784U, // ANDv16i8 |
| 12504 | 2648240U, // ANDv8i8 |
| 12505 | 0U, // APAS |
| 12506 | 270344U, // ASRD_ZPmI_B |
| 12507 | 272392U, // ASRD_ZPmI_D |
| 12508 | 104888352U, // ASRD_ZPmI_H |
| 12509 | 274440U, // ASRD_ZPmI_S |
| 12510 | 33824776U, // ASRR_ZPmZ_B |
| 12511 | 67381256U, // ASRR_ZPmZ_D |
| 12512 | 102266912U, // ASRR_ZPmZ_H |
| 12513 | 134492168U, // ASRR_ZPmZ_S |
| 12514 | 14432U, // ASRVWr |
| 12515 | 14432U, // ASRVXr |
| 12516 | 67379208U, // ASR_WIDE_ZPmZ_B |
| 12517 | 4487200U, // ASR_WIDE_ZPmZ_H |
| 12518 | 67383304U, // ASR_WIDE_ZPmZ_S |
| 12519 | 10336U, // ASR_WIDE_ZZZ_B |
| 12520 | 4288U, // ASR_WIDE_ZZZ_H |
| 12521 | 10336U, // ASR_WIDE_ZZZ_S |
| 12522 | 270344U, // ASR_ZPmI_B |
| 12523 | 272392U, // ASR_ZPmI_D |
| 12524 | 104888352U, // ASR_ZPmI_H |
| 12525 | 274440U, // ASR_ZPmI_S |
| 12526 | 33824776U, // ASR_ZPmZ_B |
| 12527 | 67381256U, // ASR_ZPmZ_D |
| 12528 | 102266912U, // ASR_ZPmZ_H |
| 12529 | 134492168U, // ASR_ZPmZ_S |
| 12530 | 14432U, // ASR_ZZI_B |
| 12531 | 14432U, // ASR_ZZI_D |
| 12532 | 4328U, // ASR_ZZI_H |
| 12533 | 14432U, // ASR_ZZI_S |
| 12534 | 1U, // AUTDA |
| 12535 | 1U, // AUTDB |
| 12536 | 0U, // AUTDZA |
| 12537 | 0U, // AUTDZB |
| 12538 | 1U, // AUTIA |
| 12539 | 0U, // AUTIA1716 |
| 12540 | 0U, // AUTIA171615 |
| 12541 | 0U, // AUTIASP |
| 12542 | 0U, // AUTIASPPCi |
| 12543 | 0U, // AUTIASPPCr |
| 12544 | 0U, // AUTIAZ |
| 12545 | 1U, // AUTIB |
| 12546 | 0U, // AUTIB1716 |
| 12547 | 0U, // AUTIB171615 |
| 12548 | 0U, // AUTIBSP |
| 12549 | 0U, // AUTIBSPPCi |
| 12550 | 0U, // AUTIBSPPCr |
| 12551 | 0U, // AUTIBZ |
| 12552 | 0U, // AUTIZA |
| 12553 | 0U, // AUTIZB |
| 12554 | 0U, // AXFLAG |
| 12555 | 0U, // B |
| 12556 | 172517528U, // BCAX |
| 12557 | 67381344U, // BCAX_ZZZZ |
| 12558 | 0U, // BCcc |
| 12559 | 8288U, // BDEP_ZZZ_B |
| 12560 | 10336U, // BDEP_ZZZ_D |
| 12561 | 4128U, // BDEP_ZZZ_H |
| 12562 | 12384U, // BDEP_ZZZ_S |
| 12563 | 8288U, // BEXT_ZZZ_B |
| 12564 | 10336U, // BEXT_ZZZ_D |
| 12565 | 4128U, // BEXT_ZZZ_H |
| 12566 | 12384U, // BEXT_ZZZ_S |
| 12567 | 5009576U, // BF16DOTlanev4bf16 |
| 12568 | 5009552U, // BF16DOTlanev8bf16 |
| 12569 | 88U, // BF1CVTL |
| 12570 | 40U, // BF1CVTL2 |
| 12571 | 1U, // BF1CVTLT_ZZ_BtoH |
| 12572 | 1U, // BF1CVTL_2ZZ_BtoH |
| 12573 | 1U, // BF1CVT_2ZZ_BtoH |
| 12574 | 1U, // BF1CVT_ZZ_BtoH |
| 12575 | 88U, // BF2CVTL |
| 12576 | 40U, // BF2CVTL2 |
| 12577 | 1U, // BF2CVTLT_ZZ_BtoH |
| 12578 | 1U, // BF2CVTL_2ZZ_BtoH |
| 12579 | 1U, // BF2CVT_2ZZ_BtoH |
| 12580 | 1U, // BF2CVT_ZZ_BtoH |
| 12581 | 4336U, // BFADD_VG2_M2Z_H |
| 12582 | 4337U, // BFADD_VG4_M4Z_H |
| 12583 | 102266912U, // BFADD_ZPmZZ |
| 12584 | 4128U, // BFADD_ZZZ |
| 12585 | 4112U, // BFCLAMP_VG2_2ZZZ_H |
| 12586 | 4112U, // BFCLAMP_VG4_4ZZZ_H |
| 12587 | 4112U, // BFCLAMP_ZZZ |
| 12588 | 0U, // BFCVT |
| 12589 | 72U, // BFCVTN |
| 12590 | 72U, // BFCVTN2 |
| 12591 | 120U, // BFCVTNT_ZPmZ |
| 12592 | 120U, // BFCVTNT_ZPzZ_StoH |
| 12593 | 1U, // BFCVTN_Z2Z_HtoB |
| 12594 | 1U, // BFCVTN_Z2Z_StoH |
| 12595 | 1U, // BFCVT_Z2Z_HtoB |
| 12596 | 1U, // BFCVT_Z2Z_StoH |
| 12597 | 120U, // BFCVT_ZPmZ |
| 12598 | 4208U, // BFCVT_ZPzZ_StoH |
| 12599 | 5273840U, // BFDOT_VG2_M2Z2Z_HtoS |
| 12600 | 206862576U, // BFDOT_VG2_M2ZZI_HtoS |
| 12601 | 106199280U, // BFDOT_VG2_M2ZZ_HtoS |
| 12602 | 5273841U, // BFDOT_VG4_M4Z4Z_HtoS |
| 12603 | 206862577U, // BFDOT_VG4_M4ZZI_HtoS |
| 12604 | 106199281U, // BFDOT_VG4_M4ZZ_HtoS |
| 12605 | 106455136U, // BFDOT_ZZI |
| 12606 | 24672U, // BFDOT_ZZZ |
| 12607 | 2388136U, // BFDOTv4bf16 |
| 12608 | 1077392U, // BFDOTv8bf16 |
| 12609 | 4344U, // BFMAXNM_VG2_2Z2Z_H |
| 12610 | 4128U, // BFMAXNM_VG2_2ZZ_H |
| 12611 | 4344U, // BFMAXNM_VG4_4Z2Z_H |
| 12612 | 4128U, // BFMAXNM_VG4_4ZZ_H |
| 12613 | 102266912U, // BFMAXNM_ZPmZZ |
| 12614 | 4344U, // BFMAX_VG2_2Z2Z_H |
| 12615 | 4128U, // BFMAX_VG2_2ZZ_H |
| 12616 | 4344U, // BFMAX_VG4_4Z2Z_H |
| 12617 | 4128U, // BFMAX_VG4_4ZZ_H |
| 12618 | 102266912U, // BFMAX_ZPmZZ |
| 12619 | 4344U, // BFMINNM_VG2_2Z2Z_H |
| 12620 | 4128U, // BFMINNM_VG2_2ZZ_H |
| 12621 | 4344U, // BFMINNM_VG4_4Z2Z_H |
| 12622 | 4128U, // BFMINNM_VG4_4ZZ_H |
| 12623 | 102266912U, // BFMINNM_ZPmZZ |
| 12624 | 4344U, // BFMIN_VG2_2Z2Z_H |
| 12625 | 4128U, // BFMIN_VG2_2ZZ_H |
| 12626 | 4344U, // BFMIN_VG4_4Z2Z_H |
| 12627 | 4128U, // BFMIN_VG4_4ZZ_H |
| 12628 | 102266912U, // BFMIN_ZPmZZ |
| 12629 | 1077392U, // BFMLALB |
| 12630 | 240939152U, // BFMLALBIdx |
| 12631 | 24672U, // BFMLALB_ZZZ |
| 12632 | 106455136U, // BFMLALB_ZZZI |
| 12633 | 1077392U, // BFMLALT |
| 12634 | 240939152U, // BFMLALTIdx |
| 12635 | 24672U, // BFMLALT_ZZZ |
| 12636 | 106455136U, // BFMLALT_ZZZI |
| 12637 | 84225U, // BFMLAL_MZZI_HtoS |
| 12638 | 4353U, // BFMLAL_MZZ_HtoS |
| 12639 | 5273840U, // BFMLAL_VG2_M2Z2Z_HtoS |
| 12640 | 206862576U, // BFMLAL_VG2_M2ZZI_HtoS |
| 12641 | 106199280U, // BFMLAL_VG2_M2ZZ_HtoS |
| 12642 | 5273841U, // BFMLAL_VG4_M4Z4Z_HtoS |
| 12643 | 206862577U, // BFMLAL_VG4_M4ZZI_HtoS |
| 12644 | 106199281U, // BFMLAL_VG4_M4ZZ_HtoS |
| 12645 | 5273840U, // BFMLA_VG2_M2Z2Z |
| 12646 | 106199280U, // BFMLA_VG2_M2ZZ |
| 12647 | 206862576U, // BFMLA_VG2_M2ZZI |
| 12648 | 5273841U, // BFMLA_VG4_M4Z4Z |
| 12649 | 106199281U, // BFMLA_VG4_M4ZZ |
| 12650 | 206862577U, // BFMLA_VG4_M4ZZI |
| 12651 | 106985488U, // BFMLA_ZPmZZ |
| 12652 | 86032U, // BFMLA_ZZZI |
| 12653 | 106455136U, // BFMLSLB_ZZZI_S |
| 12654 | 24672U, // BFMLSLB_ZZZ_S |
| 12655 | 106455136U, // BFMLSLT_ZZZI_S |
| 12656 | 24672U, // BFMLSLT_ZZZ_S |
| 12657 | 84225U, // BFMLSL_MZZI_HtoS |
| 12658 | 4353U, // BFMLSL_MZZ_HtoS |
| 12659 | 5273840U, // BFMLSL_VG2_M2Z2Z_HtoS |
| 12660 | 206862576U, // BFMLSL_VG2_M2ZZI_HtoS |
| 12661 | 106199280U, // BFMLSL_VG2_M2ZZ_HtoS |
| 12662 | 5273841U, // BFMLSL_VG4_M4Z4Z_HtoS |
| 12663 | 206862577U, // BFMLSL_VG4_M4ZZI_HtoS |
| 12664 | 106199281U, // BFMLSL_VG4_M4ZZ_HtoS |
| 12665 | 5273840U, // BFMLS_VG2_M2Z2Z |
| 12666 | 106199280U, // BFMLS_VG2_M2ZZ |
| 12667 | 206862576U, // BFMLS_VG2_M2ZZI |
| 12668 | 5273841U, // BFMLS_VG4_M4Z4Z |
| 12669 | 106199281U, // BFMLS_VG4_M4ZZ |
| 12670 | 206862577U, // BFMLS_VG4_M4ZZI |
| 12671 | 106985488U, // BFMLS_ZPmZZ |
| 12672 | 86032U, // BFMLS_ZZZI |
| 12673 | 1077392U, // BFMMLA |
| 12674 | 4112U, // BFMMLA_ZZZ_H |
| 12675 | 24672U, // BFMMLA_ZZZ_HtoS |
| 12676 | 1U, // BFMOP4A_M2Z2Z_H |
| 12677 | 1U, // BFMOP4A_M2Z2Z_S |
| 12678 | 1U, // BFMOP4A_M2ZZ_H |
| 12679 | 1U, // BFMOP4A_M2ZZ_S |
| 12680 | 264U, // BFMOP4A_MZ2Z_H |
| 12681 | 264U, // BFMOP4A_MZ2Z_S |
| 12682 | 4112U, // BFMOP4A_MZZ_H |
| 12683 | 4112U, // BFMOP4A_MZZ_S |
| 12684 | 1U, // BFMOP4S_M2Z2Z_H |
| 12685 | 1U, // BFMOP4S_M2Z2Z_S |
| 12686 | 1U, // BFMOP4S_M2ZZ_H |
| 12687 | 1U, // BFMOP4S_M2ZZ_S |
| 12688 | 264U, // BFMOP4S_MZ2Z_H |
| 12689 | 264U, // BFMOP4S_MZ2Z_S |
| 12690 | 4112U, // BFMOP4S_MZZ_H |
| 12691 | 4112U, // BFMOP4S_MZZ_S |
| 12692 | 88168U, // BFMOPA_MPPZZ |
| 12693 | 88168U, // BFMOPA_MPPZZ_H |
| 12694 | 88168U, // BFMOPS_MPPZZ |
| 12695 | 88168U, // BFMOPS_MPPZZ_H |
| 12696 | 4344U, // BFMUL_2Z2Z |
| 12697 | 4128U, // BFMUL_2ZZ |
| 12698 | 4344U, // BFMUL_4Z4Z |
| 12699 | 4128U, // BFMUL_4ZZ |
| 12700 | 102266912U, // BFMUL_ZPmZZ |
| 12701 | 4128U, // BFMUL_ZZZ |
| 12702 | 77856U, // BFMUL_ZZZI |
| 12703 | 268787809U, // BFMWri |
| 12704 | 268787809U, // BFMXri |
| 12705 | 4344U, // BFSCALE_2Z2Z |
| 12706 | 4128U, // BFSCALE_2ZZ |
| 12707 | 4344U, // BFSCALE_4Z4Z |
| 12708 | 4128U, // BFSCALE_4ZZ |
| 12709 | 102266912U, // BFSCALE_ZPZZ_H |
| 12710 | 4336U, // BFSUB_VG2_M2Z_H |
| 12711 | 4337U, // BFSUB_VG4_M4Z_H |
| 12712 | 102266912U, // BFSUB_ZPmZZ |
| 12713 | 4128U, // BFSUB_ZZZ |
| 12714 | 92257U, // BFTMOPA_M2ZZZI_HtoH |
| 12715 | 92257U, // BFTMOPA_M2ZZZI_HtoS |
| 12716 | 206862576U, // BFVDOT_VG2_M2ZZI_HtoS |
| 12717 | 8288U, // BGRP_ZZZ_B |
| 12718 | 10336U, // BGRP_ZZZ_D |
| 12719 | 4128U, // BGRP_ZZZ_H |
| 12720 | 12384U, // BGRP_ZZZ_S |
| 12721 | 34912U, // BICSWrs |
| 12722 | 34912U, // BICSXrs |
| 12723 | 33824792U, // BICS_PPzPP |
| 12724 | 34912U, // BICWrs |
| 12725 | 34912U, // BICXrs |
| 12726 | 33824792U, // BIC_PPzPP |
| 12727 | 33824776U, // BIC_ZPmZ_B |
| 12728 | 67381256U, // BIC_ZPmZ_D |
| 12729 | 102266912U, // BIC_ZPmZ_H |
| 12730 | 134492168U, // BIC_ZPmZ_S |
| 12731 | 10336U, // BIC_ZZZ |
| 12732 | 1861784U, // BICv16i8 |
| 12733 | 1U, // BICv2i32 |
| 12734 | 1U, // BICv4i16 |
| 12735 | 1U, // BICv4i32 |
| 12736 | 1U, // BICv8i16 |
| 12737 | 2648240U, // BICv8i8 |
| 12738 | 1863832U, // BIFv16i8 |
| 12739 | 2650288U, // BIFv8i8 |
| 12740 | 1863832U, // BITv16i8 |
| 12741 | 2650288U, // BITv8i8 |
| 12742 | 0U, // BL |
| 12743 | 0U, // BLR |
| 12744 | 0U, // BLRAA |
| 12745 | 0U, // BLRAAZ |
| 12746 | 0U, // BLRAB |
| 12747 | 0U, // BLRABZ |
| 12748 | 302272616U, // BMOPA_MPPZZ_S |
| 12749 | 302272616U, // BMOPS_MPPZZ_S |
| 12750 | 0U, // BR |
| 12751 | 0U, // BRAA |
| 12752 | 0U, // BRAAZ |
| 12753 | 0U, // BRAB |
| 12754 | 0U, // BRABZ |
| 12755 | 0U, // BRB_IALL |
| 12756 | 0U, // BRB_INJ |
| 12757 | 0U, // BRK |
| 12758 | 8216U, // BRKAS_PPzP |
| 12759 | 8U, // BRKA_PPmP |
| 12760 | 8216U, // BRKA_PPzP |
| 12761 | 8216U, // BRKBS_PPzP |
| 12762 | 8U, // BRKB_PPmP |
| 12763 | 8216U, // BRKB_PPzP |
| 12764 | 33824792U, // BRKNS_PPzP |
| 12765 | 33824792U, // BRKN_PPzP |
| 12766 | 33824792U, // BRKPAS_PPzPP |
| 12767 | 33824792U, // BRKPA_PPzPP |
| 12768 | 33824792U, // BRKPBS_PPzPP |
| 12769 | 33824792U, // BRKPB_PPzPP |
| 12770 | 67381344U, // BSL1N_ZZZZ |
| 12771 | 67381344U, // BSL2N_ZZZZ |
| 12772 | 67381344U, // BSL_ZZZZ |
| 12773 | 1863832U, // BSLv16i8 |
| 12774 | 2650288U, // BSLv8i8 |
| 12775 | 0U, // Bcc |
| 12776 | 335814752U, // CADD_ZZI_B |
| 12777 | 335816800U, // CADD_ZZI_D |
| 12778 | 6584352U, // CADD_ZZI_H |
| 12779 | 335818848U, // CADD_ZZI_S |
| 12780 | 6906129U, // CASAB |
| 12781 | 6906129U, // CASAH |
| 12782 | 6906129U, // CASALB |
| 12783 | 6906129U, // CASALH |
| 12784 | 6906129U, // CASALTX |
| 12785 | 6906129U, // CASALW |
| 12786 | 6906129U, // CASALX |
| 12787 | 6906129U, // CASATX |
| 12788 | 6906129U, // CASAW |
| 12789 | 6906129U, // CASAX |
| 12790 | 6906129U, // CASB |
| 12791 | 6906129U, // CASH |
| 12792 | 6906129U, // CASLB |
| 12793 | 6906129U, // CASLH |
| 12794 | 6906129U, // CASLTX |
| 12795 | 6906129U, // CASLW |
| 12796 | 6906129U, // CASLX |
| 12797 | 0U, // CASPALTX |
| 12798 | 0U, // CASPALW |
| 12799 | 0U, // CASPALX |
| 12800 | 0U, // CASPATX |
| 12801 | 0U, // CASPAW |
| 12802 | 0U, // CASPAX |
| 12803 | 0U, // CASPLTX |
| 12804 | 0U, // CASPLW |
| 12805 | 0U, // CASPLX |
| 12806 | 0U, // CASPTX |
| 12807 | 0U, // CASPW |
| 12808 | 0U, // CASPX |
| 12809 | 6906129U, // CASTX |
| 12810 | 6906129U, // CASW |
| 12811 | 6906129U, // CASX |
| 12812 | 94304U, // CBBEQWrr |
| 12813 | 94304U, // CBBGEWrr |
| 12814 | 94304U, // CBBGTWrr |
| 12815 | 94304U, // CBBHIWrr |
| 12816 | 94304U, // CBBHSWrr |
| 12817 | 94304U, // CBBNEWrr |
| 12818 | 94304U, // CBEQWri |
| 12819 | 94304U, // CBEQWrr |
| 12820 | 94304U, // CBEQXri |
| 12821 | 94304U, // CBEQXrr |
| 12822 | 94304U, // CBGEWrr |
| 12823 | 94304U, // CBGEXrr |
| 12824 | 94304U, // CBGTWri |
| 12825 | 94304U, // CBGTWrr |
| 12826 | 94304U, // CBGTXri |
| 12827 | 94304U, // CBGTXrr |
| 12828 | 94304U, // CBHEQWrr |
| 12829 | 94304U, // CBHGEWrr |
| 12830 | 94304U, // CBHGTWrr |
| 12831 | 94304U, // CBHHIWrr |
| 12832 | 94304U, // CBHHSWrr |
| 12833 | 94304U, // CBHIWri |
| 12834 | 94304U, // CBHIWrr |
| 12835 | 94304U, // CBHIXri |
| 12836 | 94304U, // CBHIXrr |
| 12837 | 94304U, // CBHNEWrr |
| 12838 | 94304U, // CBHSWrr |
| 12839 | 94304U, // CBHSXrr |
| 12840 | 94304U, // CBLOWri |
| 12841 | 94304U, // CBLOXri |
| 12842 | 94304U, // CBLTWri |
| 12843 | 94304U, // CBLTXri |
| 12844 | 94304U, // CBNEWri |
| 12845 | 94304U, // CBNEWrr |
| 12846 | 94304U, // CBNEXri |
| 12847 | 94304U, // CBNEXrr |
| 12848 | 1U, // CBNZW |
| 12849 | 1U, // CBNZX |
| 12850 | 1U, // CBZW |
| 12851 | 1U, // CBZX |
| 12852 | 369375328U, // CCMNWi |
| 12853 | 369375328U, // CCMNWr |
| 12854 | 369375328U, // CCMNXi |
| 12855 | 369375328U, // CCMNXr |
| 12856 | 369375328U, // CCMPWi |
| 12857 | 369375328U, // CCMPWr |
| 12858 | 369375328U, // CCMPXi |
| 12859 | 369375328U, // CCMPXr |
| 12860 | 408445024U, // CDOT_ZZZI_D |
| 12861 | 436556057U, // CDOT_ZZZI_S |
| 12862 | 470048864U, // CDOT_ZZZ_D |
| 12863 | 7108889U, // CDOT_ZZZ_S |
| 12864 | 0U, // CFINV |
| 12865 | 0U, // CHKFEAT |
| 12866 | 33831008U, // CLASTA_RPZ_B |
| 12867 | 67385440U, // CLASTA_RPZ_D |
| 12868 | 503593056U, // CLASTA_RPZ_H |
| 12869 | 134494304U, // CLASTA_RPZ_S |
| 12870 | 33831008U, // CLASTA_VPZ_B |
| 12871 | 67385440U, // CLASTA_VPZ_D |
| 12872 | 503593056U, // CLASTA_VPZ_H |
| 12873 | 134494304U, // CLASTA_VPZ_S |
| 12874 | 33824864U, // CLASTA_ZPZ_B |
| 12875 | 67381344U, // CLASTA_ZPZ_D |
| 12876 | 102266912U, // CLASTA_ZPZ_H |
| 12877 | 134492256U, // CLASTA_ZPZ_S |
| 12878 | 33831008U, // CLASTB_RPZ_B |
| 12879 | 67385440U, // CLASTB_RPZ_D |
| 12880 | 503593056U, // CLASTB_RPZ_H |
| 12881 | 134494304U, // CLASTB_RPZ_S |
| 12882 | 33831008U, // CLASTB_VPZ_B |
| 12883 | 67385440U, // CLASTB_VPZ_D |
| 12884 | 503593056U, // CLASTB_VPZ_H |
| 12885 | 134494304U, // CLASTB_VPZ_S |
| 12886 | 33824864U, // CLASTB_ZPZ_B |
| 12887 | 67381344U, // CLASTB_ZPZ_D |
| 12888 | 102266912U, // CLASTB_ZPZ_H |
| 12889 | 134492256U, // CLASTB_ZPZ_S |
| 12890 | 0U, // CLREX |
| 12891 | 0U, // CLSWr |
| 12892 | 0U, // CLSXr |
| 12893 | 8U, // CLS_ZPmZ_B |
| 12894 | 2056U, // CLS_ZPmZ_D |
| 12895 | 4112U, // CLS_ZPmZ_H |
| 12896 | 6152U, // CLS_ZPmZ_S |
| 12897 | 8216U, // CLS_ZPzZ_B |
| 12898 | 10264U, // CLS_ZPzZ_D |
| 12899 | 4128U, // CLS_ZPzZ_H |
| 12900 | 12312U, // CLS_ZPzZ_S |
| 12901 | 40U, // CLSv16i8 |
| 12902 | 48U, // CLSv2i32 |
| 12903 | 64U, // CLSv4i16 |
| 12904 | 72U, // CLSv4i32 |
| 12905 | 80U, // CLSv8i16 |
| 12906 | 88U, // CLSv8i8 |
| 12907 | 0U, // CLZWr |
| 12908 | 0U, // CLZXr |
| 12909 | 8U, // CLZ_ZPmZ_B |
| 12910 | 2056U, // CLZ_ZPmZ_D |
| 12911 | 4112U, // CLZ_ZPmZ_H |
| 12912 | 6152U, // CLZ_ZPmZ_S |
| 12913 | 8216U, // CLZ_ZPzZ_B |
| 12914 | 10264U, // CLZ_ZPzZ_D |
| 12915 | 4128U, // CLZ_ZPzZ_H |
| 12916 | 12312U, // CLZ_ZPzZ_S |
| 12917 | 40U, // CLZv16i8 |
| 12918 | 48U, // CLZv2i32 |
| 12919 | 64U, // CLZv4i16 |
| 12920 | 72U, // CLZv4i32 |
| 12921 | 80U, // CLZv8i16 |
| 12922 | 88U, // CLZv8i8 |
| 12923 | 1861784U, // CMEQv16i8 |
| 12924 | 288U, // CMEQv16i8rz |
| 12925 | 14432U, // CMEQv1i64 |
| 12926 | 296U, // CMEQv1i64rz |
| 12927 | 2123936U, // CMEQv2i32 |
| 12928 | 304U, // CMEQv2i32rz |
| 12929 | 551040U, // CMEQv2i64 |
| 12930 | 312U, // CMEQv2i64rz |
| 12931 | 2386088U, // CMEQv4i16 |
| 12932 | 320U, // CMEQv4i16rz |
| 12933 | 813192U, // CMEQv4i32 |
| 12934 | 328U, // CMEQv4i32rz |
| 12935 | 1075344U, // CMEQv8i16 |
| 12936 | 336U, // CMEQv8i16rz |
| 12937 | 2648240U, // CMEQv8i8 |
| 12938 | 344U, // CMEQv8i8rz |
| 12939 | 1861784U, // CMGEv16i8 |
| 12940 | 288U, // CMGEv16i8rz |
| 12941 | 14432U, // CMGEv1i64 |
| 12942 | 296U, // CMGEv1i64rz |
| 12943 | 2123936U, // CMGEv2i32 |
| 12944 | 304U, // CMGEv2i32rz |
| 12945 | 551040U, // CMGEv2i64 |
| 12946 | 312U, // CMGEv2i64rz |
| 12947 | 2386088U, // CMGEv4i16 |
| 12948 | 320U, // CMGEv4i16rz |
| 12949 | 813192U, // CMGEv4i32 |
| 12950 | 328U, // CMGEv4i32rz |
| 12951 | 1075344U, // CMGEv8i16 |
| 12952 | 336U, // CMGEv8i16rz |
| 12953 | 2648240U, // CMGEv8i8 |
| 12954 | 344U, // CMGEv8i8rz |
| 12955 | 1861784U, // CMGTv16i8 |
| 12956 | 288U, // CMGTv16i8rz |
| 12957 | 14432U, // CMGTv1i64 |
| 12958 | 296U, // CMGTv1i64rz |
| 12959 | 2123936U, // CMGTv2i32 |
| 12960 | 304U, // CMGTv2i32rz |
| 12961 | 551040U, // CMGTv2i64 |
| 12962 | 312U, // CMGTv2i64rz |
| 12963 | 2386088U, // CMGTv4i16 |
| 12964 | 320U, // CMGTv4i16rz |
| 12965 | 813192U, // CMGTv4i32 |
| 12966 | 328U, // CMGTv4i32rz |
| 12967 | 1075344U, // CMGTv8i16 |
| 12968 | 336U, // CMGTv8i16rz |
| 12969 | 2648240U, // CMGTv8i8 |
| 12970 | 344U, // CMGTv8i8rz |
| 12971 | 1861784U, // CMHIv16i8 |
| 12972 | 14432U, // CMHIv1i64 |
| 12973 | 2123936U, // CMHIv2i32 |
| 12974 | 551040U, // CMHIv2i64 |
| 12975 | 2386088U, // CMHIv4i16 |
| 12976 | 813192U, // CMHIv4i32 |
| 12977 | 1075344U, // CMHIv8i16 |
| 12978 | 2648240U, // CMHIv8i8 |
| 12979 | 1861784U, // CMHSv16i8 |
| 12980 | 14432U, // CMHSv1i64 |
| 12981 | 2123936U, // CMHSv2i32 |
| 12982 | 551040U, // CMHSv2i64 |
| 12983 | 2386088U, // CMHSv4i16 |
| 12984 | 813192U, // CMHSv4i32 |
| 12985 | 1075344U, // CMHSv8i16 |
| 12986 | 2648240U, // CMHSv8i8 |
| 12987 | 436555792U, // CMLA_ZZZI_H |
| 12988 | 408426592U, // CMLA_ZZZI_S |
| 12989 | 7108889U, // CMLA_ZZZ_B |
| 12990 | 470026336U, // CMLA_ZZZ_D |
| 12991 | 7108624U, // CMLA_ZZZ_H |
| 12992 | 470030432U, // CMLA_ZZZ_S |
| 12993 | 288U, // CMLEv16i8rz |
| 12994 | 296U, // CMLEv1i64rz |
| 12995 | 304U, // CMLEv2i32rz |
| 12996 | 312U, // CMLEv2i64rz |
| 12997 | 320U, // CMLEv4i16rz |
| 12998 | 328U, // CMLEv4i32rz |
| 12999 | 336U, // CMLEv8i16rz |
| 13000 | 344U, // CMLEv8i8rz |
| 13001 | 288U, // CMLTv16i8rz |
| 13002 | 296U, // CMLTv1i64rz |
| 13003 | 304U, // CMLTv2i32rz |
| 13004 | 312U, // CMLTv2i64rz |
| 13005 | 320U, // CMLTv4i16rz |
| 13006 | 328U, // CMLTv4i32rz |
| 13007 | 336U, // CMLTv8i16rz |
| 13008 | 344U, // CMLTv8i8rz |
| 13009 | 270360U, // CMPEQ_PPzZI_B |
| 13010 | 272408U, // CMPEQ_PPzZI_D |
| 13011 | 104888352U, // CMPEQ_PPzZI_H |
| 13012 | 274456U, // CMPEQ_PPzZI_S |
| 13013 | 33824792U, // CMPEQ_PPzZZ_B |
| 13014 | 67381272U, // CMPEQ_PPzZZ_D |
| 13015 | 102266912U, // CMPEQ_PPzZZ_H |
| 13016 | 134492184U, // CMPEQ_PPzZZ_S |
| 13017 | 67379224U, // CMPEQ_WIDE_PPzZZ_B |
| 13018 | 4487200U, // CMPEQ_WIDE_PPzZZ_H |
| 13019 | 67383320U, // CMPEQ_WIDE_PPzZZ_S |
| 13020 | 270360U, // CMPGE_PPzZI_B |
| 13021 | 272408U, // CMPGE_PPzZI_D |
| 13022 | 104888352U, // CMPGE_PPzZI_H |
| 13023 | 274456U, // CMPGE_PPzZI_S |
| 13024 | 33824792U, // CMPGE_PPzZZ_B |
| 13025 | 67381272U, // CMPGE_PPzZZ_D |
| 13026 | 102266912U, // CMPGE_PPzZZ_H |
| 13027 | 134492184U, // CMPGE_PPzZZ_S |
| 13028 | 67379224U, // CMPGE_WIDE_PPzZZ_B |
| 13029 | 4487200U, // CMPGE_WIDE_PPzZZ_H |
| 13030 | 67383320U, // CMPGE_WIDE_PPzZZ_S |
| 13031 | 270360U, // CMPGT_PPzZI_B |
| 13032 | 272408U, // CMPGT_PPzZI_D |
| 13033 | 104888352U, // CMPGT_PPzZI_H |
| 13034 | 274456U, // CMPGT_PPzZI_S |
| 13035 | 33824792U, // CMPGT_PPzZZ_B |
| 13036 | 67381272U, // CMPGT_PPzZZ_D |
| 13037 | 102266912U, // CMPGT_PPzZZ_H |
| 13038 | 134492184U, // CMPGT_PPzZZ_S |
| 13039 | 67379224U, // CMPGT_WIDE_PPzZZ_B |
| 13040 | 4487200U, // CMPGT_WIDE_PPzZZ_H |
| 13041 | 67383320U, // CMPGT_WIDE_PPzZZ_S |
| 13042 | 537141272U, // CMPHI_PPzZI_B |
| 13043 | 537143320U, // CMPHI_PPzZI_D |
| 13044 | 7370784U, // CMPHI_PPzZI_H |
| 13045 | 537145368U, // CMPHI_PPzZI_S |
| 13046 | 33824792U, // CMPHI_PPzZZ_B |
| 13047 | 67381272U, // CMPHI_PPzZZ_D |
| 13048 | 102266912U, // CMPHI_PPzZZ_H |
| 13049 | 134492184U, // CMPHI_PPzZZ_S |
| 13050 | 67379224U, // CMPHI_WIDE_PPzZZ_B |
| 13051 | 4487200U, // CMPHI_WIDE_PPzZZ_H |
| 13052 | 67383320U, // CMPHI_WIDE_PPzZZ_S |
| 13053 | 537141272U, // CMPHS_PPzZI_B |
| 13054 | 537143320U, // CMPHS_PPzZI_D |
| 13055 | 7370784U, // CMPHS_PPzZI_H |
| 13056 | 537145368U, // CMPHS_PPzZI_S |
| 13057 | 33824792U, // CMPHS_PPzZZ_B |
| 13058 | 67381272U, // CMPHS_PPzZZ_D |
| 13059 | 102266912U, // CMPHS_PPzZZ_H |
| 13060 | 134492184U, // CMPHS_PPzZZ_S |
| 13061 | 67379224U, // CMPHS_WIDE_PPzZZ_B |
| 13062 | 4487200U, // CMPHS_WIDE_PPzZZ_H |
| 13063 | 67383320U, // CMPHS_WIDE_PPzZZ_S |
| 13064 | 270360U, // CMPLE_PPzZI_B |
| 13065 | 272408U, // CMPLE_PPzZI_D |
| 13066 | 104888352U, // CMPLE_PPzZI_H |
| 13067 | 274456U, // CMPLE_PPzZI_S |
| 13068 | 67379224U, // CMPLE_WIDE_PPzZZ_B |
| 13069 | 4487200U, // CMPLE_WIDE_PPzZZ_H |
| 13070 | 67383320U, // CMPLE_WIDE_PPzZZ_S |
| 13071 | 537141272U, // CMPLO_PPzZI_B |
| 13072 | 537143320U, // CMPLO_PPzZI_D |
| 13073 | 7370784U, // CMPLO_PPzZI_H |
| 13074 | 537145368U, // CMPLO_PPzZI_S |
| 13075 | 67379224U, // CMPLO_WIDE_PPzZZ_B |
| 13076 | 4487200U, // CMPLO_WIDE_PPzZZ_H |
| 13077 | 67383320U, // CMPLO_WIDE_PPzZZ_S |
| 13078 | 537141272U, // CMPLS_PPzZI_B |
| 13079 | 537143320U, // CMPLS_PPzZI_D |
| 13080 | 7370784U, // CMPLS_PPzZI_H |
| 13081 | 537145368U, // CMPLS_PPzZI_S |
| 13082 | 67379224U, // CMPLS_WIDE_PPzZZ_B |
| 13083 | 4487200U, // CMPLS_WIDE_PPzZZ_H |
| 13084 | 67383320U, // CMPLS_WIDE_PPzZZ_S |
| 13085 | 270360U, // CMPLT_PPzZI_B |
| 13086 | 272408U, // CMPLT_PPzZI_D |
| 13087 | 104888352U, // CMPLT_PPzZI_H |
| 13088 | 274456U, // CMPLT_PPzZI_S |
| 13089 | 67379224U, // CMPLT_WIDE_PPzZZ_B |
| 13090 | 4487200U, // CMPLT_WIDE_PPzZZ_H |
| 13091 | 67383320U, // CMPLT_WIDE_PPzZZ_S |
| 13092 | 270360U, // CMPNE_PPzZI_B |
| 13093 | 272408U, // CMPNE_PPzZI_D |
| 13094 | 104888352U, // CMPNE_PPzZI_H |
| 13095 | 274456U, // CMPNE_PPzZI_S |
| 13096 | 33824792U, // CMPNE_PPzZZ_B |
| 13097 | 67381272U, // CMPNE_PPzZZ_D |
| 13098 | 102266912U, // CMPNE_PPzZZ_H |
| 13099 | 134492184U, // CMPNE_PPzZZ_S |
| 13100 | 67379224U, // CMPNE_WIDE_PPzZZ_B |
| 13101 | 4487200U, // CMPNE_WIDE_PPzZZ_H |
| 13102 | 67383320U, // CMPNE_WIDE_PPzZZ_S |
| 13103 | 1861784U, // CMTSTv16i8 |
| 13104 | 14432U, // CMTSTv1i64 |
| 13105 | 2123936U, // CMTSTv2i32 |
| 13106 | 551040U, // CMTSTv2i64 |
| 13107 | 2386088U, // CMTSTv4i16 |
| 13108 | 813192U, // CMTSTv4i32 |
| 13109 | 1075344U, // CMTSTv8i16 |
| 13110 | 2648240U, // CMTSTv8i8 |
| 13111 | 8U, // CNOT_ZPmZ_B |
| 13112 | 2056U, // CNOT_ZPmZ_D |
| 13113 | 4112U, // CNOT_ZPmZ_H |
| 13114 | 6152U, // CNOT_ZPmZ_S |
| 13115 | 8216U, // CNOT_ZPzZ_B |
| 13116 | 10264U, // CNOT_ZPzZ_D |
| 13117 | 4128U, // CNOT_ZPzZ_H |
| 13118 | 12312U, // CNOT_ZPzZ_S |
| 13119 | 353U, // CNTB_XPiI |
| 13120 | 353U, // CNTD_XPiI |
| 13121 | 353U, // CNTH_XPiI |
| 13122 | 1U, // CNTP_XCI_B |
| 13123 | 1U, // CNTP_XCI_D |
| 13124 | 1U, // CNTP_XCI_H |
| 13125 | 1U, // CNTP_XCI_S |
| 13126 | 8288U, // CNTP_XPP_B |
| 13127 | 10336U, // CNTP_XPP_D |
| 13128 | 22624U, // CNTP_XPP_H |
| 13129 | 12384U, // CNTP_XPP_S |
| 13130 | 353U, // CNTW_XPiI |
| 13131 | 0U, // CNTWr |
| 13132 | 0U, // CNTXr |
| 13133 | 8U, // CNT_ZPmZ_B |
| 13134 | 2056U, // CNT_ZPmZ_D |
| 13135 | 4112U, // CNT_ZPmZ_H |
| 13136 | 6152U, // CNT_ZPmZ_S |
| 13137 | 8216U, // CNT_ZPzZ_B |
| 13138 | 10264U, // CNT_ZPzZ_D |
| 13139 | 4128U, // CNT_ZPzZ_H |
| 13140 | 12312U, // CNT_ZPzZ_S |
| 13141 | 40U, // CNTv16i8 |
| 13142 | 88U, // CNTv8i8 |
| 13143 | 8288U, // COMPACT_ZPZ_B |
| 13144 | 10336U, // COMPACT_ZPZ_D |
| 13145 | 4128U, // COMPACT_ZPZ_H |
| 13146 | 12384U, // COMPACT_ZPZ_S |
| 13147 | 0U, // CPYE |
| 13148 | 0U, // CPYEN |
| 13149 | 0U, // CPYERN |
| 13150 | 0U, // CPYERT |
| 13151 | 0U, // CPYERTN |
| 13152 | 0U, // CPYERTRN |
| 13153 | 0U, // CPYERTWN |
| 13154 | 0U, // CPYET |
| 13155 | 0U, // CPYETN |
| 13156 | 0U, // CPYETRN |
| 13157 | 0U, // CPYETWN |
| 13158 | 0U, // CPYEWN |
| 13159 | 0U, // CPYEWT |
| 13160 | 0U, // CPYEWTN |
| 13161 | 0U, // CPYEWTRN |
| 13162 | 0U, // CPYEWTWN |
| 13163 | 0U, // CPYFE |
| 13164 | 0U, // CPYFEN |
| 13165 | 0U, // CPYFERN |
| 13166 | 0U, // CPYFERT |
| 13167 | 0U, // CPYFERTN |
| 13168 | 0U, // CPYFERTRN |
| 13169 | 0U, // CPYFERTWN |
| 13170 | 0U, // CPYFET |
| 13171 | 0U, // CPYFETN |
| 13172 | 0U, // CPYFETRN |
| 13173 | 0U, // CPYFETWN |
| 13174 | 0U, // CPYFEWN |
| 13175 | 0U, // CPYFEWT |
| 13176 | 0U, // CPYFEWTN |
| 13177 | 0U, // CPYFEWTRN |
| 13178 | 0U, // CPYFEWTWN |
| 13179 | 0U, // CPYFM |
| 13180 | 0U, // CPYFMN |
| 13181 | 0U, // CPYFMRN |
| 13182 | 0U, // CPYFMRT |
| 13183 | 0U, // CPYFMRTN |
| 13184 | 0U, // CPYFMRTRN |
| 13185 | 0U, // CPYFMRTWN |
| 13186 | 0U, // CPYFMT |
| 13187 | 0U, // CPYFMTN |
| 13188 | 0U, // CPYFMTRN |
| 13189 | 0U, // CPYFMTWN |
| 13190 | 0U, // CPYFMWN |
| 13191 | 0U, // CPYFMWT |
| 13192 | 0U, // CPYFMWTN |
| 13193 | 0U, // CPYFMWTRN |
| 13194 | 0U, // CPYFMWTWN |
| 13195 | 0U, // CPYFP |
| 13196 | 0U, // CPYFPN |
| 13197 | 0U, // CPYFPRN |
| 13198 | 0U, // CPYFPRT |
| 13199 | 0U, // CPYFPRTN |
| 13200 | 0U, // CPYFPRTRN |
| 13201 | 0U, // CPYFPRTWN |
| 13202 | 0U, // CPYFPT |
| 13203 | 0U, // CPYFPTN |
| 13204 | 0U, // CPYFPTRN |
| 13205 | 0U, // CPYFPTWN |
| 13206 | 0U, // CPYFPWN |
| 13207 | 0U, // CPYFPWT |
| 13208 | 0U, // CPYFPWTN |
| 13209 | 0U, // CPYFPWTRN |
| 13210 | 0U, // CPYFPWTWN |
| 13211 | 0U, // CPYM |
| 13212 | 0U, // CPYMN |
| 13213 | 0U, // CPYMRN |
| 13214 | 0U, // CPYMRT |
| 13215 | 0U, // CPYMRTN |
| 13216 | 0U, // CPYMRTRN |
| 13217 | 0U, // CPYMRTWN |
| 13218 | 0U, // CPYMT |
| 13219 | 0U, // CPYMTN |
| 13220 | 0U, // CPYMTRN |
| 13221 | 0U, // CPYMTWN |
| 13222 | 0U, // CPYMWN |
| 13223 | 0U, // CPYMWT |
| 13224 | 0U, // CPYMWTN |
| 13225 | 0U, // CPYMWTRN |
| 13226 | 0U, // CPYMWTWN |
| 13227 | 0U, // CPYP |
| 13228 | 0U, // CPYPN |
| 13229 | 0U, // CPYPRN |
| 13230 | 0U, // CPYPRT |
| 13231 | 0U, // CPYPRTN |
| 13232 | 0U, // CPYPRTRN |
| 13233 | 0U, // CPYPRTWN |
| 13234 | 0U, // CPYPT |
| 13235 | 0U, // CPYPTN |
| 13236 | 0U, // CPYPTRN |
| 13237 | 0U, // CPYPTWN |
| 13238 | 0U, // CPYPWN |
| 13239 | 0U, // CPYPWT |
| 13240 | 0U, // CPYPWTN |
| 13241 | 0U, // CPYPWTRN |
| 13242 | 0U, // CPYPWTWN |
| 13243 | 96264U, // CPY_ZPmI_B |
| 13244 | 98312U, // CPY_ZPmI_D |
| 13245 | 360U, // CPY_ZPmI_H |
| 13246 | 100360U, // CPY_ZPmI_S |
| 13247 | 90120U, // CPY_ZPmR_B |
| 13248 | 90120U, // CPY_ZPmR_D |
| 13249 | 4464U, // CPY_ZPmR_H |
| 13250 | 90120U, // CPY_ZPmR_S |
| 13251 | 90120U, // CPY_ZPmV_B |
| 13252 | 90120U, // CPY_ZPmV_D |
| 13253 | 4464U, // CPY_ZPmV_H |
| 13254 | 90120U, // CPY_ZPmV_S |
| 13255 | 102424U, // CPY_ZPzI_B |
| 13256 | 104472U, // CPY_ZPzI_D |
| 13257 | 376U, // CPY_ZPzI_H |
| 13258 | 106520U, // CPY_ZPzI_S |
| 13259 | 14432U, // CRC32Brr |
| 13260 | 14432U, // CRC32CBrr |
| 13261 | 14432U, // CRC32CHrr |
| 13262 | 14432U, // CRC32CWrr |
| 13263 | 14432U, // CRC32CXrr |
| 13264 | 14432U, // CRC32Hrr |
| 13265 | 14432U, // CRC32Wrr |
| 13266 | 14432U, // CRC32Xrr |
| 13267 | 369375328U, // CSELWr |
| 13268 | 369375328U, // CSELXr |
| 13269 | 369375328U, // CSINCWr |
| 13270 | 369375328U, // CSINCXr |
| 13271 | 369375328U, // CSINVWr |
| 13272 | 369375328U, // CSINVXr |
| 13273 | 369375328U, // CSNEGWr |
| 13274 | 369375328U, // CSNEGXr |
| 13275 | 0U, // CTERMEQ_WW |
| 13276 | 0U, // CTERMEQ_XX |
| 13277 | 0U, // CTERMNE_WW |
| 13278 | 0U, // CTERMNE_XX |
| 13279 | 0U, // CTZWr |
| 13280 | 0U, // CTZXr |
| 13281 | 0U, // DCPS1 |
| 13282 | 0U, // DCPS2 |
| 13283 | 0U, // DCPS3 |
| 13284 | 2U, // DECB_XPiI |
| 13285 | 2U, // DECD_XPiI |
| 13286 | 2U, // DECD_ZPiI |
| 13287 | 2U, // DECH_XPiI |
| 13288 | 0U, // DECH_ZPiI |
| 13289 | 0U, // DECP_XP_B |
| 13290 | 0U, // DECP_XP_D |
| 13291 | 0U, // DECP_XP_H |
| 13292 | 0U, // DECP_XP_S |
| 13293 | 0U, // DECP_ZP_D |
| 13294 | 1U, // DECP_ZP_H |
| 13295 | 0U, // DECP_ZP_S |
| 13296 | 2U, // DECW_XPiI |
| 13297 | 2U, // DECW_ZPiI |
| 13298 | 0U, // DMB |
| 13299 | 0U, // DRPS |
| 13300 | 0U, // DSB |
| 13301 | 0U, // DSBnXS |
| 13302 | 2U, // DUPM_ZI |
| 13303 | 384U, // DUPQ_ZZI_B |
| 13304 | 384U, // DUPQ_ZZI_D |
| 13305 | 2U, // DUPQ_ZZI_H |
| 13306 | 384U, // DUPQ_ZZI_S |
| 13307 | 2U, // DUP_ZI_B |
| 13308 | 2U, // DUP_ZI_D |
| 13309 | 0U, // DUP_ZI_H |
| 13310 | 2U, // DUP_ZI_S |
| 13311 | 0U, // DUP_ZR_B |
| 13312 | 0U, // DUP_ZR_D |
| 13313 | 1U, // DUP_ZR_H |
| 13314 | 0U, // DUP_ZR_S |
| 13315 | 384U, // DUP_ZZI_B |
| 13316 | 384U, // DUP_ZZI_D |
| 13317 | 2U, // DUP_ZZI_H |
| 13318 | 2U, // DUP_ZZI_Q |
| 13319 | 384U, // DUP_ZZI_S |
| 13320 | 108936U, // DUPi16 |
| 13321 | 108944U, // DUPi32 |
| 13322 | 108952U, // DUPi64 |
| 13323 | 108960U, // DUPi8 |
| 13324 | 0U, // DUPv16i8gpr |
| 13325 | 108960U, // DUPv16i8lane |
| 13326 | 0U, // DUPv2i32gpr |
| 13327 | 108944U, // DUPv2i32lane |
| 13328 | 0U, // DUPv2i64gpr |
| 13329 | 108952U, // DUPv2i64lane |
| 13330 | 0U, // DUPv4i16gpr |
| 13331 | 108936U, // DUPv4i16lane |
| 13332 | 0U, // DUPv4i32gpr |
| 13333 | 108944U, // DUPv4i32lane |
| 13334 | 0U, // DUPv8i16gpr |
| 13335 | 108936U, // DUPv8i16lane |
| 13336 | 0U, // DUPv8i8gpr |
| 13337 | 108960U, // DUPv8i8lane |
| 13338 | 34912U, // EONWrs |
| 13339 | 34912U, // EONXrs |
| 13340 | 172517528U, // EOR3 |
| 13341 | 67381344U, // EOR3_ZZZZ |
| 13342 | 4377U, // EORBT_ZZZ_B |
| 13343 | 2144U, // EORBT_ZZZ_D |
| 13344 | 4112U, // EORBT_ZZZ_H |
| 13345 | 6240U, // EORBT_ZZZ_S |
| 13346 | 8288U, // EORQV_VPZ_B |
| 13347 | 10336U, // EORQV_VPZ_D |
| 13348 | 22624U, // EORQV_VPZ_H |
| 13349 | 12384U, // EORQV_VPZ_S |
| 13350 | 33824792U, // EORS_PPzPP |
| 13351 | 4377U, // EORTB_ZZZ_B |
| 13352 | 2144U, // EORTB_ZZZ_D |
| 13353 | 4112U, // EORTB_ZZZ_H |
| 13354 | 6240U, // EORTB_ZZZ_S |
| 13355 | 0U, // EORV_VPZ_B |
| 13356 | 1U, // EORV_VPZ_D |
| 13357 | 1U, // EORV_VPZ_H |
| 13358 | 1U, // EORV_VPZ_S |
| 13359 | 79968U, // EORWri |
| 13360 | 34912U, // EORWrs |
| 13361 | 82016U, // EORXri |
| 13362 | 34912U, // EORXrs |
| 13363 | 33824792U, // EOR_PPzPP |
| 13364 | 82016U, // EOR_ZI |
| 13365 | 33824776U, // EOR_ZPmZ_B |
| 13366 | 67381256U, // EOR_ZPmZ_D |
| 13367 | 102266912U, // EOR_ZPmZ_H |
| 13368 | 134492168U, // EOR_ZPmZ_S |
| 13369 | 10336U, // EOR_ZZZ |
| 13370 | 1861784U, // EORv16i8 |
| 13371 | 2648240U, // EORv8i8 |
| 13372 | 0U, // ERET |
| 13373 | 0U, // ERETAA |
| 13374 | 0U, // ERETAB |
| 13375 | 8288U, // EXPAND_ZPZ_B |
| 13376 | 10336U, // EXPAND_ZPZ_D |
| 13377 | 4128U, // EXPAND_ZPZ_H |
| 13378 | 12384U, // EXPAND_ZPZ_S |
| 13379 | 270432U, // EXTQ_ZZI |
| 13380 | 110600U, // EXTRACT_ZPMXI_H_B |
| 13381 | 110600U, // EXTRACT_ZPMXI_H_D |
| 13382 | 424U, // EXTRACT_ZPMXI_H_H |
| 13383 | 424U, // EXTRACT_ZPMXI_H_Q |
| 13384 | 110600U, // EXTRACT_ZPMXI_H_S |
| 13385 | 112648U, // EXTRACT_ZPMXI_V_B |
| 13386 | 112648U, // EXTRACT_ZPMXI_V_D |
| 13387 | 432U, // EXTRACT_ZPMXI_V_H |
| 13388 | 432U, // EXTRACT_ZPMXI_V_Q |
| 13389 | 112648U, // EXTRACT_ZPMXI_V_S |
| 13390 | 276576U, // EXTRWrri |
| 13391 | 276576U, // EXTRXrri |
| 13392 | 537141344U, // EXT_ZZI |
| 13393 | 442U, // EXT_ZZI_B |
| 13394 | 4745368U, // EXTv16i8 |
| 13395 | 7628976U, // EXTv8i8 |
| 13396 | 88U, // F1CVTL |
| 13397 | 40U, // F1CVTL2 |
| 13398 | 1U, // F1CVTLT_ZZ_BtoH |
| 13399 | 1U, // F1CVTL_2ZZ_BtoH |
| 13400 | 1U, // F1CVT_2ZZ_BtoH |
| 13401 | 1U, // F1CVT_ZZ_BtoH |
| 13402 | 88U, // F2CVTL |
| 13403 | 40U, // F2CVTL2 |
| 13404 | 1U, // F2CVTLT_ZZ_BtoH |
| 13405 | 1U, // F2CVTL_2ZZ_BtoH |
| 13406 | 1U, // F2CVT_2ZZ_BtoH |
| 13407 | 1U, // F2CVT_ZZ_BtoH |
| 13408 | 14432U, // FABD16 |
| 13409 | 14432U, // FABD32 |
| 13410 | 14432U, // FABD64 |
| 13411 | 67381256U, // FABD_ZPmZ_D |
| 13412 | 102266912U, // FABD_ZPmZ_H |
| 13413 | 134492168U, // FABD_ZPmZ_S |
| 13414 | 2123936U, // FABDv2f32 |
| 13415 | 551040U, // FABDv2f64 |
| 13416 | 2386088U, // FABDv4f16 |
| 13417 | 813192U, // FABDv4f32 |
| 13418 | 1075344U, // FABDv8f16 |
| 13419 | 0U, // FABSDr |
| 13420 | 0U, // FABSHr |
| 13421 | 0U, // FABSSr |
| 13422 | 2056U, // FABS_ZPmZ_D |
| 13423 | 4112U, // FABS_ZPmZ_H |
| 13424 | 6152U, // FABS_ZPmZ_S |
| 13425 | 10264U, // FABS_ZPzZ_D |
| 13426 | 4128U, // FABS_ZPzZ_H |
| 13427 | 12312U, // FABS_ZPzZ_S |
| 13428 | 48U, // FABSv2f32 |
| 13429 | 56U, // FABSv2f64 |
| 13430 | 64U, // FABSv4f16 |
| 13431 | 72U, // FABSv4f32 |
| 13432 | 80U, // FABSv8f16 |
| 13433 | 14432U, // FACGE16 |
| 13434 | 14432U, // FACGE32 |
| 13435 | 14432U, // FACGE64 |
| 13436 | 67381272U, // FACGE_PPzZZ_D |
| 13437 | 102266912U, // FACGE_PPzZZ_H |
| 13438 | 134492184U, // FACGE_PPzZZ_S |
| 13439 | 2123936U, // FACGEv2f32 |
| 13440 | 551040U, // FACGEv2f64 |
| 13441 | 2386088U, // FACGEv4f16 |
| 13442 | 813192U, // FACGEv4f32 |
| 13443 | 1075344U, // FACGEv8f16 |
| 13444 | 14432U, // FACGT16 |
| 13445 | 14432U, // FACGT32 |
| 13446 | 14432U, // FACGT64 |
| 13447 | 67381272U, // FACGT_PPzZZ_D |
| 13448 | 102266912U, // FACGT_PPzZZ_H |
| 13449 | 134492184U, // FACGT_PPzZZ_S |
| 13450 | 2123936U, // FACGTv2f32 |
| 13451 | 551040U, // FACGTv2f64 |
| 13452 | 2386088U, // FACGTv4f16 |
| 13453 | 813192U, // FACGTv4f32 |
| 13454 | 1075344U, // FACGTv8f16 |
| 13455 | 0U, // FADDA_VPZ_D |
| 13456 | 4112U, // FADDA_VPZ_H |
| 13457 | 0U, // FADDA_VPZ_S |
| 13458 | 14432U, // FADDDrr |
| 13459 | 14432U, // FADDHrr |
| 13460 | 67381256U, // FADDP_ZPmZZ_D |
| 13461 | 102266912U, // FADDP_ZPmZZ_H |
| 13462 | 134492168U, // FADDP_ZPmZZ_S |
| 13463 | 2123936U, // FADDPv2f32 |
| 13464 | 551040U, // FADDPv2f64 |
| 13465 | 448U, // FADDPv2i16p |
| 13466 | 48U, // FADDPv2i32p |
| 13467 | 56U, // FADDPv2i64p |
| 13468 | 2386088U, // FADDPv4f16 |
| 13469 | 813192U, // FADDPv4f32 |
| 13470 | 1075344U, // FADDPv8f16 |
| 13471 | 10336U, // FADDQV_D |
| 13472 | 22624U, // FADDQV_H |
| 13473 | 12384U, // FADDQV_S |
| 13474 | 14432U, // FADDSrr |
| 13475 | 1U, // FADDV_VPZ_D |
| 13476 | 1U, // FADDV_VPZ_H |
| 13477 | 1U, // FADDV_VPZ_S |
| 13478 | 4296U, // FADD_VG2_M2Z_D |
| 13479 | 4336U, // FADD_VG2_M2Z_H |
| 13480 | 4304U, // FADD_VG2_M2Z_S |
| 13481 | 4297U, // FADD_VG4_M4Z_D |
| 13482 | 4337U, // FADD_VG4_M4Z_H |
| 13483 | 4305U, // FADD_VG4_M4Z_S |
| 13484 | 570697736U, // FADD_ZPmI_D |
| 13485 | 7895072U, // FADD_ZPmI_H |
| 13486 | 570699784U, // FADD_ZPmI_S |
| 13487 | 67381256U, // FADD_ZPmZ_D |
| 13488 | 102266912U, // FADD_ZPmZ_H |
| 13489 | 134492168U, // FADD_ZPmZ_S |
| 13490 | 10336U, // FADD_ZZZ_D |
| 13491 | 4128U, // FADD_ZZZ_H |
| 13492 | 12384U, // FADD_ZZZ_S |
| 13493 | 2123936U, // FADDv2f32 |
| 13494 | 551040U, // FADDv2f64 |
| 13495 | 2386088U, // FADDv4f16 |
| 13496 | 813192U, // FADDv4f32 |
| 13497 | 1075344U, // FADDv8f16 |
| 13498 | 4552U, // FAMAX_2Z2Z_D |
| 13499 | 4344U, // FAMAX_2Z2Z_H |
| 13500 | 4560U, // FAMAX_2Z2Z_S |
| 13501 | 4552U, // FAMAX_4Z4Z_D |
| 13502 | 4344U, // FAMAX_4Z4Z_H |
| 13503 | 4560U, // FAMAX_4Z4Z_S |
| 13504 | 67381256U, // FAMAX_ZPmZ_D |
| 13505 | 102266912U, // FAMAX_ZPmZ_H |
| 13506 | 134492168U, // FAMAX_ZPmZ_S |
| 13507 | 2123936U, // FAMAXv2f32 |
| 13508 | 551040U, // FAMAXv2f64 |
| 13509 | 2386088U, // FAMAXv4f16 |
| 13510 | 813192U, // FAMAXv4f32 |
| 13511 | 1075344U, // FAMAXv8f16 |
| 13512 | 4552U, // FAMIN_2Z2Z_D |
| 13513 | 4344U, // FAMIN_2Z2Z_H |
| 13514 | 4560U, // FAMIN_2Z2Z_S |
| 13515 | 4552U, // FAMIN_4Z4Z_D |
| 13516 | 4344U, // FAMIN_4Z4Z_H |
| 13517 | 4560U, // FAMIN_4Z4Z_S |
| 13518 | 67381256U, // FAMIN_ZPmZ_D |
| 13519 | 102266912U, // FAMIN_ZPmZ_H |
| 13520 | 134492168U, // FAMIN_ZPmZ_S |
| 13521 | 2123936U, // FAMINv2f32 |
| 13522 | 551040U, // FAMINv2f64 |
| 13523 | 2386088U, // FAMINv4f16 |
| 13524 | 813192U, // FAMINv4f32 |
| 13525 | 1075344U, // FAMINv8f16 |
| 13526 | 67381256U, // FCADD_ZPmZ_D |
| 13527 | 404256800U, // FCADD_ZPmZ_H |
| 13528 | 134492168U, // FCADD_ZPmZ_S |
| 13529 | 343697568U, // FCADDv2f32 |
| 13530 | 343959680U, // FCADDv2f64 |
| 13531 | 344221864U, // FCADDv4f16 |
| 13532 | 344483976U, // FCADDv4f32 |
| 13533 | 344746128U, // FCADDv8f16 |
| 13534 | 369375328U, // FCCMPDrr |
| 13535 | 369375328U, // FCCMPEDrr |
| 13536 | 369375328U, // FCCMPEHrr |
| 13537 | 369375328U, // FCCMPESrr |
| 13538 | 369375328U, // FCCMPHrr |
| 13539 | 369375328U, // FCCMPSrr |
| 13540 | 472U, // FCLAMP_VG2_2Z2Z_D |
| 13541 | 4112U, // FCLAMP_VG2_2Z2Z_H |
| 13542 | 120U, // FCLAMP_VG2_2Z2Z_S |
| 13543 | 472U, // FCLAMP_VG4_4Z4Z_D |
| 13544 | 4112U, // FCLAMP_VG4_4Z4Z_H |
| 13545 | 120U, // FCLAMP_VG4_4Z4Z_S |
| 13546 | 2144U, // FCLAMP_ZZZ_D |
| 13547 | 4112U, // FCLAMP_ZZZ_H |
| 13548 | 6240U, // FCLAMP_ZZZ_S |
| 13549 | 14432U, // FCMEQ16 |
| 13550 | 14432U, // FCMEQ32 |
| 13551 | 14432U, // FCMEQ64 |
| 13552 | 9447448U, // FCMEQ_PPzZ0_D |
| 13553 | 114720U, // FCMEQ_PPzZ0_H |
| 13554 | 9449496U, // FCMEQ_PPzZ0_S |
| 13555 | 67381272U, // FCMEQ_PPzZZ_D |
| 13556 | 102266912U, // FCMEQ_PPzZZ_H |
| 13557 | 134492184U, // FCMEQ_PPzZZ_S |
| 13558 | 480U, // FCMEQv1i16rz |
| 13559 | 480U, // FCMEQv1i32rz |
| 13560 | 480U, // FCMEQv1i64rz |
| 13561 | 2123936U, // FCMEQv2f32 |
| 13562 | 551040U, // FCMEQv2f64 |
| 13563 | 488U, // FCMEQv2i32rz |
| 13564 | 496U, // FCMEQv2i64rz |
| 13565 | 2386088U, // FCMEQv4f16 |
| 13566 | 813192U, // FCMEQv4f32 |
| 13567 | 504U, // FCMEQv4i16rz |
| 13568 | 512U, // FCMEQv4i32rz |
| 13569 | 1075344U, // FCMEQv8f16 |
| 13570 | 520U, // FCMEQv8i16rz |
| 13571 | 14432U, // FCMGE16 |
| 13572 | 14432U, // FCMGE32 |
| 13573 | 14432U, // FCMGE64 |
| 13574 | 9447448U, // FCMGE_PPzZ0_D |
| 13575 | 114720U, // FCMGE_PPzZ0_H |
| 13576 | 9449496U, // FCMGE_PPzZ0_S |
| 13577 | 67381272U, // FCMGE_PPzZZ_D |
| 13578 | 102266912U, // FCMGE_PPzZZ_H |
| 13579 | 134492184U, // FCMGE_PPzZZ_S |
| 13580 | 480U, // FCMGEv1i16rz |
| 13581 | 480U, // FCMGEv1i32rz |
| 13582 | 480U, // FCMGEv1i64rz |
| 13583 | 2123936U, // FCMGEv2f32 |
| 13584 | 551040U, // FCMGEv2f64 |
| 13585 | 488U, // FCMGEv2i32rz |
| 13586 | 496U, // FCMGEv2i64rz |
| 13587 | 2386088U, // FCMGEv4f16 |
| 13588 | 813192U, // FCMGEv4f32 |
| 13589 | 504U, // FCMGEv4i16rz |
| 13590 | 512U, // FCMGEv4i32rz |
| 13591 | 1075344U, // FCMGEv8f16 |
| 13592 | 520U, // FCMGEv8i16rz |
| 13593 | 14432U, // FCMGT16 |
| 13594 | 14432U, // FCMGT32 |
| 13595 | 14432U, // FCMGT64 |
| 13596 | 9447448U, // FCMGT_PPzZ0_D |
| 13597 | 114720U, // FCMGT_PPzZ0_H |
| 13598 | 9449496U, // FCMGT_PPzZ0_S |
| 13599 | 67381272U, // FCMGT_PPzZZ_D |
| 13600 | 102266912U, // FCMGT_PPzZZ_H |
| 13601 | 134492184U, // FCMGT_PPzZZ_S |
| 13602 | 480U, // FCMGTv1i16rz |
| 13603 | 480U, // FCMGTv1i32rz |
| 13604 | 480U, // FCMGTv1i64rz |
| 13605 | 2123936U, // FCMGTv2f32 |
| 13606 | 551040U, // FCMGTv2f64 |
| 13607 | 488U, // FCMGTv2i32rz |
| 13608 | 496U, // FCMGTv2i64rz |
| 13609 | 2386088U, // FCMGTv4f16 |
| 13610 | 813192U, // FCMGTv4f32 |
| 13611 | 504U, // FCMGTv4i16rz |
| 13612 | 512U, // FCMGTv4i32rz |
| 13613 | 1075344U, // FCMGTv8f16 |
| 13614 | 520U, // FCMGTv8i16rz |
| 13615 | 604243976U, // FCMLA_ZPmZZ_D |
| 13616 | 408975376U, // FCMLA_ZPmZZ_H |
| 13617 | 637802504U, // FCMLA_ZPmZZ_S |
| 13618 | 436555792U, // FCMLA_ZZZI_H |
| 13619 | 408426592U, // FCMLA_ZZZI_S |
| 13620 | 477917344U, // FCMLAv2f32 |
| 13621 | 478179456U, // FCMLAv2f64 |
| 13622 | 478441640U, // FCMLAv4f16 |
| 13623 | 240939176U, // FCMLAv4f16_indexed |
| 13624 | 478703752U, // FCMLAv4f32 |
| 13625 | 244609160U, // FCMLAv4f32_indexed |
| 13626 | 478965904U, // FCMLAv8f16 |
| 13627 | 240939152U, // FCMLAv8f16_indexed |
| 13628 | 9447448U, // FCMLE_PPzZ0_D |
| 13629 | 114720U, // FCMLE_PPzZ0_H |
| 13630 | 9449496U, // FCMLE_PPzZ0_S |
| 13631 | 480U, // FCMLEv1i16rz |
| 13632 | 480U, // FCMLEv1i32rz |
| 13633 | 480U, // FCMLEv1i64rz |
| 13634 | 488U, // FCMLEv2i32rz |
| 13635 | 496U, // FCMLEv2i64rz |
| 13636 | 504U, // FCMLEv4i16rz |
| 13637 | 512U, // FCMLEv4i32rz |
| 13638 | 520U, // FCMLEv8i16rz |
| 13639 | 9447448U, // FCMLT_PPzZ0_D |
| 13640 | 114720U, // FCMLT_PPzZ0_H |
| 13641 | 9449496U, // FCMLT_PPzZ0_S |
| 13642 | 480U, // FCMLTv1i16rz |
| 13643 | 480U, // FCMLTv1i32rz |
| 13644 | 480U, // FCMLTv1i64rz |
| 13645 | 488U, // FCMLTv2i32rz |
| 13646 | 496U, // FCMLTv2i64rz |
| 13647 | 504U, // FCMLTv4i16rz |
| 13648 | 512U, // FCMLTv4i32rz |
| 13649 | 520U, // FCMLTv8i16rz |
| 13650 | 9447448U, // FCMNE_PPzZ0_D |
| 13651 | 114720U, // FCMNE_PPzZ0_H |
| 13652 | 9449496U, // FCMNE_PPzZ0_S |
| 13653 | 67381272U, // FCMNE_PPzZZ_D |
| 13654 | 102266912U, // FCMNE_PPzZZ_H |
| 13655 | 134492184U, // FCMNE_PPzZZ_S |
| 13656 | 0U, // FCMPDri |
| 13657 | 0U, // FCMPDrr |
| 13658 | 0U, // FCMPEDri |
| 13659 | 0U, // FCMPEDrr |
| 13660 | 0U, // FCMPEHri |
| 13661 | 0U, // FCMPEHrr |
| 13662 | 0U, // FCMPESri |
| 13663 | 0U, // FCMPESrr |
| 13664 | 0U, // FCMPHri |
| 13665 | 0U, // FCMPHrr |
| 13666 | 0U, // FCMPSri |
| 13667 | 0U, // FCMPSrr |
| 13668 | 67381272U, // FCMUO_PPzZZ_D |
| 13669 | 102266912U, // FCMUO_PPzZZ_H |
| 13670 | 134492184U, // FCMUO_PPzZZ_S |
| 13671 | 116744U, // FCPY_ZPmI_D |
| 13672 | 528U, // FCPY_ZPmI_H |
| 13673 | 116744U, // FCPY_ZPmI_S |
| 13674 | 369375328U, // FCSELDrrr |
| 13675 | 369375328U, // FCSELHrrr |
| 13676 | 369375328U, // FCSELSrrr |
| 13677 | 0U, // FCVTASDHr |
| 13678 | 0U, // FCVTASDSr |
| 13679 | 0U, // FCVTASSDr |
| 13680 | 0U, // FCVTASSHr |
| 13681 | 0U, // FCVTASUWDr |
| 13682 | 0U, // FCVTASUWHr |
| 13683 | 0U, // FCVTASUWSr |
| 13684 | 0U, // FCVTASUXDr |
| 13685 | 0U, // FCVTASUXHr |
| 13686 | 0U, // FCVTASUXSr |
| 13687 | 0U, // FCVTASv1f16 |
| 13688 | 0U, // FCVTASv1i32 |
| 13689 | 0U, // FCVTASv1i64 |
| 13690 | 48U, // FCVTASv2f32 |
| 13691 | 56U, // FCVTASv2f64 |
| 13692 | 64U, // FCVTASv4f16 |
| 13693 | 72U, // FCVTASv4f32 |
| 13694 | 80U, // FCVTASv8f16 |
| 13695 | 0U, // FCVTAUDHr |
| 13696 | 0U, // FCVTAUDSr |
| 13697 | 0U, // FCVTAUSDr |
| 13698 | 0U, // FCVTAUSHr |
| 13699 | 0U, // FCVTAUUWDr |
| 13700 | 0U, // FCVTAUUWHr |
| 13701 | 0U, // FCVTAUUWSr |
| 13702 | 0U, // FCVTAUUXDr |
| 13703 | 0U, // FCVTAUUXHr |
| 13704 | 0U, // FCVTAUUXSr |
| 13705 | 0U, // FCVTAUv1f16 |
| 13706 | 0U, // FCVTAUv1i32 |
| 13707 | 0U, // FCVTAUv1i64 |
| 13708 | 48U, // FCVTAUv2f32 |
| 13709 | 56U, // FCVTAUv2f64 |
| 13710 | 64U, // FCVTAUv4f16 |
| 13711 | 72U, // FCVTAUv4f32 |
| 13712 | 80U, // FCVTAUv8f16 |
| 13713 | 0U, // FCVTDHr |
| 13714 | 0U, // FCVTDSr |
| 13715 | 0U, // FCVTHDr |
| 13716 | 0U, // FCVTHSr |
| 13717 | 24584U, // FCVTLT_ZPmZ_HtoS |
| 13718 | 6152U, // FCVTLT_ZPmZ_StoD |
| 13719 | 22552U, // FCVTLT_ZPzZ_HtoS |
| 13720 | 12312U, // FCVTLT_ZPzZ_StoD |
| 13721 | 1U, // FCVTL_2ZZ_H_S |
| 13722 | 48U, // FCVTLv2i32 |
| 13723 | 64U, // FCVTLv4i16 |
| 13724 | 72U, // FCVTLv4i32 |
| 13725 | 80U, // FCVTLv8i16 |
| 13726 | 0U, // FCVTMSDHr |
| 13727 | 0U, // FCVTMSDSr |
| 13728 | 0U, // FCVTMSSDr |
| 13729 | 0U, // FCVTMSSHr |
| 13730 | 0U, // FCVTMSUWDr |
| 13731 | 0U, // FCVTMSUWHr |
| 13732 | 0U, // FCVTMSUWSr |
| 13733 | 0U, // FCVTMSUXDr |
| 13734 | 0U, // FCVTMSUXHr |
| 13735 | 0U, // FCVTMSUXSr |
| 13736 | 0U, // FCVTMSv1f16 |
| 13737 | 0U, // FCVTMSv1i32 |
| 13738 | 0U, // FCVTMSv1i64 |
| 13739 | 48U, // FCVTMSv2f32 |
| 13740 | 56U, // FCVTMSv2f64 |
| 13741 | 64U, // FCVTMSv4f16 |
| 13742 | 72U, // FCVTMSv4f32 |
| 13743 | 80U, // FCVTMSv8f16 |
| 13744 | 0U, // FCVTMUDHr |
| 13745 | 0U, // FCVTMUDSr |
| 13746 | 0U, // FCVTMUSDr |
| 13747 | 0U, // FCVTMUSHr |
| 13748 | 0U, // FCVTMUUWDr |
| 13749 | 0U, // FCVTMUUWHr |
| 13750 | 0U, // FCVTMUUWSr |
| 13751 | 0U, // FCVTMUUXDr |
| 13752 | 0U, // FCVTMUUXHr |
| 13753 | 0U, // FCVTMUUXSr |
| 13754 | 0U, // FCVTMUv1f16 |
| 13755 | 0U, // FCVTMUv1i32 |
| 13756 | 0U, // FCVTMUv1i64 |
| 13757 | 48U, // FCVTMUv2f32 |
| 13758 | 56U, // FCVTMUv2f64 |
| 13759 | 64U, // FCVTMUv4f16 |
| 13760 | 72U, // FCVTMUv4f32 |
| 13761 | 80U, // FCVTMUv8f16 |
| 13762 | 2U, // FCVTNB_Z2Z_StoB |
| 13763 | 0U, // FCVTNSDHr |
| 13764 | 0U, // FCVTNSDSr |
| 13765 | 0U, // FCVTNSSDr |
| 13766 | 0U, // FCVTNSSHr |
| 13767 | 0U, // FCVTNSUWDr |
| 13768 | 0U, // FCVTNSUWHr |
| 13769 | 0U, // FCVTNSUWSr |
| 13770 | 0U, // FCVTNSUXDr |
| 13771 | 0U, // FCVTNSUXHr |
| 13772 | 0U, // FCVTNSUXSr |
| 13773 | 0U, // FCVTNSv1f16 |
| 13774 | 0U, // FCVTNSv1i32 |
| 13775 | 0U, // FCVTNSv1i64 |
| 13776 | 48U, // FCVTNSv2f32 |
| 13777 | 56U, // FCVTNSv2f64 |
| 13778 | 64U, // FCVTNSv4f16 |
| 13779 | 72U, // FCVTNSv4f32 |
| 13780 | 80U, // FCVTNSv8f16 |
| 13781 | 2U, // FCVTNT_Z2Z_StoB |
| 13782 | 2056U, // FCVTNT_ZPmZ_DtoS |
| 13783 | 120U, // FCVTNT_ZPmZ_StoH |
| 13784 | 2072U, // FCVTNT_ZPzZ_DtoS |
| 13785 | 120U, // FCVTNT_ZPzZ_StoH |
| 13786 | 0U, // FCVTNUDHr |
| 13787 | 0U, // FCVTNUDSr |
| 13788 | 0U, // FCVTNUSDr |
| 13789 | 0U, // FCVTNUSHr |
| 13790 | 0U, // FCVTNUUWDr |
| 13791 | 0U, // FCVTNUUWHr |
| 13792 | 0U, // FCVTNUUWSr |
| 13793 | 0U, // FCVTNUUXDr |
| 13794 | 0U, // FCVTNUUXHr |
| 13795 | 0U, // FCVTNUUXSr |
| 13796 | 0U, // FCVTNUv1f16 |
| 13797 | 0U, // FCVTNUv1i32 |
| 13798 | 0U, // FCVTNUv1i64 |
| 13799 | 48U, // FCVTNUv2f32 |
| 13800 | 56U, // FCVTNUv2f64 |
| 13801 | 64U, // FCVTNUv4f16 |
| 13802 | 72U, // FCVTNUv4f32 |
| 13803 | 80U, // FCVTNUv8f16 |
| 13804 | 1075344U, // FCVTN_F16v16f8 |
| 13805 | 2386088U, // FCVTN_F16v8f8 |
| 13806 | 815240U, // FCVTN_F322v16f8 |
| 13807 | 813192U, // FCVTN_F32v8f8 |
| 13808 | 1U, // FCVTN_Z2Z_HtoB |
| 13809 | 1U, // FCVTN_Z2Z_StoH |
| 13810 | 2U, // FCVTN_Z4Z_StoB |
| 13811 | 56U, // FCVTNv2i32 |
| 13812 | 72U, // FCVTNv4i16 |
| 13813 | 56U, // FCVTNv4i32 |
| 13814 | 72U, // FCVTNv8i16 |
| 13815 | 0U, // FCVTPSDHr |
| 13816 | 0U, // FCVTPSDSr |
| 13817 | 0U, // FCVTPSSDr |
| 13818 | 0U, // FCVTPSSHr |
| 13819 | 0U, // FCVTPSUWDr |
| 13820 | 0U, // FCVTPSUWHr |
| 13821 | 0U, // FCVTPSUWSr |
| 13822 | 0U, // FCVTPSUXDr |
| 13823 | 0U, // FCVTPSUXHr |
| 13824 | 0U, // FCVTPSUXSr |
| 13825 | 0U, // FCVTPSv1f16 |
| 13826 | 0U, // FCVTPSv1i32 |
| 13827 | 0U, // FCVTPSv1i64 |
| 13828 | 48U, // FCVTPSv2f32 |
| 13829 | 56U, // FCVTPSv2f64 |
| 13830 | 64U, // FCVTPSv4f16 |
| 13831 | 72U, // FCVTPSv4f32 |
| 13832 | 80U, // FCVTPSv8f16 |
| 13833 | 0U, // FCVTPUDHr |
| 13834 | 0U, // FCVTPUDSr |
| 13835 | 0U, // FCVTPUSDr |
| 13836 | 0U, // FCVTPUSHr |
| 13837 | 0U, // FCVTPUUWDr |
| 13838 | 0U, // FCVTPUUWHr |
| 13839 | 0U, // FCVTPUUWSr |
| 13840 | 0U, // FCVTPUUXDr |
| 13841 | 0U, // FCVTPUUXHr |
| 13842 | 0U, // FCVTPUUXSr |
| 13843 | 0U, // FCVTPUv1f16 |
| 13844 | 0U, // FCVTPUv1i32 |
| 13845 | 0U, // FCVTPUv1i64 |
| 13846 | 48U, // FCVTPUv2f32 |
| 13847 | 56U, // FCVTPUv2f64 |
| 13848 | 64U, // FCVTPUv4f16 |
| 13849 | 72U, // FCVTPUv4f32 |
| 13850 | 80U, // FCVTPUv8f16 |
| 13851 | 0U, // FCVTSDr |
| 13852 | 0U, // FCVTSHr |
| 13853 | 2056U, // FCVTXNT_ZPmZ_DtoS |
| 13854 | 2072U, // FCVTXNT_ZPzZ_StoD |
| 13855 | 0U, // FCVTXNv1i64 |
| 13856 | 56U, // FCVTXNv2f32 |
| 13857 | 56U, // FCVTXNv4f32 |
| 13858 | 2056U, // FCVTX_ZPmZ_DtoS |
| 13859 | 10264U, // FCVTX_ZPzZ_DtoS |
| 13860 | 0U, // FCVTZSDHr |
| 13861 | 0U, // FCVTZSDSr |
| 13862 | 2U, // FCVTZSN_Z2Z_DtoS |
| 13863 | 1U, // FCVTZSN_Z2Z_HtoB |
| 13864 | 1U, // FCVTZSN_Z2Z_StoH |
| 13865 | 0U, // FCVTZSSDr |
| 13866 | 0U, // FCVTZSSHr |
| 13867 | 14432U, // FCVTZSSWDri |
| 13868 | 14432U, // FCVTZSSWHri |
| 13869 | 14432U, // FCVTZSSWSri |
| 13870 | 14432U, // FCVTZSSXDri |
| 13871 | 14432U, // FCVTZSSXHri |
| 13872 | 14432U, // FCVTZSSXSri |
| 13873 | 0U, // FCVTZSUWDr |
| 13874 | 0U, // FCVTZSUWHr |
| 13875 | 0U, // FCVTZSUWSr |
| 13876 | 0U, // FCVTZSUXDr |
| 13877 | 0U, // FCVTZSUXHr |
| 13878 | 0U, // FCVTZSUXSr |
| 13879 | 1U, // FCVTZS_2Z2Z_StoS |
| 13880 | 1U, // FCVTZS_4Z4Z_StoS |
| 13881 | 2056U, // FCVTZS_ZPmZ_DtoD |
| 13882 | 2056U, // FCVTZS_ZPmZ_DtoS |
| 13883 | 24584U, // FCVTZS_ZPmZ_HtoD |
| 13884 | 4112U, // FCVTZS_ZPmZ_HtoH |
| 13885 | 24584U, // FCVTZS_ZPmZ_HtoS |
| 13886 | 6152U, // FCVTZS_ZPmZ_StoD |
| 13887 | 6152U, // FCVTZS_ZPmZ_StoS |
| 13888 | 10264U, // FCVTZS_ZPzZ_DtoD |
| 13889 | 10264U, // FCVTZS_ZPzZ_DtoS |
| 13890 | 22552U, // FCVTZS_ZPzZ_HtoD |
| 13891 | 4128U, // FCVTZS_ZPzZ_HtoH |
| 13892 | 22552U, // FCVTZS_ZPzZ_HtoS |
| 13893 | 12312U, // FCVTZS_ZPzZ_StoD |
| 13894 | 12312U, // FCVTZS_ZPzZ_StoS |
| 13895 | 14432U, // FCVTZSd |
| 13896 | 14432U, // FCVTZSh |
| 13897 | 14432U, // FCVTZSs |
| 13898 | 0U, // FCVTZSv1f16 |
| 13899 | 0U, // FCVTZSv1i32 |
| 13900 | 0U, // FCVTZSv1i64 |
| 13901 | 48U, // FCVTZSv2f32 |
| 13902 | 56U, // FCVTZSv2f64 |
| 13903 | 14496U, // FCVTZSv2i32_shift |
| 13904 | 14464U, // FCVTZSv2i64_shift |
| 13905 | 64U, // FCVTZSv4f16 |
| 13906 | 72U, // FCVTZSv4f32 |
| 13907 | 14504U, // FCVTZSv4i16_shift |
| 13908 | 14472U, // FCVTZSv4i32_shift |
| 13909 | 80U, // FCVTZSv8f16 |
| 13910 | 14480U, // FCVTZSv8i16_shift |
| 13911 | 0U, // FCVTZUDHr |
| 13912 | 0U, // FCVTZUDSr |
| 13913 | 2U, // FCVTZUN_Z2Z_DtoS |
| 13914 | 1U, // FCVTZUN_Z2Z_HtoB |
| 13915 | 1U, // FCVTZUN_Z2Z_StoH |
| 13916 | 0U, // FCVTZUSDr |
| 13917 | 0U, // FCVTZUSHr |
| 13918 | 14432U, // FCVTZUSWDri |
| 13919 | 14432U, // FCVTZUSWHri |
| 13920 | 14432U, // FCVTZUSWSri |
| 13921 | 14432U, // FCVTZUSXDri |
| 13922 | 14432U, // FCVTZUSXHri |
| 13923 | 14432U, // FCVTZUSXSri |
| 13924 | 0U, // FCVTZUUWDr |
| 13925 | 0U, // FCVTZUUWHr |
| 13926 | 0U, // FCVTZUUWSr |
| 13927 | 0U, // FCVTZUUXDr |
| 13928 | 0U, // FCVTZUUXHr |
| 13929 | 0U, // FCVTZUUXSr |
| 13930 | 1U, // FCVTZU_2Z2Z_StoS |
| 13931 | 1U, // FCVTZU_4Z4Z_StoS |
| 13932 | 2056U, // FCVTZU_ZPmZ_DtoD |
| 13933 | 2056U, // FCVTZU_ZPmZ_DtoS |
| 13934 | 24584U, // FCVTZU_ZPmZ_HtoD |
| 13935 | 4112U, // FCVTZU_ZPmZ_HtoH |
| 13936 | 24584U, // FCVTZU_ZPmZ_HtoS |
| 13937 | 6152U, // FCVTZU_ZPmZ_StoD |
| 13938 | 6152U, // FCVTZU_ZPmZ_StoS |
| 13939 | 10264U, // FCVTZU_ZPzZ_DtoD |
| 13940 | 10264U, // FCVTZU_ZPzZ_DtoS |
| 13941 | 22552U, // FCVTZU_ZPzZ_HtoD |
| 13942 | 4128U, // FCVTZU_ZPzZ_HtoH |
| 13943 | 22552U, // FCVTZU_ZPzZ_HtoS |
| 13944 | 12312U, // FCVTZU_ZPzZ_StoD |
| 13945 | 12312U, // FCVTZU_ZPzZ_StoS |
| 13946 | 14432U, // FCVTZUd |
| 13947 | 14432U, // FCVTZUh |
| 13948 | 14432U, // FCVTZUs |
| 13949 | 0U, // FCVTZUv1f16 |
| 13950 | 0U, // FCVTZUv1i32 |
| 13951 | 0U, // FCVTZUv1i64 |
| 13952 | 48U, // FCVTZUv2f32 |
| 13953 | 56U, // FCVTZUv2f64 |
| 13954 | 14496U, // FCVTZUv2i32_shift |
| 13955 | 14464U, // FCVTZUv2i64_shift |
| 13956 | 64U, // FCVTZUv4f16 |
| 13957 | 72U, // FCVTZUv4f32 |
| 13958 | 14504U, // FCVTZUv4i16_shift |
| 13959 | 14472U, // FCVTZUv4i32_shift |
| 13960 | 80U, // FCVTZUv8f16 |
| 13961 | 14480U, // FCVTZUv8i16_shift |
| 13962 | 1U, // FCVT_2ZZ_H_S |
| 13963 | 1U, // FCVT_Z2Z_HtoB |
| 13964 | 1U, // FCVT_Z2Z_StoH |
| 13965 | 2U, // FCVT_Z4Z_StoB |
| 13966 | 472U, // FCVT_ZPmZ_DtoH |
| 13967 | 2056U, // FCVT_ZPmZ_DtoS |
| 13968 | 24584U, // FCVT_ZPmZ_HtoD |
| 13969 | 24584U, // FCVT_ZPmZ_HtoS |
| 13970 | 6152U, // FCVT_ZPmZ_StoD |
| 13971 | 120U, // FCVT_ZPmZ_StoH |
| 13972 | 4288U, // FCVT_ZPzZ_DtoH |
| 13973 | 10264U, // FCVT_ZPzZ_DtoS |
| 13974 | 22552U, // FCVT_ZPzZ_HtoD |
| 13975 | 22552U, // FCVT_ZPzZ_HtoS |
| 13976 | 12312U, // FCVT_ZPzZ_StoD |
| 13977 | 4208U, // FCVT_ZPzZ_StoH |
| 13978 | 14432U, // FDIVDrr |
| 13979 | 14432U, // FDIVHrr |
| 13980 | 67381256U, // FDIVR_ZPmZ_D |
| 13981 | 102266912U, // FDIVR_ZPmZ_H |
| 13982 | 134492168U, // FDIVR_ZPmZ_S |
| 13983 | 14432U, // FDIVSrr |
| 13984 | 67381256U, // FDIV_ZPmZ_D |
| 13985 | 102266912U, // FDIV_ZPmZ_H |
| 13986 | 134492168U, // FDIV_ZPmZ_S |
| 13987 | 2123936U, // FDIVv2f32 |
| 13988 | 551040U, // FDIVv2f64 |
| 13989 | 2386088U, // FDIVv4f16 |
| 13990 | 813192U, // FDIVv4f32 |
| 13991 | 1075344U, // FDIVv8f16 |
| 13992 | 119320U, // FDOT_VG2_M2Z2Z_BtoH |
| 13993 | 119320U, // FDOT_VG2_M2Z2Z_BtoS |
| 13994 | 5273840U, // FDOT_VG2_M2Z2Z_HtoS |
| 13995 | 10082840U, // FDOT_VG2_M2ZZI_BtoH |
| 13996 | 10082840U, // FDOT_VG2_M2ZZI_BtoS |
| 13997 | 206862576U, // FDOT_VG2_M2ZZI_HtoS |
| 13998 | 121368U, // FDOT_VG2_M2ZZ_BtoH |
| 13999 | 121368U, // FDOT_VG2_M2ZZ_BtoS |
| 14000 | 106199280U, // FDOT_VG2_M2ZZ_HtoS |
| 14001 | 119321U, // FDOT_VG4_M4Z4Z_BtoH |
| 14002 | 119321U, // FDOT_VG4_M4Z4Z_BtoS |
| 14003 | 5273841U, // FDOT_VG4_M4Z4Z_HtoS |
| 14004 | 10082841U, // FDOT_VG4_M4ZZI_BtoH |
| 14005 | 10082841U, // FDOT_VG4_M4ZZI_BtoS |
| 14006 | 206862577U, // FDOT_VG4_M4ZZI_HtoS |
| 14007 | 121369U, // FDOT_VG4_M4ZZ_BtoH |
| 14008 | 121369U, // FDOT_VG4_M4ZZ_BtoS |
| 14009 | 106199281U, // FDOT_VG4_M4ZZ_HtoS |
| 14010 | 86296U, // FDOT_ZZZI_BtoH |
| 14011 | 86297U, // FDOT_ZZZI_BtoS |
| 14012 | 106455136U, // FDOT_ZZZI_S |
| 14013 | 4376U, // FDOT_ZZZ_BtoH |
| 14014 | 4377U, // FDOT_ZZZ_BtoS |
| 14015 | 24672U, // FDOT_ZZZ_S |
| 14016 | 10252464U, // FDOTlanev2f32 |
| 14017 | 10514608U, // FDOTlanev4f16 |
| 14018 | 5009576U, // FDOTlanev4f16_v2f32 |
| 14019 | 10252440U, // FDOTlanev4f32 |
| 14020 | 10514584U, // FDOTlanev8f16 |
| 14021 | 5009552U, // FDOTlanev8f16_v4f32 |
| 14022 | 2650288U, // FDOTv2f32 |
| 14023 | 2650288U, // FDOTv4f16 |
| 14024 | 2388136U, // FDOTv4f16_v2f32 |
| 14025 | 1863832U, // FDOTv4f32 |
| 14026 | 1863832U, // FDOTv8f16 |
| 14027 | 1077392U, // FDOTv8f16_v4f32 |
| 14028 | 2U, // FDUP_ZI_D |
| 14029 | 0U, // FDUP_ZI_H |
| 14030 | 2U, // FDUP_ZI_S |
| 14031 | 0U, // FEXPA_ZZ_D |
| 14032 | 1U, // FEXPA_ZZ_H |
| 14033 | 0U, // FEXPA_ZZ_S |
| 14034 | 8288U, // FIRSTP_XPP_B |
| 14035 | 10336U, // FIRSTP_XPP_D |
| 14036 | 22624U, // FIRSTP_XPP_H |
| 14037 | 12384U, // FIRSTP_XPP_S |
| 14038 | 0U, // FJCVTZS |
| 14039 | 2056U, // FLOGB_ZPmZ_D |
| 14040 | 4112U, // FLOGB_ZPmZ_H |
| 14041 | 6152U, // FLOGB_ZPmZ_S |
| 14042 | 10264U, // FLOGB_ZPzZ_D |
| 14043 | 4128U, // FLOGB_ZPzZ_H |
| 14044 | 12312U, // FLOGB_ZPzZ_S |
| 14045 | 276576U, // FMADDDrrr |
| 14046 | 276576U, // FMADDHrrr |
| 14047 | 276576U, // FMADDSrrr |
| 14048 | 604243976U, // FMAD_ZPmZZ_D |
| 14049 | 106985488U, // FMAD_ZPmZZ_H |
| 14050 | 637802504U, // FMAD_ZPmZZ_S |
| 14051 | 14432U, // FMAXDrr |
| 14052 | 14432U, // FMAXHrr |
| 14053 | 14432U, // FMAXNMDrr |
| 14054 | 14432U, // FMAXNMHrr |
| 14055 | 67381256U, // FMAXNMP_ZPmZZ_D |
| 14056 | 102266912U, // FMAXNMP_ZPmZZ_H |
| 14057 | 134492168U, // FMAXNMP_ZPmZZ_S |
| 14058 | 2123936U, // FMAXNMPv2f32 |
| 14059 | 551040U, // FMAXNMPv2f64 |
| 14060 | 448U, // FMAXNMPv2i16p |
| 14061 | 48U, // FMAXNMPv2i32p |
| 14062 | 56U, // FMAXNMPv2i64p |
| 14063 | 2386088U, // FMAXNMPv4f16 |
| 14064 | 813192U, // FMAXNMPv4f32 |
| 14065 | 1075344U, // FMAXNMPv8f16 |
| 14066 | 10336U, // FMAXNMQV_D |
| 14067 | 22624U, // FMAXNMQV_H |
| 14068 | 12384U, // FMAXNMQV_S |
| 14069 | 14432U, // FMAXNMSrr |
| 14070 | 1U, // FMAXNMV_VPZ_D |
| 14071 | 1U, // FMAXNMV_VPZ_H |
| 14072 | 1U, // FMAXNMV_VPZ_S |
| 14073 | 64U, // FMAXNMVv4i16v |
| 14074 | 72U, // FMAXNMVv4i32v |
| 14075 | 80U, // FMAXNMVv8i16v |
| 14076 | 4552U, // FMAXNM_VG2_2Z2Z_D |
| 14077 | 4344U, // FMAXNM_VG2_2Z2Z_H |
| 14078 | 4560U, // FMAXNM_VG2_2Z2Z_S |
| 14079 | 4288U, // FMAXNM_VG2_2ZZ_D |
| 14080 | 4128U, // FMAXNM_VG2_2ZZ_H |
| 14081 | 4208U, // FMAXNM_VG2_2ZZ_S |
| 14082 | 4552U, // FMAXNM_VG4_4Z4Z_D |
| 14083 | 4344U, // FMAXNM_VG4_4Z4Z_H |
| 14084 | 4560U, // FMAXNM_VG4_4Z4Z_S |
| 14085 | 4288U, // FMAXNM_VG4_4ZZ_D |
| 14086 | 4128U, // FMAXNM_VG4_4ZZ_H |
| 14087 | 4208U, // FMAXNM_VG4_4ZZ_S |
| 14088 | 671361032U, // FMAXNM_ZPmI_D |
| 14089 | 10778656U, // FMAXNM_ZPmI_H |
| 14090 | 671363080U, // FMAXNM_ZPmI_S |
| 14091 | 67381256U, // FMAXNM_ZPmZ_D |
| 14092 | 102266912U, // FMAXNM_ZPmZ_H |
| 14093 | 134492168U, // FMAXNM_ZPmZ_S |
| 14094 | 2123936U, // FMAXNMv2f32 |
| 14095 | 551040U, // FMAXNMv2f64 |
| 14096 | 2386088U, // FMAXNMv4f16 |
| 14097 | 813192U, // FMAXNMv4f32 |
| 14098 | 1075344U, // FMAXNMv8f16 |
| 14099 | 67381256U, // FMAXP_ZPmZZ_D |
| 14100 | 102266912U, // FMAXP_ZPmZZ_H |
| 14101 | 134492168U, // FMAXP_ZPmZZ_S |
| 14102 | 2123936U, // FMAXPv2f32 |
| 14103 | 551040U, // FMAXPv2f64 |
| 14104 | 448U, // FMAXPv2i16p |
| 14105 | 48U, // FMAXPv2i32p |
| 14106 | 56U, // FMAXPv2i64p |
| 14107 | 2386088U, // FMAXPv4f16 |
| 14108 | 813192U, // FMAXPv4f32 |
| 14109 | 1075344U, // FMAXPv8f16 |
| 14110 | 10336U, // FMAXQV_D |
| 14111 | 22624U, // FMAXQV_H |
| 14112 | 12384U, // FMAXQV_S |
| 14113 | 14432U, // FMAXSrr |
| 14114 | 1U, // FMAXV_VPZ_D |
| 14115 | 1U, // FMAXV_VPZ_H |
| 14116 | 1U, // FMAXV_VPZ_S |
| 14117 | 64U, // FMAXVv4i16v |
| 14118 | 72U, // FMAXVv4i32v |
| 14119 | 80U, // FMAXVv8i16v |
| 14120 | 4552U, // FMAX_VG2_2Z2Z_D |
| 14121 | 4344U, // FMAX_VG2_2Z2Z_H |
| 14122 | 4560U, // FMAX_VG2_2Z2Z_S |
| 14123 | 4288U, // FMAX_VG2_2ZZ_D |
| 14124 | 4128U, // FMAX_VG2_2ZZ_H |
| 14125 | 4208U, // FMAX_VG2_2ZZ_S |
| 14126 | 4552U, // FMAX_VG4_4Z4Z_D |
| 14127 | 4344U, // FMAX_VG4_4Z4Z_H |
| 14128 | 4560U, // FMAX_VG4_4Z4Z_S |
| 14129 | 4288U, // FMAX_VG4_4ZZ_D |
| 14130 | 4128U, // FMAX_VG4_4ZZ_H |
| 14131 | 4208U, // FMAX_VG4_4ZZ_S |
| 14132 | 671361032U, // FMAX_ZPmI_D |
| 14133 | 10778656U, // FMAX_ZPmI_H |
| 14134 | 671363080U, // FMAX_ZPmI_S |
| 14135 | 67381256U, // FMAX_ZPmZ_D |
| 14136 | 102266912U, // FMAX_ZPmZ_H |
| 14137 | 134492168U, // FMAX_ZPmZ_S |
| 14138 | 2123936U, // FMAXv2f32 |
| 14139 | 551040U, // FMAXv2f64 |
| 14140 | 2386088U, // FMAXv4f16 |
| 14141 | 813192U, // FMAXv4f32 |
| 14142 | 1075344U, // FMAXv8f16 |
| 14143 | 14432U, // FMINDrr |
| 14144 | 14432U, // FMINHrr |
| 14145 | 14432U, // FMINNMDrr |
| 14146 | 14432U, // FMINNMHrr |
| 14147 | 67381256U, // FMINNMP_ZPmZZ_D |
| 14148 | 102266912U, // FMINNMP_ZPmZZ_H |
| 14149 | 134492168U, // FMINNMP_ZPmZZ_S |
| 14150 | 2123936U, // FMINNMPv2f32 |
| 14151 | 551040U, // FMINNMPv2f64 |
| 14152 | 448U, // FMINNMPv2i16p |
| 14153 | 48U, // FMINNMPv2i32p |
| 14154 | 56U, // FMINNMPv2i64p |
| 14155 | 2386088U, // FMINNMPv4f16 |
| 14156 | 813192U, // FMINNMPv4f32 |
| 14157 | 1075344U, // FMINNMPv8f16 |
| 14158 | 10336U, // FMINNMQV_D |
| 14159 | 22624U, // FMINNMQV_H |
| 14160 | 12384U, // FMINNMQV_S |
| 14161 | 14432U, // FMINNMSrr |
| 14162 | 1U, // FMINNMV_VPZ_D |
| 14163 | 1U, // FMINNMV_VPZ_H |
| 14164 | 1U, // FMINNMV_VPZ_S |
| 14165 | 64U, // FMINNMVv4i16v |
| 14166 | 72U, // FMINNMVv4i32v |
| 14167 | 80U, // FMINNMVv8i16v |
| 14168 | 4552U, // FMINNM_VG2_2Z2Z_D |
| 14169 | 4344U, // FMINNM_VG2_2Z2Z_H |
| 14170 | 4560U, // FMINNM_VG2_2Z2Z_S |
| 14171 | 4288U, // FMINNM_VG2_2ZZ_D |
| 14172 | 4128U, // FMINNM_VG2_2ZZ_H |
| 14173 | 4208U, // FMINNM_VG2_2ZZ_S |
| 14174 | 4552U, // FMINNM_VG4_4Z4Z_D |
| 14175 | 4344U, // FMINNM_VG4_4Z4Z_H |
| 14176 | 4560U, // FMINNM_VG4_4Z4Z_S |
| 14177 | 4288U, // FMINNM_VG4_4ZZ_D |
| 14178 | 4128U, // FMINNM_VG4_4ZZ_H |
| 14179 | 4208U, // FMINNM_VG4_4ZZ_S |
| 14180 | 671361032U, // FMINNM_ZPmI_D |
| 14181 | 10778656U, // FMINNM_ZPmI_H |
| 14182 | 671363080U, // FMINNM_ZPmI_S |
| 14183 | 67381256U, // FMINNM_ZPmZ_D |
| 14184 | 102266912U, // FMINNM_ZPmZ_H |
| 14185 | 134492168U, // FMINNM_ZPmZ_S |
| 14186 | 2123936U, // FMINNMv2f32 |
| 14187 | 551040U, // FMINNMv2f64 |
| 14188 | 2386088U, // FMINNMv4f16 |
| 14189 | 813192U, // FMINNMv4f32 |
| 14190 | 1075344U, // FMINNMv8f16 |
| 14191 | 67381256U, // FMINP_ZPmZZ_D |
| 14192 | 102266912U, // FMINP_ZPmZZ_H |
| 14193 | 134492168U, // FMINP_ZPmZZ_S |
| 14194 | 2123936U, // FMINPv2f32 |
| 14195 | 551040U, // FMINPv2f64 |
| 14196 | 448U, // FMINPv2i16p |
| 14197 | 48U, // FMINPv2i32p |
| 14198 | 56U, // FMINPv2i64p |
| 14199 | 2386088U, // FMINPv4f16 |
| 14200 | 813192U, // FMINPv4f32 |
| 14201 | 1075344U, // FMINPv8f16 |
| 14202 | 10336U, // FMINQV_D |
| 14203 | 22624U, // FMINQV_H |
| 14204 | 12384U, // FMINQV_S |
| 14205 | 14432U, // FMINSrr |
| 14206 | 1U, // FMINV_VPZ_D |
| 14207 | 1U, // FMINV_VPZ_H |
| 14208 | 1U, // FMINV_VPZ_S |
| 14209 | 64U, // FMINVv4i16v |
| 14210 | 72U, // FMINVv4i32v |
| 14211 | 80U, // FMINVv8i16v |
| 14212 | 4552U, // FMIN_VG2_2Z2Z_D |
| 14213 | 4344U, // FMIN_VG2_2Z2Z_H |
| 14214 | 4560U, // FMIN_VG2_2Z2Z_S |
| 14215 | 4288U, // FMIN_VG2_2ZZ_D |
| 14216 | 4128U, // FMIN_VG2_2ZZ_H |
| 14217 | 4208U, // FMIN_VG2_2ZZ_S |
| 14218 | 4552U, // FMIN_VG4_4Z4Z_D |
| 14219 | 4344U, // FMIN_VG4_4Z4Z_H |
| 14220 | 4560U, // FMIN_VG4_4Z4Z_S |
| 14221 | 4288U, // FMIN_VG4_4ZZ_D |
| 14222 | 4128U, // FMIN_VG4_4ZZ_H |
| 14223 | 4208U, // FMIN_VG4_4ZZ_S |
| 14224 | 671361032U, // FMIN_ZPmI_D |
| 14225 | 10778656U, // FMIN_ZPmI_H |
| 14226 | 671363080U, // FMIN_ZPmI_S |
| 14227 | 67381256U, // FMIN_ZPmZ_D |
| 14228 | 102266912U, // FMIN_ZPmZ_H |
| 14229 | 134492168U, // FMIN_ZPmZ_S |
| 14230 | 2123936U, // FMINv2f32 |
| 14231 | 551040U, // FMINv2f64 |
| 14232 | 2386088U, // FMINv4f16 |
| 14233 | 813192U, // FMINv4f32 |
| 14234 | 1075344U, // FMINv8f16 |
| 14235 | 123424U, // FMLAL2lanev4f16 |
| 14236 | 240939176U, // FMLAL2lanev8f16 |
| 14237 | 125472U, // FMLAL2v4f16 |
| 14238 | 2388136U, // FMLAL2v8f16 |
| 14239 | 4376U, // FMLALB_ZZZ |
| 14240 | 86296U, // FMLALB_ZZZI |
| 14241 | 106455136U, // FMLALB_ZZZI_SHH |
| 14242 | 24672U, // FMLALB_ZZZ_SHH |
| 14243 | 11038872U, // FMLALBlanev8f16 |
| 14244 | 1863832U, // FMLALBv16i8_v8f16 |
| 14245 | 4377U, // FMLALLBB_ZZZ |
| 14246 | 86297U, // FMLALLBB_ZZZI |
| 14247 | 11038872U, // FMLALLBBlanev4f32 |
| 14248 | 1863832U, // FMLALLBBv4f32 |
| 14249 | 4377U, // FMLALLBT_ZZZ |
| 14250 | 86297U, // FMLALLBT_ZZZI |
| 14251 | 11038872U, // FMLALLBTlanev4f32 |
| 14252 | 1863832U, // FMLALLBTv4f32 |
| 14253 | 4377U, // FMLALLTB_ZZZ |
| 14254 | 86297U, // FMLALLTB_ZZZI |
| 14255 | 11038872U, // FMLALLTBlanev4f32 |
| 14256 | 1863832U, // FMLALLTBv4f32 |
| 14257 | 4377U, // FMLALLTT_ZZZ |
| 14258 | 86297U, // FMLALLTT_ZZZI |
| 14259 | 11038872U, // FMLALLTTlanev4f32 |
| 14260 | 1863832U, // FMLALLTTv4f32 |
| 14261 | 84521U, // FMLALL_MZZI_BtoS |
| 14262 | 4649U, // FMLALL_MZZ_BtoS |
| 14263 | 119320U, // FMLALL_VG2_M2Z2Z_BtoS |
| 14264 | 10082840U, // FMLALL_VG2_M2ZZI_BtoS |
| 14265 | 121370U, // FMLALL_VG2_M2ZZ_BtoS |
| 14266 | 119321U, // FMLALL_VG4_M4Z4Z_BtoS |
| 14267 | 10082841U, // FMLALL_VG4_M4ZZI_BtoS |
| 14268 | 121370U, // FMLALL_VG4_M4ZZ_BtoS |
| 14269 | 4376U, // FMLALT_ZZZ |
| 14270 | 86296U, // FMLALT_ZZZI |
| 14271 | 106455136U, // FMLALT_ZZZI_SHH |
| 14272 | 24672U, // FMLALT_ZZZ_SHH |
| 14273 | 11038872U, // FMLALTlanev8f16 |
| 14274 | 1863832U, // FMLALTv16i8_v8f16 |
| 14275 | 84521U, // FMLAL_MZZI_BtoH |
| 14276 | 84225U, // FMLAL_MZZI_HtoS |
| 14277 | 4353U, // FMLAL_MZZ_HtoS |
| 14278 | 119320U, // FMLAL_VG2_M2Z2Z_BtoH |
| 14279 | 5273840U, // FMLAL_VG2_M2Z2Z_HtoS |
| 14280 | 10082840U, // FMLAL_VG2_M2ZZI_BtoH |
| 14281 | 206862576U, // FMLAL_VG2_M2ZZI_HtoS |
| 14282 | 121368U, // FMLAL_VG2_M2ZZ_BtoH |
| 14283 | 106199280U, // FMLAL_VG2_M2ZZ_HtoS |
| 14284 | 4649U, // FMLAL_VG2_MZZ_BtoH |
| 14285 | 119321U, // FMLAL_VG4_M4Z4Z_BtoH |
| 14286 | 5273841U, // FMLAL_VG4_M4Z4Z_HtoS |
| 14287 | 10082841U, // FMLAL_VG4_M4ZZI_BtoH |
| 14288 | 206862577U, // FMLAL_VG4_M4ZZI_HtoS |
| 14289 | 121369U, // FMLAL_VG4_M4ZZ_BtoH |
| 14290 | 106199281U, // FMLAL_VG4_M4ZZ_HtoS |
| 14291 | 123424U, // FMLALlanev4f16 |
| 14292 | 240939176U, // FMLALlanev8f16 |
| 14293 | 125472U, // FMLALv4f16 |
| 14294 | 2388136U, // FMLALv8f16 |
| 14295 | 3176648U, // FMLA_VG2_M2Z2Z_D |
| 14296 | 5273840U, // FMLA_VG2_M2Z2Z_H |
| 14297 | 3438800U, // FMLA_VG2_M2Z2Z_S |
| 14298 | 205027528U, // FMLA_VG2_M2ZZI_D |
| 14299 | 206862576U, // FMLA_VG2_M2ZZI_H |
| 14300 | 205289680U, // FMLA_VG2_M2ZZI_S |
| 14301 | 104364232U, // FMLA_VG2_M2ZZ_D |
| 14302 | 106199280U, // FMLA_VG2_M2ZZ_H |
| 14303 | 104626384U, // FMLA_VG2_M2ZZ_S |
| 14304 | 3176649U, // FMLA_VG4_M4Z4Z_D |
| 14305 | 5273841U, // FMLA_VG4_M4Z4Z_H |
| 14306 | 3438801U, // FMLA_VG4_M4Z4Z_S |
| 14307 | 205027529U, // FMLA_VG4_M4ZZI_D |
| 14308 | 206862577U, // FMLA_VG4_M4ZZI_H |
| 14309 | 205289681U, // FMLA_VG4_M4ZZI_S |
| 14310 | 104364233U, // FMLA_VG4_M4ZZ_D |
| 14311 | 106199281U, // FMLA_VG4_M4ZZ_H |
| 14312 | 104626385U, // FMLA_VG4_M4ZZ_S |
| 14313 | 604243976U, // FMLA_ZPmZZ_D |
| 14314 | 106985488U, // FMLA_ZPmZZ_H |
| 14315 | 637802504U, // FMLA_ZPmZZ_S |
| 14316 | 106432608U, // FMLA_ZZZI_D |
| 14317 | 86032U, // FMLA_ZZZI_H |
| 14318 | 106436704U, // FMLA_ZZZI_S |
| 14319 | 240939105U, // FMLAv1i16_indexed |
| 14320 | 244609121U, // FMLAv1i32_indexed |
| 14321 | 246181985U, // FMLAv1i64_indexed |
| 14322 | 2125984U, // FMLAv2f32 |
| 14323 | 553088U, // FMLAv2f64 |
| 14324 | 244609184U, // FMLAv2i32_indexed |
| 14325 | 246182016U, // FMLAv2i64_indexed |
| 14326 | 2388136U, // FMLAv4f16 |
| 14327 | 815240U, // FMLAv4f32 |
| 14328 | 240939176U, // FMLAv4i16_indexed |
| 14329 | 244609160U, // FMLAv4i32_indexed |
| 14330 | 1077392U, // FMLAv8f16 |
| 14331 | 240939152U, // FMLAv8i16_indexed |
| 14332 | 24672U, // FMLLA_ZZZ_HtoS |
| 14333 | 123424U, // FMLSL2lanev4f16 |
| 14334 | 240939176U, // FMLSL2lanev8f16 |
| 14335 | 125472U, // FMLSL2v4f16 |
| 14336 | 2388136U, // FMLSL2v8f16 |
| 14337 | 106455136U, // FMLSLB_ZZZI_SHH |
| 14338 | 24672U, // FMLSLB_ZZZ_SHH |
| 14339 | 106455136U, // FMLSLT_ZZZI_SHH |
| 14340 | 24672U, // FMLSLT_ZZZ_SHH |
| 14341 | 84225U, // FMLSL_MZZI_HtoS |
| 14342 | 4353U, // FMLSL_MZZ_HtoS |
| 14343 | 5273840U, // FMLSL_VG2_M2Z2Z_HtoS |
| 14344 | 206862576U, // FMLSL_VG2_M2ZZI_HtoS |
| 14345 | 106199280U, // FMLSL_VG2_M2ZZ_HtoS |
| 14346 | 5273841U, // FMLSL_VG4_M4Z4Z_HtoS |
| 14347 | 206862577U, // FMLSL_VG4_M4ZZI_HtoS |
| 14348 | 106199281U, // FMLSL_VG4_M4ZZ_HtoS |
| 14349 | 123424U, // FMLSLlanev4f16 |
| 14350 | 240939176U, // FMLSLlanev8f16 |
| 14351 | 125472U, // FMLSLv4f16 |
| 14352 | 2388136U, // FMLSLv8f16 |
| 14353 | 3176648U, // FMLS_VG2_M2Z2Z_D |
| 14354 | 5273840U, // FMLS_VG2_M2Z2Z_H |
| 14355 | 3438800U, // FMLS_VG2_M2Z2Z_S |
| 14356 | 205027528U, // FMLS_VG2_M2ZZI_D |
| 14357 | 206862576U, // FMLS_VG2_M2ZZI_H |
| 14358 | 205289680U, // FMLS_VG2_M2ZZI_S |
| 14359 | 104364232U, // FMLS_VG2_M2ZZ_D |
| 14360 | 106199280U, // FMLS_VG2_M2ZZ_H |
| 14361 | 104626384U, // FMLS_VG2_M2ZZ_S |
| 14362 | 3176649U, // FMLS_VG4_M4Z4Z_D |
| 14363 | 5273841U, // FMLS_VG4_M4Z4Z_H |
| 14364 | 3438801U, // FMLS_VG4_M4Z4Z_S |
| 14365 | 205027529U, // FMLS_VG4_M4ZZI_D |
| 14366 | 206862577U, // FMLS_VG4_M4ZZI_H |
| 14367 | 205289681U, // FMLS_VG4_M4ZZI_S |
| 14368 | 104364233U, // FMLS_VG4_M4ZZ_D |
| 14369 | 106199281U, // FMLS_VG4_M4ZZ_H |
| 14370 | 104626385U, // FMLS_VG4_M4ZZ_S |
| 14371 | 604243976U, // FMLS_ZPmZZ_D |
| 14372 | 106985488U, // FMLS_ZPmZZ_H |
| 14373 | 637802504U, // FMLS_ZPmZZ_S |
| 14374 | 106432608U, // FMLS_ZZZI_D |
| 14375 | 86032U, // FMLS_ZZZI_H |
| 14376 | 106436704U, // FMLS_ZZZI_S |
| 14377 | 240939105U, // FMLSv1i16_indexed |
| 14378 | 244609121U, // FMLSv1i32_indexed |
| 14379 | 246181985U, // FMLSv1i64_indexed |
| 14380 | 2125984U, // FMLSv2f32 |
| 14381 | 553088U, // FMLSv2f64 |
| 14382 | 244609184U, // FMLSv2i32_indexed |
| 14383 | 246182016U, // FMLSv2i64_indexed |
| 14384 | 2388136U, // FMLSv4f16 |
| 14385 | 815240U, // FMLSv4f32 |
| 14386 | 240939176U, // FMLSv4i16_indexed |
| 14387 | 244609160U, // FMLSv4i32_indexed |
| 14388 | 1077392U, // FMLSv8f16 |
| 14389 | 240939152U, // FMLSv8i16_indexed |
| 14390 | 4376U, // FMMLA_ZZZ_BtoH |
| 14391 | 4377U, // FMMLA_ZZZ_BtoS |
| 14392 | 2144U, // FMMLA_ZZZ_D |
| 14393 | 4112U, // FMMLA_ZZZ_H |
| 14394 | 6240U, // FMMLA_ZZZ_S |
| 14395 | 1863832U, // FMMLAv4f32 |
| 14396 | 1863832U, // FMMLAv8f16 |
| 14397 | 1077392U, // FMMLAv8f16_v4f32 |
| 14398 | 1077392U, // FMMLAv8f16_v8f16 |
| 14399 | 2U, // FMOP4A_M2Z2Z_BtoH |
| 14400 | 2U, // FMOP4A_M2Z2Z_BtoS |
| 14401 | 2U, // FMOP4A_M2Z2Z_D |
| 14402 | 1U, // FMOP4A_M2Z2Z_H |
| 14403 | 1U, // FMOP4A_M2Z2Z_HtoS |
| 14404 | 2U, // FMOP4A_M2Z2Z_S |
| 14405 | 3U, // FMOP4A_M2ZZ_BtoH |
| 14406 | 3U, // FMOP4A_M2ZZ_BtoS |
| 14407 | 3U, // FMOP4A_M2ZZ_D |
| 14408 | 1U, // FMOP4A_M2ZZ_H |
| 14409 | 1U, // FMOP4A_M2ZZ_HtoS |
| 14410 | 3U, // FMOP4A_M2ZZ_S |
| 14411 | 560U, // FMOP4A_MZ2Z_BtoH |
| 14412 | 560U, // FMOP4A_MZ2Z_BtoS |
| 14413 | 568U, // FMOP4A_MZ2Z_D |
| 14414 | 264U, // FMOP4A_MZ2Z_H |
| 14415 | 264U, // FMOP4A_MZ2Z_HtoS |
| 14416 | 576U, // FMOP4A_MZ2Z_S |
| 14417 | 4376U, // FMOP4A_MZZ_BtoH |
| 14418 | 4376U, // FMOP4A_MZZ_BtoS |
| 14419 | 472U, // FMOP4A_MZZ_D |
| 14420 | 4112U, // FMOP4A_MZZ_H |
| 14421 | 4112U, // FMOP4A_MZZ_HtoS |
| 14422 | 120U, // FMOP4A_MZZ_S |
| 14423 | 2U, // FMOP4S_M2Z2Z_D |
| 14424 | 1U, // FMOP4S_M2Z2Z_H |
| 14425 | 1U, // FMOP4S_M2Z2Z_HtoS |
| 14426 | 2U, // FMOP4S_M2Z2Z_S |
| 14427 | 3U, // FMOP4S_M2ZZ_D |
| 14428 | 1U, // FMOP4S_M2ZZ_H |
| 14429 | 1U, // FMOP4S_M2ZZ_HtoS |
| 14430 | 3U, // FMOP4S_M2ZZ_S |
| 14431 | 568U, // FMOP4S_MZ2Z_D |
| 14432 | 264U, // FMOP4S_MZ2Z_H |
| 14433 | 264U, // FMOP4S_MZ2Z_HtoS |
| 14434 | 576U, // FMOP4S_MZ2Z_S |
| 14435 | 472U, // FMOP4S_MZZ_D |
| 14436 | 4112U, // FMOP4S_MZZ_H |
| 14437 | 4112U, // FMOP4S_MZZ_HtoS |
| 14438 | 120U, // FMOP4S_MZZ_S |
| 14439 | 88168U, // FMOPAL_MPPZZ |
| 14440 | 127080U, // FMOPA_MPPZZ_BtoH |
| 14441 | 127080U, // FMOPA_MPPZZ_BtoS |
| 14442 | 704923752U, // FMOPA_MPPZZ_D |
| 14443 | 88168U, // FMOPA_MPPZZ_H |
| 14444 | 302272616U, // FMOPA_MPPZZ_S |
| 14445 | 88168U, // FMOPSL_MPPZZ |
| 14446 | 704923752U, // FMOPS_MPPZZ_D |
| 14447 | 88168U, // FMOPS_MPPZZ_H |
| 14448 | 302272616U, // FMOPS_MPPZZ_S |
| 14449 | 108952U, // FMOVDXHighr |
| 14450 | 0U, // FMOVDXr |
| 14451 | 2U, // FMOVDi |
| 14452 | 0U, // FMOVDr |
| 14453 | 0U, // FMOVHWr |
| 14454 | 0U, // FMOVHXr |
| 14455 | 2U, // FMOVHi |
| 14456 | 0U, // FMOVHr |
| 14457 | 0U, // FMOVSWr |
| 14458 | 2U, // FMOVSi |
| 14459 | 0U, // FMOVSr |
| 14460 | 0U, // FMOVWHr |
| 14461 | 0U, // FMOVWSr |
| 14462 | 0U, // FMOVXDHighr |
| 14463 | 0U, // FMOVXDr |
| 14464 | 0U, // FMOVXHr |
| 14465 | 2U, // FMOVv2f32_ns |
| 14466 | 2U, // FMOVv2f64_ns |
| 14467 | 2U, // FMOVv4f16_ns |
| 14468 | 2U, // FMOVv4f32_ns |
| 14469 | 2U, // FMOVv8f16_ns |
| 14470 | 604243976U, // FMSB_ZPmZZ_D |
| 14471 | 106985488U, // FMSB_ZPmZZ_H |
| 14472 | 637802504U, // FMSB_ZPmZZ_S |
| 14473 | 276576U, // FMSUBDrrr |
| 14474 | 276576U, // FMSUBHrrr |
| 14475 | 276576U, // FMSUBSrrr |
| 14476 | 14432U, // FMULDrr |
| 14477 | 14432U, // FMULHrr |
| 14478 | 14432U, // FMULSrr |
| 14479 | 14432U, // FMULX16 |
| 14480 | 14432U, // FMULX32 |
| 14481 | 14432U, // FMULX64 |
| 14482 | 67381256U, // FMULX_ZPmZ_D |
| 14483 | 102266912U, // FMULX_ZPmZ_H |
| 14484 | 134492168U, // FMULX_ZPmZ_S |
| 14485 | 744253536U, // FMULXv1i16_indexed |
| 14486 | 747923552U, // FMULXv1i32_indexed |
| 14487 | 749496416U, // FMULXv1i64_indexed |
| 14488 | 2123936U, // FMULXv2f32 |
| 14489 | 551040U, // FMULXv2f64 |
| 14490 | 747923616U, // FMULXv2i32_indexed |
| 14491 | 749496448U, // FMULXv2i64_indexed |
| 14492 | 2386088U, // FMULXv4f16 |
| 14493 | 813192U, // FMULXv4f32 |
| 14494 | 744253608U, // FMULXv4i16_indexed |
| 14495 | 747923592U, // FMULXv4i32_indexed |
| 14496 | 1075344U, // FMULXv8f16 |
| 14497 | 744253584U, // FMULXv8i16_indexed |
| 14498 | 4552U, // FMUL_2Z2Z_D |
| 14499 | 4344U, // FMUL_2Z2Z_H |
| 14500 | 4560U, // FMUL_2Z2Z_S |
| 14501 | 4288U, // FMUL_2ZZ_D |
| 14502 | 4128U, // FMUL_2ZZ_H |
| 14503 | 4208U, // FMUL_2ZZ_S |
| 14504 | 4552U, // FMUL_4Z4Z_D |
| 14505 | 4344U, // FMUL_4Z4Z_H |
| 14506 | 4560U, // FMUL_4Z4Z_S |
| 14507 | 4288U, // FMUL_4ZZ_D |
| 14508 | 4128U, // FMUL_4ZZ_H |
| 14509 | 4208U, // FMUL_4ZZ_S |
| 14510 | 772024328U, // FMUL_ZPmI_D |
| 14511 | 11565088U, // FMUL_ZPmI_H |
| 14512 | 772026376U, // FMUL_ZPmI_S |
| 14513 | 67381256U, // FMUL_ZPmZ_D |
| 14514 | 102266912U, // FMUL_ZPmZ_H |
| 14515 | 134492168U, // FMUL_ZPmZ_S |
| 14516 | 11806816U, // FMUL_ZZZI_D |
| 14517 | 77856U, // FMUL_ZZZI_H |
| 14518 | 11808864U, // FMUL_ZZZI_S |
| 14519 | 10336U, // FMUL_ZZZ_D |
| 14520 | 4128U, // FMUL_ZZZ_H |
| 14521 | 12384U, // FMUL_ZZZ_S |
| 14522 | 744253536U, // FMULv1i16_indexed |
| 14523 | 747923552U, // FMULv1i32_indexed |
| 14524 | 749496416U, // FMULv1i64_indexed |
| 14525 | 2123936U, // FMULv2f32 |
| 14526 | 551040U, // FMULv2f64 |
| 14527 | 747923616U, // FMULv2i32_indexed |
| 14528 | 749496448U, // FMULv2i64_indexed |
| 14529 | 2386088U, // FMULv4f16 |
| 14530 | 813192U, // FMULv4f32 |
| 14531 | 744253608U, // FMULv4i16_indexed |
| 14532 | 747923592U, // FMULv4i32_indexed |
| 14533 | 1075344U, // FMULv8f16 |
| 14534 | 744253584U, // FMULv8i16_indexed |
| 14535 | 0U, // FNEGDr |
| 14536 | 0U, // FNEGHr |
| 14537 | 0U, // FNEGSr |
| 14538 | 2056U, // FNEG_ZPmZ_D |
| 14539 | 4112U, // FNEG_ZPmZ_H |
| 14540 | 6152U, // FNEG_ZPmZ_S |
| 14541 | 10264U, // FNEG_ZPzZ_D |
| 14542 | 4128U, // FNEG_ZPzZ_H |
| 14543 | 12312U, // FNEG_ZPzZ_S |
| 14544 | 48U, // FNEGv2f32 |
| 14545 | 56U, // FNEGv2f64 |
| 14546 | 64U, // FNEGv4f16 |
| 14547 | 72U, // FNEGv4f32 |
| 14548 | 80U, // FNEGv8f16 |
| 14549 | 276576U, // FNMADDDrrr |
| 14550 | 276576U, // FNMADDHrrr |
| 14551 | 276576U, // FNMADDSrrr |
| 14552 | 604243976U, // FNMAD_ZPmZZ_D |
| 14553 | 106985488U, // FNMAD_ZPmZZ_H |
| 14554 | 637802504U, // FNMAD_ZPmZZ_S |
| 14555 | 604243976U, // FNMLA_ZPmZZ_D |
| 14556 | 106985488U, // FNMLA_ZPmZZ_H |
| 14557 | 637802504U, // FNMLA_ZPmZZ_S |
| 14558 | 604243976U, // FNMLS_ZPmZZ_D |
| 14559 | 106985488U, // FNMLS_ZPmZZ_H |
| 14560 | 637802504U, // FNMLS_ZPmZZ_S |
| 14561 | 604243976U, // FNMSB_ZPmZZ_D |
| 14562 | 106985488U, // FNMSB_ZPmZZ_H |
| 14563 | 637802504U, // FNMSB_ZPmZZ_S |
| 14564 | 276576U, // FNMSUBDrrr |
| 14565 | 276576U, // FNMSUBHrrr |
| 14566 | 276576U, // FNMSUBSrrr |
| 14567 | 14432U, // FNMULDrr |
| 14568 | 14432U, // FNMULHrr |
| 14569 | 14432U, // FNMULSrr |
| 14570 | 0U, // FRECPE_ZZ_D |
| 14571 | 1U, // FRECPE_ZZ_H |
| 14572 | 0U, // FRECPE_ZZ_S |
| 14573 | 0U, // FRECPEv1f16 |
| 14574 | 0U, // FRECPEv1i32 |
| 14575 | 0U, // FRECPEv1i64 |
| 14576 | 48U, // FRECPEv2f32 |
| 14577 | 56U, // FRECPEv2f64 |
| 14578 | 64U, // FRECPEv4f16 |
| 14579 | 72U, // FRECPEv4f32 |
| 14580 | 80U, // FRECPEv8f16 |
| 14581 | 14432U, // FRECPS16 |
| 14582 | 14432U, // FRECPS32 |
| 14583 | 14432U, // FRECPS64 |
| 14584 | 10336U, // FRECPS_ZZZ_D |
| 14585 | 4128U, // FRECPS_ZZZ_H |
| 14586 | 12384U, // FRECPS_ZZZ_S |
| 14587 | 2123936U, // FRECPSv2f32 |
| 14588 | 551040U, // FRECPSv2f64 |
| 14589 | 2386088U, // FRECPSv4f16 |
| 14590 | 813192U, // FRECPSv4f32 |
| 14591 | 1075344U, // FRECPSv8f16 |
| 14592 | 2056U, // FRECPX_ZPmZ_D |
| 14593 | 4112U, // FRECPX_ZPmZ_H |
| 14594 | 6152U, // FRECPX_ZPmZ_S |
| 14595 | 10264U, // FRECPX_ZPzZ_D |
| 14596 | 4128U, // FRECPX_ZPzZ_H |
| 14597 | 12312U, // FRECPX_ZPzZ_S |
| 14598 | 0U, // FRECPXv1f16 |
| 14599 | 0U, // FRECPXv1i32 |
| 14600 | 0U, // FRECPXv1i64 |
| 14601 | 0U, // FRINT32XDr |
| 14602 | 0U, // FRINT32XSr |
| 14603 | 2056U, // FRINT32X_ZPmZ_D |
| 14604 | 6152U, // FRINT32X_ZPmZ_S |
| 14605 | 10264U, // FRINT32X_ZPzZ_D |
| 14606 | 12312U, // FRINT32X_ZPzZ_S |
| 14607 | 48U, // FRINT32Xv2f32 |
| 14608 | 56U, // FRINT32Xv2f64 |
| 14609 | 72U, // FRINT32Xv4f32 |
| 14610 | 0U, // FRINT32ZDr |
| 14611 | 0U, // FRINT32ZSr |
| 14612 | 2056U, // FRINT32Z_ZPmZ_D |
| 14613 | 6152U, // FRINT32Z_ZPmZ_S |
| 14614 | 10264U, // FRINT32Z_ZPzZ_D |
| 14615 | 12312U, // FRINT32Z_ZPzZ_S |
| 14616 | 48U, // FRINT32Zv2f32 |
| 14617 | 56U, // FRINT32Zv2f64 |
| 14618 | 72U, // FRINT32Zv4f32 |
| 14619 | 0U, // FRINT64XDr |
| 14620 | 0U, // FRINT64XSr |
| 14621 | 2056U, // FRINT64X_ZPmZ_D |
| 14622 | 6152U, // FRINT64X_ZPmZ_S |
| 14623 | 10264U, // FRINT64X_ZPzZ_D |
| 14624 | 12312U, // FRINT64X_ZPzZ_S |
| 14625 | 48U, // FRINT64Xv2f32 |
| 14626 | 56U, // FRINT64Xv2f64 |
| 14627 | 72U, // FRINT64Xv4f32 |
| 14628 | 0U, // FRINT64ZDr |
| 14629 | 0U, // FRINT64ZSr |
| 14630 | 2056U, // FRINT64Z_ZPmZ_D |
| 14631 | 6152U, // FRINT64Z_ZPmZ_S |
| 14632 | 10264U, // FRINT64Z_ZPzZ_D |
| 14633 | 12312U, // FRINT64Z_ZPzZ_S |
| 14634 | 48U, // FRINT64Zv2f32 |
| 14635 | 56U, // FRINT64Zv2f64 |
| 14636 | 72U, // FRINT64Zv4f32 |
| 14637 | 0U, // FRINTADr |
| 14638 | 0U, // FRINTAHr |
| 14639 | 0U, // FRINTASr |
| 14640 | 1U, // FRINTA_2Z2Z_S |
| 14641 | 1U, // FRINTA_4Z4Z_S |
| 14642 | 2056U, // FRINTA_ZPmZ_D |
| 14643 | 4112U, // FRINTA_ZPmZ_H |
| 14644 | 6152U, // FRINTA_ZPmZ_S |
| 14645 | 10264U, // FRINTA_ZPzZ_D |
| 14646 | 4128U, // FRINTA_ZPzZ_H |
| 14647 | 12312U, // FRINTA_ZPzZ_S |
| 14648 | 48U, // FRINTAv2f32 |
| 14649 | 56U, // FRINTAv2f64 |
| 14650 | 64U, // FRINTAv4f16 |
| 14651 | 72U, // FRINTAv4f32 |
| 14652 | 80U, // FRINTAv8f16 |
| 14653 | 0U, // FRINTIDr |
| 14654 | 0U, // FRINTIHr |
| 14655 | 0U, // FRINTISr |
| 14656 | 2056U, // FRINTI_ZPmZ_D |
| 14657 | 4112U, // FRINTI_ZPmZ_H |
| 14658 | 6152U, // FRINTI_ZPmZ_S |
| 14659 | 10264U, // FRINTI_ZPzZ_D |
| 14660 | 4128U, // FRINTI_ZPzZ_H |
| 14661 | 12312U, // FRINTI_ZPzZ_S |
| 14662 | 48U, // FRINTIv2f32 |
| 14663 | 56U, // FRINTIv2f64 |
| 14664 | 64U, // FRINTIv4f16 |
| 14665 | 72U, // FRINTIv4f32 |
| 14666 | 80U, // FRINTIv8f16 |
| 14667 | 0U, // FRINTMDr |
| 14668 | 0U, // FRINTMHr |
| 14669 | 0U, // FRINTMSr |
| 14670 | 1U, // FRINTM_2Z2Z_S |
| 14671 | 1U, // FRINTM_4Z4Z_S |
| 14672 | 2056U, // FRINTM_ZPmZ_D |
| 14673 | 4112U, // FRINTM_ZPmZ_H |
| 14674 | 6152U, // FRINTM_ZPmZ_S |
| 14675 | 10264U, // FRINTM_ZPzZ_D |
| 14676 | 4128U, // FRINTM_ZPzZ_H |
| 14677 | 12312U, // FRINTM_ZPzZ_S |
| 14678 | 48U, // FRINTMv2f32 |
| 14679 | 56U, // FRINTMv2f64 |
| 14680 | 64U, // FRINTMv4f16 |
| 14681 | 72U, // FRINTMv4f32 |
| 14682 | 80U, // FRINTMv8f16 |
| 14683 | 0U, // FRINTNDr |
| 14684 | 0U, // FRINTNHr |
| 14685 | 0U, // FRINTNSr |
| 14686 | 1U, // FRINTN_2Z2Z_S |
| 14687 | 1U, // FRINTN_4Z4Z_S |
| 14688 | 2056U, // FRINTN_ZPmZ_D |
| 14689 | 4112U, // FRINTN_ZPmZ_H |
| 14690 | 6152U, // FRINTN_ZPmZ_S |
| 14691 | 10264U, // FRINTN_ZPzZ_D |
| 14692 | 4128U, // FRINTN_ZPzZ_H |
| 14693 | 12312U, // FRINTN_ZPzZ_S |
| 14694 | 48U, // FRINTNv2f32 |
| 14695 | 56U, // FRINTNv2f64 |
| 14696 | 64U, // FRINTNv4f16 |
| 14697 | 72U, // FRINTNv4f32 |
| 14698 | 80U, // FRINTNv8f16 |
| 14699 | 0U, // FRINTPDr |
| 14700 | 0U, // FRINTPHr |
| 14701 | 0U, // FRINTPSr |
| 14702 | 1U, // FRINTP_2Z2Z_S |
| 14703 | 1U, // FRINTP_4Z4Z_S |
| 14704 | 2056U, // FRINTP_ZPmZ_D |
| 14705 | 4112U, // FRINTP_ZPmZ_H |
| 14706 | 6152U, // FRINTP_ZPmZ_S |
| 14707 | 10264U, // FRINTP_ZPzZ_D |
| 14708 | 4128U, // FRINTP_ZPzZ_H |
| 14709 | 12312U, // FRINTP_ZPzZ_S |
| 14710 | 48U, // FRINTPv2f32 |
| 14711 | 56U, // FRINTPv2f64 |
| 14712 | 64U, // FRINTPv4f16 |
| 14713 | 72U, // FRINTPv4f32 |
| 14714 | 80U, // FRINTPv8f16 |
| 14715 | 0U, // FRINTXDr |
| 14716 | 0U, // FRINTXHr |
| 14717 | 0U, // FRINTXSr |
| 14718 | 2056U, // FRINTX_ZPmZ_D |
| 14719 | 4112U, // FRINTX_ZPmZ_H |
| 14720 | 6152U, // FRINTX_ZPmZ_S |
| 14721 | 10264U, // FRINTX_ZPzZ_D |
| 14722 | 4128U, // FRINTX_ZPzZ_H |
| 14723 | 12312U, // FRINTX_ZPzZ_S |
| 14724 | 48U, // FRINTXv2f32 |
| 14725 | 56U, // FRINTXv2f64 |
| 14726 | 64U, // FRINTXv4f16 |
| 14727 | 72U, // FRINTXv4f32 |
| 14728 | 80U, // FRINTXv8f16 |
| 14729 | 0U, // FRINTZDr |
| 14730 | 0U, // FRINTZHr |
| 14731 | 0U, // FRINTZSr |
| 14732 | 2056U, // FRINTZ_ZPmZ_D |
| 14733 | 4112U, // FRINTZ_ZPmZ_H |
| 14734 | 6152U, // FRINTZ_ZPmZ_S |
| 14735 | 10264U, // FRINTZ_ZPzZ_D |
| 14736 | 4128U, // FRINTZ_ZPzZ_H |
| 14737 | 12312U, // FRINTZ_ZPzZ_S |
| 14738 | 48U, // FRINTZv2f32 |
| 14739 | 56U, // FRINTZv2f64 |
| 14740 | 64U, // FRINTZv4f16 |
| 14741 | 72U, // FRINTZv4f32 |
| 14742 | 80U, // FRINTZv8f16 |
| 14743 | 0U, // FRSQRTE_ZZ_D |
| 14744 | 1U, // FRSQRTE_ZZ_H |
| 14745 | 0U, // FRSQRTE_ZZ_S |
| 14746 | 0U, // FRSQRTEv1f16 |
| 14747 | 0U, // FRSQRTEv1i32 |
| 14748 | 0U, // FRSQRTEv1i64 |
| 14749 | 48U, // FRSQRTEv2f32 |
| 14750 | 56U, // FRSQRTEv2f64 |
| 14751 | 64U, // FRSQRTEv4f16 |
| 14752 | 72U, // FRSQRTEv4f32 |
| 14753 | 80U, // FRSQRTEv8f16 |
| 14754 | 14432U, // FRSQRTS16 |
| 14755 | 14432U, // FRSQRTS32 |
| 14756 | 14432U, // FRSQRTS64 |
| 14757 | 10336U, // FRSQRTS_ZZZ_D |
| 14758 | 4128U, // FRSQRTS_ZZZ_H |
| 14759 | 12384U, // FRSQRTS_ZZZ_S |
| 14760 | 2123936U, // FRSQRTSv2f32 |
| 14761 | 551040U, // FRSQRTSv2f64 |
| 14762 | 2386088U, // FRSQRTSv4f16 |
| 14763 | 813192U, // FRSQRTSv4f32 |
| 14764 | 1075344U, // FRSQRTSv8f16 |
| 14765 | 4552U, // FSCALE_2Z2Z_D |
| 14766 | 4344U, // FSCALE_2Z2Z_H |
| 14767 | 4560U, // FSCALE_2Z2Z_S |
| 14768 | 4288U, // FSCALE_2ZZ_D |
| 14769 | 4128U, // FSCALE_2ZZ_H |
| 14770 | 4208U, // FSCALE_2ZZ_S |
| 14771 | 4552U, // FSCALE_4Z4Z_D |
| 14772 | 4344U, // FSCALE_4Z4Z_H |
| 14773 | 4560U, // FSCALE_4Z4Z_S |
| 14774 | 4288U, // FSCALE_4ZZ_D |
| 14775 | 4128U, // FSCALE_4ZZ_H |
| 14776 | 4208U, // FSCALE_4ZZ_S |
| 14777 | 67381256U, // FSCALE_ZPmZ_D |
| 14778 | 102266912U, // FSCALE_ZPmZ_H |
| 14779 | 134492168U, // FSCALE_ZPmZ_S |
| 14780 | 2123936U, // FSCALEv2f32 |
| 14781 | 551040U, // FSCALEv2f64 |
| 14782 | 2386088U, // FSCALEv4f16 |
| 14783 | 813192U, // FSCALEv4f32 |
| 14784 | 1075344U, // FSCALEv8f16 |
| 14785 | 0U, // FSQRTDr |
| 14786 | 0U, // FSQRTHr |
| 14787 | 0U, // FSQRTSr |
| 14788 | 10264U, // FSQRT_ZPZz_D |
| 14789 | 4128U, // FSQRT_ZPZz_H |
| 14790 | 12312U, // FSQRT_ZPZz_S |
| 14791 | 2056U, // FSQRT_ZPmZ_D |
| 14792 | 4112U, // FSQRT_ZPmZ_H |
| 14793 | 6152U, // FSQRT_ZPmZ_S |
| 14794 | 48U, // FSQRTv2f32 |
| 14795 | 56U, // FSQRTv2f64 |
| 14796 | 64U, // FSQRTv4f16 |
| 14797 | 72U, // FSQRTv4f32 |
| 14798 | 80U, // FSQRTv8f16 |
| 14799 | 14432U, // FSUBDrr |
| 14800 | 14432U, // FSUBHrr |
| 14801 | 570697736U, // FSUBR_ZPmI_D |
| 14802 | 7895072U, // FSUBR_ZPmI_H |
| 14803 | 570699784U, // FSUBR_ZPmI_S |
| 14804 | 67381256U, // FSUBR_ZPmZ_D |
| 14805 | 102266912U, // FSUBR_ZPmZ_H |
| 14806 | 134492168U, // FSUBR_ZPmZ_S |
| 14807 | 14432U, // FSUBSrr |
| 14808 | 4296U, // FSUB_VG2_M2Z_D |
| 14809 | 4336U, // FSUB_VG2_M2Z_H |
| 14810 | 4304U, // FSUB_VG2_M2Z_S |
| 14811 | 4297U, // FSUB_VG4_M4Z_D |
| 14812 | 4337U, // FSUB_VG4_M4Z_H |
| 14813 | 4305U, // FSUB_VG4_M4Z_S |
| 14814 | 570697736U, // FSUB_ZPmI_D |
| 14815 | 7895072U, // FSUB_ZPmI_H |
| 14816 | 570699784U, // FSUB_ZPmI_S |
| 14817 | 67381256U, // FSUB_ZPmZ_D |
| 14818 | 102266912U, // FSUB_ZPmZ_H |
| 14819 | 134492168U, // FSUB_ZPmZ_S |
| 14820 | 10336U, // FSUB_ZZZ_D |
| 14821 | 4128U, // FSUB_ZZZ_H |
| 14822 | 12384U, // FSUB_ZZZ_S |
| 14823 | 2123936U, // FSUBv2f32 |
| 14824 | 551040U, // FSUBv2f64 |
| 14825 | 2386088U, // FSUBv4f16 |
| 14826 | 813192U, // FSUBv4f32 |
| 14827 | 1075344U, // FSUBv8f16 |
| 14828 | 272480U, // FTMAD_ZZI_D |
| 14829 | 104888352U, // FTMAD_ZZI_H |
| 14830 | 274528U, // FTMAD_ZZI_S |
| 14831 | 92259U, // FTMOPA_M2ZZZI_BtoH |
| 14832 | 92259U, // FTMOPA_M2ZZZI_BtoS |
| 14833 | 92257U, // FTMOPA_M2ZZZI_HtoH |
| 14834 | 92257U, // FTMOPA_M2ZZZI_HtoS |
| 14835 | 92259U, // FTMOPA_M2ZZZI_StoS |
| 14836 | 10336U, // FTSMUL_ZZZ_D |
| 14837 | 4128U, // FTSMUL_ZZZ_H |
| 14838 | 12384U, // FTSMUL_ZZZ_S |
| 14839 | 10336U, // FTSSEL_ZZZ_D |
| 14840 | 4128U, // FTSSEL_ZZZ_H |
| 14841 | 12384U, // FTSSEL_ZZZ_S |
| 14842 | 10082841U, // FVDOTB_VG4_M2ZZI_BtoS |
| 14843 | 10082841U, // FVDOTT_VG4_M2ZZI_BtoS |
| 14844 | 10082840U, // FVDOT_VG2_M2ZZI_BtoH |
| 14845 | 206862576U, // FVDOT_VG2_M2ZZI_HtoS |
| 14846 | 0U, // GCSPOPCX |
| 14847 | 0U, // GCSPOPM |
| 14848 | 0U, // GCSPOPX |
| 14849 | 0U, // GCSPUSHM |
| 14850 | 0U, // GCSPUSHX |
| 14851 | 0U, // GCSSS1 |
| 14852 | 0U, // GCSSS2 |
| 14853 | 584U, // GCSSTR |
| 14854 | 584U, // GCSSTTR |
| 14855 | 12089579U, // GLD1B_D |
| 14856 | 809531587U, // GLD1B_D_IMM |
| 14857 | 12351723U, // GLD1B_D_SXTW |
| 14858 | 12613867U, // GLD1B_D_UXTW |
| 14859 | 809531507U, // GLD1B_S_IMM |
| 14860 | 12876011U, // GLD1B_S_SXTW |
| 14861 | 13138155U, // GLD1B_S_UXTW |
| 14862 | 12089579U, // GLD1D |
| 14863 | 13400259U, // GLD1D_IMM |
| 14864 | 13662443U, // GLD1D_SCALED |
| 14865 | 12351723U, // GLD1D_SXTW |
| 14866 | 13924587U, // GLD1D_SXTW_SCALED |
| 14867 | 12613867U, // GLD1D_UXTW |
| 14868 | 14186731U, // GLD1D_UXTW_SCALED |
| 14869 | 12089579U, // GLD1H_D |
| 14870 | 819755203U, // GLD1H_D_IMM |
| 14871 | 14711019U, // GLD1H_D_SCALED |
| 14872 | 12351723U, // GLD1H_D_SXTW |
| 14873 | 14973163U, // GLD1H_D_SXTW_SCALED |
| 14874 | 12613867U, // GLD1H_D_UXTW |
| 14875 | 15235307U, // GLD1H_D_UXTW_SCALED |
| 14876 | 819755123U, // GLD1H_S_IMM |
| 14877 | 12876011U, // GLD1H_S_SXTW |
| 14878 | 15497451U, // GLD1H_S_SXTW_SCALED |
| 14879 | 13138155U, // GLD1H_S_UXTW |
| 14880 | 15759595U, // GLD1H_S_UXTW_SCALED |
| 14881 | 809531587U, // GLD1Q |
| 14882 | 12089579U, // GLD1SB_D |
| 14883 | 809531587U, // GLD1SB_D_IMM |
| 14884 | 12351723U, // GLD1SB_D_SXTW |
| 14885 | 12613867U, // GLD1SB_D_UXTW |
| 14886 | 809531507U, // GLD1SB_S_IMM |
| 14887 | 12876011U, // GLD1SB_S_SXTW |
| 14888 | 13138155U, // GLD1SB_S_UXTW |
| 14889 | 12089579U, // GLD1SH_D |
| 14890 | 819755203U, // GLD1SH_D_IMM |
| 14891 | 14711019U, // GLD1SH_D_SCALED |
| 14892 | 12351723U, // GLD1SH_D_SXTW |
| 14893 | 14973163U, // GLD1SH_D_SXTW_SCALED |
| 14894 | 12613867U, // GLD1SH_D_UXTW |
| 14895 | 15235307U, // GLD1SH_D_UXTW_SCALED |
| 14896 | 819755123U, // GLD1SH_S_IMM |
| 14897 | 12876011U, // GLD1SH_S_SXTW |
| 14898 | 15497451U, // GLD1SH_S_SXTW_SCALED |
| 14899 | 13138155U, // GLD1SH_S_UXTW |
| 14900 | 15759595U, // GLD1SH_S_UXTW_SCALED |
| 14901 | 12089579U, // GLD1SW_D |
| 14902 | 821328067U, // GLD1SW_D_IMM |
| 14903 | 16283883U, // GLD1SW_D_SCALED |
| 14904 | 12351723U, // GLD1SW_D_SXTW |
| 14905 | 16546027U, // GLD1SW_D_SXTW_SCALED |
| 14906 | 12613867U, // GLD1SW_D_UXTW |
| 14907 | 16808171U, // GLD1SW_D_UXTW_SCALED |
| 14908 | 12089579U, // GLD1W_D |
| 14909 | 821328067U, // GLD1W_D_IMM |
| 14910 | 16283883U, // GLD1W_D_SCALED |
| 14911 | 12351723U, // GLD1W_D_SXTW |
| 14912 | 16546027U, // GLD1W_D_SXTW_SCALED |
| 14913 | 12613867U, // GLD1W_D_UXTW |
| 14914 | 16808171U, // GLD1W_D_UXTW_SCALED |
| 14915 | 821327987U, // GLD1W_IMM |
| 14916 | 12876011U, // GLD1W_SXTW |
| 14917 | 17070315U, // GLD1W_SXTW_SCALED |
| 14918 | 13138155U, // GLD1W_UXTW |
| 14919 | 17332459U, // GLD1W_UXTW_SCALED |
| 14920 | 12089579U, // GLDFF1B_D |
| 14921 | 809531587U, // GLDFF1B_D_IMM |
| 14922 | 12351723U, // GLDFF1B_D_SXTW |
| 14923 | 12613867U, // GLDFF1B_D_UXTW |
| 14924 | 809531507U, // GLDFF1B_S_IMM |
| 14925 | 12876011U, // GLDFF1B_S_SXTW |
| 14926 | 13138155U, // GLDFF1B_S_UXTW |
| 14927 | 12089579U, // GLDFF1D |
| 14928 | 13400259U, // GLDFF1D_IMM |
| 14929 | 13662443U, // GLDFF1D_SCALED |
| 14930 | 12351723U, // GLDFF1D_SXTW |
| 14931 | 13924587U, // GLDFF1D_SXTW_SCALED |
| 14932 | 12613867U, // GLDFF1D_UXTW |
| 14933 | 14186731U, // GLDFF1D_UXTW_SCALED |
| 14934 | 12089579U, // GLDFF1H_D |
| 14935 | 819755203U, // GLDFF1H_D_IMM |
| 14936 | 14711019U, // GLDFF1H_D_SCALED |
| 14937 | 12351723U, // GLDFF1H_D_SXTW |
| 14938 | 14973163U, // GLDFF1H_D_SXTW_SCALED |
| 14939 | 12613867U, // GLDFF1H_D_UXTW |
| 14940 | 15235307U, // GLDFF1H_D_UXTW_SCALED |
| 14941 | 819755123U, // GLDFF1H_S_IMM |
| 14942 | 12876011U, // GLDFF1H_S_SXTW |
| 14943 | 15497451U, // GLDFF1H_S_SXTW_SCALED |
| 14944 | 13138155U, // GLDFF1H_S_UXTW |
| 14945 | 15759595U, // GLDFF1H_S_UXTW_SCALED |
| 14946 | 12089579U, // GLDFF1SB_D |
| 14947 | 809531587U, // GLDFF1SB_D_IMM |
| 14948 | 12351723U, // GLDFF1SB_D_SXTW |
| 14949 | 12613867U, // GLDFF1SB_D_UXTW |
| 14950 | 809531507U, // GLDFF1SB_S_IMM |
| 14951 | 12876011U, // GLDFF1SB_S_SXTW |
| 14952 | 13138155U, // GLDFF1SB_S_UXTW |
| 14953 | 12089579U, // GLDFF1SH_D |
| 14954 | 819755203U, // GLDFF1SH_D_IMM |
| 14955 | 14711019U, // GLDFF1SH_D_SCALED |
| 14956 | 12351723U, // GLDFF1SH_D_SXTW |
| 14957 | 14973163U, // GLDFF1SH_D_SXTW_SCALED |
| 14958 | 12613867U, // GLDFF1SH_D_UXTW |
| 14959 | 15235307U, // GLDFF1SH_D_UXTW_SCALED |
| 14960 | 819755123U, // GLDFF1SH_S_IMM |
| 14961 | 12876011U, // GLDFF1SH_S_SXTW |
| 14962 | 15497451U, // GLDFF1SH_S_SXTW_SCALED |
| 14963 | 13138155U, // GLDFF1SH_S_UXTW |
| 14964 | 15759595U, // GLDFF1SH_S_UXTW_SCALED |
| 14965 | 12089579U, // GLDFF1SW_D |
| 14966 | 821328067U, // GLDFF1SW_D_IMM |
| 14967 | 16283883U, // GLDFF1SW_D_SCALED |
| 14968 | 12351723U, // GLDFF1SW_D_SXTW |
| 14969 | 16546027U, // GLDFF1SW_D_SXTW_SCALED |
| 14970 | 12613867U, // GLDFF1SW_D_UXTW |
| 14971 | 16808171U, // GLDFF1SW_D_UXTW_SCALED |
| 14972 | 12089579U, // GLDFF1W_D |
| 14973 | 821328067U, // GLDFF1W_D_IMM |
| 14974 | 16283883U, // GLDFF1W_D_SCALED |
| 14975 | 12351723U, // GLDFF1W_D_SXTW |
| 14976 | 16546027U, // GLDFF1W_D_SXTW_SCALED |
| 14977 | 12613867U, // GLDFF1W_D_UXTW |
| 14978 | 16808171U, // GLDFF1W_D_UXTW_SCALED |
| 14979 | 821327987U, // GLDFF1W_IMM |
| 14980 | 12876011U, // GLDFF1W_SXTW |
| 14981 | 17070315U, // GLDFF1W_SXTW_SCALED |
| 14982 | 13138155U, // GLDFF1W_UXTW |
| 14983 | 17332459U, // GLDFF1W_UXTW_SCALED |
| 14984 | 14432U, // GMI |
| 14985 | 0U, // HINT |
| 14986 | 67381272U, // HISTCNT_ZPzZZ_D |
| 14987 | 134492184U, // HISTCNT_ZPzZZ_S |
| 14988 | 8288U, // HISTSEG_ZZZ |
| 14989 | 0U, // HLT |
| 14990 | 0U, // HVC |
| 14991 | 2U, // INCB_XPiI |
| 14992 | 2U, // INCD_XPiI |
| 14993 | 2U, // INCD_ZPiI |
| 14994 | 2U, // INCH_XPiI |
| 14995 | 0U, // INCH_ZPiI |
| 14996 | 0U, // INCP_XP_B |
| 14997 | 0U, // INCP_XP_D |
| 14998 | 0U, // INCP_XP_H |
| 14999 | 0U, // INCP_XP_S |
| 15000 | 0U, // INCP_ZP_D |
| 15001 | 1U, // INCP_ZP_H |
| 15002 | 0U, // INCP_ZP_S |
| 15003 | 2U, // INCW_XPiI |
| 15004 | 2U, // INCW_ZPiI |
| 15005 | 595U, // INDEX_II_B |
| 15006 | 14432U, // INDEX_II_D |
| 15007 | 3U, // INDEX_II_H |
| 15008 | 14432U, // INDEX_II_S |
| 15009 | 4331U, // INDEX_IR_B |
| 15010 | 14432U, // INDEX_IR_D |
| 15011 | 1U, // INDEX_IR_H |
| 15012 | 14432U, // INDEX_IR_S |
| 15013 | 129120U, // INDEX_RI_B |
| 15014 | 14432U, // INDEX_RI_D |
| 15015 | 600U, // INDEX_RI_H |
| 15016 | 14432U, // INDEX_RI_S |
| 15017 | 14432U, // INDEX_RR_B |
| 15018 | 14432U, // INDEX_RR_D |
| 15019 | 4328U, // INDEX_RR_H |
| 15020 | 14432U, // INDEX_RR_S |
| 15021 | 121440U, // INSERT_MXIPZ_H_B |
| 15022 | 131680U, // INSERT_MXIPZ_H_D |
| 15023 | 133728U, // INSERT_MXIPZ_H_H |
| 15024 | 135776U, // INSERT_MXIPZ_H_Q |
| 15025 | 137824U, // INSERT_MXIPZ_H_S |
| 15026 | 121440U, // INSERT_MXIPZ_V_B |
| 15027 | 131680U, // INSERT_MXIPZ_V_D |
| 15028 | 133728U, // INSERT_MXIPZ_V_H |
| 15029 | 135776U, // INSERT_MXIPZ_V_Q |
| 15030 | 137824U, // INSERT_MXIPZ_V_S |
| 15031 | 1U, // INSR_ZR_B |
| 15032 | 1U, // INSR_ZR_D |
| 15033 | 1U, // INSR_ZR_H |
| 15034 | 1U, // INSR_ZR_S |
| 15035 | 3U, // INSR_ZV_B |
| 15036 | 3U, // INSR_ZV_D |
| 15037 | 1U, // INSR_ZV_H |
| 15038 | 3U, // INSR_ZV_S |
| 15039 | 3U, // INSvi16gpr |
| 15040 | 86411U, // INSvi16lane |
| 15041 | 3U, // INSvi32gpr |
| 15042 | 86419U, // INSvi32lane |
| 15043 | 3U, // INSvi64gpr |
| 15044 | 86427U, // INSvi64lane |
| 15045 | 3U, // INSvi8gpr |
| 15046 | 86435U, // INSvi8lane |
| 15047 | 14432U, // IRG |
| 15048 | 0U, // ISB |
| 15049 | 8288U, // LASTA_RPZ_B |
| 15050 | 10336U, // LASTA_RPZ_D |
| 15051 | 22624U, // LASTA_RPZ_H |
| 15052 | 12384U, // LASTA_RPZ_S |
| 15053 | 8288U, // LASTA_VPZ_B |
| 15054 | 10336U, // LASTA_VPZ_D |
| 15055 | 22624U, // LASTA_VPZ_H |
| 15056 | 12384U, // LASTA_VPZ_S |
| 15057 | 8288U, // LASTB_RPZ_B |
| 15058 | 10336U, // LASTB_RPZ_D |
| 15059 | 22624U, // LASTB_RPZ_H |
| 15060 | 12384U, // LASTB_RPZ_S |
| 15061 | 8288U, // LASTB_VPZ_B |
| 15062 | 10336U, // LASTB_VPZ_D |
| 15063 | 22624U, // LASTB_VPZ_H |
| 15064 | 12384U, // LASTB_VPZ_S |
| 15065 | 8288U, // LASTP_XPP_B |
| 15066 | 10336U, // LASTP_XPP_D |
| 15067 | 22624U, // LASTP_XPP_H |
| 15068 | 12384U, // LASTP_XPP_S |
| 15069 | 17594603U, // LD1B |
| 15070 | 17594603U, // LD1B_2Z |
| 15071 | 853309675U, // LD1B_2Z_IMM |
| 15072 | 139883U, // LD1B_2Z_STRIDED |
| 15073 | 141931U, // LD1B_2Z_STRIDED_IMM |
| 15074 | 17594603U, // LD1B_4Z |
| 15075 | 854882539U, // LD1B_4Z_IMM |
| 15076 | 17594603U, // LD1B_4Z_STRIDED |
| 15077 | 854882539U, // LD1B_4Z_STRIDED_IMM |
| 15078 | 17594603U, // LD1B_D |
| 15079 | 843086059U, // LD1B_D_IMM |
| 15080 | 17594603U, // LD1B_H |
| 15081 | 843086059U, // LD1B_H_IMM |
| 15082 | 843086059U, // LD1B_IMM |
| 15083 | 17594603U, // LD1B_S |
| 15084 | 843086059U, // LD1B_S_IMM |
| 15085 | 17856747U, // LD1D |
| 15086 | 17856747U, // LD1D_2Z |
| 15087 | 853309675U, // LD1D_2Z_IMM |
| 15088 | 17856747U, // LD1D_2Z_STRIDED |
| 15089 | 853309675U, // LD1D_2Z_STRIDED_IMM |
| 15090 | 17856747U, // LD1D_4Z |
| 15091 | 854882539U, // LD1D_4Z_IMM |
| 15092 | 17856747U, // LD1D_4Z_STRIDED |
| 15093 | 854882539U, // LD1D_4Z_STRIDED_IMM |
| 15094 | 843086059U, // LD1D_IMM |
| 15095 | 17856747U, // LD1D_Q |
| 15096 | 843086059U, // LD1D_Q_IMM |
| 15097 | 0U, // LD1Fourv16b |
| 15098 | 0U, // LD1Fourv16b_POST |
| 15099 | 0U, // LD1Fourv1d |
| 15100 | 0U, // LD1Fourv1d_POST |
| 15101 | 0U, // LD1Fourv2d |
| 15102 | 0U, // LD1Fourv2d_POST |
| 15103 | 0U, // LD1Fourv2s |
| 15104 | 0U, // LD1Fourv2s_POST |
| 15105 | 0U, // LD1Fourv4h |
| 15106 | 0U, // LD1Fourv4h_POST |
| 15107 | 0U, // LD1Fourv4s |
| 15108 | 0U, // LD1Fourv4s_POST |
| 15109 | 0U, // LD1Fourv8b |
| 15110 | 0U, // LD1Fourv8b_POST |
| 15111 | 0U, // LD1Fourv8h |
| 15112 | 0U, // LD1Fourv8h_POST |
| 15113 | 18118891U, // LD1H |
| 15114 | 18118891U, // LD1H_2Z |
| 15115 | 853309675U, // LD1H_2Z_IMM |
| 15116 | 143979U, // LD1H_2Z_STRIDED |
| 15117 | 141931U, // LD1H_2Z_STRIDED_IMM |
| 15118 | 18118891U, // LD1H_4Z |
| 15119 | 854882539U, // LD1H_4Z_IMM |
| 15120 | 18118891U, // LD1H_4Z_STRIDED |
| 15121 | 854882539U, // LD1H_4Z_STRIDED_IMM |
| 15122 | 18118891U, // LD1H_D |
| 15123 | 843086059U, // LD1H_D_IMM |
| 15124 | 843086059U, // LD1H_IMM |
| 15125 | 18118891U, // LD1H_S |
| 15126 | 843086059U, // LD1H_S_IMM |
| 15127 | 0U, // LD1Onev16b |
| 15128 | 0U, // LD1Onev16b_POST |
| 15129 | 0U, // LD1Onev1d |
| 15130 | 0U, // LD1Onev1d_POST |
| 15131 | 0U, // LD1Onev2d |
| 15132 | 0U, // LD1Onev2d_POST |
| 15133 | 0U, // LD1Onev2s |
| 15134 | 0U, // LD1Onev2s_POST |
| 15135 | 0U, // LD1Onev4h |
| 15136 | 0U, // LD1Onev4h_POST |
| 15137 | 0U, // LD1Onev4s |
| 15138 | 0U, // LD1Onev4s_POST |
| 15139 | 0U, // LD1Onev8b |
| 15140 | 0U, // LD1Onev8b_POST |
| 15141 | 0U, // LD1Onev8h |
| 15142 | 0U, // LD1Onev8h_POST |
| 15143 | 809531627U, // LD1RB_D_IMM |
| 15144 | 809531627U, // LD1RB_H_IMM |
| 15145 | 809531627U, // LD1RB_IMM |
| 15146 | 809531627U, // LD1RB_S_IMM |
| 15147 | 13400299U, // LD1RD_IMM |
| 15148 | 819755243U, // LD1RH_D_IMM |
| 15149 | 819755243U, // LD1RH_IMM |
| 15150 | 819755243U, // LD1RH_S_IMM |
| 15151 | 17594603U, // LD1RO_B |
| 15152 | 18381035U, // LD1RO_B_IMM |
| 15153 | 17856747U, // LD1RO_D |
| 15154 | 18381035U, // LD1RO_D_IMM |
| 15155 | 18118891U, // LD1RO_H |
| 15156 | 18381035U, // LD1RO_H_IMM |
| 15157 | 18643179U, // LD1RO_W |
| 15158 | 18381035U, // LD1RO_W_IMM |
| 15159 | 17594603U, // LD1RQ_B |
| 15160 | 18905323U, // LD1RQ_B_IMM |
| 15161 | 17856747U, // LD1RQ_D |
| 15162 | 18905323U, // LD1RQ_D_IMM |
| 15163 | 18118891U, // LD1RQ_H |
| 15164 | 18905323U, // LD1RQ_H_IMM |
| 15165 | 18643179U, // LD1RQ_W |
| 15166 | 18905323U, // LD1RQ_W_IMM |
| 15167 | 809531627U, // LD1RSB_D_IMM |
| 15168 | 809531627U, // LD1RSB_H_IMM |
| 15169 | 809531627U, // LD1RSB_S_IMM |
| 15170 | 819755243U, // LD1RSH_D_IMM |
| 15171 | 819755243U, // LD1RSH_S_IMM |
| 15172 | 821328107U, // LD1RSW_IMM |
| 15173 | 821328107U, // LD1RW_D_IMM |
| 15174 | 821328107U, // LD1RW_IMM |
| 15175 | 0U, // LD1Rv16b |
| 15176 | 0U, // LD1Rv16b_POST |
| 15177 | 0U, // LD1Rv1d |
| 15178 | 0U, // LD1Rv1d_POST |
| 15179 | 0U, // LD1Rv2d |
| 15180 | 0U, // LD1Rv2d_POST |
| 15181 | 0U, // LD1Rv2s |
| 15182 | 0U, // LD1Rv2s_POST |
| 15183 | 0U, // LD1Rv4h |
| 15184 | 0U, // LD1Rv4h_POST |
| 15185 | 0U, // LD1Rv4s |
| 15186 | 0U, // LD1Rv4s_POST |
| 15187 | 0U, // LD1Rv8b |
| 15188 | 0U, // LD1Rv8b_POST |
| 15189 | 0U, // LD1Rv8h |
| 15190 | 0U, // LD1Rv8h_POST |
| 15191 | 17594603U, // LD1SB_D |
| 15192 | 843086059U, // LD1SB_D_IMM |
| 15193 | 17594603U, // LD1SB_H |
| 15194 | 843086059U, // LD1SB_H_IMM |
| 15195 | 17594603U, // LD1SB_S |
| 15196 | 843086059U, // LD1SB_S_IMM |
| 15197 | 18118891U, // LD1SH_D |
| 15198 | 843086059U, // LD1SH_D_IMM |
| 15199 | 18118891U, // LD1SH_S |
| 15200 | 843086059U, // LD1SH_S_IMM |
| 15201 | 18643179U, // LD1SW_D |
| 15202 | 843086059U, // LD1SW_D_IMM |
| 15203 | 0U, // LD1Threev16b |
| 15204 | 0U, // LD1Threev16b_POST |
| 15205 | 0U, // LD1Threev1d |
| 15206 | 0U, // LD1Threev1d_POST |
| 15207 | 0U, // LD1Threev2d |
| 15208 | 0U, // LD1Threev2d_POST |
| 15209 | 0U, // LD1Threev2s |
| 15210 | 0U, // LD1Threev2s_POST |
| 15211 | 0U, // LD1Threev4h |
| 15212 | 0U, // LD1Threev4h_POST |
| 15213 | 0U, // LD1Threev4s |
| 15214 | 0U, // LD1Threev4s_POST |
| 15215 | 0U, // LD1Threev8b |
| 15216 | 0U, // LD1Threev8b_POST |
| 15217 | 0U, // LD1Threev8h |
| 15218 | 0U, // LD1Threev8h_POST |
| 15219 | 0U, // LD1Twov16b |
| 15220 | 0U, // LD1Twov16b_POST |
| 15221 | 0U, // LD1Twov1d |
| 15222 | 0U, // LD1Twov1d_POST |
| 15223 | 0U, // LD1Twov2d |
| 15224 | 0U, // LD1Twov2d_POST |
| 15225 | 0U, // LD1Twov2s |
| 15226 | 0U, // LD1Twov2s_POST |
| 15227 | 0U, // LD1Twov4h |
| 15228 | 0U, // LD1Twov4h_POST |
| 15229 | 0U, // LD1Twov4s |
| 15230 | 0U, // LD1Twov4s_POST |
| 15231 | 0U, // LD1Twov8b |
| 15232 | 0U, // LD1Twov8b_POST |
| 15233 | 0U, // LD1Twov8h |
| 15234 | 0U, // LD1Twov8h_POST |
| 15235 | 18643179U, // LD1W |
| 15236 | 18643179U, // LD1W_2Z |
| 15237 | 853309675U, // LD1W_2Z_IMM |
| 15238 | 18643179U, // LD1W_2Z_STRIDED |
| 15239 | 853309675U, // LD1W_2Z_STRIDED_IMM |
| 15240 | 18643179U, // LD1W_4Z |
| 15241 | 854882539U, // LD1W_4Z_IMM |
| 15242 | 18643179U, // LD1W_4Z_STRIDED |
| 15243 | 854882539U, // LD1W_4Z_STRIDED_IMM |
| 15244 | 18643179U, // LD1W_D |
| 15245 | 843086059U, // LD1W_D_IMM |
| 15246 | 843086059U, // LD1W_IMM |
| 15247 | 18643179U, // LD1W_Q |
| 15248 | 843086059U, // LD1W_Q_IMM |
| 15249 | 19282544U, // LD1_MXIPXX_H_B |
| 15250 | 19544688U, // LD1_MXIPXX_H_D |
| 15251 | 19806832U, // LD1_MXIPXX_H_H |
| 15252 | 20068976U, // LD1_MXIPXX_H_Q |
| 15253 | 20331120U, // LD1_MXIPXX_H_S |
| 15254 | 19282544U, // LD1_MXIPXX_V_B |
| 15255 | 19544688U, // LD1_MXIPXX_V_D |
| 15256 | 19806832U, // LD1_MXIPXX_V_H |
| 15257 | 20068976U, // LD1_MXIPXX_V_Q |
| 15258 | 20331120U, // LD1_MXIPXX_V_S |
| 15259 | 0U, // LD1i16 |
| 15260 | 0U, // LD1i16_POST |
| 15261 | 0U, // LD1i32 |
| 15262 | 0U, // LD1i32_POST |
| 15263 | 0U, // LD1i64 |
| 15264 | 0U, // LD1i64_POST |
| 15265 | 0U, // LD1i8 |
| 15266 | 0U, // LD1i8_POST |
| 15267 | 17594603U, // LD2B |
| 15268 | 853309675U, // LD2B_IMM |
| 15269 | 17856747U, // LD2D |
| 15270 | 853309675U, // LD2D_IMM |
| 15271 | 18118891U, // LD2H |
| 15272 | 853309675U, // LD2H_IMM |
| 15273 | 20478187U, // LD2Q |
| 15274 | 853309675U, // LD2Q_IMM |
| 15275 | 0U, // LD2Rv16b |
| 15276 | 0U, // LD2Rv16b_POST |
| 15277 | 0U, // LD2Rv1d |
| 15278 | 0U, // LD2Rv1d_POST |
| 15279 | 0U, // LD2Rv2d |
| 15280 | 0U, // LD2Rv2d_POST |
| 15281 | 0U, // LD2Rv2s |
| 15282 | 0U, // LD2Rv2s_POST |
| 15283 | 0U, // LD2Rv4h |
| 15284 | 0U, // LD2Rv4h_POST |
| 15285 | 0U, // LD2Rv4s |
| 15286 | 0U, // LD2Rv4s_POST |
| 15287 | 0U, // LD2Rv8b |
| 15288 | 0U, // LD2Rv8b_POST |
| 15289 | 0U, // LD2Rv8h |
| 15290 | 0U, // LD2Rv8h_POST |
| 15291 | 0U, // LD2Twov16b |
| 15292 | 0U, // LD2Twov16b_POST |
| 15293 | 0U, // LD2Twov2d |
| 15294 | 0U, // LD2Twov2d_POST |
| 15295 | 0U, // LD2Twov2s |
| 15296 | 0U, // LD2Twov2s_POST |
| 15297 | 0U, // LD2Twov4h |
| 15298 | 0U, // LD2Twov4h_POST |
| 15299 | 0U, // LD2Twov4s |
| 15300 | 0U, // LD2Twov4s_POST |
| 15301 | 0U, // LD2Twov8b |
| 15302 | 0U, // LD2Twov8b_POST |
| 15303 | 0U, // LD2Twov8h |
| 15304 | 0U, // LD2Twov8h_POST |
| 15305 | 18643179U, // LD2W |
| 15306 | 853309675U, // LD2W_IMM |
| 15307 | 0U, // LD2i16 |
| 15308 | 0U, // LD2i16_POST |
| 15309 | 0U, // LD2i32 |
| 15310 | 0U, // LD2i32_POST |
| 15311 | 0U, // LD2i64 |
| 15312 | 0U, // LD2i64_POST |
| 15313 | 0U, // LD2i8 |
| 15314 | 0U, // LD2i8_POST |
| 15315 | 17594603U, // LD3B |
| 15316 | 20740331U, // LD3B_IMM |
| 15317 | 17856747U, // LD3D |
| 15318 | 20740331U, // LD3D_IMM |
| 15319 | 18118891U, // LD3H |
| 15320 | 20740331U, // LD3H_IMM |
| 15321 | 20478187U, // LD3Q |
| 15322 | 20740331U, // LD3Q_IMM |
| 15323 | 0U, // LD3Rv16b |
| 15324 | 0U, // LD3Rv16b_POST |
| 15325 | 0U, // LD3Rv1d |
| 15326 | 0U, // LD3Rv1d_POST |
| 15327 | 0U, // LD3Rv2d |
| 15328 | 0U, // LD3Rv2d_POST |
| 15329 | 0U, // LD3Rv2s |
| 15330 | 0U, // LD3Rv2s_POST |
| 15331 | 0U, // LD3Rv4h |
| 15332 | 0U, // LD3Rv4h_POST |
| 15333 | 0U, // LD3Rv4s |
| 15334 | 0U, // LD3Rv4s_POST |
| 15335 | 0U, // LD3Rv8b |
| 15336 | 0U, // LD3Rv8b_POST |
| 15337 | 0U, // LD3Rv8h |
| 15338 | 0U, // LD3Rv8h_POST |
| 15339 | 0U, // LD3Threev16b |
| 15340 | 0U, // LD3Threev16b_POST |
| 15341 | 0U, // LD3Threev2d |
| 15342 | 0U, // LD3Threev2d_POST |
| 15343 | 0U, // LD3Threev2s |
| 15344 | 0U, // LD3Threev2s_POST |
| 15345 | 0U, // LD3Threev4h |
| 15346 | 0U, // LD3Threev4h_POST |
| 15347 | 0U, // LD3Threev4s |
| 15348 | 0U, // LD3Threev4s_POST |
| 15349 | 0U, // LD3Threev8b |
| 15350 | 0U, // LD3Threev8b_POST |
| 15351 | 0U, // LD3Threev8h |
| 15352 | 0U, // LD3Threev8h_POST |
| 15353 | 18643179U, // LD3W |
| 15354 | 20740331U, // LD3W_IMM |
| 15355 | 0U, // LD3i16 |
| 15356 | 0U, // LD3i16_POST |
| 15357 | 0U, // LD3i32 |
| 15358 | 0U, // LD3i32_POST |
| 15359 | 0U, // LD3i64 |
| 15360 | 0U, // LD3i64_POST |
| 15361 | 0U, // LD3i8 |
| 15362 | 0U, // LD3i8_POST |
| 15363 | 17594603U, // LD4B |
| 15364 | 854882539U, // LD4B_IMM |
| 15365 | 17856747U, // LD4D |
| 15366 | 854882539U, // LD4D_IMM |
| 15367 | 0U, // LD4Fourv16b |
| 15368 | 0U, // LD4Fourv16b_POST |
| 15369 | 0U, // LD4Fourv2d |
| 15370 | 0U, // LD4Fourv2d_POST |
| 15371 | 0U, // LD4Fourv2s |
| 15372 | 0U, // LD4Fourv2s_POST |
| 15373 | 0U, // LD4Fourv4h |
| 15374 | 0U, // LD4Fourv4h_POST |
| 15375 | 0U, // LD4Fourv4s |
| 15376 | 0U, // LD4Fourv4s_POST |
| 15377 | 0U, // LD4Fourv8b |
| 15378 | 0U, // LD4Fourv8b_POST |
| 15379 | 0U, // LD4Fourv8h |
| 15380 | 0U, // LD4Fourv8h_POST |
| 15381 | 18118891U, // LD4H |
| 15382 | 854882539U, // LD4H_IMM |
| 15383 | 20478187U, // LD4Q |
| 15384 | 854882539U, // LD4Q_IMM |
| 15385 | 0U, // LD4Rv16b |
| 15386 | 0U, // LD4Rv16b_POST |
| 15387 | 0U, // LD4Rv1d |
| 15388 | 0U, // LD4Rv1d_POST |
| 15389 | 0U, // LD4Rv2d |
| 15390 | 0U, // LD4Rv2d_POST |
| 15391 | 0U, // LD4Rv2s |
| 15392 | 0U, // LD4Rv2s_POST |
| 15393 | 0U, // LD4Rv4h |
| 15394 | 0U, // LD4Rv4h_POST |
| 15395 | 0U, // LD4Rv4s |
| 15396 | 0U, // LD4Rv4s_POST |
| 15397 | 0U, // LD4Rv8b |
| 15398 | 0U, // LD4Rv8b_POST |
| 15399 | 0U, // LD4Rv8h |
| 15400 | 0U, // LD4Rv8h_POST |
| 15401 | 18643179U, // LD4W |
| 15402 | 854882539U, // LD4W_IMM |
| 15403 | 0U, // LD4i16 |
| 15404 | 0U, // LD4i16_POST |
| 15405 | 0U, // LD4i32 |
| 15406 | 0U, // LD4i32_POST |
| 15407 | 0U, // LD4i64 |
| 15408 | 0U, // LD4i64_POST |
| 15409 | 0U, // LD4i8 |
| 15410 | 0U, // LD4i8_POST |
| 15411 | 0U, // LD64B |
| 15412 | 3U, // LDADDAB |
| 15413 | 3U, // LDADDAH |
| 15414 | 3U, // LDADDALB |
| 15415 | 3U, // LDADDALH |
| 15416 | 3U, // LDADDALW |
| 15417 | 3U, // LDADDALX |
| 15418 | 3U, // LDADDAW |
| 15419 | 3U, // LDADDAX |
| 15420 | 3U, // LDADDB |
| 15421 | 3U, // LDADDH |
| 15422 | 3U, // LDADDLB |
| 15423 | 3U, // LDADDLH |
| 15424 | 3U, // LDADDLW |
| 15425 | 3U, // LDADDLX |
| 15426 | 3U, // LDADDW |
| 15427 | 3U, // LDADDX |
| 15428 | 0U, // LDAP1 |
| 15429 | 20986128U, // LDAPPi |
| 15430 | 584U, // LDAPRB |
| 15431 | 584U, // LDAPRH |
| 15432 | 584U, // LDAPRW |
| 15433 | 633U, // LDAPRWpost |
| 15434 | 584U, // LDAPRX |
| 15435 | 641U, // LDAPRXpost |
| 15436 | 6830176U, // LDAPURBi |
| 15437 | 6830176U, // LDAPURHi |
| 15438 | 6830176U, // LDAPURSBWi |
| 15439 | 6830176U, // LDAPURSBXi |
| 15440 | 6830176U, // LDAPURSHWi |
| 15441 | 6830176U, // LDAPURSHXi |
| 15442 | 6830176U, // LDAPURSWi |
| 15443 | 6830176U, // LDAPURXi |
| 15444 | 6830176U, // LDAPURbi |
| 15445 | 6830176U, // LDAPURdi |
| 15446 | 6830176U, // LDAPURhi |
| 15447 | 6830176U, // LDAPURi |
| 15448 | 6830176U, // LDAPURqi |
| 15449 | 6830176U, // LDAPURsi |
| 15450 | 20986128U, // LDAPi |
| 15451 | 584U, // LDARB |
| 15452 | 584U, // LDARH |
| 15453 | 584U, // LDARW |
| 15454 | 584U, // LDARX |
| 15455 | 584U, // LDATXRW |
| 15456 | 584U, // LDATXRX |
| 15457 | 6830352U, // LDAXPW |
| 15458 | 6830352U, // LDAXPX |
| 15459 | 584U, // LDAXRB |
| 15460 | 584U, // LDAXRH |
| 15461 | 584U, // LDAXRW |
| 15462 | 584U, // LDAXRX |
| 15463 | 3U, // LDBFADD |
| 15464 | 3U, // LDBFADDA |
| 15465 | 3U, // LDBFADDAL |
| 15466 | 3U, // LDBFADDL |
| 15467 | 3U, // LDBFMAX |
| 15468 | 3U, // LDBFMAXA |
| 15469 | 3U, // LDBFMAXAL |
| 15470 | 3U, // LDBFMAXL |
| 15471 | 3U, // LDBFMAXNM |
| 15472 | 3U, // LDBFMAXNMA |
| 15473 | 3U, // LDBFMAXNMAL |
| 15474 | 3U, // LDBFMAXNML |
| 15475 | 3U, // LDBFMIN |
| 15476 | 3U, // LDBFMINA |
| 15477 | 3U, // LDBFMINAL |
| 15478 | 3U, // LDBFMINL |
| 15479 | 3U, // LDBFMINNM |
| 15480 | 3U, // LDBFMINNMA |
| 15481 | 3U, // LDBFMINNMAL |
| 15482 | 3U, // LDBFMINNML |
| 15483 | 3U, // LDCLRAB |
| 15484 | 3U, // LDCLRAH |
| 15485 | 3U, // LDCLRALB |
| 15486 | 3U, // LDCLRALH |
| 15487 | 3U, // LDCLRALW |
| 15488 | 3U, // LDCLRALX |
| 15489 | 3U, // LDCLRAW |
| 15490 | 3U, // LDCLRAX |
| 15491 | 3U, // LDCLRB |
| 15492 | 3U, // LDCLRH |
| 15493 | 3U, // LDCLRLB |
| 15494 | 3U, // LDCLRLH |
| 15495 | 3U, // LDCLRLW |
| 15496 | 3U, // LDCLRLX |
| 15497 | 147731U, // LDCLRP |
| 15498 | 147731U, // LDCLRPA |
| 15499 | 147731U, // LDCLRPAL |
| 15500 | 147731U, // LDCLRPL |
| 15501 | 3U, // LDCLRW |
| 15502 | 3U, // LDCLRX |
| 15503 | 3U, // LDEORAB |
| 15504 | 3U, // LDEORAH |
| 15505 | 3U, // LDEORALB |
| 15506 | 3U, // LDEORALH |
| 15507 | 3U, // LDEORALW |
| 15508 | 3U, // LDEORALX |
| 15509 | 3U, // LDEORAW |
| 15510 | 3U, // LDEORAX |
| 15511 | 3U, // LDEORB |
| 15512 | 3U, // LDEORH |
| 15513 | 3U, // LDEORLB |
| 15514 | 3U, // LDEORLH |
| 15515 | 3U, // LDEORLW |
| 15516 | 3U, // LDEORLX |
| 15517 | 3U, // LDEORW |
| 15518 | 3U, // LDEORX |
| 15519 | 3U, // LDFADDAD |
| 15520 | 3U, // LDFADDAH |
| 15521 | 3U, // LDFADDALD |
| 15522 | 3U, // LDFADDALH |
| 15523 | 3U, // LDFADDALS |
| 15524 | 3U, // LDFADDAS |
| 15525 | 3U, // LDFADDD |
| 15526 | 3U, // LDFADDH |
| 15527 | 3U, // LDFADDLD |
| 15528 | 3U, // LDFADDLH |
| 15529 | 3U, // LDFADDLS |
| 15530 | 3U, // LDFADDS |
| 15531 | 17594603U, // LDFF1B |
| 15532 | 17594603U, // LDFF1B_D |
| 15533 | 17594603U, // LDFF1B_H |
| 15534 | 17594603U, // LDFF1B_S |
| 15535 | 17856747U, // LDFF1D |
| 15536 | 18118891U, // LDFF1H |
| 15537 | 18118891U, // LDFF1H_D |
| 15538 | 18118891U, // LDFF1H_S |
| 15539 | 17594603U, // LDFF1SB_D |
| 15540 | 17594603U, // LDFF1SB_H |
| 15541 | 17594603U, // LDFF1SB_S |
| 15542 | 18118891U, // LDFF1SH_D |
| 15543 | 18118891U, // LDFF1SH_S |
| 15544 | 18643179U, // LDFF1SW_D |
| 15545 | 18643179U, // LDFF1W |
| 15546 | 18643179U, // LDFF1W_D |
| 15547 | 3U, // LDFMAXAD |
| 15548 | 3U, // LDFMAXAH |
| 15549 | 3U, // LDFMAXALD |
| 15550 | 3U, // LDFMAXALH |
| 15551 | 3U, // LDFMAXALS |
| 15552 | 3U, // LDFMAXAS |
| 15553 | 3U, // LDFMAXD |
| 15554 | 3U, // LDFMAXH |
| 15555 | 3U, // LDFMAXLD |
| 15556 | 3U, // LDFMAXLH |
| 15557 | 3U, // LDFMAXLS |
| 15558 | 3U, // LDFMAXNMAD |
| 15559 | 3U, // LDFMAXNMAH |
| 15560 | 3U, // LDFMAXNMALD |
| 15561 | 3U, // LDFMAXNMALH |
| 15562 | 3U, // LDFMAXNMALS |
| 15563 | 3U, // LDFMAXNMAS |
| 15564 | 3U, // LDFMAXNMD |
| 15565 | 3U, // LDFMAXNMH |
| 15566 | 3U, // LDFMAXNMLD |
| 15567 | 3U, // LDFMAXNMLH |
| 15568 | 3U, // LDFMAXNMLS |
| 15569 | 3U, // LDFMAXNMS |
| 15570 | 3U, // LDFMAXS |
| 15571 | 3U, // LDFMINAD |
| 15572 | 3U, // LDFMINAH |
| 15573 | 3U, // LDFMINALD |
| 15574 | 3U, // LDFMINALH |
| 15575 | 3U, // LDFMINALS |
| 15576 | 3U, // LDFMINAS |
| 15577 | 3U, // LDFMIND |
| 15578 | 3U, // LDFMINH |
| 15579 | 3U, // LDFMINLD |
| 15580 | 3U, // LDFMINLH |
| 15581 | 3U, // LDFMINLS |
| 15582 | 3U, // LDFMINNMAD |
| 15583 | 3U, // LDFMINNMAH |
| 15584 | 3U, // LDFMINNMALD |
| 15585 | 3U, // LDFMINNMALH |
| 15586 | 3U, // LDFMINNMALS |
| 15587 | 3U, // LDFMINNMAS |
| 15588 | 3U, // LDFMINNMD |
| 15589 | 3U, // LDFMINNMH |
| 15590 | 3U, // LDFMINNMLD |
| 15591 | 3U, // LDFMINNMLH |
| 15592 | 3U, // LDFMINNMLS |
| 15593 | 3U, // LDFMINNMS |
| 15594 | 3U, // LDFMINS |
| 15595 | 6965345U, // LDG |
| 15596 | 584U, // LDGM |
| 15597 | 6830352U, // LDIAPPW |
| 15598 | 21324049U, // LDIAPPWpost |
| 15599 | 6830352U, // LDIAPPX |
| 15600 | 21586193U, // LDIAPPXpost |
| 15601 | 584U, // LDLARB |
| 15602 | 584U, // LDLARH |
| 15603 | 584U, // LDLARW |
| 15604 | 584U, // LDLARX |
| 15605 | 843086059U, // LDNF1B_D_IMM |
| 15606 | 843086059U, // LDNF1B_H_IMM |
| 15607 | 843086059U, // LDNF1B_IMM |
| 15608 | 843086059U, // LDNF1B_S_IMM |
| 15609 | 843086059U, // LDNF1D_IMM |
| 15610 | 843086059U, // LDNF1H_D_IMM |
| 15611 | 843086059U, // LDNF1H_IMM |
| 15612 | 843086059U, // LDNF1H_S_IMM |
| 15613 | 843086059U, // LDNF1SB_D_IMM |
| 15614 | 843086059U, // LDNF1SB_H_IMM |
| 15615 | 843086059U, // LDNF1SB_S_IMM |
| 15616 | 843086059U, // LDNF1SH_D_IMM |
| 15617 | 843086059U, // LDNF1SH_S_IMM |
| 15618 | 843086059U, // LDNF1SW_D_IMM |
| 15619 | 843086059U, // LDNF1W_D_IMM |
| 15620 | 843086059U, // LDNF1W_IMM |
| 15621 | 872691984U, // LDNPDi |
| 15622 | 906246416U, // LDNPQi |
| 15623 | 939800848U, // LDNPSi |
| 15624 | 939800848U, // LDNPWi |
| 15625 | 872691984U, // LDNPXi |
| 15626 | 17594603U, // LDNT1B_2Z |
| 15627 | 853309675U, // LDNT1B_2Z_IMM |
| 15628 | 139883U, // LDNT1B_2Z_STRIDED |
| 15629 | 141931U, // LDNT1B_2Z_STRIDED_IMM |
| 15630 | 17594603U, // LDNT1B_4Z |
| 15631 | 854882539U, // LDNT1B_4Z_IMM |
| 15632 | 17594603U, // LDNT1B_4Z_STRIDED |
| 15633 | 854882539U, // LDNT1B_4Z_STRIDED_IMM |
| 15634 | 843086059U, // LDNT1B_ZRI |
| 15635 | 17594603U, // LDNT1B_ZRR |
| 15636 | 809531587U, // LDNT1B_ZZR_D |
| 15637 | 809531507U, // LDNT1B_ZZR_S |
| 15638 | 17856747U, // LDNT1D_2Z |
| 15639 | 853309675U, // LDNT1D_2Z_IMM |
| 15640 | 17856747U, // LDNT1D_2Z_STRIDED |
| 15641 | 853309675U, // LDNT1D_2Z_STRIDED_IMM |
| 15642 | 17856747U, // LDNT1D_4Z |
| 15643 | 854882539U, // LDNT1D_4Z_IMM |
| 15644 | 17856747U, // LDNT1D_4Z_STRIDED |
| 15645 | 854882539U, // LDNT1D_4Z_STRIDED_IMM |
| 15646 | 843086059U, // LDNT1D_ZRI |
| 15647 | 17856747U, // LDNT1D_ZRR |
| 15648 | 809531587U, // LDNT1D_ZZR_D |
| 15649 | 18118891U, // LDNT1H_2Z |
| 15650 | 853309675U, // LDNT1H_2Z_IMM |
| 15651 | 143979U, // LDNT1H_2Z_STRIDED |
| 15652 | 141931U, // LDNT1H_2Z_STRIDED_IMM |
| 15653 | 18118891U, // LDNT1H_4Z |
| 15654 | 854882539U, // LDNT1H_4Z_IMM |
| 15655 | 18118891U, // LDNT1H_4Z_STRIDED |
| 15656 | 854882539U, // LDNT1H_4Z_STRIDED_IMM |
| 15657 | 843086059U, // LDNT1H_ZRI |
| 15658 | 18118891U, // LDNT1H_ZRR |
| 15659 | 809531587U, // LDNT1H_ZZR_D |
| 15660 | 809531507U, // LDNT1H_ZZR_S |
| 15661 | 809531587U, // LDNT1SB_ZZR_D |
| 15662 | 809531507U, // LDNT1SB_ZZR_S |
| 15663 | 809531587U, // LDNT1SH_ZZR_D |
| 15664 | 809531507U, // LDNT1SH_ZZR_S |
| 15665 | 809531587U, // LDNT1SW_ZZR_D |
| 15666 | 18643179U, // LDNT1W_2Z |
| 15667 | 853309675U, // LDNT1W_2Z_IMM |
| 15668 | 18643179U, // LDNT1W_2Z_STRIDED |
| 15669 | 853309675U, // LDNT1W_2Z_STRIDED_IMM |
| 15670 | 18643179U, // LDNT1W_4Z |
| 15671 | 854882539U, // LDNT1W_4Z_IMM |
| 15672 | 18643179U, // LDNT1W_4Z_STRIDED |
| 15673 | 854882539U, // LDNT1W_4Z_STRIDED_IMM |
| 15674 | 843086059U, // LDNT1W_ZRI |
| 15675 | 18643179U, // LDNT1W_ZRR |
| 15676 | 809531587U, // LDNT1W_ZZR_D |
| 15677 | 809531507U, // LDNT1W_ZZR_S |
| 15678 | 872691984U, // LDPDi |
| 15679 | 994926865U, // LDPDpost |
| 15680 | 973431057U, // LDPDpre |
| 15681 | 906246416U, // LDPQi |
| 15682 | 1028481297U, // LDPQpost |
| 15683 | 1006985489U, // LDPQpre |
| 15684 | 939800848U, // LDPSWi |
| 15685 | 1062035729U, // LDPSWpost |
| 15686 | 1040539921U, // LDPSWpre |
| 15687 | 939800848U, // LDPSi |
| 15688 | 1062035729U, // LDPSpost |
| 15689 | 1040539921U, // LDPSpre |
| 15690 | 939800848U, // LDPWi |
| 15691 | 1062035729U, // LDPWpost |
| 15692 | 1040539921U, // LDPWpre |
| 15693 | 872691984U, // LDPXi |
| 15694 | 994926865U, // LDPXpost |
| 15695 | 973431057U, // LDPXpre |
| 15696 | 151648U, // LDRAAindexed |
| 15697 | 153697U, // LDRAAwriteback |
| 15698 | 151648U, // LDRABindexed |
| 15699 | 153697U, // LDRABwriteback |
| 15700 | 90761U, // LDRBBpost |
| 15701 | 22110305U, // LDRBBpre |
| 15702 | 1074018400U, // LDRBBroW |
| 15703 | 1107572832U, // LDRBBroX |
| 15704 | 155744U, // LDRBBui |
| 15705 | 90761U, // LDRBpost |
| 15706 | 22110305U, // LDRBpre |
| 15707 | 1074018400U, // LDRBroW |
| 15708 | 1107572832U, // LDRBroX |
| 15709 | 155744U, // LDRBui |
| 15710 | 1U, // LDRDl |
| 15711 | 90761U, // LDRDpost |
| 15712 | 22110305U, // LDRDpre |
| 15713 | 1141127264U, // LDRDroW |
| 15714 | 1174681696U, // LDRDroX |
| 15715 | 157792U, // LDRDui |
| 15716 | 90761U, // LDRHHpost |
| 15717 | 22110305U, // LDRHHpre |
| 15718 | 1208236128U, // LDRHHroW |
| 15719 | 1241790560U, // LDRHHroX |
| 15720 | 159840U, // LDRHHui |
| 15721 | 90761U, // LDRHpost |
| 15722 | 22110305U, // LDRHpre |
| 15723 | 1208236128U, // LDRHroW |
| 15724 | 1241790560U, // LDRHroX |
| 15725 | 159840U, // LDRHui |
| 15726 | 1U, // LDRQl |
| 15727 | 90761U, // LDRQpost |
| 15728 | 22110305U, // LDRQpre |
| 15729 | 1275344992U, // LDRQroW |
| 15730 | 1308899424U, // LDRQroX |
| 15731 | 161888U, // LDRQui |
| 15732 | 90761U, // LDRSBWpost |
| 15733 | 22110305U, // LDRSBWpre |
| 15734 | 1074018400U, // LDRSBWroW |
| 15735 | 1107572832U, // LDRSBWroX |
| 15736 | 155744U, // LDRSBWui |
| 15737 | 90761U, // LDRSBXpost |
| 15738 | 22110305U, // LDRSBXpre |
| 15739 | 1074018400U, // LDRSBXroW |
| 15740 | 1107572832U, // LDRSBXroX |
| 15741 | 155744U, // LDRSBXui |
| 15742 | 90761U, // LDRSHWpost |
| 15743 | 22110305U, // LDRSHWpre |
| 15744 | 1208236128U, // LDRSHWroW |
| 15745 | 1241790560U, // LDRSHWroX |
| 15746 | 159840U, // LDRSHWui |
| 15747 | 90761U, // LDRSHXpost |
| 15748 | 22110305U, // LDRSHXpre |
| 15749 | 1208236128U, // LDRSHXroW |
| 15750 | 1241790560U, // LDRSHXroX |
| 15751 | 159840U, // LDRSHXui |
| 15752 | 1U, // LDRSWl |
| 15753 | 90761U, // LDRSWpost |
| 15754 | 22110305U, // LDRSWpre |
| 15755 | 1342453856U, // LDRSWroW |
| 15756 | 1376008288U, // LDRSWroX |
| 15757 | 163936U, // LDRSWui |
| 15758 | 1U, // LDRSl |
| 15759 | 90761U, // LDRSpost |
| 15760 | 22110305U, // LDRSpre |
| 15761 | 1342453856U, // LDRSroW |
| 15762 | 1376008288U, // LDRSroX |
| 15763 | 163936U, // LDRSui |
| 15764 | 1U, // LDRWl |
| 15765 | 90761U, // LDRWpost |
| 15766 | 22110305U, // LDRWpre |
| 15767 | 1342453856U, // LDRWroW |
| 15768 | 1376008288U, // LDRWroX |
| 15769 | 163936U, // LDRWui |
| 15770 | 1U, // LDRXl |
| 15771 | 90761U, // LDRXpost |
| 15772 | 22110305U, // LDRXpre |
| 15773 | 1141127264U, // LDRXroW |
| 15774 | 1174681696U, // LDRXroX |
| 15775 | 157792U, // LDRXui |
| 15776 | 22296672U, // LDR_PXI |
| 15777 | 584U, // LDR_TX |
| 15778 | 0U, // LDR_ZA |
| 15779 | 22296672U, // LDR_ZXI |
| 15780 | 3U, // LDSETAB |
| 15781 | 3U, // LDSETAH |
| 15782 | 3U, // LDSETALB |
| 15783 | 3U, // LDSETALH |
| 15784 | 3U, // LDSETALW |
| 15785 | 3U, // LDSETALX |
| 15786 | 3U, // LDSETAW |
| 15787 | 3U, // LDSETAX |
| 15788 | 3U, // LDSETB |
| 15789 | 3U, // LDSETH |
| 15790 | 3U, // LDSETLB |
| 15791 | 3U, // LDSETLH |
| 15792 | 3U, // LDSETLW |
| 15793 | 3U, // LDSETLX |
| 15794 | 147731U, // LDSETP |
| 15795 | 147731U, // LDSETPA |
| 15796 | 147731U, // LDSETPAL |
| 15797 | 147731U, // LDSETPL |
| 15798 | 3U, // LDSETW |
| 15799 | 3U, // LDSETX |
| 15800 | 3U, // LDSMAXAB |
| 15801 | 3U, // LDSMAXAH |
| 15802 | 3U, // LDSMAXALB |
| 15803 | 3U, // LDSMAXALH |
| 15804 | 3U, // LDSMAXALW |
| 15805 | 3U, // LDSMAXALX |
| 15806 | 3U, // LDSMAXAW |
| 15807 | 3U, // LDSMAXAX |
| 15808 | 3U, // LDSMAXB |
| 15809 | 3U, // LDSMAXH |
| 15810 | 3U, // LDSMAXLB |
| 15811 | 3U, // LDSMAXLH |
| 15812 | 3U, // LDSMAXLW |
| 15813 | 3U, // LDSMAXLX |
| 15814 | 3U, // LDSMAXW |
| 15815 | 3U, // LDSMAXX |
| 15816 | 3U, // LDSMINAB |
| 15817 | 3U, // LDSMINAH |
| 15818 | 3U, // LDSMINALB |
| 15819 | 3U, // LDSMINALH |
| 15820 | 3U, // LDSMINALW |
| 15821 | 3U, // LDSMINALX |
| 15822 | 3U, // LDSMINAW |
| 15823 | 3U, // LDSMINAX |
| 15824 | 3U, // LDSMINB |
| 15825 | 3U, // LDSMINH |
| 15826 | 3U, // LDSMINLB |
| 15827 | 3U, // LDSMINLH |
| 15828 | 3U, // LDSMINLW |
| 15829 | 3U, // LDSMINLX |
| 15830 | 3U, // LDSMINW |
| 15831 | 3U, // LDSMINX |
| 15832 | 3U, // LDTADDALW |
| 15833 | 3U, // LDTADDALX |
| 15834 | 3U, // LDTADDAW |
| 15835 | 3U, // LDTADDAX |
| 15836 | 3U, // LDTADDLW |
| 15837 | 3U, // LDTADDLX |
| 15838 | 3U, // LDTADDW |
| 15839 | 3U, // LDTADDX |
| 15840 | 3U, // LDTCLRALW |
| 15841 | 3U, // LDTCLRALX |
| 15842 | 3U, // LDTCLRAW |
| 15843 | 3U, // LDTCLRAX |
| 15844 | 3U, // LDTCLRLW |
| 15845 | 3U, // LDTCLRLX |
| 15846 | 3U, // LDTCLRW |
| 15847 | 3U, // LDTCLRX |
| 15848 | 906246416U, // LDTNPQi |
| 15849 | 872691984U, // LDTNPXi |
| 15850 | 906246416U, // LDTPQi |
| 15851 | 1028481297U, // LDTPQpost |
| 15852 | 1006985489U, // LDTPQpre |
| 15853 | 872691984U, // LDTPi |
| 15854 | 994926865U, // LDTPpost |
| 15855 | 973431057U, // LDTPpre |
| 15856 | 6830176U, // LDTRBi |
| 15857 | 6830176U, // LDTRHi |
| 15858 | 6830176U, // LDTRSBWi |
| 15859 | 6830176U, // LDTRSBXi |
| 15860 | 6830176U, // LDTRSHWi |
| 15861 | 6830176U, // LDTRSHXi |
| 15862 | 6830176U, // LDTRSWi |
| 15863 | 6830176U, // LDTRWi |
| 15864 | 6830176U, // LDTRXi |
| 15865 | 3U, // LDTSETALW |
| 15866 | 3U, // LDTSETALX |
| 15867 | 3U, // LDTSETAW |
| 15868 | 3U, // LDTSETAX |
| 15869 | 3U, // LDTSETLW |
| 15870 | 3U, // LDTSETLX |
| 15871 | 3U, // LDTSETW |
| 15872 | 3U, // LDTSETX |
| 15873 | 584U, // LDTXRWr |
| 15874 | 584U, // LDTXRXr |
| 15875 | 3U, // LDUMAXAB |
| 15876 | 3U, // LDUMAXAH |
| 15877 | 3U, // LDUMAXALB |
| 15878 | 3U, // LDUMAXALH |
| 15879 | 3U, // LDUMAXALW |
| 15880 | 3U, // LDUMAXALX |
| 15881 | 3U, // LDUMAXAW |
| 15882 | 3U, // LDUMAXAX |
| 15883 | 3U, // LDUMAXB |
| 15884 | 3U, // LDUMAXH |
| 15885 | 3U, // LDUMAXLB |
| 15886 | 3U, // LDUMAXLH |
| 15887 | 3U, // LDUMAXLW |
| 15888 | 3U, // LDUMAXLX |
| 15889 | 3U, // LDUMAXW |
| 15890 | 3U, // LDUMAXX |
| 15891 | 3U, // LDUMINAB |
| 15892 | 3U, // LDUMINAH |
| 15893 | 3U, // LDUMINALB |
| 15894 | 3U, // LDUMINALH |
| 15895 | 3U, // LDUMINALW |
| 15896 | 3U, // LDUMINALX |
| 15897 | 3U, // LDUMINAW |
| 15898 | 3U, // LDUMINAX |
| 15899 | 3U, // LDUMINB |
| 15900 | 3U, // LDUMINH |
| 15901 | 3U, // LDUMINLB |
| 15902 | 3U, // LDUMINLH |
| 15903 | 3U, // LDUMINLW |
| 15904 | 3U, // LDUMINLX |
| 15905 | 3U, // LDUMINW |
| 15906 | 3U, // LDUMINX |
| 15907 | 6830176U, // LDURBBi |
| 15908 | 6830176U, // LDURBi |
| 15909 | 6830176U, // LDURDi |
| 15910 | 6830176U, // LDURHHi |
| 15911 | 6830176U, // LDURHi |
| 15912 | 6830176U, // LDURQi |
| 15913 | 6830176U, // LDURSBWi |
| 15914 | 6830176U, // LDURSBXi |
| 15915 | 6830176U, // LDURSHWi |
| 15916 | 6830176U, // LDURSHXi |
| 15917 | 6830176U, // LDURSWi |
| 15918 | 6830176U, // LDURSi |
| 15919 | 6830176U, // LDURWi |
| 15920 | 6830176U, // LDURXi |
| 15921 | 6830352U, // LDXPW |
| 15922 | 6830352U, // LDXPX |
| 15923 | 584U, // LDXRB |
| 15924 | 584U, // LDXRH |
| 15925 | 584U, // LDXRW |
| 15926 | 584U, // LDXRX |
| 15927 | 33824776U, // LSLR_ZPmZ_B |
| 15928 | 67381256U, // LSLR_ZPmZ_D |
| 15929 | 102266912U, // LSLR_ZPmZ_H |
| 15930 | 134492168U, // LSLR_ZPmZ_S |
| 15931 | 14432U, // LSLVWr |
| 15932 | 14432U, // LSLVXr |
| 15933 | 67379208U, // LSL_WIDE_ZPmZ_B |
| 15934 | 4487200U, // LSL_WIDE_ZPmZ_H |
| 15935 | 67383304U, // LSL_WIDE_ZPmZ_S |
| 15936 | 10336U, // LSL_WIDE_ZZZ_B |
| 15937 | 4288U, // LSL_WIDE_ZZZ_H |
| 15938 | 10336U, // LSL_WIDE_ZZZ_S |
| 15939 | 270344U, // LSL_ZPmI_B |
| 15940 | 272392U, // LSL_ZPmI_D |
| 15941 | 104888352U, // LSL_ZPmI_H |
| 15942 | 274440U, // LSL_ZPmI_S |
| 15943 | 33824776U, // LSL_ZPmZ_B |
| 15944 | 67381256U, // LSL_ZPmZ_D |
| 15945 | 102266912U, // LSL_ZPmZ_H |
| 15946 | 134492168U, // LSL_ZPmZ_S |
| 15947 | 14432U, // LSL_ZZI_B |
| 15948 | 14432U, // LSL_ZZI_D |
| 15949 | 4328U, // LSL_ZZI_H |
| 15950 | 14432U, // LSL_ZZI_S |
| 15951 | 33824776U, // LSRR_ZPmZ_B |
| 15952 | 67381256U, // LSRR_ZPmZ_D |
| 15953 | 102266912U, // LSRR_ZPmZ_H |
| 15954 | 134492168U, // LSRR_ZPmZ_S |
| 15955 | 14432U, // LSRVWr |
| 15956 | 14432U, // LSRVXr |
| 15957 | 67379208U, // LSR_WIDE_ZPmZ_B |
| 15958 | 4487200U, // LSR_WIDE_ZPmZ_H |
| 15959 | 67383304U, // LSR_WIDE_ZPmZ_S |
| 15960 | 10336U, // LSR_WIDE_ZZZ_B |
| 15961 | 4288U, // LSR_WIDE_ZZZ_H |
| 15962 | 10336U, // LSR_WIDE_ZZZ_S |
| 15963 | 270344U, // LSR_ZPmI_B |
| 15964 | 272392U, // LSR_ZPmI_D |
| 15965 | 104888352U, // LSR_ZPmI_H |
| 15966 | 274440U, // LSR_ZPmI_S |
| 15967 | 33824776U, // LSR_ZPmZ_B |
| 15968 | 67381256U, // LSR_ZPmZ_D |
| 15969 | 102266912U, // LSR_ZPmZ_H |
| 15970 | 134492168U, // LSR_ZPmZ_S |
| 15971 | 14432U, // LSR_ZZI_B |
| 15972 | 14432U, // LSR_ZZI_D |
| 15973 | 4328U, // LSR_ZZI_H |
| 15974 | 14432U, // LSR_ZZI_S |
| 15975 | 659U, // LUT2_B |
| 15976 | 3U, // LUT2_H |
| 15977 | 659U, // LUT4_B |
| 15978 | 3U, // LUT4_H |
| 15979 | 78488U, // LUTI2_2ZTZI_B |
| 15980 | 78488U, // LUTI2_2ZTZI_H |
| 15981 | 78488U, // LUTI2_2ZTZI_S |
| 15982 | 78488U, // LUTI2_4ZTZI_B |
| 15983 | 78488U, // LUTI2_4ZTZI_H |
| 15984 | 78488U, // LUTI2_4ZTZI_S |
| 15985 | 11962464U, // LUTI2_S_2ZTZI_B |
| 15986 | 11962464U, // LUTI2_S_2ZTZI_H |
| 15987 | 78488U, // LUTI2_S_4ZTZI_B |
| 15988 | 78488U, // LUTI2_S_4ZTZI_H |
| 15989 | 11962464U, // LUTI2_ZTZI_B |
| 15990 | 78488U, // LUTI2_ZTZI_H |
| 15991 | 11962464U, // LUTI2_ZTZI_S |
| 15992 | 78490U, // LUTI2_ZZZI_B |
| 15993 | 78488U, // LUTI2_ZZZI_H |
| 15994 | 78488U, // LUTI4_2ZTZI_B |
| 15995 | 78488U, // LUTI4_2ZTZI_H |
| 15996 | 78488U, // LUTI4_2ZTZI_S |
| 15997 | 78488U, // LUTI4_4ZTZI_H |
| 15998 | 78488U, // LUTI4_4ZTZI_S |
| 15999 | 4768U, // LUTI4_4ZZT2Z |
| 16000 | 11962464U, // LUTI4_S_2ZTZI_B |
| 16001 | 11962464U, // LUTI4_S_2ZTZI_H |
| 16002 | 78488U, // LUTI4_S_4ZTZI_H |
| 16003 | 4768U, // LUTI4_S_4ZZT2Z |
| 16004 | 78488U, // LUTI4_Z2ZZI |
| 16005 | 11962464U, // LUTI4_ZTZI_B |
| 16006 | 78488U, // LUTI4_ZTZI_H |
| 16007 | 11962464U, // LUTI4_ZTZI_S |
| 16008 | 78490U, // LUTI4_ZZZI_B |
| 16009 | 78488U, // LUTI4_ZZZI_H |
| 16010 | 78496U, // LUTI6_4Z2Z2ZI |
| 16011 | 4768U, // LUTI6_4ZT3Z |
| 16012 | 78496U, // LUTI6_S_4Z2Z2ZI |
| 16013 | 4768U, // LUTI6_S_4ZT3Z |
| 16014 | 4762U, // LUTI6_Z2ZZ |
| 16015 | 78488U, // LUTI6_Z2ZZI_H |
| 16016 | 165984U, // LUTI6_ZTZ |
| 16017 | 276576U, // MADDPT |
| 16018 | 276576U, // MADDWrrr |
| 16019 | 276576U, // MADDXrrr |
| 16020 | 2144U, // MAD_CPA |
| 16021 | 1409548296U, // MAD_ZPmZZ_B |
| 16022 | 604243976U, // MAD_ZPmZZ_D |
| 16023 | 106985488U, // MAD_ZPmZZ_H |
| 16024 | 637802504U, // MAD_ZPmZZ_S |
| 16025 | 33824792U, // MATCH_PPzZZ_B |
| 16026 | 102266912U, // MATCH_PPzZZ_H |
| 16027 | 2144U, // MLA_CPA |
| 16028 | 1409548296U, // MLA_ZPmZZ_B |
| 16029 | 604243976U, // MLA_ZPmZZ_D |
| 16030 | 106985488U, // MLA_ZPmZZ_H |
| 16031 | 637802504U, // MLA_ZPmZZ_S |
| 16032 | 106432608U, // MLA_ZZZI_D |
| 16033 | 86032U, // MLA_ZZZI_H |
| 16034 | 106436704U, // MLA_ZZZI_S |
| 16035 | 1863832U, // MLAv16i8 |
| 16036 | 2125984U, // MLAv2i32 |
| 16037 | 244609184U, // MLAv2i32_indexed |
| 16038 | 2388136U, // MLAv4i16 |
| 16039 | 240939176U, // MLAv4i16_indexed |
| 16040 | 815240U, // MLAv4i32 |
| 16041 | 244609160U, // MLAv4i32_indexed |
| 16042 | 1077392U, // MLAv8i16 |
| 16043 | 240939152U, // MLAv8i16_indexed |
| 16044 | 2650288U, // MLAv8i8 |
| 16045 | 1409548296U, // MLS_ZPmZZ_B |
| 16046 | 604243976U, // MLS_ZPmZZ_D |
| 16047 | 106985488U, // MLS_ZPmZZ_H |
| 16048 | 637802504U, // MLS_ZPmZZ_S |
| 16049 | 106432608U, // MLS_ZZZI_D |
| 16050 | 86032U, // MLS_ZZZI_H |
| 16051 | 106436704U, // MLS_ZZZI_S |
| 16052 | 1863832U, // MLSv16i8 |
| 16053 | 2125984U, // MLSv2i32 |
| 16054 | 244609184U, // MLSv2i32_indexed |
| 16055 | 2388136U, // MLSv4i16 |
| 16056 | 240939176U, // MLSv4i16_indexed |
| 16057 | 815240U, // MLSv4i32 |
| 16058 | 244609160U, // MLSv4i32_indexed |
| 16059 | 1077392U, // MLSv8i16 |
| 16060 | 240939152U, // MLSv8i16_indexed |
| 16061 | 2650288U, // MLSv8i8 |
| 16062 | 3U, // MOPSSETGE |
| 16063 | 3U, // MOPSSETGEN |
| 16064 | 3U, // MOPSSETGET |
| 16065 | 3U, // MOPSSETGETN |
| 16066 | 4U, // MOVAZ_2ZMI_H_B |
| 16067 | 4U, // MOVAZ_2ZMI_H_D |
| 16068 | 4U, // MOVAZ_2ZMI_H_H |
| 16069 | 4U, // MOVAZ_2ZMI_H_S |
| 16070 | 4U, // MOVAZ_2ZMI_V_B |
| 16071 | 4U, // MOVAZ_2ZMI_V_D |
| 16072 | 4U, // MOVAZ_2ZMI_V_H |
| 16073 | 4U, // MOVAZ_2ZMI_V_S |
| 16074 | 4U, // MOVAZ_4ZMI_H_B |
| 16075 | 4U, // MOVAZ_4ZMI_H_D |
| 16076 | 4U, // MOVAZ_4ZMI_H_H |
| 16077 | 4U, // MOVAZ_4ZMI_H_S |
| 16078 | 4U, // MOVAZ_4ZMI_V_B |
| 16079 | 4U, // MOVAZ_4ZMI_V_D |
| 16080 | 4U, // MOVAZ_4ZMI_V_H |
| 16081 | 4U, // MOVAZ_4ZMI_V_S |
| 16082 | 4U, // MOVAZ_VG2_2ZMXI |
| 16083 | 4U, // MOVAZ_VG4_4ZMXI |
| 16084 | 4U, // MOVAZ_ZMI_H_B |
| 16085 | 4U, // MOVAZ_ZMI_H_D |
| 16086 | 168035U, // MOVAZ_ZMI_H_H |
| 16087 | 168035U, // MOVAZ_ZMI_H_Q |
| 16088 | 4U, // MOVAZ_ZMI_H_S |
| 16089 | 4U, // MOVAZ_ZMI_V_B |
| 16090 | 4U, // MOVAZ_ZMI_V_D |
| 16091 | 168035U, // MOVAZ_ZMI_V_H |
| 16092 | 168035U, // MOVAZ_ZMI_V_Q |
| 16093 | 4U, // MOVAZ_ZMI_V_S |
| 16094 | 170081U, // MOVA_2ZMXI_H_B |
| 16095 | 170081U, // MOVA_2ZMXI_H_D |
| 16096 | 170081U, // MOVA_2ZMXI_H_H |
| 16097 | 170081U, // MOVA_2ZMXI_H_S |
| 16098 | 170081U, // MOVA_2ZMXI_V_B |
| 16099 | 170081U, // MOVA_2ZMXI_V_D |
| 16100 | 170081U, // MOVA_2ZMXI_V_H |
| 16101 | 170081U, // MOVA_2ZMXI_V_S |
| 16102 | 172129U, // MOVA_4ZMXI_H_B |
| 16103 | 172129U, // MOVA_4ZMXI_H_D |
| 16104 | 172129U, // MOVA_4ZMXI_H_H |
| 16105 | 172129U, // MOVA_4ZMXI_H_S |
| 16106 | 172129U, // MOVA_4ZMXI_V_B |
| 16107 | 172129U, // MOVA_4ZMXI_V_D |
| 16108 | 172129U, // MOVA_4ZMXI_V_H |
| 16109 | 172129U, // MOVA_4ZMXI_V_S |
| 16110 | 174760U, // MOVA_MXI2Z_H_B |
| 16111 | 176808U, // MOVA_MXI2Z_H_D |
| 16112 | 178856U, // MOVA_MXI2Z_H_H |
| 16113 | 180904U, // MOVA_MXI2Z_H_S |
| 16114 | 174760U, // MOVA_MXI2Z_V_B |
| 16115 | 176808U, // MOVA_MXI2Z_V_D |
| 16116 | 178856U, // MOVA_MXI2Z_V_H |
| 16117 | 180904U, // MOVA_MXI2Z_V_S |
| 16118 | 174768U, // MOVA_MXI4Z_H_B |
| 16119 | 176816U, // MOVA_MXI4Z_H_D |
| 16120 | 178864U, // MOVA_MXI4Z_H_H |
| 16121 | 180912U, // MOVA_MXI4Z_H_S |
| 16122 | 174768U, // MOVA_MXI4Z_V_B |
| 16123 | 176816U, // MOVA_MXI4Z_V_D |
| 16124 | 178864U, // MOVA_MXI4Z_V_H |
| 16125 | 180912U, // MOVA_MXI4Z_V_S |
| 16126 | 4U, // MOVA_VG2_2ZMXI |
| 16127 | 4296U, // MOVA_VG2_MXI2Z |
| 16128 | 4U, // MOVA_VG4_4ZMXI |
| 16129 | 4297U, // MOVA_VG4_MXI4Z |
| 16130 | 4U, // MOVID |
| 16131 | 4U, // MOVIv16b_ns |
| 16132 | 4U, // MOVIv2d_ns |
| 16133 | 700U, // MOVIv2i32 |
| 16134 | 700U, // MOVIv2s_msl |
| 16135 | 700U, // MOVIv4i16 |
| 16136 | 700U, // MOVIv4i32 |
| 16137 | 700U, // MOVIv4s_msl |
| 16138 | 4U, // MOVIv8b_ns |
| 16139 | 700U, // MOVIv8i16 |
| 16140 | 1U, // MOVKWi |
| 16141 | 1U, // MOVKXi |
| 16142 | 700U, // MOVNWi |
| 16143 | 700U, // MOVNXi |
| 16144 | 8U, // MOVPRFX_ZPmZ_B |
| 16145 | 2056U, // MOVPRFX_ZPmZ_D |
| 16146 | 4112U, // MOVPRFX_ZPmZ_H |
| 16147 | 6152U, // MOVPRFX_ZPmZ_S |
| 16148 | 8216U, // MOVPRFX_ZPzZ_B |
| 16149 | 10264U, // MOVPRFX_ZPzZ_D |
| 16150 | 4128U, // MOVPRFX_ZPzZ_H |
| 16151 | 12312U, // MOVPRFX_ZPzZ_S |
| 16152 | 0U, // MOVPRFX_ZZ |
| 16153 | 4U, // MOVT_TIX |
| 16154 | 4U, // MOVT_TIZ |
| 16155 | 704U, // MOVT_XTI |
| 16156 | 700U, // MOVZWi |
| 16157 | 700U, // MOVZXi |
| 16158 | 0U, // MRRS |
| 16159 | 4U, // MRS |
| 16160 | 1409548296U, // MSB_ZPmZZ_B |
| 16161 | 604243976U, // MSB_ZPmZZ_D |
| 16162 | 106985488U, // MSB_ZPmZZ_H |
| 16163 | 637802504U, // MSB_ZPmZZ_S |
| 16164 | 1U, // MSR |
| 16165 | 0U, // MSRR |
| 16166 | 0U, // MSRpstateImm1 |
| 16167 | 0U, // MSRpstateImm4 |
| 16168 | 0U, // MSRpstatesvcrImm1 |
| 16169 | 276576U, // MSUBPT |
| 16170 | 276576U, // MSUBWrrr |
| 16171 | 276576U, // MSUBXrrr |
| 16172 | 14432U, // MUL_ZI_B |
| 16173 | 14432U, // MUL_ZI_D |
| 16174 | 4328U, // MUL_ZI_H |
| 16175 | 14432U, // MUL_ZI_S |
| 16176 | 33824776U, // MUL_ZPmZ_B |
| 16177 | 67381256U, // MUL_ZPmZ_D |
| 16178 | 102266912U, // MUL_ZPmZ_H |
| 16179 | 134492168U, // MUL_ZPmZ_S |
| 16180 | 11806816U, // MUL_ZZZI_D |
| 16181 | 77856U, // MUL_ZZZI_H |
| 16182 | 11808864U, // MUL_ZZZI_S |
| 16183 | 8288U, // MUL_ZZZ_B |
| 16184 | 10336U, // MUL_ZZZ_D |
| 16185 | 4128U, // MUL_ZZZ_H |
| 16186 | 12384U, // MUL_ZZZ_S |
| 16187 | 1861784U, // MULv16i8 |
| 16188 | 2123936U, // MULv2i32 |
| 16189 | 747923616U, // MULv2i32_indexed |
| 16190 | 2386088U, // MULv4i16 |
| 16191 | 744253608U, // MULv4i16_indexed |
| 16192 | 813192U, // MULv4i32 |
| 16193 | 747923592U, // MULv4i32_indexed |
| 16194 | 1075344U, // MULv8i16 |
| 16195 | 744253584U, // MULv8i16_indexed |
| 16196 | 2648240U, // MULv8i8 |
| 16197 | 700U, // MVNIv2i32 |
| 16198 | 700U, // MVNIv2s_msl |
| 16199 | 700U, // MVNIv4i16 |
| 16200 | 700U, // MVNIv4i32 |
| 16201 | 700U, // MVNIv4s_msl |
| 16202 | 700U, // MVNIv8i16 |
| 16203 | 33824792U, // NANDS_PPzPP |
| 16204 | 33824792U, // NAND_PPzPP |
| 16205 | 67381344U, // NBSL_ZZZZ |
| 16206 | 8U, // NEG_ZPmZ_B |
| 16207 | 2056U, // NEG_ZPmZ_D |
| 16208 | 4112U, // NEG_ZPmZ_H |
| 16209 | 6152U, // NEG_ZPmZ_S |
| 16210 | 8216U, // NEG_ZPzZ_B |
| 16211 | 10264U, // NEG_ZPzZ_D |
| 16212 | 4128U, // NEG_ZPzZ_H |
| 16213 | 12312U, // NEG_ZPzZ_S |
| 16214 | 40U, // NEGv16i8 |
| 16215 | 0U, // NEGv1i64 |
| 16216 | 48U, // NEGv2i32 |
| 16217 | 56U, // NEGv2i64 |
| 16218 | 64U, // NEGv4i16 |
| 16219 | 72U, // NEGv4i32 |
| 16220 | 80U, // NEGv8i16 |
| 16221 | 88U, // NEGv8i8 |
| 16222 | 33824792U, // NMATCH_PPzZZ_B |
| 16223 | 102266912U, // NMATCH_PPzZZ_H |
| 16224 | 0U, // NOP |
| 16225 | 33824792U, // NORS_PPzPP |
| 16226 | 33824792U, // NOR_PPzPP |
| 16227 | 8U, // NOT_ZPmZ_B |
| 16228 | 2056U, // NOT_ZPmZ_D |
| 16229 | 4112U, // NOT_ZPmZ_H |
| 16230 | 6152U, // NOT_ZPmZ_S |
| 16231 | 8216U, // NOT_ZPzZ_B |
| 16232 | 10264U, // NOT_ZPzZ_D |
| 16233 | 4128U, // NOT_ZPzZ_H |
| 16234 | 12312U, // NOT_ZPzZ_S |
| 16235 | 40U, // NOTv16i8 |
| 16236 | 88U, // NOTv8i8 |
| 16237 | 33824792U, // ORNS_PPzPP |
| 16238 | 34912U, // ORNWrs |
| 16239 | 34912U, // ORNXrs |
| 16240 | 33824792U, // ORN_PPzPP |
| 16241 | 1861784U, // ORNv16i8 |
| 16242 | 2648240U, // ORNv8i8 |
| 16243 | 8288U, // ORQV_VPZ_B |
| 16244 | 10336U, // ORQV_VPZ_D |
| 16245 | 22624U, // ORQV_VPZ_H |
| 16246 | 12384U, // ORQV_VPZ_S |
| 16247 | 33824792U, // ORRS_PPzPP |
| 16248 | 79968U, // ORRWri |
| 16249 | 34912U, // ORRWrs |
| 16250 | 82016U, // ORRXri |
| 16251 | 34912U, // ORRXrs |
| 16252 | 33824792U, // ORR_PPzPP |
| 16253 | 82016U, // ORR_ZI |
| 16254 | 33824776U, // ORR_ZPmZ_B |
| 16255 | 67381256U, // ORR_ZPmZ_D |
| 16256 | 102266912U, // ORR_ZPmZ_H |
| 16257 | 134492168U, // ORR_ZPmZ_S |
| 16258 | 10336U, // ORR_ZZZ |
| 16259 | 1861784U, // ORRv16i8 |
| 16260 | 1U, // ORRv2i32 |
| 16261 | 1U, // ORRv4i16 |
| 16262 | 1U, // ORRv4i32 |
| 16263 | 1U, // ORRv8i16 |
| 16264 | 2648240U, // ORRv8i8 |
| 16265 | 0U, // ORV_VPZ_B |
| 16266 | 1U, // ORV_VPZ_D |
| 16267 | 1U, // ORV_VPZ_H |
| 16268 | 1U, // ORV_VPZ_S |
| 16269 | 1U, // PACDA |
| 16270 | 1U, // PACDB |
| 16271 | 0U, // PACDZA |
| 16272 | 0U, // PACDZB |
| 16273 | 14432U, // PACGA |
| 16274 | 1U, // PACIA |
| 16275 | 0U, // PACIA1716 |
| 16276 | 0U, // PACIA171615 |
| 16277 | 0U, // PACIASP |
| 16278 | 0U, // PACIASPPC |
| 16279 | 0U, // PACIAZ |
| 16280 | 1U, // PACIB |
| 16281 | 0U, // PACIB1716 |
| 16282 | 0U, // PACIB171615 |
| 16283 | 0U, // PACIBSP |
| 16284 | 0U, // PACIBSPPC |
| 16285 | 0U, // PACIBZ |
| 16286 | 0U, // PACIZA |
| 16287 | 0U, // PACIZB |
| 16288 | 0U, // PACM |
| 16289 | 0U, // PACNBIASPPC |
| 16290 | 0U, // PACNBIBSPPC |
| 16291 | 2U, // PEXT_2PCI_B |
| 16292 | 2U, // PEXT_2PCI_D |
| 16293 | 2U, // PEXT_2PCI_H |
| 16294 | 2U, // PEXT_2PCI_S |
| 16295 | 387U, // PEXT_PCI_B |
| 16296 | 387U, // PEXT_PCI_D |
| 16297 | 2U, // PEXT_PCI_H |
| 16298 | 387U, // PEXT_PCI_S |
| 16299 | 0U, // PFALSE |
| 16300 | 8288U, // PFIRST_B |
| 16301 | 472U, // PMLAL_2ZZZ_Q |
| 16302 | 384U, // PMOV_PZI_B |
| 16303 | 384U, // PMOV_PZI_D |
| 16304 | 2U, // PMOV_PZI_H |
| 16305 | 384U, // PMOV_PZI_S |
| 16306 | 3U, // PMOV_ZIP_B |
| 16307 | 3U, // PMOV_ZIP_D |
| 16308 | 1U, // PMOV_ZIP_H |
| 16309 | 3U, // PMOV_ZIP_S |
| 16310 | 12384U, // PMULLB_ZZZ_D |
| 16311 | 184U, // PMULLB_ZZZ_H |
| 16312 | 0U, // PMULLB_ZZZ_Q |
| 16313 | 12384U, // PMULLT_ZZZ_D |
| 16314 | 184U, // PMULLT_ZZZ_H |
| 16315 | 0U, // PMULLT_ZZZ_Q |
| 16316 | 0U, // PMULL_2ZZZ_Q |
| 16317 | 1861784U, // PMULLv16i8 |
| 16318 | 4U, // PMULLv1i64 |
| 16319 | 4U, // PMULLv2i64 |
| 16320 | 2648240U, // PMULLv8i8 |
| 16321 | 8288U, // PMUL_ZZZ_B |
| 16322 | 1861784U, // PMULv16i8 |
| 16323 | 2648240U, // PMULv8i8 |
| 16324 | 8288U, // PNEXT_B |
| 16325 | 10336U, // PNEXT_D |
| 16326 | 4128U, // PNEXT_H |
| 16327 | 12384U, // PNEXT_S |
| 16328 | 182640U, // PRFB_D_PZI |
| 16329 | 712U, // PRFB_D_SCALED |
| 16330 | 720U, // PRFB_D_SXTW_SCALED |
| 16331 | 728U, // PRFB_D_UXTW_SCALED |
| 16332 | 184688U, // PRFB_PRI |
| 16333 | 736U, // PRFB_PRR |
| 16334 | 182640U, // PRFB_S_PZI |
| 16335 | 744U, // PRFB_S_SXTW_SCALED |
| 16336 | 752U, // PRFB_S_UXTW_SCALED |
| 16337 | 760U, // PRFD_D_PZI |
| 16338 | 768U, // PRFD_D_SCALED |
| 16339 | 776U, // PRFD_D_SXTW_SCALED |
| 16340 | 784U, // PRFD_D_UXTW_SCALED |
| 16341 | 184688U, // PRFD_PRI |
| 16342 | 792U, // PRFD_PRR |
| 16343 | 760U, // PRFD_S_PZI |
| 16344 | 800U, // PRFD_S_SXTW_SCALED |
| 16345 | 808U, // PRFD_S_UXTW_SCALED |
| 16346 | 816U, // PRFH_D_PZI |
| 16347 | 824U, // PRFH_D_SCALED |
| 16348 | 832U, // PRFH_D_SXTW_SCALED |
| 16349 | 840U, // PRFH_D_UXTW_SCALED |
| 16350 | 184688U, // PRFH_PRI |
| 16351 | 848U, // PRFH_PRR |
| 16352 | 816U, // PRFH_S_PZI |
| 16353 | 856U, // PRFH_S_SXTW_SCALED |
| 16354 | 864U, // PRFH_S_UXTW_SCALED |
| 16355 | 1U, // PRFMl |
| 16356 | 1141127264U, // PRFMroW |
| 16357 | 1174681696U, // PRFMroX |
| 16358 | 157792U, // PRFMui |
| 16359 | 6830176U, // PRFUMi |
| 16360 | 872U, // PRFW_D_PZI |
| 16361 | 880U, // PRFW_D_SCALED |
| 16362 | 888U, // PRFW_D_SXTW_SCALED |
| 16363 | 896U, // PRFW_D_UXTW_SCALED |
| 16364 | 184688U, // PRFW_PRI |
| 16365 | 904U, // PRFW_PRR |
| 16366 | 872U, // PRFW_S_PZI |
| 16367 | 912U, // PRFW_S_SXTW_SCALED |
| 16368 | 920U, // PRFW_S_UXTW_SCALED |
| 16369 | 22552672U, // PSEL_PPPRI_B |
| 16370 | 22554720U, // PSEL_PPPRI_D |
| 16371 | 22567008U, // PSEL_PPPRI_H |
| 16372 | 22556768U, // PSEL_PPPRI_S |
| 16373 | 0U, // PTEST_PP |
| 16374 | 1U, // PTRUES_B |
| 16375 | 1U, // PTRUES_D |
| 16376 | 0U, // PTRUES_H |
| 16377 | 1U, // PTRUES_S |
| 16378 | 1U, // PTRUE_B |
| 16379 | 0U, // PTRUE_C_B |
| 16380 | 0U, // PTRUE_C_D |
| 16381 | 0U, // PTRUE_C_H |
| 16382 | 0U, // PTRUE_C_S |
| 16383 | 1U, // PTRUE_D |
| 16384 | 0U, // PTRUE_H |
| 16385 | 1U, // PTRUE_S |
| 16386 | 1U, // PUNPKHI_PP |
| 16387 | 1U, // PUNPKLO_PP |
| 16388 | 22624U, // RADDHNB_ZZZ_B |
| 16389 | 4208U, // RADDHNB_ZZZ_H |
| 16390 | 10336U, // RADDHNB_ZZZ_S |
| 16391 | 24672U, // RADDHNT_ZZZ_B |
| 16392 | 120U, // RADDHNT_ZZZ_H |
| 16393 | 2144U, // RADDHNT_ZZZ_S |
| 16394 | 551040U, // RADDHNv2i64_v2i32 |
| 16395 | 553088U, // RADDHNv2i64_v4i32 |
| 16396 | 813192U, // RADDHNv4i32_v4i16 |
| 16397 | 815240U, // RADDHNv4i32_v8i16 |
| 16398 | 1077392U, // RADDHNv8i16_v16i8 |
| 16399 | 1075344U, // RADDHNv8i16_v8i8 |
| 16400 | 551040U, // RAX1 |
| 16401 | 10336U, // RAX1_ZZZ_D |
| 16402 | 0U, // RBITWr |
| 16403 | 0U, // RBITXr |
| 16404 | 8U, // RBIT_ZPmZ_B |
| 16405 | 2056U, // RBIT_ZPmZ_D |
| 16406 | 4112U, // RBIT_ZPmZ_H |
| 16407 | 6152U, // RBIT_ZPmZ_S |
| 16408 | 8216U, // RBIT_ZPzZ_B |
| 16409 | 10264U, // RBIT_ZPzZ_D |
| 16410 | 4128U, // RBIT_ZPzZ_H |
| 16411 | 12312U, // RBIT_ZPzZ_S |
| 16412 | 40U, // RBITv16i8 |
| 16413 | 88U, // RBITv8i8 |
| 16414 | 6906129U, // RCWCAS |
| 16415 | 6906129U, // RCWCASA |
| 16416 | 6906129U, // RCWCASAL |
| 16417 | 6906129U, // RCWCASL |
| 16418 | 0U, // RCWCASP |
| 16419 | 0U, // RCWCASPA |
| 16420 | 0U, // RCWCASPAL |
| 16421 | 0U, // RCWCASPL |
| 16422 | 3U, // RCWCLR |
| 16423 | 3U, // RCWCLRA |
| 16424 | 3U, // RCWCLRAL |
| 16425 | 3U, // RCWCLRL |
| 16426 | 147731U, // RCWCLRP |
| 16427 | 147731U, // RCWCLRPA |
| 16428 | 147731U, // RCWCLRPAL |
| 16429 | 147731U, // RCWCLRPL |
| 16430 | 3U, // RCWCLRS |
| 16431 | 3U, // RCWCLRSA |
| 16432 | 3U, // RCWCLRSAL |
| 16433 | 3U, // RCWCLRSL |
| 16434 | 147731U, // RCWCLRSP |
| 16435 | 147731U, // RCWCLRSPA |
| 16436 | 147731U, // RCWCLRSPAL |
| 16437 | 147731U, // RCWCLRSPL |
| 16438 | 6906129U, // RCWSCAS |
| 16439 | 6906129U, // RCWSCASA |
| 16440 | 6906129U, // RCWSCASAL |
| 16441 | 6906129U, // RCWSCASL |
| 16442 | 0U, // RCWSCASP |
| 16443 | 0U, // RCWSCASPA |
| 16444 | 0U, // RCWSCASPAL |
| 16445 | 0U, // RCWSCASPL |
| 16446 | 3U, // RCWSET |
| 16447 | 3U, // RCWSETA |
| 16448 | 3U, // RCWSETAL |
| 16449 | 3U, // RCWSETL |
| 16450 | 147731U, // RCWSETP |
| 16451 | 147731U, // RCWSETPA |
| 16452 | 147731U, // RCWSETPAL |
| 16453 | 147731U, // RCWSETPL |
| 16454 | 3U, // RCWSETS |
| 16455 | 3U, // RCWSETSA |
| 16456 | 3U, // RCWSETSAL |
| 16457 | 3U, // RCWSETSL |
| 16458 | 147731U, // RCWSETSP |
| 16459 | 147731U, // RCWSETSPA |
| 16460 | 147731U, // RCWSETSPAL |
| 16461 | 147731U, // RCWSETSPL |
| 16462 | 3U, // RCWSWP |
| 16463 | 3U, // RCWSWPA |
| 16464 | 3U, // RCWSWPAL |
| 16465 | 3U, // RCWSWPL |
| 16466 | 147731U, // RCWSWPP |
| 16467 | 147731U, // RCWSWPPA |
| 16468 | 147731U, // RCWSWPPAL |
| 16469 | 147731U, // RCWSWPPL |
| 16470 | 3U, // RCWSWPS |
| 16471 | 3U, // RCWSWPSA |
| 16472 | 3U, // RCWSWPSAL |
| 16473 | 3U, // RCWSWPSL |
| 16474 | 147731U, // RCWSWPSP |
| 16475 | 147731U, // RCWSWPSPA |
| 16476 | 147731U, // RCWSWPSPAL |
| 16477 | 147731U, // RCWSWPSPL |
| 16478 | 928U, // RDFFRS_PPz |
| 16479 | 0U, // RDFFR_P |
| 16480 | 928U, // RDFFR_PPz |
| 16481 | 0U, // RDSVLI_XI |
| 16482 | 0U, // RDVLI_XI |
| 16483 | 0U, // RET |
| 16484 | 0U, // RETAA |
| 16485 | 0U, // RETAASPPCi |
| 16486 | 0U, // RETAASPPCr |
| 16487 | 0U, // RETAB |
| 16488 | 0U, // RETABSPPCi |
| 16489 | 0U, // RETABSPPCr |
| 16490 | 0U, // REV16Wr |
| 16491 | 0U, // REV16Xr |
| 16492 | 40U, // REV16v16i8 |
| 16493 | 88U, // REV16v8i8 |
| 16494 | 0U, // REV32Xr |
| 16495 | 40U, // REV32v16i8 |
| 16496 | 64U, // REV32v4i16 |
| 16497 | 80U, // REV32v8i16 |
| 16498 | 88U, // REV32v8i8 |
| 16499 | 40U, // REV64v16i8 |
| 16500 | 48U, // REV64v2i32 |
| 16501 | 64U, // REV64v4i16 |
| 16502 | 72U, // REV64v4i32 |
| 16503 | 80U, // REV64v8i16 |
| 16504 | 88U, // REV64v8i8 |
| 16505 | 2056U, // REVB_ZPmZ_D |
| 16506 | 4112U, // REVB_ZPmZ_H |
| 16507 | 6152U, // REVB_ZPmZ_S |
| 16508 | 10264U, // REVB_ZPzZ_D |
| 16509 | 4128U, // REVB_ZPzZ_H |
| 16510 | 12312U, // REVB_ZPzZ_S |
| 16511 | 936U, // REVD_ZPmZ |
| 16512 | 4320U, // REVD_ZPzZ |
| 16513 | 2056U, // REVH_ZPmZ_D |
| 16514 | 6152U, // REVH_ZPmZ_S |
| 16515 | 10264U, // REVH_ZPzZ_D |
| 16516 | 12312U, // REVH_ZPzZ_S |
| 16517 | 2056U, // REVW_ZPmZ_D |
| 16518 | 10264U, // REVW_ZPzZ_D |
| 16519 | 0U, // REVWr |
| 16520 | 0U, // REVXr |
| 16521 | 0U, // REV_PP_B |
| 16522 | 0U, // REV_PP_D |
| 16523 | 1U, // REV_PP_H |
| 16524 | 0U, // REV_PP_S |
| 16525 | 0U, // REV_ZZ_B |
| 16526 | 0U, // REV_ZZ_D |
| 16527 | 1U, // REV_ZZ_H |
| 16528 | 0U, // REV_ZZ_S |
| 16529 | 14432U, // RMIF |
| 16530 | 14432U, // RORVWr |
| 16531 | 14432U, // RORVXr |
| 16532 | 0U, // RPRFM |
| 16533 | 14432U, // RSHRNB_ZZI_B |
| 16534 | 4328U, // RSHRNB_ZZI_H |
| 16535 | 14432U, // RSHRNB_ZZI_S |
| 16536 | 90208U, // RSHRNT_ZZI_B |
| 16537 | 4464U, // RSHRNT_ZZI_H |
| 16538 | 90208U, // RSHRNT_ZZI_S |
| 16539 | 90256U, // RSHRNv16i8_shift |
| 16540 | 14464U, // RSHRNv2i32_shift |
| 16541 | 14472U, // RSHRNv4i16_shift |
| 16542 | 90240U, // RSHRNv4i32_shift |
| 16543 | 90248U, // RSHRNv8i16_shift |
| 16544 | 14480U, // RSHRNv8i8_shift |
| 16545 | 22624U, // RSUBHNB_ZZZ_B |
| 16546 | 4208U, // RSUBHNB_ZZZ_H |
| 16547 | 10336U, // RSUBHNB_ZZZ_S |
| 16548 | 24672U, // RSUBHNT_ZZZ_B |
| 16549 | 120U, // RSUBHNT_ZZZ_H |
| 16550 | 2144U, // RSUBHNT_ZZZ_S |
| 16551 | 551040U, // RSUBHNv2i64_v2i32 |
| 16552 | 553088U, // RSUBHNv2i64_v4i32 |
| 16553 | 813192U, // RSUBHNv4i32_v4i16 |
| 16554 | 815240U, // RSUBHNv4i32_v8i16 |
| 16555 | 1077392U, // RSUBHNv8i16_v16i8 |
| 16556 | 1075344U, // RSUBHNv8i16_v8i8 |
| 16557 | 6240U, // SABALB_ZZZ_D |
| 16558 | 4376U, // SABALB_ZZZ_H |
| 16559 | 24672U, // SABALB_ZZZ_S |
| 16560 | 6240U, // SABALT_ZZZ_D |
| 16561 | 4376U, // SABALT_ZZZ_H |
| 16562 | 24672U, // SABALT_ZZZ_S |
| 16563 | 4376U, // SABAL_ZZZ_BtoH |
| 16564 | 24672U, // SABAL_ZZZ_HtoS |
| 16565 | 6240U, // SABAL_ZZZ_StoD |
| 16566 | 1863832U, // SABALv16i8_v8i16 |
| 16567 | 2125984U, // SABALv2i32_v2i64 |
| 16568 | 2388136U, // SABALv4i16_v4i32 |
| 16569 | 815240U, // SABALv4i32_v2i64 |
| 16570 | 1077392U, // SABALv8i16_v4i32 |
| 16571 | 2650288U, // SABALv8i8_v8i16 |
| 16572 | 4377U, // SABA_ZZZ_B |
| 16573 | 2144U, // SABA_ZZZ_D |
| 16574 | 4112U, // SABA_ZZZ_H |
| 16575 | 6240U, // SABA_ZZZ_S |
| 16576 | 1863832U, // SABAv16i8 |
| 16577 | 2125984U, // SABAv2i32 |
| 16578 | 2388136U, // SABAv4i16 |
| 16579 | 815240U, // SABAv4i32 |
| 16580 | 1077392U, // SABAv8i16 |
| 16581 | 2650288U, // SABAv8i8 |
| 16582 | 12384U, // SABDLB_ZZZ_D |
| 16583 | 184U, // SABDLB_ZZZ_H |
| 16584 | 22624U, // SABDLB_ZZZ_S |
| 16585 | 12384U, // SABDLT_ZZZ_D |
| 16586 | 184U, // SABDLT_ZZZ_H |
| 16587 | 22624U, // SABDLT_ZZZ_S |
| 16588 | 1861784U, // SABDLv16i8_v8i16 |
| 16589 | 2123936U, // SABDLv2i32_v2i64 |
| 16590 | 2386088U, // SABDLv4i16_v4i32 |
| 16591 | 813192U, // SABDLv4i32_v2i64 |
| 16592 | 1075344U, // SABDLv8i16_v4i32 |
| 16593 | 2648240U, // SABDLv8i8_v8i16 |
| 16594 | 33824776U, // SABD_ZPmZ_B |
| 16595 | 67381256U, // SABD_ZPmZ_D |
| 16596 | 102266912U, // SABD_ZPmZ_H |
| 16597 | 134492168U, // SABD_ZPmZ_S |
| 16598 | 1861784U, // SABDv16i8 |
| 16599 | 2123936U, // SABDv2i32 |
| 16600 | 2386088U, // SABDv4i16 |
| 16601 | 813192U, // SABDv4i32 |
| 16602 | 1075344U, // SABDv8i16 |
| 16603 | 2648240U, // SABDv8i8 |
| 16604 | 6152U, // SADALP_ZPmZ_D |
| 16605 | 4376U, // SADALP_ZPmZ_H |
| 16606 | 24584U, // SADALP_ZPmZ_S |
| 16607 | 40U, // SADALPv16i8_v8i16 |
| 16608 | 48U, // SADALPv2i32_v1i64 |
| 16609 | 64U, // SADALPv4i16_v2i32 |
| 16610 | 72U, // SADALPv4i32_v2i64 |
| 16611 | 80U, // SADALPv8i16_v4i32 |
| 16612 | 88U, // SADALPv8i8_v4i16 |
| 16613 | 12384U, // SADDLBT_ZZZ_D |
| 16614 | 184U, // SADDLBT_ZZZ_H |
| 16615 | 22624U, // SADDLBT_ZZZ_S |
| 16616 | 12384U, // SADDLB_ZZZ_D |
| 16617 | 184U, // SADDLB_ZZZ_H |
| 16618 | 22624U, // SADDLB_ZZZ_S |
| 16619 | 40U, // SADDLPv16i8_v8i16 |
| 16620 | 48U, // SADDLPv2i32_v1i64 |
| 16621 | 64U, // SADDLPv4i16_v2i32 |
| 16622 | 72U, // SADDLPv4i32_v2i64 |
| 16623 | 80U, // SADDLPv8i16_v4i32 |
| 16624 | 88U, // SADDLPv8i8_v4i16 |
| 16625 | 12384U, // SADDLT_ZZZ_D |
| 16626 | 184U, // SADDLT_ZZZ_H |
| 16627 | 22624U, // SADDLT_ZZZ_S |
| 16628 | 40U, // SADDLVv16i8v |
| 16629 | 64U, // SADDLVv4i16v |
| 16630 | 72U, // SADDLVv4i32v |
| 16631 | 80U, // SADDLVv8i16v |
| 16632 | 88U, // SADDLVv8i8v |
| 16633 | 1861784U, // SADDLv16i8_v8i16 |
| 16634 | 2123936U, // SADDLv2i32_v2i64 |
| 16635 | 2386088U, // SADDLv4i16_v4i32 |
| 16636 | 813192U, // SADDLv4i32_v2i64 |
| 16637 | 1075344U, // SADDLv8i16_v4i32 |
| 16638 | 2648240U, // SADDLv8i8_v8i16 |
| 16639 | 1U, // SADDV_VPZ_B |
| 16640 | 1U, // SADDV_VPZ_H |
| 16641 | 1U, // SADDV_VPZ_S |
| 16642 | 12384U, // SADDWB_ZZZ_D |
| 16643 | 184U, // SADDWB_ZZZ_H |
| 16644 | 22624U, // SADDWB_ZZZ_S |
| 16645 | 12384U, // SADDWT_ZZZ_D |
| 16646 | 184U, // SADDWT_ZZZ_H |
| 16647 | 22624U, // SADDWT_ZZZ_S |
| 16648 | 1861776U, // SADDWv16i8_v8i16 |
| 16649 | 2123904U, // SADDWv2i32_v2i64 |
| 16650 | 2386056U, // SADDWv4i16_v4i32 |
| 16651 | 813184U, // SADDWv4i32_v2i64 |
| 16652 | 1075336U, // SADDWv8i16_v4i32 |
| 16653 | 2648208U, // SADDWv8i8_v8i16 |
| 16654 | 0U, // SB |
| 16655 | 2144U, // SBCLB_ZZZ_D |
| 16656 | 6240U, // SBCLB_ZZZ_S |
| 16657 | 2144U, // SBCLT_ZZZ_D |
| 16658 | 6240U, // SBCLT_ZZZ_S |
| 16659 | 14432U, // SBCSWr |
| 16660 | 14432U, // SBCSXr |
| 16661 | 14432U, // SBCWr |
| 16662 | 14432U, // SBCXr |
| 16663 | 276576U, // SBFMWri |
| 16664 | 276576U, // SBFMXri |
| 16665 | 4376U, // SCLAMP_VG2_2Z2Z_B |
| 16666 | 472U, // SCLAMP_VG2_2Z2Z_D |
| 16667 | 4112U, // SCLAMP_VG2_2Z2Z_H |
| 16668 | 120U, // SCLAMP_VG2_2Z2Z_S |
| 16669 | 4376U, // SCLAMP_VG4_4Z4Z_B |
| 16670 | 472U, // SCLAMP_VG4_4Z4Z_D |
| 16671 | 4112U, // SCLAMP_VG4_4Z4Z_H |
| 16672 | 120U, // SCLAMP_VG4_4Z4Z_S |
| 16673 | 4377U, // SCLAMP_ZZZ_B |
| 16674 | 2144U, // SCLAMP_ZZZ_D |
| 16675 | 4112U, // SCLAMP_ZZZ_H |
| 16676 | 6240U, // SCLAMP_ZZZ_S |
| 16677 | 0U, // SCVTFDSr |
| 16678 | 0U, // SCVTFHDr |
| 16679 | 0U, // SCVTFHSr |
| 16680 | 1U, // SCVTFLT_ZZ_BtoH |
| 16681 | 0U, // SCVTFLT_ZZ_HtoS |
| 16682 | 0U, // SCVTFLT_ZZ_StoD |
| 16683 | 0U, // SCVTFSDr |
| 16684 | 14432U, // SCVTFSWDri |
| 16685 | 14432U, // SCVTFSWHri |
| 16686 | 14432U, // SCVTFSWSri |
| 16687 | 14432U, // SCVTFSXDri |
| 16688 | 14432U, // SCVTFSXHri |
| 16689 | 14432U, // SCVTFSXSri |
| 16690 | 0U, // SCVTFUWDri |
| 16691 | 0U, // SCVTFUWHri |
| 16692 | 0U, // SCVTFUWSri |
| 16693 | 0U, // SCVTFUXDri |
| 16694 | 0U, // SCVTFUXHri |
| 16695 | 0U, // SCVTFUXSri |
| 16696 | 1U, // SCVTF_2Z2Z_StoS |
| 16697 | 1U, // SCVTF_4Z4Z_StoS |
| 16698 | 2056U, // SCVTF_ZPmZ_DtoD |
| 16699 | 472U, // SCVTF_ZPmZ_DtoH |
| 16700 | 2056U, // SCVTF_ZPmZ_DtoS |
| 16701 | 4112U, // SCVTF_ZPmZ_HtoH |
| 16702 | 6152U, // SCVTF_ZPmZ_StoD |
| 16703 | 120U, // SCVTF_ZPmZ_StoH |
| 16704 | 6152U, // SCVTF_ZPmZ_StoS |
| 16705 | 10264U, // SCVTF_ZPzZ_DtoD |
| 16706 | 4288U, // SCVTF_ZPzZ_DtoH |
| 16707 | 10264U, // SCVTF_ZPzZ_DtoS |
| 16708 | 4128U, // SCVTF_ZPzZ_HtoH |
| 16709 | 12312U, // SCVTF_ZPzZ_StoD |
| 16710 | 4208U, // SCVTF_ZPzZ_StoH |
| 16711 | 12312U, // SCVTF_ZPzZ_StoS |
| 16712 | 1U, // SCVTF_ZZ_BtoH |
| 16713 | 0U, // SCVTF_ZZ_HtoS |
| 16714 | 0U, // SCVTF_ZZ_StoD |
| 16715 | 14432U, // SCVTFd |
| 16716 | 14432U, // SCVTFh |
| 16717 | 14432U, // SCVTFs |
| 16718 | 0U, // SCVTFv1i16 |
| 16719 | 0U, // SCVTFv1i32 |
| 16720 | 0U, // SCVTFv1i64 |
| 16721 | 48U, // SCVTFv2f32 |
| 16722 | 56U, // SCVTFv2f64 |
| 16723 | 14496U, // SCVTFv2i32_shift |
| 16724 | 14464U, // SCVTFv2i64_shift |
| 16725 | 64U, // SCVTFv4f16 |
| 16726 | 72U, // SCVTFv4f32 |
| 16727 | 14504U, // SCVTFv4i16_shift |
| 16728 | 14472U, // SCVTFv4i32_shift |
| 16729 | 80U, // SCVTFv8f16 |
| 16730 | 14480U, // SCVTFv8i16_shift |
| 16731 | 67381256U, // SDIVR_ZPmZ_D |
| 16732 | 134492168U, // SDIVR_ZPmZ_S |
| 16733 | 14432U, // SDIVWr |
| 16734 | 14432U, // SDIVXr |
| 16735 | 67381256U, // SDIV_ZPmZ_D |
| 16736 | 134492168U, // SDIV_ZPmZ_S |
| 16737 | 119320U, // SDOT_VG2_M2Z2Z_BtoS |
| 16738 | 5273840U, // SDOT_VG2_M2Z2Z_HtoD |
| 16739 | 5273840U, // SDOT_VG2_M2Z2Z_HtoS |
| 16740 | 10082840U, // SDOT_VG2_M2ZZI_BToS |
| 16741 | 206862576U, // SDOT_VG2_M2ZZI_HToS |
| 16742 | 206862576U, // SDOT_VG2_M2ZZI_HtoD |
| 16743 | 121368U, // SDOT_VG2_M2ZZ_BtoS |
| 16744 | 106199280U, // SDOT_VG2_M2ZZ_HtoD |
| 16745 | 106199280U, // SDOT_VG2_M2ZZ_HtoS |
| 16746 | 119321U, // SDOT_VG4_M4Z4Z_BtoS |
| 16747 | 5273841U, // SDOT_VG4_M4Z4Z_HtoD |
| 16748 | 5273841U, // SDOT_VG4_M4Z4Z_HtoS |
| 16749 | 10082841U, // SDOT_VG4_M4ZZI_BToS |
| 16750 | 206862577U, // SDOT_VG4_M4ZZI_HToS |
| 16751 | 206862577U, // SDOT_VG4_M4ZZI_HtoD |
| 16752 | 121369U, // SDOT_VG4_M4ZZ_BtoS |
| 16753 | 106199281U, // SDOT_VG4_M4ZZ_HtoD |
| 16754 | 106199281U, // SDOT_VG4_M4ZZ_HtoS |
| 16755 | 86296U, // SDOT_ZZZI_BtoH |
| 16756 | 86297U, // SDOT_ZZZI_BtoS |
| 16757 | 106455136U, // SDOT_ZZZI_HtoD |
| 16758 | 106455136U, // SDOT_ZZZI_HtoS |
| 16759 | 4376U, // SDOT_ZZZ_BtoH |
| 16760 | 4377U, // SDOT_ZZZ_BtoS |
| 16761 | 24672U, // SDOT_ZZZ_HtoD |
| 16762 | 24672U, // SDOT_ZZZ_HtoS |
| 16763 | 10252440U, // SDOTlanev16i8 |
| 16764 | 10252464U, // SDOTlanev8i8 |
| 16765 | 1863832U, // SDOTv16i8 |
| 16766 | 2650288U, // SDOTv8i8 |
| 16767 | 33824864U, // SEL_PPPP |
| 16768 | 22838192U, // SEL_VG2_2ZC2Z2Z_B |
| 16769 | 23099848U, // SEL_VG2_2ZC2Z2Z_D |
| 16770 | 23361784U, // SEL_VG2_2ZC2Z2Z_H |
| 16771 | 23624144U, // SEL_VG2_2ZC2Z2Z_S |
| 16772 | 22838192U, // SEL_VG4_4ZC4Z4Z_B |
| 16773 | 23099848U, // SEL_VG4_4ZC4Z4Z_D |
| 16774 | 23361784U, // SEL_VG4_4ZC4Z4Z_H |
| 16775 | 23624144U, // SEL_VG4_4ZC4Z4Z_S |
| 16776 | 33824864U, // SEL_ZPZZ_B |
| 16777 | 67381344U, // SEL_ZPZZ_D |
| 16778 | 102266912U, // SEL_ZPZZ_H |
| 16779 | 134492256U, // SEL_ZPZZ_S |
| 16780 | 3U, // SETE |
| 16781 | 3U, // SETEN |
| 16782 | 3U, // SETET |
| 16783 | 3U, // SETETN |
| 16784 | 0U, // SETF16 |
| 16785 | 0U, // SETF8 |
| 16786 | 0U, // SETFFR |
| 16787 | 3U, // SETGM |
| 16788 | 3U, // SETGMN |
| 16789 | 3U, // SETGMT |
| 16790 | 3U, // SETGMTN |
| 16791 | 4U, // SETGOE |
| 16792 | 4U, // SETGOEN |
| 16793 | 4U, // SETGOET |
| 16794 | 4U, // SETGOETN |
| 16795 | 4U, // SETGOM |
| 16796 | 4U, // SETGOMN |
| 16797 | 4U, // SETGOMT |
| 16798 | 4U, // SETGOMTN |
| 16799 | 4U, // SETGOP |
| 16800 | 4U, // SETGOPN |
| 16801 | 4U, // SETGOPT |
| 16802 | 4U, // SETGOPTN |
| 16803 | 3U, // SETGP |
| 16804 | 3U, // SETGPN |
| 16805 | 3U, // SETGPT |
| 16806 | 3U, // SETGPTN |
| 16807 | 3U, // SETM |
| 16808 | 3U, // SETMN |
| 16809 | 3U, // SETMT |
| 16810 | 3U, // SETMTN |
| 16811 | 3U, // SETP |
| 16812 | 3U, // SETPN |
| 16813 | 3U, // SETPT |
| 16814 | 3U, // SETPTN |
| 16815 | 815201U, // SHA1Crrr |
| 16816 | 0U, // SHA1Hrr |
| 16817 | 815201U, // SHA1Mrrr |
| 16818 | 815201U, // SHA1Prrr |
| 16819 | 815240U, // SHA1SU0rrr |
| 16820 | 72U, // SHA1SU1rr |
| 16821 | 815201U, // SHA256H2rrr |
| 16822 | 815201U, // SHA256Hrrr |
| 16823 | 72U, // SHA256SU0rr |
| 16824 | 815240U, // SHA256SU1rrr |
| 16825 | 553057U, // SHA512H |
| 16826 | 553057U, // SHA512H2 |
| 16827 | 56U, // SHA512SU0 |
| 16828 | 553088U, // SHA512SU1 |
| 16829 | 33824776U, // SHADD_ZPmZ_B |
| 16830 | 67381256U, // SHADD_ZPmZ_D |
| 16831 | 102266912U, // SHADD_ZPmZ_H |
| 16832 | 134492168U, // SHADD_ZPmZ_S |
| 16833 | 1861784U, // SHADDv16i8 |
| 16834 | 2123936U, // SHADDv2i32 |
| 16835 | 2386088U, // SHADDv4i16 |
| 16836 | 813192U, // SHADDv4i32 |
| 16837 | 1075344U, // SHADDv8i16 |
| 16838 | 2648240U, // SHADDv8i8 |
| 16839 | 952U, // SHLLv16i8 |
| 16840 | 960U, // SHLLv2i32 |
| 16841 | 968U, // SHLLv4i16 |
| 16842 | 976U, // SHLLv4i32 |
| 16843 | 984U, // SHLLv8i16 |
| 16844 | 992U, // SHLLv8i8 |
| 16845 | 14432U, // SHLd |
| 16846 | 14488U, // SHLv16i8_shift |
| 16847 | 14496U, // SHLv2i32_shift |
| 16848 | 14464U, // SHLv2i64_shift |
| 16849 | 14504U, // SHLv4i16_shift |
| 16850 | 14472U, // SHLv4i32_shift |
| 16851 | 14480U, // SHLv8i16_shift |
| 16852 | 14512U, // SHLv8i8_shift |
| 16853 | 14432U, // SHRNB_ZZI_B |
| 16854 | 4328U, // SHRNB_ZZI_H |
| 16855 | 14432U, // SHRNB_ZZI_S |
| 16856 | 90208U, // SHRNT_ZZI_B |
| 16857 | 4464U, // SHRNT_ZZI_H |
| 16858 | 90208U, // SHRNT_ZZI_S |
| 16859 | 90256U, // SHRNv16i8_shift |
| 16860 | 14464U, // SHRNv2i32_shift |
| 16861 | 14472U, // SHRNv4i16_shift |
| 16862 | 90240U, // SHRNv4i32_shift |
| 16863 | 90248U, // SHRNv8i16_shift |
| 16864 | 14480U, // SHRNv8i8_shift |
| 16865 | 33824776U, // SHSUBR_ZPmZ_B |
| 16866 | 67381256U, // SHSUBR_ZPmZ_D |
| 16867 | 102266912U, // SHSUBR_ZPmZ_H |
| 16868 | 134492168U, // SHSUBR_ZPmZ_S |
| 16869 | 33824776U, // SHSUB_ZPmZ_B |
| 16870 | 67381256U, // SHSUB_ZPmZ_D |
| 16871 | 102266912U, // SHSUB_ZPmZ_H |
| 16872 | 134492168U, // SHSUB_ZPmZ_S |
| 16873 | 1861784U, // SHSUBv16i8 |
| 16874 | 2123936U, // SHSUBv2i32 |
| 16875 | 2386088U, // SHSUBv4i16 |
| 16876 | 813192U, // SHSUBv4i32 |
| 16877 | 1075344U, // SHSUBv8i16 |
| 16878 | 2648240U, // SHSUBv8i8 |
| 16879 | 0U, // SHUH |
| 16880 | 4465U, // SLI_ZZI_B |
| 16881 | 90208U, // SLI_ZZI_D |
| 16882 | 4464U, // SLI_ZZI_H |
| 16883 | 90208U, // SLI_ZZI_S |
| 16884 | 90209U, // SLId |
| 16885 | 90264U, // SLIv16i8_shift |
| 16886 | 90272U, // SLIv2i32_shift |
| 16887 | 90240U, // SLIv2i64_shift |
| 16888 | 90280U, // SLIv4i16_shift |
| 16889 | 90248U, // SLIv4i32_shift |
| 16890 | 90256U, // SLIv8i16_shift |
| 16891 | 90288U, // SLIv8i8_shift |
| 16892 | 815240U, // SM3PARTW1 |
| 16893 | 815240U, // SM3PARTW2 |
| 16894 | 176711816U, // SM3SS1 |
| 16895 | 244609160U, // SM3TT1A |
| 16896 | 244609160U, // SM3TT1B |
| 16897 | 244609160U, // SM3TT2A |
| 16898 | 244609160U, // SM3TT2B |
| 16899 | 72U, // SM4E |
| 16900 | 12384U, // SM4EKEY_ZZZ_S |
| 16901 | 813192U, // SM4ENCKEY |
| 16902 | 12384U, // SM4E_ZZZ_S |
| 16903 | 276576U, // SMADDLrrr |
| 16904 | 33824776U, // SMAXP_ZPmZ_B |
| 16905 | 67381256U, // SMAXP_ZPmZ_D |
| 16906 | 102266912U, // SMAXP_ZPmZ_H |
| 16907 | 134492168U, // SMAXP_ZPmZ_S |
| 16908 | 1861784U, // SMAXPv16i8 |
| 16909 | 2123936U, // SMAXPv2i32 |
| 16910 | 2386088U, // SMAXPv4i16 |
| 16911 | 813192U, // SMAXPv4i32 |
| 16912 | 1075344U, // SMAXPv8i16 |
| 16913 | 2648240U, // SMAXPv8i8 |
| 16914 | 8288U, // SMAXQV_VPZ_B |
| 16915 | 10336U, // SMAXQV_VPZ_D |
| 16916 | 22624U, // SMAXQV_VPZ_H |
| 16917 | 12384U, // SMAXQV_VPZ_S |
| 16918 | 0U, // SMAXV_VPZ_B |
| 16919 | 1U, // SMAXV_VPZ_D |
| 16920 | 1U, // SMAXV_VPZ_H |
| 16921 | 1U, // SMAXV_VPZ_S |
| 16922 | 40U, // SMAXVv16i8v |
| 16923 | 64U, // SMAXVv4i16v |
| 16924 | 72U, // SMAXVv4i32v |
| 16925 | 80U, // SMAXVv8i16v |
| 16926 | 88U, // SMAXVv8i8v |
| 16927 | 14432U, // SMAXWri |
| 16928 | 14432U, // SMAXWrr |
| 16929 | 14432U, // SMAXXri |
| 16930 | 14432U, // SMAXXrr |
| 16931 | 5040U, // SMAX_VG2_2Z2Z_B |
| 16932 | 4552U, // SMAX_VG2_2Z2Z_D |
| 16933 | 4344U, // SMAX_VG2_2Z2Z_H |
| 16934 | 4560U, // SMAX_VG2_2Z2Z_S |
| 16935 | 184U, // SMAX_VG2_2ZZ_B |
| 16936 | 4288U, // SMAX_VG2_2ZZ_D |
| 16937 | 4128U, // SMAX_VG2_2ZZ_H |
| 16938 | 4208U, // SMAX_VG2_2ZZ_S |
| 16939 | 5040U, // SMAX_VG4_4Z4Z_B |
| 16940 | 4552U, // SMAX_VG4_4Z4Z_D |
| 16941 | 4344U, // SMAX_VG4_4Z4Z_H |
| 16942 | 4560U, // SMAX_VG4_4Z4Z_S |
| 16943 | 184U, // SMAX_VG4_4ZZ_B |
| 16944 | 4288U, // SMAX_VG4_4ZZ_D |
| 16945 | 4128U, // SMAX_VG4_4ZZ_H |
| 16946 | 4208U, // SMAX_VG4_4ZZ_S |
| 16947 | 14432U, // SMAX_ZI_B |
| 16948 | 14432U, // SMAX_ZI_D |
| 16949 | 4328U, // SMAX_ZI_H |
| 16950 | 14432U, // SMAX_ZI_S |
| 16951 | 33824776U, // SMAX_ZPmZ_B |
| 16952 | 67381256U, // SMAX_ZPmZ_D |
| 16953 | 102266912U, // SMAX_ZPmZ_H |
| 16954 | 134492168U, // SMAX_ZPmZ_S |
| 16955 | 1861784U, // SMAXv16i8 |
| 16956 | 2123936U, // SMAXv2i32 |
| 16957 | 2386088U, // SMAXv4i16 |
| 16958 | 813192U, // SMAXv4i32 |
| 16959 | 1075344U, // SMAXv8i16 |
| 16960 | 2648240U, // SMAXv8i8 |
| 16961 | 0U, // SMC |
| 16962 | 33824776U, // SMINP_ZPmZ_B |
| 16963 | 67381256U, // SMINP_ZPmZ_D |
| 16964 | 102266912U, // SMINP_ZPmZ_H |
| 16965 | 134492168U, // SMINP_ZPmZ_S |
| 16966 | 1861784U, // SMINPv16i8 |
| 16967 | 2123936U, // SMINPv2i32 |
| 16968 | 2386088U, // SMINPv4i16 |
| 16969 | 813192U, // SMINPv4i32 |
| 16970 | 1075344U, // SMINPv8i16 |
| 16971 | 2648240U, // SMINPv8i8 |
| 16972 | 8288U, // SMINQV_VPZ_B |
| 16973 | 10336U, // SMINQV_VPZ_D |
| 16974 | 22624U, // SMINQV_VPZ_H |
| 16975 | 12384U, // SMINQV_VPZ_S |
| 16976 | 0U, // SMINV_VPZ_B |
| 16977 | 1U, // SMINV_VPZ_D |
| 16978 | 1U, // SMINV_VPZ_H |
| 16979 | 1U, // SMINV_VPZ_S |
| 16980 | 40U, // SMINVv16i8v |
| 16981 | 64U, // SMINVv4i16v |
| 16982 | 72U, // SMINVv4i32v |
| 16983 | 80U, // SMINVv8i16v |
| 16984 | 88U, // SMINVv8i8v |
| 16985 | 14432U, // SMINWri |
| 16986 | 14432U, // SMINWrr |
| 16987 | 14432U, // SMINXri |
| 16988 | 14432U, // SMINXrr |
| 16989 | 5040U, // SMIN_VG2_2Z2Z_B |
| 16990 | 4552U, // SMIN_VG2_2Z2Z_D |
| 16991 | 4344U, // SMIN_VG2_2Z2Z_H |
| 16992 | 4560U, // SMIN_VG2_2Z2Z_S |
| 16993 | 184U, // SMIN_VG2_2ZZ_B |
| 16994 | 4288U, // SMIN_VG2_2ZZ_D |
| 16995 | 4128U, // SMIN_VG2_2ZZ_H |
| 16996 | 4208U, // SMIN_VG2_2ZZ_S |
| 16997 | 5040U, // SMIN_VG4_4Z4Z_B |
| 16998 | 4552U, // SMIN_VG4_4Z4Z_D |
| 16999 | 4344U, // SMIN_VG4_4Z4Z_H |
| 17000 | 4560U, // SMIN_VG4_4Z4Z_S |
| 17001 | 184U, // SMIN_VG4_4ZZ_B |
| 17002 | 4288U, // SMIN_VG4_4ZZ_D |
| 17003 | 4128U, // SMIN_VG4_4ZZ_H |
| 17004 | 4208U, // SMIN_VG4_4ZZ_S |
| 17005 | 14432U, // SMIN_ZI_B |
| 17006 | 14432U, // SMIN_ZI_D |
| 17007 | 4328U, // SMIN_ZI_H |
| 17008 | 14432U, // SMIN_ZI_S |
| 17009 | 33824776U, // SMIN_ZPmZ_B |
| 17010 | 67381256U, // SMIN_ZPmZ_D |
| 17011 | 102266912U, // SMIN_ZPmZ_H |
| 17012 | 134492168U, // SMIN_ZPmZ_S |
| 17013 | 1861784U, // SMINv16i8 |
| 17014 | 2123936U, // SMINv2i32 |
| 17015 | 2386088U, // SMINv4i16 |
| 17016 | 813192U, // SMINv4i32 |
| 17017 | 1075344U, // SMINv8i16 |
| 17018 | 2648240U, // SMINv8i8 |
| 17019 | 106436704U, // SMLALB_ZZZI_D |
| 17020 | 106455136U, // SMLALB_ZZZI_S |
| 17021 | 6240U, // SMLALB_ZZZ_D |
| 17022 | 4376U, // SMLALB_ZZZ_H |
| 17023 | 24672U, // SMLALB_ZZZ_S |
| 17024 | 84521U, // SMLALL_MZZI_BtoS |
| 17025 | 84225U, // SMLALL_MZZI_HtoD |
| 17026 | 4649U, // SMLALL_MZZ_BtoS |
| 17027 | 4353U, // SMLALL_MZZ_HtoD |
| 17028 | 119320U, // SMLALL_VG2_M2Z2Z_BtoS |
| 17029 | 5273840U, // SMLALL_VG2_M2Z2Z_HtoD |
| 17030 | 10082840U, // SMLALL_VG2_M2ZZI_BtoS |
| 17031 | 206862576U, // SMLALL_VG2_M2ZZI_HtoD |
| 17032 | 121370U, // SMLALL_VG2_M2ZZ_BtoS |
| 17033 | 106199282U, // SMLALL_VG2_M2ZZ_HtoD |
| 17034 | 119321U, // SMLALL_VG4_M4Z4Z_BtoS |
| 17035 | 5273841U, // SMLALL_VG4_M4Z4Z_HtoD |
| 17036 | 10082841U, // SMLALL_VG4_M4ZZI_BtoS |
| 17037 | 206862577U, // SMLALL_VG4_M4ZZI_HtoD |
| 17038 | 121370U, // SMLALL_VG4_M4ZZ_BtoS |
| 17039 | 106199282U, // SMLALL_VG4_M4ZZ_HtoD |
| 17040 | 106436704U, // SMLALT_ZZZI_D |
| 17041 | 106455136U, // SMLALT_ZZZI_S |
| 17042 | 6240U, // SMLALT_ZZZ_D |
| 17043 | 4376U, // SMLALT_ZZZ_H |
| 17044 | 24672U, // SMLALT_ZZZ_S |
| 17045 | 84225U, // SMLAL_MZZI_HtoS |
| 17046 | 4353U, // SMLAL_MZZ_HtoS |
| 17047 | 5273840U, // SMLAL_VG2_M2Z2Z_HtoS |
| 17048 | 206862576U, // SMLAL_VG2_M2ZZI_S |
| 17049 | 106199280U, // SMLAL_VG2_M2ZZ_HtoS |
| 17050 | 5273841U, // SMLAL_VG4_M4Z4Z_HtoS |
| 17051 | 206862577U, // SMLAL_VG4_M4ZZI_HtoS |
| 17052 | 106199281U, // SMLAL_VG4_M4ZZ_HtoS |
| 17053 | 1863832U, // SMLALv16i8_v8i16 |
| 17054 | 244609184U, // SMLALv2i32_indexed |
| 17055 | 2125984U, // SMLALv2i32_v2i64 |
| 17056 | 240939176U, // SMLALv4i16_indexed |
| 17057 | 2388136U, // SMLALv4i16_v4i32 |
| 17058 | 244609160U, // SMLALv4i32_indexed |
| 17059 | 815240U, // SMLALv4i32_v2i64 |
| 17060 | 240939152U, // SMLALv8i16_indexed |
| 17061 | 1077392U, // SMLALv8i16_v4i32 |
| 17062 | 2650288U, // SMLALv8i8_v8i16 |
| 17063 | 106436704U, // SMLSLB_ZZZI_D |
| 17064 | 106455136U, // SMLSLB_ZZZI_S |
| 17065 | 6240U, // SMLSLB_ZZZ_D |
| 17066 | 4376U, // SMLSLB_ZZZ_H |
| 17067 | 24672U, // SMLSLB_ZZZ_S |
| 17068 | 84521U, // SMLSLL_MZZI_BtoS |
| 17069 | 84225U, // SMLSLL_MZZI_HtoD |
| 17070 | 4649U, // SMLSLL_MZZ_BtoS |
| 17071 | 4353U, // SMLSLL_MZZ_HtoD |
| 17072 | 119320U, // SMLSLL_VG2_M2Z2Z_BtoS |
| 17073 | 5273840U, // SMLSLL_VG2_M2Z2Z_HtoD |
| 17074 | 10082840U, // SMLSLL_VG2_M2ZZI_BtoS |
| 17075 | 206862576U, // SMLSLL_VG2_M2ZZI_HtoD |
| 17076 | 121370U, // SMLSLL_VG2_M2ZZ_BtoS |
| 17077 | 106199282U, // SMLSLL_VG2_M2ZZ_HtoD |
| 17078 | 119321U, // SMLSLL_VG4_M4Z4Z_BtoS |
| 17079 | 5273841U, // SMLSLL_VG4_M4Z4Z_HtoD |
| 17080 | 10082841U, // SMLSLL_VG4_M4ZZI_BtoS |
| 17081 | 206862577U, // SMLSLL_VG4_M4ZZI_HtoD |
| 17082 | 121370U, // SMLSLL_VG4_M4ZZ_BtoS |
| 17083 | 106199282U, // SMLSLL_VG4_M4ZZ_HtoD |
| 17084 | 106436704U, // SMLSLT_ZZZI_D |
| 17085 | 106455136U, // SMLSLT_ZZZI_S |
| 17086 | 6240U, // SMLSLT_ZZZ_D |
| 17087 | 4376U, // SMLSLT_ZZZ_H |
| 17088 | 24672U, // SMLSLT_ZZZ_S |
| 17089 | 84225U, // SMLSL_MZZI_HtoS |
| 17090 | 4353U, // SMLSL_MZZ_HtoS |
| 17091 | 5273840U, // SMLSL_VG2_M2Z2Z_HtoS |
| 17092 | 206862576U, // SMLSL_VG2_M2ZZI_S |
| 17093 | 106199280U, // SMLSL_VG2_M2ZZ_HtoS |
| 17094 | 5273841U, // SMLSL_VG4_M4Z4Z_HtoS |
| 17095 | 206862577U, // SMLSL_VG4_M4ZZI_HtoS |
| 17096 | 106199281U, // SMLSL_VG4_M4ZZ_HtoS |
| 17097 | 1863832U, // SMLSLv16i8_v8i16 |
| 17098 | 244609184U, // SMLSLv2i32_indexed |
| 17099 | 2125984U, // SMLSLv2i32_v2i64 |
| 17100 | 240939176U, // SMLSLv4i16_indexed |
| 17101 | 2388136U, // SMLSLv4i16_v4i32 |
| 17102 | 244609160U, // SMLSLv4i32_indexed |
| 17103 | 815240U, // SMLSLv4i32_v2i64 |
| 17104 | 240939152U, // SMLSLv8i16_indexed |
| 17105 | 1077392U, // SMLSLv8i16_v4i32 |
| 17106 | 2650288U, // SMLSLv8i8_v8i16 |
| 17107 | 1863832U, // SMMLA |
| 17108 | 4377U, // SMMLA_ZZZ |
| 17109 | 2U, // SMOP4A_M2Z2Z_BToS |
| 17110 | 1U, // SMOP4A_M2Z2Z_HToS |
| 17111 | 1U, // SMOP4A_M2Z2Z_HtoD |
| 17112 | 3U, // SMOP4A_M2ZZ_BToS |
| 17113 | 1U, // SMOP4A_M2ZZ_HToS |
| 17114 | 1U, // SMOP4A_M2ZZ_HtoD |
| 17115 | 560U, // SMOP4A_MZ2Z_BToS |
| 17116 | 264U, // SMOP4A_MZ2Z_HToS |
| 17117 | 264U, // SMOP4A_MZ2Z_HtoD |
| 17118 | 4376U, // SMOP4A_MZZ_BToS |
| 17119 | 4112U, // SMOP4A_MZZ_HToS |
| 17120 | 4112U, // SMOP4A_MZZ_HtoD |
| 17121 | 2U, // SMOP4S_M2Z2Z_BToS |
| 17122 | 1U, // SMOP4S_M2Z2Z_HToS |
| 17123 | 1U, // SMOP4S_M2Z2Z_HtoD |
| 17124 | 3U, // SMOP4S_M2ZZ_BToS |
| 17125 | 1U, // SMOP4S_M2ZZ_HToS |
| 17126 | 1U, // SMOP4S_M2ZZ_HtoD |
| 17127 | 560U, // SMOP4S_MZ2Z_BToS |
| 17128 | 264U, // SMOP4S_MZ2Z_HToS |
| 17129 | 264U, // SMOP4S_MZ2Z_HtoD |
| 17130 | 4376U, // SMOP4S_MZZ_BToS |
| 17131 | 4112U, // SMOP4S_MZZ_HToS |
| 17132 | 4112U, // SMOP4S_MZZ_HtoD |
| 17133 | 88168U, // SMOPA_MPPZZ_D |
| 17134 | 88168U, // SMOPA_MPPZZ_HtoS |
| 17135 | 127080U, // SMOPA_MPPZZ_S |
| 17136 | 88168U, // SMOPS_MPPZZ_D |
| 17137 | 88168U, // SMOPS_MPPZZ_HtoS |
| 17138 | 127080U, // SMOPS_MPPZZ_S |
| 17139 | 108936U, // SMOVvi16to32 |
| 17140 | 108936U, // SMOVvi16to32_idx0 |
| 17141 | 108936U, // SMOVvi16to64 |
| 17142 | 108936U, // SMOVvi16to64_idx0 |
| 17143 | 108944U, // SMOVvi32to64 |
| 17144 | 108944U, // SMOVvi32to64_idx0 |
| 17145 | 108960U, // SMOVvi8to32 |
| 17146 | 108960U, // SMOVvi8to32_idx0 |
| 17147 | 108960U, // SMOVvi8to64 |
| 17148 | 108960U, // SMOVvi8to64_idx0 |
| 17149 | 276576U, // SMSUBLrrr |
| 17150 | 33824776U, // SMULH_ZPmZ_B |
| 17151 | 67381256U, // SMULH_ZPmZ_D |
| 17152 | 102266912U, // SMULH_ZPmZ_H |
| 17153 | 134492168U, // SMULH_ZPmZ_S |
| 17154 | 8288U, // SMULH_ZZZ_B |
| 17155 | 10336U, // SMULH_ZZZ_D |
| 17156 | 4128U, // SMULH_ZZZ_H |
| 17157 | 12384U, // SMULH_ZZZ_S |
| 17158 | 14432U, // SMULHrr |
| 17159 | 11808864U, // SMULLB_ZZZI_D |
| 17160 | 11819104U, // SMULLB_ZZZI_S |
| 17161 | 12384U, // SMULLB_ZZZ_D |
| 17162 | 184U, // SMULLB_ZZZ_H |
| 17163 | 22624U, // SMULLB_ZZZ_S |
| 17164 | 11808864U, // SMULLT_ZZZI_D |
| 17165 | 11819104U, // SMULLT_ZZZI_S |
| 17166 | 12384U, // SMULLT_ZZZ_D |
| 17167 | 184U, // SMULLT_ZZZ_H |
| 17168 | 22624U, // SMULLT_ZZZ_S |
| 17169 | 1861784U, // SMULLv16i8_v8i16 |
| 17170 | 747923616U, // SMULLv2i32_indexed |
| 17171 | 2123936U, // SMULLv2i32_v2i64 |
| 17172 | 744253608U, // SMULLv4i16_indexed |
| 17173 | 2386088U, // SMULLv4i16_v4i32 |
| 17174 | 747923592U, // SMULLv4i32_indexed |
| 17175 | 813192U, // SMULLv4i32_v2i64 |
| 17176 | 744253584U, // SMULLv8i16_indexed |
| 17177 | 1075344U, // SMULLv8i16_v4i32 |
| 17178 | 2648240U, // SMULLv8i8_v8i16 |
| 17179 | 186464U, // SPLICE_ZPZZ_B |
| 17180 | 188512U, // SPLICE_ZPZZ_D |
| 17181 | 4344U, // SPLICE_ZPZZ_H |
| 17182 | 190560U, // SPLICE_ZPZZ_S |
| 17183 | 33824864U, // SPLICE_ZPZ_B |
| 17184 | 67381344U, // SPLICE_ZPZ_D |
| 17185 | 102266912U, // SPLICE_ZPZ_H |
| 17186 | 134492256U, // SPLICE_ZPZ_S |
| 17187 | 8U, // SQABS_ZPmZ_B |
| 17188 | 2056U, // SQABS_ZPmZ_D |
| 17189 | 4112U, // SQABS_ZPmZ_H |
| 17190 | 6152U, // SQABS_ZPmZ_S |
| 17191 | 8216U, // SQABS_ZPzZ_B |
| 17192 | 10264U, // SQABS_ZPzZ_D |
| 17193 | 4128U, // SQABS_ZPzZ_H |
| 17194 | 12312U, // SQABS_ZPzZ_S |
| 17195 | 40U, // SQABSv16i8 |
| 17196 | 0U, // SQABSv1i16 |
| 17197 | 0U, // SQABSv1i32 |
| 17198 | 0U, // SQABSv1i64 |
| 17199 | 0U, // SQABSv1i8 |
| 17200 | 48U, // SQABSv2i32 |
| 17201 | 56U, // SQABSv2i64 |
| 17202 | 64U, // SQABSv4i16 |
| 17203 | 72U, // SQABSv4i32 |
| 17204 | 80U, // SQABSv8i16 |
| 17205 | 88U, // SQABSv8i8 |
| 17206 | 39008U, // SQADD_ZI_B |
| 17207 | 41056U, // SQADD_ZI_D |
| 17208 | 216U, // SQADD_ZI_H |
| 17209 | 43104U, // SQADD_ZI_S |
| 17210 | 33824776U, // SQADD_ZPmZ_B |
| 17211 | 67381256U, // SQADD_ZPmZ_D |
| 17212 | 102266912U, // SQADD_ZPmZ_H |
| 17213 | 134492168U, // SQADD_ZPmZ_S |
| 17214 | 8288U, // SQADD_ZZZ_B |
| 17215 | 10336U, // SQADD_ZZZ_D |
| 17216 | 4128U, // SQADD_ZZZ_H |
| 17217 | 12384U, // SQADD_ZZZ_S |
| 17218 | 1861784U, // SQADDv16i8 |
| 17219 | 14432U, // SQADDv1i16 |
| 17220 | 14432U, // SQADDv1i32 |
| 17221 | 14432U, // SQADDv1i64 |
| 17222 | 14432U, // SQADDv1i8 |
| 17223 | 2123936U, // SQADDv2i32 |
| 17224 | 551040U, // SQADDv2i64 |
| 17225 | 2386088U, // SQADDv4i16 |
| 17226 | 813192U, // SQADDv4i32 |
| 17227 | 1075344U, // SQADDv8i16 |
| 17228 | 2648240U, // SQADDv8i8 |
| 17229 | 335814752U, // SQCADD_ZZI_B |
| 17230 | 335816800U, // SQCADD_ZZI_D |
| 17231 | 6584352U, // SQCADD_ZZI_H |
| 17232 | 335818848U, // SQCADD_ZZI_S |
| 17233 | 1U, // SQCVTN_Z2Z_StoH |
| 17234 | 1U, // SQCVTN_Z4Z_DtoH |
| 17235 | 2U, // SQCVTN_Z4Z_StoB |
| 17236 | 1U, // SQCVTUN_Z2Z_StoH |
| 17237 | 1U, // SQCVTUN_Z4Z_DtoH |
| 17238 | 2U, // SQCVTUN_Z4Z_StoB |
| 17239 | 1U, // SQCVTU_Z2Z_StoH |
| 17240 | 1U, // SQCVTU_Z4Z_DtoH |
| 17241 | 2U, // SQCVTU_Z4Z_StoB |
| 17242 | 1U, // SQCVT_Z2Z_StoH |
| 17243 | 1U, // SQCVT_Z4Z_DtoH |
| 17244 | 2U, // SQCVT_Z4Z_StoB |
| 17245 | 2U, // SQDECB_XPiI |
| 17246 | 4U, // SQDECB_XPiWdI |
| 17247 | 2U, // SQDECD_XPiI |
| 17248 | 4U, // SQDECD_XPiWdI |
| 17249 | 2U, // SQDECD_ZPiI |
| 17250 | 2U, // SQDECH_XPiI |
| 17251 | 4U, // SQDECH_XPiWdI |
| 17252 | 0U, // SQDECH_ZPiI |
| 17253 | 192608U, // SQDECP_XPWd_B |
| 17254 | 192608U, // SQDECP_XPWd_D |
| 17255 | 192608U, // SQDECP_XPWd_H |
| 17256 | 192608U, // SQDECP_XPWd_S |
| 17257 | 0U, // SQDECP_XP_B |
| 17258 | 0U, // SQDECP_XP_D |
| 17259 | 0U, // SQDECP_XP_H |
| 17260 | 0U, // SQDECP_XP_S |
| 17261 | 0U, // SQDECP_ZP_D |
| 17262 | 1U, // SQDECP_ZP_H |
| 17263 | 0U, // SQDECP_ZP_S |
| 17264 | 2U, // SQDECW_XPiI |
| 17265 | 4U, // SQDECW_XPiWdI |
| 17266 | 2U, // SQDECW_ZPiI |
| 17267 | 6240U, // SQDMLALBT_ZZZ_D |
| 17268 | 4376U, // SQDMLALBT_ZZZ_H |
| 17269 | 24672U, // SQDMLALBT_ZZZ_S |
| 17270 | 106436704U, // SQDMLALB_ZZZI_D |
| 17271 | 106455136U, // SQDMLALB_ZZZI_S |
| 17272 | 6240U, // SQDMLALB_ZZZ_D |
| 17273 | 4376U, // SQDMLALB_ZZZ_H |
| 17274 | 24672U, // SQDMLALB_ZZZ_S |
| 17275 | 106436704U, // SQDMLALT_ZZZI_D |
| 17276 | 106455136U, // SQDMLALT_ZZZI_S |
| 17277 | 6240U, // SQDMLALT_ZZZ_D |
| 17278 | 4376U, // SQDMLALT_ZZZ_H |
| 17279 | 24672U, // SQDMLALT_ZZZ_S |
| 17280 | 90209U, // SQDMLALi16 |
| 17281 | 90209U, // SQDMLALi32 |
| 17282 | 240939105U, // SQDMLALv1i32_indexed |
| 17283 | 244609121U, // SQDMLALv1i64_indexed |
| 17284 | 244609184U, // SQDMLALv2i32_indexed |
| 17285 | 2125984U, // SQDMLALv2i32_v2i64 |
| 17286 | 240939176U, // SQDMLALv4i16_indexed |
| 17287 | 2388136U, // SQDMLALv4i16_v4i32 |
| 17288 | 244609160U, // SQDMLALv4i32_indexed |
| 17289 | 815240U, // SQDMLALv4i32_v2i64 |
| 17290 | 240939152U, // SQDMLALv8i16_indexed |
| 17291 | 1077392U, // SQDMLALv8i16_v4i32 |
| 17292 | 6240U, // SQDMLSLBT_ZZZ_D |
| 17293 | 4376U, // SQDMLSLBT_ZZZ_H |
| 17294 | 24672U, // SQDMLSLBT_ZZZ_S |
| 17295 | 106436704U, // SQDMLSLB_ZZZI_D |
| 17296 | 106455136U, // SQDMLSLB_ZZZI_S |
| 17297 | 6240U, // SQDMLSLB_ZZZ_D |
| 17298 | 4376U, // SQDMLSLB_ZZZ_H |
| 17299 | 24672U, // SQDMLSLB_ZZZ_S |
| 17300 | 106436704U, // SQDMLSLT_ZZZI_D |
| 17301 | 106455136U, // SQDMLSLT_ZZZI_S |
| 17302 | 6240U, // SQDMLSLT_ZZZ_D |
| 17303 | 4376U, // SQDMLSLT_ZZZ_H |
| 17304 | 24672U, // SQDMLSLT_ZZZ_S |
| 17305 | 90209U, // SQDMLSLi16 |
| 17306 | 90209U, // SQDMLSLi32 |
| 17307 | 240939105U, // SQDMLSLv1i32_indexed |
| 17308 | 244609121U, // SQDMLSLv1i64_indexed |
| 17309 | 244609184U, // SQDMLSLv2i32_indexed |
| 17310 | 2125984U, // SQDMLSLv2i32_v2i64 |
| 17311 | 240939176U, // SQDMLSLv4i16_indexed |
| 17312 | 2388136U, // SQDMLSLv4i16_v4i32 |
| 17313 | 244609160U, // SQDMLSLv4i32_indexed |
| 17314 | 815240U, // SQDMLSLv4i32_v2i64 |
| 17315 | 240939152U, // SQDMLSLv8i16_indexed |
| 17316 | 1077392U, // SQDMLSLv8i16_v4i32 |
| 17317 | 5040U, // SQDMULH_VG2_2Z2Z_B |
| 17318 | 4552U, // SQDMULH_VG2_2Z2Z_D |
| 17319 | 4344U, // SQDMULH_VG2_2Z2Z_H |
| 17320 | 4560U, // SQDMULH_VG2_2Z2Z_S |
| 17321 | 184U, // SQDMULH_VG2_2ZZ_B |
| 17322 | 4288U, // SQDMULH_VG2_2ZZ_D |
| 17323 | 4128U, // SQDMULH_VG2_2ZZ_H |
| 17324 | 4208U, // SQDMULH_VG2_2ZZ_S |
| 17325 | 5040U, // SQDMULH_VG4_4Z4Z_B |
| 17326 | 4552U, // SQDMULH_VG4_4Z4Z_D |
| 17327 | 4344U, // SQDMULH_VG4_4Z4Z_H |
| 17328 | 4560U, // SQDMULH_VG4_4Z4Z_S |
| 17329 | 184U, // SQDMULH_VG4_4ZZ_B |
| 17330 | 4288U, // SQDMULH_VG4_4ZZ_D |
| 17331 | 4128U, // SQDMULH_VG4_4ZZ_H |
| 17332 | 4208U, // SQDMULH_VG4_4ZZ_S |
| 17333 | 11806816U, // SQDMULH_ZZZI_D |
| 17334 | 77856U, // SQDMULH_ZZZI_H |
| 17335 | 11808864U, // SQDMULH_ZZZI_S |
| 17336 | 8288U, // SQDMULH_ZZZ_B |
| 17337 | 10336U, // SQDMULH_ZZZ_D |
| 17338 | 4128U, // SQDMULH_ZZZ_H |
| 17339 | 12384U, // SQDMULH_ZZZ_S |
| 17340 | 14432U, // SQDMULHv1i16 |
| 17341 | 744253536U, // SQDMULHv1i16_indexed |
| 17342 | 14432U, // SQDMULHv1i32 |
| 17343 | 747923552U, // SQDMULHv1i32_indexed |
| 17344 | 2123936U, // SQDMULHv2i32 |
| 17345 | 747923616U, // SQDMULHv2i32_indexed |
| 17346 | 2386088U, // SQDMULHv4i16 |
| 17347 | 744253608U, // SQDMULHv4i16_indexed |
| 17348 | 813192U, // SQDMULHv4i32 |
| 17349 | 747923592U, // SQDMULHv4i32_indexed |
| 17350 | 1075344U, // SQDMULHv8i16 |
| 17351 | 744253584U, // SQDMULHv8i16_indexed |
| 17352 | 11808864U, // SQDMULLB_ZZZI_D |
| 17353 | 11819104U, // SQDMULLB_ZZZI_S |
| 17354 | 12384U, // SQDMULLB_ZZZ_D |
| 17355 | 184U, // SQDMULLB_ZZZ_H |
| 17356 | 22624U, // SQDMULLB_ZZZ_S |
| 17357 | 11808864U, // SQDMULLT_ZZZI_D |
| 17358 | 11819104U, // SQDMULLT_ZZZI_S |
| 17359 | 12384U, // SQDMULLT_ZZZ_D |
| 17360 | 184U, // SQDMULLT_ZZZ_H |
| 17361 | 22624U, // SQDMULLT_ZZZ_S |
| 17362 | 14432U, // SQDMULLi16 |
| 17363 | 14432U, // SQDMULLi32 |
| 17364 | 744253536U, // SQDMULLv1i32_indexed |
| 17365 | 747923552U, // SQDMULLv1i64_indexed |
| 17366 | 747923616U, // SQDMULLv2i32_indexed |
| 17367 | 2123936U, // SQDMULLv2i32_v2i64 |
| 17368 | 744253608U, // SQDMULLv4i16_indexed |
| 17369 | 2386088U, // SQDMULLv4i16_v4i32 |
| 17370 | 747923592U, // SQDMULLv4i32_indexed |
| 17371 | 813192U, // SQDMULLv4i32_v2i64 |
| 17372 | 744253584U, // SQDMULLv8i16_indexed |
| 17373 | 1075344U, // SQDMULLv8i16_v4i32 |
| 17374 | 2U, // SQINCB_XPiI |
| 17375 | 4U, // SQINCB_XPiWdI |
| 17376 | 2U, // SQINCD_XPiI |
| 17377 | 4U, // SQINCD_XPiWdI |
| 17378 | 2U, // SQINCD_ZPiI |
| 17379 | 2U, // SQINCH_XPiI |
| 17380 | 4U, // SQINCH_XPiWdI |
| 17381 | 0U, // SQINCH_ZPiI |
| 17382 | 192608U, // SQINCP_XPWd_B |
| 17383 | 192608U, // SQINCP_XPWd_D |
| 17384 | 192608U, // SQINCP_XPWd_H |
| 17385 | 192608U, // SQINCP_XPWd_S |
| 17386 | 0U, // SQINCP_XP_B |
| 17387 | 0U, // SQINCP_XP_D |
| 17388 | 0U, // SQINCP_XP_H |
| 17389 | 0U, // SQINCP_XP_S |
| 17390 | 0U, // SQINCP_ZP_D |
| 17391 | 1U, // SQINCP_ZP_H |
| 17392 | 0U, // SQINCP_ZP_S |
| 17393 | 2U, // SQINCW_XPiI |
| 17394 | 4U, // SQINCW_XPiWdI |
| 17395 | 2U, // SQINCW_ZPiI |
| 17396 | 8U, // SQNEG_ZPmZ_B |
| 17397 | 2056U, // SQNEG_ZPmZ_D |
| 17398 | 4112U, // SQNEG_ZPmZ_H |
| 17399 | 6152U, // SQNEG_ZPmZ_S |
| 17400 | 8216U, // SQNEG_ZPzZ_B |
| 17401 | 10264U, // SQNEG_ZPzZ_D |
| 17402 | 4128U, // SQNEG_ZPzZ_H |
| 17403 | 12312U, // SQNEG_ZPzZ_S |
| 17404 | 40U, // SQNEGv16i8 |
| 17405 | 0U, // SQNEGv1i16 |
| 17406 | 0U, // SQNEGv1i32 |
| 17407 | 0U, // SQNEGv1i64 |
| 17408 | 0U, // SQNEGv1i8 |
| 17409 | 48U, // SQNEGv2i32 |
| 17410 | 56U, // SQNEGv2i64 |
| 17411 | 64U, // SQNEGv4i16 |
| 17412 | 72U, // SQNEGv4i32 |
| 17413 | 80U, // SQNEGv8i16 |
| 17414 | 88U, // SQNEGv8i8 |
| 17415 | 436555792U, // SQRDCMLAH_ZZZI_H |
| 17416 | 408426592U, // SQRDCMLAH_ZZZI_S |
| 17417 | 7108889U, // SQRDCMLAH_ZZZ_B |
| 17418 | 470026336U, // SQRDCMLAH_ZZZ_D |
| 17419 | 7108624U, // SQRDCMLAH_ZZZ_H |
| 17420 | 470030432U, // SQRDCMLAH_ZZZ_S |
| 17421 | 106432608U, // SQRDMLAH_ZZZI_D |
| 17422 | 86032U, // SQRDMLAH_ZZZI_H |
| 17423 | 106436704U, // SQRDMLAH_ZZZI_S |
| 17424 | 4377U, // SQRDMLAH_ZZZ_B |
| 17425 | 2144U, // SQRDMLAH_ZZZ_D |
| 17426 | 4112U, // SQRDMLAH_ZZZ_H |
| 17427 | 6240U, // SQRDMLAH_ZZZ_S |
| 17428 | 90209U, // SQRDMLAHv1i16 |
| 17429 | 240939105U, // SQRDMLAHv1i16_indexed |
| 17430 | 90209U, // SQRDMLAHv1i32 |
| 17431 | 244609121U, // SQRDMLAHv1i32_indexed |
| 17432 | 2125984U, // SQRDMLAHv2i32 |
| 17433 | 244609184U, // SQRDMLAHv2i32_indexed |
| 17434 | 2388136U, // SQRDMLAHv4i16 |
| 17435 | 240939176U, // SQRDMLAHv4i16_indexed |
| 17436 | 815240U, // SQRDMLAHv4i32 |
| 17437 | 244609160U, // SQRDMLAHv4i32_indexed |
| 17438 | 1077392U, // SQRDMLAHv8i16 |
| 17439 | 240939152U, // SQRDMLAHv8i16_indexed |
| 17440 | 106432608U, // SQRDMLSH_ZZZI_D |
| 17441 | 86032U, // SQRDMLSH_ZZZI_H |
| 17442 | 106436704U, // SQRDMLSH_ZZZI_S |
| 17443 | 4377U, // SQRDMLSH_ZZZ_B |
| 17444 | 2144U, // SQRDMLSH_ZZZ_D |
| 17445 | 4112U, // SQRDMLSH_ZZZ_H |
| 17446 | 6240U, // SQRDMLSH_ZZZ_S |
| 17447 | 90209U, // SQRDMLSHv1i16 |
| 17448 | 240939105U, // SQRDMLSHv1i16_indexed |
| 17449 | 90209U, // SQRDMLSHv1i32 |
| 17450 | 244609121U, // SQRDMLSHv1i32_indexed |
| 17451 | 2125984U, // SQRDMLSHv2i32 |
| 17452 | 244609184U, // SQRDMLSHv2i32_indexed |
| 17453 | 2388136U, // SQRDMLSHv4i16 |
| 17454 | 240939176U, // SQRDMLSHv4i16_indexed |
| 17455 | 815240U, // SQRDMLSHv4i32 |
| 17456 | 244609160U, // SQRDMLSHv4i32_indexed |
| 17457 | 1077392U, // SQRDMLSHv8i16 |
| 17458 | 240939152U, // SQRDMLSHv8i16_indexed |
| 17459 | 11806816U, // SQRDMULH_ZZZI_D |
| 17460 | 77856U, // SQRDMULH_ZZZI_H |
| 17461 | 11808864U, // SQRDMULH_ZZZI_S |
| 17462 | 8288U, // SQRDMULH_ZZZ_B |
| 17463 | 10336U, // SQRDMULH_ZZZ_D |
| 17464 | 4128U, // SQRDMULH_ZZZ_H |
| 17465 | 12384U, // SQRDMULH_ZZZ_S |
| 17466 | 14432U, // SQRDMULHv1i16 |
| 17467 | 744253536U, // SQRDMULHv1i16_indexed |
| 17468 | 14432U, // SQRDMULHv1i32 |
| 17469 | 747923552U, // SQRDMULHv1i32_indexed |
| 17470 | 2123936U, // SQRDMULHv2i32 |
| 17471 | 747923616U, // SQRDMULHv2i32_indexed |
| 17472 | 2386088U, // SQRDMULHv4i16 |
| 17473 | 744253608U, // SQRDMULHv4i16_indexed |
| 17474 | 813192U, // SQRDMULHv4i32 |
| 17475 | 747923592U, // SQRDMULHv4i32_indexed |
| 17476 | 1075344U, // SQRDMULHv8i16 |
| 17477 | 744253584U, // SQRDMULHv8i16_indexed |
| 17478 | 33824776U, // SQRSHLR_ZPmZ_B |
| 17479 | 67381256U, // SQRSHLR_ZPmZ_D |
| 17480 | 102266912U, // SQRSHLR_ZPmZ_H |
| 17481 | 134492168U, // SQRSHLR_ZPmZ_S |
| 17482 | 33824776U, // SQRSHL_ZPmZ_B |
| 17483 | 67381256U, // SQRSHL_ZPmZ_D |
| 17484 | 102266912U, // SQRSHL_ZPmZ_H |
| 17485 | 134492168U, // SQRSHL_ZPmZ_S |
| 17486 | 1861784U, // SQRSHLv16i8 |
| 17487 | 14432U, // SQRSHLv1i16 |
| 17488 | 14432U, // SQRSHLv1i32 |
| 17489 | 14432U, // SQRSHLv1i64 |
| 17490 | 14432U, // SQRSHLv1i8 |
| 17491 | 2123936U, // SQRSHLv2i32 |
| 17492 | 551040U, // SQRSHLv2i64 |
| 17493 | 2386088U, // SQRSHLv4i16 |
| 17494 | 813192U, // SQRSHLv4i32 |
| 17495 | 1075344U, // SQRSHLv8i16 |
| 17496 | 2648240U, // SQRSHLv8i8 |
| 17497 | 14432U, // SQRSHRNB_ZZI_B |
| 17498 | 4328U, // SQRSHRNB_ZZI_H |
| 17499 | 14432U, // SQRSHRNB_ZZI_S |
| 17500 | 90208U, // SQRSHRNT_ZZI_B |
| 17501 | 4464U, // SQRSHRNT_ZZI_H |
| 17502 | 90208U, // SQRSHRNT_ZZI_S |
| 17503 | 14434U, // SQRSHRN_VG4_Z4ZI_B |
| 17504 | 4328U, // SQRSHRN_VG4_Z4ZI_H |
| 17505 | 14433U, // SQRSHRN_Z2ZI_HtoB |
| 17506 | 4328U, // SQRSHRN_Z2ZI_StoH |
| 17507 | 14432U, // SQRSHRNb |
| 17508 | 14432U, // SQRSHRNh |
| 17509 | 14432U, // SQRSHRNs |
| 17510 | 90256U, // SQRSHRNv16i8_shift |
| 17511 | 14464U, // SQRSHRNv2i32_shift |
| 17512 | 14472U, // SQRSHRNv4i16_shift |
| 17513 | 90240U, // SQRSHRNv4i32_shift |
| 17514 | 90248U, // SQRSHRNv8i16_shift |
| 17515 | 14480U, // SQRSHRNv8i8_shift |
| 17516 | 14432U, // SQRSHRUNB_ZZI_B |
| 17517 | 4328U, // SQRSHRUNB_ZZI_H |
| 17518 | 14432U, // SQRSHRUNB_ZZI_S |
| 17519 | 90208U, // SQRSHRUNT_ZZI_B |
| 17520 | 4464U, // SQRSHRUNT_ZZI_H |
| 17521 | 90208U, // SQRSHRUNT_ZZI_S |
| 17522 | 14434U, // SQRSHRUN_VG4_Z4ZI_B |
| 17523 | 4328U, // SQRSHRUN_VG4_Z4ZI_H |
| 17524 | 14433U, // SQRSHRUN_Z2ZI_HtoB |
| 17525 | 4328U, // SQRSHRUN_Z2ZI_StoH |
| 17526 | 14432U, // SQRSHRUNb |
| 17527 | 14432U, // SQRSHRUNh |
| 17528 | 14432U, // SQRSHRUNs |
| 17529 | 90256U, // SQRSHRUNv16i8_shift |
| 17530 | 14464U, // SQRSHRUNv2i32_shift |
| 17531 | 14472U, // SQRSHRUNv4i16_shift |
| 17532 | 90240U, // SQRSHRUNv4i32_shift |
| 17533 | 90248U, // SQRSHRUNv8i16_shift |
| 17534 | 14480U, // SQRSHRUNv8i8_shift |
| 17535 | 4328U, // SQRSHRU_VG2_Z2ZI_H |
| 17536 | 14434U, // SQRSHRU_VG4_Z4ZI_B |
| 17537 | 4328U, // SQRSHRU_VG4_Z4ZI_H |
| 17538 | 4328U, // SQRSHR_VG2_Z2ZI_H |
| 17539 | 14434U, // SQRSHR_VG4_Z4ZI_B |
| 17540 | 4328U, // SQRSHR_VG4_Z4ZI_H |
| 17541 | 33824776U, // SQSHLR_ZPmZ_B |
| 17542 | 67381256U, // SQSHLR_ZPmZ_D |
| 17543 | 102266912U, // SQSHLR_ZPmZ_H |
| 17544 | 134492168U, // SQSHLR_ZPmZ_S |
| 17545 | 270344U, // SQSHLU_ZPmI_B |
| 17546 | 272392U, // SQSHLU_ZPmI_D |
| 17547 | 104888352U, // SQSHLU_ZPmI_H |
| 17548 | 274440U, // SQSHLU_ZPmI_S |
| 17549 | 14432U, // SQSHLUb |
| 17550 | 14432U, // SQSHLUd |
| 17551 | 14432U, // SQSHLUh |
| 17552 | 14432U, // SQSHLUs |
| 17553 | 14488U, // SQSHLUv16i8_shift |
| 17554 | 14496U, // SQSHLUv2i32_shift |
| 17555 | 14464U, // SQSHLUv2i64_shift |
| 17556 | 14504U, // SQSHLUv4i16_shift |
| 17557 | 14472U, // SQSHLUv4i32_shift |
| 17558 | 14480U, // SQSHLUv8i16_shift |
| 17559 | 14512U, // SQSHLUv8i8_shift |
| 17560 | 270344U, // SQSHL_ZPmI_B |
| 17561 | 272392U, // SQSHL_ZPmI_D |
| 17562 | 104888352U, // SQSHL_ZPmI_H |
| 17563 | 274440U, // SQSHL_ZPmI_S |
| 17564 | 33824776U, // SQSHL_ZPmZ_B |
| 17565 | 67381256U, // SQSHL_ZPmZ_D |
| 17566 | 102266912U, // SQSHL_ZPmZ_H |
| 17567 | 134492168U, // SQSHL_ZPmZ_S |
| 17568 | 14432U, // SQSHLb |
| 17569 | 14432U, // SQSHLd |
| 17570 | 14432U, // SQSHLh |
| 17571 | 14432U, // SQSHLs |
| 17572 | 1861784U, // SQSHLv16i8 |
| 17573 | 14488U, // SQSHLv16i8_shift |
| 17574 | 14432U, // SQSHLv1i16 |
| 17575 | 14432U, // SQSHLv1i32 |
| 17576 | 14432U, // SQSHLv1i64 |
| 17577 | 14432U, // SQSHLv1i8 |
| 17578 | 2123936U, // SQSHLv2i32 |
| 17579 | 14496U, // SQSHLv2i32_shift |
| 17580 | 551040U, // SQSHLv2i64 |
| 17581 | 14464U, // SQSHLv2i64_shift |
| 17582 | 2386088U, // SQSHLv4i16 |
| 17583 | 14504U, // SQSHLv4i16_shift |
| 17584 | 813192U, // SQSHLv4i32 |
| 17585 | 14472U, // SQSHLv4i32_shift |
| 17586 | 1075344U, // SQSHLv8i16 |
| 17587 | 14480U, // SQSHLv8i16_shift |
| 17588 | 2648240U, // SQSHLv8i8 |
| 17589 | 14512U, // SQSHLv8i8_shift |
| 17590 | 14432U, // SQSHRNB_ZZI_B |
| 17591 | 4328U, // SQSHRNB_ZZI_H |
| 17592 | 14432U, // SQSHRNB_ZZI_S |
| 17593 | 90208U, // SQSHRNT_ZZI_B |
| 17594 | 4464U, // SQSHRNT_ZZI_H |
| 17595 | 90208U, // SQSHRNT_ZZI_S |
| 17596 | 14433U, // SQSHRN_Z2ZI_HtoB |
| 17597 | 4328U, // SQSHRN_Z2ZI_StoH |
| 17598 | 14432U, // SQSHRNb |
| 17599 | 14432U, // SQSHRNh |
| 17600 | 14432U, // SQSHRNs |
| 17601 | 90256U, // SQSHRNv16i8_shift |
| 17602 | 14464U, // SQSHRNv2i32_shift |
| 17603 | 14472U, // SQSHRNv4i16_shift |
| 17604 | 90240U, // SQSHRNv4i32_shift |
| 17605 | 90248U, // SQSHRNv8i16_shift |
| 17606 | 14480U, // SQSHRNv8i8_shift |
| 17607 | 14432U, // SQSHRUNB_ZZI_B |
| 17608 | 4328U, // SQSHRUNB_ZZI_H |
| 17609 | 14432U, // SQSHRUNB_ZZI_S |
| 17610 | 90208U, // SQSHRUNT_ZZI_B |
| 17611 | 4464U, // SQSHRUNT_ZZI_H |
| 17612 | 90208U, // SQSHRUNT_ZZI_S |
| 17613 | 14433U, // SQSHRUN_Z2ZI_HtoB |
| 17614 | 4328U, // SQSHRUN_Z2ZI_StoH |
| 17615 | 14432U, // SQSHRUNb |
| 17616 | 14432U, // SQSHRUNh |
| 17617 | 14432U, // SQSHRUNs |
| 17618 | 90256U, // SQSHRUNv16i8_shift |
| 17619 | 14464U, // SQSHRUNv2i32_shift |
| 17620 | 14472U, // SQSHRUNv4i16_shift |
| 17621 | 90240U, // SQSHRUNv4i32_shift |
| 17622 | 90248U, // SQSHRUNv8i16_shift |
| 17623 | 14480U, // SQSHRUNv8i8_shift |
| 17624 | 33824776U, // SQSUBR_ZPmZ_B |
| 17625 | 67381256U, // SQSUBR_ZPmZ_D |
| 17626 | 102266912U, // SQSUBR_ZPmZ_H |
| 17627 | 134492168U, // SQSUBR_ZPmZ_S |
| 17628 | 39008U, // SQSUB_ZI_B |
| 17629 | 41056U, // SQSUB_ZI_D |
| 17630 | 216U, // SQSUB_ZI_H |
| 17631 | 43104U, // SQSUB_ZI_S |
| 17632 | 33824776U, // SQSUB_ZPmZ_B |
| 17633 | 67381256U, // SQSUB_ZPmZ_D |
| 17634 | 102266912U, // SQSUB_ZPmZ_H |
| 17635 | 134492168U, // SQSUB_ZPmZ_S |
| 17636 | 8288U, // SQSUB_ZZZ_B |
| 17637 | 10336U, // SQSUB_ZZZ_D |
| 17638 | 4128U, // SQSUB_ZZZ_H |
| 17639 | 12384U, // SQSUB_ZZZ_S |
| 17640 | 1861784U, // SQSUBv16i8 |
| 17641 | 14432U, // SQSUBv1i16 |
| 17642 | 14432U, // SQSUBv1i32 |
| 17643 | 14432U, // SQSUBv1i64 |
| 17644 | 14432U, // SQSUBv1i8 |
| 17645 | 2123936U, // SQSUBv2i32 |
| 17646 | 551040U, // SQSUBv2i64 |
| 17647 | 2386088U, // SQSUBv4i16 |
| 17648 | 813192U, // SQSUBv4i32 |
| 17649 | 1075344U, // SQSUBv8i16 |
| 17650 | 2648240U, // SQSUBv8i8 |
| 17651 | 0U, // SQXTNB_ZZ_B |
| 17652 | 1U, // SQXTNB_ZZ_H |
| 17653 | 0U, // SQXTNB_ZZ_S |
| 17654 | 0U, // SQXTNT_ZZ_B |
| 17655 | 1U, // SQXTNT_ZZ_H |
| 17656 | 0U, // SQXTNT_ZZ_S |
| 17657 | 80U, // SQXTNv16i8 |
| 17658 | 0U, // SQXTNv1i16 |
| 17659 | 0U, // SQXTNv1i32 |
| 17660 | 0U, // SQXTNv1i8 |
| 17661 | 56U, // SQXTNv2i32 |
| 17662 | 72U, // SQXTNv4i16 |
| 17663 | 56U, // SQXTNv4i32 |
| 17664 | 72U, // SQXTNv8i16 |
| 17665 | 80U, // SQXTNv8i8 |
| 17666 | 0U, // SQXTUNB_ZZ_B |
| 17667 | 1U, // SQXTUNB_ZZ_H |
| 17668 | 0U, // SQXTUNB_ZZ_S |
| 17669 | 0U, // SQXTUNT_ZZ_B |
| 17670 | 1U, // SQXTUNT_ZZ_H |
| 17671 | 0U, // SQXTUNT_ZZ_S |
| 17672 | 80U, // SQXTUNv16i8 |
| 17673 | 0U, // SQXTUNv1i16 |
| 17674 | 0U, // SQXTUNv1i32 |
| 17675 | 0U, // SQXTUNv1i8 |
| 17676 | 56U, // SQXTUNv2i32 |
| 17677 | 72U, // SQXTUNv4i16 |
| 17678 | 56U, // SQXTUNv4i32 |
| 17679 | 72U, // SQXTUNv8i16 |
| 17680 | 80U, // SQXTUNv8i8 |
| 17681 | 33824776U, // SRHADD_ZPmZ_B |
| 17682 | 67381256U, // SRHADD_ZPmZ_D |
| 17683 | 102266912U, // SRHADD_ZPmZ_H |
| 17684 | 134492168U, // SRHADD_ZPmZ_S |
| 17685 | 1861784U, // SRHADDv16i8 |
| 17686 | 2123936U, // SRHADDv2i32 |
| 17687 | 2386088U, // SRHADDv4i16 |
| 17688 | 813192U, // SRHADDv4i32 |
| 17689 | 1075344U, // SRHADDv8i16 |
| 17690 | 2648240U, // SRHADDv8i8 |
| 17691 | 4465U, // SRI_ZZI_B |
| 17692 | 90208U, // SRI_ZZI_D |
| 17693 | 4464U, // SRI_ZZI_H |
| 17694 | 90208U, // SRI_ZZI_S |
| 17695 | 90209U, // SRId |
| 17696 | 90264U, // SRIv16i8_shift |
| 17697 | 90272U, // SRIv2i32_shift |
| 17698 | 90240U, // SRIv2i64_shift |
| 17699 | 90280U, // SRIv4i16_shift |
| 17700 | 90248U, // SRIv4i32_shift |
| 17701 | 90256U, // SRIv8i16_shift |
| 17702 | 90288U, // SRIv8i8_shift |
| 17703 | 33824776U, // SRSHLR_ZPmZ_B |
| 17704 | 67381256U, // SRSHLR_ZPmZ_D |
| 17705 | 102266912U, // SRSHLR_ZPmZ_H |
| 17706 | 134492168U, // SRSHLR_ZPmZ_S |
| 17707 | 5040U, // SRSHL_VG2_2Z2Z_B |
| 17708 | 4552U, // SRSHL_VG2_2Z2Z_D |
| 17709 | 4344U, // SRSHL_VG2_2Z2Z_H |
| 17710 | 4560U, // SRSHL_VG2_2Z2Z_S |
| 17711 | 184U, // SRSHL_VG2_2ZZ_B |
| 17712 | 4288U, // SRSHL_VG2_2ZZ_D |
| 17713 | 4128U, // SRSHL_VG2_2ZZ_H |
| 17714 | 4208U, // SRSHL_VG2_2ZZ_S |
| 17715 | 5040U, // SRSHL_VG4_4Z4Z_B |
| 17716 | 4552U, // SRSHL_VG4_4Z4Z_D |
| 17717 | 4344U, // SRSHL_VG4_4Z4Z_H |
| 17718 | 4560U, // SRSHL_VG4_4Z4Z_S |
| 17719 | 184U, // SRSHL_VG4_4ZZ_B |
| 17720 | 4288U, // SRSHL_VG4_4ZZ_D |
| 17721 | 4128U, // SRSHL_VG4_4ZZ_H |
| 17722 | 4208U, // SRSHL_VG4_4ZZ_S |
| 17723 | 33824776U, // SRSHL_ZPmZ_B |
| 17724 | 67381256U, // SRSHL_ZPmZ_D |
| 17725 | 102266912U, // SRSHL_ZPmZ_H |
| 17726 | 134492168U, // SRSHL_ZPmZ_S |
| 17727 | 1861784U, // SRSHLv16i8 |
| 17728 | 14432U, // SRSHLv1i64 |
| 17729 | 2123936U, // SRSHLv2i32 |
| 17730 | 551040U, // SRSHLv2i64 |
| 17731 | 2386088U, // SRSHLv4i16 |
| 17732 | 813192U, // SRSHLv4i32 |
| 17733 | 1075344U, // SRSHLv8i16 |
| 17734 | 2648240U, // SRSHLv8i8 |
| 17735 | 270344U, // SRSHR_ZPmI_B |
| 17736 | 272392U, // SRSHR_ZPmI_D |
| 17737 | 104888352U, // SRSHR_ZPmI_H |
| 17738 | 274440U, // SRSHR_ZPmI_S |
| 17739 | 14432U, // SRSHRd |
| 17740 | 14488U, // SRSHRv16i8_shift |
| 17741 | 14496U, // SRSHRv2i32_shift |
| 17742 | 14464U, // SRSHRv2i64_shift |
| 17743 | 14504U, // SRSHRv4i16_shift |
| 17744 | 14472U, // SRSHRv4i32_shift |
| 17745 | 14480U, // SRSHRv8i16_shift |
| 17746 | 14512U, // SRSHRv8i8_shift |
| 17747 | 4465U, // SRSRA_ZZI_B |
| 17748 | 90208U, // SRSRA_ZZI_D |
| 17749 | 4464U, // SRSRA_ZZI_H |
| 17750 | 90208U, // SRSRA_ZZI_S |
| 17751 | 90209U, // SRSRAd |
| 17752 | 90264U, // SRSRAv16i8_shift |
| 17753 | 90272U, // SRSRAv2i32_shift |
| 17754 | 90240U, // SRSRAv2i64_shift |
| 17755 | 90280U, // SRSRAv4i16_shift |
| 17756 | 90248U, // SRSRAv4i32_shift |
| 17757 | 90256U, // SRSRAv8i16_shift |
| 17758 | 90288U, // SRSRAv8i8_shift |
| 17759 | 14432U, // SSHLLB_ZZI_D |
| 17760 | 4328U, // SSHLLB_ZZI_H |
| 17761 | 14432U, // SSHLLB_ZZI_S |
| 17762 | 14432U, // SSHLLT_ZZI_D |
| 17763 | 4328U, // SSHLLT_ZZI_H |
| 17764 | 14432U, // SSHLLT_ZZI_S |
| 17765 | 14488U, // SSHLLv16i8_shift |
| 17766 | 14496U, // SSHLLv2i32_shift |
| 17767 | 14504U, // SSHLLv4i16_shift |
| 17768 | 14472U, // SSHLLv4i32_shift |
| 17769 | 14480U, // SSHLLv8i16_shift |
| 17770 | 14512U, // SSHLLv8i8_shift |
| 17771 | 1861784U, // SSHLv16i8 |
| 17772 | 14432U, // SSHLv1i64 |
| 17773 | 2123936U, // SSHLv2i32 |
| 17774 | 551040U, // SSHLv2i64 |
| 17775 | 2386088U, // SSHLv4i16 |
| 17776 | 813192U, // SSHLv4i32 |
| 17777 | 1075344U, // SSHLv8i16 |
| 17778 | 2648240U, // SSHLv8i8 |
| 17779 | 14432U, // SSHRd |
| 17780 | 14488U, // SSHRv16i8_shift |
| 17781 | 14496U, // SSHRv2i32_shift |
| 17782 | 14464U, // SSHRv2i64_shift |
| 17783 | 14504U, // SSHRv4i16_shift |
| 17784 | 14472U, // SSHRv4i32_shift |
| 17785 | 14480U, // SSHRv8i16_shift |
| 17786 | 14512U, // SSHRv8i8_shift |
| 17787 | 4465U, // SSRA_ZZI_B |
| 17788 | 90208U, // SSRA_ZZI_D |
| 17789 | 4464U, // SSRA_ZZI_H |
| 17790 | 90208U, // SSRA_ZZI_S |
| 17791 | 90209U, // SSRAd |
| 17792 | 90264U, // SSRAv16i8_shift |
| 17793 | 90272U, // SSRAv2i32_shift |
| 17794 | 90240U, // SSRAv2i64_shift |
| 17795 | 90280U, // SSRAv4i16_shift |
| 17796 | 90248U, // SSRAv4i32_shift |
| 17797 | 90256U, // SSRAv8i16_shift |
| 17798 | 90288U, // SSRAv8i8_shift |
| 17799 | 12089580U, // SST1B_D |
| 17800 | 809531588U, // SST1B_D_IMM |
| 17801 | 12351724U, // SST1B_D_SXTW |
| 17802 | 12613868U, // SST1B_D_UXTW |
| 17803 | 809531508U, // SST1B_S_IMM |
| 17804 | 12876012U, // SST1B_S_SXTW |
| 17805 | 13138156U, // SST1B_S_UXTW |
| 17806 | 12089580U, // SST1D |
| 17807 | 13400260U, // SST1D_IMM |
| 17808 | 13662444U, // SST1D_SCALED |
| 17809 | 12351724U, // SST1D_SXTW |
| 17810 | 13924588U, // SST1D_SXTW_SCALED |
| 17811 | 12613868U, // SST1D_UXTW |
| 17812 | 14186732U, // SST1D_UXTW_SCALED |
| 17813 | 12089580U, // SST1H_D |
| 17814 | 819755204U, // SST1H_D_IMM |
| 17815 | 14711020U, // SST1H_D_SCALED |
| 17816 | 12351724U, // SST1H_D_SXTW |
| 17817 | 14973164U, // SST1H_D_SXTW_SCALED |
| 17818 | 12613868U, // SST1H_D_UXTW |
| 17819 | 15235308U, // SST1H_D_UXTW_SCALED |
| 17820 | 819755124U, // SST1H_S_IMM |
| 17821 | 12876012U, // SST1H_S_SXTW |
| 17822 | 15497452U, // SST1H_S_SXTW_SCALED |
| 17823 | 13138156U, // SST1H_S_UXTW |
| 17824 | 15759596U, // SST1H_S_UXTW_SCALED |
| 17825 | 809531588U, // SST1Q |
| 17826 | 12089580U, // SST1W_D |
| 17827 | 821328068U, // SST1W_D_IMM |
| 17828 | 16283884U, // SST1W_D_SCALED |
| 17829 | 12351724U, // SST1W_D_SXTW |
| 17830 | 16546028U, // SST1W_D_SXTW_SCALED |
| 17831 | 12613868U, // SST1W_D_UXTW |
| 17832 | 16808172U, // SST1W_D_UXTW_SCALED |
| 17833 | 821327988U, // SST1W_IMM |
| 17834 | 12876012U, // SST1W_SXTW |
| 17835 | 17070316U, // SST1W_SXTW_SCALED |
| 17836 | 13138156U, // SST1W_UXTW |
| 17837 | 17332460U, // SST1W_UXTW_SCALED |
| 17838 | 12384U, // SSUBLBT_ZZZ_D |
| 17839 | 184U, // SSUBLBT_ZZZ_H |
| 17840 | 22624U, // SSUBLBT_ZZZ_S |
| 17841 | 12384U, // SSUBLB_ZZZ_D |
| 17842 | 184U, // SSUBLB_ZZZ_H |
| 17843 | 22624U, // SSUBLB_ZZZ_S |
| 17844 | 12384U, // SSUBLTB_ZZZ_D |
| 17845 | 184U, // SSUBLTB_ZZZ_H |
| 17846 | 22624U, // SSUBLTB_ZZZ_S |
| 17847 | 12384U, // SSUBLT_ZZZ_D |
| 17848 | 184U, // SSUBLT_ZZZ_H |
| 17849 | 22624U, // SSUBLT_ZZZ_S |
| 17850 | 1861784U, // SSUBLv16i8_v8i16 |
| 17851 | 2123936U, // SSUBLv2i32_v2i64 |
| 17852 | 2386088U, // SSUBLv4i16_v4i32 |
| 17853 | 813192U, // SSUBLv4i32_v2i64 |
| 17854 | 1075344U, // SSUBLv8i16_v4i32 |
| 17855 | 2648240U, // SSUBLv8i8_v8i16 |
| 17856 | 12384U, // SSUBWB_ZZZ_D |
| 17857 | 184U, // SSUBWB_ZZZ_H |
| 17858 | 22624U, // SSUBWB_ZZZ_S |
| 17859 | 12384U, // SSUBWT_ZZZ_D |
| 17860 | 184U, // SSUBWT_ZZZ_H |
| 17861 | 22624U, // SSUBWT_ZZZ_S |
| 17862 | 1861776U, // SSUBWv16i8_v8i16 |
| 17863 | 2123904U, // SSUBWv2i32_v2i64 |
| 17864 | 2386056U, // SSUBWv4i16_v4i32 |
| 17865 | 813184U, // SSUBWv4i32_v2i64 |
| 17866 | 1075336U, // SSUBWv8i16_v4i32 |
| 17867 | 2648208U, // SSUBWv8i8_v8i16 |
| 17868 | 17594604U, // ST1B |
| 17869 | 17594604U, // ST1B_2Z |
| 17870 | 853309676U, // ST1B_2Z_IMM |
| 17871 | 1443117331U, // ST1B_2Z_STRIDED |
| 17872 | 1476671763U, // ST1B_2Z_STRIDED_IMM |
| 17873 | 17594604U, // ST1B_4Z |
| 17874 | 854882540U, // ST1B_4Z_IMM |
| 17875 | 17594604U, // ST1B_4Z_STRIDED |
| 17876 | 854882540U, // ST1B_4Z_STRIDED_IMM |
| 17877 | 17594604U, // ST1B_D |
| 17878 | 843086060U, // ST1B_D_IMM |
| 17879 | 17594604U, // ST1B_H |
| 17880 | 843086060U, // ST1B_H_IMM |
| 17881 | 843086060U, // ST1B_IMM |
| 17882 | 17594604U, // ST1B_S |
| 17883 | 843086060U, // ST1B_S_IMM |
| 17884 | 17856748U, // ST1D |
| 17885 | 17856748U, // ST1D_2Z |
| 17886 | 853309676U, // ST1D_2Z_IMM |
| 17887 | 17856748U, // ST1D_2Z_STRIDED |
| 17888 | 853309676U, // ST1D_2Z_STRIDED_IMM |
| 17889 | 17856748U, // ST1D_4Z |
| 17890 | 854882540U, // ST1D_4Z_IMM |
| 17891 | 17856748U, // ST1D_4Z_STRIDED |
| 17892 | 854882540U, // ST1D_4Z_STRIDED_IMM |
| 17893 | 843086060U, // ST1D_IMM |
| 17894 | 17856748U, // ST1D_Q |
| 17895 | 843086060U, // ST1D_Q_IMM |
| 17896 | 0U, // ST1Fourv16b |
| 17897 | 0U, // ST1Fourv16b_POST |
| 17898 | 0U, // ST1Fourv1d |
| 17899 | 0U, // ST1Fourv1d_POST |
| 17900 | 0U, // ST1Fourv2d |
| 17901 | 0U, // ST1Fourv2d_POST |
| 17902 | 0U, // ST1Fourv2s |
| 17903 | 0U, // ST1Fourv2s_POST |
| 17904 | 0U, // ST1Fourv4h |
| 17905 | 0U, // ST1Fourv4h_POST |
| 17906 | 0U, // ST1Fourv4s |
| 17907 | 0U, // ST1Fourv4s_POST |
| 17908 | 0U, // ST1Fourv8b |
| 17909 | 0U, // ST1Fourv8b_POST |
| 17910 | 0U, // ST1Fourv8h |
| 17911 | 0U, // ST1Fourv8h_POST |
| 17912 | 18118892U, // ST1H |
| 17913 | 18118892U, // ST1H_2Z |
| 17914 | 853309676U, // ST1H_2Z_IMM |
| 17915 | 1510226195U, // ST1H_2Z_STRIDED |
| 17916 | 1476671763U, // ST1H_2Z_STRIDED_IMM |
| 17917 | 18118892U, // ST1H_4Z |
| 17918 | 854882540U, // ST1H_4Z_IMM |
| 17919 | 18118892U, // ST1H_4Z_STRIDED |
| 17920 | 854882540U, // ST1H_4Z_STRIDED_IMM |
| 17921 | 18118892U, // ST1H_D |
| 17922 | 843086060U, // ST1H_D_IMM |
| 17923 | 843086060U, // ST1H_IMM |
| 17924 | 18118892U, // ST1H_S |
| 17925 | 843086060U, // ST1H_S_IMM |
| 17926 | 0U, // ST1Onev16b |
| 17927 | 0U, // ST1Onev16b_POST |
| 17928 | 0U, // ST1Onev1d |
| 17929 | 0U, // ST1Onev1d_POST |
| 17930 | 0U, // ST1Onev2d |
| 17931 | 0U, // ST1Onev2d_POST |
| 17932 | 0U, // ST1Onev2s |
| 17933 | 0U, // ST1Onev2s_POST |
| 17934 | 0U, // ST1Onev4h |
| 17935 | 0U, // ST1Onev4h_POST |
| 17936 | 0U, // ST1Onev4s |
| 17937 | 0U, // ST1Onev4s_POST |
| 17938 | 0U, // ST1Onev8b |
| 17939 | 0U, // ST1Onev8b_POST |
| 17940 | 0U, // ST1Onev8h |
| 17941 | 0U, // ST1Onev8h_POST |
| 17942 | 0U, // ST1Threev16b |
| 17943 | 0U, // ST1Threev16b_POST |
| 17944 | 0U, // ST1Threev1d |
| 17945 | 0U, // ST1Threev1d_POST |
| 17946 | 0U, // ST1Threev2d |
| 17947 | 0U, // ST1Threev2d_POST |
| 17948 | 0U, // ST1Threev2s |
| 17949 | 0U, // ST1Threev2s_POST |
| 17950 | 0U, // ST1Threev4h |
| 17951 | 0U, // ST1Threev4h_POST |
| 17952 | 0U, // ST1Threev4s |
| 17953 | 0U, // ST1Threev4s_POST |
| 17954 | 0U, // ST1Threev8b |
| 17955 | 0U, // ST1Threev8b_POST |
| 17956 | 0U, // ST1Threev8h |
| 17957 | 0U, // ST1Threev8h_POST |
| 17958 | 0U, // ST1Twov16b |
| 17959 | 0U, // ST1Twov16b_POST |
| 17960 | 0U, // ST1Twov1d |
| 17961 | 0U, // ST1Twov1d_POST |
| 17962 | 0U, // ST1Twov2d |
| 17963 | 0U, // ST1Twov2d_POST |
| 17964 | 0U, // ST1Twov2s |
| 17965 | 0U, // ST1Twov2s_POST |
| 17966 | 0U, // ST1Twov4h |
| 17967 | 0U, // ST1Twov4h_POST |
| 17968 | 0U, // ST1Twov4s |
| 17969 | 0U, // ST1Twov4s_POST |
| 17970 | 0U, // ST1Twov8b |
| 17971 | 0U, // ST1Twov8b_POST |
| 17972 | 0U, // ST1Twov8h |
| 17973 | 0U, // ST1Twov8h_POST |
| 17974 | 18643180U, // ST1W |
| 17975 | 18643180U, // ST1W_2Z |
| 17976 | 853309676U, // ST1W_2Z_IMM |
| 17977 | 18643180U, // ST1W_2Z_STRIDED |
| 17978 | 853309676U, // ST1W_2Z_STRIDED_IMM |
| 17979 | 18643180U, // ST1W_4Z |
| 17980 | 854882540U, // ST1W_4Z_IMM |
| 17981 | 18643180U, // ST1W_4Z_STRIDED |
| 17982 | 854882540U, // ST1W_4Z_STRIDED_IMM |
| 17983 | 18643180U, // ST1W_D |
| 17984 | 843086060U, // ST1W_D_IMM |
| 17985 | 843086060U, // ST1W_IMM |
| 17986 | 18643180U, // ST1W_Q |
| 17987 | 843086060U, // ST1W_Q_IMM |
| 17988 | 19331696U, // ST1_MXIPXX_H_B |
| 17989 | 19593840U, // ST1_MXIPXX_H_D |
| 17990 | 19855984U, // ST1_MXIPXX_H_H |
| 17991 | 20118128U, // ST1_MXIPXX_H_Q |
| 17992 | 20380272U, // ST1_MXIPXX_H_S |
| 17993 | 19331696U, // ST1_MXIPXX_V_B |
| 17994 | 19593840U, // ST1_MXIPXX_V_D |
| 17995 | 19855984U, // ST1_MXIPXX_V_H |
| 17996 | 20118128U, // ST1_MXIPXX_V_Q |
| 17997 | 20380272U, // ST1_MXIPXX_V_S |
| 17998 | 0U, // ST1i16 |
| 17999 | 5U, // ST1i16_POST |
| 18000 | 0U, // ST1i32 |
| 18001 | 5U, // ST1i32_POST |
| 18002 | 0U, // ST1i64 |
| 18003 | 5U, // ST1i64_POST |
| 18004 | 0U, // ST1i8 |
| 18005 | 5U, // ST1i8_POST |
| 18006 | 17594604U, // ST2B |
| 18007 | 853309676U, // ST2B_IMM |
| 18008 | 17856748U, // ST2D |
| 18009 | 853309676U, // ST2D_IMM |
| 18010 | 150153U, // ST2GPostIndex |
| 18011 | 22169697U, // ST2GPreIndex |
| 18012 | 6832224U, // ST2Gi |
| 18013 | 18118892U, // ST2H |
| 18014 | 853309676U, // ST2H_IMM |
| 18015 | 20478188U, // ST2Q |
| 18016 | 853309676U, // ST2Q_IMM |
| 18017 | 0U, // ST2Twov16b |
| 18018 | 0U, // ST2Twov16b_POST |
| 18019 | 0U, // ST2Twov2d |
| 18020 | 0U, // ST2Twov2d_POST |
| 18021 | 0U, // ST2Twov2s |
| 18022 | 0U, // ST2Twov2s_POST |
| 18023 | 0U, // ST2Twov4h |
| 18024 | 0U, // ST2Twov4h_POST |
| 18025 | 0U, // ST2Twov4s |
| 18026 | 0U, // ST2Twov4s_POST |
| 18027 | 0U, // ST2Twov8b |
| 18028 | 0U, // ST2Twov8b_POST |
| 18029 | 0U, // ST2Twov8h |
| 18030 | 0U, // ST2Twov8h_POST |
| 18031 | 18643180U, // ST2W |
| 18032 | 853309676U, // ST2W_IMM |
| 18033 | 0U, // ST2i16 |
| 18034 | 5U, // ST2i16_POST |
| 18035 | 0U, // ST2i32 |
| 18036 | 5U, // ST2i32_POST |
| 18037 | 0U, // ST2i64 |
| 18038 | 5U, // ST2i64_POST |
| 18039 | 0U, // ST2i8 |
| 18040 | 5U, // ST2i8_POST |
| 18041 | 17594604U, // ST3B |
| 18042 | 20740332U, // ST3B_IMM |
| 18043 | 17856748U, // ST3D |
| 18044 | 20740332U, // ST3D_IMM |
| 18045 | 18118892U, // ST3H |
| 18046 | 20740332U, // ST3H_IMM |
| 18047 | 20478188U, // ST3Q |
| 18048 | 20740332U, // ST3Q_IMM |
| 18049 | 0U, // ST3Threev16b |
| 18050 | 0U, // ST3Threev16b_POST |
| 18051 | 0U, // ST3Threev2d |
| 18052 | 0U, // ST3Threev2d_POST |
| 18053 | 0U, // ST3Threev2s |
| 18054 | 0U, // ST3Threev2s_POST |
| 18055 | 0U, // ST3Threev4h |
| 18056 | 0U, // ST3Threev4h_POST |
| 18057 | 0U, // ST3Threev4s |
| 18058 | 0U, // ST3Threev4s_POST |
| 18059 | 0U, // ST3Threev8b |
| 18060 | 0U, // ST3Threev8b_POST |
| 18061 | 0U, // ST3Threev8h |
| 18062 | 0U, // ST3Threev8h_POST |
| 18063 | 18643180U, // ST3W |
| 18064 | 20740332U, // ST3W_IMM |
| 18065 | 0U, // ST3i16 |
| 18066 | 5U, // ST3i16_POST |
| 18067 | 0U, // ST3i32 |
| 18068 | 5U, // ST3i32_POST |
| 18069 | 0U, // ST3i64 |
| 18070 | 5U, // ST3i64_POST |
| 18071 | 0U, // ST3i8 |
| 18072 | 5U, // ST3i8_POST |
| 18073 | 17594604U, // ST4B |
| 18074 | 854882540U, // ST4B_IMM |
| 18075 | 17856748U, // ST4D |
| 18076 | 854882540U, // ST4D_IMM |
| 18077 | 0U, // ST4Fourv16b |
| 18078 | 0U, // ST4Fourv16b_POST |
| 18079 | 0U, // ST4Fourv2d |
| 18080 | 0U, // ST4Fourv2d_POST |
| 18081 | 0U, // ST4Fourv2s |
| 18082 | 0U, // ST4Fourv2s_POST |
| 18083 | 0U, // ST4Fourv4h |
| 18084 | 0U, // ST4Fourv4h_POST |
| 18085 | 0U, // ST4Fourv4s |
| 18086 | 0U, // ST4Fourv4s_POST |
| 18087 | 0U, // ST4Fourv8b |
| 18088 | 0U, // ST4Fourv8b_POST |
| 18089 | 0U, // ST4Fourv8h |
| 18090 | 0U, // ST4Fourv8h_POST |
| 18091 | 18118892U, // ST4H |
| 18092 | 854882540U, // ST4H_IMM |
| 18093 | 20478188U, // ST4Q |
| 18094 | 854882540U, // ST4Q_IMM |
| 18095 | 18643180U, // ST4W |
| 18096 | 854882540U, // ST4W_IMM |
| 18097 | 0U, // ST4i16 |
| 18098 | 5U, // ST4i16_POST |
| 18099 | 0U, // ST4i32 |
| 18100 | 5U, // ST4i32_POST |
| 18101 | 0U, // ST4i64 |
| 18102 | 5U, // ST4i64_POST |
| 18103 | 0U, // ST4i8 |
| 18104 | 5U, // ST4i8_POST |
| 18105 | 0U, // ST64B |
| 18106 | 5U, // ST64BV |
| 18107 | 5U, // ST64BV0 |
| 18108 | 0U, // STBFADD |
| 18109 | 0U, // STBFADDL |
| 18110 | 0U, // STBFMAX |
| 18111 | 0U, // STBFMAXL |
| 18112 | 0U, // STBFMAXNM |
| 18113 | 0U, // STBFMAXNML |
| 18114 | 0U, // STBFMIN |
| 18115 | 0U, // STBFMINL |
| 18116 | 0U, // STBFMINNM |
| 18117 | 0U, // STBFMINNML |
| 18118 | 0U, // STCPH |
| 18119 | 0U, // STFADDD |
| 18120 | 0U, // STFADDH |
| 18121 | 0U, // STFADDLD |
| 18122 | 0U, // STFADDLH |
| 18123 | 0U, // STFADDLS |
| 18124 | 0U, // STFADDS |
| 18125 | 0U, // STFMAXD |
| 18126 | 0U, // STFMAXH |
| 18127 | 0U, // STFMAXLD |
| 18128 | 0U, // STFMAXLH |
| 18129 | 0U, // STFMAXLS |
| 18130 | 0U, // STFMAXNMD |
| 18131 | 0U, // STFMAXNMH |
| 18132 | 0U, // STFMAXNMLD |
| 18133 | 0U, // STFMAXNMLH |
| 18134 | 0U, // STFMAXNMLS |
| 18135 | 0U, // STFMAXNMS |
| 18136 | 0U, // STFMAXS |
| 18137 | 0U, // STFMIND |
| 18138 | 0U, // STFMINH |
| 18139 | 0U, // STFMINLD |
| 18140 | 0U, // STFMINLH |
| 18141 | 0U, // STFMINLS |
| 18142 | 0U, // STFMINNMD |
| 18143 | 0U, // STFMINNMH |
| 18144 | 0U, // STFMINNMLD |
| 18145 | 0U, // STFMINNMLH |
| 18146 | 0U, // STFMINNMLS |
| 18147 | 0U, // STFMINNMS |
| 18148 | 0U, // STFMINS |
| 18149 | 584U, // STGM |
| 18150 | 906246416U, // STGPi |
| 18151 | 150153U, // STGPostIndex |
| 18152 | 1028481297U, // STGPpost |
| 18153 | 1006985489U, // STGPpre |
| 18154 | 22169697U, // STGPreIndex |
| 18155 | 6832224U, // STGi |
| 18156 | 6830352U, // STILPW |
| 18157 | 23945489U, // STILPWpre |
| 18158 | 6830352U, // STILPX |
| 18159 | 24207633U, // STILPXpre |
| 18160 | 0U, // STL1 |
| 18161 | 584U, // STLLRB |
| 18162 | 584U, // STLLRH |
| 18163 | 584U, // STLLRW |
| 18164 | 584U, // STLLRX |
| 18165 | 20986128U, // STLPi |
| 18166 | 584U, // STLRB |
| 18167 | 584U, // STLRH |
| 18168 | 584U, // STLRW |
| 18169 | 1001U, // STLRWpre |
| 18170 | 584U, // STLRX |
| 18171 | 1009U, // STLRXpre |
| 18172 | 6830352U, // STLTXRW |
| 18173 | 6830352U, // STLTXRX |
| 18174 | 6830176U, // STLURBi |
| 18175 | 6830176U, // STLURHi |
| 18176 | 6830176U, // STLURWi |
| 18177 | 6830176U, // STLURXi |
| 18178 | 6830176U, // STLURbi |
| 18179 | 6830176U, // STLURdi |
| 18180 | 6830176U, // STLURhi |
| 18181 | 6830176U, // STLURqi |
| 18182 | 6830176U, // STLURsi |
| 18183 | 24393824U, // STLXPW |
| 18184 | 24393824U, // STLXPX |
| 18185 | 6830352U, // STLXRB |
| 18186 | 6830352U, // STLXRH |
| 18187 | 6830352U, // STLXRW |
| 18188 | 6830352U, // STLXRX |
| 18189 | 92259U, // STMOPA_M2ZZZI_BtoS |
| 18190 | 92257U, // STMOPA_M2ZZZI_HtoS |
| 18191 | 872691984U, // STNPDi |
| 18192 | 906246416U, // STNPQi |
| 18193 | 939800848U, // STNPSi |
| 18194 | 939800848U, // STNPWi |
| 18195 | 872691984U, // STNPXi |
| 18196 | 17594604U, // STNT1B_2Z |
| 18197 | 853309676U, // STNT1B_2Z_IMM |
| 18198 | 1443117331U, // STNT1B_2Z_STRIDED |
| 18199 | 1476671763U, // STNT1B_2Z_STRIDED_IMM |
| 18200 | 17594604U, // STNT1B_4Z |
| 18201 | 854882540U, // STNT1B_4Z_IMM |
| 18202 | 17594604U, // STNT1B_4Z_STRIDED |
| 18203 | 854882540U, // STNT1B_4Z_STRIDED_IMM |
| 18204 | 843086060U, // STNT1B_ZRI |
| 18205 | 17594604U, // STNT1B_ZRR |
| 18206 | 809531588U, // STNT1B_ZZR_D |
| 18207 | 809531508U, // STNT1B_ZZR_S |
| 18208 | 17856748U, // STNT1D_2Z |
| 18209 | 853309676U, // STNT1D_2Z_IMM |
| 18210 | 17856748U, // STNT1D_2Z_STRIDED |
| 18211 | 853309676U, // STNT1D_2Z_STRIDED_IMM |
| 18212 | 17856748U, // STNT1D_4Z |
| 18213 | 854882540U, // STNT1D_4Z_IMM |
| 18214 | 17856748U, // STNT1D_4Z_STRIDED |
| 18215 | 854882540U, // STNT1D_4Z_STRIDED_IMM |
| 18216 | 843086060U, // STNT1D_ZRI |
| 18217 | 17856748U, // STNT1D_ZRR |
| 18218 | 809531588U, // STNT1D_ZZR_D |
| 18219 | 18118892U, // STNT1H_2Z |
| 18220 | 853309676U, // STNT1H_2Z_IMM |
| 18221 | 1510226195U, // STNT1H_2Z_STRIDED |
| 18222 | 1476671763U, // STNT1H_2Z_STRIDED_IMM |
| 18223 | 18118892U, // STNT1H_4Z |
| 18224 | 854882540U, // STNT1H_4Z_IMM |
| 18225 | 18118892U, // STNT1H_4Z_STRIDED |
| 18226 | 854882540U, // STNT1H_4Z_STRIDED_IMM |
| 18227 | 843086060U, // STNT1H_ZRI |
| 18228 | 18118892U, // STNT1H_ZRR |
| 18229 | 809531588U, // STNT1H_ZZR_D |
| 18230 | 809531508U, // STNT1H_ZZR_S |
| 18231 | 18643180U, // STNT1W_2Z |
| 18232 | 853309676U, // STNT1W_2Z_IMM |
| 18233 | 18643180U, // STNT1W_2Z_STRIDED |
| 18234 | 853309676U, // STNT1W_2Z_STRIDED_IMM |
| 18235 | 18643180U, // STNT1W_4Z |
| 18236 | 854882540U, // STNT1W_4Z_IMM |
| 18237 | 18643180U, // STNT1W_4Z_STRIDED |
| 18238 | 854882540U, // STNT1W_4Z_STRIDED_IMM |
| 18239 | 843086060U, // STNT1W_ZRI |
| 18240 | 18643180U, // STNT1W_ZRR |
| 18241 | 809531588U, // STNT1W_ZZR_D |
| 18242 | 809531508U, // STNT1W_ZZR_S |
| 18243 | 872691984U, // STPDi |
| 18244 | 994926865U, // STPDpost |
| 18245 | 973431057U, // STPDpre |
| 18246 | 906246416U, // STPQi |
| 18247 | 1028481297U, // STPQpost |
| 18248 | 1006985489U, // STPQpre |
| 18249 | 939800848U, // STPSi |
| 18250 | 1062035729U, // STPSpost |
| 18251 | 1040539921U, // STPSpre |
| 18252 | 939800848U, // STPWi |
| 18253 | 1062035729U, // STPWpost |
| 18254 | 1040539921U, // STPWpre |
| 18255 | 872691984U, // STPXi |
| 18256 | 994926865U, // STPXpost |
| 18257 | 973431057U, // STPXpre |
| 18258 | 90761U, // STRBBpost |
| 18259 | 22110305U, // STRBBpre |
| 18260 | 1074018400U, // STRBBroW |
| 18261 | 1107572832U, // STRBBroX |
| 18262 | 155744U, // STRBBui |
| 18263 | 90761U, // STRBpost |
| 18264 | 22110305U, // STRBpre |
| 18265 | 1074018400U, // STRBroW |
| 18266 | 1107572832U, // STRBroX |
| 18267 | 155744U, // STRBui |
| 18268 | 90761U, // STRDpost |
| 18269 | 22110305U, // STRDpre |
| 18270 | 1141127264U, // STRDroW |
| 18271 | 1174681696U, // STRDroX |
| 18272 | 157792U, // STRDui |
| 18273 | 90761U, // STRHHpost |
| 18274 | 22110305U, // STRHHpre |
| 18275 | 1208236128U, // STRHHroW |
| 18276 | 1241790560U, // STRHHroX |
| 18277 | 159840U, // STRHHui |
| 18278 | 90761U, // STRHpost |
| 18279 | 22110305U, // STRHpre |
| 18280 | 1208236128U, // STRHroW |
| 18281 | 1241790560U, // STRHroX |
| 18282 | 159840U, // STRHui |
| 18283 | 90761U, // STRQpost |
| 18284 | 22110305U, // STRQpre |
| 18285 | 1275344992U, // STRQroW |
| 18286 | 1308899424U, // STRQroX |
| 18287 | 161888U, // STRQui |
| 18288 | 90761U, // STRSpost |
| 18289 | 22110305U, // STRSpre |
| 18290 | 1342453856U, // STRSroW |
| 18291 | 1376008288U, // STRSroX |
| 18292 | 163936U, // STRSui |
| 18293 | 90761U, // STRWpost |
| 18294 | 22110305U, // STRWpre |
| 18295 | 1342453856U, // STRWroW |
| 18296 | 1376008288U, // STRWroX |
| 18297 | 163936U, // STRWui |
| 18298 | 90761U, // STRXpost |
| 18299 | 22110305U, // STRXpre |
| 18300 | 1141127264U, // STRXroW |
| 18301 | 1174681696U, // STRXroX |
| 18302 | 157792U, // STRXui |
| 18303 | 22296672U, // STR_PXI |
| 18304 | 584U, // STR_TX |
| 18305 | 0U, // STR_ZA |
| 18306 | 22296672U, // STR_ZXI |
| 18307 | 0U, // STSHH |
| 18308 | 906246416U, // STTNPQi |
| 18309 | 872691984U, // STTNPXi |
| 18310 | 906246416U, // STTPQi |
| 18311 | 1028481297U, // STTPQpost |
| 18312 | 1006985489U, // STTPQpre |
| 18313 | 872691984U, // STTPi |
| 18314 | 994926865U, // STTPpost |
| 18315 | 973431057U, // STTPpre |
| 18316 | 6830176U, // STTRBi |
| 18317 | 6830176U, // STTRHi |
| 18318 | 6830176U, // STTRWi |
| 18319 | 6830176U, // STTRXi |
| 18320 | 6830352U, // STTXRWr |
| 18321 | 6830352U, // STTXRXr |
| 18322 | 6830176U, // STURBBi |
| 18323 | 6830176U, // STURBi |
| 18324 | 6830176U, // STURDi |
| 18325 | 6830176U, // STURHHi |
| 18326 | 6830176U, // STURHi |
| 18327 | 6830176U, // STURQi |
| 18328 | 6830176U, // STURSi |
| 18329 | 6830176U, // STURWi |
| 18330 | 6830176U, // STURXi |
| 18331 | 24393824U, // STXPW |
| 18332 | 24393824U, // STXPX |
| 18333 | 6830352U, // STXRB |
| 18334 | 6830352U, // STXRH |
| 18335 | 6830352U, // STXRW |
| 18336 | 6830352U, // STXRX |
| 18337 | 150153U, // STZ2GPostIndex |
| 18338 | 22169697U, // STZ2GPreIndex |
| 18339 | 6832224U, // STZ2Gi |
| 18340 | 584U, // STZGM |
| 18341 | 150153U, // STZGPostIndex |
| 18342 | 22169697U, // STZGPreIndex |
| 18343 | 6832224U, // STZGi |
| 18344 | 278624U, // SUBG |
| 18345 | 22624U, // SUBHNB_ZZZ_B |
| 18346 | 4208U, // SUBHNB_ZZZ_H |
| 18347 | 10336U, // SUBHNB_ZZZ_S |
| 18348 | 24672U, // SUBHNT_ZZZ_B |
| 18349 | 120U, // SUBHNT_ZZZ_H |
| 18350 | 2144U, // SUBHNT_ZZZ_S |
| 18351 | 551040U, // SUBHNv2i64_v2i32 |
| 18352 | 553088U, // SUBHNv2i64_v4i32 |
| 18353 | 813192U, // SUBHNv4i32_v4i16 |
| 18354 | 815240U, // SUBHNv4i32_v8i16 |
| 18355 | 1077392U, // SUBHNv8i16_v16i8 |
| 18356 | 1075344U, // SUBHNv8i16_v8i8 |
| 18357 | 14432U, // SUBP |
| 18358 | 14432U, // SUBPS |
| 18359 | 1325152U, // SUBPT_shift |
| 18360 | 33824776U, // SUBP_ZPmZZ_B |
| 18361 | 67381256U, // SUBP_ZPmZZ_D |
| 18362 | 102266912U, // SUBP_ZPmZZ_H |
| 18363 | 134492168U, // SUBP_ZPmZZ_S |
| 18364 | 39008U, // SUBR_ZI_B |
| 18365 | 41056U, // SUBR_ZI_D |
| 18366 | 216U, // SUBR_ZI_H |
| 18367 | 43104U, // SUBR_ZI_S |
| 18368 | 33824776U, // SUBR_ZPmZ_B |
| 18369 | 67381256U, // SUBR_ZPmZ_D |
| 18370 | 102266912U, // SUBR_ZPmZ_H |
| 18371 | 134492168U, // SUBR_ZPmZ_S |
| 18372 | 32864U, // SUBSWri |
| 18373 | 34912U, // SUBSWrs |
| 18374 | 36960U, // SUBSWrx |
| 18375 | 32864U, // SUBSXri |
| 18376 | 34912U, // SUBSXrs |
| 18377 | 36960U, // SUBSXrx |
| 18378 | 2898016U, // SUBSXrx64 |
| 18379 | 32864U, // SUBWri |
| 18380 | 34912U, // SUBWrs |
| 18381 | 36960U, // SUBWrx |
| 18382 | 32864U, // SUBXri |
| 18383 | 34912U, // SUBXrs |
| 18384 | 36960U, // SUBXrx |
| 18385 | 2898016U, // SUBXrx64 |
| 18386 | 3176648U, // SUB_VG2_M2Z2Z_D |
| 18387 | 3438800U, // SUB_VG2_M2Z2Z_S |
| 18388 | 104364232U, // SUB_VG2_M2ZZ_D |
| 18389 | 104626384U, // SUB_VG2_M2ZZ_S |
| 18390 | 4296U, // SUB_VG2_M2Z_D |
| 18391 | 4304U, // SUB_VG2_M2Z_S |
| 18392 | 3176649U, // SUB_VG4_M4Z4Z_D |
| 18393 | 3438801U, // SUB_VG4_M4Z4Z_S |
| 18394 | 104364233U, // SUB_VG4_M4ZZ_D |
| 18395 | 104626385U, // SUB_VG4_M4ZZ_S |
| 18396 | 4297U, // SUB_VG4_M4Z_D |
| 18397 | 4305U, // SUB_VG4_M4Z_S |
| 18398 | 39008U, // SUB_ZI_B |
| 18399 | 41056U, // SUB_ZI_D |
| 18400 | 216U, // SUB_ZI_H |
| 18401 | 43104U, // SUB_ZI_S |
| 18402 | 33824776U, // SUB_ZPmZ_B |
| 18403 | 67381256U, // SUB_ZPmZ_CPA |
| 18404 | 67381256U, // SUB_ZPmZ_D |
| 18405 | 102266912U, // SUB_ZPmZ_H |
| 18406 | 134492168U, // SUB_ZPmZ_S |
| 18407 | 8288U, // SUB_ZZZ_B |
| 18408 | 10336U, // SUB_ZZZ_CPA |
| 18409 | 10336U, // SUB_ZZZ_D |
| 18410 | 4128U, // SUB_ZZZ_H |
| 18411 | 12384U, // SUB_ZZZ_S |
| 18412 | 1861784U, // SUBv16i8 |
| 18413 | 14432U, // SUBv1i64 |
| 18414 | 2123936U, // SUBv2i32 |
| 18415 | 551040U, // SUBv2i64 |
| 18416 | 2386088U, // SUBv4i16 |
| 18417 | 813192U, // SUBv4i32 |
| 18418 | 1075344U, // SUBv8i16 |
| 18419 | 2648240U, // SUBv8i8 |
| 18420 | 10082840U, // SUDOT_VG2_M2ZZI_BToS |
| 18421 | 121368U, // SUDOT_VG2_M2ZZ_BToS |
| 18422 | 10082841U, // SUDOT_VG4_M4ZZI_BToS |
| 18423 | 121369U, // SUDOT_VG4_M4ZZ_BToS |
| 18424 | 86297U, // SUDOT_ZZZI |
| 18425 | 10252440U, // SUDOTlanev16i8 |
| 18426 | 10252464U, // SUDOTlanev8i8 |
| 18427 | 84521U, // SUMLALL_MZZI_BtoS |
| 18428 | 10082840U, // SUMLALL_VG2_M2ZZI_BtoS |
| 18429 | 121370U, // SUMLALL_VG2_M2ZZ_BtoS |
| 18430 | 10082841U, // SUMLALL_VG4_M4ZZI_BtoS |
| 18431 | 121370U, // SUMLALL_VG4_M4ZZ_BtoS |
| 18432 | 2U, // SUMOP4A_M2Z2Z_BToS |
| 18433 | 1U, // SUMOP4A_M2Z2Z_HtoD |
| 18434 | 3U, // SUMOP4A_M2ZZ_BToS |
| 18435 | 1U, // SUMOP4A_M2ZZ_HtoD |
| 18436 | 560U, // SUMOP4A_MZ2Z_BToS |
| 18437 | 264U, // SUMOP4A_MZ2Z_HtoD |
| 18438 | 4376U, // SUMOP4A_MZZ_BToS |
| 18439 | 4112U, // SUMOP4A_MZZ_HtoD |
| 18440 | 2U, // SUMOP4S_M2Z2Z_BToS |
| 18441 | 1U, // SUMOP4S_M2Z2Z_HtoD |
| 18442 | 3U, // SUMOP4S_M2ZZ_BToS |
| 18443 | 1U, // SUMOP4S_M2ZZ_HtoD |
| 18444 | 560U, // SUMOP4S_MZ2Z_BToS |
| 18445 | 264U, // SUMOP4S_MZ2Z_HtoD |
| 18446 | 4376U, // SUMOP4S_MZZ_BToS |
| 18447 | 4112U, // SUMOP4S_MZZ_HtoD |
| 18448 | 88168U, // SUMOPA_MPPZZ_D |
| 18449 | 127080U, // SUMOPA_MPPZZ_S |
| 18450 | 88168U, // SUMOPS_MPPZZ_D |
| 18451 | 127080U, // SUMOPS_MPPZZ_S |
| 18452 | 0U, // SUNPKHI_ZZ_D |
| 18453 | 1U, // SUNPKHI_ZZ_H |
| 18454 | 0U, // SUNPKHI_ZZ_S |
| 18455 | 0U, // SUNPKLO_ZZ_D |
| 18456 | 1U, // SUNPKLO_ZZ_H |
| 18457 | 0U, // SUNPKLO_ZZ_S |
| 18458 | 1U, // SUNPK_VG2_2ZZ_D |
| 18459 | 1U, // SUNPK_VG2_2ZZ_H |
| 18460 | 1U, // SUNPK_VG2_2ZZ_S |
| 18461 | 1U, // SUNPK_VG4_4Z2Z_D |
| 18462 | 1U, // SUNPK_VG4_4Z2Z_H |
| 18463 | 1U, // SUNPK_VG4_4Z2Z_S |
| 18464 | 33824776U, // SUQADD_ZPmZ_B |
| 18465 | 67381256U, // SUQADD_ZPmZ_D |
| 18466 | 102266912U, // SUQADD_ZPmZ_H |
| 18467 | 134492168U, // SUQADD_ZPmZ_S |
| 18468 | 40U, // SUQADDv16i8 |
| 18469 | 1U, // SUQADDv1i16 |
| 18470 | 1U, // SUQADDv1i32 |
| 18471 | 1U, // SUQADDv1i64 |
| 18472 | 1U, // SUQADDv1i8 |
| 18473 | 48U, // SUQADDv2i32 |
| 18474 | 56U, // SUQADDv2i64 |
| 18475 | 64U, // SUQADDv4i16 |
| 18476 | 72U, // SUQADDv4i32 |
| 18477 | 80U, // SUQADDv8i16 |
| 18478 | 88U, // SUQADDv8i8 |
| 18479 | 92259U, // SUTMOPA_M2ZZZI_BtoS |
| 18480 | 10082841U, // SUVDOT_VG4_M4ZZI_BToS |
| 18481 | 0U, // SVC |
| 18482 | 206862576U, // SVDOT_VG2_M2ZZI_HtoS |
| 18483 | 10082841U, // SVDOT_VG4_M4ZZI_BtoS |
| 18484 | 206862577U, // SVDOT_VG4_M4ZZI_HtoD |
| 18485 | 3U, // SWPAB |
| 18486 | 3U, // SWPAH |
| 18487 | 3U, // SWPALB |
| 18488 | 3U, // SWPALH |
| 18489 | 3U, // SWPALW |
| 18490 | 3U, // SWPALX |
| 18491 | 3U, // SWPAW |
| 18492 | 3U, // SWPAX |
| 18493 | 3U, // SWPB |
| 18494 | 3U, // SWPH |
| 18495 | 3U, // SWPLB |
| 18496 | 3U, // SWPLH |
| 18497 | 3U, // SWPLW |
| 18498 | 3U, // SWPLX |
| 18499 | 147731U, // SWPP |
| 18500 | 147731U, // SWPPA |
| 18501 | 147731U, // SWPPAL |
| 18502 | 147731U, // SWPPL |
| 18503 | 3U, // SWPTALW |
| 18504 | 3U, // SWPTALX |
| 18505 | 3U, // SWPTAW |
| 18506 | 3U, // SWPTAX |
| 18507 | 3U, // SWPTLW |
| 18508 | 3U, // SWPTLX |
| 18509 | 3U, // SWPTW |
| 18510 | 3U, // SWPTX |
| 18511 | 3U, // SWPW |
| 18512 | 3U, // SWPX |
| 18513 | 2056U, // SXTB_ZPmZ_D |
| 18514 | 4112U, // SXTB_ZPmZ_H |
| 18515 | 6152U, // SXTB_ZPmZ_S |
| 18516 | 10264U, // SXTB_ZPzZ_D |
| 18517 | 4128U, // SXTB_ZPzZ_H |
| 18518 | 12312U, // SXTB_ZPzZ_S |
| 18519 | 2056U, // SXTH_ZPmZ_D |
| 18520 | 6152U, // SXTH_ZPmZ_S |
| 18521 | 10264U, // SXTH_ZPzZ_D |
| 18522 | 12312U, // SXTH_ZPzZ_S |
| 18523 | 2056U, // SXTW_ZPmZ_D |
| 18524 | 10264U, // SXTW_ZPzZ_D |
| 18525 | 196704U, // SYSLxt |
| 18526 | 1021U, // SYSPxt |
| 18527 | 1029U, // SYSPxt_XZR |
| 18528 | 1037U, // SYSxt |
| 18529 | 186U, // TBLQ_ZZZ_B |
| 18530 | 10338U, // TBLQ_ZZZ_D |
| 18531 | 4128U, // TBLQ_ZZZ_H |
| 18532 | 12386U, // TBLQ_ZZZ_S |
| 18533 | 186U, // TBL_ZZZZ_B |
| 18534 | 10338U, // TBL_ZZZZ_D |
| 18535 | 4128U, // TBL_ZZZZ_H |
| 18536 | 12386U, // TBL_ZZZZ_S |
| 18537 | 186U, // TBL_ZZZ_B |
| 18538 | 10338U, // TBL_ZZZ_D |
| 18539 | 4128U, // TBL_ZZZ_H |
| 18540 | 12386U, // TBL_ZZZ_S |
| 18541 | 43U, // TBLv16i8Four |
| 18542 | 43U, // TBLv16i8One |
| 18543 | 43U, // TBLv16i8Three |
| 18544 | 43U, // TBLv16i8Two |
| 18545 | 91U, // TBLv8i8Four |
| 18546 | 91U, // TBLv8i8One |
| 18547 | 91U, // TBLv8i8Three |
| 18548 | 91U, // TBLv8i8Two |
| 18549 | 94304U, // TBNZW |
| 18550 | 94304U, // TBNZX |
| 18551 | 4377U, // TBXQ_ZZZ_B |
| 18552 | 2144U, // TBXQ_ZZZ_D |
| 18553 | 4112U, // TBXQ_ZZZ_H |
| 18554 | 6240U, // TBXQ_ZZZ_S |
| 18555 | 4377U, // TBX_ZZZ_B |
| 18556 | 2144U, // TBX_ZZZ_D |
| 18557 | 4112U, // TBX_ZZZ_H |
| 18558 | 6240U, // TBX_ZZZ_S |
| 18559 | 45U, // TBXv16i8Four |
| 18560 | 45U, // TBXv16i8One |
| 18561 | 45U, // TBXv16i8Three |
| 18562 | 45U, // TBXv16i8Two |
| 18563 | 93U, // TBXv8i8Four |
| 18564 | 93U, // TBXv8i8One |
| 18565 | 93U, // TBXv8i8Three |
| 18566 | 93U, // TBXv8i8Two |
| 18567 | 94304U, // TBZW |
| 18568 | 94304U, // TBZX |
| 18569 | 198756U, // TCHANGEBri |
| 18570 | 198752U, // TCHANGEBrr |
| 18571 | 198756U, // TCHANGEFri |
| 18572 | 198752U, // TCHANGEFrr |
| 18573 | 5U, // TENTER |
| 18574 | 0U, // TEXIT |
| 18575 | 0U, // TRCIT |
| 18576 | 8288U, // TRN1_PPP_B |
| 18577 | 10336U, // TRN1_PPP_D |
| 18578 | 4128U, // TRN1_PPP_H |
| 18579 | 12384U, // TRN1_PPP_S |
| 18580 | 8288U, // TRN1_ZZZ_B |
| 18581 | 10336U, // TRN1_ZZZ_D |
| 18582 | 4128U, // TRN1_ZZZ_H |
| 18583 | 4320U, // TRN1_ZZZ_Q |
| 18584 | 12384U, // TRN1_ZZZ_S |
| 18585 | 1861784U, // TRN1v16i8 |
| 18586 | 2123936U, // TRN1v2i32 |
| 18587 | 551040U, // TRN1v2i64 |
| 18588 | 2386088U, // TRN1v4i16 |
| 18589 | 813192U, // TRN1v4i32 |
| 18590 | 1075344U, // TRN1v8i16 |
| 18591 | 2648240U, // TRN1v8i8 |
| 18592 | 8288U, // TRN2_PPP_B |
| 18593 | 10336U, // TRN2_PPP_D |
| 18594 | 4128U, // TRN2_PPP_H |
| 18595 | 12384U, // TRN2_PPP_S |
| 18596 | 8288U, // TRN2_ZZZ_B |
| 18597 | 10336U, // TRN2_ZZZ_D |
| 18598 | 4128U, // TRN2_ZZZ_H |
| 18599 | 4320U, // TRN2_ZZZ_Q |
| 18600 | 12384U, // TRN2_ZZZ_S |
| 18601 | 1861784U, // TRN2v16i8 |
| 18602 | 2123936U, // TRN2v2i32 |
| 18603 | 551040U, // TRN2v2i64 |
| 18604 | 2386088U, // TRN2v4i16 |
| 18605 | 813192U, // TRN2v4i32 |
| 18606 | 1075344U, // TRN2v8i16 |
| 18607 | 2648240U, // TRN2v8i8 |
| 18608 | 0U, // TSB |
| 18609 | 6240U, // UABALB_ZZZ_D |
| 18610 | 4376U, // UABALB_ZZZ_H |
| 18611 | 24672U, // UABALB_ZZZ_S |
| 18612 | 6240U, // UABALT_ZZZ_D |
| 18613 | 4376U, // UABALT_ZZZ_H |
| 18614 | 24672U, // UABALT_ZZZ_S |
| 18615 | 4376U, // UABAL_ZZZ_BtoH |
| 18616 | 24672U, // UABAL_ZZZ_HtoS |
| 18617 | 6240U, // UABAL_ZZZ_StoD |
| 18618 | 1863832U, // UABALv16i8_v8i16 |
| 18619 | 2125984U, // UABALv2i32_v2i64 |
| 18620 | 2388136U, // UABALv4i16_v4i32 |
| 18621 | 815240U, // UABALv4i32_v2i64 |
| 18622 | 1077392U, // UABALv8i16_v4i32 |
| 18623 | 2650288U, // UABALv8i8_v8i16 |
| 18624 | 4377U, // UABA_ZZZ_B |
| 18625 | 2144U, // UABA_ZZZ_D |
| 18626 | 4112U, // UABA_ZZZ_H |
| 18627 | 6240U, // UABA_ZZZ_S |
| 18628 | 1863832U, // UABAv16i8 |
| 18629 | 2125984U, // UABAv2i32 |
| 18630 | 2388136U, // UABAv4i16 |
| 18631 | 815240U, // UABAv4i32 |
| 18632 | 1077392U, // UABAv8i16 |
| 18633 | 2650288U, // UABAv8i8 |
| 18634 | 12384U, // UABDLB_ZZZ_D |
| 18635 | 184U, // UABDLB_ZZZ_H |
| 18636 | 22624U, // UABDLB_ZZZ_S |
| 18637 | 12384U, // UABDLT_ZZZ_D |
| 18638 | 184U, // UABDLT_ZZZ_H |
| 18639 | 22624U, // UABDLT_ZZZ_S |
| 18640 | 1861784U, // UABDLv16i8_v8i16 |
| 18641 | 2123936U, // UABDLv2i32_v2i64 |
| 18642 | 2386088U, // UABDLv4i16_v4i32 |
| 18643 | 813192U, // UABDLv4i32_v2i64 |
| 18644 | 1075344U, // UABDLv8i16_v4i32 |
| 18645 | 2648240U, // UABDLv8i8_v8i16 |
| 18646 | 33824776U, // UABD_ZPmZ_B |
| 18647 | 67381256U, // UABD_ZPmZ_D |
| 18648 | 102266912U, // UABD_ZPmZ_H |
| 18649 | 134492168U, // UABD_ZPmZ_S |
| 18650 | 1861784U, // UABDv16i8 |
| 18651 | 2123936U, // UABDv2i32 |
| 18652 | 2386088U, // UABDv4i16 |
| 18653 | 813192U, // UABDv4i32 |
| 18654 | 1075344U, // UABDv8i16 |
| 18655 | 2648240U, // UABDv8i8 |
| 18656 | 6152U, // UADALP_ZPmZ_D |
| 18657 | 4376U, // UADALP_ZPmZ_H |
| 18658 | 24584U, // UADALP_ZPmZ_S |
| 18659 | 40U, // UADALPv16i8_v8i16 |
| 18660 | 48U, // UADALPv2i32_v1i64 |
| 18661 | 64U, // UADALPv4i16_v2i32 |
| 18662 | 72U, // UADALPv4i32_v2i64 |
| 18663 | 80U, // UADALPv8i16_v4i32 |
| 18664 | 88U, // UADALPv8i8_v4i16 |
| 18665 | 12384U, // UADDLB_ZZZ_D |
| 18666 | 184U, // UADDLB_ZZZ_H |
| 18667 | 22624U, // UADDLB_ZZZ_S |
| 18668 | 40U, // UADDLPv16i8_v8i16 |
| 18669 | 48U, // UADDLPv2i32_v1i64 |
| 18670 | 64U, // UADDLPv4i16_v2i32 |
| 18671 | 72U, // UADDLPv4i32_v2i64 |
| 18672 | 80U, // UADDLPv8i16_v4i32 |
| 18673 | 88U, // UADDLPv8i8_v4i16 |
| 18674 | 12384U, // UADDLT_ZZZ_D |
| 18675 | 184U, // UADDLT_ZZZ_H |
| 18676 | 22624U, // UADDLT_ZZZ_S |
| 18677 | 40U, // UADDLVv16i8v |
| 18678 | 64U, // UADDLVv4i16v |
| 18679 | 72U, // UADDLVv4i32v |
| 18680 | 80U, // UADDLVv8i16v |
| 18681 | 88U, // UADDLVv8i8v |
| 18682 | 1861784U, // UADDLv16i8_v8i16 |
| 18683 | 2123936U, // UADDLv2i32_v2i64 |
| 18684 | 2386088U, // UADDLv4i16_v4i32 |
| 18685 | 813192U, // UADDLv4i32_v2i64 |
| 18686 | 1075344U, // UADDLv8i16_v4i32 |
| 18687 | 2648240U, // UADDLv8i8_v8i16 |
| 18688 | 1U, // UADDV_VPZ_B |
| 18689 | 1U, // UADDV_VPZ_D |
| 18690 | 1U, // UADDV_VPZ_H |
| 18691 | 1U, // UADDV_VPZ_S |
| 18692 | 12384U, // UADDWB_ZZZ_D |
| 18693 | 184U, // UADDWB_ZZZ_H |
| 18694 | 22624U, // UADDWB_ZZZ_S |
| 18695 | 12384U, // UADDWT_ZZZ_D |
| 18696 | 184U, // UADDWT_ZZZ_H |
| 18697 | 22624U, // UADDWT_ZZZ_S |
| 18698 | 1861776U, // UADDWv16i8_v8i16 |
| 18699 | 2123904U, // UADDWv2i32_v2i64 |
| 18700 | 2386056U, // UADDWv4i16_v4i32 |
| 18701 | 813184U, // UADDWv4i32_v2i64 |
| 18702 | 1075336U, // UADDWv8i16_v4i32 |
| 18703 | 2648208U, // UADDWv8i8_v8i16 |
| 18704 | 276576U, // UBFMWri |
| 18705 | 276576U, // UBFMXri |
| 18706 | 4376U, // UCLAMP_VG2_2Z2Z_B |
| 18707 | 472U, // UCLAMP_VG2_2Z2Z_D |
| 18708 | 4112U, // UCLAMP_VG2_2Z2Z_H |
| 18709 | 120U, // UCLAMP_VG2_2Z2Z_S |
| 18710 | 4376U, // UCLAMP_VG4_4Z4Z_B |
| 18711 | 472U, // UCLAMP_VG4_4Z4Z_D |
| 18712 | 4112U, // UCLAMP_VG4_4Z4Z_H |
| 18713 | 120U, // UCLAMP_VG4_4Z4Z_S |
| 18714 | 4377U, // UCLAMP_ZZZ_B |
| 18715 | 2144U, // UCLAMP_ZZZ_D |
| 18716 | 4112U, // UCLAMP_ZZZ_H |
| 18717 | 6240U, // UCLAMP_ZZZ_S |
| 18718 | 0U, // UCVTFDSr |
| 18719 | 0U, // UCVTFHDr |
| 18720 | 0U, // UCVTFHSr |
| 18721 | 1U, // UCVTFLT_ZZ_BtoH |
| 18722 | 0U, // UCVTFLT_ZZ_HtoS |
| 18723 | 0U, // UCVTFLT_ZZ_StoD |
| 18724 | 0U, // UCVTFSDr |
| 18725 | 14432U, // UCVTFSWDri |
| 18726 | 14432U, // UCVTFSWHri |
| 18727 | 14432U, // UCVTFSWSri |
| 18728 | 14432U, // UCVTFSXDri |
| 18729 | 14432U, // UCVTFSXHri |
| 18730 | 14432U, // UCVTFSXSri |
| 18731 | 0U, // UCVTFUWDri |
| 18732 | 0U, // UCVTFUWHri |
| 18733 | 0U, // UCVTFUWSri |
| 18734 | 0U, // UCVTFUXDri |
| 18735 | 0U, // UCVTFUXHri |
| 18736 | 0U, // UCVTFUXSri |
| 18737 | 1U, // UCVTF_2Z2Z_StoS |
| 18738 | 1U, // UCVTF_4Z4Z_StoS |
| 18739 | 2056U, // UCVTF_ZPmZ_DtoD |
| 18740 | 472U, // UCVTF_ZPmZ_DtoH |
| 18741 | 2056U, // UCVTF_ZPmZ_DtoS |
| 18742 | 4112U, // UCVTF_ZPmZ_HtoH |
| 18743 | 6152U, // UCVTF_ZPmZ_StoD |
| 18744 | 120U, // UCVTF_ZPmZ_StoH |
| 18745 | 6152U, // UCVTF_ZPmZ_StoS |
| 18746 | 10264U, // UCVTF_ZPzZ_DtoD |
| 18747 | 4288U, // UCVTF_ZPzZ_DtoH |
| 18748 | 10264U, // UCVTF_ZPzZ_DtoS |
| 18749 | 4128U, // UCVTF_ZPzZ_HtoH |
| 18750 | 12312U, // UCVTF_ZPzZ_StoD |
| 18751 | 4208U, // UCVTF_ZPzZ_StoH |
| 18752 | 12312U, // UCVTF_ZPzZ_StoS |
| 18753 | 1U, // UCVTF_ZZ_BtoH |
| 18754 | 0U, // UCVTF_ZZ_HtoS |
| 18755 | 0U, // UCVTF_ZZ_StoD |
| 18756 | 14432U, // UCVTFd |
| 18757 | 14432U, // UCVTFh |
| 18758 | 14432U, // UCVTFs |
| 18759 | 0U, // UCVTFv1i16 |
| 18760 | 0U, // UCVTFv1i32 |
| 18761 | 0U, // UCVTFv1i64 |
| 18762 | 48U, // UCVTFv2f32 |
| 18763 | 56U, // UCVTFv2f64 |
| 18764 | 14496U, // UCVTFv2i32_shift |
| 18765 | 14464U, // UCVTFv2i64_shift |
| 18766 | 64U, // UCVTFv4f16 |
| 18767 | 72U, // UCVTFv4f32 |
| 18768 | 14504U, // UCVTFv4i16_shift |
| 18769 | 14472U, // UCVTFv4i32_shift |
| 18770 | 80U, // UCVTFv8f16 |
| 18771 | 14480U, // UCVTFv8i16_shift |
| 18772 | 0U, // UDF |
| 18773 | 67381256U, // UDIVR_ZPmZ_D |
| 18774 | 134492168U, // UDIVR_ZPmZ_S |
| 18775 | 14432U, // UDIVWr |
| 18776 | 14432U, // UDIVXr |
| 18777 | 67381256U, // UDIV_ZPmZ_D |
| 18778 | 134492168U, // UDIV_ZPmZ_S |
| 18779 | 119320U, // UDOT_VG2_M2Z2Z_BtoS |
| 18780 | 5273840U, // UDOT_VG2_M2Z2Z_HtoD |
| 18781 | 5273840U, // UDOT_VG2_M2Z2Z_HtoS |
| 18782 | 10082840U, // UDOT_VG2_M2ZZI_BToS |
| 18783 | 206862576U, // UDOT_VG2_M2ZZI_HToS |
| 18784 | 206862576U, // UDOT_VG2_M2ZZI_HtoD |
| 18785 | 121368U, // UDOT_VG2_M2ZZ_BtoS |
| 18786 | 106199280U, // UDOT_VG2_M2ZZ_HtoD |
| 18787 | 106199280U, // UDOT_VG2_M2ZZ_HtoS |
| 18788 | 119321U, // UDOT_VG4_M4Z4Z_BtoS |
| 18789 | 5273841U, // UDOT_VG4_M4Z4Z_HtoD |
| 18790 | 5273841U, // UDOT_VG4_M4Z4Z_HtoS |
| 18791 | 10082841U, // UDOT_VG4_M4ZZI_BtoS |
| 18792 | 206862577U, // UDOT_VG4_M4ZZI_HToS |
| 18793 | 206862577U, // UDOT_VG4_M4ZZI_HtoD |
| 18794 | 121369U, // UDOT_VG4_M4ZZ_BtoS |
| 18795 | 106199281U, // UDOT_VG4_M4ZZ_HtoD |
| 18796 | 106199281U, // UDOT_VG4_M4ZZ_HtoS |
| 18797 | 86296U, // UDOT_ZZZI_BtoH |
| 18798 | 86297U, // UDOT_ZZZI_BtoS |
| 18799 | 106455136U, // UDOT_ZZZI_HtoD |
| 18800 | 106455136U, // UDOT_ZZZI_HtoS |
| 18801 | 4376U, // UDOT_ZZZ_BtoH |
| 18802 | 4377U, // UDOT_ZZZ_BtoS |
| 18803 | 24672U, // UDOT_ZZZ_HtoD |
| 18804 | 24672U, // UDOT_ZZZ_HtoS |
| 18805 | 10252440U, // UDOTlanev16i8 |
| 18806 | 10252464U, // UDOTlanev8i8 |
| 18807 | 1863832U, // UDOTv16i8 |
| 18808 | 2650288U, // UDOTv8i8 |
| 18809 | 33824776U, // UHADD_ZPmZ_B |
| 18810 | 67381256U, // UHADD_ZPmZ_D |
| 18811 | 102266912U, // UHADD_ZPmZ_H |
| 18812 | 134492168U, // UHADD_ZPmZ_S |
| 18813 | 1861784U, // UHADDv16i8 |
| 18814 | 2123936U, // UHADDv2i32 |
| 18815 | 2386088U, // UHADDv4i16 |
| 18816 | 813192U, // UHADDv4i32 |
| 18817 | 1075344U, // UHADDv8i16 |
| 18818 | 2648240U, // UHADDv8i8 |
| 18819 | 33824776U, // UHSUBR_ZPmZ_B |
| 18820 | 67381256U, // UHSUBR_ZPmZ_D |
| 18821 | 102266912U, // UHSUBR_ZPmZ_H |
| 18822 | 134492168U, // UHSUBR_ZPmZ_S |
| 18823 | 33824776U, // UHSUB_ZPmZ_B |
| 18824 | 67381256U, // UHSUB_ZPmZ_D |
| 18825 | 102266912U, // UHSUB_ZPmZ_H |
| 18826 | 134492168U, // UHSUB_ZPmZ_S |
| 18827 | 1861784U, // UHSUBv16i8 |
| 18828 | 2123936U, // UHSUBv2i32 |
| 18829 | 2386088U, // UHSUBv4i16 |
| 18830 | 813192U, // UHSUBv4i32 |
| 18831 | 1075344U, // UHSUBv8i16 |
| 18832 | 2648240U, // UHSUBv8i8 |
| 18833 | 276576U, // UMADDLrrr |
| 18834 | 33824776U, // UMAXP_ZPmZ_B |
| 18835 | 67381256U, // UMAXP_ZPmZ_D |
| 18836 | 102266912U, // UMAXP_ZPmZ_H |
| 18837 | 134492168U, // UMAXP_ZPmZ_S |
| 18838 | 1861784U, // UMAXPv16i8 |
| 18839 | 2123936U, // UMAXPv2i32 |
| 18840 | 2386088U, // UMAXPv4i16 |
| 18841 | 813192U, // UMAXPv4i32 |
| 18842 | 1075344U, // UMAXPv8i16 |
| 18843 | 2648240U, // UMAXPv8i8 |
| 18844 | 8288U, // UMAXQV_VPZ_B |
| 18845 | 10336U, // UMAXQV_VPZ_D |
| 18846 | 22624U, // UMAXQV_VPZ_H |
| 18847 | 12384U, // UMAXQV_VPZ_S |
| 18848 | 0U, // UMAXV_VPZ_B |
| 18849 | 1U, // UMAXV_VPZ_D |
| 18850 | 1U, // UMAXV_VPZ_H |
| 18851 | 1U, // UMAXV_VPZ_S |
| 18852 | 40U, // UMAXVv16i8v |
| 18853 | 64U, // UMAXVv4i16v |
| 18854 | 72U, // UMAXVv4i32v |
| 18855 | 80U, // UMAXVv8i16v |
| 18856 | 88U, // UMAXVv8i8v |
| 18857 | 14432U, // UMAXWri |
| 18858 | 14432U, // UMAXWrr |
| 18859 | 14432U, // UMAXXri |
| 18860 | 14432U, // UMAXXrr |
| 18861 | 5040U, // UMAX_VG2_2Z2Z_B |
| 18862 | 4552U, // UMAX_VG2_2Z2Z_D |
| 18863 | 4344U, // UMAX_VG2_2Z2Z_H |
| 18864 | 4560U, // UMAX_VG2_2Z2Z_S |
| 18865 | 184U, // UMAX_VG2_2ZZ_B |
| 18866 | 4288U, // UMAX_VG2_2ZZ_D |
| 18867 | 4128U, // UMAX_VG2_2ZZ_H |
| 18868 | 4208U, // UMAX_VG2_2ZZ_S |
| 18869 | 5040U, // UMAX_VG4_4Z4Z_B |
| 18870 | 4552U, // UMAX_VG4_4Z4Z_D |
| 18871 | 4344U, // UMAX_VG4_4Z4Z_H |
| 18872 | 4560U, // UMAX_VG4_4Z4Z_S |
| 18873 | 184U, // UMAX_VG4_4ZZ_B |
| 18874 | 4288U, // UMAX_VG4_4ZZ_D |
| 18875 | 4128U, // UMAX_VG4_4ZZ_H |
| 18876 | 4208U, // UMAX_VG4_4ZZ_S |
| 18877 | 200800U, // UMAX_ZI_B |
| 18878 | 200800U, // UMAX_ZI_D |
| 18879 | 440U, // UMAX_ZI_H |
| 18880 | 200800U, // UMAX_ZI_S |
| 18881 | 33824776U, // UMAX_ZPmZ_B |
| 18882 | 67381256U, // UMAX_ZPmZ_D |
| 18883 | 102266912U, // UMAX_ZPmZ_H |
| 18884 | 134492168U, // UMAX_ZPmZ_S |
| 18885 | 1861784U, // UMAXv16i8 |
| 18886 | 2123936U, // UMAXv2i32 |
| 18887 | 2386088U, // UMAXv4i16 |
| 18888 | 813192U, // UMAXv4i32 |
| 18889 | 1075344U, // UMAXv8i16 |
| 18890 | 2648240U, // UMAXv8i8 |
| 18891 | 33824776U, // UMINP_ZPmZ_B |
| 18892 | 67381256U, // UMINP_ZPmZ_D |
| 18893 | 102266912U, // UMINP_ZPmZ_H |
| 18894 | 134492168U, // UMINP_ZPmZ_S |
| 18895 | 1861784U, // UMINPv16i8 |
| 18896 | 2123936U, // UMINPv2i32 |
| 18897 | 2386088U, // UMINPv4i16 |
| 18898 | 813192U, // UMINPv4i32 |
| 18899 | 1075344U, // UMINPv8i16 |
| 18900 | 2648240U, // UMINPv8i8 |
| 18901 | 8288U, // UMINQV_VPZ_B |
| 18902 | 10336U, // UMINQV_VPZ_D |
| 18903 | 22624U, // UMINQV_VPZ_H |
| 18904 | 12384U, // UMINQV_VPZ_S |
| 18905 | 0U, // UMINV_VPZ_B |
| 18906 | 1U, // UMINV_VPZ_D |
| 18907 | 1U, // UMINV_VPZ_H |
| 18908 | 1U, // UMINV_VPZ_S |
| 18909 | 40U, // UMINVv16i8v |
| 18910 | 64U, // UMINVv4i16v |
| 18911 | 72U, // UMINVv4i32v |
| 18912 | 80U, // UMINVv8i16v |
| 18913 | 88U, // UMINVv8i8v |
| 18914 | 14432U, // UMINWri |
| 18915 | 14432U, // UMINWrr |
| 18916 | 14432U, // UMINXri |
| 18917 | 14432U, // UMINXrr |
| 18918 | 5040U, // UMIN_VG2_2Z2Z_B |
| 18919 | 4552U, // UMIN_VG2_2Z2Z_D |
| 18920 | 4344U, // UMIN_VG2_2Z2Z_H |
| 18921 | 4560U, // UMIN_VG2_2Z2Z_S |
| 18922 | 184U, // UMIN_VG2_2ZZ_B |
| 18923 | 4288U, // UMIN_VG2_2ZZ_D |
| 18924 | 4128U, // UMIN_VG2_2ZZ_H |
| 18925 | 4208U, // UMIN_VG2_2ZZ_S |
| 18926 | 5040U, // UMIN_VG4_4Z4Z_B |
| 18927 | 4552U, // UMIN_VG4_4Z4Z_D |
| 18928 | 4344U, // UMIN_VG4_4Z4Z_H |
| 18929 | 4560U, // UMIN_VG4_4Z4Z_S |
| 18930 | 184U, // UMIN_VG4_4ZZ_B |
| 18931 | 4288U, // UMIN_VG4_4ZZ_D |
| 18932 | 4128U, // UMIN_VG4_4ZZ_H |
| 18933 | 4208U, // UMIN_VG4_4ZZ_S |
| 18934 | 200800U, // UMIN_ZI_B |
| 18935 | 200800U, // UMIN_ZI_D |
| 18936 | 440U, // UMIN_ZI_H |
| 18937 | 200800U, // UMIN_ZI_S |
| 18938 | 33824776U, // UMIN_ZPmZ_B |
| 18939 | 67381256U, // UMIN_ZPmZ_D |
| 18940 | 102266912U, // UMIN_ZPmZ_H |
| 18941 | 134492168U, // UMIN_ZPmZ_S |
| 18942 | 1861784U, // UMINv16i8 |
| 18943 | 2123936U, // UMINv2i32 |
| 18944 | 2386088U, // UMINv4i16 |
| 18945 | 813192U, // UMINv4i32 |
| 18946 | 1075344U, // UMINv8i16 |
| 18947 | 2648240U, // UMINv8i8 |
| 18948 | 106436704U, // UMLALB_ZZZI_D |
| 18949 | 106455136U, // UMLALB_ZZZI_S |
| 18950 | 6240U, // UMLALB_ZZZ_D |
| 18951 | 4376U, // UMLALB_ZZZ_H |
| 18952 | 24672U, // UMLALB_ZZZ_S |
| 18953 | 84521U, // UMLALL_MZZI_BtoS |
| 18954 | 84225U, // UMLALL_MZZI_HtoD |
| 18955 | 4649U, // UMLALL_MZZ_BtoS |
| 18956 | 4353U, // UMLALL_MZZ_HtoD |
| 18957 | 119320U, // UMLALL_VG2_M2Z2Z_BtoS |
| 18958 | 5273840U, // UMLALL_VG2_M2Z2Z_HtoD |
| 18959 | 10082840U, // UMLALL_VG2_M2ZZI_BtoS |
| 18960 | 206862576U, // UMLALL_VG2_M2ZZI_HtoD |
| 18961 | 121370U, // UMLALL_VG2_M2ZZ_BtoS |
| 18962 | 106199282U, // UMLALL_VG2_M2ZZ_HtoD |
| 18963 | 119321U, // UMLALL_VG4_M4Z4Z_BtoS |
| 18964 | 5273841U, // UMLALL_VG4_M4Z4Z_HtoD |
| 18965 | 10082841U, // UMLALL_VG4_M4ZZI_BtoS |
| 18966 | 206862577U, // UMLALL_VG4_M4ZZI_HtoD |
| 18967 | 121370U, // UMLALL_VG4_M4ZZ_BtoS |
| 18968 | 106199282U, // UMLALL_VG4_M4ZZ_HtoD |
| 18969 | 106436704U, // UMLALT_ZZZI_D |
| 18970 | 106455136U, // UMLALT_ZZZI_S |
| 18971 | 6240U, // UMLALT_ZZZ_D |
| 18972 | 4376U, // UMLALT_ZZZ_H |
| 18973 | 24672U, // UMLALT_ZZZ_S |
| 18974 | 84225U, // UMLAL_MZZI_HtoS |
| 18975 | 4353U, // UMLAL_MZZ_HtoS |
| 18976 | 5273840U, // UMLAL_VG2_M2Z2Z_HtoS |
| 18977 | 206862576U, // UMLAL_VG2_M2ZZI_S |
| 18978 | 106199280U, // UMLAL_VG2_M2ZZ_HtoS |
| 18979 | 5273841U, // UMLAL_VG4_M4Z4Z_HtoS |
| 18980 | 206862577U, // UMLAL_VG4_M4ZZI_HtoS |
| 18981 | 106199281U, // UMLAL_VG4_M4ZZ_HtoS |
| 18982 | 1863832U, // UMLALv16i8_v8i16 |
| 18983 | 244609184U, // UMLALv2i32_indexed |
| 18984 | 2125984U, // UMLALv2i32_v2i64 |
| 18985 | 240939176U, // UMLALv4i16_indexed |
| 18986 | 2388136U, // UMLALv4i16_v4i32 |
| 18987 | 244609160U, // UMLALv4i32_indexed |
| 18988 | 815240U, // UMLALv4i32_v2i64 |
| 18989 | 240939152U, // UMLALv8i16_indexed |
| 18990 | 1077392U, // UMLALv8i16_v4i32 |
| 18991 | 2650288U, // UMLALv8i8_v8i16 |
| 18992 | 106436704U, // UMLSLB_ZZZI_D |
| 18993 | 106455136U, // UMLSLB_ZZZI_S |
| 18994 | 6240U, // UMLSLB_ZZZ_D |
| 18995 | 4376U, // UMLSLB_ZZZ_H |
| 18996 | 24672U, // UMLSLB_ZZZ_S |
| 18997 | 84521U, // UMLSLL_MZZI_BtoS |
| 18998 | 84225U, // UMLSLL_MZZI_HtoD |
| 18999 | 4649U, // UMLSLL_MZZ_BtoS |
| 19000 | 4353U, // UMLSLL_MZZ_HtoD |
| 19001 | 119320U, // UMLSLL_VG2_M2Z2Z_BtoS |
| 19002 | 5273840U, // UMLSLL_VG2_M2Z2Z_HtoD |
| 19003 | 10082840U, // UMLSLL_VG2_M2ZZI_BtoS |
| 19004 | 206862576U, // UMLSLL_VG2_M2ZZI_HtoD |
| 19005 | 121370U, // UMLSLL_VG2_M2ZZ_BtoS |
| 19006 | 106199282U, // UMLSLL_VG2_M2ZZ_HtoD |
| 19007 | 119321U, // UMLSLL_VG4_M4Z4Z_BtoS |
| 19008 | 5273841U, // UMLSLL_VG4_M4Z4Z_HtoD |
| 19009 | 10082841U, // UMLSLL_VG4_M4ZZI_BtoS |
| 19010 | 206862577U, // UMLSLL_VG4_M4ZZI_HtoD |
| 19011 | 121370U, // UMLSLL_VG4_M4ZZ_BtoS |
| 19012 | 106199282U, // UMLSLL_VG4_M4ZZ_HtoD |
| 19013 | 106436704U, // UMLSLT_ZZZI_D |
| 19014 | 106455136U, // UMLSLT_ZZZI_S |
| 19015 | 6240U, // UMLSLT_ZZZ_D |
| 19016 | 4376U, // UMLSLT_ZZZ_H |
| 19017 | 24672U, // UMLSLT_ZZZ_S |
| 19018 | 84225U, // UMLSL_MZZI_HtoS |
| 19019 | 4353U, // UMLSL_MZZ_HtoS |
| 19020 | 5273840U, // UMLSL_VG2_M2Z2Z_HtoS |
| 19021 | 206862576U, // UMLSL_VG2_M2ZZI_S |
| 19022 | 106199280U, // UMLSL_VG2_M2ZZ_HtoS |
| 19023 | 5273841U, // UMLSL_VG4_M4Z4Z_HtoS |
| 19024 | 206862577U, // UMLSL_VG4_M4ZZI_HtoS |
| 19025 | 106199281U, // UMLSL_VG4_M4ZZ_HtoS |
| 19026 | 1863832U, // UMLSLv16i8_v8i16 |
| 19027 | 244609184U, // UMLSLv2i32_indexed |
| 19028 | 2125984U, // UMLSLv2i32_v2i64 |
| 19029 | 240939176U, // UMLSLv4i16_indexed |
| 19030 | 2388136U, // UMLSLv4i16_v4i32 |
| 19031 | 244609160U, // UMLSLv4i32_indexed |
| 19032 | 815240U, // UMLSLv4i32_v2i64 |
| 19033 | 240939152U, // UMLSLv8i16_indexed |
| 19034 | 1077392U, // UMLSLv8i16_v4i32 |
| 19035 | 2650288U, // UMLSLv8i8_v8i16 |
| 19036 | 1863832U, // UMMLA |
| 19037 | 4377U, // UMMLA_ZZZ |
| 19038 | 2U, // UMOP4A_M2Z2Z_BToS |
| 19039 | 1U, // UMOP4A_M2Z2Z_HToS |
| 19040 | 1U, // UMOP4A_M2Z2Z_HtoD |
| 19041 | 3U, // UMOP4A_M2ZZ_BToS |
| 19042 | 1U, // UMOP4A_M2ZZ_HToS |
| 19043 | 1U, // UMOP4A_M2ZZ_HtoD |
| 19044 | 560U, // UMOP4A_MZ2Z_BToS |
| 19045 | 264U, // UMOP4A_MZ2Z_HToS |
| 19046 | 264U, // UMOP4A_MZ2Z_HtoD |
| 19047 | 4376U, // UMOP4A_MZZ_BToS |
| 19048 | 4112U, // UMOP4A_MZZ_HToS |
| 19049 | 4112U, // UMOP4A_MZZ_HtoD |
| 19050 | 2U, // UMOP4S_M2Z2Z_BToS |
| 19051 | 1U, // UMOP4S_M2Z2Z_HToS |
| 19052 | 1U, // UMOP4S_M2Z2Z_HtoD |
| 19053 | 3U, // UMOP4S_M2ZZ_BToS |
| 19054 | 1U, // UMOP4S_M2ZZ_HToS |
| 19055 | 1U, // UMOP4S_M2ZZ_HtoD |
| 19056 | 560U, // UMOP4S_MZ2Z_BToS |
| 19057 | 264U, // UMOP4S_MZ2Z_HToS |
| 19058 | 264U, // UMOP4S_MZ2Z_HtoD |
| 19059 | 4376U, // UMOP4S_MZZ_BToS |
| 19060 | 4112U, // UMOP4S_MZZ_HToS |
| 19061 | 4112U, // UMOP4S_MZZ_HtoD |
| 19062 | 88168U, // UMOPA_MPPZZ_D |
| 19063 | 88168U, // UMOPA_MPPZZ_HtoS |
| 19064 | 127080U, // UMOPA_MPPZZ_S |
| 19065 | 88168U, // UMOPS_MPPZZ_D |
| 19066 | 88168U, // UMOPS_MPPZZ_HtoS |
| 19067 | 127080U, // UMOPS_MPPZZ_S |
| 19068 | 108936U, // UMOVvi16 |
| 19069 | 108936U, // UMOVvi16_idx0 |
| 19070 | 108944U, // UMOVvi32 |
| 19071 | 108944U, // UMOVvi32_idx0 |
| 19072 | 108952U, // UMOVvi64 |
| 19073 | 108952U, // UMOVvi64_idx0 |
| 19074 | 108960U, // UMOVvi8 |
| 19075 | 108960U, // UMOVvi8_idx0 |
| 19076 | 276576U, // UMSUBLrrr |
| 19077 | 33824776U, // UMULH_ZPmZ_B |
| 19078 | 67381256U, // UMULH_ZPmZ_D |
| 19079 | 102266912U, // UMULH_ZPmZ_H |
| 19080 | 134492168U, // UMULH_ZPmZ_S |
| 19081 | 8288U, // UMULH_ZZZ_B |
| 19082 | 10336U, // UMULH_ZZZ_D |
| 19083 | 4128U, // UMULH_ZZZ_H |
| 19084 | 12384U, // UMULH_ZZZ_S |
| 19085 | 14432U, // UMULHrr |
| 19086 | 11808864U, // UMULLB_ZZZI_D |
| 19087 | 11819104U, // UMULLB_ZZZI_S |
| 19088 | 12384U, // UMULLB_ZZZ_D |
| 19089 | 184U, // UMULLB_ZZZ_H |
| 19090 | 22624U, // UMULLB_ZZZ_S |
| 19091 | 11808864U, // UMULLT_ZZZI_D |
| 19092 | 11819104U, // UMULLT_ZZZI_S |
| 19093 | 12384U, // UMULLT_ZZZ_D |
| 19094 | 184U, // UMULLT_ZZZ_H |
| 19095 | 22624U, // UMULLT_ZZZ_S |
| 19096 | 1861784U, // UMULLv16i8_v8i16 |
| 19097 | 747923616U, // UMULLv2i32_indexed |
| 19098 | 2123936U, // UMULLv2i32_v2i64 |
| 19099 | 744253608U, // UMULLv4i16_indexed |
| 19100 | 2386088U, // UMULLv4i16_v4i32 |
| 19101 | 747923592U, // UMULLv4i32_indexed |
| 19102 | 813192U, // UMULLv4i32_v2i64 |
| 19103 | 744253584U, // UMULLv8i16_indexed |
| 19104 | 1075344U, // UMULLv8i16_v4i32 |
| 19105 | 2648240U, // UMULLv8i8_v8i16 |
| 19106 | 39008U, // UQADD_ZI_B |
| 19107 | 41056U, // UQADD_ZI_D |
| 19108 | 216U, // UQADD_ZI_H |
| 19109 | 43104U, // UQADD_ZI_S |
| 19110 | 33824776U, // UQADD_ZPmZ_B |
| 19111 | 67381256U, // UQADD_ZPmZ_D |
| 19112 | 102266912U, // UQADD_ZPmZ_H |
| 19113 | 134492168U, // UQADD_ZPmZ_S |
| 19114 | 8288U, // UQADD_ZZZ_B |
| 19115 | 10336U, // UQADD_ZZZ_D |
| 19116 | 4128U, // UQADD_ZZZ_H |
| 19117 | 12384U, // UQADD_ZZZ_S |
| 19118 | 1861784U, // UQADDv16i8 |
| 19119 | 14432U, // UQADDv1i16 |
| 19120 | 14432U, // UQADDv1i32 |
| 19121 | 14432U, // UQADDv1i64 |
| 19122 | 14432U, // UQADDv1i8 |
| 19123 | 2123936U, // UQADDv2i32 |
| 19124 | 551040U, // UQADDv2i64 |
| 19125 | 2386088U, // UQADDv4i16 |
| 19126 | 813192U, // UQADDv4i32 |
| 19127 | 1075344U, // UQADDv8i16 |
| 19128 | 2648240U, // UQADDv8i8 |
| 19129 | 1U, // UQCVTN_Z2Z_StoH |
| 19130 | 1U, // UQCVTN_Z4Z_DtoH |
| 19131 | 2U, // UQCVTN_Z4Z_StoB |
| 19132 | 1U, // UQCVT_Z2Z_StoH |
| 19133 | 1U, // UQCVT_Z4Z_DtoH |
| 19134 | 2U, // UQCVT_Z4Z_StoB |
| 19135 | 2U, // UQDECB_WPiI |
| 19136 | 2U, // UQDECB_XPiI |
| 19137 | 2U, // UQDECD_WPiI |
| 19138 | 2U, // UQDECD_XPiI |
| 19139 | 2U, // UQDECD_ZPiI |
| 19140 | 2U, // UQDECH_WPiI |
| 19141 | 2U, // UQDECH_XPiI |
| 19142 | 0U, // UQDECH_ZPiI |
| 19143 | 0U, // UQDECP_WP_B |
| 19144 | 0U, // UQDECP_WP_D |
| 19145 | 0U, // UQDECP_WP_H |
| 19146 | 0U, // UQDECP_WP_S |
| 19147 | 0U, // UQDECP_XP_B |
| 19148 | 0U, // UQDECP_XP_D |
| 19149 | 0U, // UQDECP_XP_H |
| 19150 | 0U, // UQDECP_XP_S |
| 19151 | 0U, // UQDECP_ZP_D |
| 19152 | 1U, // UQDECP_ZP_H |
| 19153 | 0U, // UQDECP_ZP_S |
| 19154 | 2U, // UQDECW_WPiI |
| 19155 | 2U, // UQDECW_XPiI |
| 19156 | 2U, // UQDECW_ZPiI |
| 19157 | 2U, // UQINCB_WPiI |
| 19158 | 2U, // UQINCB_XPiI |
| 19159 | 2U, // UQINCD_WPiI |
| 19160 | 2U, // UQINCD_XPiI |
| 19161 | 2U, // UQINCD_ZPiI |
| 19162 | 2U, // UQINCH_WPiI |
| 19163 | 2U, // UQINCH_XPiI |
| 19164 | 0U, // UQINCH_ZPiI |
| 19165 | 0U, // UQINCP_WP_B |
| 19166 | 0U, // UQINCP_WP_D |
| 19167 | 0U, // UQINCP_WP_H |
| 19168 | 0U, // UQINCP_WP_S |
| 19169 | 0U, // UQINCP_XP_B |
| 19170 | 0U, // UQINCP_XP_D |
| 19171 | 0U, // UQINCP_XP_H |
| 19172 | 0U, // UQINCP_XP_S |
| 19173 | 0U, // UQINCP_ZP_D |
| 19174 | 1U, // UQINCP_ZP_H |
| 19175 | 0U, // UQINCP_ZP_S |
| 19176 | 2U, // UQINCW_WPiI |
| 19177 | 2U, // UQINCW_XPiI |
| 19178 | 2U, // UQINCW_ZPiI |
| 19179 | 33824776U, // UQRSHLR_ZPmZ_B |
| 19180 | 67381256U, // UQRSHLR_ZPmZ_D |
| 19181 | 102266912U, // UQRSHLR_ZPmZ_H |
| 19182 | 134492168U, // UQRSHLR_ZPmZ_S |
| 19183 | 33824776U, // UQRSHL_ZPmZ_B |
| 19184 | 67381256U, // UQRSHL_ZPmZ_D |
| 19185 | 102266912U, // UQRSHL_ZPmZ_H |
| 19186 | 134492168U, // UQRSHL_ZPmZ_S |
| 19187 | 1861784U, // UQRSHLv16i8 |
| 19188 | 14432U, // UQRSHLv1i16 |
| 19189 | 14432U, // UQRSHLv1i32 |
| 19190 | 14432U, // UQRSHLv1i64 |
| 19191 | 14432U, // UQRSHLv1i8 |
| 19192 | 2123936U, // UQRSHLv2i32 |
| 19193 | 551040U, // UQRSHLv2i64 |
| 19194 | 2386088U, // UQRSHLv4i16 |
| 19195 | 813192U, // UQRSHLv4i32 |
| 19196 | 1075344U, // UQRSHLv8i16 |
| 19197 | 2648240U, // UQRSHLv8i8 |
| 19198 | 14432U, // UQRSHRNB_ZZI_B |
| 19199 | 4328U, // UQRSHRNB_ZZI_H |
| 19200 | 14432U, // UQRSHRNB_ZZI_S |
| 19201 | 90208U, // UQRSHRNT_ZZI_B |
| 19202 | 4464U, // UQRSHRNT_ZZI_H |
| 19203 | 90208U, // UQRSHRNT_ZZI_S |
| 19204 | 14434U, // UQRSHRN_VG4_Z4ZI_B |
| 19205 | 4328U, // UQRSHRN_VG4_Z4ZI_H |
| 19206 | 14433U, // UQRSHRN_Z2ZI_HtoB |
| 19207 | 4328U, // UQRSHRN_Z2ZI_StoH |
| 19208 | 14432U, // UQRSHRNb |
| 19209 | 14432U, // UQRSHRNh |
| 19210 | 14432U, // UQRSHRNs |
| 19211 | 90256U, // UQRSHRNv16i8_shift |
| 19212 | 14464U, // UQRSHRNv2i32_shift |
| 19213 | 14472U, // UQRSHRNv4i16_shift |
| 19214 | 90240U, // UQRSHRNv4i32_shift |
| 19215 | 90248U, // UQRSHRNv8i16_shift |
| 19216 | 14480U, // UQRSHRNv8i8_shift |
| 19217 | 4328U, // UQRSHR_VG2_Z2ZI_H |
| 19218 | 14434U, // UQRSHR_VG4_Z4ZI_B |
| 19219 | 4328U, // UQRSHR_VG4_Z4ZI_H |
| 19220 | 33824776U, // UQSHLR_ZPmZ_B |
| 19221 | 67381256U, // UQSHLR_ZPmZ_D |
| 19222 | 102266912U, // UQSHLR_ZPmZ_H |
| 19223 | 134492168U, // UQSHLR_ZPmZ_S |
| 19224 | 270344U, // UQSHL_ZPmI_B |
| 19225 | 272392U, // UQSHL_ZPmI_D |
| 19226 | 104888352U, // UQSHL_ZPmI_H |
| 19227 | 274440U, // UQSHL_ZPmI_S |
| 19228 | 33824776U, // UQSHL_ZPmZ_B |
| 19229 | 67381256U, // UQSHL_ZPmZ_D |
| 19230 | 102266912U, // UQSHL_ZPmZ_H |
| 19231 | 134492168U, // UQSHL_ZPmZ_S |
| 19232 | 14432U, // UQSHLb |
| 19233 | 14432U, // UQSHLd |
| 19234 | 14432U, // UQSHLh |
| 19235 | 14432U, // UQSHLs |
| 19236 | 1861784U, // UQSHLv16i8 |
| 19237 | 14488U, // UQSHLv16i8_shift |
| 19238 | 14432U, // UQSHLv1i16 |
| 19239 | 14432U, // UQSHLv1i32 |
| 19240 | 14432U, // UQSHLv1i64 |
| 19241 | 14432U, // UQSHLv1i8 |
| 19242 | 2123936U, // UQSHLv2i32 |
| 19243 | 14496U, // UQSHLv2i32_shift |
| 19244 | 551040U, // UQSHLv2i64 |
| 19245 | 14464U, // UQSHLv2i64_shift |
| 19246 | 2386088U, // UQSHLv4i16 |
| 19247 | 14504U, // UQSHLv4i16_shift |
| 19248 | 813192U, // UQSHLv4i32 |
| 19249 | 14472U, // UQSHLv4i32_shift |
| 19250 | 1075344U, // UQSHLv8i16 |
| 19251 | 14480U, // UQSHLv8i16_shift |
| 19252 | 2648240U, // UQSHLv8i8 |
| 19253 | 14512U, // UQSHLv8i8_shift |
| 19254 | 14432U, // UQSHRNB_ZZI_B |
| 19255 | 4328U, // UQSHRNB_ZZI_H |
| 19256 | 14432U, // UQSHRNB_ZZI_S |
| 19257 | 90208U, // UQSHRNT_ZZI_B |
| 19258 | 4464U, // UQSHRNT_ZZI_H |
| 19259 | 90208U, // UQSHRNT_ZZI_S |
| 19260 | 14433U, // UQSHRN_Z2ZI_HtoB |
| 19261 | 4328U, // UQSHRN_Z2ZI_StoH |
| 19262 | 14432U, // UQSHRNb |
| 19263 | 14432U, // UQSHRNh |
| 19264 | 14432U, // UQSHRNs |
| 19265 | 90256U, // UQSHRNv16i8_shift |
| 19266 | 14464U, // UQSHRNv2i32_shift |
| 19267 | 14472U, // UQSHRNv4i16_shift |
| 19268 | 90240U, // UQSHRNv4i32_shift |
| 19269 | 90248U, // UQSHRNv8i16_shift |
| 19270 | 14480U, // UQSHRNv8i8_shift |
| 19271 | 33824776U, // UQSUBR_ZPmZ_B |
| 19272 | 67381256U, // UQSUBR_ZPmZ_D |
| 19273 | 102266912U, // UQSUBR_ZPmZ_H |
| 19274 | 134492168U, // UQSUBR_ZPmZ_S |
| 19275 | 39008U, // UQSUB_ZI_B |
| 19276 | 41056U, // UQSUB_ZI_D |
| 19277 | 216U, // UQSUB_ZI_H |
| 19278 | 43104U, // UQSUB_ZI_S |
| 19279 | 33824776U, // UQSUB_ZPmZ_B |
| 19280 | 67381256U, // UQSUB_ZPmZ_D |
| 19281 | 102266912U, // UQSUB_ZPmZ_H |
| 19282 | 134492168U, // UQSUB_ZPmZ_S |
| 19283 | 8288U, // UQSUB_ZZZ_B |
| 19284 | 10336U, // UQSUB_ZZZ_D |
| 19285 | 4128U, // UQSUB_ZZZ_H |
| 19286 | 12384U, // UQSUB_ZZZ_S |
| 19287 | 1861784U, // UQSUBv16i8 |
| 19288 | 14432U, // UQSUBv1i16 |
| 19289 | 14432U, // UQSUBv1i32 |
| 19290 | 14432U, // UQSUBv1i64 |
| 19291 | 14432U, // UQSUBv1i8 |
| 19292 | 2123936U, // UQSUBv2i32 |
| 19293 | 551040U, // UQSUBv2i64 |
| 19294 | 2386088U, // UQSUBv4i16 |
| 19295 | 813192U, // UQSUBv4i32 |
| 19296 | 1075344U, // UQSUBv8i16 |
| 19297 | 2648240U, // UQSUBv8i8 |
| 19298 | 0U, // UQXTNB_ZZ_B |
| 19299 | 1U, // UQXTNB_ZZ_H |
| 19300 | 0U, // UQXTNB_ZZ_S |
| 19301 | 0U, // UQXTNT_ZZ_B |
| 19302 | 1U, // UQXTNT_ZZ_H |
| 19303 | 0U, // UQXTNT_ZZ_S |
| 19304 | 80U, // UQXTNv16i8 |
| 19305 | 0U, // UQXTNv1i16 |
| 19306 | 0U, // UQXTNv1i32 |
| 19307 | 0U, // UQXTNv1i8 |
| 19308 | 56U, // UQXTNv2i32 |
| 19309 | 72U, // UQXTNv4i16 |
| 19310 | 56U, // UQXTNv4i32 |
| 19311 | 72U, // UQXTNv8i16 |
| 19312 | 80U, // UQXTNv8i8 |
| 19313 | 6152U, // URECPE_ZPmZ_S |
| 19314 | 12312U, // URECPE_ZPzZ_S |
| 19315 | 48U, // URECPEv2i32 |
| 19316 | 72U, // URECPEv4i32 |
| 19317 | 33824776U, // URHADD_ZPmZ_B |
| 19318 | 67381256U, // URHADD_ZPmZ_D |
| 19319 | 102266912U, // URHADD_ZPmZ_H |
| 19320 | 134492168U, // URHADD_ZPmZ_S |
| 19321 | 1861784U, // URHADDv16i8 |
| 19322 | 2123936U, // URHADDv2i32 |
| 19323 | 2386088U, // URHADDv4i16 |
| 19324 | 813192U, // URHADDv4i32 |
| 19325 | 1075344U, // URHADDv8i16 |
| 19326 | 2648240U, // URHADDv8i8 |
| 19327 | 33824776U, // URSHLR_ZPmZ_B |
| 19328 | 67381256U, // URSHLR_ZPmZ_D |
| 19329 | 102266912U, // URSHLR_ZPmZ_H |
| 19330 | 134492168U, // URSHLR_ZPmZ_S |
| 19331 | 5040U, // URSHL_VG2_2Z2Z_B |
| 19332 | 4552U, // URSHL_VG2_2Z2Z_D |
| 19333 | 4344U, // URSHL_VG2_2Z2Z_H |
| 19334 | 4560U, // URSHL_VG2_2Z2Z_S |
| 19335 | 184U, // URSHL_VG2_2ZZ_B |
| 19336 | 4288U, // URSHL_VG2_2ZZ_D |
| 19337 | 4128U, // URSHL_VG2_2ZZ_H |
| 19338 | 4208U, // URSHL_VG2_2ZZ_S |
| 19339 | 5040U, // URSHL_VG4_4Z4Z_B |
| 19340 | 4552U, // URSHL_VG4_4Z4Z_D |
| 19341 | 4344U, // URSHL_VG4_4Z4Z_H |
| 19342 | 4560U, // URSHL_VG4_4Z4Z_S |
| 19343 | 184U, // URSHL_VG4_4ZZ_B |
| 19344 | 4288U, // URSHL_VG4_4ZZ_D |
| 19345 | 4128U, // URSHL_VG4_4ZZ_H |
| 19346 | 4208U, // URSHL_VG4_4ZZ_S |
| 19347 | 33824776U, // URSHL_ZPmZ_B |
| 19348 | 67381256U, // URSHL_ZPmZ_D |
| 19349 | 102266912U, // URSHL_ZPmZ_H |
| 19350 | 134492168U, // URSHL_ZPmZ_S |
| 19351 | 1861784U, // URSHLv16i8 |
| 19352 | 14432U, // URSHLv1i64 |
| 19353 | 2123936U, // URSHLv2i32 |
| 19354 | 551040U, // URSHLv2i64 |
| 19355 | 2386088U, // URSHLv4i16 |
| 19356 | 813192U, // URSHLv4i32 |
| 19357 | 1075344U, // URSHLv8i16 |
| 19358 | 2648240U, // URSHLv8i8 |
| 19359 | 270344U, // URSHR_ZPmI_B |
| 19360 | 272392U, // URSHR_ZPmI_D |
| 19361 | 104888352U, // URSHR_ZPmI_H |
| 19362 | 274440U, // URSHR_ZPmI_S |
| 19363 | 14432U, // URSHRd |
| 19364 | 14488U, // URSHRv16i8_shift |
| 19365 | 14496U, // URSHRv2i32_shift |
| 19366 | 14464U, // URSHRv2i64_shift |
| 19367 | 14504U, // URSHRv4i16_shift |
| 19368 | 14472U, // URSHRv4i32_shift |
| 19369 | 14480U, // URSHRv8i16_shift |
| 19370 | 14512U, // URSHRv8i8_shift |
| 19371 | 6152U, // URSQRTE_ZPmZ_S |
| 19372 | 12312U, // URSQRTE_ZPzZ_S |
| 19373 | 48U, // URSQRTEv2i32 |
| 19374 | 72U, // URSQRTEv4i32 |
| 19375 | 4465U, // URSRA_ZZI_B |
| 19376 | 90208U, // URSRA_ZZI_D |
| 19377 | 4464U, // URSRA_ZZI_H |
| 19378 | 90208U, // URSRA_ZZI_S |
| 19379 | 90209U, // URSRAd |
| 19380 | 90264U, // URSRAv16i8_shift |
| 19381 | 90272U, // URSRAv2i32_shift |
| 19382 | 90240U, // URSRAv2i64_shift |
| 19383 | 90280U, // URSRAv4i16_shift |
| 19384 | 90248U, // URSRAv4i32_shift |
| 19385 | 90256U, // URSRAv8i16_shift |
| 19386 | 90288U, // URSRAv8i8_shift |
| 19387 | 119320U, // USDOT_VG2_M2Z2Z_BToS |
| 19388 | 10082840U, // USDOT_VG2_M2ZZI_BToS |
| 19389 | 121368U, // USDOT_VG2_M2ZZ_BToS |
| 19390 | 119321U, // USDOT_VG4_M4Z4Z_BToS |
| 19391 | 10082841U, // USDOT_VG4_M4ZZI_BToS |
| 19392 | 121369U, // USDOT_VG4_M4ZZ_BToS |
| 19393 | 4377U, // USDOT_ZZZ |
| 19394 | 86297U, // USDOT_ZZZI |
| 19395 | 10252440U, // USDOTlanev16i8 |
| 19396 | 10252464U, // USDOTlanev8i8 |
| 19397 | 1863832U, // USDOTv16i8 |
| 19398 | 2650288U, // USDOTv8i8 |
| 19399 | 14432U, // USHLLB_ZZI_D |
| 19400 | 4328U, // USHLLB_ZZI_H |
| 19401 | 14432U, // USHLLB_ZZI_S |
| 19402 | 14432U, // USHLLT_ZZI_D |
| 19403 | 4328U, // USHLLT_ZZI_H |
| 19404 | 14432U, // USHLLT_ZZI_S |
| 19405 | 14488U, // USHLLv16i8_shift |
| 19406 | 14496U, // USHLLv2i32_shift |
| 19407 | 14504U, // USHLLv4i16_shift |
| 19408 | 14472U, // USHLLv4i32_shift |
| 19409 | 14480U, // USHLLv8i16_shift |
| 19410 | 14512U, // USHLLv8i8_shift |
| 19411 | 1861784U, // USHLv16i8 |
| 19412 | 14432U, // USHLv1i64 |
| 19413 | 2123936U, // USHLv2i32 |
| 19414 | 551040U, // USHLv2i64 |
| 19415 | 2386088U, // USHLv4i16 |
| 19416 | 813192U, // USHLv4i32 |
| 19417 | 1075344U, // USHLv8i16 |
| 19418 | 2648240U, // USHLv8i8 |
| 19419 | 14432U, // USHRd |
| 19420 | 14488U, // USHRv16i8_shift |
| 19421 | 14496U, // USHRv2i32_shift |
| 19422 | 14464U, // USHRv2i64_shift |
| 19423 | 14504U, // USHRv4i16_shift |
| 19424 | 14472U, // USHRv4i32_shift |
| 19425 | 14480U, // USHRv8i16_shift |
| 19426 | 14512U, // USHRv8i8_shift |
| 19427 | 84521U, // USMLALL_MZZI_BtoS |
| 19428 | 4649U, // USMLALL_MZZ_BtoS |
| 19429 | 119320U, // USMLALL_VG2_M2Z2Z_BtoS |
| 19430 | 10082840U, // USMLALL_VG2_M2ZZI_BtoS |
| 19431 | 121370U, // USMLALL_VG2_M2ZZ_BtoS |
| 19432 | 119321U, // USMLALL_VG4_M4Z4Z_BtoS |
| 19433 | 10082841U, // USMLALL_VG4_M4ZZI_BtoS |
| 19434 | 121370U, // USMLALL_VG4_M4ZZ_BtoS |
| 19435 | 1863832U, // USMMLA |
| 19436 | 4377U, // USMMLA_ZZZ |
| 19437 | 2U, // USMOP4A_M2Z2Z_BToS |
| 19438 | 1U, // USMOP4A_M2Z2Z_HtoD |
| 19439 | 3U, // USMOP4A_M2ZZ_BToS |
| 19440 | 1U, // USMOP4A_M2ZZ_HtoD |
| 19441 | 560U, // USMOP4A_MZ2Z_BToS |
| 19442 | 264U, // USMOP4A_MZ2Z_HtoD |
| 19443 | 4376U, // USMOP4A_MZZ_BToS |
| 19444 | 4112U, // USMOP4A_MZZ_HtoD |
| 19445 | 2U, // USMOP4S_M2Z2Z_BToS |
| 19446 | 1U, // USMOP4S_M2Z2Z_HtoD |
| 19447 | 3U, // USMOP4S_M2ZZ_BToS |
| 19448 | 1U, // USMOP4S_M2ZZ_HtoD |
| 19449 | 560U, // USMOP4S_MZ2Z_BToS |
| 19450 | 264U, // USMOP4S_MZ2Z_HtoD |
| 19451 | 4376U, // USMOP4S_MZZ_BToS |
| 19452 | 4112U, // USMOP4S_MZZ_HtoD |
| 19453 | 88168U, // USMOPA_MPPZZ_D |
| 19454 | 127080U, // USMOPA_MPPZZ_S |
| 19455 | 88168U, // USMOPS_MPPZZ_D |
| 19456 | 127080U, // USMOPS_MPPZZ_S |
| 19457 | 33824776U, // USQADD_ZPmZ_B |
| 19458 | 67381256U, // USQADD_ZPmZ_D |
| 19459 | 102266912U, // USQADD_ZPmZ_H |
| 19460 | 134492168U, // USQADD_ZPmZ_S |
| 19461 | 40U, // USQADDv16i8 |
| 19462 | 1U, // USQADDv1i16 |
| 19463 | 1U, // USQADDv1i32 |
| 19464 | 1U, // USQADDv1i64 |
| 19465 | 1U, // USQADDv1i8 |
| 19466 | 48U, // USQADDv2i32 |
| 19467 | 56U, // USQADDv2i64 |
| 19468 | 64U, // USQADDv4i16 |
| 19469 | 72U, // USQADDv4i32 |
| 19470 | 80U, // USQADDv8i16 |
| 19471 | 88U, // USQADDv8i8 |
| 19472 | 4465U, // USRA_ZZI_B |
| 19473 | 90208U, // USRA_ZZI_D |
| 19474 | 4464U, // USRA_ZZI_H |
| 19475 | 90208U, // USRA_ZZI_S |
| 19476 | 90209U, // USRAd |
| 19477 | 90264U, // USRAv16i8_shift |
| 19478 | 90272U, // USRAv2i32_shift |
| 19479 | 90240U, // USRAv2i64_shift |
| 19480 | 90280U, // USRAv4i16_shift |
| 19481 | 90248U, // USRAv4i32_shift |
| 19482 | 90256U, // USRAv8i16_shift |
| 19483 | 90288U, // USRAv8i8_shift |
| 19484 | 92259U, // USTMOPA_M2ZZZI_BtoS |
| 19485 | 12384U, // USUBLB_ZZZ_D |
| 19486 | 184U, // USUBLB_ZZZ_H |
| 19487 | 22624U, // USUBLB_ZZZ_S |
| 19488 | 12384U, // USUBLT_ZZZ_D |
| 19489 | 184U, // USUBLT_ZZZ_H |
| 19490 | 22624U, // USUBLT_ZZZ_S |
| 19491 | 1861784U, // USUBLv16i8_v8i16 |
| 19492 | 2123936U, // USUBLv2i32_v2i64 |
| 19493 | 2386088U, // USUBLv4i16_v4i32 |
| 19494 | 813192U, // USUBLv4i32_v2i64 |
| 19495 | 1075344U, // USUBLv8i16_v4i32 |
| 19496 | 2648240U, // USUBLv8i8_v8i16 |
| 19497 | 12384U, // USUBWB_ZZZ_D |
| 19498 | 184U, // USUBWB_ZZZ_H |
| 19499 | 22624U, // USUBWB_ZZZ_S |
| 19500 | 12384U, // USUBWT_ZZZ_D |
| 19501 | 184U, // USUBWT_ZZZ_H |
| 19502 | 22624U, // USUBWT_ZZZ_S |
| 19503 | 1861776U, // USUBWv16i8_v8i16 |
| 19504 | 2123904U, // USUBWv2i32_v2i64 |
| 19505 | 2386056U, // USUBWv4i16_v4i32 |
| 19506 | 813184U, // USUBWv4i32_v2i64 |
| 19507 | 1075336U, // USUBWv8i16_v4i32 |
| 19508 | 2648208U, // USUBWv8i8_v8i16 |
| 19509 | 10082841U, // USVDOT_VG4_M4ZZI_BToS |
| 19510 | 92259U, // UTMOPA_M2ZZZI_BtoS |
| 19511 | 92257U, // UTMOPA_M2ZZZI_HtoS |
| 19512 | 0U, // UUNPKHI_ZZ_D |
| 19513 | 1U, // UUNPKHI_ZZ_H |
| 19514 | 0U, // UUNPKHI_ZZ_S |
| 19515 | 0U, // UUNPKLO_ZZ_D |
| 19516 | 1U, // UUNPKLO_ZZ_H |
| 19517 | 0U, // UUNPKLO_ZZ_S |
| 19518 | 1U, // UUNPK_VG2_2ZZ_D |
| 19519 | 1U, // UUNPK_VG2_2ZZ_H |
| 19520 | 1U, // UUNPK_VG2_2ZZ_S |
| 19521 | 1U, // UUNPK_VG4_4Z2Z_D |
| 19522 | 1U, // UUNPK_VG4_4Z2Z_H |
| 19523 | 1U, // UUNPK_VG4_4Z2Z_S |
| 19524 | 206862576U, // UVDOT_VG2_M2ZZI_HtoS |
| 19525 | 10082841U, // UVDOT_VG4_M4ZZI_BtoS |
| 19526 | 206862577U, // UVDOT_VG4_M4ZZI_HtoD |
| 19527 | 2056U, // UXTB_ZPmZ_D |
| 19528 | 4112U, // UXTB_ZPmZ_H |
| 19529 | 6152U, // UXTB_ZPmZ_S |
| 19530 | 10264U, // UXTB_ZPzZ_D |
| 19531 | 4128U, // UXTB_ZPzZ_H |
| 19532 | 12312U, // UXTB_ZPzZ_S |
| 19533 | 2056U, // UXTH_ZPmZ_D |
| 19534 | 6152U, // UXTH_ZPmZ_S |
| 19535 | 10264U, // UXTH_ZPzZ_D |
| 19536 | 12312U, // UXTH_ZPzZ_S |
| 19537 | 2056U, // UXTW_ZPmZ_D |
| 19538 | 10264U, // UXTW_ZPzZ_D |
| 19539 | 8288U, // UZP1_PPP_B |
| 19540 | 10336U, // UZP1_PPP_D |
| 19541 | 4128U, // UZP1_PPP_H |
| 19542 | 12384U, // UZP1_PPP_S |
| 19543 | 8288U, // UZP1_ZZZ_B |
| 19544 | 10336U, // UZP1_ZZZ_D |
| 19545 | 4128U, // UZP1_ZZZ_H |
| 19546 | 4320U, // UZP1_ZZZ_Q |
| 19547 | 12384U, // UZP1_ZZZ_S |
| 19548 | 1861784U, // UZP1v16i8 |
| 19549 | 2123936U, // UZP1v2i32 |
| 19550 | 551040U, // UZP1v2i64 |
| 19551 | 2386088U, // UZP1v4i16 |
| 19552 | 813192U, // UZP1v4i32 |
| 19553 | 1075344U, // UZP1v8i16 |
| 19554 | 2648240U, // UZP1v8i8 |
| 19555 | 8288U, // UZP2_PPP_B |
| 19556 | 10336U, // UZP2_PPP_D |
| 19557 | 4128U, // UZP2_PPP_H |
| 19558 | 12384U, // UZP2_PPP_S |
| 19559 | 8288U, // UZP2_ZZZ_B |
| 19560 | 10336U, // UZP2_ZZZ_D |
| 19561 | 4128U, // UZP2_ZZZ_H |
| 19562 | 4320U, // UZP2_ZZZ_Q |
| 19563 | 12384U, // UZP2_ZZZ_S |
| 19564 | 1861784U, // UZP2v16i8 |
| 19565 | 2123936U, // UZP2v2i32 |
| 19566 | 551040U, // UZP2v2i64 |
| 19567 | 2386088U, // UZP2v4i16 |
| 19568 | 813192U, // UZP2v4i32 |
| 19569 | 1075344U, // UZP2v8i16 |
| 19570 | 2648240U, // UZP2v8i8 |
| 19571 | 8288U, // UZPQ1_ZZZ_B |
| 19572 | 10336U, // UZPQ1_ZZZ_D |
| 19573 | 4128U, // UZPQ1_ZZZ_H |
| 19574 | 12384U, // UZPQ1_ZZZ_S |
| 19575 | 8288U, // UZPQ2_ZZZ_B |
| 19576 | 10336U, // UZPQ2_ZZZ_D |
| 19577 | 4128U, // UZPQ2_ZZZ_H |
| 19578 | 12384U, // UZPQ2_ZZZ_S |
| 19579 | 184U, // UZP_VG2_2ZZZ_B |
| 19580 | 0U, // UZP_VG2_2ZZZ_D |
| 19581 | 4128U, // UZP_VG2_2ZZZ_H |
| 19582 | 4320U, // UZP_VG2_2ZZZ_Q |
| 19583 | 4208U, // UZP_VG2_2ZZZ_S |
| 19584 | 1U, // UZP_VG4_4Z4Z_B |
| 19585 | 1U, // UZP_VG4_4Z4Z_D |
| 19586 | 1U, // UZP_VG4_4Z4Z_H |
| 19587 | 0U, // UZP_VG4_4Z4Z_Q |
| 19588 | 1U, // UZP_VG4_4Z4Z_S |
| 19589 | 0U, // WFET |
| 19590 | 0U, // WFIT |
| 19591 | 4328U, // WHILEGE_2PXX_B |
| 19592 | 4328U, // WHILEGE_2PXX_D |
| 19593 | 4328U, // WHILEGE_2PXX_H |
| 19594 | 4328U, // WHILEGE_2PXX_S |
| 19595 | 1543780448U, // WHILEGE_CXX_B |
| 19596 | 1543780448U, // WHILEGE_CXX_D |
| 19597 | 1543780448U, // WHILEGE_CXX_H |
| 19598 | 1543780448U, // WHILEGE_CXX_S |
| 19599 | 14432U, // WHILEGE_PWW_B |
| 19600 | 14432U, // WHILEGE_PWW_D |
| 19601 | 4328U, // WHILEGE_PWW_H |
| 19602 | 14432U, // WHILEGE_PWW_S |
| 19603 | 14432U, // WHILEGE_PXX_B |
| 19604 | 14432U, // WHILEGE_PXX_D |
| 19605 | 4328U, // WHILEGE_PXX_H |
| 19606 | 14432U, // WHILEGE_PXX_S |
| 19607 | 4328U, // WHILEGT_2PXX_B |
| 19608 | 4328U, // WHILEGT_2PXX_D |
| 19609 | 4328U, // WHILEGT_2PXX_H |
| 19610 | 4328U, // WHILEGT_2PXX_S |
| 19611 | 1543780448U, // WHILEGT_CXX_B |
| 19612 | 1543780448U, // WHILEGT_CXX_D |
| 19613 | 1543780448U, // WHILEGT_CXX_H |
| 19614 | 1543780448U, // WHILEGT_CXX_S |
| 19615 | 14432U, // WHILEGT_PWW_B |
| 19616 | 14432U, // WHILEGT_PWW_D |
| 19617 | 4328U, // WHILEGT_PWW_H |
| 19618 | 14432U, // WHILEGT_PWW_S |
| 19619 | 14432U, // WHILEGT_PXX_B |
| 19620 | 14432U, // WHILEGT_PXX_D |
| 19621 | 4328U, // WHILEGT_PXX_H |
| 19622 | 14432U, // WHILEGT_PXX_S |
| 19623 | 4328U, // WHILEHI_2PXX_B |
| 19624 | 4328U, // WHILEHI_2PXX_D |
| 19625 | 4328U, // WHILEHI_2PXX_H |
| 19626 | 4328U, // WHILEHI_2PXX_S |
| 19627 | 1543780448U, // WHILEHI_CXX_B |
| 19628 | 1543780448U, // WHILEHI_CXX_D |
| 19629 | 1543780448U, // WHILEHI_CXX_H |
| 19630 | 1543780448U, // WHILEHI_CXX_S |
| 19631 | 14432U, // WHILEHI_PWW_B |
| 19632 | 14432U, // WHILEHI_PWW_D |
| 19633 | 4328U, // WHILEHI_PWW_H |
| 19634 | 14432U, // WHILEHI_PWW_S |
| 19635 | 14432U, // WHILEHI_PXX_B |
| 19636 | 14432U, // WHILEHI_PXX_D |
| 19637 | 4328U, // WHILEHI_PXX_H |
| 19638 | 14432U, // WHILEHI_PXX_S |
| 19639 | 4328U, // WHILEHS_2PXX_B |
| 19640 | 4328U, // WHILEHS_2PXX_D |
| 19641 | 4328U, // WHILEHS_2PXX_H |
| 19642 | 4328U, // WHILEHS_2PXX_S |
| 19643 | 1543780448U, // WHILEHS_CXX_B |
| 19644 | 1543780448U, // WHILEHS_CXX_D |
| 19645 | 1543780448U, // WHILEHS_CXX_H |
| 19646 | 1543780448U, // WHILEHS_CXX_S |
| 19647 | 14432U, // WHILEHS_PWW_B |
| 19648 | 14432U, // WHILEHS_PWW_D |
| 19649 | 4328U, // WHILEHS_PWW_H |
| 19650 | 14432U, // WHILEHS_PWW_S |
| 19651 | 14432U, // WHILEHS_PXX_B |
| 19652 | 14432U, // WHILEHS_PXX_D |
| 19653 | 4328U, // WHILEHS_PXX_H |
| 19654 | 14432U, // WHILEHS_PXX_S |
| 19655 | 4328U, // WHILELE_2PXX_B |
| 19656 | 4328U, // WHILELE_2PXX_D |
| 19657 | 4328U, // WHILELE_2PXX_H |
| 19658 | 4328U, // WHILELE_2PXX_S |
| 19659 | 1543780448U, // WHILELE_CXX_B |
| 19660 | 1543780448U, // WHILELE_CXX_D |
| 19661 | 1543780448U, // WHILELE_CXX_H |
| 19662 | 1543780448U, // WHILELE_CXX_S |
| 19663 | 14432U, // WHILELE_PWW_B |
| 19664 | 14432U, // WHILELE_PWW_D |
| 19665 | 4328U, // WHILELE_PWW_H |
| 19666 | 14432U, // WHILELE_PWW_S |
| 19667 | 14432U, // WHILELE_PXX_B |
| 19668 | 14432U, // WHILELE_PXX_D |
| 19669 | 4328U, // WHILELE_PXX_H |
| 19670 | 14432U, // WHILELE_PXX_S |
| 19671 | 4328U, // WHILELO_2PXX_B |
| 19672 | 4328U, // WHILELO_2PXX_D |
| 19673 | 4328U, // WHILELO_2PXX_H |
| 19674 | 4328U, // WHILELO_2PXX_S |
| 19675 | 1543780448U, // WHILELO_CXX_B |
| 19676 | 1543780448U, // WHILELO_CXX_D |
| 19677 | 1543780448U, // WHILELO_CXX_H |
| 19678 | 1543780448U, // WHILELO_CXX_S |
| 19679 | 14432U, // WHILELO_PWW_B |
| 19680 | 14432U, // WHILELO_PWW_D |
| 19681 | 4328U, // WHILELO_PWW_H |
| 19682 | 14432U, // WHILELO_PWW_S |
| 19683 | 14432U, // WHILELO_PXX_B |
| 19684 | 14432U, // WHILELO_PXX_D |
| 19685 | 4328U, // WHILELO_PXX_H |
| 19686 | 14432U, // WHILELO_PXX_S |
| 19687 | 4328U, // WHILELS_2PXX_B |
| 19688 | 4328U, // WHILELS_2PXX_D |
| 19689 | 4328U, // WHILELS_2PXX_H |
| 19690 | 4328U, // WHILELS_2PXX_S |
| 19691 | 1543780448U, // WHILELS_CXX_B |
| 19692 | 1543780448U, // WHILELS_CXX_D |
| 19693 | 1543780448U, // WHILELS_CXX_H |
| 19694 | 1543780448U, // WHILELS_CXX_S |
| 19695 | 14432U, // WHILELS_PWW_B |
| 19696 | 14432U, // WHILELS_PWW_D |
| 19697 | 4328U, // WHILELS_PWW_H |
| 19698 | 14432U, // WHILELS_PWW_S |
| 19699 | 14432U, // WHILELS_PXX_B |
| 19700 | 14432U, // WHILELS_PXX_D |
| 19701 | 4328U, // WHILELS_PXX_H |
| 19702 | 14432U, // WHILELS_PXX_S |
| 19703 | 4328U, // WHILELT_2PXX_B |
| 19704 | 4328U, // WHILELT_2PXX_D |
| 19705 | 4328U, // WHILELT_2PXX_H |
| 19706 | 4328U, // WHILELT_2PXX_S |
| 19707 | 1543780448U, // WHILELT_CXX_B |
| 19708 | 1543780448U, // WHILELT_CXX_D |
| 19709 | 1543780448U, // WHILELT_CXX_H |
| 19710 | 1543780448U, // WHILELT_CXX_S |
| 19711 | 14432U, // WHILELT_PWW_B |
| 19712 | 14432U, // WHILELT_PWW_D |
| 19713 | 4328U, // WHILELT_PWW_H |
| 19714 | 14432U, // WHILELT_PWW_S |
| 19715 | 14432U, // WHILELT_PXX_B |
| 19716 | 14432U, // WHILELT_PXX_D |
| 19717 | 4328U, // WHILELT_PXX_H |
| 19718 | 14432U, // WHILELT_PXX_S |
| 19719 | 14432U, // WHILERW_PXX_B |
| 19720 | 14432U, // WHILERW_PXX_D |
| 19721 | 4328U, // WHILERW_PXX_H |
| 19722 | 14432U, // WHILERW_PXX_S |
| 19723 | 14432U, // WHILEWR_PXX_B |
| 19724 | 14432U, // WHILEWR_PXX_D |
| 19725 | 4328U, // WHILEWR_PXX_H |
| 19726 | 14432U, // WHILEWR_PXX_S |
| 19727 | 0U, // WRFFR |
| 19728 | 0U, // XAFLAG |
| 19729 | 8415360U, // XAR |
| 19730 | 270432U, // XAR_ZZZI_B |
| 19731 | 272480U, // XAR_ZZZI_D |
| 19732 | 104888352U, // XAR_ZZZI_H |
| 19733 | 274528U, // XAR_ZZZI_S |
| 19734 | 0U, // XPACD |
| 19735 | 0U, // XPACI |
| 19736 | 0U, // XPACLRI |
| 19737 | 80U, // XTNv16i8 |
| 19738 | 56U, // XTNv2i32 |
| 19739 | 72U, // XTNv4i16 |
| 19740 | 56U, // XTNv4i32 |
| 19741 | 72U, // XTNv8i16 |
| 19742 | 80U, // XTNv8i8 |
| 19743 | 0U, // ZERO_M |
| 19744 | 5U, // ZERO_MXI_2Z |
| 19745 | 5U, // ZERO_MXI_4Z |
| 19746 | 4U, // ZERO_MXI_VG2_2Z |
| 19747 | 4U, // ZERO_MXI_VG2_4Z |
| 19748 | 4U, // ZERO_MXI_VG2_Z |
| 19749 | 4U, // ZERO_MXI_VG4_2Z |
| 19750 | 4U, // ZERO_MXI_VG4_4Z |
| 19751 | 4U, // ZERO_MXI_VG4_Z |
| 19752 | 0U, // ZERO_T |
| 19753 | 8288U, // ZIP1_PPP_B |
| 19754 | 10336U, // ZIP1_PPP_D |
| 19755 | 4128U, // ZIP1_PPP_H |
| 19756 | 12384U, // ZIP1_PPP_S |
| 19757 | 8288U, // ZIP1_ZZZ_B |
| 19758 | 10336U, // ZIP1_ZZZ_D |
| 19759 | 4128U, // ZIP1_ZZZ_H |
| 19760 | 4320U, // ZIP1_ZZZ_Q |
| 19761 | 12384U, // ZIP1_ZZZ_S |
| 19762 | 1861784U, // ZIP1v16i8 |
| 19763 | 2123936U, // ZIP1v2i32 |
| 19764 | 551040U, // ZIP1v2i64 |
| 19765 | 2386088U, // ZIP1v4i16 |
| 19766 | 813192U, // ZIP1v4i32 |
| 19767 | 1075344U, // ZIP1v8i16 |
| 19768 | 2648240U, // ZIP1v8i8 |
| 19769 | 8288U, // ZIP2_PPP_B |
| 19770 | 10336U, // ZIP2_PPP_D |
| 19771 | 4128U, // ZIP2_PPP_H |
| 19772 | 12384U, // ZIP2_PPP_S |
| 19773 | 8288U, // ZIP2_ZZZ_B |
| 19774 | 10336U, // ZIP2_ZZZ_D |
| 19775 | 4128U, // ZIP2_ZZZ_H |
| 19776 | 4320U, // ZIP2_ZZZ_Q |
| 19777 | 12384U, // ZIP2_ZZZ_S |
| 19778 | 1861784U, // ZIP2v16i8 |
| 19779 | 2123936U, // ZIP2v2i32 |
| 19780 | 551040U, // ZIP2v2i64 |
| 19781 | 2386088U, // ZIP2v4i16 |
| 19782 | 813192U, // ZIP2v4i32 |
| 19783 | 1075344U, // ZIP2v8i16 |
| 19784 | 2648240U, // ZIP2v8i8 |
| 19785 | 8288U, // ZIPQ1_ZZZ_B |
| 19786 | 10336U, // ZIPQ1_ZZZ_D |
| 19787 | 4128U, // ZIPQ1_ZZZ_H |
| 19788 | 12384U, // ZIPQ1_ZZZ_S |
| 19789 | 8288U, // ZIPQ2_ZZZ_B |
| 19790 | 10336U, // ZIPQ2_ZZZ_D |
| 19791 | 4128U, // ZIPQ2_ZZZ_H |
| 19792 | 12384U, // ZIPQ2_ZZZ_S |
| 19793 | 184U, // ZIP_VG2_2ZZZ_B |
| 19794 | 0U, // ZIP_VG2_2ZZZ_D |
| 19795 | 4128U, // ZIP_VG2_2ZZZ_H |
| 19796 | 4320U, // ZIP_VG2_2ZZZ_Q |
| 19797 | 4208U, // ZIP_VG2_2ZZZ_S |
| 19798 | 1U, // ZIP_VG4_4Z4Z_B |
| 19799 | 1U, // ZIP_VG4_4Z4Z_D |
| 19800 | 1U, // ZIP_VG4_4Z4Z_H |
| 19801 | 0U, // ZIP_VG4_4Z4Z_Q |
| 19802 | 1U, // ZIP_VG4_4Z4Z_S |
| 19803 | }; |
| 19804 | |
| 19805 | // Emit the opcode for the instruction. |
| 19806 | uint64_t Bits = 0; |
| 19807 | Bits |= (uint64_t)OpInfo0[MI.getOpcode()] << 0; |
| 19808 | Bits |= (uint64_t)OpInfo1[MI.getOpcode()] << 32; |
| 19809 | if (Bits == 0) |
| 19810 | return {nullptr, Bits}; |
| 19811 | return {AsmStrs+(Bits & 16383)-1, Bits}; |
| 19812 | |
| 19813 | } |
| 19814 | /// printInstruction - This method is automatically generated by tablegen |
| 19815 | /// from the instruction set description. |
| 19816 | LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
| 19817 | void AArch64InstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| 19818 | O << "\t"; |
| 19819 | |
| 19820 | auto MnemonicInfo = getMnemonic(MI: *MI); |
| 19821 | |
| 19822 | O << MnemonicInfo.first; |
| 19823 | |
| 19824 | uint64_t Bits = MnemonicInfo.second; |
| 19825 | assert(Bits != 0 && "Cannot print this instruction."); |
| 19826 | |
| 19827 | // Fragment 0 encoded into 7 bits for 81 unique commands. |
| 19828 | switch ((Bits >> 14) & 127) { |
| 19829 | default: llvm_unreachable("Invalid command number."); |
| 19830 | case 0: |
| 19831 | // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
| 19832 | return; |
| 19833 | break; |
| 19834 | case 1: |
| 19835 | // TLSDESCCALL, ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADD... |
| 19836 | printOperand(MI, OpNo: 0, STI, O); |
| 19837 | break; |
| 19838 | case 2: |
| 19839 | // ABS_ZPmZ_B, ABS_ZPzZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADDQP... |
| 19840 | printSVERegOp<'b'>(MI, OpNum: 0, STI, O); |
| 19841 | break; |
| 19842 | case 3: |
| 19843 | // ABS_ZPmZ_D, ABS_ZPzZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADDQP_Z... |
| 19844 | printSVERegOp<'d'>(MI, OpNum: 0, STI, O); |
| 19845 | break; |
| 19846 | case 4: |
| 19847 | // ABS_ZPmZ_H, ABS_ZPzZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADDQP... |
| 19848 | printSVERegOp<'h'>(MI, OpNum: 0, STI, O); |
| 19849 | O << ", "; |
| 19850 | break; |
| 19851 | case 5: |
| 19852 | // ABS_ZPmZ_S, ABS_ZPzZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT... |
| 19853 | printSVERegOp<'s'>(MI, OpNum: 0, STI, O); |
| 19854 | break; |
| 19855 | case 6: |
| 19856 | // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| 19857 | printVRegOperand(MI, OpNo: 0, STI, O); |
| 19858 | break; |
| 19859 | case 7: |
| 19860 | // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, BFMOP4A_M2Z2Z_... |
| 19861 | printMatrixTile(MI, OpNum: 0, STI, O); |
| 19862 | O << ", "; |
| 19863 | break; |
| 19864 | case 8: |
| 19865 | // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| 19866 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 19867 | break; |
| 19868 | case 9: |
| 19869 | // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, AESDIMC_2ZZI_B, AESDIMC_4ZZI_B, AESD_2ZZ... |
| 19870 | printTypedVectorList<0,'b'>(MI, OpNum: 0, STI, O); |
| 19871 | O << ", "; |
| 19872 | break; |
| 19873 | case 10: |
| 19874 | // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D... |
| 19875 | printTypedVectorList<0,'d'>(MI, OpNum: 0, STI, O); |
| 19876 | O << ", "; |
| 19877 | break; |
| 19878 | case 11: |
| 19879 | // ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BF1CVTL_2ZZ_BtoH, BF1CVT_2ZZ_BtoH, BF2CV... |
| 19880 | printTypedVectorList<0,'h'>(MI, OpNum: 0, STI, O); |
| 19881 | O << ", "; |
| 19882 | break; |
| 19883 | case 12: |
| 19884 | // ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, FAMAX_2Z2Z_S, FAMAX_4Z4Z_S, FAMIN_2Z2Z_S... |
| 19885 | printTypedVectorList<0,'s'>(MI, OpNum: 0, STI, O); |
| 19886 | O << ", "; |
| 19887 | break; |
| 19888 | case 13: |
| 19889 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V... |
| 19890 | printMatrix<64>(MI, OpNum: 0, STI, O); |
| 19891 | O << '['; |
| 19892 | printOperand(MI, OpNo: 2, STI, O); |
| 19893 | O << ", "; |
| 19894 | break; |
| 19895 | case 14: |
| 19896 | // ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V... |
| 19897 | printMatrix<32>(MI, OpNum: 0, STI, O); |
| 19898 | O << '['; |
| 19899 | printOperand(MI, OpNo: 2, STI, O); |
| 19900 | O << ", "; |
| 19901 | break; |
| 19902 | case 15: |
| 19903 | // ANDV_VPZ_B, EORV_VPZ_B, ORV_VPZ_B, SMAXV_VPZ_B, SMINV_VPZ_B, UMAXV_VPZ... |
| 19904 | printZPRasFPR<8>(MI, OpNum: 0, STI, O); |
| 19905 | O << ", "; |
| 19906 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 19907 | O << ", "; |
| 19908 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 19909 | return; |
| 19910 | break; |
| 19911 | case 16: |
| 19912 | // ANDV_VPZ_D, EORV_VPZ_D, FADDA_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV... |
| 19913 | printZPRasFPR<64>(MI, OpNum: 0, STI, O); |
| 19914 | O << ", "; |
| 19915 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 19916 | O << ", "; |
| 19917 | break; |
| 19918 | case 17: |
| 19919 | // ANDV_VPZ_H, EORV_VPZ_H, FADDA_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV... |
| 19920 | printZPRasFPR<16>(MI, OpNum: 0, STI, O); |
| 19921 | O << ", "; |
| 19922 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 19923 | O << ", "; |
| 19924 | break; |
| 19925 | case 18: |
| 19926 | // ANDV_VPZ_S, EORV_VPZ_S, FADDA_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAXV... |
| 19927 | printZPRasFPR<32>(MI, OpNum: 0, STI, O); |
| 19928 | O << ", "; |
| 19929 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 19930 | O << ", "; |
| 19931 | break; |
| 19932 | case 19: |
| 19933 | // AUTDA, AUTDB, AUTDZA, AUTDZB, AUTIA, AUTIB, AUTIZA, AUTIZB, CASAB, CAS... |
| 19934 | printOperand(MI, OpNo: 1, STI, O); |
| 19935 | break; |
| 19936 | case 20: |
| 19937 | // AUTIASPPCi, AUTIBSPPCi, B, BL, RETAASPPCi, RETABSPPCi |
| 19938 | printAlignedLabel(MI, Address, OpNum: 0, STI, O); |
| 19939 | return; |
| 19940 | break; |
| 19941 | case 21: |
| 19942 | // BCcc, Bcc |
| 19943 | printCondCode(MI, OpNum: 0, STI, O); |
| 19944 | O << "\t"; |
| 19945 | printAlignedLabel(MI, Address, OpNum: 1, STI, O); |
| 19946 | return; |
| 19947 | break; |
| 19948 | case 22: |
| 19949 | // BFADD_VG2_M2Z_H, BFADD_VG4_M4Z_H, BFMLA_VG2_M2Z2Z, BFMLA_VG2_M2ZZ, BFM... |
| 19950 | printMatrix<16>(MI, OpNum: 0, STI, O); |
| 19951 | O << '['; |
| 19952 | printOperand(MI, OpNo: 2, STI, O); |
| 19953 | O << ", "; |
| 19954 | break; |
| 19955 | case 23: |
| 19956 | // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC |
| 19957 | printImmHex(MI, OpNo: 0, STI, O); |
| 19958 | return; |
| 19959 | break; |
| 19960 | case 24: |
| 19961 | // CASPALTX, CASPALX, CASPATX, CASPAX, CASPLTX, CASPLX, CASPTX, CASPX, RC... |
| 19962 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 1, STI, O); |
| 19963 | O << ", "; |
| 19964 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 2, STI, O); |
| 19965 | O << ", ["; |
| 19966 | printOperand(MI, OpNo: 3, STI, O); |
| 19967 | O << ']'; |
| 19968 | return; |
| 19969 | break; |
| 19970 | case 25: |
| 19971 | // CASPALW, CASPAW, CASPLW, CASPW |
| 19972 | printGPRSeqPairsClassOperand<32>(MI, OpNum: 1, STI, O); |
| 19973 | O << ", "; |
| 19974 | printGPRSeqPairsClassOperand<32>(MI, OpNum: 2, STI, O); |
| 19975 | O << ", ["; |
| 19976 | printOperand(MI, OpNo: 3, STI, O); |
| 19977 | O << ']'; |
| 19978 | return; |
| 19979 | break; |
| 19980 | case 26: |
| 19981 | // CPYE, CPYEN, CPYERN, CPYERT, CPYERTN, CPYERTRN, CPYERTWN, CPYET, CPYET... |
| 19982 | printOperand(MI, OpNo: 3, STI, O); |
| 19983 | O << "]!, ["; |
| 19984 | printOperand(MI, OpNo: 4, STI, O); |
| 19985 | O << "]!, "; |
| 19986 | printOperand(MI, OpNo: 5, STI, O); |
| 19987 | O << '!'; |
| 19988 | return; |
| 19989 | break; |
| 19990 | case 27: |
| 19991 | // DMB, DSB, ISB, TSB |
| 19992 | printBarrierOption(MI, OpNum: 0, STI, O); |
| 19993 | return; |
| 19994 | break; |
| 19995 | case 28: |
| 19996 | // DSBnXS |
| 19997 | printBarriernXSOption(MI, OpNum: 0, STI, O); |
| 19998 | return; |
| 19999 | break; |
| 20000 | case 29: |
| 20001 | // DUP_ZZI_Q, EXTRACT_ZPMXI_H_Q, EXTRACT_ZPMXI_V_Q, MOVAZ_ZMI_H_Q, MOVAZ_... |
| 20002 | printSVERegOp<'q'>(MI, OpNum: 0, STI, O); |
| 20003 | O << ", "; |
| 20004 | break; |
| 20005 | case 30: |
| 20006 | // GLD1Q, LD1D_Q, LD1D_Q_IMM, LD1W_Q, LD1W_Q_IMM, LD2Q, LD2Q_IMM, LD3Q, L... |
| 20007 | printTypedVectorList<0,'q'>(MI, OpNum: 0, STI, O); |
| 20008 | O << ", "; |
| 20009 | break; |
| 20010 | case 31: |
| 20011 | // HINT, TENTER |
| 20012 | printImm(MI, OpNo: 0, STI, O); |
| 20013 | break; |
| 20014 | case 32: |
| 20015 | // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| 20016 | printMatrixTileVector<0>(MI, OpNum: 0, STI, O); |
| 20017 | O << '['; |
| 20018 | break; |
| 20019 | case 33: |
| 20020 | // INSERT_MXIPZ_V_B, INSERT_MXIPZ_V_D, INSERT_MXIPZ_V_H, INSERT_MXIPZ_V_Q... |
| 20021 | printMatrixTileVector<1>(MI, OpNum: 0, STI, O); |
| 20022 | O << '['; |
| 20023 | break; |
| 20024 | case 34: |
| 20025 | // LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LDNT1B_2Z_STRIDED, LDNT1B_2Z_STR... |
| 20026 | printTypedVectorList<0, 'b'>(MI, OpNum: 0, STI, O); |
| 20027 | break; |
| 20028 | case 35: |
| 20029 | // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... |
| 20030 | printTypedVectorList<16, 'b'>(MI, OpNum: 0, STI, O); |
| 20031 | O << ", ["; |
| 20032 | printOperand(MI, OpNo: 1, STI, O); |
| 20033 | O << ']'; |
| 20034 | return; |
| 20035 | break; |
| 20036 | case 36: |
| 20037 | // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... |
| 20038 | printTypedVectorList<16, 'b'>(MI, OpNum: 1, STI, O); |
| 20039 | O << ", ["; |
| 20040 | printOperand(MI, OpNo: 2, STI, O); |
| 20041 | O << "], "; |
| 20042 | break; |
| 20043 | case 37: |
| 20044 | // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... |
| 20045 | printTypedVectorList<1, 'd'>(MI, OpNum: 0, STI, O); |
| 20046 | O << ", ["; |
| 20047 | printOperand(MI, OpNo: 1, STI, O); |
| 20048 | O << ']'; |
| 20049 | return; |
| 20050 | break; |
| 20051 | case 38: |
| 20052 | // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... |
| 20053 | printTypedVectorList<1, 'd'>(MI, OpNum: 1, STI, O); |
| 20054 | O << ", ["; |
| 20055 | printOperand(MI, OpNo: 2, STI, O); |
| 20056 | O << "], "; |
| 20057 | break; |
| 20058 | case 39: |
| 20059 | // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... |
| 20060 | printTypedVectorList<2, 'd'>(MI, OpNum: 0, STI, O); |
| 20061 | O << ", ["; |
| 20062 | printOperand(MI, OpNo: 1, STI, O); |
| 20063 | O << ']'; |
| 20064 | return; |
| 20065 | break; |
| 20066 | case 40: |
| 20067 | // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... |
| 20068 | printTypedVectorList<2, 'd'>(MI, OpNum: 1, STI, O); |
| 20069 | O << ", ["; |
| 20070 | printOperand(MI, OpNo: 2, STI, O); |
| 20071 | O << "], "; |
| 20072 | break; |
| 20073 | case 41: |
| 20074 | // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... |
| 20075 | printTypedVectorList<2, 's'>(MI, OpNum: 0, STI, O); |
| 20076 | O << ", ["; |
| 20077 | printOperand(MI, OpNo: 1, STI, O); |
| 20078 | O << ']'; |
| 20079 | return; |
| 20080 | break; |
| 20081 | case 42: |
| 20082 | // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... |
| 20083 | printTypedVectorList<2, 's'>(MI, OpNum: 1, STI, O); |
| 20084 | O << ", ["; |
| 20085 | printOperand(MI, OpNo: 2, STI, O); |
| 20086 | O << "], "; |
| 20087 | break; |
| 20088 | case 43: |
| 20089 | // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... |
| 20090 | printTypedVectorList<4, 'h'>(MI, OpNum: 0, STI, O); |
| 20091 | O << ", ["; |
| 20092 | printOperand(MI, OpNo: 1, STI, O); |
| 20093 | O << ']'; |
| 20094 | return; |
| 20095 | break; |
| 20096 | case 44: |
| 20097 | // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... |
| 20098 | printTypedVectorList<4, 'h'>(MI, OpNum: 1, STI, O); |
| 20099 | O << ", ["; |
| 20100 | printOperand(MI, OpNo: 2, STI, O); |
| 20101 | O << "], "; |
| 20102 | break; |
| 20103 | case 45: |
| 20104 | // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... |
| 20105 | printTypedVectorList<4, 's'>(MI, OpNum: 0, STI, O); |
| 20106 | O << ", ["; |
| 20107 | printOperand(MI, OpNo: 1, STI, O); |
| 20108 | O << ']'; |
| 20109 | return; |
| 20110 | break; |
| 20111 | case 46: |
| 20112 | // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... |
| 20113 | printTypedVectorList<4, 's'>(MI, OpNum: 1, STI, O); |
| 20114 | O << ", ["; |
| 20115 | printOperand(MI, OpNo: 2, STI, O); |
| 20116 | O << "], "; |
| 20117 | break; |
| 20118 | case 47: |
| 20119 | // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... |
| 20120 | printTypedVectorList<8, 'b'>(MI, OpNum: 0, STI, O); |
| 20121 | O << ", ["; |
| 20122 | printOperand(MI, OpNo: 1, STI, O); |
| 20123 | O << ']'; |
| 20124 | return; |
| 20125 | break; |
| 20126 | case 48: |
| 20127 | // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... |
| 20128 | printTypedVectorList<8, 'b'>(MI, OpNum: 1, STI, O); |
| 20129 | O << ", ["; |
| 20130 | printOperand(MI, OpNo: 2, STI, O); |
| 20131 | O << "], "; |
| 20132 | break; |
| 20133 | case 49: |
| 20134 | // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... |
| 20135 | printTypedVectorList<8, 'h'>(MI, OpNum: 0, STI, O); |
| 20136 | O << ", ["; |
| 20137 | printOperand(MI, OpNo: 1, STI, O); |
| 20138 | O << ']'; |
| 20139 | return; |
| 20140 | break; |
| 20141 | case 50: |
| 20142 | // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... |
| 20143 | printTypedVectorList<8, 'h'>(MI, OpNum: 1, STI, O); |
| 20144 | O << ", ["; |
| 20145 | printOperand(MI, OpNo: 2, STI, O); |
| 20146 | O << "], "; |
| 20147 | break; |
| 20148 | case 51: |
| 20149 | // LD1H_2Z_STRIDED, LD1H_2Z_STRIDED_IMM, LDNT1H_2Z_STRIDED, LDNT1H_2Z_STR... |
| 20150 | printTypedVectorList<0, 'h'>(MI, OpNum: 0, STI, O); |
| 20151 | break; |
| 20152 | case 52: |
| 20153 | // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... |
| 20154 | printTypedVectorList<0, 'h'>(MI, OpNum: 1, STI, O); |
| 20155 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20156 | O << ", ["; |
| 20157 | printOperand(MI, OpNo: 3, STI, O); |
| 20158 | break; |
| 20159 | case 53: |
| 20160 | // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST |
| 20161 | printTypedVectorList<0, 'h'>(MI, OpNum: 2, STI, O); |
| 20162 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 20163 | O << ", ["; |
| 20164 | printOperand(MI, OpNo: 4, STI, O); |
| 20165 | O << "], "; |
| 20166 | break; |
| 20167 | case 54: |
| 20168 | // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... |
| 20169 | printTypedVectorList<0, 's'>(MI, OpNum: 1, STI, O); |
| 20170 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20171 | O << ", ["; |
| 20172 | printOperand(MI, OpNo: 3, STI, O); |
| 20173 | break; |
| 20174 | case 55: |
| 20175 | // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST |
| 20176 | printTypedVectorList<0, 's'>(MI, OpNum: 2, STI, O); |
| 20177 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 20178 | O << ", ["; |
| 20179 | printOperand(MI, OpNo: 4, STI, O); |
| 20180 | O << "], "; |
| 20181 | break; |
| 20182 | case 56: |
| 20183 | // LD1i64, LD2i64, LD3i64, LD4i64, LDAP1, ST1i64_POST, ST2i64_POST, ST3i6... |
| 20184 | printTypedVectorList<0, 'd'>(MI, OpNum: 1, STI, O); |
| 20185 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20186 | O << ", ["; |
| 20187 | printOperand(MI, OpNo: 3, STI, O); |
| 20188 | break; |
| 20189 | case 57: |
| 20190 | // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST |
| 20191 | printTypedVectorList<0, 'd'>(MI, OpNum: 2, STI, O); |
| 20192 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 20193 | O << ", ["; |
| 20194 | printOperand(MI, OpNo: 4, STI, O); |
| 20195 | O << "], "; |
| 20196 | break; |
| 20197 | case 58: |
| 20198 | // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... |
| 20199 | printTypedVectorList<0, 'b'>(MI, OpNum: 1, STI, O); |
| 20200 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20201 | O << ", ["; |
| 20202 | printOperand(MI, OpNo: 3, STI, O); |
| 20203 | break; |
| 20204 | case 59: |
| 20205 | // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST |
| 20206 | printTypedVectorList<0, 'b'>(MI, OpNum: 2, STI, O); |
| 20207 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 20208 | O << ", ["; |
| 20209 | printOperand(MI, OpNo: 4, STI, O); |
| 20210 | O << "], "; |
| 20211 | break; |
| 20212 | case 60: |
| 20213 | // LD64B, ST64B |
| 20214 | printGPR64x8(MI, OpNum: 0, STI, O); |
| 20215 | O << ", ["; |
| 20216 | printOperand(MI, OpNo: 1, STI, O); |
| 20217 | O << ']'; |
| 20218 | return; |
| 20219 | break; |
| 20220 | case 61: |
| 20221 | // LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL... |
| 20222 | printOperand(MI, OpNo: 2, STI, O); |
| 20223 | break; |
| 20224 | case 62: |
| 20225 | // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PMOV_ZIP_B, PMOV_ZIP_D, PMOV_ZIP_H, PMOV... |
| 20226 | printSVERegOp<>(MI, OpNum: 0, STI, O); |
| 20227 | break; |
| 20228 | case 63: |
| 20229 | // LDR_ZA, STR_ZA |
| 20230 | printMatrix<0>(MI, OpNum: 0, STI, O); |
| 20231 | O << '['; |
| 20232 | printOperand(MI, OpNo: 1, STI, O); |
| 20233 | O << ", "; |
| 20234 | printMatrixIndex(MI, OpNum: 2, STI, O); |
| 20235 | O << "], ["; |
| 20236 | printOperand(MI, OpNo: 3, STI, O); |
| 20237 | O << ", "; |
| 20238 | printOperand(MI, OpNo: 4, STI, O); |
| 20239 | O << ", mul vl]"; |
| 20240 | return; |
| 20241 | break; |
| 20242 | case 64: |
| 20243 | // MRRS |
| 20244 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 0, STI, O); |
| 20245 | O << ", "; |
| 20246 | printMRSSystemRegister(MI, OpNum: 1, STI, O); |
| 20247 | return; |
| 20248 | break; |
| 20249 | case 65: |
| 20250 | // MSR, MSRR |
| 20251 | printMSRSystemRegister(MI, OpNum: 0, STI, O); |
| 20252 | O << ", "; |
| 20253 | break; |
| 20254 | case 66: |
| 20255 | // MSRpstateImm1, MSRpstateImm4 |
| 20256 | printSystemPStateField(MI, OpNum: 0, STI, O); |
| 20257 | O << ", "; |
| 20258 | printOperand(MI, OpNo: 1, STI, O); |
| 20259 | return; |
| 20260 | break; |
| 20261 | case 67: |
| 20262 | // MSRpstatesvcrImm1 |
| 20263 | printSVCROp(MI, OpNum: 0, STI, O); |
| 20264 | O << ", "; |
| 20265 | printOperand(MI, OpNo: 1, STI, O); |
| 20266 | return; |
| 20267 | break; |
| 20268 | case 68: |
| 20269 | // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... |
| 20270 | printPrefetchOp<true>(MI, OpNum: 0, STI, O); |
| 20271 | O << ", "; |
| 20272 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 20273 | O << ", ["; |
| 20274 | break; |
| 20275 | case 69: |
| 20276 | // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi |
| 20277 | printPrefetchOp(MI, OpNum: 0, STI, O); |
| 20278 | break; |
| 20279 | case 70: |
| 20280 | // PTRUE_C_B, WHILEGE_CXX_B, WHILEGT_CXX_B, WHILEHI_CXX_B, WHILEHS_CXX_B,... |
| 20281 | printPredicateAsCounter<8>(MI, OpNum: 0, STI, O); |
| 20282 | break; |
| 20283 | case 71: |
| 20284 | // PTRUE_C_D, WHILEGE_CXX_D, WHILEGT_CXX_D, WHILEHI_CXX_D, WHILEHS_CXX_D,... |
| 20285 | printPredicateAsCounter<64>(MI, OpNum: 0, STI, O); |
| 20286 | break; |
| 20287 | case 72: |
| 20288 | // PTRUE_C_H, WHILEGE_CXX_H, WHILEGT_CXX_H, WHILEHI_CXX_H, WHILEHS_CXX_H,... |
| 20289 | printPredicateAsCounter<16>(MI, OpNum: 0, STI, O); |
| 20290 | break; |
| 20291 | case 73: |
| 20292 | // PTRUE_C_S, WHILEGE_CXX_S, WHILEGT_CXX_S, WHILEHI_CXX_S, WHILEHS_CXX_S,... |
| 20293 | printPredicateAsCounter<32>(MI, OpNum: 0, STI, O); |
| 20294 | break; |
| 20295 | case 74: |
| 20296 | // RPRFM |
| 20297 | printRPRFMOperand(MI, OpNum: 0, STI, O); |
| 20298 | O << ", "; |
| 20299 | printOperand(MI, OpNo: 1, STI, O); |
| 20300 | O << ", ["; |
| 20301 | printOperand(MI, OpNo: 2, STI, O); |
| 20302 | O << ']'; |
| 20303 | return; |
| 20304 | break; |
| 20305 | case 75: |
| 20306 | // SHUH |
| 20307 | printCMHPriorityHintOp(MI, OpNum: 0, STI, O); |
| 20308 | return; |
| 20309 | break; |
| 20310 | case 76: |
| 20311 | // ST1i32, ST2i32, ST3i32, ST4i32 |
| 20312 | printTypedVectorList<0, 's'>(MI, OpNum: 0, STI, O); |
| 20313 | printVectorIndex(MI, OpNum: 1, STI, O); |
| 20314 | O << ", ["; |
| 20315 | printOperand(MI, OpNo: 2, STI, O); |
| 20316 | O << ']'; |
| 20317 | return; |
| 20318 | break; |
| 20319 | case 77: |
| 20320 | // ST1i64, ST2i64, ST3i64, ST4i64, STL1 |
| 20321 | printTypedVectorList<0, 'd'>(MI, OpNum: 0, STI, O); |
| 20322 | printVectorIndex(MI, OpNum: 1, STI, O); |
| 20323 | O << ", ["; |
| 20324 | printOperand(MI, OpNo: 2, STI, O); |
| 20325 | O << ']'; |
| 20326 | return; |
| 20327 | break; |
| 20328 | case 78: |
| 20329 | // STSHH |
| 20330 | printPHintOp(MI, OpNum: 0, STI, O); |
| 20331 | return; |
| 20332 | break; |
| 20333 | case 79: |
| 20334 | // TEXIT |
| 20335 | printTIndexHintOp(MI, OpNum: 0, STI, O); |
| 20336 | return; |
| 20337 | break; |
| 20338 | case 80: |
| 20339 | // ZERO_M |
| 20340 | printMatrixTileList(MI, OpNum: 0, STI, O); |
| 20341 | return; |
| 20342 | break; |
| 20343 | } |
| 20344 | |
| 20345 | |
| 20346 | // Fragment 1 encoded into 7 bits for 88 unique commands. |
| 20347 | switch ((Bits >> 21) & 127) { |
| 20348 | default: llvm_unreachable("Invalid command number."); |
| 20349 | case 0: |
| 20350 | // TLSDESCCALL, APAS, AUTDZA, AUTDZB, AUTIASPPCr, AUTIBSPPCr, AUTIZA, AUT... |
| 20351 | return; |
| 20352 | break; |
| 20353 | case 1: |
| 20354 | // ABSWr, ABSXr, ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABS_ZPzZ_B, ABS_ZPzZ... |
| 20355 | O << ", "; |
| 20356 | break; |
| 20357 | case 2: |
| 20358 | // ABS_ZPmZ_H, ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, BF... |
| 20359 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 20360 | break; |
| 20361 | case 3: |
| 20362 | // ABS_ZPzZ_H, ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPm... |
| 20363 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 20364 | break; |
| 20365 | case 4: |
| 20366 | // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDQV_VPZ_B, ADDv16i8, AESDrr, ... |
| 20367 | O << ".16b, "; |
| 20368 | break; |
| 20369 | case 5: |
| 20370 | // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BF16DOTlanev4bf16, BF... |
| 20371 | O << ".2s, "; |
| 20372 | break; |
| 20373 | case 6: |
| 20374 | // ABSv2i64, ADDPv2i64, ADDQV_VPZ_D, ADDv2i64, ANDQV_VPZ_D, CMEQv2i64, CM... |
| 20375 | O << ".2d, "; |
| 20376 | break; |
| 20377 | case 7: |
| 20378 | // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BFCVTN, BICv4i16, CLS... |
| 20379 | O << ".4h, "; |
| 20380 | break; |
| 20381 | case 8: |
| 20382 | // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDQV_VPZ_S, ADDv4i32, ANDQV_VP... |
| 20383 | O << ".4s, "; |
| 20384 | break; |
| 20385 | case 9: |
| 20386 | // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDQV_VPZ_H, ADDv8i16, ANDQV_VP... |
| 20387 | O << ".8h, "; |
| 20388 | break; |
| 20389 | case 10: |
| 20390 | // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... |
| 20391 | O << ".8b, "; |
| 20392 | break; |
| 20393 | case 11: |
| 20394 | // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,... |
| 20395 | printSVERegOp<'s'>(MI, OpNum: 1, STI, O); |
| 20396 | break; |
| 20397 | case 12: |
| 20398 | // ADDHNT_ZZZ_H, ANDV_VPZ_S, EORV_VPZ_S, FADDV_VPZ_S, FCLAMP_VG2_2Z2Z_S, ... |
| 20399 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 20400 | break; |
| 20401 | case 13: |
| 20402 | // ADDQP_ZZZ_H, ADDSUBP_ZZZ_H, ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_Z... |
| 20403 | printSVERegOp<'h'>(MI, OpNum: 1, STI, O); |
| 20404 | break; |
| 20405 | case 14: |
| 20406 | // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, AESDIMC_2ZZI_B, AESDIMC_4ZZI_B, AESD_2ZZ... |
| 20407 | printTypedVectorList<0,'b'>(MI, OpNum: 1, STI, O); |
| 20408 | break; |
| 20409 | case 15: |
| 20410 | // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D... |
| 20411 | printTypedVectorList<0,'d'>(MI, OpNum: 1, STI, O); |
| 20412 | break; |
| 20413 | case 16: |
| 20414 | // ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG2_2ZZ_H, B... |
| 20415 | printTypedVectorList<0,'h'>(MI, OpNum: 1, STI, O); |
| 20416 | break; |
| 20417 | case 17: |
| 20418 | // ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, BFCVTN_Z2Z_StoH, BFCVT_Z2Z_StoH, FAMAX_2... |
| 20419 | printTypedVectorList<0,'s'>(MI, OpNum: 1, STI, O); |
| 20420 | break; |
| 20421 | case 18: |
| 20422 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_... |
| 20423 | printMatrixIndex(MI, OpNum: 3, STI, O); |
| 20424 | break; |
| 20425 | case 19: |
| 20426 | // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... |
| 20427 | O << ", ["; |
| 20428 | break; |
| 20429 | case 20: |
| 20430 | // ANDV_VPZ_D, EORV_VPZ_D, FADDV_VPZ_D, FCLAMP_VG2_2Z2Z_D, FCLAMP_VG4_4Z4... |
| 20431 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 20432 | break; |
| 20433 | case 21: |
| 20434 | // ANDV_VPZ_H, BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA... |
| 20435 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 20436 | break; |
| 20437 | case 22: |
| 20438 | // BF1CVTLT_ZZ_BtoH, BF1CVTL_2ZZ_BtoH, BF1CVT_2ZZ_BtoH, BF1CVT_ZZ_BtoH, B... |
| 20439 | printSVERegOp<'b'>(MI, OpNum: 1, STI, O); |
| 20440 | break; |
| 20441 | case 23: |
| 20442 | // BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLAL_VG2_M2Z2Z_HtoS, BFMLAL_VG2_M... |
| 20443 | printImmRangeScale<2, 1>(MI, OpNum: 3, STI, O); |
| 20444 | break; |
| 20445 | case 24: |
| 20446 | // BFMOP4A_M2Z2Z_H, BFMOP4A_M2Z2Z_S, BFMOP4A_M2ZZ_H, BFMOP4A_M2ZZ_S, BFMO... |
| 20447 | printTypedVectorList<0,'h'>(MI, OpNum: 2, STI, O); |
| 20448 | O << ", "; |
| 20449 | break; |
| 20450 | case 25: |
| 20451 | // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... |
| 20452 | printSVEPattern(MI, OpNum: 2, STI, O); |
| 20453 | O << ", mul "; |
| 20454 | printOperand(MI, OpNo: 3, STI, O); |
| 20455 | return; |
| 20456 | break; |
| 20457 | case 26: |
| 20458 | // DUP_ZI_H |
| 20459 | printImm8OptLsl<int16_t>(MI, OpNum: 1, STI, O); |
| 20460 | return; |
| 20461 | break; |
| 20462 | case 27: |
| 20463 | // DUP_ZR_H, INDEX_RI_H, INDEX_RR_H, LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_... |
| 20464 | printOperand(MI, OpNo: 1, STI, O); |
| 20465 | break; |
| 20466 | case 28: |
| 20467 | // DUP_ZZI_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, UZP_VG2_2ZZ... |
| 20468 | printSVERegOp<'q'>(MI, OpNum: 1, STI, O); |
| 20469 | break; |
| 20470 | case 29: |
| 20471 | // FADDA_VPZ_D |
| 20472 | printZPRasFPR<64>(MI, OpNum: 2, STI, O); |
| 20473 | O << ", "; |
| 20474 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 20475 | return; |
| 20476 | break; |
| 20477 | case 30: |
| 20478 | // FADDA_VPZ_H, INSR_ZV_H |
| 20479 | printZPRasFPR<16>(MI, OpNum: 2, STI, O); |
| 20480 | break; |
| 20481 | case 31: |
| 20482 | // FADDA_VPZ_S |
| 20483 | printZPRasFPR<32>(MI, OpNum: 2, STI, O); |
| 20484 | O << ", "; |
| 20485 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 20486 | return; |
| 20487 | break; |
| 20488 | case 32: |
| 20489 | // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri |
| 20490 | O << ", #0.0"; |
| 20491 | return; |
| 20492 | break; |
| 20493 | case 33: |
| 20494 | // FDOT_ZZZI_BtoH, FDOT_ZZZ_BtoH, FMLALB_ZZZ, FMLALB_ZZZI, FMLALT_ZZZ, FM... |
| 20495 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 20496 | break; |
| 20497 | case 34: |
| 20498 | // FDUP_ZI_H |
| 20499 | printFPImmOperand(MI, OpNum: 1, STI, O); |
| 20500 | return; |
| 20501 | break; |
| 20502 | case 35: |
| 20503 | // FMLALL_MZZI_BtoS, FMLALL_MZZ_BtoS, FMLALL_VG2_M2Z2Z_BtoS, FMLALL_VG2_M... |
| 20504 | printImmRangeScale<4, 3>(MI, OpNum: 3, STI, O); |
| 20505 | break; |
| 20506 | case 36: |
| 20507 | // FMOP4A_M2Z2Z_BtoH, FMOP4A_M2Z2Z_BtoS, FMOP4A_M2ZZ_BtoH, FMOP4A_M2ZZ_Bt... |
| 20508 | printTypedVectorList<0,'b'>(MI, OpNum: 2, STI, O); |
| 20509 | O << ", "; |
| 20510 | break; |
| 20511 | case 37: |
| 20512 | // FMOP4A_M2Z2Z_D, FMOP4A_M2ZZ_D, FMOP4S_M2Z2Z_D, FMOP4S_M2ZZ_D |
| 20513 | printTypedVectorList<0,'d'>(MI, OpNum: 2, STI, O); |
| 20514 | O << ", "; |
| 20515 | break; |
| 20516 | case 38: |
| 20517 | // FMOP4A_M2Z2Z_S, FMOP4A_M2ZZ_S, FMOP4S_M2Z2Z_S, FMOP4S_M2ZZ_S, FTMOPA_M... |
| 20518 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 20519 | O << ", "; |
| 20520 | break; |
| 20521 | case 39: |
| 20522 | // FMOVXDHighr, INSvi64gpr, INSvi64lane |
| 20523 | O << ".d"; |
| 20524 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20525 | O << ", "; |
| 20526 | break; |
| 20527 | case 40: |
| 20528 | // INDEX_II_H, INDEX_IR_H |
| 20529 | printSImm<16>(MI, OpNo: 1, STI, O); |
| 20530 | O << ", "; |
| 20531 | break; |
| 20532 | case 41: |
| 20533 | // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| 20534 | printOperand(MI, OpNo: 2, STI, O); |
| 20535 | break; |
| 20536 | case 42: |
| 20537 | // INSvi16gpr, INSvi16lane |
| 20538 | O << ".h"; |
| 20539 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20540 | O << ", "; |
| 20541 | break; |
| 20542 | case 43: |
| 20543 | // INSvi32gpr, INSvi32lane |
| 20544 | O << ".s"; |
| 20545 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20546 | O << ", "; |
| 20547 | break; |
| 20548 | case 44: |
| 20549 | // INSvi8gpr, INSvi8lane |
| 20550 | O << ".b"; |
| 20551 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20552 | O << ", "; |
| 20553 | break; |
| 20554 | case 45: |
| 20555 | // LD1B_2Z, LD1B_2Z_IMM, LD1B_4Z, LD1B_4Z_IMM, LD1B_4Z_STRIDED, LD1B_4Z_S... |
| 20556 | printPredicateAsCounter<0>(MI, OpNum: 1, STI, O); |
| 20557 | break; |
| 20558 | case 46: |
| 20559 | // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... |
| 20560 | printPostIncOperand<64>(MI, OpNo: 3, STI, O); |
| 20561 | return; |
| 20562 | break; |
| 20563 | case 47: |
| 20564 | // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... |
| 20565 | printPostIncOperand<32>(MI, OpNo: 3, STI, O); |
| 20566 | return; |
| 20567 | break; |
| 20568 | case 48: |
| 20569 | // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... |
| 20570 | printPostIncOperand<16>(MI, OpNo: 3, STI, O); |
| 20571 | return; |
| 20572 | break; |
| 20573 | case 49: |
| 20574 | // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... |
| 20575 | printPostIncOperand<8>(MI, OpNo: 3, STI, O); |
| 20576 | return; |
| 20577 | break; |
| 20578 | case 50: |
| 20579 | // LD1Rv16b_POST, LD1Rv8b_POST |
| 20580 | printPostIncOperand<1>(MI, OpNo: 3, STI, O); |
| 20581 | return; |
| 20582 | break; |
| 20583 | case 51: |
| 20584 | // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... |
| 20585 | printPostIncOperand<4>(MI, OpNo: 3, STI, O); |
| 20586 | return; |
| 20587 | break; |
| 20588 | case 52: |
| 20589 | // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST |
| 20590 | printPostIncOperand<2>(MI, OpNo: 3, STI, O); |
| 20591 | return; |
| 20592 | break; |
| 20593 | case 53: |
| 20594 | // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... |
| 20595 | printPostIncOperand<48>(MI, OpNo: 3, STI, O); |
| 20596 | return; |
| 20597 | break; |
| 20598 | case 54: |
| 20599 | // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... |
| 20600 | printPostIncOperand<24>(MI, OpNo: 3, STI, O); |
| 20601 | return; |
| 20602 | break; |
| 20603 | case 55: |
| 20604 | // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... |
| 20605 | O << ']'; |
| 20606 | return; |
| 20607 | break; |
| 20608 | case 56: |
| 20609 | // LD1i16_POST, LD2i8_POST |
| 20610 | printPostIncOperand<2>(MI, OpNo: 5, STI, O); |
| 20611 | return; |
| 20612 | break; |
| 20613 | case 57: |
| 20614 | // LD1i32_POST, LD2i16_POST, LD4i8_POST |
| 20615 | printPostIncOperand<4>(MI, OpNo: 5, STI, O); |
| 20616 | return; |
| 20617 | break; |
| 20618 | case 58: |
| 20619 | // LD1i64_POST, LD2i32_POST, LD4i16_POST |
| 20620 | printPostIncOperand<8>(MI, OpNo: 5, STI, O); |
| 20621 | return; |
| 20622 | break; |
| 20623 | case 59: |
| 20624 | // LD1i8_POST |
| 20625 | printPostIncOperand<1>(MI, OpNo: 5, STI, O); |
| 20626 | return; |
| 20627 | break; |
| 20628 | case 60: |
| 20629 | // LD2i64_POST, LD4i32_POST |
| 20630 | printPostIncOperand<16>(MI, OpNo: 5, STI, O); |
| 20631 | return; |
| 20632 | break; |
| 20633 | case 61: |
| 20634 | // LD3Rv16b_POST, LD3Rv8b_POST |
| 20635 | printPostIncOperand<3>(MI, OpNo: 3, STI, O); |
| 20636 | return; |
| 20637 | break; |
| 20638 | case 62: |
| 20639 | // LD3Rv2s_POST, LD3Rv4s_POST |
| 20640 | printPostIncOperand<12>(MI, OpNo: 3, STI, O); |
| 20641 | return; |
| 20642 | break; |
| 20643 | case 63: |
| 20644 | // LD3Rv4h_POST, LD3Rv8h_POST |
| 20645 | printPostIncOperand<6>(MI, OpNo: 3, STI, O); |
| 20646 | return; |
| 20647 | break; |
| 20648 | case 64: |
| 20649 | // LD3i16_POST |
| 20650 | printPostIncOperand<6>(MI, OpNo: 5, STI, O); |
| 20651 | return; |
| 20652 | break; |
| 20653 | case 65: |
| 20654 | // LD3i32_POST |
| 20655 | printPostIncOperand<12>(MI, OpNo: 5, STI, O); |
| 20656 | return; |
| 20657 | break; |
| 20658 | case 66: |
| 20659 | // LD3i64_POST |
| 20660 | printPostIncOperand<24>(MI, OpNo: 5, STI, O); |
| 20661 | return; |
| 20662 | break; |
| 20663 | case 67: |
| 20664 | // LD3i8_POST |
| 20665 | printPostIncOperand<3>(MI, OpNo: 5, STI, O); |
| 20666 | return; |
| 20667 | break; |
| 20668 | case 68: |
| 20669 | // LD4i64_POST |
| 20670 | printPostIncOperand<32>(MI, OpNo: 5, STI, O); |
| 20671 | return; |
| 20672 | break; |
| 20673 | case 69: |
| 20674 | // MOPSSETGE, MOPSSETGEN, MOPSSETGET, MOPSSETGETN, SETE, SETEN, SETET, SE... |
| 20675 | O << "]!, "; |
| 20676 | printOperand(MI, OpNo: 3, STI, O); |
| 20677 | break; |
| 20678 | case 70: |
| 20679 | // MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_... |
| 20680 | printMatrixTileVector<0>(MI, OpNum: 2, STI, O); |
| 20681 | O << '['; |
| 20682 | printOperand(MI, OpNo: 3, STI, O); |
| 20683 | O << ", "; |
| 20684 | break; |
| 20685 | case 71: |
| 20686 | // MOVAZ_2ZMI_V_B, MOVAZ_2ZMI_V_D, MOVAZ_2ZMI_V_H, MOVAZ_2ZMI_V_S, MOVAZ_... |
| 20687 | printMatrixTileVector<1>(MI, OpNum: 2, STI, O); |
| 20688 | O << '['; |
| 20689 | printOperand(MI, OpNo: 3, STI, O); |
| 20690 | O << ", "; |
| 20691 | break; |
| 20692 | case 72: |
| 20693 | // MOVAZ_VG2_2ZMXI, MOVAZ_VG4_4ZMXI |
| 20694 | printMatrix<64>(MI, OpNum: 2, STI, O); |
| 20695 | O << '['; |
| 20696 | printOperand(MI, OpNo: 3, STI, O); |
| 20697 | O << ", "; |
| 20698 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 20699 | break; |
| 20700 | case 73: |
| 20701 | // MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZM... |
| 20702 | printMatrixTileVector<0>(MI, OpNum: 1, STI, O); |
| 20703 | O << '['; |
| 20704 | break; |
| 20705 | case 74: |
| 20706 | // MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q, MOVA_2ZMXI_V_B, MOVA_2ZMXI_V_D, MOVA_2ZM... |
| 20707 | printMatrixTileVector<1>(MI, OpNum: 1, STI, O); |
| 20708 | O << '['; |
| 20709 | break; |
| 20710 | case 75: |
| 20711 | // MOVA_VG2_2ZMXI, MOVA_VG4_4ZMXI |
| 20712 | printMatrix<64>(MI, OpNum: 1, STI, O); |
| 20713 | O << '['; |
| 20714 | printOperand(MI, OpNo: 2, STI, O); |
| 20715 | O << ", "; |
| 20716 | printMatrixIndex(MI, OpNum: 3, STI, O); |
| 20717 | break; |
| 20718 | case 76: |
| 20719 | // MOVT_TIX, MOVT_TIZ |
| 20720 | O << '['; |
| 20721 | break; |
| 20722 | case 77: |
| 20723 | // MSRR |
| 20724 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 1, STI, O); |
| 20725 | return; |
| 20726 | break; |
| 20727 | case 78: |
| 20728 | // PMOV_ZIP_B, PMOV_ZIP_D, PMOV_ZIP_H, PMOV_ZIP_S |
| 20729 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20730 | O << ", "; |
| 20731 | break; |
| 20732 | case 79: |
| 20733 | // PMULLB_ZZZ_Q, PMULLT_ZZZ_Q, PMULL_2ZZZ_Q, UZP_VG2_2ZZZ_D, ZIP_VG2_2ZZZ... |
| 20734 | printSVERegOp<'d'>(MI, OpNum: 1, STI, O); |
| 20735 | O << ", "; |
| 20736 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 20737 | return; |
| 20738 | break; |
| 20739 | case 80: |
| 20740 | // PMULLv1i64, PMULLv2i64 |
| 20741 | O << ".1q, "; |
| 20742 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 20743 | break; |
| 20744 | case 81: |
| 20745 | // PTRUES_H, PTRUE_H |
| 20746 | printSVEPattern(MI, OpNum: 1, STI, O); |
| 20747 | return; |
| 20748 | break; |
| 20749 | case 82: |
| 20750 | // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... |
| 20751 | O << ".1d, "; |
| 20752 | break; |
| 20753 | case 83: |
| 20754 | // ST1i16, ST1i8, ST2i16, ST2i8, ST3i16, ST3i8, ST4i16, ST4i8 |
| 20755 | printVectorIndex(MI, OpNum: 1, STI, O); |
| 20756 | O << ", ["; |
| 20757 | printOperand(MI, OpNo: 2, STI, O); |
| 20758 | O << ']'; |
| 20759 | return; |
| 20760 | break; |
| 20761 | case 84: |
| 20762 | // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... |
| 20763 | O << "], "; |
| 20764 | break; |
| 20765 | case 85: |
| 20766 | // STBFADD, STBFADDL, STBFMAX, STBFMAXL, STBFMAXNM, STBFMAXNML, STBFMIN, ... |
| 20767 | O << ", ["; |
| 20768 | printOperand(MI, OpNo: 1, STI, O); |
| 20769 | O << ']'; |
| 20770 | return; |
| 20771 | break; |
| 20772 | case 86: |
| 20773 | // UZP_VG4_4Z4Z_Q, ZIP_VG4_4Z4Z_Q |
| 20774 | printTypedVectorList<0,'q'>(MI, OpNum: 1, STI, O); |
| 20775 | return; |
| 20776 | break; |
| 20777 | case 87: |
| 20778 | // ZERO_T |
| 20779 | O << " }"; |
| 20780 | return; |
| 20781 | break; |
| 20782 | } |
| 20783 | |
| 20784 | |
| 20785 | // Fragment 2 encoded into 7 bits for 95 unique commands. |
| 20786 | switch ((Bits >> 28) & 127) { |
| 20787 | default: llvm_unreachable("Invalid command number."); |
| 20788 | case 0: |
| 20789 | // ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI,... |
| 20790 | printOperand(MI, OpNo: 1, STI, O); |
| 20791 | break; |
| 20792 | case 1: |
| 20793 | // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... |
| 20794 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 20795 | break; |
| 20796 | case 2: |
| 20797 | // ABS_ZPmZ_H, ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDP_ZPmZ_H, ADDVA_MPPZ_D, ADD... |
| 20798 | O << "/m, "; |
| 20799 | break; |
| 20800 | case 3: |
| 20801 | // ABS_ZPzZ_B, ABS_ZPzZ_D, ABS_ZPzZ_S, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPm... |
| 20802 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 20803 | break; |
| 20804 | case 4: |
| 20805 | // ABS_ZPzZ_H, BFCVTNT_ZPzZ_StoH, BFCVT_ZPzZ_StoH, CLS_ZPzZ_H, CLZ_ZPzZ_H... |
| 20806 | O << "/z, "; |
| 20807 | break; |
| 20808 | case 5: |
| 20809 | // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| 20810 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 20811 | break; |
| 20812 | case 6: |
| 20813 | // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z... |
| 20814 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 20815 | break; |
| 20816 | case 7: |
| 20817 | // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ... |
| 20818 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 20819 | break; |
| 20820 | case 8: |
| 20821 | // ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH... |
| 20822 | printSVERegOp<'h'>(MI, OpNum: 1, STI, O); |
| 20823 | break; |
| 20824 | case 9: |
| 20825 | // ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDQP_ZZZ_H, ADDSUBP_ZZZ_H, ADD_VG2_2ZZ_B,... |
| 20826 | O << ", "; |
| 20827 | break; |
| 20828 | case 10: |
| 20829 | // ADDHNB_ZZZ_S, ADDQP_ZZZ_D, ADDSUBP_ZZZ_D, ADD_ZI_D, ADD_ZZZ_CPA, ADD_Z... |
| 20830 | printSVERegOp<'d'>(MI, OpNum: 1, STI, O); |
| 20831 | break; |
| 20832 | case 11: |
| 20833 | // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT... |
| 20834 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 20835 | break; |
| 20836 | case 12: |
| 20837 | // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| 20838 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 20839 | break; |
| 20840 | case 13: |
| 20841 | // ADDQP_ZZZ_B, ADDSUBP_ZZZ_B, ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_... |
| 20842 | printSVERegOp<'b'>(MI, OpNum: 1, STI, O); |
| 20843 | break; |
| 20844 | case 14: |
| 20845 | // ADDQP_ZZZ_S, ADDSUBP_ZZZ_S, ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_... |
| 20846 | printSVERegOp<'s'>(MI, OpNum: 1, STI, O); |
| 20847 | break; |
| 20848 | case 15: |
| 20849 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_... |
| 20850 | O << ", vgx2], "; |
| 20851 | break; |
| 20852 | case 16: |
| 20853 | // ADD_VG4_M4Z4Z_D, ADD_VG4_M4Z4Z_S, ADD_VG4_M4ZZ_D, ADD_VG4_M4ZZ_S, ADD_... |
| 20854 | O << ", vgx4], "; |
| 20855 | break; |
| 20856 | case 17: |
| 20857 | // ADR, ADRP |
| 20858 | printAdrAdrpLabel(MI, Address, OpNum: 1, STI, O); |
| 20859 | return; |
| 20860 | break; |
| 20861 | case 18: |
| 20862 | // ANDV_VPZ_D, ANDV_VPZ_H, ANDV_VPZ_S, BF1CVTLT_ZZ_BtoH, BF1CVTL_2ZZ_BtoH... |
| 20863 | return; |
| 20864 | break; |
| 20865 | case 19: |
| 20866 | // AUTDA, AUTDB, AUTIA, AUTIB, BFMWri, BFMXri, CASAB, CASAH, CASALB, CASA... |
| 20867 | printOperand(MI, OpNo: 2, STI, O); |
| 20868 | break; |
| 20869 | case 20: |
| 20870 | // BFCVTN_Z2Z_HtoB, BFCVT_Z2Z_HtoB, FCVTN_Z2Z_HtoB, FCVTZSN_Z2Z_HtoB, FCV... |
| 20871 | printTypedVectorList<0,'h'>(MI, OpNum: 1, STI, O); |
| 20872 | break; |
| 20873 | case 21: |
| 20874 | // BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLSL_MZZI_HtoS, BFMLSL_MZZ_HtoS, ... |
| 20875 | O << "], "; |
| 20876 | break; |
| 20877 | case 22: |
| 20878 | // BFMOP4A_M2Z2Z_H, BFMOP4A_M2Z2Z_S, BFMOP4S_M2Z2Z_H, BFMOP4S_M2Z2Z_S, FM... |
| 20879 | printTypedVectorList<0,'h'>(MI, OpNum: 3, STI, O); |
| 20880 | return; |
| 20881 | break; |
| 20882 | case 23: |
| 20883 | // BFMOP4A_M2ZZ_H, BFMOP4A_M2ZZ_S, BFMOP4S_M2ZZ_H, BFMOP4S_M2ZZ_S, BFTMOP... |
| 20884 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 20885 | break; |
| 20886 | case 24: |
| 20887 | // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... |
| 20888 | printImm(MI, OpNo: 2, STI, O); |
| 20889 | printShifter(MI, OpNum: 3, STI, O); |
| 20890 | return; |
| 20891 | break; |
| 20892 | case 25: |
| 20893 | // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... |
| 20894 | printAlignedLabel(MI, Address, OpNum: 1, STI, O); |
| 20895 | return; |
| 20896 | break; |
| 20897 | case 26: |
| 20898 | // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, FDOT_ZZ... |
| 20899 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 20900 | O << ", "; |
| 20901 | break; |
| 20902 | case 27: |
| 20903 | // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... |
| 20904 | printSVEPattern(MI, OpNum: 1, STI, O); |
| 20905 | break; |
| 20906 | case 28: |
| 20907 | // CNTP_XCI_B |
| 20908 | printPredicateAsCounter<8>(MI, OpNum: 1, STI, O); |
| 20909 | O << ", "; |
| 20910 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 20911 | return; |
| 20912 | break; |
| 20913 | case 29: |
| 20914 | // CNTP_XCI_D |
| 20915 | printPredicateAsCounter<64>(MI, OpNum: 1, STI, O); |
| 20916 | O << ", "; |
| 20917 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 20918 | return; |
| 20919 | break; |
| 20920 | case 30: |
| 20921 | // CNTP_XCI_H |
| 20922 | printPredicateAsCounter<16>(MI, OpNum: 1, STI, O); |
| 20923 | O << ", "; |
| 20924 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 20925 | return; |
| 20926 | break; |
| 20927 | case 31: |
| 20928 | // CNTP_XCI_S |
| 20929 | printPredicateAsCounter<32>(MI, OpNum: 1, STI, O); |
| 20930 | O << ", "; |
| 20931 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 20932 | return; |
| 20933 | break; |
| 20934 | case 32: |
| 20935 | // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... |
| 20936 | printSVEPattern(MI, OpNum: 2, STI, O); |
| 20937 | O << ", mul "; |
| 20938 | printOperand(MI, OpNo: 3, STI, O); |
| 20939 | return; |
| 20940 | break; |
| 20941 | case 33: |
| 20942 | // DUPM_ZI |
| 20943 | printLogicalImm<int64_t>(MI, OpNum: 1, STI, O); |
| 20944 | return; |
| 20945 | break; |
| 20946 | case 34: |
| 20947 | // DUPQ_ZZI_H, DUP_ZZI_H, DUP_ZZI_Q, PEXT_2PCI_B, PEXT_2PCI_D, PEXT_2PCI_... |
| 20948 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 20949 | return; |
| 20950 | break; |
| 20951 | case 35: |
| 20952 | // DUP_ZI_B |
| 20953 | printImm8OptLsl<int8_t>(MI, OpNum: 1, STI, O); |
| 20954 | return; |
| 20955 | break; |
| 20956 | case 36: |
| 20957 | // DUP_ZI_D |
| 20958 | printImm8OptLsl<int64_t>(MI, OpNum: 1, STI, O); |
| 20959 | return; |
| 20960 | break; |
| 20961 | case 37: |
| 20962 | // DUP_ZI_S |
| 20963 | printImm8OptLsl<int32_t>(MI, OpNum: 1, STI, O); |
| 20964 | return; |
| 20965 | break; |
| 20966 | case 38: |
| 20967 | // EXT_ZZI_B, LUTI2_ZZZI_B, LUTI4_ZZZI_B, LUTI6_Z2ZZ, TBLQ_ZZZ_B, TBL_ZZZ... |
| 20968 | printTypedVectorList<0,'b'>(MI, OpNum: 1, STI, O); |
| 20969 | O << ", "; |
| 20970 | break; |
| 20971 | case 39: |
| 20972 | // FCVTNB_Z2Z_StoB, FCVTN_Z4Z_StoB, FCVT_Z4Z_StoB, SQCVTN_Z4Z_StoB, SQCVT... |
| 20973 | printTypedVectorList<0,'s'>(MI, OpNum: 1, STI, O); |
| 20974 | break; |
| 20975 | case 40: |
| 20976 | // FCVTNT_Z2Z_StoB |
| 20977 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 20978 | return; |
| 20979 | break; |
| 20980 | case 41: |
| 20981 | // FCVTZSN_Z2Z_DtoS, FCVTZUN_Z2Z_DtoS, TBLQ_ZZZ_D, TBL_ZZZZ_D, TBL_ZZZ_D |
| 20982 | printTypedVectorList<0,'d'>(MI, OpNum: 1, STI, O); |
| 20983 | break; |
| 20984 | case 42: |
| 20985 | // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... |
| 20986 | printFPImmOperand(MI, OpNum: 1, STI, O); |
| 20987 | return; |
| 20988 | break; |
| 20989 | case 43: |
| 20990 | // FMLALL_VG2_M2ZZ_BtoS, SMLALL_VG2_M2ZZ_BtoS, SMLALL_VG2_M2ZZ_HtoD, SMLS... |
| 20991 | O << ", vgx2], "; |
| 20992 | break; |
| 20993 | case 44: |
| 20994 | // FMLALL_VG4_M4ZZ_BtoS, SMLALL_VG4_M4ZZ_BtoS, SMLALL_VG4_M4ZZ_HtoD, SMLS... |
| 20995 | O << ", vgx4], "; |
| 20996 | break; |
| 20997 | case 45: |
| 20998 | // FMOP4A_M2Z2Z_BtoH, FMOP4A_M2Z2Z_BtoS, SMOP4A_M2Z2Z_BToS, SMOP4S_M2Z2Z_... |
| 20999 | printTypedVectorList<0,'b'>(MI, OpNum: 3, STI, O); |
| 21000 | return; |
| 21001 | break; |
| 21002 | case 46: |
| 21003 | // FMOP4A_M2Z2Z_D, FMOP4S_M2Z2Z_D |
| 21004 | printTypedVectorList<0,'d'>(MI, OpNum: 3, STI, O); |
| 21005 | return; |
| 21006 | break; |
| 21007 | case 47: |
| 21008 | // FMOP4A_M2Z2Z_S, FMOP4S_M2Z2Z_S |
| 21009 | printTypedVectorList<0,'s'>(MI, OpNum: 3, STI, O); |
| 21010 | return; |
| 21011 | break; |
| 21012 | case 48: |
| 21013 | // FMOP4A_M2ZZ_BtoH, FMOP4A_M2ZZ_BtoS, FTMOPA_M2ZZZI_BtoH, FTMOPA_M2ZZZI_... |
| 21014 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 21015 | break; |
| 21016 | case 49: |
| 21017 | // FMOP4A_M2ZZ_D, FMOP4S_M2ZZ_D, PMOV_ZIP_D |
| 21018 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 21019 | return; |
| 21020 | break; |
| 21021 | case 50: |
| 21022 | // FMOP4A_M2ZZ_S, FMOP4S_M2ZZ_S, FTMOPA_M2ZZZI_StoS, PMOV_ZIP_S |
| 21023 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 21024 | break; |
| 21025 | case 51: |
| 21026 | // GLD1B_D, GLD1B_D_IMM, GLD1B_D_SXTW, GLD1B_D_UXTW, GLD1B_S_IMM, GLD1B_S... |
| 21027 | O << "/z, ["; |
| 21028 | break; |
| 21029 | case 52: |
| 21030 | // INDEX_II_B, INDEX_IR_B |
| 21031 | printSImm<8>(MI, OpNo: 1, STI, O); |
| 21032 | O << ", "; |
| 21033 | break; |
| 21034 | case 53: |
| 21035 | // INDEX_II_H |
| 21036 | printSImm<16>(MI, OpNo: 2, STI, O); |
| 21037 | return; |
| 21038 | break; |
| 21039 | case 54: |
| 21040 | // INSR_ZV_B |
| 21041 | printZPRasFPR<8>(MI, OpNum: 2, STI, O); |
| 21042 | return; |
| 21043 | break; |
| 21044 | case 55: |
| 21045 | // INSR_ZV_D |
| 21046 | printZPRasFPR<64>(MI, OpNum: 2, STI, O); |
| 21047 | return; |
| 21048 | break; |
| 21049 | case 56: |
| 21050 | // INSR_ZV_S |
| 21051 | printZPRasFPR<32>(MI, OpNum: 2, STI, O); |
| 21052 | return; |
| 21053 | break; |
| 21054 | case 57: |
| 21055 | // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr, LDCLRP, LDCLRPA, LDCLRP... |
| 21056 | printOperand(MI, OpNo: 3, STI, O); |
| 21057 | break; |
| 21058 | case 58: |
| 21059 | // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane |
| 21060 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 21061 | break; |
| 21062 | case 59: |
| 21063 | // LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED, LD1H_2Z_STRIDED... |
| 21064 | printPredicateAsCounter<0>(MI, OpNum: 1, STI, O); |
| 21065 | break; |
| 21066 | case 60: |
| 21067 | // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... |
| 21068 | printOperand(MI, OpNo: 0, STI, O); |
| 21069 | O << ", ["; |
| 21070 | printOperand(MI, OpNo: 2, STI, O); |
| 21071 | O << ']'; |
| 21072 | return; |
| 21073 | break; |
| 21074 | case 61: |
| 21075 | // LUT2_B, LUT4_B, TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two,... |
| 21076 | printTypedVectorList<16, 'b'>(MI, OpNum: 1, STI, O); |
| 21077 | O << ", "; |
| 21078 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 21079 | break; |
| 21080 | case 62: |
| 21081 | // LUT2_H, LUT4_H |
| 21082 | printTypedVectorList<8, 'h'>(MI, OpNum: 1, STI, O); |
| 21083 | O << ", "; |
| 21084 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 21085 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 21086 | return; |
| 21087 | break; |
| 21088 | case 63: |
| 21089 | // MOPSSETGE, MOPSSETGEN, MOPSSETGET, MOPSSETGETN, SETE, SETEN, SETET, SE... |
| 21090 | O << "!, "; |
| 21091 | printOperand(MI, OpNo: 4, STI, O); |
| 21092 | return; |
| 21093 | break; |
| 21094 | case 64: |
| 21095 | // MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_... |
| 21096 | printImmRangeScale<2, 1>(MI, OpNum: 4, STI, O); |
| 21097 | O << ']'; |
| 21098 | return; |
| 21099 | break; |
| 21100 | case 65: |
| 21101 | // MOVAZ_4ZMI_H_B, MOVAZ_4ZMI_H_D, MOVAZ_4ZMI_H_H, MOVAZ_4ZMI_H_S, MOVAZ_... |
| 21102 | printImmRangeScale<4, 3>(MI, OpNum: 4, STI, O); |
| 21103 | O << ']'; |
| 21104 | return; |
| 21105 | break; |
| 21106 | case 66: |
| 21107 | // MOVAZ_VG2_2ZMXI, MOVA_VG2_2ZMXI, ZERO_MXI_VG2_2Z, ZERO_MXI_VG2_4Z, ZER... |
| 21108 | O << ", vgx2]"; |
| 21109 | return; |
| 21110 | break; |
| 21111 | case 67: |
| 21112 | // MOVAZ_VG4_4ZMXI, MOVA_VG4_4ZMXI, ZERO_MXI_VG4_2Z, ZERO_MXI_VG4_4Z, ZER... |
| 21113 | O << ", vgx4]"; |
| 21114 | return; |
| 21115 | break; |
| 21116 | case 68: |
| 21117 | // MOVAZ_ZMI_H_B, MOVAZ_ZMI_H_D, MOVAZ_ZMI_H_S |
| 21118 | printMatrixTileVector<0>(MI, OpNum: 1, STI, O); |
| 21119 | O << '['; |
| 21120 | printOperand(MI, OpNo: 3, STI, O); |
| 21121 | O << ", "; |
| 21122 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 21123 | O << ']'; |
| 21124 | return; |
| 21125 | break; |
| 21126 | case 69: |
| 21127 | // MOVAZ_ZMI_V_B, MOVAZ_ZMI_V_D, MOVAZ_ZMI_V_S |
| 21128 | printMatrixTileVector<1>(MI, OpNum: 1, STI, O); |
| 21129 | O << '['; |
| 21130 | printOperand(MI, OpNo: 3, STI, O); |
| 21131 | O << ", "; |
| 21132 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 21133 | O << ']'; |
| 21134 | return; |
| 21135 | break; |
| 21136 | case 70: |
| 21137 | // MOVID, MOVIv2d_ns |
| 21138 | printSIMDType10Operand(MI, OpNum: 1, STI, O); |
| 21139 | return; |
| 21140 | break; |
| 21141 | case 71: |
| 21142 | // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... |
| 21143 | printImm(MI, OpNo: 1, STI, O); |
| 21144 | break; |
| 21145 | case 72: |
| 21146 | // MOVT_TIX |
| 21147 | printMatrixIndex<8>(MI, OpNum: 1, STI, O); |
| 21148 | O << "], "; |
| 21149 | printOperand(MI, OpNo: 2, STI, O); |
| 21150 | return; |
| 21151 | break; |
| 21152 | case 73: |
| 21153 | // MOVT_TIZ |
| 21154 | printMatrixIndex(MI, OpNum: 1, STI, O); |
| 21155 | O << ", mul vl], "; |
| 21156 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 21157 | return; |
| 21158 | break; |
| 21159 | case 74: |
| 21160 | // MRS |
| 21161 | printMRSSystemRegister(MI, OpNum: 1, STI, O); |
| 21162 | return; |
| 21163 | break; |
| 21164 | case 75: |
| 21165 | // PMULLv1i64 |
| 21166 | O << ".1d, "; |
| 21167 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 21168 | O << ".1d"; |
| 21169 | return; |
| 21170 | break; |
| 21171 | case 76: |
| 21172 | // PMULLv2i64 |
| 21173 | O << ".2d, "; |
| 21174 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 21175 | O << ".2d"; |
| 21176 | return; |
| 21177 | break; |
| 21178 | case 77: |
| 21179 | // SETGOE, SETGOEN, SETGOET, SETGOETN, SETGOM, SETGOMN, SETGOMT, SETGOMTN... |
| 21180 | O << '!'; |
| 21181 | return; |
| 21182 | break; |
| 21183 | case 78: |
| 21184 | // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... |
| 21185 | printGPR64as32(MI, OpNum: 1, STI, O); |
| 21186 | O << ", "; |
| 21187 | printSVEPattern(MI, OpNum: 2, STI, O); |
| 21188 | O << ", mul "; |
| 21189 | printOperand(MI, OpNo: 3, STI, O); |
| 21190 | return; |
| 21191 | break; |
| 21192 | case 79: |
| 21193 | // SST1B_D, SST1B_D_IMM, SST1B_D_SXTW, SST1B_D_UXTW, SST1B_S_IMM, SST1B_S... |
| 21194 | O << ", ["; |
| 21195 | break; |
| 21196 | case 80: |
| 21197 | // ST1i16_POST, ST2i8_POST |
| 21198 | printPostIncOperand<2>(MI, OpNo: 4, STI, O); |
| 21199 | return; |
| 21200 | break; |
| 21201 | case 81: |
| 21202 | // ST1i32_POST, ST2i16_POST, ST4i8_POST |
| 21203 | printPostIncOperand<4>(MI, OpNo: 4, STI, O); |
| 21204 | return; |
| 21205 | break; |
| 21206 | case 82: |
| 21207 | // ST1i64_POST, ST2i32_POST, ST4i16_POST |
| 21208 | printPostIncOperand<8>(MI, OpNo: 4, STI, O); |
| 21209 | return; |
| 21210 | break; |
| 21211 | case 83: |
| 21212 | // ST1i8_POST |
| 21213 | printPostIncOperand<1>(MI, OpNo: 4, STI, O); |
| 21214 | return; |
| 21215 | break; |
| 21216 | case 84: |
| 21217 | // ST2i64_POST, ST4i32_POST |
| 21218 | printPostIncOperand<16>(MI, OpNo: 4, STI, O); |
| 21219 | return; |
| 21220 | break; |
| 21221 | case 85: |
| 21222 | // ST3i16_POST |
| 21223 | printPostIncOperand<6>(MI, OpNo: 4, STI, O); |
| 21224 | return; |
| 21225 | break; |
| 21226 | case 86: |
| 21227 | // ST3i32_POST |
| 21228 | printPostIncOperand<12>(MI, OpNo: 4, STI, O); |
| 21229 | return; |
| 21230 | break; |
| 21231 | case 87: |
| 21232 | // ST3i64_POST |
| 21233 | printPostIncOperand<24>(MI, OpNo: 4, STI, O); |
| 21234 | return; |
| 21235 | break; |
| 21236 | case 88: |
| 21237 | // ST3i8_POST |
| 21238 | printPostIncOperand<3>(MI, OpNo: 4, STI, O); |
| 21239 | return; |
| 21240 | break; |
| 21241 | case 89: |
| 21242 | // ST4i64_POST |
| 21243 | printPostIncOperand<32>(MI, OpNo: 4, STI, O); |
| 21244 | return; |
| 21245 | break; |
| 21246 | case 90: |
| 21247 | // ST64BV, ST64BV0 |
| 21248 | printGPR64x8(MI, OpNum: 1, STI, O); |
| 21249 | O << ", ["; |
| 21250 | printOperand(MI, OpNo: 2, STI, O); |
| 21251 | O << ']'; |
| 21252 | return; |
| 21253 | break; |
| 21254 | case 91: |
| 21255 | // SYSPxt, SYSPxt_XZR, SYSxt |
| 21256 | printSysCROperand(MI, OpNo: 1, STI, O); |
| 21257 | O << ", "; |
| 21258 | printSysCROperand(MI, OpNo: 2, STI, O); |
| 21259 | O << ", "; |
| 21260 | printOperand(MI, OpNo: 3, STI, O); |
| 21261 | O << ", "; |
| 21262 | break; |
| 21263 | case 92: |
| 21264 | // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... |
| 21265 | printTypedVectorList<16, 'b'>(MI, OpNum: 2, STI, O); |
| 21266 | O << ", "; |
| 21267 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 21268 | break; |
| 21269 | case 93: |
| 21270 | // TENTER |
| 21271 | printTIndexHintOp(MI, OpNum: 1, STI, O); |
| 21272 | return; |
| 21273 | break; |
| 21274 | case 94: |
| 21275 | // ZERO_MXI_2Z, ZERO_MXI_4Z |
| 21276 | O << ']'; |
| 21277 | return; |
| 21278 | break; |
| 21279 | } |
| 21280 | |
| 21281 | |
| 21282 | // Fragment 3 encoded into 8 bits for 130 unique commands. |
| 21283 | switch ((Bits >> 35) & 255) { |
| 21284 | default: llvm_unreachable("Invalid command number."); |
| 21285 | case 0: |
| 21286 | // ABSWr, ABSXr, ABSv1i64, AESIMC_ZZ_B, AESMC_ZZ_B, AUTDA, AUTDB, AUTIA, ... |
| 21287 | return; |
| 21288 | break; |
| 21289 | case 1: |
| 21290 | // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPm... |
| 21291 | O << "/m, "; |
| 21292 | break; |
| 21293 | case 2: |
| 21294 | // ABS_ZPmZ_H, BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA... |
| 21295 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 21296 | break; |
| 21297 | case 3: |
| 21298 | // ABS_ZPzZ_B, ABS_ZPzZ_D, ABS_ZPzZ_S, ANDS_PPzPP, AND_PPzPP, BICS_PPzPP,... |
| 21299 | O << "/z, "; |
| 21300 | break; |
| 21301 | case 4: |
| 21302 | // ABS_ZPzZ_H, ADDP_ZPmZ_H, ADDQP_ZZZ_H, ADDSUBP_ZZZ_H, ADD_VG2_2ZZ_H, AD... |
| 21303 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 21304 | break; |
| 21305 | case 5: |
| 21306 | // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, BF1CVTL2, BF2... |
| 21307 | O << ".16b"; |
| 21308 | return; |
| 21309 | break; |
| 21310 | case 6: |
| 21311 | // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... |
| 21312 | O << ".2s"; |
| 21313 | return; |
| 21314 | break; |
| 21315 | case 7: |
| 21316 | // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... |
| 21317 | O << ".2d"; |
| 21318 | return; |
| 21319 | break; |
| 21320 | case 8: |
| 21321 | // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT... |
| 21322 | O << ".4h"; |
| 21323 | return; |
| 21324 | break; |
| 21325 | case 9: |
| 21326 | // ABSv4i32, ADDVv4i32v, BFCVTN, BFCVTN2, CLSv4i32, CLZv4i32, FABSv4f32, ... |
| 21327 | O << ".4s"; |
| 21328 | return; |
| 21329 | break; |
| 21330 | case 10: |
| 21331 | // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT... |
| 21332 | O << ".8h"; |
| 21333 | return; |
| 21334 | break; |
| 21335 | case 11: |
| 21336 | // ABSv8i8, ADDVv8i8v, BF1CVTL, BF2CVTL, CLSv8i8, CLZv8i8, CNTv8i8, F1CVT... |
| 21337 | O << ".8b"; |
| 21338 | return; |
| 21339 | break; |
| 21340 | case 12: |
| 21341 | // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... |
| 21342 | O << ", "; |
| 21343 | break; |
| 21344 | case 13: |
| 21345 | // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, BFMOPA_MPPZZ, ... |
| 21346 | printSVERegOp<>(MI, OpNum: 3, STI, O); |
| 21347 | O << "/m, "; |
| 21348 | break; |
| 21349 | case 14: |
| 21350 | // ADDHNB_ZZZ_H, ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, BFCVT_ZPzZ_StoH, FCVT_ZPzZ... |
| 21351 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 21352 | break; |
| 21353 | case 15: |
| 21354 | // ADDHNT_ZZZ_H, BFCVTNT_ZPmZ, BFCVTNT_ZPzZ_StoH, BFCVT_ZPmZ, FCLAMP_VG2_... |
| 21355 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 21356 | return; |
| 21357 | break; |
| 21358 | case 16: |
| 21359 | // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... |
| 21360 | O << ".2d, "; |
| 21361 | break; |
| 21362 | case 17: |
| 21363 | // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... |
| 21364 | O << ".4s, "; |
| 21365 | break; |
| 21366 | case 18: |
| 21367 | // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BF16DOTlanev8b... |
| 21368 | O << ".8h, "; |
| 21369 | break; |
| 21370 | case 19: |
| 21371 | // ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL... |
| 21372 | O << ".16b, "; |
| 21373 | break; |
| 21374 | case 20: |
| 21375 | // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... |
| 21376 | O << ".2s, "; |
| 21377 | break; |
| 21378 | case 21: |
| 21379 | // ADDPv4i16, ADDv4i16, BF16DOTlanev4bf16, BFDOTv4bf16, CMEQv4i16, CMGEv4... |
| 21380 | O << ".4h, "; |
| 21381 | break; |
| 21382 | case 22: |
| 21383 | // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... |
| 21384 | O << ".8b, "; |
| 21385 | break; |
| 21386 | case 23: |
| 21387 | // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H... |
| 21388 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 21389 | return; |
| 21390 | break; |
| 21391 | case 24: |
| 21392 | // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, ASR_WIDE_ZZZ_H, FCVT_ZPzZ_DtoH, FMAXNM_V... |
| 21393 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 21394 | break; |
| 21395 | case 25: |
| 21396 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V... |
| 21397 | printTypedVectorList<0,'d'>(MI, OpNum: 4, STI, O); |
| 21398 | break; |
| 21399 | case 26: |
| 21400 | // ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V... |
| 21401 | printTypedVectorList<0,'s'>(MI, OpNum: 4, STI, O); |
| 21402 | break; |
| 21403 | case 27: |
| 21404 | // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... |
| 21405 | printImm8OptLsl<uint16_t>(MI, OpNum: 2, STI, O); |
| 21406 | return; |
| 21407 | break; |
| 21408 | case 28: |
| 21409 | // AESDIMC_2ZZI_B, AESDIMC_4ZZI_B, AESD_2ZZI_B, AESD_4ZZI_B, AESEMC_2ZZI_... |
| 21410 | printSVERegOp<'q'>(MI, OpNum: 2, STI, O); |
| 21411 | break; |
| 21412 | case 29: |
| 21413 | // ASR_ZZI_H, GLD1B_D, GLD1B_D_SXTW, GLD1B_D_UXTW, GLD1B_S_SXTW, GLD1B_S_... |
| 21414 | printOperand(MI, OpNo: 2, STI, O); |
| 21415 | break; |
| 21416 | case 30: |
| 21417 | // BFADD_VG2_M2Z_H, BFADD_VG4_M4Z_H, BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG2_M2ZZ... |
| 21418 | printTypedVectorList<0,'h'>(MI, OpNum: 4, STI, O); |
| 21419 | break; |
| 21420 | case 31: |
| 21421 | // BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG4_4Z2Z_H, BFMAX_VG2_2Z2Z_H, BFMAX_VG4_4Z... |
| 21422 | printTypedVectorList<0,'h'>(MI, OpNum: 2, STI, O); |
| 21423 | break; |
| 21424 | case 32: |
| 21425 | // BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLSL_MZZI_HtoS, BFMLSL_MZZ_HtoS, ... |
| 21426 | printSVERegOp<'h'>(MI, OpNum: 4, STI, O); |
| 21427 | O << ", "; |
| 21428 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 21429 | break; |
| 21430 | case 33: |
| 21431 | // BFMOP4A_MZ2Z_H, BFMOP4A_MZ2Z_S, BFMOP4S_MZ2Z_H, BFMOP4S_MZ2Z_S, FMOP4A... |
| 21432 | printTypedVectorList<0,'h'>(MI, OpNum: 3, STI, O); |
| 21433 | return; |
| 21434 | break; |
| 21435 | case 34: |
| 21436 | // CASAB, CASAH, CASALB, CASALH, CASALTX, CASALW, CASALX, CASATX, CASAW, ... |
| 21437 | O << ", ["; |
| 21438 | break; |
| 21439 | case 35: |
| 21440 | // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, FDOT_ZZ... |
| 21441 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 21442 | break; |
| 21443 | case 36: |
| 21444 | // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz |
| 21445 | O << ".16b, #0"; |
| 21446 | return; |
| 21447 | break; |
| 21448 | case 37: |
| 21449 | // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz |
| 21450 | O << ", #0"; |
| 21451 | return; |
| 21452 | break; |
| 21453 | case 38: |
| 21454 | // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz |
| 21455 | O << ".2s, #0"; |
| 21456 | return; |
| 21457 | break; |
| 21458 | case 39: |
| 21459 | // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz |
| 21460 | O << ".2d, #0"; |
| 21461 | return; |
| 21462 | break; |
| 21463 | case 40: |
| 21464 | // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz |
| 21465 | O << ".4h, #0"; |
| 21466 | return; |
| 21467 | break; |
| 21468 | case 41: |
| 21469 | // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz |
| 21470 | O << ".4s, #0"; |
| 21471 | return; |
| 21472 | break; |
| 21473 | case 42: |
| 21474 | // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz |
| 21475 | O << ".8h, #0"; |
| 21476 | return; |
| 21477 | break; |
| 21478 | case 43: |
| 21479 | // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz |
| 21480 | O << ".8b, #0"; |
| 21481 | return; |
| 21482 | break; |
| 21483 | case 44: |
| 21484 | // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI |
| 21485 | O << ", mul "; |
| 21486 | printOperand(MI, OpNo: 2, STI, O); |
| 21487 | return; |
| 21488 | break; |
| 21489 | case 45: |
| 21490 | // CPY_ZPmI_H |
| 21491 | printImm8OptLsl<int16_t>(MI, OpNum: 3, STI, O); |
| 21492 | return; |
| 21493 | break; |
| 21494 | case 46: |
| 21495 | // CPY_ZPmR_H, CPY_ZPmV_H, PRFB_D_PZI, PRFB_PRI, PRFB_S_PZI, PRFD_PRI, PR... |
| 21496 | printOperand(MI, OpNo: 3, STI, O); |
| 21497 | break; |
| 21498 | case 47: |
| 21499 | // CPY_ZPzI_H |
| 21500 | printImm8OptLsl<int16_t>(MI, OpNum: 2, STI, O); |
| 21501 | return; |
| 21502 | break; |
| 21503 | case 48: |
| 21504 | // DUPQ_ZZI_B, DUPQ_ZZI_D, DUPQ_ZZI_S, DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S, P... |
| 21505 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 21506 | return; |
| 21507 | break; |
| 21508 | case 49: |
| 21509 | // DUPi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... |
| 21510 | O << ".h"; |
| 21511 | break; |
| 21512 | case 50: |
| 21513 | // DUPi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, SMOVvi3... |
| 21514 | O << ".s"; |
| 21515 | break; |
| 21516 | case 51: |
| 21517 | // DUPi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64, UMOVvi64_idx... |
| 21518 | O << ".d"; |
| 21519 | break; |
| 21520 | case 52: |
| 21521 | // DUPi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to32... |
| 21522 | O << ".b"; |
| 21523 | break; |
| 21524 | case 53: |
| 21525 | // EXTRACT_ZPMXI_H_H, EXTRACT_ZPMXI_H_Q |
| 21526 | printMatrixTileVector<0>(MI, OpNum: 3, STI, O); |
| 21527 | O << '['; |
| 21528 | printOperand(MI, OpNo: 4, STI, O); |
| 21529 | O << ", "; |
| 21530 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 21531 | O << ']'; |
| 21532 | return; |
| 21533 | break; |
| 21534 | case 54: |
| 21535 | // EXTRACT_ZPMXI_V_H, EXTRACT_ZPMXI_V_Q |
| 21536 | printMatrixTileVector<1>(MI, OpNum: 3, STI, O); |
| 21537 | O << '['; |
| 21538 | printOperand(MI, OpNo: 4, STI, O); |
| 21539 | O << ", "; |
| 21540 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 21541 | O << ']'; |
| 21542 | return; |
| 21543 | break; |
| 21544 | case 55: |
| 21545 | // EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H |
| 21546 | printImm(MI, OpNo: 2, STI, O); |
| 21547 | return; |
| 21548 | break; |
| 21549 | case 56: |
| 21550 | // FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p |
| 21551 | O << ".2h"; |
| 21552 | return; |
| 21553 | break; |
| 21554 | case 57: |
| 21555 | // FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D, FAMIN_4Z4Z_D, FMAXNM_VG2_2Z2... |
| 21556 | printTypedVectorList<0,'d'>(MI, OpNum: 2, STI, O); |
| 21557 | break; |
| 21558 | case 58: |
| 21559 | // FAMAX_2Z2Z_S, FAMAX_4Z4Z_S, FAMIN_2Z2Z_S, FAMIN_4Z4Z_S, FMAXNM_VG2_2Z2... |
| 21560 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 21561 | break; |
| 21562 | case 59: |
| 21563 | // FCLAMP_VG2_2Z2Z_D, FCLAMP_VG4_4Z4Z_D, FCVT_ZPmZ_DtoH, FMOP4A_MZZ_D, FM... |
| 21564 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 21565 | return; |
| 21566 | break; |
| 21567 | case 60: |
| 21568 | // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ... |
| 21569 | O << ", #0.0"; |
| 21570 | return; |
| 21571 | break; |
| 21572 | case 61: |
| 21573 | // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz |
| 21574 | O << ".2s, #0.0"; |
| 21575 | return; |
| 21576 | break; |
| 21577 | case 62: |
| 21578 | // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz |
| 21579 | O << ".2d, #0.0"; |
| 21580 | return; |
| 21581 | break; |
| 21582 | case 63: |
| 21583 | // FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz |
| 21584 | O << ".4h, #0.0"; |
| 21585 | return; |
| 21586 | break; |
| 21587 | case 64: |
| 21588 | // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz |
| 21589 | O << ".4s, #0.0"; |
| 21590 | return; |
| 21591 | break; |
| 21592 | case 65: |
| 21593 | // FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz |
| 21594 | O << ".8h, #0.0"; |
| 21595 | return; |
| 21596 | break; |
| 21597 | case 66: |
| 21598 | // FCPY_ZPmI_H |
| 21599 | printFPImmOperand(MI, OpNum: 3, STI, O); |
| 21600 | return; |
| 21601 | break; |
| 21602 | case 67: |
| 21603 | // FDOT_VG2_M2Z2Z_BtoH, FDOT_VG2_M2Z2Z_BtoS, FDOT_VG2_M2ZZI_BtoH, FDOT_VG... |
| 21604 | printTypedVectorList<0,'b'>(MI, OpNum: 4, STI, O); |
| 21605 | O << ", "; |
| 21606 | break; |
| 21607 | case 68: |
| 21608 | // FMLAL2lanev4f16, FMLAL2v4f16, FMLALlanev4f16, FMLALv4f16, FMLSL2lanev4... |
| 21609 | O << ".2h, "; |
| 21610 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 21611 | break; |
| 21612 | case 69: |
| 21613 | // FMLALL_MZZI_BtoS, FMLALL_MZZ_BtoS, FMLAL_MZZI_BtoH, FMLAL_VG2_MZZ_BtoH... |
| 21614 | printSVERegOp<'b'>(MI, OpNum: 4, STI, O); |
| 21615 | O << ", "; |
| 21616 | printSVERegOp<'b'>(MI, OpNum: 5, STI, O); |
| 21617 | break; |
| 21618 | case 70: |
| 21619 | // FMOP4A_MZ2Z_BtoH, FMOP4A_MZ2Z_BtoS, SMOP4A_MZ2Z_BToS, SMOP4S_MZ2Z_BToS... |
| 21620 | printTypedVectorList<0,'b'>(MI, OpNum: 3, STI, O); |
| 21621 | return; |
| 21622 | break; |
| 21623 | case 71: |
| 21624 | // FMOP4A_MZ2Z_D, FMOP4S_MZ2Z_D |
| 21625 | printTypedVectorList<0,'d'>(MI, OpNum: 3, STI, O); |
| 21626 | return; |
| 21627 | break; |
| 21628 | case 72: |
| 21629 | // FMOP4A_MZ2Z_S, FMOP4S_MZ2Z_S |
| 21630 | printTypedVectorList<0,'s'>(MI, OpNum: 3, STI, O); |
| 21631 | return; |
| 21632 | break; |
| 21633 | case 73: |
| 21634 | // GCSSTR, GCSSTTR, LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, ... |
| 21635 | O << ']'; |
| 21636 | return; |
| 21637 | break; |
| 21638 | case 74: |
| 21639 | // INDEX_II_B |
| 21640 | printSImm<8>(MI, OpNo: 2, STI, O); |
| 21641 | return; |
| 21642 | break; |
| 21643 | case 75: |
| 21644 | // INDEX_RI_H |
| 21645 | printSImm<16>(MI, OpNo: 2, STI, O); |
| 21646 | return; |
| 21647 | break; |
| 21648 | case 76: |
| 21649 | // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| 21650 | printMatrixIndex(MI, OpNum: 3, STI, O); |
| 21651 | O << "], "; |
| 21652 | printSVERegOp<>(MI, OpNum: 4, STI, O); |
| 21653 | O << "/m, "; |
| 21654 | break; |
| 21655 | case 77: |
| 21656 | // LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED, LD1H_2Z_STRIDED... |
| 21657 | O << "/z, ["; |
| 21658 | printOperand(MI, OpNo: 2, STI, O); |
| 21659 | O << ", "; |
| 21660 | break; |
| 21661 | case 78: |
| 21662 | // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... |
| 21663 | printMatrixIndex(MI, OpNum: 2, STI, O); |
| 21664 | O << "]}, "; |
| 21665 | printSVERegOp<>(MI, OpNum: 3, STI, O); |
| 21666 | break; |
| 21667 | case 79: |
| 21668 | // LDAPRWpost |
| 21669 | O << "], #4"; |
| 21670 | return; |
| 21671 | break; |
| 21672 | case 80: |
| 21673 | // LDAPRXpost |
| 21674 | O << "], #8"; |
| 21675 | return; |
| 21676 | break; |
| 21677 | case 81: |
| 21678 | // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... |
| 21679 | O << "], "; |
| 21680 | break; |
| 21681 | case 82: |
| 21682 | // LUT2_B, LUT4_B |
| 21683 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 21684 | return; |
| 21685 | break; |
| 21686 | case 83: |
| 21687 | // LUTI2_2ZTZI_B, LUTI2_2ZTZI_H, LUTI2_2ZTZI_S, LUTI2_4ZTZI_B, LUTI2_4ZTZ... |
| 21688 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 21689 | break; |
| 21690 | case 84: |
| 21691 | // LUTI4_4ZZT2Z, LUTI4_S_4ZZT2Z, LUTI6_4Z2Z2ZI, LUTI6_4ZT3Z, LUTI6_S_4Z2Z... |
| 21692 | printTypedVectorList<0,0>(MI, OpNum: 2, STI, O); |
| 21693 | break; |
| 21694 | case 85: |
| 21695 | // MOVA_MXI2Z_H_B, MOVA_MXI2Z_H_D, MOVA_MXI2Z_H_H, MOVA_MXI2Z_H_S, MOVA_M... |
| 21696 | printImmRangeScale<2, 1>(MI, OpNum: 3, STI, O); |
| 21697 | O << "], "; |
| 21698 | break; |
| 21699 | case 86: |
| 21700 | // MOVA_MXI4Z_H_B, MOVA_MXI4Z_H_D, MOVA_MXI4Z_H_H, MOVA_MXI4Z_H_S, MOVA_M... |
| 21701 | printImmRangeScale<4, 3>(MI, OpNum: 3, STI, O); |
| 21702 | O << "], "; |
| 21703 | break; |
| 21704 | case 87: |
| 21705 | // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... |
| 21706 | printShifter(MI, OpNum: 2, STI, O); |
| 21707 | return; |
| 21708 | break; |
| 21709 | case 88: |
| 21710 | // MOVT_XTI |
| 21711 | O << '['; |
| 21712 | printMatrixIndex<8>(MI, OpNum: 2, STI, O); |
| 21713 | O << ']'; |
| 21714 | return; |
| 21715 | break; |
| 21716 | case 89: |
| 21717 | // PRFB_D_SCALED |
| 21718 | printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 21719 | O << ']'; |
| 21720 | return; |
| 21721 | break; |
| 21722 | case 90: |
| 21723 | // PRFB_D_SXTW_SCALED |
| 21724 | printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21725 | O << ']'; |
| 21726 | return; |
| 21727 | break; |
| 21728 | case 91: |
| 21729 | // PRFB_D_UXTW_SCALED |
| 21730 | printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21731 | O << ']'; |
| 21732 | return; |
| 21733 | break; |
| 21734 | case 92: |
| 21735 | // PRFB_PRR |
| 21736 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21737 | O << ']'; |
| 21738 | return; |
| 21739 | break; |
| 21740 | case 93: |
| 21741 | // PRFB_S_SXTW_SCALED |
| 21742 | printRegWithShiftExtend<true, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21743 | O << ']'; |
| 21744 | return; |
| 21745 | break; |
| 21746 | case 94: |
| 21747 | // PRFB_S_UXTW_SCALED |
| 21748 | printRegWithShiftExtend<false, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21749 | O << ']'; |
| 21750 | return; |
| 21751 | break; |
| 21752 | case 95: |
| 21753 | // PRFD_D_PZI, PRFD_S_PZI |
| 21754 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 21755 | O << ']'; |
| 21756 | return; |
| 21757 | break; |
| 21758 | case 96: |
| 21759 | // PRFD_D_SCALED |
| 21760 | printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 21761 | O << ']'; |
| 21762 | return; |
| 21763 | break; |
| 21764 | case 97: |
| 21765 | // PRFD_D_SXTW_SCALED |
| 21766 | printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21767 | O << ']'; |
| 21768 | return; |
| 21769 | break; |
| 21770 | case 98: |
| 21771 | // PRFD_D_UXTW_SCALED |
| 21772 | printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21773 | O << ']'; |
| 21774 | return; |
| 21775 | break; |
| 21776 | case 99: |
| 21777 | // PRFD_PRR |
| 21778 | printRegWithShiftExtend<false, 64, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21779 | O << ']'; |
| 21780 | return; |
| 21781 | break; |
| 21782 | case 100: |
| 21783 | // PRFD_S_SXTW_SCALED |
| 21784 | printRegWithShiftExtend<true, 64, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21785 | O << ']'; |
| 21786 | return; |
| 21787 | break; |
| 21788 | case 101: |
| 21789 | // PRFD_S_UXTW_SCALED |
| 21790 | printRegWithShiftExtend<false, 64, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21791 | O << ']'; |
| 21792 | return; |
| 21793 | break; |
| 21794 | case 102: |
| 21795 | // PRFH_D_PZI, PRFH_S_PZI |
| 21796 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 21797 | O << ']'; |
| 21798 | return; |
| 21799 | break; |
| 21800 | case 103: |
| 21801 | // PRFH_D_SCALED |
| 21802 | printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 21803 | O << ']'; |
| 21804 | return; |
| 21805 | break; |
| 21806 | case 104: |
| 21807 | // PRFH_D_SXTW_SCALED |
| 21808 | printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21809 | O << ']'; |
| 21810 | return; |
| 21811 | break; |
| 21812 | case 105: |
| 21813 | // PRFH_D_UXTW_SCALED |
| 21814 | printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21815 | O << ']'; |
| 21816 | return; |
| 21817 | break; |
| 21818 | case 106: |
| 21819 | // PRFH_PRR |
| 21820 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21821 | O << ']'; |
| 21822 | return; |
| 21823 | break; |
| 21824 | case 107: |
| 21825 | // PRFH_S_SXTW_SCALED |
| 21826 | printRegWithShiftExtend<true, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21827 | O << ']'; |
| 21828 | return; |
| 21829 | break; |
| 21830 | case 108: |
| 21831 | // PRFH_S_UXTW_SCALED |
| 21832 | printRegWithShiftExtend<false, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21833 | O << ']'; |
| 21834 | return; |
| 21835 | break; |
| 21836 | case 109: |
| 21837 | // PRFW_D_PZI, PRFW_S_PZI |
| 21838 | printImmScale<4>(MI, OpNum: 3, STI, O); |
| 21839 | O << ']'; |
| 21840 | return; |
| 21841 | break; |
| 21842 | case 110: |
| 21843 | // PRFW_D_SCALED |
| 21844 | printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 21845 | O << ']'; |
| 21846 | return; |
| 21847 | break; |
| 21848 | case 111: |
| 21849 | // PRFW_D_SXTW_SCALED |
| 21850 | printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21851 | O << ']'; |
| 21852 | return; |
| 21853 | break; |
| 21854 | case 112: |
| 21855 | // PRFW_D_UXTW_SCALED |
| 21856 | printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 21857 | O << ']'; |
| 21858 | return; |
| 21859 | break; |
| 21860 | case 113: |
| 21861 | // PRFW_PRR |
| 21862 | printRegWithShiftExtend<false, 32, 'x', 0>(MI, OpNum: 3, STI, O); |
| 21863 | O << ']'; |
| 21864 | return; |
| 21865 | break; |
| 21866 | case 114: |
| 21867 | // PRFW_S_SXTW_SCALED |
| 21868 | printRegWithShiftExtend<true, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21869 | O << ']'; |
| 21870 | return; |
| 21871 | break; |
| 21872 | case 115: |
| 21873 | // PRFW_S_UXTW_SCALED |
| 21874 | printRegWithShiftExtend<false, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 21875 | O << ']'; |
| 21876 | return; |
| 21877 | break; |
| 21878 | case 116: |
| 21879 | // RDFFRS_PPz, RDFFR_PPz |
| 21880 | O << "/z"; |
| 21881 | return; |
| 21882 | break; |
| 21883 | case 117: |
| 21884 | // REVD_ZPmZ |
| 21885 | printSVERegOp<'q'>(MI, OpNum: 3, STI, O); |
| 21886 | return; |
| 21887 | break; |
| 21888 | case 118: |
| 21889 | // SEL_VG2_2ZC2Z2Z_B, SEL_VG4_4ZC4Z4Z_B, SMAX_VG2_2Z2Z_B, SMAX_VG4_4Z4Z_B... |
| 21890 | printTypedVectorList<0,'b'>(MI, OpNum: 2, STI, O); |
| 21891 | break; |
| 21892 | case 119: |
| 21893 | // SHLLv16i8 |
| 21894 | O << ".16b, #8"; |
| 21895 | return; |
| 21896 | break; |
| 21897 | case 120: |
| 21898 | // SHLLv2i32 |
| 21899 | O << ".2s, #32"; |
| 21900 | return; |
| 21901 | break; |
| 21902 | case 121: |
| 21903 | // SHLLv4i16 |
| 21904 | O << ".4h, #16"; |
| 21905 | return; |
| 21906 | break; |
| 21907 | case 122: |
| 21908 | // SHLLv4i32 |
| 21909 | O << ".4s, #32"; |
| 21910 | return; |
| 21911 | break; |
| 21912 | case 123: |
| 21913 | // SHLLv8i16 |
| 21914 | O << ".8h, #16"; |
| 21915 | return; |
| 21916 | break; |
| 21917 | case 124: |
| 21918 | // SHLLv8i8 |
| 21919 | O << ".8b, #8"; |
| 21920 | return; |
| 21921 | break; |
| 21922 | case 125: |
| 21923 | // STLRWpre |
| 21924 | O << ", #-4]!"; |
| 21925 | return; |
| 21926 | break; |
| 21927 | case 126: |
| 21928 | // STLRXpre |
| 21929 | O << ", #-8]!"; |
| 21930 | return; |
| 21931 | break; |
| 21932 | case 127: |
| 21933 | // SYSPxt |
| 21934 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 4, STI, O); |
| 21935 | return; |
| 21936 | break; |
| 21937 | case 128: |
| 21938 | // SYSPxt_XZR |
| 21939 | printSyspXzrPair(MI, OpNum: 4, STI, O); |
| 21940 | return; |
| 21941 | break; |
| 21942 | case 129: |
| 21943 | // SYSxt |
| 21944 | printOperand(MI, OpNo: 4, STI, O); |
| 21945 | return; |
| 21946 | break; |
| 21947 | } |
| 21948 | |
| 21949 | |
| 21950 | // Fragment 4 encoded into 7 bits for 99 unique commands. |
| 21951 | switch ((Bits >> 43) & 127) { |
| 21952 | default: llvm_unreachable("Invalid command number."); |
| 21953 | case 0: |
| 21954 | // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, CLZ_ZPmZ_B, CNOT_ZPmZ_B,... |
| 21955 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 21956 | break; |
| 21957 | case 1: |
| 21958 | // ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CLS_ZPmZ_D, CLZ_ZP... |
| 21959 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 21960 | break; |
| 21961 | case 2: |
| 21962 | // ABS_ZPmZ_H, ABS_ZPzZ_H, ADDHNB_ZZZ_H, ADDQP_ZZZ_H, ADDSUBP_ZZZ_H, ADD_... |
| 21963 | return; |
| 21964 | break; |
| 21965 | case 3: |
| 21966 | // ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, CLS_ZPmZ_S, CLZ_ZPmZ_S, CMLA_ZZZ... |
| 21967 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 21968 | break; |
| 21969 | case 4: |
| 21970 | // ABS_ZPzZ_B, ADDP_ZPmZ_B, ADDQP_ZZZ_B, ADDQV_VPZ_B, ADDSUBP_ZZZ_B, ADD_... |
| 21971 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 21972 | break; |
| 21973 | case 5: |
| 21974 | // ABS_ZPzZ_D, ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADDQP_ZZZ_D, ADDQV_VPZ_D, ADDSU... |
| 21975 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 21976 | break; |
| 21977 | case 6: |
| 21978 | // ABS_ZPzZ_S, ADDP_ZPmZ_S, ADDQP_ZZZ_S, ADDQV_VPZ_S, ADDSUBP_ZZZ_S, ADD_... |
| 21979 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 21980 | break; |
| 21981 | case 7: |
| 21982 | // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDPT_shift, ADDSPL_XXI, ADDS... |
| 21983 | printOperand(MI, OpNo: 2, STI, O); |
| 21984 | break; |
| 21985 | case 8: |
| 21986 | // ADDG, ST2Gi, STGi, STZ2Gi, STZGi, SUBG |
| 21987 | printImmScale<16>(MI, OpNum: 2, STI, O); |
| 21988 | break; |
| 21989 | case 9: |
| 21990 | // ADDHA_MPPZ_D, ADDVA_MPPZ_D, FMOPA_MPPZZ_D, FMOPS_MPPZZ_D |
| 21991 | printSVERegOp<'d'>(MI, OpNum: 4, STI, O); |
| 21992 | break; |
| 21993 | case 10: |
| 21994 | // ADDHA_MPPZ_S, ADDVA_MPPZ_S, BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_... |
| 21995 | printSVERegOp<'s'>(MI, OpNum: 4, STI, O); |
| 21996 | break; |
| 21997 | case 11: |
| 21998 | // ADDHNB_ZZZ_B, ADDQV_VPZ_H, ANDQV_VPZ_H, CNTP_XPP_H, EORQV_VPZ_H, FADDQ... |
| 21999 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 22000 | break; |
| 22001 | case 12: |
| 22002 | // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT... |
| 22003 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 22004 | break; |
| 22005 | case 13: |
| 22006 | // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... |
| 22007 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 22008 | break; |
| 22009 | case 14: |
| 22010 | // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BF16DOTlanev4bf1... |
| 22011 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 22012 | break; |
| 22013 | case 15: |
| 22014 | // ADDP_ZPmZ_H, ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2... |
| 22015 | O << ", "; |
| 22016 | break; |
| 22017 | case 16: |
| 22018 | // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri |
| 22019 | printAddSubImm(MI, OpNum: 2, STI, O); |
| 22020 | return; |
| 22021 | break; |
| 22022 | case 17: |
| 22023 | // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... |
| 22024 | printShiftedRegister(MI, OpNum: 2, STI, O); |
| 22025 | return; |
| 22026 | break; |
| 22027 | case 18: |
| 22028 | // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx |
| 22029 | printExtendedRegister(MI, OpNum: 2, STI, O); |
| 22030 | return; |
| 22031 | break; |
| 22032 | case 19: |
| 22033 | // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... |
| 22034 | printImm8OptLsl<uint8_t>(MI, OpNum: 2, STI, O); |
| 22035 | return; |
| 22036 | break; |
| 22037 | case 20: |
| 22038 | // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... |
| 22039 | printImm8OptLsl<uint64_t>(MI, OpNum: 2, STI, O); |
| 22040 | return; |
| 22041 | break; |
| 22042 | case 21: |
| 22043 | // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... |
| 22044 | printImm8OptLsl<uint32_t>(MI, OpNum: 2, STI, O); |
| 22045 | return; |
| 22046 | break; |
| 22047 | case 22: |
| 22048 | // ADR_LSL_ZZZ_D_0 |
| 22049 | printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 22050 | O << ']'; |
| 22051 | return; |
| 22052 | break; |
| 22053 | case 23: |
| 22054 | // ADR_LSL_ZZZ_D_1 |
| 22055 | printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 22056 | O << ']'; |
| 22057 | return; |
| 22058 | break; |
| 22059 | case 24: |
| 22060 | // ADR_LSL_ZZZ_D_2 |
| 22061 | printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 22062 | O << ']'; |
| 22063 | return; |
| 22064 | break; |
| 22065 | case 25: |
| 22066 | // ADR_LSL_ZZZ_D_3 |
| 22067 | printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 22068 | O << ']'; |
| 22069 | return; |
| 22070 | break; |
| 22071 | case 26: |
| 22072 | // ADR_LSL_ZZZ_S_0 |
| 22073 | printRegWithShiftExtend<false, 8, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 22074 | O << ']'; |
| 22075 | return; |
| 22076 | break; |
| 22077 | case 27: |
| 22078 | // ADR_LSL_ZZZ_S_1 |
| 22079 | printRegWithShiftExtend<false, 16, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 22080 | O << ']'; |
| 22081 | return; |
| 22082 | break; |
| 22083 | case 28: |
| 22084 | // ADR_LSL_ZZZ_S_2 |
| 22085 | printRegWithShiftExtend<false, 32, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 22086 | O << ']'; |
| 22087 | return; |
| 22088 | break; |
| 22089 | case 29: |
| 22090 | // ADR_LSL_ZZZ_S_3 |
| 22091 | printRegWithShiftExtend<false, 64, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 22092 | O << ']'; |
| 22093 | return; |
| 22094 | break; |
| 22095 | case 30: |
| 22096 | // ADR_SXTW_ZZZ_D_0 |
| 22097 | printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 22098 | O << ']'; |
| 22099 | return; |
| 22100 | break; |
| 22101 | case 31: |
| 22102 | // ADR_SXTW_ZZZ_D_1 |
| 22103 | printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 22104 | O << ']'; |
| 22105 | return; |
| 22106 | break; |
| 22107 | case 32: |
| 22108 | // ADR_SXTW_ZZZ_D_2 |
| 22109 | printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 22110 | O << ']'; |
| 22111 | return; |
| 22112 | break; |
| 22113 | case 33: |
| 22114 | // ADR_SXTW_ZZZ_D_3 |
| 22115 | printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 22116 | O << ']'; |
| 22117 | return; |
| 22118 | break; |
| 22119 | case 34: |
| 22120 | // ADR_UXTW_ZZZ_D_0 |
| 22121 | printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 22122 | O << ']'; |
| 22123 | return; |
| 22124 | break; |
| 22125 | case 35: |
| 22126 | // ADR_UXTW_ZZZ_D_1 |
| 22127 | printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 22128 | O << ']'; |
| 22129 | return; |
| 22130 | break; |
| 22131 | case 36: |
| 22132 | // ADR_UXTW_ZZZ_D_2 |
| 22133 | printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 22134 | O << ']'; |
| 22135 | return; |
| 22136 | break; |
| 22137 | case 37: |
| 22138 | // ADR_UXTW_ZZZ_D_3 |
| 22139 | printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 22140 | O << ']'; |
| 22141 | return; |
| 22142 | break; |
| 22143 | case 38: |
| 22144 | // AESDIMC_2ZZI_B, AESDIMC_4ZZI_B, AESD_2ZZI_B, AESD_4ZZI_B, AESEMC_2ZZI_... |
| 22145 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 22146 | return; |
| 22147 | break; |
| 22148 | case 39: |
| 22149 | // ANDSWri, ANDWri, EORWri, ORRWri |
| 22150 | printLogicalImm<int32_t>(MI, OpNum: 2, STI, O); |
| 22151 | return; |
| 22152 | break; |
| 22153 | case 40: |
| 22154 | // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI |
| 22155 | printLogicalImm<int64_t>(MI, OpNum: 2, STI, O); |
| 22156 | return; |
| 22157 | break; |
| 22158 | case 41: |
| 22159 | // BFMLAL_MZZI_HtoS, BFMLSL_MZZI_HtoS, FMLALL_MZZI_BtoS, FMLAL_MZZI_BtoH,... |
| 22160 | printVectorIndex(MI, OpNum: 6, STI, O); |
| 22161 | return; |
| 22162 | break; |
| 22163 | case 42: |
| 22164 | // BFMLA_ZZZI, BFMLS_ZZZI, CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FDOT_Z... |
| 22165 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 22166 | break; |
| 22167 | case 43: |
| 22168 | // BFMOPA_MPPZZ, BFMOPA_MPPZZ_H, BFMOPS_MPPZZ, BFMOPS_MPPZZ_H, FMOPAL_MPP... |
| 22169 | printSVERegOp<'h'>(MI, OpNum: 4, STI, O); |
| 22170 | O << ", "; |
| 22171 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 22172 | return; |
| 22173 | break; |
| 22174 | case 44: |
| 22175 | // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALTX, CASALW, CASALX,... |
| 22176 | printOperand(MI, OpNo: 3, STI, O); |
| 22177 | break; |
| 22178 | case 45: |
| 22179 | // BFTMOPA_M2ZZZI_HtoH, BFTMOPA_M2ZZZI_HtoS, FTMOPA_M2ZZZI_BtoH, FTMOPA_M... |
| 22180 | printSVERegOp<>(MI, OpNum: 4, STI, O); |
| 22181 | printVectorIndex(MI, OpNum: 5, STI, O); |
| 22182 | return; |
| 22183 | break; |
| 22184 | case 46: |
| 22185 | // CBBEQWrr, CBBGEWrr, CBBGTWrr, CBBHIWrr, CBBHSWrr, CBBNEWrr, CBEQWri, C... |
| 22186 | printAlignedLabel(MI, Address, OpNum: 2, STI, O); |
| 22187 | return; |
| 22188 | break; |
| 22189 | case 47: |
| 22190 | // CPY_ZPmI_B |
| 22191 | printImm8OptLsl<int8_t>(MI, OpNum: 3, STI, O); |
| 22192 | return; |
| 22193 | break; |
| 22194 | case 48: |
| 22195 | // CPY_ZPmI_D |
| 22196 | printImm8OptLsl<int64_t>(MI, OpNum: 3, STI, O); |
| 22197 | return; |
| 22198 | break; |
| 22199 | case 49: |
| 22200 | // CPY_ZPmI_S |
| 22201 | printImm8OptLsl<int32_t>(MI, OpNum: 3, STI, O); |
| 22202 | return; |
| 22203 | break; |
| 22204 | case 50: |
| 22205 | // CPY_ZPzI_B |
| 22206 | printImm8OptLsl<int8_t>(MI, OpNum: 2, STI, O); |
| 22207 | return; |
| 22208 | break; |
| 22209 | case 51: |
| 22210 | // CPY_ZPzI_D |
| 22211 | printImm8OptLsl<int64_t>(MI, OpNum: 2, STI, O); |
| 22212 | return; |
| 22213 | break; |
| 22214 | case 52: |
| 22215 | // CPY_ZPzI_S |
| 22216 | printImm8OptLsl<int32_t>(MI, OpNum: 2, STI, O); |
| 22217 | return; |
| 22218 | break; |
| 22219 | case 53: |
| 22220 | // DUPi16, DUPi32, DUPi64, DUPi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... |
| 22221 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 22222 | return; |
| 22223 | break; |
| 22224 | case 54: |
| 22225 | // EXTRACT_ZPMXI_H_B, EXTRACT_ZPMXI_H_D, EXTRACT_ZPMXI_H_S |
| 22226 | printMatrixTileVector<0>(MI, OpNum: 3, STI, O); |
| 22227 | O << '['; |
| 22228 | printOperand(MI, OpNo: 4, STI, O); |
| 22229 | O << ", "; |
| 22230 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 22231 | O << ']'; |
| 22232 | return; |
| 22233 | break; |
| 22234 | case 55: |
| 22235 | // EXTRACT_ZPMXI_V_B, EXTRACT_ZPMXI_V_D, EXTRACT_ZPMXI_V_S |
| 22236 | printMatrixTileVector<1>(MI, OpNum: 3, STI, O); |
| 22237 | O << '['; |
| 22238 | printOperand(MI, OpNo: 4, STI, O); |
| 22239 | O << ", "; |
| 22240 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 22241 | O << ']'; |
| 22242 | return; |
| 22243 | break; |
| 22244 | case 56: |
| 22245 | // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... |
| 22246 | O << ", #0.0"; |
| 22247 | return; |
| 22248 | break; |
| 22249 | case 57: |
| 22250 | // FCPY_ZPmI_D, FCPY_ZPmI_S |
| 22251 | printFPImmOperand(MI, OpNum: 3, STI, O); |
| 22252 | return; |
| 22253 | break; |
| 22254 | case 58: |
| 22255 | // FDOT_VG2_M2Z2Z_BtoH, FDOT_VG2_M2Z2Z_BtoS, FDOT_VG4_M4Z4Z_BtoH, FDOT_VG... |
| 22256 | printTypedVectorList<0,'b'>(MI, OpNum: 5, STI, O); |
| 22257 | return; |
| 22258 | break; |
| 22259 | case 59: |
| 22260 | // FDOT_VG2_M2ZZI_BtoH, FDOT_VG2_M2ZZI_BtoS, FDOT_VG2_M2ZZ_BtoH, FDOT_VG2... |
| 22261 | printSVERegOp<'b'>(MI, OpNum: 5, STI, O); |
| 22262 | break; |
| 22263 | case 60: |
| 22264 | // FMLAL2lanev4f16, FMLALlanev4f16, FMLSL2lanev4f16, FMLSLlanev4f16 |
| 22265 | O << ".h"; |
| 22266 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 22267 | return; |
| 22268 | break; |
| 22269 | case 61: |
| 22270 | // FMLAL2v4f16, FMLALv4f16, FMLSL2v4f16, FMLSLv4f16 |
| 22271 | O << ".2h"; |
| 22272 | return; |
| 22273 | break; |
| 22274 | case 62: |
| 22275 | // FMOPA_MPPZZ_BtoH, FMOPA_MPPZZ_BtoS, SMOPA_MPPZZ_S, SMOPS_MPPZZ_S, SUMO... |
| 22276 | printSVERegOp<'b'>(MI, OpNum: 4, STI, O); |
| 22277 | O << ", "; |
| 22278 | printSVERegOp<'b'>(MI, OpNum: 5, STI, O); |
| 22279 | return; |
| 22280 | break; |
| 22281 | case 63: |
| 22282 | // INDEX_RI_B |
| 22283 | printSImm<8>(MI, OpNo: 2, STI, O); |
| 22284 | return; |
| 22285 | break; |
| 22286 | case 64: |
| 22287 | // INSERT_MXIPZ_H_D, INSERT_MXIPZ_V_D |
| 22288 | printSVERegOp<'d'>(MI, OpNum: 5, STI, O); |
| 22289 | return; |
| 22290 | break; |
| 22291 | case 65: |
| 22292 | // INSERT_MXIPZ_H_H, INSERT_MXIPZ_V_H |
| 22293 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 22294 | return; |
| 22295 | break; |
| 22296 | case 66: |
| 22297 | // INSERT_MXIPZ_H_Q, INSERT_MXIPZ_V_Q |
| 22298 | printSVERegOp<'q'>(MI, OpNum: 5, STI, O); |
| 22299 | return; |
| 22300 | break; |
| 22301 | case 67: |
| 22302 | // INSERT_MXIPZ_H_S, INSERT_MXIPZ_V_S |
| 22303 | printSVERegOp<'s'>(MI, OpNum: 5, STI, O); |
| 22304 | return; |
| 22305 | break; |
| 22306 | case 68: |
| 22307 | // LD1B_2Z_STRIDED, LDNT1B_2Z_STRIDED |
| 22308 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 22309 | O << ']'; |
| 22310 | return; |
| 22311 | break; |
| 22312 | case 69: |
| 22313 | // LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED_IMM, LDNT1B_2Z_STRIDED_IMM, LDNT1... |
| 22314 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 22315 | O << ", mul vl]"; |
| 22316 | return; |
| 22317 | break; |
| 22318 | case 70: |
| 22319 | // LD1H_2Z_STRIDED, LDNT1H_2Z_STRIDED |
| 22320 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 22321 | O << ']'; |
| 22322 | return; |
| 22323 | break; |
| 22324 | case 71: |
| 22325 | // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... |
| 22326 | O << "/z, ["; |
| 22327 | printOperand(MI, OpNo: 4, STI, O); |
| 22328 | O << ", "; |
| 22329 | break; |
| 22330 | case 72: |
| 22331 | // LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL... |
| 22332 | printOperand(MI, OpNo: 4, STI, O); |
| 22333 | O << ']'; |
| 22334 | return; |
| 22335 | break; |
| 22336 | case 73: |
| 22337 | // LDG, ST2GPostIndex, ST2GPreIndex, STGPostIndex, STGPreIndex, STZ2GPost... |
| 22338 | printImmScale<16>(MI, OpNum: 3, STI, O); |
| 22339 | break; |
| 22340 | case 74: |
| 22341 | // LDRAAindexed, LDRABindexed |
| 22342 | printImmScale<8>(MI, OpNum: 2, STI, O); |
| 22343 | O << ']'; |
| 22344 | return; |
| 22345 | break; |
| 22346 | case 75: |
| 22347 | // LDRAAwriteback, LDRABwriteback |
| 22348 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 22349 | O << "]!"; |
| 22350 | return; |
| 22351 | break; |
| 22352 | case 76: |
| 22353 | // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui |
| 22354 | printUImm12Offset<1>(MI, OpNum: 2, STI, O); |
| 22355 | O << ']'; |
| 22356 | return; |
| 22357 | break; |
| 22358 | case 77: |
| 22359 | // LDRDui, LDRXui, PRFMui, STRDui, STRXui |
| 22360 | printUImm12Offset<8>(MI, OpNum: 2, STI, O); |
| 22361 | O << ']'; |
| 22362 | return; |
| 22363 | break; |
| 22364 | case 78: |
| 22365 | // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui |
| 22366 | printUImm12Offset<2>(MI, OpNum: 2, STI, O); |
| 22367 | O << ']'; |
| 22368 | return; |
| 22369 | break; |
| 22370 | case 79: |
| 22371 | // LDRQui, STRQui |
| 22372 | printUImm12Offset<16>(MI, OpNum: 2, STI, O); |
| 22373 | O << ']'; |
| 22374 | return; |
| 22375 | break; |
| 22376 | case 80: |
| 22377 | // LDRSWui, LDRSui, LDRWui, STRSui, STRWui |
| 22378 | printUImm12Offset<4>(MI, OpNum: 2, STI, O); |
| 22379 | O << ']'; |
| 22380 | return; |
| 22381 | break; |
| 22382 | case 81: |
| 22383 | // LUTI2_S_2ZTZI_B, LUTI2_S_2ZTZI_H, LUTI2_ZTZI_B, LUTI2_ZTZI_S, LUTI4_S_... |
| 22384 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 22385 | break; |
| 22386 | case 82: |
| 22387 | // MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q |
| 22388 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 22389 | O << ']'; |
| 22390 | return; |
| 22391 | break; |
| 22392 | case 83: |
| 22393 | // MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZMXI_H_H, MOVA_2ZMXI_H_S, MOVA_2... |
| 22394 | printImmRangeScale<2, 1>(MI, OpNum: 3, STI, O); |
| 22395 | O << ']'; |
| 22396 | return; |
| 22397 | break; |
| 22398 | case 84: |
| 22399 | // MOVA_4ZMXI_H_B, MOVA_4ZMXI_H_D, MOVA_4ZMXI_H_H, MOVA_4ZMXI_H_S, MOVA_4... |
| 22400 | printImmRangeScale<4, 3>(MI, OpNum: 3, STI, O); |
| 22401 | O << ']'; |
| 22402 | return; |
| 22403 | break; |
| 22404 | case 85: |
| 22405 | // MOVA_MXI2Z_H_B, MOVA_MXI2Z_V_B, MOVA_MXI4Z_H_B, MOVA_MXI4Z_V_B |
| 22406 | printTypedVectorList<0,'b'>(MI, OpNum: 4, STI, O); |
| 22407 | return; |
| 22408 | break; |
| 22409 | case 86: |
| 22410 | // MOVA_MXI2Z_H_D, MOVA_MXI2Z_V_D, MOVA_MXI4Z_H_D, MOVA_MXI4Z_V_D |
| 22411 | printTypedVectorList<0,'d'>(MI, OpNum: 4, STI, O); |
| 22412 | return; |
| 22413 | break; |
| 22414 | case 87: |
| 22415 | // MOVA_MXI2Z_H_H, MOVA_MXI2Z_V_H, MOVA_MXI4Z_H_H, MOVA_MXI4Z_V_H |
| 22416 | printTypedVectorList<0,'h'>(MI, OpNum: 4, STI, O); |
| 22417 | return; |
| 22418 | break; |
| 22419 | case 88: |
| 22420 | // MOVA_MXI2Z_H_S, MOVA_MXI2Z_V_S, MOVA_MXI4Z_H_S, MOVA_MXI4Z_V_S |
| 22421 | printTypedVectorList<0,'s'>(MI, OpNum: 4, STI, O); |
| 22422 | return; |
| 22423 | break; |
| 22424 | case 89: |
| 22425 | // PRFB_D_PZI, PRFB_S_PZI |
| 22426 | O << ']'; |
| 22427 | return; |
| 22428 | break; |
| 22429 | case 90: |
| 22430 | // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI |
| 22431 | O << ", mul vl]"; |
| 22432 | return; |
| 22433 | break; |
| 22434 | case 91: |
| 22435 | // SPLICE_ZPZZ_B |
| 22436 | printTypedVectorList<0,'b'>(MI, OpNum: 2, STI, O); |
| 22437 | return; |
| 22438 | break; |
| 22439 | case 92: |
| 22440 | // SPLICE_ZPZZ_D |
| 22441 | printTypedVectorList<0,'d'>(MI, OpNum: 2, STI, O); |
| 22442 | return; |
| 22443 | break; |
| 22444 | case 93: |
| 22445 | // SPLICE_ZPZZ_S |
| 22446 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 22447 | return; |
| 22448 | break; |
| 22449 | case 94: |
| 22450 | // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... |
| 22451 | printGPR64as32(MI, OpNum: 2, STI, O); |
| 22452 | return; |
| 22453 | break; |
| 22454 | case 95: |
| 22455 | // ST1_MXIPXX_H_B, ST1_MXIPXX_H_D, ST1_MXIPXX_H_H, ST1_MXIPXX_H_Q, ST1_MX... |
| 22456 | O << ", ["; |
| 22457 | printOperand(MI, OpNo: 4, STI, O); |
| 22458 | O << ", "; |
| 22459 | break; |
| 22460 | case 96: |
| 22461 | // SYSLxt |
| 22462 | printSysCROperand(MI, OpNo: 2, STI, O); |
| 22463 | O << ", "; |
| 22464 | printSysCROperand(MI, OpNo: 3, STI, O); |
| 22465 | O << ", "; |
| 22466 | printOperand(MI, OpNo: 4, STI, O); |
| 22467 | return; |
| 22468 | break; |
| 22469 | case 97: |
| 22470 | // TCHANGEBri, TCHANGEBrr, TCHANGEFri, TCHANGEFrr |
| 22471 | printTIndexHintOp(MI, OpNum: 2, STI, O); |
| 22472 | return; |
| 22473 | break; |
| 22474 | case 98: |
| 22475 | // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S |
| 22476 | printImm(MI, OpNo: 2, STI, O); |
| 22477 | return; |
| 22478 | break; |
| 22479 | } |
| 22480 | |
| 22481 | |
| 22482 | // Fragment 5 encoded into 7 bits for 94 unique commands. |
| 22483 | switch ((Bits >> 50) & 127) { |
| 22484 | default: llvm_unreachable("Invalid command number."); |
| 22485 | case 0: |
| 22486 | // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABS_ZPzZ_B, ABS_ZPzZ_D, ABS_ZPzZ_S... |
| 22487 | return; |
| 22488 | break; |
| 22489 | case 1: |
| 22490 | // ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_CPA,... |
| 22491 | O << ", "; |
| 22492 | break; |
| 22493 | case 2: |
| 22494 | // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... |
| 22495 | O << ".2d"; |
| 22496 | return; |
| 22497 | break; |
| 22498 | case 3: |
| 22499 | // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... |
| 22500 | O << ".4s"; |
| 22501 | return; |
| 22502 | break; |
| 22503 | case 4: |
| 22504 | // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BFDOTv8bf16, B... |
| 22505 | O << ".8h"; |
| 22506 | return; |
| 22507 | break; |
| 22508 | case 5: |
| 22509 | // ADDPT_shift, SUBPT_shift |
| 22510 | printShifter(MI, OpNum: 3, STI, O); |
| 22511 | return; |
| 22512 | break; |
| 22513 | case 6: |
| 22514 | // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BFADD_ZP... |
| 22515 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 22516 | break; |
| 22517 | case 7: |
| 22518 | // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... |
| 22519 | O << ".16b"; |
| 22520 | return; |
| 22521 | break; |
| 22522 | case 8: |
| 22523 | // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... |
| 22524 | O << ".2s"; |
| 22525 | return; |
| 22526 | break; |
| 22527 | case 9: |
| 22528 | // ADDPv4i16, ADDv4i16, BFDOTv4bf16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMH... |
| 22529 | O << ".4h"; |
| 22530 | return; |
| 22531 | break; |
| 22532 | case 10: |
| 22533 | // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... |
| 22534 | O << ".8b"; |
| 22535 | return; |
| 22536 | break; |
| 22537 | case 11: |
| 22538 | // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 |
| 22539 | printArithExtend(MI, OpNum: 3, STI, O); |
| 22540 | return; |
| 22541 | break; |
| 22542 | case 12: |
| 22543 | // ADD_VG2_M2Z2Z_D, ADD_VG4_M4Z4Z_D, FMLA_VG2_M2Z2Z_D, FMLA_VG4_M4Z4Z_D, ... |
| 22544 | printTypedVectorList<0,'d'>(MI, OpNum: 5, STI, O); |
| 22545 | return; |
| 22546 | break; |
| 22547 | case 13: |
| 22548 | // ADD_VG2_M2Z2Z_S, ADD_VG4_M4Z4Z_S, FMLA_VG2_M2Z2Z_S, FMLA_VG4_M4Z4Z_S, ... |
| 22549 | printTypedVectorList<0,'s'>(MI, OpNum: 5, STI, O); |
| 22550 | return; |
| 22551 | break; |
| 22552 | case 14: |
| 22553 | // ADD_VG2_M2ZZ_D, ADD_VG4_M4ZZ_D, FMLA_VG2_M2ZZI_D, FMLA_VG2_M2ZZ_D, FML... |
| 22554 | printSVERegOp<'d'>(MI, OpNum: 5, STI, O); |
| 22555 | break; |
| 22556 | case 15: |
| 22557 | // ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_S, FMLA_VG2_M2ZZI_S, FMLA_VG2_M2ZZ_S, FML... |
| 22558 | printSVERegOp<'s'>(MI, OpNum: 5, STI, O); |
| 22559 | break; |
| 22560 | case 16: |
| 22561 | // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... |
| 22562 | printOperand(MI, OpNo: 3, STI, O); |
| 22563 | break; |
| 22564 | case 17: |
| 22565 | // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... |
| 22566 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 22567 | return; |
| 22568 | break; |
| 22569 | case 18: |
| 22570 | // BCAX, EOR3, EXTv16i8 |
| 22571 | O << ".16b, "; |
| 22572 | break; |
| 22573 | case 19: |
| 22574 | // BF16DOTlanev4bf16, BF16DOTlanev8bf16, FDOTlanev4f16_v2f32, FDOTlanev8f... |
| 22575 | O << ".2h"; |
| 22576 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 22577 | return; |
| 22578 | break; |
| 22579 | case 20: |
| 22580 | // BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG4_M4Z4Z_HtoS, BFMLAL_VG2_M2Z2Z_HtoS, BFM... |
| 22581 | printTypedVectorList<0,'h'>(MI, OpNum: 5, STI, O); |
| 22582 | return; |
| 22583 | break; |
| 22584 | case 21: |
| 22585 | // BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG2_M2ZZ_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFDOT... |
| 22586 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 22587 | break; |
| 22588 | case 22: |
| 22589 | // BFDOT_ZZI, BFMLALB_ZZZI, BFMLALT_ZZZI, BFMLSLB_ZZZI_S, BFMLSLT_ZZZI_S,... |
| 22590 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 22591 | break; |
| 22592 | case 23: |
| 22593 | // BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAL2... |
| 22594 | O << ".h"; |
| 22595 | break; |
| 22596 | case 24: |
| 22597 | // BFMLA_ZPmZZ, BFMLS_ZPmZZ, FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, F... |
| 22598 | printSVERegOp<'h'>(MI, OpNum: 4, STI, O); |
| 22599 | break; |
| 22600 | case 25: |
| 22601 | // CADD_ZZI_H, SQCADD_ZZI_H |
| 22602 | printComplexRotationOp<180, 90>(MI, OpNo: 3, STI, O); |
| 22603 | return; |
| 22604 | break; |
| 22605 | case 26: |
| 22606 | // CASAB, CASAH, CASALB, CASALH, CASALTX, CASALW, CASALX, CASATX, CASAW, ... |
| 22607 | O << ']'; |
| 22608 | return; |
| 22609 | break; |
| 22610 | case 27: |
| 22611 | // CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H |
| 22612 | printComplexRotationOp<90, 0>(MI, OpNo: 4, STI, O); |
| 22613 | return; |
| 22614 | break; |
| 22615 | case 28: |
| 22616 | // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H |
| 22617 | printImm(MI, OpNo: 3, STI, O); |
| 22618 | return; |
| 22619 | break; |
| 22620 | case 29: |
| 22621 | // EXTv8i8 |
| 22622 | O << ".8b, "; |
| 22623 | printOperand(MI, OpNo: 3, STI, O); |
| 22624 | return; |
| 22625 | break; |
| 22626 | case 30: |
| 22627 | // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H |
| 22628 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 22629 | return; |
| 22630 | break; |
| 22631 | case 31: |
| 22632 | // FCADDv2f32, FCMLAv2f32 |
| 22633 | O << ".2s, "; |
| 22634 | break; |
| 22635 | case 32: |
| 22636 | // FCADDv2f64, FCMLAv2f64, XAR |
| 22637 | O << ".2d, "; |
| 22638 | break; |
| 22639 | case 33: |
| 22640 | // FCADDv4f16, FCMLAv4f16 |
| 22641 | O << ".4h, "; |
| 22642 | break; |
| 22643 | case 34: |
| 22644 | // FCADDv4f32, FCMLAv4f32, SM3SS1 |
| 22645 | O << ".4s, "; |
| 22646 | break; |
| 22647 | case 35: |
| 22648 | // FCADDv8f16, FCMLAv8f16 |
| 22649 | O << ".8h, "; |
| 22650 | break; |
| 22651 | case 36: |
| 22652 | // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... |
| 22653 | O << ", #0.0"; |
| 22654 | return; |
| 22655 | break; |
| 22656 | case 37: |
| 22657 | // FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in... |
| 22658 | O << ".s"; |
| 22659 | break; |
| 22660 | case 38: |
| 22661 | // FDOT_VG2_M2ZZI_BtoH, FDOT_VG2_M2ZZI_BtoS, FDOT_VG4_M4ZZI_BtoH, FDOT_VG... |
| 22662 | printVectorIndex(MI, OpNum: 6, STI, O); |
| 22663 | return; |
| 22664 | break; |
| 22665 | case 39: |
| 22666 | // FDOTlanev2f32, FDOTlanev4f32, SDOTlanev16i8, SDOTlanev8i8, SUDOTlanev1... |
| 22667 | O << ".4b"; |
| 22668 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 22669 | return; |
| 22670 | break; |
| 22671 | case 40: |
| 22672 | // FDOTlanev4f16, FDOTlanev8f16 |
| 22673 | O << ".2b"; |
| 22674 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 22675 | return; |
| 22676 | break; |
| 22677 | case 41: |
| 22678 | // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H |
| 22679 | printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 22680 | return; |
| 22681 | break; |
| 22682 | case 42: |
| 22683 | // FMLALBlanev8f16, FMLALLBBlanev4f32, FMLALLBTlanev4f32, FMLALLTBlanev4f... |
| 22684 | O << ".b"; |
| 22685 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 22686 | return; |
| 22687 | break; |
| 22688 | case 43: |
| 22689 | // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... |
| 22690 | O << ".d"; |
| 22691 | break; |
| 22692 | case 44: |
| 22693 | // FMUL_ZPmI_H |
| 22694 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, OpNum: 3, STI, O); |
| 22695 | return; |
| 22696 | break; |
| 22697 | case 45: |
| 22698 | // FMUL_ZZZI_D, FMUL_ZZZI_S, LUTI2_S_2ZTZI_B, LUTI2_S_2ZTZI_H, LUTI2_ZTZI... |
| 22699 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 22700 | return; |
| 22701 | break; |
| 22702 | case 46: |
| 22703 | // GLD1B_D, GLD1D, GLD1H_D, GLD1SB_D, GLD1SH_D, GLD1SW_D, GLD1W_D, GLDFF1... |
| 22704 | printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 22705 | O << ']'; |
| 22706 | return; |
| 22707 | break; |
| 22708 | case 47: |
| 22709 | // GLD1B_D_SXTW, GLD1D_SXTW, GLD1H_D_SXTW, GLD1SB_D_SXTW, GLD1SH_D_SXTW, ... |
| 22710 | printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 22711 | O << ']'; |
| 22712 | return; |
| 22713 | break; |
| 22714 | case 48: |
| 22715 | // GLD1B_D_UXTW, GLD1D_UXTW, GLD1H_D_UXTW, GLD1SB_D_UXTW, GLD1SH_D_UXTW, ... |
| 22716 | printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 22717 | O << ']'; |
| 22718 | return; |
| 22719 | break; |
| 22720 | case 49: |
| 22721 | // GLD1B_S_SXTW, GLD1H_S_SXTW, GLD1SB_S_SXTW, GLD1SH_S_SXTW, GLD1W_SXTW, ... |
| 22722 | printRegWithShiftExtend<true, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 22723 | O << ']'; |
| 22724 | return; |
| 22725 | break; |
| 22726 | case 50: |
| 22727 | // GLD1B_S_UXTW, GLD1H_S_UXTW, GLD1SB_S_UXTW, GLD1SH_S_UXTW, GLD1W_UXTW, ... |
| 22728 | printRegWithShiftExtend<false, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 22729 | O << ']'; |
| 22730 | return; |
| 22731 | break; |
| 22732 | case 51: |
| 22733 | // GLD1D_IMM, GLDFF1D_IMM, LD1RD_IMM, SST1D_IMM |
| 22734 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 22735 | O << ']'; |
| 22736 | return; |
| 22737 | break; |
| 22738 | case 52: |
| 22739 | // GLD1D_SCALED, GLDFF1D_SCALED, SST1D_SCALED |
| 22740 | printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 22741 | O << ']'; |
| 22742 | return; |
| 22743 | break; |
| 22744 | case 53: |
| 22745 | // GLD1D_SXTW_SCALED, GLDFF1D_SXTW_SCALED, SST1D_SXTW_SCALED |
| 22746 | printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 22747 | O << ']'; |
| 22748 | return; |
| 22749 | break; |
| 22750 | case 54: |
| 22751 | // GLD1D_UXTW_SCALED, GLDFF1D_UXTW_SCALED, SST1D_UXTW_SCALED |
| 22752 | printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 22753 | O << ']'; |
| 22754 | return; |
| 22755 | break; |
| 22756 | case 55: |
| 22757 | // GLD1H_D_IMM, GLD1H_S_IMM, GLD1SH_D_IMM, GLD1SH_S_IMM, GLDFF1H_D_IMM, G... |
| 22758 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 22759 | break; |
| 22760 | case 56: |
| 22761 | // GLD1H_D_SCALED, GLD1SH_D_SCALED, GLDFF1H_D_SCALED, GLDFF1SH_D_SCALED, ... |
| 22762 | printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 22763 | O << ']'; |
| 22764 | return; |
| 22765 | break; |
| 22766 | case 57: |
| 22767 | // GLD1H_D_SXTW_SCALED, GLD1SH_D_SXTW_SCALED, GLDFF1H_D_SXTW_SCALED, GLDF... |
| 22768 | printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 22769 | O << ']'; |
| 22770 | return; |
| 22771 | break; |
| 22772 | case 58: |
| 22773 | // GLD1H_D_UXTW_SCALED, GLD1SH_D_UXTW_SCALED, GLDFF1H_D_UXTW_SCALED, GLDF... |
| 22774 | printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 22775 | O << ']'; |
| 22776 | return; |
| 22777 | break; |
| 22778 | case 59: |
| 22779 | // GLD1H_S_SXTW_SCALED, GLD1SH_S_SXTW_SCALED, GLDFF1H_S_SXTW_SCALED, GLDF... |
| 22780 | printRegWithShiftExtend<true, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 22781 | O << ']'; |
| 22782 | return; |
| 22783 | break; |
| 22784 | case 60: |
| 22785 | // GLD1H_S_UXTW_SCALED, GLD1SH_S_UXTW_SCALED, GLDFF1H_S_UXTW_SCALED, GLDF... |
| 22786 | printRegWithShiftExtend<false, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 22787 | O << ']'; |
| 22788 | return; |
| 22789 | break; |
| 22790 | case 61: |
| 22791 | // GLD1SW_D_IMM, GLD1W_D_IMM, GLD1W_IMM, GLDFF1SW_D_IMM, GLDFF1W_D_IMM, G... |
| 22792 | printImmScale<4>(MI, OpNum: 3, STI, O); |
| 22793 | break; |
| 22794 | case 62: |
| 22795 | // GLD1SW_D_SCALED, GLD1W_D_SCALED, GLDFF1SW_D_SCALED, GLDFF1W_D_SCALED, ... |
| 22796 | printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 22797 | O << ']'; |
| 22798 | return; |
| 22799 | break; |
| 22800 | case 63: |
| 22801 | // GLD1SW_D_SXTW_SCALED, GLD1W_D_SXTW_SCALED, GLDFF1SW_D_SXTW_SCALED, GLD... |
| 22802 | printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 22803 | O << ']'; |
| 22804 | return; |
| 22805 | break; |
| 22806 | case 64: |
| 22807 | // GLD1SW_D_UXTW_SCALED, GLD1W_D_UXTW_SCALED, GLDFF1SW_D_UXTW_SCALED, GLD... |
| 22808 | printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 22809 | O << ']'; |
| 22810 | return; |
| 22811 | break; |
| 22812 | case 65: |
| 22813 | // GLD1W_SXTW_SCALED, GLDFF1W_SXTW_SCALED, SST1W_SXTW_SCALED |
| 22814 | printRegWithShiftExtend<true, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 22815 | O << ']'; |
| 22816 | return; |
| 22817 | break; |
| 22818 | case 66: |
| 22819 | // GLD1W_UXTW_SCALED, GLDFF1W_UXTW_SCALED, SST1W_UXTW_SCALED |
| 22820 | printRegWithShiftExtend<false, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 22821 | O << ']'; |
| 22822 | return; |
| 22823 | break; |
| 22824 | case 67: |
| 22825 | // LD1B, LD1B_2Z, LD1B_4Z, LD1B_4Z_STRIDED, LD1B_D, LD1B_H, LD1B_S, LD1RO... |
| 22826 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 22827 | O << ']'; |
| 22828 | return; |
| 22829 | break; |
| 22830 | case 68: |
| 22831 | // LD1D, LD1D_2Z, LD1D_2Z_STRIDED, LD1D_4Z, LD1D_4Z_STRIDED, LD1D_Q, LD1R... |
| 22832 | printRegWithShiftExtend<false, 64, 'x', 0>(MI, OpNum: 3, STI, O); |
| 22833 | O << ']'; |
| 22834 | return; |
| 22835 | break; |
| 22836 | case 69: |
| 22837 | // LD1H, LD1H_2Z, LD1H_4Z, LD1H_4Z_STRIDED, LD1H_D, LD1H_S, LD1RO_H, LD1R... |
| 22838 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 22839 | O << ']'; |
| 22840 | return; |
| 22841 | break; |
| 22842 | case 70: |
| 22843 | // LD1RO_B_IMM, LD1RO_D_IMM, LD1RO_H_IMM, LD1RO_W_IMM |
| 22844 | printImmScale<32>(MI, OpNum: 3, STI, O); |
| 22845 | O << ']'; |
| 22846 | return; |
| 22847 | break; |
| 22848 | case 71: |
| 22849 | // LD1RO_W, LD1RQ_W, LD1SW_D, LD1W, LD1W_2Z, LD1W_2Z_STRIDED, LD1W_4Z, LD... |
| 22850 | printRegWithShiftExtend<false, 32, 'x', 0>(MI, OpNum: 3, STI, O); |
| 22851 | O << ']'; |
| 22852 | return; |
| 22853 | break; |
| 22854 | case 72: |
| 22855 | // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM |
| 22856 | printImmScale<16>(MI, OpNum: 3, STI, O); |
| 22857 | O << ']'; |
| 22858 | return; |
| 22859 | break; |
| 22860 | case 73: |
| 22861 | // LD1_MXIPXX_H_B, LD1_MXIPXX_V_B, ST1_MXIPXX_H_B, ST1_MXIPXX_V_B |
| 22862 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 5, STI, O); |
| 22863 | O << ']'; |
| 22864 | return; |
| 22865 | break; |
| 22866 | case 74: |
| 22867 | // LD1_MXIPXX_H_D, LD1_MXIPXX_V_D, ST1_MXIPXX_H_D, ST1_MXIPXX_V_D |
| 22868 | printRegWithShiftExtend<false, 64, 'x', 0>(MI, OpNum: 5, STI, O); |
| 22869 | O << ']'; |
| 22870 | return; |
| 22871 | break; |
| 22872 | case 75: |
| 22873 | // LD1_MXIPXX_H_H, LD1_MXIPXX_V_H, ST1_MXIPXX_H_H, ST1_MXIPXX_V_H |
| 22874 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 5, STI, O); |
| 22875 | O << ']'; |
| 22876 | return; |
| 22877 | break; |
| 22878 | case 76: |
| 22879 | // LD1_MXIPXX_H_Q, LD1_MXIPXX_V_Q, ST1_MXIPXX_H_Q, ST1_MXIPXX_V_Q |
| 22880 | printRegWithShiftExtend<false, 128, 'x', 0>(MI, OpNum: 5, STI, O); |
| 22881 | O << ']'; |
| 22882 | return; |
| 22883 | break; |
| 22884 | case 77: |
| 22885 | // LD1_MXIPXX_H_S, LD1_MXIPXX_V_S, ST1_MXIPXX_H_S, ST1_MXIPXX_V_S |
| 22886 | printRegWithShiftExtend<false, 32, 'x', 0>(MI, OpNum: 5, STI, O); |
| 22887 | O << ']'; |
| 22888 | return; |
| 22889 | break; |
| 22890 | case 78: |
| 22891 | // LD2Q, LD3Q, LD4Q, ST2Q, ST3Q, ST4Q |
| 22892 | printRegWithShiftExtend<false, 128, 'x', 0>(MI, OpNum: 3, STI, O); |
| 22893 | O << ']'; |
| 22894 | return; |
| 22895 | break; |
| 22896 | case 79: |
| 22897 | // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3Q_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ... |
| 22898 | printImmScale<3>(MI, OpNum: 3, STI, O); |
| 22899 | O << ", mul vl]"; |
| 22900 | return; |
| 22901 | break; |
| 22902 | case 80: |
| 22903 | // LDAPPi, LDAPi, STLPi |
| 22904 | O << ", #0]"; |
| 22905 | return; |
| 22906 | break; |
| 22907 | case 81: |
| 22908 | // LDIAPPWpost |
| 22909 | O << "], #8"; |
| 22910 | return; |
| 22911 | break; |
| 22912 | case 82: |
| 22913 | // LDIAPPXpost |
| 22914 | O << "], #16"; |
| 22915 | return; |
| 22916 | break; |
| 22917 | case 83: |
| 22918 | // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, LDTPQpost... |
| 22919 | O << "], "; |
| 22920 | break; |
| 22921 | case 84: |
| 22922 | // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR... |
| 22923 | O << "]!"; |
| 22924 | return; |
| 22925 | break; |
| 22926 | case 85: |
| 22927 | // LDR_PXI, LDR_ZXI, STR_PXI, STR_ZXI |
| 22928 | O << ", mul vl]"; |
| 22929 | return; |
| 22930 | break; |
| 22931 | case 86: |
| 22932 | // PSEL_PPPRI_B, PSEL_PPPRI_D, PSEL_PPPRI_H, PSEL_PPPRI_S |
| 22933 | O << '['; |
| 22934 | printOperand(MI, OpNo: 3, STI, O); |
| 22935 | O << ", "; |
| 22936 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 22937 | O << ']'; |
| 22938 | return; |
| 22939 | break; |
| 22940 | case 87: |
| 22941 | // SEL_VG2_2ZC2Z2Z_B, SEL_VG4_4ZC4Z4Z_B |
| 22942 | printTypedVectorList<0,'b'>(MI, OpNum: 3, STI, O); |
| 22943 | return; |
| 22944 | break; |
| 22945 | case 88: |
| 22946 | // SEL_VG2_2ZC2Z2Z_D, SEL_VG4_4ZC4Z4Z_D |
| 22947 | printTypedVectorList<0,'d'>(MI, OpNum: 3, STI, O); |
| 22948 | return; |
| 22949 | break; |
| 22950 | case 89: |
| 22951 | // SEL_VG2_2ZC2Z2Z_H, SEL_VG4_4ZC4Z4Z_H |
| 22952 | printTypedVectorList<0,'h'>(MI, OpNum: 3, STI, O); |
| 22953 | return; |
| 22954 | break; |
| 22955 | case 90: |
| 22956 | // SEL_VG2_2ZC2Z2Z_S, SEL_VG4_4ZC4Z4Z_S |
| 22957 | printTypedVectorList<0,'s'>(MI, OpNum: 3, STI, O); |
| 22958 | return; |
| 22959 | break; |
| 22960 | case 91: |
| 22961 | // STILPWpre |
| 22962 | O << ", #-8]!"; |
| 22963 | return; |
| 22964 | break; |
| 22965 | case 92: |
| 22966 | // STILPXpre |
| 22967 | O << ", #-16]!"; |
| 22968 | return; |
| 22969 | break; |
| 22970 | case 93: |
| 22971 | // STLXPW, STLXPX, STXPW, STXPX |
| 22972 | O << ", ["; |
| 22973 | printOperand(MI, OpNo: 3, STI, O); |
| 22974 | O << ']'; |
| 22975 | return; |
| 22976 | break; |
| 22977 | } |
| 22978 | |
| 22979 | |
| 22980 | // Fragment 6 encoded into 6 bits for 47 unique commands. |
| 22981 | switch ((Bits >> 57) & 63) { |
| 22982 | default: llvm_unreachable("Invalid command number."); |
| 22983 | case 0: |
| 22984 | // ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A... |
| 22985 | printOperand(MI, OpNo: 3, STI, O); |
| 22986 | return; |
| 22987 | break; |
| 22988 | case 1: |
| 22989 | // ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_... |
| 22990 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 22991 | return; |
| 22992 | break; |
| 22993 | case 2: |
| 22994 | // ADDP_ZPmZ_D, ADD_ZPmZ_CPA, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WI... |
| 22995 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 22996 | break; |
| 22997 | case 3: |
| 22998 | // ADDP_ZPmZ_H, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_D, ADD_VG4_M... |
| 22999 | return; |
| 23000 | break; |
| 23001 | case 4: |
| 23002 | // ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ... |
| 23003 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 23004 | break; |
| 23005 | case 5: |
| 23006 | // BCAX, EOR3, SM3SS1 |
| 23007 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 23008 | break; |
| 23009 | case 6: |
| 23010 | // BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFMLAL_VG2_M2ZZI_HtoS, BFM... |
| 23011 | printVectorIndex(MI, OpNum: 6, STI, O); |
| 23012 | return; |
| 23013 | break; |
| 23014 | case 7: |
| 23015 | // BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv... |
| 23016 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 23017 | break; |
| 23018 | case 8: |
| 23019 | // BFMWri, BFMXri |
| 23020 | printOperand(MI, OpNo: 4, STI, O); |
| 23021 | return; |
| 23022 | break; |
| 23023 | case 9: |
| 23024 | // BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_S, FMOPS_MPPZZ_S |
| 23025 | printSVERegOp<'s'>(MI, OpNum: 5, STI, O); |
| 23026 | return; |
| 23027 | break; |
| 23028 | case 10: |
| 23029 | // CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16... |
| 23030 | printComplexRotationOp<180, 90>(MI, OpNo: 3, STI, O); |
| 23031 | return; |
| 23032 | break; |
| 23033 | case 11: |
| 23034 | // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... |
| 23035 | printCondCode(MI, OpNum: 3, STI, O); |
| 23036 | return; |
| 23037 | break; |
| 23038 | case 12: |
| 23039 | // CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, S... |
| 23040 | O << ", "; |
| 23041 | break; |
| 23042 | case 13: |
| 23043 | // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H |
| 23044 | printComplexRotationOp<90, 0>(MI, OpNo: 5, STI, O); |
| 23045 | return; |
| 23046 | break; |
| 23047 | case 14: |
| 23048 | // CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16... |
| 23049 | printComplexRotationOp<90, 0>(MI, OpNo: 4, STI, O); |
| 23050 | return; |
| 23051 | break; |
| 23052 | case 15: |
| 23053 | // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H |
| 23054 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 23055 | return; |
| 23056 | break; |
| 23057 | case 16: |
| 23058 | // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... |
| 23059 | printImm(MI, OpNo: 3, STI, O); |
| 23060 | return; |
| 23061 | break; |
| 23062 | case 17: |
| 23063 | // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... |
| 23064 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 23065 | return; |
| 23066 | break; |
| 23067 | case 18: |
| 23068 | // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... |
| 23069 | printSVERegOp<'d'>(MI, OpNum: 4, STI, O); |
| 23070 | break; |
| 23071 | case 19: |
| 23072 | // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... |
| 23073 | printSVERegOp<'s'>(MI, OpNum: 4, STI, O); |
| 23074 | break; |
| 23075 | case 20: |
| 23076 | // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... |
| 23077 | printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 23078 | return; |
| 23079 | break; |
| 23080 | case 21: |
| 23081 | // FMOPA_MPPZZ_D, FMOPS_MPPZZ_D |
| 23082 | printSVERegOp<'d'>(MI, OpNum: 5, STI, O); |
| 23083 | return; |
| 23084 | break; |
| 23085 | case 22: |
| 23086 | // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... |
| 23087 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 23088 | return; |
| 23089 | break; |
| 23090 | case 23: |
| 23091 | // FMUL_ZPmI_D, FMUL_ZPmI_S |
| 23092 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, OpNum: 3, STI, O); |
| 23093 | return; |
| 23094 | break; |
| 23095 | case 24: |
| 23096 | // GLD1B_D_IMM, GLD1B_S_IMM, GLD1H_D_IMM, GLD1H_S_IMM, GLD1Q, GLD1SB_D_IM... |
| 23097 | O << ']'; |
| 23098 | return; |
| 23099 | break; |
| 23100 | case 25: |
| 23101 | // LD1B_2Z_IMM, LD1B_4Z_IMM, LD1B_4Z_STRIDED_IMM, LD1B_D_IMM, LD1B_H_IMM,... |
| 23102 | O << ", mul vl]"; |
| 23103 | return; |
| 23104 | break; |
| 23105 | case 26: |
| 23106 | // LDNPDi, LDNPXi, LDPDi, LDPXi, LDTNPXi, LDTPi, STNPDi, STNPXi, STPDi, S... |
| 23107 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 23108 | O << ']'; |
| 23109 | return; |
| 23110 | break; |
| 23111 | case 27: |
| 23112 | // LDNPQi, LDPQi, LDTNPQi, LDTPQi, STGPi, STNPQi, STPQi, STTNPQi, STTPQi |
| 23113 | printImmScale<16>(MI, OpNum: 3, STI, O); |
| 23114 | O << ']'; |
| 23115 | return; |
| 23116 | break; |
| 23117 | case 28: |
| 23118 | // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi |
| 23119 | printImmScale<4>(MI, OpNum: 3, STI, O); |
| 23120 | O << ']'; |
| 23121 | return; |
| 23122 | break; |
| 23123 | case 29: |
| 23124 | // LDPDpost, LDPDpre, LDPXpost, LDPXpre, LDTPpost, LDTPpre, STPDpost, STP... |
| 23125 | printImmScale<8>(MI, OpNum: 4, STI, O); |
| 23126 | break; |
| 23127 | case 30: |
| 23128 | // LDPQpost, LDPQpre, LDTPQpost, LDTPQpre, STGPpost, STGPpre, STPQpost, S... |
| 23129 | printImmScale<16>(MI, OpNum: 4, STI, O); |
| 23130 | break; |
| 23131 | case 31: |
| 23132 | // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... |
| 23133 | printImmScale<4>(MI, OpNum: 4, STI, O); |
| 23134 | break; |
| 23135 | case 32: |
| 23136 | // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW |
| 23137 | printMemExtend<'w', 8>(MI, OpNum: 3, STI, O); |
| 23138 | O << ']'; |
| 23139 | return; |
| 23140 | break; |
| 23141 | case 33: |
| 23142 | // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX |
| 23143 | printMemExtend<'x', 8>(MI, OpNum: 3, STI, O); |
| 23144 | O << ']'; |
| 23145 | return; |
| 23146 | break; |
| 23147 | case 34: |
| 23148 | // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW |
| 23149 | printMemExtend<'w', 64>(MI, OpNum: 3, STI, O); |
| 23150 | O << ']'; |
| 23151 | return; |
| 23152 | break; |
| 23153 | case 35: |
| 23154 | // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX |
| 23155 | printMemExtend<'x', 64>(MI, OpNum: 3, STI, O); |
| 23156 | O << ']'; |
| 23157 | return; |
| 23158 | break; |
| 23159 | case 36: |
| 23160 | // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW |
| 23161 | printMemExtend<'w', 16>(MI, OpNum: 3, STI, O); |
| 23162 | O << ']'; |
| 23163 | return; |
| 23164 | break; |
| 23165 | case 37: |
| 23166 | // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX |
| 23167 | printMemExtend<'x', 16>(MI, OpNum: 3, STI, O); |
| 23168 | O << ']'; |
| 23169 | return; |
| 23170 | break; |
| 23171 | case 38: |
| 23172 | // LDRQroW, STRQroW |
| 23173 | printMemExtend<'w', 128>(MI, OpNum: 3, STI, O); |
| 23174 | O << ']'; |
| 23175 | return; |
| 23176 | break; |
| 23177 | case 39: |
| 23178 | // LDRQroX, STRQroX |
| 23179 | printMemExtend<'x', 128>(MI, OpNum: 3, STI, O); |
| 23180 | O << ']'; |
| 23181 | return; |
| 23182 | break; |
| 23183 | case 40: |
| 23184 | // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW |
| 23185 | printMemExtend<'w', 32>(MI, OpNum: 3, STI, O); |
| 23186 | O << ']'; |
| 23187 | return; |
| 23188 | break; |
| 23189 | case 41: |
| 23190 | // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX |
| 23191 | printMemExtend<'x', 32>(MI, OpNum: 3, STI, O); |
| 23192 | O << ']'; |
| 23193 | return; |
| 23194 | break; |
| 23195 | case 42: |
| 23196 | // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B |
| 23197 | printSVERegOp<'b'>(MI, OpNum: 4, STI, O); |
| 23198 | return; |
| 23199 | break; |
| 23200 | case 43: |
| 23201 | // ST1B_2Z_STRIDED, STNT1B_2Z_STRIDED |
| 23202 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 23203 | O << ']'; |
| 23204 | return; |
| 23205 | break; |
| 23206 | case 44: |
| 23207 | // ST1B_2Z_STRIDED_IMM, ST1H_2Z_STRIDED_IMM, STNT1B_2Z_STRIDED_IMM, STNT1... |
| 23208 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 23209 | O << ", mul vl]"; |
| 23210 | return; |
| 23211 | break; |
| 23212 | case 45: |
| 23213 | // ST1H_2Z_STRIDED, STNT1H_2Z_STRIDED |
| 23214 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 23215 | O << ']'; |
| 23216 | return; |
| 23217 | break; |
| 23218 | case 46: |
| 23219 | // WHILEGE_CXX_B, WHILEGE_CXX_D, WHILEGE_CXX_H, WHILEGE_CXX_S, WHILEGT_CX... |
| 23220 | printSVEVecLenSpecifier(MI, OpNum: 3, STI, O); |
| 23221 | return; |
| 23222 | break; |
| 23223 | } |
| 23224 | |
| 23225 | switch (MI->getOpcode()) { |
| 23226 | default: llvm_unreachable("Unexpected opcode."); |
| 23227 | case AArch64::ADDP_ZPmZ_D: |
| 23228 | case AArch64::ADDP_ZPmZ_S: |
| 23229 | case AArch64::ADD_ZPmZ_CPA: |
| 23230 | case AArch64::ADD_ZPmZ_D: |
| 23231 | case AArch64::ADD_ZPmZ_S: |
| 23232 | case AArch64::AND_ZPmZ_D: |
| 23233 | case AArch64::AND_ZPmZ_S: |
| 23234 | case AArch64::ASRR_ZPmZ_D: |
| 23235 | case AArch64::ASRR_ZPmZ_S: |
| 23236 | case AArch64::ASR_WIDE_ZPmZ_B: |
| 23237 | case AArch64::ASR_WIDE_ZPmZ_S: |
| 23238 | case AArch64::ASR_ZPmZ_D: |
| 23239 | case AArch64::ASR_ZPmZ_S: |
| 23240 | case AArch64::BCAX_ZZZZ: |
| 23241 | case AArch64::BFMLALBIdx: |
| 23242 | case AArch64::BFMLALTIdx: |
| 23243 | case AArch64::BIC_ZPmZ_D: |
| 23244 | case AArch64::BIC_ZPmZ_S: |
| 23245 | case AArch64::BSL1N_ZZZZ: |
| 23246 | case AArch64::BSL2N_ZZZZ: |
| 23247 | case AArch64::BSL_ZZZZ: |
| 23248 | case AArch64::CLASTA_RPZ_D: |
| 23249 | case AArch64::CLASTA_RPZ_S: |
| 23250 | case AArch64::CLASTA_VPZ_D: |
| 23251 | case AArch64::CLASTA_VPZ_S: |
| 23252 | case AArch64::CLASTA_ZPZ_D: |
| 23253 | case AArch64::CLASTA_ZPZ_S: |
| 23254 | case AArch64::CLASTB_RPZ_D: |
| 23255 | case AArch64::CLASTB_RPZ_S: |
| 23256 | case AArch64::CLASTB_VPZ_D: |
| 23257 | case AArch64::CLASTB_VPZ_S: |
| 23258 | case AArch64::CLASTB_ZPZ_D: |
| 23259 | case AArch64::CLASTB_ZPZ_S: |
| 23260 | case AArch64::CMPEQ_PPzZZ_D: |
| 23261 | case AArch64::CMPEQ_PPzZZ_S: |
| 23262 | case AArch64::CMPEQ_WIDE_PPzZZ_B: |
| 23263 | case AArch64::CMPEQ_WIDE_PPzZZ_S: |
| 23264 | case AArch64::CMPGE_PPzZZ_D: |
| 23265 | case AArch64::CMPGE_PPzZZ_S: |
| 23266 | case AArch64::CMPGE_WIDE_PPzZZ_B: |
| 23267 | case AArch64::CMPGE_WIDE_PPzZZ_S: |
| 23268 | case AArch64::CMPGT_PPzZZ_D: |
| 23269 | case AArch64::CMPGT_PPzZZ_S: |
| 23270 | case AArch64::CMPGT_WIDE_PPzZZ_B: |
| 23271 | case AArch64::CMPGT_WIDE_PPzZZ_S: |
| 23272 | case AArch64::CMPHI_PPzZZ_D: |
| 23273 | case AArch64::CMPHI_PPzZZ_S: |
| 23274 | case AArch64::CMPHI_WIDE_PPzZZ_B: |
| 23275 | case AArch64::CMPHI_WIDE_PPzZZ_S: |
| 23276 | case AArch64::CMPHS_PPzZZ_D: |
| 23277 | case AArch64::CMPHS_PPzZZ_S: |
| 23278 | case AArch64::CMPHS_WIDE_PPzZZ_B: |
| 23279 | case AArch64::CMPHS_WIDE_PPzZZ_S: |
| 23280 | case AArch64::CMPLE_WIDE_PPzZZ_B: |
| 23281 | case AArch64::CMPLE_WIDE_PPzZZ_S: |
| 23282 | case AArch64::CMPLO_WIDE_PPzZZ_B: |
| 23283 | case AArch64::CMPLO_WIDE_PPzZZ_S: |
| 23284 | case AArch64::CMPLS_WIDE_PPzZZ_B: |
| 23285 | case AArch64::CMPLS_WIDE_PPzZZ_S: |
| 23286 | case AArch64::CMPLT_WIDE_PPzZZ_B: |
| 23287 | case AArch64::CMPLT_WIDE_PPzZZ_S: |
| 23288 | case AArch64::CMPNE_PPzZZ_D: |
| 23289 | case AArch64::CMPNE_PPzZZ_S: |
| 23290 | case AArch64::CMPNE_WIDE_PPzZZ_B: |
| 23291 | case AArch64::CMPNE_WIDE_PPzZZ_S: |
| 23292 | case AArch64::EOR3_ZZZZ: |
| 23293 | case AArch64::EOR_ZPmZ_D: |
| 23294 | case AArch64::EOR_ZPmZ_S: |
| 23295 | case AArch64::FABD_ZPmZ_D: |
| 23296 | case AArch64::FABD_ZPmZ_S: |
| 23297 | case AArch64::FACGE_PPzZZ_D: |
| 23298 | case AArch64::FACGE_PPzZZ_S: |
| 23299 | case AArch64::FACGT_PPzZZ_D: |
| 23300 | case AArch64::FACGT_PPzZZ_S: |
| 23301 | case AArch64::FADDP_ZPmZZ_D: |
| 23302 | case AArch64::FADDP_ZPmZZ_S: |
| 23303 | case AArch64::FADD_ZPmZ_D: |
| 23304 | case AArch64::FADD_ZPmZ_S: |
| 23305 | case AArch64::FAMAX_ZPmZ_D: |
| 23306 | case AArch64::FAMAX_ZPmZ_S: |
| 23307 | case AArch64::FAMIN_ZPmZ_D: |
| 23308 | case AArch64::FAMIN_ZPmZ_S: |
| 23309 | case AArch64::FCMEQ_PPzZZ_D: |
| 23310 | case AArch64::FCMEQ_PPzZZ_S: |
| 23311 | case AArch64::FCMGE_PPzZZ_D: |
| 23312 | case AArch64::FCMGE_PPzZZ_S: |
| 23313 | case AArch64::FCMGT_PPzZZ_D: |
| 23314 | case AArch64::FCMGT_PPzZZ_S: |
| 23315 | case AArch64::FCMNE_PPzZZ_D: |
| 23316 | case AArch64::FCMNE_PPzZZ_S: |
| 23317 | case AArch64::FCMUO_PPzZZ_D: |
| 23318 | case AArch64::FCMUO_PPzZZ_S: |
| 23319 | case AArch64::FDIVR_ZPmZ_D: |
| 23320 | case AArch64::FDIVR_ZPmZ_S: |
| 23321 | case AArch64::FDIV_ZPmZ_D: |
| 23322 | case AArch64::FDIV_ZPmZ_S: |
| 23323 | case AArch64::FMAD_ZPmZZ_D: |
| 23324 | case AArch64::FMAD_ZPmZZ_S: |
| 23325 | case AArch64::FMAXNMP_ZPmZZ_D: |
| 23326 | case AArch64::FMAXNMP_ZPmZZ_S: |
| 23327 | case AArch64::FMAXNM_ZPmZ_D: |
| 23328 | case AArch64::FMAXNM_ZPmZ_S: |
| 23329 | case AArch64::FMAXP_ZPmZZ_D: |
| 23330 | case AArch64::FMAXP_ZPmZZ_S: |
| 23331 | case AArch64::FMAX_ZPmZ_D: |
| 23332 | case AArch64::FMAX_ZPmZ_S: |
| 23333 | case AArch64::FMINNMP_ZPmZZ_D: |
| 23334 | case AArch64::FMINNMP_ZPmZZ_S: |
| 23335 | case AArch64::FMINNM_ZPmZ_D: |
| 23336 | case AArch64::FMINNM_ZPmZ_S: |
| 23337 | case AArch64::FMINP_ZPmZZ_D: |
| 23338 | case AArch64::FMINP_ZPmZZ_S: |
| 23339 | case AArch64::FMIN_ZPmZ_D: |
| 23340 | case AArch64::FMIN_ZPmZ_S: |
| 23341 | case AArch64::FMLAL2lanev8f16: |
| 23342 | case AArch64::FMLALlanev8f16: |
| 23343 | case AArch64::FMLA_ZPmZZ_D: |
| 23344 | case AArch64::FMLA_ZPmZZ_S: |
| 23345 | case AArch64::FMLAv1i16_indexed: |
| 23346 | case AArch64::FMLAv1i32_indexed: |
| 23347 | case AArch64::FMLAv1i64_indexed: |
| 23348 | case AArch64::FMLAv2i32_indexed: |
| 23349 | case AArch64::FMLAv2i64_indexed: |
| 23350 | case AArch64::FMLAv4i16_indexed: |
| 23351 | case AArch64::FMLAv4i32_indexed: |
| 23352 | case AArch64::FMLAv8i16_indexed: |
| 23353 | case AArch64::FMLSL2lanev8f16: |
| 23354 | case AArch64::FMLSLlanev8f16: |
| 23355 | case AArch64::FMLS_ZPmZZ_D: |
| 23356 | case AArch64::FMLS_ZPmZZ_S: |
| 23357 | case AArch64::FMLSv1i16_indexed: |
| 23358 | case AArch64::FMLSv1i32_indexed: |
| 23359 | case AArch64::FMLSv1i64_indexed: |
| 23360 | case AArch64::FMLSv2i32_indexed: |
| 23361 | case AArch64::FMLSv2i64_indexed: |
| 23362 | case AArch64::FMLSv4i16_indexed: |
| 23363 | case AArch64::FMLSv4i32_indexed: |
| 23364 | case AArch64::FMLSv8i16_indexed: |
| 23365 | case AArch64::FMSB_ZPmZZ_D: |
| 23366 | case AArch64::FMSB_ZPmZZ_S: |
| 23367 | case AArch64::FMULX_ZPmZ_D: |
| 23368 | case AArch64::FMULX_ZPmZ_S: |
| 23369 | case AArch64::FMUL_ZPmZ_D: |
| 23370 | case AArch64::FMUL_ZPmZ_S: |
| 23371 | case AArch64::FNMAD_ZPmZZ_D: |
| 23372 | case AArch64::FNMAD_ZPmZZ_S: |
| 23373 | case AArch64::FNMLA_ZPmZZ_D: |
| 23374 | case AArch64::FNMLA_ZPmZZ_S: |
| 23375 | case AArch64::FNMLS_ZPmZZ_D: |
| 23376 | case AArch64::FNMLS_ZPmZZ_S: |
| 23377 | case AArch64::FNMSB_ZPmZZ_D: |
| 23378 | case AArch64::FNMSB_ZPmZZ_S: |
| 23379 | case AArch64::FSCALE_ZPmZ_D: |
| 23380 | case AArch64::FSCALE_ZPmZ_S: |
| 23381 | case AArch64::FSUBR_ZPmZ_D: |
| 23382 | case AArch64::FSUBR_ZPmZ_S: |
| 23383 | case AArch64::FSUB_ZPmZ_D: |
| 23384 | case AArch64::FSUB_ZPmZ_S: |
| 23385 | case AArch64::HISTCNT_ZPzZZ_D: |
| 23386 | case AArch64::HISTCNT_ZPzZZ_S: |
| 23387 | case AArch64::LDPDpost: |
| 23388 | case AArch64::LDPQpost: |
| 23389 | case AArch64::LDPSWpost: |
| 23390 | case AArch64::LDPSpost: |
| 23391 | case AArch64::LDPWpost: |
| 23392 | case AArch64::LDPXpost: |
| 23393 | case AArch64::LDTPQpost: |
| 23394 | case AArch64::LDTPpost: |
| 23395 | case AArch64::LSLR_ZPmZ_D: |
| 23396 | case AArch64::LSLR_ZPmZ_S: |
| 23397 | case AArch64::LSL_WIDE_ZPmZ_B: |
| 23398 | case AArch64::LSL_WIDE_ZPmZ_S: |
| 23399 | case AArch64::LSL_ZPmZ_D: |
| 23400 | case AArch64::LSL_ZPmZ_S: |
| 23401 | case AArch64::LSRR_ZPmZ_D: |
| 23402 | case AArch64::LSRR_ZPmZ_S: |
| 23403 | case AArch64::LSR_WIDE_ZPmZ_B: |
| 23404 | case AArch64::LSR_WIDE_ZPmZ_S: |
| 23405 | case AArch64::LSR_ZPmZ_D: |
| 23406 | case AArch64::LSR_ZPmZ_S: |
| 23407 | case AArch64::MAD_ZPmZZ_D: |
| 23408 | case AArch64::MAD_ZPmZZ_S: |
| 23409 | case AArch64::MLA_ZPmZZ_D: |
| 23410 | case AArch64::MLA_ZPmZZ_S: |
| 23411 | case AArch64::MLAv2i32_indexed: |
| 23412 | case AArch64::MLAv4i16_indexed: |
| 23413 | case AArch64::MLAv4i32_indexed: |
| 23414 | case AArch64::MLAv8i16_indexed: |
| 23415 | case AArch64::MLS_ZPmZZ_D: |
| 23416 | case AArch64::MLS_ZPmZZ_S: |
| 23417 | case AArch64::MLSv2i32_indexed: |
| 23418 | case AArch64::MLSv4i16_indexed: |
| 23419 | case AArch64::MLSv4i32_indexed: |
| 23420 | case AArch64::MLSv8i16_indexed: |
| 23421 | case AArch64::MSB_ZPmZZ_D: |
| 23422 | case AArch64::MSB_ZPmZZ_S: |
| 23423 | case AArch64::MUL_ZPmZ_D: |
| 23424 | case AArch64::MUL_ZPmZ_S: |
| 23425 | case AArch64::NBSL_ZZZZ: |
| 23426 | case AArch64::ORR_ZPmZ_D: |
| 23427 | case AArch64::ORR_ZPmZ_S: |
| 23428 | case AArch64::SABD_ZPmZ_D: |
| 23429 | case AArch64::SABD_ZPmZ_S: |
| 23430 | case AArch64::SDIVR_ZPmZ_D: |
| 23431 | case AArch64::SDIVR_ZPmZ_S: |
| 23432 | case AArch64::SDIV_ZPmZ_D: |
| 23433 | case AArch64::SDIV_ZPmZ_S: |
| 23434 | case AArch64::SEL_ZPZZ_D: |
| 23435 | case AArch64::SEL_ZPZZ_S: |
| 23436 | case AArch64::SHADD_ZPmZ_D: |
| 23437 | case AArch64::SHADD_ZPmZ_S: |
| 23438 | case AArch64::SHSUBR_ZPmZ_D: |
| 23439 | case AArch64::SHSUBR_ZPmZ_S: |
| 23440 | case AArch64::SHSUB_ZPmZ_D: |
| 23441 | case AArch64::SHSUB_ZPmZ_S: |
| 23442 | case AArch64::SM3TT1A: |
| 23443 | case AArch64::SM3TT1B: |
| 23444 | case AArch64::SM3TT2A: |
| 23445 | case AArch64::SM3TT2B: |
| 23446 | case AArch64::SMAXP_ZPmZ_D: |
| 23447 | case AArch64::SMAXP_ZPmZ_S: |
| 23448 | case AArch64::SMAX_ZPmZ_D: |
| 23449 | case AArch64::SMAX_ZPmZ_S: |
| 23450 | case AArch64::SMINP_ZPmZ_D: |
| 23451 | case AArch64::SMINP_ZPmZ_S: |
| 23452 | case AArch64::SMIN_ZPmZ_D: |
| 23453 | case AArch64::SMIN_ZPmZ_S: |
| 23454 | case AArch64::SMLALv2i32_indexed: |
| 23455 | case AArch64::SMLALv4i16_indexed: |
| 23456 | case AArch64::SMLALv4i32_indexed: |
| 23457 | case AArch64::SMLALv8i16_indexed: |
| 23458 | case AArch64::SMLSLv2i32_indexed: |
| 23459 | case AArch64::SMLSLv4i16_indexed: |
| 23460 | case AArch64::SMLSLv4i32_indexed: |
| 23461 | case AArch64::SMLSLv8i16_indexed: |
| 23462 | case AArch64::SMULH_ZPmZ_D: |
| 23463 | case AArch64::SMULH_ZPmZ_S: |
| 23464 | case AArch64::SPLICE_ZPZ_D: |
| 23465 | case AArch64::SPLICE_ZPZ_S: |
| 23466 | case AArch64::SQADD_ZPmZ_D: |
| 23467 | case AArch64::SQADD_ZPmZ_S: |
| 23468 | case AArch64::SQDMLALv1i32_indexed: |
| 23469 | case AArch64::SQDMLALv1i64_indexed: |
| 23470 | case AArch64::SQDMLALv2i32_indexed: |
| 23471 | case AArch64::SQDMLALv4i16_indexed: |
| 23472 | case AArch64::SQDMLALv4i32_indexed: |
| 23473 | case AArch64::SQDMLALv8i16_indexed: |
| 23474 | case AArch64::SQDMLSLv1i32_indexed: |
| 23475 | case AArch64::SQDMLSLv1i64_indexed: |
| 23476 | case AArch64::SQDMLSLv2i32_indexed: |
| 23477 | case AArch64::SQDMLSLv4i16_indexed: |
| 23478 | case AArch64::SQDMLSLv4i32_indexed: |
| 23479 | case AArch64::SQDMLSLv8i16_indexed: |
| 23480 | case AArch64::SQRDMLAHv1i16_indexed: |
| 23481 | case AArch64::SQRDMLAHv1i32_indexed: |
| 23482 | case AArch64::SQRDMLAHv2i32_indexed: |
| 23483 | case AArch64::SQRDMLAHv4i16_indexed: |
| 23484 | case AArch64::SQRDMLAHv4i32_indexed: |
| 23485 | case AArch64::SQRDMLAHv8i16_indexed: |
| 23486 | case AArch64::SQRDMLSHv1i16_indexed: |
| 23487 | case AArch64::SQRDMLSHv1i32_indexed: |
| 23488 | case AArch64::SQRDMLSHv2i32_indexed: |
| 23489 | case AArch64::SQRDMLSHv4i16_indexed: |
| 23490 | case AArch64::SQRDMLSHv4i32_indexed: |
| 23491 | case AArch64::SQRDMLSHv8i16_indexed: |
| 23492 | case AArch64::SQRSHLR_ZPmZ_D: |
| 23493 | case AArch64::SQRSHLR_ZPmZ_S: |
| 23494 | case AArch64::SQRSHL_ZPmZ_D: |
| 23495 | case AArch64::SQRSHL_ZPmZ_S: |
| 23496 | case AArch64::SQSHLR_ZPmZ_D: |
| 23497 | case AArch64::SQSHLR_ZPmZ_S: |
| 23498 | case AArch64::SQSHL_ZPmZ_D: |
| 23499 | case AArch64::SQSHL_ZPmZ_S: |
| 23500 | case AArch64::SQSUBR_ZPmZ_D: |
| 23501 | case AArch64::SQSUBR_ZPmZ_S: |
| 23502 | case AArch64::SQSUB_ZPmZ_D: |
| 23503 | case AArch64::SQSUB_ZPmZ_S: |
| 23504 | case AArch64::SRHADD_ZPmZ_D: |
| 23505 | case AArch64::SRHADD_ZPmZ_S: |
| 23506 | case AArch64::SRSHLR_ZPmZ_D: |
| 23507 | case AArch64::SRSHLR_ZPmZ_S: |
| 23508 | case AArch64::SRSHL_ZPmZ_D: |
| 23509 | case AArch64::SRSHL_ZPmZ_S: |
| 23510 | case AArch64::STGPpost: |
| 23511 | case AArch64::STPDpost: |
| 23512 | case AArch64::STPQpost: |
| 23513 | case AArch64::STPSpost: |
| 23514 | case AArch64::STPWpost: |
| 23515 | case AArch64::STPXpost: |
| 23516 | case AArch64::STTPQpost: |
| 23517 | case AArch64::STTPpost: |
| 23518 | case AArch64::SUBP_ZPmZZ_D: |
| 23519 | case AArch64::SUBP_ZPmZZ_S: |
| 23520 | case AArch64::SUBR_ZPmZ_D: |
| 23521 | case AArch64::SUBR_ZPmZ_S: |
| 23522 | case AArch64::SUB_ZPmZ_CPA: |
| 23523 | case AArch64::SUB_ZPmZ_D: |
| 23524 | case AArch64::SUB_ZPmZ_S: |
| 23525 | case AArch64::SUQADD_ZPmZ_D: |
| 23526 | case AArch64::SUQADD_ZPmZ_S: |
| 23527 | case AArch64::UABD_ZPmZ_D: |
| 23528 | case AArch64::UABD_ZPmZ_S: |
| 23529 | case AArch64::UDIVR_ZPmZ_D: |
| 23530 | case AArch64::UDIVR_ZPmZ_S: |
| 23531 | case AArch64::UDIV_ZPmZ_D: |
| 23532 | case AArch64::UDIV_ZPmZ_S: |
| 23533 | case AArch64::UHADD_ZPmZ_D: |
| 23534 | case AArch64::UHADD_ZPmZ_S: |
| 23535 | case AArch64::UHSUBR_ZPmZ_D: |
| 23536 | case AArch64::UHSUBR_ZPmZ_S: |
| 23537 | case AArch64::UHSUB_ZPmZ_D: |
| 23538 | case AArch64::UHSUB_ZPmZ_S: |
| 23539 | case AArch64::UMAXP_ZPmZ_D: |
| 23540 | case AArch64::UMAXP_ZPmZ_S: |
| 23541 | case AArch64::UMAX_ZPmZ_D: |
| 23542 | case AArch64::UMAX_ZPmZ_S: |
| 23543 | case AArch64::UMINP_ZPmZ_D: |
| 23544 | case AArch64::UMINP_ZPmZ_S: |
| 23545 | case AArch64::UMIN_ZPmZ_D: |
| 23546 | case AArch64::UMIN_ZPmZ_S: |
| 23547 | case AArch64::UMLALv2i32_indexed: |
| 23548 | case AArch64::UMLALv4i16_indexed: |
| 23549 | case AArch64::UMLALv4i32_indexed: |
| 23550 | case AArch64::UMLALv8i16_indexed: |
| 23551 | case AArch64::UMLSLv2i32_indexed: |
| 23552 | case AArch64::UMLSLv4i16_indexed: |
| 23553 | case AArch64::UMLSLv4i32_indexed: |
| 23554 | case AArch64::UMLSLv8i16_indexed: |
| 23555 | case AArch64::UMULH_ZPmZ_D: |
| 23556 | case AArch64::UMULH_ZPmZ_S: |
| 23557 | case AArch64::UQADD_ZPmZ_D: |
| 23558 | case AArch64::UQADD_ZPmZ_S: |
| 23559 | case AArch64::UQRSHLR_ZPmZ_D: |
| 23560 | case AArch64::UQRSHLR_ZPmZ_S: |
| 23561 | case AArch64::UQRSHL_ZPmZ_D: |
| 23562 | case AArch64::UQRSHL_ZPmZ_S: |
| 23563 | case AArch64::UQSHLR_ZPmZ_D: |
| 23564 | case AArch64::UQSHLR_ZPmZ_S: |
| 23565 | case AArch64::UQSHL_ZPmZ_D: |
| 23566 | case AArch64::UQSHL_ZPmZ_S: |
| 23567 | case AArch64::UQSUBR_ZPmZ_D: |
| 23568 | case AArch64::UQSUBR_ZPmZ_S: |
| 23569 | case AArch64::UQSUB_ZPmZ_D: |
| 23570 | case AArch64::UQSUB_ZPmZ_S: |
| 23571 | case AArch64::URHADD_ZPmZ_D: |
| 23572 | case AArch64::URHADD_ZPmZ_S: |
| 23573 | case AArch64::URSHLR_ZPmZ_D: |
| 23574 | case AArch64::URSHLR_ZPmZ_S: |
| 23575 | case AArch64::URSHL_ZPmZ_D: |
| 23576 | case AArch64::URSHL_ZPmZ_S: |
| 23577 | case AArch64::USQADD_ZPmZ_D: |
| 23578 | case AArch64::USQADD_ZPmZ_S: |
| 23579 | return; |
| 23580 | break; |
| 23581 | case AArch64::BCAX: |
| 23582 | case AArch64::CDOT_ZZZI_D: |
| 23583 | case AArch64::CMLA_ZZZI_S: |
| 23584 | case AArch64::EOR3: |
| 23585 | case AArch64::FCADD_ZPmZ_H: |
| 23586 | case AArch64::FCMLA_ZPmZZ_H: |
| 23587 | case AArch64::FCMLA_ZZZI_S: |
| 23588 | case AArch64::LDPDpre: |
| 23589 | case AArch64::LDPQpre: |
| 23590 | case AArch64::LDPSWpre: |
| 23591 | case AArch64::LDPSpre: |
| 23592 | case AArch64::LDPWpre: |
| 23593 | case AArch64::LDPXpre: |
| 23594 | case AArch64::LDTPQpre: |
| 23595 | case AArch64::LDTPpre: |
| 23596 | case AArch64::SM3SS1: |
| 23597 | case AArch64::SQRDCMLAH_ZZZI_S: |
| 23598 | case AArch64::STGPpre: |
| 23599 | case AArch64::STPDpre: |
| 23600 | case AArch64::STPQpre: |
| 23601 | case AArch64::STPSpre: |
| 23602 | case AArch64::STPWpre: |
| 23603 | case AArch64::STPXpre: |
| 23604 | case AArch64::STTPQpre: |
| 23605 | case AArch64::STTPpre: |
| 23606 | switch (MI->getOpcode()) { |
| 23607 | default: llvm_unreachable("Unexpected opcode."); |
| 23608 | case AArch64::BCAX: |
| 23609 | case AArch64::EOR3: |
| 23610 | O << ".16b"; |
| 23611 | break; |
| 23612 | case AArch64::CDOT_ZZZI_D: |
| 23613 | case AArch64::CMLA_ZZZI_S: |
| 23614 | case AArch64::FCMLA_ZPmZZ_H: |
| 23615 | case AArch64::FCMLA_ZZZI_S: |
| 23616 | case AArch64::SQRDCMLAH_ZZZI_S: |
| 23617 | printComplexRotationOp<90, 0>(MI, OpNo: 5, STI, O); |
| 23618 | break; |
| 23619 | case AArch64::FCADD_ZPmZ_H: |
| 23620 | printComplexRotationOp<180, 90>(MI, OpNo: 4, STI, O); |
| 23621 | break; |
| 23622 | case AArch64::LDPDpre: |
| 23623 | case AArch64::LDPQpre: |
| 23624 | case AArch64::LDPSWpre: |
| 23625 | case AArch64::LDPSpre: |
| 23626 | case AArch64::LDPWpre: |
| 23627 | case AArch64::LDPXpre: |
| 23628 | case AArch64::LDTPQpre: |
| 23629 | case AArch64::LDTPpre: |
| 23630 | case AArch64::STGPpre: |
| 23631 | case AArch64::STPDpre: |
| 23632 | case AArch64::STPQpre: |
| 23633 | case AArch64::STPSpre: |
| 23634 | case AArch64::STPWpre: |
| 23635 | case AArch64::STPXpre: |
| 23636 | case AArch64::STTPQpre: |
| 23637 | case AArch64::STTPpre: |
| 23638 | O << "]!"; |
| 23639 | break; |
| 23640 | case AArch64::SM3SS1: |
| 23641 | O << ".4s"; |
| 23642 | break; |
| 23643 | } |
| 23644 | return; |
| 23645 | break; |
| 23646 | case AArch64::FCADD_ZPmZ_D: |
| 23647 | case AArch64::FCADD_ZPmZ_S: |
| 23648 | case AArch64::FCMLA_ZPmZZ_D: |
| 23649 | case AArch64::FCMLA_ZPmZZ_S: |
| 23650 | case AArch64::FCMLAv4f16_indexed: |
| 23651 | case AArch64::FCMLAv4f32_indexed: |
| 23652 | case AArch64::FCMLAv8f16_indexed: |
| 23653 | O << ", "; |
| 23654 | switch (MI->getOpcode()) { |
| 23655 | default: llvm_unreachable("Unexpected opcode."); |
| 23656 | case AArch64::FCADD_ZPmZ_D: |
| 23657 | case AArch64::FCADD_ZPmZ_S: |
| 23658 | printComplexRotationOp<180, 90>(MI, OpNo: 4, STI, O); |
| 23659 | break; |
| 23660 | case AArch64::FCMLA_ZPmZZ_D: |
| 23661 | case AArch64::FCMLA_ZPmZZ_S: |
| 23662 | case AArch64::FCMLAv4f16_indexed: |
| 23663 | case AArch64::FCMLAv4f32_indexed: |
| 23664 | case AArch64::FCMLAv8f16_indexed: |
| 23665 | printComplexRotationOp<90, 0>(MI, OpNo: 5, STI, O); |
| 23666 | break; |
| 23667 | } |
| 23668 | return; |
| 23669 | break; |
| 23670 | } |
| 23671 | } |
| 23672 | |
| 23673 | |
| 23674 | /// getRegisterName - This method is automatically generated by tblgen |
| 23675 | /// from the register set description. This returns the assembler name |
| 23676 | /// for the specified register. |
| 23677 | const char *AArch64InstPrinter:: |
| 23678 | getRegisterName(MCRegister Reg, unsigned AltIdx) { |
| 23679 | unsigned RegNo = Reg.id(); |
| 23680 | assert(RegNo && RegNo < 895 && "Invalid register number!"); |
| 23681 | |
| 23682 | |
| 23683 | #ifdef __GNUC__ |
| 23684 | #pragma GCC diagnostic push |
| 23685 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 23686 | #endif |
| 23687 | static const char AsmStrsNoRegAltName[] = { |
| 23688 | /* 0 */ "D7_D8_D9_D10\000" |
| 23689 | /* 13 */ "P9_P10\000" |
| 23690 | /* 20 */ "Q7_Q8_Q9_Q10\000" |
| 23691 | /* 33 */ "Z2_Z10\000" |
| 23692 | /* 40 */ "Z7_Z8_Z9_Z10\000" |
| 23693 | /* 53 */ "b10\000" |
| 23694 | /* 57 */ "d10\000" |
| 23695 | /* 61 */ "h10\000" |
| 23696 | /* 65 */ "pn10\000" |
| 23697 | /* 70 */ "p10\000" |
| 23698 | /* 74 */ "q10\000" |
| 23699 | /* 78 */ "s10\000" |
| 23700 | /* 82 */ "w10\000" |
| 23701 | /* 86 */ "x10\000" |
| 23702 | /* 90 */ "z10\000" |
| 23703 | /* 94 */ "D17_D18_D19_D20\000" |
| 23704 | /* 110 */ "Q17_Q18_Q19_Q20\000" |
| 23705 | /* 126 */ "Z17_Z18_Z19_Z20\000" |
| 23706 | /* 142 */ "b20\000" |
| 23707 | /* 146 */ "d20\000" |
| 23708 | /* 150 */ "h20\000" |
| 23709 | /* 154 */ "q20\000" |
| 23710 | /* 158 */ "s20\000" |
| 23711 | /* 162 */ "w20\000" |
| 23712 | /* 166 */ "x20\000" |
| 23713 | /* 170 */ "z20\000" |
| 23714 | /* 174 */ "D27_D28_D29_D30\000" |
| 23715 | /* 190 */ "Q27_Q28_Q29_Q30\000" |
| 23716 | /* 206 */ "Z22_Z30\000" |
| 23717 | /* 214 */ "Z18_Z22_Z26_Z30\000" |
| 23718 | /* 230 */ "Z27_Z28_Z29_Z30\000" |
| 23719 | /* 246 */ "b30\000" |
| 23720 | /* 250 */ "d30\000" |
| 23721 | /* 254 */ "h30\000" |
| 23722 | /* 258 */ "q30\000" |
| 23723 | /* 262 */ "s30\000" |
| 23724 | /* 266 */ "w30\000" |
| 23725 | /* 270 */ "x30\000" |
| 23726 | /* 274 */ "z30\000" |
| 23727 | /* 278 */ "D29_D30_D31_D0\000" |
| 23728 | /* 293 */ "P15_P0\000" |
| 23729 | /* 300 */ "Q29_Q30_Q31_Q0\000" |
| 23730 | /* 315 */ "Z29_Z30_Z31_Z0\000" |
| 23731 | /* 330 */ "b0\000" |
| 23732 | /* 333 */ "d0\000" |
| 23733 | /* 336 */ "h0\000" |
| 23734 | /* 339 */ "pn0\000" |
| 23735 | /* 343 */ "p0\000" |
| 23736 | /* 346 */ "q0\000" |
| 23737 | /* 349 */ "s0\000" |
| 23738 | /* 352 */ "zt0\000" |
| 23739 | /* 356 */ "w0\000" |
| 23740 | /* 359 */ "x0\000" |
| 23741 | /* 362 */ "z0\000" |
| 23742 | /* 365 */ "D8_D9_D10_D11\000" |
| 23743 | /* 379 */ "P10_P11\000" |
| 23744 | /* 387 */ "Q8_Q9_Q10_Q11\000" |
| 23745 | /* 401 */ "W10_W11\000" |
| 23746 | /* 409 */ "X4_X5_X6_X7_X8_X9_X10_X11\000" |
| 23747 | /* 435 */ "Z8_Z9_Z10_Z11\000" |
| 23748 | /* 449 */ "Z3_Z11\000" |
| 23749 | /* 456 */ "b11\000" |
| 23750 | /* 460 */ "d11\000" |
| 23751 | /* 464 */ "h11\000" |
| 23752 | /* 468 */ "pn11\000" |
| 23753 | /* 473 */ "p11\000" |
| 23754 | /* 477 */ "q11\000" |
| 23755 | /* 481 */ "s11\000" |
| 23756 | /* 485 */ "w11\000" |
| 23757 | /* 489 */ "x11\000" |
| 23758 | /* 493 */ "z11\000" |
| 23759 | /* 497 */ "D18_D19_D20_D21\000" |
| 23760 | /* 513 */ "Q18_Q19_Q20_Q21\000" |
| 23761 | /* 529 */ "W20_W21\000" |
| 23762 | /* 537 */ "X14_X15_X16_X17_X18_X19_X20_X21\000" |
| 23763 | /* 569 */ "Z18_Z19_Z20_Z21\000" |
| 23764 | /* 585 */ "b21\000" |
| 23765 | /* 589 */ "d21\000" |
| 23766 | /* 593 */ "h21\000" |
| 23767 | /* 597 */ "q21\000" |
| 23768 | /* 601 */ "s21\000" |
| 23769 | /* 605 */ "w21\000" |
| 23770 | /* 609 */ "x21\000" |
| 23771 | /* 613 */ "z21\000" |
| 23772 | /* 617 */ "D28_D29_D30_D31\000" |
| 23773 | /* 633 */ "Q28_Q29_Q30_Q31\000" |
| 23774 | /* 649 */ "Z28_Z29_Z30_Z31\000" |
| 23775 | /* 665 */ "Z23_Z31\000" |
| 23776 | /* 673 */ "Z19_Z23_Z27_Z31\000" |
| 23777 | /* 689 */ "b31\000" |
| 23778 | /* 693 */ "d31\000" |
| 23779 | /* 697 */ "h31\000" |
| 23780 | /* 701 */ "q31\000" |
| 23781 | /* 705 */ "s31\000" |
| 23782 | /* 709 */ "z31\000" |
| 23783 | /* 713 */ "D30_D31_D0_D1\000" |
| 23784 | /* 727 */ "P0_P1\000" |
| 23785 | /* 733 */ "Q30_Q31_Q0_Q1\000" |
| 23786 | /* 747 */ "W0_W1\000" |
| 23787 | /* 753 */ "X0_X1\000" |
| 23788 | /* 759 */ "Z30_Z31_Z0_Z1\000" |
| 23789 | /* 773 */ "b1\000" |
| 23790 | /* 776 */ "d1\000" |
| 23791 | /* 779 */ "h1\000" |
| 23792 | /* 782 */ "pn1\000" |
| 23793 | /* 786 */ "p1\000" |
| 23794 | /* 789 */ "q1\000" |
| 23795 | /* 792 */ "s1\000" |
| 23796 | /* 795 */ "w1\000" |
| 23797 | /* 798 */ "x1\000" |
| 23798 | /* 801 */ "z1\000" |
| 23799 | /* 804 */ "D9_D10_D11_D12\000" |
| 23800 | /* 819 */ "P11_P12\000" |
| 23801 | /* 827 */ "Q9_Q10_Q11_Q12\000" |
| 23802 | /* 842 */ "Z9_Z10_Z11_Z12\000" |
| 23803 | /* 857 */ "Z4_Z12\000" |
| 23804 | /* 864 */ "Z0_Z4_Z8_Z12\000" |
| 23805 | /* 877 */ "b12\000" |
| 23806 | /* 881 */ "d12\000" |
| 23807 | /* 885 */ "h12\000" |
| 23808 | /* 889 */ "pn12\000" |
| 23809 | /* 894 */ "p12\000" |
| 23810 | /* 898 */ "q12\000" |
| 23811 | /* 902 */ "s12\000" |
| 23812 | /* 906 */ "w12\000" |
| 23813 | /* 910 */ "x12\000" |
| 23814 | /* 914 */ "z12\000" |
| 23815 | /* 918 */ "D19_D20_D21_D22\000" |
| 23816 | /* 934 */ "Q19_Q20_Q21_Q22\000" |
| 23817 | /* 950 */ "Z19_Z20_Z21_Z22\000" |
| 23818 | /* 966 */ "b22\000" |
| 23819 | /* 970 */ "d22\000" |
| 23820 | /* 974 */ "h22\000" |
| 23821 | /* 978 */ "q22\000" |
| 23822 | /* 982 */ "s22\000" |
| 23823 | /* 986 */ "w22\000" |
| 23824 | /* 990 */ "x22\000" |
| 23825 | /* 994 */ "z22\000" |
| 23826 | /* 998 */ "D31_D0_D1_D2\000" |
| 23827 | /* 1011 */ "P1_P2\000" |
| 23828 | /* 1017 */ "Q31_Q0_Q1_Q2\000" |
| 23829 | /* 1030 */ "Z31_Z0_Z1_Z2\000" |
| 23830 | /* 1043 */ "b2\000" |
| 23831 | /* 1046 */ "d2\000" |
| 23832 | /* 1049 */ "h2\000" |
| 23833 | /* 1052 */ "pn2\000" |
| 23834 | /* 1056 */ "p2\000" |
| 23835 | /* 1059 */ "q2\000" |
| 23836 | /* 1062 */ "s2\000" |
| 23837 | /* 1065 */ "w2\000" |
| 23838 | /* 1068 */ "x2\000" |
| 23839 | /* 1071 */ "z2\000" |
| 23840 | /* 1074 */ "D10_D11_D12_D13\000" |
| 23841 | /* 1090 */ "P12_P13\000" |
| 23842 | /* 1098 */ "Q10_Q11_Q12_Q13\000" |
| 23843 | /* 1114 */ "W12_W13\000" |
| 23844 | /* 1122 */ "X6_X7_X8_X9_X10_X11_X12_X13\000" |
| 23845 | /* 1150 */ "Z10_Z11_Z12_Z13\000" |
| 23846 | /* 1166 */ "Z5_Z13\000" |
| 23847 | /* 1173 */ "Z1_Z5_Z9_Z13\000" |
| 23848 | /* 1186 */ "b13\000" |
| 23849 | /* 1190 */ "d13\000" |
| 23850 | /* 1194 */ "h13\000" |
| 23851 | /* 1198 */ "pn13\000" |
| 23852 | /* 1203 */ "p13\000" |
| 23853 | /* 1207 */ "q13\000" |
| 23854 | /* 1211 */ "s13\000" |
| 23855 | /* 1215 */ "w13\000" |
| 23856 | /* 1219 */ "x13\000" |
| 23857 | /* 1223 */ "z13\000" |
| 23858 | /* 1227 */ "D20_D21_D22_D23\000" |
| 23859 | /* 1243 */ "Q20_Q21_Q22_Q23\000" |
| 23860 | /* 1259 */ "W22_W23\000" |
| 23861 | /* 1267 */ "X16_X17_X18_X19_X20_X21_X22_X23\000" |
| 23862 | /* 1299 */ "Z20_Z21_Z22_Z23\000" |
| 23863 | /* 1315 */ "b23\000" |
| 23864 | /* 1319 */ "d23\000" |
| 23865 | /* 1323 */ "h23\000" |
| 23866 | /* 1327 */ "q23\000" |
| 23867 | /* 1331 */ "s23\000" |
| 23868 | /* 1335 */ "w23\000" |
| 23869 | /* 1339 */ "x23\000" |
| 23870 | /* 1343 */ "z23\000" |
| 23871 | /* 1347 */ "D0_D1_D2_D3\000" |
| 23872 | /* 1359 */ "P2_P3\000" |
| 23873 | /* 1365 */ "Q0_Q1_Q2_Q3\000" |
| 23874 | /* 1377 */ "W2_W3\000" |
| 23875 | /* 1383 */ "X2_X3\000" |
| 23876 | /* 1389 */ "Z0_Z1_Z2_Z3\000" |
| 23877 | /* 1401 */ "b3\000" |
| 23878 | /* 1404 */ "d3\000" |
| 23879 | /* 1407 */ "h3\000" |
| 23880 | /* 1410 */ "pn3\000" |
| 23881 | /* 1414 */ "p3\000" |
| 23882 | /* 1417 */ "q3\000" |
| 23883 | /* 1420 */ "s3\000" |
| 23884 | /* 1423 */ "w3\000" |
| 23885 | /* 1426 */ "x3\000" |
| 23886 | /* 1429 */ "z3\000" |
| 23887 | /* 1432 */ "D11_D12_D13_D14\000" |
| 23888 | /* 1448 */ "P13_P14\000" |
| 23889 | /* 1456 */ "Q11_Q12_Q13_Q14\000" |
| 23890 | /* 1472 */ "Z2_Z6_Z10_Z14\000" |
| 23891 | /* 1486 */ "Z11_Z12_Z13_Z14\000" |
| 23892 | /* 1502 */ "Z6_Z14\000" |
| 23893 | /* 1509 */ "b14\000" |
| 23894 | /* 1513 */ "d14\000" |
| 23895 | /* 1517 */ "h14\000" |
| 23896 | /* 1521 */ "pn14\000" |
| 23897 | /* 1526 */ "p14\000" |
| 23898 | /* 1530 */ "q14\000" |
| 23899 | /* 1534 */ "s14\000" |
| 23900 | /* 1538 */ "w14\000" |
| 23901 | /* 1542 */ "x14\000" |
| 23902 | /* 1546 */ "z14\000" |
| 23903 | /* 1550 */ "D21_D22_D23_D24\000" |
| 23904 | /* 1566 */ "Q21_Q22_Q23_Q24\000" |
| 23905 | /* 1582 */ "Z21_Z22_Z23_Z24\000" |
| 23906 | /* 1598 */ "Z16_Z24\000" |
| 23907 | /* 1606 */ "b24\000" |
| 23908 | /* 1610 */ "d24\000" |
| 23909 | /* 1614 */ "h24\000" |
| 23910 | /* 1618 */ "q24\000" |
| 23911 | /* 1622 */ "s24\000" |
| 23912 | /* 1626 */ "w24\000" |
| 23913 | /* 1630 */ "x24\000" |
| 23914 | /* 1634 */ "z24\000" |
| 23915 | /* 1638 */ "D1_D2_D3_D4\000" |
| 23916 | /* 1650 */ "P3_P4\000" |
| 23917 | /* 1656 */ "Q1_Q2_Q3_Q4\000" |
| 23918 | /* 1668 */ "Z1_Z2_Z3_Z4\000" |
| 23919 | /* 1680 */ "b4\000" |
| 23920 | /* 1683 */ "d4\000" |
| 23921 | /* 1686 */ "h4\000" |
| 23922 | /* 1689 */ "pn4\000" |
| 23923 | /* 1693 */ "p4\000" |
| 23924 | /* 1696 */ "q4\000" |
| 23925 | /* 1699 */ "s4\000" |
| 23926 | /* 1702 */ "w4\000" |
| 23927 | /* 1705 */ "x4\000" |
| 23928 | /* 1708 */ "z4\000" |
| 23929 | /* 1711 */ "D12_D13_D14_D15\000" |
| 23930 | /* 1727 */ "P14_P15\000" |
| 23931 | /* 1735 */ "Q12_Q13_Q14_Q15\000" |
| 23932 | /* 1751 */ "W14_W15\000" |
| 23933 | /* 1759 */ "X8_X9_X10_X11_X12_X13_X14_X15\000" |
| 23934 | /* 1789 */ "Z3_Z7_Z11_Z15\000" |
| 23935 | /* 1803 */ "Z12_Z13_Z14_Z15\000" |
| 23936 | /* 1819 */ "Z7_Z15\000" |
| 23937 | /* 1826 */ "b15\000" |
| 23938 | /* 1830 */ "d15\000" |
| 23939 | /* 1834 */ "h15\000" |
| 23940 | /* 1838 */ "pn15\000" |
| 23941 | /* 1843 */ "p15\000" |
| 23942 | /* 1847 */ "q15\000" |
| 23943 | /* 1851 */ "s15\000" |
| 23944 | /* 1855 */ "w15\000" |
| 23945 | /* 1859 */ "x15\000" |
| 23946 | /* 1863 */ "z15\000" |
| 23947 | /* 1867 */ "D22_D23_D24_D25\000" |
| 23948 | /* 1883 */ "Q22_Q23_Q24_Q25\000" |
| 23949 | /* 1899 */ "W24_W25\000" |
| 23950 | /* 1907 */ "X18_X19_X20_X21_X22_X23_X24_X25\000" |
| 23951 | /* 1939 */ "Z22_Z23_Z24_Z25\000" |
| 23952 | /* 1955 */ "Z17_Z25\000" |
| 23953 | /* 1963 */ "b25\000" |
| 23954 | /* 1967 */ "d25\000" |
| 23955 | /* 1971 */ "h25\000" |
| 23956 | /* 1975 */ "q25\000" |
| 23957 | /* 1979 */ "s25\000" |
| 23958 | /* 1983 */ "w25\000" |
| 23959 | /* 1987 */ "x25\000" |
| 23960 | /* 1991 */ "z25\000" |
| 23961 | /* 1995 */ "D2_D3_D4_D5\000" |
| 23962 | /* 2007 */ "P4_P5\000" |
| 23963 | /* 2013 */ "Q2_Q3_Q4_Q5\000" |
| 23964 | /* 2025 */ "W4_W5\000" |
| 23965 | /* 2031 */ "X4_X5\000" |
| 23966 | /* 2037 */ "Z2_Z3_Z4_Z5\000" |
| 23967 | /* 2049 */ "b5\000" |
| 23968 | /* 2052 */ "d5\000" |
| 23969 | /* 2055 */ "h5\000" |
| 23970 | /* 2058 */ "pn5\000" |
| 23971 | /* 2062 */ "p5\000" |
| 23972 | /* 2065 */ "q5\000" |
| 23973 | /* 2068 */ "s5\000" |
| 23974 | /* 2071 */ "w5\000" |
| 23975 | /* 2074 */ "x5\000" |
| 23976 | /* 2077 */ "z5\000" |
| 23977 | /* 2080 */ "D13_D14_D15_D16\000" |
| 23978 | /* 2096 */ "Q13_Q14_Q15_Q16\000" |
| 23979 | /* 2112 */ "Z13_Z14_Z15_Z16\000" |
| 23980 | /* 2128 */ "b16\000" |
| 23981 | /* 2132 */ "d16\000" |
| 23982 | /* 2136 */ "h16\000" |
| 23983 | /* 2140 */ "q16\000" |
| 23984 | /* 2144 */ "s16\000" |
| 23985 | /* 2148 */ "w16\000" |
| 23986 | /* 2152 */ "x16\000" |
| 23987 | /* 2156 */ "z16\000" |
| 23988 | /* 2160 */ "D23_D24_D25_D26\000" |
| 23989 | /* 2176 */ "Q23_Q24_Q25_Q26\000" |
| 23990 | /* 2192 */ "Z23_Z24_Z25_Z26\000" |
| 23991 | /* 2208 */ "Z18_Z26\000" |
| 23992 | /* 2216 */ "b26\000" |
| 23993 | /* 2220 */ "d26\000" |
| 23994 | /* 2224 */ "h26\000" |
| 23995 | /* 2228 */ "q26\000" |
| 23996 | /* 2232 */ "s26\000" |
| 23997 | /* 2236 */ "w26\000" |
| 23998 | /* 2240 */ "x26\000" |
| 23999 | /* 2244 */ "z26\000" |
| 24000 | /* 2248 */ "D3_D4_D5_D6\000" |
| 24001 | /* 2260 */ "P5_P6\000" |
| 24002 | /* 2266 */ "Q3_Q4_Q5_Q6\000" |
| 24003 | /* 2278 */ "Z3_Z4_Z5_Z6\000" |
| 24004 | /* 2290 */ "b6\000" |
| 24005 | /* 2293 */ "d6\000" |
| 24006 | /* 2296 */ "h6\000" |
| 24007 | /* 2299 */ "pn6\000" |
| 24008 | /* 2303 */ "p6\000" |
| 24009 | /* 2306 */ "q6\000" |
| 24010 | /* 2309 */ "s6\000" |
| 24011 | /* 2312 */ "w6\000" |
| 24012 | /* 2315 */ "x6\000" |
| 24013 | /* 2318 */ "z6\000" |
| 24014 | /* 2321 */ "D14_D15_D16_D17\000" |
| 24015 | /* 2337 */ "Q14_Q15_Q16_Q17\000" |
| 24016 | /* 2353 */ "W16_W17\000" |
| 24017 | /* 2361 */ "X10_X11_X12_X13_X14_X15_X16_X17\000" |
| 24018 | /* 2393 */ "Z14_Z15_Z16_Z17\000" |
| 24019 | /* 2409 */ "b17\000" |
| 24020 | /* 2413 */ "d17\000" |
| 24021 | /* 2417 */ "h17\000" |
| 24022 | /* 2421 */ "q17\000" |
| 24023 | /* 2425 */ "s17\000" |
| 24024 | /* 2429 */ "w17\000" |
| 24025 | /* 2433 */ "x17\000" |
| 24026 | /* 2437 */ "z17\000" |
| 24027 | /* 2441 */ "D24_D25_D26_D27\000" |
| 24028 | /* 2457 */ "Q24_Q25_Q26_Q27\000" |
| 24029 | /* 2473 */ "W26_W27\000" |
| 24030 | /* 2481 */ "X20_X21_X22_X23_X24_X25_X26_X27\000" |
| 24031 | /* 2513 */ "Z24_Z25_Z26_Z27\000" |
| 24032 | /* 2529 */ "Z19_Z27\000" |
| 24033 | /* 2537 */ "b27\000" |
| 24034 | /* 2541 */ "d27\000" |
| 24035 | /* 2545 */ "h27\000" |
| 24036 | /* 2549 */ "q27\000" |
| 24037 | /* 2553 */ "s27\000" |
| 24038 | /* 2557 */ "w27\000" |
| 24039 | /* 2561 */ "x27\000" |
| 24040 | /* 2565 */ "z27\000" |
| 24041 | /* 2569 */ "D4_D5_D6_D7\000" |
| 24042 | /* 2581 */ "P6_P7\000" |
| 24043 | /* 2587 */ "Q4_Q5_Q6_Q7\000" |
| 24044 | /* 2599 */ "W6_W7\000" |
| 24045 | /* 2605 */ "X0_X1_X2_X3_X4_X5_X6_X7\000" |
| 24046 | /* 2629 */ "Z4_Z5_Z6_Z7\000" |
| 24047 | /* 2641 */ "b7\000" |
| 24048 | /* 2644 */ "d7\000" |
| 24049 | /* 2647 */ "h7\000" |
| 24050 | /* 2650 */ "pn7\000" |
| 24051 | /* 2654 */ "p7\000" |
| 24052 | /* 2657 */ "q7\000" |
| 24053 | /* 2660 */ "s7\000" |
| 24054 | /* 2663 */ "w7\000" |
| 24055 | /* 2666 */ "x7\000" |
| 24056 | /* 2669 */ "z7\000" |
| 24057 | /* 2672 */ "D15_D16_D17_D18\000" |
| 24058 | /* 2688 */ "Q15_Q16_Q17_Q18\000" |
| 24059 | /* 2704 */ "Z15_Z16_Z17_Z18\000" |
| 24060 | /* 2720 */ "b18\000" |
| 24061 | /* 2724 */ "d18\000" |
| 24062 | /* 2728 */ "h18\000" |
| 24063 | /* 2732 */ "q18\000" |
| 24064 | /* 2736 */ "s18\000" |
| 24065 | /* 2740 */ "w18\000" |
| 24066 | /* 2744 */ "x18\000" |
| 24067 | /* 2748 */ "z18\000" |
| 24068 | /* 2752 */ "D25_D26_D27_D28\000" |
| 24069 | /* 2768 */ "Q25_Q26_Q27_Q28\000" |
| 24070 | /* 2784 */ "Z20_Z28\000" |
| 24071 | /* 2792 */ "Z16_Z20_Z24_Z28\000" |
| 24072 | /* 2808 */ "Z25_Z26_Z27_Z28\000" |
| 24073 | /* 2824 */ "b28\000" |
| 24074 | /* 2828 */ "d28\000" |
| 24075 | /* 2832 */ "h28\000" |
| 24076 | /* 2836 */ "q28\000" |
| 24077 | /* 2840 */ "s28\000" |
| 24078 | /* 2844 */ "w28\000" |
| 24079 | /* 2848 */ "x28\000" |
| 24080 | /* 2852 */ "z28\000" |
| 24081 | /* 2856 */ "D5_D6_D7_D8\000" |
| 24082 | /* 2868 */ "P7_P8\000" |
| 24083 | /* 2874 */ "Q5_Q6_Q7_Q8\000" |
| 24084 | /* 2886 */ "Z0_Z8\000" |
| 24085 | /* 2892 */ "Z5_Z6_Z7_Z8\000" |
| 24086 | /* 2904 */ "b8\000" |
| 24087 | /* 2907 */ "d8\000" |
| 24088 | /* 2910 */ "h8\000" |
| 24089 | /* 2913 */ "pn8\000" |
| 24090 | /* 2917 */ "p8\000" |
| 24091 | /* 2920 */ "q8\000" |
| 24092 | /* 2923 */ "s8\000" |
| 24093 | /* 2926 */ "w8\000" |
| 24094 | /* 2929 */ "x8\000" |
| 24095 | /* 2932 */ "z8\000" |
| 24096 | /* 2935 */ "D16_D17_D18_D19\000" |
| 24097 | /* 2951 */ "Q16_Q17_Q18_Q19\000" |
| 24098 | /* 2967 */ "W18_W19\000" |
| 24099 | /* 2975 */ "X12_X13_X14_X15_X16_X17_X18_X19\000" |
| 24100 | /* 3007 */ "Z16_Z17_Z18_Z19\000" |
| 24101 | /* 3023 */ "b19\000" |
| 24102 | /* 3027 */ "d19\000" |
| 24103 | /* 3031 */ "h19\000" |
| 24104 | /* 3035 */ "q19\000" |
| 24105 | /* 3039 */ "s19\000" |
| 24106 | /* 3043 */ "w19\000" |
| 24107 | /* 3047 */ "x19\000" |
| 24108 | /* 3051 */ "z19\000" |
| 24109 | /* 3055 */ "D26_D27_D28_D29\000" |
| 24110 | /* 3071 */ "Q26_Q27_Q28_Q29\000" |
| 24111 | /* 3087 */ "W28_W29\000" |
| 24112 | /* 3095 */ "Z21_Z29\000" |
| 24113 | /* 3103 */ "Z17_Z21_Z25_Z29\000" |
| 24114 | /* 3119 */ "Z26_Z27_Z28_Z29\000" |
| 24115 | /* 3135 */ "b29\000" |
| 24116 | /* 3139 */ "d29\000" |
| 24117 | /* 3143 */ "h29\000" |
| 24118 | /* 3147 */ "q29\000" |
| 24119 | /* 3151 */ "s29\000" |
| 24120 | /* 3155 */ "w29\000" |
| 24121 | /* 3159 */ "x29\000" |
| 24122 | /* 3163 */ "z29\000" |
| 24123 | /* 3167 */ "D6_D7_D8_D9\000" |
| 24124 | /* 3179 */ "P8_P9\000" |
| 24125 | /* 3185 */ "Q6_Q7_Q8_Q9\000" |
| 24126 | /* 3197 */ "W8_W9\000" |
| 24127 | /* 3203 */ "X2_X3_X4_X5_X6_X7_X8_X9\000" |
| 24128 | /* 3227 */ "Z1_Z9\000" |
| 24129 | /* 3233 */ "Z6_Z7_Z8_Z9\000" |
| 24130 | /* 3245 */ "b9\000" |
| 24131 | /* 3248 */ "d9\000" |
| 24132 | /* 3251 */ "h9\000" |
| 24133 | /* 3254 */ "pn9\000" |
| 24134 | /* 3258 */ "p9\000" |
| 24135 | /* 3261 */ "q9\000" |
| 24136 | /* 3264 */ "s9\000" |
| 24137 | /* 3267 */ "w9\000" |
| 24138 | /* 3270 */ "x9\000" |
| 24139 | /* 3273 */ "z9\000" |
| 24140 | /* 3276 */ "X22_X23_X24_X25_X26_X27_X28_FP\000" |
| 24141 | /* 3307 */ "W30_WZR\000" |
| 24142 | /* 3315 */ "LR_XZR\000" |
| 24143 | /* 3322 */ "za\000" |
| 24144 | /* 3325 */ "za0.b\000" |
| 24145 | /* 3331 */ "za0.d\000" |
| 24146 | /* 3337 */ "za1.d\000" |
| 24147 | /* 3343 */ "za2.d\000" |
| 24148 | /* 3349 */ "za3.d\000" |
| 24149 | /* 3355 */ "za4.d\000" |
| 24150 | /* 3361 */ "za5.d\000" |
| 24151 | /* 3367 */ "za6.d\000" |
| 24152 | /* 3373 */ "za7.d\000" |
| 24153 | /* 3379 */ "vg\000" |
| 24154 | /* 3382 */ "za0.h\000" |
| 24155 | /* 3388 */ "za1.h\000" |
| 24156 | /* 3394 */ "b10_hi\000" |
| 24157 | /* 3401 */ "d10_hi\000" |
| 24158 | /* 3408 */ "h10_hi\000" |
| 24159 | /* 3415 */ "q10_hi\000" |
| 24160 | /* 3422 */ "s10_hi\000" |
| 24161 | /* 3429 */ "w10_hi\000" |
| 24162 | /* 3436 */ "b20_hi\000" |
| 24163 | /* 3443 */ "d20_hi\000" |
| 24164 | /* 3450 */ "h20_hi\000" |
| 24165 | /* 3457 */ "q20_hi\000" |
| 24166 | /* 3464 */ "s20_hi\000" |
| 24167 | /* 3471 */ "w20_hi\000" |
| 24168 | /* 3478 */ "b30_hi\000" |
| 24169 | /* 3485 */ "d30_hi\000" |
| 24170 | /* 3492 */ "h30_hi\000" |
| 24171 | /* 3499 */ "q30_hi\000" |
| 24172 | /* 3506 */ "s30_hi\000" |
| 24173 | /* 3513 */ "w30_hi\000" |
| 24174 | /* 3520 */ "b0_hi\000" |
| 24175 | /* 3526 */ "d0_hi\000" |
| 24176 | /* 3532 */ "h0_hi\000" |
| 24177 | /* 3538 */ "q0_hi\000" |
| 24178 | /* 3544 */ "s0_hi\000" |
| 24179 | /* 3550 */ "w0_hi\000" |
| 24180 | /* 3556 */ "b11_hi\000" |
| 24181 | /* 3563 */ "d11_hi\000" |
| 24182 | /* 3570 */ "h11_hi\000" |
| 24183 | /* 3577 */ "q11_hi\000" |
| 24184 | /* 3584 */ "s11_hi\000" |
| 24185 | /* 3591 */ "w11_hi\000" |
| 24186 | /* 3598 */ "b21_hi\000" |
| 24187 | /* 3605 */ "d21_hi\000" |
| 24188 | /* 3612 */ "h21_hi\000" |
| 24189 | /* 3619 */ "q21_hi\000" |
| 24190 | /* 3626 */ "s21_hi\000" |
| 24191 | /* 3633 */ "w21_hi\000" |
| 24192 | /* 3640 */ "b31_hi\000" |
| 24193 | /* 3647 */ "d31_hi\000" |
| 24194 | /* 3654 */ "h31_hi\000" |
| 24195 | /* 3661 */ "q31_hi\000" |
| 24196 | /* 3668 */ "s31_hi\000" |
| 24197 | /* 3675 */ "b1_hi\000" |
| 24198 | /* 3681 */ "d1_hi\000" |
| 24199 | /* 3687 */ "h1_hi\000" |
| 24200 | /* 3693 */ "q1_hi\000" |
| 24201 | /* 3699 */ "s1_hi\000" |
| 24202 | /* 3705 */ "w1_hi\000" |
| 24203 | /* 3711 */ "b12_hi\000" |
| 24204 | /* 3718 */ "d12_hi\000" |
| 24205 | /* 3725 */ "h12_hi\000" |
| 24206 | /* 3732 */ "q12_hi\000" |
| 24207 | /* 3739 */ "s12_hi\000" |
| 24208 | /* 3746 */ "w12_hi\000" |
| 24209 | /* 3753 */ "b22_hi\000" |
| 24210 | /* 3760 */ "d22_hi\000" |
| 24211 | /* 3767 */ "h22_hi\000" |
| 24212 | /* 3774 */ "q22_hi\000" |
| 24213 | /* 3781 */ "s22_hi\000" |
| 24214 | /* 3788 */ "w22_hi\000" |
| 24215 | /* 3795 */ "b2_hi\000" |
| 24216 | /* 3801 */ "d2_hi\000" |
| 24217 | /* 3807 */ "h2_hi\000" |
| 24218 | /* 3813 */ "q2_hi\000" |
| 24219 | /* 3819 */ "s2_hi\000" |
| 24220 | /* 3825 */ "w2_hi\000" |
| 24221 | /* 3831 */ "b13_hi\000" |
| 24222 | /* 3838 */ "d13_hi\000" |
| 24223 | /* 3845 */ "h13_hi\000" |
| 24224 | /* 3852 */ "q13_hi\000" |
| 24225 | /* 3859 */ "s13_hi\000" |
| 24226 | /* 3866 */ "w13_hi\000" |
| 24227 | /* 3873 */ "b23_hi\000" |
| 24228 | /* 3880 */ "d23_hi\000" |
| 24229 | /* 3887 */ "h23_hi\000" |
| 24230 | /* 3894 */ "q23_hi\000" |
| 24231 | /* 3901 */ "s23_hi\000" |
| 24232 | /* 3908 */ "w23_hi\000" |
| 24233 | /* 3915 */ "b3_hi\000" |
| 24234 | /* 3921 */ "d3_hi\000" |
| 24235 | /* 3927 */ "h3_hi\000" |
| 24236 | /* 3933 */ "q3_hi\000" |
| 24237 | /* 3939 */ "s3_hi\000" |
| 24238 | /* 3945 */ "w3_hi\000" |
| 24239 | /* 3951 */ "b14_hi\000" |
| 24240 | /* 3958 */ "d14_hi\000" |
| 24241 | /* 3965 */ "h14_hi\000" |
| 24242 | /* 3972 */ "q14_hi\000" |
| 24243 | /* 3979 */ "s14_hi\000" |
| 24244 | /* 3986 */ "w14_hi\000" |
| 24245 | /* 3993 */ "b24_hi\000" |
| 24246 | /* 4000 */ "d24_hi\000" |
| 24247 | /* 4007 */ "h24_hi\000" |
| 24248 | /* 4014 */ "q24_hi\000" |
| 24249 | /* 4021 */ "s24_hi\000" |
| 24250 | /* 4028 */ "w24_hi\000" |
| 24251 | /* 4035 */ "b4_hi\000" |
| 24252 | /* 4041 */ "d4_hi\000" |
| 24253 | /* 4047 */ "h4_hi\000" |
| 24254 | /* 4053 */ "q4_hi\000" |
| 24255 | /* 4059 */ "s4_hi\000" |
| 24256 | /* 4065 */ "w4_hi\000" |
| 24257 | /* 4071 */ "b15_hi\000" |
| 24258 | /* 4078 */ "d15_hi\000" |
| 24259 | /* 4085 */ "h15_hi\000" |
| 24260 | /* 4092 */ "q15_hi\000" |
| 24261 | /* 4099 */ "s15_hi\000" |
| 24262 | /* 4106 */ "w15_hi\000" |
| 24263 | /* 4113 */ "b25_hi\000" |
| 24264 | /* 4120 */ "d25_hi\000" |
| 24265 | /* 4127 */ "h25_hi\000" |
| 24266 | /* 4134 */ "q25_hi\000" |
| 24267 | /* 4141 */ "s25_hi\000" |
| 24268 | /* 4148 */ "w25_hi\000" |
| 24269 | /* 4155 */ "b5_hi\000" |
| 24270 | /* 4161 */ "d5_hi\000" |
| 24271 | /* 4167 */ "h5_hi\000" |
| 24272 | /* 4173 */ "q5_hi\000" |
| 24273 | /* 4179 */ "s5_hi\000" |
| 24274 | /* 4185 */ "w5_hi\000" |
| 24275 | /* 4191 */ "b16_hi\000" |
| 24276 | /* 4198 */ "d16_hi\000" |
| 24277 | /* 4205 */ "h16_hi\000" |
| 24278 | /* 4212 */ "q16_hi\000" |
| 24279 | /* 4219 */ "s16_hi\000" |
| 24280 | /* 4226 */ "w16_hi\000" |
| 24281 | /* 4233 */ "b26_hi\000" |
| 24282 | /* 4240 */ "d26_hi\000" |
| 24283 | /* 4247 */ "h26_hi\000" |
| 24284 | /* 4254 */ "q26_hi\000" |
| 24285 | /* 4261 */ "s26_hi\000" |
| 24286 | /* 4268 */ "w26_hi\000" |
| 24287 | /* 4275 */ "b6_hi\000" |
| 24288 | /* 4281 */ "d6_hi\000" |
| 24289 | /* 4287 */ "h6_hi\000" |
| 24290 | /* 4293 */ "q6_hi\000" |
| 24291 | /* 4299 */ "s6_hi\000" |
| 24292 | /* 4305 */ "w6_hi\000" |
| 24293 | /* 4311 */ "b17_hi\000" |
| 24294 | /* 4318 */ "d17_hi\000" |
| 24295 | /* 4325 */ "h17_hi\000" |
| 24296 | /* 4332 */ "q17_hi\000" |
| 24297 | /* 4339 */ "s17_hi\000" |
| 24298 | /* 4346 */ "w17_hi\000" |
| 24299 | /* 4353 */ "b27_hi\000" |
| 24300 | /* 4360 */ "d27_hi\000" |
| 24301 | /* 4367 */ "h27_hi\000" |
| 24302 | /* 4374 */ "q27_hi\000" |
| 24303 | /* 4381 */ "s27_hi\000" |
| 24304 | /* 4388 */ "w27_hi\000" |
| 24305 | /* 4395 */ "b7_hi\000" |
| 24306 | /* 4401 */ "d7_hi\000" |
| 24307 | /* 4407 */ "h7_hi\000" |
| 24308 | /* 4413 */ "q7_hi\000" |
| 24309 | /* 4419 */ "s7_hi\000" |
| 24310 | /* 4425 */ "w7_hi\000" |
| 24311 | /* 4431 */ "b18_hi\000" |
| 24312 | /* 4438 */ "d18_hi\000" |
| 24313 | /* 4445 */ "h18_hi\000" |
| 24314 | /* 4452 */ "q18_hi\000" |
| 24315 | /* 4459 */ "s18_hi\000" |
| 24316 | /* 4466 */ "w18_hi\000" |
| 24317 | /* 4473 */ "b28_hi\000" |
| 24318 | /* 4480 */ "d28_hi\000" |
| 24319 | /* 4487 */ "h28_hi\000" |
| 24320 | /* 4494 */ "q28_hi\000" |
| 24321 | /* 4501 */ "s28_hi\000" |
| 24322 | /* 4508 */ "w28_hi\000" |
| 24323 | /* 4515 */ "b8_hi\000" |
| 24324 | /* 4521 */ "d8_hi\000" |
| 24325 | /* 4527 */ "h8_hi\000" |
| 24326 | /* 4533 */ "q8_hi\000" |
| 24327 | /* 4539 */ "s8_hi\000" |
| 24328 | /* 4545 */ "w8_hi\000" |
| 24329 | /* 4551 */ "b19_hi\000" |
| 24330 | /* 4558 */ "d19_hi\000" |
| 24331 | /* 4565 */ "h19_hi\000" |
| 24332 | /* 4572 */ "q19_hi\000" |
| 24333 | /* 4579 */ "s19_hi\000" |
| 24334 | /* 4586 */ "w19_hi\000" |
| 24335 | /* 4593 */ "b29_hi\000" |
| 24336 | /* 4600 */ "d29_hi\000" |
| 24337 | /* 4607 */ "h29_hi\000" |
| 24338 | /* 4614 */ "q29_hi\000" |
| 24339 | /* 4621 */ "s29_hi\000" |
| 24340 | /* 4628 */ "w29_hi\000" |
| 24341 | /* 4635 */ "b9_hi\000" |
| 24342 | /* 4641 */ "d9_hi\000" |
| 24343 | /* 4647 */ "h9_hi\000" |
| 24344 | /* 4653 */ "q9_hi\000" |
| 24345 | /* 4659 */ "s9_hi\000" |
| 24346 | /* 4665 */ "w9_hi\000" |
| 24347 | /* 4671 */ "wsp_hi\000" |
| 24348 | /* 4678 */ "wzr_hi\000" |
| 24349 | /* 4685 */ "wsp\000" |
| 24350 | /* 4689 */ "za10.q\000" |
| 24351 | /* 4696 */ "za0.q\000" |
| 24352 | /* 4702 */ "za11.q\000" |
| 24353 | /* 4709 */ "za1.q\000" |
| 24354 | /* 4715 */ "za12.q\000" |
| 24355 | /* 4722 */ "za2.q\000" |
| 24356 | /* 4728 */ "za13.q\000" |
| 24357 | /* 4735 */ "za3.q\000" |
| 24358 | /* 4741 */ "za14.q\000" |
| 24359 | /* 4748 */ "za4.q\000" |
| 24360 | /* 4754 */ "za15.q\000" |
| 24361 | /* 4761 */ "za5.q\000" |
| 24362 | /* 4767 */ "za6.q\000" |
| 24363 | /* 4773 */ "za7.q\000" |
| 24364 | /* 4779 */ "za8.q\000" |
| 24365 | /* 4785 */ "za9.q\000" |
| 24366 | /* 4791 */ "fpcr\000" |
| 24367 | /* 4796 */ "ffr\000" |
| 24368 | /* 4800 */ "fpmr\000" |
| 24369 | /* 4805 */ "fpsr\000" |
| 24370 | /* 4810 */ "wzr\000" |
| 24371 | /* 4814 */ "xzr\000" |
| 24372 | /* 4818 */ "za0.s\000" |
| 24373 | /* 4824 */ "za1.s\000" |
| 24374 | /* 4830 */ "za2.s\000" |
| 24375 | /* 4836 */ "za3.s\000" |
| 24376 | /* 4842 */ "nzcv\000" |
| 24377 | }; |
| 24378 | #ifdef __GNUC__ |
| 24379 | #pragma GCC diagnostic pop |
| 24380 | #endif |
| 24381 | |
| 24382 | static const uint16_t RegAsmOffsetNoRegAltName[] = { |
| 24383 | 4796, 3159, 4791, 4800, 4805, 270, 4842, 4686, 3379, 4685, 4671, 4810, 4678, 4814, |
| 24384 | 3322, 330, 773, 1043, 1401, 1680, 2049, 2290, 2641, 2904, 3245, 53, 456, 877, |
| 24385 | 1186, 1509, 1826, 2128, 2409, 2720, 3023, 142, 585, 966, 1315, 1606, 1963, 2216, |
| 24386 | 2537, 2824, 3135, 246, 689, 333, 776, 1046, 1404, 1683, 2052, 2293, 2644, 2907, |
| 24387 | 3248, 57, 460, 881, 1190, 1513, 1830, 2132, 2413, 2724, 3027, 146, 589, 970, |
| 24388 | 1319, 1610, 1967, 2220, 2541, 2828, 3139, 250, 693, 336, 779, 1049, 1407, 1686, |
| 24389 | 2055, 2296, 2647, 2910, 3251, 61, 464, 885, 1194, 1517, 1834, 2136, 2417, 2728, |
| 24390 | 3031, 150, 593, 974, 1323, 1614, 1971, 2224, 2545, 2832, 3143, 254, 697, 343, |
| 24391 | 786, 1056, 1414, 1693, 2062, 2303, 2654, 2917, 3258, 70, 473, 894, 1203, 1526, |
| 24392 | 1843, 339, 782, 1052, 1410, 1689, 2058, 2299, 2650, 2913, 3254, 65, 468, 889, |
| 24393 | 1198, 1521, 1838, 346, 789, 1059, 1417, 1696, 2065, 2306, 2657, 2920, 3261, 74, |
| 24394 | 477, 898, 1207, 1530, 1847, 2140, 2421, 2732, 3035, 154, 597, 978, 1327, 1618, |
| 24395 | 1975, 2228, 2549, 2836, 3147, 258, 701, 349, 792, 1062, 1420, 1699, 2068, 2309, |
| 24396 | 2660, 2923, 3264, 78, 481, 902, 1211, 1534, 1851, 2144, 2425, 2736, 3039, 158, |
| 24397 | 601, 982, 1331, 1622, 1979, 2232, 2553, 2840, 3151, 262, 705, 356, 795, 1065, |
| 24398 | 1423, 1702, 2071, 2312, 2663, 2926, 3267, 82, 485, 906, 1215, 1538, 1855, 2148, |
| 24399 | 2429, 2740, 3043, 162, 605, 986, 1335, 1626, 1983, 2236, 2557, 2844, 3155, 266, |
| 24400 | 359, 798, 1068, 1426, 1705, 2074, 2315, 2666, 2929, 3270, 86, 489, 910, 1219, |
| 24401 | 1542, 1859, 2152, 2433, 2744, 3047, 166, 609, 990, 1339, 1630, 1987, 2240, 2561, |
| 24402 | 2848, 362, 801, 1071, 1429, 1708, 2077, 2318, 2669, 2932, 3273, 90, 493, 914, |
| 24403 | 1223, 1546, 1863, 2156, 2437, 2748, 3051, 170, 613, 994, 1343, 1634, 1991, 2244, |
| 24404 | 2565, 2852, 3163, 274, 709, 3325, 3331, 3337, 3343, 3349, 3355, 3361, 3367, 3373, |
| 24405 | 3382, 3388, 4696, 4709, 4722, 4735, 4748, 4761, 4767, 4773, 4779, 4785, 4689, 4702, |
| 24406 | 4715, 4728, 4741, 4754, 4818, 4824, 4830, 4836, 352, 3520, 3675, 3795, 3915, 4035, |
| 24407 | 4155, 4275, 4395, 4515, 4635, 3394, 3556, 3711, 3831, 3951, 4071, 4191, 4311, 4431, |
| 24408 | 4551, 3436, 3598, 3753, 3873, 3993, 4113, 4233, 4353, 4473, 4593, 3478, 3640, 3526, |
| 24409 | 3681, 3801, 3921, 4041, 4161, 4281, 4401, 4521, 4641, 3401, 3563, 3718, 3838, 3958, |
| 24410 | 4078, 4198, 4318, 4438, 4558, 3443, 3605, 3760, 3880, 4000, 4120, 4240, 4360, 4480, |
| 24411 | 4600, 3485, 3647, 3532, 3687, 3807, 3927, 4047, 4167, 4287, 4407, 4527, 4647, 3408, |
| 24412 | 3570, 3725, 3845, 3965, 4085, 4205, 4325, 4445, 4565, 3450, 3612, 3767, 3887, 4007, |
| 24413 | 4127, 4247, 4367, 4487, 4607, 3492, 3654, 3538, 3693, 3813, 3933, 4053, 4173, 4293, |
| 24414 | 4413, 4533, 4653, 3415, 3577, 3732, 3852, 3972, 4092, 4212, 4332, 4452, 4572, 3457, |
| 24415 | 3619, 3774, 3894, 4014, 4134, 4254, 4374, 4494, 4614, 3499, 3661, 3544, 3699, 3819, |
| 24416 | 3939, 4059, 4179, 4299, 4419, 4539, 4659, 3422, 3584, 3739, 3859, 3979, 4099, 4219, |
| 24417 | 4339, 4459, 4579, 3464, 3626, 3781, 3901, 4021, 4141, 4261, 4381, 4501, 4621, 3506, |
| 24418 | 3668, 3550, 3705, 3825, 3945, 4065, 4185, 4305, 4425, 4545, 4665, 3429, 3591, 3746, |
| 24419 | 3866, 3986, 4106, 4226, 4346, 4466, 4586, 3471, 3633, 3788, 3908, 4028, 4148, 4268, |
| 24420 | 4388, 4508, 4628, 3513, 721, 1005, 1353, 1644, 2001, 2254, 2575, 2862, 3173, 6, |
| 24421 | 371, 811, 1082, 1440, 1719, 2088, 2329, 2680, 2943, 102, 505, 926, 1235, 1558, |
| 24422 | 1875, 2168, 2449, 2760, 3063, 182, 625, 286, 1347, 1638, 1995, 2248, 2569, 2856, |
| 24423 | 3167, 0, 365, 804, 1074, 1432, 1711, 2080, 2321, 2672, 2935, 94, 497, 918, |
| 24424 | 1227, 1550, 1867, 2160, 2441, 2752, 3055, 174, 617, 278, 713, 998, 1002, 1350, |
| 24425 | 1641, 1998, 2251, 2572, 2859, 3170, 3, 368, 807, 1078, 1436, 1715, 2084, 2325, |
| 24426 | 2676, 2939, 98, 501, 922, 1231, 1554, 1871, 2164, 2445, 2756, 3059, 178, 621, |
| 24427 | 282, 717, 727, 1011, 1359, 1650, 2007, 2260, 2581, 2868, 3179, 13, 379, 819, |
| 24428 | 1090, 1448, 1727, 293, 741, 1024, 1371, 1662, 2019, 2272, 2593, 2880, 3191, 26, |
| 24429 | 393, 834, 1106, 1464, 1743, 2104, 2345, 2696, 2959, 118, 521, 942, 1251, 1574, |
| 24430 | 1891, 2184, 2465, 2776, 3079, 198, 641, 308, 1365, 1656, 2013, 2266, 2587, 2874, |
| 24431 | 3185, 20, 387, 827, 1098, 1456, 1735, 2096, 2337, 2688, 2951, 110, 513, 934, |
| 24432 | 1243, 1566, 1883, 2176, 2457, 2768, 3071, 190, 633, 300, 733, 1017, 1021, 1368, |
| 24433 | 1659, 2016, 2269, 2590, 2877, 3188, 23, 390, 830, 1102, 1460, 1739, 2100, 2341, |
| 24434 | 2692, 2955, 114, 517, 938, 1247, 1570, 1887, 2180, 2461, 2772, 3075, 194, 637, |
| 24435 | 304, 737, 3276, 2605, 3203, 409, 1122, 1759, 2361, 2975, 537, 1267, 1907, 2481, |
| 24436 | 3307, 747, 1377, 2025, 2599, 3197, 401, 1114, 1751, 2353, 2967, 529, 1259, 1899, |
| 24437 | 2473, 3087, 3315, 3300, 753, 1383, 2031, 2623, 3221, 427, 1142, 1781, 2385, 2999, |
| 24438 | 561, 1291, 1931, 2505, 767, 1037, 1395, 1674, 2043, 2284, 2635, 2898, 3239, 46, |
| 24439 | 441, 849, 1158, 1494, 1811, 2120, 2401, 2712, 3015, 134, 577, 958, 1307, 1590, |
| 24440 | 1947, 2200, 2521, 2816, 3127, 238, 657, 323, 1389, 1668, 2037, 2278, 2629, 2892, |
| 24441 | 3233, 40, 435, 842, 1150, 1486, 1803, 2112, 2393, 2704, 3007, 126, 569, 950, |
| 24442 | 1299, 1582, 1939, 2192, 2513, 2808, 3119, 230, 649, 315, 759, 1030, 1034, 1392, |
| 24443 | 1671, 2040, 2281, 2632, 2895, 3236, 43, 438, 845, 1154, 1490, 1807, 2116, 2397, |
| 24444 | 2708, 3011, 130, 573, 954, 1303, 1586, 1943, 2196, 2517, 2812, 3123, 234, 653, |
| 24445 | 319, 763, 1598, 1955, 2208, 2529, 2784, 3095, 206, 665, 2886, 3227, 33, 449, |
| 24446 | 857, 1166, 1502, 1819, 2792, 3103, 214, 673, 864, 1173, 1472, 1789, |
| 24447 | }; |
| 24448 | |
| 24449 | |
| 24450 | #ifdef __GNUC__ |
| 24451 | #pragma GCC diagnostic push |
| 24452 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 24453 | #endif |
| 24454 | static const char AsmStrsvlist1[] = { |
| 24455 | /* 0 */ "\000" |
| 24456 | }; |
| 24457 | #ifdef __GNUC__ |
| 24458 | #pragma GCC diagnostic pop |
| 24459 | #endif |
| 24460 | |
| 24461 | static const uint8_t RegAsmOffsetvlist1[] = { |
| 24462 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24463 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24464 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24465 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24466 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24467 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24468 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24469 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24470 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24471 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24472 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24473 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24474 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24475 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24476 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24477 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24478 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24479 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24480 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24481 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24482 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24483 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24484 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24485 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24486 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24487 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24488 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24489 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24490 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24491 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24492 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24493 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24494 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24495 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24496 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24497 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24498 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24499 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24500 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24501 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24502 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24503 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24504 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24505 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24506 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24507 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24508 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24509 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24510 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24511 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24512 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24513 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24514 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24515 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24516 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24517 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24518 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24519 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24520 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24521 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24522 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24523 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24524 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24525 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 24526 | }; |
| 24527 | |
| 24528 | |
| 24529 | #ifdef __GNUC__ |
| 24530 | #pragma GCC diagnostic push |
| 24531 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 24532 | #endif |
| 24533 | static const char AsmStrsvreg[] = { |
| 24534 | /* 0 */ "v10\000" |
| 24535 | /* 4 */ "v20\000" |
| 24536 | /* 8 */ "v30\000" |
| 24537 | /* 12 */ "v0\000" |
| 24538 | /* 15 */ "v11\000" |
| 24539 | /* 19 */ "v21\000" |
| 24540 | /* 23 */ "v31\000" |
| 24541 | /* 27 */ "v1\000" |
| 24542 | /* 30 */ "v12\000" |
| 24543 | /* 34 */ "v22\000" |
| 24544 | /* 38 */ "v2\000" |
| 24545 | /* 41 */ "v13\000" |
| 24546 | /* 45 */ "v23\000" |
| 24547 | /* 49 */ "v3\000" |
| 24548 | /* 52 */ "v14\000" |
| 24549 | /* 56 */ "v24\000" |
| 24550 | /* 60 */ "v4\000" |
| 24551 | /* 63 */ "v15\000" |
| 24552 | /* 67 */ "v25\000" |
| 24553 | /* 71 */ "v5\000" |
| 24554 | /* 74 */ "v16\000" |
| 24555 | /* 78 */ "v26\000" |
| 24556 | /* 82 */ "v6\000" |
| 24557 | /* 85 */ "v17\000" |
| 24558 | /* 89 */ "v27\000" |
| 24559 | /* 93 */ "v7\000" |
| 24560 | /* 96 */ "v18\000" |
| 24561 | /* 100 */ "v28\000" |
| 24562 | /* 104 */ "v8\000" |
| 24563 | /* 107 */ "v19\000" |
| 24564 | /* 111 */ "v29\000" |
| 24565 | /* 115 */ "v9\000" |
| 24566 | }; |
| 24567 | #ifdef __GNUC__ |
| 24568 | #pragma GCC diagnostic pop |
| 24569 | #endif |
| 24570 | |
| 24571 | static const uint8_t RegAsmOffsetvreg[] = { |
| 24572 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24573 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24574 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24575 | 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, |
| 24576 | 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, |
| 24577 | 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, |
| 24578 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24579 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24580 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24581 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24582 | 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, |
| 24583 | 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, |
| 24584 | 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, |
| 24585 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24586 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24587 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24588 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24589 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24590 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24591 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24592 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24593 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24594 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24595 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24596 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24597 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24598 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24599 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24600 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24601 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24602 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24603 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24604 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24605 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24606 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24607 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24608 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24609 | 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, |
| 24610 | 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, |
| 24611 | 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, |
| 24612 | 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 24613 | 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, |
| 24614 | 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 24615 | 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 24616 | 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24617 | 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, |
| 24618 | 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, |
| 24619 | 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, |
| 24620 | 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 24621 | 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, |
| 24622 | 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 24623 | 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 24624 | 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24625 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24626 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24627 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24628 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24629 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24630 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24631 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24632 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24633 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24634 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24635 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 24636 | }; |
| 24637 | |
| 24638 | switch(AltIdx) { |
| 24639 | default: llvm_unreachable("Invalid register alt name index!"); |
| 24640 | case AArch64::NoRegAltName: |
| 24641 | assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| 24642 | "Invalid alt name index for register!"); |
| 24643 | return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| 24644 | case AArch64::vlist1: |
| 24645 | assert(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) && |
| 24646 | "Invalid alt name index for register!"); |
| 24647 | return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]; |
| 24648 | case AArch64::vreg: |
| 24649 | assert(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) && |
| 24650 | "Invalid alt name index for register!"); |
| 24651 | return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]; |
| 24652 | } |
| 24653 | } |
| 24654 | |
| 24655 | #ifdef PRINT_ALIAS_INSTR |
| 24656 | #undef PRINT_ALIAS_INSTR |
| 24657 | |
| 24658 | static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp, |
| 24659 | const MCSubtargetInfo &STI, |
| 24660 | unsigned PredicateIndex); |
| 24661 | bool AArch64InstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| 24662 | static const PatternsForOpcode OpToPatterns[] = { |
| 24663 | {.Opcode: AArch64::ADDPT_shift, .PatternStart: 0, .NumPatterns: 1 }, |
| 24664 | {.Opcode: AArch64::ADDSWri, .PatternStart: 1, .NumPatterns: 1 }, |
| 24665 | {.Opcode: AArch64::ADDSWrs, .PatternStart: 2, .NumPatterns: 3 }, |
| 24666 | {.Opcode: AArch64::ADDSWrx, .PatternStart: 5, .NumPatterns: 3 }, |
| 24667 | {.Opcode: AArch64::ADDSXri, .PatternStart: 8, .NumPatterns: 1 }, |
| 24668 | {.Opcode: AArch64::ADDSXrs, .PatternStart: 9, .NumPatterns: 3 }, |
| 24669 | {.Opcode: AArch64::ADDSXrx, .PatternStart: 12, .NumPatterns: 1 }, |
| 24670 | {.Opcode: AArch64::ADDSXrx64, .PatternStart: 13, .NumPatterns: 3 }, |
| 24671 | {.Opcode: AArch64::ADDWri, .PatternStart: 16, .NumPatterns: 2 }, |
| 24672 | {.Opcode: AArch64::ADDWrs, .PatternStart: 18, .NumPatterns: 1 }, |
| 24673 | {.Opcode: AArch64::ADDWrx, .PatternStart: 19, .NumPatterns: 2 }, |
| 24674 | {.Opcode: AArch64::ADDXri, .PatternStart: 21, .NumPatterns: 2 }, |
| 24675 | {.Opcode: AArch64::ADDXrs, .PatternStart: 23, .NumPatterns: 1 }, |
| 24676 | {.Opcode: AArch64::ADDXrx64, .PatternStart: 24, .NumPatterns: 2 }, |
| 24677 | {.Opcode: AArch64::ANDSWri, .PatternStart: 26, .NumPatterns: 1 }, |
| 24678 | {.Opcode: AArch64::ANDSWrs, .PatternStart: 27, .NumPatterns: 3 }, |
| 24679 | {.Opcode: AArch64::ANDSXri, .PatternStart: 30, .NumPatterns: 1 }, |
| 24680 | {.Opcode: AArch64::ANDSXrs, .PatternStart: 31, .NumPatterns: 3 }, |
| 24681 | {.Opcode: AArch64::ANDS_PPzPP, .PatternStart: 34, .NumPatterns: 1 }, |
| 24682 | {.Opcode: AArch64::ANDWrs, .PatternStart: 35, .NumPatterns: 1 }, |
| 24683 | {.Opcode: AArch64::ANDXrs, .PatternStart: 36, .NumPatterns: 1 }, |
| 24684 | {.Opcode: AArch64::AND_PPzPP, .PatternStart: 37, .NumPatterns: 1 }, |
| 24685 | {.Opcode: AArch64::AND_ZI, .PatternStart: 38, .NumPatterns: 3 }, |
| 24686 | {.Opcode: AArch64::AUTIA1716, .PatternStart: 41, .NumPatterns: 1 }, |
| 24687 | {.Opcode: AArch64::AUTIASP, .PatternStart: 42, .NumPatterns: 1 }, |
| 24688 | {.Opcode: AArch64::AUTIAZ, .PatternStart: 43, .NumPatterns: 1 }, |
| 24689 | {.Opcode: AArch64::AUTIB1716, .PatternStart: 44, .NumPatterns: 1 }, |
| 24690 | {.Opcode: AArch64::AUTIBSP, .PatternStart: 45, .NumPatterns: 1 }, |
| 24691 | {.Opcode: AArch64::AUTIBZ, .PatternStart: 46, .NumPatterns: 1 }, |
| 24692 | {.Opcode: AArch64::BICSWrs, .PatternStart: 47, .NumPatterns: 1 }, |
| 24693 | {.Opcode: AArch64::BICSXrs, .PatternStart: 48, .NumPatterns: 1 }, |
| 24694 | {.Opcode: AArch64::BICWrs, .PatternStart: 49, .NumPatterns: 1 }, |
| 24695 | {.Opcode: AArch64::BICXrs, .PatternStart: 50, .NumPatterns: 1 }, |
| 24696 | {.Opcode: AArch64::CHKFEAT, .PatternStart: 51, .NumPatterns: 1 }, |
| 24697 | {.Opcode: AArch64::CLREX, .PatternStart: 52, .NumPatterns: 1 }, |
| 24698 | {.Opcode: AArch64::CNTB_XPiI, .PatternStart: 53, .NumPatterns: 2 }, |
| 24699 | {.Opcode: AArch64::CNTD_XPiI, .PatternStart: 55, .NumPatterns: 2 }, |
| 24700 | {.Opcode: AArch64::CNTH_XPiI, .PatternStart: 57, .NumPatterns: 2 }, |
| 24701 | {.Opcode: AArch64::CNTW_XPiI, .PatternStart: 59, .NumPatterns: 2 }, |
| 24702 | {.Opcode: AArch64::CPY_ZPmI_B, .PatternStart: 61, .NumPatterns: 1 }, |
| 24703 | {.Opcode: AArch64::CPY_ZPmI_D, .PatternStart: 62, .NumPatterns: 1 }, |
| 24704 | {.Opcode: AArch64::CPY_ZPmI_H, .PatternStart: 63, .NumPatterns: 1 }, |
| 24705 | {.Opcode: AArch64::CPY_ZPmI_S, .PatternStart: 64, .NumPatterns: 1 }, |
| 24706 | {.Opcode: AArch64::CPY_ZPmR_B, .PatternStart: 65, .NumPatterns: 1 }, |
| 24707 | {.Opcode: AArch64::CPY_ZPmR_D, .PatternStart: 66, .NumPatterns: 1 }, |
| 24708 | {.Opcode: AArch64::CPY_ZPmR_H, .PatternStart: 67, .NumPatterns: 1 }, |
| 24709 | {.Opcode: AArch64::CPY_ZPmR_S, .PatternStart: 68, .NumPatterns: 1 }, |
| 24710 | {.Opcode: AArch64::CPY_ZPmV_B, .PatternStart: 69, .NumPatterns: 1 }, |
| 24711 | {.Opcode: AArch64::CPY_ZPmV_D, .PatternStart: 70, .NumPatterns: 1 }, |
| 24712 | {.Opcode: AArch64::CPY_ZPmV_H, .PatternStart: 71, .NumPatterns: 1 }, |
| 24713 | {.Opcode: AArch64::CPY_ZPmV_S, .PatternStart: 72, .NumPatterns: 1 }, |
| 24714 | {.Opcode: AArch64::CPY_ZPzI_B, .PatternStart: 73, .NumPatterns: 1 }, |
| 24715 | {.Opcode: AArch64::CPY_ZPzI_D, .PatternStart: 74, .NumPatterns: 1 }, |
| 24716 | {.Opcode: AArch64::CPY_ZPzI_H, .PatternStart: 75, .NumPatterns: 1 }, |
| 24717 | {.Opcode: AArch64::CPY_ZPzI_S, .PatternStart: 76, .NumPatterns: 1 }, |
| 24718 | {.Opcode: AArch64::CSINCWr, .PatternStart: 77, .NumPatterns: 2 }, |
| 24719 | {.Opcode: AArch64::CSINCXr, .PatternStart: 79, .NumPatterns: 2 }, |
| 24720 | {.Opcode: AArch64::CSINVWr, .PatternStart: 81, .NumPatterns: 2 }, |
| 24721 | {.Opcode: AArch64::CSINVXr, .PatternStart: 83, .NumPatterns: 2 }, |
| 24722 | {.Opcode: AArch64::CSNEGWr, .PatternStart: 85, .NumPatterns: 1 }, |
| 24723 | {.Opcode: AArch64::CSNEGXr, .PatternStart: 86, .NumPatterns: 1 }, |
| 24724 | {.Opcode: AArch64::DCPS1, .PatternStart: 87, .NumPatterns: 1 }, |
| 24725 | {.Opcode: AArch64::DCPS2, .PatternStart: 88, .NumPatterns: 1 }, |
| 24726 | {.Opcode: AArch64::DCPS3, .PatternStart: 89, .NumPatterns: 1 }, |
| 24727 | {.Opcode: AArch64::DECB_XPiI, .PatternStart: 90, .NumPatterns: 2 }, |
| 24728 | {.Opcode: AArch64::DECD_XPiI, .PatternStart: 92, .NumPatterns: 2 }, |
| 24729 | {.Opcode: AArch64::DECD_ZPiI, .PatternStart: 94, .NumPatterns: 2 }, |
| 24730 | {.Opcode: AArch64::DECH_XPiI, .PatternStart: 96, .NumPatterns: 2 }, |
| 24731 | {.Opcode: AArch64::DECH_ZPiI, .PatternStart: 98, .NumPatterns: 2 }, |
| 24732 | {.Opcode: AArch64::DECW_XPiI, .PatternStart: 100, .NumPatterns: 2 }, |
| 24733 | {.Opcode: AArch64::DECW_ZPiI, .PatternStart: 102, .NumPatterns: 2 }, |
| 24734 | {.Opcode: AArch64::DSB, .PatternStart: 104, .NumPatterns: 3 }, |
| 24735 | {.Opcode: AArch64::DUPM_ZI, .PatternStart: 107, .NumPatterns: 6 }, |
| 24736 | {.Opcode: AArch64::DUP_ZI_B, .PatternStart: 113, .NumPatterns: 1 }, |
| 24737 | {.Opcode: AArch64::DUP_ZI_D, .PatternStart: 114, .NumPatterns: 2 }, |
| 24738 | {.Opcode: AArch64::DUP_ZI_H, .PatternStart: 116, .NumPatterns: 2 }, |
| 24739 | {.Opcode: AArch64::DUP_ZI_S, .PatternStart: 118, .NumPatterns: 2 }, |
| 24740 | {.Opcode: AArch64::DUP_ZR_B, .PatternStart: 120, .NumPatterns: 1 }, |
| 24741 | {.Opcode: AArch64::DUP_ZR_D, .PatternStart: 121, .NumPatterns: 1 }, |
| 24742 | {.Opcode: AArch64::DUP_ZR_H, .PatternStart: 122, .NumPatterns: 1 }, |
| 24743 | {.Opcode: AArch64::DUP_ZR_S, .PatternStart: 123, .NumPatterns: 1 }, |
| 24744 | {.Opcode: AArch64::DUP_ZZI_B, .PatternStart: 124, .NumPatterns: 2 }, |
| 24745 | {.Opcode: AArch64::DUP_ZZI_D, .PatternStart: 126, .NumPatterns: 2 }, |
| 24746 | {.Opcode: AArch64::DUP_ZZI_H, .PatternStart: 128, .NumPatterns: 2 }, |
| 24747 | {.Opcode: AArch64::DUP_ZZI_Q, .PatternStart: 130, .NumPatterns: 2 }, |
| 24748 | {.Opcode: AArch64::DUP_ZZI_S, .PatternStart: 132, .NumPatterns: 2 }, |
| 24749 | {.Opcode: AArch64::EONWrs, .PatternStart: 134, .NumPatterns: 1 }, |
| 24750 | {.Opcode: AArch64::EONXrs, .PatternStart: 135, .NumPatterns: 1 }, |
| 24751 | {.Opcode: AArch64::EORS_PPzPP, .PatternStart: 136, .NumPatterns: 1 }, |
| 24752 | {.Opcode: AArch64::EORWrs, .PatternStart: 137, .NumPatterns: 1 }, |
| 24753 | {.Opcode: AArch64::EORXrs, .PatternStart: 138, .NumPatterns: 1 }, |
| 24754 | {.Opcode: AArch64::EOR_PPzPP, .PatternStart: 139, .NumPatterns: 1 }, |
| 24755 | {.Opcode: AArch64::EOR_ZI, .PatternStart: 140, .NumPatterns: 3 }, |
| 24756 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_B, .PatternStart: 143, .NumPatterns: 1 }, |
| 24757 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_D, .PatternStart: 144, .NumPatterns: 1 }, |
| 24758 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_H, .PatternStart: 145, .NumPatterns: 1 }, |
| 24759 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_Q, .PatternStart: 146, .NumPatterns: 1 }, |
| 24760 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_S, .PatternStart: 147, .NumPatterns: 1 }, |
| 24761 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_B, .PatternStart: 148, .NumPatterns: 1 }, |
| 24762 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_D, .PatternStart: 149, .NumPatterns: 1 }, |
| 24763 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_H, .PatternStart: 150, .NumPatterns: 1 }, |
| 24764 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_Q, .PatternStart: 151, .NumPatterns: 1 }, |
| 24765 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_S, .PatternStart: 152, .NumPatterns: 1 }, |
| 24766 | {.Opcode: AArch64::EXTRWrri, .PatternStart: 153, .NumPatterns: 1 }, |
| 24767 | {.Opcode: AArch64::EXTRXrri, .PatternStart: 154, .NumPatterns: 1 }, |
| 24768 | {.Opcode: AArch64::FCPY_ZPmI_D, .PatternStart: 155, .NumPatterns: 1 }, |
| 24769 | {.Opcode: AArch64::FCPY_ZPmI_H, .PatternStart: 156, .NumPatterns: 1 }, |
| 24770 | {.Opcode: AArch64::FCPY_ZPmI_S, .PatternStart: 157, .NumPatterns: 1 }, |
| 24771 | {.Opcode: AArch64::FDUP_ZI_D, .PatternStart: 158, .NumPatterns: 1 }, |
| 24772 | {.Opcode: AArch64::FDUP_ZI_H, .PatternStart: 159, .NumPatterns: 1 }, |
| 24773 | {.Opcode: AArch64::FDUP_ZI_S, .PatternStart: 160, .NumPatterns: 1 }, |
| 24774 | {.Opcode: AArch64::GCSPOPM, .PatternStart: 161, .NumPatterns: 1 }, |
| 24775 | {.Opcode: AArch64::GLD1B_D_IMM, .PatternStart: 162, .NumPatterns: 1 }, |
| 24776 | {.Opcode: AArch64::GLD1B_S_IMM, .PatternStart: 163, .NumPatterns: 1 }, |
| 24777 | {.Opcode: AArch64::GLD1D_IMM, .PatternStart: 164, .NumPatterns: 1 }, |
| 24778 | {.Opcode: AArch64::GLD1H_D_IMM, .PatternStart: 165, .NumPatterns: 1 }, |
| 24779 | {.Opcode: AArch64::GLD1H_S_IMM, .PatternStart: 166, .NumPatterns: 1 }, |
| 24780 | {.Opcode: AArch64::GLD1Q, .PatternStart: 167, .NumPatterns: 1 }, |
| 24781 | {.Opcode: AArch64::GLD1SB_D_IMM, .PatternStart: 168, .NumPatterns: 1 }, |
| 24782 | {.Opcode: AArch64::GLD1SB_S_IMM, .PatternStart: 169, .NumPatterns: 1 }, |
| 24783 | {.Opcode: AArch64::GLD1SH_D_IMM, .PatternStart: 170, .NumPatterns: 1 }, |
| 24784 | {.Opcode: AArch64::GLD1SH_S_IMM, .PatternStart: 171, .NumPatterns: 1 }, |
| 24785 | {.Opcode: AArch64::GLD1SW_D_IMM, .PatternStart: 172, .NumPatterns: 1 }, |
| 24786 | {.Opcode: AArch64::GLD1W_D_IMM, .PatternStart: 173, .NumPatterns: 1 }, |
| 24787 | {.Opcode: AArch64::GLD1W_IMM, .PatternStart: 174, .NumPatterns: 1 }, |
| 24788 | {.Opcode: AArch64::GLDFF1B_D_IMM, .PatternStart: 175, .NumPatterns: 1 }, |
| 24789 | {.Opcode: AArch64::GLDFF1B_S_IMM, .PatternStart: 176, .NumPatterns: 1 }, |
| 24790 | {.Opcode: AArch64::GLDFF1D_IMM, .PatternStart: 177, .NumPatterns: 1 }, |
| 24791 | {.Opcode: AArch64::GLDFF1H_D_IMM, .PatternStart: 178, .NumPatterns: 1 }, |
| 24792 | {.Opcode: AArch64::GLDFF1H_S_IMM, .PatternStart: 179, .NumPatterns: 1 }, |
| 24793 | {.Opcode: AArch64::GLDFF1SB_D_IMM, .PatternStart: 180, .NumPatterns: 1 }, |
| 24794 | {.Opcode: AArch64::GLDFF1SB_S_IMM, .PatternStart: 181, .NumPatterns: 1 }, |
| 24795 | {.Opcode: AArch64::GLDFF1SH_D_IMM, .PatternStart: 182, .NumPatterns: 1 }, |
| 24796 | {.Opcode: AArch64::GLDFF1SH_S_IMM, .PatternStart: 183, .NumPatterns: 1 }, |
| 24797 | {.Opcode: AArch64::GLDFF1SW_D_IMM, .PatternStart: 184, .NumPatterns: 1 }, |
| 24798 | {.Opcode: AArch64::GLDFF1W_D_IMM, .PatternStart: 185, .NumPatterns: 1 }, |
| 24799 | {.Opcode: AArch64::GLDFF1W_IMM, .PatternStart: 186, .NumPatterns: 1 }, |
| 24800 | {.Opcode: AArch64::HINT, .PatternStart: 187, .NumPatterns: 14 }, |
| 24801 | {.Opcode: AArch64::INCB_XPiI, .PatternStart: 201, .NumPatterns: 2 }, |
| 24802 | {.Opcode: AArch64::INCD_XPiI, .PatternStart: 203, .NumPatterns: 2 }, |
| 24803 | {.Opcode: AArch64::INCD_ZPiI, .PatternStart: 205, .NumPatterns: 2 }, |
| 24804 | {.Opcode: AArch64::INCH_XPiI, .PatternStart: 207, .NumPatterns: 2 }, |
| 24805 | {.Opcode: AArch64::INCH_ZPiI, .PatternStart: 209, .NumPatterns: 2 }, |
| 24806 | {.Opcode: AArch64::INCW_XPiI, .PatternStart: 211, .NumPatterns: 2 }, |
| 24807 | {.Opcode: AArch64::INCW_ZPiI, .PatternStart: 213, .NumPatterns: 2 }, |
| 24808 | {.Opcode: AArch64::INSERT_MXIPZ_H_B, .PatternStart: 215, .NumPatterns: 1 }, |
| 24809 | {.Opcode: AArch64::INSERT_MXIPZ_H_D, .PatternStart: 216, .NumPatterns: 1 }, |
| 24810 | {.Opcode: AArch64::INSERT_MXIPZ_H_H, .PatternStart: 217, .NumPatterns: 1 }, |
| 24811 | {.Opcode: AArch64::INSERT_MXIPZ_H_Q, .PatternStart: 218, .NumPatterns: 1 }, |
| 24812 | {.Opcode: AArch64::INSERT_MXIPZ_H_S, .PatternStart: 219, .NumPatterns: 1 }, |
| 24813 | {.Opcode: AArch64::INSERT_MXIPZ_V_B, .PatternStart: 220, .NumPatterns: 1 }, |
| 24814 | {.Opcode: AArch64::INSERT_MXIPZ_V_D, .PatternStart: 221, .NumPatterns: 1 }, |
| 24815 | {.Opcode: AArch64::INSERT_MXIPZ_V_H, .PatternStart: 222, .NumPatterns: 1 }, |
| 24816 | {.Opcode: AArch64::INSERT_MXIPZ_V_Q, .PatternStart: 223, .NumPatterns: 1 }, |
| 24817 | {.Opcode: AArch64::INSERT_MXIPZ_V_S, .PatternStart: 224, .NumPatterns: 1 }, |
| 24818 | {.Opcode: AArch64::INSvi16gpr, .PatternStart: 225, .NumPatterns: 1 }, |
| 24819 | {.Opcode: AArch64::INSvi16lane, .PatternStart: 226, .NumPatterns: 1 }, |
| 24820 | {.Opcode: AArch64::INSvi32gpr, .PatternStart: 227, .NumPatterns: 1 }, |
| 24821 | {.Opcode: AArch64::INSvi32lane, .PatternStart: 228, .NumPatterns: 1 }, |
| 24822 | {.Opcode: AArch64::INSvi64gpr, .PatternStart: 229, .NumPatterns: 1 }, |
| 24823 | {.Opcode: AArch64::INSvi64lane, .PatternStart: 230, .NumPatterns: 1 }, |
| 24824 | {.Opcode: AArch64::INSvi8gpr, .PatternStart: 231, .NumPatterns: 1 }, |
| 24825 | {.Opcode: AArch64::INSvi8lane, .PatternStart: 232, .NumPatterns: 1 }, |
| 24826 | {.Opcode: AArch64::IRG, .PatternStart: 233, .NumPatterns: 1 }, |
| 24827 | {.Opcode: AArch64::ISB, .PatternStart: 234, .NumPatterns: 1 }, |
| 24828 | {.Opcode: AArch64::LD1B_2Z_IMM, .PatternStart: 235, .NumPatterns: 1 }, |
| 24829 | {.Opcode: AArch64::LD1B_2Z_STRIDED_IMM, .PatternStart: 236, .NumPatterns: 1 }, |
| 24830 | {.Opcode: AArch64::LD1B_4Z_IMM, .PatternStart: 237, .NumPatterns: 1 }, |
| 24831 | {.Opcode: AArch64::LD1B_4Z_STRIDED_IMM, .PatternStart: 238, .NumPatterns: 1 }, |
| 24832 | {.Opcode: AArch64::LD1B_D_IMM, .PatternStart: 239, .NumPatterns: 1 }, |
| 24833 | {.Opcode: AArch64::LD1B_H_IMM, .PatternStart: 240, .NumPatterns: 1 }, |
| 24834 | {.Opcode: AArch64::LD1B_IMM, .PatternStart: 241, .NumPatterns: 1 }, |
| 24835 | {.Opcode: AArch64::LD1B_S_IMM, .PatternStart: 242, .NumPatterns: 1 }, |
| 24836 | {.Opcode: AArch64::LD1D_2Z_IMM, .PatternStart: 243, .NumPatterns: 1 }, |
| 24837 | {.Opcode: AArch64::LD1D_2Z_STRIDED_IMM, .PatternStart: 244, .NumPatterns: 1 }, |
| 24838 | {.Opcode: AArch64::LD1D_4Z_IMM, .PatternStart: 245, .NumPatterns: 1 }, |
| 24839 | {.Opcode: AArch64::LD1D_4Z_STRIDED_IMM, .PatternStart: 246, .NumPatterns: 1 }, |
| 24840 | {.Opcode: AArch64::LD1D_IMM, .PatternStart: 247, .NumPatterns: 1 }, |
| 24841 | {.Opcode: AArch64::LD1D_Q_IMM, .PatternStart: 248, .NumPatterns: 1 }, |
| 24842 | {.Opcode: AArch64::LD1Fourv16b_POST, .PatternStart: 249, .NumPatterns: 1 }, |
| 24843 | {.Opcode: AArch64::LD1Fourv1d_POST, .PatternStart: 250, .NumPatterns: 1 }, |
| 24844 | {.Opcode: AArch64::LD1Fourv2d_POST, .PatternStart: 251, .NumPatterns: 1 }, |
| 24845 | {.Opcode: AArch64::LD1Fourv2s_POST, .PatternStart: 252, .NumPatterns: 1 }, |
| 24846 | {.Opcode: AArch64::LD1Fourv4h_POST, .PatternStart: 253, .NumPatterns: 1 }, |
| 24847 | {.Opcode: AArch64::LD1Fourv4s_POST, .PatternStart: 254, .NumPatterns: 1 }, |
| 24848 | {.Opcode: AArch64::LD1Fourv8b_POST, .PatternStart: 255, .NumPatterns: 1 }, |
| 24849 | {.Opcode: AArch64::LD1Fourv8h_POST, .PatternStart: 256, .NumPatterns: 1 }, |
| 24850 | {.Opcode: AArch64::LD1H_2Z_IMM, .PatternStart: 257, .NumPatterns: 1 }, |
| 24851 | {.Opcode: AArch64::LD1H_2Z_STRIDED_IMM, .PatternStart: 258, .NumPatterns: 1 }, |
| 24852 | {.Opcode: AArch64::LD1H_4Z_IMM, .PatternStart: 259, .NumPatterns: 1 }, |
| 24853 | {.Opcode: AArch64::LD1H_4Z_STRIDED_IMM, .PatternStart: 260, .NumPatterns: 1 }, |
| 24854 | {.Opcode: AArch64::LD1H_D_IMM, .PatternStart: 261, .NumPatterns: 1 }, |
| 24855 | {.Opcode: AArch64::LD1H_IMM, .PatternStart: 262, .NumPatterns: 1 }, |
| 24856 | {.Opcode: AArch64::LD1H_S_IMM, .PatternStart: 263, .NumPatterns: 1 }, |
| 24857 | {.Opcode: AArch64::LD1Onev16b_POST, .PatternStart: 264, .NumPatterns: 1 }, |
| 24858 | {.Opcode: AArch64::LD1Onev1d_POST, .PatternStart: 265, .NumPatterns: 1 }, |
| 24859 | {.Opcode: AArch64::LD1Onev2d_POST, .PatternStart: 266, .NumPatterns: 1 }, |
| 24860 | {.Opcode: AArch64::LD1Onev2s_POST, .PatternStart: 267, .NumPatterns: 1 }, |
| 24861 | {.Opcode: AArch64::LD1Onev4h_POST, .PatternStart: 268, .NumPatterns: 1 }, |
| 24862 | {.Opcode: AArch64::LD1Onev4s_POST, .PatternStart: 269, .NumPatterns: 1 }, |
| 24863 | {.Opcode: AArch64::LD1Onev8b_POST, .PatternStart: 270, .NumPatterns: 1 }, |
| 24864 | {.Opcode: AArch64::LD1Onev8h_POST, .PatternStart: 271, .NumPatterns: 1 }, |
| 24865 | {.Opcode: AArch64::LD1RB_D_IMM, .PatternStart: 272, .NumPatterns: 1 }, |
| 24866 | {.Opcode: AArch64::LD1RB_H_IMM, .PatternStart: 273, .NumPatterns: 1 }, |
| 24867 | {.Opcode: AArch64::LD1RB_IMM, .PatternStart: 274, .NumPatterns: 1 }, |
| 24868 | {.Opcode: AArch64::LD1RB_S_IMM, .PatternStart: 275, .NumPatterns: 1 }, |
| 24869 | {.Opcode: AArch64::LD1RD_IMM, .PatternStart: 276, .NumPatterns: 1 }, |
| 24870 | {.Opcode: AArch64::LD1RH_D_IMM, .PatternStart: 277, .NumPatterns: 1 }, |
| 24871 | {.Opcode: AArch64::LD1RH_IMM, .PatternStart: 278, .NumPatterns: 1 }, |
| 24872 | {.Opcode: AArch64::LD1RH_S_IMM, .PatternStart: 279, .NumPatterns: 1 }, |
| 24873 | {.Opcode: AArch64::LD1RO_B_IMM, .PatternStart: 280, .NumPatterns: 1 }, |
| 24874 | {.Opcode: AArch64::LD1RO_D_IMM, .PatternStart: 281, .NumPatterns: 1 }, |
| 24875 | {.Opcode: AArch64::LD1RO_H_IMM, .PatternStart: 282, .NumPatterns: 1 }, |
| 24876 | {.Opcode: AArch64::LD1RO_W_IMM, .PatternStart: 283, .NumPatterns: 1 }, |
| 24877 | {.Opcode: AArch64::LD1RQ_B_IMM, .PatternStart: 284, .NumPatterns: 1 }, |
| 24878 | {.Opcode: AArch64::LD1RQ_D_IMM, .PatternStart: 285, .NumPatterns: 1 }, |
| 24879 | {.Opcode: AArch64::LD1RQ_H_IMM, .PatternStart: 286, .NumPatterns: 1 }, |
| 24880 | {.Opcode: AArch64::LD1RQ_W_IMM, .PatternStart: 287, .NumPatterns: 1 }, |
| 24881 | {.Opcode: AArch64::LD1RSB_D_IMM, .PatternStart: 288, .NumPatterns: 1 }, |
| 24882 | {.Opcode: AArch64::LD1RSB_H_IMM, .PatternStart: 289, .NumPatterns: 1 }, |
| 24883 | {.Opcode: AArch64::LD1RSB_S_IMM, .PatternStart: 290, .NumPatterns: 1 }, |
| 24884 | {.Opcode: AArch64::LD1RSH_D_IMM, .PatternStart: 291, .NumPatterns: 1 }, |
| 24885 | {.Opcode: AArch64::LD1RSH_S_IMM, .PatternStart: 292, .NumPatterns: 1 }, |
| 24886 | {.Opcode: AArch64::LD1RSW_IMM, .PatternStart: 293, .NumPatterns: 1 }, |
| 24887 | {.Opcode: AArch64::LD1RW_D_IMM, .PatternStart: 294, .NumPatterns: 1 }, |
| 24888 | {.Opcode: AArch64::LD1RW_IMM, .PatternStart: 295, .NumPatterns: 1 }, |
| 24889 | {.Opcode: AArch64::LD1Rv16b_POST, .PatternStart: 296, .NumPatterns: 1 }, |
| 24890 | {.Opcode: AArch64::LD1Rv1d_POST, .PatternStart: 297, .NumPatterns: 1 }, |
| 24891 | {.Opcode: AArch64::LD1Rv2d_POST, .PatternStart: 298, .NumPatterns: 1 }, |
| 24892 | {.Opcode: AArch64::LD1Rv2s_POST, .PatternStart: 299, .NumPatterns: 1 }, |
| 24893 | {.Opcode: AArch64::LD1Rv4h_POST, .PatternStart: 300, .NumPatterns: 1 }, |
| 24894 | {.Opcode: AArch64::LD1Rv4s_POST, .PatternStart: 301, .NumPatterns: 1 }, |
| 24895 | {.Opcode: AArch64::LD1Rv8b_POST, .PatternStart: 302, .NumPatterns: 1 }, |
| 24896 | {.Opcode: AArch64::LD1Rv8h_POST, .PatternStart: 303, .NumPatterns: 1 }, |
| 24897 | {.Opcode: AArch64::LD1SB_D_IMM, .PatternStart: 304, .NumPatterns: 1 }, |
| 24898 | {.Opcode: AArch64::LD1SB_H_IMM, .PatternStart: 305, .NumPatterns: 1 }, |
| 24899 | {.Opcode: AArch64::LD1SB_S_IMM, .PatternStart: 306, .NumPatterns: 1 }, |
| 24900 | {.Opcode: AArch64::LD1SH_D_IMM, .PatternStart: 307, .NumPatterns: 1 }, |
| 24901 | {.Opcode: AArch64::LD1SH_S_IMM, .PatternStart: 308, .NumPatterns: 1 }, |
| 24902 | {.Opcode: AArch64::LD1SW_D_IMM, .PatternStart: 309, .NumPatterns: 1 }, |
| 24903 | {.Opcode: AArch64::LD1Threev16b_POST, .PatternStart: 310, .NumPatterns: 1 }, |
| 24904 | {.Opcode: AArch64::LD1Threev1d_POST, .PatternStart: 311, .NumPatterns: 1 }, |
| 24905 | {.Opcode: AArch64::LD1Threev2d_POST, .PatternStart: 312, .NumPatterns: 1 }, |
| 24906 | {.Opcode: AArch64::LD1Threev2s_POST, .PatternStart: 313, .NumPatterns: 1 }, |
| 24907 | {.Opcode: AArch64::LD1Threev4h_POST, .PatternStart: 314, .NumPatterns: 1 }, |
| 24908 | {.Opcode: AArch64::LD1Threev4s_POST, .PatternStart: 315, .NumPatterns: 1 }, |
| 24909 | {.Opcode: AArch64::LD1Threev8b_POST, .PatternStart: 316, .NumPatterns: 1 }, |
| 24910 | {.Opcode: AArch64::LD1Threev8h_POST, .PatternStart: 317, .NumPatterns: 1 }, |
| 24911 | {.Opcode: AArch64::LD1Twov16b_POST, .PatternStart: 318, .NumPatterns: 1 }, |
| 24912 | {.Opcode: AArch64::LD1Twov1d_POST, .PatternStart: 319, .NumPatterns: 1 }, |
| 24913 | {.Opcode: AArch64::LD1Twov2d_POST, .PatternStart: 320, .NumPatterns: 1 }, |
| 24914 | {.Opcode: AArch64::LD1Twov2s_POST, .PatternStart: 321, .NumPatterns: 1 }, |
| 24915 | {.Opcode: AArch64::LD1Twov4h_POST, .PatternStart: 322, .NumPatterns: 1 }, |
| 24916 | {.Opcode: AArch64::LD1Twov4s_POST, .PatternStart: 323, .NumPatterns: 1 }, |
| 24917 | {.Opcode: AArch64::LD1Twov8b_POST, .PatternStart: 324, .NumPatterns: 1 }, |
| 24918 | {.Opcode: AArch64::LD1Twov8h_POST, .PatternStart: 325, .NumPatterns: 1 }, |
| 24919 | {.Opcode: AArch64::LD1W_2Z_IMM, .PatternStart: 326, .NumPatterns: 1 }, |
| 24920 | {.Opcode: AArch64::LD1W_2Z_STRIDED_IMM, .PatternStart: 327, .NumPatterns: 1 }, |
| 24921 | {.Opcode: AArch64::LD1W_4Z_IMM, .PatternStart: 328, .NumPatterns: 1 }, |
| 24922 | {.Opcode: AArch64::LD1W_4Z_STRIDED_IMM, .PatternStart: 329, .NumPatterns: 1 }, |
| 24923 | {.Opcode: AArch64::LD1W_D_IMM, .PatternStart: 330, .NumPatterns: 1 }, |
| 24924 | {.Opcode: AArch64::LD1W_IMM, .PatternStart: 331, .NumPatterns: 1 }, |
| 24925 | {.Opcode: AArch64::LD1W_Q_IMM, .PatternStart: 332, .NumPatterns: 1 }, |
| 24926 | {.Opcode: AArch64::LD1_MXIPXX_H_B, .PatternStart: 333, .NumPatterns: 1 }, |
| 24927 | {.Opcode: AArch64::LD1_MXIPXX_H_D, .PatternStart: 334, .NumPatterns: 1 }, |
| 24928 | {.Opcode: AArch64::LD1_MXIPXX_H_H, .PatternStart: 335, .NumPatterns: 1 }, |
| 24929 | {.Opcode: AArch64::LD1_MXIPXX_H_Q, .PatternStart: 336, .NumPatterns: 1 }, |
| 24930 | {.Opcode: AArch64::LD1_MXIPXX_H_S, .PatternStart: 337, .NumPatterns: 1 }, |
| 24931 | {.Opcode: AArch64::LD1_MXIPXX_V_B, .PatternStart: 338, .NumPatterns: 1 }, |
| 24932 | {.Opcode: AArch64::LD1_MXIPXX_V_D, .PatternStart: 339, .NumPatterns: 1 }, |
| 24933 | {.Opcode: AArch64::LD1_MXIPXX_V_H, .PatternStart: 340, .NumPatterns: 1 }, |
| 24934 | {.Opcode: AArch64::LD1_MXIPXX_V_Q, .PatternStart: 341, .NumPatterns: 1 }, |
| 24935 | {.Opcode: AArch64::LD1_MXIPXX_V_S, .PatternStart: 342, .NumPatterns: 1 }, |
| 24936 | {.Opcode: AArch64::LD1i16_POST, .PatternStart: 343, .NumPatterns: 1 }, |
| 24937 | {.Opcode: AArch64::LD1i32_POST, .PatternStart: 344, .NumPatterns: 1 }, |
| 24938 | {.Opcode: AArch64::LD1i64_POST, .PatternStart: 345, .NumPatterns: 1 }, |
| 24939 | {.Opcode: AArch64::LD1i8_POST, .PatternStart: 346, .NumPatterns: 1 }, |
| 24940 | {.Opcode: AArch64::LD2B_IMM, .PatternStart: 347, .NumPatterns: 1 }, |
| 24941 | {.Opcode: AArch64::LD2D_IMM, .PatternStart: 348, .NumPatterns: 1 }, |
| 24942 | {.Opcode: AArch64::LD2H_IMM, .PatternStart: 349, .NumPatterns: 1 }, |
| 24943 | {.Opcode: AArch64::LD2Q_IMM, .PatternStart: 350, .NumPatterns: 1 }, |
| 24944 | {.Opcode: AArch64::LD2Rv16b_POST, .PatternStart: 351, .NumPatterns: 1 }, |
| 24945 | {.Opcode: AArch64::LD2Rv1d_POST, .PatternStart: 352, .NumPatterns: 1 }, |
| 24946 | {.Opcode: AArch64::LD2Rv2d_POST, .PatternStart: 353, .NumPatterns: 1 }, |
| 24947 | {.Opcode: AArch64::LD2Rv2s_POST, .PatternStart: 354, .NumPatterns: 1 }, |
| 24948 | {.Opcode: AArch64::LD2Rv4h_POST, .PatternStart: 355, .NumPatterns: 1 }, |
| 24949 | {.Opcode: AArch64::LD2Rv4s_POST, .PatternStart: 356, .NumPatterns: 1 }, |
| 24950 | {.Opcode: AArch64::LD2Rv8b_POST, .PatternStart: 357, .NumPatterns: 1 }, |
| 24951 | {.Opcode: AArch64::LD2Rv8h_POST, .PatternStart: 358, .NumPatterns: 1 }, |
| 24952 | {.Opcode: AArch64::LD2Twov16b_POST, .PatternStart: 359, .NumPatterns: 1 }, |
| 24953 | {.Opcode: AArch64::LD2Twov2d_POST, .PatternStart: 360, .NumPatterns: 1 }, |
| 24954 | {.Opcode: AArch64::LD2Twov2s_POST, .PatternStart: 361, .NumPatterns: 1 }, |
| 24955 | {.Opcode: AArch64::LD2Twov4h_POST, .PatternStart: 362, .NumPatterns: 1 }, |
| 24956 | {.Opcode: AArch64::LD2Twov4s_POST, .PatternStart: 363, .NumPatterns: 1 }, |
| 24957 | {.Opcode: AArch64::LD2Twov8b_POST, .PatternStart: 364, .NumPatterns: 1 }, |
| 24958 | {.Opcode: AArch64::LD2Twov8h_POST, .PatternStart: 365, .NumPatterns: 1 }, |
| 24959 | {.Opcode: AArch64::LD2W_IMM, .PatternStart: 366, .NumPatterns: 1 }, |
| 24960 | {.Opcode: AArch64::LD2i16_POST, .PatternStart: 367, .NumPatterns: 1 }, |
| 24961 | {.Opcode: AArch64::LD2i32_POST, .PatternStart: 368, .NumPatterns: 1 }, |
| 24962 | {.Opcode: AArch64::LD2i64_POST, .PatternStart: 369, .NumPatterns: 1 }, |
| 24963 | {.Opcode: AArch64::LD2i8_POST, .PatternStart: 370, .NumPatterns: 1 }, |
| 24964 | {.Opcode: AArch64::LD3B_IMM, .PatternStart: 371, .NumPatterns: 1 }, |
| 24965 | {.Opcode: AArch64::LD3D_IMM, .PatternStart: 372, .NumPatterns: 1 }, |
| 24966 | {.Opcode: AArch64::LD3H_IMM, .PatternStart: 373, .NumPatterns: 1 }, |
| 24967 | {.Opcode: AArch64::LD3Q_IMM, .PatternStart: 374, .NumPatterns: 1 }, |
| 24968 | {.Opcode: AArch64::LD3Rv16b_POST, .PatternStart: 375, .NumPatterns: 1 }, |
| 24969 | {.Opcode: AArch64::LD3Rv1d_POST, .PatternStart: 376, .NumPatterns: 1 }, |
| 24970 | {.Opcode: AArch64::LD3Rv2d_POST, .PatternStart: 377, .NumPatterns: 1 }, |
| 24971 | {.Opcode: AArch64::LD3Rv2s_POST, .PatternStart: 378, .NumPatterns: 1 }, |
| 24972 | {.Opcode: AArch64::LD3Rv4h_POST, .PatternStart: 379, .NumPatterns: 1 }, |
| 24973 | {.Opcode: AArch64::LD3Rv4s_POST, .PatternStart: 380, .NumPatterns: 1 }, |
| 24974 | {.Opcode: AArch64::LD3Rv8b_POST, .PatternStart: 381, .NumPatterns: 1 }, |
| 24975 | {.Opcode: AArch64::LD3Rv8h_POST, .PatternStart: 382, .NumPatterns: 1 }, |
| 24976 | {.Opcode: AArch64::LD3Threev16b_POST, .PatternStart: 383, .NumPatterns: 1 }, |
| 24977 | {.Opcode: AArch64::LD3Threev2d_POST, .PatternStart: 384, .NumPatterns: 1 }, |
| 24978 | {.Opcode: AArch64::LD3Threev2s_POST, .PatternStart: 385, .NumPatterns: 1 }, |
| 24979 | {.Opcode: AArch64::LD3Threev4h_POST, .PatternStart: 386, .NumPatterns: 1 }, |
| 24980 | {.Opcode: AArch64::LD3Threev4s_POST, .PatternStart: 387, .NumPatterns: 1 }, |
| 24981 | {.Opcode: AArch64::LD3Threev8b_POST, .PatternStart: 388, .NumPatterns: 1 }, |
| 24982 | {.Opcode: AArch64::LD3Threev8h_POST, .PatternStart: 389, .NumPatterns: 1 }, |
| 24983 | {.Opcode: AArch64::LD3W_IMM, .PatternStart: 390, .NumPatterns: 1 }, |
| 24984 | {.Opcode: AArch64::LD3i16_POST, .PatternStart: 391, .NumPatterns: 1 }, |
| 24985 | {.Opcode: AArch64::LD3i32_POST, .PatternStart: 392, .NumPatterns: 1 }, |
| 24986 | {.Opcode: AArch64::LD3i64_POST, .PatternStart: 393, .NumPatterns: 1 }, |
| 24987 | {.Opcode: AArch64::LD3i8_POST, .PatternStart: 394, .NumPatterns: 1 }, |
| 24988 | {.Opcode: AArch64::LD4B_IMM, .PatternStart: 395, .NumPatterns: 1 }, |
| 24989 | {.Opcode: AArch64::LD4D_IMM, .PatternStart: 396, .NumPatterns: 1 }, |
| 24990 | {.Opcode: AArch64::LD4Fourv16b_POST, .PatternStart: 397, .NumPatterns: 1 }, |
| 24991 | {.Opcode: AArch64::LD4Fourv2d_POST, .PatternStart: 398, .NumPatterns: 1 }, |
| 24992 | {.Opcode: AArch64::LD4Fourv2s_POST, .PatternStart: 399, .NumPatterns: 1 }, |
| 24993 | {.Opcode: AArch64::LD4Fourv4h_POST, .PatternStart: 400, .NumPatterns: 1 }, |
| 24994 | {.Opcode: AArch64::LD4Fourv4s_POST, .PatternStart: 401, .NumPatterns: 1 }, |
| 24995 | {.Opcode: AArch64::LD4Fourv8b_POST, .PatternStart: 402, .NumPatterns: 1 }, |
| 24996 | {.Opcode: AArch64::LD4Fourv8h_POST, .PatternStart: 403, .NumPatterns: 1 }, |
| 24997 | {.Opcode: AArch64::LD4H_IMM, .PatternStart: 404, .NumPatterns: 1 }, |
| 24998 | {.Opcode: AArch64::LD4Q_IMM, .PatternStart: 405, .NumPatterns: 1 }, |
| 24999 | {.Opcode: AArch64::LD4Rv16b_POST, .PatternStart: 406, .NumPatterns: 1 }, |
| 25000 | {.Opcode: AArch64::LD4Rv1d_POST, .PatternStart: 407, .NumPatterns: 1 }, |
| 25001 | {.Opcode: AArch64::LD4Rv2d_POST, .PatternStart: 408, .NumPatterns: 1 }, |
| 25002 | {.Opcode: AArch64::LD4Rv2s_POST, .PatternStart: 409, .NumPatterns: 1 }, |
| 25003 | {.Opcode: AArch64::LD4Rv4h_POST, .PatternStart: 410, .NumPatterns: 1 }, |
| 25004 | {.Opcode: AArch64::LD4Rv4s_POST, .PatternStart: 411, .NumPatterns: 1 }, |
| 25005 | {.Opcode: AArch64::LD4Rv8b_POST, .PatternStart: 412, .NumPatterns: 1 }, |
| 25006 | {.Opcode: AArch64::LD4Rv8h_POST, .PatternStart: 413, .NumPatterns: 1 }, |
| 25007 | {.Opcode: AArch64::LD4W_IMM, .PatternStart: 414, .NumPatterns: 1 }, |
| 25008 | {.Opcode: AArch64::LD4i16_POST, .PatternStart: 415, .NumPatterns: 1 }, |
| 25009 | {.Opcode: AArch64::LD4i32_POST, .PatternStart: 416, .NumPatterns: 1 }, |
| 25010 | {.Opcode: AArch64::LD4i64_POST, .PatternStart: 417, .NumPatterns: 1 }, |
| 25011 | {.Opcode: AArch64::LD4i8_POST, .PatternStart: 418, .NumPatterns: 1 }, |
| 25012 | {.Opcode: AArch64::LDADDB, .PatternStart: 419, .NumPatterns: 1 }, |
| 25013 | {.Opcode: AArch64::LDADDH, .PatternStart: 420, .NumPatterns: 1 }, |
| 25014 | {.Opcode: AArch64::LDADDLB, .PatternStart: 421, .NumPatterns: 1 }, |
| 25015 | {.Opcode: AArch64::LDADDLH, .PatternStart: 422, .NumPatterns: 1 }, |
| 25016 | {.Opcode: AArch64::LDADDLW, .PatternStart: 423, .NumPatterns: 1 }, |
| 25017 | {.Opcode: AArch64::LDADDLX, .PatternStart: 424, .NumPatterns: 1 }, |
| 25018 | {.Opcode: AArch64::LDADDW, .PatternStart: 425, .NumPatterns: 1 }, |
| 25019 | {.Opcode: AArch64::LDADDX, .PatternStart: 426, .NumPatterns: 1 }, |
| 25020 | {.Opcode: AArch64::LDAPPi, .PatternStart: 427, .NumPatterns: 1 }, |
| 25021 | {.Opcode: AArch64::LDAPURBi, .PatternStart: 428, .NumPatterns: 1 }, |
| 25022 | {.Opcode: AArch64::LDAPURHi, .PatternStart: 429, .NumPatterns: 1 }, |
| 25023 | {.Opcode: AArch64::LDAPURSBWi, .PatternStart: 430, .NumPatterns: 1 }, |
| 25024 | {.Opcode: AArch64::LDAPURSBXi, .PatternStart: 431, .NumPatterns: 1 }, |
| 25025 | {.Opcode: AArch64::LDAPURSHWi, .PatternStart: 432, .NumPatterns: 1 }, |
| 25026 | {.Opcode: AArch64::LDAPURSHXi, .PatternStart: 433, .NumPatterns: 1 }, |
| 25027 | {.Opcode: AArch64::LDAPURSWi, .PatternStart: 434, .NumPatterns: 1 }, |
| 25028 | {.Opcode: AArch64::LDAPURXi, .PatternStart: 435, .NumPatterns: 1 }, |
| 25029 | {.Opcode: AArch64::LDAPURbi, .PatternStart: 436, .NumPatterns: 1 }, |
| 25030 | {.Opcode: AArch64::LDAPURdi, .PatternStart: 437, .NumPatterns: 1 }, |
| 25031 | {.Opcode: AArch64::LDAPURhi, .PatternStart: 438, .NumPatterns: 1 }, |
| 25032 | {.Opcode: AArch64::LDAPURi, .PatternStart: 439, .NumPatterns: 1 }, |
| 25033 | {.Opcode: AArch64::LDAPURqi, .PatternStart: 440, .NumPatterns: 1 }, |
| 25034 | {.Opcode: AArch64::LDAPURsi, .PatternStart: 441, .NumPatterns: 1 }, |
| 25035 | {.Opcode: AArch64::LDAPi, .PatternStart: 442, .NumPatterns: 1 }, |
| 25036 | {.Opcode: AArch64::LDCLRB, .PatternStart: 443, .NumPatterns: 1 }, |
| 25037 | {.Opcode: AArch64::LDCLRH, .PatternStart: 444, .NumPatterns: 1 }, |
| 25038 | {.Opcode: AArch64::LDCLRLB, .PatternStart: 445, .NumPatterns: 1 }, |
| 25039 | {.Opcode: AArch64::LDCLRLH, .PatternStart: 446, .NumPatterns: 1 }, |
| 25040 | {.Opcode: AArch64::LDCLRLW, .PatternStart: 447, .NumPatterns: 1 }, |
| 25041 | {.Opcode: AArch64::LDCLRLX, .PatternStart: 448, .NumPatterns: 1 }, |
| 25042 | {.Opcode: AArch64::LDCLRW, .PatternStart: 449, .NumPatterns: 1 }, |
| 25043 | {.Opcode: AArch64::LDCLRX, .PatternStart: 450, .NumPatterns: 1 }, |
| 25044 | {.Opcode: AArch64::LDEORB, .PatternStart: 451, .NumPatterns: 1 }, |
| 25045 | {.Opcode: AArch64::LDEORH, .PatternStart: 452, .NumPatterns: 1 }, |
| 25046 | {.Opcode: AArch64::LDEORLB, .PatternStart: 453, .NumPatterns: 1 }, |
| 25047 | {.Opcode: AArch64::LDEORLH, .PatternStart: 454, .NumPatterns: 1 }, |
| 25048 | {.Opcode: AArch64::LDEORLW, .PatternStart: 455, .NumPatterns: 1 }, |
| 25049 | {.Opcode: AArch64::LDEORLX, .PatternStart: 456, .NumPatterns: 1 }, |
| 25050 | {.Opcode: AArch64::LDEORW, .PatternStart: 457, .NumPatterns: 1 }, |
| 25051 | {.Opcode: AArch64::LDEORX, .PatternStart: 458, .NumPatterns: 1 }, |
| 25052 | {.Opcode: AArch64::LDFF1B, .PatternStart: 459, .NumPatterns: 1 }, |
| 25053 | {.Opcode: AArch64::LDFF1B_D, .PatternStart: 460, .NumPatterns: 1 }, |
| 25054 | {.Opcode: AArch64::LDFF1B_H, .PatternStart: 461, .NumPatterns: 1 }, |
| 25055 | {.Opcode: AArch64::LDFF1B_S, .PatternStart: 462, .NumPatterns: 1 }, |
| 25056 | {.Opcode: AArch64::LDFF1D, .PatternStart: 463, .NumPatterns: 1 }, |
| 25057 | {.Opcode: AArch64::LDFF1H, .PatternStart: 464, .NumPatterns: 1 }, |
| 25058 | {.Opcode: AArch64::LDFF1H_D, .PatternStart: 465, .NumPatterns: 1 }, |
| 25059 | {.Opcode: AArch64::LDFF1H_S, .PatternStart: 466, .NumPatterns: 1 }, |
| 25060 | {.Opcode: AArch64::LDFF1SB_D, .PatternStart: 467, .NumPatterns: 1 }, |
| 25061 | {.Opcode: AArch64::LDFF1SB_H, .PatternStart: 468, .NumPatterns: 1 }, |
| 25062 | {.Opcode: AArch64::LDFF1SB_S, .PatternStart: 469, .NumPatterns: 1 }, |
| 25063 | {.Opcode: AArch64::LDFF1SH_D, .PatternStart: 470, .NumPatterns: 1 }, |
| 25064 | {.Opcode: AArch64::LDFF1SH_S, .PatternStart: 471, .NumPatterns: 1 }, |
| 25065 | {.Opcode: AArch64::LDFF1SW_D, .PatternStart: 472, .NumPatterns: 1 }, |
| 25066 | {.Opcode: AArch64::LDFF1W, .PatternStart: 473, .NumPatterns: 1 }, |
| 25067 | {.Opcode: AArch64::LDFF1W_D, .PatternStart: 474, .NumPatterns: 1 }, |
| 25068 | {.Opcode: AArch64::LDG, .PatternStart: 475, .NumPatterns: 1 }, |
| 25069 | {.Opcode: AArch64::LDNF1B_D_IMM, .PatternStart: 476, .NumPatterns: 1 }, |
| 25070 | {.Opcode: AArch64::LDNF1B_H_IMM, .PatternStart: 477, .NumPatterns: 1 }, |
| 25071 | {.Opcode: AArch64::LDNF1B_IMM, .PatternStart: 478, .NumPatterns: 1 }, |
| 25072 | {.Opcode: AArch64::LDNF1B_S_IMM, .PatternStart: 479, .NumPatterns: 1 }, |
| 25073 | {.Opcode: AArch64::LDNF1D_IMM, .PatternStart: 480, .NumPatterns: 1 }, |
| 25074 | {.Opcode: AArch64::LDNF1H_D_IMM, .PatternStart: 481, .NumPatterns: 1 }, |
| 25075 | {.Opcode: AArch64::LDNF1H_IMM, .PatternStart: 482, .NumPatterns: 1 }, |
| 25076 | {.Opcode: AArch64::LDNF1H_S_IMM, .PatternStart: 483, .NumPatterns: 1 }, |
| 25077 | {.Opcode: AArch64::LDNF1SB_D_IMM, .PatternStart: 484, .NumPatterns: 1 }, |
| 25078 | {.Opcode: AArch64::LDNF1SB_H_IMM, .PatternStart: 485, .NumPatterns: 1 }, |
| 25079 | {.Opcode: AArch64::LDNF1SB_S_IMM, .PatternStart: 486, .NumPatterns: 1 }, |
| 25080 | {.Opcode: AArch64::LDNF1SH_D_IMM, .PatternStart: 487, .NumPatterns: 1 }, |
| 25081 | {.Opcode: AArch64::LDNF1SH_S_IMM, .PatternStart: 488, .NumPatterns: 1 }, |
| 25082 | {.Opcode: AArch64::LDNF1SW_D_IMM, .PatternStart: 489, .NumPatterns: 1 }, |
| 25083 | {.Opcode: AArch64::LDNF1W_D_IMM, .PatternStart: 490, .NumPatterns: 1 }, |
| 25084 | {.Opcode: AArch64::LDNF1W_IMM, .PatternStart: 491, .NumPatterns: 1 }, |
| 25085 | {.Opcode: AArch64::LDNPDi, .PatternStart: 492, .NumPatterns: 1 }, |
| 25086 | {.Opcode: AArch64::LDNPQi, .PatternStart: 493, .NumPatterns: 1 }, |
| 25087 | {.Opcode: AArch64::LDNPSi, .PatternStart: 494, .NumPatterns: 1 }, |
| 25088 | {.Opcode: AArch64::LDNPWi, .PatternStart: 495, .NumPatterns: 1 }, |
| 25089 | {.Opcode: AArch64::LDNPXi, .PatternStart: 496, .NumPatterns: 1 }, |
| 25090 | {.Opcode: AArch64::LDNT1B_2Z_IMM, .PatternStart: 497, .NumPatterns: 1 }, |
| 25091 | {.Opcode: AArch64::LDNT1B_2Z_STRIDED_IMM, .PatternStart: 498, .NumPatterns: 1 }, |
| 25092 | {.Opcode: AArch64::LDNT1B_4Z_IMM, .PatternStart: 499, .NumPatterns: 1 }, |
| 25093 | {.Opcode: AArch64::LDNT1B_4Z_STRIDED_IMM, .PatternStart: 500, .NumPatterns: 1 }, |
| 25094 | {.Opcode: AArch64::LDNT1B_ZRI, .PatternStart: 501, .NumPatterns: 1 }, |
| 25095 | {.Opcode: AArch64::LDNT1B_ZZR_D, .PatternStart: 502, .NumPatterns: 1 }, |
| 25096 | {.Opcode: AArch64::LDNT1B_ZZR_S, .PatternStart: 503, .NumPatterns: 1 }, |
| 25097 | {.Opcode: AArch64::LDNT1D_2Z_IMM, .PatternStart: 504, .NumPatterns: 1 }, |
| 25098 | {.Opcode: AArch64::LDNT1D_2Z_STRIDED_IMM, .PatternStart: 505, .NumPatterns: 1 }, |
| 25099 | {.Opcode: AArch64::LDNT1D_4Z_IMM, .PatternStart: 506, .NumPatterns: 1 }, |
| 25100 | {.Opcode: AArch64::LDNT1D_4Z_STRIDED_IMM, .PatternStart: 507, .NumPatterns: 1 }, |
| 25101 | {.Opcode: AArch64::LDNT1D_ZRI, .PatternStart: 508, .NumPatterns: 1 }, |
| 25102 | {.Opcode: AArch64::LDNT1D_ZZR_D, .PatternStart: 509, .NumPatterns: 1 }, |
| 25103 | {.Opcode: AArch64::LDNT1H_2Z_IMM, .PatternStart: 510, .NumPatterns: 1 }, |
| 25104 | {.Opcode: AArch64::LDNT1H_2Z_STRIDED_IMM, .PatternStart: 511, .NumPatterns: 1 }, |
| 25105 | {.Opcode: AArch64::LDNT1H_4Z_IMM, .PatternStart: 512, .NumPatterns: 1 }, |
| 25106 | {.Opcode: AArch64::LDNT1H_4Z_STRIDED_IMM, .PatternStart: 513, .NumPatterns: 1 }, |
| 25107 | {.Opcode: AArch64::LDNT1H_ZRI, .PatternStart: 514, .NumPatterns: 1 }, |
| 25108 | {.Opcode: AArch64::LDNT1H_ZZR_D, .PatternStart: 515, .NumPatterns: 1 }, |
| 25109 | {.Opcode: AArch64::LDNT1H_ZZR_S, .PatternStart: 516, .NumPatterns: 1 }, |
| 25110 | {.Opcode: AArch64::LDNT1SB_ZZR_D, .PatternStart: 517, .NumPatterns: 1 }, |
| 25111 | {.Opcode: AArch64::LDNT1SB_ZZR_S, .PatternStart: 518, .NumPatterns: 1 }, |
| 25112 | {.Opcode: AArch64::LDNT1SH_ZZR_D, .PatternStart: 519, .NumPatterns: 1 }, |
| 25113 | {.Opcode: AArch64::LDNT1SH_ZZR_S, .PatternStart: 520, .NumPatterns: 1 }, |
| 25114 | {.Opcode: AArch64::LDNT1SW_ZZR_D, .PatternStart: 521, .NumPatterns: 1 }, |
| 25115 | {.Opcode: AArch64::LDNT1W_2Z_IMM, .PatternStart: 522, .NumPatterns: 1 }, |
| 25116 | {.Opcode: AArch64::LDNT1W_2Z_STRIDED_IMM, .PatternStart: 523, .NumPatterns: 1 }, |
| 25117 | {.Opcode: AArch64::LDNT1W_4Z_IMM, .PatternStart: 524, .NumPatterns: 1 }, |
| 25118 | {.Opcode: AArch64::LDNT1W_4Z_STRIDED_IMM, .PatternStart: 525, .NumPatterns: 1 }, |
| 25119 | {.Opcode: AArch64::LDNT1W_ZRI, .PatternStart: 526, .NumPatterns: 1 }, |
| 25120 | {.Opcode: AArch64::LDNT1W_ZZR_D, .PatternStart: 527, .NumPatterns: 1 }, |
| 25121 | {.Opcode: AArch64::LDNT1W_ZZR_S, .PatternStart: 528, .NumPatterns: 1 }, |
| 25122 | {.Opcode: AArch64::LDPDi, .PatternStart: 529, .NumPatterns: 1 }, |
| 25123 | {.Opcode: AArch64::LDPQi, .PatternStart: 530, .NumPatterns: 1 }, |
| 25124 | {.Opcode: AArch64::LDPSWi, .PatternStart: 531, .NumPatterns: 1 }, |
| 25125 | {.Opcode: AArch64::LDPSi, .PatternStart: 532, .NumPatterns: 1 }, |
| 25126 | {.Opcode: AArch64::LDPWi, .PatternStart: 533, .NumPatterns: 1 }, |
| 25127 | {.Opcode: AArch64::LDPXi, .PatternStart: 534, .NumPatterns: 1 }, |
| 25128 | {.Opcode: AArch64::LDRAAindexed, .PatternStart: 535, .NumPatterns: 1 }, |
| 25129 | {.Opcode: AArch64::LDRABindexed, .PatternStart: 536, .NumPatterns: 1 }, |
| 25130 | {.Opcode: AArch64::LDRBBroX, .PatternStart: 537, .NumPatterns: 1 }, |
| 25131 | {.Opcode: AArch64::LDRBBui, .PatternStart: 538, .NumPatterns: 1 }, |
| 25132 | {.Opcode: AArch64::LDRBroX, .PatternStart: 539, .NumPatterns: 1 }, |
| 25133 | {.Opcode: AArch64::LDRBui, .PatternStart: 540, .NumPatterns: 1 }, |
| 25134 | {.Opcode: AArch64::LDRDroX, .PatternStart: 541, .NumPatterns: 1 }, |
| 25135 | {.Opcode: AArch64::LDRDui, .PatternStart: 542, .NumPatterns: 1 }, |
| 25136 | {.Opcode: AArch64::LDRHHroX, .PatternStart: 543, .NumPatterns: 1 }, |
| 25137 | {.Opcode: AArch64::LDRHHui, .PatternStart: 544, .NumPatterns: 1 }, |
| 25138 | {.Opcode: AArch64::LDRHroX, .PatternStart: 545, .NumPatterns: 1 }, |
| 25139 | {.Opcode: AArch64::LDRHui, .PatternStart: 546, .NumPatterns: 1 }, |
| 25140 | {.Opcode: AArch64::LDRQroX, .PatternStart: 547, .NumPatterns: 1 }, |
| 25141 | {.Opcode: AArch64::LDRQui, .PatternStart: 548, .NumPatterns: 1 }, |
| 25142 | {.Opcode: AArch64::LDRSBWroX, .PatternStart: 549, .NumPatterns: 1 }, |
| 25143 | {.Opcode: AArch64::LDRSBWui, .PatternStart: 550, .NumPatterns: 1 }, |
| 25144 | {.Opcode: AArch64::LDRSBXroX, .PatternStart: 551, .NumPatterns: 1 }, |
| 25145 | {.Opcode: AArch64::LDRSBXui, .PatternStart: 552, .NumPatterns: 1 }, |
| 25146 | {.Opcode: AArch64::LDRSHWroX, .PatternStart: 553, .NumPatterns: 1 }, |
| 25147 | {.Opcode: AArch64::LDRSHWui, .PatternStart: 554, .NumPatterns: 1 }, |
| 25148 | {.Opcode: AArch64::LDRSHXroX, .PatternStart: 555, .NumPatterns: 1 }, |
| 25149 | {.Opcode: AArch64::LDRSHXui, .PatternStart: 556, .NumPatterns: 1 }, |
| 25150 | {.Opcode: AArch64::LDRSWroX, .PatternStart: 557, .NumPatterns: 1 }, |
| 25151 | {.Opcode: AArch64::LDRSWui, .PatternStart: 558, .NumPatterns: 1 }, |
| 25152 | {.Opcode: AArch64::LDRSroX, .PatternStart: 559, .NumPatterns: 1 }, |
| 25153 | {.Opcode: AArch64::LDRSui, .PatternStart: 560, .NumPatterns: 1 }, |
| 25154 | {.Opcode: AArch64::LDRWroX, .PatternStart: 561, .NumPatterns: 1 }, |
| 25155 | {.Opcode: AArch64::LDRWui, .PatternStart: 562, .NumPatterns: 1 }, |
| 25156 | {.Opcode: AArch64::LDRXroX, .PatternStart: 563, .NumPatterns: 1 }, |
| 25157 | {.Opcode: AArch64::LDRXui, .PatternStart: 564, .NumPatterns: 1 }, |
| 25158 | {.Opcode: AArch64::LDR_PXI, .PatternStart: 565, .NumPatterns: 1 }, |
| 25159 | {.Opcode: AArch64::LDR_ZA, .PatternStart: 566, .NumPatterns: 1 }, |
| 25160 | {.Opcode: AArch64::LDR_ZXI, .PatternStart: 567, .NumPatterns: 1 }, |
| 25161 | {.Opcode: AArch64::LDSETB, .PatternStart: 568, .NumPatterns: 1 }, |
| 25162 | {.Opcode: AArch64::LDSETH, .PatternStart: 569, .NumPatterns: 1 }, |
| 25163 | {.Opcode: AArch64::LDSETLB, .PatternStart: 570, .NumPatterns: 1 }, |
| 25164 | {.Opcode: AArch64::LDSETLH, .PatternStart: 571, .NumPatterns: 1 }, |
| 25165 | {.Opcode: AArch64::LDSETLW, .PatternStart: 572, .NumPatterns: 1 }, |
| 25166 | {.Opcode: AArch64::LDSETLX, .PatternStart: 573, .NumPatterns: 1 }, |
| 25167 | {.Opcode: AArch64::LDSETW, .PatternStart: 574, .NumPatterns: 1 }, |
| 25168 | {.Opcode: AArch64::LDSETX, .PatternStart: 575, .NumPatterns: 1 }, |
| 25169 | {.Opcode: AArch64::LDSMAXB, .PatternStart: 576, .NumPatterns: 1 }, |
| 25170 | {.Opcode: AArch64::LDSMAXH, .PatternStart: 577, .NumPatterns: 1 }, |
| 25171 | {.Opcode: AArch64::LDSMAXLB, .PatternStart: 578, .NumPatterns: 1 }, |
| 25172 | {.Opcode: AArch64::LDSMAXLH, .PatternStart: 579, .NumPatterns: 1 }, |
| 25173 | {.Opcode: AArch64::LDSMAXLW, .PatternStart: 580, .NumPatterns: 1 }, |
| 25174 | {.Opcode: AArch64::LDSMAXLX, .PatternStart: 581, .NumPatterns: 1 }, |
| 25175 | {.Opcode: AArch64::LDSMAXW, .PatternStart: 582, .NumPatterns: 1 }, |
| 25176 | {.Opcode: AArch64::LDSMAXX, .PatternStart: 583, .NumPatterns: 1 }, |
| 25177 | {.Opcode: AArch64::LDSMINB, .PatternStart: 584, .NumPatterns: 1 }, |
| 25178 | {.Opcode: AArch64::LDSMINH, .PatternStart: 585, .NumPatterns: 1 }, |
| 25179 | {.Opcode: AArch64::LDSMINLB, .PatternStart: 586, .NumPatterns: 1 }, |
| 25180 | {.Opcode: AArch64::LDSMINLH, .PatternStart: 587, .NumPatterns: 1 }, |
| 25181 | {.Opcode: AArch64::LDSMINLW, .PatternStart: 588, .NumPatterns: 1 }, |
| 25182 | {.Opcode: AArch64::LDSMINLX, .PatternStart: 589, .NumPatterns: 1 }, |
| 25183 | {.Opcode: AArch64::LDSMINW, .PatternStart: 590, .NumPatterns: 1 }, |
| 25184 | {.Opcode: AArch64::LDSMINX, .PatternStart: 591, .NumPatterns: 1 }, |
| 25185 | {.Opcode: AArch64::LDTADDLW, .PatternStart: 592, .NumPatterns: 1 }, |
| 25186 | {.Opcode: AArch64::LDTADDLX, .PatternStart: 593, .NumPatterns: 1 }, |
| 25187 | {.Opcode: AArch64::LDTADDW, .PatternStart: 594, .NumPatterns: 1 }, |
| 25188 | {.Opcode: AArch64::LDTADDX, .PatternStart: 595, .NumPatterns: 1 }, |
| 25189 | {.Opcode: AArch64::LDTCLRLW, .PatternStart: 596, .NumPatterns: 1 }, |
| 25190 | {.Opcode: AArch64::LDTCLRLX, .PatternStart: 597, .NumPatterns: 1 }, |
| 25191 | {.Opcode: AArch64::LDTCLRW, .PatternStart: 598, .NumPatterns: 1 }, |
| 25192 | {.Opcode: AArch64::LDTCLRX, .PatternStart: 599, .NumPatterns: 1 }, |
| 25193 | {.Opcode: AArch64::LDTNPQi, .PatternStart: 600, .NumPatterns: 1 }, |
| 25194 | {.Opcode: AArch64::LDTNPXi, .PatternStart: 601, .NumPatterns: 1 }, |
| 25195 | {.Opcode: AArch64::LDTPQi, .PatternStart: 602, .NumPatterns: 1 }, |
| 25196 | {.Opcode: AArch64::LDTPi, .PatternStart: 603, .NumPatterns: 1 }, |
| 25197 | {.Opcode: AArch64::LDTRBi, .PatternStart: 604, .NumPatterns: 1 }, |
| 25198 | {.Opcode: AArch64::LDTRHi, .PatternStart: 605, .NumPatterns: 1 }, |
| 25199 | {.Opcode: AArch64::LDTRSBWi, .PatternStart: 606, .NumPatterns: 1 }, |
| 25200 | {.Opcode: AArch64::LDTRSBXi, .PatternStart: 607, .NumPatterns: 1 }, |
| 25201 | {.Opcode: AArch64::LDTRSHWi, .PatternStart: 608, .NumPatterns: 1 }, |
| 25202 | {.Opcode: AArch64::LDTRSHXi, .PatternStart: 609, .NumPatterns: 1 }, |
| 25203 | {.Opcode: AArch64::LDTRSWi, .PatternStart: 610, .NumPatterns: 1 }, |
| 25204 | {.Opcode: AArch64::LDTRWi, .PatternStart: 611, .NumPatterns: 1 }, |
| 25205 | {.Opcode: AArch64::LDTRXi, .PatternStart: 612, .NumPatterns: 1 }, |
| 25206 | {.Opcode: AArch64::LDTSETLW, .PatternStart: 613, .NumPatterns: 1 }, |
| 25207 | {.Opcode: AArch64::LDTSETLX, .PatternStart: 614, .NumPatterns: 1 }, |
| 25208 | {.Opcode: AArch64::LDTSETW, .PatternStart: 615, .NumPatterns: 1 }, |
| 25209 | {.Opcode: AArch64::LDTSETX, .PatternStart: 616, .NumPatterns: 1 }, |
| 25210 | {.Opcode: AArch64::LDUMAXB, .PatternStart: 617, .NumPatterns: 1 }, |
| 25211 | {.Opcode: AArch64::LDUMAXH, .PatternStart: 618, .NumPatterns: 1 }, |
| 25212 | {.Opcode: AArch64::LDUMAXLB, .PatternStart: 619, .NumPatterns: 1 }, |
| 25213 | {.Opcode: AArch64::LDUMAXLH, .PatternStart: 620, .NumPatterns: 1 }, |
| 25214 | {.Opcode: AArch64::LDUMAXLW, .PatternStart: 621, .NumPatterns: 1 }, |
| 25215 | {.Opcode: AArch64::LDUMAXLX, .PatternStart: 622, .NumPatterns: 1 }, |
| 25216 | {.Opcode: AArch64::LDUMAXW, .PatternStart: 623, .NumPatterns: 1 }, |
| 25217 | {.Opcode: AArch64::LDUMAXX, .PatternStart: 624, .NumPatterns: 1 }, |
| 25218 | {.Opcode: AArch64::LDUMINB, .PatternStart: 625, .NumPatterns: 1 }, |
| 25219 | {.Opcode: AArch64::LDUMINH, .PatternStart: 626, .NumPatterns: 1 }, |
| 25220 | {.Opcode: AArch64::LDUMINLB, .PatternStart: 627, .NumPatterns: 1 }, |
| 25221 | {.Opcode: AArch64::LDUMINLH, .PatternStart: 628, .NumPatterns: 1 }, |
| 25222 | {.Opcode: AArch64::LDUMINLW, .PatternStart: 629, .NumPatterns: 1 }, |
| 25223 | {.Opcode: AArch64::LDUMINLX, .PatternStart: 630, .NumPatterns: 1 }, |
| 25224 | {.Opcode: AArch64::LDUMINW, .PatternStart: 631, .NumPatterns: 1 }, |
| 25225 | {.Opcode: AArch64::LDUMINX, .PatternStart: 632, .NumPatterns: 1 }, |
| 25226 | {.Opcode: AArch64::LDURBBi, .PatternStart: 633, .NumPatterns: 1 }, |
| 25227 | {.Opcode: AArch64::LDURBi, .PatternStart: 634, .NumPatterns: 1 }, |
| 25228 | {.Opcode: AArch64::LDURDi, .PatternStart: 635, .NumPatterns: 1 }, |
| 25229 | {.Opcode: AArch64::LDURHHi, .PatternStart: 636, .NumPatterns: 1 }, |
| 25230 | {.Opcode: AArch64::LDURHi, .PatternStart: 637, .NumPatterns: 1 }, |
| 25231 | {.Opcode: AArch64::LDURQi, .PatternStart: 638, .NumPatterns: 1 }, |
| 25232 | {.Opcode: AArch64::LDURSBWi, .PatternStart: 639, .NumPatterns: 1 }, |
| 25233 | {.Opcode: AArch64::LDURSBXi, .PatternStart: 640, .NumPatterns: 1 }, |
| 25234 | {.Opcode: AArch64::LDURSHWi, .PatternStart: 641, .NumPatterns: 1 }, |
| 25235 | {.Opcode: AArch64::LDURSHXi, .PatternStart: 642, .NumPatterns: 1 }, |
| 25236 | {.Opcode: AArch64::LDURSWi, .PatternStart: 643, .NumPatterns: 1 }, |
| 25237 | {.Opcode: AArch64::LDURSi, .PatternStart: 644, .NumPatterns: 1 }, |
| 25238 | {.Opcode: AArch64::LDURWi, .PatternStart: 645, .NumPatterns: 1 }, |
| 25239 | {.Opcode: AArch64::LDURXi, .PatternStart: 646, .NumPatterns: 1 }, |
| 25240 | {.Opcode: AArch64::MADDWrrr, .PatternStart: 647, .NumPatterns: 1 }, |
| 25241 | {.Opcode: AArch64::MADDXrrr, .PatternStart: 648, .NumPatterns: 1 }, |
| 25242 | {.Opcode: AArch64::MOVA_2ZMXI_H_B, .PatternStart: 649, .NumPatterns: 1 }, |
| 25243 | {.Opcode: AArch64::MOVA_2ZMXI_H_D, .PatternStart: 650, .NumPatterns: 1 }, |
| 25244 | {.Opcode: AArch64::MOVA_2ZMXI_H_H, .PatternStart: 651, .NumPatterns: 1 }, |
| 25245 | {.Opcode: AArch64::MOVA_2ZMXI_H_S, .PatternStart: 652, .NumPatterns: 1 }, |
| 25246 | {.Opcode: AArch64::MOVA_2ZMXI_V_B, .PatternStart: 653, .NumPatterns: 1 }, |
| 25247 | {.Opcode: AArch64::MOVA_2ZMXI_V_D, .PatternStart: 654, .NumPatterns: 1 }, |
| 25248 | {.Opcode: AArch64::MOVA_2ZMXI_V_H, .PatternStart: 655, .NumPatterns: 1 }, |
| 25249 | {.Opcode: AArch64::MOVA_2ZMXI_V_S, .PatternStart: 656, .NumPatterns: 1 }, |
| 25250 | {.Opcode: AArch64::MOVA_4ZMXI_H_B, .PatternStart: 657, .NumPatterns: 1 }, |
| 25251 | {.Opcode: AArch64::MOVA_4ZMXI_H_D, .PatternStart: 658, .NumPatterns: 1 }, |
| 25252 | {.Opcode: AArch64::MOVA_4ZMXI_H_H, .PatternStart: 659, .NumPatterns: 1 }, |
| 25253 | {.Opcode: AArch64::MOVA_4ZMXI_H_S, .PatternStart: 660, .NumPatterns: 1 }, |
| 25254 | {.Opcode: AArch64::MOVA_4ZMXI_V_B, .PatternStart: 661, .NumPatterns: 1 }, |
| 25255 | {.Opcode: AArch64::MOVA_4ZMXI_V_D, .PatternStart: 662, .NumPatterns: 1 }, |
| 25256 | {.Opcode: AArch64::MOVA_4ZMXI_V_H, .PatternStart: 663, .NumPatterns: 1 }, |
| 25257 | {.Opcode: AArch64::MOVA_4ZMXI_V_S, .PatternStart: 664, .NumPatterns: 1 }, |
| 25258 | {.Opcode: AArch64::MOVA_MXI2Z_H_B, .PatternStart: 665, .NumPatterns: 1 }, |
| 25259 | {.Opcode: AArch64::MOVA_MXI2Z_H_D, .PatternStart: 666, .NumPatterns: 1 }, |
| 25260 | {.Opcode: AArch64::MOVA_MXI2Z_H_H, .PatternStart: 667, .NumPatterns: 1 }, |
| 25261 | {.Opcode: AArch64::MOVA_MXI2Z_H_S, .PatternStart: 668, .NumPatterns: 1 }, |
| 25262 | {.Opcode: AArch64::MOVA_MXI2Z_V_B, .PatternStart: 669, .NumPatterns: 1 }, |
| 25263 | {.Opcode: AArch64::MOVA_MXI2Z_V_D, .PatternStart: 670, .NumPatterns: 1 }, |
| 25264 | {.Opcode: AArch64::MOVA_MXI2Z_V_H, .PatternStart: 671, .NumPatterns: 1 }, |
| 25265 | {.Opcode: AArch64::MOVA_MXI2Z_V_S, .PatternStart: 672, .NumPatterns: 1 }, |
| 25266 | {.Opcode: AArch64::MOVA_MXI4Z_H_B, .PatternStart: 673, .NumPatterns: 1 }, |
| 25267 | {.Opcode: AArch64::MOVA_MXI4Z_H_D, .PatternStart: 674, .NumPatterns: 1 }, |
| 25268 | {.Opcode: AArch64::MOVA_MXI4Z_H_H, .PatternStart: 675, .NumPatterns: 1 }, |
| 25269 | {.Opcode: AArch64::MOVA_MXI4Z_H_S, .PatternStart: 676, .NumPatterns: 1 }, |
| 25270 | {.Opcode: AArch64::MOVA_MXI4Z_V_B, .PatternStart: 677, .NumPatterns: 1 }, |
| 25271 | {.Opcode: AArch64::MOVA_MXI4Z_V_D, .PatternStart: 678, .NumPatterns: 1 }, |
| 25272 | {.Opcode: AArch64::MOVA_MXI4Z_V_H, .PatternStart: 679, .NumPatterns: 1 }, |
| 25273 | {.Opcode: AArch64::MOVA_MXI4Z_V_S, .PatternStart: 680, .NumPatterns: 1 }, |
| 25274 | {.Opcode: AArch64::MOVA_VG2_2ZMXI, .PatternStart: 681, .NumPatterns: 1 }, |
| 25275 | {.Opcode: AArch64::MOVA_VG2_MXI2Z, .PatternStart: 682, .NumPatterns: 1 }, |
| 25276 | {.Opcode: AArch64::MOVA_VG4_4ZMXI, .PatternStart: 683, .NumPatterns: 1 }, |
| 25277 | {.Opcode: AArch64::MOVA_VG4_MXI4Z, .PatternStart: 684, .NumPatterns: 1 }, |
| 25278 | {.Opcode: AArch64::MOVT_TIZ, .PatternStart: 685, .NumPatterns: 1 }, |
| 25279 | {.Opcode: AArch64::MSRpstatesvcrImm1, .PatternStart: 686, .NumPatterns: 6 }, |
| 25280 | {.Opcode: AArch64::MSUBWrrr, .PatternStart: 692, .NumPatterns: 1 }, |
| 25281 | {.Opcode: AArch64::MSUBXrrr, .PatternStart: 693, .NumPatterns: 1 }, |
| 25282 | {.Opcode: AArch64::NOP, .PatternStart: 694, .NumPatterns: 1 }, |
| 25283 | {.Opcode: AArch64::NOTv16i8, .PatternStart: 695, .NumPatterns: 1 }, |
| 25284 | {.Opcode: AArch64::NOTv8i8, .PatternStart: 696, .NumPatterns: 1 }, |
| 25285 | {.Opcode: AArch64::ORNWrs, .PatternStart: 697, .NumPatterns: 3 }, |
| 25286 | {.Opcode: AArch64::ORNXrs, .PatternStart: 700, .NumPatterns: 3 }, |
| 25287 | {.Opcode: AArch64::ORRS_PPzPP, .PatternStart: 703, .NumPatterns: 1 }, |
| 25288 | {.Opcode: AArch64::ORRWrs, .PatternStart: 704, .NumPatterns: 2 }, |
| 25289 | {.Opcode: AArch64::ORRXrs, .PatternStart: 706, .NumPatterns: 2 }, |
| 25290 | {.Opcode: AArch64::ORR_PPzPP, .PatternStart: 708, .NumPatterns: 1 }, |
| 25291 | {.Opcode: AArch64::ORR_ZI, .PatternStart: 709, .NumPatterns: 3 }, |
| 25292 | {.Opcode: AArch64::ORR_ZZZ, .PatternStart: 712, .NumPatterns: 1 }, |
| 25293 | {.Opcode: AArch64::ORRv16i8, .PatternStart: 713, .NumPatterns: 1 }, |
| 25294 | {.Opcode: AArch64::ORRv8i8, .PatternStart: 714, .NumPatterns: 1 }, |
| 25295 | {.Opcode: AArch64::PACIA1716, .PatternStart: 715, .NumPatterns: 1 }, |
| 25296 | {.Opcode: AArch64::PACIASP, .PatternStart: 716, .NumPatterns: 1 }, |
| 25297 | {.Opcode: AArch64::PACIAZ, .PatternStart: 717, .NumPatterns: 1 }, |
| 25298 | {.Opcode: AArch64::PACIB1716, .PatternStart: 718, .NumPatterns: 1 }, |
| 25299 | {.Opcode: AArch64::PACIBSP, .PatternStart: 719, .NumPatterns: 1 }, |
| 25300 | {.Opcode: AArch64::PACIBZ, .PatternStart: 720, .NumPatterns: 1 }, |
| 25301 | {.Opcode: AArch64::PACM, .PatternStart: 721, .NumPatterns: 1 }, |
| 25302 | {.Opcode: AArch64::PMOV_PZI_B, .PatternStart: 722, .NumPatterns: 1 }, |
| 25303 | {.Opcode: AArch64::PMOV_ZIP_B, .PatternStart: 723, .NumPatterns: 1 }, |
| 25304 | {.Opcode: AArch64::PRFB_D_PZI, .PatternStart: 724, .NumPatterns: 1 }, |
| 25305 | {.Opcode: AArch64::PRFB_PRI, .PatternStart: 725, .NumPatterns: 1 }, |
| 25306 | {.Opcode: AArch64::PRFB_S_PZI, .PatternStart: 726, .NumPatterns: 1 }, |
| 25307 | {.Opcode: AArch64::PRFD_D_PZI, .PatternStart: 727, .NumPatterns: 1 }, |
| 25308 | {.Opcode: AArch64::PRFD_PRI, .PatternStart: 728, .NumPatterns: 1 }, |
| 25309 | {.Opcode: AArch64::PRFD_S_PZI, .PatternStart: 729, .NumPatterns: 1 }, |
| 25310 | {.Opcode: AArch64::PRFH_D_PZI, .PatternStart: 730, .NumPatterns: 1 }, |
| 25311 | {.Opcode: AArch64::PRFH_PRI, .PatternStart: 731, .NumPatterns: 1 }, |
| 25312 | {.Opcode: AArch64::PRFH_S_PZI, .PatternStart: 732, .NumPatterns: 1 }, |
| 25313 | {.Opcode: AArch64::PRFMroX, .PatternStart: 733, .NumPatterns: 1 }, |
| 25314 | {.Opcode: AArch64::PRFMui, .PatternStart: 734, .NumPatterns: 1 }, |
| 25315 | {.Opcode: AArch64::PRFUMi, .PatternStart: 735, .NumPatterns: 1 }, |
| 25316 | {.Opcode: AArch64::PRFW_D_PZI, .PatternStart: 736, .NumPatterns: 1 }, |
| 25317 | {.Opcode: AArch64::PRFW_PRI, .PatternStart: 737, .NumPatterns: 1 }, |
| 25318 | {.Opcode: AArch64::PRFW_S_PZI, .PatternStart: 738, .NumPatterns: 1 }, |
| 25319 | {.Opcode: AArch64::PTRUES_B, .PatternStart: 739, .NumPatterns: 1 }, |
| 25320 | {.Opcode: AArch64::PTRUES_D, .PatternStart: 740, .NumPatterns: 1 }, |
| 25321 | {.Opcode: AArch64::PTRUES_H, .PatternStart: 741, .NumPatterns: 1 }, |
| 25322 | {.Opcode: AArch64::PTRUES_S, .PatternStart: 742, .NumPatterns: 1 }, |
| 25323 | {.Opcode: AArch64::PTRUE_B, .PatternStart: 743, .NumPatterns: 1 }, |
| 25324 | {.Opcode: AArch64::PTRUE_D, .PatternStart: 744, .NumPatterns: 1 }, |
| 25325 | {.Opcode: AArch64::PTRUE_H, .PatternStart: 745, .NumPatterns: 1 }, |
| 25326 | {.Opcode: AArch64::PTRUE_S, .PatternStart: 746, .NumPatterns: 1 }, |
| 25327 | {.Opcode: AArch64::RET, .PatternStart: 747, .NumPatterns: 1 }, |
| 25328 | {.Opcode: AArch64::SBCSWr, .PatternStart: 748, .NumPatterns: 1 }, |
| 25329 | {.Opcode: AArch64::SBCSXr, .PatternStart: 749, .NumPatterns: 1 }, |
| 25330 | {.Opcode: AArch64::SBCWr, .PatternStart: 750, .NumPatterns: 1 }, |
| 25331 | {.Opcode: AArch64::SBCXr, .PatternStart: 751, .NumPatterns: 1 }, |
| 25332 | {.Opcode: AArch64::SBFMWri, .PatternStart: 752, .NumPatterns: 3 }, |
| 25333 | {.Opcode: AArch64::SBFMXri, .PatternStart: 755, .NumPatterns: 4 }, |
| 25334 | {.Opcode: AArch64::SEL_PPPP, .PatternStart: 759, .NumPatterns: 1 }, |
| 25335 | {.Opcode: AArch64::SEL_ZPZZ_B, .PatternStart: 760, .NumPatterns: 1 }, |
| 25336 | {.Opcode: AArch64::SEL_ZPZZ_D, .PatternStart: 761, .NumPatterns: 1 }, |
| 25337 | {.Opcode: AArch64::SEL_ZPZZ_H, .PatternStart: 762, .NumPatterns: 1 }, |
| 25338 | {.Opcode: AArch64::SEL_ZPZZ_S, .PatternStart: 763, .NumPatterns: 1 }, |
| 25339 | {.Opcode: AArch64::SHUH, .PatternStart: 764, .NumPatterns: 1 }, |
| 25340 | {.Opcode: AArch64::SMADDLrrr, .PatternStart: 765, .NumPatterns: 1 }, |
| 25341 | {.Opcode: AArch64::SMSUBLrrr, .PatternStart: 766, .NumPatterns: 1 }, |
| 25342 | {.Opcode: AArch64::SQDECB_XPiI, .PatternStart: 767, .NumPatterns: 2 }, |
| 25343 | {.Opcode: AArch64::SQDECB_XPiWdI, .PatternStart: 769, .NumPatterns: 2 }, |
| 25344 | {.Opcode: AArch64::SQDECD_XPiI, .PatternStart: 771, .NumPatterns: 2 }, |
| 25345 | {.Opcode: AArch64::SQDECD_XPiWdI, .PatternStart: 773, .NumPatterns: 2 }, |
| 25346 | {.Opcode: AArch64::SQDECD_ZPiI, .PatternStart: 775, .NumPatterns: 2 }, |
| 25347 | {.Opcode: AArch64::SQDECH_XPiI, .PatternStart: 777, .NumPatterns: 2 }, |
| 25348 | {.Opcode: AArch64::SQDECH_XPiWdI, .PatternStart: 779, .NumPatterns: 2 }, |
| 25349 | {.Opcode: AArch64::SQDECH_ZPiI, .PatternStart: 781, .NumPatterns: 2 }, |
| 25350 | {.Opcode: AArch64::SQDECW_XPiI, .PatternStart: 783, .NumPatterns: 2 }, |
| 25351 | {.Opcode: AArch64::SQDECW_XPiWdI, .PatternStart: 785, .NumPatterns: 2 }, |
| 25352 | {.Opcode: AArch64::SQDECW_ZPiI, .PatternStart: 787, .NumPatterns: 2 }, |
| 25353 | {.Opcode: AArch64::SQINCB_XPiI, .PatternStart: 789, .NumPatterns: 2 }, |
| 25354 | {.Opcode: AArch64::SQINCB_XPiWdI, .PatternStart: 791, .NumPatterns: 2 }, |
| 25355 | {.Opcode: AArch64::SQINCD_XPiI, .PatternStart: 793, .NumPatterns: 2 }, |
| 25356 | {.Opcode: AArch64::SQINCD_XPiWdI, .PatternStart: 795, .NumPatterns: 2 }, |
| 25357 | {.Opcode: AArch64::SQINCD_ZPiI, .PatternStart: 797, .NumPatterns: 2 }, |
| 25358 | {.Opcode: AArch64::SQINCH_XPiI, .PatternStart: 799, .NumPatterns: 2 }, |
| 25359 | {.Opcode: AArch64::SQINCH_XPiWdI, .PatternStart: 801, .NumPatterns: 2 }, |
| 25360 | {.Opcode: AArch64::SQINCH_ZPiI, .PatternStart: 803, .NumPatterns: 2 }, |
| 25361 | {.Opcode: AArch64::SQINCW_XPiI, .PatternStart: 805, .NumPatterns: 2 }, |
| 25362 | {.Opcode: AArch64::SQINCW_XPiWdI, .PatternStart: 807, .NumPatterns: 2 }, |
| 25363 | {.Opcode: AArch64::SQINCW_ZPiI, .PatternStart: 809, .NumPatterns: 2 }, |
| 25364 | {.Opcode: AArch64::SST1B_D_IMM, .PatternStart: 811, .NumPatterns: 1 }, |
| 25365 | {.Opcode: AArch64::SST1B_S_IMM, .PatternStart: 812, .NumPatterns: 1 }, |
| 25366 | {.Opcode: AArch64::SST1D_IMM, .PatternStart: 813, .NumPatterns: 1 }, |
| 25367 | {.Opcode: AArch64::SST1H_D_IMM, .PatternStart: 814, .NumPatterns: 1 }, |
| 25368 | {.Opcode: AArch64::SST1H_S_IMM, .PatternStart: 815, .NumPatterns: 1 }, |
| 25369 | {.Opcode: AArch64::SST1Q, .PatternStart: 816, .NumPatterns: 1 }, |
| 25370 | {.Opcode: AArch64::SST1W_D_IMM, .PatternStart: 817, .NumPatterns: 1 }, |
| 25371 | {.Opcode: AArch64::SST1W_IMM, .PatternStart: 818, .NumPatterns: 1 }, |
| 25372 | {.Opcode: AArch64::ST1B_2Z_IMM, .PatternStart: 819, .NumPatterns: 1 }, |
| 25373 | {.Opcode: AArch64::ST1B_2Z_STRIDED_IMM, .PatternStart: 820, .NumPatterns: 1 }, |
| 25374 | {.Opcode: AArch64::ST1B_4Z_IMM, .PatternStart: 821, .NumPatterns: 1 }, |
| 25375 | {.Opcode: AArch64::ST1B_4Z_STRIDED_IMM, .PatternStart: 822, .NumPatterns: 1 }, |
| 25376 | {.Opcode: AArch64::ST1B_D_IMM, .PatternStart: 823, .NumPatterns: 1 }, |
| 25377 | {.Opcode: AArch64::ST1B_H_IMM, .PatternStart: 824, .NumPatterns: 1 }, |
| 25378 | {.Opcode: AArch64::ST1B_IMM, .PatternStart: 825, .NumPatterns: 1 }, |
| 25379 | {.Opcode: AArch64::ST1B_S_IMM, .PatternStart: 826, .NumPatterns: 1 }, |
| 25380 | {.Opcode: AArch64::ST1D_2Z_IMM, .PatternStart: 827, .NumPatterns: 1 }, |
| 25381 | {.Opcode: AArch64::ST1D_2Z_STRIDED_IMM, .PatternStart: 828, .NumPatterns: 1 }, |
| 25382 | {.Opcode: AArch64::ST1D_4Z_IMM, .PatternStart: 829, .NumPatterns: 1 }, |
| 25383 | {.Opcode: AArch64::ST1D_4Z_STRIDED_IMM, .PatternStart: 830, .NumPatterns: 1 }, |
| 25384 | {.Opcode: AArch64::ST1D_IMM, .PatternStart: 831, .NumPatterns: 1 }, |
| 25385 | {.Opcode: AArch64::ST1D_Q_IMM, .PatternStart: 832, .NumPatterns: 1 }, |
| 25386 | {.Opcode: AArch64::ST1Fourv16b_POST, .PatternStart: 833, .NumPatterns: 1 }, |
| 25387 | {.Opcode: AArch64::ST1Fourv1d_POST, .PatternStart: 834, .NumPatterns: 1 }, |
| 25388 | {.Opcode: AArch64::ST1Fourv2d_POST, .PatternStart: 835, .NumPatterns: 1 }, |
| 25389 | {.Opcode: AArch64::ST1Fourv2s_POST, .PatternStart: 836, .NumPatterns: 1 }, |
| 25390 | {.Opcode: AArch64::ST1Fourv4h_POST, .PatternStart: 837, .NumPatterns: 1 }, |
| 25391 | {.Opcode: AArch64::ST1Fourv4s_POST, .PatternStart: 838, .NumPatterns: 1 }, |
| 25392 | {.Opcode: AArch64::ST1Fourv8b_POST, .PatternStart: 839, .NumPatterns: 1 }, |
| 25393 | {.Opcode: AArch64::ST1Fourv8h_POST, .PatternStart: 840, .NumPatterns: 1 }, |
| 25394 | {.Opcode: AArch64::ST1H_2Z_IMM, .PatternStart: 841, .NumPatterns: 1 }, |
| 25395 | {.Opcode: AArch64::ST1H_2Z_STRIDED_IMM, .PatternStart: 842, .NumPatterns: 1 }, |
| 25396 | {.Opcode: AArch64::ST1H_4Z_IMM, .PatternStart: 843, .NumPatterns: 1 }, |
| 25397 | {.Opcode: AArch64::ST1H_4Z_STRIDED_IMM, .PatternStart: 844, .NumPatterns: 1 }, |
| 25398 | {.Opcode: AArch64::ST1H_D_IMM, .PatternStart: 845, .NumPatterns: 1 }, |
| 25399 | {.Opcode: AArch64::ST1H_IMM, .PatternStart: 846, .NumPatterns: 1 }, |
| 25400 | {.Opcode: AArch64::ST1H_S_IMM, .PatternStart: 847, .NumPatterns: 1 }, |
| 25401 | {.Opcode: AArch64::ST1Onev16b_POST, .PatternStart: 848, .NumPatterns: 1 }, |
| 25402 | {.Opcode: AArch64::ST1Onev1d_POST, .PatternStart: 849, .NumPatterns: 1 }, |
| 25403 | {.Opcode: AArch64::ST1Onev2d_POST, .PatternStart: 850, .NumPatterns: 1 }, |
| 25404 | {.Opcode: AArch64::ST1Onev2s_POST, .PatternStart: 851, .NumPatterns: 1 }, |
| 25405 | {.Opcode: AArch64::ST1Onev4h_POST, .PatternStart: 852, .NumPatterns: 1 }, |
| 25406 | {.Opcode: AArch64::ST1Onev4s_POST, .PatternStart: 853, .NumPatterns: 1 }, |
| 25407 | {.Opcode: AArch64::ST1Onev8b_POST, .PatternStart: 854, .NumPatterns: 1 }, |
| 25408 | {.Opcode: AArch64::ST1Onev8h_POST, .PatternStart: 855, .NumPatterns: 1 }, |
| 25409 | {.Opcode: AArch64::ST1Threev16b_POST, .PatternStart: 856, .NumPatterns: 1 }, |
| 25410 | {.Opcode: AArch64::ST1Threev1d_POST, .PatternStart: 857, .NumPatterns: 1 }, |
| 25411 | {.Opcode: AArch64::ST1Threev2d_POST, .PatternStart: 858, .NumPatterns: 1 }, |
| 25412 | {.Opcode: AArch64::ST1Threev2s_POST, .PatternStart: 859, .NumPatterns: 1 }, |
| 25413 | {.Opcode: AArch64::ST1Threev4h_POST, .PatternStart: 860, .NumPatterns: 1 }, |
| 25414 | {.Opcode: AArch64::ST1Threev4s_POST, .PatternStart: 861, .NumPatterns: 1 }, |
| 25415 | {.Opcode: AArch64::ST1Threev8b_POST, .PatternStart: 862, .NumPatterns: 1 }, |
| 25416 | {.Opcode: AArch64::ST1Threev8h_POST, .PatternStart: 863, .NumPatterns: 1 }, |
| 25417 | {.Opcode: AArch64::ST1Twov16b_POST, .PatternStart: 864, .NumPatterns: 1 }, |
| 25418 | {.Opcode: AArch64::ST1Twov1d_POST, .PatternStart: 865, .NumPatterns: 1 }, |
| 25419 | {.Opcode: AArch64::ST1Twov2d_POST, .PatternStart: 866, .NumPatterns: 1 }, |
| 25420 | {.Opcode: AArch64::ST1Twov2s_POST, .PatternStart: 867, .NumPatterns: 1 }, |
| 25421 | {.Opcode: AArch64::ST1Twov4h_POST, .PatternStart: 868, .NumPatterns: 1 }, |
| 25422 | {.Opcode: AArch64::ST1Twov4s_POST, .PatternStart: 869, .NumPatterns: 1 }, |
| 25423 | {.Opcode: AArch64::ST1Twov8b_POST, .PatternStart: 870, .NumPatterns: 1 }, |
| 25424 | {.Opcode: AArch64::ST1Twov8h_POST, .PatternStart: 871, .NumPatterns: 1 }, |
| 25425 | {.Opcode: AArch64::ST1W_2Z_IMM, .PatternStart: 872, .NumPatterns: 1 }, |
| 25426 | {.Opcode: AArch64::ST1W_2Z_STRIDED_IMM, .PatternStart: 873, .NumPatterns: 1 }, |
| 25427 | {.Opcode: AArch64::ST1W_4Z_IMM, .PatternStart: 874, .NumPatterns: 1 }, |
| 25428 | {.Opcode: AArch64::ST1W_4Z_STRIDED_IMM, .PatternStart: 875, .NumPatterns: 1 }, |
| 25429 | {.Opcode: AArch64::ST1W_D_IMM, .PatternStart: 876, .NumPatterns: 1 }, |
| 25430 | {.Opcode: AArch64::ST1W_IMM, .PatternStart: 877, .NumPatterns: 1 }, |
| 25431 | {.Opcode: AArch64::ST1W_Q_IMM, .PatternStart: 878, .NumPatterns: 1 }, |
| 25432 | {.Opcode: AArch64::ST1_MXIPXX_H_B, .PatternStart: 879, .NumPatterns: 1 }, |
| 25433 | {.Opcode: AArch64::ST1_MXIPXX_H_D, .PatternStart: 880, .NumPatterns: 1 }, |
| 25434 | {.Opcode: AArch64::ST1_MXIPXX_H_H, .PatternStart: 881, .NumPatterns: 1 }, |
| 25435 | {.Opcode: AArch64::ST1_MXIPXX_H_Q, .PatternStart: 882, .NumPatterns: 1 }, |
| 25436 | {.Opcode: AArch64::ST1_MXIPXX_H_S, .PatternStart: 883, .NumPatterns: 1 }, |
| 25437 | {.Opcode: AArch64::ST1_MXIPXX_V_B, .PatternStart: 884, .NumPatterns: 1 }, |
| 25438 | {.Opcode: AArch64::ST1_MXIPXX_V_D, .PatternStart: 885, .NumPatterns: 1 }, |
| 25439 | {.Opcode: AArch64::ST1_MXIPXX_V_H, .PatternStart: 886, .NumPatterns: 1 }, |
| 25440 | {.Opcode: AArch64::ST1_MXIPXX_V_Q, .PatternStart: 887, .NumPatterns: 1 }, |
| 25441 | {.Opcode: AArch64::ST1_MXIPXX_V_S, .PatternStart: 888, .NumPatterns: 1 }, |
| 25442 | {.Opcode: AArch64::ST1i16_POST, .PatternStart: 889, .NumPatterns: 1 }, |
| 25443 | {.Opcode: AArch64::ST1i32_POST, .PatternStart: 890, .NumPatterns: 1 }, |
| 25444 | {.Opcode: AArch64::ST1i64_POST, .PatternStart: 891, .NumPatterns: 1 }, |
| 25445 | {.Opcode: AArch64::ST1i8_POST, .PatternStart: 892, .NumPatterns: 1 }, |
| 25446 | {.Opcode: AArch64::ST2B_IMM, .PatternStart: 893, .NumPatterns: 1 }, |
| 25447 | {.Opcode: AArch64::ST2D_IMM, .PatternStart: 894, .NumPatterns: 1 }, |
| 25448 | {.Opcode: AArch64::ST2Gi, .PatternStart: 895, .NumPatterns: 1 }, |
| 25449 | {.Opcode: AArch64::ST2H_IMM, .PatternStart: 896, .NumPatterns: 1 }, |
| 25450 | {.Opcode: AArch64::ST2Q_IMM, .PatternStart: 897, .NumPatterns: 1 }, |
| 25451 | {.Opcode: AArch64::ST2Twov16b_POST, .PatternStart: 898, .NumPatterns: 1 }, |
| 25452 | {.Opcode: AArch64::ST2Twov2d_POST, .PatternStart: 899, .NumPatterns: 1 }, |
| 25453 | {.Opcode: AArch64::ST2Twov2s_POST, .PatternStart: 900, .NumPatterns: 1 }, |
| 25454 | {.Opcode: AArch64::ST2Twov4h_POST, .PatternStart: 901, .NumPatterns: 1 }, |
| 25455 | {.Opcode: AArch64::ST2Twov4s_POST, .PatternStart: 902, .NumPatterns: 1 }, |
| 25456 | {.Opcode: AArch64::ST2Twov8b_POST, .PatternStart: 903, .NumPatterns: 1 }, |
| 25457 | {.Opcode: AArch64::ST2Twov8h_POST, .PatternStart: 904, .NumPatterns: 1 }, |
| 25458 | {.Opcode: AArch64::ST2W_IMM, .PatternStart: 905, .NumPatterns: 1 }, |
| 25459 | {.Opcode: AArch64::ST2i16_POST, .PatternStart: 906, .NumPatterns: 1 }, |
| 25460 | {.Opcode: AArch64::ST2i32_POST, .PatternStart: 907, .NumPatterns: 1 }, |
| 25461 | {.Opcode: AArch64::ST2i64_POST, .PatternStart: 908, .NumPatterns: 1 }, |
| 25462 | {.Opcode: AArch64::ST2i8_POST, .PatternStart: 909, .NumPatterns: 1 }, |
| 25463 | {.Opcode: AArch64::ST3B_IMM, .PatternStart: 910, .NumPatterns: 1 }, |
| 25464 | {.Opcode: AArch64::ST3D_IMM, .PatternStart: 911, .NumPatterns: 1 }, |
| 25465 | {.Opcode: AArch64::ST3H_IMM, .PatternStart: 912, .NumPatterns: 1 }, |
| 25466 | {.Opcode: AArch64::ST3Q_IMM, .PatternStart: 913, .NumPatterns: 1 }, |
| 25467 | {.Opcode: AArch64::ST3Threev16b_POST, .PatternStart: 914, .NumPatterns: 1 }, |
| 25468 | {.Opcode: AArch64::ST3Threev2d_POST, .PatternStart: 915, .NumPatterns: 1 }, |
| 25469 | {.Opcode: AArch64::ST3Threev2s_POST, .PatternStart: 916, .NumPatterns: 1 }, |
| 25470 | {.Opcode: AArch64::ST3Threev4h_POST, .PatternStart: 917, .NumPatterns: 1 }, |
| 25471 | {.Opcode: AArch64::ST3Threev4s_POST, .PatternStart: 918, .NumPatterns: 1 }, |
| 25472 | {.Opcode: AArch64::ST3Threev8b_POST, .PatternStart: 919, .NumPatterns: 1 }, |
| 25473 | {.Opcode: AArch64::ST3Threev8h_POST, .PatternStart: 920, .NumPatterns: 1 }, |
| 25474 | {.Opcode: AArch64::ST3W_IMM, .PatternStart: 921, .NumPatterns: 1 }, |
| 25475 | {.Opcode: AArch64::ST3i16_POST, .PatternStart: 922, .NumPatterns: 1 }, |
| 25476 | {.Opcode: AArch64::ST3i32_POST, .PatternStart: 923, .NumPatterns: 1 }, |
| 25477 | {.Opcode: AArch64::ST3i64_POST, .PatternStart: 924, .NumPatterns: 1 }, |
| 25478 | {.Opcode: AArch64::ST3i8_POST, .PatternStart: 925, .NumPatterns: 1 }, |
| 25479 | {.Opcode: AArch64::ST4B_IMM, .PatternStart: 926, .NumPatterns: 1 }, |
| 25480 | {.Opcode: AArch64::ST4D_IMM, .PatternStart: 927, .NumPatterns: 1 }, |
| 25481 | {.Opcode: AArch64::ST4Fourv16b_POST, .PatternStart: 928, .NumPatterns: 1 }, |
| 25482 | {.Opcode: AArch64::ST4Fourv2d_POST, .PatternStart: 929, .NumPatterns: 1 }, |
| 25483 | {.Opcode: AArch64::ST4Fourv2s_POST, .PatternStart: 930, .NumPatterns: 1 }, |
| 25484 | {.Opcode: AArch64::ST4Fourv4h_POST, .PatternStart: 931, .NumPatterns: 1 }, |
| 25485 | {.Opcode: AArch64::ST4Fourv4s_POST, .PatternStart: 932, .NumPatterns: 1 }, |
| 25486 | {.Opcode: AArch64::ST4Fourv8b_POST, .PatternStart: 933, .NumPatterns: 1 }, |
| 25487 | {.Opcode: AArch64::ST4Fourv8h_POST, .PatternStart: 934, .NumPatterns: 1 }, |
| 25488 | {.Opcode: AArch64::ST4H_IMM, .PatternStart: 935, .NumPatterns: 1 }, |
| 25489 | {.Opcode: AArch64::ST4Q_IMM, .PatternStart: 936, .NumPatterns: 1 }, |
| 25490 | {.Opcode: AArch64::ST4W_IMM, .PatternStart: 937, .NumPatterns: 1 }, |
| 25491 | {.Opcode: AArch64::ST4i16_POST, .PatternStart: 938, .NumPatterns: 1 }, |
| 25492 | {.Opcode: AArch64::ST4i32_POST, .PatternStart: 939, .NumPatterns: 1 }, |
| 25493 | {.Opcode: AArch64::ST4i64_POST, .PatternStart: 940, .NumPatterns: 1 }, |
| 25494 | {.Opcode: AArch64::ST4i8_POST, .PatternStart: 941, .NumPatterns: 1 }, |
| 25495 | {.Opcode: AArch64::STGPi, .PatternStart: 942, .NumPatterns: 1 }, |
| 25496 | {.Opcode: AArch64::STGi, .PatternStart: 943, .NumPatterns: 1 }, |
| 25497 | {.Opcode: AArch64::STLPi, .PatternStart: 944, .NumPatterns: 1 }, |
| 25498 | {.Opcode: AArch64::STLURBi, .PatternStart: 945, .NumPatterns: 1 }, |
| 25499 | {.Opcode: AArch64::STLURHi, .PatternStart: 946, .NumPatterns: 1 }, |
| 25500 | {.Opcode: AArch64::STLURWi, .PatternStart: 947, .NumPatterns: 1 }, |
| 25501 | {.Opcode: AArch64::STLURXi, .PatternStart: 948, .NumPatterns: 1 }, |
| 25502 | {.Opcode: AArch64::STLURbi, .PatternStart: 949, .NumPatterns: 1 }, |
| 25503 | {.Opcode: AArch64::STLURdi, .PatternStart: 950, .NumPatterns: 1 }, |
| 25504 | {.Opcode: AArch64::STLURhi, .PatternStart: 951, .NumPatterns: 1 }, |
| 25505 | {.Opcode: AArch64::STLURqi, .PatternStart: 952, .NumPatterns: 1 }, |
| 25506 | {.Opcode: AArch64::STLURsi, .PatternStart: 953, .NumPatterns: 1 }, |
| 25507 | {.Opcode: AArch64::STNPDi, .PatternStart: 954, .NumPatterns: 1 }, |
| 25508 | {.Opcode: AArch64::STNPQi, .PatternStart: 955, .NumPatterns: 1 }, |
| 25509 | {.Opcode: AArch64::STNPSi, .PatternStart: 956, .NumPatterns: 1 }, |
| 25510 | {.Opcode: AArch64::STNPWi, .PatternStart: 957, .NumPatterns: 1 }, |
| 25511 | {.Opcode: AArch64::STNPXi, .PatternStart: 958, .NumPatterns: 1 }, |
| 25512 | {.Opcode: AArch64::STNT1B_2Z_IMM, .PatternStart: 959, .NumPatterns: 1 }, |
| 25513 | {.Opcode: AArch64::STNT1B_2Z_STRIDED_IMM, .PatternStart: 960, .NumPatterns: 1 }, |
| 25514 | {.Opcode: AArch64::STNT1B_4Z_IMM, .PatternStart: 961, .NumPatterns: 1 }, |
| 25515 | {.Opcode: AArch64::STNT1B_4Z_STRIDED_IMM, .PatternStart: 962, .NumPatterns: 1 }, |
| 25516 | {.Opcode: AArch64::STNT1B_ZRI, .PatternStart: 963, .NumPatterns: 1 }, |
| 25517 | {.Opcode: AArch64::STNT1B_ZZR_D, .PatternStart: 964, .NumPatterns: 1 }, |
| 25518 | {.Opcode: AArch64::STNT1B_ZZR_S, .PatternStart: 965, .NumPatterns: 1 }, |
| 25519 | {.Opcode: AArch64::STNT1D_2Z_IMM, .PatternStart: 966, .NumPatterns: 1 }, |
| 25520 | {.Opcode: AArch64::STNT1D_2Z_STRIDED_IMM, .PatternStart: 967, .NumPatterns: 1 }, |
| 25521 | {.Opcode: AArch64::STNT1D_4Z_IMM, .PatternStart: 968, .NumPatterns: 1 }, |
| 25522 | {.Opcode: AArch64::STNT1D_4Z_STRIDED_IMM, .PatternStart: 969, .NumPatterns: 1 }, |
| 25523 | {.Opcode: AArch64::STNT1D_ZRI, .PatternStart: 970, .NumPatterns: 1 }, |
| 25524 | {.Opcode: AArch64::STNT1D_ZZR_D, .PatternStart: 971, .NumPatterns: 1 }, |
| 25525 | {.Opcode: AArch64::STNT1H_2Z_IMM, .PatternStart: 972, .NumPatterns: 1 }, |
| 25526 | {.Opcode: AArch64::STNT1H_2Z_STRIDED_IMM, .PatternStart: 973, .NumPatterns: 1 }, |
| 25527 | {.Opcode: AArch64::STNT1H_4Z_IMM, .PatternStart: 974, .NumPatterns: 1 }, |
| 25528 | {.Opcode: AArch64::STNT1H_4Z_STRIDED_IMM, .PatternStart: 975, .NumPatterns: 1 }, |
| 25529 | {.Opcode: AArch64::STNT1H_ZRI, .PatternStart: 976, .NumPatterns: 1 }, |
| 25530 | {.Opcode: AArch64::STNT1H_ZZR_D, .PatternStart: 977, .NumPatterns: 1 }, |
| 25531 | {.Opcode: AArch64::STNT1H_ZZR_S, .PatternStart: 978, .NumPatterns: 1 }, |
| 25532 | {.Opcode: AArch64::STNT1W_2Z_IMM, .PatternStart: 979, .NumPatterns: 1 }, |
| 25533 | {.Opcode: AArch64::STNT1W_2Z_STRIDED_IMM, .PatternStart: 980, .NumPatterns: 1 }, |
| 25534 | {.Opcode: AArch64::STNT1W_4Z_IMM, .PatternStart: 981, .NumPatterns: 1 }, |
| 25535 | {.Opcode: AArch64::STNT1W_4Z_STRIDED_IMM, .PatternStart: 982, .NumPatterns: 1 }, |
| 25536 | {.Opcode: AArch64::STNT1W_ZRI, .PatternStart: 983, .NumPatterns: 1 }, |
| 25537 | {.Opcode: AArch64::STNT1W_ZZR_D, .PatternStart: 984, .NumPatterns: 1 }, |
| 25538 | {.Opcode: AArch64::STNT1W_ZZR_S, .PatternStart: 985, .NumPatterns: 1 }, |
| 25539 | {.Opcode: AArch64::STPDi, .PatternStart: 986, .NumPatterns: 1 }, |
| 25540 | {.Opcode: AArch64::STPQi, .PatternStart: 987, .NumPatterns: 1 }, |
| 25541 | {.Opcode: AArch64::STPSi, .PatternStart: 988, .NumPatterns: 1 }, |
| 25542 | {.Opcode: AArch64::STPWi, .PatternStart: 989, .NumPatterns: 1 }, |
| 25543 | {.Opcode: AArch64::STPXi, .PatternStart: 990, .NumPatterns: 1 }, |
| 25544 | {.Opcode: AArch64::STRBBroX, .PatternStart: 991, .NumPatterns: 1 }, |
| 25545 | {.Opcode: AArch64::STRBBui, .PatternStart: 992, .NumPatterns: 1 }, |
| 25546 | {.Opcode: AArch64::STRBroX, .PatternStart: 993, .NumPatterns: 1 }, |
| 25547 | {.Opcode: AArch64::STRBui, .PatternStart: 994, .NumPatterns: 1 }, |
| 25548 | {.Opcode: AArch64::STRDroX, .PatternStart: 995, .NumPatterns: 1 }, |
| 25549 | {.Opcode: AArch64::STRDui, .PatternStart: 996, .NumPatterns: 1 }, |
| 25550 | {.Opcode: AArch64::STRHHroX, .PatternStart: 997, .NumPatterns: 1 }, |
| 25551 | {.Opcode: AArch64::STRHHui, .PatternStart: 998, .NumPatterns: 1 }, |
| 25552 | {.Opcode: AArch64::STRHroX, .PatternStart: 999, .NumPatterns: 1 }, |
| 25553 | {.Opcode: AArch64::STRHui, .PatternStart: 1000, .NumPatterns: 1 }, |
| 25554 | {.Opcode: AArch64::STRQroX, .PatternStart: 1001, .NumPatterns: 1 }, |
| 25555 | {.Opcode: AArch64::STRQui, .PatternStart: 1002, .NumPatterns: 1 }, |
| 25556 | {.Opcode: AArch64::STRSroX, .PatternStart: 1003, .NumPatterns: 1 }, |
| 25557 | {.Opcode: AArch64::STRSui, .PatternStart: 1004, .NumPatterns: 1 }, |
| 25558 | {.Opcode: AArch64::STRWroX, .PatternStart: 1005, .NumPatterns: 1 }, |
| 25559 | {.Opcode: AArch64::STRWui, .PatternStart: 1006, .NumPatterns: 1 }, |
| 25560 | {.Opcode: AArch64::STRXroX, .PatternStart: 1007, .NumPatterns: 1 }, |
| 25561 | {.Opcode: AArch64::STRXui, .PatternStart: 1008, .NumPatterns: 1 }, |
| 25562 | {.Opcode: AArch64::STR_PXI, .PatternStart: 1009, .NumPatterns: 1 }, |
| 25563 | {.Opcode: AArch64::STR_ZA, .PatternStart: 1010, .NumPatterns: 1 }, |
| 25564 | {.Opcode: AArch64::STR_ZXI, .PatternStart: 1011, .NumPatterns: 1 }, |
| 25565 | {.Opcode: AArch64::STTNPQi, .PatternStart: 1012, .NumPatterns: 1 }, |
| 25566 | {.Opcode: AArch64::STTNPXi, .PatternStart: 1013, .NumPatterns: 1 }, |
| 25567 | {.Opcode: AArch64::STTPQi, .PatternStart: 1014, .NumPatterns: 1 }, |
| 25568 | {.Opcode: AArch64::STTPi, .PatternStart: 1015, .NumPatterns: 1 }, |
| 25569 | {.Opcode: AArch64::STTRBi, .PatternStart: 1016, .NumPatterns: 1 }, |
| 25570 | {.Opcode: AArch64::STTRHi, .PatternStart: 1017, .NumPatterns: 1 }, |
| 25571 | {.Opcode: AArch64::STTRWi, .PatternStart: 1018, .NumPatterns: 1 }, |
| 25572 | {.Opcode: AArch64::STTRXi, .PatternStart: 1019, .NumPatterns: 1 }, |
| 25573 | {.Opcode: AArch64::STURBBi, .PatternStart: 1020, .NumPatterns: 1 }, |
| 25574 | {.Opcode: AArch64::STURBi, .PatternStart: 1021, .NumPatterns: 1 }, |
| 25575 | {.Opcode: AArch64::STURDi, .PatternStart: 1022, .NumPatterns: 1 }, |
| 25576 | {.Opcode: AArch64::STURHHi, .PatternStart: 1023, .NumPatterns: 1 }, |
| 25577 | {.Opcode: AArch64::STURHi, .PatternStart: 1024, .NumPatterns: 1 }, |
| 25578 | {.Opcode: AArch64::STURQi, .PatternStart: 1025, .NumPatterns: 1 }, |
| 25579 | {.Opcode: AArch64::STURSi, .PatternStart: 1026, .NumPatterns: 1 }, |
| 25580 | {.Opcode: AArch64::STURWi, .PatternStart: 1027, .NumPatterns: 1 }, |
| 25581 | {.Opcode: AArch64::STURXi, .PatternStart: 1028, .NumPatterns: 1 }, |
| 25582 | {.Opcode: AArch64::STZ2Gi, .PatternStart: 1029, .NumPatterns: 1 }, |
| 25583 | {.Opcode: AArch64::STZGi, .PatternStart: 1030, .NumPatterns: 1 }, |
| 25584 | {.Opcode: AArch64::SUBPT_shift, .PatternStart: 1031, .NumPatterns: 1 }, |
| 25585 | {.Opcode: AArch64::SUBSWri, .PatternStart: 1032, .NumPatterns: 1 }, |
| 25586 | {.Opcode: AArch64::SUBSWrs, .PatternStart: 1033, .NumPatterns: 5 }, |
| 25587 | {.Opcode: AArch64::SUBSWrx, .PatternStart: 1038, .NumPatterns: 3 }, |
| 25588 | {.Opcode: AArch64::SUBSXri, .PatternStart: 1041, .NumPatterns: 1 }, |
| 25589 | {.Opcode: AArch64::SUBSXrs, .PatternStart: 1042, .NumPatterns: 5 }, |
| 25590 | {.Opcode: AArch64::SUBSXrx, .PatternStart: 1047, .NumPatterns: 1 }, |
| 25591 | {.Opcode: AArch64::SUBSXrx64, .PatternStart: 1048, .NumPatterns: 3 }, |
| 25592 | {.Opcode: AArch64::SUBWrs, .PatternStart: 1051, .NumPatterns: 3 }, |
| 25593 | {.Opcode: AArch64::SUBWrx, .PatternStart: 1054, .NumPatterns: 2 }, |
| 25594 | {.Opcode: AArch64::SUBXrs, .PatternStart: 1056, .NumPatterns: 3 }, |
| 25595 | {.Opcode: AArch64::SUBXrx64, .PatternStart: 1059, .NumPatterns: 2 }, |
| 25596 | {.Opcode: AArch64::SYSPxt_XZR, .PatternStart: 1061, .NumPatterns: 1 }, |
| 25597 | {.Opcode: AArch64::SYSxt, .PatternStart: 1062, .NumPatterns: 1 }, |
| 25598 | {.Opcode: AArch64::TCHANGEBri, .PatternStart: 1063, .NumPatterns: 1 }, |
| 25599 | {.Opcode: AArch64::TCHANGEBrr, .PatternStart: 1064, .NumPatterns: 1 }, |
| 25600 | {.Opcode: AArch64::TCHANGEFri, .PatternStart: 1065, .NumPatterns: 1 }, |
| 25601 | {.Opcode: AArch64::TCHANGEFrr, .PatternStart: 1066, .NumPatterns: 1 }, |
| 25602 | {.Opcode: AArch64::TENTER, .PatternStart: 1067, .NumPatterns: 1 }, |
| 25603 | {.Opcode: AArch64::TEXIT, .PatternStart: 1068, .NumPatterns: 1 }, |
| 25604 | {.Opcode: AArch64::UBFMWri, .PatternStart: 1069, .NumPatterns: 3 }, |
| 25605 | {.Opcode: AArch64::UBFMXri, .PatternStart: 1072, .NumPatterns: 4 }, |
| 25606 | {.Opcode: AArch64::UMADDLrrr, .PatternStart: 1076, .NumPatterns: 1 }, |
| 25607 | {.Opcode: AArch64::UMOVvi32, .PatternStart: 1077, .NumPatterns: 1 }, |
| 25608 | {.Opcode: AArch64::UMOVvi32_idx0, .PatternStart: 1078, .NumPatterns: 1 }, |
| 25609 | {.Opcode: AArch64::UMOVvi64, .PatternStart: 1079, .NumPatterns: 1 }, |
| 25610 | {.Opcode: AArch64::UMOVvi64_idx0, .PatternStart: 1080, .NumPatterns: 1 }, |
| 25611 | {.Opcode: AArch64::UMSUBLrrr, .PatternStart: 1081, .NumPatterns: 1 }, |
| 25612 | {.Opcode: AArch64::UQDECB_WPiI, .PatternStart: 1082, .NumPatterns: 2 }, |
| 25613 | {.Opcode: AArch64::UQDECB_XPiI, .PatternStart: 1084, .NumPatterns: 2 }, |
| 25614 | {.Opcode: AArch64::UQDECD_WPiI, .PatternStart: 1086, .NumPatterns: 2 }, |
| 25615 | {.Opcode: AArch64::UQDECD_XPiI, .PatternStart: 1088, .NumPatterns: 2 }, |
| 25616 | {.Opcode: AArch64::UQDECD_ZPiI, .PatternStart: 1090, .NumPatterns: 2 }, |
| 25617 | {.Opcode: AArch64::UQDECH_WPiI, .PatternStart: 1092, .NumPatterns: 2 }, |
| 25618 | {.Opcode: AArch64::UQDECH_XPiI, .PatternStart: 1094, .NumPatterns: 2 }, |
| 25619 | {.Opcode: AArch64::UQDECH_ZPiI, .PatternStart: 1096, .NumPatterns: 2 }, |
| 25620 | {.Opcode: AArch64::UQDECW_WPiI, .PatternStart: 1098, .NumPatterns: 2 }, |
| 25621 | {.Opcode: AArch64::UQDECW_XPiI, .PatternStart: 1100, .NumPatterns: 2 }, |
| 25622 | {.Opcode: AArch64::UQDECW_ZPiI, .PatternStart: 1102, .NumPatterns: 2 }, |
| 25623 | {.Opcode: AArch64::UQINCB_WPiI, .PatternStart: 1104, .NumPatterns: 2 }, |
| 25624 | {.Opcode: AArch64::UQINCB_XPiI, .PatternStart: 1106, .NumPatterns: 2 }, |
| 25625 | {.Opcode: AArch64::UQINCD_WPiI, .PatternStart: 1108, .NumPatterns: 2 }, |
| 25626 | {.Opcode: AArch64::UQINCD_XPiI, .PatternStart: 1110, .NumPatterns: 2 }, |
| 25627 | {.Opcode: AArch64::UQINCD_ZPiI, .PatternStart: 1112, .NumPatterns: 2 }, |
| 25628 | {.Opcode: AArch64::UQINCH_WPiI, .PatternStart: 1114, .NumPatterns: 2 }, |
| 25629 | {.Opcode: AArch64::UQINCH_XPiI, .PatternStart: 1116, .NumPatterns: 2 }, |
| 25630 | {.Opcode: AArch64::UQINCH_ZPiI, .PatternStart: 1118, .NumPatterns: 2 }, |
| 25631 | {.Opcode: AArch64::UQINCW_WPiI, .PatternStart: 1120, .NumPatterns: 2 }, |
| 25632 | {.Opcode: AArch64::UQINCW_XPiI, .PatternStart: 1122, .NumPatterns: 2 }, |
| 25633 | {.Opcode: AArch64::UQINCW_ZPiI, .PatternStart: 1124, .NumPatterns: 2 }, |
| 25634 | {.Opcode: AArch64::XPACLRI, .PatternStart: 1126, .NumPatterns: 1 }, |
| 25635 | {.Opcode: AArch64::ZERO_M, .PatternStart: 1127, .NumPatterns: 15 }, |
| 25636 | }; |
| 25637 | |
| 25638 | static const AliasPattern Patterns[] = { |
| 25639 | // AArch64::ADDPT_shift - 0 |
| 25640 | {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 4, .NumConds: 7 }, |
| 25641 | // AArch64::ADDSWri - 1 |
| 25642 | {.AsmStrOffset: 17, .AliasCondStart: 7, .NumOperands: 4, .NumConds: 2 }, |
| 25643 | // AArch64::ADDSWrs - 2 |
| 25644 | {.AsmStrOffset: 30, .AliasCondStart: 9, .NumOperands: 4, .NumConds: 4 }, |
| 25645 | {.AsmStrOffset: 41, .AliasCondStart: 13, .NumOperands: 4, .NumConds: 3 }, |
| 25646 | {.AsmStrOffset: 56, .AliasCondStart: 16, .NumOperands: 4, .NumConds: 4 }, |
| 25647 | // AArch64::ADDSWrx - 5 |
| 25648 | {.AsmStrOffset: 30, .AliasCondStart: 20, .NumOperands: 4, .NumConds: 4 }, |
| 25649 | {.AsmStrOffset: 72, .AliasCondStart: 24, .NumOperands: 4, .NumConds: 3 }, |
| 25650 | {.AsmStrOffset: 56, .AliasCondStart: 27, .NumOperands: 4, .NumConds: 4 }, |
| 25651 | // AArch64::ADDSXri - 8 |
| 25652 | {.AsmStrOffset: 17, .AliasCondStart: 31, .NumOperands: 4, .NumConds: 2 }, |
| 25653 | // AArch64::ADDSXrs - 9 |
| 25654 | {.AsmStrOffset: 30, .AliasCondStart: 33, .NumOperands: 4, .NumConds: 4 }, |
| 25655 | {.AsmStrOffset: 41, .AliasCondStart: 37, .NumOperands: 4, .NumConds: 3 }, |
| 25656 | {.AsmStrOffset: 56, .AliasCondStart: 40, .NumOperands: 4, .NumConds: 4 }, |
| 25657 | // AArch64::ADDSXrx - 12 |
| 25658 | {.AsmStrOffset: 72, .AliasCondStart: 44, .NumOperands: 4, .NumConds: 3 }, |
| 25659 | // AArch64::ADDSXrx64 - 13 |
| 25660 | {.AsmStrOffset: 30, .AliasCondStart: 47, .NumOperands: 4, .NumConds: 4 }, |
| 25661 | {.AsmStrOffset: 72, .AliasCondStart: 51, .NumOperands: 4, .NumConds: 3 }, |
| 25662 | {.AsmStrOffset: 56, .AliasCondStart: 54, .NumOperands: 4, .NumConds: 4 }, |
| 25663 | // AArch64::ADDWri - 16 |
| 25664 | {.AsmStrOffset: 87, .AliasCondStart: 58, .NumOperands: 4, .NumConds: 4 }, |
| 25665 | {.AsmStrOffset: 87, .AliasCondStart: 62, .NumOperands: 4, .NumConds: 4 }, |
| 25666 | // AArch64::ADDWrs - 18 |
| 25667 | {.AsmStrOffset: 98, .AliasCondStart: 66, .NumOperands: 4, .NumConds: 4 }, |
| 25668 | // AArch64::ADDWrx - 19 |
| 25669 | {.AsmStrOffset: 98, .AliasCondStart: 70, .NumOperands: 4, .NumConds: 4 }, |
| 25670 | {.AsmStrOffset: 98, .AliasCondStart: 74, .NumOperands: 4, .NumConds: 4 }, |
| 25671 | // AArch64::ADDXri - 21 |
| 25672 | {.AsmStrOffset: 87, .AliasCondStart: 78, .NumOperands: 4, .NumConds: 4 }, |
| 25673 | {.AsmStrOffset: 87, .AliasCondStart: 82, .NumOperands: 4, .NumConds: 4 }, |
| 25674 | // AArch64::ADDXrs - 23 |
| 25675 | {.AsmStrOffset: 98, .AliasCondStart: 86, .NumOperands: 4, .NumConds: 4 }, |
| 25676 | // AArch64::ADDXrx64 - 24 |
| 25677 | {.AsmStrOffset: 98, .AliasCondStart: 90, .NumOperands: 4, .NumConds: 4 }, |
| 25678 | {.AsmStrOffset: 98, .AliasCondStart: 94, .NumOperands: 4, .NumConds: 4 }, |
| 25679 | // AArch64::ANDSWri - 26 |
| 25680 | {.AsmStrOffset: 113, .AliasCondStart: 98, .NumOperands: 3, .NumConds: 2 }, |
| 25681 | // AArch64::ANDSWrs - 27 |
| 25682 | {.AsmStrOffset: 126, .AliasCondStart: 100, .NumOperands: 4, .NumConds: 4 }, |
| 25683 | {.AsmStrOffset: 137, .AliasCondStart: 104, .NumOperands: 4, .NumConds: 3 }, |
| 25684 | {.AsmStrOffset: 152, .AliasCondStart: 107, .NumOperands: 4, .NumConds: 4 }, |
| 25685 | // AArch64::ANDSXri - 30 |
| 25686 | {.AsmStrOffset: 168, .AliasCondStart: 111, .NumOperands: 3, .NumConds: 2 }, |
| 25687 | // AArch64::ANDSXrs - 31 |
| 25688 | {.AsmStrOffset: 126, .AliasCondStart: 113, .NumOperands: 4, .NumConds: 4 }, |
| 25689 | {.AsmStrOffset: 137, .AliasCondStart: 117, .NumOperands: 4, .NumConds: 3 }, |
| 25690 | {.AsmStrOffset: 152, .AliasCondStart: 120, .NumOperands: 4, .NumConds: 4 }, |
| 25691 | // AArch64::ANDS_PPzPP - 34 |
| 25692 | {.AsmStrOffset: 181, .AliasCondStart: 124, .NumOperands: 4, .NumConds: 8 }, |
| 25693 | // AArch64::ANDWrs - 35 |
| 25694 | {.AsmStrOffset: 205, .AliasCondStart: 132, .NumOperands: 4, .NumConds: 4 }, |
| 25695 | // AArch64::ANDXrs - 36 |
| 25696 | {.AsmStrOffset: 205, .AliasCondStart: 136, .NumOperands: 4, .NumConds: 4 }, |
| 25697 | // AArch64::AND_PPzPP - 37 |
| 25698 | {.AsmStrOffset: 220, .AliasCondStart: 140, .NumOperands: 4, .NumConds: 8 }, |
| 25699 | // AArch64::AND_ZI - 38 |
| 25700 | {.AsmStrOffset: 243, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 7 }, |
| 25701 | {.AsmStrOffset: 264, .AliasCondStart: 155, .NumOperands: 3, .NumConds: 7 }, |
| 25702 | {.AsmStrOffset: 285, .AliasCondStart: 162, .NumOperands: 3, .NumConds: 7 }, |
| 25703 | // AArch64::AUTIA1716 - 41 |
| 25704 | {.AsmStrOffset: 306, .AliasCondStart: 169, .NumOperands: 0, .NumConds: 3 }, |
| 25705 | // AArch64::AUTIASP - 42 |
| 25706 | {.AsmStrOffset: 316, .AliasCondStart: 172, .NumOperands: 0, .NumConds: 3 }, |
| 25707 | // AArch64::AUTIAZ - 43 |
| 25708 | {.AsmStrOffset: 324, .AliasCondStart: 175, .NumOperands: 0, .NumConds: 3 }, |
| 25709 | // AArch64::AUTIB1716 - 44 |
| 25710 | {.AsmStrOffset: 331, .AliasCondStart: 178, .NumOperands: 0, .NumConds: 3 }, |
| 25711 | // AArch64::AUTIBSP - 45 |
| 25712 | {.AsmStrOffset: 341, .AliasCondStart: 181, .NumOperands: 0, .NumConds: 3 }, |
| 25713 | // AArch64::AUTIBZ - 46 |
| 25714 | {.AsmStrOffset: 349, .AliasCondStart: 184, .NumOperands: 0, .NumConds: 3 }, |
| 25715 | // AArch64::BICSWrs - 47 |
| 25716 | {.AsmStrOffset: 356, .AliasCondStart: 187, .NumOperands: 4, .NumConds: 4 }, |
| 25717 | // AArch64::BICSXrs - 48 |
| 25718 | {.AsmStrOffset: 356, .AliasCondStart: 191, .NumOperands: 4, .NumConds: 4 }, |
| 25719 | // AArch64::BICWrs - 49 |
| 25720 | {.AsmStrOffset: 372, .AliasCondStart: 195, .NumOperands: 4, .NumConds: 4 }, |
| 25721 | // AArch64::BICXrs - 50 |
| 25722 | {.AsmStrOffset: 372, .AliasCondStart: 199, .NumOperands: 4, .NumConds: 4 }, |
| 25723 | // AArch64::CHKFEAT - 51 |
| 25724 | {.AsmStrOffset: 387, .AliasCondStart: 203, .NumOperands: 0, .NumConds: 3 }, |
| 25725 | // AArch64::CLREX - 52 |
| 25726 | {.AsmStrOffset: 399, .AliasCondStart: 206, .NumOperands: 1, .NumConds: 1 }, |
| 25727 | // AArch64::CNTB_XPiI - 53 |
| 25728 | {.AsmStrOffset: 405, .AliasCondStart: 207, .NumOperands: 3, .NumConds: 7 }, |
| 25729 | {.AsmStrOffset: 413, .AliasCondStart: 214, .NumOperands: 3, .NumConds: 7 }, |
| 25730 | // AArch64::CNTD_XPiI - 55 |
| 25731 | {.AsmStrOffset: 427, .AliasCondStart: 221, .NumOperands: 3, .NumConds: 7 }, |
| 25732 | {.AsmStrOffset: 435, .AliasCondStart: 228, .NumOperands: 3, .NumConds: 7 }, |
| 25733 | // AArch64::CNTH_XPiI - 57 |
| 25734 | {.AsmStrOffset: 449, .AliasCondStart: 235, .NumOperands: 3, .NumConds: 7 }, |
| 25735 | {.AsmStrOffset: 457, .AliasCondStart: 242, .NumOperands: 3, .NumConds: 7 }, |
| 25736 | // AArch64::CNTW_XPiI - 59 |
| 25737 | {.AsmStrOffset: 471, .AliasCondStart: 249, .NumOperands: 3, .NumConds: 7 }, |
| 25738 | {.AsmStrOffset: 479, .AliasCondStart: 256, .NumOperands: 3, .NumConds: 7 }, |
| 25739 | // AArch64::CPY_ZPmI_B - 61 |
| 25740 | {.AsmStrOffset: 493, .AliasCondStart: 263, .NumOperands: 5, .NumConds: 7 }, |
| 25741 | // AArch64::CPY_ZPmI_D - 62 |
| 25742 | {.AsmStrOffset: 516, .AliasCondStart: 270, .NumOperands: 5, .NumConds: 7 }, |
| 25743 | // AArch64::CPY_ZPmI_H - 63 |
| 25744 | {.AsmStrOffset: 539, .AliasCondStart: 277, .NumOperands: 5, .NumConds: 7 }, |
| 25745 | // AArch64::CPY_ZPmI_S - 64 |
| 25746 | {.AsmStrOffset: 562, .AliasCondStart: 284, .NumOperands: 5, .NumConds: 7 }, |
| 25747 | // AArch64::CPY_ZPmR_B - 65 |
| 25748 | {.AsmStrOffset: 585, .AliasCondStart: 291, .NumOperands: 4, .NumConds: 8 }, |
| 25749 | // AArch64::CPY_ZPmR_D - 66 |
| 25750 | {.AsmStrOffset: 606, .AliasCondStart: 299, .NumOperands: 4, .NumConds: 8 }, |
| 25751 | // AArch64::CPY_ZPmR_H - 67 |
| 25752 | {.AsmStrOffset: 627, .AliasCondStart: 307, .NumOperands: 4, .NumConds: 8 }, |
| 25753 | // AArch64::CPY_ZPmR_S - 68 |
| 25754 | {.AsmStrOffset: 648, .AliasCondStart: 315, .NumOperands: 4, .NumConds: 8 }, |
| 25755 | // AArch64::CPY_ZPmV_B - 69 |
| 25756 | {.AsmStrOffset: 585, .AliasCondStart: 323, .NumOperands: 4, .NumConds: 8 }, |
| 25757 | // AArch64::CPY_ZPmV_D - 70 |
| 25758 | {.AsmStrOffset: 606, .AliasCondStart: 331, .NumOperands: 4, .NumConds: 8 }, |
| 25759 | // AArch64::CPY_ZPmV_H - 71 |
| 25760 | {.AsmStrOffset: 627, .AliasCondStart: 339, .NumOperands: 4, .NumConds: 8 }, |
| 25761 | // AArch64::CPY_ZPmV_S - 72 |
| 25762 | {.AsmStrOffset: 648, .AliasCondStart: 347, .NumOperands: 4, .NumConds: 8 }, |
| 25763 | // AArch64::CPY_ZPzI_B - 73 |
| 25764 | {.AsmStrOffset: 669, .AliasCondStart: 355, .NumOperands: 4, .NumConds: 6 }, |
| 25765 | // AArch64::CPY_ZPzI_D - 74 |
| 25766 | {.AsmStrOffset: 692, .AliasCondStart: 361, .NumOperands: 4, .NumConds: 6 }, |
| 25767 | // AArch64::CPY_ZPzI_H - 75 |
| 25768 | {.AsmStrOffset: 715, .AliasCondStart: 367, .NumOperands: 4, .NumConds: 6 }, |
| 25769 | // AArch64::CPY_ZPzI_S - 76 |
| 25770 | {.AsmStrOffset: 738, .AliasCondStart: 373, .NumOperands: 4, .NumConds: 6 }, |
| 25771 | // AArch64::CSINCWr - 77 |
| 25772 | {.AsmStrOffset: 761, .AliasCondStart: 379, .NumOperands: 4, .NumConds: 4 }, |
| 25773 | {.AsmStrOffset: 775, .AliasCondStart: 383, .NumOperands: 4, .NumConds: 4 }, |
| 25774 | // AArch64::CSINCXr - 79 |
| 25775 | {.AsmStrOffset: 761, .AliasCondStart: 387, .NumOperands: 4, .NumConds: 4 }, |
| 25776 | {.AsmStrOffset: 775, .AliasCondStart: 391, .NumOperands: 4, .NumConds: 4 }, |
| 25777 | // AArch64::CSINVWr - 81 |
| 25778 | {.AsmStrOffset: 793, .AliasCondStart: 395, .NumOperands: 4, .NumConds: 4 }, |
| 25779 | {.AsmStrOffset: 808, .AliasCondStart: 399, .NumOperands: 4, .NumConds: 4 }, |
| 25780 | // AArch64::CSINVXr - 83 |
| 25781 | {.AsmStrOffset: 793, .AliasCondStart: 403, .NumOperands: 4, .NumConds: 4 }, |
| 25782 | {.AsmStrOffset: 808, .AliasCondStart: 407, .NumOperands: 4, .NumConds: 4 }, |
| 25783 | // AArch64::CSNEGWr - 85 |
| 25784 | {.AsmStrOffset: 826, .AliasCondStart: 411, .NumOperands: 4, .NumConds: 4 }, |
| 25785 | // AArch64::CSNEGXr - 86 |
| 25786 | {.AsmStrOffset: 826, .AliasCondStart: 415, .NumOperands: 4, .NumConds: 4 }, |
| 25787 | // AArch64::DCPS1 - 87 |
| 25788 | {.AsmStrOffset: 844, .AliasCondStart: 419, .NumOperands: 1, .NumConds: 1 }, |
| 25789 | // AArch64::DCPS2 - 88 |
| 25790 | {.AsmStrOffset: 850, .AliasCondStart: 420, .NumOperands: 1, .NumConds: 1 }, |
| 25791 | // AArch64::DCPS3 - 89 |
| 25792 | {.AsmStrOffset: 856, .AliasCondStart: 421, .NumOperands: 1, .NumConds: 4 }, |
| 25793 | // AArch64::DECB_XPiI - 90 |
| 25794 | {.AsmStrOffset: 862, .AliasCondStart: 425, .NumOperands: 4, .NumConds: 8 }, |
| 25795 | {.AsmStrOffset: 870, .AliasCondStart: 433, .NumOperands: 4, .NumConds: 8 }, |
| 25796 | // AArch64::DECD_XPiI - 92 |
| 25797 | {.AsmStrOffset: 884, .AliasCondStart: 441, .NumOperands: 4, .NumConds: 8 }, |
| 25798 | {.AsmStrOffset: 892, .AliasCondStart: 449, .NumOperands: 4, .NumConds: 8 }, |
| 25799 | // AArch64::DECD_ZPiI - 94 |
| 25800 | {.AsmStrOffset: 906, .AliasCondStart: 457, .NumOperands: 4, .NumConds: 8 }, |
| 25801 | {.AsmStrOffset: 916, .AliasCondStart: 465, .NumOperands: 4, .NumConds: 8 }, |
| 25802 | // AArch64::DECH_XPiI - 96 |
| 25803 | {.AsmStrOffset: 932, .AliasCondStart: 473, .NumOperands: 4, .NumConds: 8 }, |
| 25804 | {.AsmStrOffset: 940, .AliasCondStart: 481, .NumOperands: 4, .NumConds: 8 }, |
| 25805 | // AArch64::DECH_ZPiI - 98 |
| 25806 | {.AsmStrOffset: 954, .AliasCondStart: 489, .NumOperands: 4, .NumConds: 8 }, |
| 25807 | {.AsmStrOffset: 964, .AliasCondStart: 497, .NumOperands: 4, .NumConds: 8 }, |
| 25808 | // AArch64::DECW_XPiI - 100 |
| 25809 | {.AsmStrOffset: 980, .AliasCondStart: 505, .NumOperands: 4, .NumConds: 8 }, |
| 25810 | {.AsmStrOffset: 988, .AliasCondStart: 513, .NumOperands: 4, .NumConds: 8 }, |
| 25811 | // AArch64::DECW_ZPiI - 102 |
| 25812 | {.AsmStrOffset: 1002, .AliasCondStart: 521, .NumOperands: 4, .NumConds: 8 }, |
| 25813 | {.AsmStrOffset: 1012, .AliasCondStart: 529, .NumOperands: 4, .NumConds: 8 }, |
| 25814 | // AArch64::DSB - 104 |
| 25815 | {.AsmStrOffset: 1028, .AliasCondStart: 537, .NumOperands: 1, .NumConds: 1 }, |
| 25816 | {.AsmStrOffset: 1033, .AliasCondStart: 538, .NumOperands: 1, .NumConds: 1 }, |
| 25817 | {.AsmStrOffset: 1039, .AliasCondStart: 539, .NumOperands: 1, .NumConds: 4 }, |
| 25818 | // AArch64::DUPM_ZI - 107 |
| 25819 | {.AsmStrOffset: 1043, .AliasCondStart: 543, .NumOperands: 2, .NumConds: 6 }, |
| 25820 | {.AsmStrOffset: 1058, .AliasCondStart: 549, .NumOperands: 2, .NumConds: 6 }, |
| 25821 | {.AsmStrOffset: 1073, .AliasCondStart: 555, .NumOperands: 2, .NumConds: 6 }, |
| 25822 | {.AsmStrOffset: 1088, .AliasCondStart: 561, .NumOperands: 2, .NumConds: 6 }, |
| 25823 | {.AsmStrOffset: 1104, .AliasCondStart: 567, .NumOperands: 2, .NumConds: 6 }, |
| 25824 | {.AsmStrOffset: 1120, .AliasCondStart: 573, .NumOperands: 2, .NumConds: 6 }, |
| 25825 | // AArch64::DUP_ZI_B - 113 |
| 25826 | {.AsmStrOffset: 1136, .AliasCondStart: 579, .NumOperands: 3, .NumConds: 5 }, |
| 25827 | // AArch64::DUP_ZI_D - 114 |
| 25828 | {.AsmStrOffset: 1151, .AliasCondStart: 584, .NumOperands: 3, .NumConds: 5 }, |
| 25829 | {.AsmStrOffset: 1166, .AliasCondStart: 589, .NumOperands: 3, .NumConds: 7 }, |
| 25830 | // AArch64::DUP_ZI_H - 116 |
| 25831 | {.AsmStrOffset: 1182, .AliasCondStart: 596, .NumOperands: 3, .NumConds: 5 }, |
| 25832 | {.AsmStrOffset: 1197, .AliasCondStart: 601, .NumOperands: 3, .NumConds: 7 }, |
| 25833 | // AArch64::DUP_ZI_S - 118 |
| 25834 | {.AsmStrOffset: 1213, .AliasCondStart: 608, .NumOperands: 3, .NumConds: 5 }, |
| 25835 | {.AsmStrOffset: 1228, .AliasCondStart: 613, .NumOperands: 3, .NumConds: 7 }, |
| 25836 | // AArch64::DUP_ZR_B - 120 |
| 25837 | {.AsmStrOffset: 1244, .AliasCondStart: 620, .NumOperands: 2, .NumConds: 6 }, |
| 25838 | // AArch64::DUP_ZR_D - 121 |
| 25839 | {.AsmStrOffset: 1257, .AliasCondStart: 626, .NumOperands: 2, .NumConds: 6 }, |
| 25840 | // AArch64::DUP_ZR_H - 122 |
| 25841 | {.AsmStrOffset: 1270, .AliasCondStart: 632, .NumOperands: 2, .NumConds: 6 }, |
| 25842 | // AArch64::DUP_ZR_S - 123 |
| 25843 | {.AsmStrOffset: 1283, .AliasCondStart: 638, .NumOperands: 2, .NumConds: 6 }, |
| 25844 | // AArch64::DUP_ZZI_B - 124 |
| 25845 | {.AsmStrOffset: 1296, .AliasCondStart: 644, .NumOperands: 3, .NumConds: 7 }, |
| 25846 | {.AsmStrOffset: 1311, .AliasCondStart: 651, .NumOperands: 3, .NumConds: 6 }, |
| 25847 | // AArch64::DUP_ZZI_D - 126 |
| 25848 | {.AsmStrOffset: 1330, .AliasCondStart: 657, .NumOperands: 3, .NumConds: 7 }, |
| 25849 | {.AsmStrOffset: 1345, .AliasCondStart: 664, .NumOperands: 3, .NumConds: 6 }, |
| 25850 | // AArch64::DUP_ZZI_H - 128 |
| 25851 | {.AsmStrOffset: 1364, .AliasCondStart: 670, .NumOperands: 3, .NumConds: 7 }, |
| 25852 | {.AsmStrOffset: 1379, .AliasCondStart: 677, .NumOperands: 3, .NumConds: 6 }, |
| 25853 | // AArch64::DUP_ZZI_Q - 130 |
| 25854 | {.AsmStrOffset: 1398, .AliasCondStart: 683, .NumOperands: 3, .NumConds: 7 }, |
| 25855 | {.AsmStrOffset: 1413, .AliasCondStart: 690, .NumOperands: 3, .NumConds: 6 }, |
| 25856 | // AArch64::DUP_ZZI_S - 132 |
| 25857 | {.AsmStrOffset: 1432, .AliasCondStart: 696, .NumOperands: 3, .NumConds: 7 }, |
| 25858 | {.AsmStrOffset: 1447, .AliasCondStart: 703, .NumOperands: 3, .NumConds: 6 }, |
| 25859 | // AArch64::EONWrs - 134 |
| 25860 | {.AsmStrOffset: 1466, .AliasCondStart: 709, .NumOperands: 4, .NumConds: 4 }, |
| 25861 | // AArch64::EONXrs - 135 |
| 25862 | {.AsmStrOffset: 1466, .AliasCondStart: 713, .NumOperands: 4, .NumConds: 4 }, |
| 25863 | // AArch64::EORS_PPzPP - 136 |
| 25864 | {.AsmStrOffset: 1481, .AliasCondStart: 717, .NumOperands: 4, .NumConds: 8 }, |
| 25865 | // AArch64::EORWrs - 137 |
| 25866 | {.AsmStrOffset: 1505, .AliasCondStart: 725, .NumOperands: 4, .NumConds: 4 }, |
| 25867 | // AArch64::EORXrs - 138 |
| 25868 | {.AsmStrOffset: 1505, .AliasCondStart: 729, .NumOperands: 4, .NumConds: 4 }, |
| 25869 | // AArch64::EOR_PPzPP - 139 |
| 25870 | {.AsmStrOffset: 1520, .AliasCondStart: 733, .NumOperands: 4, .NumConds: 8 }, |
| 25871 | // AArch64::EOR_ZI - 140 |
| 25872 | {.AsmStrOffset: 1543, .AliasCondStart: 741, .NumOperands: 3, .NumConds: 7 }, |
| 25873 | {.AsmStrOffset: 1564, .AliasCondStart: 748, .NumOperands: 3, .NumConds: 7 }, |
| 25874 | {.AsmStrOffset: 1585, .AliasCondStart: 755, .NumOperands: 3, .NumConds: 7 }, |
| 25875 | // AArch64::EXTRACT_ZPMXI_H_B - 143 |
| 25876 | {.AsmStrOffset: 1606, .AliasCondStart: 762, .NumOperands: 6, .NumConds: 8 }, |
| 25877 | // AArch64::EXTRACT_ZPMXI_H_D - 144 |
| 25878 | {.AsmStrOffset: 1639, .AliasCondStart: 770, .NumOperands: 6, .NumConds: 8 }, |
| 25879 | // AArch64::EXTRACT_ZPMXI_H_H - 145 |
| 25880 | {.AsmStrOffset: 1672, .AliasCondStart: 778, .NumOperands: 6, .NumConds: 8 }, |
| 25881 | // AArch64::EXTRACT_ZPMXI_H_Q - 146 |
| 25882 | {.AsmStrOffset: 1705, .AliasCondStart: 786, .NumOperands: 6, .NumConds: 8 }, |
| 25883 | // AArch64::EXTRACT_ZPMXI_H_S - 147 |
| 25884 | {.AsmStrOffset: 1738, .AliasCondStart: 794, .NumOperands: 6, .NumConds: 8 }, |
| 25885 | // AArch64::EXTRACT_ZPMXI_V_B - 148 |
| 25886 | {.AsmStrOffset: 1771, .AliasCondStart: 802, .NumOperands: 6, .NumConds: 8 }, |
| 25887 | // AArch64::EXTRACT_ZPMXI_V_D - 149 |
| 25888 | {.AsmStrOffset: 1804, .AliasCondStart: 810, .NumOperands: 6, .NumConds: 8 }, |
| 25889 | // AArch64::EXTRACT_ZPMXI_V_H - 150 |
| 25890 | {.AsmStrOffset: 1837, .AliasCondStart: 818, .NumOperands: 6, .NumConds: 8 }, |
| 25891 | // AArch64::EXTRACT_ZPMXI_V_Q - 151 |
| 25892 | {.AsmStrOffset: 1870, .AliasCondStart: 826, .NumOperands: 6, .NumConds: 8 }, |
| 25893 | // AArch64::EXTRACT_ZPMXI_V_S - 152 |
| 25894 | {.AsmStrOffset: 1903, .AliasCondStart: 834, .NumOperands: 6, .NumConds: 8 }, |
| 25895 | // AArch64::EXTRWrri - 153 |
| 25896 | {.AsmStrOffset: 1936, .AliasCondStart: 842, .NumOperands: 4, .NumConds: 3 }, |
| 25897 | // AArch64::EXTRXrri - 154 |
| 25898 | {.AsmStrOffset: 1936, .AliasCondStart: 845, .NumOperands: 4, .NumConds: 3 }, |
| 25899 | // AArch64::FCPY_ZPmI_D - 155 |
| 25900 | {.AsmStrOffset: 1951, .AliasCondStart: 848, .NumOperands: 4, .NumConds: 7 }, |
| 25901 | // AArch64::FCPY_ZPmI_H - 156 |
| 25902 | {.AsmStrOffset: 1975, .AliasCondStart: 855, .NumOperands: 4, .NumConds: 7 }, |
| 25903 | // AArch64::FCPY_ZPmI_S - 157 |
| 25904 | {.AsmStrOffset: 1999, .AliasCondStart: 862, .NumOperands: 4, .NumConds: 7 }, |
| 25905 | // AArch64::FDUP_ZI_D - 158 |
| 25906 | {.AsmStrOffset: 2023, .AliasCondStart: 869, .NumOperands: 2, .NumConds: 5 }, |
| 25907 | // AArch64::FDUP_ZI_H - 159 |
| 25908 | {.AsmStrOffset: 2039, .AliasCondStart: 874, .NumOperands: 2, .NumConds: 5 }, |
| 25909 | // AArch64::FDUP_ZI_S - 160 |
| 25910 | {.AsmStrOffset: 2055, .AliasCondStart: 879, .NumOperands: 2, .NumConds: 5 }, |
| 25911 | // AArch64::GCSPOPM - 161 |
| 25912 | {.AsmStrOffset: 2071, .AliasCondStart: 884, .NumOperands: 2, .NumConds: 4 }, |
| 25913 | // AArch64::GLD1B_D_IMM - 162 |
| 25914 | {.AsmStrOffset: 2079, .AliasCondStart: 888, .NumOperands: 4, .NumConds: 7 }, |
| 25915 | // AArch64::GLD1B_S_IMM - 163 |
| 25916 | {.AsmStrOffset: 2105, .AliasCondStart: 895, .NumOperands: 4, .NumConds: 7 }, |
| 25917 | // AArch64::GLD1D_IMM - 164 |
| 25918 | {.AsmStrOffset: 2131, .AliasCondStart: 902, .NumOperands: 4, .NumConds: 7 }, |
| 25919 | // AArch64::GLD1H_D_IMM - 165 |
| 25920 | {.AsmStrOffset: 2157, .AliasCondStart: 909, .NumOperands: 4, .NumConds: 7 }, |
| 25921 | // AArch64::GLD1H_S_IMM - 166 |
| 25922 | {.AsmStrOffset: 2183, .AliasCondStart: 916, .NumOperands: 4, .NumConds: 7 }, |
| 25923 | // AArch64::GLD1Q - 167 |
| 25924 | {.AsmStrOffset: 2209, .AliasCondStart: 923, .NumOperands: 4, .NumConds: 7 }, |
| 25925 | // AArch64::GLD1SB_D_IMM - 168 |
| 25926 | {.AsmStrOffset: 2235, .AliasCondStart: 930, .NumOperands: 4, .NumConds: 7 }, |
| 25927 | // AArch64::GLD1SB_S_IMM - 169 |
| 25928 | {.AsmStrOffset: 2262, .AliasCondStart: 937, .NumOperands: 4, .NumConds: 7 }, |
| 25929 | // AArch64::GLD1SH_D_IMM - 170 |
| 25930 | {.AsmStrOffset: 2289, .AliasCondStart: 944, .NumOperands: 4, .NumConds: 7 }, |
| 25931 | // AArch64::GLD1SH_S_IMM - 171 |
| 25932 | {.AsmStrOffset: 2316, .AliasCondStart: 951, .NumOperands: 4, .NumConds: 7 }, |
| 25933 | // AArch64::GLD1SW_D_IMM - 172 |
| 25934 | {.AsmStrOffset: 2343, .AliasCondStart: 958, .NumOperands: 4, .NumConds: 7 }, |
| 25935 | // AArch64::GLD1W_D_IMM - 173 |
| 25936 | {.AsmStrOffset: 2370, .AliasCondStart: 965, .NumOperands: 4, .NumConds: 7 }, |
| 25937 | // AArch64::GLD1W_IMM - 174 |
| 25938 | {.AsmStrOffset: 2396, .AliasCondStart: 972, .NumOperands: 4, .NumConds: 7 }, |
| 25939 | // AArch64::GLDFF1B_D_IMM - 175 |
| 25940 | {.AsmStrOffset: 2422, .AliasCondStart: 979, .NumOperands: 4, .NumConds: 7 }, |
| 25941 | // AArch64::GLDFF1B_S_IMM - 176 |
| 25942 | {.AsmStrOffset: 2450, .AliasCondStart: 986, .NumOperands: 4, .NumConds: 7 }, |
| 25943 | // AArch64::GLDFF1D_IMM - 177 |
| 25944 | {.AsmStrOffset: 2478, .AliasCondStart: 993, .NumOperands: 4, .NumConds: 7 }, |
| 25945 | // AArch64::GLDFF1H_D_IMM - 178 |
| 25946 | {.AsmStrOffset: 2506, .AliasCondStart: 1000, .NumOperands: 4, .NumConds: 7 }, |
| 25947 | // AArch64::GLDFF1H_S_IMM - 179 |
| 25948 | {.AsmStrOffset: 2534, .AliasCondStart: 1007, .NumOperands: 4, .NumConds: 7 }, |
| 25949 | // AArch64::GLDFF1SB_D_IMM - 180 |
| 25950 | {.AsmStrOffset: 2562, .AliasCondStart: 1014, .NumOperands: 4, .NumConds: 7 }, |
| 25951 | // AArch64::GLDFF1SB_S_IMM - 181 |
| 25952 | {.AsmStrOffset: 2591, .AliasCondStart: 1021, .NumOperands: 4, .NumConds: 7 }, |
| 25953 | // AArch64::GLDFF1SH_D_IMM - 182 |
| 25954 | {.AsmStrOffset: 2620, .AliasCondStart: 1028, .NumOperands: 4, .NumConds: 7 }, |
| 25955 | // AArch64::GLDFF1SH_S_IMM - 183 |
| 25956 | {.AsmStrOffset: 2649, .AliasCondStart: 1035, .NumOperands: 4, .NumConds: 7 }, |
| 25957 | // AArch64::GLDFF1SW_D_IMM - 184 |
| 25958 | {.AsmStrOffset: 2678, .AliasCondStart: 1042, .NumOperands: 4, .NumConds: 7 }, |
| 25959 | // AArch64::GLDFF1W_D_IMM - 185 |
| 25960 | {.AsmStrOffset: 2707, .AliasCondStart: 1049, .NumOperands: 4, .NumConds: 7 }, |
| 25961 | // AArch64::GLDFF1W_IMM - 186 |
| 25962 | {.AsmStrOffset: 2735, .AliasCondStart: 1056, .NumOperands: 4, .NumConds: 7 }, |
| 25963 | // AArch64::HINT - 187 |
| 25964 | {.AsmStrOffset: 2763, .AliasCondStart: 1063, .NumOperands: 1, .NumConds: 1 }, |
| 25965 | {.AsmStrOffset: 2769, .AliasCondStart: 1064, .NumOperands: 1, .NumConds: 1 }, |
| 25966 | {.AsmStrOffset: 2773, .AliasCondStart: 1065, .NumOperands: 1, .NumConds: 1 }, |
| 25967 | {.AsmStrOffset: 2777, .AliasCondStart: 1066, .NumOperands: 1, .NumConds: 1 }, |
| 25968 | {.AsmStrOffset: 2781, .AliasCondStart: 1067, .NumOperands: 1, .NumConds: 1 }, |
| 25969 | {.AsmStrOffset: 2786, .AliasCondStart: 1068, .NumOperands: 1, .NumConds: 1 }, |
| 25970 | {.AsmStrOffset: 2790, .AliasCondStart: 1069, .NumOperands: 1, .NumConds: 4 }, |
| 25971 | {.AsmStrOffset: 2794, .AliasCondStart: 1073, .NumOperands: 1, .NumConds: 1 }, |
| 25972 | {.AsmStrOffset: 2799, .AliasCondStart: 1074, .NumOperands: 1, .NumConds: 4 }, |
| 25973 | {.AsmStrOffset: 2805, .AliasCondStart: 1078, .NumOperands: 1, .NumConds: 4 }, |
| 25974 | {.AsmStrOffset: 2809, .AliasCondStart: 1082, .NumOperands: 1, .NumConds: 4 }, |
| 25975 | {.AsmStrOffset: 2818, .AliasCondStart: 1086, .NumOperands: 1, .NumConds: 4 }, |
| 25976 | {.AsmStrOffset: 2827, .AliasCondStart: 1090, .NumOperands: 1, .NumConds: 4 }, |
| 25977 | {.AsmStrOffset: 2838, .AliasCondStart: 1094, .NumOperands: 1, .NumConds: 4 }, |
| 25978 | // AArch64::INCB_XPiI - 201 |
| 25979 | {.AsmStrOffset: 2845, .AliasCondStart: 1098, .NumOperands: 4, .NumConds: 8 }, |
| 25980 | {.AsmStrOffset: 2853, .AliasCondStart: 1106, .NumOperands: 4, .NumConds: 8 }, |
| 25981 | // AArch64::INCD_XPiI - 203 |
| 25982 | {.AsmStrOffset: 2867, .AliasCondStart: 1114, .NumOperands: 4, .NumConds: 8 }, |
| 25983 | {.AsmStrOffset: 2875, .AliasCondStart: 1122, .NumOperands: 4, .NumConds: 8 }, |
| 25984 | // AArch64::INCD_ZPiI - 205 |
| 25985 | {.AsmStrOffset: 2889, .AliasCondStart: 1130, .NumOperands: 4, .NumConds: 8 }, |
| 25986 | {.AsmStrOffset: 2899, .AliasCondStart: 1138, .NumOperands: 4, .NumConds: 8 }, |
| 25987 | // AArch64::INCH_XPiI - 207 |
| 25988 | {.AsmStrOffset: 2915, .AliasCondStart: 1146, .NumOperands: 4, .NumConds: 8 }, |
| 25989 | {.AsmStrOffset: 2923, .AliasCondStart: 1154, .NumOperands: 4, .NumConds: 8 }, |
| 25990 | // AArch64::INCH_ZPiI - 209 |
| 25991 | {.AsmStrOffset: 2937, .AliasCondStart: 1162, .NumOperands: 4, .NumConds: 8 }, |
| 25992 | {.AsmStrOffset: 2947, .AliasCondStart: 1170, .NumOperands: 4, .NumConds: 8 }, |
| 25993 | // AArch64::INCW_XPiI - 211 |
| 25994 | {.AsmStrOffset: 2963, .AliasCondStart: 1178, .NumOperands: 4, .NumConds: 8 }, |
| 25995 | {.AsmStrOffset: 2971, .AliasCondStart: 1186, .NumOperands: 4, .NumConds: 8 }, |
| 25996 | // AArch64::INCW_ZPiI - 213 |
| 25997 | {.AsmStrOffset: 2985, .AliasCondStart: 1194, .NumOperands: 4, .NumConds: 8 }, |
| 25998 | {.AsmStrOffset: 2995, .AliasCondStart: 1202, .NumOperands: 4, .NumConds: 8 }, |
| 25999 | // AArch64::INSERT_MXIPZ_H_B - 215 |
| 26000 | {.AsmStrOffset: 3011, .AliasCondStart: 1210, .NumOperands: 6, .NumConds: 9 }, |
| 26001 | // AArch64::INSERT_MXIPZ_H_D - 216 |
| 26002 | {.AsmStrOffset: 3044, .AliasCondStart: 1219, .NumOperands: 6, .NumConds: 9 }, |
| 26003 | // AArch64::INSERT_MXIPZ_H_H - 217 |
| 26004 | {.AsmStrOffset: 3077, .AliasCondStart: 1228, .NumOperands: 6, .NumConds: 9 }, |
| 26005 | // AArch64::INSERT_MXIPZ_H_Q - 218 |
| 26006 | {.AsmStrOffset: 3110, .AliasCondStart: 1237, .NumOperands: 6, .NumConds: 9 }, |
| 26007 | // AArch64::INSERT_MXIPZ_H_S - 219 |
| 26008 | {.AsmStrOffset: 3143, .AliasCondStart: 1246, .NumOperands: 6, .NumConds: 9 }, |
| 26009 | // AArch64::INSERT_MXIPZ_V_B - 220 |
| 26010 | {.AsmStrOffset: 3176, .AliasCondStart: 1255, .NumOperands: 6, .NumConds: 9 }, |
| 26011 | // AArch64::INSERT_MXIPZ_V_D - 221 |
| 26012 | {.AsmStrOffset: 3209, .AliasCondStart: 1264, .NumOperands: 6, .NumConds: 9 }, |
| 26013 | // AArch64::INSERT_MXIPZ_V_H - 222 |
| 26014 | {.AsmStrOffset: 3242, .AliasCondStart: 1273, .NumOperands: 6, .NumConds: 9 }, |
| 26015 | // AArch64::INSERT_MXIPZ_V_Q - 223 |
| 26016 | {.AsmStrOffset: 3275, .AliasCondStart: 1282, .NumOperands: 6, .NumConds: 9 }, |
| 26017 | // AArch64::INSERT_MXIPZ_V_S - 224 |
| 26018 | {.AsmStrOffset: 3308, .AliasCondStart: 1291, .NumOperands: 6, .NumConds: 9 }, |
| 26019 | // AArch64::INSvi16gpr - 225 |
| 26020 | {.AsmStrOffset: 3341, .AliasCondStart: 1300, .NumOperands: 4, .NumConds: 7 }, |
| 26021 | // AArch64::INSvi16lane - 226 |
| 26022 | {.AsmStrOffset: 3360, .AliasCondStart: 1307, .NumOperands: 5, .NumConds: 7 }, |
| 26023 | // AArch64::INSvi32gpr - 227 |
| 26024 | {.AsmStrOffset: 3387, .AliasCondStart: 1314, .NumOperands: 4, .NumConds: 7 }, |
| 26025 | // AArch64::INSvi32lane - 228 |
| 26026 | {.AsmStrOffset: 3406, .AliasCondStart: 1321, .NumOperands: 5, .NumConds: 7 }, |
| 26027 | // AArch64::INSvi64gpr - 229 |
| 26028 | {.AsmStrOffset: 3433, .AliasCondStart: 1328, .NumOperands: 4, .NumConds: 7 }, |
| 26029 | // AArch64::INSvi64lane - 230 |
| 26030 | {.AsmStrOffset: 3452, .AliasCondStart: 1335, .NumOperands: 5, .NumConds: 7 }, |
| 26031 | // AArch64::INSvi8gpr - 231 |
| 26032 | {.AsmStrOffset: 3479, .AliasCondStart: 1342, .NumOperands: 4, .NumConds: 7 }, |
| 26033 | // AArch64::INSvi8lane - 232 |
| 26034 | {.AsmStrOffset: 3498, .AliasCondStart: 1349, .NumOperands: 5, .NumConds: 7 }, |
| 26035 | // AArch64::IRG - 233 |
| 26036 | {.AsmStrOffset: 3525, .AliasCondStart: 1356, .NumOperands: 3, .NumConds: 6 }, |
| 26037 | // AArch64::ISB - 234 |
| 26038 | {.AsmStrOffset: 3536, .AliasCondStart: 1362, .NumOperands: 1, .NumConds: 1 }, |
| 26039 | // AArch64::LD1B_2Z_IMM - 235 |
| 26040 | {.AsmStrOffset: 3540, .AliasCondStart: 1363, .NumOperands: 4, .NumConds: 8 }, |
| 26041 | // AArch64::LD1B_2Z_STRIDED_IMM - 236 |
| 26042 | {.AsmStrOffset: 3564, .AliasCondStart: 1371, .NumOperands: 4, .NumConds: 7 }, |
| 26043 | // AArch64::LD1B_4Z_IMM - 237 |
| 26044 | {.AsmStrOffset: 3540, .AliasCondStart: 1378, .NumOperands: 4, .NumConds: 8 }, |
| 26045 | // AArch64::LD1B_4Z_STRIDED_IMM - 238 |
| 26046 | {.AsmStrOffset: 3588, .AliasCondStart: 1386, .NumOperands: 4, .NumConds: 7 }, |
| 26047 | // AArch64::LD1B_D_IMM - 239 |
| 26048 | {.AsmStrOffset: 3612, .AliasCondStart: 1393, .NumOperands: 4, .NumConds: 8 }, |
| 26049 | // AArch64::LD1B_H_IMM - 240 |
| 26050 | {.AsmStrOffset: 3636, .AliasCondStart: 1401, .NumOperands: 4, .NumConds: 8 }, |
| 26051 | // AArch64::LD1B_IMM - 241 |
| 26052 | {.AsmStrOffset: 3660, .AliasCondStart: 1409, .NumOperands: 4, .NumConds: 8 }, |
| 26053 | // AArch64::LD1B_S_IMM - 242 |
| 26054 | {.AsmStrOffset: 3684, .AliasCondStart: 1417, .NumOperands: 4, .NumConds: 8 }, |
| 26055 | // AArch64::LD1D_2Z_IMM - 243 |
| 26056 | {.AsmStrOffset: 3708, .AliasCondStart: 1425, .NumOperands: 4, .NumConds: 8 }, |
| 26057 | // AArch64::LD1D_2Z_STRIDED_IMM - 244 |
| 26058 | {.AsmStrOffset: 3732, .AliasCondStart: 1433, .NumOperands: 4, .NumConds: 7 }, |
| 26059 | // AArch64::LD1D_4Z_IMM - 245 |
| 26060 | {.AsmStrOffset: 3708, .AliasCondStart: 1440, .NumOperands: 4, .NumConds: 8 }, |
| 26061 | // AArch64::LD1D_4Z_STRIDED_IMM - 246 |
| 26062 | {.AsmStrOffset: 3732, .AliasCondStart: 1448, .NumOperands: 4, .NumConds: 7 }, |
| 26063 | // AArch64::LD1D_IMM - 247 |
| 26064 | {.AsmStrOffset: 3756, .AliasCondStart: 1455, .NumOperands: 4, .NumConds: 8 }, |
| 26065 | // AArch64::LD1D_Q_IMM - 248 |
| 26066 | {.AsmStrOffset: 3780, .AliasCondStart: 1463, .NumOperands: 4, .NumConds: 7 }, |
| 26067 | // AArch64::LD1Fourv16b_POST - 249 |
| 26068 | {.AsmStrOffset: 3804, .AliasCondStart: 1470, .NumOperands: 4, .NumConds: 7 }, |
| 26069 | // AArch64::LD1Fourv1d_POST - 250 |
| 26070 | {.AsmStrOffset: 3824, .AliasCondStart: 1477, .NumOperands: 4, .NumConds: 7 }, |
| 26071 | // AArch64::LD1Fourv2d_POST - 251 |
| 26072 | {.AsmStrOffset: 3844, .AliasCondStart: 1484, .NumOperands: 4, .NumConds: 7 }, |
| 26073 | // AArch64::LD1Fourv2s_POST - 252 |
| 26074 | {.AsmStrOffset: 3864, .AliasCondStart: 1491, .NumOperands: 4, .NumConds: 7 }, |
| 26075 | // AArch64::LD1Fourv4h_POST - 253 |
| 26076 | {.AsmStrOffset: 3884, .AliasCondStart: 1498, .NumOperands: 4, .NumConds: 7 }, |
| 26077 | // AArch64::LD1Fourv4s_POST - 254 |
| 26078 | {.AsmStrOffset: 3904, .AliasCondStart: 1505, .NumOperands: 4, .NumConds: 7 }, |
| 26079 | // AArch64::LD1Fourv8b_POST - 255 |
| 26080 | {.AsmStrOffset: 3924, .AliasCondStart: 1512, .NumOperands: 4, .NumConds: 7 }, |
| 26081 | // AArch64::LD1Fourv8h_POST - 256 |
| 26082 | {.AsmStrOffset: 3944, .AliasCondStart: 1519, .NumOperands: 4, .NumConds: 7 }, |
| 26083 | // AArch64::LD1H_2Z_IMM - 257 |
| 26084 | {.AsmStrOffset: 3964, .AliasCondStart: 1526, .NumOperands: 4, .NumConds: 8 }, |
| 26085 | // AArch64::LD1H_2Z_STRIDED_IMM - 258 |
| 26086 | {.AsmStrOffset: 3988, .AliasCondStart: 1534, .NumOperands: 4, .NumConds: 7 }, |
| 26087 | // AArch64::LD1H_4Z_IMM - 259 |
| 26088 | {.AsmStrOffset: 3964, .AliasCondStart: 1541, .NumOperands: 4, .NumConds: 8 }, |
| 26089 | // AArch64::LD1H_4Z_STRIDED_IMM - 260 |
| 26090 | {.AsmStrOffset: 4012, .AliasCondStart: 1549, .NumOperands: 4, .NumConds: 7 }, |
| 26091 | // AArch64::LD1H_D_IMM - 261 |
| 26092 | {.AsmStrOffset: 4036, .AliasCondStart: 1556, .NumOperands: 4, .NumConds: 8 }, |
| 26093 | // AArch64::LD1H_IMM - 262 |
| 26094 | {.AsmStrOffset: 4060, .AliasCondStart: 1564, .NumOperands: 4, .NumConds: 8 }, |
| 26095 | // AArch64::LD1H_S_IMM - 263 |
| 26096 | {.AsmStrOffset: 4084, .AliasCondStart: 1572, .NumOperands: 4, .NumConds: 8 }, |
| 26097 | // AArch64::LD1Onev16b_POST - 264 |
| 26098 | {.AsmStrOffset: 4108, .AliasCondStart: 1580, .NumOperands: 4, .NumConds: 7 }, |
| 26099 | // AArch64::LD1Onev1d_POST - 265 |
| 26100 | {.AsmStrOffset: 4128, .AliasCondStart: 1587, .NumOperands: 4, .NumConds: 7 }, |
| 26101 | // AArch64::LD1Onev2d_POST - 266 |
| 26102 | {.AsmStrOffset: 4147, .AliasCondStart: 1594, .NumOperands: 4, .NumConds: 7 }, |
| 26103 | // AArch64::LD1Onev2s_POST - 267 |
| 26104 | {.AsmStrOffset: 4167, .AliasCondStart: 1601, .NumOperands: 4, .NumConds: 7 }, |
| 26105 | // AArch64::LD1Onev4h_POST - 268 |
| 26106 | {.AsmStrOffset: 4186, .AliasCondStart: 1608, .NumOperands: 4, .NumConds: 7 }, |
| 26107 | // AArch64::LD1Onev4s_POST - 269 |
| 26108 | {.AsmStrOffset: 4205, .AliasCondStart: 1615, .NumOperands: 4, .NumConds: 7 }, |
| 26109 | // AArch64::LD1Onev8b_POST - 270 |
| 26110 | {.AsmStrOffset: 4225, .AliasCondStart: 1622, .NumOperands: 4, .NumConds: 7 }, |
| 26111 | // AArch64::LD1Onev8h_POST - 271 |
| 26112 | {.AsmStrOffset: 4244, .AliasCondStart: 1629, .NumOperands: 4, .NumConds: 7 }, |
| 26113 | // AArch64::LD1RB_D_IMM - 272 |
| 26114 | {.AsmStrOffset: 4264, .AliasCondStart: 1636, .NumOperands: 4, .NumConds: 8 }, |
| 26115 | // AArch64::LD1RB_H_IMM - 273 |
| 26116 | {.AsmStrOffset: 4289, .AliasCondStart: 1644, .NumOperands: 4, .NumConds: 8 }, |
| 26117 | // AArch64::LD1RB_IMM - 274 |
| 26118 | {.AsmStrOffset: 4314, .AliasCondStart: 1652, .NumOperands: 4, .NumConds: 8 }, |
| 26119 | // AArch64::LD1RB_S_IMM - 275 |
| 26120 | {.AsmStrOffset: 4339, .AliasCondStart: 1660, .NumOperands: 4, .NumConds: 8 }, |
| 26121 | // AArch64::LD1RD_IMM - 276 |
| 26122 | {.AsmStrOffset: 4364, .AliasCondStart: 1668, .NumOperands: 4, .NumConds: 8 }, |
| 26123 | // AArch64::LD1RH_D_IMM - 277 |
| 26124 | {.AsmStrOffset: 4389, .AliasCondStart: 1676, .NumOperands: 4, .NumConds: 8 }, |
| 26125 | // AArch64::LD1RH_IMM - 278 |
| 26126 | {.AsmStrOffset: 4414, .AliasCondStart: 1684, .NumOperands: 4, .NumConds: 8 }, |
| 26127 | // AArch64::LD1RH_S_IMM - 279 |
| 26128 | {.AsmStrOffset: 4439, .AliasCondStart: 1692, .NumOperands: 4, .NumConds: 8 }, |
| 26129 | // AArch64::LD1RO_B_IMM - 280 |
| 26130 | {.AsmStrOffset: 4464, .AliasCondStart: 1700, .NumOperands: 4, .NumConds: 10 }, |
| 26131 | // AArch64::LD1RO_D_IMM - 281 |
| 26132 | {.AsmStrOffset: 4490, .AliasCondStart: 1710, .NumOperands: 4, .NumConds: 10 }, |
| 26133 | // AArch64::LD1RO_H_IMM - 282 |
| 26134 | {.AsmStrOffset: 4516, .AliasCondStart: 1720, .NumOperands: 4, .NumConds: 10 }, |
| 26135 | // AArch64::LD1RO_W_IMM - 283 |
| 26136 | {.AsmStrOffset: 4542, .AliasCondStart: 1730, .NumOperands: 4, .NumConds: 10 }, |
| 26137 | // AArch64::LD1RQ_B_IMM - 284 |
| 26138 | {.AsmStrOffset: 4568, .AliasCondStart: 1740, .NumOperands: 4, .NumConds: 8 }, |
| 26139 | // AArch64::LD1RQ_D_IMM - 285 |
| 26140 | {.AsmStrOffset: 4594, .AliasCondStart: 1748, .NumOperands: 4, .NumConds: 8 }, |
| 26141 | // AArch64::LD1RQ_H_IMM - 286 |
| 26142 | {.AsmStrOffset: 4620, .AliasCondStart: 1756, .NumOperands: 4, .NumConds: 8 }, |
| 26143 | // AArch64::LD1RQ_W_IMM - 287 |
| 26144 | {.AsmStrOffset: 4646, .AliasCondStart: 1764, .NumOperands: 4, .NumConds: 8 }, |
| 26145 | // AArch64::LD1RSB_D_IMM - 288 |
| 26146 | {.AsmStrOffset: 4672, .AliasCondStart: 1772, .NumOperands: 4, .NumConds: 8 }, |
| 26147 | // AArch64::LD1RSB_H_IMM - 289 |
| 26148 | {.AsmStrOffset: 4698, .AliasCondStart: 1780, .NumOperands: 4, .NumConds: 8 }, |
| 26149 | // AArch64::LD1RSB_S_IMM - 290 |
| 26150 | {.AsmStrOffset: 4724, .AliasCondStart: 1788, .NumOperands: 4, .NumConds: 8 }, |
| 26151 | // AArch64::LD1RSH_D_IMM - 291 |
| 26152 | {.AsmStrOffset: 4750, .AliasCondStart: 1796, .NumOperands: 4, .NumConds: 8 }, |
| 26153 | // AArch64::LD1RSH_S_IMM - 292 |
| 26154 | {.AsmStrOffset: 4776, .AliasCondStart: 1804, .NumOperands: 4, .NumConds: 8 }, |
| 26155 | // AArch64::LD1RSW_IMM - 293 |
| 26156 | {.AsmStrOffset: 4802, .AliasCondStart: 1812, .NumOperands: 4, .NumConds: 8 }, |
| 26157 | // AArch64::LD1RW_D_IMM - 294 |
| 26158 | {.AsmStrOffset: 4828, .AliasCondStart: 1820, .NumOperands: 4, .NumConds: 8 }, |
| 26159 | // AArch64::LD1RW_IMM - 295 |
| 26160 | {.AsmStrOffset: 4853, .AliasCondStart: 1828, .NumOperands: 4, .NumConds: 8 }, |
| 26161 | // AArch64::LD1Rv16b_POST - 296 |
| 26162 | {.AsmStrOffset: 4878, .AliasCondStart: 1836, .NumOperands: 4, .NumConds: 7 }, |
| 26163 | // AArch64::LD1Rv1d_POST - 297 |
| 26164 | {.AsmStrOffset: 4898, .AliasCondStart: 1843, .NumOperands: 4, .NumConds: 7 }, |
| 26165 | // AArch64::LD1Rv2d_POST - 298 |
| 26166 | {.AsmStrOffset: 4918, .AliasCondStart: 1850, .NumOperands: 4, .NumConds: 7 }, |
| 26167 | // AArch64::LD1Rv2s_POST - 299 |
| 26168 | {.AsmStrOffset: 4938, .AliasCondStart: 1857, .NumOperands: 4, .NumConds: 7 }, |
| 26169 | // AArch64::LD1Rv4h_POST - 300 |
| 26170 | {.AsmStrOffset: 4958, .AliasCondStart: 1864, .NumOperands: 4, .NumConds: 7 }, |
| 26171 | // AArch64::LD1Rv4s_POST - 301 |
| 26172 | {.AsmStrOffset: 4978, .AliasCondStart: 1871, .NumOperands: 4, .NumConds: 7 }, |
| 26173 | // AArch64::LD1Rv8b_POST - 302 |
| 26174 | {.AsmStrOffset: 4998, .AliasCondStart: 1878, .NumOperands: 4, .NumConds: 7 }, |
| 26175 | // AArch64::LD1Rv8h_POST - 303 |
| 26176 | {.AsmStrOffset: 5018, .AliasCondStart: 1885, .NumOperands: 4, .NumConds: 7 }, |
| 26177 | // AArch64::LD1SB_D_IMM - 304 |
| 26178 | {.AsmStrOffset: 5038, .AliasCondStart: 1892, .NumOperands: 4, .NumConds: 8 }, |
| 26179 | // AArch64::LD1SB_H_IMM - 305 |
| 26180 | {.AsmStrOffset: 5063, .AliasCondStart: 1900, .NumOperands: 4, .NumConds: 8 }, |
| 26181 | // AArch64::LD1SB_S_IMM - 306 |
| 26182 | {.AsmStrOffset: 5088, .AliasCondStart: 1908, .NumOperands: 4, .NumConds: 8 }, |
| 26183 | // AArch64::LD1SH_D_IMM - 307 |
| 26184 | {.AsmStrOffset: 5113, .AliasCondStart: 1916, .NumOperands: 4, .NumConds: 8 }, |
| 26185 | // AArch64::LD1SH_S_IMM - 308 |
| 26186 | {.AsmStrOffset: 5138, .AliasCondStart: 1924, .NumOperands: 4, .NumConds: 8 }, |
| 26187 | // AArch64::LD1SW_D_IMM - 309 |
| 26188 | {.AsmStrOffset: 5163, .AliasCondStart: 1932, .NumOperands: 4, .NumConds: 8 }, |
| 26189 | // AArch64::LD1Threev16b_POST - 310 |
| 26190 | {.AsmStrOffset: 5188, .AliasCondStart: 1940, .NumOperands: 4, .NumConds: 7 }, |
| 26191 | // AArch64::LD1Threev1d_POST - 311 |
| 26192 | {.AsmStrOffset: 5208, .AliasCondStart: 1947, .NumOperands: 4, .NumConds: 7 }, |
| 26193 | // AArch64::LD1Threev2d_POST - 312 |
| 26194 | {.AsmStrOffset: 5228, .AliasCondStart: 1954, .NumOperands: 4, .NumConds: 7 }, |
| 26195 | // AArch64::LD1Threev2s_POST - 313 |
| 26196 | {.AsmStrOffset: 5248, .AliasCondStart: 1961, .NumOperands: 4, .NumConds: 7 }, |
| 26197 | // AArch64::LD1Threev4h_POST - 314 |
| 26198 | {.AsmStrOffset: 5268, .AliasCondStart: 1968, .NumOperands: 4, .NumConds: 7 }, |
| 26199 | // AArch64::LD1Threev4s_POST - 315 |
| 26200 | {.AsmStrOffset: 5288, .AliasCondStart: 1975, .NumOperands: 4, .NumConds: 7 }, |
| 26201 | // AArch64::LD1Threev8b_POST - 316 |
| 26202 | {.AsmStrOffset: 5308, .AliasCondStart: 1982, .NumOperands: 4, .NumConds: 7 }, |
| 26203 | // AArch64::LD1Threev8h_POST - 317 |
| 26204 | {.AsmStrOffset: 5328, .AliasCondStart: 1989, .NumOperands: 4, .NumConds: 7 }, |
| 26205 | // AArch64::LD1Twov16b_POST - 318 |
| 26206 | {.AsmStrOffset: 5348, .AliasCondStart: 1996, .NumOperands: 4, .NumConds: 7 }, |
| 26207 | // AArch64::LD1Twov1d_POST - 319 |
| 26208 | {.AsmStrOffset: 5368, .AliasCondStart: 2003, .NumOperands: 4, .NumConds: 7 }, |
| 26209 | // AArch64::LD1Twov2d_POST - 320 |
| 26210 | {.AsmStrOffset: 5388, .AliasCondStart: 2010, .NumOperands: 4, .NumConds: 7 }, |
| 26211 | // AArch64::LD1Twov2s_POST - 321 |
| 26212 | {.AsmStrOffset: 5408, .AliasCondStart: 2017, .NumOperands: 4, .NumConds: 7 }, |
| 26213 | // AArch64::LD1Twov4h_POST - 322 |
| 26214 | {.AsmStrOffset: 5428, .AliasCondStart: 2024, .NumOperands: 4, .NumConds: 7 }, |
| 26215 | // AArch64::LD1Twov4s_POST - 323 |
| 26216 | {.AsmStrOffset: 5448, .AliasCondStart: 2031, .NumOperands: 4, .NumConds: 7 }, |
| 26217 | // AArch64::LD1Twov8b_POST - 324 |
| 26218 | {.AsmStrOffset: 5468, .AliasCondStart: 2038, .NumOperands: 4, .NumConds: 7 }, |
| 26219 | // AArch64::LD1Twov8h_POST - 325 |
| 26220 | {.AsmStrOffset: 5488, .AliasCondStart: 2045, .NumOperands: 4, .NumConds: 7 }, |
| 26221 | // AArch64::LD1W_2Z_IMM - 326 |
| 26222 | {.AsmStrOffset: 5508, .AliasCondStart: 2052, .NumOperands: 4, .NumConds: 8 }, |
| 26223 | // AArch64::LD1W_2Z_STRIDED_IMM - 327 |
| 26224 | {.AsmStrOffset: 5532, .AliasCondStart: 2060, .NumOperands: 4, .NumConds: 7 }, |
| 26225 | // AArch64::LD1W_4Z_IMM - 328 |
| 26226 | {.AsmStrOffset: 5508, .AliasCondStart: 2067, .NumOperands: 4, .NumConds: 8 }, |
| 26227 | // AArch64::LD1W_4Z_STRIDED_IMM - 329 |
| 26228 | {.AsmStrOffset: 5532, .AliasCondStart: 2075, .NumOperands: 4, .NumConds: 7 }, |
| 26229 | // AArch64::LD1W_D_IMM - 330 |
| 26230 | {.AsmStrOffset: 5556, .AliasCondStart: 2082, .NumOperands: 4, .NumConds: 8 }, |
| 26231 | // AArch64::LD1W_IMM - 331 |
| 26232 | {.AsmStrOffset: 5580, .AliasCondStart: 2090, .NumOperands: 4, .NumConds: 8 }, |
| 26233 | // AArch64::LD1W_Q_IMM - 332 |
| 26234 | {.AsmStrOffset: 5604, .AliasCondStart: 2098, .NumOperands: 4, .NumConds: 7 }, |
| 26235 | // AArch64::LD1_MXIPXX_H_B - 333 |
| 26236 | {.AsmStrOffset: 5628, .AliasCondStart: 2105, .NumOperands: 6, .NumConds: 9 }, |
| 26237 | // AArch64::LD1_MXIPXX_H_D - 334 |
| 26238 | {.AsmStrOffset: 5664, .AliasCondStart: 2114, .NumOperands: 6, .NumConds: 9 }, |
| 26239 | // AArch64::LD1_MXIPXX_H_H - 335 |
| 26240 | {.AsmStrOffset: 5700, .AliasCondStart: 2123, .NumOperands: 6, .NumConds: 9 }, |
| 26241 | // AArch64::LD1_MXIPXX_H_Q - 336 |
| 26242 | {.AsmStrOffset: 5736, .AliasCondStart: 2132, .NumOperands: 6, .NumConds: 9 }, |
| 26243 | // AArch64::LD1_MXIPXX_H_S - 337 |
| 26244 | {.AsmStrOffset: 5772, .AliasCondStart: 2141, .NumOperands: 6, .NumConds: 9 }, |
| 26245 | // AArch64::LD1_MXIPXX_V_B - 338 |
| 26246 | {.AsmStrOffset: 5808, .AliasCondStart: 2150, .NumOperands: 6, .NumConds: 9 }, |
| 26247 | // AArch64::LD1_MXIPXX_V_D - 339 |
| 26248 | {.AsmStrOffset: 5844, .AliasCondStart: 2159, .NumOperands: 6, .NumConds: 9 }, |
| 26249 | // AArch64::LD1_MXIPXX_V_H - 340 |
| 26250 | {.AsmStrOffset: 5880, .AliasCondStart: 2168, .NumOperands: 6, .NumConds: 9 }, |
| 26251 | // AArch64::LD1_MXIPXX_V_Q - 341 |
| 26252 | {.AsmStrOffset: 5916, .AliasCondStart: 2177, .NumOperands: 6, .NumConds: 9 }, |
| 26253 | // AArch64::LD1_MXIPXX_V_S - 342 |
| 26254 | {.AsmStrOffset: 5952, .AliasCondStart: 2186, .NumOperands: 6, .NumConds: 9 }, |
| 26255 | // AArch64::LD1i16_POST - 343 |
| 26256 | {.AsmStrOffset: 5988, .AliasCondStart: 2195, .NumOperands: 6, .NumConds: 9 }, |
| 26257 | // AArch64::LD1i32_POST - 344 |
| 26258 | {.AsmStrOffset: 6011, .AliasCondStart: 2204, .NumOperands: 6, .NumConds: 9 }, |
| 26259 | // AArch64::LD1i64_POST - 345 |
| 26260 | {.AsmStrOffset: 6034, .AliasCondStart: 2213, .NumOperands: 6, .NumConds: 9 }, |
| 26261 | // AArch64::LD1i8_POST - 346 |
| 26262 | {.AsmStrOffset: 6057, .AliasCondStart: 2222, .NumOperands: 6, .NumConds: 9 }, |
| 26263 | // AArch64::LD2B_IMM - 347 |
| 26264 | {.AsmStrOffset: 6080, .AliasCondStart: 2231, .NumOperands: 4, .NumConds: 8 }, |
| 26265 | // AArch64::LD2D_IMM - 348 |
| 26266 | {.AsmStrOffset: 6104, .AliasCondStart: 2239, .NumOperands: 4, .NumConds: 8 }, |
| 26267 | // AArch64::LD2H_IMM - 349 |
| 26268 | {.AsmStrOffset: 6128, .AliasCondStart: 2247, .NumOperands: 4, .NumConds: 8 }, |
| 26269 | // AArch64::LD2Q_IMM - 350 |
| 26270 | {.AsmStrOffset: 6152, .AliasCondStart: 2255, .NumOperands: 4, .NumConds: 8 }, |
| 26271 | // AArch64::LD2Rv16b_POST - 351 |
| 26272 | {.AsmStrOffset: 6176, .AliasCondStart: 2263, .NumOperands: 4, .NumConds: 7 }, |
| 26273 | // AArch64::LD2Rv1d_POST - 352 |
| 26274 | {.AsmStrOffset: 6196, .AliasCondStart: 2270, .NumOperands: 4, .NumConds: 7 }, |
| 26275 | // AArch64::LD2Rv2d_POST - 353 |
| 26276 | {.AsmStrOffset: 6217, .AliasCondStart: 2277, .NumOperands: 4, .NumConds: 7 }, |
| 26277 | // AArch64::LD2Rv2s_POST - 354 |
| 26278 | {.AsmStrOffset: 6238, .AliasCondStart: 2284, .NumOperands: 4, .NumConds: 7 }, |
| 26279 | // AArch64::LD2Rv4h_POST - 355 |
| 26280 | {.AsmStrOffset: 6258, .AliasCondStart: 2291, .NumOperands: 4, .NumConds: 7 }, |
| 26281 | // AArch64::LD2Rv4s_POST - 356 |
| 26282 | {.AsmStrOffset: 6278, .AliasCondStart: 2298, .NumOperands: 4, .NumConds: 7 }, |
| 26283 | // AArch64::LD2Rv8b_POST - 357 |
| 26284 | {.AsmStrOffset: 6298, .AliasCondStart: 2305, .NumOperands: 4, .NumConds: 7 }, |
| 26285 | // AArch64::LD2Rv8h_POST - 358 |
| 26286 | {.AsmStrOffset: 6318, .AliasCondStart: 2312, .NumOperands: 4, .NumConds: 7 }, |
| 26287 | // AArch64::LD2Twov16b_POST - 359 |
| 26288 | {.AsmStrOffset: 6338, .AliasCondStart: 2319, .NumOperands: 4, .NumConds: 7 }, |
| 26289 | // AArch64::LD2Twov2d_POST - 360 |
| 26290 | {.AsmStrOffset: 6358, .AliasCondStart: 2326, .NumOperands: 4, .NumConds: 7 }, |
| 26291 | // AArch64::LD2Twov2s_POST - 361 |
| 26292 | {.AsmStrOffset: 6378, .AliasCondStart: 2333, .NumOperands: 4, .NumConds: 7 }, |
| 26293 | // AArch64::LD2Twov4h_POST - 362 |
| 26294 | {.AsmStrOffset: 6398, .AliasCondStart: 2340, .NumOperands: 4, .NumConds: 7 }, |
| 26295 | // AArch64::LD2Twov4s_POST - 363 |
| 26296 | {.AsmStrOffset: 6418, .AliasCondStart: 2347, .NumOperands: 4, .NumConds: 7 }, |
| 26297 | // AArch64::LD2Twov8b_POST - 364 |
| 26298 | {.AsmStrOffset: 6438, .AliasCondStart: 2354, .NumOperands: 4, .NumConds: 7 }, |
| 26299 | // AArch64::LD2Twov8h_POST - 365 |
| 26300 | {.AsmStrOffset: 6458, .AliasCondStart: 2361, .NumOperands: 4, .NumConds: 7 }, |
| 26301 | // AArch64::LD2W_IMM - 366 |
| 26302 | {.AsmStrOffset: 6478, .AliasCondStart: 2368, .NumOperands: 4, .NumConds: 8 }, |
| 26303 | // AArch64::LD2i16_POST - 367 |
| 26304 | {.AsmStrOffset: 6502, .AliasCondStart: 2376, .NumOperands: 6, .NumConds: 9 }, |
| 26305 | // AArch64::LD2i32_POST - 368 |
| 26306 | {.AsmStrOffset: 6525, .AliasCondStart: 2385, .NumOperands: 6, .NumConds: 9 }, |
| 26307 | // AArch64::LD2i64_POST - 369 |
| 26308 | {.AsmStrOffset: 6548, .AliasCondStart: 2394, .NumOperands: 6, .NumConds: 9 }, |
| 26309 | // AArch64::LD2i8_POST - 370 |
| 26310 | {.AsmStrOffset: 6572, .AliasCondStart: 2403, .NumOperands: 6, .NumConds: 9 }, |
| 26311 | // AArch64::LD3B_IMM - 371 |
| 26312 | {.AsmStrOffset: 6595, .AliasCondStart: 2412, .NumOperands: 4, .NumConds: 8 }, |
| 26313 | // AArch64::LD3D_IMM - 372 |
| 26314 | {.AsmStrOffset: 6619, .AliasCondStart: 2420, .NumOperands: 4, .NumConds: 8 }, |
| 26315 | // AArch64::LD3H_IMM - 373 |
| 26316 | {.AsmStrOffset: 6643, .AliasCondStart: 2428, .NumOperands: 4, .NumConds: 8 }, |
| 26317 | // AArch64::LD3Q_IMM - 374 |
| 26318 | {.AsmStrOffset: 6667, .AliasCondStart: 2436, .NumOperands: 4, .NumConds: 8 }, |
| 26319 | // AArch64::LD3Rv16b_POST - 375 |
| 26320 | {.AsmStrOffset: 6691, .AliasCondStart: 2444, .NumOperands: 4, .NumConds: 7 }, |
| 26321 | // AArch64::LD3Rv1d_POST - 376 |
| 26322 | {.AsmStrOffset: 6711, .AliasCondStart: 2451, .NumOperands: 4, .NumConds: 7 }, |
| 26323 | // AArch64::LD3Rv2d_POST - 377 |
| 26324 | {.AsmStrOffset: 6732, .AliasCondStart: 2458, .NumOperands: 4, .NumConds: 7 }, |
| 26325 | // AArch64::LD3Rv2s_POST - 378 |
| 26326 | {.AsmStrOffset: 6753, .AliasCondStart: 2465, .NumOperands: 4, .NumConds: 7 }, |
| 26327 | // AArch64::LD3Rv4h_POST - 379 |
| 26328 | {.AsmStrOffset: 6774, .AliasCondStart: 2472, .NumOperands: 4, .NumConds: 7 }, |
| 26329 | // AArch64::LD3Rv4s_POST - 380 |
| 26330 | {.AsmStrOffset: 6794, .AliasCondStart: 2479, .NumOperands: 4, .NumConds: 7 }, |
| 26331 | // AArch64::LD3Rv8b_POST - 381 |
| 26332 | {.AsmStrOffset: 6815, .AliasCondStart: 2486, .NumOperands: 4, .NumConds: 7 }, |
| 26333 | // AArch64::LD3Rv8h_POST - 382 |
| 26334 | {.AsmStrOffset: 6835, .AliasCondStart: 2493, .NumOperands: 4, .NumConds: 7 }, |
| 26335 | // AArch64::LD3Threev16b_POST - 383 |
| 26336 | {.AsmStrOffset: 6855, .AliasCondStart: 2500, .NumOperands: 4, .NumConds: 7 }, |
| 26337 | // AArch64::LD3Threev2d_POST - 384 |
| 26338 | {.AsmStrOffset: 6875, .AliasCondStart: 2507, .NumOperands: 4, .NumConds: 7 }, |
| 26339 | // AArch64::LD3Threev2s_POST - 385 |
| 26340 | {.AsmStrOffset: 6895, .AliasCondStart: 2514, .NumOperands: 4, .NumConds: 7 }, |
| 26341 | // AArch64::LD3Threev4h_POST - 386 |
| 26342 | {.AsmStrOffset: 6915, .AliasCondStart: 2521, .NumOperands: 4, .NumConds: 7 }, |
| 26343 | // AArch64::LD3Threev4s_POST - 387 |
| 26344 | {.AsmStrOffset: 6935, .AliasCondStart: 2528, .NumOperands: 4, .NumConds: 7 }, |
| 26345 | // AArch64::LD3Threev8b_POST - 388 |
| 26346 | {.AsmStrOffset: 6955, .AliasCondStart: 2535, .NumOperands: 4, .NumConds: 7 }, |
| 26347 | // AArch64::LD3Threev8h_POST - 389 |
| 26348 | {.AsmStrOffset: 6975, .AliasCondStart: 2542, .NumOperands: 4, .NumConds: 7 }, |
| 26349 | // AArch64::LD3W_IMM - 390 |
| 26350 | {.AsmStrOffset: 6995, .AliasCondStart: 2549, .NumOperands: 4, .NumConds: 8 }, |
| 26351 | // AArch64::LD3i16_POST - 391 |
| 26352 | {.AsmStrOffset: 7019, .AliasCondStart: 2557, .NumOperands: 6, .NumConds: 9 }, |
| 26353 | // AArch64::LD3i32_POST - 392 |
| 26354 | {.AsmStrOffset: 7042, .AliasCondStart: 2566, .NumOperands: 6, .NumConds: 9 }, |
| 26355 | // AArch64::LD3i64_POST - 393 |
| 26356 | {.AsmStrOffset: 7066, .AliasCondStart: 2575, .NumOperands: 6, .NumConds: 9 }, |
| 26357 | // AArch64::LD3i8_POST - 394 |
| 26358 | {.AsmStrOffset: 7090, .AliasCondStart: 2584, .NumOperands: 6, .NumConds: 9 }, |
| 26359 | // AArch64::LD4B_IMM - 395 |
| 26360 | {.AsmStrOffset: 7113, .AliasCondStart: 2593, .NumOperands: 4, .NumConds: 8 }, |
| 26361 | // AArch64::LD4D_IMM - 396 |
| 26362 | {.AsmStrOffset: 7137, .AliasCondStart: 2601, .NumOperands: 4, .NumConds: 8 }, |
| 26363 | // AArch64::LD4Fourv16b_POST - 397 |
| 26364 | {.AsmStrOffset: 7161, .AliasCondStart: 2609, .NumOperands: 4, .NumConds: 7 }, |
| 26365 | // AArch64::LD4Fourv2d_POST - 398 |
| 26366 | {.AsmStrOffset: 7181, .AliasCondStart: 2616, .NumOperands: 4, .NumConds: 7 }, |
| 26367 | // AArch64::LD4Fourv2s_POST - 399 |
| 26368 | {.AsmStrOffset: 7201, .AliasCondStart: 2623, .NumOperands: 4, .NumConds: 7 }, |
| 26369 | // AArch64::LD4Fourv4h_POST - 400 |
| 26370 | {.AsmStrOffset: 7221, .AliasCondStart: 2630, .NumOperands: 4, .NumConds: 7 }, |
| 26371 | // AArch64::LD4Fourv4s_POST - 401 |
| 26372 | {.AsmStrOffset: 7241, .AliasCondStart: 2637, .NumOperands: 4, .NumConds: 7 }, |
| 26373 | // AArch64::LD4Fourv8b_POST - 402 |
| 26374 | {.AsmStrOffset: 7261, .AliasCondStart: 2644, .NumOperands: 4, .NumConds: 7 }, |
| 26375 | // AArch64::LD4Fourv8h_POST - 403 |
| 26376 | {.AsmStrOffset: 7281, .AliasCondStart: 2651, .NumOperands: 4, .NumConds: 7 }, |
| 26377 | // AArch64::LD4H_IMM - 404 |
| 26378 | {.AsmStrOffset: 7301, .AliasCondStart: 2658, .NumOperands: 4, .NumConds: 8 }, |
| 26379 | // AArch64::LD4Q_IMM - 405 |
| 26380 | {.AsmStrOffset: 7325, .AliasCondStart: 2666, .NumOperands: 4, .NumConds: 8 }, |
| 26381 | // AArch64::LD4Rv16b_POST - 406 |
| 26382 | {.AsmStrOffset: 7349, .AliasCondStart: 2674, .NumOperands: 4, .NumConds: 7 }, |
| 26383 | // AArch64::LD4Rv1d_POST - 407 |
| 26384 | {.AsmStrOffset: 7369, .AliasCondStart: 2681, .NumOperands: 4, .NumConds: 7 }, |
| 26385 | // AArch64::LD4Rv2d_POST - 408 |
| 26386 | {.AsmStrOffset: 7390, .AliasCondStart: 2688, .NumOperands: 4, .NumConds: 7 }, |
| 26387 | // AArch64::LD4Rv2s_POST - 409 |
| 26388 | {.AsmStrOffset: 7411, .AliasCondStart: 2695, .NumOperands: 4, .NumConds: 7 }, |
| 26389 | // AArch64::LD4Rv4h_POST - 410 |
| 26390 | {.AsmStrOffset: 7432, .AliasCondStart: 2702, .NumOperands: 4, .NumConds: 7 }, |
| 26391 | // AArch64::LD4Rv4s_POST - 411 |
| 26392 | {.AsmStrOffset: 7452, .AliasCondStart: 2709, .NumOperands: 4, .NumConds: 7 }, |
| 26393 | // AArch64::LD4Rv8b_POST - 412 |
| 26394 | {.AsmStrOffset: 7473, .AliasCondStart: 2716, .NumOperands: 4, .NumConds: 7 }, |
| 26395 | // AArch64::LD4Rv8h_POST - 413 |
| 26396 | {.AsmStrOffset: 7493, .AliasCondStart: 2723, .NumOperands: 4, .NumConds: 7 }, |
| 26397 | // AArch64::LD4W_IMM - 414 |
| 26398 | {.AsmStrOffset: 7513, .AliasCondStart: 2730, .NumOperands: 4, .NumConds: 8 }, |
| 26399 | // AArch64::LD4i16_POST - 415 |
| 26400 | {.AsmStrOffset: 7537, .AliasCondStart: 2738, .NumOperands: 6, .NumConds: 9 }, |
| 26401 | // AArch64::LD4i32_POST - 416 |
| 26402 | {.AsmStrOffset: 7560, .AliasCondStart: 2747, .NumOperands: 6, .NumConds: 9 }, |
| 26403 | // AArch64::LD4i64_POST - 417 |
| 26404 | {.AsmStrOffset: 7584, .AliasCondStart: 2756, .NumOperands: 6, .NumConds: 9 }, |
| 26405 | // AArch64::LD4i8_POST - 418 |
| 26406 | {.AsmStrOffset: 7608, .AliasCondStart: 2765, .NumOperands: 6, .NumConds: 9 }, |
| 26407 | // AArch64::LDADDB - 419 |
| 26408 | {.AsmStrOffset: 7631, .AliasCondStart: 2774, .NumOperands: 3, .NumConds: 6 }, |
| 26409 | // AArch64::LDADDH - 420 |
| 26410 | {.AsmStrOffset: 7647, .AliasCondStart: 2780, .NumOperands: 3, .NumConds: 6 }, |
| 26411 | // AArch64::LDADDLB - 421 |
| 26412 | {.AsmStrOffset: 7663, .AliasCondStart: 2786, .NumOperands: 3, .NumConds: 6 }, |
| 26413 | // AArch64::LDADDLH - 422 |
| 26414 | {.AsmStrOffset: 7680, .AliasCondStart: 2792, .NumOperands: 3, .NumConds: 6 }, |
| 26415 | // AArch64::LDADDLW - 423 |
| 26416 | {.AsmStrOffset: 7697, .AliasCondStart: 2798, .NumOperands: 3, .NumConds: 6 }, |
| 26417 | // AArch64::LDADDLX - 424 |
| 26418 | {.AsmStrOffset: 7697, .AliasCondStart: 2804, .NumOperands: 3, .NumConds: 6 }, |
| 26419 | // AArch64::LDADDW - 425 |
| 26420 | {.AsmStrOffset: 7713, .AliasCondStart: 2810, .NumOperands: 3, .NumConds: 6 }, |
| 26421 | // AArch64::LDADDX - 426 |
| 26422 | {.AsmStrOffset: 7713, .AliasCondStart: 2816, .NumOperands: 3, .NumConds: 6 }, |
| 26423 | // AArch64::LDAPPi - 427 |
| 26424 | {.AsmStrOffset: 7728, .AliasCondStart: 2822, .NumOperands: 3, .NumConds: 6 }, |
| 26425 | // AArch64::LDAPURBi - 428 |
| 26426 | {.AsmStrOffset: 7747, .AliasCondStart: 2828, .NumOperands: 3, .NumConds: 6 }, |
| 26427 | // AArch64::LDAPURHi - 429 |
| 26428 | {.AsmStrOffset: 7764, .AliasCondStart: 2834, .NumOperands: 3, .NumConds: 6 }, |
| 26429 | // AArch64::LDAPURSBWi - 430 |
| 26430 | {.AsmStrOffset: 7781, .AliasCondStart: 2840, .NumOperands: 3, .NumConds: 6 }, |
| 26431 | // AArch64::LDAPURSBXi - 431 |
| 26432 | {.AsmStrOffset: 7781, .AliasCondStart: 2846, .NumOperands: 3, .NumConds: 6 }, |
| 26433 | // AArch64::LDAPURSHWi - 432 |
| 26434 | {.AsmStrOffset: 7799, .AliasCondStart: 2852, .NumOperands: 3, .NumConds: 6 }, |
| 26435 | // AArch64::LDAPURSHXi - 433 |
| 26436 | {.AsmStrOffset: 7799, .AliasCondStart: 2858, .NumOperands: 3, .NumConds: 6 }, |
| 26437 | // AArch64::LDAPURSWi - 434 |
| 26438 | {.AsmStrOffset: 7817, .AliasCondStart: 2864, .NumOperands: 3, .NumConds: 6 }, |
| 26439 | // AArch64::LDAPURXi - 435 |
| 26440 | {.AsmStrOffset: 7835, .AliasCondStart: 2870, .NumOperands: 3, .NumConds: 6 }, |
| 26441 | // AArch64::LDAPURbi - 436 |
| 26442 | {.AsmStrOffset: 7835, .AliasCondStart: 2876, .NumOperands: 3, .NumConds: 9 }, |
| 26443 | // AArch64::LDAPURdi - 437 |
| 26444 | {.AsmStrOffset: 7835, .AliasCondStart: 2885, .NumOperands: 3, .NumConds: 9 }, |
| 26445 | // AArch64::LDAPURhi - 438 |
| 26446 | {.AsmStrOffset: 7835, .AliasCondStart: 2894, .NumOperands: 3, .NumConds: 9 }, |
| 26447 | // AArch64::LDAPURi - 439 |
| 26448 | {.AsmStrOffset: 7835, .AliasCondStart: 2903, .NumOperands: 3, .NumConds: 6 }, |
| 26449 | // AArch64::LDAPURqi - 440 |
| 26450 | {.AsmStrOffset: 7835, .AliasCondStart: 2909, .NumOperands: 3, .NumConds: 9 }, |
| 26451 | // AArch64::LDAPURsi - 441 |
| 26452 | {.AsmStrOffset: 7835, .AliasCondStart: 2918, .NumOperands: 3, .NumConds: 9 }, |
| 26453 | // AArch64::LDAPi - 442 |
| 26454 | {.AsmStrOffset: 7851, .AliasCondStart: 2927, .NumOperands: 3, .NumConds: 6 }, |
| 26455 | // AArch64::LDCLRB - 443 |
| 26456 | {.AsmStrOffset: 7869, .AliasCondStart: 2933, .NumOperands: 3, .NumConds: 6 }, |
| 26457 | // AArch64::LDCLRH - 444 |
| 26458 | {.AsmStrOffset: 7885, .AliasCondStart: 2939, .NumOperands: 3, .NumConds: 6 }, |
| 26459 | // AArch64::LDCLRLB - 445 |
| 26460 | {.AsmStrOffset: 7901, .AliasCondStart: 2945, .NumOperands: 3, .NumConds: 6 }, |
| 26461 | // AArch64::LDCLRLH - 446 |
| 26462 | {.AsmStrOffset: 7918, .AliasCondStart: 2951, .NumOperands: 3, .NumConds: 6 }, |
| 26463 | // AArch64::LDCLRLW - 447 |
| 26464 | {.AsmStrOffset: 7935, .AliasCondStart: 2957, .NumOperands: 3, .NumConds: 6 }, |
| 26465 | // AArch64::LDCLRLX - 448 |
| 26466 | {.AsmStrOffset: 7935, .AliasCondStart: 2963, .NumOperands: 3, .NumConds: 6 }, |
| 26467 | // AArch64::LDCLRW - 449 |
| 26468 | {.AsmStrOffset: 7951, .AliasCondStart: 2969, .NumOperands: 3, .NumConds: 6 }, |
| 26469 | // AArch64::LDCLRX - 450 |
| 26470 | {.AsmStrOffset: 7951, .AliasCondStart: 2975, .NumOperands: 3, .NumConds: 6 }, |
| 26471 | // AArch64::LDEORB - 451 |
| 26472 | {.AsmStrOffset: 7966, .AliasCondStart: 2981, .NumOperands: 3, .NumConds: 6 }, |
| 26473 | // AArch64::LDEORH - 452 |
| 26474 | {.AsmStrOffset: 7982, .AliasCondStart: 2987, .NumOperands: 3, .NumConds: 6 }, |
| 26475 | // AArch64::LDEORLB - 453 |
| 26476 | {.AsmStrOffset: 7998, .AliasCondStart: 2993, .NumOperands: 3, .NumConds: 6 }, |
| 26477 | // AArch64::LDEORLH - 454 |
| 26478 | {.AsmStrOffset: 8015, .AliasCondStart: 2999, .NumOperands: 3, .NumConds: 6 }, |
| 26479 | // AArch64::LDEORLW - 455 |
| 26480 | {.AsmStrOffset: 8032, .AliasCondStart: 3005, .NumOperands: 3, .NumConds: 6 }, |
| 26481 | // AArch64::LDEORLX - 456 |
| 26482 | {.AsmStrOffset: 8032, .AliasCondStart: 3011, .NumOperands: 3, .NumConds: 6 }, |
| 26483 | // AArch64::LDEORW - 457 |
| 26484 | {.AsmStrOffset: 8048, .AliasCondStart: 3017, .NumOperands: 3, .NumConds: 6 }, |
| 26485 | // AArch64::LDEORX - 458 |
| 26486 | {.AsmStrOffset: 8048, .AliasCondStart: 3023, .NumOperands: 3, .NumConds: 6 }, |
| 26487 | // AArch64::LDFF1B - 459 |
| 26488 | {.AsmStrOffset: 8063, .AliasCondStart: 3029, .NumOperands: 4, .NumConds: 7 }, |
| 26489 | // AArch64::LDFF1B_D - 460 |
| 26490 | {.AsmStrOffset: 8089, .AliasCondStart: 3036, .NumOperands: 4, .NumConds: 7 }, |
| 26491 | // AArch64::LDFF1B_H - 461 |
| 26492 | {.AsmStrOffset: 8115, .AliasCondStart: 3043, .NumOperands: 4, .NumConds: 7 }, |
| 26493 | // AArch64::LDFF1B_S - 462 |
| 26494 | {.AsmStrOffset: 8141, .AliasCondStart: 3050, .NumOperands: 4, .NumConds: 7 }, |
| 26495 | // AArch64::LDFF1D - 463 |
| 26496 | {.AsmStrOffset: 8167, .AliasCondStart: 3057, .NumOperands: 4, .NumConds: 7 }, |
| 26497 | // AArch64::LDFF1H - 464 |
| 26498 | {.AsmStrOffset: 8193, .AliasCondStart: 3064, .NumOperands: 4, .NumConds: 7 }, |
| 26499 | // AArch64::LDFF1H_D - 465 |
| 26500 | {.AsmStrOffset: 8219, .AliasCondStart: 3071, .NumOperands: 4, .NumConds: 7 }, |
| 26501 | // AArch64::LDFF1H_S - 466 |
| 26502 | {.AsmStrOffset: 8245, .AliasCondStart: 3078, .NumOperands: 4, .NumConds: 7 }, |
| 26503 | // AArch64::LDFF1SB_D - 467 |
| 26504 | {.AsmStrOffset: 8271, .AliasCondStart: 3085, .NumOperands: 4, .NumConds: 7 }, |
| 26505 | // AArch64::LDFF1SB_H - 468 |
| 26506 | {.AsmStrOffset: 8298, .AliasCondStart: 3092, .NumOperands: 4, .NumConds: 7 }, |
| 26507 | // AArch64::LDFF1SB_S - 469 |
| 26508 | {.AsmStrOffset: 8325, .AliasCondStart: 3099, .NumOperands: 4, .NumConds: 7 }, |
| 26509 | // AArch64::LDFF1SH_D - 470 |
| 26510 | {.AsmStrOffset: 8352, .AliasCondStart: 3106, .NumOperands: 4, .NumConds: 7 }, |
| 26511 | // AArch64::LDFF1SH_S - 471 |
| 26512 | {.AsmStrOffset: 8379, .AliasCondStart: 3113, .NumOperands: 4, .NumConds: 7 }, |
| 26513 | // AArch64::LDFF1SW_D - 472 |
| 26514 | {.AsmStrOffset: 8406, .AliasCondStart: 3120, .NumOperands: 4, .NumConds: 7 }, |
| 26515 | // AArch64::LDFF1W - 473 |
| 26516 | {.AsmStrOffset: 8433, .AliasCondStart: 3127, .NumOperands: 4, .NumConds: 7 }, |
| 26517 | // AArch64::LDFF1W_D - 474 |
| 26518 | {.AsmStrOffset: 8459, .AliasCondStart: 3134, .NumOperands: 4, .NumConds: 7 }, |
| 26519 | // AArch64::LDG - 475 |
| 26520 | {.AsmStrOffset: 8485, .AliasCondStart: 3141, .NumOperands: 4, .NumConds: 7 }, |
| 26521 | // AArch64::LDNF1B_D_IMM - 476 |
| 26522 | {.AsmStrOffset: 8498, .AliasCondStart: 3148, .NumOperands: 4, .NumConds: 7 }, |
| 26523 | // AArch64::LDNF1B_H_IMM - 477 |
| 26524 | {.AsmStrOffset: 8524, .AliasCondStart: 3155, .NumOperands: 4, .NumConds: 7 }, |
| 26525 | // AArch64::LDNF1B_IMM - 478 |
| 26526 | {.AsmStrOffset: 8550, .AliasCondStart: 3162, .NumOperands: 4, .NumConds: 7 }, |
| 26527 | // AArch64::LDNF1B_S_IMM - 479 |
| 26528 | {.AsmStrOffset: 8576, .AliasCondStart: 3169, .NumOperands: 4, .NumConds: 7 }, |
| 26529 | // AArch64::LDNF1D_IMM - 480 |
| 26530 | {.AsmStrOffset: 8602, .AliasCondStart: 3176, .NumOperands: 4, .NumConds: 7 }, |
| 26531 | // AArch64::LDNF1H_D_IMM - 481 |
| 26532 | {.AsmStrOffset: 8628, .AliasCondStart: 3183, .NumOperands: 4, .NumConds: 7 }, |
| 26533 | // AArch64::LDNF1H_IMM - 482 |
| 26534 | {.AsmStrOffset: 8654, .AliasCondStart: 3190, .NumOperands: 4, .NumConds: 7 }, |
| 26535 | // AArch64::LDNF1H_S_IMM - 483 |
| 26536 | {.AsmStrOffset: 8680, .AliasCondStart: 3197, .NumOperands: 4, .NumConds: 7 }, |
| 26537 | // AArch64::LDNF1SB_D_IMM - 484 |
| 26538 | {.AsmStrOffset: 8706, .AliasCondStart: 3204, .NumOperands: 4, .NumConds: 7 }, |
| 26539 | // AArch64::LDNF1SB_H_IMM - 485 |
| 26540 | {.AsmStrOffset: 8733, .AliasCondStart: 3211, .NumOperands: 4, .NumConds: 7 }, |
| 26541 | // AArch64::LDNF1SB_S_IMM - 486 |
| 26542 | {.AsmStrOffset: 8760, .AliasCondStart: 3218, .NumOperands: 4, .NumConds: 7 }, |
| 26543 | // AArch64::LDNF1SH_D_IMM - 487 |
| 26544 | {.AsmStrOffset: 8787, .AliasCondStart: 3225, .NumOperands: 4, .NumConds: 7 }, |
| 26545 | // AArch64::LDNF1SH_S_IMM - 488 |
| 26546 | {.AsmStrOffset: 8814, .AliasCondStart: 3232, .NumOperands: 4, .NumConds: 7 }, |
| 26547 | // AArch64::LDNF1SW_D_IMM - 489 |
| 26548 | {.AsmStrOffset: 8841, .AliasCondStart: 3239, .NumOperands: 4, .NumConds: 7 }, |
| 26549 | // AArch64::LDNF1W_D_IMM - 490 |
| 26550 | {.AsmStrOffset: 8868, .AliasCondStart: 3246, .NumOperands: 4, .NumConds: 7 }, |
| 26551 | // AArch64::LDNF1W_IMM - 491 |
| 26552 | {.AsmStrOffset: 8894, .AliasCondStart: 3253, .NumOperands: 4, .NumConds: 7 }, |
| 26553 | // AArch64::LDNPDi - 492 |
| 26554 | {.AsmStrOffset: 8920, .AliasCondStart: 3260, .NumOperands: 4, .NumConds: 7 }, |
| 26555 | // AArch64::LDNPQi - 493 |
| 26556 | {.AsmStrOffset: 8920, .AliasCondStart: 3267, .NumOperands: 4, .NumConds: 7 }, |
| 26557 | // AArch64::LDNPSi - 494 |
| 26558 | {.AsmStrOffset: 8920, .AliasCondStart: 3274, .NumOperands: 4, .NumConds: 7 }, |
| 26559 | // AArch64::LDNPWi - 495 |
| 26560 | {.AsmStrOffset: 8920, .AliasCondStart: 3281, .NumOperands: 4, .NumConds: 4 }, |
| 26561 | // AArch64::LDNPXi - 496 |
| 26562 | {.AsmStrOffset: 8920, .AliasCondStart: 3285, .NumOperands: 4, .NumConds: 4 }, |
| 26563 | // AArch64::LDNT1B_2Z_IMM - 497 |
| 26564 | {.AsmStrOffset: 8938, .AliasCondStart: 3289, .NumOperands: 4, .NumConds: 8 }, |
| 26565 | // AArch64::LDNT1B_2Z_STRIDED_IMM - 498 |
| 26566 | {.AsmStrOffset: 8964, .AliasCondStart: 3297, .NumOperands: 4, .NumConds: 7 }, |
| 26567 | // AArch64::LDNT1B_4Z_IMM - 499 |
| 26568 | {.AsmStrOffset: 8938, .AliasCondStart: 3304, .NumOperands: 4, .NumConds: 8 }, |
| 26569 | // AArch64::LDNT1B_4Z_STRIDED_IMM - 500 |
| 26570 | {.AsmStrOffset: 8990, .AliasCondStart: 3312, .NumOperands: 4, .NumConds: 7 }, |
| 26571 | // AArch64::LDNT1B_ZRI - 501 |
| 26572 | {.AsmStrOffset: 9016, .AliasCondStart: 3319, .NumOperands: 4, .NumConds: 8 }, |
| 26573 | // AArch64::LDNT1B_ZZR_D - 502 |
| 26574 | {.AsmStrOffset: 9042, .AliasCondStart: 3327, .NumOperands: 4, .NumConds: 7 }, |
| 26575 | // AArch64::LDNT1B_ZZR_S - 503 |
| 26576 | {.AsmStrOffset: 9070, .AliasCondStart: 3334, .NumOperands: 4, .NumConds: 7 }, |
| 26577 | // AArch64::LDNT1D_2Z_IMM - 504 |
| 26578 | {.AsmStrOffset: 9098, .AliasCondStart: 3341, .NumOperands: 4, .NumConds: 8 }, |
| 26579 | // AArch64::LDNT1D_2Z_STRIDED_IMM - 505 |
| 26580 | {.AsmStrOffset: 9124, .AliasCondStart: 3349, .NumOperands: 4, .NumConds: 7 }, |
| 26581 | // AArch64::LDNT1D_4Z_IMM - 506 |
| 26582 | {.AsmStrOffset: 9098, .AliasCondStart: 3356, .NumOperands: 4, .NumConds: 8 }, |
| 26583 | // AArch64::LDNT1D_4Z_STRIDED_IMM - 507 |
| 26584 | {.AsmStrOffset: 9124, .AliasCondStart: 3364, .NumOperands: 4, .NumConds: 7 }, |
| 26585 | // AArch64::LDNT1D_ZRI - 508 |
| 26586 | {.AsmStrOffset: 9150, .AliasCondStart: 3371, .NumOperands: 4, .NumConds: 8 }, |
| 26587 | // AArch64::LDNT1D_ZZR_D - 509 |
| 26588 | {.AsmStrOffset: 9176, .AliasCondStart: 3379, .NumOperands: 4, .NumConds: 7 }, |
| 26589 | // AArch64::LDNT1H_2Z_IMM - 510 |
| 26590 | {.AsmStrOffset: 9204, .AliasCondStart: 3386, .NumOperands: 4, .NumConds: 8 }, |
| 26591 | // AArch64::LDNT1H_2Z_STRIDED_IMM - 511 |
| 26592 | {.AsmStrOffset: 9230, .AliasCondStart: 3394, .NumOperands: 4, .NumConds: 7 }, |
| 26593 | // AArch64::LDNT1H_4Z_IMM - 512 |
| 26594 | {.AsmStrOffset: 9204, .AliasCondStart: 3401, .NumOperands: 4, .NumConds: 8 }, |
| 26595 | // AArch64::LDNT1H_4Z_STRIDED_IMM - 513 |
| 26596 | {.AsmStrOffset: 9256, .AliasCondStart: 3409, .NumOperands: 4, .NumConds: 7 }, |
| 26597 | // AArch64::LDNT1H_ZRI - 514 |
| 26598 | {.AsmStrOffset: 9282, .AliasCondStart: 3416, .NumOperands: 4, .NumConds: 8 }, |
| 26599 | // AArch64::LDNT1H_ZZR_D - 515 |
| 26600 | {.AsmStrOffset: 9308, .AliasCondStart: 3424, .NumOperands: 4, .NumConds: 7 }, |
| 26601 | // AArch64::LDNT1H_ZZR_S - 516 |
| 26602 | {.AsmStrOffset: 9336, .AliasCondStart: 3431, .NumOperands: 4, .NumConds: 7 }, |
| 26603 | // AArch64::LDNT1SB_ZZR_D - 517 |
| 26604 | {.AsmStrOffset: 9364, .AliasCondStart: 3438, .NumOperands: 4, .NumConds: 7 }, |
| 26605 | // AArch64::LDNT1SB_ZZR_S - 518 |
| 26606 | {.AsmStrOffset: 9393, .AliasCondStart: 3445, .NumOperands: 4, .NumConds: 7 }, |
| 26607 | // AArch64::LDNT1SH_ZZR_D - 519 |
| 26608 | {.AsmStrOffset: 9422, .AliasCondStart: 3452, .NumOperands: 4, .NumConds: 7 }, |
| 26609 | // AArch64::LDNT1SH_ZZR_S - 520 |
| 26610 | {.AsmStrOffset: 9451, .AliasCondStart: 3459, .NumOperands: 4, .NumConds: 7 }, |
| 26611 | // AArch64::LDNT1SW_ZZR_D - 521 |
| 26612 | {.AsmStrOffset: 9480, .AliasCondStart: 3466, .NumOperands: 4, .NumConds: 7 }, |
| 26613 | // AArch64::LDNT1W_2Z_IMM - 522 |
| 26614 | {.AsmStrOffset: 9509, .AliasCondStart: 3473, .NumOperands: 4, .NumConds: 8 }, |
| 26615 | // AArch64::LDNT1W_2Z_STRIDED_IMM - 523 |
| 26616 | {.AsmStrOffset: 9535, .AliasCondStart: 3481, .NumOperands: 4, .NumConds: 7 }, |
| 26617 | // AArch64::LDNT1W_4Z_IMM - 524 |
| 26618 | {.AsmStrOffset: 9509, .AliasCondStart: 3488, .NumOperands: 4, .NumConds: 8 }, |
| 26619 | // AArch64::LDNT1W_4Z_STRIDED_IMM - 525 |
| 26620 | {.AsmStrOffset: 9535, .AliasCondStart: 3496, .NumOperands: 4, .NumConds: 7 }, |
| 26621 | // AArch64::LDNT1W_ZRI - 526 |
| 26622 | {.AsmStrOffset: 9561, .AliasCondStart: 3503, .NumOperands: 4, .NumConds: 8 }, |
| 26623 | // AArch64::LDNT1W_ZZR_D - 527 |
| 26624 | {.AsmStrOffset: 9587, .AliasCondStart: 3511, .NumOperands: 4, .NumConds: 7 }, |
| 26625 | // AArch64::LDNT1W_ZZR_S - 528 |
| 26626 | {.AsmStrOffset: 9615, .AliasCondStart: 3518, .NumOperands: 4, .NumConds: 7 }, |
| 26627 | // AArch64::LDPDi - 529 |
| 26628 | {.AsmStrOffset: 9643, .AliasCondStart: 3525, .NumOperands: 4, .NumConds: 7 }, |
| 26629 | // AArch64::LDPQi - 530 |
| 26630 | {.AsmStrOffset: 9643, .AliasCondStart: 3532, .NumOperands: 4, .NumConds: 7 }, |
| 26631 | // AArch64::LDPSWi - 531 |
| 26632 | {.AsmStrOffset: 9660, .AliasCondStart: 3539, .NumOperands: 4, .NumConds: 4 }, |
| 26633 | // AArch64::LDPSi - 532 |
| 26634 | {.AsmStrOffset: 9643, .AliasCondStart: 3543, .NumOperands: 4, .NumConds: 7 }, |
| 26635 | // AArch64::LDPWi - 533 |
| 26636 | {.AsmStrOffset: 9643, .AliasCondStart: 3550, .NumOperands: 4, .NumConds: 4 }, |
| 26637 | // AArch64::LDPXi - 534 |
| 26638 | {.AsmStrOffset: 9643, .AliasCondStart: 3554, .NumOperands: 4, .NumConds: 4 }, |
| 26639 | // AArch64::LDRAAindexed - 535 |
| 26640 | {.AsmStrOffset: 9679, .AliasCondStart: 3558, .NumOperands: 3, .NumConds: 6 }, |
| 26641 | // AArch64::LDRABindexed - 536 |
| 26642 | {.AsmStrOffset: 9694, .AliasCondStart: 3564, .NumOperands: 3, .NumConds: 6 }, |
| 26643 | // AArch64::LDRBBroX - 537 |
| 26644 | {.AsmStrOffset: 9709, .AliasCondStart: 3570, .NumOperands: 5, .NumConds: 5 }, |
| 26645 | // AArch64::LDRBBui - 538 |
| 26646 | {.AsmStrOffset: 9727, .AliasCondStart: 3575, .NumOperands: 3, .NumConds: 3 }, |
| 26647 | // AArch64::LDRBroX - 539 |
| 26648 | {.AsmStrOffset: 9741, .AliasCondStart: 3578, .NumOperands: 5, .NumConds: 8 }, |
| 26649 | // AArch64::LDRBui - 540 |
| 26650 | {.AsmStrOffset: 9758, .AliasCondStart: 3586, .NumOperands: 3, .NumConds: 6 }, |
| 26651 | // AArch64::LDRDroX - 541 |
| 26652 | {.AsmStrOffset: 9741, .AliasCondStart: 3592, .NumOperands: 5, .NumConds: 8 }, |
| 26653 | // AArch64::LDRDui - 542 |
| 26654 | {.AsmStrOffset: 9758, .AliasCondStart: 3600, .NumOperands: 3, .NumConds: 6 }, |
| 26655 | // AArch64::LDRHHroX - 543 |
| 26656 | {.AsmStrOffset: 9771, .AliasCondStart: 3606, .NumOperands: 5, .NumConds: 5 }, |
| 26657 | // AArch64::LDRHHui - 544 |
| 26658 | {.AsmStrOffset: 9789, .AliasCondStart: 3611, .NumOperands: 3, .NumConds: 3 }, |
| 26659 | // AArch64::LDRHroX - 545 |
| 26660 | {.AsmStrOffset: 9741, .AliasCondStart: 3614, .NumOperands: 5, .NumConds: 8 }, |
| 26661 | // AArch64::LDRHui - 546 |
| 26662 | {.AsmStrOffset: 9758, .AliasCondStart: 3622, .NumOperands: 3, .NumConds: 6 }, |
| 26663 | // AArch64::LDRQroX - 547 |
| 26664 | {.AsmStrOffset: 9741, .AliasCondStart: 3628, .NumOperands: 5, .NumConds: 8 }, |
| 26665 | // AArch64::LDRQui - 548 |
| 26666 | {.AsmStrOffset: 9758, .AliasCondStart: 3636, .NumOperands: 3, .NumConds: 6 }, |
| 26667 | // AArch64::LDRSBWroX - 549 |
| 26668 | {.AsmStrOffset: 9803, .AliasCondStart: 3642, .NumOperands: 5, .NumConds: 5 }, |
| 26669 | // AArch64::LDRSBWui - 550 |
| 26670 | {.AsmStrOffset: 9822, .AliasCondStart: 3647, .NumOperands: 3, .NumConds: 3 }, |
| 26671 | // AArch64::LDRSBXroX - 551 |
| 26672 | {.AsmStrOffset: 9803, .AliasCondStart: 3650, .NumOperands: 5, .NumConds: 5 }, |
| 26673 | // AArch64::LDRSBXui - 552 |
| 26674 | {.AsmStrOffset: 9822, .AliasCondStart: 3655, .NumOperands: 3, .NumConds: 3 }, |
| 26675 | // AArch64::LDRSHWroX - 553 |
| 26676 | {.AsmStrOffset: 9837, .AliasCondStart: 3658, .NumOperands: 5, .NumConds: 5 }, |
| 26677 | // AArch64::LDRSHWui - 554 |
| 26678 | {.AsmStrOffset: 9856, .AliasCondStart: 3663, .NumOperands: 3, .NumConds: 3 }, |
| 26679 | // AArch64::LDRSHXroX - 555 |
| 26680 | {.AsmStrOffset: 9837, .AliasCondStart: 3666, .NumOperands: 5, .NumConds: 5 }, |
| 26681 | // AArch64::LDRSHXui - 556 |
| 26682 | {.AsmStrOffset: 9856, .AliasCondStart: 3671, .NumOperands: 3, .NumConds: 3 }, |
| 26683 | // AArch64::LDRSWroX - 557 |
| 26684 | {.AsmStrOffset: 9871, .AliasCondStart: 3674, .NumOperands: 5, .NumConds: 5 }, |
| 26685 | // AArch64::LDRSWui - 558 |
| 26686 | {.AsmStrOffset: 9890, .AliasCondStart: 3679, .NumOperands: 3, .NumConds: 3 }, |
| 26687 | // AArch64::LDRSroX - 559 |
| 26688 | {.AsmStrOffset: 9741, .AliasCondStart: 3682, .NumOperands: 5, .NumConds: 8 }, |
| 26689 | // AArch64::LDRSui - 560 |
| 26690 | {.AsmStrOffset: 9758, .AliasCondStart: 3690, .NumOperands: 3, .NumConds: 6 }, |
| 26691 | // AArch64::LDRWroX - 561 |
| 26692 | {.AsmStrOffset: 9741, .AliasCondStart: 3696, .NumOperands: 5, .NumConds: 5 }, |
| 26693 | // AArch64::LDRWui - 562 |
| 26694 | {.AsmStrOffset: 9758, .AliasCondStart: 3701, .NumOperands: 3, .NumConds: 3 }, |
| 26695 | // AArch64::LDRXroX - 563 |
| 26696 | {.AsmStrOffset: 9741, .AliasCondStart: 3704, .NumOperands: 5, .NumConds: 5 }, |
| 26697 | // AArch64::LDRXui - 564 |
| 26698 | {.AsmStrOffset: 9758, .AliasCondStart: 3709, .NumOperands: 3, .NumConds: 3 }, |
| 26699 | // AArch64::LDR_PXI - 565 |
| 26700 | {.AsmStrOffset: 9905, .AliasCondStart: 3712, .NumOperands: 3, .NumConds: 7 }, |
| 26701 | // AArch64::LDR_ZA - 566 |
| 26702 | {.AsmStrOffset: 9920, .AliasCondStart: 3719, .NumOperands: 5, .NumConds: 8 }, |
| 26703 | // AArch64::LDR_ZXI - 567 |
| 26704 | {.AsmStrOffset: 9905, .AliasCondStart: 3727, .NumOperands: 3, .NumConds: 7 }, |
| 26705 | // AArch64::LDSETB - 568 |
| 26706 | {.AsmStrOffset: 9945, .AliasCondStart: 3734, .NumOperands: 3, .NumConds: 6 }, |
| 26707 | // AArch64::LDSETH - 569 |
| 26708 | {.AsmStrOffset: 9961, .AliasCondStart: 3740, .NumOperands: 3, .NumConds: 6 }, |
| 26709 | // AArch64::LDSETLB - 570 |
| 26710 | {.AsmStrOffset: 9977, .AliasCondStart: 3746, .NumOperands: 3, .NumConds: 6 }, |
| 26711 | // AArch64::LDSETLH - 571 |
| 26712 | {.AsmStrOffset: 9994, .AliasCondStart: 3752, .NumOperands: 3, .NumConds: 6 }, |
| 26713 | // AArch64::LDSETLW - 572 |
| 26714 | {.AsmStrOffset: 10011, .AliasCondStart: 3758, .NumOperands: 3, .NumConds: 6 }, |
| 26715 | // AArch64::LDSETLX - 573 |
| 26716 | {.AsmStrOffset: 10011, .AliasCondStart: 3764, .NumOperands: 3, .NumConds: 6 }, |
| 26717 | // AArch64::LDSETW - 574 |
| 26718 | {.AsmStrOffset: 10027, .AliasCondStart: 3770, .NumOperands: 3, .NumConds: 6 }, |
| 26719 | // AArch64::LDSETX - 575 |
| 26720 | {.AsmStrOffset: 10027, .AliasCondStart: 3776, .NumOperands: 3, .NumConds: 6 }, |
| 26721 | // AArch64::LDSMAXB - 576 |
| 26722 | {.AsmStrOffset: 10042, .AliasCondStart: 3782, .NumOperands: 3, .NumConds: 6 }, |
| 26723 | // AArch64::LDSMAXH - 577 |
| 26724 | {.AsmStrOffset: 10059, .AliasCondStart: 3788, .NumOperands: 3, .NumConds: 6 }, |
| 26725 | // AArch64::LDSMAXLB - 578 |
| 26726 | {.AsmStrOffset: 10076, .AliasCondStart: 3794, .NumOperands: 3, .NumConds: 6 }, |
| 26727 | // AArch64::LDSMAXLH - 579 |
| 26728 | {.AsmStrOffset: 10094, .AliasCondStart: 3800, .NumOperands: 3, .NumConds: 6 }, |
| 26729 | // AArch64::LDSMAXLW - 580 |
| 26730 | {.AsmStrOffset: 10112, .AliasCondStart: 3806, .NumOperands: 3, .NumConds: 6 }, |
| 26731 | // AArch64::LDSMAXLX - 581 |
| 26732 | {.AsmStrOffset: 10112, .AliasCondStart: 3812, .NumOperands: 3, .NumConds: 6 }, |
| 26733 | // AArch64::LDSMAXW - 582 |
| 26734 | {.AsmStrOffset: 10129, .AliasCondStart: 3818, .NumOperands: 3, .NumConds: 6 }, |
| 26735 | // AArch64::LDSMAXX - 583 |
| 26736 | {.AsmStrOffset: 10129, .AliasCondStart: 3824, .NumOperands: 3, .NumConds: 6 }, |
| 26737 | // AArch64::LDSMINB - 584 |
| 26738 | {.AsmStrOffset: 10145, .AliasCondStart: 3830, .NumOperands: 3, .NumConds: 6 }, |
| 26739 | // AArch64::LDSMINH - 585 |
| 26740 | {.AsmStrOffset: 10162, .AliasCondStart: 3836, .NumOperands: 3, .NumConds: 6 }, |
| 26741 | // AArch64::LDSMINLB - 586 |
| 26742 | {.AsmStrOffset: 10179, .AliasCondStart: 3842, .NumOperands: 3, .NumConds: 6 }, |
| 26743 | // AArch64::LDSMINLH - 587 |
| 26744 | {.AsmStrOffset: 10197, .AliasCondStart: 3848, .NumOperands: 3, .NumConds: 6 }, |
| 26745 | // AArch64::LDSMINLW - 588 |
| 26746 | {.AsmStrOffset: 10215, .AliasCondStart: 3854, .NumOperands: 3, .NumConds: 6 }, |
| 26747 | // AArch64::LDSMINLX - 589 |
| 26748 | {.AsmStrOffset: 10215, .AliasCondStart: 3860, .NumOperands: 3, .NumConds: 6 }, |
| 26749 | // AArch64::LDSMINW - 590 |
| 26750 | {.AsmStrOffset: 10232, .AliasCondStart: 3866, .NumOperands: 3, .NumConds: 6 }, |
| 26751 | // AArch64::LDSMINX - 591 |
| 26752 | {.AsmStrOffset: 10232, .AliasCondStart: 3872, .NumOperands: 3, .NumConds: 6 }, |
| 26753 | // AArch64::LDTADDLW - 592 |
| 26754 | {.AsmStrOffset: 10248, .AliasCondStart: 3878, .NumOperands: 3, .NumConds: 6 }, |
| 26755 | // AArch64::LDTADDLX - 593 |
| 26756 | {.AsmStrOffset: 10248, .AliasCondStart: 3884, .NumOperands: 3, .NumConds: 6 }, |
| 26757 | // AArch64::LDTADDW - 594 |
| 26758 | {.AsmStrOffset: 10265, .AliasCondStart: 3890, .NumOperands: 3, .NumConds: 6 }, |
| 26759 | // AArch64::LDTADDX - 595 |
| 26760 | {.AsmStrOffset: 10265, .AliasCondStart: 3896, .NumOperands: 3, .NumConds: 6 }, |
| 26761 | // AArch64::LDTCLRLW - 596 |
| 26762 | {.AsmStrOffset: 10281, .AliasCondStart: 3902, .NumOperands: 3, .NumConds: 6 }, |
| 26763 | // AArch64::LDTCLRLX - 597 |
| 26764 | {.AsmStrOffset: 10281, .AliasCondStart: 3908, .NumOperands: 3, .NumConds: 6 }, |
| 26765 | // AArch64::LDTCLRW - 598 |
| 26766 | {.AsmStrOffset: 10298, .AliasCondStart: 3914, .NumOperands: 3, .NumConds: 6 }, |
| 26767 | // AArch64::LDTCLRX - 599 |
| 26768 | {.AsmStrOffset: 10298, .AliasCondStart: 3920, .NumOperands: 3, .NumConds: 6 }, |
| 26769 | // AArch64::LDTNPQi - 600 |
| 26770 | {.AsmStrOffset: 10314, .AliasCondStart: 3926, .NumOperands: 4, .NumConds: 10 }, |
| 26771 | // AArch64::LDTNPXi - 601 |
| 26772 | {.AsmStrOffset: 10314, .AliasCondStart: 3936, .NumOperands: 4, .NumConds: 7 }, |
| 26773 | // AArch64::LDTPQi - 602 |
| 26774 | {.AsmStrOffset: 10333, .AliasCondStart: 3943, .NumOperands: 4, .NumConds: 10 }, |
| 26775 | // AArch64::LDTPi - 603 |
| 26776 | {.AsmStrOffset: 10333, .AliasCondStart: 3953, .NumOperands: 4, .NumConds: 7 }, |
| 26777 | // AArch64::LDTRBi - 604 |
| 26778 | {.AsmStrOffset: 10351, .AliasCondStart: 3960, .NumOperands: 3, .NumConds: 3 }, |
| 26779 | // AArch64::LDTRHi - 605 |
| 26780 | {.AsmStrOffset: 10366, .AliasCondStart: 3963, .NumOperands: 3, .NumConds: 3 }, |
| 26781 | // AArch64::LDTRSBWi - 606 |
| 26782 | {.AsmStrOffset: 10381, .AliasCondStart: 3966, .NumOperands: 3, .NumConds: 3 }, |
| 26783 | // AArch64::LDTRSBXi - 607 |
| 26784 | {.AsmStrOffset: 10381, .AliasCondStart: 3969, .NumOperands: 3, .NumConds: 3 }, |
| 26785 | // AArch64::LDTRSHWi - 608 |
| 26786 | {.AsmStrOffset: 10397, .AliasCondStart: 3972, .NumOperands: 3, .NumConds: 3 }, |
| 26787 | // AArch64::LDTRSHXi - 609 |
| 26788 | {.AsmStrOffset: 10397, .AliasCondStart: 3975, .NumOperands: 3, .NumConds: 3 }, |
| 26789 | // AArch64::LDTRSWi - 610 |
| 26790 | {.AsmStrOffset: 10413, .AliasCondStart: 3978, .NumOperands: 3, .NumConds: 3 }, |
| 26791 | // AArch64::LDTRWi - 611 |
| 26792 | {.AsmStrOffset: 10429, .AliasCondStart: 3981, .NumOperands: 3, .NumConds: 3 }, |
| 26793 | // AArch64::LDTRXi - 612 |
| 26794 | {.AsmStrOffset: 10429, .AliasCondStart: 3984, .NumOperands: 3, .NumConds: 3 }, |
| 26795 | // AArch64::LDTSETLW - 613 |
| 26796 | {.AsmStrOffset: 10443, .AliasCondStart: 3987, .NumOperands: 3, .NumConds: 6 }, |
| 26797 | // AArch64::LDTSETLX - 614 |
| 26798 | {.AsmStrOffset: 10443, .AliasCondStart: 3993, .NumOperands: 3, .NumConds: 6 }, |
| 26799 | // AArch64::LDTSETW - 615 |
| 26800 | {.AsmStrOffset: 10460, .AliasCondStart: 3999, .NumOperands: 3, .NumConds: 6 }, |
| 26801 | // AArch64::LDTSETX - 616 |
| 26802 | {.AsmStrOffset: 10460, .AliasCondStart: 4005, .NumOperands: 3, .NumConds: 6 }, |
| 26803 | // AArch64::LDUMAXB - 617 |
| 26804 | {.AsmStrOffset: 10476, .AliasCondStart: 4011, .NumOperands: 3, .NumConds: 6 }, |
| 26805 | // AArch64::LDUMAXH - 618 |
| 26806 | {.AsmStrOffset: 10493, .AliasCondStart: 4017, .NumOperands: 3, .NumConds: 6 }, |
| 26807 | // AArch64::LDUMAXLB - 619 |
| 26808 | {.AsmStrOffset: 10510, .AliasCondStart: 4023, .NumOperands: 3, .NumConds: 6 }, |
| 26809 | // AArch64::LDUMAXLH - 620 |
| 26810 | {.AsmStrOffset: 10528, .AliasCondStart: 4029, .NumOperands: 3, .NumConds: 6 }, |
| 26811 | // AArch64::LDUMAXLW - 621 |
| 26812 | {.AsmStrOffset: 10546, .AliasCondStart: 4035, .NumOperands: 3, .NumConds: 6 }, |
| 26813 | // AArch64::LDUMAXLX - 622 |
| 26814 | {.AsmStrOffset: 10546, .AliasCondStart: 4041, .NumOperands: 3, .NumConds: 6 }, |
| 26815 | // AArch64::LDUMAXW - 623 |
| 26816 | {.AsmStrOffset: 10563, .AliasCondStart: 4047, .NumOperands: 3, .NumConds: 6 }, |
| 26817 | // AArch64::LDUMAXX - 624 |
| 26818 | {.AsmStrOffset: 10563, .AliasCondStart: 4053, .NumOperands: 3, .NumConds: 6 }, |
| 26819 | // AArch64::LDUMINB - 625 |
| 26820 | {.AsmStrOffset: 10579, .AliasCondStart: 4059, .NumOperands: 3, .NumConds: 6 }, |
| 26821 | // AArch64::LDUMINH - 626 |
| 26822 | {.AsmStrOffset: 10596, .AliasCondStart: 4065, .NumOperands: 3, .NumConds: 6 }, |
| 26823 | // AArch64::LDUMINLB - 627 |
| 26824 | {.AsmStrOffset: 10613, .AliasCondStart: 4071, .NumOperands: 3, .NumConds: 6 }, |
| 26825 | // AArch64::LDUMINLH - 628 |
| 26826 | {.AsmStrOffset: 10631, .AliasCondStart: 4077, .NumOperands: 3, .NumConds: 6 }, |
| 26827 | // AArch64::LDUMINLW - 629 |
| 26828 | {.AsmStrOffset: 10649, .AliasCondStart: 4083, .NumOperands: 3, .NumConds: 6 }, |
| 26829 | // AArch64::LDUMINLX - 630 |
| 26830 | {.AsmStrOffset: 10649, .AliasCondStart: 4089, .NumOperands: 3, .NumConds: 6 }, |
| 26831 | // AArch64::LDUMINW - 631 |
| 26832 | {.AsmStrOffset: 10666, .AliasCondStart: 4095, .NumOperands: 3, .NumConds: 6 }, |
| 26833 | // AArch64::LDUMINX - 632 |
| 26834 | {.AsmStrOffset: 10666, .AliasCondStart: 4101, .NumOperands: 3, .NumConds: 6 }, |
| 26835 | // AArch64::LDURBBi - 633 |
| 26836 | {.AsmStrOffset: 10682, .AliasCondStart: 4107, .NumOperands: 3, .NumConds: 3 }, |
| 26837 | // AArch64::LDURBi - 634 |
| 26838 | {.AsmStrOffset: 10697, .AliasCondStart: 4110, .NumOperands: 3, .NumConds: 6 }, |
| 26839 | // AArch64::LDURDi - 635 |
| 26840 | {.AsmStrOffset: 10697, .AliasCondStart: 4116, .NumOperands: 3, .NumConds: 6 }, |
| 26841 | // AArch64::LDURHHi - 636 |
| 26842 | {.AsmStrOffset: 10711, .AliasCondStart: 4122, .NumOperands: 3, .NumConds: 3 }, |
| 26843 | // AArch64::LDURHi - 637 |
| 26844 | {.AsmStrOffset: 10697, .AliasCondStart: 4125, .NumOperands: 3, .NumConds: 6 }, |
| 26845 | // AArch64::LDURQi - 638 |
| 26846 | {.AsmStrOffset: 10697, .AliasCondStart: 4131, .NumOperands: 3, .NumConds: 6 }, |
| 26847 | // AArch64::LDURSBWi - 639 |
| 26848 | {.AsmStrOffset: 10726, .AliasCondStart: 4137, .NumOperands: 3, .NumConds: 3 }, |
| 26849 | // AArch64::LDURSBXi - 640 |
| 26850 | {.AsmStrOffset: 10726, .AliasCondStart: 4140, .NumOperands: 3, .NumConds: 3 }, |
| 26851 | // AArch64::LDURSHWi - 641 |
| 26852 | {.AsmStrOffset: 10742, .AliasCondStart: 4143, .NumOperands: 3, .NumConds: 3 }, |
| 26853 | // AArch64::LDURSHXi - 642 |
| 26854 | {.AsmStrOffset: 10742, .AliasCondStart: 4146, .NumOperands: 3, .NumConds: 3 }, |
| 26855 | // AArch64::LDURSWi - 643 |
| 26856 | {.AsmStrOffset: 10758, .AliasCondStart: 4149, .NumOperands: 3, .NumConds: 3 }, |
| 26857 | // AArch64::LDURSi - 644 |
| 26858 | {.AsmStrOffset: 10697, .AliasCondStart: 4152, .NumOperands: 3, .NumConds: 6 }, |
| 26859 | // AArch64::LDURWi - 645 |
| 26860 | {.AsmStrOffset: 10697, .AliasCondStart: 4158, .NumOperands: 3, .NumConds: 3 }, |
| 26861 | // AArch64::LDURXi - 646 |
| 26862 | {.AsmStrOffset: 10697, .AliasCondStart: 4161, .NumOperands: 3, .NumConds: 3 }, |
| 26863 | // AArch64::MADDWrrr - 647 |
| 26864 | {.AsmStrOffset: 10774, .AliasCondStart: 4164, .NumOperands: 4, .NumConds: 4 }, |
| 26865 | // AArch64::MADDXrrr - 648 |
| 26866 | {.AsmStrOffset: 10774, .AliasCondStart: 4168, .NumOperands: 4, .NumConds: 4 }, |
| 26867 | // AArch64::MOVA_2ZMXI_H_B - 649 |
| 26868 | {.AsmStrOffset: 10789, .AliasCondStart: 4172, .NumOperands: 4, .NumConds: 6 }, |
| 26869 | // AArch64::MOVA_2ZMXI_H_D - 650 |
| 26870 | {.AsmStrOffset: 10814, .AliasCondStart: 4178, .NumOperands: 4, .NumConds: 6 }, |
| 26871 | // AArch64::MOVA_2ZMXI_H_H - 651 |
| 26872 | {.AsmStrOffset: 10839, .AliasCondStart: 4184, .NumOperands: 4, .NumConds: 6 }, |
| 26873 | // AArch64::MOVA_2ZMXI_H_S - 652 |
| 26874 | {.AsmStrOffset: 10864, .AliasCondStart: 4190, .NumOperands: 4, .NumConds: 6 }, |
| 26875 | // AArch64::MOVA_2ZMXI_V_B - 653 |
| 26876 | {.AsmStrOffset: 10889, .AliasCondStart: 4196, .NumOperands: 4, .NumConds: 6 }, |
| 26877 | // AArch64::MOVA_2ZMXI_V_D - 654 |
| 26878 | {.AsmStrOffset: 10914, .AliasCondStart: 4202, .NumOperands: 4, .NumConds: 6 }, |
| 26879 | // AArch64::MOVA_2ZMXI_V_H - 655 |
| 26880 | {.AsmStrOffset: 10939, .AliasCondStart: 4208, .NumOperands: 4, .NumConds: 6 }, |
| 26881 | // AArch64::MOVA_2ZMXI_V_S - 656 |
| 26882 | {.AsmStrOffset: 10964, .AliasCondStart: 4214, .NumOperands: 4, .NumConds: 6 }, |
| 26883 | // AArch64::MOVA_4ZMXI_H_B - 657 |
| 26884 | {.AsmStrOffset: 10989, .AliasCondStart: 4220, .NumOperands: 4, .NumConds: 6 }, |
| 26885 | // AArch64::MOVA_4ZMXI_H_D - 658 |
| 26886 | {.AsmStrOffset: 11014, .AliasCondStart: 4226, .NumOperands: 4, .NumConds: 6 }, |
| 26887 | // AArch64::MOVA_4ZMXI_H_H - 659 |
| 26888 | {.AsmStrOffset: 11039, .AliasCondStart: 4232, .NumOperands: 4, .NumConds: 6 }, |
| 26889 | // AArch64::MOVA_4ZMXI_H_S - 660 |
| 26890 | {.AsmStrOffset: 11064, .AliasCondStart: 4238, .NumOperands: 4, .NumConds: 6 }, |
| 26891 | // AArch64::MOVA_4ZMXI_V_B - 661 |
| 26892 | {.AsmStrOffset: 11089, .AliasCondStart: 4244, .NumOperands: 4, .NumConds: 6 }, |
| 26893 | // AArch64::MOVA_4ZMXI_V_D - 662 |
| 26894 | {.AsmStrOffset: 11114, .AliasCondStart: 4250, .NumOperands: 4, .NumConds: 6 }, |
| 26895 | // AArch64::MOVA_4ZMXI_V_H - 663 |
| 26896 | {.AsmStrOffset: 11139, .AliasCondStart: 4256, .NumOperands: 4, .NumConds: 6 }, |
| 26897 | // AArch64::MOVA_4ZMXI_V_S - 664 |
| 26898 | {.AsmStrOffset: 11164, .AliasCondStart: 4262, .NumOperands: 4, .NumConds: 6 }, |
| 26899 | // AArch64::MOVA_MXI2Z_H_B - 665 |
| 26900 | {.AsmStrOffset: 11189, .AliasCondStart: 4268, .NumOperands: 5, .NumConds: 8 }, |
| 26901 | // AArch64::MOVA_MXI2Z_H_D - 666 |
| 26902 | {.AsmStrOffset: 11214, .AliasCondStart: 4276, .NumOperands: 5, .NumConds: 8 }, |
| 26903 | // AArch64::MOVA_MXI2Z_H_H - 667 |
| 26904 | {.AsmStrOffset: 11239, .AliasCondStart: 4284, .NumOperands: 5, .NumConds: 8 }, |
| 26905 | // AArch64::MOVA_MXI2Z_H_S - 668 |
| 26906 | {.AsmStrOffset: 11264, .AliasCondStart: 4292, .NumOperands: 5, .NumConds: 8 }, |
| 26907 | // AArch64::MOVA_MXI2Z_V_B - 669 |
| 26908 | {.AsmStrOffset: 11289, .AliasCondStart: 4300, .NumOperands: 5, .NumConds: 8 }, |
| 26909 | // AArch64::MOVA_MXI2Z_V_D - 670 |
| 26910 | {.AsmStrOffset: 11314, .AliasCondStart: 4308, .NumOperands: 5, .NumConds: 8 }, |
| 26911 | // AArch64::MOVA_MXI2Z_V_H - 671 |
| 26912 | {.AsmStrOffset: 11339, .AliasCondStart: 4316, .NumOperands: 5, .NumConds: 8 }, |
| 26913 | // AArch64::MOVA_MXI2Z_V_S - 672 |
| 26914 | {.AsmStrOffset: 11364, .AliasCondStart: 4324, .NumOperands: 5, .NumConds: 8 }, |
| 26915 | // AArch64::MOVA_MXI4Z_H_B - 673 |
| 26916 | {.AsmStrOffset: 11389, .AliasCondStart: 4332, .NumOperands: 5, .NumConds: 8 }, |
| 26917 | // AArch64::MOVA_MXI4Z_H_D - 674 |
| 26918 | {.AsmStrOffset: 11414, .AliasCondStart: 4340, .NumOperands: 5, .NumConds: 8 }, |
| 26919 | // AArch64::MOVA_MXI4Z_H_H - 675 |
| 26920 | {.AsmStrOffset: 11439, .AliasCondStart: 4348, .NumOperands: 5, .NumConds: 8 }, |
| 26921 | // AArch64::MOVA_MXI4Z_H_S - 676 |
| 26922 | {.AsmStrOffset: 11464, .AliasCondStart: 4356, .NumOperands: 5, .NumConds: 8 }, |
| 26923 | // AArch64::MOVA_MXI4Z_V_B - 677 |
| 26924 | {.AsmStrOffset: 11489, .AliasCondStart: 4364, .NumOperands: 5, .NumConds: 8 }, |
| 26925 | // AArch64::MOVA_MXI4Z_V_D - 678 |
| 26926 | {.AsmStrOffset: 11514, .AliasCondStart: 4372, .NumOperands: 5, .NumConds: 8 }, |
| 26927 | // AArch64::MOVA_MXI4Z_V_H - 679 |
| 26928 | {.AsmStrOffset: 11539, .AliasCondStart: 4380, .NumOperands: 5, .NumConds: 8 }, |
| 26929 | // AArch64::MOVA_MXI4Z_V_S - 680 |
| 26930 | {.AsmStrOffset: 11564, .AliasCondStart: 4388, .NumOperands: 5, .NumConds: 8 }, |
| 26931 | // AArch64::MOVA_VG2_2ZMXI - 681 |
| 26932 | {.AsmStrOffset: 11589, .AliasCondStart: 4396, .NumOperands: 4, .NumConds: 6 }, |
| 26933 | // AArch64::MOVA_VG2_MXI2Z - 682 |
| 26934 | {.AsmStrOffset: 11620, .AliasCondStart: 4402, .NumOperands: 5, .NumConds: 8 }, |
| 26935 | // AArch64::MOVA_VG4_4ZMXI - 683 |
| 26936 | {.AsmStrOffset: 11651, .AliasCondStart: 4410, .NumOperands: 4, .NumConds: 6 }, |
| 26937 | // AArch64::MOVA_VG4_MXI4Z - 684 |
| 26938 | {.AsmStrOffset: 11682, .AliasCondStart: 4416, .NumOperands: 5, .NumConds: 8 }, |
| 26939 | // AArch64::MOVT_TIZ - 685 |
| 26940 | {.AsmStrOffset: 11713, .AliasCondStart: 4424, .NumOperands: 3, .NumConds: 6 }, |
| 26941 | // AArch64::MSRpstatesvcrImm1 - 686 |
| 26942 | {.AsmStrOffset: 11727, .AliasCondStart: 4430, .NumOperands: 2, .NumConds: 2 }, |
| 26943 | {.AsmStrOffset: 11735, .AliasCondStart: 4432, .NumOperands: 2, .NumConds: 2 }, |
| 26944 | {.AsmStrOffset: 11746, .AliasCondStart: 4434, .NumOperands: 2, .NumConds: 2 }, |
| 26945 | {.AsmStrOffset: 11757, .AliasCondStart: 4436, .NumOperands: 2, .NumConds: 2 }, |
| 26946 | {.AsmStrOffset: 11764, .AliasCondStart: 4438, .NumOperands: 2, .NumConds: 2 }, |
| 26947 | {.AsmStrOffset: 11774, .AliasCondStart: 4440, .NumOperands: 2, .NumConds: 2 }, |
| 26948 | // AArch64::MSUBWrrr - 692 |
| 26949 | {.AsmStrOffset: 11784, .AliasCondStart: 4442, .NumOperands: 4, .NumConds: 4 }, |
| 26950 | // AArch64::MSUBXrrr - 693 |
| 26951 | {.AsmStrOffset: 11784, .AliasCondStart: 4446, .NumOperands: 4, .NumConds: 4 }, |
| 26952 | // AArch64::NOP - 694 |
| 26953 | {.AsmStrOffset: 11800, .AliasCondStart: 4450, .NumOperands: 0, .NumConds: 0 }, |
| 26954 | // AArch64::NOTv16i8 - 695 |
| 26955 | {.AsmStrOffset: 11804, .AliasCondStart: 4450, .NumOperands: 2, .NumConds: 5 }, |
| 26956 | // AArch64::NOTv8i8 - 696 |
| 26957 | {.AsmStrOffset: 11827, .AliasCondStart: 4455, .NumOperands: 2, .NumConds: 5 }, |
| 26958 | // AArch64::ORNWrs - 697 |
| 26959 | {.AsmStrOffset: 11848, .AliasCondStart: 4460, .NumOperands: 4, .NumConds: 4 }, |
| 26960 | {.AsmStrOffset: 11859, .AliasCondStart: 4464, .NumOperands: 4, .NumConds: 3 }, |
| 26961 | {.AsmStrOffset: 11874, .AliasCondStart: 4467, .NumOperands: 4, .NumConds: 4 }, |
| 26962 | // AArch64::ORNXrs - 700 |
| 26963 | {.AsmStrOffset: 11848, .AliasCondStart: 4471, .NumOperands: 4, .NumConds: 4 }, |
| 26964 | {.AsmStrOffset: 11859, .AliasCondStart: 4475, .NumOperands: 4, .NumConds: 3 }, |
| 26965 | {.AsmStrOffset: 11874, .AliasCondStart: 4478, .NumOperands: 4, .NumConds: 4 }, |
| 26966 | // AArch64::ORRS_PPzPP - 703 |
| 26967 | {.AsmStrOffset: 11889, .AliasCondStart: 4482, .NumOperands: 4, .NumConds: 8 }, |
| 26968 | // AArch64::ORRWrs - 704 |
| 26969 | {.AsmStrOffset: 11905, .AliasCondStart: 4490, .NumOperands: 4, .NumConds: 4 }, |
| 26970 | {.AsmStrOffset: 11916, .AliasCondStart: 4494, .NumOperands: 4, .NumConds: 4 }, |
| 26971 | // AArch64::ORRXrs - 706 |
| 26972 | {.AsmStrOffset: 11905, .AliasCondStart: 4498, .NumOperands: 4, .NumConds: 4 }, |
| 26973 | {.AsmStrOffset: 11916, .AliasCondStart: 4502, .NumOperands: 4, .NumConds: 4 }, |
| 26974 | // AArch64::ORR_PPzPP - 708 |
| 26975 | {.AsmStrOffset: 11931, .AliasCondStart: 4506, .NumOperands: 4, .NumConds: 8 }, |
| 26976 | // AArch64::ORR_ZI - 709 |
| 26977 | {.AsmStrOffset: 11946, .AliasCondStart: 4514, .NumOperands: 3, .NumConds: 7 }, |
| 26978 | {.AsmStrOffset: 11967, .AliasCondStart: 4521, .NumOperands: 3, .NumConds: 7 }, |
| 26979 | {.AsmStrOffset: 11988, .AliasCondStart: 4528, .NumOperands: 3, .NumConds: 7 }, |
| 26980 | // AArch64::ORR_ZZZ - 712 |
| 26981 | {.AsmStrOffset: 12009, .AliasCondStart: 4535, .NumOperands: 3, .NumConds: 7 }, |
| 26982 | // AArch64::ORRv16i8 - 713 |
| 26983 | {.AsmStrOffset: 12024, .AliasCondStart: 4542, .NumOperands: 3, .NumConds: 6 }, |
| 26984 | // AArch64::ORRv8i8 - 714 |
| 26985 | {.AsmStrOffset: 12047, .AliasCondStart: 4548, .NumOperands: 3, .NumConds: 6 }, |
| 26986 | // AArch64::PACIA1716 - 715 |
| 26987 | {.AsmStrOffset: 12068, .AliasCondStart: 4554, .NumOperands: 0, .NumConds: 3 }, |
| 26988 | // AArch64::PACIASP - 716 |
| 26989 | {.AsmStrOffset: 12078, .AliasCondStart: 4557, .NumOperands: 0, .NumConds: 3 }, |
| 26990 | // AArch64::PACIAZ - 717 |
| 26991 | {.AsmStrOffset: 12086, .AliasCondStart: 4560, .NumOperands: 0, .NumConds: 3 }, |
| 26992 | // AArch64::PACIB1716 - 718 |
| 26993 | {.AsmStrOffset: 12093, .AliasCondStart: 4563, .NumOperands: 0, .NumConds: 3 }, |
| 26994 | // AArch64::PACIBSP - 719 |
| 26995 | {.AsmStrOffset: 12103, .AliasCondStart: 4566, .NumOperands: 0, .NumConds: 3 }, |
| 26996 | // AArch64::PACIBZ - 720 |
| 26997 | {.AsmStrOffset: 12111, .AliasCondStart: 4569, .NumOperands: 0, .NumConds: 3 }, |
| 26998 | // AArch64::PACM - 721 |
| 26999 | {.AsmStrOffset: 12118, .AliasCondStart: 4572, .NumOperands: 0, .NumConds: 3 }, |
| 27000 | // AArch64::PMOV_PZI_B - 722 |
| 27001 | {.AsmStrOffset: 12123, .AliasCondStart: 4575, .NumOperands: 3, .NumConds: 7 }, |
| 27002 | // AArch64::PMOV_ZIP_B - 723 |
| 27003 | {.AsmStrOffset: 12139, .AliasCondStart: 4582, .NumOperands: 4, .NumConds: 8 }, |
| 27004 | // AArch64::PRFB_D_PZI - 724 |
| 27005 | {.AsmStrOffset: 12155, .AliasCondStart: 4590, .NumOperands: 4, .NumConds: 7 }, |
| 27006 | // AArch64::PRFB_PRI - 725 |
| 27007 | {.AsmStrOffset: 12179, .AliasCondStart: 4597, .NumOperands: 4, .NumConds: 8 }, |
| 27008 | // AArch64::PRFB_S_PZI - 726 |
| 27009 | {.AsmStrOffset: 12201, .AliasCondStart: 4605, .NumOperands: 4, .NumConds: 7 }, |
| 27010 | // AArch64::PRFD_D_PZI - 727 |
| 27011 | {.AsmStrOffset: 12225, .AliasCondStart: 4612, .NumOperands: 4, .NumConds: 7 }, |
| 27012 | // AArch64::PRFD_PRI - 728 |
| 27013 | {.AsmStrOffset: 12249, .AliasCondStart: 4619, .NumOperands: 4, .NumConds: 8 }, |
| 27014 | // AArch64::PRFD_S_PZI - 729 |
| 27015 | {.AsmStrOffset: 12271, .AliasCondStart: 4627, .NumOperands: 4, .NumConds: 7 }, |
| 27016 | // AArch64::PRFH_D_PZI - 730 |
| 27017 | {.AsmStrOffset: 12295, .AliasCondStart: 4634, .NumOperands: 4, .NumConds: 7 }, |
| 27018 | // AArch64::PRFH_PRI - 731 |
| 27019 | {.AsmStrOffset: 12319, .AliasCondStart: 4641, .NumOperands: 4, .NumConds: 8 }, |
| 27020 | // AArch64::PRFH_S_PZI - 732 |
| 27021 | {.AsmStrOffset: 12341, .AliasCondStart: 4649, .NumOperands: 4, .NumConds: 7 }, |
| 27022 | // AArch64::PRFMroX - 733 |
| 27023 | {.AsmStrOffset: 12365, .AliasCondStart: 4656, .NumOperands: 5, .NumConds: 5 }, |
| 27024 | // AArch64::PRFMui - 734 |
| 27025 | {.AsmStrOffset: 12385, .AliasCondStart: 4661, .NumOperands: 3, .NumConds: 3 }, |
| 27026 | // AArch64::PRFUMi - 735 |
| 27027 | {.AsmStrOffset: 12401, .AliasCondStart: 4664, .NumOperands: 3, .NumConds: 3 }, |
| 27028 | // AArch64::PRFW_D_PZI - 736 |
| 27029 | {.AsmStrOffset: 12418, .AliasCondStart: 4667, .NumOperands: 4, .NumConds: 7 }, |
| 27030 | // AArch64::PRFW_PRI - 737 |
| 27031 | {.AsmStrOffset: 12442, .AliasCondStart: 4674, .NumOperands: 4, .NumConds: 8 }, |
| 27032 | // AArch64::PRFW_S_PZI - 738 |
| 27033 | {.AsmStrOffset: 12464, .AliasCondStart: 4682, .NumOperands: 4, .NumConds: 7 }, |
| 27034 | // AArch64::PTRUES_B - 739 |
| 27035 | {.AsmStrOffset: 12488, .AliasCondStart: 4689, .NumOperands: 2, .NumConds: 6 }, |
| 27036 | // AArch64::PTRUES_D - 740 |
| 27037 | {.AsmStrOffset: 12500, .AliasCondStart: 4695, .NumOperands: 2, .NumConds: 6 }, |
| 27038 | // AArch64::PTRUES_H - 741 |
| 27039 | {.AsmStrOffset: 12512, .AliasCondStart: 4701, .NumOperands: 2, .NumConds: 6 }, |
| 27040 | // AArch64::PTRUES_S - 742 |
| 27041 | {.AsmStrOffset: 12524, .AliasCondStart: 4707, .NumOperands: 2, .NumConds: 6 }, |
| 27042 | // AArch64::PTRUE_B - 743 |
| 27043 | {.AsmStrOffset: 12536, .AliasCondStart: 4713, .NumOperands: 2, .NumConds: 6 }, |
| 27044 | // AArch64::PTRUE_D - 744 |
| 27045 | {.AsmStrOffset: 12547, .AliasCondStart: 4719, .NumOperands: 2, .NumConds: 6 }, |
| 27046 | // AArch64::PTRUE_H - 745 |
| 27047 | {.AsmStrOffset: 12558, .AliasCondStart: 4725, .NumOperands: 2, .NumConds: 6 }, |
| 27048 | // AArch64::PTRUE_S - 746 |
| 27049 | {.AsmStrOffset: 12569, .AliasCondStart: 4731, .NumOperands: 2, .NumConds: 6 }, |
| 27050 | // AArch64::RET - 747 |
| 27051 | {.AsmStrOffset: 12580, .AliasCondStart: 4737, .NumOperands: 1, .NumConds: 1 }, |
| 27052 | // AArch64::SBCSWr - 748 |
| 27053 | {.AsmStrOffset: 12584, .AliasCondStart: 4738, .NumOperands: 3, .NumConds: 3 }, |
| 27054 | // AArch64::SBCSXr - 749 |
| 27055 | {.AsmStrOffset: 12584, .AliasCondStart: 4741, .NumOperands: 3, .NumConds: 3 }, |
| 27056 | // AArch64::SBCWr - 750 |
| 27057 | {.AsmStrOffset: 12596, .AliasCondStart: 4744, .NumOperands: 3, .NumConds: 3 }, |
| 27058 | // AArch64::SBCXr - 751 |
| 27059 | {.AsmStrOffset: 12596, .AliasCondStart: 4747, .NumOperands: 3, .NumConds: 3 }, |
| 27060 | // AArch64::SBFMWri - 752 |
| 27061 | {.AsmStrOffset: 12607, .AliasCondStart: 4750, .NumOperands: 4, .NumConds: 4 }, |
| 27062 | {.AsmStrOffset: 12622, .AliasCondStart: 4754, .NumOperands: 4, .NumConds: 4 }, |
| 27063 | {.AsmStrOffset: 12634, .AliasCondStart: 4758, .NumOperands: 4, .NumConds: 4 }, |
| 27064 | // AArch64::SBFMXri - 755 |
| 27065 | {.AsmStrOffset: 12607, .AliasCondStart: 4762, .NumOperands: 4, .NumConds: 4 }, |
| 27066 | {.AsmStrOffset: 12622, .AliasCondStart: 4766, .NumOperands: 4, .NumConds: 4 }, |
| 27067 | {.AsmStrOffset: 12634, .AliasCondStart: 4770, .NumOperands: 4, .NumConds: 4 }, |
| 27068 | {.AsmStrOffset: 12646, .AliasCondStart: 4774, .NumOperands: 4, .NumConds: 4 }, |
| 27069 | // AArch64::SEL_PPPP - 759 |
| 27070 | {.AsmStrOffset: 12658, .AliasCondStart: 4778, .NumOperands: 4, .NumConds: 8 }, |
| 27071 | // AArch64::SEL_ZPZZ_B - 760 |
| 27072 | {.AsmStrOffset: 12658, .AliasCondStart: 4786, .NumOperands: 4, .NumConds: 8 }, |
| 27073 | // AArch64::SEL_ZPZZ_D - 761 |
| 27074 | {.AsmStrOffset: 12681, .AliasCondStart: 4794, .NumOperands: 4, .NumConds: 8 }, |
| 27075 | // AArch64::SEL_ZPZZ_H - 762 |
| 27076 | {.AsmStrOffset: 12704, .AliasCondStart: 4802, .NumOperands: 4, .NumConds: 8 }, |
| 27077 | // AArch64::SEL_ZPZZ_S - 763 |
| 27078 | {.AsmStrOffset: 12727, .AliasCondStart: 4810, .NumOperands: 4, .NumConds: 8 }, |
| 27079 | // AArch64::SHUH - 764 |
| 27080 | {.AsmStrOffset: 12750, .AliasCondStart: 4818, .NumOperands: 1, .NumConds: 1 }, |
| 27081 | // AArch64::SMADDLrrr - 765 |
| 27082 | {.AsmStrOffset: 12755, .AliasCondStart: 4819, .NumOperands: 4, .NumConds: 4 }, |
| 27083 | // AArch64::SMSUBLrrr - 766 |
| 27084 | {.AsmStrOffset: 12772, .AliasCondStart: 4823, .NumOperands: 4, .NumConds: 4 }, |
| 27085 | // AArch64::SQDECB_XPiI - 767 |
| 27086 | {.AsmStrOffset: 12790, .AliasCondStart: 4827, .NumOperands: 4, .NumConds: 8 }, |
| 27087 | {.AsmStrOffset: 12800, .AliasCondStart: 4835, .NumOperands: 4, .NumConds: 8 }, |
| 27088 | // AArch64::SQDECB_XPiWdI - 769 |
| 27089 | {.AsmStrOffset: 12816, .AliasCondStart: 4843, .NumOperands: 4, .NumConds: 8 }, |
| 27090 | {.AsmStrOffset: 12832, .AliasCondStart: 4851, .NumOperands: 4, .NumConds: 8 }, |
| 27091 | // AArch64::SQDECD_XPiI - 771 |
| 27092 | {.AsmStrOffset: 12854, .AliasCondStart: 4859, .NumOperands: 4, .NumConds: 8 }, |
| 27093 | {.AsmStrOffset: 12864, .AliasCondStart: 4867, .NumOperands: 4, .NumConds: 8 }, |
| 27094 | // AArch64::SQDECD_XPiWdI - 773 |
| 27095 | {.AsmStrOffset: 12880, .AliasCondStart: 4875, .NumOperands: 4, .NumConds: 8 }, |
| 27096 | {.AsmStrOffset: 12896, .AliasCondStart: 4883, .NumOperands: 4, .NumConds: 8 }, |
| 27097 | // AArch64::SQDECD_ZPiI - 775 |
| 27098 | {.AsmStrOffset: 12918, .AliasCondStart: 4891, .NumOperands: 4, .NumConds: 8 }, |
| 27099 | {.AsmStrOffset: 12930, .AliasCondStart: 4899, .NumOperands: 4, .NumConds: 8 }, |
| 27100 | // AArch64::SQDECH_XPiI - 777 |
| 27101 | {.AsmStrOffset: 12948, .AliasCondStart: 4907, .NumOperands: 4, .NumConds: 8 }, |
| 27102 | {.AsmStrOffset: 12958, .AliasCondStart: 4915, .NumOperands: 4, .NumConds: 8 }, |
| 27103 | // AArch64::SQDECH_XPiWdI - 779 |
| 27104 | {.AsmStrOffset: 12974, .AliasCondStart: 4923, .NumOperands: 4, .NumConds: 8 }, |
| 27105 | {.AsmStrOffset: 12990, .AliasCondStart: 4931, .NumOperands: 4, .NumConds: 8 }, |
| 27106 | // AArch64::SQDECH_ZPiI - 781 |
| 27107 | {.AsmStrOffset: 13012, .AliasCondStart: 4939, .NumOperands: 4, .NumConds: 8 }, |
| 27108 | {.AsmStrOffset: 13024, .AliasCondStart: 4947, .NumOperands: 4, .NumConds: 8 }, |
| 27109 | // AArch64::SQDECW_XPiI - 783 |
| 27110 | {.AsmStrOffset: 13042, .AliasCondStart: 4955, .NumOperands: 4, .NumConds: 8 }, |
| 27111 | {.AsmStrOffset: 13052, .AliasCondStart: 4963, .NumOperands: 4, .NumConds: 8 }, |
| 27112 | // AArch64::SQDECW_XPiWdI - 785 |
| 27113 | {.AsmStrOffset: 13068, .AliasCondStart: 4971, .NumOperands: 4, .NumConds: 8 }, |
| 27114 | {.AsmStrOffset: 13084, .AliasCondStart: 4979, .NumOperands: 4, .NumConds: 8 }, |
| 27115 | // AArch64::SQDECW_ZPiI - 787 |
| 27116 | {.AsmStrOffset: 13106, .AliasCondStart: 4987, .NumOperands: 4, .NumConds: 8 }, |
| 27117 | {.AsmStrOffset: 13118, .AliasCondStart: 4995, .NumOperands: 4, .NumConds: 8 }, |
| 27118 | // AArch64::SQINCB_XPiI - 789 |
| 27119 | {.AsmStrOffset: 13136, .AliasCondStart: 5003, .NumOperands: 4, .NumConds: 8 }, |
| 27120 | {.AsmStrOffset: 13146, .AliasCondStart: 5011, .NumOperands: 4, .NumConds: 8 }, |
| 27121 | // AArch64::SQINCB_XPiWdI - 791 |
| 27122 | {.AsmStrOffset: 13162, .AliasCondStart: 5019, .NumOperands: 4, .NumConds: 8 }, |
| 27123 | {.AsmStrOffset: 13178, .AliasCondStart: 5027, .NumOperands: 4, .NumConds: 8 }, |
| 27124 | // AArch64::SQINCD_XPiI - 793 |
| 27125 | {.AsmStrOffset: 13200, .AliasCondStart: 5035, .NumOperands: 4, .NumConds: 8 }, |
| 27126 | {.AsmStrOffset: 13210, .AliasCondStart: 5043, .NumOperands: 4, .NumConds: 8 }, |
| 27127 | // AArch64::SQINCD_XPiWdI - 795 |
| 27128 | {.AsmStrOffset: 13226, .AliasCondStart: 5051, .NumOperands: 4, .NumConds: 8 }, |
| 27129 | {.AsmStrOffset: 13242, .AliasCondStart: 5059, .NumOperands: 4, .NumConds: 8 }, |
| 27130 | // AArch64::SQINCD_ZPiI - 797 |
| 27131 | {.AsmStrOffset: 13264, .AliasCondStart: 5067, .NumOperands: 4, .NumConds: 8 }, |
| 27132 | {.AsmStrOffset: 13276, .AliasCondStart: 5075, .NumOperands: 4, .NumConds: 8 }, |
| 27133 | // AArch64::SQINCH_XPiI - 799 |
| 27134 | {.AsmStrOffset: 13294, .AliasCondStart: 5083, .NumOperands: 4, .NumConds: 8 }, |
| 27135 | {.AsmStrOffset: 13304, .AliasCondStart: 5091, .NumOperands: 4, .NumConds: 8 }, |
| 27136 | // AArch64::SQINCH_XPiWdI - 801 |
| 27137 | {.AsmStrOffset: 13320, .AliasCondStart: 5099, .NumOperands: 4, .NumConds: 8 }, |
| 27138 | {.AsmStrOffset: 13336, .AliasCondStart: 5107, .NumOperands: 4, .NumConds: 8 }, |
| 27139 | // AArch64::SQINCH_ZPiI - 803 |
| 27140 | {.AsmStrOffset: 13358, .AliasCondStart: 5115, .NumOperands: 4, .NumConds: 8 }, |
| 27141 | {.AsmStrOffset: 13370, .AliasCondStart: 5123, .NumOperands: 4, .NumConds: 8 }, |
| 27142 | // AArch64::SQINCW_XPiI - 805 |
| 27143 | {.AsmStrOffset: 13388, .AliasCondStart: 5131, .NumOperands: 4, .NumConds: 8 }, |
| 27144 | {.AsmStrOffset: 13398, .AliasCondStart: 5139, .NumOperands: 4, .NumConds: 8 }, |
| 27145 | // AArch64::SQINCW_XPiWdI - 807 |
| 27146 | {.AsmStrOffset: 13414, .AliasCondStart: 5147, .NumOperands: 4, .NumConds: 8 }, |
| 27147 | {.AsmStrOffset: 13430, .AliasCondStart: 5155, .NumOperands: 4, .NumConds: 8 }, |
| 27148 | // AArch64::SQINCW_ZPiI - 809 |
| 27149 | {.AsmStrOffset: 13452, .AliasCondStart: 5163, .NumOperands: 4, .NumConds: 8 }, |
| 27150 | {.AsmStrOffset: 13464, .AliasCondStart: 5171, .NumOperands: 4, .NumConds: 8 }, |
| 27151 | // AArch64::SST1B_D_IMM - 811 |
| 27152 | {.AsmStrOffset: 13482, .AliasCondStart: 5179, .NumOperands: 4, .NumConds: 7 }, |
| 27153 | // AArch64::SST1B_S_IMM - 812 |
| 27154 | {.AsmStrOffset: 13506, .AliasCondStart: 5186, .NumOperands: 4, .NumConds: 7 }, |
| 27155 | // AArch64::SST1D_IMM - 813 |
| 27156 | {.AsmStrOffset: 13530, .AliasCondStart: 5193, .NumOperands: 4, .NumConds: 7 }, |
| 27157 | // AArch64::SST1H_D_IMM - 814 |
| 27158 | {.AsmStrOffset: 13554, .AliasCondStart: 5200, .NumOperands: 4, .NumConds: 7 }, |
| 27159 | // AArch64::SST1H_S_IMM - 815 |
| 27160 | {.AsmStrOffset: 13578, .AliasCondStart: 5207, .NumOperands: 4, .NumConds: 7 }, |
| 27161 | // AArch64::SST1Q - 816 |
| 27162 | {.AsmStrOffset: 13602, .AliasCondStart: 5214, .NumOperands: 4, .NumConds: 7 }, |
| 27163 | // AArch64::SST1W_D_IMM - 817 |
| 27164 | {.AsmStrOffset: 13626, .AliasCondStart: 5221, .NumOperands: 4, .NumConds: 7 }, |
| 27165 | // AArch64::SST1W_IMM - 818 |
| 27166 | {.AsmStrOffset: 13650, .AliasCondStart: 5228, .NumOperands: 4, .NumConds: 7 }, |
| 27167 | // AArch64::ST1B_2Z_IMM - 819 |
| 27168 | {.AsmStrOffset: 13674, .AliasCondStart: 5235, .NumOperands: 4, .NumConds: 8 }, |
| 27169 | // AArch64::ST1B_2Z_STRIDED_IMM - 820 |
| 27170 | {.AsmStrOffset: 13696, .AliasCondStart: 5243, .NumOperands: 4, .NumConds: 7 }, |
| 27171 | // AArch64::ST1B_4Z_IMM - 821 |
| 27172 | {.AsmStrOffset: 13674, .AliasCondStart: 5250, .NumOperands: 4, .NumConds: 8 }, |
| 27173 | // AArch64::ST1B_4Z_STRIDED_IMM - 822 |
| 27174 | {.AsmStrOffset: 13718, .AliasCondStart: 5258, .NumOperands: 4, .NumConds: 7 }, |
| 27175 | // AArch64::ST1B_D_IMM - 823 |
| 27176 | {.AsmStrOffset: 13740, .AliasCondStart: 5265, .NumOperands: 4, .NumConds: 8 }, |
| 27177 | // AArch64::ST1B_H_IMM - 824 |
| 27178 | {.AsmStrOffset: 13762, .AliasCondStart: 5273, .NumOperands: 4, .NumConds: 8 }, |
| 27179 | // AArch64::ST1B_IMM - 825 |
| 27180 | {.AsmStrOffset: 13784, .AliasCondStart: 5281, .NumOperands: 4, .NumConds: 8 }, |
| 27181 | // AArch64::ST1B_S_IMM - 826 |
| 27182 | {.AsmStrOffset: 13806, .AliasCondStart: 5289, .NumOperands: 4, .NumConds: 8 }, |
| 27183 | // AArch64::ST1D_2Z_IMM - 827 |
| 27184 | {.AsmStrOffset: 13828, .AliasCondStart: 5297, .NumOperands: 4, .NumConds: 8 }, |
| 27185 | // AArch64::ST1D_2Z_STRIDED_IMM - 828 |
| 27186 | {.AsmStrOffset: 13850, .AliasCondStart: 5305, .NumOperands: 4, .NumConds: 7 }, |
| 27187 | // AArch64::ST1D_4Z_IMM - 829 |
| 27188 | {.AsmStrOffset: 13828, .AliasCondStart: 5312, .NumOperands: 4, .NumConds: 8 }, |
| 27189 | // AArch64::ST1D_4Z_STRIDED_IMM - 830 |
| 27190 | {.AsmStrOffset: 13850, .AliasCondStart: 5320, .NumOperands: 4, .NumConds: 7 }, |
| 27191 | // AArch64::ST1D_IMM - 831 |
| 27192 | {.AsmStrOffset: 13872, .AliasCondStart: 5327, .NumOperands: 4, .NumConds: 8 }, |
| 27193 | // AArch64::ST1D_Q_IMM - 832 |
| 27194 | {.AsmStrOffset: 13894, .AliasCondStart: 5335, .NumOperands: 4, .NumConds: 7 }, |
| 27195 | // AArch64::ST1Fourv16b_POST - 833 |
| 27196 | {.AsmStrOffset: 13916, .AliasCondStart: 5342, .NumOperands: 4, .NumConds: 7 }, |
| 27197 | // AArch64::ST1Fourv1d_POST - 834 |
| 27198 | {.AsmStrOffset: 13936, .AliasCondStart: 5349, .NumOperands: 4, .NumConds: 7 }, |
| 27199 | // AArch64::ST1Fourv2d_POST - 835 |
| 27200 | {.AsmStrOffset: 13956, .AliasCondStart: 5356, .NumOperands: 4, .NumConds: 7 }, |
| 27201 | // AArch64::ST1Fourv2s_POST - 836 |
| 27202 | {.AsmStrOffset: 13976, .AliasCondStart: 5363, .NumOperands: 4, .NumConds: 7 }, |
| 27203 | // AArch64::ST1Fourv4h_POST - 837 |
| 27204 | {.AsmStrOffset: 13996, .AliasCondStart: 5370, .NumOperands: 4, .NumConds: 7 }, |
| 27205 | // AArch64::ST1Fourv4s_POST - 838 |
| 27206 | {.AsmStrOffset: 14016, .AliasCondStart: 5377, .NumOperands: 4, .NumConds: 7 }, |
| 27207 | // AArch64::ST1Fourv8b_POST - 839 |
| 27208 | {.AsmStrOffset: 14036, .AliasCondStart: 5384, .NumOperands: 4, .NumConds: 7 }, |
| 27209 | // AArch64::ST1Fourv8h_POST - 840 |
| 27210 | {.AsmStrOffset: 14056, .AliasCondStart: 5391, .NumOperands: 4, .NumConds: 7 }, |
| 27211 | // AArch64::ST1H_2Z_IMM - 841 |
| 27212 | {.AsmStrOffset: 14076, .AliasCondStart: 5398, .NumOperands: 4, .NumConds: 8 }, |
| 27213 | // AArch64::ST1H_2Z_STRIDED_IMM - 842 |
| 27214 | {.AsmStrOffset: 14098, .AliasCondStart: 5406, .NumOperands: 4, .NumConds: 7 }, |
| 27215 | // AArch64::ST1H_4Z_IMM - 843 |
| 27216 | {.AsmStrOffset: 14076, .AliasCondStart: 5413, .NumOperands: 4, .NumConds: 8 }, |
| 27217 | // AArch64::ST1H_4Z_STRIDED_IMM - 844 |
| 27218 | {.AsmStrOffset: 14120, .AliasCondStart: 5421, .NumOperands: 4, .NumConds: 7 }, |
| 27219 | // AArch64::ST1H_D_IMM - 845 |
| 27220 | {.AsmStrOffset: 14142, .AliasCondStart: 5428, .NumOperands: 4, .NumConds: 8 }, |
| 27221 | // AArch64::ST1H_IMM - 846 |
| 27222 | {.AsmStrOffset: 14164, .AliasCondStart: 5436, .NumOperands: 4, .NumConds: 8 }, |
| 27223 | // AArch64::ST1H_S_IMM - 847 |
| 27224 | {.AsmStrOffset: 14186, .AliasCondStart: 5444, .NumOperands: 4, .NumConds: 8 }, |
| 27225 | // AArch64::ST1Onev16b_POST - 848 |
| 27226 | {.AsmStrOffset: 14208, .AliasCondStart: 5452, .NumOperands: 4, .NumConds: 7 }, |
| 27227 | // AArch64::ST1Onev1d_POST - 849 |
| 27228 | {.AsmStrOffset: 14228, .AliasCondStart: 5459, .NumOperands: 4, .NumConds: 7 }, |
| 27229 | // AArch64::ST1Onev2d_POST - 850 |
| 27230 | {.AsmStrOffset: 14247, .AliasCondStart: 5466, .NumOperands: 4, .NumConds: 7 }, |
| 27231 | // AArch64::ST1Onev2s_POST - 851 |
| 27232 | {.AsmStrOffset: 14267, .AliasCondStart: 5473, .NumOperands: 4, .NumConds: 7 }, |
| 27233 | // AArch64::ST1Onev4h_POST - 852 |
| 27234 | {.AsmStrOffset: 14286, .AliasCondStart: 5480, .NumOperands: 4, .NumConds: 7 }, |
| 27235 | // AArch64::ST1Onev4s_POST - 853 |
| 27236 | {.AsmStrOffset: 14305, .AliasCondStart: 5487, .NumOperands: 4, .NumConds: 7 }, |
| 27237 | // AArch64::ST1Onev8b_POST - 854 |
| 27238 | {.AsmStrOffset: 14325, .AliasCondStart: 5494, .NumOperands: 4, .NumConds: 7 }, |
| 27239 | // AArch64::ST1Onev8h_POST - 855 |
| 27240 | {.AsmStrOffset: 14344, .AliasCondStart: 5501, .NumOperands: 4, .NumConds: 7 }, |
| 27241 | // AArch64::ST1Threev16b_POST - 856 |
| 27242 | {.AsmStrOffset: 14364, .AliasCondStart: 5508, .NumOperands: 4, .NumConds: 7 }, |
| 27243 | // AArch64::ST1Threev1d_POST - 857 |
| 27244 | {.AsmStrOffset: 14384, .AliasCondStart: 5515, .NumOperands: 4, .NumConds: 7 }, |
| 27245 | // AArch64::ST1Threev2d_POST - 858 |
| 27246 | {.AsmStrOffset: 14404, .AliasCondStart: 5522, .NumOperands: 4, .NumConds: 7 }, |
| 27247 | // AArch64::ST1Threev2s_POST - 859 |
| 27248 | {.AsmStrOffset: 14424, .AliasCondStart: 5529, .NumOperands: 4, .NumConds: 7 }, |
| 27249 | // AArch64::ST1Threev4h_POST - 860 |
| 27250 | {.AsmStrOffset: 14444, .AliasCondStart: 5536, .NumOperands: 4, .NumConds: 7 }, |
| 27251 | // AArch64::ST1Threev4s_POST - 861 |
| 27252 | {.AsmStrOffset: 14464, .AliasCondStart: 5543, .NumOperands: 4, .NumConds: 7 }, |
| 27253 | // AArch64::ST1Threev8b_POST - 862 |
| 27254 | {.AsmStrOffset: 14484, .AliasCondStart: 5550, .NumOperands: 4, .NumConds: 7 }, |
| 27255 | // AArch64::ST1Threev8h_POST - 863 |
| 27256 | {.AsmStrOffset: 14504, .AliasCondStart: 5557, .NumOperands: 4, .NumConds: 7 }, |
| 27257 | // AArch64::ST1Twov16b_POST - 864 |
| 27258 | {.AsmStrOffset: 14524, .AliasCondStart: 5564, .NumOperands: 4, .NumConds: 7 }, |
| 27259 | // AArch64::ST1Twov1d_POST - 865 |
| 27260 | {.AsmStrOffset: 14544, .AliasCondStart: 5571, .NumOperands: 4, .NumConds: 7 }, |
| 27261 | // AArch64::ST1Twov2d_POST - 866 |
| 27262 | {.AsmStrOffset: 14564, .AliasCondStart: 5578, .NumOperands: 4, .NumConds: 7 }, |
| 27263 | // AArch64::ST1Twov2s_POST - 867 |
| 27264 | {.AsmStrOffset: 14584, .AliasCondStart: 5585, .NumOperands: 4, .NumConds: 7 }, |
| 27265 | // AArch64::ST1Twov4h_POST - 868 |
| 27266 | {.AsmStrOffset: 14604, .AliasCondStart: 5592, .NumOperands: 4, .NumConds: 7 }, |
| 27267 | // AArch64::ST1Twov4s_POST - 869 |
| 27268 | {.AsmStrOffset: 14624, .AliasCondStart: 5599, .NumOperands: 4, .NumConds: 7 }, |
| 27269 | // AArch64::ST1Twov8b_POST - 870 |
| 27270 | {.AsmStrOffset: 14644, .AliasCondStart: 5606, .NumOperands: 4, .NumConds: 7 }, |
| 27271 | // AArch64::ST1Twov8h_POST - 871 |
| 27272 | {.AsmStrOffset: 14664, .AliasCondStart: 5613, .NumOperands: 4, .NumConds: 7 }, |
| 27273 | // AArch64::ST1W_2Z_IMM - 872 |
| 27274 | {.AsmStrOffset: 14684, .AliasCondStart: 5620, .NumOperands: 4, .NumConds: 8 }, |
| 27275 | // AArch64::ST1W_2Z_STRIDED_IMM - 873 |
| 27276 | {.AsmStrOffset: 14706, .AliasCondStart: 5628, .NumOperands: 4, .NumConds: 7 }, |
| 27277 | // AArch64::ST1W_4Z_IMM - 874 |
| 27278 | {.AsmStrOffset: 14684, .AliasCondStart: 5635, .NumOperands: 4, .NumConds: 8 }, |
| 27279 | // AArch64::ST1W_4Z_STRIDED_IMM - 875 |
| 27280 | {.AsmStrOffset: 14706, .AliasCondStart: 5643, .NumOperands: 4, .NumConds: 7 }, |
| 27281 | // AArch64::ST1W_D_IMM - 876 |
| 27282 | {.AsmStrOffset: 14728, .AliasCondStart: 5650, .NumOperands: 4, .NumConds: 8 }, |
| 27283 | // AArch64::ST1W_IMM - 877 |
| 27284 | {.AsmStrOffset: 14750, .AliasCondStart: 5658, .NumOperands: 4, .NumConds: 8 }, |
| 27285 | // AArch64::ST1W_Q_IMM - 878 |
| 27286 | {.AsmStrOffset: 14772, .AliasCondStart: 5666, .NumOperands: 4, .NumConds: 7 }, |
| 27287 | // AArch64::ST1_MXIPXX_H_B - 879 |
| 27288 | {.AsmStrOffset: 14794, .AliasCondStart: 5673, .NumOperands: 6, .NumConds: 9 }, |
| 27289 | // AArch64::ST1_MXIPXX_H_D - 880 |
| 27290 | {.AsmStrOffset: 14828, .AliasCondStart: 5682, .NumOperands: 6, .NumConds: 9 }, |
| 27291 | // AArch64::ST1_MXIPXX_H_H - 881 |
| 27292 | {.AsmStrOffset: 14862, .AliasCondStart: 5691, .NumOperands: 6, .NumConds: 9 }, |
| 27293 | // AArch64::ST1_MXIPXX_H_Q - 882 |
| 27294 | {.AsmStrOffset: 14896, .AliasCondStart: 5700, .NumOperands: 6, .NumConds: 9 }, |
| 27295 | // AArch64::ST1_MXIPXX_H_S - 883 |
| 27296 | {.AsmStrOffset: 14930, .AliasCondStart: 5709, .NumOperands: 6, .NumConds: 9 }, |
| 27297 | // AArch64::ST1_MXIPXX_V_B - 884 |
| 27298 | {.AsmStrOffset: 14964, .AliasCondStart: 5718, .NumOperands: 6, .NumConds: 9 }, |
| 27299 | // AArch64::ST1_MXIPXX_V_D - 885 |
| 27300 | {.AsmStrOffset: 14998, .AliasCondStart: 5727, .NumOperands: 6, .NumConds: 9 }, |
| 27301 | // AArch64::ST1_MXIPXX_V_H - 886 |
| 27302 | {.AsmStrOffset: 15032, .AliasCondStart: 5736, .NumOperands: 6, .NumConds: 9 }, |
| 27303 | // AArch64::ST1_MXIPXX_V_Q - 887 |
| 27304 | {.AsmStrOffset: 15066, .AliasCondStart: 5745, .NumOperands: 6, .NumConds: 9 }, |
| 27305 | // AArch64::ST1_MXIPXX_V_S - 888 |
| 27306 | {.AsmStrOffset: 15100, .AliasCondStart: 5754, .NumOperands: 6, .NumConds: 9 }, |
| 27307 | // AArch64::ST1i16_POST - 889 |
| 27308 | {.AsmStrOffset: 15134, .AliasCondStart: 5763, .NumOperands: 5, .NumConds: 8 }, |
| 27309 | // AArch64::ST1i32_POST - 890 |
| 27310 | {.AsmStrOffset: 15157, .AliasCondStart: 5771, .NumOperands: 5, .NumConds: 8 }, |
| 27311 | // AArch64::ST1i64_POST - 891 |
| 27312 | {.AsmStrOffset: 15180, .AliasCondStart: 5779, .NumOperands: 5, .NumConds: 8 }, |
| 27313 | // AArch64::ST1i8_POST - 892 |
| 27314 | {.AsmStrOffset: 15203, .AliasCondStart: 5787, .NumOperands: 5, .NumConds: 8 }, |
| 27315 | // AArch64::ST2B_IMM - 893 |
| 27316 | {.AsmStrOffset: 15226, .AliasCondStart: 5795, .NumOperands: 4, .NumConds: 8 }, |
| 27317 | // AArch64::ST2D_IMM - 894 |
| 27318 | {.AsmStrOffset: 15248, .AliasCondStart: 5803, .NumOperands: 4, .NumConds: 8 }, |
| 27319 | // AArch64::ST2Gi - 895 |
| 27320 | {.AsmStrOffset: 15270, .AliasCondStart: 5811, .NumOperands: 3, .NumConds: 6 }, |
| 27321 | // AArch64::ST2H_IMM - 896 |
| 27322 | {.AsmStrOffset: 15284, .AliasCondStart: 5817, .NumOperands: 4, .NumConds: 8 }, |
| 27323 | // AArch64::ST2Q_IMM - 897 |
| 27324 | {.AsmStrOffset: 15306, .AliasCondStart: 5825, .NumOperands: 4, .NumConds: 8 }, |
| 27325 | // AArch64::ST2Twov16b_POST - 898 |
| 27326 | {.AsmStrOffset: 15328, .AliasCondStart: 5833, .NumOperands: 4, .NumConds: 7 }, |
| 27327 | // AArch64::ST2Twov2d_POST - 899 |
| 27328 | {.AsmStrOffset: 15348, .AliasCondStart: 5840, .NumOperands: 4, .NumConds: 7 }, |
| 27329 | // AArch64::ST2Twov2s_POST - 900 |
| 27330 | {.AsmStrOffset: 15368, .AliasCondStart: 5847, .NumOperands: 4, .NumConds: 7 }, |
| 27331 | // AArch64::ST2Twov4h_POST - 901 |
| 27332 | {.AsmStrOffset: 15388, .AliasCondStart: 5854, .NumOperands: 4, .NumConds: 7 }, |
| 27333 | // AArch64::ST2Twov4s_POST - 902 |
| 27334 | {.AsmStrOffset: 15408, .AliasCondStart: 5861, .NumOperands: 4, .NumConds: 7 }, |
| 27335 | // AArch64::ST2Twov8b_POST - 903 |
| 27336 | {.AsmStrOffset: 15428, .AliasCondStart: 5868, .NumOperands: 4, .NumConds: 7 }, |
| 27337 | // AArch64::ST2Twov8h_POST - 904 |
| 27338 | {.AsmStrOffset: 15448, .AliasCondStart: 5875, .NumOperands: 4, .NumConds: 7 }, |
| 27339 | // AArch64::ST2W_IMM - 905 |
| 27340 | {.AsmStrOffset: 15468, .AliasCondStart: 5882, .NumOperands: 4, .NumConds: 8 }, |
| 27341 | // AArch64::ST2i16_POST - 906 |
| 27342 | {.AsmStrOffset: 15490, .AliasCondStart: 5890, .NumOperands: 5, .NumConds: 8 }, |
| 27343 | // AArch64::ST2i32_POST - 907 |
| 27344 | {.AsmStrOffset: 15513, .AliasCondStart: 5898, .NumOperands: 5, .NumConds: 8 }, |
| 27345 | // AArch64::ST2i64_POST - 908 |
| 27346 | {.AsmStrOffset: 15536, .AliasCondStart: 5906, .NumOperands: 5, .NumConds: 8 }, |
| 27347 | // AArch64::ST2i8_POST - 909 |
| 27348 | {.AsmStrOffset: 15560, .AliasCondStart: 5914, .NumOperands: 5, .NumConds: 8 }, |
| 27349 | // AArch64::ST3B_IMM - 910 |
| 27350 | {.AsmStrOffset: 15583, .AliasCondStart: 5922, .NumOperands: 4, .NumConds: 8 }, |
| 27351 | // AArch64::ST3D_IMM - 911 |
| 27352 | {.AsmStrOffset: 15605, .AliasCondStart: 5930, .NumOperands: 4, .NumConds: 8 }, |
| 27353 | // AArch64::ST3H_IMM - 912 |
| 27354 | {.AsmStrOffset: 15627, .AliasCondStart: 5938, .NumOperands: 4, .NumConds: 8 }, |
| 27355 | // AArch64::ST3Q_IMM - 913 |
| 27356 | {.AsmStrOffset: 15649, .AliasCondStart: 5946, .NumOperands: 4, .NumConds: 8 }, |
| 27357 | // AArch64::ST3Threev16b_POST - 914 |
| 27358 | {.AsmStrOffset: 15671, .AliasCondStart: 5954, .NumOperands: 4, .NumConds: 7 }, |
| 27359 | // AArch64::ST3Threev2d_POST - 915 |
| 27360 | {.AsmStrOffset: 15691, .AliasCondStart: 5961, .NumOperands: 4, .NumConds: 7 }, |
| 27361 | // AArch64::ST3Threev2s_POST - 916 |
| 27362 | {.AsmStrOffset: 15711, .AliasCondStart: 5968, .NumOperands: 4, .NumConds: 7 }, |
| 27363 | // AArch64::ST3Threev4h_POST - 917 |
| 27364 | {.AsmStrOffset: 15731, .AliasCondStart: 5975, .NumOperands: 4, .NumConds: 7 }, |
| 27365 | // AArch64::ST3Threev4s_POST - 918 |
| 27366 | {.AsmStrOffset: 15751, .AliasCondStart: 5982, .NumOperands: 4, .NumConds: 7 }, |
| 27367 | // AArch64::ST3Threev8b_POST - 919 |
| 27368 | {.AsmStrOffset: 15771, .AliasCondStart: 5989, .NumOperands: 4, .NumConds: 7 }, |
| 27369 | // AArch64::ST3Threev8h_POST - 920 |
| 27370 | {.AsmStrOffset: 15791, .AliasCondStart: 5996, .NumOperands: 4, .NumConds: 7 }, |
| 27371 | // AArch64::ST3W_IMM - 921 |
| 27372 | {.AsmStrOffset: 15811, .AliasCondStart: 6003, .NumOperands: 4, .NumConds: 8 }, |
| 27373 | // AArch64::ST3i16_POST - 922 |
| 27374 | {.AsmStrOffset: 15833, .AliasCondStart: 6011, .NumOperands: 5, .NumConds: 8 }, |
| 27375 | // AArch64::ST3i32_POST - 923 |
| 27376 | {.AsmStrOffset: 15856, .AliasCondStart: 6019, .NumOperands: 5, .NumConds: 8 }, |
| 27377 | // AArch64::ST3i64_POST - 924 |
| 27378 | {.AsmStrOffset: 15880, .AliasCondStart: 6027, .NumOperands: 5, .NumConds: 8 }, |
| 27379 | // AArch64::ST3i8_POST - 925 |
| 27380 | {.AsmStrOffset: 15904, .AliasCondStart: 6035, .NumOperands: 5, .NumConds: 8 }, |
| 27381 | // AArch64::ST4B_IMM - 926 |
| 27382 | {.AsmStrOffset: 15927, .AliasCondStart: 6043, .NumOperands: 4, .NumConds: 8 }, |
| 27383 | // AArch64::ST4D_IMM - 927 |
| 27384 | {.AsmStrOffset: 15949, .AliasCondStart: 6051, .NumOperands: 4, .NumConds: 8 }, |
| 27385 | // AArch64::ST4Fourv16b_POST - 928 |
| 27386 | {.AsmStrOffset: 15971, .AliasCondStart: 6059, .NumOperands: 4, .NumConds: 7 }, |
| 27387 | // AArch64::ST4Fourv2d_POST - 929 |
| 27388 | {.AsmStrOffset: 15991, .AliasCondStart: 6066, .NumOperands: 4, .NumConds: 7 }, |
| 27389 | // AArch64::ST4Fourv2s_POST - 930 |
| 27390 | {.AsmStrOffset: 16011, .AliasCondStart: 6073, .NumOperands: 4, .NumConds: 7 }, |
| 27391 | // AArch64::ST4Fourv4h_POST - 931 |
| 27392 | {.AsmStrOffset: 16031, .AliasCondStart: 6080, .NumOperands: 4, .NumConds: 7 }, |
| 27393 | // AArch64::ST4Fourv4s_POST - 932 |
| 27394 | {.AsmStrOffset: 16051, .AliasCondStart: 6087, .NumOperands: 4, .NumConds: 7 }, |
| 27395 | // AArch64::ST4Fourv8b_POST - 933 |
| 27396 | {.AsmStrOffset: 16071, .AliasCondStart: 6094, .NumOperands: 4, .NumConds: 7 }, |
| 27397 | // AArch64::ST4Fourv8h_POST - 934 |
| 27398 | {.AsmStrOffset: 16091, .AliasCondStart: 6101, .NumOperands: 4, .NumConds: 7 }, |
| 27399 | // AArch64::ST4H_IMM - 935 |
| 27400 | {.AsmStrOffset: 16111, .AliasCondStart: 6108, .NumOperands: 4, .NumConds: 8 }, |
| 27401 | // AArch64::ST4Q_IMM - 936 |
| 27402 | {.AsmStrOffset: 16133, .AliasCondStart: 6116, .NumOperands: 4, .NumConds: 8 }, |
| 27403 | // AArch64::ST4W_IMM - 937 |
| 27404 | {.AsmStrOffset: 16155, .AliasCondStart: 6124, .NumOperands: 4, .NumConds: 8 }, |
| 27405 | // AArch64::ST4i16_POST - 938 |
| 27406 | {.AsmStrOffset: 16177, .AliasCondStart: 6132, .NumOperands: 5, .NumConds: 8 }, |
| 27407 | // AArch64::ST4i32_POST - 939 |
| 27408 | {.AsmStrOffset: 16200, .AliasCondStart: 6140, .NumOperands: 5, .NumConds: 8 }, |
| 27409 | // AArch64::ST4i64_POST - 940 |
| 27410 | {.AsmStrOffset: 16224, .AliasCondStart: 6148, .NumOperands: 5, .NumConds: 8 }, |
| 27411 | // AArch64::ST4i8_POST - 941 |
| 27412 | {.AsmStrOffset: 16248, .AliasCondStart: 6156, .NumOperands: 5, .NumConds: 8 }, |
| 27413 | // AArch64::STGPi - 942 |
| 27414 | {.AsmStrOffset: 16271, .AliasCondStart: 6164, .NumOperands: 4, .NumConds: 7 }, |
| 27415 | // AArch64::STGi - 943 |
| 27416 | {.AsmStrOffset: 16289, .AliasCondStart: 6171, .NumOperands: 3, .NumConds: 6 }, |
| 27417 | // AArch64::STLPi - 944 |
| 27418 | {.AsmStrOffset: 16302, .AliasCondStart: 6177, .NumOperands: 3, .NumConds: 6 }, |
| 27419 | // AArch64::STLURBi - 945 |
| 27420 | {.AsmStrOffset: 16320, .AliasCondStart: 6183, .NumOperands: 3, .NumConds: 6 }, |
| 27421 | // AArch64::STLURHi - 946 |
| 27422 | {.AsmStrOffset: 16336, .AliasCondStart: 6189, .NumOperands: 3, .NumConds: 6 }, |
| 27423 | // AArch64::STLURWi - 947 |
| 27424 | {.AsmStrOffset: 16352, .AliasCondStart: 6195, .NumOperands: 3, .NumConds: 6 }, |
| 27425 | // AArch64::STLURXi - 948 |
| 27426 | {.AsmStrOffset: 16352, .AliasCondStart: 6201, .NumOperands: 3, .NumConds: 6 }, |
| 27427 | // AArch64::STLURbi - 949 |
| 27428 | {.AsmStrOffset: 16352, .AliasCondStart: 6207, .NumOperands: 3, .NumConds: 9 }, |
| 27429 | // AArch64::STLURdi - 950 |
| 27430 | {.AsmStrOffset: 16352, .AliasCondStart: 6216, .NumOperands: 3, .NumConds: 9 }, |
| 27431 | // AArch64::STLURhi - 951 |
| 27432 | {.AsmStrOffset: 16352, .AliasCondStart: 6225, .NumOperands: 3, .NumConds: 9 }, |
| 27433 | // AArch64::STLURqi - 952 |
| 27434 | {.AsmStrOffset: 16352, .AliasCondStart: 6234, .NumOperands: 3, .NumConds: 9 }, |
| 27435 | // AArch64::STLURsi - 953 |
| 27436 | {.AsmStrOffset: 16352, .AliasCondStart: 6243, .NumOperands: 3, .NumConds: 9 }, |
| 27437 | // AArch64::STNPDi - 954 |
| 27438 | {.AsmStrOffset: 16367, .AliasCondStart: 6252, .NumOperands: 4, .NumConds: 7 }, |
| 27439 | // AArch64::STNPQi - 955 |
| 27440 | {.AsmStrOffset: 16367, .AliasCondStart: 6259, .NumOperands: 4, .NumConds: 7 }, |
| 27441 | // AArch64::STNPSi - 956 |
| 27442 | {.AsmStrOffset: 16367, .AliasCondStart: 6266, .NumOperands: 4, .NumConds: 7 }, |
| 27443 | // AArch64::STNPWi - 957 |
| 27444 | {.AsmStrOffset: 16367, .AliasCondStart: 6273, .NumOperands: 4, .NumConds: 4 }, |
| 27445 | // AArch64::STNPXi - 958 |
| 27446 | {.AsmStrOffset: 16367, .AliasCondStart: 6277, .NumOperands: 4, .NumConds: 4 }, |
| 27447 | // AArch64::STNT1B_2Z_IMM - 959 |
| 27448 | {.AsmStrOffset: 16385, .AliasCondStart: 6281, .NumOperands: 4, .NumConds: 8 }, |
| 27449 | // AArch64::STNT1B_2Z_STRIDED_IMM - 960 |
| 27450 | {.AsmStrOffset: 16409, .AliasCondStart: 6289, .NumOperands: 4, .NumConds: 7 }, |
| 27451 | // AArch64::STNT1B_4Z_IMM - 961 |
| 27452 | {.AsmStrOffset: 16385, .AliasCondStart: 6296, .NumOperands: 4, .NumConds: 8 }, |
| 27453 | // AArch64::STNT1B_4Z_STRIDED_IMM - 962 |
| 27454 | {.AsmStrOffset: 16433, .AliasCondStart: 6304, .NumOperands: 4, .NumConds: 7 }, |
| 27455 | // AArch64::STNT1B_ZRI - 963 |
| 27456 | {.AsmStrOffset: 16457, .AliasCondStart: 6311, .NumOperands: 4, .NumConds: 8 }, |
| 27457 | // AArch64::STNT1B_ZZR_D - 964 |
| 27458 | {.AsmStrOffset: 16481, .AliasCondStart: 6319, .NumOperands: 4, .NumConds: 7 }, |
| 27459 | // AArch64::STNT1B_ZZR_S - 965 |
| 27460 | {.AsmStrOffset: 16507, .AliasCondStart: 6326, .NumOperands: 4, .NumConds: 7 }, |
| 27461 | // AArch64::STNT1D_2Z_IMM - 966 |
| 27462 | {.AsmStrOffset: 16533, .AliasCondStart: 6333, .NumOperands: 4, .NumConds: 8 }, |
| 27463 | // AArch64::STNT1D_2Z_STRIDED_IMM - 967 |
| 27464 | {.AsmStrOffset: 16557, .AliasCondStart: 6341, .NumOperands: 4, .NumConds: 7 }, |
| 27465 | // AArch64::STNT1D_4Z_IMM - 968 |
| 27466 | {.AsmStrOffset: 16533, .AliasCondStart: 6348, .NumOperands: 4, .NumConds: 8 }, |
| 27467 | // AArch64::STNT1D_4Z_STRIDED_IMM - 969 |
| 27468 | {.AsmStrOffset: 16557, .AliasCondStart: 6356, .NumOperands: 4, .NumConds: 7 }, |
| 27469 | // AArch64::STNT1D_ZRI - 970 |
| 27470 | {.AsmStrOffset: 16581, .AliasCondStart: 6363, .NumOperands: 4, .NumConds: 8 }, |
| 27471 | // AArch64::STNT1D_ZZR_D - 971 |
| 27472 | {.AsmStrOffset: 16605, .AliasCondStart: 6371, .NumOperands: 4, .NumConds: 7 }, |
| 27473 | // AArch64::STNT1H_2Z_IMM - 972 |
| 27474 | {.AsmStrOffset: 16631, .AliasCondStart: 6378, .NumOperands: 4, .NumConds: 8 }, |
| 27475 | // AArch64::STNT1H_2Z_STRIDED_IMM - 973 |
| 27476 | {.AsmStrOffset: 16655, .AliasCondStart: 6386, .NumOperands: 4, .NumConds: 7 }, |
| 27477 | // AArch64::STNT1H_4Z_IMM - 974 |
| 27478 | {.AsmStrOffset: 16631, .AliasCondStart: 6393, .NumOperands: 4, .NumConds: 8 }, |
| 27479 | // AArch64::STNT1H_4Z_STRIDED_IMM - 975 |
| 27480 | {.AsmStrOffset: 16679, .AliasCondStart: 6401, .NumOperands: 4, .NumConds: 7 }, |
| 27481 | // AArch64::STNT1H_ZRI - 976 |
| 27482 | {.AsmStrOffset: 16703, .AliasCondStart: 6408, .NumOperands: 4, .NumConds: 8 }, |
| 27483 | // AArch64::STNT1H_ZZR_D - 977 |
| 27484 | {.AsmStrOffset: 16727, .AliasCondStart: 6416, .NumOperands: 4, .NumConds: 7 }, |
| 27485 | // AArch64::STNT1H_ZZR_S - 978 |
| 27486 | {.AsmStrOffset: 16753, .AliasCondStart: 6423, .NumOperands: 4, .NumConds: 7 }, |
| 27487 | // AArch64::STNT1W_2Z_IMM - 979 |
| 27488 | {.AsmStrOffset: 16779, .AliasCondStart: 6430, .NumOperands: 4, .NumConds: 8 }, |
| 27489 | // AArch64::STNT1W_2Z_STRIDED_IMM - 980 |
| 27490 | {.AsmStrOffset: 16803, .AliasCondStart: 6438, .NumOperands: 4, .NumConds: 7 }, |
| 27491 | // AArch64::STNT1W_4Z_IMM - 981 |
| 27492 | {.AsmStrOffset: 16779, .AliasCondStart: 6445, .NumOperands: 4, .NumConds: 8 }, |
| 27493 | // AArch64::STNT1W_4Z_STRIDED_IMM - 982 |
| 27494 | {.AsmStrOffset: 16803, .AliasCondStart: 6453, .NumOperands: 4, .NumConds: 7 }, |
| 27495 | // AArch64::STNT1W_ZRI - 983 |
| 27496 | {.AsmStrOffset: 16827, .AliasCondStart: 6460, .NumOperands: 4, .NumConds: 8 }, |
| 27497 | // AArch64::STNT1W_ZZR_D - 984 |
| 27498 | {.AsmStrOffset: 16851, .AliasCondStart: 6468, .NumOperands: 4, .NumConds: 7 }, |
| 27499 | // AArch64::STNT1W_ZZR_S - 985 |
| 27500 | {.AsmStrOffset: 16877, .AliasCondStart: 6475, .NumOperands: 4, .NumConds: 7 }, |
| 27501 | // AArch64::STPDi - 986 |
| 27502 | {.AsmStrOffset: 16903, .AliasCondStart: 6482, .NumOperands: 4, .NumConds: 7 }, |
| 27503 | // AArch64::STPQi - 987 |
| 27504 | {.AsmStrOffset: 16903, .AliasCondStart: 6489, .NumOperands: 4, .NumConds: 7 }, |
| 27505 | // AArch64::STPSi - 988 |
| 27506 | {.AsmStrOffset: 16903, .AliasCondStart: 6496, .NumOperands: 4, .NumConds: 7 }, |
| 27507 | // AArch64::STPWi - 989 |
| 27508 | {.AsmStrOffset: 16903, .AliasCondStart: 6503, .NumOperands: 4, .NumConds: 4 }, |
| 27509 | // AArch64::STPXi - 990 |
| 27510 | {.AsmStrOffset: 16903, .AliasCondStart: 6507, .NumOperands: 4, .NumConds: 4 }, |
| 27511 | // AArch64::STRBBroX - 991 |
| 27512 | {.AsmStrOffset: 16920, .AliasCondStart: 6511, .NumOperands: 5, .NumConds: 5 }, |
| 27513 | // AArch64::STRBBui - 992 |
| 27514 | {.AsmStrOffset: 16938, .AliasCondStart: 6516, .NumOperands: 3, .NumConds: 3 }, |
| 27515 | // AArch64::STRBroX - 993 |
| 27516 | {.AsmStrOffset: 16952, .AliasCondStart: 6519, .NumOperands: 5, .NumConds: 8 }, |
| 27517 | // AArch64::STRBui - 994 |
| 27518 | {.AsmStrOffset: 16969, .AliasCondStart: 6527, .NumOperands: 3, .NumConds: 6 }, |
| 27519 | // AArch64::STRDroX - 995 |
| 27520 | {.AsmStrOffset: 16952, .AliasCondStart: 6533, .NumOperands: 5, .NumConds: 8 }, |
| 27521 | // AArch64::STRDui - 996 |
| 27522 | {.AsmStrOffset: 16969, .AliasCondStart: 6541, .NumOperands: 3, .NumConds: 6 }, |
| 27523 | // AArch64::STRHHroX - 997 |
| 27524 | {.AsmStrOffset: 16982, .AliasCondStart: 6547, .NumOperands: 5, .NumConds: 5 }, |
| 27525 | // AArch64::STRHHui - 998 |
| 27526 | {.AsmStrOffset: 17000, .AliasCondStart: 6552, .NumOperands: 3, .NumConds: 3 }, |
| 27527 | // AArch64::STRHroX - 999 |
| 27528 | {.AsmStrOffset: 16952, .AliasCondStart: 6555, .NumOperands: 5, .NumConds: 8 }, |
| 27529 | // AArch64::STRHui - 1000 |
| 27530 | {.AsmStrOffset: 16969, .AliasCondStart: 6563, .NumOperands: 3, .NumConds: 6 }, |
| 27531 | // AArch64::STRQroX - 1001 |
| 27532 | {.AsmStrOffset: 16952, .AliasCondStart: 6569, .NumOperands: 5, .NumConds: 8 }, |
| 27533 | // AArch64::STRQui - 1002 |
| 27534 | {.AsmStrOffset: 16969, .AliasCondStart: 6577, .NumOperands: 3, .NumConds: 6 }, |
| 27535 | // AArch64::STRSroX - 1003 |
| 27536 | {.AsmStrOffset: 16952, .AliasCondStart: 6583, .NumOperands: 5, .NumConds: 8 }, |
| 27537 | // AArch64::STRSui - 1004 |
| 27538 | {.AsmStrOffset: 16969, .AliasCondStart: 6591, .NumOperands: 3, .NumConds: 6 }, |
| 27539 | // AArch64::STRWroX - 1005 |
| 27540 | {.AsmStrOffset: 16952, .AliasCondStart: 6597, .NumOperands: 5, .NumConds: 5 }, |
| 27541 | // AArch64::STRWui - 1006 |
| 27542 | {.AsmStrOffset: 16969, .AliasCondStart: 6602, .NumOperands: 3, .NumConds: 3 }, |
| 27543 | // AArch64::STRXroX - 1007 |
| 27544 | {.AsmStrOffset: 16952, .AliasCondStart: 6605, .NumOperands: 5, .NumConds: 5 }, |
| 27545 | // AArch64::STRXui - 1008 |
| 27546 | {.AsmStrOffset: 16969, .AliasCondStart: 6610, .NumOperands: 3, .NumConds: 3 }, |
| 27547 | // AArch64::STR_PXI - 1009 |
| 27548 | {.AsmStrOffset: 17014, .AliasCondStart: 6613, .NumOperands: 3, .NumConds: 7 }, |
| 27549 | // AArch64::STR_ZA - 1010 |
| 27550 | {.AsmStrOffset: 17029, .AliasCondStart: 6620, .NumOperands: 5, .NumConds: 8 }, |
| 27551 | // AArch64::STR_ZXI - 1011 |
| 27552 | {.AsmStrOffset: 17014, .AliasCondStart: 6628, .NumOperands: 3, .NumConds: 7 }, |
| 27553 | // AArch64::STTNPQi - 1012 |
| 27554 | {.AsmStrOffset: 17054, .AliasCondStart: 6635, .NumOperands: 4, .NumConds: 10 }, |
| 27555 | // AArch64::STTNPXi - 1013 |
| 27556 | {.AsmStrOffset: 17054, .AliasCondStart: 6645, .NumOperands: 4, .NumConds: 7 }, |
| 27557 | // AArch64::STTPQi - 1014 |
| 27558 | {.AsmStrOffset: 17073, .AliasCondStart: 6652, .NumOperands: 4, .NumConds: 10 }, |
| 27559 | // AArch64::STTPi - 1015 |
| 27560 | {.AsmStrOffset: 17073, .AliasCondStart: 6662, .NumOperands: 4, .NumConds: 7 }, |
| 27561 | // AArch64::STTRBi - 1016 |
| 27562 | {.AsmStrOffset: 17091, .AliasCondStart: 6669, .NumOperands: 3, .NumConds: 3 }, |
| 27563 | // AArch64::STTRHi - 1017 |
| 27564 | {.AsmStrOffset: 17106, .AliasCondStart: 6672, .NumOperands: 3, .NumConds: 3 }, |
| 27565 | // AArch64::STTRWi - 1018 |
| 27566 | {.AsmStrOffset: 17121, .AliasCondStart: 6675, .NumOperands: 3, .NumConds: 3 }, |
| 27567 | // AArch64::STTRXi - 1019 |
| 27568 | {.AsmStrOffset: 17121, .AliasCondStart: 6678, .NumOperands: 3, .NumConds: 3 }, |
| 27569 | // AArch64::STURBBi - 1020 |
| 27570 | {.AsmStrOffset: 17135, .AliasCondStart: 6681, .NumOperands: 3, .NumConds: 3 }, |
| 27571 | // AArch64::STURBi - 1021 |
| 27572 | {.AsmStrOffset: 17150, .AliasCondStart: 6684, .NumOperands: 3, .NumConds: 6 }, |
| 27573 | // AArch64::STURDi - 1022 |
| 27574 | {.AsmStrOffset: 17150, .AliasCondStart: 6690, .NumOperands: 3, .NumConds: 6 }, |
| 27575 | // AArch64::STURHHi - 1023 |
| 27576 | {.AsmStrOffset: 17164, .AliasCondStart: 6696, .NumOperands: 3, .NumConds: 3 }, |
| 27577 | // AArch64::STURHi - 1024 |
| 27578 | {.AsmStrOffset: 17150, .AliasCondStart: 6699, .NumOperands: 3, .NumConds: 6 }, |
| 27579 | // AArch64::STURQi - 1025 |
| 27580 | {.AsmStrOffset: 17150, .AliasCondStart: 6705, .NumOperands: 3, .NumConds: 6 }, |
| 27581 | // AArch64::STURSi - 1026 |
| 27582 | {.AsmStrOffset: 17150, .AliasCondStart: 6711, .NumOperands: 3, .NumConds: 6 }, |
| 27583 | // AArch64::STURWi - 1027 |
| 27584 | {.AsmStrOffset: 17150, .AliasCondStart: 6717, .NumOperands: 3, .NumConds: 3 }, |
| 27585 | // AArch64::STURXi - 1028 |
| 27586 | {.AsmStrOffset: 17150, .AliasCondStart: 6720, .NumOperands: 3, .NumConds: 3 }, |
| 27587 | // AArch64::STZ2Gi - 1029 |
| 27588 | {.AsmStrOffset: 17179, .AliasCondStart: 6723, .NumOperands: 3, .NumConds: 6 }, |
| 27589 | // AArch64::STZGi - 1030 |
| 27590 | {.AsmStrOffset: 17194, .AliasCondStart: 6729, .NumOperands: 3, .NumConds: 6 }, |
| 27591 | // AArch64::SUBPT_shift - 1031 |
| 27592 | {.AsmStrOffset: 17208, .AliasCondStart: 6735, .NumOperands: 4, .NumConds: 7 }, |
| 27593 | // AArch64::SUBSWri - 1032 |
| 27594 | {.AsmStrOffset: 17225, .AliasCondStart: 6742, .NumOperands: 4, .NumConds: 2 }, |
| 27595 | // AArch64::SUBSWrs - 1033 |
| 27596 | {.AsmStrOffset: 17238, .AliasCondStart: 6744, .NumOperands: 4, .NumConds: 4 }, |
| 27597 | {.AsmStrOffset: 17249, .AliasCondStart: 6748, .NumOperands: 4, .NumConds: 3 }, |
| 27598 | {.AsmStrOffset: 17264, .AliasCondStart: 6751, .NumOperands: 4, .NumConds: 4 }, |
| 27599 | {.AsmStrOffset: 17276, .AliasCondStart: 6755, .NumOperands: 4, .NumConds: 3 }, |
| 27600 | {.AsmStrOffset: 17292, .AliasCondStart: 6758, .NumOperands: 4, .NumConds: 4 }, |
| 27601 | // AArch64::SUBSWrx - 1038 |
| 27602 | {.AsmStrOffset: 17238, .AliasCondStart: 6762, .NumOperands: 4, .NumConds: 4 }, |
| 27603 | {.AsmStrOffset: 17308, .AliasCondStart: 6766, .NumOperands: 4, .NumConds: 3 }, |
| 27604 | {.AsmStrOffset: 17292, .AliasCondStart: 6769, .NumOperands: 4, .NumConds: 4 }, |
| 27605 | // AArch64::SUBSXri - 1041 |
| 27606 | {.AsmStrOffset: 17225, .AliasCondStart: 6773, .NumOperands: 4, .NumConds: 2 }, |
| 27607 | // AArch64::SUBSXrs - 1042 |
| 27608 | {.AsmStrOffset: 17238, .AliasCondStart: 6775, .NumOperands: 4, .NumConds: 4 }, |
| 27609 | {.AsmStrOffset: 17249, .AliasCondStart: 6779, .NumOperands: 4, .NumConds: 3 }, |
| 27610 | {.AsmStrOffset: 17264, .AliasCondStart: 6782, .NumOperands: 4, .NumConds: 4 }, |
| 27611 | {.AsmStrOffset: 17276, .AliasCondStart: 6786, .NumOperands: 4, .NumConds: 3 }, |
| 27612 | {.AsmStrOffset: 17292, .AliasCondStart: 6789, .NumOperands: 4, .NumConds: 4 }, |
| 27613 | // AArch64::SUBSXrx - 1047 |
| 27614 | {.AsmStrOffset: 17308, .AliasCondStart: 6793, .NumOperands: 4, .NumConds: 3 }, |
| 27615 | // AArch64::SUBSXrx64 - 1048 |
| 27616 | {.AsmStrOffset: 17238, .AliasCondStart: 6796, .NumOperands: 4, .NumConds: 4 }, |
| 27617 | {.AsmStrOffset: 17308, .AliasCondStart: 6800, .NumOperands: 4, .NumConds: 3 }, |
| 27618 | {.AsmStrOffset: 17292, .AliasCondStart: 6803, .NumOperands: 4, .NumConds: 4 }, |
| 27619 | // AArch64::SUBWrs - 1051 |
| 27620 | {.AsmStrOffset: 17323, .AliasCondStart: 6807, .NumOperands: 4, .NumConds: 4 }, |
| 27621 | {.AsmStrOffset: 17334, .AliasCondStart: 6811, .NumOperands: 4, .NumConds: 3 }, |
| 27622 | {.AsmStrOffset: 17349, .AliasCondStart: 6814, .NumOperands: 4, .NumConds: 4 }, |
| 27623 | // AArch64::SUBWrx - 1054 |
| 27624 | {.AsmStrOffset: 17349, .AliasCondStart: 6818, .NumOperands: 4, .NumConds: 4 }, |
| 27625 | {.AsmStrOffset: 17349, .AliasCondStart: 6822, .NumOperands: 4, .NumConds: 4 }, |
| 27626 | // AArch64::SUBXrs - 1056 |
| 27627 | {.AsmStrOffset: 17323, .AliasCondStart: 6826, .NumOperands: 4, .NumConds: 4 }, |
| 27628 | {.AsmStrOffset: 17334, .AliasCondStart: 6830, .NumOperands: 4, .NumConds: 3 }, |
| 27629 | {.AsmStrOffset: 17349, .AliasCondStart: 6833, .NumOperands: 4, .NumConds: 4 }, |
| 27630 | // AArch64::SUBXrx64 - 1059 |
| 27631 | {.AsmStrOffset: 17349, .AliasCondStart: 6837, .NumOperands: 4, .NumConds: 4 }, |
| 27632 | {.AsmStrOffset: 17349, .AliasCondStart: 6841, .NumOperands: 4, .NumConds: 4 }, |
| 27633 | // AArch64::SYSPxt_XZR - 1061 |
| 27634 | {.AsmStrOffset: 17364, .AliasCondStart: 6845, .NumOperands: 5, .NumConds: 5 }, |
| 27635 | // AArch64::SYSxt - 1062 |
| 27636 | {.AsmStrOffset: 17388, .AliasCondStart: 6850, .NumOperands: 5, .NumConds: 5 }, |
| 27637 | // AArch64::TCHANGEBri - 1063 |
| 27638 | {.AsmStrOffset: 17411, .AliasCondStart: 6855, .NumOperands: 3, .NumConds: 6 }, |
| 27639 | // AArch64::TCHANGEBrr - 1064 |
| 27640 | {.AsmStrOffset: 17429, .AliasCondStart: 6861, .NumOperands: 3, .NumConds: 6 }, |
| 27641 | // AArch64::TCHANGEFri - 1065 |
| 27642 | {.AsmStrOffset: 17445, .AliasCondStart: 6867, .NumOperands: 3, .NumConds: 6 }, |
| 27643 | // AArch64::TCHANGEFrr - 1066 |
| 27644 | {.AsmStrOffset: 17463, .AliasCondStart: 6873, .NumOperands: 3, .NumConds: 6 }, |
| 27645 | // AArch64::TENTER - 1067 |
| 27646 | {.AsmStrOffset: 17479, .AliasCondStart: 6879, .NumOperands: 2, .NumConds: 5 }, |
| 27647 | // AArch64::TEXIT - 1068 |
| 27648 | {.AsmStrOffset: 17491, .AliasCondStart: 6884, .NumOperands: 1, .NumConds: 4 }, |
| 27649 | // AArch64::UBFMWri - 1069 |
| 27650 | {.AsmStrOffset: 17497, .AliasCondStart: 6888, .NumOperands: 4, .NumConds: 4 }, |
| 27651 | {.AsmStrOffset: 17512, .AliasCondStart: 6892, .NumOperands: 4, .NumConds: 4 }, |
| 27652 | {.AsmStrOffset: 17524, .AliasCondStart: 6896, .NumOperands: 4, .NumConds: 4 }, |
| 27653 | // AArch64::UBFMXri - 1072 |
| 27654 | {.AsmStrOffset: 17497, .AliasCondStart: 6900, .NumOperands: 4, .NumConds: 4 }, |
| 27655 | {.AsmStrOffset: 17512, .AliasCondStart: 6904, .NumOperands: 4, .NumConds: 4 }, |
| 27656 | {.AsmStrOffset: 17524, .AliasCondStart: 6908, .NumOperands: 4, .NumConds: 4 }, |
| 27657 | {.AsmStrOffset: 17536, .AliasCondStart: 6912, .NumOperands: 4, .NumConds: 4 }, |
| 27658 | // AArch64::UMADDLrrr - 1076 |
| 27659 | {.AsmStrOffset: 17548, .AliasCondStart: 6916, .NumOperands: 4, .NumConds: 4 }, |
| 27660 | // AArch64::UMOVvi32 - 1077 |
| 27661 | {.AsmStrOffset: 17565, .AliasCondStart: 6920, .NumOperands: 3, .NumConds: 5 }, |
| 27662 | // AArch64::UMOVvi32_idx0 - 1078 |
| 27663 | {.AsmStrOffset: 17565, .AliasCondStart: 6925, .NumOperands: 3, .NumConds: 5 }, |
| 27664 | // AArch64::UMOVvi64 - 1079 |
| 27665 | {.AsmStrOffset: 17584, .AliasCondStart: 6930, .NumOperands: 3, .NumConds: 5 }, |
| 27666 | // AArch64::UMOVvi64_idx0 - 1080 |
| 27667 | {.AsmStrOffset: 17584, .AliasCondStart: 6935, .NumOperands: 3, .NumConds: 5 }, |
| 27668 | // AArch64::UMSUBLrrr - 1081 |
| 27669 | {.AsmStrOffset: 17603, .AliasCondStart: 6940, .NumOperands: 4, .NumConds: 4 }, |
| 27670 | // AArch64::UQDECB_WPiI - 1082 |
| 27671 | {.AsmStrOffset: 17621, .AliasCondStart: 6944, .NumOperands: 4, .NumConds: 8 }, |
| 27672 | {.AsmStrOffset: 17631, .AliasCondStart: 6952, .NumOperands: 4, .NumConds: 8 }, |
| 27673 | // AArch64::UQDECB_XPiI - 1084 |
| 27674 | {.AsmStrOffset: 17621, .AliasCondStart: 6960, .NumOperands: 4, .NumConds: 8 }, |
| 27675 | {.AsmStrOffset: 17631, .AliasCondStart: 6968, .NumOperands: 4, .NumConds: 8 }, |
| 27676 | // AArch64::UQDECD_WPiI - 1086 |
| 27677 | {.AsmStrOffset: 17647, .AliasCondStart: 6976, .NumOperands: 4, .NumConds: 8 }, |
| 27678 | {.AsmStrOffset: 17657, .AliasCondStart: 6984, .NumOperands: 4, .NumConds: 8 }, |
| 27679 | // AArch64::UQDECD_XPiI - 1088 |
| 27680 | {.AsmStrOffset: 17647, .AliasCondStart: 6992, .NumOperands: 4, .NumConds: 8 }, |
| 27681 | {.AsmStrOffset: 17657, .AliasCondStart: 7000, .NumOperands: 4, .NumConds: 8 }, |
| 27682 | // AArch64::UQDECD_ZPiI - 1090 |
| 27683 | {.AsmStrOffset: 17673, .AliasCondStart: 7008, .NumOperands: 4, .NumConds: 8 }, |
| 27684 | {.AsmStrOffset: 17685, .AliasCondStart: 7016, .NumOperands: 4, .NumConds: 8 }, |
| 27685 | // AArch64::UQDECH_WPiI - 1092 |
| 27686 | {.AsmStrOffset: 17703, .AliasCondStart: 7024, .NumOperands: 4, .NumConds: 8 }, |
| 27687 | {.AsmStrOffset: 17713, .AliasCondStart: 7032, .NumOperands: 4, .NumConds: 8 }, |
| 27688 | // AArch64::UQDECH_XPiI - 1094 |
| 27689 | {.AsmStrOffset: 17703, .AliasCondStart: 7040, .NumOperands: 4, .NumConds: 8 }, |
| 27690 | {.AsmStrOffset: 17713, .AliasCondStart: 7048, .NumOperands: 4, .NumConds: 8 }, |
| 27691 | // AArch64::UQDECH_ZPiI - 1096 |
| 27692 | {.AsmStrOffset: 17729, .AliasCondStart: 7056, .NumOperands: 4, .NumConds: 8 }, |
| 27693 | {.AsmStrOffset: 17741, .AliasCondStart: 7064, .NumOperands: 4, .NumConds: 8 }, |
| 27694 | // AArch64::UQDECW_WPiI - 1098 |
| 27695 | {.AsmStrOffset: 17759, .AliasCondStart: 7072, .NumOperands: 4, .NumConds: 8 }, |
| 27696 | {.AsmStrOffset: 17769, .AliasCondStart: 7080, .NumOperands: 4, .NumConds: 8 }, |
| 27697 | // AArch64::UQDECW_XPiI - 1100 |
| 27698 | {.AsmStrOffset: 17759, .AliasCondStart: 7088, .NumOperands: 4, .NumConds: 8 }, |
| 27699 | {.AsmStrOffset: 17769, .AliasCondStart: 7096, .NumOperands: 4, .NumConds: 8 }, |
| 27700 | // AArch64::UQDECW_ZPiI - 1102 |
| 27701 | {.AsmStrOffset: 17785, .AliasCondStart: 7104, .NumOperands: 4, .NumConds: 8 }, |
| 27702 | {.AsmStrOffset: 17797, .AliasCondStart: 7112, .NumOperands: 4, .NumConds: 8 }, |
| 27703 | // AArch64::UQINCB_WPiI - 1104 |
| 27704 | {.AsmStrOffset: 17815, .AliasCondStart: 7120, .NumOperands: 4, .NumConds: 8 }, |
| 27705 | {.AsmStrOffset: 17825, .AliasCondStart: 7128, .NumOperands: 4, .NumConds: 8 }, |
| 27706 | // AArch64::UQINCB_XPiI - 1106 |
| 27707 | {.AsmStrOffset: 17815, .AliasCondStart: 7136, .NumOperands: 4, .NumConds: 8 }, |
| 27708 | {.AsmStrOffset: 17825, .AliasCondStart: 7144, .NumOperands: 4, .NumConds: 8 }, |
| 27709 | // AArch64::UQINCD_WPiI - 1108 |
| 27710 | {.AsmStrOffset: 17841, .AliasCondStart: 7152, .NumOperands: 4, .NumConds: 8 }, |
| 27711 | {.AsmStrOffset: 17851, .AliasCondStart: 7160, .NumOperands: 4, .NumConds: 8 }, |
| 27712 | // AArch64::UQINCD_XPiI - 1110 |
| 27713 | {.AsmStrOffset: 17841, .AliasCondStart: 7168, .NumOperands: 4, .NumConds: 8 }, |
| 27714 | {.AsmStrOffset: 17851, .AliasCondStart: 7176, .NumOperands: 4, .NumConds: 8 }, |
| 27715 | // AArch64::UQINCD_ZPiI - 1112 |
| 27716 | {.AsmStrOffset: 17867, .AliasCondStart: 7184, .NumOperands: 4, .NumConds: 8 }, |
| 27717 | {.AsmStrOffset: 17879, .AliasCondStart: 7192, .NumOperands: 4, .NumConds: 8 }, |
| 27718 | // AArch64::UQINCH_WPiI - 1114 |
| 27719 | {.AsmStrOffset: 17897, .AliasCondStart: 7200, .NumOperands: 4, .NumConds: 8 }, |
| 27720 | {.AsmStrOffset: 17907, .AliasCondStart: 7208, .NumOperands: 4, .NumConds: 8 }, |
| 27721 | // AArch64::UQINCH_XPiI - 1116 |
| 27722 | {.AsmStrOffset: 17897, .AliasCondStart: 7216, .NumOperands: 4, .NumConds: 8 }, |
| 27723 | {.AsmStrOffset: 17907, .AliasCondStart: 7224, .NumOperands: 4, .NumConds: 8 }, |
| 27724 | // AArch64::UQINCH_ZPiI - 1118 |
| 27725 | {.AsmStrOffset: 17923, .AliasCondStart: 7232, .NumOperands: 4, .NumConds: 8 }, |
| 27726 | {.AsmStrOffset: 17935, .AliasCondStart: 7240, .NumOperands: 4, .NumConds: 8 }, |
| 27727 | // AArch64::UQINCW_WPiI - 1120 |
| 27728 | {.AsmStrOffset: 17953, .AliasCondStart: 7248, .NumOperands: 4, .NumConds: 8 }, |
| 27729 | {.AsmStrOffset: 17963, .AliasCondStart: 7256, .NumOperands: 4, .NumConds: 8 }, |
| 27730 | // AArch64::UQINCW_XPiI - 1122 |
| 27731 | {.AsmStrOffset: 17953, .AliasCondStart: 7264, .NumOperands: 4, .NumConds: 8 }, |
| 27732 | {.AsmStrOffset: 17963, .AliasCondStart: 7272, .NumOperands: 4, .NumConds: 8 }, |
| 27733 | // AArch64::UQINCW_ZPiI - 1124 |
| 27734 | {.AsmStrOffset: 17979, .AliasCondStart: 7280, .NumOperands: 4, .NumConds: 8 }, |
| 27735 | {.AsmStrOffset: 17991, .AliasCondStart: 7288, .NumOperands: 4, .NumConds: 8 }, |
| 27736 | // AArch64::XPACLRI - 1126 |
| 27737 | {.AsmStrOffset: 18009, .AliasCondStart: 7296, .NumOperands: 0, .NumConds: 3 }, |
| 27738 | // AArch64::ZERO_M - 1127 |
| 27739 | {.AsmStrOffset: 18017, .AliasCondStart: 7299, .NumOperands: 1, .NumConds: 4 }, |
| 27740 | {.AsmStrOffset: 18027, .AliasCondStart: 7303, .NumOperands: 1, .NumConds: 4 }, |
| 27741 | {.AsmStrOffset: 18040, .AliasCondStart: 7307, .NumOperands: 1, .NumConds: 4 }, |
| 27742 | {.AsmStrOffset: 18053, .AliasCondStart: 7311, .NumOperands: 1, .NumConds: 4 }, |
| 27743 | {.AsmStrOffset: 18066, .AliasCondStart: 7315, .NumOperands: 1, .NumConds: 4 }, |
| 27744 | {.AsmStrOffset: 18079, .AliasCondStart: 7319, .NumOperands: 1, .NumConds: 4 }, |
| 27745 | {.AsmStrOffset: 18092, .AliasCondStart: 7323, .NumOperands: 1, .NumConds: 4 }, |
| 27746 | {.AsmStrOffset: 18105, .AliasCondStart: 7327, .NumOperands: 1, .NumConds: 4 }, |
| 27747 | {.AsmStrOffset: 18124, .AliasCondStart: 7331, .NumOperands: 1, .NumConds: 4 }, |
| 27748 | {.AsmStrOffset: 18143, .AliasCondStart: 7335, .NumOperands: 1, .NumConds: 4 }, |
| 27749 | {.AsmStrOffset: 18162, .AliasCondStart: 7339, .NumOperands: 1, .NumConds: 4 }, |
| 27750 | {.AsmStrOffset: 18181, .AliasCondStart: 7343, .NumOperands: 1, .NumConds: 4 }, |
| 27751 | {.AsmStrOffset: 18206, .AliasCondStart: 7347, .NumOperands: 1, .NumConds: 4 }, |
| 27752 | {.AsmStrOffset: 18231, .AliasCondStart: 7351, .NumOperands: 1, .NumConds: 4 }, |
| 27753 | {.AsmStrOffset: 18256, .AliasCondStart: 7355, .NumOperands: 1, .NumConds: 4 }, |
| 27754 | }; |
| 27755 | |
| 27756 | static const AliasPatternCond Conds[] = { |
| 27757 | // (ADDPT_shift GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0) - 0 |
| 27758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27759 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27760 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27761 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27763 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCPA}, |
| 27764 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27765 | // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 7 |
| 27766 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 27767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 27768 | // (ADDSWrs WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 9 |
| 27769 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 27770 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27771 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27772 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27773 | // (ADDSWrs WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, arith_shift32:$sh)) - 13 |
| 27774 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 27775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27776 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27777 | // (ADDSWrs GPR32:$dst, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 16 |
| 27778 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27780 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27781 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27782 | // (ADDSWrx WZR, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 20 |
| 27783 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 27784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 27785 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27786 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 27787 | // (ADDSWrx WZR, GPR32sp:$src1, (arith_extended_reg32_i32 GPR32:$src2, arith_extend:$sh)) - 24 |
| 27788 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 27789 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 27790 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27791 | // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 27 |
| 27792 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 27794 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27795 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 27796 | // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 31 |
| 27797 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27799 | // (ADDSXrs XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 33 |
| 27800 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27801 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27803 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27804 | // (ADDSXrs XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, arith_shift64:$sh)) - 37 |
| 27805 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27807 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27808 | // (ADDSXrs GPR64:$dst, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 40 |
| 27809 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27810 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27812 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27813 | // (ADDSXrx XZR, GPR64sp:$src1, (arith_extended_reg32_i64 GPR32:$src2, arith_extend:$sh)) - 44 |
| 27814 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27815 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27816 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27817 | // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 47 |
| 27818 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27819 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 27820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27821 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 27822 | // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 51 |
| 27823 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27824 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27825 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27826 | // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 54 |
| 27827 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 27829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27830 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 27831 | // (ADDWri GPR32sponly:$dst, GPR32sp:$src, (addsub_shifted_imm32 0, 0)) - 58 |
| 27832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 27833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 27834 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27835 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27836 | // (ADDWri GPR32sp:$dst, GPR32sponly:$src, (addsub_shifted_imm32 0, 0)) - 62 |
| 27837 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 27838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 27839 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27840 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27841 | // (ADDWrs GPR32:$dst, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 66 |
| 27842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27843 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27844 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27845 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27846 | // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 70 |
| 27847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 27848 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 27849 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27850 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 27851 | // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 74 |
| 27852 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 27853 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 27854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27855 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 27856 | // (ADDXri GPR64sponly:$dst, GPR64sp:$src, (addsub_shifted_imm64 0, 0)) - 78 |
| 27857 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 27858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27859 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27860 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27861 | // (ADDXri GPR64sp:$dst, GPR64sponly:$src, (addsub_shifted_imm64 0, 0)) - 82 |
| 27862 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 27864 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27865 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27866 | // (ADDXrs GPR64:$dst, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 86 |
| 27867 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27868 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27869 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27870 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27871 | // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 90 |
| 27872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 27873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27875 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 27876 | // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 94 |
| 27877 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 27878 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 27879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27880 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 27881 | // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 98 |
| 27882 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 27883 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27884 | // (ANDSWrs WZR, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 100 |
| 27885 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 27886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27887 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27888 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27889 | // (ANDSWrs WZR, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, logical_shift32:$sh)) - 104 |
| 27890 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 27891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27893 | // (ANDSWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 107 |
| 27894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27895 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27896 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27897 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27898 | // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 111 |
| 27899 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27901 | // (ANDSXrs XZR, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 113 |
| 27902 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27903 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27905 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27906 | // (ANDSXrs XZR, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, logical_shift64:$sh)) - 117 |
| 27907 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 27908 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27910 | // (ANDSXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 120 |
| 27911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27913 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27914 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27915 | // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 124 |
| 27916 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 27917 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 27918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 27919 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 2}, |
| 27920 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27921 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27922 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27923 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27924 | // (ANDWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 132 |
| 27925 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27928 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27929 | // (ANDXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 136 |
| 27930 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27931 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27932 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27933 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27934 | // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 140 |
| 27935 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 27936 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 27937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 27938 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 2}, |
| 27939 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27940 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27942 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27943 | // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 148 |
| 27944 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27945 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27946 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 27947 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27949 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27950 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27951 | // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 155 |
| 27952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27953 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27954 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 27955 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27956 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27957 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27958 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27959 | // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 162 |
| 27960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27961 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27962 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 27963 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27964 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27965 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27966 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27967 | // (AUTIA1716) - 169 |
| 27968 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 27970 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27971 | // (AUTIASP) - 172 |
| 27972 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27973 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 27974 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27975 | // (AUTIAZ) - 175 |
| 27976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 27978 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27979 | // (AUTIB1716) - 178 |
| 27980 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27981 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 27982 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27983 | // (AUTIBSP) - 181 |
| 27984 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27985 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 27986 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27987 | // (AUTIBZ) - 184 |
| 27988 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27989 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 27990 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27991 | // (BICSWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 187 |
| 27992 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27993 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27994 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27995 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 27996 | // (BICSXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 191 |
| 27997 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27998 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27999 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28000 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28001 | // (BICWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 195 |
| 28002 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28003 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28004 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28005 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28006 | // (BICXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 199 |
| 28007 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28010 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28011 | // (CHKFEAT) - 203 |
| 28012 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28013 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCHK}, |
| 28014 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28015 | // (CLREX 15) - 206 |
| 28016 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 28017 | // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 207 |
| 28018 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28019 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28020 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28021 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28022 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28023 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28024 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28025 | // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 214 |
| 28026 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28027 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28028 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28029 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28030 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28032 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28033 | // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 221 |
| 28034 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28035 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28036 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28037 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28038 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28040 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28041 | // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 228 |
| 28042 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28043 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28044 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28045 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28046 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28047 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28048 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28049 | // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 235 |
| 28050 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28051 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28052 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28053 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28054 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28055 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28056 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28057 | // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 242 |
| 28058 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28059 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28060 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28061 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28062 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28064 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28065 | // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 249 |
| 28066 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28067 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28068 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28069 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28070 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28072 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28073 | // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 256 |
| 28074 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28075 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28076 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28077 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28078 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28079 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28080 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28081 | // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 263 |
| 28082 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28083 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28087 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28088 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28089 | // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 270 |
| 28090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28091 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28092 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28093 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28094 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28096 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28097 | // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 277 |
| 28098 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28099 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28100 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28101 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28102 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28103 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28104 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28105 | // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 284 |
| 28106 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28107 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28108 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28109 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28112 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28113 | // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 291 |
| 28114 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28115 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28116 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28117 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 28118 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28121 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28122 | // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 299 |
| 28123 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28124 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28126 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28128 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28129 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28130 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28131 | // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 307 |
| 28132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28133 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28134 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28135 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 28136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28137 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28138 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28139 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28140 | // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 315 |
| 28141 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28142 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28143 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28144 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 28145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28146 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28147 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28148 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28149 | // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 323 |
| 28150 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28151 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28152 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28153 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 28154 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28155 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28156 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28157 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28158 | // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 331 |
| 28159 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28160 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28161 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28162 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 28163 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28164 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28165 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28166 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28167 | // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 339 |
| 28168 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28169 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28170 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 28172 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28173 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28174 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28175 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28176 | // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 347 |
| 28177 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28178 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28180 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 28181 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28182 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28184 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28185 | // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 355 |
| 28186 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28187 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28188 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28191 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28192 | // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 361 |
| 28193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28195 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28196 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28197 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28198 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28199 | // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 367 |
| 28200 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28201 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28202 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28203 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28204 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28205 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28206 | // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 373 |
| 28207 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28208 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28209 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28210 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28211 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28212 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28213 | // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 379 |
| 28214 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28215 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 28216 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 28217 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28218 | // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 383 |
| 28219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28221 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28222 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28223 | // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 387 |
| 28224 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28225 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28226 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28227 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28228 | // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 391 |
| 28229 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28230 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28231 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28232 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28233 | // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 395 |
| 28234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28235 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 28236 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 28237 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28238 | // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 399 |
| 28239 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28240 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28241 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28242 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28243 | // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 403 |
| 28244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28245 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28246 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28247 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28248 | // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 407 |
| 28249 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28250 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28251 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28252 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28253 | // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 411 |
| 28254 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28255 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28256 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28257 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28258 | // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 415 |
| 28259 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28260 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28261 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28262 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 28263 | // (DCPS1 0) - 419 |
| 28264 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28265 | // (DCPS2 0) - 420 |
| 28266 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28267 | // (DCPS3 0) - 421 |
| 28268 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28269 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28270 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureEL3}, |
| 28271 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28272 | // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 425 |
| 28273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28274 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28275 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28276 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28277 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28278 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28279 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28280 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28281 | // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 433 |
| 28282 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28283 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28284 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28285 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28286 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28287 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28288 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28289 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28290 | // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 441 |
| 28291 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28292 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28293 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28294 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28295 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28296 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28297 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28298 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28299 | // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 449 |
| 28300 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28301 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28302 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28303 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28304 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28305 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28306 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28307 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28308 | // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 457 |
| 28309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28310 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28311 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28312 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28313 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28314 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28315 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28316 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28317 | // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 465 |
| 28318 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28319 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28320 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28321 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28323 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28324 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28325 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28326 | // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 473 |
| 28327 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28328 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28329 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28330 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28331 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28332 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28333 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28334 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28335 | // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 481 |
| 28336 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28337 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28338 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28339 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28340 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28343 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28344 | // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 489 |
| 28345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28346 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28347 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28348 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28349 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28350 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28351 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28352 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28353 | // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 497 |
| 28354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28355 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28356 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28357 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28358 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28359 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28360 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28361 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28362 | // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 505 |
| 28363 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28364 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28365 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28366 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28367 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28368 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28369 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28370 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28371 | // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 513 |
| 28372 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28373 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28374 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28375 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28376 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28377 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28378 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28379 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28380 | // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 521 |
| 28381 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28382 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28383 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 28384 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28386 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28387 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28388 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28389 | // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 529 |
| 28390 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28391 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28392 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28393 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 28394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28395 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28396 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28397 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28398 | // (DSB 0) - 537 |
| 28399 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28400 | // (DSB 4) - 538 |
| 28401 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 28402 | // (DSB { 1, 1, 0, 0 }) - 539 |
| 28403 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 28404 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28405 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::HasV8_0rOps}, |
| 28406 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28407 | // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 543 |
| 28408 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28409 | {.Kind: AliasPatternCond::K_Custom, .Value: 5}, |
| 28410 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28411 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28412 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28413 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28414 | // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 549 |
| 28415 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28416 | {.Kind: AliasPatternCond::K_Custom, .Value: 6}, |
| 28417 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28418 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28419 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28420 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28421 | // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 555 |
| 28422 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28423 | {.Kind: AliasPatternCond::K_Custom, .Value: 7}, |
| 28424 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28425 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28426 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28427 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28428 | // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 561 |
| 28429 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28430 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 28431 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28433 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28434 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28435 | // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 567 |
| 28436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28437 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 28438 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28439 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28441 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28442 | // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 573 |
| 28443 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28444 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 28445 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28446 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28447 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28448 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28449 | // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 579 |
| 28450 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28453 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28454 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28455 | // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 584 |
| 28456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28457 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28458 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28460 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28461 | // (DUP_ZI_D ZPR64:$Zd, (cpy_imm8_opt_lsl_i64 0, 0)) - 589 |
| 28462 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28463 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28464 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28465 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28466 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28467 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28468 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28469 | // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 596 |
| 28470 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28471 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28472 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28473 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28474 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28475 | // (DUP_ZI_H ZPR16:$Zd, (cpy_imm8_opt_lsl_i16 0, 0)) - 601 |
| 28476 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28477 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28478 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28479 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28480 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28481 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28482 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28483 | // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 608 |
| 28484 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28485 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28486 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28487 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28488 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28489 | // (DUP_ZI_S ZPR32:$Zd, (cpy_imm8_opt_lsl_i32 0, 0)) - 613 |
| 28490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28491 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28492 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28493 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28494 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28495 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28496 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28497 | // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 620 |
| 28498 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28499 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 28500 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28501 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28502 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28503 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28504 | // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 626 |
| 28505 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28506 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 28507 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28508 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28509 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28510 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28511 | // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 632 |
| 28512 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28513 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 28514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28515 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28516 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28517 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28518 | // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 638 |
| 28519 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28520 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 28521 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28522 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28523 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28524 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28525 | // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 644 |
| 28526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28528 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28529 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28530 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28531 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28532 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28533 | // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 651 |
| 28534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28535 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28536 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28537 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28538 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28539 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28540 | // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 657 |
| 28541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28543 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28544 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28545 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28546 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28547 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28548 | // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 664 |
| 28549 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28551 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28552 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28553 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28554 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28555 | // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 670 |
| 28556 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28557 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28558 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28559 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28560 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28561 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28562 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28563 | // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 677 |
| 28564 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28565 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28566 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28567 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28568 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28569 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28570 | // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 683 |
| 28571 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28572 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28573 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28574 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28575 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28576 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28577 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28578 | // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 690 |
| 28579 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28581 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28582 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28583 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28584 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28585 | // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 696 |
| 28586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28587 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28588 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28589 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28591 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28592 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28593 | // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 703 |
| 28594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28596 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28597 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28598 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28599 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28600 | // (EONWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 709 |
| 28601 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28602 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28604 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28605 | // (EONXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 713 |
| 28606 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28607 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28608 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28609 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28610 | // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 717 |
| 28611 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28612 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28614 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28615 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28616 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28617 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28618 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28619 | // (EORWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 725 |
| 28620 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28623 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28624 | // (EORXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 729 |
| 28625 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28626 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28627 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28628 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28629 | // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 733 |
| 28630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28631 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28632 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28633 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28634 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28635 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28636 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28637 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28638 | // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 741 |
| 28639 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28640 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28641 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 28642 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28643 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28644 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28645 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28646 | // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 748 |
| 28647 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28648 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28649 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 28650 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28651 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28652 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28653 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28654 | // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 755 |
| 28655 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28656 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28657 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 28658 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28659 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28660 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28661 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28662 | // (EXTRACT_ZPMXI_H_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 762 |
| 28663 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28664 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28665 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28666 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 28667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28668 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28669 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28670 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28671 | // (EXTRACT_ZPMXI_H_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 770 |
| 28672 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28673 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28674 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28675 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 28676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28677 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28678 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28679 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28680 | // (EXTRACT_ZPMXI_H_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 778 |
| 28681 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28682 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28683 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 28685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28686 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28687 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28688 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28689 | // (EXTRACT_ZPMXI_H_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpH128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 786 |
| 28690 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28691 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28692 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28693 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 28694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28695 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28696 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28697 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28698 | // (EXTRACT_ZPMXI_H_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 794 |
| 28699 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28700 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28701 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28702 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 28703 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28704 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28705 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28706 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28707 | // (EXTRACT_ZPMXI_V_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 802 |
| 28708 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28709 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28710 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28711 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 28712 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28713 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28714 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28715 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28716 | // (EXTRACT_ZPMXI_V_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 810 |
| 28717 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28718 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28719 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28720 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 28721 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28722 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28723 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28724 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28725 | // (EXTRACT_ZPMXI_V_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 818 |
| 28726 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28727 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28728 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28729 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 28730 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28731 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28732 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28733 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28734 | // (EXTRACT_ZPMXI_V_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpV128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 826 |
| 28735 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28736 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28737 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28738 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 28739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28740 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28741 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28742 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28743 | // (EXTRACT_ZPMXI_V_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 834 |
| 28744 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28745 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28746 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 28748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 28749 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28750 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28751 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28752 | // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 842 |
| 28753 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28754 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 28755 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28756 | // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 845 |
| 28757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 28759 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 28760 | // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 848 |
| 28761 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28762 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28763 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28764 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28765 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28766 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28767 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28768 | // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 855 |
| 28769 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28770 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28771 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28772 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28773 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28774 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28775 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28776 | // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 862 |
| 28777 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28778 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 28779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 28780 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28781 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28782 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28783 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28784 | // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 869 |
| 28785 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28786 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28787 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28788 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28789 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28790 | // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 874 |
| 28791 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28792 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28793 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28794 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28795 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28796 | // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 879 |
| 28797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28798 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28799 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28800 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 28801 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28802 | // (GCSPOPM XZR) - 884 |
| 28803 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28804 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28805 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureGCS}, |
| 28806 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28807 | // (GLD1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 888 |
| 28808 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28809 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28810 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28811 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28812 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28813 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28814 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28815 | // (GLD1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 895 |
| 28816 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28817 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28818 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28819 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28820 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28821 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28822 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28823 | // (GLD1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 902 |
| 28824 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28825 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28826 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28827 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28828 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28829 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28830 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28831 | // (GLD1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 909 |
| 28832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28834 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28835 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28836 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28837 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28838 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28839 | // (GLD1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 916 |
| 28840 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28841 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28843 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28844 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28845 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28846 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28847 | // (GLD1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 923 |
| 28848 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28849 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28850 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28851 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 28852 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28853 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 28854 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28855 | // (GLD1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 930 |
| 28856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28857 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28859 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28862 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28863 | // (GLD1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 937 |
| 28864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28866 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28867 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28868 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28870 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28871 | // (GLD1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 944 |
| 28872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28875 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28876 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28877 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28878 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28879 | // (GLD1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 951 |
| 28880 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28881 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28882 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28883 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28884 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28885 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28886 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28887 | // (GLD1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 958 |
| 28888 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28889 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28890 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28891 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28892 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28893 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28894 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28895 | // (GLD1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 965 |
| 28896 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28897 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28898 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28899 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28900 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28901 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28902 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28903 | // (GLD1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 972 |
| 28904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28905 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28906 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28907 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28908 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28909 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28910 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28911 | // (GLDFF1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 979 |
| 28912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28913 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28914 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28915 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28916 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28917 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28918 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28919 | // (GLDFF1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 986 |
| 28920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28921 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28922 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28923 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28925 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28926 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28927 | // (GLDFF1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 993 |
| 28928 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28930 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28931 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28933 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28934 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28935 | // (GLDFF1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1000 |
| 28936 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28938 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28939 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28940 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28942 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28943 | // (GLDFF1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1007 |
| 28944 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28945 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28946 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28947 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28949 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28950 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28951 | // (GLDFF1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1014 |
| 28952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28955 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28956 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28957 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28958 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28959 | // (GLDFF1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1021 |
| 28960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28961 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28962 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28963 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28964 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28965 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28966 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28967 | // (GLDFF1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1028 |
| 28968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28969 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28970 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28971 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28972 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28973 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28974 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28975 | // (GLDFF1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1035 |
| 28976 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28977 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28978 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28979 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28980 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28981 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28982 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28983 | // (GLDFF1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1042 |
| 28984 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28985 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28986 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28987 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28988 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28989 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28990 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28991 | // (GLDFF1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1049 |
| 28992 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28993 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 28994 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 28995 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 28996 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 28997 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 28998 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 28999 | // (GLDFF1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1056 |
| 29000 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29002 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29003 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29006 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29007 | // (HINT { 0, 0, 1 }) - 1063 |
| 29008 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29009 | // (HINT { 0, 1, 0 }) - 1064 |
| 29010 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 29011 | // (HINT { 0, 1, 1 }) - 1065 |
| 29012 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 29013 | // (HINT { 1, 0, 0 }) - 1066 |
| 29014 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 29015 | // (HINT { 1, 0, 1 }) - 1067 |
| 29016 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 29017 | // (HINT { 1, 1, 0 }) - 1068 |
| 29018 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 29019 | // (HINT { 1, 0, 0, 0, 0 }) - 1069 |
| 29020 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 29021 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29022 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRAS}, |
| 29023 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29024 | // (HINT 20) - 1073 |
| 29025 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(20)}, |
| 29026 | // (HINT 32) - 1074 |
| 29027 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(32)}, |
| 29028 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29029 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBTIE}, |
| 29030 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29031 | // (HINT 32) - 1078 |
| 29032 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(32)}, |
| 29033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29034 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBranchTargetId}, |
| 29035 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29036 | // (HINT btihint_op:$op) - 1082 |
| 29037 | {.Kind: AliasPatternCond::K_Custom, .Value: 8}, |
| 29038 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBranchTargetId}, |
| 29040 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29041 | // (HINT psbhint_op:$op) - 1086 |
| 29042 | {.Kind: AliasPatternCond::K_Custom, .Value: 9}, |
| 29043 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29044 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSPE}, |
| 29045 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29046 | // (HINT 19) - 1090 |
| 29047 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(19)}, |
| 29048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureGCS}, |
| 29050 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29051 | // (HINT 22) - 1094 |
| 29052 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(22)}, |
| 29053 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29054 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCLRBHB}, |
| 29055 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29056 | // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1098 |
| 29057 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29058 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29059 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 29060 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29061 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29062 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29064 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29065 | // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1106 |
| 29066 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29067 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29068 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29069 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29070 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29073 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29074 | // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1114 |
| 29075 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29076 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29077 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 29078 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29079 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29081 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29082 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29083 | // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1122 |
| 29084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29085 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29086 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29087 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29088 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29089 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29090 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29091 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29092 | // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1130 |
| 29093 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29094 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29095 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 29096 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29097 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29098 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29099 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29100 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29101 | // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 1138 |
| 29102 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29103 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29104 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29105 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29106 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29107 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29108 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29109 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29110 | // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1146 |
| 29111 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29112 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29113 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 29114 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29115 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29116 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29117 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29118 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29119 | // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1154 |
| 29120 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29121 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29122 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29123 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29124 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29125 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29126 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29127 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29128 | // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1162 |
| 29129 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29130 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29131 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 29132 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29133 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29134 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29135 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29136 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29137 | // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 1170 |
| 29138 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29139 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29140 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29141 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29142 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29143 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29145 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29146 | // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1178 |
| 29147 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29148 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29149 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 29150 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29151 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29153 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29154 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29155 | // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1186 |
| 29156 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29157 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29158 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29159 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29160 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29161 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29163 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29164 | // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1194 |
| 29165 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29166 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29167 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 29168 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29169 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29170 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29171 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29172 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29173 | // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 1202 |
| 29174 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29175 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29176 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29177 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 29178 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29179 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29181 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29182 | // (INSERT_MXIPZ_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1210 |
| 29183 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 29184 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29185 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29186 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29187 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29188 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29191 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29192 | // (INSERT_MXIPZ_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1219 |
| 29193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 29194 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29196 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29197 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29198 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29199 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29200 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29201 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29202 | // (INSERT_MXIPZ_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1228 |
| 29203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 29204 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29205 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29206 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29207 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29208 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29209 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29210 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29211 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29212 | // (INSERT_MXIPZ_H_Q TileVectorOpH128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1237 |
| 29213 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 29214 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29215 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29216 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29217 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29218 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29219 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29220 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29221 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29222 | // (INSERT_MXIPZ_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1246 |
| 29223 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 29224 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29225 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29226 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29229 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29231 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29232 | // (INSERT_MXIPZ_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1255 |
| 29233 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 29234 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29236 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29238 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29240 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29241 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29242 | // (INSERT_MXIPZ_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1264 |
| 29243 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 29244 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29245 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29246 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29247 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29248 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29249 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29250 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29251 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29252 | // (INSERT_MXIPZ_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1273 |
| 29253 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 29254 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29255 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29256 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29257 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29258 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29259 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29260 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29261 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29262 | // (INSERT_MXIPZ_V_Q TileVectorOpV128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1282 |
| 29263 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 29264 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29265 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29266 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29268 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29269 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29270 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29271 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29272 | // (INSERT_MXIPZ_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1291 |
| 29273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 29274 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29275 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 29276 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29277 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29278 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29279 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29280 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29281 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29282 | // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 1300 |
| 29283 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29284 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29285 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29287 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29288 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29289 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29290 | // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 1307 |
| 29291 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29292 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29293 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29294 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29295 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29296 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29297 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29298 | // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 1314 |
| 29299 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29300 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29301 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29302 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29303 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29304 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29305 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29306 | // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 1321 |
| 29307 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29308 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29309 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29310 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29311 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29312 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29313 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29314 | // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 1328 |
| 29315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29316 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29317 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29318 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 29319 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29320 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29321 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29322 | // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 1335 |
| 29323 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29324 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29325 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29326 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29327 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29328 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29329 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29330 | // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 1342 |
| 29331 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29332 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29333 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 29335 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29336 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29337 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29338 | // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 1349 |
| 29339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29340 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29341 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29342 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29343 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29344 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29345 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29346 | // (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 1356 |
| 29347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29348 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29349 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29350 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29351 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 29352 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29353 | // (ISB 15) - 1362 |
| 29354 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 29355 | // (LD1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1363 |
| 29356 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 29357 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29358 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29359 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29360 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29361 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29362 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29363 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29364 | // (LD1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1371 |
| 29365 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 29366 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29367 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29368 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29369 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29370 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29371 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29372 | // (LD1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1378 |
| 29373 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 29374 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29375 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29376 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29377 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29378 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29379 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29380 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29381 | // (LD1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1386 |
| 29382 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 29383 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29384 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29385 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29386 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29387 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29388 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29389 | // (LD1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1393 |
| 29390 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29391 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29392 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29393 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29395 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29396 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29397 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29398 | // (LD1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1401 |
| 29399 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29400 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29401 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29402 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29403 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29404 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29405 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29406 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29407 | // (LD1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1409 |
| 29408 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29409 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29410 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29411 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29412 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29413 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29414 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29415 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29416 | // (LD1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1417 |
| 29417 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29418 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29419 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29420 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29421 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29422 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29423 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29424 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29425 | // (LD1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1425 |
| 29426 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 29427 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29428 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29429 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29430 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29431 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29433 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29434 | // (LD1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1433 |
| 29435 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 29436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29437 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29438 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29439 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29441 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29442 | // (LD1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1440 |
| 29443 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 29444 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29445 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29446 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29447 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29448 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29449 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29450 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29451 | // (LD1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1448 |
| 29452 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 29453 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29454 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29455 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29456 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29457 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29458 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29459 | // (LD1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1455 |
| 29460 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29461 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29462 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29463 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29464 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29465 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29466 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29467 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29468 | // (LD1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1463 |
| 29469 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29470 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29471 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29472 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29473 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29474 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29475 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29476 | // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1470 |
| 29477 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29478 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 29479 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29480 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29481 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29482 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29483 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29484 | // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1477 |
| 29485 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29486 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 29487 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29488 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29489 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29490 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29491 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29492 | // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1484 |
| 29493 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29494 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 29495 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29496 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29497 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29498 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29499 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29500 | // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1491 |
| 29501 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29502 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 29503 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29504 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29505 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29506 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29507 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29508 | // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1498 |
| 29509 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29510 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 29511 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29512 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29513 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29515 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29516 | // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1505 |
| 29517 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29518 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 29519 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29520 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29521 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29522 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29523 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29524 | // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1512 |
| 29525 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 29527 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29528 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29529 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29530 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29531 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29532 | // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1519 |
| 29533 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 29535 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29536 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29537 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29538 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29539 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29540 | // (LD1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1526 |
| 29541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 29542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29543 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29544 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29545 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29546 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29547 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29548 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29549 | // (LD1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1534 |
| 29550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 29551 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29552 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29553 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29554 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29555 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29556 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29557 | // (LD1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1541 |
| 29558 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 29559 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29560 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29561 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29562 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29563 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29564 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 29565 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29566 | // (LD1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1549 |
| 29567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 29568 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 29569 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29570 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29571 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29572 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 29573 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29574 | // (LD1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1556 |
| 29575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29577 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29578 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29579 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29580 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29581 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29582 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29583 | // (LD1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1564 |
| 29584 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29585 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29587 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29588 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29589 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29591 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29592 | // (LD1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1572 |
| 29593 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29596 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29597 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29598 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29600 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29601 | // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1580 |
| 29602 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29604 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29605 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29606 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29607 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29608 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29609 | // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1587 |
| 29610 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29611 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29612 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29613 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29614 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29615 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29616 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29617 | // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1594 |
| 29618 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29619 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29620 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29621 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29622 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29623 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29624 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29625 | // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1601 |
| 29626 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29627 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29628 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29629 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29630 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29631 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29632 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29633 | // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1608 |
| 29634 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29635 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29636 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29637 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29638 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29639 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29640 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29641 | // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1615 |
| 29642 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29643 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29644 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29645 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29647 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29648 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29649 | // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1622 |
| 29650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29651 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29652 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29653 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29655 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29656 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29657 | // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1629 |
| 29658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29660 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29661 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29662 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29663 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29664 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29665 | // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1636 |
| 29666 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29668 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29669 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29670 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29671 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29672 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29673 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29674 | // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1644 |
| 29675 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29677 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29678 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29679 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29682 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29683 | // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1652 |
| 29684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29686 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29687 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29688 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29689 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29690 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29691 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29692 | // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1660 |
| 29693 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29695 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29696 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29697 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29698 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29699 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29700 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29701 | // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1668 |
| 29702 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29703 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29704 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29705 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29706 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29707 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29708 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29709 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29710 | // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1676 |
| 29711 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29712 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29713 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29714 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29715 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29716 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29717 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29718 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29719 | // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1684 |
| 29720 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29721 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29722 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29723 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29724 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29725 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29726 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29727 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29728 | // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1692 |
| 29729 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29730 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29732 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29733 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29734 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29735 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29736 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29737 | // (LD1RO_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1700 |
| 29738 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29741 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29742 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29744 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29745 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29746 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 29747 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29748 | // (LD1RO_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1710 |
| 29749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29751 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29752 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29753 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29754 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29755 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29756 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29757 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 29758 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29759 | // (LD1RO_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1720 |
| 29760 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29761 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29762 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29763 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29764 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29765 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29766 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29767 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29768 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 29769 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29770 | // (LD1RO_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1730 |
| 29771 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29773 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29774 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29775 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29776 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29777 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29778 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29779 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 29780 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29781 | // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1740 |
| 29782 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29785 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29786 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29787 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29788 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29789 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29790 | // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1748 |
| 29791 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29792 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29794 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29795 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29796 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29797 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29798 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29799 | // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1756 |
| 29800 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29801 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29803 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29804 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29805 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29806 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29807 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29808 | // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1764 |
| 29809 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29810 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29812 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29813 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29814 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29815 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29816 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29817 | // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1772 |
| 29818 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29819 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29821 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29822 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29823 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29825 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29826 | // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1780 |
| 29827 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29830 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29831 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29832 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29833 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29834 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29835 | // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1788 |
| 29836 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29837 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29839 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29840 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29841 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29843 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29844 | // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1796 |
| 29845 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29848 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29849 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29850 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29852 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29853 | // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1804 |
| 29854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29857 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29858 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29859 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29861 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29862 | // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1812 |
| 29863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29866 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29867 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29868 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29870 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29871 | // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1820 |
| 29872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29875 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29876 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29877 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29878 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29879 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29880 | // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1828 |
| 29881 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29882 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29883 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29884 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29885 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29886 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29887 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29888 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29889 | // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1836 |
| 29890 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29892 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29893 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29894 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29895 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29896 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29897 | // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1843 |
| 29898 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29899 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29900 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29901 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29902 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29903 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29904 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29905 | // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1850 |
| 29906 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29907 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29908 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29909 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29910 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29911 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29912 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29913 | // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1857 |
| 29914 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29915 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29916 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29917 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29918 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29919 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29920 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29921 | // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1864 |
| 29922 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29923 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29924 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29925 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29926 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29927 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29928 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29929 | // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1871 |
| 29930 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29931 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29932 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29933 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29934 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29935 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29936 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29937 | // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1878 |
| 29938 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29939 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 29940 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29941 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29942 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29943 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29944 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29945 | // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1885 |
| 29946 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29947 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 29948 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 29949 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 29950 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29951 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 29952 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29953 | // (LD1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1892 |
| 29954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29955 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29956 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29957 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29958 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29959 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29960 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29961 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29962 | // (LD1SB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1900 |
| 29963 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29964 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29965 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29966 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29967 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29968 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29970 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29971 | // (LD1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1908 |
| 29972 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29974 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29975 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29978 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29979 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29980 | // (LD1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1916 |
| 29981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29983 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29984 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29985 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29986 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29987 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29988 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29989 | // (LD1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1924 |
| 29990 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 29991 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 29992 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 29993 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 29994 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 29995 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 29996 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 29997 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 29998 | // (LD1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1932 |
| 29999 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30000 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30002 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30003 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30006 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30007 | // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1940 |
| 30008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30010 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30011 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30012 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30013 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30014 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30015 | // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1947 |
| 30016 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30017 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30018 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30019 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30020 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30021 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30022 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30023 | // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1954 |
| 30024 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30025 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30026 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30027 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30028 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30029 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30030 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30031 | // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1961 |
| 30032 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30033 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30034 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30035 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30036 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30037 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30038 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30039 | // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1968 |
| 30040 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30041 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30042 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30043 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30044 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30045 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30046 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30047 | // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1975 |
| 30048 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30049 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30050 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30051 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30052 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30053 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30054 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30055 | // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1982 |
| 30056 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30057 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30058 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30059 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30060 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30061 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30062 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30063 | // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1989 |
| 30064 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30065 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30066 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30067 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30068 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30069 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30070 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30071 | // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1996 |
| 30072 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30073 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30074 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30075 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30076 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30077 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30078 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30079 | // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 2003 |
| 30080 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30081 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30082 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30083 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30084 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30086 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30087 | // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2010 |
| 30088 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30089 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30090 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30091 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30092 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30093 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30094 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30095 | // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2017 |
| 30096 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30097 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30098 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30099 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30100 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30101 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30102 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30103 | // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2024 |
| 30104 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30105 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30106 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30107 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30108 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30109 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30110 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30111 | // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2031 |
| 30112 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30113 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30114 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30115 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30116 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30117 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30118 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30119 | // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2038 |
| 30120 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30121 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30122 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30123 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30124 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30125 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30126 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30127 | // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2045 |
| 30128 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30129 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30130 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30131 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30132 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30133 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30134 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30135 | // (LD1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2052 |
| 30136 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 30137 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 30138 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30139 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30140 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30141 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30142 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 30143 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30144 | // (LD1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2060 |
| 30145 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 30146 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 30147 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30148 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30149 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30150 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30151 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30152 | // (LD1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2067 |
| 30153 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 30154 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 30155 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30156 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30157 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 30160 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30161 | // (LD1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2075 |
| 30162 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 30163 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 30164 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30165 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30167 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 30168 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30169 | // (LD1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2082 |
| 30170 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30172 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30173 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30174 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30175 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30176 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30177 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30178 | // (LD1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2090 |
| 30179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30180 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30181 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30182 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30184 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30185 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30186 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30187 | // (LD1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2098 |
| 30188 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 30189 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30190 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30191 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30192 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30193 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 30194 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30195 | // (LD1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2105 |
| 30196 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30197 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30198 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30199 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30200 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30201 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30202 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30203 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30204 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30205 | // (LD1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2114 |
| 30206 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30207 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30208 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30209 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30211 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30212 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30213 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30214 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30215 | // (LD1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2123 |
| 30216 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30217 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30218 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30221 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30224 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30225 | // (LD1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2132 |
| 30226 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 30227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30228 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30229 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30230 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30231 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30233 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30234 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30235 | // (LD1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2141 |
| 30236 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30238 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30239 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30240 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30241 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30242 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30243 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30244 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30245 | // (LD1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2150 |
| 30246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 30247 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30248 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30249 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30250 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30251 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30252 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30253 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30254 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30255 | // (LD1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2159 |
| 30256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 30257 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30258 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30259 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30260 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30261 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30262 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30263 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30264 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30265 | // (LD1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2168 |
| 30266 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 30267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30268 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30269 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30271 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30272 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30273 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30274 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30275 | // (LD1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2177 |
| 30276 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 30277 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30278 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30281 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30284 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30285 | // (LD1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2186 |
| 30286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 30287 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 30288 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30289 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30290 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30291 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30292 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30293 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30294 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30295 | // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 2195 |
| 30296 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30297 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30298 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30299 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30300 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30301 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30302 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30303 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30304 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30305 | // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 2204 |
| 30306 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30307 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30308 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30309 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30310 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30311 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30312 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30313 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30314 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30315 | // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 2213 |
| 30316 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30317 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30318 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30319 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30320 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30321 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30323 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30324 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30325 | // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 2222 |
| 30326 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30327 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 30328 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30329 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30330 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30331 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30332 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30333 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30334 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30335 | // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2231 |
| 30336 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 30337 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30338 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30339 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30340 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30343 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30344 | // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2239 |
| 30345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 30346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30348 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30349 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30350 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30351 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30352 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30353 | // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2247 |
| 30354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 30355 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30356 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30357 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30358 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30359 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30360 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30361 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30362 | // (LD2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2255 |
| 30363 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 30364 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30365 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30366 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30367 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30368 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 30369 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 30370 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30371 | // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2263 |
| 30372 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30373 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30374 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30375 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30376 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30377 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30378 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30379 | // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 2270 |
| 30380 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30381 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30382 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30383 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30384 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30386 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30387 | // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2277 |
| 30388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30389 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30390 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30391 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30392 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30393 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30394 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30395 | // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2284 |
| 30396 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30397 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30398 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30399 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30400 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30401 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30402 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30403 | // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2291 |
| 30404 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30405 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30406 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30407 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30408 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30409 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30410 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30411 | // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2298 |
| 30412 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30413 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30414 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30415 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30416 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30417 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30418 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30419 | // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2305 |
| 30420 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30421 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30422 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30423 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30424 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30425 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30426 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30427 | // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2312 |
| 30428 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30429 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30430 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30431 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30433 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30434 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30435 | // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2319 |
| 30436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30437 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30438 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30439 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30441 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30442 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30443 | // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2326 |
| 30444 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30445 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30446 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30447 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30448 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30449 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30450 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30451 | // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2333 |
| 30452 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30453 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30454 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30455 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30456 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30457 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30458 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30459 | // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2340 |
| 30460 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30461 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30462 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30463 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30464 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30465 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30466 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30467 | // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2347 |
| 30468 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30469 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30470 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30471 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30472 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30473 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30474 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30475 | // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2354 |
| 30476 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30477 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 30478 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30479 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30480 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30481 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30482 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30483 | // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2361 |
| 30484 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30485 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30486 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30487 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30488 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30489 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30490 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30491 | // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2368 |
| 30492 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 30493 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30494 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30495 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30496 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30497 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30498 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30499 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30500 | // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 2376 |
| 30501 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30502 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30503 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30504 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30505 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30506 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30507 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30508 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30509 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30510 | // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 2385 |
| 30511 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30512 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30513 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30514 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30515 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30516 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30517 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30518 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30519 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30520 | // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 2394 |
| 30521 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30522 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30523 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30524 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30525 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30526 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30527 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30528 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30529 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30530 | // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 2403 |
| 30531 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30532 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 30533 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30534 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30535 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30536 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30537 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30538 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30539 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30540 | // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2412 |
| 30541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 30542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30543 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30544 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30545 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30546 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30547 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30548 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30549 | // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2420 |
| 30550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 30551 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30552 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30553 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30554 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30555 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30556 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30557 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30558 | // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2428 |
| 30559 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 30560 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30561 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30562 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30563 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30564 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30565 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30566 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30567 | // (LD3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2436 |
| 30568 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 30569 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30570 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30571 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30572 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30573 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 30574 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 30575 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30576 | // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2444 |
| 30577 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30578 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30579 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30580 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30581 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30582 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30583 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30584 | // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 2451 |
| 30585 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30587 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30588 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30589 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30591 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30592 | // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2458 |
| 30593 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30595 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30596 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30597 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30598 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30599 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30600 | // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2465 |
| 30601 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30602 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30603 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30604 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30605 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30606 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30607 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30608 | // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2472 |
| 30609 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30610 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30611 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30612 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30613 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30614 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30615 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30616 | // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2479 |
| 30617 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30618 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30619 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30620 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30621 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30622 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30623 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30624 | // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2486 |
| 30625 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30626 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30627 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30628 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30629 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30630 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30631 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30632 | // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2493 |
| 30633 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30634 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30635 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30636 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30637 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30638 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30639 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30640 | // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2500 |
| 30641 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30642 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30643 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30644 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30645 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30647 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30648 | // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2507 |
| 30649 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30651 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30652 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30653 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30655 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30656 | // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2514 |
| 30657 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30659 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30660 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30661 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30662 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30663 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30664 | // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2521 |
| 30665 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30666 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30667 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30668 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30669 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30670 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30671 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30672 | // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2528 |
| 30673 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30674 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30675 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30676 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30677 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30678 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30679 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30680 | // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2535 |
| 30681 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30682 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 30683 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30684 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30685 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30686 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30687 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30688 | // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2542 |
| 30689 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30690 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30691 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30692 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30693 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30694 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30695 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30696 | // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2549 |
| 30697 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 30698 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30699 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30700 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30701 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30702 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30703 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30704 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30705 | // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 2557 |
| 30706 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30707 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30708 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30709 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30710 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30711 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30712 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30713 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30714 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30715 | // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 2566 |
| 30716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30717 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30718 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30719 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30720 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30721 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30722 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30723 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30724 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30725 | // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 2575 |
| 30726 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30727 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30728 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30729 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30730 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30731 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30732 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30733 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30734 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30735 | // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 2584 |
| 30736 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30737 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 30738 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30739 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30740 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30741 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30742 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30744 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30745 | // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2593 |
| 30746 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 30747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30749 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30750 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30751 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30752 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30753 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30754 | // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2601 |
| 30755 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 30756 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30758 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30759 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30760 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30761 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30762 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30763 | // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2609 |
| 30764 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30765 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30766 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30767 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30768 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30769 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30770 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30771 | // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2616 |
| 30772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30773 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30774 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30775 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30776 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30777 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30778 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30779 | // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2623 |
| 30780 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 30782 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30783 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30784 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30785 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30786 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30787 | // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2630 |
| 30788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30789 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 30790 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30791 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30792 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30793 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30794 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30795 | // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2637 |
| 30796 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30798 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30799 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30800 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30802 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30803 | // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2644 |
| 30804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30805 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 30806 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30807 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30809 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30810 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30811 | // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2651 |
| 30812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30814 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30815 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30818 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30819 | // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2658 |
| 30820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 30821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30823 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30826 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30827 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30828 | // (LD4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2666 |
| 30829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 30830 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30831 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30832 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30833 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 30835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 30836 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30837 | // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2674 |
| 30838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30839 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30840 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30841 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30843 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30844 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30845 | // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 2681 |
| 30846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 30848 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30849 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30850 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30852 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30853 | // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2688 |
| 30854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30856 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30857 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30858 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30859 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30860 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30861 | // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2695 |
| 30862 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 30864 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30865 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30866 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30867 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30868 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30869 | // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2702 |
| 30870 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30871 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 30872 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30873 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30874 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30875 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30876 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30877 | // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2709 |
| 30878 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30880 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30881 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30882 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30883 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30884 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30885 | // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2716 |
| 30886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30887 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 30888 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30889 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30890 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30891 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30892 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30893 | // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2723 |
| 30894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30895 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30896 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30897 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30898 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30899 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30900 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30901 | // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2730 |
| 30902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 30903 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 30904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30905 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 30906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30907 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 30908 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 30909 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30910 | // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 2738 |
| 30911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30913 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30914 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30915 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30916 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30917 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30918 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30919 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30920 | // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 2747 |
| 30921 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30922 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30923 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30924 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30925 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30926 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30927 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30928 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30929 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30930 | // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 2756 |
| 30931 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30932 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30933 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30934 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30935 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30936 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30937 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30938 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30939 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30940 | // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 2765 |
| 30941 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 30943 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30944 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30945 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 30946 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30947 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 30949 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30950 | // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2774 |
| 30951 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30954 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30955 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30956 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30957 | // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2780 |
| 30958 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30961 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30962 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30963 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30964 | // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2786 |
| 30965 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30966 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30967 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30968 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30970 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30971 | // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2792 |
| 30972 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30974 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30975 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30977 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30978 | // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2798 |
| 30979 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30980 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30982 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30983 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30984 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30985 | // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2804 |
| 30986 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 30987 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 30988 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30989 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30990 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30991 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30992 | // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2810 |
| 30993 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 30994 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 30995 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 30996 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 30997 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 30998 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 30999 | // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2816 |
| 31000 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31002 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31003 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31005 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31006 | // (LDAPPi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn) - 2822 |
| 31007 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31011 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSCP}, |
| 31012 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31013 | // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2828 |
| 31014 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31015 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31016 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31017 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31018 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 31019 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31020 | // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2834 |
| 31021 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31022 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31023 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 31026 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31027 | // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2840 |
| 31028 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31029 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31030 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 31033 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31034 | // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2846 |
| 31035 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31037 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31038 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 31040 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31041 | // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2852 |
| 31042 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31043 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31044 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31045 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31046 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 31047 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31048 | // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2858 |
| 31049 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31050 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31051 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31052 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31053 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 31054 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31055 | // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2864 |
| 31056 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31057 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31058 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31059 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31060 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 31061 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31062 | // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2870 |
| 31063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31064 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31065 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31066 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31067 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 31068 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31069 | // (LDAPURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 2876 |
| 31070 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 31071 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31072 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31074 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 31075 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31076 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31077 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31078 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31079 | // (LDAPURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 2885 |
| 31080 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 31081 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31082 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31083 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31084 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 31085 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31087 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31088 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31089 | // (LDAPURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 2894 |
| 31090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 31091 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31092 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31093 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31094 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 31095 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31096 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31097 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31098 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31099 | // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 2903 |
| 31100 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31101 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31102 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31103 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31104 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 31105 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31106 | // (LDAPURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 2909 |
| 31107 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 31108 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31109 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 31112 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31114 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31115 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31116 | // (LDAPURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 2918 |
| 31117 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 31118 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31119 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 31122 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31123 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31124 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 31125 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31126 | // (LDAPi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn) - 2927 |
| 31127 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31128 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31129 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31130 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSCP}, |
| 31132 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31133 | // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2933 |
| 31134 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31135 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31136 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31137 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31138 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31139 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31140 | // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2939 |
| 31141 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31142 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31143 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31146 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31147 | // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2945 |
| 31148 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31149 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31150 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31151 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31153 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31154 | // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2951 |
| 31155 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31156 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31157 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31160 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31161 | // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2957 |
| 31162 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31163 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31164 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31165 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31167 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31168 | // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2963 |
| 31169 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31170 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31172 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31173 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31174 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31175 | // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2969 |
| 31176 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31177 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31178 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31179 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31181 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31182 | // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2975 |
| 31183 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31184 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31185 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31186 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31187 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31188 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31189 | // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2981 |
| 31190 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31191 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31192 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31193 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31194 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31195 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31196 | // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2987 |
| 31197 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31198 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31199 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31200 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31201 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31202 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31203 | // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2993 |
| 31204 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31205 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31206 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31207 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31208 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31209 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31210 | // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2999 |
| 31211 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31212 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31213 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31214 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31216 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31217 | // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3005 |
| 31218 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31221 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31223 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31224 | // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3011 |
| 31225 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31226 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31228 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31229 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31230 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31231 | // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3017 |
| 31232 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 31233 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31235 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31236 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31237 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31238 | // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3023 |
| 31239 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31240 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31241 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31242 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31243 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 31244 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31245 | // (LDFF1B Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3029 |
| 31246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31247 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31248 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31249 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31250 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31251 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31252 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31253 | // (LDFF1B_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3036 |
| 31254 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31255 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31257 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31258 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31259 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31260 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31261 | // (LDFF1B_H Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3043 |
| 31262 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31263 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31264 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31265 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31266 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31267 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31268 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31269 | // (LDFF1B_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3050 |
| 31270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31272 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31273 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31274 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31275 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31276 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31277 | // (LDFF1D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3057 |
| 31278 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31281 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31284 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31285 | // (LDFF1H Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3064 |
| 31286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31287 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31288 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31289 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31290 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31291 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31292 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31293 | // (LDFF1H_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3071 |
| 31294 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31295 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31296 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31297 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31298 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31299 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31300 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31301 | // (LDFF1H_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3078 |
| 31302 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31303 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31304 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31305 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31306 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31307 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31308 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31309 | // (LDFF1SB_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3085 |
| 31310 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31311 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31312 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31313 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31314 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31315 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31316 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31317 | // (LDFF1SB_H Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3092 |
| 31318 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31319 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31320 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31321 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31323 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31324 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31325 | // (LDFF1SB_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3099 |
| 31326 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31327 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31328 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31329 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31330 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31331 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31332 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31333 | // (LDFF1SH_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3106 |
| 31334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31335 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31336 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31337 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31338 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31339 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31340 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31341 | // (LDFF1SH_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3113 |
| 31342 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31343 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31344 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31345 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31346 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31347 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31348 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31349 | // (LDFF1SW_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3120 |
| 31350 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31351 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31352 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31353 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31354 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31355 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31356 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31357 | // (LDFF1W Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3127 |
| 31358 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31359 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31360 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31361 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31362 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31363 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31364 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31365 | // (LDFF1W_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3134 |
| 31366 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31367 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31368 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31369 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31370 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31371 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31372 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31373 | // (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 3141 |
| 31374 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31375 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 31376 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31377 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31378 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31379 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 31380 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31381 | // (LDNF1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3148 |
| 31382 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31383 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31384 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31385 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31386 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31387 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31388 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31389 | // (LDNF1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3155 |
| 31390 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31391 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31392 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31393 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31395 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31396 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31397 | // (LDNF1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3162 |
| 31398 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31399 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31400 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31401 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31402 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31403 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31404 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31405 | // (LDNF1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3169 |
| 31406 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31407 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31408 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31409 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31410 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31411 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31412 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31413 | // (LDNF1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3176 |
| 31414 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31415 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31416 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31417 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31418 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31419 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31420 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31421 | // (LDNF1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3183 |
| 31422 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31423 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31424 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31425 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31426 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31427 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31428 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31429 | // (LDNF1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3190 |
| 31430 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31431 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31432 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31433 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31434 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31435 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31436 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31437 | // (LDNF1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3197 |
| 31438 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31439 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31440 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31441 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31442 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31443 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31444 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31445 | // (LDNF1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3204 |
| 31446 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31447 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31448 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31449 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31450 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31452 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31453 | // (LDNF1SB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3211 |
| 31454 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31457 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31458 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31460 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31461 | // (LDNF1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3218 |
| 31462 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31463 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31464 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31465 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31466 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31467 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31468 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31469 | // (LDNF1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3225 |
| 31470 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31471 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31472 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31473 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31474 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31475 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31476 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31477 | // (LDNF1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3232 |
| 31478 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31479 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31480 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31481 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31482 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31483 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31484 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31485 | // (LDNF1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3239 |
| 31486 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31487 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31488 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31489 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31490 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31491 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31492 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31493 | // (LDNF1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3246 |
| 31494 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31495 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31497 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31498 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31499 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31500 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31501 | // (LDNF1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3253 |
| 31502 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31503 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31504 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31505 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31506 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31507 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31508 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31509 | // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3260 |
| 31510 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 31511 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 31512 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31513 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31515 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31516 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31517 | // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3267 |
| 31518 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 31519 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 31520 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31521 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31522 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31523 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31524 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31525 | // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3274 |
| 31526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 31527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 31528 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31529 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31530 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31531 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31532 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31533 | // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3281 |
| 31534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31535 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31536 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31537 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31538 | // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3285 |
| 31539 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31540 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31542 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31543 | // (LDNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3289 |
| 31544 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 31545 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31547 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31548 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31549 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31550 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31551 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31552 | // (LDNT1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3297 |
| 31553 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 31554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31556 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31557 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31558 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31559 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31560 | // (LDNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3304 |
| 31561 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 31562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31563 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31564 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31565 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31566 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31567 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31568 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31569 | // (LDNT1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3312 |
| 31570 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 31571 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31572 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31573 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31574 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31575 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31576 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31577 | // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3319 |
| 31578 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31579 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31581 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31582 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31583 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31584 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31585 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31586 | // (LDNT1B_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3327 |
| 31587 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31588 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31589 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31590 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31591 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31592 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31593 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31594 | // (LDNT1B_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3334 |
| 31595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31596 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31597 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31598 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31600 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31601 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31602 | // (LDNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3341 |
| 31603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 31604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31605 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31606 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31607 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31608 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31609 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31610 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31611 | // (LDNT1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3349 |
| 31612 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 31613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31614 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31615 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31616 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31617 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31618 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31619 | // (LDNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3356 |
| 31620 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 31621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31623 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31624 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31625 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31626 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31627 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31628 | // (LDNT1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3364 |
| 31629 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 31630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31631 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31632 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31633 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31634 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31635 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31636 | // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3371 |
| 31637 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31638 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31639 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31640 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31641 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31642 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31643 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31644 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31645 | // (LDNT1D_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3379 |
| 31646 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31647 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31648 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31649 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31650 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31651 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31652 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31653 | // (LDNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3386 |
| 31654 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 31655 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31656 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31657 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31658 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31659 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31660 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31661 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31662 | // (LDNT1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3394 |
| 31663 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 31664 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31665 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31666 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31667 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31668 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31669 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31670 | // (LDNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3401 |
| 31671 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 31672 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31673 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31674 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31675 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31676 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31677 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31678 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31679 | // (LDNT1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3409 |
| 31680 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 31681 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31682 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31683 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31684 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31685 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31686 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31687 | // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3416 |
| 31688 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31689 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31690 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31691 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31692 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31693 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31694 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31695 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31696 | // (LDNT1H_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3424 |
| 31697 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31698 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31699 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31700 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31701 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31702 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31703 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31704 | // (LDNT1H_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3431 |
| 31705 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31706 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31707 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31708 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31709 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31710 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31711 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31712 | // (LDNT1SB_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3438 |
| 31713 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31714 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31715 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31716 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31717 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31718 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31719 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31720 | // (LDNT1SB_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3445 |
| 31721 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31722 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31723 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31724 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31725 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31726 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31727 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31728 | // (LDNT1SH_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3452 |
| 31729 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31730 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31732 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31733 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31734 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31735 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31736 | // (LDNT1SH_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3459 |
| 31737 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31738 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31740 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31741 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31742 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31743 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31744 | // (LDNT1SW_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3466 |
| 31745 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31746 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31748 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31749 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31750 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31751 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31752 | // (LDNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3473 |
| 31753 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 31754 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31755 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31756 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31757 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31758 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31759 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31760 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31761 | // (LDNT1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3481 |
| 31762 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 31763 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31764 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31765 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31766 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31767 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31768 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31769 | // (LDNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3488 |
| 31770 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 31771 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31773 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31774 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31775 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31776 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 31777 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31778 | // (LDNT1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3496 |
| 31779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 31780 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 31781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31782 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31783 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31784 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 31785 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31786 | // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3503 |
| 31787 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31789 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31790 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31791 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31792 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 31793 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 31794 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31795 | // (LDNT1W_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3511 |
| 31796 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31799 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31800 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31802 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31803 | // (LDNT1W_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3518 |
| 31804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31805 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 31806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 31807 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 31808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31809 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 31810 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31811 | // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3525 |
| 31812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 31813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 31814 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31815 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31818 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31819 | // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3532 |
| 31820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 31821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 31822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31823 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31826 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31827 | // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3539 |
| 31828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31830 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31831 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31832 | // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3543 |
| 31833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 31834 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 31835 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31836 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31837 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31838 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31839 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31840 | // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3550 |
| 31841 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31843 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31844 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31845 | // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3554 |
| 31846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31848 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31849 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31850 | // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3558 |
| 31851 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31852 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31853 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31854 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31855 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 31856 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31857 | // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3564 |
| 31858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31859 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31860 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31862 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 31863 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31864 | // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 3570 |
| 31865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31866 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31867 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31868 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31869 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31870 | // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 3575 |
| 31871 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31873 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31874 | // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 3578 |
| 31875 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 31876 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31877 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31878 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31879 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31880 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31881 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31882 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31883 | // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3586 |
| 31884 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 31885 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31886 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31887 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31888 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31889 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31890 | // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 3592 |
| 31891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 31892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31894 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31895 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31898 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31899 | // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3600 |
| 31900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 31901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31902 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31903 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31904 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31905 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31906 | // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 3606 |
| 31907 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31908 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31910 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31911 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31912 | // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 3611 |
| 31913 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31914 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31915 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31916 | // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 3614 |
| 31917 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 31918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31920 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31921 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31922 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31924 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31925 | // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3622 |
| 31926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 31927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31928 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31929 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31930 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31931 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31932 | // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend128 0, 0)) - 3628 |
| 31933 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 31934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31935 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31936 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31937 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31938 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31939 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31940 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31941 | // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3636 |
| 31942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 31943 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31944 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31945 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 31946 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 31947 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 31948 | // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 3642 |
| 31949 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31950 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31951 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31952 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31953 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31954 | // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3647 |
| 31955 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31956 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31957 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31958 | // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 3650 |
| 31959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31961 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31962 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31963 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31964 | // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3655 |
| 31965 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31966 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31967 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31968 | // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 3658 |
| 31969 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31970 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31971 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31972 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31973 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31974 | // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3663 |
| 31975 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 31976 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31977 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31978 | // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 3666 |
| 31979 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31980 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31982 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31983 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31984 | // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3671 |
| 31985 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31986 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31987 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31988 | // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 3674 |
| 31989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31990 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31991 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31992 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31993 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31994 | // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 3679 |
| 31995 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 31996 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 31997 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 31998 | // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 3682 |
| 31999 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 32000 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32002 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32003 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32006 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32007 | // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3690 |
| 32008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 32009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32010 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32011 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32012 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32013 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32014 | // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 3696 |
| 32015 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32016 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32017 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32018 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32019 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32020 | // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3701 |
| 32021 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32022 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32023 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32024 | // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 3704 |
| 32025 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32026 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32027 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32028 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32029 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32030 | // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 3709 |
| 32031 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32032 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32033 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32034 | // (LDR_PXI PPRorPNRAny:$Pt, GPR64sp:$Rn, 0) - 3712 |
| 32035 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRorPNRRegClassID}, |
| 32036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32037 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32038 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32041 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32042 | // (LDR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 3719 |
| 32043 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 32044 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32045 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32046 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32047 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32050 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32051 | // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 3727 |
| 32052 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32053 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32054 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32055 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32056 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32057 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32058 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32059 | // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3734 |
| 32060 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32061 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32062 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32065 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32066 | // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3740 |
| 32067 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32069 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32070 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32072 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32073 | // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3746 |
| 32074 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32075 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32076 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32077 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32078 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32079 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32080 | // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3752 |
| 32081 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32082 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32084 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32086 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32087 | // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3758 |
| 32088 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32089 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32091 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32092 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32093 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32094 | // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3764 |
| 32095 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32096 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32097 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32098 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32099 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32100 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32101 | // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3770 |
| 32102 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32103 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32104 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32105 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32106 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32107 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32108 | // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3776 |
| 32109 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32110 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32111 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32112 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32114 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32115 | // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3782 |
| 32116 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32117 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32118 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32121 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32122 | // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3788 |
| 32123 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32124 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32126 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32128 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32129 | // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3794 |
| 32130 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32131 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32133 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32134 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32135 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32136 | // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3800 |
| 32137 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32138 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32139 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32140 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32141 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32142 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32143 | // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3806 |
| 32144 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32145 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32146 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32147 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32148 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32149 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32150 | // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3812 |
| 32151 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32152 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32153 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32154 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32155 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32156 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32157 | // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3818 |
| 32158 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32159 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32160 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32161 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32163 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32164 | // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3824 |
| 32165 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32166 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32167 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32168 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32169 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32170 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32171 | // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3830 |
| 32172 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32173 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32174 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32175 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32176 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32177 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32178 | // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3836 |
| 32179 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32180 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32181 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32182 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32184 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32185 | // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3842 |
| 32186 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32187 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32188 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32191 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32192 | // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3848 |
| 32193 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32196 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32197 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32198 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32199 | // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3854 |
| 32200 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32201 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32202 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32203 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32204 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32205 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32206 | // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3860 |
| 32207 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32208 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32209 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32210 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32211 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32212 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32213 | // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3866 |
| 32214 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32215 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32216 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32217 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32218 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32219 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32220 | // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3872 |
| 32221 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32222 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32223 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32224 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32225 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32226 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32227 | // (LDTADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3878 |
| 32228 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32229 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32230 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32233 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32234 | // (LDTADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3884 |
| 32235 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32236 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32238 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32240 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32241 | // (LDTADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3890 |
| 32242 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32243 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32245 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32246 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32247 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32248 | // (LDTADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3896 |
| 32249 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32250 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32251 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32252 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32253 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32254 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32255 | // (LDTCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3902 |
| 32256 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32257 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32258 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32259 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32260 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32261 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32262 | // (LDTCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3908 |
| 32263 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32264 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32265 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32266 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32267 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32268 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32269 | // (LDTCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3914 |
| 32270 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32272 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32273 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32274 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32275 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32276 | // (LDTCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3920 |
| 32277 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32278 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32280 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32281 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32282 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32283 | // (LDTNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3926 |
| 32284 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32285 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32287 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32288 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32289 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32290 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32291 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32292 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32293 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32294 | // (LDTNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3936 |
| 32295 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32296 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32297 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32298 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32299 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32300 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32301 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32302 | // (LDTPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3943 |
| 32303 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32304 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32305 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32306 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32307 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32308 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32309 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32310 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32311 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32312 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32313 | // (LDTPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3953 |
| 32314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32316 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32317 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32318 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32319 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32320 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32321 | // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3960 |
| 32322 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32323 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32324 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32325 | // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3963 |
| 32326 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32327 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32328 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32329 | // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3966 |
| 32330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32331 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32332 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32333 | // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3969 |
| 32334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32335 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32336 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32337 | // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3972 |
| 32338 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32340 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32341 | // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3975 |
| 32342 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32343 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32344 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32345 | // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 3978 |
| 32346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32348 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32349 | // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3981 |
| 32350 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32351 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32352 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32353 | // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3984 |
| 32354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32355 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32356 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32357 | // (LDTSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3987 |
| 32358 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32359 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32360 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32361 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32362 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32363 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32364 | // (LDTSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3993 |
| 32365 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32366 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32367 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32368 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32369 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32370 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32371 | // (LDTSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3999 |
| 32372 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32373 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32374 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32375 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32376 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32377 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32378 | // (LDTSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4005 |
| 32379 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32380 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32381 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32382 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32383 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 32384 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32385 | // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 4011 |
| 32386 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32387 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32389 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32390 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32391 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32392 | // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 4017 |
| 32393 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32394 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32395 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32396 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32397 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32398 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32399 | // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 4023 |
| 32400 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32401 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32402 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32403 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32404 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32405 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32406 | // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 4029 |
| 32407 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32408 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32409 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32410 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32411 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32412 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32413 | // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4035 |
| 32414 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32415 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32416 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32417 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32418 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32419 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32420 | // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4041 |
| 32421 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32422 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32423 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32424 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32425 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32426 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32427 | // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4047 |
| 32428 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32429 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32430 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32431 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32433 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32434 | // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4053 |
| 32435 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32437 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32438 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32439 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32440 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32441 | // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 4059 |
| 32442 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32443 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32444 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32445 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32446 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32447 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32448 | // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 4065 |
| 32449 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32450 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32451 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32453 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32454 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32455 | // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 4071 |
| 32456 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32457 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32458 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32460 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32461 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32462 | // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 4077 |
| 32463 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32464 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32465 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32466 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32467 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32468 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32469 | // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4083 |
| 32470 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32471 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32472 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32473 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32474 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32475 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32476 | // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4089 |
| 32477 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32478 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32479 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32480 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32481 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32482 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32483 | // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4095 |
| 32484 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32485 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32486 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32487 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32488 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32489 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32490 | // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4101 |
| 32491 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32492 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32493 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32494 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32495 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 32496 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32497 | // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 4107 |
| 32498 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32499 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32500 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32501 | // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 4110 |
| 32502 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 32503 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32504 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32505 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32506 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32507 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32508 | // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 4116 |
| 32509 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32510 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32511 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32512 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32513 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32514 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32515 | // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 4122 |
| 32516 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32517 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32518 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32519 | // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 4125 |
| 32520 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 32521 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32522 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32523 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32524 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32525 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32526 | // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 4131 |
| 32527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32528 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32529 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32530 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32531 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32532 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32533 | // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4137 |
| 32534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32535 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32536 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32537 | // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4140 |
| 32538 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32539 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32540 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32541 | // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4143 |
| 32542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32543 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32544 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32545 | // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4146 |
| 32546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32547 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32548 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32549 | // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 4149 |
| 32550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32551 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32552 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32553 | // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 4152 |
| 32554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 32555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32556 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32557 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32558 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 32559 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32560 | // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4158 |
| 32561 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32563 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32564 | // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 4161 |
| 32565 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32566 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 32567 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32568 | // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 4164 |
| 32569 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32570 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32571 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32572 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32573 | // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 4168 |
| 32574 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32577 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32578 | // (MOVA_2ZMXI_H_B ZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 4172 |
| 32579 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32582 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32583 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32584 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32585 | // (MOVA_2ZMXI_H_D ZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 4178 |
| 32586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32587 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32588 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32589 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32591 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32592 | // (MOVA_2ZMXI_H_H ZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 4184 |
| 32593 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32596 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32597 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32598 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32599 | // (MOVA_2ZMXI_H_S ZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 4190 |
| 32600 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32601 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32602 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32603 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32604 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32605 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32606 | // (MOVA_2ZMXI_V_B ZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 4196 |
| 32607 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32608 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32609 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32610 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32611 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32612 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32613 | // (MOVA_2ZMXI_V_D ZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 4202 |
| 32614 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32615 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32616 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32617 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32618 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32619 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32620 | // (MOVA_2ZMXI_V_H ZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 4208 |
| 32621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32623 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32624 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32625 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32626 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32627 | // (MOVA_2ZMXI_V_S ZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 4214 |
| 32628 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32629 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32631 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32632 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32633 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32634 | // (MOVA_4ZMXI_H_B ZZZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4220 |
| 32635 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32636 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32637 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32638 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32639 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32640 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32641 | // (MOVA_4ZMXI_H_D ZZZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4226 |
| 32642 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32643 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32644 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32645 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32647 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32648 | // (MOVA_4ZMXI_H_H ZZZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4232 |
| 32649 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32651 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32652 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32653 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32654 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32655 | // (MOVA_4ZMXI_H_S ZZZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4238 |
| 32656 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32657 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32659 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32660 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32661 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32662 | // (MOVA_4ZMXI_V_B ZZZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4244 |
| 32663 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32664 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32665 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32666 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32667 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32668 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32669 | // (MOVA_4ZMXI_V_D ZZZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4250 |
| 32670 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32671 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32672 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32673 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32674 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32675 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32676 | // (MOVA_4ZMXI_V_H ZZZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4256 |
| 32677 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32678 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32679 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32682 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32683 | // (MOVA_4ZMXI_V_S ZZZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4262 |
| 32684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32686 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32687 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32688 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32689 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32690 | // (MOVA_MXI2Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4268 |
| 32691 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32692 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32693 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32694 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32695 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32696 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32697 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32698 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32699 | // (MOVA_MXI2Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4276 |
| 32700 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32701 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32702 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32703 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32704 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32705 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32706 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32707 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32708 | // (MOVA_MXI2Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4284 |
| 32709 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32710 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32711 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32712 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32713 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32714 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32715 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32716 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32717 | // (MOVA_MXI2Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4292 |
| 32718 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32719 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32720 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32721 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32722 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32723 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32724 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32725 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32726 | // (MOVA_MXI2Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4300 |
| 32727 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32728 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32729 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32730 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32732 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32733 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32734 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32735 | // (MOVA_MXI2Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4308 |
| 32736 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32737 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32738 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32739 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32741 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32742 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32743 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32744 | // (MOVA_MXI2Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4316 |
| 32745 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32746 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32748 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32750 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32751 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32752 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32753 | // (MOVA_MXI2Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4324 |
| 32754 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32755 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32756 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32757 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32759 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32760 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32761 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32762 | // (MOVA_MXI4Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4332 |
| 32763 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32764 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32765 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32766 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32768 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32769 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32770 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32771 | // (MOVA_MXI4Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4340 |
| 32772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32773 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32775 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32776 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32777 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32778 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32779 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32780 | // (MOVA_MXI4Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4348 |
| 32781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32782 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32784 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32785 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32786 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32787 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32788 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32789 | // (MOVA_MXI4Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4356 |
| 32790 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32791 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32792 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32793 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32794 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32795 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32796 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32797 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32798 | // (MOVA_MXI4Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4364 |
| 32799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 32800 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32801 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32802 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32803 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32804 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32805 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32806 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32807 | // (MOVA_MXI4Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4372 |
| 32808 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 32809 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32810 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32811 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32813 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32814 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32815 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32816 | // (MOVA_MXI4Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4380 |
| 32817 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 32818 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32819 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32820 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32822 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32823 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32824 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32825 | // (MOVA_MXI4Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4388 |
| 32826 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 32827 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 32829 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32830 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32831 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32832 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32833 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32834 | // (MOVA_VG2_2ZMXI ZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4396 |
| 32835 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32836 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 32837 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 32838 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32839 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32840 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32841 | // (MOVA_VG2_MXI2Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZ_d_mul_r:$Zn) - 4402 |
| 32842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 32843 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32844 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 32845 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 32847 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32848 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32849 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32850 | // (MOVA_VG4_4ZMXI ZZZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4410 |
| 32851 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32852 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 32853 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 32854 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32855 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32856 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32857 | // (MOVA_VG4_MXI4Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZZZ_d_mul_r:$Zn) - 4416 |
| 32858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 32859 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32860 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 32861 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32862 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 32863 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32864 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 32865 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32866 | // (MOVT_TIZ ZTR:$ZTt, 0, ZPRAny:$Zt) - 4424 |
| 32867 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZTRRegClassID}, |
| 32868 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32869 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32870 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32871 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME_LUTv2}, |
| 32872 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32873 | // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 1 }) - 4430 |
| 32874 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 32875 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 32876 | // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 1 }) - 4432 |
| 32877 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 32878 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 32879 | // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 1 }) - 4434 |
| 32880 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 32881 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 32882 | // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 0 }) - 4436 |
| 32883 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 32884 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32885 | // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 0 }) - 4438 |
| 32886 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 32887 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32888 | // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 0 }) - 4440 |
| 32889 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 32890 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32891 | // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 4442 |
| 32892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32895 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32896 | // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 4446 |
| 32897 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32898 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32899 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32900 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32901 | // (NOP) - 4450 |
| 32902 | // (NOTv16i8 V128:$Vd, V128:$Vn) - 4450 |
| 32903 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 32905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32907 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32908 | // (NOTv8i8 V64:$Vd, V64:$Vn) - 4455 |
| 32909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 32911 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32912 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 32913 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32914 | // (ORNWrs GPR32:$Wd, WZR, (logical_shifted_reg32 GPR32:$Wm, 0)) - 4460 |
| 32915 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32916 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32917 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32918 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32919 | // (ORNWrs GPR32:$Wd, WZR, (logical_shifted_reg32 GPR32:$Wm, logical_shift32:$sh)) - 4464 |
| 32920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32921 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32922 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32923 | // (ORNWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 4467 |
| 32924 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32925 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32927 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32928 | // (ORNXrs GPR64:$Xd, XZR, (logical_shifted_reg64 GPR64:$Xm, 0)) - 4471 |
| 32929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32930 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32931 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32932 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32933 | // (ORNXrs GPR64:$Xd, XZR, (logical_shifted_reg64 GPR64:$Xm, logical_shift64:$sh)) - 4475 |
| 32934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32935 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32936 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32937 | // (ORNXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 4478 |
| 32938 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32939 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32940 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32941 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32942 | // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4482 |
| 32943 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 32944 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 32945 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 32946 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 32947 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32949 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32950 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32951 | // (ORRWrs GPR32:$dst, WZR, (logical_shifted_reg32 GPR32:$src, 0)) - 4490 |
| 32952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32953 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 32954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32955 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32956 | // (ORRWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 4494 |
| 32957 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32958 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 32960 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32961 | // (ORRXrs GPR64:$dst, XZR, (logical_shifted_reg64 GPR64:$src, 0)) - 4498 |
| 32962 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32963 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 32964 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32965 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32966 | // (ORRXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 4502 |
| 32967 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32969 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 32970 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 32971 | // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4506 |
| 32972 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 32973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 32974 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 32975 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 32976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32978 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32979 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32980 | // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 4514 |
| 32981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32982 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32983 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 32984 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32985 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32986 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32987 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32988 | // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 4521 |
| 32989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32990 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32991 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 32992 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 32993 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 32994 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 32995 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 32996 | // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 4528 |
| 32997 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 32998 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 32999 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 33000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33001 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33002 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33003 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33004 | // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 4535 |
| 33005 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33006 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33007 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 33008 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33009 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33011 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33012 | // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 4542 |
| 33013 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33014 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 33015 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 33016 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33017 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33018 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33019 | // (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 4548 |
| 33020 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 33021 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 33022 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 33023 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33025 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33026 | // (PACIA1716) - 4554 |
| 33027 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33028 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 33029 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33030 | // (PACIASP) - 4557 |
| 33031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 33033 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33034 | // (PACIAZ) - 4560 |
| 33035 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33036 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 33037 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33038 | // (PACIB1716) - 4563 |
| 33039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 33041 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33042 | // (PACIBSP) - 4566 |
| 33043 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33044 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 33045 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33046 | // (PACIBZ) - 4569 |
| 33047 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 33049 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33050 | // (PACM) - 4572 |
| 33051 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33052 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuthLR}, |
| 33053 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33054 | // (PMOV_PZI_B PPR8:$Pd, ZPRAny:$Zn, 0) - 4575 |
| 33055 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33056 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33057 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33059 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 33060 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33061 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33062 | // (PMOV_ZIP_B ZPRAny:$Zd, 0, PPR8:$Pn) - 4582 |
| 33063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33064 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33065 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33066 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33067 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33068 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 33069 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33070 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33071 | // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4590 |
| 33072 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33073 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33074 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33075 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33076 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33077 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33078 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33079 | // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4597 |
| 33080 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33081 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33082 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33083 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33084 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33087 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33088 | // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4605 |
| 33089 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33091 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33092 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33093 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33094 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33095 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33096 | // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4612 |
| 33097 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33098 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33099 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33100 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33101 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33102 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33103 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33104 | // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4619 |
| 33105 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33106 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33107 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33108 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33109 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33112 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33113 | // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4627 |
| 33114 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33115 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33116 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33117 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33118 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33120 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33121 | // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4634 |
| 33122 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33123 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33124 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33125 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33126 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33128 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33129 | // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4641 |
| 33130 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33131 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33133 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33134 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33135 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33137 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33138 | // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4649 |
| 33139 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33140 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33141 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33142 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33143 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33145 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33146 | // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 4656 |
| 33147 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33148 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33149 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33150 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33151 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33152 | // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 4661 |
| 33153 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33154 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33155 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33156 | // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 4664 |
| 33157 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33158 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33159 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33160 | // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4667 |
| 33161 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33162 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33163 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33164 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33165 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33167 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33168 | // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4674 |
| 33169 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33170 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33172 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33173 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33174 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33175 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33176 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33177 | // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4682 |
| 33178 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33180 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33181 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33182 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33184 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33185 | // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4689 |
| 33186 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33187 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33188 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33191 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33192 | // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4695 |
| 33193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33194 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33195 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33196 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33197 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33198 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33199 | // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4701 |
| 33200 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33201 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33202 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33203 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33204 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33205 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33206 | // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4707 |
| 33207 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33208 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33209 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33210 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33211 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33212 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33213 | // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4713 |
| 33214 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33215 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33216 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33217 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33218 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33219 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33220 | // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4719 |
| 33221 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33222 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33224 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33225 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33226 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33227 | // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4725 |
| 33228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33229 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33233 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33234 | // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4731 |
| 33235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33236 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33237 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33238 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33240 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33241 | // (RET LR) - 4737 |
| 33242 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::LR}, |
| 33243 | // (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 4738 |
| 33244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33245 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33247 | // (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 4741 |
| 33248 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33249 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33250 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33251 | // (SBCWr GPR32:$dst, WZR, GPR32:$src) - 4744 |
| 33252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33253 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 33254 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33255 | // (SBCXr GPR64:$dst, XZR, GPR64:$src) - 4747 |
| 33256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33257 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33258 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33259 | // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 4750 |
| 33260 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33261 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33262 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33263 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33264 | // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 4754 |
| 33265 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33266 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33267 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33268 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 33269 | // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 4758 |
| 33270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33272 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33273 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 33274 | // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 4762 |
| 33275 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33276 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33277 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33278 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(63)}, |
| 33279 | // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 4766 |
| 33280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33281 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33282 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33283 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 33284 | // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 4770 |
| 33285 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33287 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33288 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 33289 | // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 4774 |
| 33290 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33291 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33292 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33293 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33294 | // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 4778 |
| 33295 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33296 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33297 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33298 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 33299 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33300 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33301 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33302 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33303 | // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 4786 |
| 33304 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33305 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33306 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33307 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 33308 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33309 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33310 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33311 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33312 | // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 4794 |
| 33313 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33316 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 33317 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33318 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33319 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33320 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33321 | // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 4802 |
| 33322 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33323 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33324 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33325 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 33326 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33327 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33328 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33329 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33330 | // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 4810 |
| 33331 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33332 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 33333 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33334 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 33335 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33336 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33337 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33338 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33339 | // (SHUH 0) - 4818 |
| 33340 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33341 | // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4819 |
| 33342 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33343 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33344 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33345 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33346 | // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4823 |
| 33347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33348 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33349 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 33350 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33351 | // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4827 |
| 33352 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33353 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33354 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33355 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33356 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33357 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33358 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33359 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33360 | // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4835 |
| 33361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33362 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33363 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33364 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33365 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33366 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33367 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33368 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33369 | // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4843 |
| 33370 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33371 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33372 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33373 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33374 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33375 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33376 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33377 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33378 | // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4851 |
| 33379 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33380 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33381 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33382 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33383 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33384 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33386 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33387 | // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4859 |
| 33388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33389 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33390 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33391 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33392 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33393 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33395 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33396 | // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4867 |
| 33397 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33398 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33399 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33400 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33401 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33402 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33403 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33404 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33405 | // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4875 |
| 33406 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33407 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33408 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33409 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33410 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33411 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33412 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33413 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33414 | // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4883 |
| 33415 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33416 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33417 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33418 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33419 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33420 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33421 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33422 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33423 | // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4891 |
| 33424 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33425 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33426 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33427 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33428 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33429 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33430 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33431 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33432 | // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4899 |
| 33433 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33434 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33435 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33436 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33437 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33438 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33439 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33440 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33441 | // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4907 |
| 33442 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33443 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33444 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33445 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33446 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33447 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33448 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33449 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33450 | // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4915 |
| 33451 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33452 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33453 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33454 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33455 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33456 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33457 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33458 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33459 | // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4923 |
| 33460 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33461 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33462 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33463 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33464 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33465 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33466 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33467 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33468 | // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4931 |
| 33469 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33470 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33471 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33472 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33473 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33474 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33475 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33476 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33477 | // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4939 |
| 33478 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33479 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33480 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33481 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33482 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33483 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33484 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33485 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33486 | // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4947 |
| 33487 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33488 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33489 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33490 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33491 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33492 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33493 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33494 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33495 | // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4955 |
| 33496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33497 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33498 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33499 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33500 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33501 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33502 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33503 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33504 | // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4963 |
| 33505 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33506 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33507 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33508 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33509 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33510 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33511 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33512 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33513 | // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4971 |
| 33514 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33515 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33516 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33517 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33518 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33519 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33520 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33521 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33522 | // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4979 |
| 33523 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33524 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33525 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33526 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33527 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33528 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33529 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33530 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33531 | // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4987 |
| 33532 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33533 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33534 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33535 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33536 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33537 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33538 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33539 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33540 | // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 4995 |
| 33541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33542 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33543 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33544 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33545 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33546 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33547 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33548 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33549 | // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5003 |
| 33550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33551 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33552 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33553 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33554 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33555 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33556 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33557 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33558 | // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5011 |
| 33559 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33560 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33561 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33562 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33563 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33564 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33565 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33566 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33567 | // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5019 |
| 33568 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33569 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33570 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33571 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33572 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33573 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33574 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33575 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33576 | // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5027 |
| 33577 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33578 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33579 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33580 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33581 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33582 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33583 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33584 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33585 | // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5035 |
| 33586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33587 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33588 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33589 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33591 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33592 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33593 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33594 | // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5043 |
| 33595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33596 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33597 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33598 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33600 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33601 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33602 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33603 | // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5051 |
| 33604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33605 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33606 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33607 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33608 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33609 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33610 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33611 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33612 | // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5059 |
| 33613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33614 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33615 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33616 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33617 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33618 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33619 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33620 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33621 | // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 5067 |
| 33622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33623 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33624 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33625 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33626 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33627 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33628 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33629 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33630 | // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 5075 |
| 33631 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33632 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33633 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33634 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33635 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33636 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33637 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33638 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33639 | // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5083 |
| 33640 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33641 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33642 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33643 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33644 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33645 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33647 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33648 | // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5091 |
| 33649 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33650 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33651 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33652 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33653 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33655 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33656 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33657 | // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5099 |
| 33658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33660 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33661 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33662 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33663 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33664 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33665 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33666 | // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5107 |
| 33667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33668 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33669 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33670 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33671 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33672 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33673 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33674 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33675 | // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 5115 |
| 33676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33677 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33678 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33679 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33682 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33683 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33684 | // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 5123 |
| 33685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33686 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33687 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33688 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33689 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33690 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33691 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33692 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33693 | // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5131 |
| 33694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33695 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33696 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33697 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33698 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33699 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33700 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33701 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33702 | // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5139 |
| 33703 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33704 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33705 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33706 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33707 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33708 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33709 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33710 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33711 | // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5147 |
| 33712 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33713 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33714 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33715 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33716 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33717 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33718 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33719 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33720 | // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5155 |
| 33721 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33722 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 33723 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33724 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33725 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33726 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33727 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33728 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33729 | // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 5163 |
| 33730 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33731 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33732 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 33733 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33734 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33735 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33737 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33738 | // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 5171 |
| 33739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33740 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33741 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33742 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 33743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33745 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33746 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33747 | // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5179 |
| 33748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33751 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33752 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33753 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33754 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33755 | // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5186 |
| 33756 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33759 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33760 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33761 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33762 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33763 | // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5193 |
| 33764 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33765 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33767 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33768 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33769 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33770 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33771 | // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5200 |
| 33772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33773 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33775 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33776 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33777 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33778 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33779 | // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5207 |
| 33780 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33782 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33783 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33784 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33785 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33786 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33787 | // (SST1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 5214 |
| 33788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33789 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33790 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33791 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33792 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33793 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33794 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33795 | // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5221 |
| 33796 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33799 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33800 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33802 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33803 | // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5228 |
| 33804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33805 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33807 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33809 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33810 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33811 | // (ST1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5235 |
| 33812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 33813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33814 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33815 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33818 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33819 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33820 | // (ST1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5243 |
| 33821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 33822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33823 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33824 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33826 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33827 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33828 | // (ST1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5250 |
| 33829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 33830 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33831 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33832 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33833 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33836 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33837 | // (ST1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5258 |
| 33838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 33839 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33840 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33841 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33843 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33844 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33845 | // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5265 |
| 33846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33848 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33849 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33850 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33852 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33853 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33854 | // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5273 |
| 33855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33857 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33858 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33859 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33862 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33863 | // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5281 |
| 33864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33866 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33867 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33868 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33870 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33871 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33872 | // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5289 |
| 33873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33875 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33876 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33877 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33878 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33879 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33880 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33881 | // (ST1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5297 |
| 33882 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 33883 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33884 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33885 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33886 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33887 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33888 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33889 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33890 | // (ST1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5305 |
| 33891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 33892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33894 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33895 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33897 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33898 | // (ST1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5312 |
| 33899 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 33900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33902 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33903 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33904 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33906 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33907 | // (ST1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5320 |
| 33908 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 33909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33911 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33912 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33913 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 33914 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33915 | // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5327 |
| 33916 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33917 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33919 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33920 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33921 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 33922 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 33923 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33924 | // (ST1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5335 |
| 33925 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 33926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 33927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33928 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 33929 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33930 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 33931 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33932 | // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 5342 |
| 33933 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 33935 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33936 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33937 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33938 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33939 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33940 | // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 5349 |
| 33941 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 33943 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33944 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33945 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33946 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33947 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33948 | // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 5356 |
| 33949 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33950 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 33951 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33952 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33953 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33954 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33955 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33956 | // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 5363 |
| 33957 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33958 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 33959 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33960 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33961 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33962 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33963 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33964 | // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 5370 |
| 33965 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33966 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 33967 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33968 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33970 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33971 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33972 | // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 5377 |
| 33973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33974 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 33975 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33976 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33978 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33979 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33980 | // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 5384 |
| 33981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 33983 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33984 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33985 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33986 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33987 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33988 | // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 5391 |
| 33989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 33990 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 33991 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 33992 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 33993 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 33994 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 33995 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 33996 | // (ST1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5398 |
| 33997 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 33998 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 33999 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34000 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34001 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34002 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 34003 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 34004 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34005 | // (ST1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5406 |
| 34006 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 34007 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 34008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34009 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34011 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 34012 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34013 | // (ST1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5413 |
| 34014 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 34015 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 34016 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34017 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34018 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34019 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 34020 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 34021 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34022 | // (ST1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5421 |
| 34023 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 34024 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 34025 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34026 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34027 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34028 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 34029 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34030 | // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5428 |
| 34031 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 34032 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34033 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34034 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34035 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34036 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34037 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34038 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34039 | // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5436 |
| 34040 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 34041 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34042 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34043 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34044 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34045 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34046 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34047 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34048 | // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5444 |
| 34049 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 34050 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34051 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34052 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34053 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34054 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34055 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34056 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34057 | // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 5452 |
| 34058 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34059 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34060 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34061 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34062 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34064 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34065 | // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 5459 |
| 34066 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34067 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 34068 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34069 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34070 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34072 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34073 | // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 5466 |
| 34074 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34075 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34076 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34077 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34078 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34079 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34080 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34081 | // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 5473 |
| 34082 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 34084 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34085 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34087 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34088 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34089 | // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 5480 |
| 34090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34091 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 34092 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34093 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34094 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34096 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34097 | // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 5487 |
| 34098 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34099 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34100 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34101 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34102 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34103 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34104 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34105 | // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 5494 |
| 34106 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34107 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 34108 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34109 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34112 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34113 | // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 5501 |
| 34114 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34115 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34116 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34117 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34118 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34120 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34121 | // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5508 |
| 34122 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34123 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34124 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34125 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34126 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34128 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34129 | // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 5515 |
| 34130 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34131 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 34132 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34133 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34134 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34135 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34136 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34137 | // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5522 |
| 34138 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34139 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34140 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34141 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34142 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34143 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34144 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34145 | // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5529 |
| 34146 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34147 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 34148 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34149 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34150 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34151 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34152 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34153 | // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5536 |
| 34154 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34155 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 34156 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34157 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34160 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34161 | // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 5543 |
| 34162 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34163 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34164 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34165 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34167 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34168 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34169 | // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 5550 |
| 34170 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 34172 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34173 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34174 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34175 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34176 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34177 | // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 5557 |
| 34178 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34180 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34181 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34182 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34184 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34185 | // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5564 |
| 34186 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34187 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34188 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34189 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34191 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34192 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34193 | // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 5571 |
| 34194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 34196 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34197 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34198 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34199 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34200 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34201 | // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5578 |
| 34202 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34204 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34205 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34206 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34207 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34208 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34209 | // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5585 |
| 34210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34211 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 34212 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34213 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34214 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34216 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34217 | // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5592 |
| 34218 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 34220 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34221 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34224 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34225 | // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5599 |
| 34226 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34228 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34229 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34232 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34233 | // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5606 |
| 34234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 34236 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34237 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34238 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34240 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34241 | // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5613 |
| 34242 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34243 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34244 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34245 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34246 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34247 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34248 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34249 | // (ST1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5620 |
| 34250 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 34251 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 34252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34253 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34254 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34255 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 34256 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 34257 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34258 | // (ST1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5628 |
| 34259 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 34260 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 34261 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34262 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34263 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34264 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 34265 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34266 | // (ST1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5635 |
| 34267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 34268 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 34269 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34270 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34271 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34272 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 34273 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 34274 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34275 | // (ST1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5643 |
| 34276 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 34277 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 34278 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34279 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34280 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34281 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 34282 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34283 | // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5650 |
| 34284 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 34285 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34287 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34288 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34289 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34290 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34291 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34292 | // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5658 |
| 34293 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 34294 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34295 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34296 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34297 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34298 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34299 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34300 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34301 | // (ST1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5666 |
| 34302 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 34303 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34304 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34305 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34306 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34307 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 34308 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34309 | // (ST1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5673 |
| 34310 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 34311 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34312 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34313 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34315 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34316 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34317 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34318 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34319 | // (ST1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5682 |
| 34320 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 34321 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34322 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34323 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34324 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34325 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34326 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34327 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34328 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34329 | // (ST1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5691 |
| 34330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 34331 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34332 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34333 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34335 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34336 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34337 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34338 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34339 | // (ST1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5700 |
| 34340 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 34341 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34342 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34343 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34344 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34345 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34346 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34347 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34348 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34349 | // (ST1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5709 |
| 34350 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 34351 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34352 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34353 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34355 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34356 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34357 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34358 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34359 | // (ST1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5718 |
| 34360 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 34361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34362 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34363 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34364 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34365 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34366 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34367 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34368 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34369 | // (ST1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5727 |
| 34370 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 34371 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34372 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34373 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34374 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34375 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34376 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34377 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34378 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34379 | // (ST1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5736 |
| 34380 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 34381 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34382 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34383 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34384 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34385 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34386 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34387 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34388 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34389 | // (ST1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5745 |
| 34390 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 34391 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34392 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34393 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34394 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34395 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34396 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34397 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34398 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34399 | // (ST1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5754 |
| 34400 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 34401 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 34402 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34403 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34404 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34405 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34406 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34407 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34408 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34409 | // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 5763 |
| 34410 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34411 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34412 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34413 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34414 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34415 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34416 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34417 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34418 | // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 5771 |
| 34419 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34420 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34421 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34422 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34423 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34424 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34425 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34426 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34427 | // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 5779 |
| 34428 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34429 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34430 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34431 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34432 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34433 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34434 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34435 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34436 | // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 5787 |
| 34437 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34438 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34439 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34440 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34441 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34442 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34443 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34444 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34445 | // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5795 |
| 34446 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 34447 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34448 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34449 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34450 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34453 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34454 | // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5803 |
| 34455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 34456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34457 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34458 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34460 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34461 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34462 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34463 | // (ST2Gi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 5811 |
| 34464 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34465 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34466 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34467 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34468 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 34469 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34470 | // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5817 |
| 34471 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 34472 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34473 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34474 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34475 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34476 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34477 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34478 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34479 | // (ST2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5825 |
| 34480 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 34481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34482 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34483 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34484 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34485 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 34486 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 34487 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34488 | // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5833 |
| 34489 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34491 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34492 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34493 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34494 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34495 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34496 | // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5840 |
| 34497 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34498 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34499 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34500 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34501 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34502 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34503 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34504 | // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5847 |
| 34505 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34506 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 34507 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34508 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34509 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34510 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34511 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34512 | // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5854 |
| 34513 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34514 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 34515 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34516 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34517 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34518 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34519 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34520 | // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5861 |
| 34521 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34522 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34523 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34524 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34525 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34526 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34527 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34528 | // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5868 |
| 34529 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34530 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 34531 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34532 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34533 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34534 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34535 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34536 | // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5875 |
| 34537 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34538 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34539 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34540 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34541 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34542 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34543 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34544 | // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5882 |
| 34545 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 34546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34547 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34548 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34549 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34550 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34551 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34552 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34553 | // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 5890 |
| 34554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34556 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34557 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34558 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34559 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34560 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34561 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34562 | // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 5898 |
| 34563 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34564 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34565 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34566 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34567 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34568 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34569 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34570 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34571 | // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 5906 |
| 34572 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34573 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34574 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34575 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34576 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34577 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34578 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34579 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34580 | // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 5914 |
| 34581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34582 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 34583 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34584 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34585 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34586 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34587 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34588 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34589 | // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5922 |
| 34590 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 34591 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34592 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34593 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34594 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34595 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34596 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34597 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34598 | // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5930 |
| 34599 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 34600 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34601 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34602 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34603 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34604 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34605 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34606 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34607 | // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5938 |
| 34608 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 34609 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34610 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34611 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34612 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34613 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34614 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34615 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34616 | // (ST3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5946 |
| 34617 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 34618 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34619 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34620 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34621 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34622 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 34623 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 34624 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34625 | // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5954 |
| 34626 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34627 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34628 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34629 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34630 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34631 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34632 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34633 | // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5961 |
| 34634 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34635 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34636 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34637 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34638 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34639 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34640 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34641 | // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5968 |
| 34642 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34643 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 34644 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34645 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34647 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34648 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34649 | // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5975 |
| 34650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34651 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 34652 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34653 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34655 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34656 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34657 | // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 5982 |
| 34658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34660 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34661 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34662 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34663 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34664 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34665 | // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 5989 |
| 34666 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 34668 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34669 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34670 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34671 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34672 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34673 | // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 5996 |
| 34674 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34675 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34676 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34677 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34678 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34679 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34680 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34681 | // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6003 |
| 34682 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 34683 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34685 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34686 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34687 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34688 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34689 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34690 | // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 6011 |
| 34691 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34692 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34693 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34694 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34695 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34696 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34697 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34698 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34699 | // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 6019 |
| 34700 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34701 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34702 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34703 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34704 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34705 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34706 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34707 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34708 | // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 6027 |
| 34709 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34710 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34711 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34712 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34713 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34714 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34715 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34716 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34717 | // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 6035 |
| 34718 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34719 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 34720 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34721 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34722 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34723 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34724 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34725 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34726 | // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6043 |
| 34727 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 34728 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34729 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34730 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34731 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34732 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34733 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34734 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34735 | // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6051 |
| 34736 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 34737 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34738 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34739 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34740 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34741 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34742 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34743 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34744 | // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 6059 |
| 34745 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34746 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 34747 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34748 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34749 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34750 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34751 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34752 | // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 6066 |
| 34753 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34754 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 34755 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34756 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34757 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34758 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34759 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34760 | // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 6073 |
| 34761 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34762 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 34763 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34764 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34765 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34766 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34767 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34768 | // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 6080 |
| 34769 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34770 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 34771 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34772 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34773 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34774 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34775 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34776 | // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 6087 |
| 34777 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34778 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 34779 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34780 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34781 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34782 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34783 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34784 | // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 6094 |
| 34785 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34786 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 34787 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34788 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34789 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34790 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34791 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34792 | // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 6101 |
| 34793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34794 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 34795 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34796 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34797 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34798 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34799 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34800 | // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6108 |
| 34801 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 34802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34803 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34804 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34805 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34806 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34807 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34808 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34809 | // (ST4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6116 |
| 34810 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 34811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34813 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34814 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34815 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 34816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 34817 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34818 | // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6124 |
| 34819 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 34820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 34821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34822 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34823 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 34825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 34826 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34827 | // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 6132 |
| 34828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 34830 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34831 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34832 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34833 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34835 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34836 | // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 6140 |
| 34837 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 34839 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34840 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34841 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34843 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34844 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34845 | // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 6148 |
| 34846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 34848 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34849 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34850 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34852 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34853 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34854 | // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 6156 |
| 34855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 34857 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34858 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 34859 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 34860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34862 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34863 | // (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6164 |
| 34864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 34865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 34866 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34867 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34868 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 34870 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34871 | // (STGi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6171 |
| 34872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34874 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34875 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34876 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 34877 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34878 | // (STLPi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn) - 6177 |
| 34879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 34880 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 34881 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34882 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34883 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSCP}, |
| 34884 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34885 | // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 6183 |
| 34886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 34887 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34888 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34889 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34890 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 34891 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34892 | // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 6189 |
| 34893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 34894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34895 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 34898 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34899 | // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 6195 |
| 34900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 34901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34902 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34903 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34904 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 34905 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34906 | // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 6201 |
| 34907 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 34908 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34909 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34910 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34911 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 34912 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34913 | // (STLURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 6207 |
| 34914 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 34915 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34916 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34917 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34918 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 34919 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34920 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34921 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34922 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34923 | // (STLURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 6216 |
| 34924 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 34925 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34926 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34927 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34928 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 34929 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34930 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34931 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34932 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34933 | // (STLURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 6225 |
| 34934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 34935 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34936 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34937 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34938 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 34939 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34940 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34942 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34943 | // (STLURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 6234 |
| 34944 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34945 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34946 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34947 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 34949 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34950 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34951 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34952 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34953 | // (STLURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 6243 |
| 34954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 34955 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34956 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34957 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34958 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 34959 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34960 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34961 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 34962 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34963 | // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6252 |
| 34964 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 34965 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 34966 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34967 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34968 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 34970 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34971 | // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6259 |
| 34972 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 34974 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34975 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 34978 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34979 | // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6266 |
| 34980 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 34981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 34982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34983 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34984 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 34985 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 34986 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 34987 | // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6273 |
| 34988 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 34989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 34990 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34991 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34992 | // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6277 |
| 34993 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 34994 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 34995 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 34996 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 34997 | // (STNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6281 |
| 34998 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 34999 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35000 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35001 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35002 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35003 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 35005 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35006 | // (STNT1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6289 |
| 35007 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 35008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35010 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35011 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35012 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35013 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35014 | // (STNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6296 |
| 35015 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 35016 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35017 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35018 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35019 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35020 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35021 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 35022 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35023 | // (STNT1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6304 |
| 35024 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 35025 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35026 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35027 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35028 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35029 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35030 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35031 | // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6311 |
| 35032 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35033 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35034 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35035 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35036 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35037 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35038 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35039 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35040 | // (STNT1B_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6319 |
| 35041 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35042 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35043 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35044 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35045 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35046 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 35047 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35048 | // (STNT1B_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6326 |
| 35049 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35050 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35051 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35052 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35053 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35054 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 35055 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35056 | // (STNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6333 |
| 35057 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 35058 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35059 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35060 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35061 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35062 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 35064 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35065 | // (STNT1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6341 |
| 35066 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 35067 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35069 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35070 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35072 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35073 | // (STNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6348 |
| 35074 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 35075 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35076 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35077 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35078 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35079 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 35081 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35082 | // (STNT1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6356 |
| 35083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 35084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35085 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35086 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35087 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35088 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35089 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35090 | // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6363 |
| 35091 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35092 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35093 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35094 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35096 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35097 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35098 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35099 | // (STNT1D_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6371 |
| 35100 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35101 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35102 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35103 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35104 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35105 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 35106 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35107 | // (STNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6378 |
| 35108 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 35109 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35110 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35111 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35112 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35114 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 35115 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35116 | // (STNT1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6386 |
| 35117 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 35118 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35119 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35120 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35122 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35123 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35124 | // (STNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6393 |
| 35125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 35126 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35127 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35128 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35129 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35130 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 35132 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35133 | // (STNT1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6401 |
| 35134 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 35135 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35136 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35137 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35138 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35139 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35140 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35141 | // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6408 |
| 35142 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35143 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35144 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35145 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35146 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35147 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35148 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35149 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35150 | // (STNT1H_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6416 |
| 35151 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35152 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35153 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35154 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35155 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35156 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 35157 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35158 | // (STNT1H_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6423 |
| 35159 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35160 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35161 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35162 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35163 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35164 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 35165 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35166 | // (STNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6430 |
| 35167 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 35168 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35169 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35170 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35171 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35172 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35173 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 35174 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35175 | // (STNT1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6438 |
| 35176 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 35177 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35178 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35179 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35181 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35182 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35183 | // (STNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6445 |
| 35184 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 35185 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35186 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35187 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35188 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 35191 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35192 | // (STNT1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6453 |
| 35193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 35194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 35195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35196 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35197 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35198 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 35199 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35200 | // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6460 |
| 35201 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35202 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35204 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35205 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35206 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35207 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35208 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35209 | // (STNT1W_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6468 |
| 35210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35211 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35212 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35213 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35214 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 35216 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35217 | // (STNT1W_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6475 |
| 35218 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 35220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35221 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 35224 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35225 | // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6482 |
| 35226 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 35227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 35228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35229 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35232 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35233 | // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6489 |
| 35234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35236 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35237 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35238 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35240 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35241 | // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6496 |
| 35242 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 35243 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 35244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35245 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35246 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35247 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35248 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35249 | // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6503 |
| 35250 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35251 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35253 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35254 | // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6507 |
| 35255 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35257 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35258 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35259 | // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 6511 |
| 35260 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35261 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35262 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35263 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35264 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35265 | // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6516 |
| 35266 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35268 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35269 | // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 6519 |
| 35270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 35271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35272 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35273 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35274 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35275 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35276 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35277 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35278 | // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6527 |
| 35279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 35280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35281 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35284 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35285 | // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 6533 |
| 35286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 35287 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35288 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35289 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35290 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35291 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35292 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35293 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35294 | // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6541 |
| 35295 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 35296 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35297 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35298 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35299 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35300 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35301 | // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 6547 |
| 35302 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35303 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35304 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35305 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35306 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35307 | // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6552 |
| 35308 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35310 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35311 | // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 6555 |
| 35312 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 35313 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35315 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35316 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35317 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35318 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35319 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35320 | // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6563 |
| 35321 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 35322 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35323 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35324 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35325 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35326 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35327 | // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend128 0, 0)) - 6569 |
| 35328 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35331 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35332 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35333 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35334 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35335 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35336 | // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6577 |
| 35337 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35338 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35339 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35340 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35342 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35343 | // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 6583 |
| 35344 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 35345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35347 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35348 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35349 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35350 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35351 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35352 | // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6591 |
| 35353 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 35354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35355 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35356 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35357 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35358 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35359 | // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 6597 |
| 35360 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35362 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35363 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35364 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35365 | // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6602 |
| 35366 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35367 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35368 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35369 | // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 6605 |
| 35370 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35371 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35372 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35373 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35374 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35375 | // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 6610 |
| 35376 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35377 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35378 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35379 | // (STR_PXI PPRorPNRAny:$Pt, GPR64sp:$Rn, 0) - 6613 |
| 35380 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRorPNRRegClassID}, |
| 35381 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35382 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35383 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35384 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35386 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35387 | // (STR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 6620 |
| 35388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 35389 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 35390 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35391 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35392 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35393 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35395 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35396 | // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 6628 |
| 35397 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35398 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35399 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35400 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35401 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35402 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35403 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35404 | // (STTNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6635 |
| 35405 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35406 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35407 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35408 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35409 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35410 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 35411 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35412 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35413 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 35414 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35415 | // (STTNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6645 |
| 35416 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35417 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35418 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35419 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35420 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35421 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 35422 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35423 | // (STTPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6652 |
| 35424 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35425 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35426 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35427 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35428 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35429 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 35430 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35431 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 35433 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35434 | // (STTPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6662 |
| 35435 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35437 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35438 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35439 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 35441 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35442 | // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 6669 |
| 35443 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35444 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35445 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35446 | // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 6672 |
| 35447 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35448 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35449 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35450 | // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 6675 |
| 35451 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35452 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35453 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35454 | // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 6678 |
| 35455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35457 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35458 | // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6681 |
| 35459 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35460 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35461 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35462 | // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6684 |
| 35463 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 35464 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35465 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35466 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35467 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35468 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35469 | // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6690 |
| 35470 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 35471 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35472 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35473 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35474 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35475 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35476 | // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6696 |
| 35477 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35478 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35479 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35480 | // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6699 |
| 35481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 35482 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35483 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35484 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35485 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35486 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35487 | // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6705 |
| 35488 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35489 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35490 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35491 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35492 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35493 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35494 | // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6711 |
| 35495 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 35496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35497 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35498 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35499 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 35500 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35501 | // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6717 |
| 35502 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35503 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35504 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35505 | // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 6720 |
| 35506 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35507 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35508 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35509 | // (STZ2Gi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6723 |
| 35510 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35511 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35512 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35513 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 35515 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35516 | // (STZGi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6729 |
| 35517 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35518 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35519 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35520 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35521 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 35522 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35523 | // (SUBPT_shift GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0) - 6735 |
| 35524 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35525 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35527 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35528 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35529 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCPA}, |
| 35530 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35531 | // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 6742 |
| 35532 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 35533 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 35534 | // (SUBSWrs WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 6744 |
| 35535 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 35536 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35537 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35538 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35539 | // (SUBSWrs WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, arith_shift32:$sh)) - 6748 |
| 35540 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 35541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35543 | // (SUBSWrs GPR32:$dst, WZR, (arith_shifted_reg32 GPR32:$src, 0)) - 6751 |
| 35544 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35545 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 35546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35547 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35548 | // (SUBSWrs GPR32:$dst, WZR, (arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)) - 6755 |
| 35549 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35550 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 35551 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35552 | // (SUBSWrs GPR32:$dst, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 6758 |
| 35553 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35556 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35557 | // (SUBSWrx WZR, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 6762 |
| 35558 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 35559 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 35560 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35561 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 35562 | // (SUBSWrx WZR, GPR32sp:$src1, (arith_extended_reg32_i32 GPR32:$src2, arith_extend:$sh)) - 6766 |
| 35563 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 35564 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 35565 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35566 | // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 6769 |
| 35567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35568 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 35569 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35570 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 35571 | // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 6773 |
| 35572 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35573 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35574 | // (SUBSXrs XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 6775 |
| 35575 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35577 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35578 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35579 | // (SUBSXrs XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, arith_shift64:$sh)) - 6779 |
| 35580 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35582 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35583 | // (SUBSXrs GPR64:$dst, XZR, (arith_shifted_reg64 GPR64:$src, 0)) - 6782 |
| 35584 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35585 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35587 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35588 | // (SUBSXrs GPR64:$dst, XZR, (arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)) - 6786 |
| 35589 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35590 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35591 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35592 | // (SUBSXrs GPR64:$dst, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 6789 |
| 35593 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35596 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35597 | // (SUBSXrx XZR, GPR64sp:$src1, (arith_extended_reg32_i64 GPR32:$src2, arith_extend:$sh)) - 6793 |
| 35598 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35599 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35600 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35601 | // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 6796 |
| 35602 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 35604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35605 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 35606 | // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 6800 |
| 35607 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35608 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35609 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35610 | // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6803 |
| 35611 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35612 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 35613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35614 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 35615 | // (SUBWrs GPR32:$dst, WZR, (arith_shifted_reg32 GPR32:$src, 0)) - 6807 |
| 35616 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35617 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 35618 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35619 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35620 | // (SUBWrs GPR32:$dst, WZR, (arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)) - 6811 |
| 35621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35622 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 35623 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35624 | // (SUBWrs GPR32:$dst, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 6814 |
| 35625 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35626 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35627 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35628 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35629 | // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 6818 |
| 35630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 35631 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 35632 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35633 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 35634 | // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 6822 |
| 35635 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 35636 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 35637 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35638 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 35639 | // (SUBXrs GPR64:$dst, XZR, (arith_shifted_reg64 GPR64:$src, 0)) - 6826 |
| 35640 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35641 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35642 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35643 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35644 | // (SUBXrs GPR64:$dst, XZR, (arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)) - 6830 |
| 35645 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35646 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35647 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35648 | // (SUBXrs GPR64:$dst, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 6833 |
| 35649 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35651 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35652 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35653 | // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 6837 |
| 35654 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 35655 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35656 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35657 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 35658 | // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6841 |
| 35659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 35660 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 35661 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35662 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 35663 | // (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 6845 |
| 35664 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35665 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35666 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35667 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35668 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35669 | // (SYSxt timm32_0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, timm32_0_7:$op2, XZR) - 6850 |
| 35670 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35671 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35672 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35673 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35674 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35675 | // (TCHANGEBri GPR64:$Xd, imm0_127:$imm, 0) - 6855 |
| 35676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35677 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35678 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35679 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureS1POE2}, |
| 35681 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35682 | // (TCHANGEBrr GPR64:$Xd, GPR64:$Xn, 0) - 6861 |
| 35683 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35685 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35686 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35687 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureS1POE2}, |
| 35688 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35689 | // (TCHANGEFri GPR64:$Xd, imm0_127:$imm, 0) - 6867 |
| 35690 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35691 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35692 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35693 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35694 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureS1POE2}, |
| 35695 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35696 | // (TCHANGEFrr GPR64:$Xd, GPR64:$Xn, 0) - 6873 |
| 35697 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35698 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35699 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35700 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35701 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureS1POE2}, |
| 35702 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35703 | // (TENTER imm0_127:$imm, 0) - 6879 |
| 35704 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35705 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35706 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35707 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureTEV}, |
| 35708 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35709 | // (TEXIT 0) - 6884 |
| 35710 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35711 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35712 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureTEV}, |
| 35713 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35714 | // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 6888 |
| 35715 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35717 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35718 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35719 | // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 6892 |
| 35720 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35721 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35722 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35723 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 35724 | // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 6896 |
| 35725 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35726 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35727 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35728 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 35729 | // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 6900 |
| 35730 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35732 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35733 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(63)}, |
| 35734 | // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 6904 |
| 35735 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35736 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35737 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35738 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 35739 | // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 6908 |
| 35740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35741 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35742 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35743 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 35744 | // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 6912 |
| 35745 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35746 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35747 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 35748 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35749 | // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 6916 |
| 35750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35751 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35752 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35753 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35754 | // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 6920 |
| 35755 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35756 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35757 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35758 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 35759 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35760 | // (UMOVvi32_idx0 GPR32:$dst, V128:$src, VectorIndex0:$idx) - 6925 |
| 35761 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35762 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35763 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35764 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 35765 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35766 | // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 6930 |
| 35767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35768 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35769 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35770 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 35771 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35772 | // (UMOVvi64_idx0 GPR64:$dst, V128:$src, VectorIndex0:$idx) - 6935 |
| 35773 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 35775 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35776 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 35777 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35778 | // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 6940 |
| 35779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35780 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35782 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 35783 | // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6944 |
| 35784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35785 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35786 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35787 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35788 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35789 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35790 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35791 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35792 | // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6952 |
| 35793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35794 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35795 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35796 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35797 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35798 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35799 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35800 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35801 | // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6960 |
| 35802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35803 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35804 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35805 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35806 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35807 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35809 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35810 | // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6968 |
| 35811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35812 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35813 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35814 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35815 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35818 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35819 | // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6976 |
| 35820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35821 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35822 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35823 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35826 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35827 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35828 | // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6984 |
| 35829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35830 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35831 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35832 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35833 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35836 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35837 | // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6992 |
| 35838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35839 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35840 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35841 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35843 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35844 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35845 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35846 | // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7000 |
| 35847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35848 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35849 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35850 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35852 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35853 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35854 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35855 | // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7008 |
| 35856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35857 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35858 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35859 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35862 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35863 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35864 | // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 7016 |
| 35865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35866 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35867 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35868 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35870 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35871 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35872 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35873 | // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7024 |
| 35874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35875 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35876 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35877 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35878 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35879 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35880 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35881 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35882 | // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7032 |
| 35883 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35884 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35885 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35886 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35887 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35888 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35889 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35890 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35891 | // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7040 |
| 35892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35893 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35894 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35895 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35898 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35899 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35900 | // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7048 |
| 35901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35902 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35903 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35904 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35907 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35908 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35909 | // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7056 |
| 35910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35911 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35912 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35913 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35914 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35915 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35916 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35917 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35918 | // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 7064 |
| 35919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35920 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35921 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35922 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35925 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35926 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35927 | // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7072 |
| 35928 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35929 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35930 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35931 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35933 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35934 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35935 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35936 | // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7080 |
| 35937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35938 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35939 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35940 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35942 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35943 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35944 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35945 | // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7088 |
| 35946 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35947 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35948 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35949 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35950 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35951 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35952 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35953 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35954 | // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7096 |
| 35955 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 35956 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35957 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35958 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35959 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35960 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35961 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35962 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35963 | // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7104 |
| 35964 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35965 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35966 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35967 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35968 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35970 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35971 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35972 | // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 7112 |
| 35973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 35974 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35975 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35976 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35978 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35979 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35980 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35981 | // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7120 |
| 35982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35983 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35984 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 35985 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35986 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35987 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35988 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35989 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35990 | // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7128 |
| 35991 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 35992 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35993 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 35994 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 35995 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 35996 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 35997 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 35998 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 35999 | // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7136 |
| 36000 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 36001 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36002 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36003 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36006 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36007 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36008 | // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7144 |
| 36009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 36010 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36011 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36012 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36013 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36014 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36015 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36016 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36017 | // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7152 |
| 36018 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 36019 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36020 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36021 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36022 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36023 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36025 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36026 | // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7160 |
| 36027 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 36028 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36029 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36030 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36034 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36035 | // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7168 |
| 36036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 36037 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36038 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36039 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36041 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36042 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36043 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36044 | // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7176 |
| 36045 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 36046 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36047 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36048 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36051 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36052 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36053 | // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7184 |
| 36054 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 36055 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36056 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36057 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36059 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36060 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36061 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36062 | // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 7192 |
| 36063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 36064 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36065 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36066 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36067 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36068 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36069 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36070 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36071 | // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7200 |
| 36072 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 36073 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36074 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36075 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36076 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36077 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36078 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36079 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36080 | // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7208 |
| 36081 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 36082 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36083 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36084 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36087 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36088 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36089 | // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7216 |
| 36090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 36091 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36092 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36093 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36094 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36096 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36097 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36098 | // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7224 |
| 36099 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 36100 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36101 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36102 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36103 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36104 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36105 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36106 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36107 | // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7232 |
| 36108 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 36109 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36110 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36111 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36112 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36114 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36115 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36116 | // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 7240 |
| 36117 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 36118 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36119 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36120 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36122 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36123 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36124 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36125 | // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7248 |
| 36126 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 36127 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36128 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36129 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36130 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36132 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36133 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36134 | // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7256 |
| 36135 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 36136 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36137 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36138 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36139 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36140 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36141 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36142 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36143 | // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7264 |
| 36144 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 36145 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36146 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36147 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36148 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36149 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36150 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36151 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36152 | // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7272 |
| 36153 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 36154 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36155 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36156 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36157 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36160 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36161 | // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7280 |
| 36162 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 36163 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36164 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 36165 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36167 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36168 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36169 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36170 | // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 7288 |
| 36171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 36172 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36173 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 36174 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 36175 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36176 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 36177 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36178 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36179 | // (XPACLRI) - 7296 |
| 36180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36181 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 36182 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36183 | // (ZERO_M { 1, 1, 1, 1, 1, 1, 1, 1 }) - 7299 |
| 36184 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(255)}, |
| 36185 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36186 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36187 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36188 | // (ZERO_M { 0, 1, 0, 1, 0, 1, 0, 1 }) - 7303 |
| 36189 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(85)}, |
| 36190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36191 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36192 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36193 | // (ZERO_M { 1, 0, 1, 0, 1, 0, 1, 0 }) - 7307 |
| 36194 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(170)}, |
| 36195 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36196 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36197 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36198 | // (ZERO_M { 0, 0, 0, 1, 0, 0, 0, 1 }) - 7311 |
| 36199 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(17)}, |
| 36200 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36201 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36202 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36203 | // (ZERO_M { 0, 0, 1, 0, 0, 0, 1, 0 }) - 7315 |
| 36204 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(34)}, |
| 36205 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36206 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36207 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36208 | // (ZERO_M { 0, 1, 0, 0, 0, 1, 0, 0 }) - 7319 |
| 36209 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(68)}, |
| 36210 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36211 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36212 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36213 | // (ZERO_M { 1, 0, 0, 0, 1, 0, 0, 0 }) - 7323 |
| 36214 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)}, |
| 36215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36216 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36217 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36218 | // (ZERO_M { 0, 0, 1, 1, 0, 0, 1, 1 }) - 7327 |
| 36219 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(51)}, |
| 36220 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36221 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36222 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36223 | // (ZERO_M { 1, 0, 0, 1, 1, 0, 0, 1 }) - 7331 |
| 36224 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(153)}, |
| 36225 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36226 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36227 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36228 | // (ZERO_M { 0, 1, 1, 0, 0, 1, 1, 0 }) - 7335 |
| 36229 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(102)}, |
| 36230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36232 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36233 | // (ZERO_M { 1, 1, 0, 0, 1, 1, 0, 0 }) - 7339 |
| 36234 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(204)}, |
| 36235 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36236 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36237 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36238 | // (ZERO_M { 0, 1, 1, 1, 0, 1, 1, 1 }) - 7343 |
| 36239 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(119)}, |
| 36240 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36241 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36242 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36243 | // (ZERO_M { 1, 0, 1, 1, 1, 0, 1, 1 }) - 7347 |
| 36244 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(187)}, |
| 36245 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36246 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36247 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36248 | // (ZERO_M { 1, 1, 0, 1, 1, 1, 0, 1 }) - 7351 |
| 36249 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(221)}, |
| 36250 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36251 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36252 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36253 | // (ZERO_M { 1, 1, 1, 0, 1, 1, 1, 0 }) - 7355 |
| 36254 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(238)}, |
| 36255 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 36256 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 36257 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 36258 | }; |
| 36259 | |
| 36260 | static const char AsmStrings[] = |
| 36261 | /* 0 */ "addpt $\x01, $\x02, $\x03\0" |
| 36262 | /* 17 */ "cmn $\x02, $\xFF\x03\x01\0" |
| 36263 | /* 30 */ "cmn $\x02, $\x03\0" |
| 36264 | /* 41 */ "cmn $\x02, $\x03$\xFF\x04\x02\0" |
| 36265 | /* 56 */ "adds $\x01, $\x02, $\x03\0" |
| 36266 | /* 72 */ "cmn $\x02, $\x03$\xFF\x04\x03\0" |
| 36267 | /* 87 */ "mov $\x01, $\x02\0" |
| 36268 | /* 98 */ "add $\x01, $\x02, $\x03\0" |
| 36269 | /* 113 */ "tst $\x02, $\xFF\x03\x04\0" |
| 36270 | /* 126 */ "tst $\x02, $\x03\0" |
| 36271 | /* 137 */ "tst $\x02, $\x03$\xFF\x04\x02\0" |
| 36272 | /* 152 */ "ands $\x01, $\x02, $\x03\0" |
| 36273 | /* 168 */ "tst $\x02, $\xFF\x03\x05\0" |
| 36274 | /* 181 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 36275 | /* 205 */ "and $\x01, $\x02, $\x03\0" |
| 36276 | /* 220 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 36277 | /* 243 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| 36278 | /* 264 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| 36279 | /* 285 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| 36280 | /* 306 */ "autia1716\0" |
| 36281 | /* 316 */ "autiasp\0" |
| 36282 | /* 324 */ "autiaz\0" |
| 36283 | /* 331 */ "autib1716\0" |
| 36284 | /* 341 */ "autibsp\0" |
| 36285 | /* 349 */ "autibz\0" |
| 36286 | /* 356 */ "bics $\x01, $\x02, $\x03\0" |
| 36287 | /* 372 */ "bic $\x01, $\x02, $\x03\0" |
| 36288 | /* 387 */ "chkfeat x16\0" |
| 36289 | /* 399 */ "clrex\0" |
| 36290 | /* 405 */ "cntb $\x01\0" |
| 36291 | /* 413 */ "cntb $\x01, $\xFF\x02\x0E\0" |
| 36292 | /* 427 */ "cntd $\x01\0" |
| 36293 | /* 435 */ "cntd $\x01, $\xFF\x02\x0E\0" |
| 36294 | /* 449 */ "cnth $\x01\0" |
| 36295 | /* 457 */ "cnth $\x01, $\xFF\x02\x0E\0" |
| 36296 | /* 471 */ "cntw $\x01\0" |
| 36297 | /* 479 */ "cntw $\x01, $\xFF\x02\x0E\0" |
| 36298 | /* 493 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0" |
| 36299 | /* 516 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0" |
| 36300 | /* 539 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0" |
| 36301 | /* 562 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0" |
| 36302 | /* 585 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0" |
| 36303 | /* 606 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0" |
| 36304 | /* 627 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0" |
| 36305 | /* 648 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0" |
| 36306 | /* 669 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0" |
| 36307 | /* 692 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0" |
| 36308 | /* 715 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0" |
| 36309 | /* 738 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0" |
| 36310 | /* 761 */ "cset $\x01, $\xFF\x04\x14\0" |
| 36311 | /* 775 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0" |
| 36312 | /* 793 */ "csetm $\x01, $\xFF\x04\x14\0" |
| 36313 | /* 808 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0" |
| 36314 | /* 826 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0" |
| 36315 | /* 844 */ "dcps1\0" |
| 36316 | /* 850 */ "dcps2\0" |
| 36317 | /* 856 */ "dcps3\0" |
| 36318 | /* 862 */ "decb $\x01\0" |
| 36319 | /* 870 */ "decb $\x01, $\xFF\x03\x0E\0" |
| 36320 | /* 884 */ "decd $\x01\0" |
| 36321 | /* 892 */ "decd $\x01, $\xFF\x03\x0E\0" |
| 36322 | /* 906 */ "decd $\xFF\x01\x10\0" |
| 36323 | /* 916 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 36324 | /* 932 */ "dech $\x01\0" |
| 36325 | /* 940 */ "dech $\x01, $\xFF\x03\x0E\0" |
| 36326 | /* 954 */ "dech $\xFF\x01\x09\0" |
| 36327 | /* 964 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 36328 | /* 980 */ "decw $\x01\0" |
| 36329 | /* 988 */ "decw $\x01, $\xFF\x03\x0E\0" |
| 36330 | /* 1002 */ "decw $\xFF\x01\x0B\0" |
| 36331 | /* 1012 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 36332 | /* 1028 */ "ssbb\0" |
| 36333 | /* 1033 */ "pssbb\0" |
| 36334 | /* 1039 */ "dfb\0" |
| 36335 | /* 1043 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0" |
| 36336 | /* 1058 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0" |
| 36337 | /* 1073 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0" |
| 36338 | /* 1088 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0" |
| 36339 | /* 1104 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0" |
| 36340 | /* 1120 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0" |
| 36341 | /* 1136 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0" |
| 36342 | /* 1151 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0" |
| 36343 | /* 1166 */ "fmov $\xFF\x01\x10, #0.0\0" |
| 36344 | /* 1182 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0" |
| 36345 | /* 1197 */ "fmov $\xFF\x01\x09, #0.0\0" |
| 36346 | /* 1213 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0" |
| 36347 | /* 1228 */ "fmov $\xFF\x01\x0B, #0.0\0" |
| 36348 | /* 1244 */ "mov $\xFF\x01\x06, $\x02\0" |
| 36349 | /* 1257 */ "mov $\xFF\x01\x10, $\x02\0" |
| 36350 | /* 1270 */ "mov $\xFF\x01\x09, $\x02\0" |
| 36351 | /* 1283 */ "mov $\xFF\x01\x0B, $\x02\0" |
| 36352 | /* 1296 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0" |
| 36353 | /* 1311 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0" |
| 36354 | /* 1330 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0" |
| 36355 | /* 1345 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0" |
| 36356 | /* 1364 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0" |
| 36357 | /* 1379 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0" |
| 36358 | /* 1398 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0" |
| 36359 | /* 1413 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0" |
| 36360 | /* 1432 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0" |
| 36361 | /* 1447 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0" |
| 36362 | /* 1466 */ "eon $\x01, $\x02, $\x03\0" |
| 36363 | /* 1481 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 36364 | /* 1505 */ "eor $\x01, $\x02, $\x03\0" |
| 36365 | /* 1520 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 36366 | /* 1543 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| 36367 | /* 1564 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| 36368 | /* 1585 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| 36369 | /* 1606 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 36370 | /* 1639 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 36371 | /* 1672 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 36372 | /* 1705 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 36373 | /* 1738 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 36374 | /* 1771 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 36375 | /* 1804 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 36376 | /* 1837 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 36377 | /* 1870 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 36378 | /* 1903 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 36379 | /* 1936 */ "ror $\x01, $\x02, $\x04\0" |
| 36380 | /* 1951 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| 36381 | /* 1975 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| 36382 | /* 1999 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| 36383 | /* 2023 */ "fmov $\xFF\x01\x10, $\xFF\x02\x22\0" |
| 36384 | /* 2039 */ "fmov $\xFF\x01\x09, $\xFF\x02\x22\0" |
| 36385 | /* 2055 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x22\0" |
| 36386 | /* 2071 */ "gcspopm\0" |
| 36387 | /* 2079 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36388 | /* 2105 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36389 | /* 2131 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36390 | /* 2157 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36391 | /* 2183 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36392 | /* 2209 */ "ld1q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36393 | /* 2235 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36394 | /* 2262 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36395 | /* 2289 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36396 | /* 2316 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36397 | /* 2343 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36398 | /* 2370 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36399 | /* 2396 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36400 | /* 2422 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36401 | /* 2450 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36402 | /* 2478 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36403 | /* 2506 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36404 | /* 2534 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36405 | /* 2562 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36406 | /* 2591 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36407 | /* 2620 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36408 | /* 2649 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36409 | /* 2678 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36410 | /* 2707 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36411 | /* 2735 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36412 | /* 2763 */ "yield\0" |
| 36413 | /* 2769 */ "wfe\0" |
| 36414 | /* 2773 */ "wfi\0" |
| 36415 | /* 2777 */ "sev\0" |
| 36416 | /* 2781 */ "sevl\0" |
| 36417 | /* 2786 */ "dgh\0" |
| 36418 | /* 2790 */ "esb\0" |
| 36419 | /* 2794 */ "csdb\0" |
| 36420 | /* 2799 */ "bti r\0" |
| 36421 | /* 2805 */ "bti\0" |
| 36422 | /* 2809 */ "bti $\xFF\x01\x26\0" |
| 36423 | /* 2818 */ "psb $\xFF\x01\x27\0" |
| 36424 | /* 2827 */ "gcsb dsync\0" |
| 36425 | /* 2838 */ "clrbhb\0" |
| 36426 | /* 2845 */ "incb $\x01\0" |
| 36427 | /* 2853 */ "incb $\x01, $\xFF\x03\x0E\0" |
| 36428 | /* 2867 */ "incd $\x01\0" |
| 36429 | /* 2875 */ "incd $\x01, $\xFF\x03\x0E\0" |
| 36430 | /* 2889 */ "incd $\xFF\x01\x10\0" |
| 36431 | /* 2899 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 36432 | /* 2915 */ "inch $\x01\0" |
| 36433 | /* 2923 */ "inch $\x01, $\xFF\x03\x0E\0" |
| 36434 | /* 2937 */ "inch $\xFF\x01\x09\0" |
| 36435 | /* 2947 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 36436 | /* 2963 */ "incw $\x01\0" |
| 36437 | /* 2971 */ "incw $\x01, $\xFF\x03\x0E\0" |
| 36438 | /* 2985 */ "incw $\xFF\x01\x0B\0" |
| 36439 | /* 2995 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 36440 | /* 3011 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0" |
| 36441 | /* 3044 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0" |
| 36442 | /* 3077 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0" |
| 36443 | /* 3110 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0" |
| 36444 | /* 3143 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0" |
| 36445 | /* 3176 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0" |
| 36446 | /* 3209 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0" |
| 36447 | /* 3242 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0" |
| 36448 | /* 3275 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0" |
| 36449 | /* 3308 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0" |
| 36450 | /* 3341 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04\0" |
| 36451 | /* 3360 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19\0" |
| 36452 | /* 3387 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04\0" |
| 36453 | /* 3406 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19\0" |
| 36454 | /* 3433 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04\0" |
| 36455 | /* 3452 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19\0" |
| 36456 | /* 3479 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04\0" |
| 36457 | /* 3498 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19\0" |
| 36458 | /* 3525 */ "irg $\x01, $\x02\0" |
| 36459 | /* 3536 */ "isb\0" |
| 36460 | /* 3540 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| 36461 | /* 3564 */ "ld1b $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0" |
| 36462 | /* 3588 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| 36463 | /* 3612 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36464 | /* 3636 */ "ld1b $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36465 | /* 3660 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36466 | /* 3684 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36467 | /* 3708 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| 36468 | /* 3732 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| 36469 | /* 3756 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36470 | /* 3780 */ "ld1d $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 36471 | /* 3804 */ "ld1 $\xFF\x02\x2C, [$\x01], #64\0" |
| 36472 | /* 3824 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0" |
| 36473 | /* 3844 */ "ld1 $\xFF\x02\x2E, [$\x01], #64\0" |
| 36474 | /* 3864 */ "ld1 $\xFF\x02\x2F, [$\x01], #32\0" |
| 36475 | /* 3884 */ "ld1 $\xFF\x02\x30, [$\x01], #32\0" |
| 36476 | /* 3904 */ "ld1 $\xFF\x02\x31, [$\x01], #64\0" |
| 36477 | /* 3924 */ "ld1 $\xFF\x02\x32, [$\x01], #32\0" |
| 36478 | /* 3944 */ "ld1 $\xFF\x02\x33, [$\x01], #64\0" |
| 36479 | /* 3964 */ "ld1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| 36480 | /* 3988 */ "ld1h $\xFF\x01\x34, $\xFF\x02\x29/z, [$\x03]\0" |
| 36481 | /* 4012 */ "ld1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| 36482 | /* 4036 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36483 | /* 4060 */ "ld1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36484 | /* 4084 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36485 | /* 4108 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0" |
| 36486 | /* 4128 */ "ld1 $\xFF\x02\x2D, [$\x01], #8\0" |
| 36487 | /* 4147 */ "ld1 $\xFF\x02\x2E, [$\x01], #16\0" |
| 36488 | /* 4167 */ "ld1 $\xFF\x02\x2F, [$\x01], #8\0" |
| 36489 | /* 4186 */ "ld1 $\xFF\x02\x30, [$\x01], #8\0" |
| 36490 | /* 4205 */ "ld1 $\xFF\x02\x31, [$\x01], #16\0" |
| 36491 | /* 4225 */ "ld1 $\xFF\x02\x32, [$\x01], #8\0" |
| 36492 | /* 4244 */ "ld1 $\xFF\x02\x33, [$\x01], #16\0" |
| 36493 | /* 4264 */ "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36494 | /* 4289 */ "ld1rb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36495 | /* 4314 */ "ld1rb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36496 | /* 4339 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36497 | /* 4364 */ "ld1rd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36498 | /* 4389 */ "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36499 | /* 4414 */ "ld1rh $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36500 | /* 4439 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36501 | /* 4464 */ "ld1rob $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36502 | /* 4490 */ "ld1rod $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36503 | /* 4516 */ "ld1roh $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36504 | /* 4542 */ "ld1row $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36505 | /* 4568 */ "ld1rqb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36506 | /* 4594 */ "ld1rqd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36507 | /* 4620 */ "ld1rqh $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36508 | /* 4646 */ "ld1rqw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36509 | /* 4672 */ "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36510 | /* 4698 */ "ld1rsb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36511 | /* 4724 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36512 | /* 4750 */ "ld1rsh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36513 | /* 4776 */ "ld1rsh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36514 | /* 4802 */ "ld1rsw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36515 | /* 4828 */ "ld1rw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36516 | /* 4853 */ "ld1rw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36517 | /* 4878 */ "ld1r $\xFF\x02\x2C, [$\x01], #1\0" |
| 36518 | /* 4898 */ "ld1r $\xFF\x02\x2D, [$\x01], #8\0" |
| 36519 | /* 4918 */ "ld1r $\xFF\x02\x2E, [$\x01], #8\0" |
| 36520 | /* 4938 */ "ld1r $\xFF\x02\x2F, [$\x01], #4\0" |
| 36521 | /* 4958 */ "ld1r $\xFF\x02\x30, [$\x01], #2\0" |
| 36522 | /* 4978 */ "ld1r $\xFF\x02\x31, [$\x01], #4\0" |
| 36523 | /* 4998 */ "ld1r $\xFF\x02\x32, [$\x01], #1\0" |
| 36524 | /* 5018 */ "ld1r $\xFF\x02\x33, [$\x01], #2\0" |
| 36525 | /* 5038 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36526 | /* 5063 */ "ld1sb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36527 | /* 5088 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36528 | /* 5113 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36529 | /* 5138 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36530 | /* 5163 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36531 | /* 5188 */ "ld1 $\xFF\x02\x2C, [$\x01], #48\0" |
| 36532 | /* 5208 */ "ld1 $\xFF\x02\x2D, [$\x01], #24\0" |
| 36533 | /* 5228 */ "ld1 $\xFF\x02\x2E, [$\x01], #48\0" |
| 36534 | /* 5248 */ "ld1 $\xFF\x02\x2F, [$\x01], #24\0" |
| 36535 | /* 5268 */ "ld1 $\xFF\x02\x30, [$\x01], #24\0" |
| 36536 | /* 5288 */ "ld1 $\xFF\x02\x31, [$\x01], #48\0" |
| 36537 | /* 5308 */ "ld1 $\xFF\x02\x32, [$\x01], #24\0" |
| 36538 | /* 5328 */ "ld1 $\xFF\x02\x33, [$\x01], #48\0" |
| 36539 | /* 5348 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0" |
| 36540 | /* 5368 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0" |
| 36541 | /* 5388 */ "ld1 $\xFF\x02\x2E, [$\x01], #32\0" |
| 36542 | /* 5408 */ "ld1 $\xFF\x02\x2F, [$\x01], #16\0" |
| 36543 | /* 5428 */ "ld1 $\xFF\x02\x30, [$\x01], #16\0" |
| 36544 | /* 5448 */ "ld1 $\xFF\x02\x31, [$\x01], #32\0" |
| 36545 | /* 5468 */ "ld1 $\xFF\x02\x32, [$\x01], #16\0" |
| 36546 | /* 5488 */ "ld1 $\xFF\x02\x33, [$\x01], #32\0" |
| 36547 | /* 5508 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| 36548 | /* 5532 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| 36549 | /* 5556 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36550 | /* 5580 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36551 | /* 5604 */ "ld1w $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 36552 | /* 5628 */ "ld1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36553 | /* 5664 */ "ld1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36554 | /* 5700 */ "ld1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36555 | /* 5736 */ "ld1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36556 | /* 5772 */ "ld1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36557 | /* 5808 */ "ld1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36558 | /* 5844 */ "ld1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36559 | /* 5880 */ "ld1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36560 | /* 5916 */ "ld1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36561 | /* 5952 */ "ld1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 36562 | /* 5988 */ "ld1 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #2\0" |
| 36563 | /* 6011 */ "ld1 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #4\0" |
| 36564 | /* 6034 */ "ld1 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #8\0" |
| 36565 | /* 6057 */ "ld1 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #1\0" |
| 36566 | /* 6080 */ "ld2b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36567 | /* 6104 */ "ld2d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36568 | /* 6128 */ "ld2h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36569 | /* 6152 */ "ld2q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 36570 | /* 6176 */ "ld2r $\xFF\x02\x2C, [$\x01], #2\0" |
| 36571 | /* 6196 */ "ld2r $\xFF\x02\x2D, [$\x01], #16\0" |
| 36572 | /* 6217 */ "ld2r $\xFF\x02\x2E, [$\x01], #16\0" |
| 36573 | /* 6238 */ "ld2r $\xFF\x02\x2F, [$\x01], #8\0" |
| 36574 | /* 6258 */ "ld2r $\xFF\x02\x30, [$\x01], #4\0" |
| 36575 | /* 6278 */ "ld2r $\xFF\x02\x31, [$\x01], #8\0" |
| 36576 | /* 6298 */ "ld2r $\xFF\x02\x32, [$\x01], #2\0" |
| 36577 | /* 6318 */ "ld2r $\xFF\x02\x33, [$\x01], #4\0" |
| 36578 | /* 6338 */ "ld2 $\xFF\x02\x2C, [$\x01], #32\0" |
| 36579 | /* 6358 */ "ld2 $\xFF\x02\x2E, [$\x01], #32\0" |
| 36580 | /* 6378 */ "ld2 $\xFF\x02\x2F, [$\x01], #16\0" |
| 36581 | /* 6398 */ "ld2 $\xFF\x02\x30, [$\x01], #16\0" |
| 36582 | /* 6418 */ "ld2 $\xFF\x02\x31, [$\x01], #32\0" |
| 36583 | /* 6438 */ "ld2 $\xFF\x02\x32, [$\x01], #16\0" |
| 36584 | /* 6458 */ "ld2 $\xFF\x02\x33, [$\x01], #32\0" |
| 36585 | /* 6478 */ "ld2w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36586 | /* 6502 */ "ld2 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #4\0" |
| 36587 | /* 6525 */ "ld2 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #8\0" |
| 36588 | /* 6548 */ "ld2 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #16\0" |
| 36589 | /* 6572 */ "ld2 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #2\0" |
| 36590 | /* 6595 */ "ld3b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36591 | /* 6619 */ "ld3d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36592 | /* 6643 */ "ld3h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36593 | /* 6667 */ "ld3q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 36594 | /* 6691 */ "ld3r $\xFF\x02\x2C, [$\x01], #3\0" |
| 36595 | /* 6711 */ "ld3r $\xFF\x02\x2D, [$\x01], #24\0" |
| 36596 | /* 6732 */ "ld3r $\xFF\x02\x2E, [$\x01], #24\0" |
| 36597 | /* 6753 */ "ld3r $\xFF\x02\x2F, [$\x01], #12\0" |
| 36598 | /* 6774 */ "ld3r $\xFF\x02\x30, [$\x01], #6\0" |
| 36599 | /* 6794 */ "ld3r $\xFF\x02\x31, [$\x01], #12\0" |
| 36600 | /* 6815 */ "ld3r $\xFF\x02\x32, [$\x01], #3\0" |
| 36601 | /* 6835 */ "ld3r $\xFF\x02\x33, [$\x01], #6\0" |
| 36602 | /* 6855 */ "ld3 $\xFF\x02\x2C, [$\x01], #48\0" |
| 36603 | /* 6875 */ "ld3 $\xFF\x02\x2E, [$\x01], #48\0" |
| 36604 | /* 6895 */ "ld3 $\xFF\x02\x2F, [$\x01], #24\0" |
| 36605 | /* 6915 */ "ld3 $\xFF\x02\x30, [$\x01], #24\0" |
| 36606 | /* 6935 */ "ld3 $\xFF\x02\x31, [$\x01], #48\0" |
| 36607 | /* 6955 */ "ld3 $\xFF\x02\x32, [$\x01], #24\0" |
| 36608 | /* 6975 */ "ld3 $\xFF\x02\x33, [$\x01], #48\0" |
| 36609 | /* 6995 */ "ld3w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36610 | /* 7019 */ "ld3 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #6\0" |
| 36611 | /* 7042 */ "ld3 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #12\0" |
| 36612 | /* 7066 */ "ld3 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #24\0" |
| 36613 | /* 7090 */ "ld3 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #3\0" |
| 36614 | /* 7113 */ "ld4b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36615 | /* 7137 */ "ld4d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36616 | /* 7161 */ "ld4 $\xFF\x02\x2C, [$\x01], #64\0" |
| 36617 | /* 7181 */ "ld4 $\xFF\x02\x2E, [$\x01], #64\0" |
| 36618 | /* 7201 */ "ld4 $\xFF\x02\x2F, [$\x01], #32\0" |
| 36619 | /* 7221 */ "ld4 $\xFF\x02\x30, [$\x01], #32\0" |
| 36620 | /* 7241 */ "ld4 $\xFF\x02\x31, [$\x01], #64\0" |
| 36621 | /* 7261 */ "ld4 $\xFF\x02\x32, [$\x01], #32\0" |
| 36622 | /* 7281 */ "ld4 $\xFF\x02\x33, [$\x01], #64\0" |
| 36623 | /* 7301 */ "ld4h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36624 | /* 7325 */ "ld4q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 36625 | /* 7349 */ "ld4r $\xFF\x02\x2C, [$\x01], #4\0" |
| 36626 | /* 7369 */ "ld4r $\xFF\x02\x2D, [$\x01], #32\0" |
| 36627 | /* 7390 */ "ld4r $\xFF\x02\x2E, [$\x01], #32\0" |
| 36628 | /* 7411 */ "ld4r $\xFF\x02\x2F, [$\x01], #16\0" |
| 36629 | /* 7432 */ "ld4r $\xFF\x02\x30, [$\x01], #8\0" |
| 36630 | /* 7452 */ "ld4r $\xFF\x02\x31, [$\x01], #16\0" |
| 36631 | /* 7473 */ "ld4r $\xFF\x02\x32, [$\x01], #4\0" |
| 36632 | /* 7493 */ "ld4r $\xFF\x02\x33, [$\x01], #8\0" |
| 36633 | /* 7513 */ "ld4w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36634 | /* 7537 */ "ld4 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #8\0" |
| 36635 | /* 7560 */ "ld4 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #16\0" |
| 36636 | /* 7584 */ "ld4 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #32\0" |
| 36637 | /* 7608 */ "ld4 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #4\0" |
| 36638 | /* 7631 */ "staddb $\x02, [$\x03]\0" |
| 36639 | /* 7647 */ "staddh $\x02, [$\x03]\0" |
| 36640 | /* 7663 */ "staddlb $\x02, [$\x03]\0" |
| 36641 | /* 7680 */ "staddlh $\x02, [$\x03]\0" |
| 36642 | /* 7697 */ "staddl $\x02, [$\x03]\0" |
| 36643 | /* 7713 */ "stadd $\x02, [$\x03]\0" |
| 36644 | /* 7728 */ "ldapp $\x01, $\x02, [$\x03]\0" |
| 36645 | /* 7747 */ "ldapurb $\x01, [$\x02]\0" |
| 36646 | /* 7764 */ "ldapurh $\x01, [$\x02]\0" |
| 36647 | /* 7781 */ "ldapursb $\x01, [$\x02]\0" |
| 36648 | /* 7799 */ "ldapursh $\x01, [$\x02]\0" |
| 36649 | /* 7817 */ "ldapursw $\x01, [$\x02]\0" |
| 36650 | /* 7835 */ "ldapur $\x01, [$\x02]\0" |
| 36651 | /* 7851 */ "ldap $\x01, $\x02, [$\x03]\0" |
| 36652 | /* 7869 */ "stclrb $\x02, [$\x03]\0" |
| 36653 | /* 7885 */ "stclrh $\x02, [$\x03]\0" |
| 36654 | /* 7901 */ "stclrlb $\x02, [$\x03]\0" |
| 36655 | /* 7918 */ "stclrlh $\x02, [$\x03]\0" |
| 36656 | /* 7935 */ "stclrl $\x02, [$\x03]\0" |
| 36657 | /* 7951 */ "stclr $\x02, [$\x03]\0" |
| 36658 | /* 7966 */ "steorb $\x02, [$\x03]\0" |
| 36659 | /* 7982 */ "steorh $\x02, [$\x03]\0" |
| 36660 | /* 7998 */ "steorlb $\x02, [$\x03]\0" |
| 36661 | /* 8015 */ "steorlh $\x02, [$\x03]\0" |
| 36662 | /* 8032 */ "steorl $\x02, [$\x03]\0" |
| 36663 | /* 8048 */ "steor $\x02, [$\x03]\0" |
| 36664 | /* 8063 */ "ldff1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36665 | /* 8089 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36666 | /* 8115 */ "ldff1b $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36667 | /* 8141 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36668 | /* 8167 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36669 | /* 8193 */ "ldff1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36670 | /* 8219 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36671 | /* 8245 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36672 | /* 8271 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36673 | /* 8298 */ "ldff1sb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36674 | /* 8325 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36675 | /* 8352 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36676 | /* 8379 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36677 | /* 8406 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36678 | /* 8433 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36679 | /* 8459 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36680 | /* 8485 */ "ldg $\x01, [$\x03]\0" |
| 36681 | /* 8498 */ "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36682 | /* 8524 */ "ldnf1b $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36683 | /* 8550 */ "ldnf1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36684 | /* 8576 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36685 | /* 8602 */ "ldnf1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36686 | /* 8628 */ "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36687 | /* 8654 */ "ldnf1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36688 | /* 8680 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36689 | /* 8706 */ "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36690 | /* 8733 */ "ldnf1sb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36691 | /* 8760 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36692 | /* 8787 */ "ldnf1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36693 | /* 8814 */ "ldnf1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36694 | /* 8841 */ "ldnf1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36695 | /* 8868 */ "ldnf1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36696 | /* 8894 */ "ldnf1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36697 | /* 8920 */ "ldnp $\x01, $\x02, [$\x03]\0" |
| 36698 | /* 8938 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| 36699 | /* 8964 */ "ldnt1b $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0" |
| 36700 | /* 8990 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| 36701 | /* 9016 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| 36702 | /* 9042 */ "ldnt1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36703 | /* 9070 */ "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36704 | /* 9098 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| 36705 | /* 9124 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| 36706 | /* 9150 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 36707 | /* 9176 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36708 | /* 9204 */ "ldnt1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| 36709 | /* 9230 */ "ldnt1h $\xFF\x01\x34, $\xFF\x02\x29/z, [$\x03]\0" |
| 36710 | /* 9256 */ "ldnt1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| 36711 | /* 9282 */ "ldnt1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0" |
| 36712 | /* 9308 */ "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36713 | /* 9336 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36714 | /* 9364 */ "ldnt1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36715 | /* 9393 */ "ldnt1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36716 | /* 9422 */ "ldnt1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36717 | /* 9451 */ "ldnt1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36718 | /* 9480 */ "ldnt1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36719 | /* 9509 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| 36720 | /* 9535 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| 36721 | /* 9561 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 36722 | /* 9587 */ "ldnt1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 36723 | /* 9615 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 36724 | /* 9643 */ "ldp $\x01, $\x02, [$\x03]\0" |
| 36725 | /* 9660 */ "ldpsw $\x01, $\x02, [$\x03]\0" |
| 36726 | /* 9679 */ "ldraa $\x01, [$\x02]\0" |
| 36727 | /* 9694 */ "ldrab $\x01, [$\x02]\0" |
| 36728 | /* 9709 */ "ldrb $\x01, [$\x02, $\x03]\0" |
| 36729 | /* 9727 */ "ldrb $\x01, [$\x02]\0" |
| 36730 | /* 9741 */ "ldr $\x01, [$\x02, $\x03]\0" |
| 36731 | /* 9758 */ "ldr $\x01, [$\x02]\0" |
| 36732 | /* 9771 */ "ldrh $\x01, [$\x02, $\x03]\0" |
| 36733 | /* 9789 */ "ldrh $\x01, [$\x02]\0" |
| 36734 | /* 9803 */ "ldrsb $\x01, [$\x02, $\x03]\0" |
| 36735 | /* 9822 */ "ldrsb $\x01, [$\x02]\0" |
| 36736 | /* 9837 */ "ldrsh $\x01, [$\x02, $\x03]\0" |
| 36737 | /* 9856 */ "ldrsh $\x01, [$\x02]\0" |
| 36738 | /* 9871 */ "ldrsw $\x01, [$\x02, $\x03]\0" |
| 36739 | /* 9890 */ "ldrsw $\x01, [$\x02]\0" |
| 36740 | /* 9905 */ "ldr $\xFF\x01\x07, [$\x02]\0" |
| 36741 | /* 9920 */ "ldr $\xFF\x01\x37[$\x02, $\xFF\x03\x20], [$\x04]\0" |
| 36742 | /* 9945 */ "stsetb $\x02, [$\x03]\0" |
| 36743 | /* 9961 */ "stseth $\x02, [$\x03]\0" |
| 36744 | /* 9977 */ "stsetlb $\x02, [$\x03]\0" |
| 36745 | /* 9994 */ "stsetlh $\x02, [$\x03]\0" |
| 36746 | /* 10011 */ "stsetl $\x02, [$\x03]\0" |
| 36747 | /* 10027 */ "stset $\x02, [$\x03]\0" |
| 36748 | /* 10042 */ "stsmaxb $\x02, [$\x03]\0" |
| 36749 | /* 10059 */ "stsmaxh $\x02, [$\x03]\0" |
| 36750 | /* 10076 */ "stsmaxlb $\x02, [$\x03]\0" |
| 36751 | /* 10094 */ "stsmaxlh $\x02, [$\x03]\0" |
| 36752 | /* 10112 */ "stsmaxl $\x02, [$\x03]\0" |
| 36753 | /* 10129 */ "stsmax $\x02, [$\x03]\0" |
| 36754 | /* 10145 */ "stsminb $\x02, [$\x03]\0" |
| 36755 | /* 10162 */ "stsminh $\x02, [$\x03]\0" |
| 36756 | /* 10179 */ "stsminlb $\x02, [$\x03]\0" |
| 36757 | /* 10197 */ "stsminlh $\x02, [$\x03]\0" |
| 36758 | /* 10215 */ "stsminl $\x02, [$\x03]\0" |
| 36759 | /* 10232 */ "stsmin $\x02, [$\x03]\0" |
| 36760 | /* 10248 */ "sttaddl $\x02, [$\x03]\0" |
| 36761 | /* 10265 */ "sttadd $\x02, [$\x03]\0" |
| 36762 | /* 10281 */ "sttclrl $\x02, [$\x03]\0" |
| 36763 | /* 10298 */ "sttclr $\x02, [$\x03]\0" |
| 36764 | /* 10314 */ "ldtnp $\x01, $\x02, [$\x03]\0" |
| 36765 | /* 10333 */ "ldtp $\x01, $\x02, [$\x03]\0" |
| 36766 | /* 10351 */ "ldtrb $\x01, [$\x02]\0" |
| 36767 | /* 10366 */ "ldtrh $\x01, [$\x02]\0" |
| 36768 | /* 10381 */ "ldtrsb $\x01, [$\x02]\0" |
| 36769 | /* 10397 */ "ldtrsh $\x01, [$\x02]\0" |
| 36770 | /* 10413 */ "ldtrsw $\x01, [$\x02]\0" |
| 36771 | /* 10429 */ "ldtr $\x01, [$\x02]\0" |
| 36772 | /* 10443 */ "sttsetl $\x02, [$\x03]\0" |
| 36773 | /* 10460 */ "sttset $\x02, [$\x03]\0" |
| 36774 | /* 10476 */ "stumaxb $\x02, [$\x03]\0" |
| 36775 | /* 10493 */ "stumaxh $\x02, [$\x03]\0" |
| 36776 | /* 10510 */ "stumaxlb $\x02, [$\x03]\0" |
| 36777 | /* 10528 */ "stumaxlh $\x02, [$\x03]\0" |
| 36778 | /* 10546 */ "stumaxl $\x02, [$\x03]\0" |
| 36779 | /* 10563 */ "stumax $\x02, [$\x03]\0" |
| 36780 | /* 10579 */ "stuminb $\x02, [$\x03]\0" |
| 36781 | /* 10596 */ "stuminh $\x02, [$\x03]\0" |
| 36782 | /* 10613 */ "stuminlb $\x02, [$\x03]\0" |
| 36783 | /* 10631 */ "stuminlh $\x02, [$\x03]\0" |
| 36784 | /* 10649 */ "stuminl $\x02, [$\x03]\0" |
| 36785 | /* 10666 */ "stumin $\x02, [$\x03]\0" |
| 36786 | /* 10682 */ "ldurb $\x01, [$\x02]\0" |
| 36787 | /* 10697 */ "ldur $\x01, [$\x02]\0" |
| 36788 | /* 10711 */ "ldurh $\x01, [$\x02]\0" |
| 36789 | /* 10726 */ "ldursb $\x01, [$\x02]\0" |
| 36790 | /* 10742 */ "ldursh $\x01, [$\x02]\0" |
| 36791 | /* 10758 */ "ldursw $\x01, [$\x02]\0" |
| 36792 | /* 10774 */ "mul $\x01, $\x02, $\x03\0" |
| 36793 | /* 10789 */ "mov $\xFF\x01\x28, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| 36794 | /* 10814 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| 36795 | /* 10839 */ "mov $\xFF\x01\x2B, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| 36796 | /* 10864 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| 36797 | /* 10889 */ "mov $\xFF\x01\x28, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| 36798 | /* 10914 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| 36799 | /* 10939 */ "mov $\xFF\x01\x2B, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| 36800 | /* 10964 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| 36801 | /* 10989 */ "mov $\xFF\x01\x28, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| 36802 | /* 11014 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| 36803 | /* 11039 */ "mov $\xFF\x01\x2B, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| 36804 | /* 11064 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| 36805 | /* 11089 */ "mov $\xFF\x01\x28, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| 36806 | /* 11114 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| 36807 | /* 11139 */ "mov $\xFF\x01\x2B, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| 36808 | /* 11164 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| 36809 | /* 11189 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x28\0" |
| 36810 | /* 11214 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x23\0" |
| 36811 | /* 11239 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x2B\0" |
| 36812 | /* 11264 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x24\0" |
| 36813 | /* 11289 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x28\0" |
| 36814 | /* 11314 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x23\0" |
| 36815 | /* 11339 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x2B\0" |
| 36816 | /* 11364 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x24\0" |
| 36817 | /* 11389 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x28\0" |
| 36818 | /* 11414 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x23\0" |
| 36819 | /* 11439 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x2B\0" |
| 36820 | /* 11464 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x24\0" |
| 36821 | /* 11489 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x28\0" |
| 36822 | /* 11514 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x23\0" |
| 36823 | /* 11539 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x2B\0" |
| 36824 | /* 11564 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x24\0" |
| 36825 | /* 11589 */ "mov $\xFF\x01\x23, $\xFF\x02\x3A[$\x03, $\xFF\x04\x20, vgx2]\0" |
| 36826 | /* 11620 */ "mov $\xFF\x01\x3A[$\x03, $\xFF\x04\x20, vgx2], $\xFF\x05\x23\0" |
| 36827 | /* 11651 */ "mov $\xFF\x01\x23, $\xFF\x02\x3A[$\x03, $\xFF\x04\x20, vgx4]\0" |
| 36828 | /* 11682 */ "mov $\xFF\x01\x3A[$\x03, $\xFF\x04\x20, vgx4], $\xFF\x05\x23\0" |
| 36829 | /* 11713 */ "movt $\x01, $\xFF\x03\x07\0" |
| 36830 | /* 11727 */ "smstart\0" |
| 36831 | /* 11735 */ "smstart sm\0" |
| 36832 | /* 11746 */ "smstart za\0" |
| 36833 | /* 11757 */ "smstop\0" |
| 36834 | /* 11764 */ "smstop sm\0" |
| 36835 | /* 11774 */ "smstop za\0" |
| 36836 | /* 11784 */ "mneg $\x01, $\x02, $\x03\0" |
| 36837 | /* 11800 */ "nop\0" |
| 36838 | /* 11804 */ "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0" |
| 36839 | /* 11827 */ "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0" |
| 36840 | /* 11848 */ "mvn $\x01, $\x03\0" |
| 36841 | /* 11859 */ "mvn $\x01, $\x03$\xFF\x04\x02\0" |
| 36842 | /* 11874 */ "orn $\x01, $\x02, $\x03\0" |
| 36843 | /* 11889 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0" |
| 36844 | /* 11905 */ "mov $\x01, $\x03\0" |
| 36845 | /* 11916 */ "orr $\x01, $\x02, $\x03\0" |
| 36846 | /* 11931 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0" |
| 36847 | /* 11946 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| 36848 | /* 11967 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| 36849 | /* 11988 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| 36850 | /* 12009 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0" |
| 36851 | /* 12024 */ "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0" |
| 36852 | /* 12047 */ "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0" |
| 36853 | /* 12068 */ "pacia1716\0" |
| 36854 | /* 12078 */ "paciasp\0" |
| 36855 | /* 12086 */ "paciaz\0" |
| 36856 | /* 12093 */ "pacib1716\0" |
| 36857 | /* 12103 */ "pacibsp\0" |
| 36858 | /* 12111 */ "pacibz\0" |
| 36859 | /* 12118 */ "pacm\0" |
| 36860 | /* 12123 */ "pmov $\xFF\x01\x06, $\xFF\x02\x07\0" |
| 36861 | /* 12139 */ "pmov $\xFF\x01\x07, $\xFF\x04\x06\0" |
| 36862 | /* 12155 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 36863 | /* 12179 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| 36864 | /* 12201 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 36865 | /* 12225 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 36866 | /* 12249 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| 36867 | /* 12271 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 36868 | /* 12295 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 36869 | /* 12319 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| 36870 | /* 12341 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 36871 | /* 12365 */ "prfm $\xFF\x01\x3D, [$\x02, $\x03]\0" |
| 36872 | /* 12385 */ "prfm $\xFF\x01\x3D, [$\x02]\0" |
| 36873 | /* 12401 */ "prfum $\xFF\x01\x3D, [$\x02]\0" |
| 36874 | /* 12418 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 36875 | /* 12442 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| 36876 | /* 12464 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 36877 | /* 12488 */ "ptrues $\xFF\x01\x06\0" |
| 36878 | /* 12500 */ "ptrues $\xFF\x01\x10\0" |
| 36879 | /* 12512 */ "ptrues $\xFF\x01\x09\0" |
| 36880 | /* 12524 */ "ptrues $\xFF\x01\x0B\0" |
| 36881 | /* 12536 */ "ptrue $\xFF\x01\x06\0" |
| 36882 | /* 12547 */ "ptrue $\xFF\x01\x10\0" |
| 36883 | /* 12558 */ "ptrue $\xFF\x01\x09\0" |
| 36884 | /* 12569 */ "ptrue $\xFF\x01\x0B\0" |
| 36885 | /* 12580 */ "ret\0" |
| 36886 | /* 12584 */ "ngcs $\x01, $\x03\0" |
| 36887 | /* 12596 */ "ngc $\x01, $\x03\0" |
| 36888 | /* 12607 */ "asr $\x01, $\x02, $\x03\0" |
| 36889 | /* 12622 */ "sxtb $\x01, $\x02\0" |
| 36890 | /* 12634 */ "sxth $\x01, $\x02\0" |
| 36891 | /* 12646 */ "sxtw $\x01, $\x02\0" |
| 36892 | /* 12658 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0" |
| 36893 | /* 12681 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0" |
| 36894 | /* 12704 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0" |
| 36895 | /* 12727 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0" |
| 36896 | /* 12750 */ "shuh\0" |
| 36897 | /* 12755 */ "smull $\x01, $\x02, $\x03\0" |
| 36898 | /* 12772 */ "smnegl $\x01, $\x02, $\x03\0" |
| 36899 | /* 12790 */ "sqdecb $\x01\0" |
| 36900 | /* 12800 */ "sqdecb $\x01, $\xFF\x03\x0E\0" |
| 36901 | /* 12816 */ "sqdecb $\x01, $\xFF\x02\x3E\0" |
| 36902 | /* 12832 */ "sqdecb $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 36903 | /* 12854 */ "sqdecd $\x01\0" |
| 36904 | /* 12864 */ "sqdecd $\x01, $\xFF\x03\x0E\0" |
| 36905 | /* 12880 */ "sqdecd $\x01, $\xFF\x02\x3E\0" |
| 36906 | /* 12896 */ "sqdecd $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 36907 | /* 12918 */ "sqdecd $\xFF\x01\x10\0" |
| 36908 | /* 12930 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 36909 | /* 12948 */ "sqdech $\x01\0" |
| 36910 | /* 12958 */ "sqdech $\x01, $\xFF\x03\x0E\0" |
| 36911 | /* 12974 */ "sqdech $\x01, $\xFF\x02\x3E\0" |
| 36912 | /* 12990 */ "sqdech $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 36913 | /* 13012 */ "sqdech $\xFF\x01\x09\0" |
| 36914 | /* 13024 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 36915 | /* 13042 */ "sqdecw $\x01\0" |
| 36916 | /* 13052 */ "sqdecw $\x01, $\xFF\x03\x0E\0" |
| 36917 | /* 13068 */ "sqdecw $\x01, $\xFF\x02\x3E\0" |
| 36918 | /* 13084 */ "sqdecw $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 36919 | /* 13106 */ "sqdecw $\xFF\x01\x0B\0" |
| 36920 | /* 13118 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 36921 | /* 13136 */ "sqincb $\x01\0" |
| 36922 | /* 13146 */ "sqincb $\x01, $\xFF\x03\x0E\0" |
| 36923 | /* 13162 */ "sqincb $\x01, $\xFF\x02\x3E\0" |
| 36924 | /* 13178 */ "sqincb $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 36925 | /* 13200 */ "sqincd $\x01\0" |
| 36926 | /* 13210 */ "sqincd $\x01, $\xFF\x03\x0E\0" |
| 36927 | /* 13226 */ "sqincd $\x01, $\xFF\x02\x3E\0" |
| 36928 | /* 13242 */ "sqincd $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 36929 | /* 13264 */ "sqincd $\xFF\x01\x10\0" |
| 36930 | /* 13276 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 36931 | /* 13294 */ "sqinch $\x01\0" |
| 36932 | /* 13304 */ "sqinch $\x01, $\xFF\x03\x0E\0" |
| 36933 | /* 13320 */ "sqinch $\x01, $\xFF\x02\x3E\0" |
| 36934 | /* 13336 */ "sqinch $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 36935 | /* 13358 */ "sqinch $\xFF\x01\x09\0" |
| 36936 | /* 13370 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 36937 | /* 13388 */ "sqincw $\x01\0" |
| 36938 | /* 13398 */ "sqincw $\x01, $\xFF\x03\x0E\0" |
| 36939 | /* 13414 */ "sqincw $\x01, $\xFF\x02\x3E\0" |
| 36940 | /* 13430 */ "sqincw $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| 36941 | /* 13452 */ "sqincw $\xFF\x01\x0B\0" |
| 36942 | /* 13464 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 36943 | /* 13482 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 36944 | /* 13506 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 36945 | /* 13530 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 36946 | /* 13554 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 36947 | /* 13578 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 36948 | /* 13602 */ "st1q $\xFF\x01\x25, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 36949 | /* 13626 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 36950 | /* 13650 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 36951 | /* 13674 */ "st1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| 36952 | /* 13696 */ "st1b $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0" |
| 36953 | /* 13718 */ "st1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| 36954 | /* 13740 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 36955 | /* 13762 */ "st1b $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 36956 | /* 13784 */ "st1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 36957 | /* 13806 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 36958 | /* 13828 */ "st1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| 36959 | /* 13850 */ "st1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| 36960 | /* 13872 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 36961 | /* 13894 */ "st1d $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 36962 | /* 13916 */ "st1 $\xFF\x02\x2C, [$\x01], #64\0" |
| 36963 | /* 13936 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0" |
| 36964 | /* 13956 */ "st1 $\xFF\x02\x2E, [$\x01], #64\0" |
| 36965 | /* 13976 */ "st1 $\xFF\x02\x2F, [$\x01], #32\0" |
| 36966 | /* 13996 */ "st1 $\xFF\x02\x30, [$\x01], #32\0" |
| 36967 | /* 14016 */ "st1 $\xFF\x02\x31, [$\x01], #64\0" |
| 36968 | /* 14036 */ "st1 $\xFF\x02\x32, [$\x01], #32\0" |
| 36969 | /* 14056 */ "st1 $\xFF\x02\x33, [$\x01], #64\0" |
| 36970 | /* 14076 */ "st1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| 36971 | /* 14098 */ "st1h $\xFF\x01\x34, $\xFF\x02\x29, [$\x03]\0" |
| 36972 | /* 14120 */ "st1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| 36973 | /* 14142 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 36974 | /* 14164 */ "st1h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 36975 | /* 14186 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 36976 | /* 14208 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0" |
| 36977 | /* 14228 */ "st1 $\xFF\x02\x2D, [$\x01], #8\0" |
| 36978 | /* 14247 */ "st1 $\xFF\x02\x2E, [$\x01], #16\0" |
| 36979 | /* 14267 */ "st1 $\xFF\x02\x2F, [$\x01], #8\0" |
| 36980 | /* 14286 */ "st1 $\xFF\x02\x30, [$\x01], #8\0" |
| 36981 | /* 14305 */ "st1 $\xFF\x02\x31, [$\x01], #16\0" |
| 36982 | /* 14325 */ "st1 $\xFF\x02\x32, [$\x01], #8\0" |
| 36983 | /* 14344 */ "st1 $\xFF\x02\x33, [$\x01], #16\0" |
| 36984 | /* 14364 */ "st1 $\xFF\x02\x2C, [$\x01], #48\0" |
| 36985 | /* 14384 */ "st1 $\xFF\x02\x2D, [$\x01], #24\0" |
| 36986 | /* 14404 */ "st1 $\xFF\x02\x2E, [$\x01], #48\0" |
| 36987 | /* 14424 */ "st1 $\xFF\x02\x2F, [$\x01], #24\0" |
| 36988 | /* 14444 */ "st1 $\xFF\x02\x30, [$\x01], #24\0" |
| 36989 | /* 14464 */ "st1 $\xFF\x02\x31, [$\x01], #48\0" |
| 36990 | /* 14484 */ "st1 $\xFF\x02\x32, [$\x01], #24\0" |
| 36991 | /* 14504 */ "st1 $\xFF\x02\x33, [$\x01], #48\0" |
| 36992 | /* 14524 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0" |
| 36993 | /* 14544 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0" |
| 36994 | /* 14564 */ "st1 $\xFF\x02\x2E, [$\x01], #32\0" |
| 36995 | /* 14584 */ "st1 $\xFF\x02\x2F, [$\x01], #16\0" |
| 36996 | /* 14604 */ "st1 $\xFF\x02\x30, [$\x01], #16\0" |
| 36997 | /* 14624 */ "st1 $\xFF\x02\x31, [$\x01], #32\0" |
| 36998 | /* 14644 */ "st1 $\xFF\x02\x32, [$\x01], #16\0" |
| 36999 | /* 14664 */ "st1 $\xFF\x02\x33, [$\x01], #32\0" |
| 37000 | /* 14684 */ "st1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| 37001 | /* 14706 */ "st1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| 37002 | /* 14728 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 37003 | /* 14750 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 37004 | /* 14772 */ "st1w $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 37005 | /* 14794 */ "st1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37006 | /* 14828 */ "st1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37007 | /* 14862 */ "st1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37008 | /* 14896 */ "st1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37009 | /* 14930 */ "st1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37010 | /* 14964 */ "st1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37011 | /* 14998 */ "st1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37012 | /* 15032 */ "st1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37013 | /* 15066 */ "st1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37014 | /* 15100 */ "st1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 37015 | /* 15134 */ "st1 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #2\0" |
| 37016 | /* 15157 */ "st1 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #4\0" |
| 37017 | /* 15180 */ "st1 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #8\0" |
| 37018 | /* 15203 */ "st1 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #1\0" |
| 37019 | /* 15226 */ "st2b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 37020 | /* 15248 */ "st2d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 37021 | /* 15270 */ "st2g $\x01, [$\x02]\0" |
| 37022 | /* 15284 */ "st2h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 37023 | /* 15306 */ "st2q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 37024 | /* 15328 */ "st2 $\xFF\x02\x2C, [$\x01], #32\0" |
| 37025 | /* 15348 */ "st2 $\xFF\x02\x2E, [$\x01], #32\0" |
| 37026 | /* 15368 */ "st2 $\xFF\x02\x2F, [$\x01], #16\0" |
| 37027 | /* 15388 */ "st2 $\xFF\x02\x30, [$\x01], #16\0" |
| 37028 | /* 15408 */ "st2 $\xFF\x02\x31, [$\x01], #32\0" |
| 37029 | /* 15428 */ "st2 $\xFF\x02\x32, [$\x01], #16\0" |
| 37030 | /* 15448 */ "st2 $\xFF\x02\x33, [$\x01], #32\0" |
| 37031 | /* 15468 */ "st2w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 37032 | /* 15490 */ "st2 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #4\0" |
| 37033 | /* 15513 */ "st2 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #8\0" |
| 37034 | /* 15536 */ "st2 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #16\0" |
| 37035 | /* 15560 */ "st2 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #2\0" |
| 37036 | /* 15583 */ "st3b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 37037 | /* 15605 */ "st3d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 37038 | /* 15627 */ "st3h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 37039 | /* 15649 */ "st3q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 37040 | /* 15671 */ "st3 $\xFF\x02\x2C, [$\x01], #48\0" |
| 37041 | /* 15691 */ "st3 $\xFF\x02\x2E, [$\x01], #48\0" |
| 37042 | /* 15711 */ "st3 $\xFF\x02\x2F, [$\x01], #24\0" |
| 37043 | /* 15731 */ "st3 $\xFF\x02\x30, [$\x01], #24\0" |
| 37044 | /* 15751 */ "st3 $\xFF\x02\x31, [$\x01], #48\0" |
| 37045 | /* 15771 */ "st3 $\xFF\x02\x32, [$\x01], #24\0" |
| 37046 | /* 15791 */ "st3 $\xFF\x02\x33, [$\x01], #48\0" |
| 37047 | /* 15811 */ "st3w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 37048 | /* 15833 */ "st3 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #6\0" |
| 37049 | /* 15856 */ "st3 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #12\0" |
| 37050 | /* 15880 */ "st3 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #24\0" |
| 37051 | /* 15904 */ "st3 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #3\0" |
| 37052 | /* 15927 */ "st4b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 37053 | /* 15949 */ "st4d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 37054 | /* 15971 */ "st4 $\xFF\x02\x2C, [$\x01], #64\0" |
| 37055 | /* 15991 */ "st4 $\xFF\x02\x2E, [$\x01], #64\0" |
| 37056 | /* 16011 */ "st4 $\xFF\x02\x2F, [$\x01], #32\0" |
| 37057 | /* 16031 */ "st4 $\xFF\x02\x30, [$\x01], #32\0" |
| 37058 | /* 16051 */ "st4 $\xFF\x02\x31, [$\x01], #64\0" |
| 37059 | /* 16071 */ "st4 $\xFF\x02\x32, [$\x01], #32\0" |
| 37060 | /* 16091 */ "st4 $\xFF\x02\x33, [$\x01], #64\0" |
| 37061 | /* 16111 */ "st4h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 37062 | /* 16133 */ "st4q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 37063 | /* 16155 */ "st4w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 37064 | /* 16177 */ "st4 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #8\0" |
| 37065 | /* 16200 */ "st4 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #16\0" |
| 37066 | /* 16224 */ "st4 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #32\0" |
| 37067 | /* 16248 */ "st4 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #4\0" |
| 37068 | /* 16271 */ "stgp $\x01, $\x02, [$\x03]\0" |
| 37069 | /* 16289 */ "stg $\x01, [$\x02]\0" |
| 37070 | /* 16302 */ "stlp $\x01, $\x02, [$\x03]\0" |
| 37071 | /* 16320 */ "stlurb $\x01, [$\x02]\0" |
| 37072 | /* 16336 */ "stlurh $\x01, [$\x02]\0" |
| 37073 | /* 16352 */ "stlur $\x01, [$\x02]\0" |
| 37074 | /* 16367 */ "stnp $\x01, $\x02, [$\x03]\0" |
| 37075 | /* 16385 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| 37076 | /* 16409 */ "stnt1b $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0" |
| 37077 | /* 16433 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| 37078 | /* 16457 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| 37079 | /* 16481 */ "stnt1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 37080 | /* 16507 */ "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 37081 | /* 16533 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| 37082 | /* 16557 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| 37083 | /* 16581 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 37084 | /* 16605 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 37085 | /* 16631 */ "stnt1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| 37086 | /* 16655 */ "stnt1h $\xFF\x01\x34, $\xFF\x02\x29, [$\x03]\0" |
| 37087 | /* 16679 */ "stnt1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| 37088 | /* 16703 */ "stnt1h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0" |
| 37089 | /* 16727 */ "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 37090 | /* 16753 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 37091 | /* 16779 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| 37092 | /* 16803 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| 37093 | /* 16827 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 37094 | /* 16851 */ "stnt1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 37095 | /* 16877 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 37096 | /* 16903 */ "stp $\x01, $\x02, [$\x03]\0" |
| 37097 | /* 16920 */ "strb $\x01, [$\x02, $\x03]\0" |
| 37098 | /* 16938 */ "strb $\x01, [$\x02]\0" |
| 37099 | /* 16952 */ "str $\x01, [$\x02, $\x03]\0" |
| 37100 | /* 16969 */ "str $\x01, [$\x02]\0" |
| 37101 | /* 16982 */ "strh $\x01, [$\x02, $\x03]\0" |
| 37102 | /* 17000 */ "strh $\x01, [$\x02]\0" |
| 37103 | /* 17014 */ "str $\xFF\x01\x07, [$\x02]\0" |
| 37104 | /* 17029 */ "str $\xFF\x01\x37[$\x02, $\xFF\x03\x20], [$\x04]\0" |
| 37105 | /* 17054 */ "sttnp $\x01, $\x02, [$\x03]\0" |
| 37106 | /* 17073 */ "sttp $\x01, $\x02, [$\x03]\0" |
| 37107 | /* 17091 */ "sttrb $\x01, [$\x02]\0" |
| 37108 | /* 17106 */ "sttrh $\x01, [$\x02]\0" |
| 37109 | /* 17121 */ "sttr $\x01, [$\x02]\0" |
| 37110 | /* 17135 */ "sturb $\x01, [$\x02]\0" |
| 37111 | /* 17150 */ "stur $\x01, [$\x02]\0" |
| 37112 | /* 17164 */ "sturh $\x01, [$\x02]\0" |
| 37113 | /* 17179 */ "stz2g $\x01, [$\x02]\0" |
| 37114 | /* 17194 */ "stzg $\x01, [$\x02]\0" |
| 37115 | /* 17208 */ "subpt $\x01, $\x02, $\x03\0" |
| 37116 | /* 17225 */ "cmp $\x02, $\xFF\x03\x01\0" |
| 37117 | /* 17238 */ "cmp $\x02, $\x03\0" |
| 37118 | /* 17249 */ "cmp $\x02, $\x03$\xFF\x04\x02\0" |
| 37119 | /* 17264 */ "negs $\x01, $\x03\0" |
| 37120 | /* 17276 */ "negs $\x01, $\x03$\xFF\x04\x02\0" |
| 37121 | /* 17292 */ "subs $\x01, $\x02, $\x03\0" |
| 37122 | /* 17308 */ "cmp $\x02, $\x03$\xFF\x04\x03\0" |
| 37123 | /* 17323 */ "neg $\x01, $\x03\0" |
| 37124 | /* 17334 */ "neg $\x01, $\x03$\xFF\x04\x02\0" |
| 37125 | /* 17349 */ "sub $\x01, $\x02, $\x03\0" |
| 37126 | /* 17364 */ "sysp $\x01, $\xFF\x02\x3F, $\xFF\x03\x3F, $\x04\0" |
| 37127 | /* 17388 */ "sys $\x01, $\xFF\x02\x3F, $\xFF\x03\x3F, $\x04\0" |
| 37128 | /* 17411 */ "tchangeb $\x01, $\xFF\x02\x0D\0" |
| 37129 | /* 17429 */ "tchangeb $\x01, $\x02\0" |
| 37130 | /* 17445 */ "tchangef $\x01, $\xFF\x02\x0D\0" |
| 37131 | /* 17463 */ "tchangef $\x01, $\x02\0" |
| 37132 | /* 17479 */ "tenter $\xFF\x01\x0D\0" |
| 37133 | /* 17491 */ "texit\0" |
| 37134 | /* 17497 */ "lsr $\x01, $\x02, $\x03\0" |
| 37135 | /* 17512 */ "uxtb $\x01, $\x02\0" |
| 37136 | /* 17524 */ "uxth $\x01, $\x02\0" |
| 37137 | /* 17536 */ "uxtw $\x01, $\x02\0" |
| 37138 | /* 17548 */ "umull $\x01, $\x02, $\x03\0" |
| 37139 | /* 17565 */ "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19\0" |
| 37140 | /* 17584 */ "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19\0" |
| 37141 | /* 17603 */ "umnegl $\x01, $\x02, $\x03\0" |
| 37142 | /* 17621 */ "uqdecb $\x01\0" |
| 37143 | /* 17631 */ "uqdecb $\x01, $\xFF\x03\x0E\0" |
| 37144 | /* 17647 */ "uqdecd $\x01\0" |
| 37145 | /* 17657 */ "uqdecd $\x01, $\xFF\x03\x0E\0" |
| 37146 | /* 17673 */ "uqdecd $\xFF\x01\x10\0" |
| 37147 | /* 17685 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 37148 | /* 17703 */ "uqdech $\x01\0" |
| 37149 | /* 17713 */ "uqdech $\x01, $\xFF\x03\x0E\0" |
| 37150 | /* 17729 */ "uqdech $\xFF\x01\x09\0" |
| 37151 | /* 17741 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 37152 | /* 17759 */ "uqdecw $\x01\0" |
| 37153 | /* 17769 */ "uqdecw $\x01, $\xFF\x03\x0E\0" |
| 37154 | /* 17785 */ "uqdecw $\xFF\x01\x0B\0" |
| 37155 | /* 17797 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 37156 | /* 17815 */ "uqincb $\x01\0" |
| 37157 | /* 17825 */ "uqincb $\x01, $\xFF\x03\x0E\0" |
| 37158 | /* 17841 */ "uqincd $\x01\0" |
| 37159 | /* 17851 */ "uqincd $\x01, $\xFF\x03\x0E\0" |
| 37160 | /* 17867 */ "uqincd $\xFF\x01\x10\0" |
| 37161 | /* 17879 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 37162 | /* 17897 */ "uqinch $\x01\0" |
| 37163 | /* 17907 */ "uqinch $\x01, $\xFF\x03\x0E\0" |
| 37164 | /* 17923 */ "uqinch $\xFF\x01\x09\0" |
| 37165 | /* 17935 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 37166 | /* 17953 */ "uqincw $\x01\0" |
| 37167 | /* 17963 */ "uqincw $\x01, $\xFF\x03\x0E\0" |
| 37168 | /* 17979 */ "uqincw $\xFF\x01\x0B\0" |
| 37169 | /* 17991 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 37170 | /* 18009 */ "xpaclri\0" |
| 37171 | /* 18017 */ "zero {za}\0" |
| 37172 | /* 18027 */ "zero {za0.h}\0" |
| 37173 | /* 18040 */ "zero {za1.h}\0" |
| 37174 | /* 18053 */ "zero {za0.s}\0" |
| 37175 | /* 18066 */ "zero {za1.s}\0" |
| 37176 | /* 18079 */ "zero {za2.s}\0" |
| 37177 | /* 18092 */ "zero {za3.s}\0" |
| 37178 | /* 18105 */ "zero {za0.s,za1.s}\0" |
| 37179 | /* 18124 */ "zero {za0.s,za3.s}\0" |
| 37180 | /* 18143 */ "zero {za1.s,za2.s}\0" |
| 37181 | /* 18162 */ "zero {za2.s,za3.s}\0" |
| 37182 | /* 18181 */ "zero {za0.s,za1.s,za2.s}\0" |
| 37183 | /* 18206 */ "zero {za0.s,za1.s,za3.s}\0" |
| 37184 | /* 18231 */ "zero {za0.s,za2.s,za3.s}\0" |
| 37185 | /* 18256 */ "zero {za1.s,za2.s,za3.s}\0" |
| 37186 | ; |
| 37187 | |
| 37188 | #ifndef NDEBUG |
| 37189 | static struct SortCheck { |
| 37190 | SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| 37191 | assert(std::is_sorted( |
| 37192 | OpToPatterns.begin(), OpToPatterns.end(), |
| 37193 | [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| 37194 | return L.Opcode < R.Opcode; |
| 37195 | }) && |
| 37196 | "tablegen failed to sort opcode patterns"); |
| 37197 | } |
| 37198 | } sortCheckVar(OpToPatterns); |
| 37199 | #endif |
| 37200 | |
| 37201 | AliasMatchingData M { |
| 37202 | .OpToPatterns: ArrayRef(OpToPatterns), |
| 37203 | .Patterns: ArrayRef(Patterns), |
| 37204 | .PatternConds: ArrayRef(Conds), |
| 37205 | .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)), |
| 37206 | .ValidateMCOperand: &AArch64InstPrinterValidateMCOperand, |
| 37207 | }; |
| 37208 | const char *AsmString = matchAliasPatterns(MI, STI: &STI, M); |
| 37209 | if (!AsmString) return false; |
| 37210 | |
| 37211 | unsigned I = 0; |
| 37212 | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| 37213 | AsmString[I] != '$' && AsmString[I] != '\0') |
| 37214 | ++I; |
| 37215 | OS << '\t' << StringRef(AsmString, I); |
| 37216 | if (AsmString[I] != '\0') { |
| 37217 | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| 37218 | OS << '\t'; |
| 37219 | ++I; |
| 37220 | } |
| 37221 | do { |
| 37222 | if (AsmString[I] == '$') { |
| 37223 | ++I; |
| 37224 | if (AsmString[I] == (char)0xff) { |
| 37225 | ++I; |
| 37226 | int OpIdx = AsmString[I++] - 1; |
| 37227 | int PrintMethodIdx = AsmString[I++] - 1; |
| 37228 | printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS); |
| 37229 | } else |
| 37230 | printOperand(MI, OpNo: unsigned(AsmString[I++]) - 1, STI, O&: OS); |
| 37231 | } else { |
| 37232 | OS << AsmString[I++]; |
| 37233 | } |
| 37234 | } while (AsmString[I] != '\0'); |
| 37235 | } |
| 37236 | |
| 37237 | return true; |
| 37238 | } |
| 37239 | |
| 37240 | void AArch64InstPrinter::printCustomAliasOperand( |
| 37241 | const MCInst *MI, uint64_t Address, unsigned OpIdx, |
| 37242 | unsigned PrintMethodIdx, |
| 37243 | const MCSubtargetInfo &STI, |
| 37244 | raw_ostream &OS) { |
| 37245 | switch (PrintMethodIdx) { |
| 37246 | default: |
| 37247 | llvm_unreachable("Unknown PrintMethod kind"); |
| 37248 | break; |
| 37249 | case 0: |
| 37250 | printAddSubImm(MI, OpNum: OpIdx, STI, O&: OS); |
| 37251 | break; |
| 37252 | case 1: |
| 37253 | printShifter(MI, OpNum: OpIdx, STI, O&: OS); |
| 37254 | break; |
| 37255 | case 2: |
| 37256 | printArithExtend(MI, OpNum: OpIdx, STI, O&: OS); |
| 37257 | break; |
| 37258 | case 3: |
| 37259 | printLogicalImm<int32_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37260 | break; |
| 37261 | case 4: |
| 37262 | printLogicalImm<int64_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37263 | break; |
| 37264 | case 5: |
| 37265 | printSVERegOp<'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37266 | break; |
| 37267 | case 6: |
| 37268 | printSVERegOp<>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37269 | break; |
| 37270 | case 7: |
| 37271 | printLogicalImm<int8_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37272 | break; |
| 37273 | case 8: |
| 37274 | printSVERegOp<'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37275 | break; |
| 37276 | case 9: |
| 37277 | printLogicalImm<int16_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37278 | break; |
| 37279 | case 10: |
| 37280 | printSVERegOp<'s'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37281 | break; |
| 37282 | case 11: |
| 37283 | printVRegOperand(MI, OpNo: OpIdx, STI, O&: OS); |
| 37284 | break; |
| 37285 | case 12: |
| 37286 | printImm(MI, OpNo: OpIdx, STI, O&: OS); |
| 37287 | break; |
| 37288 | case 13: |
| 37289 | printSVEPattern(MI, OpNum: OpIdx, STI, O&: OS); |
| 37290 | break; |
| 37291 | case 14: |
| 37292 | printImm8OptLsl<int8_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37293 | break; |
| 37294 | case 15: |
| 37295 | printSVERegOp<'d'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37296 | break; |
| 37297 | case 16: |
| 37298 | printImm8OptLsl<int64_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37299 | break; |
| 37300 | case 17: |
| 37301 | printImm8OptLsl<int16_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37302 | break; |
| 37303 | case 18: |
| 37304 | printImm8OptLsl<int32_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37305 | break; |
| 37306 | case 19: |
| 37307 | printInverseCondCode(MI, OpNum: OpIdx, STI, O&: OS); |
| 37308 | break; |
| 37309 | case 20: |
| 37310 | printSVELogicalImm<int16_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37311 | break; |
| 37312 | case 21: |
| 37313 | printSVELogicalImm<int32_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37314 | break; |
| 37315 | case 22: |
| 37316 | printSVELogicalImm<int64_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37317 | break; |
| 37318 | case 23: |
| 37319 | printZPRasFPR<8>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37320 | break; |
| 37321 | case 24: |
| 37322 | printVectorIndex(MI, OpNum: OpIdx, STI, O&: OS); |
| 37323 | break; |
| 37324 | case 25: |
| 37325 | printZPRasFPR<64>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37326 | break; |
| 37327 | case 26: |
| 37328 | printZPRasFPR<16>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37329 | break; |
| 37330 | case 27: |
| 37331 | printSVERegOp<'q'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37332 | break; |
| 37333 | case 28: |
| 37334 | printZPRasFPR<128>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37335 | break; |
| 37336 | case 29: |
| 37337 | printZPRasFPR<32>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37338 | break; |
| 37339 | case 30: |
| 37340 | printMatrixTileVector<0>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37341 | break; |
| 37342 | case 31: |
| 37343 | printMatrixIndex(MI, OpNum: OpIdx, STI, O&: OS); |
| 37344 | break; |
| 37345 | case 32: |
| 37346 | printMatrixTileVector<1>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37347 | break; |
| 37348 | case 33: |
| 37349 | printFPImmOperand(MI, OpNum: OpIdx, STI, O&: OS); |
| 37350 | break; |
| 37351 | case 34: |
| 37352 | printTypedVectorList<0,'d'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37353 | break; |
| 37354 | case 35: |
| 37355 | printTypedVectorList<0,'s'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37356 | break; |
| 37357 | case 36: |
| 37358 | printTypedVectorList<0,'q'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37359 | break; |
| 37360 | case 37: |
| 37361 | printBTIHintOp(MI, OpNum: OpIdx, STI, O&: OS); |
| 37362 | break; |
| 37363 | case 38: |
| 37364 | printPSBHintOp(MI, OpNum: OpIdx, STI, O&: OS); |
| 37365 | break; |
| 37366 | case 39: |
| 37367 | printTypedVectorList<0,'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37368 | break; |
| 37369 | case 40: |
| 37370 | printPredicateAsCounter<0>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37371 | break; |
| 37372 | case 41: |
| 37373 | printTypedVectorList<0, 'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37374 | break; |
| 37375 | case 42: |
| 37376 | printTypedVectorList<0,'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37377 | break; |
| 37378 | case 43: |
| 37379 | printTypedVectorList<16, 'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37380 | break; |
| 37381 | case 44: |
| 37382 | printTypedVectorList<1, 'd'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37383 | break; |
| 37384 | case 45: |
| 37385 | printTypedVectorList<2, 'd'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37386 | break; |
| 37387 | case 46: |
| 37388 | printTypedVectorList<2, 's'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37389 | break; |
| 37390 | case 47: |
| 37391 | printTypedVectorList<4, 'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37392 | break; |
| 37393 | case 48: |
| 37394 | printTypedVectorList<4, 's'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37395 | break; |
| 37396 | case 49: |
| 37397 | printTypedVectorList<8, 'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37398 | break; |
| 37399 | case 50: |
| 37400 | printTypedVectorList<8, 'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37401 | break; |
| 37402 | case 51: |
| 37403 | printTypedVectorList<0, 'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37404 | break; |
| 37405 | case 52: |
| 37406 | printTypedVectorList<0, 's'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37407 | break; |
| 37408 | case 53: |
| 37409 | printTypedVectorList<0, 'd'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37410 | break; |
| 37411 | case 54: |
| 37412 | printMatrix<0>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37413 | break; |
| 37414 | case 55: |
| 37415 | printImmRangeScale<2, 1>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37416 | break; |
| 37417 | case 56: |
| 37418 | printImmRangeScale<4, 3>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37419 | break; |
| 37420 | case 57: |
| 37421 | printMatrix<64>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37422 | break; |
| 37423 | case 58: |
| 37424 | printImmHex(MI, OpNo: OpIdx, STI, O&: OS); |
| 37425 | break; |
| 37426 | case 59: |
| 37427 | printPrefetchOp<true>(MI, OpNum: OpIdx, STI, O&: OS); |
| 37428 | break; |
| 37429 | case 60: |
| 37430 | printPrefetchOp(MI, OpNum: OpIdx, STI, O&: OS); |
| 37431 | break; |
| 37432 | case 61: |
| 37433 | printGPR64as32(MI, OpNum: OpIdx, STI, O&: OS); |
| 37434 | break; |
| 37435 | case 62: |
| 37436 | printSysCROperand(MI, OpNo: OpIdx, STI, O&: OS); |
| 37437 | break; |
| 37438 | } |
| 37439 | } |
| 37440 | |
| 37441 | static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp, |
| 37442 | const MCSubtargetInfo &STI, |
| 37443 | unsigned PredicateIndex) { |
| 37444 | switch (PredicateIndex) { |
| 37445 | default: |
| 37446 | llvm_unreachable("Unknown MCOperandPredicate kind"); |
| 37447 | break; |
| 37448 | case 1: { |
| 37449 | |
| 37450 | if (!MCOp.isImm()) |
| 37451 | return false; |
| 37452 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 37453 | return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Imm: Val); |
| 37454 | |
| 37455 | } |
| 37456 | case 2: { |
| 37457 | |
| 37458 | if (!MCOp.isImm()) |
| 37459 | return false; |
| 37460 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 37461 | return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Imm: Val); |
| 37462 | |
| 37463 | } |
| 37464 | case 3: { |
| 37465 | |
| 37466 | if (!MCOp.isImm()) |
| 37467 | return false; |
| 37468 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 37469 | return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Imm: Val); |
| 37470 | |
| 37471 | } |
| 37472 | case 4: { |
| 37473 | |
| 37474 | return MCOp.isImm() && |
| 37475 | MCOp.getImm() != AArch64CC::AL && |
| 37476 | MCOp.getImm() != AArch64CC::NV; |
| 37477 | |
| 37478 | } |
| 37479 | case 5: { |
| 37480 | |
| 37481 | if (!MCOp.isImm()) |
| 37482 | return false; |
| 37483 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 37484 | return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Imm: Val) && |
| 37485 | AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Imm: Val); |
| 37486 | |
| 37487 | } |
| 37488 | case 6: { |
| 37489 | |
| 37490 | if (!MCOp.isImm()) |
| 37491 | return false; |
| 37492 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 37493 | return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Imm: Val) && |
| 37494 | AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Imm: Val); |
| 37495 | |
| 37496 | } |
| 37497 | case 7: { |
| 37498 | |
| 37499 | if (!MCOp.isImm()) |
| 37500 | return false; |
| 37501 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 37502 | return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Imm: Val) && |
| 37503 | AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Imm: Val); |
| 37504 | |
| 37505 | } |
| 37506 | case 8: { |
| 37507 | |
| 37508 | // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| 37509 | if (!MCOp.isImm()) |
| 37510 | return false; |
| 37511 | return AArch64BTIHint::lookupBTIByEncoding(Encoding: MCOp.getImm() ^ 32) != nullptr; |
| 37512 | |
| 37513 | } |
| 37514 | case 9: { |
| 37515 | |
| 37516 | // Check, if operand is valid, to fix exhaustive aliasing in disassembly. |
| 37517 | // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| 37518 | if (!MCOp.isImm()) |
| 37519 | return false; |
| 37520 | return AArch64PSBHint::lookupPSBByEncoding(Encoding: MCOp.getImm()) != nullptr; |
| 37521 | |
| 37522 | } |
| 37523 | } |
| 37524 | } |
| 37525 | |
| 37526 | #endif // PRINT_ALIAS_INSTR |
| 37527 |
Generated while processing llvm_projects/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
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