| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Assembly Writer Source Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* From: AArch64.td *| |
| 7 | |* *| |
| 8 | \*===----------------------------------------------------------------------===*/ |
| 9 | |
| 10 | /// getMnemonic - This method is automatically generated by tablegen |
| 11 | /// from the instruction set description. |
| 12 | std::pair<const char *, uint64_t> |
| 13 | AArch64InstPrinter::getMnemonic(const MCInst &MI) const { |
| 14 | |
| 15 | #ifdef __GNUC__ |
| 16 | #pragma GCC diagnostic push |
| 17 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 18 | #endif |
| 19 | static const char AsmStrs[] = { |
| 20 | /* 0 */ "sha1su0\t\000" |
| 21 | /* 9 */ "sha512su0\t\000" |
| 22 | /* 20 */ "sha256su0\t\000" |
| 23 | /* 31 */ "stl64bv0\t\000" |
| 24 | /* 41 */ "st64bv0\t\000" |
| 25 | /* 50 */ "ld1\t\000" |
| 26 | /* 55 */ "stl1\t\000" |
| 27 | /* 61 */ "trn1\t\000" |
| 28 | /* 67 */ "ldap1\t\000" |
| 29 | /* 74 */ "zip1\t\000" |
| 30 | /* 80 */ "uzp1\t\000" |
| 31 | /* 86 */ "zipq1\t\000" |
| 32 | /* 93 */ "uzpq1\t\000" |
| 33 | /* 100 */ "dcps1\t\000" |
| 34 | /* 107 */ "sm3ss1\t\000" |
| 35 | /* 115 */ "gcsss1\t\000" |
| 36 | /* 123 */ "st1\t\000" |
| 37 | /* 128 */ "sha1su1\t\000" |
| 38 | /* 137 */ "sha512su1\t\000" |
| 39 | /* 148 */ "sha256su1\t\000" |
| 40 | /* 159 */ "sm3partw1\t\000" |
| 41 | /* 170 */ "rax1\t\000" |
| 42 | /* 176 */ "rev32\t\000" |
| 43 | /* 183 */ "ld2\t\000" |
| 44 | /* 188 */ "sha512h2\t\000" |
| 45 | /* 198 */ "sha256h2\t\000" |
| 46 | /* 208 */ "luti2\t\000" |
| 47 | /* 215 */ "sabal2\t\000" |
| 48 | /* 223 */ "uabal2\t\000" |
| 49 | /* 231 */ "sqdmlal2\t\000" |
| 50 | /* 241 */ "fmlal2\t\000" |
| 51 | /* 249 */ "smlal2\t\000" |
| 52 | /* 257 */ "umlal2\t\000" |
| 53 | /* 265 */ "ssubl2\t\000" |
| 54 | /* 273 */ "usubl2\t\000" |
| 55 | /* 281 */ "sabdl2\t\000" |
| 56 | /* 289 */ "uabdl2\t\000" |
| 57 | /* 297 */ "saddl2\t\000" |
| 58 | /* 305 */ "uaddl2\t\000" |
| 59 | /* 313 */ "sshll2\t\000" |
| 60 | /* 321 */ "ushll2\t\000" |
| 61 | /* 329 */ "sqdmull2\t\000" |
| 62 | /* 339 */ "pmull2\t\000" |
| 63 | /* 347 */ "smull2\t\000" |
| 64 | /* 355 */ "umull2\t\000" |
| 65 | /* 363 */ "sqdmlsl2\t\000" |
| 66 | /* 373 */ "fmlsl2\t\000" |
| 67 | /* 381 */ "smlsl2\t\000" |
| 68 | /* 389 */ "umlsl2\t\000" |
| 69 | /* 397 */ "bf1cvtl2\t\000" |
| 70 | /* 407 */ "bf2cvtl2\t\000" |
| 71 | /* 417 */ "fcvtl2\t\000" |
| 72 | /* 425 */ "rsubhn2\t\000" |
| 73 | /* 434 */ "raddhn2\t\000" |
| 74 | /* 443 */ "sqshrn2\t\000" |
| 75 | /* 452 */ "uqshrn2\t\000" |
| 76 | /* 461 */ "sqrshrn2\t\000" |
| 77 | /* 471 */ "uqrshrn2\t\000" |
| 78 | /* 481 */ "trn2\t\000" |
| 79 | /* 487 */ "bfcvtn2\t\000" |
| 80 | /* 496 */ "sqxtn2\t\000" |
| 81 | /* 504 */ "uqxtn2\t\000" |
| 82 | /* 512 */ "sqshrun2\t\000" |
| 83 | /* 522 */ "sqrshrun2\t\000" |
| 84 | /* 533 */ "sqxtun2\t\000" |
| 85 | /* 542 */ "fcvtxn2\t\000" |
| 86 | /* 551 */ "zip2\t\000" |
| 87 | /* 557 */ "uzp2\t\000" |
| 88 | /* 563 */ "zipq2\t\000" |
| 89 | /* 570 */ "uzpq2\t\000" |
| 90 | /* 577 */ "dcps2\t\000" |
| 91 | /* 584 */ "gcsss2\t\000" |
| 92 | /* 592 */ "st2\t\000" |
| 93 | /* 597 */ "ssubw2\t\000" |
| 94 | /* 605 */ "usubw2\t\000" |
| 95 | /* 613 */ "saddw2\t\000" |
| 96 | /* 621 */ "uaddw2\t\000" |
| 97 | /* 629 */ "sm3partw2\t\000" |
| 98 | /* 640 */ "ld3\t\000" |
| 99 | /* 645 */ "eor3\t\000" |
| 100 | /* 651 */ "dcps3\t\000" |
| 101 | /* 658 */ "st3\t\000" |
| 102 | /* 663 */ "rev64\t\000" |
| 103 | /* 670 */ "ld4\t\000" |
| 104 | /* 675 */ "luti4\t\000" |
| 105 | /* 682 */ "st4\t\000" |
| 106 | /* 687 */ "setf16\t\000" |
| 107 | /* 695 */ "rev16\t\000" |
| 108 | /* 702 */ "luti6\t\000" |
| 109 | /* 709 */ "setf8\t\000" |
| 110 | /* 716 */ "sm3tt1a\t\000" |
| 111 | /* 725 */ "sm3tt2a\t\000" |
| 112 | /* 734 */ "bfmop4a\t\000" |
| 113 | /* 743 */ "usmop4a\t\000" |
| 114 | /* 752 */ "sumop4a\t\000" |
| 115 | /* 761 */ "braa\t\000" |
| 116 | /* 767 */ "ldraa\t\000" |
| 117 | /* 774 */ "blraa\t\000" |
| 118 | /* 781 */ "saba\t\000" |
| 119 | /* 787 */ "uaba\t\000" |
| 120 | /* 793 */ "pacda\t\000" |
| 121 | /* 800 */ "ldadda\t\000" |
| 122 | /* 808 */ "ldbfadda\t\000" |
| 123 | /* 818 */ "ldfadda\t\000" |
| 124 | /* 827 */ "ldtadda\t\000" |
| 125 | /* 836 */ "autda\t\000" |
| 126 | /* 843 */ "pacga\t\000" |
| 127 | /* 850 */ "addha\t\000" |
| 128 | /* 857 */ "pacia\t\000" |
| 129 | /* 864 */ "autia\t\000" |
| 130 | /* 871 */ "brka\t\000" |
| 131 | /* 877 */ "fcmla\t\000" |
| 132 | /* 884 */ "bfmla\t\000" |
| 133 | /* 891 */ "bfmmla\t\000" |
| 134 | /* 899 */ "usmmla\t\000" |
| 135 | /* 907 */ "ummla\t\000" |
| 136 | /* 914 */ "fnmla\t\000" |
| 137 | /* 921 */ "ldbfminnma\t\000" |
| 138 | /* 933 */ "ldfminnma\t\000" |
| 139 | /* 944 */ "ldbfmaxnma\t\000" |
| 140 | /* 956 */ "ldfmaxnma\t\000" |
| 141 | /* 967 */ "ldbfmina\t\000" |
| 142 | /* 977 */ "ldfmina\t\000" |
| 143 | /* 986 */ "ldsmina\t\000" |
| 144 | /* 995 */ "ldumina\t\000" |
| 145 | /* 1004 */ "brkpa\t\000" |
| 146 | /* 1011 */ "bmopa\t\000" |
| 147 | /* 1018 */ "bfmopa\t\000" |
| 148 | /* 1026 */ "usmopa\t\000" |
| 149 | /* 1034 */ "bftmopa\t\000" |
| 150 | /* 1043 */ "ustmopa\t\000" |
| 151 | /* 1052 */ "sutmopa\t\000" |
| 152 | /* 1061 */ "sumopa\t\000" |
| 153 | /* 1069 */ "rcwsswppa\t\000" |
| 154 | /* 1080 */ "rcwswppa\t\000" |
| 155 | /* 1090 */ "ldclrpa\t\000" |
| 156 | /* 1099 */ "rcwsclrpa\t\000" |
| 157 | /* 1110 */ "rcwclrpa\t\000" |
| 158 | /* 1120 */ "rcwscaspa\t\000" |
| 159 | /* 1131 */ "rcwcaspa\t\000" |
| 160 | /* 1141 */ "ldsetpa\t\000" |
| 161 | /* 1150 */ "rcwssetpa\t\000" |
| 162 | /* 1161 */ "rcwsetpa\t\000" |
| 163 | /* 1171 */ "rcwsswpa\t\000" |
| 164 | /* 1181 */ "rcwswpa\t\000" |
| 165 | /* 1190 */ "fexpa\t\000" |
| 166 | /* 1197 */ "ldclra\t\000" |
| 167 | /* 1205 */ "rcwsclra\t\000" |
| 168 | /* 1215 */ "ldtclra\t\000" |
| 169 | /* 1224 */ "rcwclra\t\000" |
| 170 | /* 1233 */ "ldeora\t\000" |
| 171 | /* 1241 */ "srsra\t\000" |
| 172 | /* 1248 */ "ursra\t\000" |
| 173 | /* 1255 */ "ssra\t\000" |
| 174 | /* 1261 */ "usra\t\000" |
| 175 | /* 1267 */ "rcwscasa\t\000" |
| 176 | /* 1277 */ "rcwcasa\t\000" |
| 177 | /* 1286 */ "ldseta\t\000" |
| 178 | /* 1294 */ "rcwsseta\t\000" |
| 179 | /* 1304 */ "ldtseta\t\000" |
| 180 | /* 1313 */ "rcwseta\t\000" |
| 181 | /* 1322 */ "frinta\t\000" |
| 182 | /* 1330 */ "swpta\t\000" |
| 183 | /* 1337 */ "clasta\t\000" |
| 184 | /* 1345 */ "addva\t\000" |
| 185 | /* 1352 */ "mova\t\000" |
| 186 | /* 1358 */ "ldbfmaxa\t\000" |
| 187 | /* 1368 */ "ldfmaxa\t\000" |
| 188 | /* 1377 */ "ldsmaxa\t\000" |
| 189 | /* 1386 */ "ldumaxa\t\000" |
| 190 | /* 1395 */ "pacdza\t\000" |
| 191 | /* 1403 */ "autdza\t\000" |
| 192 | /* 1411 */ "paciza\t\000" |
| 193 | /* 1419 */ "autiza\t\000" |
| 194 | /* 1427 */ "ld1b\t\000" |
| 195 | /* 1433 */ "ldff1b\t\000" |
| 196 | /* 1441 */ "ldnf1b\t\000" |
| 197 | /* 1449 */ "ldnt1b\t\000" |
| 198 | /* 1457 */ "stnt1b\t\000" |
| 199 | /* 1465 */ "st1b\t\000" |
| 200 | /* 1471 */ "sm3tt1b\t\000" |
| 201 | /* 1480 */ "crc32b\t\000" |
| 202 | /* 1488 */ "ld2b\t\000" |
| 203 | /* 1494 */ "st2b\t\000" |
| 204 | /* 1500 */ "sm3tt2b\t\000" |
| 205 | /* 1509 */ "ld3b\t\000" |
| 206 | /* 1515 */ "st3b\t\000" |
| 207 | /* 1521 */ "lda64b\t\000" |
| 208 | /* 1529 */ "ld64b\t\000" |
| 209 | /* 1536 */ "stl64b\t\000" |
| 210 | /* 1544 */ "st64b\t\000" |
| 211 | /* 1551 */ "ld4b\t\000" |
| 212 | /* 1557 */ "st4b\t\000" |
| 213 | /* 1563 */ "ldaddab\t\000" |
| 214 | /* 1572 */ "ldsminab\t\000" |
| 215 | /* 1582 */ "lduminab\t\000" |
| 216 | /* 1592 */ "swpab\t\000" |
| 217 | /* 1599 */ "brab\t\000" |
| 218 | /* 1605 */ "ldrab\t\000" |
| 219 | /* 1612 */ "blrab\t\000" |
| 220 | /* 1619 */ "ldclrab\t\000" |
| 221 | /* 1628 */ "ldeorab\t\000" |
| 222 | /* 1637 */ "casab\t\000" |
| 223 | /* 1644 */ "ldsetab\t\000" |
| 224 | /* 1653 */ "ldsmaxab\t\000" |
| 225 | /* 1663 */ "ldumaxab\t\000" |
| 226 | /* 1673 */ "fmlallbb\t\000" |
| 227 | /* 1683 */ "crc32cb\t\000" |
| 228 | /* 1692 */ "sqdecb\t\000" |
| 229 | /* 1700 */ "uqdecb\t\000" |
| 230 | /* 1708 */ "sqincb\t\000" |
| 231 | /* 1716 */ "uqincb\t\000" |
| 232 | /* 1724 */ "pacdb\t\000" |
| 233 | /* 1731 */ "ldaddb\t\000" |
| 234 | /* 1739 */ "autdb\t\000" |
| 235 | /* 1746 */ "tchangeb\t\000" |
| 236 | /* 1756 */ "prfb\t\000" |
| 237 | /* 1762 */ "flogb\t\000" |
| 238 | /* 1769 */ "pacib\t\000" |
| 239 | /* 1776 */ "autib\t\000" |
| 240 | /* 1783 */ "brkb\t\000" |
| 241 | /* 1789 */ "sabalb\t\000" |
| 242 | /* 1797 */ "uabalb\t\000" |
| 243 | /* 1805 */ "ldaddalb\t\000" |
| 244 | /* 1815 */ "sqdmlalb\t\000" |
| 245 | /* 1825 */ "bfmlalb\t\000" |
| 246 | /* 1834 */ "smlalb\t\000" |
| 247 | /* 1842 */ "umlalb\t\000" |
| 248 | /* 1850 */ "ldsminalb\t\000" |
| 249 | /* 1861 */ "lduminalb\t\000" |
| 250 | /* 1872 */ "swpalb\t\000" |
| 251 | /* 1880 */ "ldclralb\t\000" |
| 252 | /* 1890 */ "ldeoralb\t\000" |
| 253 | /* 1900 */ "casalb\t\000" |
| 254 | /* 1908 */ "ldsetalb\t\000" |
| 255 | /* 1918 */ "ldsmaxalb\t\000" |
| 256 | /* 1929 */ "ldumaxalb\t\000" |
| 257 | /* 1940 */ "ssublb\t\000" |
| 258 | /* 1948 */ "usublb\t\000" |
| 259 | /* 1956 */ "sbclb\t\000" |
| 260 | /* 1963 */ "adclb\t\000" |
| 261 | /* 1970 */ "sabdlb\t\000" |
| 262 | /* 1978 */ "uabdlb\t\000" |
| 263 | /* 1986 */ "ldaddlb\t\000" |
| 264 | /* 1995 */ "saddlb\t\000" |
| 265 | /* 2003 */ "uaddlb\t\000" |
| 266 | /* 2011 */ "sshllb\t\000" |
| 267 | /* 2019 */ "ushllb\t\000" |
| 268 | /* 2027 */ "sqdmullb\t\000" |
| 269 | /* 2037 */ "pmullb\t\000" |
| 270 | /* 2045 */ "smullb\t\000" |
| 271 | /* 2053 */ "umullb\t\000" |
| 272 | /* 2061 */ "ldsminlb\t\000" |
| 273 | /* 2071 */ "lduminlb\t\000" |
| 274 | /* 2081 */ "swplb\t\000" |
| 275 | /* 2088 */ "ldclrlb\t\000" |
| 276 | /* 2097 */ "ldeorlb\t\000" |
| 277 | /* 2106 */ "caslb\t\000" |
| 278 | /* 2113 */ "sqdmlslb\t\000" |
| 279 | /* 2123 */ "bfmlslb\t\000" |
| 280 | /* 2132 */ "smlslb\t\000" |
| 281 | /* 2140 */ "umlslb\t\000" |
| 282 | /* 2148 */ "ldsetlb\t\000" |
| 283 | /* 2157 */ "ldsmaxlb\t\000" |
| 284 | /* 2167 */ "ldumaxlb\t\000" |
| 285 | /* 2177 */ "dmb\t\000" |
| 286 | /* 2182 */ "rsubhnb\t\000" |
| 287 | /* 2191 */ "raddhnb\t\000" |
| 288 | /* 2200 */ "ldsminb\t\000" |
| 289 | /* 2209 */ "lduminb\t\000" |
| 290 | /* 2218 */ "sqshrnb\t\000" |
| 291 | /* 2227 */ "uqshrnb\t\000" |
| 292 | /* 2236 */ "sqrshrnb\t\000" |
| 293 | /* 2246 */ "uqrshrnb\t\000" |
| 294 | /* 2256 */ "fcvtnb\t\000" |
| 295 | /* 2264 */ "sqxtnb\t\000" |
| 296 | /* 2272 */ "uqxtnb\t\000" |
| 297 | /* 2280 */ "sqshrunb\t\000" |
| 298 | /* 2290 */ "sqrshrunb\t\000" |
| 299 | /* 2301 */ "sqxtunb\t\000" |
| 300 | /* 2310 */ "ld1rob\t\000" |
| 301 | /* 2318 */ "brkpb\t\000" |
| 302 | /* 2325 */ "swpb\t\000" |
| 303 | /* 2331 */ "ld1rqb\t\000" |
| 304 | /* 2339 */ "ld1rb\t\000" |
| 305 | /* 2346 */ "ldarb\t\000" |
| 306 | /* 2353 */ "ldlarb\t\000" |
| 307 | /* 2361 */ "ldrb\t\000" |
| 308 | /* 2367 */ "ldclrb\t\000" |
| 309 | /* 2375 */ "stllrb\t\000" |
| 310 | /* 2383 */ "stlrb\t\000" |
| 311 | /* 2390 */ "ldeorb\t\000" |
| 312 | /* 2398 */ "ldaprb\t\000" |
| 313 | /* 2406 */ "ldtrb\t\000" |
| 314 | /* 2413 */ "strb\t\000" |
| 315 | /* 2419 */ "sttrb\t\000" |
| 316 | /* 2426 */ "ldurb\t\000" |
| 317 | /* 2433 */ "stlurb\t\000" |
| 318 | /* 2441 */ "ldapurb\t\000" |
| 319 | /* 2450 */ "sturb\t\000" |
| 320 | /* 2457 */ "ldaxrb\t\000" |
| 321 | /* 2465 */ "ldxrb\t\000" |
| 322 | /* 2472 */ "stlxrb\t\000" |
| 323 | /* 2480 */ "stxrb\t\000" |
| 324 | /* 2487 */ "ld1sb\t\000" |
| 325 | /* 2494 */ "ldff1sb\t\000" |
| 326 | /* 2503 */ "ldnf1sb\t\000" |
| 327 | /* 2512 */ "ldnt1sb\t\000" |
| 328 | /* 2521 */ "casb\t\000" |
| 329 | /* 2527 */ "dsb\t\000" |
| 330 | /* 2532 */ "isb\t\000" |
| 331 | /* 2537 */ "fmsb\t\000" |
| 332 | /* 2543 */ "fnmsb\t\000" |
| 333 | /* 2550 */ "ld1rsb\t\000" |
| 334 | /* 2558 */ "ldrsb\t\000" |
| 335 | /* 2565 */ "ldtrsb\t\000" |
| 336 | /* 2573 */ "ldursb\t\000" |
| 337 | /* 2581 */ "ldapursb\t\000" |
| 338 | /* 2591 */ "ldsetb\t\000" |
| 339 | /* 2599 */ "ssubltb\t\000" |
| 340 | /* 2608 */ "fmlalltb\t\000" |
| 341 | /* 2618 */ "cntb\t\000" |
| 342 | /* 2624 */ "fvdotb\t\000" |
| 343 | /* 2632 */ "eortb\t\000" |
| 344 | /* 2639 */ "clastb\t\000" |
| 345 | /* 2647 */ "sxtb\t\000" |
| 346 | /* 2653 */ "uxtb\t\000" |
| 347 | /* 2659 */ "bfsub\t\000" |
| 348 | /* 2666 */ "shsub\t\000" |
| 349 | /* 2673 */ "uhsub\t\000" |
| 350 | /* 2680 */ "fmsub\t\000" |
| 351 | /* 2687 */ "fnmsub\t\000" |
| 352 | /* 2695 */ "sqsub\t\000" |
| 353 | /* 2702 */ "uqsub\t\000" |
| 354 | /* 2709 */ "revb\t\000" |
| 355 | /* 2715 */ "ssubwb\t\000" |
| 356 | /* 2723 */ "usubwb\t\000" |
| 357 | /* 2731 */ "saddwb\t\000" |
| 358 | /* 2739 */ "uaddwb\t\000" |
| 359 | /* 2747 */ "ldsmaxb\t\000" |
| 360 | /* 2756 */ "ldumaxb\t\000" |
| 361 | /* 2765 */ "pacdzb\t\000" |
| 362 | /* 2773 */ "autdzb\t\000" |
| 363 | /* 2781 */ "pacizb\t\000" |
| 364 | /* 2789 */ "autizb\t\000" |
| 365 | /* 2797 */ "sha1c\t\000" |
| 366 | /* 2804 */ "sbc\t\000" |
| 367 | /* 2809 */ "adc\t\000" |
| 368 | /* 2814 */ "bic\t\000" |
| 369 | /* 2819 */ "aesemc\t\000" |
| 370 | /* 2827 */ "aesdimc\t\000" |
| 371 | /* 2836 */ "aesimc\t\000" |
| 372 | /* 2844 */ "aesmc\t\000" |
| 373 | /* 2851 */ "csinc\t\000" |
| 374 | /* 2858 */ "retaasppc\t\000" |
| 375 | /* 2869 */ "autiasppc\t\000" |
| 376 | /* 2880 */ "retabsppc\t\000" |
| 377 | /* 2891 */ "autibsppc\t\000" |
| 378 | /* 2902 */ "hvc\t\000" |
| 379 | /* 2907 */ "svc\t\000" |
| 380 | /* 2912 */ "ld1d\t\000" |
| 381 | /* 2918 */ "ldff1d\t\000" |
| 382 | /* 2926 */ "ldnf1d\t\000" |
| 383 | /* 2934 */ "ldnt1d\t\000" |
| 384 | /* 2942 */ "stnt1d\t\000" |
| 385 | /* 2950 */ "st1d\t\000" |
| 386 | /* 2956 */ "ld2d\t\000" |
| 387 | /* 2962 */ "st2d\t\000" |
| 388 | /* 2968 */ "ld3d\t\000" |
| 389 | /* 2974 */ "st3d\t\000" |
| 390 | /* 2980 */ "ld4d\t\000" |
| 391 | /* 2986 */ "st4d\t\000" |
| 392 | /* 2992 */ "fmad\t\000" |
| 393 | /* 2998 */ "fnmad\t\000" |
| 394 | /* 3005 */ "ftmad\t\000" |
| 395 | /* 3012 */ "fabd\t\000" |
| 396 | /* 3018 */ "sabd\t\000" |
| 397 | /* 3024 */ "uabd\t\000" |
| 398 | /* 3030 */ "xpacd\t\000" |
| 399 | /* 3037 */ "sqdecd\t\000" |
| 400 | /* 3045 */ "uqdecd\t\000" |
| 401 | /* 3053 */ "sqincd\t\000" |
| 402 | /* 3061 */ "uqincd\t\000" |
| 403 | /* 3069 */ "fcadd\t\000" |
| 404 | /* 3076 */ "sqcadd\t\000" |
| 405 | /* 3084 */ "ldadd\t\000" |
| 406 | /* 3091 */ "ldbfadd\t\000" |
| 407 | /* 3100 */ "stbfadd\t\000" |
| 408 | /* 3109 */ "ldfadd\t\000" |
| 409 | /* 3117 */ "stfadd\t\000" |
| 410 | /* 3125 */ "srhadd\t\000" |
| 411 | /* 3133 */ "urhadd\t\000" |
| 412 | /* 3141 */ "shadd\t\000" |
| 413 | /* 3148 */ "uhadd\t\000" |
| 414 | /* 3155 */ "fmadd\t\000" |
| 415 | /* 3162 */ "fnmadd\t\000" |
| 416 | /* 3170 */ "usqadd\t\000" |
| 417 | /* 3178 */ "suqadd\t\000" |
| 418 | /* 3186 */ "ldtadd\t\000" |
| 419 | /* 3194 */ "prfd\t\000" |
| 420 | /* 3200 */ "nand\t\000" |
| 421 | /* 3206 */ "expand\t\000" |
| 422 | /* 3214 */ "ld1rod\t\000" |
| 423 | /* 3222 */ "ld1rqd\t\000" |
| 424 | /* 3230 */ "ld1rd\t\000" |
| 425 | /* 3237 */ "asrd\t\000" |
| 426 | /* 3243 */ "aesd\t\000" |
| 427 | /* 3249 */ "cntd\t\000" |
| 428 | /* 3255 */ "revd\t\000" |
| 429 | /* 3261 */ "sm4e\t\000" |
| 430 | /* 3267 */ "splice\t\000" |
| 431 | /* 3275 */ "cbbge\t\000" |
| 432 | /* 3282 */ "cbge\t\000" |
| 433 | /* 3288 */ "facge\t\000" |
| 434 | /* 3295 */ "whilege\t\000" |
| 435 | /* 3304 */ "cbhge\t\000" |
| 436 | /* 3311 */ "fcmge\t\000" |
| 437 | /* 3318 */ "cmpge\t\000" |
| 438 | /* 3325 */ "cfltge\t\000" |
| 439 | /* 3333 */ "bfscale\t\000" |
| 440 | /* 3342 */ "whilele\t\000" |
| 441 | /* 3351 */ "fcmle\t\000" |
| 442 | /* 3358 */ "cmple\t\000" |
| 443 | /* 3365 */ "cbbne\t\000" |
| 444 | /* 3372 */ "cbne\t\000" |
| 445 | /* 3378 */ "cbhne\t\000" |
| 446 | /* 3385 */ "fcmne\t\000" |
| 447 | /* 3392 */ "ctermne\t\000" |
| 448 | /* 3401 */ "cmpne\t\000" |
| 449 | /* 3408 */ "cfltne\t\000" |
| 450 | /* 3416 */ "frecpe\t\000" |
| 451 | /* 3424 */ "urecpe\t\000" |
| 452 | /* 3432 */ "fccmpe\t\000" |
| 453 | /* 3440 */ "fcmpe\t\000" |
| 454 | /* 3447 */ "aese\t\000" |
| 455 | /* 3453 */ "pfalse\t\000" |
| 456 | /* 3461 */ "hinte\t\000" |
| 457 | /* 3468 */ "frsqrte\t\000" |
| 458 | /* 3477 */ "ursqrte\t\000" |
| 459 | /* 3486 */ "ptrue\t\000" |
| 460 | /* 3493 */ "udf\t\000" |
| 461 | /* 3498 */ "tchangef\t\000" |
| 462 | /* 3508 */ "bif\t\000" |
| 463 | /* 3513 */ "rmif\t\000" |
| 464 | /* 3519 */ "scvtf\t\000" |
| 465 | /* 3526 */ "ucvtf\t\000" |
| 466 | /* 3533 */ "st2g\t\000" |
| 467 | /* 3539 */ "stz2g\t\000" |
| 468 | /* 3546 */ "subg\t\000" |
| 469 | /* 3552 */ "addg\t\000" |
| 470 | /* 3558 */ "ldg\t\000" |
| 471 | /* 3563 */ "fneg\t\000" |
| 472 | /* 3569 */ "sqneg\t\000" |
| 473 | /* 3576 */ "csneg\t\000" |
| 474 | /* 3583 */ "histseg\t\000" |
| 475 | /* 3592 */ "irg\t\000" |
| 476 | /* 3597 */ "stg\t\000" |
| 477 | /* 3602 */ "stzg\t\000" |
| 478 | /* 3608 */ "sha1h\t\000" |
| 479 | /* 3615 */ "ld1h\t\000" |
| 480 | /* 3621 */ "ldff1h\t\000" |
| 481 | /* 3629 */ "ldnf1h\t\000" |
| 482 | /* 3637 */ "ldnt1h\t\000" |
| 483 | /* 3645 */ "stnt1h\t\000" |
| 484 | /* 3653 */ "st1h\t\000" |
| 485 | /* 3659 */ "sha512h\t\000" |
| 486 | /* 3668 */ "crc32h\t\000" |
| 487 | /* 3676 */ "ld2h\t\000" |
| 488 | /* 3682 */ "st2h\t\000" |
| 489 | /* 3688 */ "ld3h\t\000" |
| 490 | /* 3694 */ "st3h\t\000" |
| 491 | /* 3700 */ "ld4h\t\000" |
| 492 | /* 3706 */ "st4h\t\000" |
| 493 | /* 3712 */ "sha256h\t\000" |
| 494 | /* 3721 */ "ldaddah\t\000" |
| 495 | /* 3730 */ "sqrdcmlah\t\000" |
| 496 | /* 3741 */ "sqrdmlah\t\000" |
| 497 | /* 3751 */ "ldsminah\t\000" |
| 498 | /* 3761 */ "lduminah\t\000" |
| 499 | /* 3771 */ "swpah\t\000" |
| 500 | /* 3778 */ "ldclrah\t\000" |
| 501 | /* 3787 */ "ldeorah\t\000" |
| 502 | /* 3796 */ "casah\t\000" |
| 503 | /* 3803 */ "ldsetah\t\000" |
| 504 | /* 3812 */ "ldsmaxah\t\000" |
| 505 | /* 3822 */ "ldumaxah\t\000" |
| 506 | /* 3832 */ "crc32ch\t\000" |
| 507 | /* 3841 */ "sqdech\t\000" |
| 508 | /* 3849 */ "uqdech\t\000" |
| 509 | /* 3857 */ "sqinch\t\000" |
| 510 | /* 3865 */ "uqinch\t\000" |
| 511 | /* 3873 */ "nmatch\t\000" |
| 512 | /* 3881 */ "ldaddh\t\000" |
| 513 | /* 3889 */ "prfh\t\000" |
| 514 | /* 3895 */ "ldaddalh\t\000" |
| 515 | /* 3905 */ "ldsminalh\t\000" |
| 516 | /* 3916 */ "lduminalh\t\000" |
| 517 | /* 3927 */ "swpalh\t\000" |
| 518 | /* 3935 */ "ldclralh\t\000" |
| 519 | /* 3945 */ "ldeoralh\t\000" |
| 520 | /* 3955 */ "casalh\t\000" |
| 521 | /* 3963 */ "ldsetalh\t\000" |
| 522 | /* 3973 */ "ldsmaxalh\t\000" |
| 523 | /* 3984 */ "ldumaxalh\t\000" |
| 524 | /* 3995 */ "ldaddlh\t\000" |
| 525 | /* 4004 */ "ldsminlh\t\000" |
| 526 | /* 4014 */ "lduminlh\t\000" |
| 527 | /* 4024 */ "swplh\t\000" |
| 528 | /* 4031 */ "ldclrlh\t\000" |
| 529 | /* 4040 */ "ldeorlh\t\000" |
| 530 | /* 4049 */ "caslh\t\000" |
| 531 | /* 4056 */ "ldsetlh\t\000" |
| 532 | /* 4065 */ "sqdmulh\t\000" |
| 533 | /* 4074 */ "sqrdmulh\t\000" |
| 534 | /* 4084 */ "smulh\t\000" |
| 535 | /* 4091 */ "umulh\t\000" |
| 536 | /* 4098 */ "ldsmaxlh\t\000" |
| 537 | /* 4108 */ "ldumaxlh\t\000" |
| 538 | /* 4118 */ "ldsminh\t\000" |
| 539 | /* 4127 */ "lduminh\t\000" |
| 540 | /* 4136 */ "ld1roh\t\000" |
| 541 | /* 4144 */ "swph\t\000" |
| 542 | /* 4150 */ "ld1rqh\t\000" |
| 543 | /* 4158 */ "ld1rh\t\000" |
| 544 | /* 4165 */ "ldarh\t\000" |
| 545 | /* 4172 */ "ldlarh\t\000" |
| 546 | /* 4180 */ "ldrh\t\000" |
| 547 | /* 4186 */ "ldclrh\t\000" |
| 548 | /* 4194 */ "stllrh\t\000" |
| 549 | /* 4202 */ "stlrh\t\000" |
| 550 | /* 4209 */ "ldeorh\t\000" |
| 551 | /* 4217 */ "ldaprh\t\000" |
| 552 | /* 4225 */ "ldtrh\t\000" |
| 553 | /* 4232 */ "strh\t\000" |
| 554 | /* 4238 */ "sttrh\t\000" |
| 555 | /* 4245 */ "ldurh\t\000" |
| 556 | /* 4252 */ "stlurh\t\000" |
| 557 | /* 4260 */ "ldapurh\t\000" |
| 558 | /* 4269 */ "sturh\t\000" |
| 559 | /* 4276 */ "ldaxrh\t\000" |
| 560 | /* 4284 */ "ldxrh\t\000" |
| 561 | /* 4291 */ "stlxrh\t\000" |
| 562 | /* 4299 */ "stxrh\t\000" |
| 563 | /* 4306 */ "ld1sh\t\000" |
| 564 | /* 4313 */ "ldff1sh\t\000" |
| 565 | /* 4322 */ "ldnf1sh\t\000" |
| 566 | /* 4331 */ "ldnt1sh\t\000" |
| 567 | /* 4340 */ "cash\t\000" |
| 568 | /* 4346 */ "sqrdmlsh\t\000" |
| 569 | /* 4356 */ "ld1rsh\t\000" |
| 570 | /* 4364 */ "ldrsh\t\000" |
| 571 | /* 4371 */ "ldtrsh\t\000" |
| 572 | /* 4379 */ "ldursh\t\000" |
| 573 | /* 4387 */ "ldapursh\t\000" |
| 574 | /* 4397 */ "ldseth\t\000" |
| 575 | /* 4405 */ "cnth\t\000" |
| 576 | /* 4411 */ "sxth\t\000" |
| 577 | /* 4417 */ "uxth\t\000" |
| 578 | /* 4423 */ "revh\t\000" |
| 579 | /* 4429 */ "ldsmaxh\t\000" |
| 580 | /* 4438 */ "ldumaxh\t\000" |
| 581 | /* 4447 */ "xpaci\t\000" |
| 582 | /* 4454 */ "cbbhi\t\000" |
| 583 | /* 4461 */ "cbhi\t\000" |
| 584 | /* 4467 */ "whilehi\t\000" |
| 585 | /* 4476 */ "cbhhi\t\000" |
| 586 | /* 4483 */ "punpkhi\t\000" |
| 587 | /* 4492 */ "sunpkhi\t\000" |
| 588 | /* 4501 */ "uunpkhi\t\000" |
| 589 | /* 4510 */ "cmhi\t\000" |
| 590 | /* 4516 */ "cmphi\t\000" |
| 591 | /* 4523 */ "cflthi\t\000" |
| 592 | /* 4531 */ "sli\t\000" |
| 593 | /* 4536 */ "gmi\t\000" |
| 594 | /* 4541 */ "mvni\t\000" |
| 595 | /* 4547 */ "sri\t\000" |
| 596 | /* 4552 */ "frinti\t\000" |
| 597 | /* 4560 */ "movi\t\000" |
| 598 | /* 4566 */ "sunpk\t\000" |
| 599 | /* 4573 */ "uunpk\t\000" |
| 600 | /* 4580 */ "brk\t\000" |
| 601 | /* 4585 */ "movk\t\000" |
| 602 | /* 4591 */ "sabal\t\000" |
| 603 | /* 4598 */ "uabal\t\000" |
| 604 | /* 4605 */ "ldaddal\t\000" |
| 605 | /* 4614 */ "ldbfaddal\t\000" |
| 606 | /* 4625 */ "ldfaddal\t\000" |
| 607 | /* 4635 */ "ldtaddal\t\000" |
| 608 | /* 4645 */ "sqdmlal\t\000" |
| 609 | /* 4654 */ "bfmlal\t\000" |
| 610 | /* 4662 */ "pmlal\t\000" |
| 611 | /* 4669 */ "smlal\t\000" |
| 612 | /* 4676 */ "umlal\t\000" |
| 613 | /* 4683 */ "ldbfminnmal\t\000" |
| 614 | /* 4696 */ "ldfminnmal\t\000" |
| 615 | /* 4708 */ "ldbfmaxnmal\t\000" |
| 616 | /* 4721 */ "ldfmaxnmal\t\000" |
| 617 | /* 4733 */ "ldbfminal\t\000" |
| 618 | /* 4744 */ "ldfminal\t\000" |
| 619 | /* 4754 */ "ldsminal\t\000" |
| 620 | /* 4764 */ "lduminal\t\000" |
| 621 | /* 4774 */ "rcwsswppal\t\000" |
| 622 | /* 4786 */ "rcwswppal\t\000" |
| 623 | /* 4797 */ "ldclrpal\t\000" |
| 624 | /* 4807 */ "rcwsclrpal\t\000" |
| 625 | /* 4819 */ "rcwclrpal\t\000" |
| 626 | /* 4830 */ "rcwscaspal\t\000" |
| 627 | /* 4842 */ "rcwcaspal\t\000" |
| 628 | /* 4853 */ "ldsetpal\t\000" |
| 629 | /* 4863 */ "rcwssetpal\t\000" |
| 630 | /* 4875 */ "rcwsetpal\t\000" |
| 631 | /* 4886 */ "rcwsswpal\t\000" |
| 632 | /* 4897 */ "rcwswpal\t\000" |
| 633 | /* 4907 */ "ldclral\t\000" |
| 634 | /* 4916 */ "rcwsclral\t\000" |
| 635 | /* 4927 */ "ldtclral\t\000" |
| 636 | /* 4937 */ "rcwclral\t\000" |
| 637 | /* 4947 */ "ldeoral\t\000" |
| 638 | /* 4956 */ "rcwscasal\t\000" |
| 639 | /* 4967 */ "rcwcasal\t\000" |
| 640 | /* 4977 */ "ldsetal\t\000" |
| 641 | /* 4986 */ "rcwssetal\t\000" |
| 642 | /* 4997 */ "ldtsetal\t\000" |
| 643 | /* 5007 */ "rcwsetal\t\000" |
| 644 | /* 5017 */ "swptal\t\000" |
| 645 | /* 5025 */ "ldbfmaxal\t\000" |
| 646 | /* 5036 */ "ldfmaxal\t\000" |
| 647 | /* 5046 */ "ldsmaxal\t\000" |
| 648 | /* 5056 */ "ldumaxal\t\000" |
| 649 | /* 5066 */ "tbl\t\000" |
| 650 | /* 5071 */ "smsubl\t\000" |
| 651 | /* 5079 */ "umsubl\t\000" |
| 652 | /* 5087 */ "ssubl\t\000" |
| 653 | /* 5094 */ "usubl\t\000" |
| 654 | /* 5101 */ "sabdl\t\000" |
| 655 | /* 5108 */ "uabdl\t\000" |
| 656 | /* 5115 */ "ldaddl\t\000" |
| 657 | /* 5123 */ "ldbfaddl\t\000" |
| 658 | /* 5133 */ "stbfaddl\t\000" |
| 659 | /* 5143 */ "ldfaddl\t\000" |
| 660 | /* 5152 */ "stfaddl\t\000" |
| 661 | /* 5161 */ "smaddl\t\000" |
| 662 | /* 5169 */ "umaddl\t\000" |
| 663 | /* 5177 */ "saddl\t\000" |
| 664 | /* 5184 */ "ldtaddl\t\000" |
| 665 | /* 5193 */ "uaddl\t\000" |
| 666 | /* 5200 */ "fcsel\t\000" |
| 667 | /* 5207 */ "psel\t\000" |
| 668 | /* 5213 */ "ftssel\t\000" |
| 669 | /* 5221 */ "sqshl\t\000" |
| 670 | /* 5228 */ "uqshl\t\000" |
| 671 | /* 5235 */ "sqrshl\t\000" |
| 672 | /* 5243 */ "uqrshl\t\000" |
| 673 | /* 5251 */ "srshl\t\000" |
| 674 | /* 5258 */ "urshl\t\000" |
| 675 | /* 5265 */ "sshl\t\000" |
| 676 | /* 5271 */ "ushl\t\000" |
| 677 | /* 5277 */ "fmlall\t\000" |
| 678 | /* 5285 */ "usmlall\t\000" |
| 679 | /* 5294 */ "sumlall\t\000" |
| 680 | /* 5303 */ "sshll\t\000" |
| 681 | /* 5310 */ "ushll\t\000" |
| 682 | /* 5317 */ "smlsll\t\000" |
| 683 | /* 5325 */ "umlsll\t\000" |
| 684 | /* 5333 */ "sqdmull\t\000" |
| 685 | /* 5342 */ "pmull\t\000" |
| 686 | /* 5349 */ "smull\t\000" |
| 687 | /* 5356 */ "umull\t\000" |
| 688 | /* 5363 */ "ldbfminnml\t\000" |
| 689 | /* 5375 */ "stbfminnml\t\000" |
| 690 | /* 5387 */ "ldfminnml\t\000" |
| 691 | /* 5398 */ "stfminnml\t\000" |
| 692 | /* 5409 */ "ldbfmaxnml\t\000" |
| 693 | /* 5421 */ "stbfmaxnml\t\000" |
| 694 | /* 5433 */ "ldfmaxnml\t\000" |
| 695 | /* 5444 */ "stfmaxnml\t\000" |
| 696 | /* 5455 */ "ldbfminl\t\000" |
| 697 | /* 5465 */ "stbfminl\t\000" |
| 698 | /* 5475 */ "ldfminl\t\000" |
| 699 | /* 5484 */ "stfminl\t\000" |
| 700 | /* 5493 */ "ldsminl\t\000" |
| 701 | /* 5502 */ "lduminl\t\000" |
| 702 | /* 5511 */ "addpl\t\000" |
| 703 | /* 5518 */ "rcwsswppl\t\000" |
| 704 | /* 5529 */ "rcwswppl\t\000" |
| 705 | /* 5539 */ "ldclrpl\t\000" |
| 706 | /* 5548 */ "rcwsclrpl\t\000" |
| 707 | /* 5559 */ "rcwclrpl\t\000" |
| 708 | /* 5569 */ "rcwscaspl\t\000" |
| 709 | /* 5580 */ "rcwcaspl\t\000" |
| 710 | /* 5590 */ "addspl\t\000" |
| 711 | /* 5598 */ "ldsetpl\t\000" |
| 712 | /* 5607 */ "rcwssetpl\t\000" |
| 713 | /* 5618 */ "rcwsetpl\t\000" |
| 714 | /* 5628 */ "rcwsswpl\t\000" |
| 715 | /* 5638 */ "rcwswpl\t\000" |
| 716 | /* 5647 */ "ldclrl\t\000" |
| 717 | /* 5655 */ "rcwsclrl\t\000" |
| 718 | /* 5665 */ "ldtclrl\t\000" |
| 719 | /* 5674 */ "rcwclrl\t\000" |
| 720 | /* 5683 */ "ldeorl\t\000" |
| 721 | /* 5691 */ "rcwscasl\t\000" |
| 722 | /* 5701 */ "rcwcasl\t\000" |
| 723 | /* 5710 */ "nbsl\t\000" |
| 724 | /* 5716 */ "sqdmlsl\t\000" |
| 725 | /* 5725 */ "bfmlsl\t\000" |
| 726 | /* 5733 */ "smlsl\t\000" |
| 727 | /* 5740 */ "umlsl\t\000" |
| 728 | /* 5747 */ "sysl\t\000" |
| 729 | /* 5753 */ "ldsetl\t\000" |
| 730 | /* 5761 */ "rcwssetl\t\000" |
| 731 | /* 5771 */ "ldtsetl\t\000" |
| 732 | /* 5780 */ "rcwsetl\t\000" |
| 733 | /* 5789 */ "swptl\t\000" |
| 734 | /* 5796 */ "bf1cvtl\t\000" |
| 735 | /* 5805 */ "bf2cvtl\t\000" |
| 736 | /* 5814 */ "fcvtl\t\000" |
| 737 | /* 5821 */ "bfmul\t\000" |
| 738 | /* 5828 */ "fnmul\t\000" |
| 739 | /* 5835 */ "pmul\t\000" |
| 740 | /* 5841 */ "ftsmul\t\000" |
| 741 | /* 5849 */ "addvl\t\000" |
| 742 | /* 5856 */ "rdvl\t\000" |
| 743 | /* 5862 */ "addsvl\t\000" |
| 744 | /* 5870 */ "rdsvl\t\000" |
| 745 | /* 5877 */ "ldbfmaxl\t\000" |
| 746 | /* 5887 */ "stbfmaxl\t\000" |
| 747 | /* 5897 */ "ldfmaxl\t\000" |
| 748 | /* 5906 */ "stfmaxl\t\000" |
| 749 | /* 5915 */ "ldsmaxl\t\000" |
| 750 | /* 5924 */ "ldumaxl\t\000" |
| 751 | /* 5933 */ "sha1m\t\000" |
| 752 | /* 5940 */ "sbfm\t\000" |
| 753 | /* 5946 */ "ubfm\t\000" |
| 754 | /* 5952 */ "rprfm\t\000" |
| 755 | /* 5959 */ "ldgm\t\000" |
| 756 | /* 5965 */ "stgm\t\000" |
| 757 | /* 5971 */ "stzgm\t\000" |
| 758 | /* 5978 */ "gcspushm\t\000" |
| 759 | /* 5988 */ "ldbfminnm\t\000" |
| 760 | /* 5999 */ "stbfminnm\t\000" |
| 761 | /* 6010 */ "ldfminnm\t\000" |
| 762 | /* 6020 */ "stfminnm\t\000" |
| 763 | /* 6030 */ "ldbfmaxnm\t\000" |
| 764 | /* 6041 */ "stbfmaxnm\t\000" |
| 765 | /* 6052 */ "ldfmaxnm\t\000" |
| 766 | /* 6062 */ "stfmaxnm\t\000" |
| 767 | /* 6072 */ "gcspopm\t\000" |
| 768 | /* 6081 */ "dupm\t\000" |
| 769 | /* 6087 */ "frintm\t\000" |
| 770 | /* 6095 */ "prfum\t\000" |
| 771 | /* 6102 */ "bsl1n\t\000" |
| 772 | /* 6109 */ "bsl2n\t\000" |
| 773 | /* 6116 */ "rsubhn\t\000" |
| 774 | /* 6124 */ "raddhn\t\000" |
| 775 | /* 6132 */ "famin\t\000" |
| 776 | /* 6139 */ "ldbfmin\t\000" |
| 777 | /* 6148 */ "stbfmin\t\000" |
| 778 | /* 6157 */ "ldfmin\t\000" |
| 779 | /* 6165 */ "stfmin\t\000" |
| 780 | /* 6173 */ "ldsmin\t\000" |
| 781 | /* 6181 */ "ldumin\t\000" |
| 782 | /* 6189 */ "brkn\t\000" |
| 783 | /* 6195 */ "ccmn\t\000" |
| 784 | /* 6201 */ "eon\t\000" |
| 785 | /* 6206 */ "sqshrn\t\000" |
| 786 | /* 6214 */ "uqshrn\t\000" |
| 787 | /* 6222 */ "sqrshrn\t\000" |
| 788 | /* 6231 */ "uqrshrn\t\000" |
| 789 | /* 6240 */ "orn\t\000" |
| 790 | /* 6245 */ "fcvtzsn\t\000" |
| 791 | /* 6254 */ "frintn\t\000" |
| 792 | /* 6262 */ "bfcvtn\t\000" |
| 793 | /* 6270 */ "sqcvtn\t\000" |
| 794 | /* 6278 */ "uqcvtn\t\000" |
| 795 | /* 6286 */ "sqxtn\t\000" |
| 796 | /* 6293 */ "uqxtn\t\000" |
| 797 | /* 6300 */ "sqshrun\t\000" |
| 798 | /* 6309 */ "sqrshrun\t\000" |
| 799 | /* 6319 */ "sqcvtun\t\000" |
| 800 | /* 6328 */ "sqxtun\t\000" |
| 801 | /* 6336 */ "fcvtzun\t\000" |
| 802 | /* 6345 */ "movn\t\000" |
| 803 | /* 6351 */ "fcvtxn\t\000" |
| 804 | /* 6359 */ "cblo\t\000" |
| 805 | /* 6365 */ "whilelo\t\000" |
| 806 | /* 6374 */ "punpklo\t\000" |
| 807 | /* 6383 */ "sunpklo\t\000" |
| 808 | /* 6392 */ "uunpklo\t\000" |
| 809 | /* 6401 */ "cmplo\t\000" |
| 810 | /* 6408 */ "cfltlo\t\000" |
| 811 | /* 6416 */ "zero\t\000" |
| 812 | /* 6422 */ "fcmuo\t\000" |
| 813 | /* 6429 */ "sha1p\t\000" |
| 814 | /* 6436 */ "ldap\t\000" |
| 815 | /* 6442 */ "addsubp\t\000" |
| 816 | /* 6451 */ "sqdecp\t\000" |
| 817 | /* 6459 */ "uqdecp\t\000" |
| 818 | /* 6467 */ "sqincp\t\000" |
| 819 | /* 6475 */ "uqincp\t\000" |
| 820 | /* 6483 */ "faddp\t\000" |
| 821 | /* 6490 */ "ldp\t\000" |
| 822 | /* 6495 */ "bdep\t\000" |
| 823 | /* 6501 */ "stgp\t\000" |
| 824 | /* 6507 */ "zip\t\000" |
| 825 | /* 6512 */ "sadalp\t\000" |
| 826 | /* 6520 */ "uadalp\t\000" |
| 827 | /* 6528 */ "saddlp\t\000" |
| 828 | /* 6536 */ "uaddlp\t\000" |
| 829 | /* 6544 */ "stilp\t\000" |
| 830 | /* 6551 */ "stlp\t\000" |
| 831 | /* 6557 */ "bfclamp\t\000" |
| 832 | /* 6566 */ "sclamp\t\000" |
| 833 | /* 6574 */ "uclamp\t\000" |
| 834 | /* 6582 */ "fccmp\t\000" |
| 835 | /* 6589 */ "fcmp\t\000" |
| 836 | /* 6595 */ "fminnmp\t\000" |
| 837 | /* 6604 */ "fmaxnmp\t\000" |
| 838 | /* 6613 */ "ldnp\t\000" |
| 839 | /* 6619 */ "fminp\t\000" |
| 840 | /* 6626 */ "sminp\t\000" |
| 841 | /* 6633 */ "uminp\t\000" |
| 842 | /* 6640 */ "ldtnp\t\000" |
| 843 | /* 6647 */ "stnp\t\000" |
| 844 | /* 6653 */ "sttnp\t\000" |
| 845 | /* 6660 */ "ldapp\t\000" |
| 846 | /* 6667 */ "ldiapp\t\000" |
| 847 | /* 6675 */ "rcwsswpp\t\000" |
| 848 | /* 6685 */ "rcwswpp\t\000" |
| 849 | /* 6694 */ "addqp\t\000" |
| 850 | /* 6701 */ "adrp\t\000" |
| 851 | /* 6707 */ "bgrp\t\000" |
| 852 | /* 6713 */ "ldclrp\t\000" |
| 853 | /* 6721 */ "rcwsclrp\t\000" |
| 854 | /* 6731 */ "rcwclrp\t\000" |
| 855 | /* 6740 */ "rcwscasp\t\000" |
| 856 | /* 6750 */ "rcwcasp\t\000" |
| 857 | /* 6759 */ "sysp\t\000" |
| 858 | /* 6765 */ "ldtp\t\000" |
| 859 | /* 6771 */ "ldsetp\t\000" |
| 860 | /* 6779 */ "rcwssetp\t\000" |
| 861 | /* 6789 */ "rcwsetp\t\000" |
| 862 | /* 6798 */ "cntp\t\000" |
| 863 | /* 6804 */ "frintp\t\000" |
| 864 | /* 6812 */ "lastp\t\000" |
| 865 | /* 6819 */ "firstp\t\000" |
| 866 | /* 6827 */ "sttp\t\000" |
| 867 | /* 6833 */ "fdup\t\000" |
| 868 | /* 6839 */ "rcwsswp\t\000" |
| 869 | /* 6848 */ "rcwswp\t\000" |
| 870 | /* 6856 */ "ldaxp\t\000" |
| 871 | /* 6863 */ "fmaxp\t\000" |
| 872 | /* 6870 */ "smaxp\t\000" |
| 873 | /* 6877 */ "umaxp\t\000" |
| 874 | /* 6884 */ "ldxp\t\000" |
| 875 | /* 6890 */ "stlxp\t\000" |
| 876 | /* 6897 */ "stxp\t\000" |
| 877 | /* 6903 */ "uzp\t\000" |
| 878 | /* 6908 */ "ld1q\t\000" |
| 879 | /* 6914 */ "st1q\t\000" |
| 880 | /* 6920 */ "ld2q\t\000" |
| 881 | /* 6926 */ "st2q\t\000" |
| 882 | /* 6932 */ "ld3q\t\000" |
| 883 | /* 6938 */ "st3q\t\000" |
| 884 | /* 6944 */ "ld4q\t\000" |
| 885 | /* 6950 */ "st4q\t\000" |
| 886 | /* 6956 */ "cbbeq\t\000" |
| 887 | /* 6963 */ "cbeq\t\000" |
| 888 | /* 6969 */ "cbheq\t\000" |
| 889 | /* 6976 */ "fcmeq\t\000" |
| 890 | /* 6983 */ "ctermeq\t\000" |
| 891 | /* 6992 */ "cmpeq\t\000" |
| 892 | /* 6999 */ "cflteq\t\000" |
| 893 | /* 7007 */ "tblq\t\000" |
| 894 | /* 7013 */ "dupq\t\000" |
| 895 | /* 7019 */ "extq\t\000" |
| 896 | /* 7025 */ "tbxq\t\000" |
| 897 | /* 7031 */ "ld1r\t\000" |
| 898 | /* 7037 */ "ld2r\t\000" |
| 899 | /* 7043 */ "ld3r\t\000" |
| 900 | /* 7049 */ "ld4r\t\000" |
| 901 | /* 7055 */ "ldar\t\000" |
| 902 | /* 7061 */ "ldlar\t\000" |
| 903 | /* 7068 */ "xar\t\000" |
| 904 | /* 7073 */ "fsubr\t\000" |
| 905 | /* 7080 */ "shsubr\t\000" |
| 906 | /* 7088 */ "uhsubr\t\000" |
| 907 | /* 7096 */ "sqsubr\t\000" |
| 908 | /* 7104 */ "uqsubr\t\000" |
| 909 | /* 7112 */ "retaasppcr\t\000" |
| 910 | /* 7124 */ "autiasppcr\t\000" |
| 911 | /* 7136 */ "retabsppcr\t\000" |
| 912 | /* 7148 */ "autibsppcr\t\000" |
| 913 | /* 7160 */ "adr\t\000" |
| 914 | /* 7165 */ "ldr\t\000" |
| 915 | /* 7170 */ "tenter\t\000" |
| 916 | /* 7178 */ "rdffr\t\000" |
| 917 | /* 7185 */ "wrffr\t\000" |
| 918 | /* 7192 */ "sqrshr\t\000" |
| 919 | /* 7200 */ "uqrshr\t\000" |
| 920 | /* 7208 */ "srshr\t\000" |
| 921 | /* 7215 */ "urshr\t\000" |
| 922 | /* 7222 */ "sshr\t\000" |
| 923 | /* 7228 */ "ushr\t\000" |
| 924 | /* 7234 */ "blr\t\000" |
| 925 | /* 7239 */ "ldclr\t\000" |
| 926 | /* 7246 */ "rcwsclr\t\000" |
| 927 | /* 7255 */ "ldtclr\t\000" |
| 928 | /* 7263 */ "rcwclr\t\000" |
| 929 | /* 7271 */ "sqshlr\t\000" |
| 930 | /* 7279 */ "uqshlr\t\000" |
| 931 | /* 7287 */ "sqrshlr\t\000" |
| 932 | /* 7296 */ "uqrshlr\t\000" |
| 933 | /* 7305 */ "srshlr\t\000" |
| 934 | /* 7313 */ "urshlr\t\000" |
| 935 | /* 7321 */ "stllr\t\000" |
| 936 | /* 7328 */ "lslr\t\000" |
| 937 | /* 7334 */ "stlr\t\000" |
| 938 | /* 7340 */ "ldeor\t\000" |
| 939 | /* 7347 */ "nor\t\000" |
| 940 | /* 7352 */ "ror\t\000" |
| 941 | /* 7357 */ "ldapr\t\000" |
| 942 | /* 7364 */ "orr\t\000" |
| 943 | /* 7369 */ "asrr\t\000" |
| 944 | /* 7375 */ "lsrr\t\000" |
| 945 | /* 7381 */ "msrr\t\000" |
| 946 | /* 7387 */ "asr\t\000" |
| 947 | /* 7392 */ "lsr\t\000" |
| 948 | /* 7397 */ "msr\t\000" |
| 949 | /* 7402 */ "insr\t\000" |
| 950 | /* 7408 */ "ldtr\t\000" |
| 951 | /* 7414 */ "gcsstr\t\000" |
| 952 | /* 7422 */ "gcssttr\t\000" |
| 953 | /* 7431 */ "extr\t\000" |
| 954 | /* 7437 */ "ldur\t\000" |
| 955 | /* 7443 */ "stlur\t\000" |
| 956 | /* 7450 */ "ldapur\t\000" |
| 957 | /* 7458 */ "stur\t\000" |
| 958 | /* 7464 */ "fdivr\t\000" |
| 959 | /* 7471 */ "sdivr\t\000" |
| 960 | /* 7478 */ "udivr\t\000" |
| 961 | /* 7485 */ "whilewr\t\000" |
| 962 | /* 7494 */ "ldaxr\t\000" |
| 963 | /* 7501 */ "ldxr\t\000" |
| 964 | /* 7507 */ "stlxr\t\000" |
| 965 | /* 7514 */ "ldatxr\t\000" |
| 966 | /* 7522 */ "ldtxr\t\000" |
| 967 | /* 7529 */ "stltxr\t\000" |
| 968 | /* 7537 */ "stxr\t\000" |
| 969 | /* 7543 */ "sttxr\t\000" |
| 970 | /* 7550 */ "bfmop4s\t\000" |
| 971 | /* 7559 */ "usmop4s\t\000" |
| 972 | /* 7568 */ "sumop4s\t\000" |
| 973 | /* 7577 */ "rcwscas\t\000" |
| 974 | /* 7586 */ "rcwcas\t\000" |
| 975 | /* 7594 */ "brkas\t\000" |
| 976 | /* 7601 */ "brkpas\t\000" |
| 977 | /* 7609 */ "fcvtas\t\000" |
| 978 | /* 7617 */ "fabs\t\000" |
| 979 | /* 7623 */ "sqabs\t\000" |
| 980 | /* 7630 */ "brkbs\t\000" |
| 981 | /* 7637 */ "brkpbs\t\000" |
| 982 | /* 7645 */ "subs\t\000" |
| 983 | /* 7651 */ "sbcs\t\000" |
| 984 | /* 7657 */ "adcs\t\000" |
| 985 | /* 7663 */ "bics\t\000" |
| 986 | /* 7669 */ "adds\t\000" |
| 987 | /* 7675 */ "nands\t\000" |
| 988 | /* 7682 */ "ptrues\t\000" |
| 989 | /* 7690 */ "cbbhs\t\000" |
| 990 | /* 7697 */ "cbhs\t\000" |
| 991 | /* 7703 */ "whilehs\t\000" |
| 992 | /* 7712 */ "cbhhs\t\000" |
| 993 | /* 7719 */ "cmhs\t\000" |
| 994 | /* 7725 */ "cmphs\t\000" |
| 995 | /* 7732 */ "cflths\t\000" |
| 996 | /* 7740 */ "cls\t\000" |
| 997 | /* 7745 */ "whilels\t\000" |
| 998 | /* 7754 */ "bfmls\t\000" |
| 999 | /* 7761 */ "fnmls\t\000" |
| 1000 | /* 7768 */ "cmpls\t\000" |
| 1001 | /* 7775 */ "fcvtms\t\000" |
| 1002 | /* 7783 */ "ins\t\000" |
| 1003 | /* 7788 */ "brkns\t\000" |
| 1004 | /* 7795 */ "orns\t\000" |
| 1005 | /* 7801 */ "fcvtns\t\000" |
| 1006 | /* 7809 */ "subps\t\000" |
| 1007 | /* 7816 */ "frecps\t\000" |
| 1008 | /* 7824 */ "bmops\t\000" |
| 1009 | /* 7831 */ "bfmops\t\000" |
| 1010 | /* 7839 */ "usmops\t\000" |
| 1011 | /* 7847 */ "sumops\t\000" |
| 1012 | /* 7855 */ "fcvtps\t\000" |
| 1013 | /* 7863 */ "rdffrs\t\000" |
| 1014 | /* 7871 */ "mrs\t\000" |
| 1015 | /* 7876 */ "eors\t\000" |
| 1016 | /* 7882 */ "nors\t\000" |
| 1017 | /* 7888 */ "mrrs\t\000" |
| 1018 | /* 7894 */ "orrs\t\000" |
| 1019 | /* 7900 */ "frsqrts\t\000" |
| 1020 | /* 7909 */ "sys\t\000" |
| 1021 | /* 7914 */ "fcvtzs\t\000" |
| 1022 | /* 7922 */ "fjcvtzs\t\000" |
| 1023 | /* 7931 */ "caspat\t\000" |
| 1024 | /* 7939 */ "casat\t\000" |
| 1025 | /* 7946 */ "sqdmlalbt\t\000" |
| 1026 | /* 7957 */ "ssublbt\t\000" |
| 1027 | /* 7966 */ "saddlbt\t\000" |
| 1028 | /* 7975 */ "fmlallbt\t\000" |
| 1029 | /* 7985 */ "sqdmlslbt\t\000" |
| 1030 | /* 7996 */ "eorbt\t\000" |
| 1031 | /* 8003 */ "compact\t\000" |
| 1032 | /* 8012 */ "wfet\t\000" |
| 1033 | /* 8018 */ "ret\t\000" |
| 1034 | /* 8023 */ "ldset\t\000" |
| 1035 | /* 8030 */ "rcwsset\t\000" |
| 1036 | /* 8039 */ "ldtset\t\000" |
| 1037 | /* 8047 */ "rcwset\t\000" |
| 1038 | /* 8055 */ "cbbgt\t\000" |
| 1039 | /* 8062 */ "cbgt\t\000" |
| 1040 | /* 8068 */ "facgt\t\000" |
| 1041 | /* 8075 */ "whilegt\t\000" |
| 1042 | /* 8084 */ "cbhgt\t\000" |
| 1043 | /* 8091 */ "fcmgt\t\000" |
| 1044 | /* 8098 */ "cmpgt\t\000" |
| 1045 | /* 8105 */ "cfltgt\t\000" |
| 1046 | /* 8113 */ "rbit\t\000" |
| 1047 | /* 8119 */ "wfit\t\000" |
| 1048 | /* 8125 */ "texit\t\000" |
| 1049 | /* 8132 */ "sabalt\t\000" |
| 1050 | /* 8140 */ "uabalt\t\000" |
| 1051 | /* 8148 */ "sqdmlalt\t\000" |
| 1052 | /* 8158 */ "bfmlalt\t\000" |
| 1053 | /* 8167 */ "smlalt\t\000" |
| 1054 | /* 8175 */ "umlalt\t\000" |
| 1055 | /* 8183 */ "caspalt\t\000" |
| 1056 | /* 8192 */ "casalt\t\000" |
| 1057 | /* 8200 */ "cblt\t\000" |
| 1058 | /* 8206 */ "ssublt\t\000" |
| 1059 | /* 8214 */ "usublt\t\000" |
| 1060 | /* 8222 */ "sbclt\t\000" |
| 1061 | /* 8229 */ "adclt\t\000" |
| 1062 | /* 8236 */ "sabdlt\t\000" |
| 1063 | /* 8244 */ "uabdlt\t\000" |
| 1064 | /* 8252 */ "saddlt\t\000" |
| 1065 | /* 8260 */ "uaddlt\t\000" |
| 1066 | /* 8268 */ "whilelt\t\000" |
| 1067 | /* 8277 */ "scvtflt\t\000" |
| 1068 | /* 8286 */ "ucvtflt\t\000" |
| 1069 | /* 8295 */ "hlt\t\000" |
| 1070 | /* 8300 */ "sshllt\t\000" |
| 1071 | /* 8308 */ "ushllt\t\000" |
| 1072 | /* 8316 */ "sqdmullt\t\000" |
| 1073 | /* 8326 */ "pmullt\t\000" |
| 1074 | /* 8334 */ "smullt\t\000" |
| 1075 | /* 8342 */ "umullt\t\000" |
| 1076 | /* 8350 */ "fcmlt\t\000" |
| 1077 | /* 8357 */ "cmplt\t\000" |
| 1078 | /* 8364 */ "casplt\t\000" |
| 1079 | /* 8372 */ "caslt\t\000" |
| 1080 | /* 8379 */ "sqdmlslt\t\000" |
| 1081 | /* 8389 */ "bfmlslt\t\000" |
| 1082 | /* 8398 */ "smlslt\t\000" |
| 1083 | /* 8406 */ "umlslt\t\000" |
| 1084 | /* 8414 */ "cfltlt\t\000" |
| 1085 | /* 8422 */ "bf1cvtlt\t\000" |
| 1086 | /* 8432 */ "bf2cvtlt\t\000" |
| 1087 | /* 8442 */ "fcvtlt\t\000" |
| 1088 | /* 8450 */ "histcnt\t\000" |
| 1089 | /* 8459 */ "rsubhnt\t\000" |
| 1090 | /* 8468 */ "raddhnt\t\000" |
| 1091 | /* 8477 */ "hint\t\000" |
| 1092 | /* 8483 */ "sqshrnt\t\000" |
| 1093 | /* 8492 */ "uqshrnt\t\000" |
| 1094 | /* 8501 */ "sqrshrnt\t\000" |
| 1095 | /* 8511 */ "uqrshrnt\t\000" |
| 1096 | /* 8521 */ "bfcvtnt\t\000" |
| 1097 | /* 8530 */ "sqxtnt\t\000" |
| 1098 | /* 8538 */ "uqxtnt\t\000" |
| 1099 | /* 8546 */ "sqshrunt\t\000" |
| 1100 | /* 8556 */ "sqrshrunt\t\000" |
| 1101 | /* 8567 */ "sqxtunt\t\000" |
| 1102 | /* 8576 */ "fcvtxnt\t\000" |
| 1103 | /* 8585 */ "cdot\t\000" |
| 1104 | /* 8591 */ "bfdot\t\000" |
| 1105 | /* 8598 */ "usdot\t\000" |
| 1106 | /* 8605 */ "sudot\t\000" |
| 1107 | /* 8612 */ "bfvdot\t\000" |
| 1108 | /* 8620 */ "usvdot\t\000" |
| 1109 | /* 8628 */ "suvdot\t\000" |
| 1110 | /* 8636 */ "cnot\t\000" |
| 1111 | /* 8642 */ "mlapt\t\000" |
| 1112 | /* 8649 */ "msubpt\t\000" |
| 1113 | /* 8657 */ "madpt\t\000" |
| 1114 | /* 8664 */ "maddpt\t\000" |
| 1115 | /* 8672 */ "caspt\t\000" |
| 1116 | /* 8679 */ "swpt\t\000" |
| 1117 | /* 8685 */ "fsqrt\t\000" |
| 1118 | /* 8692 */ "cast\t\000" |
| 1119 | /* 8698 */ "ptest\t\000" |
| 1120 | /* 8705 */ "pfirst\t\000" |
| 1121 | /* 8713 */ "cmtst\t\000" |
| 1122 | /* 8720 */ "fmlalltt\t\000" |
| 1123 | /* 8730 */ "fvdott\t\000" |
| 1124 | /* 8738 */ "bf1cvt\t\000" |
| 1125 | /* 8746 */ "bf2cvt\t\000" |
| 1126 | /* 8754 */ "bfcvt\t\000" |
| 1127 | /* 8761 */ "sqcvt\t\000" |
| 1128 | /* 8768 */ "uqcvt\t\000" |
| 1129 | /* 8775 */ "movt\t\000" |
| 1130 | /* 8781 */ "ssubwt\t\000" |
| 1131 | /* 8789 */ "usubwt\t\000" |
| 1132 | /* 8797 */ "saddwt\t\000" |
| 1133 | /* 8805 */ "uaddwt\t\000" |
| 1134 | /* 8813 */ "bext\t\000" |
| 1135 | /* 8819 */ "pnext\t\000" |
| 1136 | /* 8826 */ "pext\t\000" |
| 1137 | /* 8832 */ "fcvtau\t\000" |
| 1138 | /* 8840 */ "sqshlu\t\000" |
| 1139 | /* 8848 */ "fcvtmu\t\000" |
| 1140 | /* 8856 */ "fcvtnu\t\000" |
| 1141 | /* 8864 */ "fcvtpu\t\000" |
| 1142 | /* 8872 */ "sqrshru\t\000" |
| 1143 | /* 8881 */ "sqcvtu\t\000" |
| 1144 | /* 8889 */ "fcvtzu\t\000" |
| 1145 | /* 8897 */ "stl64bv\t\000" |
| 1146 | /* 8906 */ "st64bv\t\000" |
| 1147 | /* 8914 */ "faddv\t\000" |
| 1148 | /* 8921 */ "saddv\t\000" |
| 1149 | /* 8928 */ "uaddv\t\000" |
| 1150 | /* 8935 */ "andv\t\000" |
| 1151 | /* 8941 */ "rev\t\000" |
| 1152 | /* 8946 */ "fdiv\t\000" |
| 1153 | /* 8952 */ "sdiv\t\000" |
| 1154 | /* 8958 */ "udiv\t\000" |
| 1155 | /* 8964 */ "saddlv\t\000" |
| 1156 | /* 8972 */ "uaddlv\t\000" |
| 1157 | /* 8980 */ "fminnmv\t\000" |
| 1158 | /* 8989 */ "fmaxnmv\t\000" |
| 1159 | /* 8998 */ "fminv\t\000" |
| 1160 | /* 9005 */ "sminv\t\000" |
| 1161 | /* 9012 */ "uminv\t\000" |
| 1162 | /* 9019 */ "csinv\t\000" |
| 1163 | /* 9026 */ "fmov\t\000" |
| 1164 | /* 9032 */ "pmov\t\000" |
| 1165 | /* 9038 */ "smov\t\000" |
| 1166 | /* 9044 */ "umov\t\000" |
| 1167 | /* 9050 */ "faddqv\t\000" |
| 1168 | /* 9058 */ "andqv\t\000" |
| 1169 | /* 9065 */ "fminnmqv\t\000" |
| 1170 | /* 9075 */ "fmaxnmqv\t\000" |
| 1171 | /* 9085 */ "fminqv\t\000" |
| 1172 | /* 9093 */ "sminqv\t\000" |
| 1173 | /* 9101 */ "uminqv\t\000" |
| 1174 | /* 9109 */ "eorqv\t\000" |
| 1175 | /* 9116 */ "fmaxqv\t\000" |
| 1176 | /* 9124 */ "smaxqv\t\000" |
| 1177 | /* 9132 */ "umaxqv\t\000" |
| 1178 | /* 9140 */ "eorv\t\000" |
| 1179 | /* 9146 */ "fmaxv\t\000" |
| 1180 | /* 9153 */ "smaxv\t\000" |
| 1181 | /* 9160 */ "umaxv\t\000" |
| 1182 | /* 9167 */ "ld1w\t\000" |
| 1183 | /* 9173 */ "ldff1w\t\000" |
| 1184 | /* 9181 */ "ldnf1w\t\000" |
| 1185 | /* 9189 */ "ldnt1w\t\000" |
| 1186 | /* 9197 */ "stnt1w\t\000" |
| 1187 | /* 9205 */ "st1w\t\000" |
| 1188 | /* 9211 */ "crc32w\t\000" |
| 1189 | /* 9219 */ "ld2w\t\000" |
| 1190 | /* 9225 */ "st2w\t\000" |
| 1191 | /* 9231 */ "ld3w\t\000" |
| 1192 | /* 9237 */ "st3w\t\000" |
| 1193 | /* 9243 */ "ld4w\t\000" |
| 1194 | /* 9249 */ "st4w\t\000" |
| 1195 | /* 9255 */ "ssubw\t\000" |
| 1196 | /* 9262 */ "usubw\t\000" |
| 1197 | /* 9269 */ "crc32cw\t\000" |
| 1198 | /* 9278 */ "sqdecw\t\000" |
| 1199 | /* 9286 */ "uqdecw\t\000" |
| 1200 | /* 9294 */ "sqincw\t\000" |
| 1201 | /* 9302 */ "uqincw\t\000" |
| 1202 | /* 9310 */ "saddw\t\000" |
| 1203 | /* 9317 */ "uaddw\t\000" |
| 1204 | /* 9324 */ "prfw\t\000" |
| 1205 | /* 9330 */ "ld1row\t\000" |
| 1206 | /* 9338 */ "ld1rqw\t\000" |
| 1207 | /* 9346 */ "ld1rw\t\000" |
| 1208 | /* 9353 */ "whilerw\t\000" |
| 1209 | /* 9362 */ "ld1sw\t\000" |
| 1210 | /* 9369 */ "ldff1sw\t\000" |
| 1211 | /* 9378 */ "ldnf1sw\t\000" |
| 1212 | /* 9387 */ "ldnt1sw\t\000" |
| 1213 | /* 9396 */ "ldpsw\t\000" |
| 1214 | /* 9403 */ "ld1rsw\t\000" |
| 1215 | /* 9411 */ "ldrsw\t\000" |
| 1216 | /* 9418 */ "ldtrsw\t\000" |
| 1217 | /* 9426 */ "ldursw\t\000" |
| 1218 | /* 9434 */ "ldapursw\t\000" |
| 1219 | /* 9444 */ "cntw\t\000" |
| 1220 | /* 9450 */ "sxtw\t\000" |
| 1221 | /* 9456 */ "uxtw\t\000" |
| 1222 | /* 9462 */ "revw\t\000" |
| 1223 | /* 9468 */ "crc32x\t\000" |
| 1224 | /* 9476 */ "frint32x\t\000" |
| 1225 | /* 9486 */ "frint64x\t\000" |
| 1226 | /* 9496 */ "bcax\t\000" |
| 1227 | /* 9502 */ "famax\t\000" |
| 1228 | /* 9509 */ "ldbfmax\t\000" |
| 1229 | /* 9518 */ "stbfmax\t\000" |
| 1230 | /* 9527 */ "ldfmax\t\000" |
| 1231 | /* 9535 */ "stfmax\t\000" |
| 1232 | /* 9543 */ "ldsmax\t\000" |
| 1233 | /* 9551 */ "ldumax\t\000" |
| 1234 | /* 9559 */ "tbx\t\000" |
| 1235 | /* 9564 */ "crc32cx\t\000" |
| 1236 | /* 9573 */ "index\t\000" |
| 1237 | /* 9580 */ "clrex\t\000" |
| 1238 | /* 9587 */ "movprfx\t\000" |
| 1239 | /* 9596 */ "fmulx\t\000" |
| 1240 | /* 9603 */ "frecpx\t\000" |
| 1241 | /* 9611 */ "frintx\t\000" |
| 1242 | /* 9619 */ "fcvtx\t\000" |
| 1243 | /* 9626 */ "sm4ekey\t\000" |
| 1244 | /* 9635 */ "fcpy\t\000" |
| 1245 | /* 9641 */ "frint32z\t\000" |
| 1246 | /* 9651 */ "frint64z\t\000" |
| 1247 | /* 9661 */ "braaz\t\000" |
| 1248 | /* 9668 */ "blraaz\t\000" |
| 1249 | /* 9676 */ "movaz\t\000" |
| 1250 | /* 9683 */ "brabz\t\000" |
| 1251 | /* 9690 */ "blrabz\t\000" |
| 1252 | /* 9698 */ "cbz\t\000" |
| 1253 | /* 9703 */ "tbz\t\000" |
| 1254 | /* 9708 */ "clz\t\000" |
| 1255 | /* 9713 */ "cbnz\t\000" |
| 1256 | /* 9719 */ "tbnz\t\000" |
| 1257 | /* 9725 */ "tfltnz\t\000" |
| 1258 | /* 9733 */ "ctz\t\000" |
| 1259 | /* 9738 */ "tfltz\t\000" |
| 1260 | /* 9745 */ "frintz\t\000" |
| 1261 | /* 9753 */ "movz\t\000" |
| 1262 | /* 9759 */ ".tlsauthdesccall \000" |
| 1263 | /* 9777 */ ".tlsdesccall \000" |
| 1264 | /* 9791 */ "zero\t{ \000" |
| 1265 | /* 9799 */ "# XRay Function Patchable RET.\000" |
| 1266 | /* 9830 */ "b.\000" |
| 1267 | /* 9833 */ "bc.\000" |
| 1268 | /* 9837 */ "# XRay Typed Event Log.\000" |
| 1269 | /* 9861 */ "# XRay Custom Event Log.\000" |
| 1270 | /* 9886 */ "# XRay Function Enter.\000" |
| 1271 | /* 9909 */ "# XRay Tail Call Exit.\000" |
| 1272 | /* 9932 */ "# XRay Function Exit.\000" |
| 1273 | /* 9954 */ "flt.\000" |
| 1274 | /* 9959 */ "hint\t#0\000" |
| 1275 | /* 9967 */ "hint\t#10\000" |
| 1276 | /* 9976 */ "hint\t#30\000" |
| 1277 | /* 9985 */ "hint\t#40\000" |
| 1278 | /* 9994 */ "hint\t#31\000" |
| 1279 | /* 10003 */ "hint\t#12\000" |
| 1280 | /* 10012 */ "hint\t#14\000" |
| 1281 | /* 10021 */ "hint\t#24\000" |
| 1282 | /* 10030 */ "pacia171615\000" |
| 1283 | /* 10042 */ "autia171615\000" |
| 1284 | /* 10054 */ "pacib171615\000" |
| 1285 | /* 10066 */ "autib171615\000" |
| 1286 | /* 10078 */ "hint\t#25\000" |
| 1287 | /* 10087 */ "hint\t#26\000" |
| 1288 | /* 10096 */ "hint\t#7\000" |
| 1289 | /* 10104 */ "hint\t#27\000" |
| 1290 | /* 10113 */ "hint\t#8\000" |
| 1291 | /* 10121 */ "hint\t#28\000" |
| 1292 | /* 10130 */ "hint\t#29\000" |
| 1293 | /* 10139 */ "hint\t#39\000" |
| 1294 | /* 10148 */ "LIFETIME_END\000" |
| 1295 | /* 10161 */ "PSEUDO_PROBE\000" |
| 1296 | /* 10174 */ "BUNDLE\000" |
| 1297 | /* 10181 */ "FAKE_USE\000" |
| 1298 | /* 10190 */ "DBG_VALUE\000" |
| 1299 | /* 10200 */ "DBG_INSTR_REF\000" |
| 1300 | /* 10214 */ "DBG_PHI\000" |
| 1301 | /* 10222 */ "DBG_LABEL\000" |
| 1302 | /* 10232 */ "LIFETIME_START\000" |
| 1303 | /* 10247 */ "DBG_VALUE_LIST\000" |
| 1304 | /* 10262 */ "cpyfe\t[\000" |
| 1305 | /* 10270 */ "setge\t[\000" |
| 1306 | /* 10278 */ "setgoe\t[\000" |
| 1307 | /* 10287 */ "sete\t[\000" |
| 1308 | /* 10294 */ "cpye\t[\000" |
| 1309 | /* 10301 */ "cpyfm\t[\000" |
| 1310 | /* 10309 */ "setgm\t[\000" |
| 1311 | /* 10317 */ "setgom\t[\000" |
| 1312 | /* 10326 */ "setm\t[\000" |
| 1313 | /* 10333 */ "cpym\t[\000" |
| 1314 | /* 10340 */ "cpyfen\t[\000" |
| 1315 | /* 10349 */ "setgen\t[\000" |
| 1316 | /* 10358 */ "setgoen\t[\000" |
| 1317 | /* 10368 */ "seten\t[\000" |
| 1318 | /* 10376 */ "cpyen\t[\000" |
| 1319 | /* 10384 */ "cpyfmn\t[\000" |
| 1320 | /* 10393 */ "setgmn\t[\000" |
| 1321 | /* 10402 */ "setgomn\t[\000" |
| 1322 | /* 10412 */ "setmn\t[\000" |
| 1323 | /* 10420 */ "cpymn\t[\000" |
| 1324 | /* 10428 */ "cpyfpn\t[\000" |
| 1325 | /* 10437 */ "setgpn\t[\000" |
| 1326 | /* 10446 */ "setgopn\t[\000" |
| 1327 | /* 10456 */ "setpn\t[\000" |
| 1328 | /* 10464 */ "cpypn\t[\000" |
| 1329 | /* 10472 */ "cpyfern\t[\000" |
| 1330 | /* 10482 */ "cpyern\t[\000" |
| 1331 | /* 10491 */ "cpyfmrn\t[\000" |
| 1332 | /* 10501 */ "cpymrn\t[\000" |
| 1333 | /* 10510 */ "cpyfprn\t[\000" |
| 1334 | /* 10520 */ "cpyprn\t[\000" |
| 1335 | /* 10529 */ "cpyfetrn\t[\000" |
| 1336 | /* 10540 */ "cpyetrn\t[\000" |
| 1337 | /* 10550 */ "cpyfmtrn\t[\000" |
| 1338 | /* 10561 */ "cpymtrn\t[\000" |
| 1339 | /* 10571 */ "cpyfptrn\t[\000" |
| 1340 | /* 10582 */ "cpyptrn\t[\000" |
| 1341 | /* 10592 */ "cpyfertrn\t[\000" |
| 1342 | /* 10604 */ "cpyertrn\t[\000" |
| 1343 | /* 10615 */ "cpyfmrtrn\t[\000" |
| 1344 | /* 10627 */ "cpymrtrn\t[\000" |
| 1345 | /* 10638 */ "cpyfprtrn\t[\000" |
| 1346 | /* 10650 */ "cpyprtrn\t[\000" |
| 1347 | /* 10661 */ "cpyfewtrn\t[\000" |
| 1348 | /* 10673 */ "cpyewtrn\t[\000" |
| 1349 | /* 10684 */ "cpyfmwtrn\t[\000" |
| 1350 | /* 10696 */ "cpymwtrn\t[\000" |
| 1351 | /* 10707 */ "cpyfpwtrn\t[\000" |
| 1352 | /* 10719 */ "cpypwtrn\t[\000" |
| 1353 | /* 10730 */ "cpyfetn\t[\000" |
| 1354 | /* 10740 */ "setgetn\t[\000" |
| 1355 | /* 10750 */ "setgoetn\t[\000" |
| 1356 | /* 10761 */ "setetn\t[\000" |
| 1357 | /* 10770 */ "cpyetn\t[\000" |
| 1358 | /* 10779 */ "cpyfmtn\t[\000" |
| 1359 | /* 10789 */ "setgmtn\t[\000" |
| 1360 | /* 10799 */ "setgomtn\t[\000" |
| 1361 | /* 10810 */ "setmtn\t[\000" |
| 1362 | /* 10819 */ "cpymtn\t[\000" |
| 1363 | /* 10828 */ "cpyfptn\t[\000" |
| 1364 | /* 10838 */ "setgptn\t[\000" |
| 1365 | /* 10848 */ "setgoptn\t[\000" |
| 1366 | /* 10859 */ "setptn\t[\000" |
| 1367 | /* 10868 */ "cpyptn\t[\000" |
| 1368 | /* 10877 */ "cpyfertn\t[\000" |
| 1369 | /* 10888 */ "cpyertn\t[\000" |
| 1370 | /* 10898 */ "cpyfmrtn\t[\000" |
| 1371 | /* 10909 */ "cpymrtn\t[\000" |
| 1372 | /* 10919 */ "cpyfprtn\t[\000" |
| 1373 | /* 10930 */ "cpyprtn\t[\000" |
| 1374 | /* 10940 */ "cpyfewtn\t[\000" |
| 1375 | /* 10951 */ "cpyewtn\t[\000" |
| 1376 | /* 10961 */ "cpyfmwtn\t[\000" |
| 1377 | /* 10972 */ "cpymwtn\t[\000" |
| 1378 | /* 10982 */ "cpyfpwtn\t[\000" |
| 1379 | /* 10993 */ "cpypwtn\t[\000" |
| 1380 | /* 11003 */ "cpyfewn\t[\000" |
| 1381 | /* 11013 */ "cpyewn\t[\000" |
| 1382 | /* 11022 */ "cpyfmwn\t[\000" |
| 1383 | /* 11032 */ "cpymwn\t[\000" |
| 1384 | /* 11041 */ "cpyfpwn\t[\000" |
| 1385 | /* 11051 */ "cpypwn\t[\000" |
| 1386 | /* 11060 */ "cpyfetwn\t[\000" |
| 1387 | /* 11071 */ "cpyetwn\t[\000" |
| 1388 | /* 11081 */ "cpyfmtwn\t[\000" |
| 1389 | /* 11092 */ "cpymtwn\t[\000" |
| 1390 | /* 11102 */ "cpyfptwn\t[\000" |
| 1391 | /* 11113 */ "cpyptwn\t[\000" |
| 1392 | /* 11123 */ "cpyfertwn\t[\000" |
| 1393 | /* 11135 */ "cpyertwn\t[\000" |
| 1394 | /* 11146 */ "cpyfmrtwn\t[\000" |
| 1395 | /* 11158 */ "cpymrtwn\t[\000" |
| 1396 | /* 11169 */ "cpyfprtwn\t[\000" |
| 1397 | /* 11181 */ "cpyprtwn\t[\000" |
| 1398 | /* 11192 */ "cpyfewtwn\t[\000" |
| 1399 | /* 11204 */ "cpyewtwn\t[\000" |
| 1400 | /* 11215 */ "cpyfmwtwn\t[\000" |
| 1401 | /* 11227 */ "cpymwtwn\t[\000" |
| 1402 | /* 11238 */ "cpyfpwtwn\t[\000" |
| 1403 | /* 11250 */ "cpypwtwn\t[\000" |
| 1404 | /* 11261 */ "cpyfp\t[\000" |
| 1405 | /* 11269 */ "setgp\t[\000" |
| 1406 | /* 11277 */ "setgop\t[\000" |
| 1407 | /* 11286 */ "setp\t[\000" |
| 1408 | /* 11293 */ "cpyp\t[\000" |
| 1409 | /* 11300 */ "cpyfet\t[\000" |
| 1410 | /* 11309 */ "setget\t[\000" |
| 1411 | /* 11318 */ "setgoet\t[\000" |
| 1412 | /* 11328 */ "setet\t[\000" |
| 1413 | /* 11336 */ "cpyet\t[\000" |
| 1414 | /* 11344 */ "cpyfmt\t[\000" |
| 1415 | /* 11353 */ "setgmt\t[\000" |
| 1416 | /* 11362 */ "setgomt\t[\000" |
| 1417 | /* 11372 */ "setmt\t[\000" |
| 1418 | /* 11380 */ "cpymt\t[\000" |
| 1419 | /* 11388 */ "cpyfpt\t[\000" |
| 1420 | /* 11397 */ "setgpt\t[\000" |
| 1421 | /* 11406 */ "setgopt\t[\000" |
| 1422 | /* 11416 */ "setpt\t[\000" |
| 1423 | /* 11424 */ "cpypt\t[\000" |
| 1424 | /* 11432 */ "cpyfert\t[\000" |
| 1425 | /* 11442 */ "cpyert\t[\000" |
| 1426 | /* 11451 */ "cpyfmrt\t[\000" |
| 1427 | /* 11461 */ "cpymrt\t[\000" |
| 1428 | /* 11470 */ "cpyfprt\t[\000" |
| 1429 | /* 11480 */ "cpyprt\t[\000" |
| 1430 | /* 11489 */ "cpyfewt\t[\000" |
| 1431 | /* 11499 */ "cpyewt\t[\000" |
| 1432 | /* 11508 */ "cpyfmwt\t[\000" |
| 1433 | /* 11518 */ "cpymwt\t[\000" |
| 1434 | /* 11527 */ "cpyfpwt\t[\000" |
| 1435 | /* 11537 */ "cpypwt\t[\000" |
| 1436 | /* 11546 */ "eretaa\000" |
| 1437 | /* 11553 */ "eretab\000" |
| 1438 | /* 11560 */ "sb\000" |
| 1439 | /* 11563 */ "pacnbiasppc\000" |
| 1440 | /* 11575 */ "paciasppc\000" |
| 1441 | /* 11585 */ "pacnbibsppc\000" |
| 1442 | /* 11597 */ "pacibsppc\000" |
| 1443 | /* 11607 */ "xaflag\000" |
| 1444 | /* 11614 */ "axflag\000" |
| 1445 | /* 11621 */ "# FEntry call\000" |
| 1446 | /* 11635 */ "setffr\000" |
| 1447 | /* 11642 */ "drps\000" |
| 1448 | /* 11647 */ "eret\000" |
| 1449 | /* 11652 */ "cfinv\000" |
| 1450 | /* 11658 */ "gcspopcx\000" |
| 1451 | /* 11667 */ "gcspushx\000" |
| 1452 | /* 11676 */ "gcspopx\000" |
| 1453 | /* 11684 */ "ld1b\t{\000" |
| 1454 | /* 11691 */ "st1b\t{\000" |
| 1455 | /* 11698 */ "ld1d\t{\000" |
| 1456 | /* 11705 */ "st1d\t{\000" |
| 1457 | /* 11712 */ "ld1h\t{\000" |
| 1458 | /* 11719 */ "st1h\t{\000" |
| 1459 | /* 11726 */ "ld1q\t{\000" |
| 1460 | /* 11733 */ "st1q\t{\000" |
| 1461 | /* 11740 */ "ld1w\t{\000" |
| 1462 | /* 11747 */ "st1w\t{\000" |
| 1463 | }; |
| 1464 | #ifdef __GNUC__ |
| 1465 | #pragma GCC diagnostic pop |
| 1466 | #endif |
| 1467 | |
| 1468 | static const uint64_t OpInfo0[] = { |
| 1469 | 0ULL, // PHI |
| 1470 | 0ULL, // INLINEASM |
| 1471 | 0ULL, // INLINEASM_BR |
| 1472 | 0ULL, // CFI_INSTRUCTION |
| 1473 | 0ULL, // EH_LABEL |
| 1474 | 0ULL, // GC_LABEL |
| 1475 | 0ULL, // ANNOTATION_LABEL |
| 1476 | 0ULL, // KILL |
| 1477 | 0ULL, // EXTRACT_SUBREG |
| 1478 | 0ULL, // INSERT_SUBREG |
| 1479 | 0ULL, // IMPLICIT_DEF |
| 1480 | 0ULL, // INIT_UNDEF |
| 1481 | 0ULL, // SUBREG_TO_REG |
| 1482 | 0ULL, // COPY_TO_REGCLASS |
| 1483 | 10191ULL, // DBG_VALUE |
| 1484 | 10248ULL, // DBG_VALUE_LIST |
| 1485 | 10201ULL, // DBG_INSTR_REF |
| 1486 | 10215ULL, // DBG_PHI |
| 1487 | 10223ULL, // DBG_LABEL |
| 1488 | 0ULL, // REG_SEQUENCE |
| 1489 | 0ULL, // COPY |
| 1490 | 0ULL, // COPY_LANEMASK |
| 1491 | 10175ULL, // BUNDLE |
| 1492 | 10233ULL, // LIFETIME_START |
| 1493 | 10149ULL, // LIFETIME_END |
| 1494 | 10162ULL, // PSEUDO_PROBE |
| 1495 | 0ULL, // ARITH_FENCE |
| 1496 | 0ULL, // STACKMAP |
| 1497 | 11622ULL, // FENTRY_CALL |
| 1498 | 0ULL, // PATCHPOINT |
| 1499 | 0ULL, // LOAD_STACK_GUARD |
| 1500 | 0ULL, // PREALLOCATED_SETUP |
| 1501 | 0ULL, // PREALLOCATED_ARG |
| 1502 | 0ULL, // STATEPOINT |
| 1503 | 0ULL, // LOCAL_ESCAPE |
| 1504 | 0ULL, // FAULTING_OP |
| 1505 | 0ULL, // PATCHABLE_OP |
| 1506 | 9887ULL, // PATCHABLE_FUNCTION_ENTER |
| 1507 | 9800ULL, // PATCHABLE_RET |
| 1508 | 9933ULL, // PATCHABLE_FUNCTION_EXIT |
| 1509 | 9910ULL, // PATCHABLE_TAIL_CALL |
| 1510 | 9862ULL, // PATCHABLE_EVENT_CALL |
| 1511 | 9838ULL, // PATCHABLE_TYPED_EVENT_CALL |
| 1512 | 0ULL, // ICALL_BRANCH_FUNNEL |
| 1513 | 10182ULL, // FAKE_USE |
| 1514 | 0ULL, // MEMBARRIER |
| 1515 | 0ULL, // JUMP_TABLE_DEBUG_INFO |
| 1516 | 0ULL, // RELOC_NONE |
| 1517 | 0ULL, // CONVERGENCECTRL_ENTRY |
| 1518 | 0ULL, // CONVERGENCECTRL_ANCHOR |
| 1519 | 0ULL, // CONVERGENCECTRL_LOOP |
| 1520 | 0ULL, // CONVERGENCECTRL_GLUE |
| 1521 | 0ULL, // G_ASSERT_SEXT |
| 1522 | 0ULL, // G_ASSERT_ZEXT |
| 1523 | 0ULL, // G_ASSERT_ALIGN |
| 1524 | 0ULL, // G_ADD |
| 1525 | 0ULL, // G_SUB |
| 1526 | 0ULL, // G_MUL |
| 1527 | 0ULL, // G_SDIV |
| 1528 | 0ULL, // G_UDIV |
| 1529 | 0ULL, // G_SREM |
| 1530 | 0ULL, // G_UREM |
| 1531 | 0ULL, // G_SDIVREM |
| 1532 | 0ULL, // G_UDIVREM |
| 1533 | 0ULL, // G_AND |
| 1534 | 0ULL, // G_OR |
| 1535 | 0ULL, // G_XOR |
| 1536 | 0ULL, // G_ABDS |
| 1537 | 0ULL, // G_ABDU |
| 1538 | 0ULL, // G_UAVGFLOOR |
| 1539 | 0ULL, // G_UAVGCEIL |
| 1540 | 0ULL, // G_SAVGFLOOR |
| 1541 | 0ULL, // G_SAVGCEIL |
| 1542 | 0ULL, // G_IMPLICIT_DEF |
| 1543 | 0ULL, // G_PHI |
| 1544 | 0ULL, // G_FRAME_INDEX |
| 1545 | 0ULL, // G_GLOBAL_VALUE |
| 1546 | 0ULL, // G_PTRAUTH_GLOBAL_VALUE |
| 1547 | 0ULL, // G_CONSTANT_POOL |
| 1548 | 0ULL, // G_EXTRACT |
| 1549 | 0ULL, // G_UNMERGE_VALUES |
| 1550 | 0ULL, // G_INSERT |
| 1551 | 0ULL, // G_MERGE_VALUES |
| 1552 | 0ULL, // G_BUILD_VECTOR |
| 1553 | 0ULL, // G_BUILD_VECTOR_TRUNC |
| 1554 | 0ULL, // G_CONCAT_VECTORS |
| 1555 | 0ULL, // G_PTRTOINT |
| 1556 | 0ULL, // G_INTTOPTR |
| 1557 | 0ULL, // G_BITCAST |
| 1558 | 0ULL, // G_FREEZE |
| 1559 | 0ULL, // G_CONSTANT_FOLD_BARRIER |
| 1560 | 0ULL, // G_INTRINSIC_FPTRUNC_ROUND |
| 1561 | 0ULL, // G_INTRINSIC_TRUNC |
| 1562 | 0ULL, // G_INTRINSIC_ROUND |
| 1563 | 0ULL, // G_INTRINSIC_LRINT |
| 1564 | 0ULL, // G_INTRINSIC_LLRINT |
| 1565 | 0ULL, // G_INTRINSIC_ROUNDEVEN |
| 1566 | 0ULL, // G_READCYCLECOUNTER |
| 1567 | 0ULL, // G_READSTEADYCOUNTER |
| 1568 | 0ULL, // G_LOAD |
| 1569 | 0ULL, // G_SEXTLOAD |
| 1570 | 0ULL, // G_ZEXTLOAD |
| 1571 | 0ULL, // G_FPEXTLOAD |
| 1572 | 0ULL, // G_INDEXED_LOAD |
| 1573 | 0ULL, // G_INDEXED_SEXTLOAD |
| 1574 | 0ULL, // G_INDEXED_ZEXTLOAD |
| 1575 | 0ULL, // G_STORE |
| 1576 | 0ULL, // G_FPTRUNCSTORE |
| 1577 | 0ULL, // G_INDEXED_STORE |
| 1578 | 0ULL, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 1579 | 0ULL, // G_ATOMIC_CMPXCHG |
| 1580 | 0ULL, // G_ATOMICRMW_XCHG |
| 1581 | 0ULL, // G_ATOMICRMW_ADD |
| 1582 | 0ULL, // G_ATOMICRMW_SUB |
| 1583 | 0ULL, // G_ATOMICRMW_AND |
| 1584 | 0ULL, // G_ATOMICRMW_NAND |
| 1585 | 0ULL, // G_ATOMICRMW_OR |
| 1586 | 0ULL, // G_ATOMICRMW_XOR |
| 1587 | 0ULL, // G_ATOMICRMW_MAX |
| 1588 | 0ULL, // G_ATOMICRMW_MIN |
| 1589 | 0ULL, // G_ATOMICRMW_UMAX |
| 1590 | 0ULL, // G_ATOMICRMW_UMIN |
| 1591 | 0ULL, // G_ATOMICRMW_FADD |
| 1592 | 0ULL, // G_ATOMICRMW_FSUB |
| 1593 | 0ULL, // G_ATOMICRMW_FMAX |
| 1594 | 0ULL, // G_ATOMICRMW_FMIN |
| 1595 | 0ULL, // G_ATOMICRMW_FMAXIMUM |
| 1596 | 0ULL, // G_ATOMICRMW_FMINIMUM |
| 1597 | 0ULL, // G_ATOMICRMW_FMAXIMUMNUM |
| 1598 | 0ULL, // G_ATOMICRMW_FMINIMUMNUM |
| 1599 | 0ULL, // G_ATOMICRMW_UINC_WRAP |
| 1600 | 0ULL, // G_ATOMICRMW_UDEC_WRAP |
| 1601 | 0ULL, // G_ATOMICRMW_USUB_COND |
| 1602 | 0ULL, // G_ATOMICRMW_USUB_SAT |
| 1603 | 0ULL, // G_FENCE |
| 1604 | 0ULL, // G_PREFETCH |
| 1605 | 0ULL, // G_BRCOND |
| 1606 | 0ULL, // G_BRINDIRECT |
| 1607 | 0ULL, // G_INVOKE_REGION_START |
| 1608 | 0ULL, // G_INTRINSIC |
| 1609 | 0ULL, // G_INTRINSIC_W_SIDE_EFFECTS |
| 1610 | 0ULL, // G_INTRINSIC_CONVERGENT |
| 1611 | 0ULL, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 1612 | 0ULL, // G_ANYEXT |
| 1613 | 0ULL, // G_TRUNC |
| 1614 | 0ULL, // G_TRUNC_SSAT_S |
| 1615 | 0ULL, // G_TRUNC_SSAT_U |
| 1616 | 0ULL, // G_TRUNC_USAT_U |
| 1617 | 0ULL, // G_CONSTANT |
| 1618 | 0ULL, // G_FCONSTANT |
| 1619 | 0ULL, // G_VASTART |
| 1620 | 0ULL, // G_VAARG |
| 1621 | 0ULL, // G_SEXT |
| 1622 | 0ULL, // G_SEXT_INREG |
| 1623 | 0ULL, // G_ZEXT |
| 1624 | 0ULL, // G_SHL |
| 1625 | 0ULL, // G_LSHR |
| 1626 | 0ULL, // G_ASHR |
| 1627 | 0ULL, // G_FSHL |
| 1628 | 0ULL, // G_FSHR |
| 1629 | 0ULL, // G_ROTR |
| 1630 | 0ULL, // G_ROTL |
| 1631 | 0ULL, // G_ICMP |
| 1632 | 0ULL, // G_FCMP |
| 1633 | 0ULL, // G_SCMP |
| 1634 | 0ULL, // G_UCMP |
| 1635 | 0ULL, // G_SELECT |
| 1636 | 0ULL, // G_UADDO |
| 1637 | 0ULL, // G_UADDE |
| 1638 | 0ULL, // G_USUBO |
| 1639 | 0ULL, // G_USUBE |
| 1640 | 0ULL, // G_SADDO |
| 1641 | 0ULL, // G_SADDE |
| 1642 | 0ULL, // G_SSUBO |
| 1643 | 0ULL, // G_SSUBE |
| 1644 | 0ULL, // G_UMULO |
| 1645 | 0ULL, // G_SMULO |
| 1646 | 0ULL, // G_UMULH |
| 1647 | 0ULL, // G_SMULH |
| 1648 | 0ULL, // G_UADDSAT |
| 1649 | 0ULL, // G_SADDSAT |
| 1650 | 0ULL, // G_USUBSAT |
| 1651 | 0ULL, // G_SSUBSAT |
| 1652 | 0ULL, // G_USHLSAT |
| 1653 | 0ULL, // G_SSHLSAT |
| 1654 | 0ULL, // G_SMULFIX |
| 1655 | 0ULL, // G_UMULFIX |
| 1656 | 0ULL, // G_SMULFIXSAT |
| 1657 | 0ULL, // G_UMULFIXSAT |
| 1658 | 0ULL, // G_SDIVFIX |
| 1659 | 0ULL, // G_UDIVFIX |
| 1660 | 0ULL, // G_SDIVFIXSAT |
| 1661 | 0ULL, // G_UDIVFIXSAT |
| 1662 | 0ULL, // G_FADD |
| 1663 | 0ULL, // G_FSUB |
| 1664 | 0ULL, // G_FMUL |
| 1665 | 0ULL, // G_FMA |
| 1666 | 0ULL, // G_FMAD |
| 1667 | 0ULL, // G_FDIV |
| 1668 | 0ULL, // G_FREM |
| 1669 | 0ULL, // G_FMODF |
| 1670 | 0ULL, // G_FPOW |
| 1671 | 0ULL, // G_FPOWI |
| 1672 | 0ULL, // G_FEXP |
| 1673 | 0ULL, // G_FEXP2 |
| 1674 | 0ULL, // G_FEXP10 |
| 1675 | 0ULL, // G_FLOG |
| 1676 | 0ULL, // G_FLOG2 |
| 1677 | 0ULL, // G_FLOG10 |
| 1678 | 0ULL, // G_FLDEXP |
| 1679 | 0ULL, // G_FFREXP |
| 1680 | 0ULL, // G_FNEG |
| 1681 | 0ULL, // G_FPEXT |
| 1682 | 0ULL, // G_FPTRUNC |
| 1683 | 0ULL, // G_FPTOSI |
| 1684 | 0ULL, // G_FPTOUI |
| 1685 | 0ULL, // G_SITOFP |
| 1686 | 0ULL, // G_UITOFP |
| 1687 | 0ULL, // G_FPTOSI_SAT |
| 1688 | 0ULL, // G_FPTOUI_SAT |
| 1689 | 0ULL, // G_FABS |
| 1690 | 0ULL, // G_FCOPYSIGN |
| 1691 | 0ULL, // G_IS_FPCLASS |
| 1692 | 0ULL, // G_FCANONICALIZE |
| 1693 | 0ULL, // G_FMINNUM |
| 1694 | 0ULL, // G_FMAXNUM |
| 1695 | 0ULL, // G_FMINNUM_IEEE |
| 1696 | 0ULL, // G_FMAXNUM_IEEE |
| 1697 | 0ULL, // G_FMINIMUM |
| 1698 | 0ULL, // G_FMAXIMUM |
| 1699 | 0ULL, // G_FMINIMUMNUM |
| 1700 | 0ULL, // G_FMAXIMUMNUM |
| 1701 | 0ULL, // G_GET_FPENV |
| 1702 | 0ULL, // G_SET_FPENV |
| 1703 | 0ULL, // G_RESET_FPENV |
| 1704 | 0ULL, // G_GET_FPMODE |
| 1705 | 0ULL, // G_SET_FPMODE |
| 1706 | 0ULL, // G_RESET_FPMODE |
| 1707 | 0ULL, // G_GET_ROUNDING |
| 1708 | 0ULL, // G_SET_ROUNDING |
| 1709 | 0ULL, // G_PTR_ADD |
| 1710 | 0ULL, // G_PTRMASK |
| 1711 | 0ULL, // G_SMIN |
| 1712 | 0ULL, // G_SMAX |
| 1713 | 0ULL, // G_UMIN |
| 1714 | 0ULL, // G_UMAX |
| 1715 | 0ULL, // G_ABS |
| 1716 | 0ULL, // G_LROUND |
| 1717 | 0ULL, // G_LLROUND |
| 1718 | 0ULL, // G_BR |
| 1719 | 0ULL, // G_BRJT |
| 1720 | 0ULL, // G_VSCALE |
| 1721 | 0ULL, // G_INSERT_SUBVECTOR |
| 1722 | 0ULL, // G_EXTRACT_SUBVECTOR |
| 1723 | 0ULL, // G_INSERT_VECTOR_ELT |
| 1724 | 0ULL, // G_EXTRACT_VECTOR_ELT |
| 1725 | 0ULL, // G_SHUFFLE_VECTOR |
| 1726 | 0ULL, // G_SPLAT_VECTOR |
| 1727 | 0ULL, // G_STEP_VECTOR |
| 1728 | 0ULL, // G_VECTOR_COMPRESS |
| 1729 | 0ULL, // G_CTTZ |
| 1730 | 0ULL, // G_CTTZ_ZERO_POISON |
| 1731 | 0ULL, // G_CTLZ |
| 1732 | 0ULL, // G_CTLZ_ZERO_POISON |
| 1733 | 0ULL, // G_CTLS |
| 1734 | 0ULL, // G_CTPOP |
| 1735 | 0ULL, // G_BSWAP |
| 1736 | 0ULL, // G_BITREVERSE |
| 1737 | 0ULL, // G_CLMUL |
| 1738 | 0ULL, // G_CLMULH |
| 1739 | 0ULL, // G_CLMULR |
| 1740 | 0ULL, // G_FCEIL |
| 1741 | 0ULL, // G_FCOS |
| 1742 | 0ULL, // G_FSIN |
| 1743 | 0ULL, // G_FSINCOS |
| 1744 | 0ULL, // G_FTAN |
| 1745 | 0ULL, // G_FACOS |
| 1746 | 0ULL, // G_FASIN |
| 1747 | 0ULL, // G_FATAN |
| 1748 | 0ULL, // G_FATAN2 |
| 1749 | 0ULL, // G_FCOSH |
| 1750 | 0ULL, // G_FSINH |
| 1751 | 0ULL, // G_FTANH |
| 1752 | 0ULL, // G_FSQRT |
| 1753 | 0ULL, // G_FFLOOR |
| 1754 | 0ULL, // G_FRINT |
| 1755 | 0ULL, // G_FNEARBYINT |
| 1756 | 0ULL, // G_ADDRSPACE_CAST |
| 1757 | 0ULL, // G_BLOCK_ADDR |
| 1758 | 0ULL, // G_JUMP_TABLE |
| 1759 | 0ULL, // G_DYN_STACKALLOC |
| 1760 | 0ULL, // G_STACKSAVE |
| 1761 | 0ULL, // G_STACKRESTORE |
| 1762 | 0ULL, // G_STRICT_FADD |
| 1763 | 0ULL, // G_STRICT_FSUB |
| 1764 | 0ULL, // G_STRICT_FMUL |
| 1765 | 0ULL, // G_STRICT_FDIV |
| 1766 | 0ULL, // G_STRICT_FREM |
| 1767 | 0ULL, // G_STRICT_FMA |
| 1768 | 0ULL, // G_STRICT_FSQRT |
| 1769 | 0ULL, // G_STRICT_FLDEXP |
| 1770 | 0ULL, // G_STRICT_FCMP |
| 1771 | 0ULL, // G_STRICT_FCMPS |
| 1772 | 0ULL, // G_READ_REGISTER |
| 1773 | 0ULL, // G_WRITE_REGISTER |
| 1774 | 0ULL, // G_MEMCPY |
| 1775 | 0ULL, // G_MEMCPY_INLINE |
| 1776 | 0ULL, // G_MEMMOVE |
| 1777 | 0ULL, // G_MEMSET |
| 1778 | 0ULL, // G_BZERO |
| 1779 | 0ULL, // G_MEMSET_INLINE |
| 1780 | 0ULL, // G_TRAP |
| 1781 | 0ULL, // G_DEBUGTRAP |
| 1782 | 0ULL, // G_UBSANTRAP |
| 1783 | 0ULL, // G_VECREDUCE_SEQ_FADD |
| 1784 | 0ULL, // G_VECREDUCE_SEQ_FMUL |
| 1785 | 0ULL, // G_VECREDUCE_FADD |
| 1786 | 0ULL, // G_VECREDUCE_FMUL |
| 1787 | 0ULL, // G_VECREDUCE_FMAX |
| 1788 | 0ULL, // G_VECREDUCE_FMIN |
| 1789 | 0ULL, // G_VECREDUCE_FMAXIMUM |
| 1790 | 0ULL, // G_VECREDUCE_FMINIMUM |
| 1791 | 0ULL, // G_VECREDUCE_FMAXIMUMNUM |
| 1792 | 0ULL, // G_VECREDUCE_FMINIMUMNUM |
| 1793 | 0ULL, // G_VECREDUCE_ADD |
| 1794 | 0ULL, // G_VECREDUCE_MUL |
| 1795 | 0ULL, // G_VECREDUCE_AND |
| 1796 | 0ULL, // G_VECREDUCE_OR |
| 1797 | 0ULL, // G_VECREDUCE_XOR |
| 1798 | 0ULL, // G_VECREDUCE_SMAX |
| 1799 | 0ULL, // G_VECREDUCE_SMIN |
| 1800 | 0ULL, // G_VECREDUCE_UMAX |
| 1801 | 0ULL, // G_VECREDUCE_UMIN |
| 1802 | 0ULL, // G_SBFX |
| 1803 | 0ULL, // G_UBFX |
| 1804 | 0ULL, // ABS_ZPmZ_B_UNDEF |
| 1805 | 0ULL, // ABS_ZPmZ_D_UNDEF |
| 1806 | 0ULL, // ABS_ZPmZ_H_UNDEF |
| 1807 | 0ULL, // ABS_ZPmZ_S_UNDEF |
| 1808 | 0ULL, // ADDHA_MPPZ_D_PSEUDO_D |
| 1809 | 0ULL, // ADDHA_MPPZ_S_PSEUDO_S |
| 1810 | 0ULL, // ADDSWrr |
| 1811 | 0ULL, // ADDSXrr |
| 1812 | 0ULL, // ADDVA_MPPZ_D_PSEUDO_D |
| 1813 | 0ULL, // ADDVA_MPPZ_S_PSEUDO_S |
| 1814 | 0ULL, // ADDWrr |
| 1815 | 0ULL, // ADDXrr |
| 1816 | 0ULL, // ADD_VG2_M2Z2Z_D_PSEUDO |
| 1817 | 0ULL, // ADD_VG2_M2Z2Z_S_PSEUDO |
| 1818 | 0ULL, // ADD_VG2_M2ZZ_D_PSEUDO |
| 1819 | 0ULL, // ADD_VG2_M2ZZ_S_PSEUDO |
| 1820 | 0ULL, // ADD_VG2_M2Z_D_PSEUDO |
| 1821 | 0ULL, // ADD_VG2_M2Z_S_PSEUDO |
| 1822 | 0ULL, // ADD_VG4_M4Z4Z_D_PSEUDO |
| 1823 | 0ULL, // ADD_VG4_M4Z4Z_S_PSEUDO |
| 1824 | 0ULL, // ADD_VG4_M4ZZ_D_PSEUDO |
| 1825 | 0ULL, // ADD_VG4_M4ZZ_S_PSEUDO |
| 1826 | 0ULL, // ADD_VG4_M4Z_D_PSEUDO |
| 1827 | 0ULL, // ADD_VG4_M4Z_S_PSEUDO |
| 1828 | 0ULL, // ADD_ZI_B_PSEUDO |
| 1829 | 0ULL, // ADD_ZI_D_PSEUDO |
| 1830 | 0ULL, // ADD_ZI_H_PSEUDO |
| 1831 | 0ULL, // ADD_ZI_S_PSEUDO |
| 1832 | 0ULL, // ADD_ZPZZ_B_ZERO |
| 1833 | 0ULL, // ADD_ZPZZ_D_ZERO |
| 1834 | 0ULL, // ADD_ZPZZ_H_ZERO |
| 1835 | 0ULL, // ADD_ZPZZ_S_ZERO |
| 1836 | 0ULL, // ADDlowTLS |
| 1837 | 0ULL, // ADJCALLSTACKDOWN |
| 1838 | 0ULL, // ADJCALLSTACKUP |
| 1839 | 0ULL, // AESIMCrrTied |
| 1840 | 0ULL, // AESMCrrTied |
| 1841 | 0ULL, // ANDSWrr |
| 1842 | 0ULL, // ANDSXrr |
| 1843 | 0ULL, // ANDWrr |
| 1844 | 0ULL, // ANDXrr |
| 1845 | 0ULL, // AND_ZI_PSEUDO |
| 1846 | 0ULL, // AND_ZPZZ_B_ZERO |
| 1847 | 0ULL, // AND_ZPZZ_D_ZERO |
| 1848 | 0ULL, // AND_ZPZZ_H_ZERO |
| 1849 | 0ULL, // AND_ZPZZ_S_ZERO |
| 1850 | 0ULL, // ASRD_ZPZI_B_ZERO |
| 1851 | 0ULL, // ASRD_ZPZI_D_ZERO |
| 1852 | 0ULL, // ASRD_ZPZI_H_ZERO |
| 1853 | 0ULL, // ASRD_ZPZI_S_ZERO |
| 1854 | 0ULL, // ASR_ZPZI_B_UNDEF |
| 1855 | 0ULL, // ASR_ZPZI_B_ZERO |
| 1856 | 0ULL, // ASR_ZPZI_D_UNDEF |
| 1857 | 0ULL, // ASR_ZPZI_D_ZERO |
| 1858 | 0ULL, // ASR_ZPZI_H_UNDEF |
| 1859 | 0ULL, // ASR_ZPZI_H_ZERO |
| 1860 | 0ULL, // ASR_ZPZI_S_UNDEF |
| 1861 | 0ULL, // ASR_ZPZI_S_ZERO |
| 1862 | 0ULL, // ASR_ZPZZ_B_UNDEF |
| 1863 | 0ULL, // ASR_ZPZZ_B_ZERO |
| 1864 | 0ULL, // ASR_ZPZZ_D_UNDEF |
| 1865 | 0ULL, // ASR_ZPZZ_D_ZERO |
| 1866 | 0ULL, // ASR_ZPZZ_H_UNDEF |
| 1867 | 0ULL, // ASR_ZPZZ_H_ZERO |
| 1868 | 0ULL, // ASR_ZPZZ_S_UNDEF |
| 1869 | 0ULL, // ASR_ZPZZ_S_ZERO |
| 1870 | 0ULL, // ATOMIC_STORE_HINT_B |
| 1871 | 0ULL, // ATOMIC_STORE_HINT_Bi |
| 1872 | 0ULL, // ATOMIC_STORE_HINT_BroW |
| 1873 | 0ULL, // ATOMIC_STORE_HINT_BroX |
| 1874 | 0ULL, // ATOMIC_STORE_HINT_Bui |
| 1875 | 0ULL, // ATOMIC_STORE_HINT_D |
| 1876 | 0ULL, // ATOMIC_STORE_HINT_Di |
| 1877 | 0ULL, // ATOMIC_STORE_HINT_DroW |
| 1878 | 0ULL, // ATOMIC_STORE_HINT_DroX |
| 1879 | 0ULL, // ATOMIC_STORE_HINT_Dui |
| 1880 | 0ULL, // ATOMIC_STORE_HINT_H |
| 1881 | 0ULL, // ATOMIC_STORE_HINT_Hi |
| 1882 | 0ULL, // ATOMIC_STORE_HINT_HroW |
| 1883 | 0ULL, // ATOMIC_STORE_HINT_HroX |
| 1884 | 0ULL, // ATOMIC_STORE_HINT_Hui |
| 1885 | 0ULL, // ATOMIC_STORE_HINT_S |
| 1886 | 0ULL, // ATOMIC_STORE_HINT_Si |
| 1887 | 0ULL, // ATOMIC_STORE_HINT_SroW |
| 1888 | 0ULL, // ATOMIC_STORE_HINT_SroX |
| 1889 | 0ULL, // ATOMIC_STORE_HINT_Sui |
| 1890 | 0ULL, // ATOMIC_STORE_HINT_W |
| 1891 | 0ULL, // ATOMIC_STORE_HINT_Wi |
| 1892 | 0ULL, // ATOMIC_STORE_HINT_WroW |
| 1893 | 0ULL, // ATOMIC_STORE_HINT_WroX |
| 1894 | 0ULL, // ATOMIC_STORE_HINT_Wui |
| 1895 | 0ULL, // ATOMIC_STORE_HINT_X |
| 1896 | 0ULL, // ATOMIC_STORE_HINT_Xi |
| 1897 | 0ULL, // ATOMIC_STORE_HINT_XroW |
| 1898 | 0ULL, // ATOMIC_STORE_HINT_XroX |
| 1899 | 0ULL, // ATOMIC_STORE_HINT_Xui |
| 1900 | 0ULL, // AUTH_TCRETURN |
| 1901 | 0ULL, // AUTH_TCRETURN_BTI |
| 1902 | 0ULL, // AUTPAC |
| 1903 | 0ULL, // AUTPCPAC |
| 1904 | 0ULL, // AUTRELLOADPAC |
| 1905 | 0ULL, // AUTx16x17 |
| 1906 | 0ULL, // AUTxMxN |
| 1907 | 0ULL, // BFADD_VG2_M2Z_H_PSEUDO |
| 1908 | 0ULL, // BFADD_VG4_M4Z_H_PSEUDO |
| 1909 | 0ULL, // BFADD_ZPZZ_UNDEF |
| 1910 | 0ULL, // BFADD_ZPZZ_ZERO |
| 1911 | 0ULL, // BFDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 1912 | 0ULL, // BFDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 1913 | 0ULL, // BFDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 1914 | 0ULL, // BFDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 1915 | 0ULL, // BFDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 1916 | 0ULL, // BFDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 1917 | 0ULL, // BFMAXNM_ZPZZ_UNDEF |
| 1918 | 0ULL, // BFMAXNM_ZPZZ_ZERO |
| 1919 | 0ULL, // BFMAX_ZPZZ_UNDEF |
| 1920 | 0ULL, // BFMAX_ZPZZ_ZERO |
| 1921 | 0ULL, // BFMINNM_ZPZZ_UNDEF |
| 1922 | 0ULL, // BFMINNM_ZPZZ_ZERO |
| 1923 | 0ULL, // BFMIN_ZPZZ_UNDEF |
| 1924 | 0ULL, // BFMIN_ZPZZ_ZERO |
| 1925 | 0ULL, // BFMLAL_MZZI_HtoS_PSEUDO |
| 1926 | 0ULL, // BFMLAL_MZZ_HtoS_PSEUDO |
| 1927 | 0ULL, // BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 1928 | 0ULL, // BFMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 1929 | 0ULL, // BFMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 1930 | 0ULL, // BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 1931 | 0ULL, // BFMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 1932 | 0ULL, // BFMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 1933 | 0ULL, // BFMLA_VG2_M2Z2Z_PSEUDO |
| 1934 | 0ULL, // BFMLA_VG2_M2ZZI_PSEUDO |
| 1935 | 0ULL, // BFMLA_VG2_M2ZZ_PSEUDO |
| 1936 | 0ULL, // BFMLA_VG4_M4Z4Z_PSEUDO |
| 1937 | 0ULL, // BFMLA_VG4_M4ZZI_PSEUDO |
| 1938 | 0ULL, // BFMLA_VG4_M4ZZ_PSEUDO |
| 1939 | 0ULL, // BFMLA_ZPZZZ_UNDEF |
| 1940 | 0ULL, // BFMLSL_MZZI_HtoS_PSEUDO |
| 1941 | 0ULL, // BFMLSL_MZZ_HtoS_PSEUDO |
| 1942 | 0ULL, // BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 1943 | 0ULL, // BFMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 1944 | 0ULL, // BFMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 1945 | 0ULL, // BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 1946 | 0ULL, // BFMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 1947 | 0ULL, // BFMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 1948 | 0ULL, // BFMLS_VG2_M2Z2Z_PSEUDO |
| 1949 | 0ULL, // BFMLS_VG2_M2ZZI_PSEUDO |
| 1950 | 0ULL, // BFMLS_VG2_M2ZZ_PSEUDO |
| 1951 | 0ULL, // BFMLS_VG4_M4Z4Z_PSEUDO |
| 1952 | 0ULL, // BFMLS_VG4_M4ZZI_PSEUDO |
| 1953 | 0ULL, // BFMLS_VG4_M4ZZ_PSEUDO |
| 1954 | 0ULL, // BFMLS_ZPZZZ_UNDEF |
| 1955 | 0ULL, // BFMOP4A_M2Z2Z_H_PSEUDO |
| 1956 | 0ULL, // BFMOP4A_M2Z2Z_S_PSEUDO |
| 1957 | 0ULL, // BFMOP4A_M2ZZ_H_PSEUDO |
| 1958 | 0ULL, // BFMOP4A_M2ZZ_S_PSEUDO |
| 1959 | 0ULL, // BFMOP4A_MZ2Z_H_PSEUDO |
| 1960 | 0ULL, // BFMOP4A_MZ2Z_S_PSEUDO |
| 1961 | 0ULL, // BFMOP4A_MZZ_H_PSEUDO |
| 1962 | 0ULL, // BFMOP4A_MZZ_S_PSEUDO |
| 1963 | 0ULL, // BFMOP4S_M2Z2Z_H_PSEUDO |
| 1964 | 0ULL, // BFMOP4S_M2Z2Z_S_PSEUDO |
| 1965 | 0ULL, // BFMOP4S_M2ZZ_H_PSEUDO |
| 1966 | 0ULL, // BFMOP4S_M2ZZ_S_PSEUDO |
| 1967 | 0ULL, // BFMOP4S_MZ2Z_H_PSEUDO |
| 1968 | 0ULL, // BFMOP4S_MZ2Z_S_PSEUDO |
| 1969 | 0ULL, // BFMOP4S_MZZ_H_PSEUDO |
| 1970 | 0ULL, // BFMOP4S_MZZ_S_PSEUDO |
| 1971 | 0ULL, // BFMOPA_MPPZZ_H_PSEUDO |
| 1972 | 0ULL, // BFMOPA_MPPZZ_PSEUDO |
| 1973 | 0ULL, // BFMOPS_MPPZZ_H_PSEUDO |
| 1974 | 0ULL, // BFMOPS_MPPZZ_PSEUDO |
| 1975 | 0ULL, // BFMUL_ZPZZ_UNDEF |
| 1976 | 0ULL, // BFMUL_ZPZZ_ZERO |
| 1977 | 0ULL, // BFSCALE_ZPZZ_UNDEF |
| 1978 | 0ULL, // BFSUB_VG2_M2Z_H_PSEUDO |
| 1979 | 0ULL, // BFSUB_VG4_M4Z_H_PSEUDO |
| 1980 | 0ULL, // BFSUB_ZPZZ_UNDEF |
| 1981 | 0ULL, // BFSUB_ZPZZ_ZERO |
| 1982 | 0ULL, // BFTMOPA_M2ZZZI_HtoH_PSEUDO |
| 1983 | 0ULL, // BFTMOPA_M2ZZZI_HtoS_PSEUDO |
| 1984 | 0ULL, // BFVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 1985 | 0ULL, // BICSWrr |
| 1986 | 0ULL, // BICSXrr |
| 1987 | 0ULL, // BICWrr |
| 1988 | 0ULL, // BICXrr |
| 1989 | 0ULL, // BIC_ZPZZ_B_ZERO |
| 1990 | 0ULL, // BIC_ZPZZ_D_ZERO |
| 1991 | 0ULL, // BIC_ZPZZ_H_ZERO |
| 1992 | 0ULL, // BIC_ZPZZ_S_ZERO |
| 1993 | 0ULL, // BLRA |
| 1994 | 0ULL, // BLRA_RVMARKER |
| 1995 | 0ULL, // BLRNoIP |
| 1996 | 0ULL, // BLR_BTI |
| 1997 | 0ULL, // BLR_RVMARKER |
| 1998 | 0ULL, // BLR_X16 |
| 1999 | 0ULL, // BMOPA_MPPZZ_S_PSEUDO |
| 2000 | 0ULL, // BMOPS_MPPZZ_S_PSEUDO |
| 2001 | 0ULL, // BRA |
| 2002 | 0ULL, // BR_JumpTable |
| 2003 | 0ULL, // BSPv16i8 |
| 2004 | 0ULL, // BSPv8i8 |
| 2005 | 0ULL, // CATCHRET |
| 2006 | 0ULL, // CBBAssertExt |
| 2007 | 0ULL, // CBHAssertExt |
| 2008 | 0ULL, // CBWPri |
| 2009 | 0ULL, // CBWPrr |
| 2010 | 0ULL, // CBXPri |
| 2011 | 0ULL, // CBXPrr |
| 2012 | 0ULL, // CHECK_MATCHING_VL_PSEUDO |
| 2013 | 0ULL, // CLEANUPRET |
| 2014 | 0ULL, // CLS_ZPmZ_B_UNDEF |
| 2015 | 0ULL, // CLS_ZPmZ_D_UNDEF |
| 2016 | 0ULL, // CLS_ZPmZ_H_UNDEF |
| 2017 | 0ULL, // CLS_ZPmZ_S_UNDEF |
| 2018 | 0ULL, // CLZ_ZPmZ_B_UNDEF |
| 2019 | 0ULL, // CLZ_ZPmZ_D_UNDEF |
| 2020 | 0ULL, // CLZ_ZPmZ_H_UNDEF |
| 2021 | 0ULL, // CLZ_ZPmZ_S_UNDEF |
| 2022 | 0ULL, // CMP_SWAP_128 |
| 2023 | 0ULL, // CMP_SWAP_128_ACQUIRE |
| 2024 | 0ULL, // CMP_SWAP_128_MONOTONIC |
| 2025 | 0ULL, // CMP_SWAP_128_RELEASE |
| 2026 | 0ULL, // CMP_SWAP_16 |
| 2027 | 0ULL, // CMP_SWAP_32 |
| 2028 | 0ULL, // CMP_SWAP_64 |
| 2029 | 0ULL, // CMP_SWAP_8 |
| 2030 | 0ULL, // CNOT_ZPmZ_B_UNDEF |
| 2031 | 0ULL, // CNOT_ZPmZ_D_UNDEF |
| 2032 | 0ULL, // CNOT_ZPmZ_H_UNDEF |
| 2033 | 0ULL, // CNOT_ZPmZ_S_UNDEF |
| 2034 | 0ULL, // CNT_ZPmZ_B_UNDEF |
| 2035 | 0ULL, // CNT_ZPmZ_D_UNDEF |
| 2036 | 0ULL, // CNT_ZPmZ_H_UNDEF |
| 2037 | 0ULL, // CNT_ZPmZ_S_UNDEF |
| 2038 | 0ULL, // COALESCER_BARRIER_FPR128 |
| 2039 | 0ULL, // COALESCER_BARRIER_FPR16 |
| 2040 | 0ULL, // COALESCER_BARRIER_FPR32 |
| 2041 | 0ULL, // COALESCER_BARRIER_FPR64 |
| 2042 | 0ULL, // COPY_INTO_TRANSPOSED_TUPLE |
| 2043 | 0ULL, // CommitZASavePseudo |
| 2044 | 0ULL, // EMITBKEY |
| 2045 | 0ULL, // EMITMTETAGGED |
| 2046 | 0ULL, // EONWrr |
| 2047 | 0ULL, // EONXrr |
| 2048 | 0ULL, // EON_ZZZ |
| 2049 | 0ULL, // EORWrr |
| 2050 | 0ULL, // EORXrr |
| 2051 | 0ULL, // EOR_ZI_PSEUDO |
| 2052 | 0ULL, // EOR_ZPZZ_B_ZERO |
| 2053 | 0ULL, // EOR_ZPZZ_D_ZERO |
| 2054 | 0ULL, // EOR_ZPZZ_H_ZERO |
| 2055 | 0ULL, // EOR_ZPZZ_S_ZERO |
| 2056 | 0ULL, // EXT_ZZI_CONSTRUCTIVE |
| 2057 | 0ULL, // EntryPStateSM |
| 2058 | 0ULL, // F128CSEL |
| 2059 | 0ULL, // FABD_ZPZZ_D_UNDEF |
| 2060 | 0ULL, // FABD_ZPZZ_D_ZERO |
| 2061 | 0ULL, // FABD_ZPZZ_H_UNDEF |
| 2062 | 0ULL, // FABD_ZPZZ_H_ZERO |
| 2063 | 0ULL, // FABD_ZPZZ_S_UNDEF |
| 2064 | 0ULL, // FABD_ZPZZ_S_ZERO |
| 2065 | 0ULL, // FABS_ZPmZ_D_UNDEF |
| 2066 | 0ULL, // FABS_ZPmZ_H_UNDEF |
| 2067 | 0ULL, // FABS_ZPmZ_S_UNDEF |
| 2068 | 0ULL, // FADD_VG2_M2Z_D_PSEUDO |
| 2069 | 0ULL, // FADD_VG2_M2Z_H_PSEUDO |
| 2070 | 0ULL, // FADD_VG2_M2Z_S_PSEUDO |
| 2071 | 0ULL, // FADD_VG4_M4Z_D_PSEUDO |
| 2072 | 0ULL, // FADD_VG4_M4Z_H_PSEUDO |
| 2073 | 0ULL, // FADD_VG4_M4Z_S_PSEUDO |
| 2074 | 0ULL, // FADD_ZPZI_D_UNDEF |
| 2075 | 0ULL, // FADD_ZPZI_D_ZERO |
| 2076 | 0ULL, // FADD_ZPZI_H_UNDEF |
| 2077 | 0ULL, // FADD_ZPZI_H_ZERO |
| 2078 | 0ULL, // FADD_ZPZI_S_UNDEF |
| 2079 | 0ULL, // FADD_ZPZI_S_ZERO |
| 2080 | 0ULL, // FADD_ZPZZ_D_UNDEF |
| 2081 | 0ULL, // FADD_ZPZZ_D_ZERO |
| 2082 | 0ULL, // FADD_ZPZZ_H_UNDEF |
| 2083 | 0ULL, // FADD_ZPZZ_H_ZERO |
| 2084 | 0ULL, // FADD_ZPZZ_S_UNDEF |
| 2085 | 0ULL, // FADD_ZPZZ_S_ZERO |
| 2086 | 0ULL, // FAMAX_ZPZZ_D_UNDEF |
| 2087 | 0ULL, // FAMAX_ZPZZ_H_UNDEF |
| 2088 | 0ULL, // FAMAX_ZPZZ_S_UNDEF |
| 2089 | 0ULL, // FAMIN_ZPZZ_D_UNDEF |
| 2090 | 0ULL, // FAMIN_ZPZZ_H_UNDEF |
| 2091 | 0ULL, // FAMIN_ZPZZ_S_UNDEF |
| 2092 | 0ULL, // FCVTZS_ZPmZ_DtoD_UNDEF |
| 2093 | 0ULL, // FCVTZS_ZPmZ_DtoS_UNDEF |
| 2094 | 0ULL, // FCVTZS_ZPmZ_HtoD_UNDEF |
| 2095 | 0ULL, // FCVTZS_ZPmZ_HtoH_UNDEF |
| 2096 | 0ULL, // FCVTZS_ZPmZ_HtoS_UNDEF |
| 2097 | 0ULL, // FCVTZS_ZPmZ_StoD_UNDEF |
| 2098 | 0ULL, // FCVTZS_ZPmZ_StoS_UNDEF |
| 2099 | 0ULL, // FCVTZU_ZPmZ_DtoD_UNDEF |
| 2100 | 0ULL, // FCVTZU_ZPmZ_DtoS_UNDEF |
| 2101 | 0ULL, // FCVTZU_ZPmZ_HtoD_UNDEF |
| 2102 | 0ULL, // FCVTZU_ZPmZ_HtoH_UNDEF |
| 2103 | 0ULL, // FCVTZU_ZPmZ_HtoS_UNDEF |
| 2104 | 0ULL, // FCVTZU_ZPmZ_StoD_UNDEF |
| 2105 | 0ULL, // FCVTZU_ZPmZ_StoS_UNDEF |
| 2106 | 0ULL, // FCVT_ZPmZ_DtoH_UNDEF |
| 2107 | 0ULL, // FCVT_ZPmZ_DtoS_UNDEF |
| 2108 | 0ULL, // FCVT_ZPmZ_HtoD_UNDEF |
| 2109 | 0ULL, // FCVT_ZPmZ_HtoS_UNDEF |
| 2110 | 0ULL, // FCVT_ZPmZ_StoD_UNDEF |
| 2111 | 0ULL, // FCVT_ZPmZ_StoH_UNDEF |
| 2112 | 0ULL, // FDIVR_ZPZZ_D_ZERO |
| 2113 | 0ULL, // FDIVR_ZPZZ_H_ZERO |
| 2114 | 0ULL, // FDIVR_ZPZZ_S_ZERO |
| 2115 | 0ULL, // FDIV_ZPZZ_D_UNDEF |
| 2116 | 0ULL, // FDIV_ZPZZ_D_ZERO |
| 2117 | 0ULL, // FDIV_ZPZZ_H_UNDEF |
| 2118 | 0ULL, // FDIV_ZPZZ_H_ZERO |
| 2119 | 0ULL, // FDIV_ZPZZ_S_UNDEF |
| 2120 | 0ULL, // FDIV_ZPZZ_S_ZERO |
| 2121 | 0ULL, // FDOT_VG2_M2Z2Z_BtoH_PSEUDO |
| 2122 | 0ULL, // FDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 2123 | 0ULL, // FDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 2124 | 0ULL, // FDOT_VG2_M2ZZI_BtoH_PSEUDO |
| 2125 | 0ULL, // FDOT_VG2_M2ZZI_BtoS_PSEUDO |
| 2126 | 0ULL, // FDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 2127 | 0ULL, // FDOT_VG2_M2ZZ_BtoH_PSEUDO |
| 2128 | 0ULL, // FDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 2129 | 0ULL, // FDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 2130 | 0ULL, // FDOT_VG4_M4Z4Z_BtoH_PSEUDO |
| 2131 | 0ULL, // FDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 2132 | 0ULL, // FDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 2133 | 0ULL, // FDOT_VG4_M4ZZI_BtoH_PSEUDO |
| 2134 | 0ULL, // FDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 2135 | 0ULL, // FDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 2136 | 0ULL, // FDOT_VG4_M4ZZ_BtoH_PSEUDO |
| 2137 | 0ULL, // FDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 2138 | 0ULL, // FDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 2139 | 0ULL, // FLOGB_ZPZZ_D_ZERO |
| 2140 | 0ULL, // FLOGB_ZPZZ_H_ZERO |
| 2141 | 0ULL, // FLOGB_ZPZZ_S_ZERO |
| 2142 | 0ULL, // FMAXNM_ZPZI_D_UNDEF |
| 2143 | 0ULL, // FMAXNM_ZPZI_D_ZERO |
| 2144 | 0ULL, // FMAXNM_ZPZI_H_UNDEF |
| 2145 | 0ULL, // FMAXNM_ZPZI_H_ZERO |
| 2146 | 0ULL, // FMAXNM_ZPZI_S_UNDEF |
| 2147 | 0ULL, // FMAXNM_ZPZI_S_ZERO |
| 2148 | 0ULL, // FMAXNM_ZPZZ_D_UNDEF |
| 2149 | 0ULL, // FMAXNM_ZPZZ_D_ZERO |
| 2150 | 0ULL, // FMAXNM_ZPZZ_H_UNDEF |
| 2151 | 0ULL, // FMAXNM_ZPZZ_H_ZERO |
| 2152 | 0ULL, // FMAXNM_ZPZZ_S_UNDEF |
| 2153 | 0ULL, // FMAXNM_ZPZZ_S_ZERO |
| 2154 | 0ULL, // FMAX_ZPZI_D_UNDEF |
| 2155 | 0ULL, // FMAX_ZPZI_D_ZERO |
| 2156 | 0ULL, // FMAX_ZPZI_H_UNDEF |
| 2157 | 0ULL, // FMAX_ZPZI_H_ZERO |
| 2158 | 0ULL, // FMAX_ZPZI_S_UNDEF |
| 2159 | 0ULL, // FMAX_ZPZI_S_ZERO |
| 2160 | 0ULL, // FMAX_ZPZZ_D_UNDEF |
| 2161 | 0ULL, // FMAX_ZPZZ_D_ZERO |
| 2162 | 0ULL, // FMAX_ZPZZ_H_UNDEF |
| 2163 | 0ULL, // FMAX_ZPZZ_H_ZERO |
| 2164 | 0ULL, // FMAX_ZPZZ_S_UNDEF |
| 2165 | 0ULL, // FMAX_ZPZZ_S_ZERO |
| 2166 | 0ULL, // FMINNM_ZPZI_D_UNDEF |
| 2167 | 0ULL, // FMINNM_ZPZI_D_ZERO |
| 2168 | 0ULL, // FMINNM_ZPZI_H_UNDEF |
| 2169 | 0ULL, // FMINNM_ZPZI_H_ZERO |
| 2170 | 0ULL, // FMINNM_ZPZI_S_UNDEF |
| 2171 | 0ULL, // FMINNM_ZPZI_S_ZERO |
| 2172 | 0ULL, // FMINNM_ZPZZ_D_UNDEF |
| 2173 | 0ULL, // FMINNM_ZPZZ_D_ZERO |
| 2174 | 0ULL, // FMINNM_ZPZZ_H_UNDEF |
| 2175 | 0ULL, // FMINNM_ZPZZ_H_ZERO |
| 2176 | 0ULL, // FMINNM_ZPZZ_S_UNDEF |
| 2177 | 0ULL, // FMINNM_ZPZZ_S_ZERO |
| 2178 | 0ULL, // FMIN_ZPZI_D_UNDEF |
| 2179 | 0ULL, // FMIN_ZPZI_D_ZERO |
| 2180 | 0ULL, // FMIN_ZPZI_H_UNDEF |
| 2181 | 0ULL, // FMIN_ZPZI_H_ZERO |
| 2182 | 0ULL, // FMIN_ZPZI_S_UNDEF |
| 2183 | 0ULL, // FMIN_ZPZI_S_ZERO |
| 2184 | 0ULL, // FMIN_ZPZZ_D_UNDEF |
| 2185 | 0ULL, // FMIN_ZPZZ_D_ZERO |
| 2186 | 0ULL, // FMIN_ZPZZ_H_UNDEF |
| 2187 | 0ULL, // FMIN_ZPZZ_H_ZERO |
| 2188 | 0ULL, // FMIN_ZPZZ_S_UNDEF |
| 2189 | 0ULL, // FMIN_ZPZZ_S_ZERO |
| 2190 | 0ULL, // FMLALL_MZZI_BtoS_PSEUDO |
| 2191 | 0ULL, // FMLALL_MZZ_BtoS_PSEUDO |
| 2192 | 0ULL, // FMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 2193 | 0ULL, // FMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 2194 | 0ULL, // FMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 2195 | 0ULL, // FMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 2196 | 0ULL, // FMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 2197 | 0ULL, // FMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 2198 | 0ULL, // FMLAL_MZZI_BtoH_PSEUDO |
| 2199 | 0ULL, // FMLAL_MZZI_HtoS_PSEUDO |
| 2200 | 0ULL, // FMLAL_MZZ_HtoS_PSEUDO |
| 2201 | 0ULL, // FMLAL_VG2_M2Z2Z_BtoH_PSEUDO |
| 2202 | 0ULL, // FMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2203 | 0ULL, // FMLAL_VG2_M2ZZI_BtoH_PSEUDO |
| 2204 | 0ULL, // FMLAL_VG2_M2ZZI_HtoS_PSEUDO |
| 2205 | 0ULL, // FMLAL_VG2_M2ZZ_BtoH_PSEUDO |
| 2206 | 0ULL, // FMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 2207 | 0ULL, // FMLAL_VG2_MZZ_BtoH_PSEUDO |
| 2208 | 0ULL, // FMLAL_VG4_M4Z4Z_BtoH_PSEUDO |
| 2209 | 0ULL, // FMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2210 | 0ULL, // FMLAL_VG4_M4ZZI_BtoH_PSEUDO |
| 2211 | 0ULL, // FMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 2212 | 0ULL, // FMLAL_VG4_M4ZZ_BtoH_PSEUDO |
| 2213 | 0ULL, // FMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 2214 | 0ULL, // FMLA_VG2_M2Z2Z_D_PSEUDO |
| 2215 | 0ULL, // FMLA_VG2_M2Z2Z_H_PSEUDO |
| 2216 | 0ULL, // FMLA_VG2_M2Z2Z_S_PSEUDO |
| 2217 | 0ULL, // FMLA_VG2_M2ZZI_D_PSEUDO |
| 2218 | 0ULL, // FMLA_VG2_M2ZZI_H_PSEUDO |
| 2219 | 0ULL, // FMLA_VG2_M2ZZI_S_PSEUDO |
| 2220 | 0ULL, // FMLA_VG2_M2ZZ_D_PSEUDO |
| 2221 | 0ULL, // FMLA_VG2_M2ZZ_H_PSEUDO |
| 2222 | 0ULL, // FMLA_VG2_M2ZZ_S_PSEUDO |
| 2223 | 0ULL, // FMLA_VG4_M4Z4Z_D_PSEUDO |
| 2224 | 0ULL, // FMLA_VG4_M4Z4Z_H_PSEUDO |
| 2225 | 0ULL, // FMLA_VG4_M4Z4Z_S_PSEUDO |
| 2226 | 0ULL, // FMLA_VG4_M4ZZI_D_PSEUDO |
| 2227 | 0ULL, // FMLA_VG4_M4ZZI_H_PSEUDO |
| 2228 | 0ULL, // FMLA_VG4_M4ZZI_S_PSEUDO |
| 2229 | 0ULL, // FMLA_VG4_M4ZZ_D_PSEUDO |
| 2230 | 0ULL, // FMLA_VG4_M4ZZ_H_PSEUDO |
| 2231 | 0ULL, // FMLA_VG4_M4ZZ_S_PSEUDO |
| 2232 | 0ULL, // FMLA_ZPZZZ_D_UNDEF |
| 2233 | 0ULL, // FMLA_ZPZZZ_H_UNDEF |
| 2234 | 0ULL, // FMLA_ZPZZZ_S_UNDEF |
| 2235 | 0ULL, // FMLSL_MZZI_HtoS_PSEUDO |
| 2236 | 0ULL, // FMLSL_MZZ_HtoS_PSEUDO |
| 2237 | 0ULL, // FMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2238 | 0ULL, // FMLSL_VG2_M2ZZI_HtoS_PSEUDO |
| 2239 | 0ULL, // FMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 2240 | 0ULL, // FMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2241 | 0ULL, // FMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 2242 | 0ULL, // FMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 2243 | 0ULL, // FMLS_VG2_M2Z2Z_D_PSEUDO |
| 2244 | 0ULL, // FMLS_VG2_M2Z2Z_H_PSEUDO |
| 2245 | 0ULL, // FMLS_VG2_M2Z2Z_S_PSEUDO |
| 2246 | 0ULL, // FMLS_VG2_M2ZZI_D_PSEUDO |
| 2247 | 0ULL, // FMLS_VG2_M2ZZI_H_PSEUDO |
| 2248 | 0ULL, // FMLS_VG2_M2ZZI_S_PSEUDO |
| 2249 | 0ULL, // FMLS_VG2_M2ZZ_D_PSEUDO |
| 2250 | 0ULL, // FMLS_VG2_M2ZZ_H_PSEUDO |
| 2251 | 0ULL, // FMLS_VG2_M2ZZ_S_PSEUDO |
| 2252 | 0ULL, // FMLS_VG4_M4Z4Z_D_PSEUDO |
| 2253 | 0ULL, // FMLS_VG4_M4Z4Z_H_PSEUDO |
| 2254 | 0ULL, // FMLS_VG4_M4Z4Z_S_PSEUDO |
| 2255 | 0ULL, // FMLS_VG4_M4ZZI_D_PSEUDO |
| 2256 | 0ULL, // FMLS_VG4_M4ZZI_H_PSEUDO |
| 2257 | 0ULL, // FMLS_VG4_M4ZZI_S_PSEUDO |
| 2258 | 0ULL, // FMLS_VG4_M4ZZ_D_PSEUDO |
| 2259 | 0ULL, // FMLS_VG4_M4ZZ_H_PSEUDO |
| 2260 | 0ULL, // FMLS_VG4_M4ZZ_S_PSEUDO |
| 2261 | 0ULL, // FMLS_ZPZZZ_D_UNDEF |
| 2262 | 0ULL, // FMLS_ZPZZZ_H_UNDEF |
| 2263 | 0ULL, // FMLS_ZPZZZ_S_UNDEF |
| 2264 | 0ULL, // FMOP4A_M2Z2Z_BtoH_PSEUDO |
| 2265 | 0ULL, // FMOP4A_M2Z2Z_BtoS_PSEUDO |
| 2266 | 0ULL, // FMOP4A_M2Z2Z_D_PSEUDO |
| 2267 | 0ULL, // FMOP4A_M2Z2Z_H_PSEUDO |
| 2268 | 0ULL, // FMOP4A_M2Z2Z_HtoS_PSEUDO |
| 2269 | 0ULL, // FMOP4A_M2Z2Z_S_PSEUDO |
| 2270 | 0ULL, // FMOP4A_M2ZZ_BtoH_PSEUDO |
| 2271 | 0ULL, // FMOP4A_M2ZZ_BtoS_PSEUDO |
| 2272 | 0ULL, // FMOP4A_M2ZZ_D_PSEUDO |
| 2273 | 0ULL, // FMOP4A_M2ZZ_H_PSEUDO |
| 2274 | 0ULL, // FMOP4A_M2ZZ_HtoS_PSEUDO |
| 2275 | 0ULL, // FMOP4A_M2ZZ_S_PSEUDO |
| 2276 | 0ULL, // FMOP4A_MZ2Z_BtoH_PSEUDO |
| 2277 | 0ULL, // FMOP4A_MZ2Z_BtoS_PSEUDO |
| 2278 | 0ULL, // FMOP4A_MZ2Z_D_PSEUDO |
| 2279 | 0ULL, // FMOP4A_MZ2Z_H_PSEUDO |
| 2280 | 0ULL, // FMOP4A_MZ2Z_HtoS_PSEUDO |
| 2281 | 0ULL, // FMOP4A_MZ2Z_S_PSEUDO |
| 2282 | 0ULL, // FMOP4A_MZZ_BtoH_PSEUDO |
| 2283 | 0ULL, // FMOP4A_MZZ_BtoS_PSEUDO |
| 2284 | 0ULL, // FMOP4A_MZZ_D_PSEUDO |
| 2285 | 0ULL, // FMOP4A_MZZ_H_PSEUDO |
| 2286 | 0ULL, // FMOP4A_MZZ_HtoS_PSEUDO |
| 2287 | 0ULL, // FMOP4A_MZZ_S_PSEUDO |
| 2288 | 0ULL, // FMOP4S_M2Z2Z_D_PSEUDO |
| 2289 | 0ULL, // FMOP4S_M2Z2Z_H_PSEUDO |
| 2290 | 0ULL, // FMOP4S_M2Z2Z_HtoS_PSEUDO |
| 2291 | 0ULL, // FMOP4S_M2Z2Z_S_PSEUDO |
| 2292 | 0ULL, // FMOP4S_M2ZZ_D_PSEUDO |
| 2293 | 0ULL, // FMOP4S_M2ZZ_H_PSEUDO |
| 2294 | 0ULL, // FMOP4S_M2ZZ_HtoS_PSEUDO |
| 2295 | 0ULL, // FMOP4S_M2ZZ_S_PSEUDO |
| 2296 | 0ULL, // FMOP4S_MZ2Z_D_PSEUDO |
| 2297 | 0ULL, // FMOP4S_MZ2Z_H_PSEUDO |
| 2298 | 0ULL, // FMOP4S_MZ2Z_HtoS_PSEUDO |
| 2299 | 0ULL, // FMOP4S_MZ2Z_S_PSEUDO |
| 2300 | 0ULL, // FMOP4S_MZZ_D_PSEUDO |
| 2301 | 0ULL, // FMOP4S_MZZ_H_PSEUDO |
| 2302 | 0ULL, // FMOP4S_MZZ_HtoS_PSEUDO |
| 2303 | 0ULL, // FMOP4S_MZZ_S_PSEUDO |
| 2304 | 0ULL, // FMOPAL_MPPZZ_PSEUDO |
| 2305 | 0ULL, // FMOPA_MPPZZ_BtoH_PSEUDO |
| 2306 | 0ULL, // FMOPA_MPPZZ_BtoS_PSEUDO |
| 2307 | 0ULL, // FMOPA_MPPZZ_D_PSEUDO |
| 2308 | 0ULL, // FMOPA_MPPZZ_H_PSEUDO |
| 2309 | 0ULL, // FMOPA_MPPZZ_S_PSEUDO |
| 2310 | 0ULL, // FMOPSL_MPPZZ_PSEUDO |
| 2311 | 0ULL, // FMOPS_MPPZZ_D_PSEUDO |
| 2312 | 0ULL, // FMOPS_MPPZZ_H_PSEUDO |
| 2313 | 0ULL, // FMOPS_MPPZZ_S_PSEUDO |
| 2314 | 0ULL, // FMOVD0 |
| 2315 | 0ULL, // FMOVH0 |
| 2316 | 0ULL, // FMOVS0 |
| 2317 | 0ULL, // FMULX_ZPZZ_D_UNDEF |
| 2318 | 0ULL, // FMULX_ZPZZ_D_ZERO |
| 2319 | 0ULL, // FMULX_ZPZZ_H_UNDEF |
| 2320 | 0ULL, // FMULX_ZPZZ_H_ZERO |
| 2321 | 0ULL, // FMULX_ZPZZ_S_UNDEF |
| 2322 | 0ULL, // FMULX_ZPZZ_S_ZERO |
| 2323 | 0ULL, // FMUL_ZPZI_D_UNDEF |
| 2324 | 0ULL, // FMUL_ZPZI_D_ZERO |
| 2325 | 0ULL, // FMUL_ZPZI_H_UNDEF |
| 2326 | 0ULL, // FMUL_ZPZI_H_ZERO |
| 2327 | 0ULL, // FMUL_ZPZI_S_UNDEF |
| 2328 | 0ULL, // FMUL_ZPZI_S_ZERO |
| 2329 | 0ULL, // FMUL_ZPZZ_D_UNDEF |
| 2330 | 0ULL, // FMUL_ZPZZ_D_ZERO |
| 2331 | 0ULL, // FMUL_ZPZZ_H_UNDEF |
| 2332 | 0ULL, // FMUL_ZPZZ_H_ZERO |
| 2333 | 0ULL, // FMUL_ZPZZ_S_UNDEF |
| 2334 | 0ULL, // FMUL_ZPZZ_S_ZERO |
| 2335 | 0ULL, // FNEG_ZPmZ_D_UNDEF |
| 2336 | 0ULL, // FNEG_ZPmZ_H_UNDEF |
| 2337 | 0ULL, // FNEG_ZPmZ_S_UNDEF |
| 2338 | 0ULL, // FNMLA_ZPZZZ_D_UNDEF |
| 2339 | 0ULL, // FNMLA_ZPZZZ_H_UNDEF |
| 2340 | 0ULL, // FNMLA_ZPZZZ_S_UNDEF |
| 2341 | 0ULL, // FNMLS_ZPZZZ_D_UNDEF |
| 2342 | 0ULL, // FNMLS_ZPZZZ_H_UNDEF |
| 2343 | 0ULL, // FNMLS_ZPZZZ_S_UNDEF |
| 2344 | 0ULL, // FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO |
| 2345 | 0ULL, // FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO |
| 2346 | 0ULL, // FRECPX_ZPmZ_D_UNDEF |
| 2347 | 0ULL, // FRECPX_ZPmZ_H_UNDEF |
| 2348 | 0ULL, // FRECPX_ZPmZ_S_UNDEF |
| 2349 | 0ULL, // FRINT32X_ZPmZ_D_UNDEF |
| 2350 | 0ULL, // FRINT32X_ZPmZ_S_UNDEF |
| 2351 | 0ULL, // FRINT32Z_ZPmZ_D_UNDEF |
| 2352 | 0ULL, // FRINT32Z_ZPmZ_S_UNDEF |
| 2353 | 0ULL, // FRINT64X_ZPmZ_D_UNDEF |
| 2354 | 0ULL, // FRINT64X_ZPmZ_S_UNDEF |
| 2355 | 0ULL, // FRINT64Z_ZPmZ_D_UNDEF |
| 2356 | 0ULL, // FRINT64Z_ZPmZ_S_UNDEF |
| 2357 | 0ULL, // FRINTA_ZPmZ_D_UNDEF |
| 2358 | 0ULL, // FRINTA_ZPmZ_H_UNDEF |
| 2359 | 0ULL, // FRINTA_ZPmZ_S_UNDEF |
| 2360 | 0ULL, // FRINTI_ZPmZ_D_UNDEF |
| 2361 | 0ULL, // FRINTI_ZPmZ_H_UNDEF |
| 2362 | 0ULL, // FRINTI_ZPmZ_S_UNDEF |
| 2363 | 0ULL, // FRINTM_ZPmZ_D_UNDEF |
| 2364 | 0ULL, // FRINTM_ZPmZ_H_UNDEF |
| 2365 | 0ULL, // FRINTM_ZPmZ_S_UNDEF |
| 2366 | 0ULL, // FRINTN_ZPmZ_D_UNDEF |
| 2367 | 0ULL, // FRINTN_ZPmZ_H_UNDEF |
| 2368 | 0ULL, // FRINTN_ZPmZ_S_UNDEF |
| 2369 | 0ULL, // FRINTP_ZPmZ_D_UNDEF |
| 2370 | 0ULL, // FRINTP_ZPmZ_H_UNDEF |
| 2371 | 0ULL, // FRINTP_ZPmZ_S_UNDEF |
| 2372 | 0ULL, // FRINTX_ZPmZ_D_UNDEF |
| 2373 | 0ULL, // FRINTX_ZPmZ_H_UNDEF |
| 2374 | 0ULL, // FRINTX_ZPmZ_S_UNDEF |
| 2375 | 0ULL, // FRINTZ_ZPmZ_D_UNDEF |
| 2376 | 0ULL, // FRINTZ_ZPmZ_H_UNDEF |
| 2377 | 0ULL, // FRINTZ_ZPmZ_S_UNDEF |
| 2378 | 0ULL, // FSCALE_ZPZZ_D_UNDEF |
| 2379 | 0ULL, // FSCALE_ZPZZ_H_UNDEF |
| 2380 | 0ULL, // FSCALE_ZPZZ_S_UNDEF |
| 2381 | 0ULL, // FSQRT_ZPmZ_D_UNDEF |
| 2382 | 0ULL, // FSQRT_ZPmZ_H_UNDEF |
| 2383 | 0ULL, // FSQRT_ZPmZ_S_UNDEF |
| 2384 | 0ULL, // FSUBR_ZPZI_D_UNDEF |
| 2385 | 0ULL, // FSUBR_ZPZI_D_ZERO |
| 2386 | 0ULL, // FSUBR_ZPZI_H_UNDEF |
| 2387 | 0ULL, // FSUBR_ZPZI_H_ZERO |
| 2388 | 0ULL, // FSUBR_ZPZI_S_UNDEF |
| 2389 | 0ULL, // FSUBR_ZPZI_S_ZERO |
| 2390 | 0ULL, // FSUBR_ZPZZ_D_ZERO |
| 2391 | 0ULL, // FSUBR_ZPZZ_H_ZERO |
| 2392 | 0ULL, // FSUBR_ZPZZ_S_ZERO |
| 2393 | 0ULL, // FSUB_VG2_M2Z_D_PSEUDO |
| 2394 | 0ULL, // FSUB_VG2_M2Z_H_PSEUDO |
| 2395 | 0ULL, // FSUB_VG2_M2Z_S_PSEUDO |
| 2396 | 0ULL, // FSUB_VG4_M4Z_D_PSEUDO |
| 2397 | 0ULL, // FSUB_VG4_M4Z_H_PSEUDO |
| 2398 | 0ULL, // FSUB_VG4_M4Z_S_PSEUDO |
| 2399 | 0ULL, // FSUB_ZPZI_D_UNDEF |
| 2400 | 0ULL, // FSUB_ZPZI_D_ZERO |
| 2401 | 0ULL, // FSUB_ZPZI_H_UNDEF |
| 2402 | 0ULL, // FSUB_ZPZI_H_ZERO |
| 2403 | 0ULL, // FSUB_ZPZI_S_UNDEF |
| 2404 | 0ULL, // FSUB_ZPZI_S_ZERO |
| 2405 | 0ULL, // FSUB_ZPZZ_D_UNDEF |
| 2406 | 0ULL, // FSUB_ZPZZ_D_ZERO |
| 2407 | 0ULL, // FSUB_ZPZZ_H_UNDEF |
| 2408 | 0ULL, // FSUB_ZPZZ_H_ZERO |
| 2409 | 0ULL, // FSUB_ZPZZ_S_UNDEF |
| 2410 | 0ULL, // FSUB_ZPZZ_S_ZERO |
| 2411 | 0ULL, // FTMOPA_M2ZZZI_BtoH_PSEUDO |
| 2412 | 0ULL, // FTMOPA_M2ZZZI_BtoS_PSEUDO |
| 2413 | 0ULL, // FTMOPA_M2ZZZI_HtoH_PSEUDO |
| 2414 | 0ULL, // FTMOPA_M2ZZZI_HtoS_PSEUDO |
| 2415 | 0ULL, // FTMOPA_M2ZZZI_StoS_PSEUDO |
| 2416 | 0ULL, // FVDOTB_VG4_M2ZZI_BtoS_PSEUDO |
| 2417 | 0ULL, // FVDOTT_VG4_M2ZZI_BtoS_PSEUDO |
| 2418 | 0ULL, // FVDOT_VG2_M2ZZI_BtoH_PSEUDO |
| 2419 | 0ULL, // FVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 2420 | 0ULL, // G_AARCH64_PREFETCH |
| 2421 | 0ULL, // G_AARCH64_RANGE_PREFETCH |
| 2422 | 0ULL, // G_ADDHN |
| 2423 | 0ULL, // G_ADD_LOW |
| 2424 | 0ULL, // G_BSP |
| 2425 | 0ULL, // G_DUP |
| 2426 | 0ULL, // G_DUPLANE16 |
| 2427 | 0ULL, // G_DUPLANE32 |
| 2428 | 0ULL, // G_DUPLANE64 |
| 2429 | 0ULL, // G_DUPLANE8 |
| 2430 | 0ULL, // G_EXT |
| 2431 | 0ULL, // G_FCMEQ |
| 2432 | 0ULL, // G_FCMGE |
| 2433 | 0ULL, // G_FCMGT |
| 2434 | 0ULL, // G_FPTRUNC_ODD |
| 2435 | 0ULL, // G_PMULL |
| 2436 | 0ULL, // G_REV32 |
| 2437 | 0ULL, // G_REV64 |
| 2438 | 0ULL, // G_SADDLP |
| 2439 | 0ULL, // G_SADDLV |
| 2440 | 0ULL, // G_SDOT |
| 2441 | 0ULL, // G_SITOF |
| 2442 | 0ULL, // G_SLI |
| 2443 | 0ULL, // G_SMULL |
| 2444 | 0ULL, // G_SQSHLU_I |
| 2445 | 0ULL, // G_SRI |
| 2446 | 0ULL, // G_SRSHR_I |
| 2447 | 0ULL, // G_TRN1 |
| 2448 | 0ULL, // G_TRN2 |
| 2449 | 0ULL, // G_UADDLP |
| 2450 | 0ULL, // G_UADDLV |
| 2451 | 0ULL, // G_UDOT |
| 2452 | 0ULL, // G_UITOF |
| 2453 | 0ULL, // G_UMULL |
| 2454 | 0ULL, // G_URSHR_I |
| 2455 | 0ULL, // G_USDOT |
| 2456 | 0ULL, // G_UZP1 |
| 2457 | 0ULL, // G_UZP2 |
| 2458 | 0ULL, // G_VASHR |
| 2459 | 0ULL, // G_VLSHR |
| 2460 | 0ULL, // G_ZIP1 |
| 2461 | 0ULL, // G_ZIP2 |
| 2462 | 0ULL, // HOM_Epilog |
| 2463 | 0ULL, // HOM_Prolog |
| 2464 | 0ULL, // HWASAN_CHECK_MEMACCESS |
| 2465 | 0ULL, // HWASAN_CHECK_MEMACCESS_FIXEDSHADOW |
| 2466 | 0ULL, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| 2467 | 0ULL, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW |
| 2468 | 0ULL, // INSERT_MXIPZ_H_PSEUDO_B |
| 2469 | 0ULL, // INSERT_MXIPZ_H_PSEUDO_D |
| 2470 | 0ULL, // INSERT_MXIPZ_H_PSEUDO_H |
| 2471 | 0ULL, // INSERT_MXIPZ_H_PSEUDO_Q |
| 2472 | 0ULL, // INSERT_MXIPZ_H_PSEUDO_S |
| 2473 | 0ULL, // INSERT_MXIPZ_V_PSEUDO_B |
| 2474 | 0ULL, // INSERT_MXIPZ_V_PSEUDO_D |
| 2475 | 0ULL, // INSERT_MXIPZ_V_PSEUDO_H |
| 2476 | 0ULL, // INSERT_MXIPZ_V_PSEUDO_Q |
| 2477 | 0ULL, // INSERT_MXIPZ_V_PSEUDO_S |
| 2478 | 0ULL, // IRGstack |
| 2479 | 0ULL, // InOutZAUsePseudo |
| 2480 | 0ULL, // JumpTableDest16 |
| 2481 | 0ULL, // JumpTableDest32 |
| 2482 | 0ULL, // JumpTableDest8 |
| 2483 | 0ULL, // KCFI_CHECK |
| 2484 | 0ULL, // LD1B_2Z_IMM_PSEUDO |
| 2485 | 0ULL, // LD1B_2Z_PSEUDO |
| 2486 | 0ULL, // LD1B_4Z_IMM_PSEUDO |
| 2487 | 0ULL, // LD1B_4Z_PSEUDO |
| 2488 | 0ULL, // LD1D_2Z_IMM_PSEUDO |
| 2489 | 0ULL, // LD1D_2Z_PSEUDO |
| 2490 | 0ULL, // LD1D_4Z_IMM_PSEUDO |
| 2491 | 0ULL, // LD1D_4Z_PSEUDO |
| 2492 | 0ULL, // LD1H_2Z_IMM_PSEUDO |
| 2493 | 0ULL, // LD1H_2Z_PSEUDO |
| 2494 | 0ULL, // LD1H_4Z_IMM_PSEUDO |
| 2495 | 0ULL, // LD1H_4Z_PSEUDO |
| 2496 | 0ULL, // LD1W_2Z_IMM_PSEUDO |
| 2497 | 0ULL, // LD1W_2Z_PSEUDO |
| 2498 | 0ULL, // LD1W_4Z_IMM_PSEUDO |
| 2499 | 0ULL, // LD1W_4Z_PSEUDO |
| 2500 | 0ULL, // LD1_MXIPXX_H_PSEUDO_B |
| 2501 | 0ULL, // LD1_MXIPXX_H_PSEUDO_D |
| 2502 | 0ULL, // LD1_MXIPXX_H_PSEUDO_H |
| 2503 | 0ULL, // LD1_MXIPXX_H_PSEUDO_Q |
| 2504 | 0ULL, // LD1_MXIPXX_H_PSEUDO_S |
| 2505 | 0ULL, // LD1_MXIPXX_V_PSEUDO_B |
| 2506 | 0ULL, // LD1_MXIPXX_V_PSEUDO_D |
| 2507 | 0ULL, // LD1_MXIPXX_V_PSEUDO_H |
| 2508 | 0ULL, // LD1_MXIPXX_V_PSEUDO_Q |
| 2509 | 0ULL, // LD1_MXIPXX_V_PSEUDO_S |
| 2510 | 0ULL, // LDNT1B_2Z_IMM_PSEUDO |
| 2511 | 0ULL, // LDNT1B_2Z_PSEUDO |
| 2512 | 0ULL, // LDNT1B_4Z_IMM_PSEUDO |
| 2513 | 0ULL, // LDNT1B_4Z_PSEUDO |
| 2514 | 0ULL, // LDNT1D_2Z_IMM_PSEUDO |
| 2515 | 0ULL, // LDNT1D_2Z_PSEUDO |
| 2516 | 0ULL, // LDNT1D_4Z_IMM_PSEUDO |
| 2517 | 0ULL, // LDNT1D_4Z_PSEUDO |
| 2518 | 0ULL, // LDNT1H_2Z_IMM_PSEUDO |
| 2519 | 0ULL, // LDNT1H_2Z_PSEUDO |
| 2520 | 0ULL, // LDNT1H_4Z_IMM_PSEUDO |
| 2521 | 0ULL, // LDNT1H_4Z_PSEUDO |
| 2522 | 0ULL, // LDNT1W_2Z_IMM_PSEUDO |
| 2523 | 0ULL, // LDNT1W_2Z_PSEUDO |
| 2524 | 0ULL, // LDNT1W_4Z_IMM_PSEUDO |
| 2525 | 0ULL, // LDNT1W_4Z_PSEUDO |
| 2526 | 0ULL, // LDR_PPXI |
| 2527 | 0ULL, // LDR_TX_PSEUDO |
| 2528 | 0ULL, // LDR_ZA_PSEUDO |
| 2529 | 0ULL, // LDR_ZZXI |
| 2530 | 0ULL, // LDR_ZZXI_STRIDED_CONTIGUOUS |
| 2531 | 0ULL, // LDR_ZZZXI |
| 2532 | 0ULL, // LDR_ZZZZXI |
| 2533 | 0ULL, // LDR_ZZZZXI_STRIDED_CONTIGUOUS |
| 2534 | 0ULL, // LOADauthptrstatic |
| 2535 | 0ULL, // LOADgot |
| 2536 | 0ULL, // LOADgotAUTH |
| 2537 | 0ULL, // LOADgotPAC |
| 2538 | 0ULL, // LSL_ZPZI_B_UNDEF |
| 2539 | 0ULL, // LSL_ZPZI_B_ZERO |
| 2540 | 0ULL, // LSL_ZPZI_D_UNDEF |
| 2541 | 0ULL, // LSL_ZPZI_D_ZERO |
| 2542 | 0ULL, // LSL_ZPZI_H_UNDEF |
| 2543 | 0ULL, // LSL_ZPZI_H_ZERO |
| 2544 | 0ULL, // LSL_ZPZI_S_UNDEF |
| 2545 | 0ULL, // LSL_ZPZI_S_ZERO |
| 2546 | 0ULL, // LSL_ZPZZ_B_UNDEF |
| 2547 | 0ULL, // LSL_ZPZZ_B_ZERO |
| 2548 | 0ULL, // LSL_ZPZZ_D_UNDEF |
| 2549 | 0ULL, // LSL_ZPZZ_D_ZERO |
| 2550 | 0ULL, // LSL_ZPZZ_H_UNDEF |
| 2551 | 0ULL, // LSL_ZPZZ_H_ZERO |
| 2552 | 0ULL, // LSL_ZPZZ_S_UNDEF |
| 2553 | 0ULL, // LSL_ZPZZ_S_ZERO |
| 2554 | 0ULL, // LSR_ZPZI_B_UNDEF |
| 2555 | 0ULL, // LSR_ZPZI_B_ZERO |
| 2556 | 0ULL, // LSR_ZPZI_D_UNDEF |
| 2557 | 0ULL, // LSR_ZPZI_D_ZERO |
| 2558 | 0ULL, // LSR_ZPZI_H_UNDEF |
| 2559 | 0ULL, // LSR_ZPZI_H_ZERO |
| 2560 | 0ULL, // LSR_ZPZI_S_UNDEF |
| 2561 | 0ULL, // LSR_ZPZI_S_ZERO |
| 2562 | 0ULL, // LSR_ZPZZ_B_UNDEF |
| 2563 | 0ULL, // LSR_ZPZZ_B_ZERO |
| 2564 | 0ULL, // LSR_ZPZZ_D_UNDEF |
| 2565 | 0ULL, // LSR_ZPZZ_D_ZERO |
| 2566 | 0ULL, // LSR_ZPZZ_H_UNDEF |
| 2567 | 0ULL, // LSR_ZPZZ_H_ZERO |
| 2568 | 0ULL, // LSR_ZPZZ_S_UNDEF |
| 2569 | 0ULL, // LSR_ZPZZ_S_ZERO |
| 2570 | 0ULL, // MLA_ZPZZZ_B_UNDEF |
| 2571 | 0ULL, // MLA_ZPZZZ_D_UNDEF |
| 2572 | 0ULL, // MLA_ZPZZZ_H_UNDEF |
| 2573 | 0ULL, // MLA_ZPZZZ_S_UNDEF |
| 2574 | 0ULL, // MLS_ZPZZZ_B_UNDEF |
| 2575 | 0ULL, // MLS_ZPZZZ_D_UNDEF |
| 2576 | 0ULL, // MLS_ZPZZZ_H_UNDEF |
| 2577 | 0ULL, // MLS_ZPZZZ_S_UNDEF |
| 2578 | 0ULL, // MOPSMemoryCopyPseudo |
| 2579 | 0ULL, // MOPSMemoryMovePseudo |
| 2580 | 0ULL, // MOPSMemorySetPseudo |
| 2581 | 0ULL, // MOPSMemorySetTaggingPseudo |
| 2582 | 0ULL, // MOVAZ_2ZMI_H_B_PSEUDO |
| 2583 | 0ULL, // MOVAZ_2ZMI_H_D_PSEUDO |
| 2584 | 0ULL, // MOVAZ_2ZMI_H_H_PSEUDO |
| 2585 | 0ULL, // MOVAZ_2ZMI_H_S_PSEUDO |
| 2586 | 0ULL, // MOVAZ_2ZMI_V_B_PSEUDO |
| 2587 | 0ULL, // MOVAZ_2ZMI_V_D_PSEUDO |
| 2588 | 0ULL, // MOVAZ_2ZMI_V_H_PSEUDO |
| 2589 | 0ULL, // MOVAZ_2ZMI_V_S_PSEUDO |
| 2590 | 0ULL, // MOVAZ_4ZMI_H_B_PSEUDO |
| 2591 | 0ULL, // MOVAZ_4ZMI_H_D_PSEUDO |
| 2592 | 0ULL, // MOVAZ_4ZMI_H_H_PSEUDO |
| 2593 | 0ULL, // MOVAZ_4ZMI_H_S_PSEUDO |
| 2594 | 0ULL, // MOVAZ_4ZMI_V_B_PSEUDO |
| 2595 | 0ULL, // MOVAZ_4ZMI_V_D_PSEUDO |
| 2596 | 0ULL, // MOVAZ_4ZMI_V_H_PSEUDO |
| 2597 | 0ULL, // MOVAZ_4ZMI_V_S_PSEUDO |
| 2598 | 0ULL, // MOVAZ_VG2_2ZMXI_PSEUDO |
| 2599 | 0ULL, // MOVAZ_VG4_4ZMXI_PSEUDO |
| 2600 | 0ULL, // MOVAZ_ZMI_H_B_PSEUDO |
| 2601 | 0ULL, // MOVAZ_ZMI_H_D_PSEUDO |
| 2602 | 0ULL, // MOVAZ_ZMI_H_H_PSEUDO |
| 2603 | 0ULL, // MOVAZ_ZMI_H_Q_PSEUDO |
| 2604 | 0ULL, // MOVAZ_ZMI_H_S_PSEUDO |
| 2605 | 0ULL, // MOVAZ_ZMI_V_B_PSEUDO |
| 2606 | 0ULL, // MOVAZ_ZMI_V_D_PSEUDO |
| 2607 | 0ULL, // MOVAZ_ZMI_V_H_PSEUDO |
| 2608 | 0ULL, // MOVAZ_ZMI_V_Q_PSEUDO |
| 2609 | 0ULL, // MOVAZ_ZMI_V_S_PSEUDO |
| 2610 | 0ULL, // MOVA_MXI2Z_H_B_PSEUDO |
| 2611 | 0ULL, // MOVA_MXI2Z_H_D_PSEUDO |
| 2612 | 0ULL, // MOVA_MXI2Z_H_H_PSEUDO |
| 2613 | 0ULL, // MOVA_MXI2Z_H_S_PSEUDO |
| 2614 | 0ULL, // MOVA_MXI2Z_V_B_PSEUDO |
| 2615 | 0ULL, // MOVA_MXI2Z_V_D_PSEUDO |
| 2616 | 0ULL, // MOVA_MXI2Z_V_H_PSEUDO |
| 2617 | 0ULL, // MOVA_MXI2Z_V_S_PSEUDO |
| 2618 | 0ULL, // MOVA_MXI4Z_H_B_PSEUDO |
| 2619 | 0ULL, // MOVA_MXI4Z_H_D_PSEUDO |
| 2620 | 0ULL, // MOVA_MXI4Z_H_H_PSEUDO |
| 2621 | 0ULL, // MOVA_MXI4Z_H_S_PSEUDO |
| 2622 | 0ULL, // MOVA_MXI4Z_V_B_PSEUDO |
| 2623 | 0ULL, // MOVA_MXI4Z_V_D_PSEUDO |
| 2624 | 0ULL, // MOVA_MXI4Z_V_H_PSEUDO |
| 2625 | 0ULL, // MOVA_MXI4Z_V_S_PSEUDO |
| 2626 | 0ULL, // MOVA_VG2_MXI2Z_PSEUDO |
| 2627 | 0ULL, // MOVA_VG4_MXI4Z_PSEUDO |
| 2628 | 0ULL, // MOVMCSym |
| 2629 | 0ULL, // MOVT_TIZ_PSEUDO |
| 2630 | 0ULL, // MOVaddr |
| 2631 | 0ULL, // MOVaddrBA |
| 2632 | 0ULL, // MOVaddrCP |
| 2633 | 0ULL, // MOVaddrEXT |
| 2634 | 0ULL, // MOVaddrJT |
| 2635 | 0ULL, // MOVaddrPAC |
| 2636 | 0ULL, // MOVaddrTLS |
| 2637 | 0ULL, // MOVbaseTLS |
| 2638 | 0ULL, // MOVi32imm |
| 2639 | 0ULL, // MOVi64imm |
| 2640 | 0ULL, // MRS_FPCR |
| 2641 | 0ULL, // MRS_FPSR |
| 2642 | 0ULL, // MSR_FPCR |
| 2643 | 0ULL, // MSR_FPMR |
| 2644 | 0ULL, // MSR_FPSR |
| 2645 | 0ULL, // MSRpstatePseudo |
| 2646 | 0ULL, // MUL_ZI_B_PSEUDO |
| 2647 | 0ULL, // MUL_ZI_D_PSEUDO |
| 2648 | 0ULL, // MUL_ZI_H_PSEUDO |
| 2649 | 0ULL, // MUL_ZI_S_PSEUDO |
| 2650 | 0ULL, // MUL_ZPZZ_B_UNDEF |
| 2651 | 0ULL, // MUL_ZPZZ_D_UNDEF |
| 2652 | 0ULL, // MUL_ZPZZ_H_UNDEF |
| 2653 | 0ULL, // MUL_ZPZZ_S_UNDEF |
| 2654 | 0ULL, // NAND_ZZZ |
| 2655 | 0ULL, // NEG_ZPmZ_B_UNDEF |
| 2656 | 0ULL, // NEG_ZPmZ_D_UNDEF |
| 2657 | 0ULL, // NEG_ZPmZ_H_UNDEF |
| 2658 | 0ULL, // NEG_ZPmZ_S_UNDEF |
| 2659 | 0ULL, // NOR_ZZZ |
| 2660 | 0ULL, // NOT_ZPmZ_B_UNDEF |
| 2661 | 0ULL, // NOT_ZPmZ_D_UNDEF |
| 2662 | 0ULL, // NOT_ZPmZ_H_UNDEF |
| 2663 | 0ULL, // NOT_ZPmZ_S_UNDEF |
| 2664 | 0ULL, // ORNWrr |
| 2665 | 0ULL, // ORNXrr |
| 2666 | 0ULL, // ORRWrr |
| 2667 | 0ULL, // ORRXrr |
| 2668 | 0ULL, // ORR_ZI_PSEUDO |
| 2669 | 0ULL, // ORR_ZPZZ_B_ZERO |
| 2670 | 0ULL, // ORR_ZPZZ_D_ZERO |
| 2671 | 0ULL, // ORR_ZPZZ_H_ZERO |
| 2672 | 0ULL, // ORR_ZPZZ_S_ZERO |
| 2673 | 0ULL, // PAC |
| 2674 | 0ULL, // PAUTH_EPILOGUE |
| 2675 | 0ULL, // PAUTH_PROLOGUE |
| 2676 | 0ULL, // PROBED_STACKALLOC |
| 2677 | 0ULL, // PROBED_STACKALLOC_DYN |
| 2678 | 0ULL, // PROBED_STACKALLOC_VAR |
| 2679 | 0ULL, // PTEST_PP_ANY |
| 2680 | 0ULL, // PTEST_PP_FIRST |
| 2681 | 0ULL, // READ_REGISTER_FPR64 |
| 2682 | 0ULL, // READ_REGISTER_GPR64 |
| 2683 | 0ULL, // RET_ReallyLR |
| 2684 | 0ULL, // RequiresZASavePseudo |
| 2685 | 0ULL, // RequiresZT0SavePseudo |
| 2686 | 0ULL, // RestoreZAPseudo |
| 2687 | 0ULL, // SABD_ZPZZ_B_UNDEF |
| 2688 | 0ULL, // SABD_ZPZZ_D_UNDEF |
| 2689 | 0ULL, // SABD_ZPZZ_H_UNDEF |
| 2690 | 0ULL, // SABD_ZPZZ_S_UNDEF |
| 2691 | 0ULL, // SCVTF_ZPmZ_DtoD_UNDEF |
| 2692 | 0ULL, // SCVTF_ZPmZ_DtoH_UNDEF |
| 2693 | 0ULL, // SCVTF_ZPmZ_DtoS_UNDEF |
| 2694 | 0ULL, // SCVTF_ZPmZ_HtoH_UNDEF |
| 2695 | 0ULL, // SCVTF_ZPmZ_StoD_UNDEF |
| 2696 | 0ULL, // SCVTF_ZPmZ_StoH_UNDEF |
| 2697 | 0ULL, // SCVTF_ZPmZ_StoS_UNDEF |
| 2698 | 0ULL, // SDIV_ZPZZ_D_UNDEF |
| 2699 | 0ULL, // SDIV_ZPZZ_S_UNDEF |
| 2700 | 0ULL, // SDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 2701 | 0ULL, // SDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 2702 | 0ULL, // SDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 2703 | 0ULL, // SDOT_VG2_M2ZZI_BToS_PSEUDO |
| 2704 | 0ULL, // SDOT_VG2_M2ZZI_HToS_PSEUDO |
| 2705 | 0ULL, // SDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 2706 | 0ULL, // SDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 2707 | 0ULL, // SDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 2708 | 0ULL, // SDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 2709 | 0ULL, // SDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 2710 | 0ULL, // SDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 2711 | 0ULL, // SDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 2712 | 0ULL, // SDOT_VG4_M4ZZI_BToS_PSEUDO |
| 2713 | 0ULL, // SDOT_VG4_M4ZZI_HToS_PSEUDO |
| 2714 | 0ULL, // SDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 2715 | 0ULL, // SDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 2716 | 0ULL, // SDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 2717 | 0ULL, // SDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 2718 | 0ULL, // SEH_AddFP |
| 2719 | 0ULL, // SEH_AllocZ |
| 2720 | 0ULL, // SEH_EpilogEnd |
| 2721 | 0ULL, // SEH_EpilogStart |
| 2722 | 0ULL, // SEH_Nop |
| 2723 | 0ULL, // SEH_PACSignLR |
| 2724 | 0ULL, // SEH_PrologEnd |
| 2725 | 0ULL, // SEH_SaveAnyRegI |
| 2726 | 0ULL, // SEH_SaveAnyRegIP |
| 2727 | 0ULL, // SEH_SaveAnyRegQP |
| 2728 | 0ULL, // SEH_SaveAnyRegQPX |
| 2729 | 0ULL, // SEH_SaveFPLR |
| 2730 | 0ULL, // SEH_SaveFPLR_X |
| 2731 | 0ULL, // SEH_SaveFReg |
| 2732 | 0ULL, // SEH_SaveFRegP |
| 2733 | 0ULL, // SEH_SaveFRegP_X |
| 2734 | 0ULL, // SEH_SaveFReg_X |
| 2735 | 0ULL, // SEH_SavePReg |
| 2736 | 0ULL, // SEH_SaveReg |
| 2737 | 0ULL, // SEH_SaveRegP |
| 2738 | 0ULL, // SEH_SaveRegP_X |
| 2739 | 0ULL, // SEH_SaveReg_X |
| 2740 | 0ULL, // SEH_SaveZReg |
| 2741 | 0ULL, // SEH_SetFP |
| 2742 | 0ULL, // SEH_StackAlloc |
| 2743 | 0ULL, // SHSUB_ZPZZ_B_UNDEF |
| 2744 | 0ULL, // SHSUB_ZPZZ_D_UNDEF |
| 2745 | 0ULL, // SHSUB_ZPZZ_H_UNDEF |
| 2746 | 0ULL, // SHSUB_ZPZZ_S_UNDEF |
| 2747 | 0ULL, // SMAX_ZI_B_PSEUDO |
| 2748 | 0ULL, // SMAX_ZI_D_PSEUDO |
| 2749 | 0ULL, // SMAX_ZI_H_PSEUDO |
| 2750 | 0ULL, // SMAX_ZI_S_PSEUDO |
| 2751 | 0ULL, // SMAX_ZPZZ_B_UNDEF |
| 2752 | 0ULL, // SMAX_ZPZZ_D_UNDEF |
| 2753 | 0ULL, // SMAX_ZPZZ_H_UNDEF |
| 2754 | 0ULL, // SMAX_ZPZZ_S_UNDEF |
| 2755 | 0ULL, // SMEStateAllocPseudo |
| 2756 | 0ULL, // SMIN_ZI_B_PSEUDO |
| 2757 | 0ULL, // SMIN_ZI_D_PSEUDO |
| 2758 | 0ULL, // SMIN_ZI_H_PSEUDO |
| 2759 | 0ULL, // SMIN_ZI_S_PSEUDO |
| 2760 | 0ULL, // SMIN_ZPZZ_B_UNDEF |
| 2761 | 0ULL, // SMIN_ZPZZ_D_UNDEF |
| 2762 | 0ULL, // SMIN_ZPZZ_H_UNDEF |
| 2763 | 0ULL, // SMIN_ZPZZ_S_UNDEF |
| 2764 | 0ULL, // SMLALL_MZZI_BtoS_PSEUDO |
| 2765 | 0ULL, // SMLALL_MZZI_HtoD_PSEUDO |
| 2766 | 0ULL, // SMLALL_MZZ_BtoS_PSEUDO |
| 2767 | 0ULL, // SMLALL_MZZ_HtoD_PSEUDO |
| 2768 | 0ULL, // SMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 2769 | 0ULL, // SMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 2770 | 0ULL, // SMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 2771 | 0ULL, // SMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 2772 | 0ULL, // SMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 2773 | 0ULL, // SMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 2774 | 0ULL, // SMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 2775 | 0ULL, // SMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 2776 | 0ULL, // SMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 2777 | 0ULL, // SMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 2778 | 0ULL, // SMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 2779 | 0ULL, // SMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 2780 | 0ULL, // SMLAL_MZZI_HtoS_PSEUDO |
| 2781 | 0ULL, // SMLAL_MZZ_HtoS_PSEUDO |
| 2782 | 0ULL, // SMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2783 | 0ULL, // SMLAL_VG2_M2ZZI_S_PSEUDO |
| 2784 | 0ULL, // SMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 2785 | 0ULL, // SMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2786 | 0ULL, // SMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 2787 | 0ULL, // SMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 2788 | 0ULL, // SMLSLL_MZZI_BtoS_PSEUDO |
| 2789 | 0ULL, // SMLSLL_MZZI_HtoD_PSEUDO |
| 2790 | 0ULL, // SMLSLL_MZZ_BtoS_PSEUDO |
| 2791 | 0ULL, // SMLSLL_MZZ_HtoD_PSEUDO |
| 2792 | 0ULL, // SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 2793 | 0ULL, // SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 2794 | 0ULL, // SMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 2795 | 0ULL, // SMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 2796 | 0ULL, // SMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 2797 | 0ULL, // SMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 2798 | 0ULL, // SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 2799 | 0ULL, // SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 2800 | 0ULL, // SMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 2801 | 0ULL, // SMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 2802 | 0ULL, // SMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 2803 | 0ULL, // SMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 2804 | 0ULL, // SMLSL_MZZI_HtoS_PSEUDO |
| 2805 | 0ULL, // SMLSL_MZZ_HtoS_PSEUDO |
| 2806 | 0ULL, // SMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 2807 | 0ULL, // SMLSL_VG2_M2ZZI_S_PSEUDO |
| 2808 | 0ULL, // SMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 2809 | 0ULL, // SMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 2810 | 0ULL, // SMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 2811 | 0ULL, // SMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 2812 | 0ULL, // SMOP4A_M2Z2Z_BToS_PSEUDO |
| 2813 | 0ULL, // SMOP4A_M2Z2Z_HToS_PSEUDO |
| 2814 | 0ULL, // SMOP4A_M2Z2Z_HtoD_PSEUDO |
| 2815 | 0ULL, // SMOP4A_M2ZZ_BToS_PSEUDO |
| 2816 | 0ULL, // SMOP4A_M2ZZ_HToS_PSEUDO |
| 2817 | 0ULL, // SMOP4A_M2ZZ_HtoD_PSEUDO |
| 2818 | 0ULL, // SMOP4A_MZ2Z_BToS_PSEUDO |
| 2819 | 0ULL, // SMOP4A_MZ2Z_HToS_PSEUDO |
| 2820 | 0ULL, // SMOP4A_MZ2Z_HtoD_PSEUDO |
| 2821 | 0ULL, // SMOP4A_MZZ_BToS_PSEUDO |
| 2822 | 0ULL, // SMOP4A_MZZ_HToS_PSEUDO |
| 2823 | 0ULL, // SMOP4A_MZZ_HtoD_PSEUDO |
| 2824 | 0ULL, // SMOP4S_M2Z2Z_BToS_PSEUDO |
| 2825 | 0ULL, // SMOP4S_M2Z2Z_HToS_PSEUDO |
| 2826 | 0ULL, // SMOP4S_M2Z2Z_HtoD_PSEUDO |
| 2827 | 0ULL, // SMOP4S_M2ZZ_BToS_PSEUDO |
| 2828 | 0ULL, // SMOP4S_M2ZZ_HToS_PSEUDO |
| 2829 | 0ULL, // SMOP4S_M2ZZ_HtoD_PSEUDO |
| 2830 | 0ULL, // SMOP4S_MZ2Z_BToS_PSEUDO |
| 2831 | 0ULL, // SMOP4S_MZ2Z_HToS_PSEUDO |
| 2832 | 0ULL, // SMOP4S_MZ2Z_HtoD_PSEUDO |
| 2833 | 0ULL, // SMOP4S_MZZ_BToS_PSEUDO |
| 2834 | 0ULL, // SMOP4S_MZZ_HToS_PSEUDO |
| 2835 | 0ULL, // SMOP4S_MZZ_HtoD_PSEUDO |
| 2836 | 0ULL, // SMOPA_MPPZZ_D_PSEUDO |
| 2837 | 0ULL, // SMOPA_MPPZZ_HtoS_PSEUDO |
| 2838 | 0ULL, // SMOPA_MPPZZ_S_PSEUDO |
| 2839 | 0ULL, // SMOPS_MPPZZ_D_PSEUDO |
| 2840 | 0ULL, // SMOPS_MPPZZ_HtoS_PSEUDO |
| 2841 | 0ULL, // SMOPS_MPPZZ_S_PSEUDO |
| 2842 | 0ULL, // SMULH_ZPZZ_B_UNDEF |
| 2843 | 0ULL, // SMULH_ZPZZ_D_UNDEF |
| 2844 | 0ULL, // SMULH_ZPZZ_H_UNDEF |
| 2845 | 0ULL, // SMULH_ZPZZ_S_UNDEF |
| 2846 | 0ULL, // SPACE |
| 2847 | 0ULL, // SQABS_ZPmZ_B_UNDEF |
| 2848 | 0ULL, // SQABS_ZPmZ_D_UNDEF |
| 2849 | 0ULL, // SQABS_ZPmZ_H_UNDEF |
| 2850 | 0ULL, // SQABS_ZPmZ_S_UNDEF |
| 2851 | 0ULL, // SQADD_ZI_B_PSEUDO |
| 2852 | 0ULL, // SQADD_ZI_D_PSEUDO |
| 2853 | 0ULL, // SQADD_ZI_H_PSEUDO |
| 2854 | 0ULL, // SQADD_ZI_S_PSEUDO |
| 2855 | 0ULL, // SQNEG_ZPmZ_B_UNDEF |
| 2856 | 0ULL, // SQNEG_ZPmZ_D_UNDEF |
| 2857 | 0ULL, // SQNEG_ZPmZ_H_UNDEF |
| 2858 | 0ULL, // SQNEG_ZPmZ_S_UNDEF |
| 2859 | 0ULL, // SQRSHL_ZPZZ_B_UNDEF |
| 2860 | 0ULL, // SQRSHL_ZPZZ_D_UNDEF |
| 2861 | 0ULL, // SQRSHL_ZPZZ_H_UNDEF |
| 2862 | 0ULL, // SQRSHL_ZPZZ_S_UNDEF |
| 2863 | 0ULL, // SQSHLU_ZPZI_B_ZERO |
| 2864 | 0ULL, // SQSHLU_ZPZI_D_ZERO |
| 2865 | 0ULL, // SQSHLU_ZPZI_H_ZERO |
| 2866 | 0ULL, // SQSHLU_ZPZI_S_ZERO |
| 2867 | 0ULL, // SQSHL_ZPZI_B_UNDEF |
| 2868 | 0ULL, // SQSHL_ZPZI_B_ZERO |
| 2869 | 0ULL, // SQSHL_ZPZI_D_UNDEF |
| 2870 | 0ULL, // SQSHL_ZPZI_D_ZERO |
| 2871 | 0ULL, // SQSHL_ZPZI_H_UNDEF |
| 2872 | 0ULL, // SQSHL_ZPZI_H_ZERO |
| 2873 | 0ULL, // SQSHL_ZPZI_S_UNDEF |
| 2874 | 0ULL, // SQSHL_ZPZI_S_ZERO |
| 2875 | 0ULL, // SQSHL_ZPZZ_B_UNDEF |
| 2876 | 0ULL, // SQSHL_ZPZZ_D_UNDEF |
| 2877 | 0ULL, // SQSHL_ZPZZ_H_UNDEF |
| 2878 | 0ULL, // SQSHL_ZPZZ_S_UNDEF |
| 2879 | 0ULL, // SQSUB_ZI_B_PSEUDO |
| 2880 | 0ULL, // SQSUB_ZI_D_PSEUDO |
| 2881 | 0ULL, // SQSUB_ZI_H_PSEUDO |
| 2882 | 0ULL, // SQSUB_ZI_S_PSEUDO |
| 2883 | 0ULL, // SRSHL_ZPZZ_B_UNDEF |
| 2884 | 0ULL, // SRSHL_ZPZZ_D_UNDEF |
| 2885 | 0ULL, // SRSHL_ZPZZ_H_UNDEF |
| 2886 | 0ULL, // SRSHL_ZPZZ_S_UNDEF |
| 2887 | 0ULL, // SRSHR_ZPZI_B_ZERO |
| 2888 | 0ULL, // SRSHR_ZPZI_D_ZERO |
| 2889 | 0ULL, // SRSHR_ZPZI_H_ZERO |
| 2890 | 0ULL, // SRSHR_ZPZI_S_ZERO |
| 2891 | 0ULL, // ST1B_2Z_IMM_PSEUDO |
| 2892 | 0ULL, // ST1B_4Z_IMM_PSEUDO |
| 2893 | 0ULL, // ST1D_2Z_IMM_PSEUDO |
| 2894 | 0ULL, // ST1D_4Z_IMM_PSEUDO |
| 2895 | 0ULL, // ST1H_2Z_IMM_PSEUDO |
| 2896 | 0ULL, // ST1H_4Z_IMM_PSEUDO |
| 2897 | 0ULL, // ST1W_2Z_IMM_PSEUDO |
| 2898 | 0ULL, // ST1W_4Z_IMM_PSEUDO |
| 2899 | 0ULL, // STACK_GUARD_UNMIX |
| 2900 | 0ULL, // STGloop |
| 2901 | 0ULL, // STGloop_wback |
| 2902 | 0ULL, // STMOPA_M2ZZZI_BtoS_PSEUDO |
| 2903 | 0ULL, // STMOPA_M2ZZZI_HtoS_PSEUDO |
| 2904 | 0ULL, // STNT1B_2Z_IMM_PSEUDO |
| 2905 | 0ULL, // STNT1B_4Z_IMM_PSEUDO |
| 2906 | 0ULL, // STNT1D_2Z_IMM_PSEUDO |
| 2907 | 0ULL, // STNT1D_4Z_IMM_PSEUDO |
| 2908 | 0ULL, // STNT1H_2Z_IMM_PSEUDO |
| 2909 | 0ULL, // STNT1H_4Z_IMM_PSEUDO |
| 2910 | 0ULL, // STNT1W_2Z_IMM_PSEUDO |
| 2911 | 0ULL, // STNT1W_4Z_IMM_PSEUDO |
| 2912 | 0ULL, // STR_PPXI |
| 2913 | 0ULL, // STR_TX_PSEUDO |
| 2914 | 0ULL, // STR_ZZXI |
| 2915 | 0ULL, // STR_ZZXI_STRIDED_CONTIGUOUS |
| 2916 | 0ULL, // STR_ZZZXI |
| 2917 | 0ULL, // STR_ZZZZXI |
| 2918 | 0ULL, // STR_ZZZZXI_STRIDED_CONTIGUOUS |
| 2919 | 0ULL, // STZGloop |
| 2920 | 0ULL, // STZGloop_wback |
| 2921 | 0ULL, // SUBR_ZI_B_PSEUDO |
| 2922 | 0ULL, // SUBR_ZI_D_PSEUDO |
| 2923 | 0ULL, // SUBR_ZI_H_PSEUDO |
| 2924 | 0ULL, // SUBR_ZI_S_PSEUDO |
| 2925 | 0ULL, // SUBR_ZPZZ_B_ZERO |
| 2926 | 0ULL, // SUBR_ZPZZ_D_ZERO |
| 2927 | 0ULL, // SUBR_ZPZZ_H_ZERO |
| 2928 | 0ULL, // SUBR_ZPZZ_S_ZERO |
| 2929 | 0ULL, // SUBSWrr |
| 2930 | 0ULL, // SUBSXrr |
| 2931 | 0ULL, // SUBWrr |
| 2932 | 0ULL, // SUBXrr |
| 2933 | 0ULL, // SUB_VG2_M2Z2Z_D_PSEUDO |
| 2934 | 0ULL, // SUB_VG2_M2Z2Z_S_PSEUDO |
| 2935 | 0ULL, // SUB_VG2_M2ZZ_D_PSEUDO |
| 2936 | 0ULL, // SUB_VG2_M2ZZ_S_PSEUDO |
| 2937 | 0ULL, // SUB_VG2_M2Z_D_PSEUDO |
| 2938 | 0ULL, // SUB_VG2_M2Z_S_PSEUDO |
| 2939 | 0ULL, // SUB_VG4_M4Z4Z_D_PSEUDO |
| 2940 | 0ULL, // SUB_VG4_M4Z4Z_S_PSEUDO |
| 2941 | 0ULL, // SUB_VG4_M4ZZ_D_PSEUDO |
| 2942 | 0ULL, // SUB_VG4_M4ZZ_S_PSEUDO |
| 2943 | 0ULL, // SUB_VG4_M4Z_D_PSEUDO |
| 2944 | 0ULL, // SUB_VG4_M4Z_S_PSEUDO |
| 2945 | 0ULL, // SUB_ZI_B_PSEUDO |
| 2946 | 0ULL, // SUB_ZI_D_PSEUDO |
| 2947 | 0ULL, // SUB_ZI_H_PSEUDO |
| 2948 | 0ULL, // SUB_ZI_S_PSEUDO |
| 2949 | 0ULL, // SUB_ZPZZ_B_ZERO |
| 2950 | 0ULL, // SUB_ZPZZ_D_ZERO |
| 2951 | 0ULL, // SUB_ZPZZ_H_ZERO |
| 2952 | 0ULL, // SUB_ZPZZ_S_ZERO |
| 2953 | 0ULL, // SUDOT_VG2_M2ZZI_BToS_PSEUDO |
| 2954 | 0ULL, // SUDOT_VG2_M2ZZ_BToS_PSEUDO |
| 2955 | 0ULL, // SUDOT_VG4_M4ZZI_BToS_PSEUDO |
| 2956 | 0ULL, // SUDOT_VG4_M4ZZ_BToS_PSEUDO |
| 2957 | 0ULL, // SUMLALL_MZZI_BtoS_PSEUDO |
| 2958 | 0ULL, // SUMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 2959 | 0ULL, // SUMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 2960 | 0ULL, // SUMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 2961 | 0ULL, // SUMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 2962 | 0ULL, // SUMOP4A_M2Z2Z_BToS_PSEUDO |
| 2963 | 0ULL, // SUMOP4A_M2Z2Z_HtoD_PSEUDO |
| 2964 | 0ULL, // SUMOP4A_M2ZZ_BToS_PSEUDO |
| 2965 | 0ULL, // SUMOP4A_M2ZZ_HtoD_PSEUDO |
| 2966 | 0ULL, // SUMOP4A_MZ2Z_BToS_PSEUDO |
| 2967 | 0ULL, // SUMOP4A_MZ2Z_HtoD_PSEUDO |
| 2968 | 0ULL, // SUMOP4A_MZZ_BToS_PSEUDO |
| 2969 | 0ULL, // SUMOP4A_MZZ_HtoD_PSEUDO |
| 2970 | 0ULL, // SUMOP4S_M2Z2Z_BToS_PSEUDO |
| 2971 | 0ULL, // SUMOP4S_M2Z2Z_HtoD_PSEUDO |
| 2972 | 0ULL, // SUMOP4S_M2ZZ_BToS_PSEUDO |
| 2973 | 0ULL, // SUMOP4S_M2ZZ_HtoD_PSEUDO |
| 2974 | 0ULL, // SUMOP4S_MZ2Z_BToS_PSEUDO |
| 2975 | 0ULL, // SUMOP4S_MZ2Z_HtoD_PSEUDO |
| 2976 | 0ULL, // SUMOP4S_MZZ_BToS_PSEUDO |
| 2977 | 0ULL, // SUMOP4S_MZZ_HtoD_PSEUDO |
| 2978 | 0ULL, // SUMOPA_MPPZZ_D_PSEUDO |
| 2979 | 0ULL, // SUMOPA_MPPZZ_S_PSEUDO |
| 2980 | 0ULL, // SUMOPS_MPPZZ_D_PSEUDO |
| 2981 | 0ULL, // SUMOPS_MPPZZ_S_PSEUDO |
| 2982 | 0ULL, // SUTMOPA_M2ZZZI_BtoS_PSEUDO |
| 2983 | 0ULL, // SUVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 2984 | 0ULL, // SVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 2985 | 0ULL, // SVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 2986 | 0ULL, // SVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 2987 | 0ULL, // SXTB_ZPmZ_D_UNDEF |
| 2988 | 0ULL, // SXTB_ZPmZ_H_UNDEF |
| 2989 | 0ULL, // SXTB_ZPmZ_S_UNDEF |
| 2990 | 0ULL, // SXTH_ZPmZ_D_UNDEF |
| 2991 | 0ULL, // SXTH_ZPmZ_S_UNDEF |
| 2992 | 0ULL, // SXTW_ZPmZ_D_UNDEF |
| 2993 | 0ULL, // SpeculationBarrierISBDSBEndBB |
| 2994 | 0ULL, // SpeculationBarrierSBEndBB |
| 2995 | 0ULL, // SpeculationSafeValueW |
| 2996 | 0ULL, // SpeculationSafeValueX |
| 2997 | 0ULL, // StoreSwiftAsyncContext |
| 2998 | 0ULL, // TAGPstack |
| 2999 | 0ULL, // TCRETURNdi |
| 3000 | 0ULL, // TCRETURNri |
| 3001 | 0ULL, // TCRETURNriALL |
| 3002 | 0ULL, // TCRETURNrinotx16 |
| 3003 | 0ULL, // TCRETURNrix16x17 |
| 3004 | 0ULL, // TCRETURNrix17 |
| 3005 | 26144ULL, // TLSAUTHDESCCALL |
| 3006 | 26162ULL, // TLSDESCCALL |
| 3007 | 0ULL, // TLSDESC_AUTH_CALLSEQ |
| 3008 | 0ULL, // TLSDESC_CALLSEQ |
| 3009 | 0ULL, // UABD_ZPZZ_B_UNDEF |
| 3010 | 0ULL, // UABD_ZPZZ_D_UNDEF |
| 3011 | 0ULL, // UABD_ZPZZ_H_UNDEF |
| 3012 | 0ULL, // UABD_ZPZZ_S_UNDEF |
| 3013 | 0ULL, // UCVTF_ZPmZ_DtoD_UNDEF |
| 3014 | 0ULL, // UCVTF_ZPmZ_DtoH_UNDEF |
| 3015 | 0ULL, // UCVTF_ZPmZ_DtoS_UNDEF |
| 3016 | 0ULL, // UCVTF_ZPmZ_HtoH_UNDEF |
| 3017 | 0ULL, // UCVTF_ZPmZ_StoD_UNDEF |
| 3018 | 0ULL, // UCVTF_ZPmZ_StoH_UNDEF |
| 3019 | 0ULL, // UCVTF_ZPmZ_StoS_UNDEF |
| 3020 | 0ULL, // UDIV_ZPZZ_D_UNDEF |
| 3021 | 0ULL, // UDIV_ZPZZ_S_UNDEF |
| 3022 | 0ULL, // UDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 3023 | 0ULL, // UDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 3024 | 0ULL, // UDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 3025 | 0ULL, // UDOT_VG2_M2ZZI_BToS_PSEUDO |
| 3026 | 0ULL, // UDOT_VG2_M2ZZI_HToS_PSEUDO |
| 3027 | 0ULL, // UDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 3028 | 0ULL, // UDOT_VG2_M2ZZ_BtoS_PSEUDO |
| 3029 | 0ULL, // UDOT_VG2_M2ZZ_HtoD_PSEUDO |
| 3030 | 0ULL, // UDOT_VG2_M2ZZ_HtoS_PSEUDO |
| 3031 | 0ULL, // UDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 3032 | 0ULL, // UDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 3033 | 0ULL, // UDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 3034 | 0ULL, // UDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 3035 | 0ULL, // UDOT_VG4_M4ZZI_HToS_PSEUDO |
| 3036 | 0ULL, // UDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 3037 | 0ULL, // UDOT_VG4_M4ZZ_BtoS_PSEUDO |
| 3038 | 0ULL, // UDOT_VG4_M4ZZ_HtoD_PSEUDO |
| 3039 | 0ULL, // UDOT_VG4_M4ZZ_HtoS_PSEUDO |
| 3040 | 0ULL, // UHSUB_ZPZZ_B_UNDEF |
| 3041 | 0ULL, // UHSUB_ZPZZ_D_UNDEF |
| 3042 | 0ULL, // UHSUB_ZPZZ_H_UNDEF |
| 3043 | 0ULL, // UHSUB_ZPZZ_S_UNDEF |
| 3044 | 0ULL, // UMAX_ZI_B_PSEUDO |
| 3045 | 0ULL, // UMAX_ZI_D_PSEUDO |
| 3046 | 0ULL, // UMAX_ZI_H_PSEUDO |
| 3047 | 0ULL, // UMAX_ZI_S_PSEUDO |
| 3048 | 0ULL, // UMAX_ZPZZ_B_UNDEF |
| 3049 | 0ULL, // UMAX_ZPZZ_D_UNDEF |
| 3050 | 0ULL, // UMAX_ZPZZ_H_UNDEF |
| 3051 | 0ULL, // UMAX_ZPZZ_S_UNDEF |
| 3052 | 0ULL, // UMIN_ZI_B_PSEUDO |
| 3053 | 0ULL, // UMIN_ZI_D_PSEUDO |
| 3054 | 0ULL, // UMIN_ZI_H_PSEUDO |
| 3055 | 0ULL, // UMIN_ZI_S_PSEUDO |
| 3056 | 0ULL, // UMIN_ZPZZ_B_UNDEF |
| 3057 | 0ULL, // UMIN_ZPZZ_D_UNDEF |
| 3058 | 0ULL, // UMIN_ZPZZ_H_UNDEF |
| 3059 | 0ULL, // UMIN_ZPZZ_S_UNDEF |
| 3060 | 0ULL, // UMLALL_MZZI_BtoS_PSEUDO |
| 3061 | 0ULL, // UMLALL_MZZI_HtoD_PSEUDO |
| 3062 | 0ULL, // UMLALL_MZZ_BtoS_PSEUDO |
| 3063 | 0ULL, // UMLALL_MZZ_HtoD_PSEUDO |
| 3064 | 0ULL, // UMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 3065 | 0ULL, // UMLALL_VG2_M2Z2Z_HtoD_PSEUDO |
| 3066 | 0ULL, // UMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 3067 | 0ULL, // UMLALL_VG2_M2ZZI_HtoD_PSEUDO |
| 3068 | 0ULL, // UMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 3069 | 0ULL, // UMLALL_VG2_M2ZZ_HtoD_PSEUDO |
| 3070 | 0ULL, // UMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3071 | 0ULL, // UMLALL_VG4_M4Z4Z_HtoD_PSEUDO |
| 3072 | 0ULL, // UMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 3073 | 0ULL, // UMLALL_VG4_M4ZZI_HtoD_PSEUDO |
| 3074 | 0ULL, // UMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 3075 | 0ULL, // UMLALL_VG4_M4ZZ_HtoD_PSEUDO |
| 3076 | 0ULL, // UMLAL_MZZI_HtoS_PSEUDO |
| 3077 | 0ULL, // UMLAL_MZZ_HtoS_PSEUDO |
| 3078 | 0ULL, // UMLAL_VG2_M2Z2Z_HtoS_PSEUDO |
| 3079 | 0ULL, // UMLAL_VG2_M2ZZI_S_PSEUDO |
| 3080 | 0ULL, // UMLAL_VG2_M2ZZ_HtoS_PSEUDO |
| 3081 | 0ULL, // UMLAL_VG4_M4Z4Z_HtoS_PSEUDO |
| 3082 | 0ULL, // UMLAL_VG4_M4ZZI_HtoS_PSEUDO |
| 3083 | 0ULL, // UMLAL_VG4_M4ZZ_HtoS_PSEUDO |
| 3084 | 0ULL, // UMLSLL_MZZI_BtoS_PSEUDO |
| 3085 | 0ULL, // UMLSLL_MZZI_HtoD_PSEUDO |
| 3086 | 0ULL, // UMLSLL_MZZ_BtoS_PSEUDO |
| 3087 | 0ULL, // UMLSLL_MZZ_HtoD_PSEUDO |
| 3088 | 0ULL, // UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO |
| 3089 | 0ULL, // UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO |
| 3090 | 0ULL, // UMLSLL_VG2_M2ZZI_BtoS_PSEUDO |
| 3091 | 0ULL, // UMLSLL_VG2_M2ZZI_HtoD_PSEUDO |
| 3092 | 0ULL, // UMLSLL_VG2_M2ZZ_BtoS_PSEUDO |
| 3093 | 0ULL, // UMLSLL_VG2_M2ZZ_HtoD_PSEUDO |
| 3094 | 0ULL, // UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3095 | 0ULL, // UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO |
| 3096 | 0ULL, // UMLSLL_VG4_M4ZZI_BtoS_PSEUDO |
| 3097 | 0ULL, // UMLSLL_VG4_M4ZZI_HtoD_PSEUDO |
| 3098 | 0ULL, // UMLSLL_VG4_M4ZZ_BtoS_PSEUDO |
| 3099 | 0ULL, // UMLSLL_VG4_M4ZZ_HtoD_PSEUDO |
| 3100 | 0ULL, // UMLSL_MZZI_HtoS_PSEUDO |
| 3101 | 0ULL, // UMLSL_MZZ_HtoS_PSEUDO |
| 3102 | 0ULL, // UMLSL_VG2_M2Z2Z_HtoS_PSEUDO |
| 3103 | 0ULL, // UMLSL_VG2_M2ZZI_S_PSEUDO |
| 3104 | 0ULL, // UMLSL_VG2_M2ZZ_HtoS_PSEUDO |
| 3105 | 0ULL, // UMLSL_VG4_M4Z4Z_HtoS_PSEUDO |
| 3106 | 0ULL, // UMLSL_VG4_M4ZZI_HtoS_PSEUDO |
| 3107 | 0ULL, // UMLSL_VG4_M4ZZ_HtoS_PSEUDO |
| 3108 | 0ULL, // UMOP4A_M2Z2Z_BToS_PSEUDO |
| 3109 | 0ULL, // UMOP4A_M2Z2Z_HToS_PSEUDO |
| 3110 | 0ULL, // UMOP4A_M2Z2Z_HtoD_PSEUDO |
| 3111 | 0ULL, // UMOP4A_M2ZZ_BToS_PSEUDO |
| 3112 | 0ULL, // UMOP4A_M2ZZ_HToS_PSEUDO |
| 3113 | 0ULL, // UMOP4A_M2ZZ_HtoD_PSEUDO |
| 3114 | 0ULL, // UMOP4A_MZ2Z_BToS_PSEUDO |
| 3115 | 0ULL, // UMOP4A_MZ2Z_HToS_PSEUDO |
| 3116 | 0ULL, // UMOP4A_MZ2Z_HtoD_PSEUDO |
| 3117 | 0ULL, // UMOP4A_MZZ_BToS_PSEUDO |
| 3118 | 0ULL, // UMOP4A_MZZ_HToS_PSEUDO |
| 3119 | 0ULL, // UMOP4A_MZZ_HtoD_PSEUDO |
| 3120 | 0ULL, // UMOP4S_M2Z2Z_BToS_PSEUDO |
| 3121 | 0ULL, // UMOP4S_M2Z2Z_HToS_PSEUDO |
| 3122 | 0ULL, // UMOP4S_M2Z2Z_HtoD_PSEUDO |
| 3123 | 0ULL, // UMOP4S_M2ZZ_BToS_PSEUDO |
| 3124 | 0ULL, // UMOP4S_M2ZZ_HToS_PSEUDO |
| 3125 | 0ULL, // UMOP4S_M2ZZ_HtoD_PSEUDO |
| 3126 | 0ULL, // UMOP4S_MZ2Z_BToS_PSEUDO |
| 3127 | 0ULL, // UMOP4S_MZ2Z_HToS_PSEUDO |
| 3128 | 0ULL, // UMOP4S_MZ2Z_HtoD_PSEUDO |
| 3129 | 0ULL, // UMOP4S_MZZ_BToS_PSEUDO |
| 3130 | 0ULL, // UMOP4S_MZZ_HToS_PSEUDO |
| 3131 | 0ULL, // UMOP4S_MZZ_HtoD_PSEUDO |
| 3132 | 0ULL, // UMOPA_MPPZZ_D_PSEUDO |
| 3133 | 0ULL, // UMOPA_MPPZZ_HtoS_PSEUDO |
| 3134 | 0ULL, // UMOPA_MPPZZ_S_PSEUDO |
| 3135 | 0ULL, // UMOPS_MPPZZ_D_PSEUDO |
| 3136 | 0ULL, // UMOPS_MPPZZ_HtoS_PSEUDO |
| 3137 | 0ULL, // UMOPS_MPPZZ_S_PSEUDO |
| 3138 | 0ULL, // UMULH_ZPZZ_B_UNDEF |
| 3139 | 0ULL, // UMULH_ZPZZ_D_UNDEF |
| 3140 | 0ULL, // UMULH_ZPZZ_H_UNDEF |
| 3141 | 0ULL, // UMULH_ZPZZ_S_UNDEF |
| 3142 | 0ULL, // UQADD_ZI_B_PSEUDO |
| 3143 | 0ULL, // UQADD_ZI_D_PSEUDO |
| 3144 | 0ULL, // UQADD_ZI_H_PSEUDO |
| 3145 | 0ULL, // UQADD_ZI_S_PSEUDO |
| 3146 | 0ULL, // UQRSHL_ZPZZ_B_UNDEF |
| 3147 | 0ULL, // UQRSHL_ZPZZ_D_UNDEF |
| 3148 | 0ULL, // UQRSHL_ZPZZ_H_UNDEF |
| 3149 | 0ULL, // UQRSHL_ZPZZ_S_UNDEF |
| 3150 | 0ULL, // UQSHL_ZPZI_B_UNDEF |
| 3151 | 0ULL, // UQSHL_ZPZI_B_ZERO |
| 3152 | 0ULL, // UQSHL_ZPZI_D_UNDEF |
| 3153 | 0ULL, // UQSHL_ZPZI_D_ZERO |
| 3154 | 0ULL, // UQSHL_ZPZI_H_UNDEF |
| 3155 | 0ULL, // UQSHL_ZPZI_H_ZERO |
| 3156 | 0ULL, // UQSHL_ZPZI_S_UNDEF |
| 3157 | 0ULL, // UQSHL_ZPZI_S_ZERO |
| 3158 | 0ULL, // UQSHL_ZPZZ_B_UNDEF |
| 3159 | 0ULL, // UQSHL_ZPZZ_D_UNDEF |
| 3160 | 0ULL, // UQSHL_ZPZZ_H_UNDEF |
| 3161 | 0ULL, // UQSHL_ZPZZ_S_UNDEF |
| 3162 | 0ULL, // UQSUB_ZI_B_PSEUDO |
| 3163 | 0ULL, // UQSUB_ZI_D_PSEUDO |
| 3164 | 0ULL, // UQSUB_ZI_H_PSEUDO |
| 3165 | 0ULL, // UQSUB_ZI_S_PSEUDO |
| 3166 | 0ULL, // URECPE_ZPmZ_S_UNDEF |
| 3167 | 0ULL, // URSHL_ZPZZ_B_UNDEF |
| 3168 | 0ULL, // URSHL_ZPZZ_D_UNDEF |
| 3169 | 0ULL, // URSHL_ZPZZ_H_UNDEF |
| 3170 | 0ULL, // URSHL_ZPZZ_S_UNDEF |
| 3171 | 0ULL, // URSHR_ZPZI_B_ZERO |
| 3172 | 0ULL, // URSHR_ZPZI_D_ZERO |
| 3173 | 0ULL, // URSHR_ZPZI_H_ZERO |
| 3174 | 0ULL, // URSHR_ZPZI_S_ZERO |
| 3175 | 0ULL, // URSQRTE_ZPmZ_S_UNDEF |
| 3176 | 0ULL, // USDOT_VG2_M2Z2Z_BToS_PSEUDO |
| 3177 | 0ULL, // USDOT_VG2_M2ZZI_BToS_PSEUDO |
| 3178 | 0ULL, // USDOT_VG2_M2ZZ_BToS_PSEUDO |
| 3179 | 0ULL, // USDOT_VG4_M4Z4Z_BToS_PSEUDO |
| 3180 | 0ULL, // USDOT_VG4_M4ZZI_BToS_PSEUDO |
| 3181 | 0ULL, // USDOT_VG4_M4ZZ_BToS_PSEUDO |
| 3182 | 0ULL, // USMLALL_MZZI_BtoS_PSEUDO |
| 3183 | 0ULL, // USMLALL_MZZ_BtoS_PSEUDO |
| 3184 | 0ULL, // USMLALL_VG2_M2Z2Z_BtoS_PSEUDO |
| 3185 | 0ULL, // USMLALL_VG2_M2ZZI_BtoS_PSEUDO |
| 3186 | 0ULL, // USMLALL_VG2_M2ZZ_BtoS_PSEUDO |
| 3187 | 0ULL, // USMLALL_VG4_M4Z4Z_BtoS_PSEUDO |
| 3188 | 0ULL, // USMLALL_VG4_M4ZZI_BtoS_PSEUDO |
| 3189 | 0ULL, // USMLALL_VG4_M4ZZ_BtoS_PSEUDO |
| 3190 | 0ULL, // USMOP4A_M2Z2Z_BToS_PSEUDO |
| 3191 | 0ULL, // USMOP4A_M2Z2Z_HtoD_PSEUDO |
| 3192 | 0ULL, // USMOP4A_M2ZZ_BToS_PSEUDO |
| 3193 | 0ULL, // USMOP4A_M2ZZ_HtoD_PSEUDO |
| 3194 | 0ULL, // USMOP4A_MZ2Z_BToS_PSEUDO |
| 3195 | 0ULL, // USMOP4A_MZ2Z_HtoD_PSEUDO |
| 3196 | 0ULL, // USMOP4A_MZZ_BToS_PSEUDO |
| 3197 | 0ULL, // USMOP4A_MZZ_HtoD_PSEUDO |
| 3198 | 0ULL, // USMOP4S_M2Z2Z_BToS_PSEUDO |
| 3199 | 0ULL, // USMOP4S_M2Z2Z_HtoD_PSEUDO |
| 3200 | 0ULL, // USMOP4S_M2ZZ_BToS_PSEUDO |
| 3201 | 0ULL, // USMOP4S_M2ZZ_HtoD_PSEUDO |
| 3202 | 0ULL, // USMOP4S_MZ2Z_BToS_PSEUDO |
| 3203 | 0ULL, // USMOP4S_MZ2Z_HtoD_PSEUDO |
| 3204 | 0ULL, // USMOP4S_MZZ_BToS_PSEUDO |
| 3205 | 0ULL, // USMOP4S_MZZ_HtoD_PSEUDO |
| 3206 | 0ULL, // USMOPA_MPPZZ_D_PSEUDO |
| 3207 | 0ULL, // USMOPA_MPPZZ_S_PSEUDO |
| 3208 | 0ULL, // USMOPS_MPPZZ_D_PSEUDO |
| 3209 | 0ULL, // USMOPS_MPPZZ_S_PSEUDO |
| 3210 | 0ULL, // USTMOPA_M2ZZZI_BtoS_PSEUDO |
| 3211 | 0ULL, // USVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 3212 | 0ULL, // UTMOPA_M2ZZZI_BtoS_PSEUDO |
| 3213 | 0ULL, // UTMOPA_M2ZZZI_HtoS_PSEUDO |
| 3214 | 0ULL, // UVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 3215 | 0ULL, // UVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 3216 | 0ULL, // UVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 3217 | 0ULL, // UXTB_ZPmZ_D_UNDEF |
| 3218 | 0ULL, // UXTB_ZPmZ_H_UNDEF |
| 3219 | 0ULL, // UXTB_ZPmZ_S_UNDEF |
| 3220 | 0ULL, // UXTH_ZPmZ_D_UNDEF |
| 3221 | 0ULL, // UXTH_ZPmZ_S_UNDEF |
| 3222 | 0ULL, // UXTW_ZPmZ_D_UNDEF |
| 3223 | 0ULL, // ZERO_MXI_2Z_PSEUDO |
| 3224 | 0ULL, // ZERO_MXI_4Z_PSEUDO |
| 3225 | 0ULL, // ZERO_MXI_VG2_2Z_PSEUDO |
| 3226 | 0ULL, // ZERO_MXI_VG2_4Z_PSEUDO |
| 3227 | 0ULL, // ZERO_MXI_VG2_Z_PSEUDO |
| 3228 | 0ULL, // ZERO_MXI_VG4_2Z_PSEUDO |
| 3229 | 0ULL, // ZERO_MXI_VG4_4Z_PSEUDO |
| 3230 | 0ULL, // ZERO_MXI_VG4_Z_PSEUDO |
| 3231 | 0ULL, // ZERO_M_PSEUDO |
| 3232 | 0ULL, // ZERO_T_PSEUDO |
| 3233 | 2121155ULL, // ABSWr |
| 3234 | 2121155ULL, // ABSXr |
| 3235 | 34630311363ULL, // ABS_ZPmZ_B |
| 3236 | 8830723349955ULL, // ABS_ZPmZ_D |
| 3237 | 17661446659523ULL, // ABS_ZPmZ_H |
| 3238 | 26422909427139ULL, // ABS_ZPmZ_S |
| 3239 | 35288258747843ULL, // ABS_ZPzZ_B |
| 3240 | 44084351786435ULL, // ABS_ZPzZ_D |
| 3241 | 17730705104323ULL, // ABS_ZPzZ_H |
| 3242 | 52880444841411ULL, // ABS_ZPzZ_S |
| 3243 | 173149363651ULL, // ABSv16i8 |
| 3244 | 2121155ULL, // ABSv1i64 |
| 3245 | 207511199171ULL, // ABSv2i32 |
| 3246 | 241873034691ULL, // ABSv2i64 |
| 3247 | 276234870211ULL, // ABSv4i16 |
| 3248 | 310596705731ULL, // ABSv4i32 |
| 3249 | 344958541251ULL, // ABSv8i16 |
| 3250 | 379320376771ULL, // ABSv8i8 |
| 3251 | 9210022643628ULL, // ADCLB_ZZZ_D |
| 3252 | 26802477156268ULL, // ADCLB_ZZZ_S |
| 3253 | 9210022649894ULL, // ADCLT_ZZZ_D |
| 3254 | 26802477162534ULL, // ADCLT_ZZZ_S |
| 3255 | 61984970137066ULL, // ADCSWr |
| 3256 | 61984970137066ULL, // ADCSXr |
| 3257 | 61984970132218ULL, // ADCWr |
| 3258 | 61984970132218ULL, // ADCXr |
| 3259 | 1196680969997793ULL, // ADDG |
| 3260 | 79612054979411ULL, // ADDHA_MPPZ_D |
| 3261 | 88408148001619ULL, // ADDHA_MPPZ_S |
| 3262 | 97171489720465ULL, // ADDHNB_ZZZ_B |
| 3263 | 18075661437073ULL, // ADDHNB_ZZZ_H |
| 3264 | 44395468507281ULL, // ADDHNB_ZZZ_S |
| 3265 | 105968388055318ULL, // ADDHNT_ZZZ_B |
| 3266 | 517837234454ULL, // ADDHNT_ZZZ_H |
| 3267 | 9210022682902ULL, // ADDHNT_ZZZ_S |
| 3268 | 2366700131555310ULL, // ADDHNv2i64_v2i32 |
| 3269 | 2375498109944244ULL, // ADDHNv2i64_v4i32 |
| 3270 | 3492634402330606ULL, // ADDHNv4i32_v4i16 |
| 3271 | 3501432378622388ULL, // ADDHNv4i32_v8i16 |
| 3272 | 4627366634717620ULL, // ADDHNv8i16_v16i8 |
| 3273 | 4618568675203054ULL, // ADDHNv8i16_v8i8 |
| 3274 | 61984970134920ULL, // ADDPL_XXI |
| 3275 | 5691484504351194ULL, // ADDPT_shift |
| 3276 | 145276307521968469ULL, // ADDP_ZPmZ_B |
| 3277 | 289400291690862933ULL, // ADDP_ZPmZ_D |
| 3278 | 439233043046144341ULL, // ADDP_ZPmZ_H |
| 3279 | 577639463935629653ULL, // ADDP_ZPmZ_S |
| 3280 | 7996302742886741ULL, // ADDPv16i8 |
| 3281 | 9122237011564885ULL, // ADDPv2i32 |
| 3282 | 2366700133652821ULL, // ADDPv2i64 |
| 3283 | 241862465877ULL, // ADDPv2i64p |
| 3284 | 10248171282340181ULL, // ADDPv4i16 |
| 3285 | 3492634404428117ULL, // ADDPv4i32 |
| 3286 | 4618568673106261ULL, // ADDPv8i16 |
| 3287 | 11374105555212629ULL, // ADDPv8i8 |
| 3288 | 35600180746791ULL, // ADDQP_ZZZ_B |
| 3289 | 44395468479015ULL, // ADDQP_ZZZ_D |
| 3290 | 17732068252199ULL, // ADDQP_ZZZ_H |
| 3291 | 53192635275815ULL, // ADDQP_ZZZ_S |
| 3292 | 35597502751580ULL, // ADDQV_VPZ_B |
| 3293 | 44393599968092ULL, // ADDQV_VPZ_D |
| 3294 | 97170164392796ULL, // ADDQV_VPZ_H |
| 3295 | 53189697184604ULL, // ADDQV_VPZ_S |
| 3296 | 61984970134999ULL, // ADDSPL_XXI |
| 3297 | 35600180746539ULL, // ADDSUBP_ZZZ_B |
| 3298 | 44395468478763ULL, // ADDSUBP_ZZZ_D |
| 3299 | 17732068251947ULL, // ADDSUBP_ZZZ_H |
| 3300 | 53192635275563ULL, // ADDSUBP_ZZZ_S |
| 3301 | 61984970135271ULL, // ADDSVL_XXI |
| 3302 | 141149807336950ULL, // ADDSWri |
| 3303 | 149945900359158ULL, // ADDSWrs |
| 3304 | 158741993381366ULL, // ADDSWrx |
| 3305 | 141149807336950ULL, // ADDSXri |
| 3306 | 149945900359158ULL, // ADDSXrs |
| 3307 | 158741993381366ULL, // ADDSXrx |
| 3308 | 12446883945405942ULL, // ADDSXrx64 |
| 3309 | 79612054979906ULL, // ADDVA_MPPZ_D |
| 3310 | 88408148002114ULL, // ADDVA_MPPZ_S |
| 3311 | 61984970135258ULL, // ADDVL_XXI |
| 3312 | 173142991572ULL, // ADDVv16i8v |
| 3313 | 276222206676ULL, // ADDVv4i16v |
| 3314 | 310581945044ULL, // ADDVv4i32v |
| 3315 | 344941683412ULL, // ADDVv8i16v |
| 3316 | 379301421780ULL, // ADDVv8i8v |
| 3317 | 141149807332352ULL, // ADDWri |
| 3318 | 149945900354560ULL, // ADDWrs |
| 3319 | 158741993376768ULL, // ADDWrx |
| 3320 | 141149807332352ULL, // ADDXri |
| 3321 | 149945900354560ULL, // ADDXrs |
| 3322 | 158741993376768ULL, // ADDXrx |
| 3323 | 12446883945401344ULL, // ADDXrx64 |
| 3324 | 792719412224ULL, // ADD_VG2_2ZZ_B |
| 3325 | 18419267308544ULL, // ADD_VG2_2ZZ_D |
| 3326 | 17732074654720ULL, // ADD_VG2_2ZZ_H |
| 3327 | 18075674151936ULL, // ADD_VG2_2ZZ_S |
| 3328 | 13643603335400448ULL, // ADD_VG2_M2Z2Z_D |
| 3329 | 14769537601997824ULL, // ADD_VG2_M2Z2Z_S |
| 3330 | 448240967376653312ULL, // ADD_VG2_M2ZZ_D |
| 3331 | 449366901643250688ULL, // ADD_VG2_M2ZZ_S |
| 3332 | 18455244000256ULL, // ADD_VG2_M2Z_D |
| 3333 | 18489603755008ULL, // ADD_VG2_M2Z_S |
| 3334 | 792719412224ULL, // ADD_VG4_4ZZ_B |
| 3335 | 18419267308544ULL, // ADD_VG4_4ZZ_D |
| 3336 | 17732074654720ULL, // ADD_VG4_4ZZ_H |
| 3337 | 18075674151936ULL, // ADD_VG4_4ZZ_S |
| 3338 | 13643603603835904ULL, // ADD_VG4_M4Z4Z_D |
| 3339 | 14769537870433280ULL, // ADD_VG4_M4Z4Z_S |
| 3340 | 448240967645088768ULL, // ADD_VG4_M4ZZ_D |
| 3341 | 449366901911686144ULL, // ADD_VG4_M4ZZ_S |
| 3342 | 18455512435712ULL, // ADD_VG4_M4Z_D |
| 3343 | 18489872190464ULL, // ADD_VG4_M4Z_S |
| 3344 | 167541576076288ULL, // ADD_ZI_B |
| 3345 | 176336863808512ULL, // ADD_ZI_D |
| 3346 | 930156186624ULL, // ADD_ZI_H |
| 3347 | 185134030605312ULL, // ADD_ZI_S |
| 3348 | 145276307521965056ULL, // ADD_ZPmZ_B |
| 3349 | 289400291690865114ULL, // ADD_ZPmZ_CPA |
| 3350 | 289400291690859520ULL, // ADD_ZPmZ_D |
| 3351 | 439233043046140928ULL, // ADD_ZPmZ_H |
| 3352 | 577639463935626240ULL, // ADD_ZPmZ_S |
| 3353 | 35600180743168ULL, // ADD_ZZZ_B |
| 3354 | 44395468480986ULL, // ADD_ZZZ_CPA |
| 3355 | 44395468475392ULL, // ADD_ZZZ_D |
| 3356 | 17732068248576ULL, // ADD_ZZZ_H |
| 3357 | 53192635272192ULL, // ADD_ZZZ_S |
| 3358 | 7996302742883328ULL, // ADDv16i8 |
| 3359 | 61984970132480ULL, // ADDv1i64 |
| 3360 | 9122237011561472ULL, // ADDv2i32 |
| 3361 | 2366700133649408ULL, // ADDv2i64 |
| 3362 | 10248171282336768ULL, // ADDv4i16 |
| 3363 | 3492634404424704ULL, // ADDv4i32 |
| 3364 | 4618568673102848ULL, // ADDv8i16 |
| 3365 | 11374105555209216ULL, // ADDv8i8 |
| 3366 | 4565523449ULL, // ADR |
| 3367 | 4565522990ULL, // ADRP |
| 3368 | 193929087605753ULL, // ADR_LSL_ZZZ_D_0 |
| 3369 | 202725180627961ULL, // ADR_LSL_ZZZ_D_1 |
| 3370 | 211521273650169ULL, // ADR_LSL_ZZZ_D_2 |
| 3371 | 220317366672377ULL, // ADR_LSL_ZZZ_D_3 |
| 3372 | 229114533469177ULL, // ADR_LSL_ZZZ_S_0 |
| 3373 | 237910626491385ULL, // ADR_LSL_ZZZ_S_1 |
| 3374 | 246706719513593ULL, // ADR_LSL_ZZZ_S_2 |
| 3375 | 255502812535801ULL, // ADR_LSL_ZZZ_S_3 |
| 3376 | 264297831783417ULL, // ADR_SXTW_ZZZ_D_0 |
| 3377 | 273093924805625ULL, // ADR_SXTW_ZZZ_D_1 |
| 3378 | 281890017827833ULL, // ADR_SXTW_ZZZ_D_2 |
| 3379 | 290686110850041ULL, // ADR_SXTW_ZZZ_D_3 |
| 3380 | 299482203872249ULL, // ADR_UXTW_ZZZ_D_0 |
| 3381 | 308278296894457ULL, // ADR_UXTW_ZZZ_D_1 |
| 3382 | 317074389916665ULL, // ADR_UXTW_ZZZ_D_2 |
| 3383 | 325870482938873ULL, // ADR_UXTW_ZZZ_D_3 |
| 3384 | 335216052947724ULL, // AESDIMC_2ZZI_B |
| 3385 | 335216052947724ULL, // AESDIMC_4ZZI_B |
| 3386 | 335216052948140ULL, // AESD_2ZZI_B |
| 3387 | 335216052948140ULL, // AESD_4ZZI_B |
| 3388 | 35600180743340ULL, // AESD_ZZZ_B |
| 3389 | 175028440236ULL, // AESDrr |
| 3390 | 335216052947716ULL, // AESEMC_2ZZI_B |
| 3391 | 335216052947716ULL, // AESEMC_4ZZI_B |
| 3392 | 335216052948344ULL, // AESE_2ZZI_B |
| 3393 | 335216052948344ULL, // AESE_4ZZI_B |
| 3394 | 35600180743544ULL, // AESE_ZZZ_B |
| 3395 | 175028440440ULL, // AESErr |
| 3396 | 3491793685ULL, // AESIMC_ZZ_B |
| 3397 | 173149358869ULL, // AESIMCrr |
| 3398 | 3491793693ULL, // AESMC_ZZ_B |
| 3399 | 173149358877ULL, // AESMCrr |
| 3400 | 35597502751587ULL, // ANDQV_VPZ_B |
| 3401 | 44393599968099ULL, // ANDQV_VPZ_D |
| 3402 | 97170164392803ULL, // ANDQV_VPZ_H |
| 3403 | 53189697184611ULL, // ANDQV_VPZ_S |
| 3404 | 343459946847741ULL, // ANDSWri |
| 3405 | 149945900359165ULL, // ANDSWrs |
| 3406 | 352256039869949ULL, // ANDSXri |
| 3407 | 149945900359165ULL, // ANDSXrs |
| 3408 | 145276376241446397ULL, // ANDS_PPzPP |
| 3409 | 254696ULL, // ANDV_VPZ_B |
| 3410 | 4874052328ULL, // ANDV_VPZ_D |
| 3411 | 4876165864ULL, // ANDV_VPZ_H |
| 3412 | 4857307880ULL, // ANDV_VPZ_S |
| 3413 | 343459946843266ULL, // ANDWri |
| 3414 | 149945900354690ULL, // ANDWrs |
| 3415 | 352256039865474ULL, // ANDXri |
| 3416 | 149945900354690ULL, // ANDXrs |
| 3417 | 145276376241441922ULL, // AND_PPzPP |
| 3418 | 352258724252802ULL, // AND_ZI |
| 3419 | 145276307521965186ULL, // AND_ZPmZ_B |
| 3420 | 289400291690859650ULL, // AND_ZPmZ_D |
| 3421 | 439233043046141058ULL, // AND_ZPmZ_H |
| 3422 | 577639463935626370ULL, // AND_ZPmZ_S |
| 3423 | 44395468475522ULL, // AND_ZZZ |
| 3424 | 7996302742883458ULL, // ANDv16i8 |
| 3425 | 11374105555209346ULL, // ANDv8i8 |
| 3426 | 1161119446109350ULL, // ASRD_ZPmI_B |
| 3427 | 1169915539147942ULL, // ASRD_ZPmI_D |
| 3428 | 450492042114567334ULL, // ASRD_ZPmI_H |
| 3429 | 1178711632202918ULL, // ASRD_ZPmI_S |
| 3430 | 145276307521969354ULL, // ASRR_ZPmZ_B |
| 3431 | 289400291690863818ULL, // ASRR_ZPmZ_D |
| 3432 | 439233043046145226ULL, // ASRR_ZPmZ_H |
| 3433 | 577639463935630538ULL, // ASRR_ZPmZ_S |
| 3434 | 61984970136796ULL, // ASRVWr |
| 3435 | 61984970136796ULL, // ASRVXr |
| 3436 | 289391495597825244ULL, // ASR_WIDE_ZPmZ_B |
| 3437 | 19272377793846492ULL, // ASR_WIDE_ZPmZ_H |
| 3438 | 289409087783918812ULL, // ASR_WIDE_ZPmZ_S |
| 3439 | 44396273769692ULL, // ASR_WIDE_ZZZ_B |
| 3440 | 18419263020252ULL, // ASR_WIDE_ZZZ_H |
| 3441 | 44396542254300ULL, // ASR_WIDE_ZZZ_S |
| 3442 | 1161119446113500ULL, // ASR_ZPmI_B |
| 3443 | 1169915539152092ULL, // ASR_ZPmI_D |
| 3444 | 450492042114571484ULL, // ASR_ZPmI_H |
| 3445 | 1178711632207068ULL, // ASR_ZPmI_S |
| 3446 | 145276307521969372ULL, // ASR_ZPmZ_B |
| 3447 | 289400291690863836ULL, // ASR_ZPmZ_D |
| 3448 | 439233043046145244ULL, // ASR_ZPmZ_H |
| 3449 | 577639463935630556ULL, // ASR_ZPmZ_S |
| 3450 | 61988459814108ULL, // ASR_ZZI_B |
| 3451 | 61987654524124ULL, // ASR_ZZI_D |
| 3452 | 18591061712092ULL, // ASR_ZZI_H |
| 3453 | 61988728298716ULL, // ASR_ZZI_S |
| 3454 | 5102682949ULL, // AUTDA |
| 3455 | 5102683852ULL, // AUTDB |
| 3456 | 312700ULL, // AUTDZA |
| 3457 | 314070ULL, // AUTDZB |
| 3458 | 5102682977ULL, // AUTIA |
| 3459 | 10004ULL, // AUTIA1716 |
| 3460 | 10043ULL, // AUTIA171615 |
| 3461 | 10131ULL, // AUTIASP |
| 3462 | 330550ULL, // AUTIASPPCi |
| 3463 | 23509ULL, // AUTIASPPCr |
| 3464 | 10122ULL, // AUTIAZ |
| 3465 | 5102683889ULL, // AUTIB |
| 3466 | 10013ULL, // AUTIB1716 |
| 3467 | 10067ULL, // AUTIB171615 |
| 3468 | 9995ULL, // AUTIBSP |
| 3469 | 330572ULL, // AUTIBSPPCi |
| 3470 | 23533ULL, // AUTIBSPPCr |
| 3471 | 9977ULL, // AUTIBZ |
| 3472 | 312716ULL, // AUTIZA |
| 3473 | 314086ULL, // AUTIZB |
| 3474 | 11615ULL, // AXFLAG |
| 3475 | 329111ULL, // B |
| 3476 | 740957142097437977ULL, // BCAX |
| 3477 | 289400671527036185ULL, // BCAX_ZZZZ |
| 3478 | 46491242ULL, // BCcc |
| 3479 | 35600180746592ULL, // BDEP_ZZZ_B |
| 3480 | 44395468478816ULL, // BDEP_ZZZ_D |
| 3481 | 17732068252000ULL, // BDEP_ZZZ_H |
| 3482 | 53192635275616ULL, // BDEP_ZZZ_S |
| 3483 | 35600180748910ULL, // BEXT_ZZZ_B |
| 3484 | 44395468481134ULL, // BEXT_ZZZ_D |
| 3485 | 17732068254318ULL, // BEXT_ZZZ_H |
| 3486 | 53192635277934ULL, // BEXT_ZZZ_S |
| 3487 | 21515968318677392ULL, // BF16DOTlanev4bf16 |
| 3488 | 21515865245753744ULL, // BF16DOTlanev8bf16 |
| 3489 | 379318277797ULL, // BF1CVTL |
| 3490 | 173159842190ULL, // BF1CVTL2 |
| 3491 | 4880146663ULL, // BF1CVTLT_ZZ_BtoH |
| 3492 | 4880258725ULL, // BF1CVTL_2ZZ_BtoH |
| 3493 | 4880261667ULL, // BF1CVT_2ZZ_BtoH |
| 3494 | 4880146979ULL, // BF1CVT_ZZ_BtoH |
| 3495 | 379318277806ULL, // BF2CVTL |
| 3496 | 173159842200ULL, // BF2CVTL2 |
| 3497 | 4880146673ULL, // BF2CVTLT_ZZ_BtoH |
| 3498 | 4880258734ULL, // BF2CVTL_2ZZ_BtoH |
| 3499 | 4880261675ULL, // BF2CVT_2ZZ_BtoH |
| 3500 | 4880146987ULL, // BF2CVT_ZZ_BtoH |
| 3501 | 18627042839574ULL, // BFADD_VG2_M2Z_H |
| 3502 | 18627311275030ULL, // BFADD_VG4_M4Z_H |
| 3503 | 439233043046140950ULL, // BFADD_ZPmZ |
| 3504 | 17732068248598ULL, // BFADD_ZZZ |
| 3505 | 17663365667230ULL, // BFCLAMP_VG2_2ZZZ_H |
| 3506 | 17663365667230ULL, // BFCLAMP_VG4_4ZZZ_H |
| 3507 | 17663365552542ULL, // BFCLAMP_ZZZ |
| 3508 | 2122291ULL, // BFCVT |
| 3509 | 310594607223ULL, // BFCVTN |
| 3510 | 312477876712ULL, // BFCVTN2 |
| 3511 | 515937214794ULL, // BFCVTNT_ZPmZ |
| 3512 | 516474085706ULL, // BFCVTNT_ZPzZ_StoH |
| 3513 | 5370845303ULL, // BFCVTN_Z2Z_HtoB |
| 3514 | 4867561591ULL, // BFCVTN_Z2Z_StoH |
| 3515 | 5370847795ULL, // BFCVT_Z2Z_HtoB |
| 3516 | 4867564083ULL, // BFCVT_Z2Z_StoH |
| 3517 | 515937215027ULL, // BFCVT_ZPmZ |
| 3518 | 18074302489139ULL, // BFCVT_ZPzZ_StoH |
| 3519 | 22650974388855184ULL, // BFDOT_VG2_M2Z2Z_HtoS |
| 3520 | 888468002750833040ULL, // BFDOT_VG2_M2ZZI_HtoS |
| 3521 | 456122438523265424ULL, // BFDOT_VG2_M2ZZ_HtoS |
| 3522 | 22650974657290640ULL, // BFDOT_VG4_M4Z4Z_HtoS |
| 3523 | 888468003019268496ULL, // BFDOT_VG4_M4ZZI_HtoS |
| 3524 | 456122438791700880ULL, // BFDOT_VG4_M4ZZ_HtoS |
| 3525 | 457221330566209936ULL, // BFDOT_ZZI |
| 3526 | 105968388104592ULL, // BFDOT_ZZZ |
| 3527 | 10256969250251152ULL, // BFDOTv4bf16 |
| 3528 | 4627366643114384ULL, // BFDOTv8bf16 |
| 3529 | 18659787593617ULL, // BFMAXNM_VG2_2Z2Z_H |
| 3530 | 17732074657681ULL, // BFMAXNM_VG2_2ZZ_H |
| 3531 | 18659787593617ULL, // BFMAXNM_VG4_4Z2Z_H |
| 3532 | 17732074657681ULL, // BFMAXNM_VG4_4ZZ_H |
| 3533 | 439233043046143889ULL, // BFMAXNM_ZPmZ |
| 3534 | 18659787597096ULL, // BFMAX_VG2_2Z2Z_H |
| 3535 | 17732074661160ULL, // BFMAX_VG2_2ZZ_H |
| 3536 | 18659787597096ULL, // BFMAX_VG4_4Z2Z_H |
| 3537 | 17732074661160ULL, // BFMAX_VG4_4ZZ_H |
| 3538 | 439233043046147368ULL, // BFMAX_ZPmZ |
| 3539 | 18659787593575ULL, // BFMINNM_VG2_2Z2Z_H |
| 3540 | 17732074657639ULL, // BFMINNM_VG2_2ZZ_H |
| 3541 | 18659787593575ULL, // BFMINNM_VG4_4Z2Z_H |
| 3542 | 17732074657639ULL, // BFMINNM_VG4_4ZZ_H |
| 3543 | 439233043046143847ULL, // BFMINNM_ZPmZ |
| 3544 | 18659787593726ULL, // BFMIN_VG2_2Z2Z_H |
| 3545 | 17732074657790ULL, // BFMIN_VG2_2ZZ_H |
| 3546 | 18659787593726ULL, // BFMIN_VG4_4Z2Z_H |
| 3547 | 17732074657790ULL, // BFMIN_VG4_4ZZ_H |
| 3548 | 439233043046143998ULL, // BFMIN_ZPmZ |
| 3549 | 4627366643107618ULL, // BFMLALB |
| 3550 | 1034825781404108578ULL, // BFMLALBIdx |
| 3551 | 105968388097826ULL, // BFMLALB_ZZZ |
| 3552 | 457221330566203170ULL, // BFMLALB_ZZZI |
| 3553 | 4627366643113951ULL, // BFMLALT |
| 3554 | 1034825781404114911ULL, // BFMLALTIdx |
| 3555 | 105968388104159ULL, // BFMLALT_ZZZ |
| 3556 | 457221330566209503ULL, // BFMLALT_ZZZI |
| 3557 | 361745013248559ULL, // BFMLAL_MZZI_HtoS |
| 3558 | 18697385382447ULL, // BFMLAL_MZZ_HtoS |
| 3559 | 22650974401434159ULL, // BFMLAL_VG2_M2Z2Z_HtoS |
| 3560 | 888468002763412015ULL, // BFMLAL_VG2_M2ZZI_HtoS |
| 3561 | 456122438535844399ULL, // BFMLAL_VG2_M2ZZ_HtoS |
| 3562 | 22650974669869615ULL, // BFMLAL_VG4_M4Z4Z_HtoS |
| 3563 | 888468003031847471ULL, // BFMLAL_VG4_M4ZZI_HtoS |
| 3564 | 456122438804279855ULL, // BFMLAL_VG4_M4ZZ_HtoS |
| 3565 | 22650974388978549ULL, // BFMLA_VG2_M2Z2Z |
| 3566 | 456122438523388789ULL, // BFMLA_VG2_M2ZZ |
| 3567 | 888468002750956405ULL, // BFMLA_VG2_M2ZZI |
| 3568 | 22650974657414005ULL, // BFMLA_VG4_M4Z4Z |
| 3569 | 456122438791824245ULL, // BFMLA_VG4_M4ZZ |
| 3570 | 888468003019391861ULL, // BFMLA_VG4_M4ZZI |
| 3571 | 459499172649829237ULL, // BFMLA_ZPmZZ |
| 3572 | 369507086435189ULL, // BFMLA_ZZZI |
| 3573 | 457221330566203468ULL, // BFMLSLB_ZZZI_S |
| 3574 | 105968388098124ULL, // BFMLSLB_ZZZ_S |
| 3575 | 457221330566209734ULL, // BFMLSLT_ZZZI_S |
| 3576 | 105968388104390ULL, // BFMLSLT_ZZZ_S |
| 3577 | 361745013249630ULL, // BFMLSL_MZZI_HtoS |
| 3578 | 18697385383518ULL, // BFMLSL_MZZ_HtoS |
| 3579 | 22650974401435230ULL, // BFMLSL_VG2_M2Z2Z_HtoS |
| 3580 | 888468002763413086ULL, // BFMLSL_VG2_M2ZZI_HtoS |
| 3581 | 456122438535845470ULL, // BFMLSL_VG2_M2ZZ_HtoS |
| 3582 | 22650974669870686ULL, // BFMLSL_VG4_M4Z4Z_HtoS |
| 3583 | 888468003031848542ULL, // BFMLSL_VG4_M4ZZI_HtoS |
| 3584 | 456122438804280926ULL, // BFMLSL_VG4_M4ZZ_HtoS |
| 3585 | 22650974388985419ULL, // BFMLS_VG2_M2Z2Z |
| 3586 | 456122438523395659ULL, // BFMLS_VG2_M2ZZ |
| 3587 | 888468002750963275ULL, // BFMLS_VG2_M2ZZI |
| 3588 | 22650974657420875ULL, // BFMLS_VG4_M4Z4Z |
| 3589 | 456122438791831115ULL, // BFMLS_VG4_M4ZZ |
| 3590 | 888468003019398731ULL, // BFMLS_VG4_M4ZZI |
| 3591 | 459499172649836107ULL, // BFMLS_ZPmZZ |
| 3592 | 369507086442059ULL, // BFMLS_ZZZI |
| 3593 | 4627366643106684ULL, // BFMMLA |
| 3594 | 17663365546876ULL, // BFMMLA_ZZZ_H |
| 3595 | 105968388096892ULL, // BFMMLA_ZZZ_HtoS |
| 3596 | 5958124255ULL, // BFMOP4A_M2Z2Z_H |
| 3597 | 5958124255ULL, // BFMOP4A_M2Z2Z_S |
| 3598 | 6226559711ULL, // BFMOP4A_M2ZZ_H |
| 3599 | 6226559711ULL, // BFMOP4A_M2ZZ_S |
| 3600 | 1136331440863ULL, // BFMOP4A_MZ2Z_H |
| 3601 | 1136331440863ULL, // BFMOP4A_MZ2Z_S |
| 3602 | 17663365595871ULL, // BFMOP4A_MZZ_H |
| 3603 | 17663365595871ULL, // BFMOP4A_MZZ_S |
| 3604 | 5958131071ULL, // BFMOP4S_M2Z2Z_H |
| 3605 | 5958131071ULL, // BFMOP4S_M2Z2Z_S |
| 3606 | 6226566527ULL, // BFMOP4S_M2ZZ_H |
| 3607 | 6226566527ULL, // BFMOP4S_M2ZZ_S |
| 3608 | 1136331447679ULL, // BFMOP4S_MZ2Z_H |
| 3609 | 1136331447679ULL, // BFMOP4S_MZ2Z_S |
| 3610 | 17663365602687ULL, // BFMOP4S_MZZ_H |
| 3611 | 17663365602687ULL, // BFMOP4S_MZZ_S |
| 3612 | 378679217734651ULL, // BFMOPA_MPPZZ |
| 3613 | 378679217734651ULL, // BFMOPA_MPPZZ_H |
| 3614 | 378679217741464ULL, // BFMOPS_MPPZZ |
| 3615 | 378679217741464ULL, // BFMOPS_MPPZZ_H |
| 3616 | 18659787593406ULL, // BFMUL_2Z2Z |
| 3617 | 17732074657470ULL, // BFMUL_2ZZ |
| 3618 | 18659787593406ULL, // BFMUL_4Z4Z |
| 3619 | 17732074657470ULL, // BFMUL_4ZZ |
| 3620 | 439233043046143678ULL, // BFMUL_ZPmZ |
| 3621 | 17732068251326ULL, // BFMUL_ZZZ |
| 3622 | 334391417050814ULL, // BFMUL_ZZZI |
| 3623 | 1154434850025920310ULL, // BFMWri |
| 3624 | 1154434850025920310ULL, // BFMXri |
| 3625 | 18659787590918ULL, // BFSCALE_2Z2Z |
| 3626 | 17732074654982ULL, // BFSCALE_2ZZ |
| 3627 | 18659787590918ULL, // BFSCALE_4Z4Z |
| 3628 | 17732074654982ULL, // BFSCALE_4ZZ |
| 3629 | 439233043046141190ULL, // BFSCALE_ZPmZ |
| 3630 | 18627042839140ULL, // BFSUB_VG2_M2Z_H |
| 3631 | 18627311274596ULL, // BFSUB_VG4_M4Z_H |
| 3632 | 439233043046140516ULL, // BFSUB_ZPmZ |
| 3633 | 17732068248164ULL, // BFSUB_ZZZ |
| 3634 | 396242729419787ULL, // BFTMOPA_M2ZZZI_HtoH |
| 3635 | 396242729419787ULL, // BFTMOPA_M2ZZZI_HtoS |
| 3636 | 888468002750833061ULL, // BFVDOT_VG2_M2ZZI_HtoS |
| 3637 | 35600180746804ULL, // BGRP_ZZZ_B |
| 3638 | 44395468479028ULL, // BGRP_ZZZ_D |
| 3639 | 17732068252212ULL, // BGRP_ZZZ_H |
| 3640 | 53192635275828ULL, // BGRP_ZZZ_S |
| 3641 | 149945900359152ULL, // BICSWrs |
| 3642 | 149945900359152ULL, // BICSXrs |
| 3643 | 145276376241446384ULL, // BICS_PPzPP |
| 3644 | 149945900354303ULL, // BICWrs |
| 3645 | 149945900354303ULL, // BICXrs |
| 3646 | 145276376241441535ULL, // BIC_PPzPP |
| 3647 | 145276307521964799ULL, // BIC_ZPmZ_B |
| 3648 | 289400291690859263ULL, // BIC_ZPmZ_D |
| 3649 | 439233043046140671ULL, // BIC_ZPmZ_H |
| 3650 | 577639463935625983ULL, // BIC_ZPmZ_S |
| 3651 | 44395468475135ULL, // BIC_ZZZ |
| 3652 | 7996302742883071ULL, // BICv16i8 |
| 3653 | 6453070591ULL, // BICv2i32 |
| 3654 | 6457264895ULL, // BICv4i16 |
| 3655 | 6459362047ULL, // BICv4i32 |
| 3656 | 6461459199ULL, // BICv8i16 |
| 3657 | 11374105555208959ULL, // BICv8i8 |
| 3658 | 8005100714986933ULL, // BIFv16i8 |
| 3659 | 11382903527312821ULL, // BIFv8i8 |
| 3660 | 8005100714991539ULL, // BITv16i8 |
| 3661 | 11382903527317427ULL, // BITv8i8 |
| 3662 | 332748ULL, // BL |
| 3663 | 23619ULL, // BLR |
| 3664 | 2114311ULL, // BLRAA |
| 3665 | 26053ULL, // BLRAAZ |
| 3666 | 2115149ULL, // BLRAB |
| 3667 | 26075ULL, // BLRABZ |
| 3668 | 1298251000737547252ULL, // BMOPA_MPPZZ_S |
| 3669 | 1298251000737554065ULL, // BMOPS_MPPZZ_S |
| 3670 | 23461ULL, // BR |
| 3671 | 2114298ULL, // BRAA |
| 3672 | 26046ULL, // BRAAZ |
| 3673 | 2115136ULL, // BRAB |
| 3674 | 26068ULL, // BRABZ |
| 3675 | 381413ULL, // BRK |
| 3676 | 35288258747819ULL, // BRKAS_PPzP |
| 3677 | 34630304616ULL, // BRKA_PPmP |
| 3678 | 35288258741096ULL, // BRKA_PPzP |
| 3679 | 35288258747855ULL, // BRKBS_PPzP |
| 3680 | 34630305528ULL, // BRKB_PPmP |
| 3681 | 35288258742008ULL, // BRKB_PPzP |
| 3682 | 145276376241446509ULL, // BRKNS_PPzP |
| 3683 | 145276376241444910ULL, // BRKN_PPzP |
| 3684 | 145276376241446322ULL, // BRKPAS_PPzPP |
| 3685 | 145276376241439725ULL, // BRKPA_PPzPP |
| 3686 | 145276376241446358ULL, // BRKPBS_PPzPP |
| 3687 | 145276376241441039ULL, // BRKPB_PPzPP |
| 3688 | 289400671527032791ULL, // BSL1N_ZZZZ |
| 3689 | 289400671527032798ULL, // BSL2N_ZZZZ |
| 3690 | 289400671527032400ULL, // BSL_ZZZZ |
| 3691 | 8005100714989136ULL, // BSLv16i8 |
| 3692 | 11382903527315024ULL, // BSLv8i8 |
| 3693 | 46491239ULL, // Bcc |
| 3694 | 1442313380846144511ULL, // CADD_ZZI_B |
| 3695 | 1442322176133876735ULL, // CADD_ZZI_D |
| 3696 | 28279578948602879ULL, // CADD_ZZI_H |
| 3697 | 1442330973300673535ULL, // CADD_ZZI_S |
| 3698 | 29661599004673638ULL, // CASAB |
| 3699 | 29661599004675797ULL, // CASAH |
| 3700 | 29661599004673901ULL, // CASALB |
| 3701 | 29661599004675956ULL, // CASALH |
| 3702 | 29661599004680193ULL, // CASALTX |
| 3703 | 29661599004676961ULL, // CASALW |
| 3704 | 29661599004676961ULL, // CASALX |
| 3705 | 29661599004679940ULL, // CASATX |
| 3706 | 29661599004673272ULL, // CASAW |
| 3707 | 29661599004673272ULL, // CASAX |
| 3708 | 29661599004674522ULL, // CASB |
| 3709 | 29661599004676341ULL, // CASH |
| 3710 | 29661599004674107ULL, // CASLB |
| 3711 | 29661599004676050ULL, // CASLH |
| 3712 | 29661599004680373ULL, // CASLTX |
| 3713 | 29661599004677696ULL, // CASLW |
| 3714 | 29661599004677696ULL, // CASLX |
| 3715 | 401400ULL, // CASPALTX |
| 3716 | 414435ULL, // CASPALW |
| 3717 | 398051ULL, // CASPALX |
| 3718 | 401148ULL, // CASPATX |
| 3719 | 410725ULL, // CASPAW |
| 3720 | 394341ULL, // CASPAX |
| 3721 | 401581ULL, // CASPLTX |
| 3722 | 415174ULL, // CASPLW |
| 3723 | 398790ULL, // CASPLX |
| 3724 | 401889ULL, // CASPTX |
| 3725 | 416345ULL, // CASPW |
| 3726 | 399961ULL, // CASPX |
| 3727 | 29661599004680693ULL, // CASTX |
| 3728 | 29661599004679582ULL, // CASW |
| 3729 | 29661599004679582ULL, // CASX |
| 3730 | 405032598002477ULL, // CBBEQWrr |
| 3731 | 405032597998796ULL, // CBBGEWrr |
| 3732 | 405032598003576ULL, // CBBGTWrr |
| 3733 | 405032597999975ULL, // CBBHIWrr |
| 3734 | 405032598003211ULL, // CBBHSWrr |
| 3735 | 405032597998886ULL, // CBBNEWrr |
| 3736 | 405032598002484ULL, // CBEQWri |
| 3737 | 405032598002484ULL, // CBEQWrr |
| 3738 | 405032598002484ULL, // CBEQXri |
| 3739 | 405032598002484ULL, // CBEQXrr |
| 3740 | 405032597998803ULL, // CBGEWrr |
| 3741 | 405032597998803ULL, // CBGEXrr |
| 3742 | 405032598003583ULL, // CBGTWri |
| 3743 | 405032598003583ULL, // CBGTWrr |
| 3744 | 405032598003583ULL, // CBGTXri |
| 3745 | 405032598003583ULL, // CBGTXrr |
| 3746 | 405032598002490ULL, // CBHEQWrr |
| 3747 | 405032597998825ULL, // CBHGEWrr |
| 3748 | 405032598003605ULL, // CBHGTWrr |
| 3749 | 405032597999997ULL, // CBHHIWrr |
| 3750 | 405032598003233ULL, // CBHHSWrr |
| 3751 | 405032597999982ULL, // CBHIWri |
| 3752 | 405032597999982ULL, // CBHIWrr |
| 3753 | 405032597999982ULL, // CBHIXri |
| 3754 | 405032597999982ULL, // CBHIXrr |
| 3755 | 405032597998899ULL, // CBHNEWrr |
| 3756 | 405032598003218ULL, // CBHSWrr |
| 3757 | 405032598003218ULL, // CBHSXrr |
| 3758 | 405032598001880ULL, // CBLOWri |
| 3759 | 405032598001880ULL, // CBLOXri |
| 3760 | 405032598003721ULL, // CBLTWri |
| 3761 | 405032598003721ULL, // CBLTXri |
| 3762 | 405032597998893ULL, // CBNEWri |
| 3763 | 405032597998893ULL, // CBNEWrr |
| 3764 | 405032597998893ULL, // CBNEXri |
| 3765 | 405032597998893ULL, // CBNEXrr |
| 3766 | 6713009650ULL, // CBNZW |
| 3767 | 6713009650ULL, // CBNZX |
| 3768 | 6713009635ULL, // CBZW |
| 3769 | 6713009635ULL, // CBZX |
| 3770 | 1586454953711392820ULL, // CCMNWi |
| 3771 | 1586454953711392820ULL, // CCMNWr |
| 3772 | 1586454953711392820ULL, // CCMNXi |
| 3773 | 1586454953711392820ULL, // CCMNXr |
| 3774 | 1586454953711393208ULL, // CCMPWi |
| 3775 | 1586454953711393208ULL, // CCMPWr |
| 3776 | 1586454953711393208ULL, // CCMPXi |
| 3777 | 1586454953711393208ULL, // CCMPXr |
| 3778 | 1754258023248880010ULL, // CDOT_ZZZI_D |
| 3779 | 1874993990372254090ULL, // CDOT_ZZZI_S |
| 3780 | 2018844501356896650ULL, // CDOT_ZZZ_D |
| 3781 | 30532448452436362ULL, // CDOT_ZZZ_S |
| 3782 | 11653ULL, // CFINV |
| 3783 | 61984970136408ULL, // CFLTEQWi |
| 3784 | 61984970136408ULL, // CFLTEQWr |
| 3785 | 61984970136408ULL, // CFLTEQXi |
| 3786 | 61984970136408ULL, // CFLTEQXr |
| 3787 | 61984970132734ULL, // CFLTGEWr |
| 3788 | 61984970132734ULL, // CFLTGEXr |
| 3789 | 61984970137514ULL, // CFLTGTWi |
| 3790 | 61984970137514ULL, // CFLTGTWr |
| 3791 | 61984970137514ULL, // CFLTGTXi |
| 3792 | 61984970137514ULL, // CFLTGTXr |
| 3793 | 61984970133932ULL, // CFLTHIWi |
| 3794 | 61984970133932ULL, // CFLTHIWr |
| 3795 | 61984970133932ULL, // CFLTHIXi |
| 3796 | 61984970133932ULL, // CFLTHIXr |
| 3797 | 61984970137141ULL, // CFLTHSWr |
| 3798 | 61984970137141ULL, // CFLTHSXr |
| 3799 | 61984970135817ULL, // CFLTLOWi |
| 3800 | 61984970135817ULL, // CFLTLOXi |
| 3801 | 61984970137823ULL, // CFLTLTWi |
| 3802 | 61984970137823ULL, // CFLTLTXi |
| 3803 | 61984970132817ULL, // CFLTNEWi |
| 3804 | 61984970132817ULL, // CFLTNEWr |
| 3805 | 61984970132817ULL, // CFLTNEXi |
| 3806 | 61984970132817ULL, // CFLTNEXr |
| 3807 | 9986ULL, // CHKFEAT |
| 3808 | 145303073758135610ULL, // CLASTA_RPZ_B |
| 3809 | 289418261833991482ULL, // CLASTA_RPZ_D |
| 3810 | 2162915706820117818ULL, // CLASTA_RPZ_H |
| 3811 | 577648637985703226ULL, // CLASTA_RPZ_S |
| 3812 | 145303073758135610ULL, // CLASTA_VPZ_B |
| 3813 | 289418261833991482ULL, // CLASTA_VPZ_D |
| 3814 | 2162915706820117818ULL, // CLASTA_VPZ_H |
| 3815 | 577648637985703226ULL, // CLASTA_VPZ_S |
| 3816 | 145276685479085370ULL, // CLASTA_ZPZ_B |
| 3817 | 289400669647979834ULL, // CLASTA_ZPZ_D |
| 3818 | 439233044925187386ULL, // CLASTA_ZPZ_H |
| 3819 | 577639841892746554ULL, // CLASTA_ZPZ_S |
| 3820 | 145303073758136912ULL, // CLASTB_RPZ_B |
| 3821 | 289418261833992784ULL, // CLASTB_RPZ_D |
| 3822 | 2162915706820119120ULL, // CLASTB_RPZ_H |
| 3823 | 577648637985704528ULL, // CLASTB_RPZ_S |
| 3824 | 145303073758136912ULL, // CLASTB_VPZ_B |
| 3825 | 289418261833992784ULL, // CLASTB_VPZ_D |
| 3826 | 2162915706820119120ULL, // CLASTB_VPZ_H |
| 3827 | 577648637985704528ULL, // CLASTB_VPZ_S |
| 3828 | 145276685479086672ULL, // CLASTB_ZPZ_B |
| 3829 | 289400669647981136ULL, // CLASTB_ZPZ_D |
| 3830 | 439233044925188688ULL, // CLASTB_ZPZ_H |
| 3831 | 577639841892747856ULL, // CLASTB_ZPZ_S |
| 3832 | 25965ULL, // CLREX |
| 3833 | 2121277ULL, // CLSWr |
| 3834 | 2121277ULL, // CLSXr |
| 3835 | 34630311485ULL, // CLS_ZPmZ_B |
| 3836 | 8830723350077ULL, // CLS_ZPmZ_D |
| 3837 | 17661446659645ULL, // CLS_ZPmZ_H |
| 3838 | 26422909427261ULL, // CLS_ZPmZ_S |
| 3839 | 35288258747965ULL, // CLS_ZPzZ_B |
| 3840 | 44084351786557ULL, // CLS_ZPzZ_D |
| 3841 | 17730705104445ULL, // CLS_ZPzZ_H |
| 3842 | 52880444841533ULL, // CLS_ZPzZ_S |
| 3843 | 173149363773ULL, // CLSv16i8 |
| 3844 | 207511199293ULL, // CLSv2i32 |
| 3845 | 276234870333ULL, // CLSv4i16 |
| 3846 | 310596705853ULL, // CLSv4i32 |
| 3847 | 344958541373ULL, // CLSv8i16 |
| 3848 | 379320376893ULL, // CLSv8i8 |
| 3849 | 2123245ULL, // CLZWr |
| 3850 | 2123245ULL, // CLZXr |
| 3851 | 34630313453ULL, // CLZ_ZPmZ_B |
| 3852 | 8830723352045ULL, // CLZ_ZPmZ_D |
| 3853 | 17661446661613ULL, // CLZ_ZPmZ_H |
| 3854 | 26422909429229ULL, // CLZ_ZPmZ_S |
| 3855 | 35288258749933ULL, // CLZ_ZPzZ_B |
| 3856 | 44084351788525ULL, // CLZ_ZPzZ_D |
| 3857 | 17730705106413ULL, // CLZ_ZPzZ_H |
| 3858 | 52880444843501ULL, // CLZ_ZPzZ_S |
| 3859 | 173149365741ULL, // CLZv16i8 |
| 3860 | 207511201261ULL, // CLZv2i32 |
| 3861 | 276234872301ULL, // CLZv4i16 |
| 3862 | 310596707821ULL, // CLZv4i32 |
| 3863 | 344958543341ULL, // CLZv8i16 |
| 3864 | 379320378861ULL, // CLZv8i8 |
| 3865 | 7996302742887234ULL, // CMEQv16i8 |
| 3866 | 1238301252418ULL, // CMEQv16i8rz |
| 3867 | 61984970136386ULL, // CMEQv1i64 |
| 3868 | 1271312440130ULL, // CMEQv1i64rz |
| 3869 | 9122237011565378ULL, // CMEQv2i32 |
| 3870 | 1307022826306ULL, // CMEQv2i32rz |
| 3871 | 2366700133653314ULL, // CMEQv2i64 |
| 3872 | 1341384661826ULL, // CMEQv2i64rz |
| 3873 | 10248171282340674ULL, // CMEQv4i16 |
| 3874 | 1375746497346ULL, // CMEQv4i16rz |
| 3875 | 3492634404428610ULL, // CMEQv4i32 |
| 3876 | 1410108332866ULL, // CMEQv4i32rz |
| 3877 | 4618568673106754ULL, // CMEQv8i16 |
| 3878 | 1444470168386ULL, // CMEQv8i16rz |
| 3879 | 11374105555213122ULL, // CMEQv8i8 |
| 3880 | 1478832003906ULL, // CMEQv8i8rz |
| 3881 | 7996302742883569ULL, // CMGEv16i8 |
| 3882 | 1238301248753ULL, // CMGEv16i8rz |
| 3883 | 61984970132721ULL, // CMGEv1i64 |
| 3884 | 1271312436465ULL, // CMGEv1i64rz |
| 3885 | 9122237011561713ULL, // CMGEv2i32 |
| 3886 | 1307022822641ULL, // CMGEv2i32rz |
| 3887 | 2366700133649649ULL, // CMGEv2i64 |
| 3888 | 1341384658161ULL, // CMGEv2i64rz |
| 3889 | 10248171282337009ULL, // CMGEv4i16 |
| 3890 | 1375746493681ULL, // CMGEv4i16rz |
| 3891 | 3492634404424945ULL, // CMGEv4i32 |
| 3892 | 1410108329201ULL, // CMGEv4i32rz |
| 3893 | 4618568673103089ULL, // CMGEv8i16 |
| 3894 | 1444470164721ULL, // CMGEv8i16rz |
| 3895 | 11374105555209457ULL, // CMGEv8i8 |
| 3896 | 1478832000241ULL, // CMGEv8i8rz |
| 3897 | 7996302742888349ULL, // CMGTv16i8 |
| 3898 | 1238301253533ULL, // CMGTv16i8rz |
| 3899 | 61984970137501ULL, // CMGTv1i64 |
| 3900 | 1271312441245ULL, // CMGTv1i64rz |
| 3901 | 9122237011566493ULL, // CMGTv2i32 |
| 3902 | 1307022827421ULL, // CMGTv2i32rz |
| 3903 | 2366700133654429ULL, // CMGTv2i64 |
| 3904 | 1341384662941ULL, // CMGTv2i64rz |
| 3905 | 10248171282341789ULL, // CMGTv4i16 |
| 3906 | 1375746498461ULL, // CMGTv4i16rz |
| 3907 | 3492634404429725ULL, // CMGTv4i32 |
| 3908 | 1410108333981ULL, // CMGTv4i32rz |
| 3909 | 4618568673107869ULL, // CMGTv8i16 |
| 3910 | 1444470169501ULL, // CMGTv8i16rz |
| 3911 | 11374105555214237ULL, // CMGTv8i8 |
| 3912 | 1478832005021ULL, // CMGTv8i8rz |
| 3913 | 7996302742884767ULL, // CMHIv16i8 |
| 3914 | 61984970133919ULL, // CMHIv1i64 |
| 3915 | 9122237011562911ULL, // CMHIv2i32 |
| 3916 | 2366700133650847ULL, // CMHIv2i64 |
| 3917 | 10248171282338207ULL, // CMHIv4i16 |
| 3918 | 3492634404426143ULL, // CMHIv4i32 |
| 3919 | 4618568673104287ULL, // CMHIv8i16 |
| 3920 | 11374105555210655ULL, // CMHIv8i8 |
| 3921 | 7996302742887976ULL, // CMHSv16i8 |
| 3922 | 61984970137128ULL, // CMHSv1i64 |
| 3923 | 9122237011566120ULL, // CMHSv2i32 |
| 3924 | 2366700133654056ULL, // CMHSv2i64 |
| 3925 | 10248171282341416ULL, // CMHSv4i16 |
| 3926 | 3492634404429352ULL, // CMHSv4i32 |
| 3927 | 4618568673107496ULL, // CMHSv8i16 |
| 3928 | 11374105555213864ULL, // CMHSv8i8 |
| 3929 | 1874992851979404143ULL, // CMLA_ZZZI_H |
| 3930 | 1754178857337963375ULL, // CMLA_ZZZI_S |
| 3931 | 30532448452379503ULL, // CMLA_ZZZ_B |
| 3932 | 2018747742991467375ULL, // CMLA_ZZZ_D |
| 3933 | 30531310059586415ULL, // CMLA_ZZZ_H |
| 3934 | 2018765335445980015ULL, // CMLA_ZZZ_S |
| 3935 | 1238301248793ULL, // CMLEv16i8rz |
| 3936 | 1271312436505ULL, // CMLEv1i64rz |
| 3937 | 1307022822681ULL, // CMLEv2i32rz |
| 3938 | 1341384658201ULL, // CMLEv2i64rz |
| 3939 | 1375746493721ULL, // CMLEv4i16rz |
| 3940 | 1410108329241ULL, // CMLEv4i32rz |
| 3941 | 1444470164761ULL, // CMLEv8i16rz |
| 3942 | 1478832000281ULL, // CMLEv8i8rz |
| 3943 | 1238301253792ULL, // CMLTv16i8rz |
| 3944 | 1271312441504ULL, // CMLTv1i64rz |
| 3945 | 1307022827680ULL, // CMLTv2i32rz |
| 3946 | 1341384663200ULL, // CMLTv2i64rz |
| 3947 | 1375746498720ULL, // CMLTv4i16rz |
| 3948 | 1410108334240ULL, // CMLTv4i32rz |
| 3949 | 1444470169760ULL, // CMLTv8i16rz |
| 3950 | 1478832005280ULL, // CMLTv8i8rz |
| 3951 | 1161188165589841ULL, // CMPEQ_PPzZI_B |
| 3952 | 1169984258628433ULL, // CMPEQ_PPzZI_D |
| 3953 | 450492042651442001ULL, // CMPEQ_PPzZI_H |
| 3954 | 1178780351683409ULL, // CMPEQ_PPzZI_S |
| 3955 | 145276376241445713ULL, // CMPEQ_PPzZZ_B |
| 3956 | 289400360410340177ULL, // CMPEQ_PPzZZ_D |
| 3957 | 439233043583015761ULL, // CMPEQ_PPzZZ_H |
| 3958 | 577639532655106897ULL, // CMPEQ_PPzZZ_S |
| 3959 | 289391564317301585ULL, // CMPEQ_WIDE_PPzZZ_B |
| 3960 | 19272378330717009ULL, // CMPEQ_WIDE_PPzZZ_H |
| 3961 | 289409156503395153ULL, // CMPEQ_WIDE_PPzZZ_S |
| 3962 | 1161188165586167ULL, // CMPGE_PPzZI_B |
| 3963 | 1169984258624759ULL, // CMPGE_PPzZI_D |
| 3964 | 450492042651438327ULL, // CMPGE_PPzZI_H |
| 3965 | 1178780351679735ULL, // CMPGE_PPzZI_S |
| 3966 | 145276376241442039ULL, // CMPGE_PPzZZ_B |
| 3967 | 289400360410336503ULL, // CMPGE_PPzZZ_D |
| 3968 | 439233043583012087ULL, // CMPGE_PPzZZ_H |
| 3969 | 577639532655103223ULL, // CMPGE_PPzZZ_S |
| 3970 | 289391564317297911ULL, // CMPGE_WIDE_PPzZZ_B |
| 3971 | 19272378330713335ULL, // CMPGE_WIDE_PPzZZ_H |
| 3972 | 289409156503391479ULL, // CMPGE_WIDE_PPzZZ_S |
| 3973 | 1161188165590947ULL, // CMPGT_PPzZI_B |
| 3974 | 1169984258629539ULL, // CMPGT_PPzZI_D |
| 3975 | 450492042651443107ULL, // CMPGT_PPzZI_H |
| 3976 | 1178780351684515ULL, // CMPGT_PPzZI_S |
| 3977 | 145276376241446819ULL, // CMPGT_PPzZZ_B |
| 3978 | 289400360410341283ULL, // CMPGT_PPzZZ_D |
| 3979 | 439233043583016867ULL, // CMPGT_PPzZZ_H |
| 3980 | 577639532655108003ULL, // CMPGT_PPzZZ_S |
| 3981 | 289391564317302691ULL, // CMPGT_WIDE_PPzZZ_B |
| 3982 | 19272378330718115ULL, // CMPGT_WIDE_PPzZZ_H |
| 3983 | 289409156503396259ULL, // CMPGT_WIDE_PPzZZ_S |
| 3984 | 2307004197379281317ULL, // CMPHI_PPzZI_B |
| 3985 | 2307012993472319909ULL, // CMPHI_PPzZI_D |
| 3986 | 31657277305983397ULL, // CMPHI_PPzZI_H |
| 3987 | 2307021789565374885ULL, // CMPHI_PPzZI_S |
| 3988 | 145276376241443237ULL, // CMPHI_PPzZZ_B |
| 3989 | 289400360410337701ULL, // CMPHI_PPzZZ_D |
| 3990 | 439233043583013285ULL, // CMPHI_PPzZZ_H |
| 3991 | 577639532655104421ULL, // CMPHI_PPzZZ_S |
| 3992 | 289391564317299109ULL, // CMPHI_WIDE_PPzZZ_B |
| 3993 | 19272378330714533ULL, // CMPHI_WIDE_PPzZZ_H |
| 3994 | 289409156503392677ULL, // CMPHI_WIDE_PPzZZ_S |
| 3995 | 2307004197379284526ULL, // CMPHS_PPzZI_B |
| 3996 | 2307012993472323118ULL, // CMPHS_PPzZI_D |
| 3997 | 31657277305986606ULL, // CMPHS_PPzZI_H |
| 3998 | 2307021789565378094ULL, // CMPHS_PPzZI_S |
| 3999 | 145276376241446446ULL, // CMPHS_PPzZZ_B |
| 4000 | 289400360410340910ULL, // CMPHS_PPzZZ_D |
| 4001 | 439233043583016494ULL, // CMPHS_PPzZZ_H |
| 4002 | 577639532655107630ULL, // CMPHS_PPzZZ_S |
| 4003 | 289391564317302318ULL, // CMPHS_WIDE_PPzZZ_B |
| 4004 | 19272378330717742ULL, // CMPHS_WIDE_PPzZZ_H |
| 4005 | 289409156503395886ULL, // CMPHS_WIDE_PPzZZ_S |
| 4006 | 1161188165586207ULL, // CMPLE_PPzZI_B |
| 4007 | 1169984258624799ULL, // CMPLE_PPzZI_D |
| 4008 | 450492042651438367ULL, // CMPLE_PPzZI_H |
| 4009 | 1178780351679775ULL, // CMPLE_PPzZI_S |
| 4010 | 289391564317297951ULL, // CMPLE_WIDE_PPzZZ_B |
| 4011 | 19272378330713375ULL, // CMPLE_WIDE_PPzZZ_H |
| 4012 | 289409156503391519ULL, // CMPLE_WIDE_PPzZZ_S |
| 4013 | 2307004197379283202ULL, // CMPLO_PPzZI_B |
| 4014 | 2307012993472321794ULL, // CMPLO_PPzZI_D |
| 4015 | 31657277305985282ULL, // CMPLO_PPzZI_H |
| 4016 | 2307021789565376770ULL, // CMPLO_PPzZI_S |
| 4017 | 289391564317300994ULL, // CMPLO_WIDE_PPzZZ_B |
| 4018 | 19272378330716418ULL, // CMPLO_WIDE_PPzZZ_H |
| 4019 | 289409156503394562ULL, // CMPLO_WIDE_PPzZZ_S |
| 4020 | 2307004197379284569ULL, // CMPLS_PPzZI_B |
| 4021 | 2307012993472323161ULL, // CMPLS_PPzZI_D |
| 4022 | 31657277305986649ULL, // CMPLS_PPzZI_H |
| 4023 | 2307021789565378137ULL, // CMPLS_PPzZI_S |
| 4024 | 289391564317302361ULL, // CMPLS_WIDE_PPzZZ_B |
| 4025 | 19272378330717785ULL, // CMPLS_WIDE_PPzZZ_H |
| 4026 | 289409156503395929ULL, // CMPLS_WIDE_PPzZZ_S |
| 4027 | 1161188165591206ULL, // CMPLT_PPzZI_B |
| 4028 | 1169984258629798ULL, // CMPLT_PPzZI_D |
| 4029 | 450492042651443366ULL, // CMPLT_PPzZI_H |
| 4030 | 1178780351684774ULL, // CMPLT_PPzZI_S |
| 4031 | 289391564317302950ULL, // CMPLT_WIDE_PPzZZ_B |
| 4032 | 19272378330718374ULL, // CMPLT_WIDE_PPzZZ_H |
| 4033 | 289409156503396518ULL, // CMPLT_WIDE_PPzZZ_S |
| 4034 | 1161188165586250ULL, // CMPNE_PPzZI_B |
| 4035 | 1169984258624842ULL, // CMPNE_PPzZI_D |
| 4036 | 450492042651438410ULL, // CMPNE_PPzZI_H |
| 4037 | 1178780351679818ULL, // CMPNE_PPzZI_S |
| 4038 | 145276376241442122ULL, // CMPNE_PPzZZ_B |
| 4039 | 289400360410336586ULL, // CMPNE_PPzZZ_D |
| 4040 | 439233043583012170ULL, // CMPNE_PPzZZ_H |
| 4041 | 577639532655103306ULL, // CMPNE_PPzZZ_S |
| 4042 | 289391564317297994ULL, // CMPNE_WIDE_PPzZZ_B |
| 4043 | 19272378330713418ULL, // CMPNE_WIDE_PPzZZ_H |
| 4044 | 289409156503391562ULL, // CMPNE_WIDE_PPzZZ_S |
| 4045 | 7996302742888970ULL, // CMTSTv16i8 |
| 4046 | 61984970138122ULL, // CMTSTv1i64 |
| 4047 | 9122237011567114ULL, // CMTSTv2i32 |
| 4048 | 2366700133655050ULL, // CMTSTv2i64 |
| 4049 | 10248171282342410ULL, // CMTSTv4i16 |
| 4050 | 3492634404430346ULL, // CMTSTv4i32 |
| 4051 | 4618568673108490ULL, // CMTSTv8i16 |
| 4052 | 11374105555214858ULL, // CMTSTv8i8 |
| 4053 | 34630312381ULL, // CNOT_ZPmZ_B |
| 4054 | 8830723350973ULL, // CNOT_ZPmZ_D |
| 4055 | 17661446660541ULL, // CNOT_ZPmZ_H |
| 4056 | 26422909428157ULL, // CNOT_ZPmZ_S |
| 4057 | 35288258748861ULL, // CNOT_ZPzZ_B |
| 4058 | 44084351787453ULL, // CNOT_ZPzZ_D |
| 4059 | 17730705105341ULL, // CNOT_ZPzZ_H |
| 4060 | 52880444842429ULL, // CNOT_ZPzZ_S |
| 4061 | 1519078361659ULL, // CNTB_XPiI |
| 4062 | 1519078362290ULL, // CNTD_XPiI |
| 4063 | 1519078363446ULL, // CNTH_XPiI |
| 4064 | 7518313103ULL, // CNTP_XCI_B |
| 4065 | 7786748559ULL, // CNTP_XCI_D |
| 4066 | 8055184015ULL, // CNTP_XCI_H |
| 4067 | 8323619471ULL, // CNTP_XCI_S |
| 4068 | 35597496375951ULL, // CNTP_XPP_B |
| 4069 | 44393589398159ULL, // CNTP_XPP_D |
| 4070 | 97170147531407ULL, // CNTP_XPP_H |
| 4071 | 53189682420367ULL, // CNTP_XPP_S |
| 4072 | 1519078368485ULL, // CNTW_XPiI |
| 4073 | 2121991ULL, // CNTWr |
| 4074 | 2121991ULL, // CNTXr |
| 4075 | 34630312199ULL, // CNT_ZPmZ_B |
| 4076 | 8830723350791ULL, // CNT_ZPmZ_D |
| 4077 | 17661446660359ULL, // CNT_ZPmZ_H |
| 4078 | 26422909427975ULL, // CNT_ZPmZ_S |
| 4079 | 35288258748679ULL, // CNT_ZPzZ_B |
| 4080 | 44084351787271ULL, // CNT_ZPzZ_D |
| 4081 | 17730705105159ULL, // CNT_ZPzZ_H |
| 4082 | 52880444842247ULL, // CNT_ZPzZ_S |
| 4083 | 173149364487ULL, // CNTv16i8 |
| 4084 | 379320377607ULL, // CNTv8i8 |
| 4085 | 35597496393540ULL, // COMPACT_ZPZ_B |
| 4086 | 44393589432132ULL, // COMPACT_ZPZ_D |
| 4087 | 17732047281988ULL, // COMPACT_ZPZ_H |
| 4088 | 53189682487108ULL, // COMPACT_ZPZ_S |
| 4089 | 436279ULL, // CPYE |
| 4090 | 436361ULL, // CPYEN |
| 4091 | 436467ULL, // CPYERN |
| 4092 | 437427ULL, // CPYERT |
| 4093 | 436873ULL, // CPYERTN |
| 4094 | 436589ULL, // CPYERTRN |
| 4095 | 437120ULL, // CPYERTWN |
| 4096 | 437321ULL, // CPYET |
| 4097 | 436755ULL, // CPYETN |
| 4098 | 436525ULL, // CPYETRN |
| 4099 | 437056ULL, // CPYETWN |
| 4100 | 436998ULL, // CPYEWN |
| 4101 | 437484ULL, // CPYEWT |
| 4102 | 436936ULL, // CPYEWTN |
| 4103 | 436658ULL, // CPYEWTRN |
| 4104 | 437189ULL, // CPYEWTWN |
| 4105 | 436247ULL, // CPYFE |
| 4106 | 436325ULL, // CPYFEN |
| 4107 | 436457ULL, // CPYFERN |
| 4108 | 437417ULL, // CPYFERT |
| 4109 | 436862ULL, // CPYFERTN |
| 4110 | 436577ULL, // CPYFERTRN |
| 4111 | 437108ULL, // CPYFERTWN |
| 4112 | 437285ULL, // CPYFET |
| 4113 | 436715ULL, // CPYFETN |
| 4114 | 436514ULL, // CPYFETRN |
| 4115 | 437045ULL, // CPYFETWN |
| 4116 | 436988ULL, // CPYFEWN |
| 4117 | 437474ULL, // CPYFEWT |
| 4118 | 436925ULL, // CPYFEWTN |
| 4119 | 436646ULL, // CPYFEWTRN |
| 4120 | 437177ULL, // CPYFEWTWN |
| 4121 | 436286ULL, // CPYFM |
| 4122 | 436369ULL, // CPYFMN |
| 4123 | 436476ULL, // CPYFMRN |
| 4124 | 437436ULL, // CPYFMRT |
| 4125 | 436883ULL, // CPYFMRTN |
| 4126 | 436600ULL, // CPYFMRTRN |
| 4127 | 437131ULL, // CPYFMRTWN |
| 4128 | 437329ULL, // CPYFMT |
| 4129 | 436764ULL, // CPYFMTN |
| 4130 | 436535ULL, // CPYFMTRN |
| 4131 | 437066ULL, // CPYFMTWN |
| 4132 | 437007ULL, // CPYFMWN |
| 4133 | 437493ULL, // CPYFMWT |
| 4134 | 436946ULL, // CPYFMWTN |
| 4135 | 436669ULL, // CPYFMWTRN |
| 4136 | 437200ULL, // CPYFMWTWN |
| 4137 | 437246ULL, // CPYFP |
| 4138 | 436413ULL, // CPYFPN |
| 4139 | 436495ULL, // CPYFPRN |
| 4140 | 437455ULL, // CPYFPRT |
| 4141 | 436904ULL, // CPYFPRTN |
| 4142 | 436623ULL, // CPYFPRTRN |
| 4143 | 437154ULL, // CPYFPRTWN |
| 4144 | 437373ULL, // CPYFPT |
| 4145 | 436813ULL, // CPYFPTN |
| 4146 | 436556ULL, // CPYFPTRN |
| 4147 | 437087ULL, // CPYFPTWN |
| 4148 | 437026ULL, // CPYFPWN |
| 4149 | 437512ULL, // CPYFPWT |
| 4150 | 436967ULL, // CPYFPWTN |
| 4151 | 436692ULL, // CPYFPWTRN |
| 4152 | 437223ULL, // CPYFPWTWN |
| 4153 | 436318ULL, // CPYM |
| 4154 | 436405ULL, // CPYMN |
| 4155 | 436486ULL, // CPYMRN |
| 4156 | 437446ULL, // CPYMRT |
| 4157 | 436894ULL, // CPYMRTN |
| 4158 | 436612ULL, // CPYMRTRN |
| 4159 | 437143ULL, // CPYMRTWN |
| 4160 | 437365ULL, // CPYMT |
| 4161 | 436804ULL, // CPYMTN |
| 4162 | 436546ULL, // CPYMTRN |
| 4163 | 437077ULL, // CPYMTWN |
| 4164 | 437017ULL, // CPYMWN |
| 4165 | 437503ULL, // CPYMWT |
| 4166 | 436957ULL, // CPYMWTN |
| 4167 | 436681ULL, // CPYMWTRN |
| 4168 | 437212ULL, // CPYMWTWN |
| 4169 | 437278ULL, // CPYP |
| 4170 | 436449ULL, // CPYPN |
| 4171 | 436505ULL, // CPYPRN |
| 4172 | 437465ULL, // CPYPRT |
| 4173 | 436915ULL, // CPYPRTN |
| 4174 | 436635ULL, // CPYPRTRN |
| 4175 | 437166ULL, // CPYPRTWN |
| 4176 | 437409ULL, // CPYPT |
| 4177 | 436853ULL, // CPYPTN |
| 4178 | 436567ULL, // CPYPTRN |
| 4179 | 437098ULL, // CPYPTWN |
| 4180 | 437036ULL, // CPYPWN |
| 4181 | 437522ULL, // CPYPWT |
| 4182 | 436978ULL, // CPYPWTN |
| 4183 | 436704ULL, // CPYPWTRN |
| 4184 | 437235ULL, // CPYPWTWN |
| 4185 | 413451002357157ULL, // CPY_ZPmI_B |
| 4186 | 422247095395749ULL, // CPY_ZPmI_D |
| 4187 | 1546729366949ULL, // CPY_ZPmI_H |
| 4188 | 431043188450725ULL, // CPY_ZPmI_S |
| 4189 | 387062723290533ULL, // CPY_ZPmR_B |
| 4190 | 387062723306917ULL, // CPY_ZPmR_D |
| 4191 | 19173275149733ULL, // CPY_ZPmR_H |
| 4192 | 387062723339685ULL, // CPY_ZPmR_S |
| 4193 | 387062723290533ULL, // CPY_ZPmV_B |
| 4194 | 387062723306917ULL, // CPY_ZPmV_D |
| 4195 | 19173275149733ULL, // CPY_ZPmV_H |
| 4196 | 387062723339685ULL, // CPY_ZPmV_S |
| 4197 | 439908537771429ULL, // CPY_ZPzI_B |
| 4198 | 448704630810021ULL, // CPY_ZPzI_D |
| 4199 | 1615987811749ULL, // CPY_ZPzI_H |
| 4200 | 457500723864997ULL, // CPY_ZPzI_S |
| 4201 | 61984970130889ULL, // CRC32Brr |
| 4202 | 61984970131092ULL, // CRC32CBrr |
| 4203 | 61984970133241ULL, // CRC32CHrr |
| 4204 | 61984970138678ULL, // CRC32CWrr |
| 4205 | 61984970138973ULL, // CRC32CXrr |
| 4206 | 61984970133077ULL, // CRC32Hrr |
| 4207 | 61984970138620ULL, // CRC32Wrr |
| 4208 | 61984970138877ULL, // CRC32Xrr |
| 4209 | 1586454953711391826ULL, // CSELWr |
| 4210 | 1586454953711391826ULL, // CSELXr |
| 4211 | 1586454953711389476ULL, // CSINCWr |
| 4212 | 1586454953711389476ULL, // CSINCXr |
| 4213 | 1586454953711395644ULL, // CSINVWr |
| 4214 | 1586454953711395644ULL, // CSINVXr |
| 4215 | 1586454953711390201ULL, // CSNEGWr |
| 4216 | 1586454953711390201ULL, // CSNEGXr |
| 4217 | 2120520ULL, // CTERMEQ_WW |
| 4218 | 2120520ULL, // CTERMEQ_XX |
| 4219 | 2116929ULL, // CTERMNE_WW |
| 4220 | 2116929ULL, // CTERMNE_XX |
| 4221 | 2123270ULL, // CTZWr |
| 4222 | 2123270ULL, // CTZXr |
| 4223 | 376933ULL, // DCPS1 |
| 4224 | 377410ULL, // DCPS2 |
| 4225 | 377484ULL, // DCPS3 |
| 4226 | 8592049823ULL, // DECB_XPiI |
| 4227 | 8592051168ULL, // DECD_XPiI |
| 4228 | 8592083936ULL, // DECD_ZPiI |
| 4229 | 8592051972ULL, // DECH_XPiI |
| 4230 | 54595332ULL, // DECH_ZPiI |
| 4231 | 3491780918ULL, // DECP_XP_B |
| 4232 | 2686474550ULL, // DECP_XP_D |
| 4233 | 2149603638ULL, // DECP_XP_H |
| 4234 | 3760216374ULL, // DECP_XP_S |
| 4235 | 1612765494ULL, // DECP_ZP_D |
| 4236 | 4875950390ULL, // DECP_ZP_H |
| 4237 | 1881233718ULL, // DECP_ZP_S |
| 4238 | 8592057409ULL, // DECW_XPiI |
| 4239 | 8592122945ULL, // DECW_ZPiI |
| 4240 | 444546ULL, // DMB |
| 4241 | 11643ULL, // DRPS |
| 4242 | 444896ULL, // DSB |
| 4243 | 461280ULL, // DSBnXS |
| 4244 | 8860522434ULL, // DUPM_ZI |
| 4245 | 1652759239526ULL, // DUPQ_ZZI_B |
| 4246 | 1651953949542ULL, // DUPQ_ZZI_D |
| 4247 | 9154141030ULL, // DUPQ_ZZI_H |
| 4248 | 1653027724134ULL, // DUPQ_ZZI_S |
| 4249 | 9397377715ULL, // DUP_ZI_B |
| 4250 | 9665829555ULL, // DUP_ZI_D |
| 4251 | 56695475ULL, // DUP_ZI_H |
| 4252 | 9934297779ULL, // DUP_ZI_S |
| 4253 | 2136755ULL, // DUP_ZR_B |
| 4254 | 2153139ULL, // DUP_ZR_D |
| 4255 | 4890630835ULL, // DUP_ZR_H |
| 4256 | 2185907ULL, // DUP_ZR_S |
| 4257 | 1652759239347ULL, // DUP_ZZI_B |
| 4258 | 1651953949363ULL, // DUP_ZZI_D |
| 4259 | 9154140851ULL, // DUP_ZZI_H |
| 4260 | 9188104883ULL, // DUP_ZZI_Q |
| 4261 | 1653027723955ULL, // DUP_ZZI_S |
| 4262 | 467877901656900ULL, // DUPi16 |
| 4263 | 467912261395268ULL, // DUPi32 |
| 4264 | 467946621133636ULL, // DUPi64 |
| 4265 | 467980980872004ULL, // DUPi8 |
| 4266 | 8493747ULL, // DUPv16i8gpr |
| 4267 | 467980987243187ULL, // DUPv16i8lane |
| 4268 | 10590899ULL, // DUPv2i32gpr |
| 4269 | 467912269863603ULL, // DUPv2i32lane |
| 4270 | 12688051ULL, // DUPv2i64gpr |
| 4271 | 467946631699123ULL, // DUPv2i64lane |
| 4272 | 14785203ULL, // DUPv4i16gpr |
| 4273 | 467877914319539ULL, // DUPv4i16lane |
| 4274 | 16882355ULL, // DUPv4i32gpr |
| 4275 | 467912276155059ULL, // DUPv4i32lane |
| 4276 | 18979507ULL, // DUPv8i16gpr |
| 4277 | 467877918513843ULL, // DUPv8i16lane |
| 4278 | 21076659ULL, // DUPv8i8gpr |
| 4279 | 467980999826099ULL, // DUPv8i8lane |
| 4280 | 149945900357690ULL, // EONWrs |
| 4281 | 149945900357690ULL, // EONXrs |
| 4282 | 740957142097429126ULL, // EOR3 |
| 4283 | 289400671527027334ULL, // EOR3_ZZZZ |
| 4284 | 18801758347069ULL, // EORBT_ZZZ_B |
| 4285 | 9210022649661ULL, // EORBT_ZZZ_D |
| 4286 | 17663365553981ULL, // EORBT_ZZZ_H |
| 4287 | 26802477162301ULL, // EORBT_ZZZ_S |
| 4288 | 35597502751638ULL, // EORQV_VPZ_B |
| 4289 | 44393599968150ULL, // EORQV_VPZ_D |
| 4290 | 97170164392854ULL, // EORQV_VPZ_H |
| 4291 | 53189697184662ULL, // EORQV_VPZ_S |
| 4292 | 145276376241446597ULL, // EORS_PPzPP |
| 4293 | 18801758341705ULL, // EORTB_ZZZ_B |
| 4294 | 9210022644297ULL, // EORTB_ZZZ_D |
| 4295 | 17663365548617ULL, // EORTB_ZZZ_H |
| 4296 | 26802477156937ULL, // EORTB_ZZZ_S |
| 4297 | 254901ULL, // EORV_VPZ_B |
| 4298 | 4874052533ULL, // EORV_VPZ_D |
| 4299 | 4876166069ULL, // EORV_VPZ_H |
| 4300 | 4857308085ULL, // EORV_VPZ_S |
| 4301 | 343459946847407ULL, // EORWri |
| 4302 | 149945900358831ULL, // EORWrs |
| 4303 | 352256039869615ULL, // EORXri |
| 4304 | 149945900358831ULL, // EORXrs |
| 4305 | 145276376241446063ULL, // EOR_PPzPP |
| 4306 | 352258724256943ULL, // EOR_ZI |
| 4307 | 145276307521969327ULL, // EOR_ZPmZ_B |
| 4308 | 289400291690863791ULL, // EOR_ZPmZ_D |
| 4309 | 439233043046145199ULL, // EOR_ZPmZ_H |
| 4310 | 577639463935630511ULL, // EOR_ZPmZ_S |
| 4311 | 44395468479663ULL, // EOR_ZZZ |
| 4312 | 7996302742887599ULL, // EORv16i8 |
| 4313 | 11374105555213487ULL, // EORv8i8 |
| 4314 | 11648ULL, // ERET |
| 4315 | 11547ULL, // ERETAA |
| 4316 | 11554ULL, // ERETAB |
| 4317 | 35597496388743ULL, // EXPAND_ZPZ_B |
| 4318 | 44393589427335ULL, // EXPAND_ZPZ_D |
| 4319 | 17732047277191ULL, // EXPAND_ZPZ_H |
| 4320 | 53189682482311ULL, // EXPAND_ZPZ_S |
| 4321 | 1161500087589740ULL, // EXTQ_ZZI |
| 4322 | 475023653504329ULL, // EXTRACT_ZPMXI_H_B |
| 4323 | 475023653520713ULL, // EXTRACT_ZPMXI_H_D |
| 4324 | 1821607265609ULL, // EXTRACT_ZPMXI_H_H |
| 4325 | 1821607675209ULL, // EXTRACT_ZPMXI_H_Q |
| 4326 | 475023653553481ULL, // EXTRACT_ZPMXI_H_S |
| 4327 | 483819746526537ULL, // EXTRACT_ZPMXI_V_B |
| 4328 | 483819746542921ULL, // EXTRACT_ZPMXI_V_D |
| 4329 | 1855967003977ULL, // EXTRACT_ZPMXI_V_H |
| 4330 | 1855967413577ULL, // EXTRACT_ZPMXI_V_Q |
| 4331 | 483819746575689ULL, // EXTRACT_ZPMXI_V_S |
| 4332 | 1187884876979464ULL, // EXTRWrri |
| 4333 | 1187884876979464ULL, // EXTRXrri |
| 4334 | 2307004509301285487ULL, // EXT_ZZI |
| 4335 | 1899988296303ULL, // EXT_ZZI_B |
| 4336 | 20381201718157935ULL, // EXTv16i8 |
| 4337 | 32766203785224815ULL, // EXTv8i8 |
| 4338 | 379318277798ULL, // F1CVTL |
| 4339 | 173159842191ULL, // F1CVTL2 |
| 4340 | 4880146664ULL, // F1CVTLT_ZZ_BtoH |
| 4341 | 4880258726ULL, // F1CVTL_2ZZ_BtoH |
| 4342 | 4880261668ULL, // F1CVT_2ZZ_BtoH |
| 4343 | 4880146980ULL, // F1CVT_ZZ_BtoH |
| 4344 | 379318277807ULL, // F2CVTL |
| 4345 | 173159842201ULL, // F2CVTL2 |
| 4346 | 4880146674ULL, // F2CVTLT_ZZ_BtoH |
| 4347 | 4880258735ULL, // F2CVTL_2ZZ_BtoH |
| 4348 | 4880261676ULL, // F2CVT_2ZZ_BtoH |
| 4349 | 4880146988ULL, // F2CVT_ZZ_BtoH |
| 4350 | 61984970132421ULL, // FABD16 |
| 4351 | 61984970132421ULL, // FABD32 |
| 4352 | 61984970132421ULL, // FABD64 |
| 4353 | 289400291690859461ULL, // FABD_ZPmZ_D |
| 4354 | 439233043046140869ULL, // FABD_ZPmZ_H |
| 4355 | 577639463935626181ULL, // FABD_ZPmZ_S |
| 4356 | 9122237011561413ULL, // FABDv2f32 |
| 4357 | 2366700133649349ULL, // FABDv2f64 |
| 4358 | 10248171282336709ULL, // FABDv4f16 |
| 4359 | 3492634404424645ULL, // FABDv4f32 |
| 4360 | 4618568673102789ULL, // FABDv8f16 |
| 4361 | 2121154ULL, // FABSDr |
| 4362 | 2121154ULL, // FABSHr |
| 4363 | 2121154ULL, // FABSSr |
| 4364 | 8830723349954ULL, // FABS_ZPmZ_D |
| 4365 | 17661446659522ULL, // FABS_ZPmZ_H |
| 4366 | 26422909427138ULL, // FABS_ZPmZ_S |
| 4367 | 44084351786434ULL, // FABS_ZPzZ_D |
| 4368 | 17730705104322ULL, // FABS_ZPzZ_H |
| 4369 | 52880444841410ULL, // FABS_ZPzZ_S |
| 4370 | 207511199170ULL, // FABSv2f32 |
| 4371 | 241873034690ULL, // FABSv2f64 |
| 4372 | 276234870210ULL, // FABSv4f16 |
| 4373 | 310596705730ULL, // FABSv4f32 |
| 4374 | 344958541250ULL, // FABSv8f16 |
| 4375 | 61984970132697ULL, // FACGE16 |
| 4376 | 61984970132697ULL, // FACGE32 |
| 4377 | 61984970132697ULL, // FACGE64 |
| 4378 | 289400360410336473ULL, // FACGE_PPzZZ_D |
| 4379 | 439233043583012057ULL, // FACGE_PPzZZ_H |
| 4380 | 577639532655103193ULL, // FACGE_PPzZZ_S |
| 4381 | 9122237011561689ULL, // FACGEv2f32 |
| 4382 | 2366700133649625ULL, // FACGEv2f64 |
| 4383 | 10248171282336985ULL, // FACGEv4f16 |
| 4384 | 3492634404424921ULL, // FACGEv4f32 |
| 4385 | 4618568673103065ULL, // FACGEv8f16 |
| 4386 | 61984970137477ULL, // FACGT16 |
| 4387 | 61984970137477ULL, // FACGT32 |
| 4388 | 61984970137477ULL, // FACGT64 |
| 4389 | 289400360410341253ULL, // FACGT_PPzZZ_D |
| 4390 | 439233043583016837ULL, // FACGT_PPzZZ_H |
| 4391 | 577639532655107973ULL, // FACGT_PPzZZ_S |
| 4392 | 9122237011566469ULL, // FACGTv2f32 |
| 4393 | 2366700133654405ULL, // FACGTv2f64 |
| 4394 | 10248171282341765ULL, // FACGTv4f16 |
| 4395 | 3492634404429701ULL, // FACGTv4f32 |
| 4396 | 4618568673107845ULL, // FACGTv8f16 |
| 4397 | 63177516ULL, // FADDA_VPZ_D |
| 4398 | 17663386731308ULL, // FADDA_VPZ_H |
| 4399 | 67404588ULL, // FADDA_VPZ_S |
| 4400 | 61984970132503ULL, // FADDDrr |
| 4401 | 61984970132503ULL, // FADDHrr |
| 4402 | 289400291690862932ULL, // FADDP_ZPmZZ_D |
| 4403 | 439233043046144340ULL, // FADDP_ZPmZZ_H |
| 4404 | 577639463935629652ULL, // FADDP_ZPmZZ_S |
| 4405 | 9122237011564884ULL, // FADDPv2f32 |
| 4406 | 2366700133652820ULL, // FADDPv2f64 |
| 4407 | 1925489645908ULL, // FADDPv2i16p |
| 4408 | 207502727508ULL, // FADDPv2i32p |
| 4409 | 241862465876ULL, // FADDPv2i64p |
| 4410 | 10248171282340180ULL, // FADDPv4f16 |
| 4411 | 3492634404428116ULL, // FADDPv4f32 |
| 4412 | 4618568673106260ULL, // FADDPv8f16 |
| 4413 | 44393599968091ULL, // FADDQV_D |
| 4414 | 97170164392795ULL, // FADDQV_H |
| 4415 | 53189697184603ULL, // FADDQV_S |
| 4416 | 61984970132503ULL, // FADDSrr |
| 4417 | 4874052307ULL, // FADDV_VPZ_D |
| 4418 | 4876165843ULL, // FADDV_VPZ_H |
| 4419 | 4857307859ULL, // FADDV_VPZ_S |
| 4420 | 18455244000279ULL, // FADD_VG2_M2Z_D |
| 4421 | 18627042839575ULL, // FADD_VG2_M2Z_H |
| 4422 | 18489603755031ULL, // FADD_VG2_M2Z_S |
| 4423 | 18455512435735ULL, // FADD_VG4_M4Z_D |
| 4424 | 18627311275031ULL, // FADD_VG4_M4Z_H |
| 4425 | 18489872190487ULL, // FADD_VG4_M4Z_S |
| 4426 | 2451128112828697623ULL, // FADD_ZPmI_D |
| 4427 | 33909076582796311ULL, // FADD_ZPmI_H |
| 4428 | 2451136908921752599ULL, // FADD_ZPmI_S |
| 4429 | 289400291690859543ULL, // FADD_ZPmZ_D |
| 4430 | 439233043046140951ULL, // FADD_ZPmZ_H |
| 4431 | 577639463935626263ULL, // FADD_ZPmZ_S |
| 4432 | 44395468475415ULL, // FADD_ZZZ_D |
| 4433 | 17732068248599ULL, // FADD_ZZZ_H |
| 4434 | 53192635272215ULL, // FADD_ZZZ_S |
| 4435 | 9122237011561495ULL, // FADDv2f32 |
| 4436 | 2366700133649431ULL, // FADDv2f64 |
| 4437 | 10248171282336791ULL, // FADDv4f16 |
| 4438 | 3492634404424727ULL, // FADDv4f32 |
| 4439 | 4618568673102871ULL, // FADDv8f16 |
| 4440 | 19553138681119ULL, // FAMAX_2Z2Z_D |
| 4441 | 18659787597087ULL, // FAMAX_2Z2Z_H |
| 4442 | 19587502646559ULL, // FAMAX_2Z2Z_S |
| 4443 | 19553138681119ULL, // FAMAX_4Z4Z_D |
| 4444 | 18659787597087ULL, // FAMAX_4Z4Z_H |
| 4445 | 19587502646559ULL, // FAMAX_4Z4Z_S |
| 4446 | 289400291690865951ULL, // FAMAX_ZPmZ_D |
| 4447 | 439233043046147359ULL, // FAMAX_ZPmZ_H |
| 4448 | 577639463935632671ULL, // FAMAX_ZPmZ_S |
| 4449 | 9122237011567903ULL, // FAMAXv2f32 |
| 4450 | 2366700133655839ULL, // FAMAXv2f64 |
| 4451 | 10248171282343199ULL, // FAMAXv4f16 |
| 4452 | 3492634404431135ULL, // FAMAXv4f32 |
| 4453 | 4618568673109279ULL, // FAMAXv8f16 |
| 4454 | 19553138677749ULL, // FAMIN_2Z2Z_D |
| 4455 | 18659787593717ULL, // FAMIN_2Z2Z_H |
| 4456 | 19587502643189ULL, // FAMIN_2Z2Z_S |
| 4457 | 19553138677749ULL, // FAMIN_4Z4Z_D |
| 4458 | 18659787593717ULL, // FAMIN_4Z4Z_H |
| 4459 | 19587502643189ULL, // FAMIN_4Z4Z_S |
| 4460 | 289400291690862581ULL, // FAMIN_ZPmZ_D |
| 4461 | 439233043046143989ULL, // FAMIN_ZPmZ_H |
| 4462 | 577639463935629301ULL, // FAMIN_ZPmZ_S |
| 4463 | 9122237011564533ULL, // FAMINv2f32 |
| 4464 | 2366700133652469ULL, // FAMINv2f64 |
| 4465 | 10248171282339829ULL, // FAMINv4f16 |
| 4466 | 3492634404427765ULL, // FAMINv4f32 |
| 4467 | 4618568673105909ULL, // FAMINv8f16 |
| 4468 | 289400291690859518ULL, // FCADD_ZPmZ_D |
| 4469 | 1736269735728843774ULL, // FCADD_ZPmZ_H |
| 4470 | 577639463935626238ULL, // FCADD_ZPmZ_S |
| 4471 | 1476169815627500542ULL, // FCADDv2f32 |
| 4472 | 1477295578097486846ULL, // FCADDv2f64 |
| 4473 | 1478421649805118462ULL, // FCADDv4f16 |
| 4474 | 1479547412275104766ULL, // FCADDv4f32 |
| 4475 | 1480673346543782910ULL, // FCADDv8f16 |
| 4476 | 1586454953711393207ULL, // FCCMPDrr |
| 4477 | 1586454953711390057ULL, // FCCMPEDrr |
| 4478 | 1586454953711390057ULL, // FCCMPEHrr |
| 4479 | 1586454953711390057ULL, // FCCMPESrr |
| 4480 | 1586454953711393207ULL, // FCCMPHrr |
| 4481 | 1586454953711393207ULL, // FCCMPSrr |
| 4482 | 2029682596255ULL, // FCLAMP_VG2_2Z2Z_D |
| 4483 | 17663365667231ULL, // FCLAMP_VG2_2Z2Z_H |
| 4484 | 517837363615ULL, // FCLAMP_VG2_2Z2Z_S |
| 4485 | 2029682596255ULL, // FCLAMP_VG4_4Z4Z_D |
| 4486 | 17663365667231ULL, // FCLAMP_VG4_4Z4Z_H |
| 4487 | 517837363615ULL, // FCLAMP_VG4_4Z4Z_S |
| 4488 | 9210022648223ULL, // FCLAMP_ZZZ_D |
| 4489 | 17663365552543ULL, // FCLAMP_ZZZ_H |
| 4490 | 26802477160863ULL, // FCLAMP_ZZZ_S |
| 4491 | 61984970136385ULL, // FCMEQ16 |
| 4492 | 61984970136385ULL, // FCMEQ32 |
| 4493 | 61984970136385ULL, // FCMEQ64 |
| 4494 | 40576480998120257ULL, // FCMEQ_PPzZ0_D |
| 4495 | 492719728302913ULL, // FCMEQ_PPzZ0_H |
| 4496 | 40585277091175233ULL, // FCMEQ_PPzZ0_S |
| 4497 | 289400360410340161ULL, // FCMEQ_PPzZZ_D |
| 4498 | 439233043583015745ULL, // FCMEQ_PPzZZ_H |
| 4499 | 577639532655106881ULL, // FCMEQ_PPzZZ_S |
| 4500 | 2061586422593ULL, // FCMEQv1i16rz |
| 4501 | 2061586422593ULL, // FCMEQv1i32rz |
| 4502 | 2061586422593ULL, // FCMEQv1i64rz |
| 4503 | 9122237011565377ULL, // FCMEQv2f32 |
| 4504 | 2366700133653313ULL, // FCMEQv2f64 |
| 4505 | 2097296808769ULL, // FCMEQv2i32rz |
| 4506 | 2131658644289ULL, // FCMEQv2i64rz |
| 4507 | 10248171282340673ULL, // FCMEQv4f16 |
| 4508 | 3492634404428609ULL, // FCMEQv4f32 |
| 4509 | 2166020479809ULL, // FCMEQv4i16rz |
| 4510 | 2200382315329ULL, // FCMEQv4i32rz |
| 4511 | 4618568673106753ULL, // FCMEQv8f16 |
| 4512 | 2234744150849ULL, // FCMEQv8i16rz |
| 4513 | 61984970132720ULL, // FCMGE16 |
| 4514 | 61984970132720ULL, // FCMGE32 |
| 4515 | 61984970132720ULL, // FCMGE64 |
| 4516 | 40576480998116592ULL, // FCMGE_PPzZ0_D |
| 4517 | 492719728299248ULL, // FCMGE_PPzZ0_H |
| 4518 | 40585277091171568ULL, // FCMGE_PPzZ0_S |
| 4519 | 289400360410336496ULL, // FCMGE_PPzZZ_D |
| 4520 | 439233043583012080ULL, // FCMGE_PPzZZ_H |
| 4521 | 577639532655103216ULL, // FCMGE_PPzZZ_S |
| 4522 | 2061586418928ULL, // FCMGEv1i16rz |
| 4523 | 2061586418928ULL, // FCMGEv1i32rz |
| 4524 | 2061586418928ULL, // FCMGEv1i64rz |
| 4525 | 9122237011561712ULL, // FCMGEv2f32 |
| 4526 | 2366700133649648ULL, // FCMGEv2f64 |
| 4527 | 2097296805104ULL, // FCMGEv2i32rz |
| 4528 | 2131658640624ULL, // FCMGEv2i64rz |
| 4529 | 10248171282337008ULL, // FCMGEv4f16 |
| 4530 | 3492634404424944ULL, // FCMGEv4f32 |
| 4531 | 2166020476144ULL, // FCMGEv4i16rz |
| 4532 | 2200382311664ULL, // FCMGEv4i32rz |
| 4533 | 4618568673103088ULL, // FCMGEv8f16 |
| 4534 | 2234744147184ULL, // FCMGEv8i16rz |
| 4535 | 61984970137500ULL, // FCMGT16 |
| 4536 | 61984970137500ULL, // FCMGT32 |
| 4537 | 61984970137500ULL, // FCMGT64 |
| 4538 | 40576480998121372ULL, // FCMGT_PPzZ0_D |
| 4539 | 492719728304028ULL, // FCMGT_PPzZ0_H |
| 4540 | 40585277091176348ULL, // FCMGT_PPzZ0_S |
| 4541 | 289400360410341276ULL, // FCMGT_PPzZZ_D |
| 4542 | 439233043583016860ULL, // FCMGT_PPzZZ_H |
| 4543 | 577639532655107996ULL, // FCMGT_PPzZZ_S |
| 4544 | 2061586423708ULL, // FCMGTv1i16rz |
| 4545 | 2061586423708ULL, // FCMGTv1i32rz |
| 4546 | 2061586423708ULL, // FCMGTv1i64rz |
| 4547 | 9122237011566492ULL, // FCMGTv2f32 |
| 4548 | 2366700133654428ULL, // FCMGTv2f64 |
| 4549 | 2097296809884ULL, // FCMGTv2i32rz |
| 4550 | 2131658645404ULL, // FCMGTv2i64rz |
| 4551 | 10248171282341788ULL, // FCMGTv4f16 |
| 4552 | 3492634404429724ULL, // FCMGTv4f32 |
| 4553 | 2166020480924ULL, // FCMGTv4i16rz |
| 4554 | 2200382316444ULL, // FCMGTv4i32rz |
| 4555 | 4618568673107868ULL, // FCMGTv8f16 |
| 4556 | 2234744151964ULL, // FCMGTv8i16rz |
| 4557 | 2595208116532462446ULL, // FCMLA_ZPmZZ_D |
| 4558 | 1756535865332532078ULL, // FCMLA_ZPmZZ_H |
| 4559 | 2739340896794395502ULL, // FCMLA_ZPmZZ_S |
| 4560 | 1874992851979404142ULL, // FCMLA_ZZZI_H |
| 4561 | 1754178857337963374ULL, // FCMLA_ZZZI_S |
| 4562 | 2052639365903025006ULL, // FCMLAv2f32 |
| 4563 | 2053765128373011310ULL, // FCMLAv2f64 |
| 4564 | 2054891200080642926ULL, // FCMLAv4f16 |
| 4565 | 1034825884481225582ULL, // FCMLAv4f16_indexed |
| 4566 | 2056016962550629230ULL, // FCMLAv4f32 |
| 4567 | 1050588345740165998ULL, // FCMLAv4f32_indexed |
| 4568 | 2057142896819307374ULL, // FCMLAv8f16 |
| 4569 | 1034825781406204782ULL, // FCMLAv8f16_indexed |
| 4570 | 40576480998116632ULL, // FCMLE_PPzZ0_D |
| 4571 | 492719728299288ULL, // FCMLE_PPzZ0_H |
| 4572 | 40585277091171608ULL, // FCMLE_PPzZ0_S |
| 4573 | 2061586418968ULL, // FCMLEv1i16rz |
| 4574 | 2061586418968ULL, // FCMLEv1i32rz |
| 4575 | 2061586418968ULL, // FCMLEv1i64rz |
| 4576 | 2097296805144ULL, // FCMLEv2i32rz |
| 4577 | 2131658640664ULL, // FCMLEv2i64rz |
| 4578 | 2166020476184ULL, // FCMLEv4i16rz |
| 4579 | 2200382311704ULL, // FCMLEv4i32rz |
| 4580 | 2234744147224ULL, // FCMLEv8i16rz |
| 4581 | 40576480998121631ULL, // FCMLT_PPzZ0_D |
| 4582 | 492719728304287ULL, // FCMLT_PPzZ0_H |
| 4583 | 40585277091176607ULL, // FCMLT_PPzZ0_S |
| 4584 | 2061586423967ULL, // FCMLTv1i16rz |
| 4585 | 2061586423967ULL, // FCMLTv1i32rz |
| 4586 | 2061586423967ULL, // FCMLTv1i64rz |
| 4587 | 2097296810143ULL, // FCMLTv2i32rz |
| 4588 | 2131658645663ULL, // FCMLTv2i64rz |
| 4589 | 2166020481183ULL, // FCMLTv4i16rz |
| 4590 | 2200382316703ULL, // FCMLTv4i32rz |
| 4591 | 2234744152223ULL, // FCMLTv8i16rz |
| 4592 | 40576480998116666ULL, // FCMNE_PPzZ0_D |
| 4593 | 492719728299322ULL, // FCMNE_PPzZ0_H |
| 4594 | 40585277091171642ULL, // FCMNE_PPzZ0_S |
| 4595 | 289400360410336570ULL, // FCMNE_PPzZZ_D |
| 4596 | 439233043583012154ULL, // FCMNE_PPzZZ_H |
| 4597 | 577639532655103290ULL, // FCMNE_PPzZZ_S |
| 4598 | 69228990ULL, // FCMPDri |
| 4599 | 2120126ULL, // FCMPDrr |
| 4600 | 69225841ULL, // FCMPEDri |
| 4601 | 2116977ULL, // FCMPEDrr |
| 4602 | 69225841ULL, // FCMPEHri |
| 4603 | 2116977ULL, // FCMPEHrr |
| 4604 | 69225841ULL, // FCMPESri |
| 4605 | 2116977ULL, // FCMPESrr |
| 4606 | 69228990ULL, // FCMPHri |
| 4607 | 2120126ULL, // FCMPHrr |
| 4608 | 69228990ULL, // FCMPSri |
| 4609 | 2120126ULL, // FCMPSrr |
| 4610 | 289400360410339607ULL, // FCMUO_PPzZZ_D |
| 4611 | 439233043583015191ULL, // FCMUO_PPzZZ_H |
| 4612 | 577639532655106327ULL, // FCMUO_PPzZZ_S |
| 4613 | 501411932595620ULL, // FCPY_ZPmI_D |
| 4614 | 2268283872676ULL, // FCPY_ZPmI_H |
| 4615 | 501411932628388ULL, // FCPY_ZPmI_S |
| 4616 | 1586454953711391825ULL, // FCSELDrrr |
| 4617 | 1586454953711391825ULL, // FCSELHrrr |
| 4618 | 1586454953711391825ULL, // FCSELSrrr |
| 4619 | 2121146ULL, // FCVTASDHr |
| 4620 | 2121146ULL, // FCVTASDSr |
| 4621 | 2121146ULL, // FCVTASSDr |
| 4622 | 2121146ULL, // FCVTASSHr |
| 4623 | 2121146ULL, // FCVTASUWDr |
| 4624 | 2121146ULL, // FCVTASUWHr |
| 4625 | 2121146ULL, // FCVTASUWSr |
| 4626 | 2121146ULL, // FCVTASUXDr |
| 4627 | 2121146ULL, // FCVTASUXHr |
| 4628 | 2121146ULL, // FCVTASUXSr |
| 4629 | 2121146ULL, // FCVTASv1f16 |
| 4630 | 2121146ULL, // FCVTASv1i32 |
| 4631 | 2121146ULL, // FCVTASv1i64 |
| 4632 | 207511199162ULL, // FCVTASv2f32 |
| 4633 | 241873034682ULL, // FCVTASv2f64 |
| 4634 | 276234870202ULL, // FCVTASv4f16 |
| 4635 | 310596705722ULL, // FCVTASv4f32 |
| 4636 | 344958541242ULL, // FCVTASv8f16 |
| 4637 | 2122369ULL, // FCVTAUDHr |
| 4638 | 2122369ULL, // FCVTAUDSr |
| 4639 | 2122369ULL, // FCVTAUSDr |
| 4640 | 2122369ULL, // FCVTAUSHr |
| 4641 | 2122369ULL, // FCVTAUUWDr |
| 4642 | 2122369ULL, // FCVTAUUWHr |
| 4643 | 2122369ULL, // FCVTAUUWSr |
| 4644 | 2122369ULL, // FCVTAUUXDr |
| 4645 | 2122369ULL, // FCVTAUUXHr |
| 4646 | 2122369ULL, // FCVTAUUXSr |
| 4647 | 2122369ULL, // FCVTAUv1f16 |
| 4648 | 2122369ULL, // FCVTAUv1i32 |
| 4649 | 2122369ULL, // FCVTAUv1i64 |
| 4650 | 207511200385ULL, // FCVTAUv2f32 |
| 4651 | 241873035905ULL, // FCVTAUv2f64 |
| 4652 | 276234871425ULL, // FCVTAUv4f16 |
| 4653 | 310596706945ULL, // FCVTAUv4f32 |
| 4654 | 344958542465ULL, // FCVTAUv8f16 |
| 4655 | 2122292ULL, // FCVTDHr |
| 4656 | 2122292ULL, // FCVTDSr |
| 4657 | 2122292ULL, // FCVTHDr |
| 4658 | 2122292ULL, // FCVTHSr |
| 4659 | 105587746627835ULL, // FCVTLT_ZPmZ_HtoS |
| 4660 | 26422909395195ULL, // FCVTLT_ZPmZ_StoD |
| 4661 | 96860909953275ULL, // FCVTLT_ZPzZ_HtoS |
| 4662 | 52880444809467ULL, // FCVTLT_ZPzZ_StoD |
| 4663 | 4859303607ULL, // FCVTL_2ZZ_H_S |
| 4664 | 207513294519ULL, // FCVTLv2i32 |
| 4665 | 276236965559ULL, // FCVTLv4i16 |
| 4666 | 310592504226ULL, // FCVTLv4i32 |
| 4667 | 344956436898ULL, // FCVTLv8i16 |
| 4668 | 2121312ULL, // FCVTMSDHr |
| 4669 | 2121312ULL, // FCVTMSDSr |
| 4670 | 2121312ULL, // FCVTMSSDr |
| 4671 | 2121312ULL, // FCVTMSSHr |
| 4672 | 2121312ULL, // FCVTMSUWDr |
| 4673 | 2121312ULL, // FCVTMSUWHr |
| 4674 | 2121312ULL, // FCVTMSUWSr |
| 4675 | 2121312ULL, // FCVTMSUXDr |
| 4676 | 2121312ULL, // FCVTMSUXHr |
| 4677 | 2121312ULL, // FCVTMSUXSr |
| 4678 | 2121312ULL, // FCVTMSv1f16 |
| 4679 | 2121312ULL, // FCVTMSv1i32 |
| 4680 | 2121312ULL, // FCVTMSv1i64 |
| 4681 | 207511199328ULL, // FCVTMSv2f32 |
| 4682 | 241873034848ULL, // FCVTMSv2f64 |
| 4683 | 276234870368ULL, // FCVTMSv4f16 |
| 4684 | 310596705888ULL, // FCVTMSv4f32 |
| 4685 | 344958541408ULL, // FCVTMSv8f16 |
| 4686 | 2122385ULL, // FCVTMUDHr |
| 4687 | 2122385ULL, // FCVTMUDSr |
| 4688 | 2122385ULL, // FCVTMUSDr |
| 4689 | 2122385ULL, // FCVTMUSHr |
| 4690 | 2122385ULL, // FCVTMUUWDr |
| 4691 | 2122385ULL, // FCVTMUUWHr |
| 4692 | 2122385ULL, // FCVTMUUWSr |
| 4693 | 2122385ULL, // FCVTMUUXDr |
| 4694 | 2122385ULL, // FCVTMUUXHr |
| 4695 | 2122385ULL, // FCVTMUUXSr |
| 4696 | 2122385ULL, // FCVTMUv1f16 |
| 4697 | 2122385ULL, // FCVTMUv1i32 |
| 4698 | 2122385ULL, // FCVTMUv1i64 |
| 4699 | 207511200401ULL, // FCVTMUv2f32 |
| 4700 | 241873035921ULL, // FCVTMUv2f64 |
| 4701 | 276234871441ULL, // FCVTMUv4f16 |
| 4702 | 310596706961ULL, // FCVTMUv4f32 |
| 4703 | 344958542481ULL, // FCVTMUv8f16 |
| 4704 | 10471114961ULL, // FCVTNB_Z2Z_StoB |
| 4705 | 2121338ULL, // FCVTNSDHr |
| 4706 | 2121338ULL, // FCVTNSDSr |
| 4707 | 2121338ULL, // FCVTNSSDr |
| 4708 | 2121338ULL, // FCVTNSSHr |
| 4709 | 2121338ULL, // FCVTNSUWDr |
| 4710 | 2121338ULL, // FCVTNSUWHr |
| 4711 | 2121338ULL, // FCVTNSUWSr |
| 4712 | 2121338ULL, // FCVTNSUXDr |
| 4713 | 2121338ULL, // FCVTNSUXHr |
| 4714 | 2121338ULL, // FCVTNSUXSr |
| 4715 | 2121338ULL, // FCVTNSv1f16 |
| 4716 | 2121338ULL, // FCVTNSv1i32 |
| 4717 | 2121338ULL, // FCVTNSv1i64 |
| 4718 | 207511199354ULL, // FCVTNSv2f32 |
| 4719 | 241873034874ULL, // FCVTNSv2f64 |
| 4720 | 276234870394ULL, // FCVTNSv4f16 |
| 4721 | 310596705914ULL, // FCVTNSv4f32 |
| 4722 | 344958541434ULL, // FCVTNSv8f16 |
| 4723 | 10739556683ULL, // FCVTNT_Z2Z_StoB |
| 4724 | 8830723383627ULL, // FCVTNT_ZPmZ_DtoS |
| 4725 | 515937214795ULL, // FCVTNT_ZPmZ_StoH |
| 4726 | 8899442860363ULL, // FCVTNT_ZPzZ_DtoS |
| 4727 | 516474085707ULL, // FCVTNT_ZPzZ_StoH |
| 4728 | 2122393ULL, // FCVTNUDHr |
| 4729 | 2122393ULL, // FCVTNUDSr |
| 4730 | 2122393ULL, // FCVTNUSDr |
| 4731 | 2122393ULL, // FCVTNUSHr |
| 4732 | 2122393ULL, // FCVTNUUWDr |
| 4733 | 2122393ULL, // FCVTNUUWHr |
| 4734 | 2122393ULL, // FCVTNUUWSr |
| 4735 | 2122393ULL, // FCVTNUUXDr |
| 4736 | 2122393ULL, // FCVTNUUXHr |
| 4737 | 2122393ULL, // FCVTNUUXSr |
| 4738 | 2122393ULL, // FCVTNUv1f16 |
| 4739 | 2122393ULL, // FCVTNUv1i32 |
| 4740 | 2122393ULL, // FCVTNUv1i64 |
| 4741 | 207511200409ULL, // FCVTNUv2f32 |
| 4742 | 241873035929ULL, // FCVTNUv2f64 |
| 4743 | 276234871449ULL, // FCVTNUv4f16 |
| 4744 | 310596706969ULL, // FCVTNUv4f32 |
| 4745 | 344958542489ULL, // FCVTNUv8f16 |
| 4746 | 4618568662620280ULL, // FCVTN_F16v16f8 |
| 4747 | 10248171288631416ULL, // FCVTN_F16v8f8 |
| 4748 | 3501432368136681ULL, // FCVTN_F322v16f8 |
| 4749 | 3492634408622200ULL, // FCVTN_F32v8f8 |
| 4750 | 5370845304ULL, // FCVTN_Z2Z_HtoB |
| 4751 | 4867561592ULL, // FCVTN_Z2Z_StoH |
| 4752 | 10471118968ULL, // FCVTN_Z4Z_StoB |
| 4753 | 241870936184ULL, // FCVTNv2i32 |
| 4754 | 310594607224ULL, // FCVTNv4i16 |
| 4755 | 243756302825ULL, // FCVTNv4i32 |
| 4756 | 312477876713ULL, // FCVTNv8i16 |
| 4757 | 2121392ULL, // FCVTPSDHr |
| 4758 | 2121392ULL, // FCVTPSDSr |
| 4759 | 2121392ULL, // FCVTPSSDr |
| 4760 | 2121392ULL, // FCVTPSSHr |
| 4761 | 2121392ULL, // FCVTPSUWDr |
| 4762 | 2121392ULL, // FCVTPSUWHr |
| 4763 | 2121392ULL, // FCVTPSUWSr |
| 4764 | 2121392ULL, // FCVTPSUXDr |
| 4765 | 2121392ULL, // FCVTPSUXHr |
| 4766 | 2121392ULL, // FCVTPSUXSr |
| 4767 | 2121392ULL, // FCVTPSv1f16 |
| 4768 | 2121392ULL, // FCVTPSv1i32 |
| 4769 | 2121392ULL, // FCVTPSv1i64 |
| 4770 | 207511199408ULL, // FCVTPSv2f32 |
| 4771 | 241873034928ULL, // FCVTPSv2f64 |
| 4772 | 276234870448ULL, // FCVTPSv4f16 |
| 4773 | 310596705968ULL, // FCVTPSv4f32 |
| 4774 | 344958541488ULL, // FCVTPSv8f16 |
| 4775 | 2122401ULL, // FCVTPUDHr |
| 4776 | 2122401ULL, // FCVTPUDSr |
| 4777 | 2122401ULL, // FCVTPUSDr |
| 4778 | 2122401ULL, // FCVTPUSHr |
| 4779 | 2122401ULL, // FCVTPUUWDr |
| 4780 | 2122401ULL, // FCVTPUUWHr |
| 4781 | 2122401ULL, // FCVTPUUWSr |
| 4782 | 2122401ULL, // FCVTPUUXDr |
| 4783 | 2122401ULL, // FCVTPUUXHr |
| 4784 | 2122401ULL, // FCVTPUUXSr |
| 4785 | 2122401ULL, // FCVTPUv1f16 |
| 4786 | 2122401ULL, // FCVTPUv1i32 |
| 4787 | 2122401ULL, // FCVTPUv1i64 |
| 4788 | 207511200417ULL, // FCVTPUv2f32 |
| 4789 | 241873035937ULL, // FCVTPUv2f64 |
| 4790 | 276234871457ULL, // FCVTPUv4f16 |
| 4791 | 310596706977ULL, // FCVTPUv4f32 |
| 4792 | 344958542497ULL, // FCVTPUv8f16 |
| 4793 | 2122292ULL, // FCVTSDr |
| 4794 | 2122292ULL, // FCVTSHr |
| 4795 | 8830723383681ULL, // FCVTXNT_ZPmZ_DtoS |
| 4796 | 8899442860417ULL, // FCVTXNT_ZPzZ_StoD |
| 4797 | 2119888ULL, // FCVTXNv1i64 |
| 4798 | 241870936272ULL, // FCVTXNv2f32 |
| 4799 | 243756302879ULL, // FCVTXNv4f32 |
| 4800 | 8830723384724ULL, // FCVTX_ZPmZ_DtoS |
| 4801 | 44084351821204ULL, // FCVTX_ZPzZ_DtoS |
| 4802 | 2121451ULL, // FCVTZSDHr |
| 4803 | 2121451ULL, // FCVTZSDSr |
| 4804 | 11008039014ULL, // FCVTZSN_Z2Z_DtoS |
| 4805 | 5370845286ULL, // FCVTZSN_Z2Z_HtoB |
| 4806 | 4867561574ULL, // FCVTZSN_Z2Z_StoH |
| 4807 | 2121451ULL, // FCVTZSSDr |
| 4808 | 2121451ULL, // FCVTZSSHr |
| 4809 | 61984970137323ULL, // FCVTZSSWDri |
| 4810 | 61984970137323ULL, // FCVTZSSWHri |
| 4811 | 61984970137323ULL, // FCVTZSSWSri |
| 4812 | 61984970137323ULL, // FCVTZSSXDri |
| 4813 | 61984970137323ULL, // FCVTZSSXHri |
| 4814 | 61984970137323ULL, // FCVTZSSXSri |
| 4815 | 2121451ULL, // FCVTZSUWDr |
| 4816 | 2121451ULL, // FCVTZSUWHr |
| 4817 | 2121451ULL, // FCVTZSUWSr |
| 4818 | 2121451ULL, // FCVTZSUXDr |
| 4819 | 2121451ULL, // FCVTZSUXHr |
| 4820 | 2121451ULL, // FCVTZSUXSr |
| 4821 | 4867694315ULL, // FCVTZS_2Z2Z_StoS |
| 4822 | 4867694315ULL, // FCVTZS_4Z4Z_StoS |
| 4823 | 8830723350251ULL, // FCVTZS_ZPmZ_DtoD |
| 4824 | 8830723383019ULL, // FCVTZS_ZPmZ_DtoS |
| 4825 | 105587746594539ULL, // FCVTZS_ZPmZ_HtoD |
| 4826 | 17661446659819ULL, // FCVTZS_ZPmZ_HtoH |
| 4827 | 105587746627307ULL, // FCVTZS_ZPmZ_HtoS |
| 4828 | 26422909394667ULL, // FCVTZS_ZPmZ_StoD |
| 4829 | 26422909427435ULL, // FCVTZS_ZPmZ_StoS |
| 4830 | 44084351786731ULL, // FCVTZS_ZPzZ_DtoD |
| 4831 | 44084351819499ULL, // FCVTZS_ZPzZ_DtoS |
| 4832 | 96860909919979ULL, // FCVTZS_ZPzZ_HtoD |
| 4833 | 17730705104619ULL, // FCVTZS_ZPzZ_HtoH |
| 4834 | 96860909952747ULL, // FCVTZS_ZPzZ_HtoS |
| 4835 | 52880444808939ULL, // FCVTZS_ZPzZ_StoD |
| 4836 | 52880444841707ULL, // FCVTZS_ZPzZ_StoS |
| 4837 | 61984970137323ULL, // FCVTZSd |
| 4838 | 61984970137323ULL, // FCVTZSh |
| 4839 | 61984970137323ULL, // FCVTZSs |
| 4840 | 2121451ULL, // FCVTZSv1f16 |
| 4841 | 2121451ULL, // FCVTZSv1i32 |
| 4842 | 2121451ULL, // FCVTZSv1i64 |
| 4843 | 207511199467ULL, // FCVTZSv2f32 |
| 4844 | 241873034987ULL, // FCVTZSv2f64 |
| 4845 | 62261198692075ULL, // FCVTZSv2i32_shift |
| 4846 | 62123761835755ULL, // FCVTZSv2i64_shift |
| 4847 | 276234870507ULL, // FCVTZSv4f16 |
| 4848 | 310596706027ULL, // FCVTZSv4f32 |
| 4849 | 62295562624747ULL, // FCVTZSv4i16_shift |
| 4850 | 62158125768427ULL, // FCVTZSv4i32_shift |
| 4851 | 344958541547ULL, // FCVTZSv8f16 |
| 4852 | 62192487603947ULL, // FCVTZSv8i16_shift |
| 4853 | 2122426ULL, // FCVTZUDHr |
| 4854 | 2122426ULL, // FCVTZUDSr |
| 4855 | 11008039105ULL, // FCVTZUN_Z2Z_DtoS |
| 4856 | 5370845377ULL, // FCVTZUN_Z2Z_HtoB |
| 4857 | 4867561665ULL, // FCVTZUN_Z2Z_StoH |
| 4858 | 2122426ULL, // FCVTZUSDr |
| 4859 | 2122426ULL, // FCVTZUSHr |
| 4860 | 61984970138298ULL, // FCVTZUSWDri |
| 4861 | 61984970138298ULL, // FCVTZUSWHri |
| 4862 | 61984970138298ULL, // FCVTZUSWSri |
| 4863 | 61984970138298ULL, // FCVTZUSXDri |
| 4864 | 61984970138298ULL, // FCVTZUSXHri |
| 4865 | 61984970138298ULL, // FCVTZUSXSri |
| 4866 | 2122426ULL, // FCVTZUUWDr |
| 4867 | 2122426ULL, // FCVTZUUWHr |
| 4868 | 2122426ULL, // FCVTZUUWSr |
| 4869 | 2122426ULL, // FCVTZUUXDr |
| 4870 | 2122426ULL, // FCVTZUUXHr |
| 4871 | 2122426ULL, // FCVTZUUXSr |
| 4872 | 4867695290ULL, // FCVTZU_2Z2Z_StoS |
| 4873 | 4867695290ULL, // FCVTZU_4Z4Z_StoS |
| 4874 | 8830723351226ULL, // FCVTZU_ZPmZ_DtoD |
| 4875 | 8830723383994ULL, // FCVTZU_ZPmZ_DtoS |
| 4876 | 105587746595514ULL, // FCVTZU_ZPmZ_HtoD |
| 4877 | 17661446660794ULL, // FCVTZU_ZPmZ_HtoH |
| 4878 | 105587746628282ULL, // FCVTZU_ZPmZ_HtoS |
| 4879 | 26422909395642ULL, // FCVTZU_ZPmZ_StoD |
| 4880 | 26422909428410ULL, // FCVTZU_ZPmZ_StoS |
| 4881 | 44084351787706ULL, // FCVTZU_ZPzZ_DtoD |
| 4882 | 44084351820474ULL, // FCVTZU_ZPzZ_DtoS |
| 4883 | 96860909920954ULL, // FCVTZU_ZPzZ_HtoD |
| 4884 | 17730705105594ULL, // FCVTZU_ZPzZ_HtoH |
| 4885 | 96860909953722ULL, // FCVTZU_ZPzZ_HtoS |
| 4886 | 52880444809914ULL, // FCVTZU_ZPzZ_StoD |
| 4887 | 52880444842682ULL, // FCVTZU_ZPzZ_StoS |
| 4888 | 61984970138298ULL, // FCVTZUd |
| 4889 | 61984970138298ULL, // FCVTZUh |
| 4890 | 61984970138298ULL, // FCVTZUs |
| 4891 | 2122426ULL, // FCVTZUv1f16 |
| 4892 | 2122426ULL, // FCVTZUv1i32 |
| 4893 | 2122426ULL, // FCVTZUv1i64 |
| 4894 | 207511200442ULL, // FCVTZUv2f32 |
| 4895 | 241873035962ULL, // FCVTZUv2f64 |
| 4896 | 62261198693050ULL, // FCVTZUv2i32_shift |
| 4897 | 62123761836730ULL, // FCVTZUv2i64_shift |
| 4898 | 276234871482ULL, // FCVTZUv4f16 |
| 4899 | 310596707002ULL, // FCVTZUv4f32 |
| 4900 | 62295562625722ULL, // FCVTZUv4i16_shift |
| 4901 | 62158125769402ULL, // FCVTZUv4i32_shift |
| 4902 | 344958542522ULL, // FCVTZUv8f16 |
| 4903 | 62192487604922ULL, // FCVTZUv8i16_shift |
| 4904 | 4859306548ULL, // FCVT_2ZZ_H_S |
| 4905 | 5370847796ULL, // FCVT_Z2Z_HtoB |
| 4906 | 4867564084ULL, // FCVT_Z2Z_StoH |
| 4907 | 10471121460ULL, // FCVT_Z4Z_StoB |
| 4908 | 2027765703220ULL, // FCVT_ZPmZ_DtoH |
| 4909 | 8830723383860ULL, // FCVT_ZPmZ_DtoS |
| 4910 | 105587746595380ULL, // FCVT_ZPmZ_HtoD |
| 4911 | 105587746628148ULL, // FCVT_ZPmZ_HtoS |
| 4912 | 26422909395508ULL, // FCVT_ZPmZ_StoD |
| 4913 | 515937215028ULL, // FCVT_ZPmZ_StoH |
| 4914 | 18417899872820ULL, // FCVT_ZPzZ_DtoH |
| 4915 | 44084351820340ULL, // FCVT_ZPzZ_DtoS |
| 4916 | 96860909920820ULL, // FCVT_ZPzZ_HtoD |
| 4917 | 96860909953588ULL, // FCVT_ZPzZ_HtoS |
| 4918 | 52880444809780ULL, // FCVT_ZPzZ_StoD |
| 4919 | 18074302489140ULL, // FCVT_ZPzZ_StoH |
| 4920 | 61984970138355ULL, // FDIVDrr |
| 4921 | 61984970138355ULL, // FDIVHrr |
| 4922 | 289400291690863913ULL, // FDIVR_ZPmZ_D |
| 4923 | 439233043046145321ULL, // FDIVR_ZPmZ_H |
| 4924 | 577639463935630633ULL, // FDIVR_ZPmZ_S |
| 4925 | 61984970138355ULL, // FDIVSrr |
| 4926 | 289400291690865395ULL, // FDIV_ZPmZ_D |
| 4927 | 439233043046146803ULL, // FDIV_ZPmZ_H |
| 4928 | 577639463935632115ULL, // FDIV_ZPmZ_S |
| 4929 | 9122237011567347ULL, // FDIVv2f32 |
| 4930 | 2366700133655283ULL, // FDIVv2f64 |
| 4931 | 10248171282342643ULL, // FDIVv4f16 |
| 4932 | 3492634404430579ULL, // FDIVv4f32 |
| 4933 | 4618568673108723ULL, // FDIVv8f16 |
| 4934 | 512479562408337ULL, // FDOT_VG2_M2Z2Z_BtoH |
| 4935 | 512479562277265ULL, // FDOT_VG2_M2Z2Z_BtoS |
| 4936 | 22650974388855185ULL, // FDOT_VG2_M2Z2Z_HtoS |
| 4937 | 43305472115450257ULL, // FDOT_VG2_M2ZZI_BtoH |
| 4938 | 43305472115319185ULL, // FDOT_VG2_M2ZZI_BtoS |
| 4939 | 888468002750833041ULL, // FDOT_VG2_M2ZZI_HtoS |
| 4940 | 521275655430545ULL, // FDOT_VG2_M2ZZ_BtoH |
| 4941 | 521275655299473ULL, // FDOT_VG2_M2ZZ_BtoS |
| 4942 | 456122438523265425ULL, // FDOT_VG2_M2ZZ_HtoS |
| 4943 | 512479830843793ULL, // FDOT_VG4_M4Z4Z_BtoH |
| 4944 | 512479830712721ULL, // FDOT_VG4_M4Z4Z_BtoS |
| 4945 | 22650974657290641ULL, // FDOT_VG4_M4Z4Z_HtoS |
| 4946 | 43305472383885713ULL, // FDOT_VG4_M4ZZI_BtoH |
| 4947 | 43305472383754641ULL, // FDOT_VG4_M4ZZI_BtoS |
| 4948 | 888468003019268497ULL, // FDOT_VG4_M4ZZI_HtoS |
| 4949 | 521275923866001ULL, // FDOT_VG4_M4ZZ_BtoH |
| 4950 | 521275923734929ULL, // FDOT_VG4_M4ZZ_BtoS |
| 4951 | 456122438791700881ULL, // FDOT_VG4_M4ZZ_HtoS |
| 4952 | 370640985072017ULL, // FDOT_ZZZI_BtoH |
| 4953 | 370645479285137ULL, // FDOT_ZZZI_BtoS |
| 4954 | 457221330566209937ULL, // FDOT_ZZZI_S |
| 4955 | 18797264183697ULL, // FDOT_ZZZ_BtoH |
| 4956 | 18801758396817ULL, // FDOT_ZZZ_BtoS |
| 4957 | 105968388104593ULL, // FDOT_ZZZ_S |
| 4958 | 44034000815268241ULL, // FDOTlanev2f32 |
| 4959 | 45159900726305169ULL, // FDOTlanev4f16 |
| 4960 | 21515968318677393ULL, // FDOTlanev4f16_v2f32 |
| 4961 | 44033897742344593ULL, // FDOTlanev4f32 |
| 4962 | 45159797651284369ULL, // FDOTlanev8f16 |
| 4963 | 21515865245753745ULL, // FDOTlanev8f16_v4f32 |
| 4964 | 11382903516832145ULL, // FDOTv2f32 |
| 4965 | 11382903521026449ULL, // FDOTv4f16 |
| 4966 | 10256969250251153ULL, // FDOTv4f16_v2f32 |
| 4967 | 8005100723380625ULL, // FDOTv4f32 |
| 4968 | 8005100725477777ULL, // FDOTv8f16 |
| 4969 | 4627366643114385ULL, // FDOTv8f16_v4f32 |
| 4970 | 11276442290ULL, // FDUP_ZI_D |
| 4971 | 73472690ULL, // FDUP_ZI_H |
| 4972 | 11276475058ULL, // FDUP_ZI_S |
| 4973 | 2686502055ULL, // FEXPA_ZZ_D |
| 4974 | 4859167911ULL, // FEXPA_ZZ_H |
| 4975 | 3760276647ULL, // FEXPA_ZZ_S |
| 4976 | 35597496375972ULL, // FIRSTP_XPP_B |
| 4977 | 44393589398180ULL, // FIRSTP_XPP_D |
| 4978 | 97170147531428ULL, // FIRSTP_XPP_H |
| 4979 | 53189682420388ULL, // FIRSTP_XPP_S |
| 4980 | 2121459ULL, // FJCVTZS |
| 4981 | 8830723344099ULL, // FLOGB_ZPmZ_D |
| 4982 | 17661446653667ULL, // FLOGB_ZPmZ_H |
| 4983 | 26422909421283ULL, // FLOGB_ZPmZ_S |
| 4984 | 44084351780579ULL, // FLOGB_ZPzZ_D |
| 4985 | 17730705098467ULL, // FLOGB_ZPzZ_H |
| 4986 | 52880444835555ULL, // FLOGB_ZPzZ_S |
| 4987 | 4890912483ULL, // FLTcc |
| 4988 | 1187884876975188ULL, // FMADDDrrr |
| 4989 | 1187884876975188ULL, // FMADDHrrr |
| 4990 | 1187884876975188ULL, // FMADDSrrr |
| 4991 | 2595208116532464561ULL, // FMAD_ZPmZZ_D |
| 4992 | 459499172649831345ULL, // FMAD_ZPmZZ_H |
| 4993 | 2739340896794397617ULL, // FMAD_ZPmZZ_S |
| 4994 | 61984970138921ULL, // FMAXDrr |
| 4995 | 61984970138921ULL, // FMAXHrr |
| 4996 | 61984970135442ULL, // FMAXNMDrr |
| 4997 | 61984970135442ULL, // FMAXNMHrr |
| 4998 | 289400291690863053ULL, // FMAXNMP_ZPmZZ_D |
| 4999 | 439233043046144461ULL, // FMAXNMP_ZPmZZ_H |
| 5000 | 577639463935629773ULL, // FMAXNMP_ZPmZZ_S |
| 5001 | 9122237011565005ULL, // FMAXNMPv2f32 |
| 5002 | 2366700133652941ULL, // FMAXNMPv2f64 |
| 5003 | 1925489646029ULL, // FMAXNMPv2i16p |
| 5004 | 207502727629ULL, // FMAXNMPv2i32p |
| 5005 | 241862465997ULL, // FMAXNMPv2i64p |
| 5006 | 10248171282340301ULL, // FMAXNMPv4f16 |
| 5007 | 3492634404428237ULL, // FMAXNMPv4f32 |
| 5008 | 4618568673106381ULL, // FMAXNMPv8f16 |
| 5009 | 44393599968116ULL, // FMAXNMQV_D |
| 5010 | 97170164392820ULL, // FMAXNMQV_H |
| 5011 | 53189697184628ULL, // FMAXNMQV_S |
| 5012 | 61984970135442ULL, // FMAXNMSrr |
| 5013 | 4874052382ULL, // FMAXNMV_VPZ_D |
| 5014 | 4876165918ULL, // FMAXNMV_VPZ_H |
| 5015 | 4857307934ULL, // FMAXNMV_VPZ_S |
| 5016 | 276222206750ULL, // FMAXNMVv4i16v |
| 5017 | 310581945118ULL, // FMAXNMVv4i32v |
| 5018 | 344941683486ULL, // FMAXNMVv8i16v |
| 5019 | 19553138677650ULL, // FMAXNM_VG2_2Z2Z_D |
| 5020 | 18659787593618ULL, // FMAXNM_VG2_2Z2Z_H |
| 5021 | 19587502643090ULL, // FMAXNM_VG2_2Z2Z_S |
| 5022 | 18419267311506ULL, // FMAXNM_VG2_2ZZ_D |
| 5023 | 17732074657682ULL, // FMAXNM_VG2_2ZZ_H |
| 5024 | 18075674154898ULL, // FMAXNM_VG2_2ZZ_S |
| 5025 | 19553138677650ULL, // FMAXNM_VG4_4Z4Z_D |
| 5026 | 18659787593618ULL, // FMAXNM_VG4_4Z4Z_H |
| 5027 | 19587502643090ULL, // FMAXNM_VG4_4Z4Z_S |
| 5028 | 18419267311506ULL, // FMAXNM_VG4_4ZZ_D |
| 5029 | 17732074657682ULL, // FMAXNM_VG4_4ZZ_H |
| 5030 | 18075674154898ULL, // FMAXNM_VG4_4ZZ_S |
| 5031 | 2883473677056268178ULL, // FMAXNM_ZPmI_D |
| 5032 | 46293975558068114ULL, // FMAXNM_ZPmI_H |
| 5033 | 2883482473149323154ULL, // FMAXNM_ZPmI_S |
| 5034 | 289400291690862482ULL, // FMAXNM_ZPmZ_D |
| 5035 | 439233043046143890ULL, // FMAXNM_ZPmZ_H |
| 5036 | 577639463935629202ULL, // FMAXNM_ZPmZ_S |
| 5037 | 9122237011564434ULL, // FMAXNMv2f32 |
| 5038 | 2366700133652370ULL, // FMAXNMv2f64 |
| 5039 | 10248171282339730ULL, // FMAXNMv4f16 |
| 5040 | 3492634404427666ULL, // FMAXNMv4f32 |
| 5041 | 4618568673105810ULL, // FMAXNMv8f16 |
| 5042 | 289400291690863312ULL, // FMAXP_ZPmZZ_D |
| 5043 | 439233043046144720ULL, // FMAXP_ZPmZZ_H |
| 5044 | 577639463935630032ULL, // FMAXP_ZPmZZ_S |
| 5045 | 9122237011565264ULL, // FMAXPv2f32 |
| 5046 | 2366700133653200ULL, // FMAXPv2f64 |
| 5047 | 1925489646288ULL, // FMAXPv2i16p |
| 5048 | 207502727888ULL, // FMAXPv2i32p |
| 5049 | 241862466256ULL, // FMAXPv2i64p |
| 5050 | 10248171282340560ULL, // FMAXPv4f16 |
| 5051 | 3492634404428496ULL, // FMAXPv4f32 |
| 5052 | 4618568673106640ULL, // FMAXPv8f16 |
| 5053 | 44393599968157ULL, // FMAXQV_D |
| 5054 | 97170164392861ULL, // FMAXQV_H |
| 5055 | 53189697184669ULL, // FMAXQV_S |
| 5056 | 61984970138921ULL, // FMAXSrr |
| 5057 | 4874052539ULL, // FMAXV_VPZ_D |
| 5058 | 4876166075ULL, // FMAXV_VPZ_H |
| 5059 | 4857308091ULL, // FMAXV_VPZ_S |
| 5060 | 276222206907ULL, // FMAXVv4i16v |
| 5061 | 310581945275ULL, // FMAXVv4i32v |
| 5062 | 344941683643ULL, // FMAXVv8i16v |
| 5063 | 19553138681129ULL, // FMAX_VG2_2Z2Z_D |
| 5064 | 18659787597097ULL, // FMAX_VG2_2Z2Z_H |
| 5065 | 19587502646569ULL, // FMAX_VG2_2Z2Z_S |
| 5066 | 18419267314985ULL, // FMAX_VG2_2ZZ_D |
| 5067 | 17732074661161ULL, // FMAX_VG2_2ZZ_H |
| 5068 | 18075674158377ULL, // FMAX_VG2_2ZZ_S |
| 5069 | 19553138681129ULL, // FMAX_VG4_4Z4Z_D |
| 5070 | 18659787597097ULL, // FMAX_VG4_4Z4Z_H |
| 5071 | 19587502646569ULL, // FMAX_VG4_4Z4Z_S |
| 5072 | 18419267314985ULL, // FMAX_VG4_4ZZ_D |
| 5073 | 17732074661161ULL, // FMAX_VG4_4ZZ_H |
| 5074 | 18075674158377ULL, // FMAX_VG4_4ZZ_S |
| 5075 | 2883473677056271657ULL, // FMAX_ZPmI_D |
| 5076 | 46293975558071593ULL, // FMAX_ZPmI_H |
| 5077 | 2883482473149326633ULL, // FMAX_ZPmI_S |
| 5078 | 289400291690865961ULL, // FMAX_ZPmZ_D |
| 5079 | 439233043046147369ULL, // FMAX_ZPmZ_H |
| 5080 | 577639463935632681ULL, // FMAX_ZPmZ_S |
| 5081 | 9122237011567913ULL, // FMAXv2f32 |
| 5082 | 2366700133655849ULL, // FMAXv2f64 |
| 5083 | 10248171282343209ULL, // FMAXv4f16 |
| 5084 | 3492634404431145ULL, // FMAXv4f32 |
| 5085 | 4618568673109289ULL, // FMAXv8f16 |
| 5086 | 61984970135551ULL, // FMINDrr |
| 5087 | 61984970135551ULL, // FMINHrr |
| 5088 | 61984970135400ULL, // FMINNMDrr |
| 5089 | 61984970135400ULL, // FMINNMHrr |
| 5090 | 289400291690863044ULL, // FMINNMP_ZPmZZ_D |
| 5091 | 439233043046144452ULL, // FMINNMP_ZPmZZ_H |
| 5092 | 577639463935629764ULL, // FMINNMP_ZPmZZ_S |
| 5093 | 9122237011564996ULL, // FMINNMPv2f32 |
| 5094 | 2366700133652932ULL, // FMINNMPv2f64 |
| 5095 | 1925489646020ULL, // FMINNMPv2i16p |
| 5096 | 207502727620ULL, // FMINNMPv2i32p |
| 5097 | 241862465988ULL, // FMINNMPv2i64p |
| 5098 | 10248171282340292ULL, // FMINNMPv4f16 |
| 5099 | 3492634404428228ULL, // FMINNMPv4f32 |
| 5100 | 4618568673106372ULL, // FMINNMPv8f16 |
| 5101 | 44393599968106ULL, // FMINNMQV_D |
| 5102 | 97170164392810ULL, // FMINNMQV_H |
| 5103 | 53189697184618ULL, // FMINNMQV_S |
| 5104 | 61984970135400ULL, // FMINNMSrr |
| 5105 | 4874052373ULL, // FMINNMV_VPZ_D |
| 5106 | 4876165909ULL, // FMINNMV_VPZ_H |
| 5107 | 4857307925ULL, // FMINNMV_VPZ_S |
| 5108 | 276222206741ULL, // FMINNMVv4i16v |
| 5109 | 310581945109ULL, // FMINNMVv4i32v |
| 5110 | 344941683477ULL, // FMINNMVv8i16v |
| 5111 | 19553138677608ULL, // FMINNM_VG2_2Z2Z_D |
| 5112 | 18659787593576ULL, // FMINNM_VG2_2Z2Z_H |
| 5113 | 19587502643048ULL, // FMINNM_VG2_2Z2Z_S |
| 5114 | 18419267311464ULL, // FMINNM_VG2_2ZZ_D |
| 5115 | 17732074657640ULL, // FMINNM_VG2_2ZZ_H |
| 5116 | 18075674154856ULL, // FMINNM_VG2_2ZZ_S |
| 5117 | 19553138677608ULL, // FMINNM_VG4_4Z4Z_D |
| 5118 | 18659787593576ULL, // FMINNM_VG4_4Z4Z_H |
| 5119 | 19587502643048ULL, // FMINNM_VG4_4Z4Z_S |
| 5120 | 18419267311464ULL, // FMINNM_VG4_4ZZ_D |
| 5121 | 17732074657640ULL, // FMINNM_VG4_4ZZ_H |
| 5122 | 18075674154856ULL, // FMINNM_VG4_4ZZ_S |
| 5123 | 2883473677056268136ULL, // FMINNM_ZPmI_D |
| 5124 | 46293975558068072ULL, // FMINNM_ZPmI_H |
| 5125 | 2883482473149323112ULL, // FMINNM_ZPmI_S |
| 5126 | 289400291690862440ULL, // FMINNM_ZPmZ_D |
| 5127 | 439233043046143848ULL, // FMINNM_ZPmZ_H |
| 5128 | 577639463935629160ULL, // FMINNM_ZPmZ_S |
| 5129 | 9122237011564392ULL, // FMINNMv2f32 |
| 5130 | 2366700133652328ULL, // FMINNMv2f64 |
| 5131 | 10248171282339688ULL, // FMINNMv4f16 |
| 5132 | 3492634404427624ULL, // FMINNMv4f32 |
| 5133 | 4618568673105768ULL, // FMINNMv8f16 |
| 5134 | 289400291690863068ULL, // FMINP_ZPmZZ_D |
| 5135 | 439233043046144476ULL, // FMINP_ZPmZZ_H |
| 5136 | 577639463935629788ULL, // FMINP_ZPmZZ_S |
| 5137 | 9122237011565020ULL, // FMINPv2f32 |
| 5138 | 2366700133652956ULL, // FMINPv2f64 |
| 5139 | 1925489646044ULL, // FMINPv2i16p |
| 5140 | 207502727644ULL, // FMINPv2i32p |
| 5141 | 241862466012ULL, // FMINPv2i64p |
| 5142 | 10248171282340316ULL, // FMINPv4f16 |
| 5143 | 3492634404428252ULL, // FMINPv4f32 |
| 5144 | 4618568673106396ULL, // FMINPv8f16 |
| 5145 | 44393599968126ULL, // FMINQV_D |
| 5146 | 97170164392830ULL, // FMINQV_H |
| 5147 | 53189697184638ULL, // FMINQV_S |
| 5148 | 61984970135551ULL, // FMINSrr |
| 5149 | 4874052391ULL, // FMINV_VPZ_D |
| 5150 | 4876165927ULL, // FMINV_VPZ_H |
| 5151 | 4857307943ULL, // FMINV_VPZ_S |
| 5152 | 276222206759ULL, // FMINVv4i16v |
| 5153 | 310581945127ULL, // FMINVv4i32v |
| 5154 | 344941683495ULL, // FMINVv8i16v |
| 5155 | 19553138677759ULL, // FMIN_VG2_2Z2Z_D |
| 5156 | 18659787593727ULL, // FMIN_VG2_2Z2Z_H |
| 5157 | 19587502643199ULL, // FMIN_VG2_2Z2Z_S |
| 5158 | 18419267311615ULL, // FMIN_VG2_2ZZ_D |
| 5159 | 17732074657791ULL, // FMIN_VG2_2ZZ_H |
| 5160 | 18075674155007ULL, // FMIN_VG2_2ZZ_S |
| 5161 | 19553138677759ULL, // FMIN_VG4_4Z4Z_D |
| 5162 | 18659787593727ULL, // FMIN_VG4_4Z4Z_H |
| 5163 | 19587502643199ULL, // FMIN_VG4_4Z4Z_S |
| 5164 | 18419267311615ULL, // FMIN_VG4_4ZZ_D |
| 5165 | 17732074657791ULL, // FMIN_VG4_4ZZ_H |
| 5166 | 18075674155007ULL, // FMIN_VG4_4ZZ_S |
| 5167 | 2883473677056268287ULL, // FMIN_ZPmI_D |
| 5168 | 46293975558068223ULL, // FMIN_ZPmI_H |
| 5169 | 2883482473149323263ULL, // FMIN_ZPmI_S |
| 5170 | 289400291690862591ULL, // FMIN_ZPmZ_D |
| 5171 | 439233043046143999ULL, // FMIN_ZPmZ_H |
| 5172 | 577639463935629311ULL, // FMIN_ZPmZ_S |
| 5173 | 9122237011564543ULL, // FMINv2f32 |
| 5174 | 2366700133652479ULL, // FMINv2f64 |
| 5175 | 10248171282339839ULL, // FMINv4f16 |
| 5176 | 3492634404427775ULL, // FMINv4f32 |
| 5177 | 4618568673105919ULL, // FMINv8f16 |
| 5178 | 530105275384050ULL, // FMLAL2lanev4f16 |
| 5179 | 1034825884483322098ULL, // FMLAL2lanev8f16 |
| 5180 | 538901368406258ULL, // FMLAL2v4f16 |
| 5181 | 10256969256534258ULL, // FMLAL2v8f16 |
| 5182 | 18797264176931ULL, // FMLALB_ZZZ |
| 5183 | 370640985065251ULL, // FMLALB_ZZZI |
| 5184 | 457221330566203171ULL, // FMLALB_ZZZI_SHH |
| 5185 | 105968388097827ULL, // FMLALB_ZZZ_SHH |
| 5186 | 47411597464962851ULL, // FMLALBlanev8f16 |
| 5187 | 8005100725471011ULL, // FMLALBv16i8_v8f16 |
| 5188 | 18801758389898ULL, // FMLALLBB_ZZZ |
| 5189 | 370645479278218ULL, // FMLALLBB_ZZZI |
| 5190 | 47411597462865546ULL, // FMLALLBBlanev4f32 |
| 5191 | 8005100723373706ULL, // FMLALLBBv4f32 |
| 5192 | 18801758396200ULL, // FMLALLBT_ZZZ |
| 5193 | 370645479284520ULL, // FMLALLBT_ZZZI |
| 5194 | 47411597462871848ULL, // FMLALLBTlanev4f32 |
| 5195 | 8005100723380008ULL, // FMLALLBTv4f32 |
| 5196 | 18801758390833ULL, // FMLALLTB_ZZZ |
| 5197 | 370645479279153ULL, // FMLALLTB_ZZZI |
| 5198 | 47411597462866481ULL, // FMLALLTBlanev4f32 |
| 5199 | 8005100723374641ULL, // FMLALLTBv4f32 |
| 5200 | 18801758396945ULL, // FMLALLTT_ZZZ |
| 5201 | 370645479285265ULL, // FMLALLTT_ZZZI |
| 5202 | 47411597462872593ULL, // FMLALLTTlanev4f32 |
| 5203 | 8005100723380753ULL, // FMLALLTTv4f32 |
| 5204 | 363016348734622ULL, // FMLALL_MZZI_BtoS |
| 5205 | 19968720868510ULL, // FMLALL_MZZ_BtoS |
| 5206 | 512479600022686ULL, // FMLALL_VG2_M2Z2Z_BtoS |
| 5207 | 43305472153064606ULL, // FMLALL_VG2_M2ZZI_BtoS |
| 5208 | 521283209237662ULL, // FMLALL_VG2_M2ZZ_BtoS |
| 5209 | 512479868458142ULL, // FMLALL_VG4_M4Z4Z_BtoS |
| 5210 | 43305472421500062ULL, // FMLALL_VG4_M4ZZI_BtoS |
| 5211 | 521283477673118ULL, // FMLALL_VG4_M4ZZ_BtoS |
| 5212 | 18797264183264ULL, // FMLALT_ZZZ |
| 5213 | 370640985071584ULL, // FMLALT_ZZZI |
| 5214 | 457221330566209504ULL, // FMLALT_ZZZI_SHH |
| 5215 | 105968388104160ULL, // FMLALT_ZZZ_SHH |
| 5216 | 47411597464969184ULL, // FMLALTlanev8f16 |
| 5217 | 8005100725477344ULL, // FMLALTv16i8_v8f16 |
| 5218 | 363016323699248ULL, // FMLAL_MZZI_BtoH |
| 5219 | 361745013248560ULL, // FMLAL_MZZI_HtoS |
| 5220 | 18697385382448ULL, // FMLAL_MZZ_HtoS |
| 5221 | 512479574987312ULL, // FMLAL_VG2_M2Z2Z_BtoH |
| 5222 | 22650974401434160ULL, // FMLAL_VG2_M2Z2Z_HtoS |
| 5223 | 43305472128029232ULL, // FMLAL_VG2_M2ZZI_BtoH |
| 5224 | 888468002763412016ULL, // FMLAL_VG2_M2ZZI_HtoS |
| 5225 | 521275668009520ULL, // FMLAL_VG2_M2ZZ_BtoH |
| 5226 | 456122438535844400ULL, // FMLAL_VG2_M2ZZ_HtoS |
| 5227 | 19968695833136ULL, // FMLAL_VG2_MZZ_BtoH |
| 5228 | 512479843422768ULL, // FMLAL_VG4_M4Z4Z_BtoH |
| 5229 | 22650974669869616ULL, // FMLAL_VG4_M4Z4Z_HtoS |
| 5230 | 43305472396464688ULL, // FMLAL_VG4_M4ZZI_BtoH |
| 5231 | 888468003031847472ULL, // FMLAL_VG4_M4ZZI_HtoS |
| 5232 | 521275936444976ULL, // FMLAL_VG4_M4ZZ_BtoH |
| 5233 | 456122438804279856ULL, // FMLAL_VG4_M4ZZ_HtoS |
| 5234 | 530105275388464ULL, // FMLALlanev4f16 |
| 5235 | 1034825884483326512ULL, // FMLALlanev8f16 |
| 5236 | 538901368410672ULL, // FMLALv4f16 |
| 5237 | 10256969256538672ULL, // FMLALv8f16 |
| 5238 | 13643603335398262ULL, // FMLA_VG2_M2Z2Z_D |
| 5239 | 22650974388978550ULL, // FMLA_VG2_M2Z2Z_H |
| 5240 | 14769537601995638ULL, // FMLA_VG2_M2Z2Z_S |
| 5241 | 880586531604218742ULL, // FMLA_VG2_M2ZZI_D |
| 5242 | 888468002750956406ULL, // FMLA_VG2_M2ZZI_H |
| 5243 | 881712465870816118ULL, // FMLA_VG2_M2ZZI_S |
| 5244 | 448240967376651126ULL, // FMLA_VG2_M2ZZ_D |
| 5245 | 456122438523388790ULL, // FMLA_VG2_M2ZZ_H |
| 5246 | 449366901643248502ULL, // FMLA_VG2_M2ZZ_S |
| 5247 | 13643603603833718ULL, // FMLA_VG4_M4Z4Z_D |
| 5248 | 22650974657414006ULL, // FMLA_VG4_M4Z4Z_H |
| 5249 | 14769537870431094ULL, // FMLA_VG4_M4Z4Z_S |
| 5250 | 880586531872654198ULL, // FMLA_VG4_M4ZZI_D |
| 5251 | 888468003019391862ULL, // FMLA_VG4_M4ZZI_H |
| 5252 | 881712466139251574ULL, // FMLA_VG4_M4ZZI_S |
| 5253 | 448240967645086582ULL, // FMLA_VG4_M4ZZ_D |
| 5254 | 456122438791824246ULL, // FMLA_VG4_M4ZZ_H |
| 5255 | 449366901911683958ULL, // FMLA_VG4_M4ZZ_S |
| 5256 | 2595208116532462454ULL, // FMLA_ZPmZZ_D |
| 5257 | 459499172649829238ULL, // FMLA_ZPmZZ_H |
| 5258 | 2739340896794395510ULL, // FMLA_ZPmZZ_S |
| 5259 | 457124572200747894ULL, // FMLA_ZZZI_D |
| 5260 | 369507086435190ULL, // FMLA_ZZZI_H |
| 5261 | 457142164655260534ULL, // FMLA_ZZZI_S |
| 5262 | 1034825577110225782ULL, // FMLAv1i16_indexed |
| 5263 | 1050588175806022518ULL, // FMLAv1i32_indexed |
| 5264 | 1057343575247078262ULL, // FMLAv1i64_indexed |
| 5265 | 9131034983662454ULL, // FMLAv2f32 |
| 5266 | 2375498105750390ULL, // FMLAv2f64 |
| 5267 | 1050588448813089654ULL, // FMLAv2i32_indexed |
| 5268 | 1057343710817289078ULL, // FMLAv2i64_indexed |
| 5269 | 10256969254437750ULL, // FMLAv4f16 |
| 5270 | 3501432376525686ULL, // FMLAv4f32 |
| 5271 | 1034825884481225590ULL, // FMLAv4i16_indexed |
| 5272 | 1050588345740166006ULL, // FMLAv4i32_indexed |
| 5273 | 4627366645203830ULL, // FMLAv8f16 |
| 5274 | 1034825781406204790ULL, // FMLAv8i16_indexed |
| 5275 | 105968388096893ULL, // FMLLA_ZZZ_HtoS |
| 5276 | 530105275384182ULL, // FMLSL2lanev4f16 |
| 5277 | 1034825884483322230ULL, // FMLSL2lanev8f16 |
| 5278 | 538901368406390ULL, // FMLSL2v4f16 |
| 5279 | 10256969256534390ULL, // FMLSL2v8f16 |
| 5280 | 457221330566203469ULL, // FMLSLB_ZZZI_SHH |
| 5281 | 105968388098125ULL, // FMLSLB_ZZZ_SHH |
| 5282 | 457221330566209735ULL, // FMLSLT_ZZZI_SHH |
| 5283 | 105968388104391ULL, // FMLSLT_ZZZ_SHH |
| 5284 | 361745013249631ULL, // FMLSL_MZZI_HtoS |
| 5285 | 18697385383519ULL, // FMLSL_MZZ_HtoS |
| 5286 | 22650974401435231ULL, // FMLSL_VG2_M2Z2Z_HtoS |
| 5287 | 888468002763413087ULL, // FMLSL_VG2_M2ZZI_HtoS |
| 5288 | 456122438535845471ULL, // FMLSL_VG2_M2ZZ_HtoS |
| 5289 | 22650974669870687ULL, // FMLSL_VG4_M4Z4Z_HtoS |
| 5290 | 888468003031848543ULL, // FMLSL_VG4_M4ZZI_HtoS |
| 5291 | 456122438804280927ULL, // FMLSL_VG4_M4ZZ_HtoS |
| 5292 | 530105275389535ULL, // FMLSLlanev4f16 |
| 5293 | 1034825884483327583ULL, // FMLSLlanev8f16 |
| 5294 | 538901368411743ULL, // FMLSLv4f16 |
| 5295 | 10256969256539743ULL, // FMLSLv8f16 |
| 5296 | 13643603335405132ULL, // FMLS_VG2_M2Z2Z_D |
| 5297 | 22650974388985420ULL, // FMLS_VG2_M2Z2Z_H |
| 5298 | 14769537602002508ULL, // FMLS_VG2_M2Z2Z_S |
| 5299 | 880586531604225612ULL, // FMLS_VG2_M2ZZI_D |
| 5300 | 888468002750963276ULL, // FMLS_VG2_M2ZZI_H |
| 5301 | 881712465870822988ULL, // FMLS_VG2_M2ZZI_S |
| 5302 | 448240967376657996ULL, // FMLS_VG2_M2ZZ_D |
| 5303 | 456122438523395660ULL, // FMLS_VG2_M2ZZ_H |
| 5304 | 449366901643255372ULL, // FMLS_VG2_M2ZZ_S |
| 5305 | 13643603603840588ULL, // FMLS_VG4_M4Z4Z_D |
| 5306 | 22650974657420876ULL, // FMLS_VG4_M4Z4Z_H |
| 5307 | 14769537870437964ULL, // FMLS_VG4_M4Z4Z_S |
| 5308 | 880586531872661068ULL, // FMLS_VG4_M4ZZI_D |
| 5309 | 888468003019398732ULL, // FMLS_VG4_M4ZZI_H |
| 5310 | 881712466139258444ULL, // FMLS_VG4_M4ZZI_S |
| 5311 | 448240967645093452ULL, // FMLS_VG4_M4ZZ_D |
| 5312 | 456122438791831116ULL, // FMLS_VG4_M4ZZ_H |
| 5313 | 449366901911690828ULL, // FMLS_VG4_M4ZZ_S |
| 5314 | 2595208116532469324ULL, // FMLS_ZPmZZ_D |
| 5315 | 459499172649836108ULL, // FMLS_ZPmZZ_H |
| 5316 | 2739340896794402380ULL, // FMLS_ZPmZZ_S |
| 5317 | 457124572200754764ULL, // FMLS_ZZZI_D |
| 5318 | 369507086442060ULL, // FMLS_ZZZI_H |
| 5319 | 457142164655267404ULL, // FMLS_ZZZI_S |
| 5320 | 1034825577110232652ULL, // FMLSv1i16_indexed |
| 5321 | 1050588175806029388ULL, // FMLSv1i32_indexed |
| 5322 | 1057343575247085132ULL, // FMLSv1i64_indexed |
| 5323 | 9131034983669324ULL, // FMLSv2f32 |
| 5324 | 2375498105757260ULL, // FMLSv2f64 |
| 5325 | 1050588448813096524ULL, // FMLSv2i32_indexed |
| 5326 | 1057343710817295948ULL, // FMLSv2i64_indexed |
| 5327 | 10256969254444620ULL, // FMLSv4f16 |
| 5328 | 3501432376532556ULL, // FMLSv4f32 |
| 5329 | 1034825884481232460ULL, // FMLSv4i16_indexed |
| 5330 | 1050588345740172876ULL, // FMLSv4i32_indexed |
| 5331 | 4627366645210700ULL, // FMLSv8f16 |
| 5332 | 1034825781406211660ULL, // FMLSv8i16_indexed |
| 5333 | 18797264175997ULL, // FMMLA_ZZZ_BtoH |
| 5334 | 18801758389117ULL, // FMMLA_ZZZ_BtoS |
| 5335 | 9210022642557ULL, // FMMLA_ZZZ_D |
| 5336 | 17663365546877ULL, // FMMLA_ZZZ_H |
| 5337 | 26802477155197ULL, // FMMLA_ZZZ_S |
| 5338 | 8005100723372925ULL, // FMMLAv4f32 |
| 5339 | 8005100725470077ULL, // FMMLAv8f16 |
| 5340 | 4627366643106685ULL, // FMMLAv8f16_v4f32 |
| 5341 | 4627366645203837ULL, // FMMLAv8f16_v8f16 |
| 5342 | 12157305568ULL, // FMOP4A_M2Z2Z_BtoH |
| 5343 | 12157305568ULL, // FMOP4A_M2Z2Z_BtoS |
| 5344 | 12427838176ULL, // FMOP4A_M2Z2Z_D |
| 5345 | 5958124256ULL, // FMOP4A_M2Z2Z_H |
| 5346 | 5958124256ULL, // FMOP4A_M2Z2Z_HtoS |
| 5347 | 12698370784ULL, // FMOP4A_M2Z2Z_S |
| 5348 | 12962611936ULL, // FMOP4A_M2ZZ_BtoH |
| 5349 | 12962611936ULL, // FMOP4A_M2ZZ_BtoS |
| 5350 | 13233144544ULL, // FMOP4A_M2ZZ_D |
| 5351 | 6226559712ULL, // FMOP4A_M2ZZ_H |
| 5352 | 6226559712ULL, // FMOP4A_M2ZZ_HtoS |
| 5353 | 13503677152ULL, // FMOP4A_M2ZZ_S |
| 5354 | 2407669023456ULL, // FMOP4A_MZ2Z_BtoH |
| 5355 | 2407669023456ULL, // FMOP4A_MZ2Z_BtoS |
| 5356 | 2441999401696ULL, // FMOP4A_MZ2Z_D |
| 5357 | 1136331440864ULL, // FMOP4A_MZ2Z_H |
| 5358 | 1136331440864ULL, // FMOP4A_MZ2Z_HtoS |
| 5359 | 2476342362848ULL, // FMOP4A_MZ2Z_S |
| 5360 | 18797264224992ULL, // FMOP4A_MZZ_BtoH |
| 5361 | 18797264224992ULL, // FMOP4A_MZZ_BtoS |
| 5362 | 2029682541280ULL, // FMOP4A_MZZ_D |
| 5363 | 17663365595872ULL, // FMOP4A_MZZ_H |
| 5364 | 17663365595872ULL, // FMOP4A_MZZ_HtoS |
| 5365 | 517837275872ULL, // FMOP4A_MZZ_S |
| 5366 | 12427844992ULL, // FMOP4S_M2Z2Z_D |
| 5367 | 5958131072ULL, // FMOP4S_M2Z2Z_H |
| 5368 | 5958131072ULL, // FMOP4S_M2Z2Z_HtoS |
| 5369 | 12698377600ULL, // FMOP4S_M2Z2Z_S |
| 5370 | 13233151360ULL, // FMOP4S_M2ZZ_D |
| 5371 | 6226566528ULL, // FMOP4S_M2ZZ_H |
| 5372 | 6226566528ULL, // FMOP4S_M2ZZ_HtoS |
| 5373 | 13503683968ULL, // FMOP4S_M2ZZ_S |
| 5374 | 2441999408512ULL, // FMOP4S_MZ2Z_D |
| 5375 | 1136331447680ULL, // FMOP4S_MZ2Z_H |
| 5376 | 1136331447680ULL, // FMOP4S_MZ2Z_HtoS |
| 5377 | 2476342369664ULL, // FMOP4S_MZ2Z_S |
| 5378 | 2029682548096ULL, // FMOP4S_MZZ_D |
| 5379 | 17663365602688ULL, // FMOP4S_MZZ_H |
| 5380 | 17663365602688ULL, // FMOP4S_MZZ_HtoS |
| 5381 | 517837282688ULL, // FMOP4S_MZZ_S |
| 5382 | 378679217734652ULL, // FMOPAL_MPPZZ |
| 5383 | 545804985156604ULL, // FMOPA_MPPZZ_BtoH |
| 5384 | 545804985156604ULL, // FMOPA_MPPZZ_BtoS |
| 5385 | 3027624461554795516ULL, // FMOPA_MPPZZ_D |
| 5386 | 378679217734652ULL, // FMOPA_MPPZZ_H |
| 5387 | 1298251000737547260ULL, // FMOPA_MPPZZ_S |
| 5388 | 378679217741465ULL, // FMOPSL_MPPZZ |
| 5389 | 3027624461554802329ULL, // FMOPS_MPPZZ_D |
| 5390 | 378679217741465ULL, // FMOPS_MPPZZ_H |
| 5391 | 1298251000737554073ULL, // FMOPS_MPPZZ_S |
| 5392 | 467946621133635ULL, // FMOVDXHighr |
| 5393 | 2122563ULL, // FMOVDXr |
| 5394 | 11276411715ULL, // FMOVDi |
| 5395 | 2122563ULL, // FMOVDr |
| 5396 | 2122563ULL, // FMOVHWr |
| 5397 | 2122563ULL, // FMOVHXr |
| 5398 | 11276411715ULL, // FMOVHi |
| 5399 | 2122563ULL, // FMOVHr |
| 5400 | 2122563ULL, // FMOVSWr |
| 5401 | 11276411715ULL, // FMOVSi |
| 5402 | 2122563ULL, // FMOVSr |
| 5403 | 2122563ULL, // FMOVWHr |
| 5404 | 2122563ULL, // FMOVWSr |
| 5405 | 83993411ULL, // FMOVXDHighr |
| 5406 | 2122563ULL, // FMOVXDr |
| 5407 | 2122563ULL, // FMOVXHr |
| 5408 | 11284882243ULL, // FMOVv2f32_ns |
| 5409 | 11286979395ULL, // FMOVv2f64_ns |
| 5410 | 11289076547ULL, // FMOVv4f16_ns |
| 5411 | 11291173699ULL, // FMOVv4f32_ns |
| 5412 | 11293270851ULL, // FMOVv8f16_ns |
| 5413 | 2595208116532464106ULL, // FMSB_ZPmZZ_D |
| 5414 | 459499172649830890ULL, // FMSB_ZPmZZ_H |
| 5415 | 2739340896794397162ULL, // FMSB_ZPmZZ_S |
| 5416 | 1187884876974713ULL, // FMSUBDrrr |
| 5417 | 1187884876974713ULL, // FMSUBHrrr |
| 5418 | 1187884876974713ULL, // FMSUBSrrr |
| 5419 | 61984970135231ULL, // FMULDrr |
| 5420 | 61984970135231ULL, // FMULHrr |
| 5421 | 61984970135231ULL, // FMULSrr |
| 5422 | 61984970139005ULL, // FMULX16 |
| 5423 | 61984970139005ULL, // FMULX32 |
| 5424 | 61984970139005ULL, // FMULX64 |
| 5425 | 289400291690866045ULL, // FMULX_ZPmZ_D |
| 5426 | 439233043046147453ULL, // FMULX_ZPmZ_H |
| 5427 | 577639463935632765ULL, // FMULX_ZPmZ_S |
| 5428 | 3196544597054481789ULL, // FMULXv1i16_indexed |
| 5429 | 3212307195750278525ULL, // FMULXv1i32_indexed |
| 5430 | 3219062595191334269ULL, // FMULXv1i64_indexed |
| 5431 | 9122237011567997ULL, // FMULXv2f32 |
| 5432 | 2366700133655933ULL, // FMULXv2f64 |
| 5433 | 3212307471978833277ULL, // FMULXv2i32_indexed |
| 5434 | 3219062733983032701ULL, // FMULXv2i64_indexed |
| 5435 | 10248171282343293ULL, // FMULXv4f16 |
| 5436 | 3492634404431229ULL, // FMULXv4f32 |
| 5437 | 3196544907646969213ULL, // FMULXv4i16_indexed |
| 5438 | 3212307368905909629ULL, // FMULXv4i32_indexed |
| 5439 | 4618568673109373ULL, // FMULXv8f16 |
| 5440 | 3196544804571948413ULL, // FMULXv8i16_indexed |
| 5441 | 19553138677439ULL, // FMUL_2Z2Z_D |
| 5442 | 18659787593407ULL, // FMUL_2Z2Z_H |
| 5443 | 19587502642879ULL, // FMUL_2Z2Z_S |
| 5444 | 18419267311295ULL, // FMUL_2ZZ_D |
| 5445 | 17732074657471ULL, // FMUL_2ZZ_H |
| 5446 | 18075674154687ULL, // FMUL_2ZZ_S |
| 5447 | 19553138677439ULL, // FMUL_4Z4Z_D |
| 5448 | 18659787593407ULL, // FMUL_4Z4Z_H |
| 5449 | 19587502642879ULL, // FMUL_4Z4Z_S |
| 5450 | 18419267311295ULL, // FMUL_4ZZ_D |
| 5451 | 17732074657471ULL, // FMUL_4ZZ_H |
| 5452 | 18075674154687ULL, // FMUL_4ZZ_S |
| 5453 | 3315819241283835583ULL, // FMUL_ZPmI_D |
| 5454 | 49671675278595775ULL, // FMUL_ZPmI_H |
| 5455 | 3315828037376890559ULL, // FMUL_ZPmI_S |
| 5456 | 289400291690862271ULL, // FMUL_ZPmZ_D |
| 5457 | 439233043046143679ULL, // FMUL_ZPmZ_H |
| 5458 | 577639463935628991ULL, // FMUL_ZPmZ_S |
| 5459 | 50709891276396223ULL, // FMUL_ZZZI_D |
| 5460 | 334391417050815ULL, // FMUL_ZZZI_H |
| 5461 | 50718688443193023ULL, // FMUL_ZZZI_S |
| 5462 | 44395468478143ULL, // FMUL_ZZZ_D |
| 5463 | 17732068251327ULL, // FMUL_ZZZ_H |
| 5464 | 53192635274943ULL, // FMUL_ZZZ_S |
| 5465 | 3196544597054478015ULL, // FMULv1i16_indexed |
| 5466 | 3212307195750274751ULL, // FMULv1i32_indexed |
| 5467 | 3219062595191330495ULL, // FMULv1i64_indexed |
| 5468 | 9122237011564223ULL, // FMULv2f32 |
| 5469 | 2366700133652159ULL, // FMULv2f64 |
| 5470 | 3212307471978829503ULL, // FMULv2i32_indexed |
| 5471 | 3219062733983028927ULL, // FMULv2i64_indexed |
| 5472 | 10248171282339519ULL, // FMULv4f16 |
| 5473 | 3492634404427455ULL, // FMULv4f32 |
| 5474 | 3196544907646965439ULL, // FMULv4i16_indexed |
| 5475 | 3212307368905905855ULL, // FMULv4i32_indexed |
| 5476 | 4618568673105599ULL, // FMULv8f16 |
| 5477 | 3196544804571944639ULL, // FMULv8i16_indexed |
| 5478 | 2117100ULL, // FNEGDr |
| 5479 | 2117100ULL, // FNEGHr |
| 5480 | 2117100ULL, // FNEGSr |
| 5481 | 8830723345900ULL, // FNEG_ZPmZ_D |
| 5482 | 17661446655468ULL, // FNEG_ZPmZ_H |
| 5483 | 26422909423084ULL, // FNEG_ZPmZ_S |
| 5484 | 44084351782380ULL, // FNEG_ZPzZ_D |
| 5485 | 17730705100268ULL, // FNEG_ZPzZ_H |
| 5486 | 52880444837356ULL, // FNEG_ZPzZ_S |
| 5487 | 207511195116ULL, // FNEGv2f32 |
| 5488 | 241873030636ULL, // FNEGv2f64 |
| 5489 | 276234866156ULL, // FNEGv4f16 |
| 5490 | 310596701676ULL, // FNEGv4f32 |
| 5491 | 344958537196ULL, // FNEGv8f16 |
| 5492 | 1187884876975195ULL, // FNMADDDrrr |
| 5493 | 1187884876975195ULL, // FNMADDHrrr |
| 5494 | 1187884876975195ULL, // FNMADDSrrr |
| 5495 | 2595208116532464567ULL, // FNMAD_ZPmZZ_D |
| 5496 | 459499172649831351ULL, // FNMAD_ZPmZZ_H |
| 5497 | 2739340896794397623ULL, // FNMAD_ZPmZZ_S |
| 5498 | 2595208116532462483ULL, // FNMLA_ZPmZZ_D |
| 5499 | 459499172649829267ULL, // FNMLA_ZPmZZ_H |
| 5500 | 2739340896794395539ULL, // FNMLA_ZPmZZ_S |
| 5501 | 2595208116532469330ULL, // FNMLS_ZPmZZ_D |
| 5502 | 459499172649836114ULL, // FNMLS_ZPmZZ_H |
| 5503 | 2739340896794402386ULL, // FNMLS_ZPmZZ_S |
| 5504 | 2595208116532464112ULL, // FNMSB_ZPmZZ_D |
| 5505 | 459499172649830896ULL, // FNMSB_ZPmZZ_H |
| 5506 | 2739340896794397168ULL, // FNMSB_ZPmZZ_S |
| 5507 | 1187884876974720ULL, // FNMSUBDrrr |
| 5508 | 1187884876974720ULL, // FNMSUBHrrr |
| 5509 | 1187884876974720ULL, // FNMSUBSrrr |
| 5510 | 61984970135237ULL, // FNMULDrr |
| 5511 | 61984970135237ULL, // FNMULHrr |
| 5512 | 61984970135237ULL, // FNMULSrr |
| 5513 | 2686504281ULL, // FRECPE_ZZ_D |
| 5514 | 4859170137ULL, // FRECPE_ZZ_H |
| 5515 | 3760278873ULL, // FRECPE_ZZ_S |
| 5516 | 2116953ULL, // FRECPEv1f16 |
| 5517 | 2116953ULL, // FRECPEv1i32 |
| 5518 | 2116953ULL, // FRECPEv1i64 |
| 5519 | 207511194969ULL, // FRECPEv2f32 |
| 5520 | 241873030489ULL, // FRECPEv2f64 |
| 5521 | 276234866009ULL, // FRECPEv4f16 |
| 5522 | 310596701529ULL, // FRECPEv4f32 |
| 5523 | 344958537049ULL, // FRECPEv8f16 |
| 5524 | 61984970137225ULL, // FRECPS16 |
| 5525 | 61984970137225ULL, // FRECPS32 |
| 5526 | 61984970137225ULL, // FRECPS64 |
| 5527 | 44395468480137ULL, // FRECPS_ZZZ_D |
| 5528 | 17732068253321ULL, // FRECPS_ZZZ_H |
| 5529 | 53192635276937ULL, // FRECPS_ZZZ_S |
| 5530 | 9122237011566217ULL, // FRECPSv2f32 |
| 5531 | 2366700133654153ULL, // FRECPSv2f64 |
| 5532 | 10248171282341513ULL, // FRECPSv4f16 |
| 5533 | 3492634404429449ULL, // FRECPSv4f32 |
| 5534 | 4618568673107593ULL, // FRECPSv8f16 |
| 5535 | 8830723351940ULL, // FRECPX_ZPmZ_D |
| 5536 | 17661446661508ULL, // FRECPX_ZPmZ_H |
| 5537 | 26422909429124ULL, // FRECPX_ZPmZ_S |
| 5538 | 44084351788420ULL, // FRECPX_ZPzZ_D |
| 5539 | 17730705106308ULL, // FRECPX_ZPzZ_H |
| 5540 | 52880444843396ULL, // FRECPX_ZPzZ_S |
| 5541 | 2123140ULL, // FRECPXv1f16 |
| 5542 | 2123140ULL, // FRECPXv1i32 |
| 5543 | 2123140ULL, // FRECPXv1i64 |
| 5544 | 2123013ULL, // FRINT32XDr |
| 5545 | 2123013ULL, // FRINT32XSr |
| 5546 | 8830723351813ULL, // FRINT32X_ZPmZ_D |
| 5547 | 26422909428997ULL, // FRINT32X_ZPmZ_S |
| 5548 | 44084351788293ULL, // FRINT32X_ZPzZ_D |
| 5549 | 52880444843269ULL, // FRINT32X_ZPzZ_S |
| 5550 | 207511201029ULL, // FRINT32Xv2f32 |
| 5551 | 241873036549ULL, // FRINT32Xv2f64 |
| 5552 | 310596707589ULL, // FRINT32Xv4f32 |
| 5553 | 2123178ULL, // FRINT32ZDr |
| 5554 | 2123178ULL, // FRINT32ZSr |
| 5555 | 8830723351978ULL, // FRINT32Z_ZPmZ_D |
| 5556 | 26422909429162ULL, // FRINT32Z_ZPmZ_S |
| 5557 | 44084351788458ULL, // FRINT32Z_ZPzZ_D |
| 5558 | 52880444843434ULL, // FRINT32Z_ZPzZ_S |
| 5559 | 207511201194ULL, // FRINT32Zv2f32 |
| 5560 | 241873036714ULL, // FRINT32Zv2f64 |
| 5561 | 310596707754ULL, // FRINT32Zv4f32 |
| 5562 | 2123023ULL, // FRINT64XDr |
| 5563 | 2123023ULL, // FRINT64XSr |
| 5564 | 8830723351823ULL, // FRINT64X_ZPmZ_D |
| 5565 | 26422909429007ULL, // FRINT64X_ZPmZ_S |
| 5566 | 44084351788303ULL, // FRINT64X_ZPzZ_D |
| 5567 | 52880444843279ULL, // FRINT64X_ZPzZ_S |
| 5568 | 207511201039ULL, // FRINT64Xv2f32 |
| 5569 | 241873036559ULL, // FRINT64Xv2f64 |
| 5570 | 310596707599ULL, // FRINT64Xv4f32 |
| 5571 | 2123188ULL, // FRINT64ZDr |
| 5572 | 2123188ULL, // FRINT64ZSr |
| 5573 | 8830723351988ULL, // FRINT64Z_ZPmZ_D |
| 5574 | 26422909429172ULL, // FRINT64Z_ZPmZ_S |
| 5575 | 44084351788468ULL, // FRINT64Z_ZPzZ_D |
| 5576 | 52880444843444ULL, // FRINT64Z_ZPzZ_S |
| 5577 | 207511201204ULL, // FRINT64Zv2f32 |
| 5578 | 241873036724ULL, // FRINT64Zv2f64 |
| 5579 | 310596707764ULL, // FRINT64Zv4f32 |
| 5580 | 2114859ULL, // FRINTADr |
| 5581 | 2114859ULL, // FRINTAHr |
| 5582 | 2114859ULL, // FRINTASr |
| 5583 | 4867687723ULL, // FRINTA_2Z2Z_S |
| 5584 | 4867687723ULL, // FRINTA_4Z4Z_S |
| 5585 | 8830723343659ULL, // FRINTA_ZPmZ_D |
| 5586 | 17661446653227ULL, // FRINTA_ZPmZ_H |
| 5587 | 26422909420843ULL, // FRINTA_ZPmZ_S |
| 5588 | 44084351780139ULL, // FRINTA_ZPzZ_D |
| 5589 | 17730705098027ULL, // FRINTA_ZPzZ_H |
| 5590 | 52880444835115ULL, // FRINTA_ZPzZ_S |
| 5591 | 207511192875ULL, // FRINTAv2f32 |
| 5592 | 241873028395ULL, // FRINTAv2f64 |
| 5593 | 276234863915ULL, // FRINTAv4f16 |
| 5594 | 310596699435ULL, // FRINTAv4f32 |
| 5595 | 344958534955ULL, // FRINTAv8f16 |
| 5596 | 2118089ULL, // FRINTIDr |
| 5597 | 2118089ULL, // FRINTIHr |
| 5598 | 2118089ULL, // FRINTISr |
| 5599 | 8830723346889ULL, // FRINTI_ZPmZ_D |
| 5600 | 17661446656457ULL, // FRINTI_ZPmZ_H |
| 5601 | 26422909424073ULL, // FRINTI_ZPmZ_S |
| 5602 | 44084351783369ULL, // FRINTI_ZPzZ_D |
| 5603 | 17730705101257ULL, // FRINTI_ZPzZ_H |
| 5604 | 52880444838345ULL, // FRINTI_ZPzZ_S |
| 5605 | 207511196105ULL, // FRINTIv2f32 |
| 5606 | 241873031625ULL, // FRINTIv2f64 |
| 5607 | 276234867145ULL, // FRINTIv4f16 |
| 5608 | 310596702665ULL, // FRINTIv4f32 |
| 5609 | 344958538185ULL, // FRINTIv8f16 |
| 5610 | 2119624ULL, // FRINTMDr |
| 5611 | 2119624ULL, // FRINTMHr |
| 5612 | 2119624ULL, // FRINTMSr |
| 5613 | 4867692488ULL, // FRINTM_2Z2Z_S |
| 5614 | 4867692488ULL, // FRINTM_4Z4Z_S |
| 5615 | 8830723348424ULL, // FRINTM_ZPmZ_D |
| 5616 | 17661446657992ULL, // FRINTM_ZPmZ_H |
| 5617 | 26422909425608ULL, // FRINTM_ZPmZ_S |
| 5618 | 44084351784904ULL, // FRINTM_ZPzZ_D |
| 5619 | 17730705102792ULL, // FRINTM_ZPzZ_H |
| 5620 | 52880444839880ULL, // FRINTM_ZPzZ_S |
| 5621 | 207511197640ULL, // FRINTMv2f32 |
| 5622 | 241873033160ULL, // FRINTMv2f64 |
| 5623 | 276234868680ULL, // FRINTMv4f16 |
| 5624 | 310596704200ULL, // FRINTMv4f32 |
| 5625 | 344958539720ULL, // FRINTMv8f16 |
| 5626 | 2119791ULL, // FRINTNDr |
| 5627 | 2119791ULL, // FRINTNHr |
| 5628 | 2119791ULL, // FRINTNSr |
| 5629 | 4867692655ULL, // FRINTN_2Z2Z_S |
| 5630 | 4867692655ULL, // FRINTN_4Z4Z_S |
| 5631 | 8830723348591ULL, // FRINTN_ZPmZ_D |
| 5632 | 17661446658159ULL, // FRINTN_ZPmZ_H |
| 5633 | 26422909425775ULL, // FRINTN_ZPmZ_S |
| 5634 | 44084351785071ULL, // FRINTN_ZPzZ_D |
| 5635 | 17730705102959ULL, // FRINTN_ZPzZ_H |
| 5636 | 52880444840047ULL, // FRINTN_ZPzZ_S |
| 5637 | 207511197807ULL, // FRINTNv2f32 |
| 5638 | 241873033327ULL, // FRINTNv2f64 |
| 5639 | 276234868847ULL, // FRINTNv4f16 |
| 5640 | 310596704367ULL, // FRINTNv4f32 |
| 5641 | 344958539887ULL, // FRINTNv8f16 |
| 5642 | 2120341ULL, // FRINTPDr |
| 5643 | 2120341ULL, // FRINTPHr |
| 5644 | 2120341ULL, // FRINTPSr |
| 5645 | 4867693205ULL, // FRINTP_2Z2Z_S |
| 5646 | 4867693205ULL, // FRINTP_4Z4Z_S |
| 5647 | 8830723349141ULL, // FRINTP_ZPmZ_D |
| 5648 | 17661446658709ULL, // FRINTP_ZPmZ_H |
| 5649 | 26422909426325ULL, // FRINTP_ZPmZ_S |
| 5650 | 44084351785621ULL, // FRINTP_ZPzZ_D |
| 5651 | 17730705103509ULL, // FRINTP_ZPzZ_H |
| 5652 | 52880444840597ULL, // FRINTP_ZPzZ_S |
| 5653 | 207511198357ULL, // FRINTPv2f32 |
| 5654 | 241873033877ULL, // FRINTPv2f64 |
| 5655 | 276234869397ULL, // FRINTPv4f16 |
| 5656 | 310596704917ULL, // FRINTPv4f32 |
| 5657 | 344958540437ULL, // FRINTPv8f16 |
| 5658 | 2123148ULL, // FRINTXDr |
| 5659 | 2123148ULL, // FRINTXHr |
| 5660 | 2123148ULL, // FRINTXSr |
| 5661 | 8830723351948ULL, // FRINTX_ZPmZ_D |
| 5662 | 17661446661516ULL, // FRINTX_ZPmZ_H |
| 5663 | 26422909429132ULL, // FRINTX_ZPmZ_S |
| 5664 | 44084351788428ULL, // FRINTX_ZPzZ_D |
| 5665 | 17730705106316ULL, // FRINTX_ZPzZ_H |
| 5666 | 52880444843404ULL, // FRINTX_ZPzZ_S |
| 5667 | 207511201164ULL, // FRINTXv2f32 |
| 5668 | 241873036684ULL, // FRINTXv2f64 |
| 5669 | 276234872204ULL, // FRINTXv4f16 |
| 5670 | 310596707724ULL, // FRINTXv4f32 |
| 5671 | 344958543244ULL, // FRINTXv8f16 |
| 5672 | 2123282ULL, // FRINTZDr |
| 5673 | 2123282ULL, // FRINTZHr |
| 5674 | 2123282ULL, // FRINTZSr |
| 5675 | 8830723352082ULL, // FRINTZ_ZPmZ_D |
| 5676 | 17661446661650ULL, // FRINTZ_ZPmZ_H |
| 5677 | 26422909429266ULL, // FRINTZ_ZPmZ_S |
| 5678 | 44084351788562ULL, // FRINTZ_ZPzZ_D |
| 5679 | 17730705106450ULL, // FRINTZ_ZPzZ_H |
| 5680 | 52880444843538ULL, // FRINTZ_ZPzZ_S |
| 5681 | 207511201298ULL, // FRINTZv2f32 |
| 5682 | 241873036818ULL, // FRINTZv2f64 |
| 5683 | 276234872338ULL, // FRINTZv4f16 |
| 5684 | 310596707858ULL, // FRINTZv4f32 |
| 5685 | 344958543378ULL, // FRINTZv8f16 |
| 5686 | 2686504333ULL, // FRSQRTE_ZZ_D |
| 5687 | 4859170189ULL, // FRSQRTE_ZZ_H |
| 5688 | 3760278925ULL, // FRSQRTE_ZZ_S |
| 5689 | 2117005ULL, // FRSQRTEv1f16 |
| 5690 | 2117005ULL, // FRSQRTEv1i32 |
| 5691 | 2117005ULL, // FRSQRTEv1i64 |
| 5692 | 207511195021ULL, // FRSQRTEv2f32 |
| 5693 | 241873030541ULL, // FRSQRTEv2f64 |
| 5694 | 276234866061ULL, // FRSQRTEv4f16 |
| 5695 | 310596701581ULL, // FRSQRTEv4f32 |
| 5696 | 344958537101ULL, // FRSQRTEv8f16 |
| 5697 | 61984970137309ULL, // FRSQRTS16 |
| 5698 | 61984970137309ULL, // FRSQRTS32 |
| 5699 | 61984970137309ULL, // FRSQRTS64 |
| 5700 | 44395468480221ULL, // FRSQRTS_ZZZ_D |
| 5701 | 17732068253405ULL, // FRSQRTS_ZZZ_H |
| 5702 | 53192635277021ULL, // FRSQRTS_ZZZ_S |
| 5703 | 9122237011566301ULL, // FRSQRTSv2f32 |
| 5704 | 2366700133654237ULL, // FRSQRTSv2f64 |
| 5705 | 10248171282341597ULL, // FRSQRTSv4f16 |
| 5706 | 3492634404429533ULL, // FRSQRTSv4f32 |
| 5707 | 4618568673107677ULL, // FRSQRTSv8f16 |
| 5708 | 19553138674951ULL, // FSCALE_2Z2Z_D |
| 5709 | 18659787590919ULL, // FSCALE_2Z2Z_H |
| 5710 | 19587502640391ULL, // FSCALE_2Z2Z_S |
| 5711 | 18419267308807ULL, // FSCALE_2ZZ_D |
| 5712 | 17732074654983ULL, // FSCALE_2ZZ_H |
| 5713 | 18075674152199ULL, // FSCALE_2ZZ_S |
| 5714 | 19553138674951ULL, // FSCALE_4Z4Z_D |
| 5715 | 18659787590919ULL, // FSCALE_4Z4Z_H |
| 5716 | 19587502640391ULL, // FSCALE_4Z4Z_S |
| 5717 | 18419267308807ULL, // FSCALE_4ZZ_D |
| 5718 | 17732074654983ULL, // FSCALE_4ZZ_H |
| 5719 | 18075674152199ULL, // FSCALE_4ZZ_S |
| 5720 | 289400291690859783ULL, // FSCALE_ZPmZ_D |
| 5721 | 439233043046141191ULL, // FSCALE_ZPmZ_H |
| 5722 | 577639463935626503ULL, // FSCALE_ZPmZ_S |
| 5723 | 9122237011561735ULL, // FSCALEv2f32 |
| 5724 | 2366700133649671ULL, // FSCALEv2f64 |
| 5725 | 10248171282337031ULL, // FSCALEv4f16 |
| 5726 | 3492634404424967ULL, // FSCALEv4f32 |
| 5727 | 4618568673103111ULL, // FSCALEv8f16 |
| 5728 | 2122222ULL, // FSQRTDr |
| 5729 | 2122222ULL, // FSQRTHr |
| 5730 | 2122222ULL, // FSQRTSr |
| 5731 | 44084351787502ULL, // FSQRT_ZPZz_D |
| 5732 | 17730705105390ULL, // FSQRT_ZPZz_H |
| 5733 | 52880444842478ULL, // FSQRT_ZPZz_S |
| 5734 | 8830723351022ULL, // FSQRT_ZPmZ_D |
| 5735 | 17661446660590ULL, // FSQRT_ZPmZ_H |
| 5736 | 26422909428206ULL, // FSQRT_ZPmZ_S |
| 5737 | 207511200238ULL, // FSQRTv2f32 |
| 5738 | 241873035758ULL, // FSQRTv2f64 |
| 5739 | 276234871278ULL, // FSQRTv4f16 |
| 5740 | 310596706798ULL, // FSQRTv4f32 |
| 5741 | 344958542318ULL, // FSQRTv8f16 |
| 5742 | 61984970132069ULL, // FSUBDrr |
| 5743 | 61984970132069ULL, // FSUBHrr |
| 5744 | 2451128112828701602ULL, // FSUBR_ZPmI_D |
| 5745 | 33909076582800290ULL, // FSUBR_ZPmI_H |
| 5746 | 2451136908921756578ULL, // FSUBR_ZPmI_S |
| 5747 | 289400291690863522ULL, // FSUBR_ZPmZ_D |
| 5748 | 439233043046144930ULL, // FSUBR_ZPmZ_H |
| 5749 | 577639463935630242ULL, // FSUBR_ZPmZ_S |
| 5750 | 61984970132069ULL, // FSUBSrr |
| 5751 | 18455243999845ULL, // FSUB_VG2_M2Z_D |
| 5752 | 18627042839141ULL, // FSUB_VG2_M2Z_H |
| 5753 | 18489603754597ULL, // FSUB_VG2_M2Z_S |
| 5754 | 18455512435301ULL, // FSUB_VG4_M4Z_D |
| 5755 | 18627311274597ULL, // FSUB_VG4_M4Z_H |
| 5756 | 18489872190053ULL, // FSUB_VG4_M4Z_S |
| 5757 | 2451128112828697189ULL, // FSUB_ZPmI_D |
| 5758 | 33909076582795877ULL, // FSUB_ZPmI_H |
| 5759 | 2451136908921752165ULL, // FSUB_ZPmI_S |
| 5760 | 289400291690859109ULL, // FSUB_ZPmZ_D |
| 5761 | 439233043046140517ULL, // FSUB_ZPmZ_H |
| 5762 | 577639463935625829ULL, // FSUB_ZPmZ_S |
| 5763 | 44395468474981ULL, // FSUB_ZZZ_D |
| 5764 | 17732068248165ULL, // FSUB_ZZZ_H |
| 5765 | 53192635271781ULL, // FSUB_ZZZ_S |
| 5766 | 9122237011561061ULL, // FSUBv2f32 |
| 5767 | 2366700133648997ULL, // FSUBv2f64 |
| 5768 | 10248171282336357ULL, // FSUBv4f16 |
| 5769 | 3492634404424293ULL, // FSUBv4f32 |
| 5770 | 4618568673102437ULL, // FSUBv8f16 |
| 5771 | 1170295375317950ULL, // FTMAD_ZZI_D |
| 5772 | 450492044014586814ULL, // FTMAD_ZZI_H |
| 5773 | 1179092542114750ULL, // FTMAD_ZZI_S |
| 5774 | 396249465472012ULL, // FTMOPA_M2ZZZI_BtoH |
| 5775 | 396249465472012ULL, // FTMOPA_M2ZZZI_BtoS |
| 5776 | 396242729419788ULL, // FTMOPA_M2ZZZI_HtoH |
| 5777 | 396242729419788ULL, // FTMOPA_M2ZZZI_HtoS |
| 5778 | 396250006537228ULL, // FTMOPA_M2ZZZI_StoS |
| 5779 | 44395468478162ULL, // FTSMUL_ZZZ_D |
| 5780 | 17732068251346ULL, // FTSMUL_ZZZ_H |
| 5781 | 53192635274962ULL, // FTSMUL_ZZZ_S |
| 5782 | 44395468477534ULL, // FTSSEL_ZZZ_D |
| 5783 | 17732068250718ULL, // FTSSEL_ZZZ_H |
| 5784 | 53192635274334ULL, // FTSSEL_ZZZ_S |
| 5785 | 43305472383748673ULL, // FVDOTB_VG4_M2ZZI_BtoS |
| 5786 | 43305472383754779ULL, // FVDOTT_VG4_M2ZZI_BtoS |
| 5787 | 43305472115450278ULL, // FVDOT_VG2_M2ZZI_BtoH |
| 5788 | 888468002750833062ULL, // FVDOT_VG2_M2ZZI_HtoS |
| 5789 | 11659ULL, // GCSPOPCX |
| 5790 | 22457ULL, // GCSPOPM |
| 5791 | 11677ULL, // GCSPOPX |
| 5792 | 22363ULL, // GCSPUSHM |
| 5793 | 11668ULL, // GCSPUSHX |
| 5794 | 16500ULL, // GCSSS1 |
| 5795 | 16969ULL, // GCSSS2 |
| 5796 | 2508300770551ULL, // GCSSTR |
| 5797 | 2508300770559ULL, // GCSSTTR |
| 5798 | 51924347239171476ULL, // GLD1B_D |
| 5799 | 3476911692055741844ULL, // GLD1B_D_IMM |
| 5800 | 53050247146014100ULL, // GLD1B_D_SXTW |
| 5801 | 54176147052856724ULL, // GLD1B_D_UXTW |
| 5802 | 3476911348458390932ULL, // GLD1B_S_IMM |
| 5803 | 55302046959732116ULL, // GLD1B_S_SXTW |
| 5804 | 56427946866574740ULL, // GLD1B_S_UXTW |
| 5805 | 51924347239172961ULL, // GLD1D |
| 5806 | 57553674974694241ULL, // GLD1D_IMM |
| 5807 | 58679746680228705ULL, // GLD1D_SCALED |
| 5808 | 53050247146015585ULL, // GLD1D_SXTW |
| 5809 | 59805646587071329ULL, // GLD1D_SXTW_SCALED |
| 5810 | 54176147052858209ULL, // GLD1D_UXTW |
| 5811 | 60931546493913953ULL, // GLD1D_UXTW_SCALED |
| 5812 | 51924347239173664ULL, // GLD1H_D |
| 5813 | 3520821788422606368ULL, // GLD1H_D_IMM |
| 5814 | 63183346307599904ULL, // GLD1H_D_SCALED |
| 5815 | 53050247146016288ULL, // GLD1H_D_SXTW |
| 5816 | 64309246214442528ULL, // GLD1H_D_SXTW_SCALED |
| 5817 | 54176147052858912ULL, // GLD1H_D_UXTW |
| 5818 | 65435146121285152ULL, // GLD1H_D_UXTW_SCALED |
| 5819 | 3520821444825255456ULL, // GLD1H_S_IMM |
| 5820 | 55302046959734304ULL, // GLD1H_S_SXTW |
| 5821 | 66561046028160544ULL, // GLD1H_S_SXTW_SCALED |
| 5822 | 56427946866576928ULL, // GLD1H_S_UXTW |
| 5823 | 67686945935003168ULL, // GLD1H_S_UXTW_SCALED |
| 5824 | 3476911692056075005ULL, // GLD1Q |
| 5825 | 51924347239172536ULL, // GLD1SB_D |
| 5826 | 3476911692055742904ULL, // GLD1SB_D_IMM |
| 5827 | 53050247146015160ULL, // GLD1SB_D_SXTW |
| 5828 | 54176147052857784ULL, // GLD1SB_D_UXTW |
| 5829 | 3476911348458391992ULL, // GLD1SB_S_IMM |
| 5830 | 55302046959733176ULL, // GLD1SB_S_SXTW |
| 5831 | 56427946866575800ULL, // GLD1SB_S_UXTW |
| 5832 | 51924347239174355ULL, // GLD1SH_D |
| 5833 | 3520821788422607059ULL, // GLD1SH_D_IMM |
| 5834 | 63183346307600595ULL, // GLD1SH_D_SCALED |
| 5835 | 53050247146016979ULL, // GLD1SH_D_SXTW |
| 5836 | 64309246214443219ULL, // GLD1SH_D_SXTW_SCALED |
| 5837 | 54176147052859603ULL, // GLD1SH_D_UXTW |
| 5838 | 65435146121285843ULL, // GLD1SH_D_UXTW_SCALED |
| 5839 | 3520821444825256147ULL, // GLD1SH_S_IMM |
| 5840 | 55302046959734995ULL, // GLD1SH_S_SXTW |
| 5841 | 66561046028161235ULL, // GLD1SH_S_SXTW_SCALED |
| 5842 | 56427946866577619ULL, // GLD1SH_S_UXTW |
| 5843 | 67686945935003859ULL, // GLD1SH_S_UXTW_SCALED |
| 5844 | 51924347239179411ULL, // GLD1SW_D |
| 5845 | 3527577187863667859ULL, // GLD1SW_D_IMM |
| 5846 | 69938745748661395ULL, // GLD1SW_D_SCALED |
| 5847 | 53050247146022035ULL, // GLD1SW_D_SXTW |
| 5848 | 71064645655504019ULL, // GLD1SW_D_SXTW_SCALED |
| 5849 | 54176147052864659ULL, // GLD1SW_D_UXTW |
| 5850 | 72190545562346643ULL, // GLD1SW_D_UXTW_SCALED |
| 5851 | 51924347239179216ULL, // GLD1W_D |
| 5852 | 3527577187863667664ULL, // GLD1W_D_IMM |
| 5853 | 69938745748661200ULL, // GLD1W_D_SCALED |
| 5854 | 53050247146021840ULL, // GLD1W_D_SXTW |
| 5855 | 71064645655503824ULL, // GLD1W_D_SXTW_SCALED |
| 5856 | 54176147052864464ULL, // GLD1W_D_UXTW |
| 5857 | 72190545562346448ULL, // GLD1W_D_UXTW_SCALED |
| 5858 | 3527576844266316752ULL, // GLD1W_IMM |
| 5859 | 55302046959739856ULL, // GLD1W_SXTW |
| 5860 | 73316445469221840ULL, // GLD1W_SXTW_SCALED |
| 5861 | 56427946866582480ULL, // GLD1W_UXTW |
| 5862 | 74442345376064464ULL, // GLD1W_UXTW_SCALED |
| 5863 | 51924347239171482ULL, // GLDFF1B_D |
| 5864 | 3476911692055741850ULL, // GLDFF1B_D_IMM |
| 5865 | 53050247146014106ULL, // GLDFF1B_D_SXTW |
| 5866 | 54176147052856730ULL, // GLDFF1B_D_UXTW |
| 5867 | 3476911348458390938ULL, // GLDFF1B_S_IMM |
| 5868 | 55302046959732122ULL, // GLDFF1B_S_SXTW |
| 5869 | 56427946866574746ULL, // GLDFF1B_S_UXTW |
| 5870 | 51924347239172967ULL, // GLDFF1D |
| 5871 | 57553674974694247ULL, // GLDFF1D_IMM |
| 5872 | 58679746680228711ULL, // GLDFF1D_SCALED |
| 5873 | 53050247146015591ULL, // GLDFF1D_SXTW |
| 5874 | 59805646587071335ULL, // GLDFF1D_SXTW_SCALED |
| 5875 | 54176147052858215ULL, // GLDFF1D_UXTW |
| 5876 | 60931546493913959ULL, // GLDFF1D_UXTW_SCALED |
| 5877 | 51924347239173670ULL, // GLDFF1H_D |
| 5878 | 3520821788422606374ULL, // GLDFF1H_D_IMM |
| 5879 | 63183346307599910ULL, // GLDFF1H_D_SCALED |
| 5880 | 53050247146016294ULL, // GLDFF1H_D_SXTW |
| 5881 | 64309246214442534ULL, // GLDFF1H_D_SXTW_SCALED |
| 5882 | 54176147052858918ULL, // GLDFF1H_D_UXTW |
| 5883 | 65435146121285158ULL, // GLDFF1H_D_UXTW_SCALED |
| 5884 | 3520821444825255462ULL, // GLDFF1H_S_IMM |
| 5885 | 55302046959734310ULL, // GLDFF1H_S_SXTW |
| 5886 | 66561046028160550ULL, // GLDFF1H_S_SXTW_SCALED |
| 5887 | 56427946866576934ULL, // GLDFF1H_S_UXTW |
| 5888 | 67686945935003174ULL, // GLDFF1H_S_UXTW_SCALED |
| 5889 | 51924347239172543ULL, // GLDFF1SB_D |
| 5890 | 3476911692055742911ULL, // GLDFF1SB_D_IMM |
| 5891 | 53050247146015167ULL, // GLDFF1SB_D_SXTW |
| 5892 | 54176147052857791ULL, // GLDFF1SB_D_UXTW |
| 5893 | 3476911348458391999ULL, // GLDFF1SB_S_IMM |
| 5894 | 55302046959733183ULL, // GLDFF1SB_S_SXTW |
| 5895 | 56427946866575807ULL, // GLDFF1SB_S_UXTW |
| 5896 | 51924347239174362ULL, // GLDFF1SH_D |
| 5897 | 3520821788422607066ULL, // GLDFF1SH_D_IMM |
| 5898 | 63183346307600602ULL, // GLDFF1SH_D_SCALED |
| 5899 | 53050247146016986ULL, // GLDFF1SH_D_SXTW |
| 5900 | 64309246214443226ULL, // GLDFF1SH_D_SXTW_SCALED |
| 5901 | 54176147052859610ULL, // GLDFF1SH_D_UXTW |
| 5902 | 65435146121285850ULL, // GLDFF1SH_D_UXTW_SCALED |
| 5903 | 3520821444825256154ULL, // GLDFF1SH_S_IMM |
| 5904 | 55302046959735002ULL, // GLDFF1SH_S_SXTW |
| 5905 | 66561046028161242ULL, // GLDFF1SH_S_SXTW_SCALED |
| 5906 | 56427946866577626ULL, // GLDFF1SH_S_UXTW |
| 5907 | 67686945935003866ULL, // GLDFF1SH_S_UXTW_SCALED |
| 5908 | 51924347239179418ULL, // GLDFF1SW_D |
| 5909 | 3527577187863667866ULL, // GLDFF1SW_D_IMM |
| 5910 | 69938745748661402ULL, // GLDFF1SW_D_SCALED |
| 5911 | 53050247146022042ULL, // GLDFF1SW_D_SXTW |
| 5912 | 71064645655504026ULL, // GLDFF1SW_D_SXTW_SCALED |
| 5913 | 54176147052864666ULL, // GLDFF1SW_D_UXTW |
| 5914 | 72190545562346650ULL, // GLDFF1SW_D_UXTW_SCALED |
| 5915 | 51924347239179222ULL, // GLDFF1W_D |
| 5916 | 3527577187863667670ULL, // GLDFF1W_D_IMM |
| 5917 | 69938745748661206ULL, // GLDFF1W_D_SCALED |
| 5918 | 53050247146021846ULL, // GLDFF1W_D_SXTW |
| 5919 | 71064645655503830ULL, // GLDFF1W_D_SXTW_SCALED |
| 5920 | 54176147052864470ULL, // GLDFF1W_D_UXTW |
| 5921 | 72190545562346454ULL, // GLDFF1W_D_UXTW_SCALED |
| 5922 | 3527576844266316758ULL, // GLDFF1W_IMM |
| 5923 | 55302046959739862ULL, // GLDFF1W_SXTW |
| 5924 | 73316445469221846ULL, // GLDFF1W_SXTW_SCALED |
| 5925 | 56427946866582486ULL, // GLDFF1W_UXTW |
| 5926 | 74442345376064470ULL, // GLDFF1W_UXTW_SCALED |
| 5927 | 61984970133945ULL, // GMI |
| 5928 | 516382ULL, // HINT |
| 5929 | 19846ULL, // HINTE |
| 5930 | 289400360410341635ULL, // HISTCNT_ZPzZZ_D |
| 5931 | 577639532655108355ULL, // HISTCNT_ZPzZZ_S |
| 5932 | 35600180743680ULL, // HISTSEG_ZZZ |
| 5933 | 385128ULL, // HLT |
| 5934 | 379735ULL, // HVC |
| 5935 | 8592049839ULL, // INCB_XPiI |
| 5936 | 8592051184ULL, // INCD_XPiI |
| 5937 | 8592083952ULL, // INCD_ZPiI |
| 5938 | 8592051988ULL, // INCH_XPiI |
| 5939 | 54595348ULL, // INCH_ZPiI |
| 5940 | 3491780934ULL, // INCP_XP_B |
| 5941 | 2686474566ULL, // INCP_XP_D |
| 5942 | 2149603654ULL, // INCP_XP_H |
| 5943 | 3760216390ULL, // INCP_XP_S |
| 5944 | 1612765510ULL, // INCP_ZP_D |
| 5945 | 4875950406ULL, // INCP_ZP_H |
| 5946 | 1881233734ULL, // INCP_ZP_S |
| 5947 | 8592057425ULL, // INCW_XPiI |
| 5948 | 8592122961ULL, // INCW_ZPiI |
| 5949 | 2556581422438ULL, // INDEX_II_B |
| 5950 | 61984970171750ULL, // INDEX_II_D |
| 5951 | 14313137510ULL, // INDEX_II_H |
| 5952 | 61984970204518ULL, // INDEX_II_S |
| 5953 | 18602579240294ULL, // INDEX_IR_B |
| 5954 | 61984970171750ULL, // INDEX_IR_D |
| 5955 | 5186332006ULL, // INDEX_IR_H |
| 5956 | 61984970204518ULL, // INDEX_IR_S |
| 5957 | 554566179399014ULL, // INDEX_RI_B |
| 5958 | 61984970171750ULL, // INDEX_RI_D |
| 5959 | 2579455092070ULL, // INDEX_RI_H |
| 5960 | 61984970204518ULL, // INDEX_RI_S |
| 5961 | 61984970155366ULL, // INDEX_RR_B |
| 5962 | 61984970171750ULL, // INDEX_RR_D |
| 5963 | 18591093171558ULL, // INDEX_RR_H |
| 5964 | 61984970204518ULL, // INDEX_RR_S |
| 5965 | 521583332951369ULL, // INSERT_MXIPZ_H_B |
| 5966 | 565563798062409ULL, // INSERT_MXIPZ_H_D |
| 5967 | 574359891084617ULL, // INSERT_MXIPZ_H_H |
| 5968 | 583155984106825ULL, // INSERT_MXIPZ_H_Q |
| 5969 | 591952077129033ULL, // INSERT_MXIPZ_H_S |
| 5970 | 521583332967753ULL, // INSERT_MXIPZ_V_B |
| 5971 | 565563798078793ULL, // INSERT_MXIPZ_V_D |
| 5972 | 574359891101001ULL, // INSERT_MXIPZ_V_H |
| 5973 | 583155984123209ULL, // INSERT_MXIPZ_V_Q |
| 5974 | 591952077145417ULL, // INSERT_MXIPZ_V_S |
| 5975 | 5102410987ULL, // INSR_ZR_B |
| 5976 | 5102427371ULL, // INSR_ZR_D |
| 5977 | 4919991531ULL, // INSR_ZR_H |
| 5978 | 5102460139ULL, // INSR_ZR_S |
| 5979 | 14497651947ULL, // INSR_ZV_B |
| 5980 | 14766103787ULL, // INSR_ZV_D |
| 5981 | 4896922859ULL, // INSR_ZV_H |
| 5982 | 15034572011ULL, // INSR_ZV_S |
| 5983 | 15391137384ULL, // INSvi16gpr |
| 5984 | 371135193685608ULL, // INSvi16lane |
| 5985 | 15393234536ULL, // INSvi32gpr |
| 5986 | 371169555521128ULL, // INSvi32lane |
| 5987 | 15384845928ULL, // INSvi64gpr |
| 5988 | 371203906870888ULL, // INSvi64lane |
| 5989 | 15395331688ULL, // INSvi8gpr |
| 5990 | 371238277095016ULL, // INSvi8lane |
| 5991 | 61984970133001ULL, // IRG |
| 5992 | 444901ULL, // ISB |
| 5993 | 35597496370491ULL, // LASTA_RPZ_B |
| 5994 | 44393589392699ULL, // LASTA_RPZ_D |
| 5995 | 97170147525947ULL, // LASTA_RPZ_H |
| 5996 | 53189682414907ULL, // LASTA_RPZ_S |
| 5997 | 35597496370491ULL, // LASTA_VPZ_B |
| 5998 | 44393589392699ULL, // LASTA_VPZ_D |
| 5999 | 97170147525947ULL, // LASTA_VPZ_H |
| 6000 | 53189682414907ULL, // LASTA_VPZ_S |
| 6001 | 35597496371793ULL, // LASTB_RPZ_B |
| 6002 | 44393589394001ULL, // LASTB_RPZ_D |
| 6003 | 97170147527249ULL, // LASTB_RPZ_H |
| 6004 | 53189682416209ULL, // LASTB_RPZ_S |
| 6005 | 35597496371793ULL, // LASTB_VPZ_B |
| 6006 | 44393589394001ULL, // LASTB_VPZ_D |
| 6007 | 97170147527249ULL, // LASTB_VPZ_H |
| 6008 | 53189682416209ULL, // LASTB_VPZ_S |
| 6009 | 35597496375965ULL, // LASTP_XPP_B |
| 6010 | 44393589398173ULL, // LASTP_XPP_D |
| 6011 | 97170147531421ULL, // LASTP_XPP_H |
| 6012 | 53189682420381ULL, // LASTP_XPP_S |
| 6013 | 75568245282850196ULL, // LD1B |
| 6014 | 75568245373027732ULL, // LD1B_2Z |
| 6015 | 3664937148387313044ULL, // LD1B_2Z_IMM |
| 6016 | 600795865712020ULL, // LD1B_2Z_STRIDED |
| 6017 | 609591958734228ULL, // LD1B_2Z_STRIDED_IMM |
| 6018 | 75568245373027732ULL, // LD1B_4Z |
| 6019 | 3671692547828368788ULL, // LD1B_4Z_IMM |
| 6020 | 75568245373027732ULL, // LD1B_4Z_STRIDED |
| 6021 | 3671692547828368788ULL, // LD1B_4Z_STRIDED_IMM |
| 6022 | 75568245282866580ULL, // LD1B_D |
| 6023 | 3621027051930289556ULL, // LD1B_D_IMM |
| 6024 | 75568245282882964ULL, // LD1B_H |
| 6025 | 3621027051930305940ULL, // LD1B_H_IMM |
| 6026 | 3621027051930273172ULL, // LD1B_IMM |
| 6027 | 75568245282899348ULL, // LD1B_S |
| 6028 | 3621027051930322324ULL, // LD1B_S_IMM |
| 6029 | 76694145189710689ULL, // LD1D |
| 6030 | 76694145279888225ULL, // LD1D_2Z |
| 6031 | 3664937148387330913ULL, // LD1D_2Z_IMM |
| 6032 | 76694145279888225ULL, // LD1D_2Z_STRIDED |
| 6033 | 3664937148387330913ULL, // LD1D_2Z_STRIDED_IMM |
| 6034 | 76694145279888225ULL, // LD1D_4Z |
| 6035 | 3671692547828386657ULL, // LD1D_4Z_IMM |
| 6036 | 76694145279888225ULL, // LD1D_4Z_STRIDED |
| 6037 | 3671692547828386657ULL, // LD1D_4Z_STRIDED_IMM |
| 6038 | 3621027051930291041ULL, // LD1D_IMM |
| 6039 | 76694145190038369ULL, // LD1D_Q |
| 6040 | 3621027051930618721ULL, // LD1D_Q_IMM |
| 6041 | 573491ULL, // LD1Fourv16b |
| 6042 | 99156019ULL, // LD1Fourv16b_POST |
| 6043 | 606259ULL, // LD1Fourv1d |
| 6044 | 101285939ULL, // LD1Fourv1d_POST |
| 6045 | 639027ULL, // LD1Fourv2d |
| 6046 | 99221555ULL, // LD1Fourv2d_POST |
| 6047 | 671795ULL, // LD1Fourv2s |
| 6048 | 101351475ULL, // LD1Fourv2s_POST |
| 6049 | 704563ULL, // LD1Fourv4h |
| 6050 | 101384243ULL, // LD1Fourv4h_POST |
| 6051 | 737331ULL, // LD1Fourv4s |
| 6052 | 99319859ULL, // LD1Fourv4s_POST |
| 6053 | 770099ULL, // LD1Fourv8b |
| 6054 | 101449779ULL, // LD1Fourv8b_POST |
| 6055 | 802867ULL, // LD1Fourv8h |
| 6056 | 99385395ULL, // LD1Fourv8h_POST |
| 6057 | 77820045096570400ULL, // LD1H |
| 6058 | 77820045186747936ULL, // LD1H_2Z |
| 6059 | 3664937148387348000ULL, // LD1H_2Z_IMM |
| 6060 | 618388052037152ULL, // LD1H_2Z_STRIDED |
| 6061 | 609591959014944ULL, // LD1H_2Z_STRIDED_IMM |
| 6062 | 77820045186747936ULL, // LD1H_4Z |
| 6063 | 3671692547828403744ULL, // LD1H_4Z_IMM |
| 6064 | 77820045186747936ULL, // LD1H_4Z_STRIDED |
| 6065 | 3671692547828403744ULL, // LD1H_4Z_STRIDED_IMM |
| 6066 | 77820045096554016ULL, // LD1H_D |
| 6067 | 3621027051930291744ULL, // LD1H_D_IMM |
| 6068 | 3621027051930308128ULL, // LD1H_IMM |
| 6069 | 77820045096586784ULL, // LD1H_S |
| 6070 | 3621027051930324512ULL, // LD1H_S_IMM |
| 6071 | 573491ULL, // LD1Onev16b |
| 6072 | 103350323ULL, // LD1Onev16b_POST |
| 6073 | 606259ULL, // LD1Onev1d |
| 6074 | 105480243ULL, // LD1Onev1d_POST |
| 6075 | 639027ULL, // LD1Onev2d |
| 6076 | 103415859ULL, // LD1Onev2d_POST |
| 6077 | 671795ULL, // LD1Onev2s |
| 6078 | 105545779ULL, // LD1Onev2s_POST |
| 6079 | 704563ULL, // LD1Onev4h |
| 6080 | 105578547ULL, // LD1Onev4h_POST |
| 6081 | 737331ULL, // LD1Onev4s |
| 6082 | 103514163ULL, // LD1Onev4s_POST |
| 6083 | 770099ULL, // LD1Onev8b |
| 6084 | 105644083ULL, // LD1Onev8b_POST |
| 6085 | 802867ULL, // LD1Onev8h |
| 6086 | 103579699ULL, // LD1Onev8h_POST |
| 6087 | 3476911863854434596ULL, // LD1RB_D_IMM |
| 6088 | 3476911863854450980ULL, // LD1RB_H_IMM |
| 6089 | 3476911863854418212ULL, // LD1RB_IMM |
| 6090 | 3476911863854467364ULL, // LD1RB_S_IMM |
| 6091 | 57553846773386399ULL, // LD1RD_IMM |
| 6092 | 3520821960221298751ULL, // LD1RH_D_IMM |
| 6093 | 3520821960221315135ULL, // LD1RH_IMM |
| 6094 | 3520821960221331519ULL, // LD1RH_S_IMM |
| 6095 | 75568245282851079ULL, // LD1RO_B |
| 6096 | 78945945003378951ULL, // LD1RO_B_IMM |
| 6097 | 76694145189710991ULL, // LD1RO_D |
| 6098 | 78945945003396239ULL, // LD1RO_D_IMM |
| 6099 | 77820045096570921ULL, // LD1RO_H |
| 6100 | 78945945003413545ULL, // LD1RO_H_IMM |
| 6101 | 80071844910277747ULL, // LD1RO_W |
| 6102 | 78945945003435123ULL, // LD1RO_W_IMM |
| 6103 | 75568245282851100ULL, // LD1RQ_B |
| 6104 | 81197744817064220ULL, // LD1RQ_B_IMM |
| 6105 | 76694145189710999ULL, // LD1RQ_D |
| 6106 | 81197744817081495ULL, // LD1RQ_D_IMM |
| 6107 | 77820045096570935ULL, // LD1RQ_H |
| 6108 | 81197744817098807ULL, // LD1RQ_H_IMM |
| 6109 | 80071844910277755ULL, // LD1RQ_W |
| 6110 | 81197744817120379ULL, // LD1RQ_W_IMM |
| 6111 | 3476911863854434807ULL, // LD1RSB_D_IMM |
| 6112 | 3476911863854451191ULL, // LD1RSB_H_IMM |
| 6113 | 3476911863854467575ULL, // LD1RSB_S_IMM |
| 6114 | 3520821960221298949ULL, // LD1RSH_D_IMM |
| 6115 | 3520821960221331717ULL, // LD1RSH_S_IMM |
| 6116 | 3527577359662359740ULL, // LD1RSW_IMM |
| 6117 | 3527577359662359683ULL, // LD1RW_D_IMM |
| 6118 | 3527577359662392451ULL, // LD1RW_IMM |
| 6119 | 580472ULL, // LD1Rv16b |
| 6120 | 107551608ULL, // LD1Rv16b_POST |
| 6121 | 613240ULL, // LD1Rv1d |
| 6122 | 105487224ULL, // LD1Rv1d_POST |
| 6123 | 646008ULL, // LD1Rv2d |
| 6124 | 105519992ULL, // LD1Rv2d_POST |
| 6125 | 678776ULL, // LD1Rv2s |
| 6126 | 109747064ULL, // LD1Rv2s_POST |
| 6127 | 711544ULL, // LD1Rv4h |
| 6128 | 111876984ULL, // LD1Rv4h_POST |
| 6129 | 744312ULL, // LD1Rv4s |
| 6130 | 109812600ULL, // LD1Rv4s_POST |
| 6131 | 777080ULL, // LD1Rv8b |
| 6132 | 107748216ULL, // LD1Rv8b_POST |
| 6133 | 809848ULL, // LD1Rv8h |
| 6134 | 111975288ULL, // LD1Rv8h_POST |
| 6135 | 75568245282867640ULL, // LD1SB_D |
| 6136 | 3621027051930290616ULL, // LD1SB_D_IMM |
| 6137 | 75568245282884024ULL, // LD1SB_H |
| 6138 | 3621027051930307000ULL, // LD1SB_H_IMM |
| 6139 | 75568245282900408ULL, // LD1SB_S |
| 6140 | 3621027051930323384ULL, // LD1SB_S_IMM |
| 6141 | 77820045096554707ULL, // LD1SH_D |
| 6142 | 3621027051930292435ULL, // LD1SH_D_IMM |
| 6143 | 77820045096587475ULL, // LD1SH_S |
| 6144 | 3621027051930325203ULL, // LD1SH_S_IMM |
| 6145 | 80071844910245011ULL, // LD1SW_D |
| 6146 | 3621027051930297491ULL, // LD1SW_D_IMM |
| 6147 | 573491ULL, // LD1Threev16b |
| 6148 | 113836083ULL, // LD1Threev16b_POST |
| 6149 | 606259ULL, // LD1Threev1d |
| 6150 | 115966003ULL, // LD1Threev1d_POST |
| 6151 | 639027ULL, // LD1Threev2d |
| 6152 | 113901619ULL, // LD1Threev2d_POST |
| 6153 | 671795ULL, // LD1Threev2s |
| 6154 | 116031539ULL, // LD1Threev2s_POST |
| 6155 | 704563ULL, // LD1Threev4h |
| 6156 | 116064307ULL, // LD1Threev4h_POST |
| 6157 | 737331ULL, // LD1Threev4s |
| 6158 | 113999923ULL, // LD1Threev4s_POST |
| 6159 | 770099ULL, // LD1Threev8b |
| 6160 | 116129843ULL, // LD1Threev8b_POST |
| 6161 | 802867ULL, // LD1Threev8h |
| 6162 | 114065459ULL, // LD1Threev8h_POST |
| 6163 | 573491ULL, // LD1Twov16b |
| 6164 | 101253171ULL, // LD1Twov16b_POST |
| 6165 | 606259ULL, // LD1Twov1d |
| 6166 | 103383091ULL, // LD1Twov1d_POST |
| 6167 | 639027ULL, // LD1Twov2d |
| 6168 | 101318707ULL, // LD1Twov2d_POST |
| 6169 | 671795ULL, // LD1Twov2s |
| 6170 | 103448627ULL, // LD1Twov2s_POST |
| 6171 | 704563ULL, // LD1Twov4h |
| 6172 | 103481395ULL, // LD1Twov4h_POST |
| 6173 | 737331ULL, // LD1Twov4s |
| 6174 | 101417011ULL, // LD1Twov4s_POST |
| 6175 | 770099ULL, // LD1Twov8b |
| 6176 | 103546931ULL, // LD1Twov8b_POST |
| 6177 | 802867ULL, // LD1Twov8h |
| 6178 | 101482547ULL, // LD1Twov8h_POST |
| 6179 | 80071844910277584ULL, // LD1W |
| 6180 | 80071845000455120ULL, // LD1W_2Z |
| 6181 | 3664937148387369936ULL, // LD1W_2Z_IMM |
| 6182 | 80071845000455120ULL, // LD1W_2Z_STRIDED |
| 6183 | 3664937148387369936ULL, // LD1W_2Z_STRIDED_IMM |
| 6184 | 80071845000455120ULL, // LD1W_4Z |
| 6185 | 3671692547828425680ULL, // LD1W_4Z_IMM |
| 6186 | 80071845000455120ULL, // LD1W_4Z_STRIDED |
| 6187 | 3671692547828425680ULL, // LD1W_4Z_STRIDED_IMM |
| 6188 | 80071844910244816ULL, // LD1W_D |
| 6189 | 3621027051930297296ULL, // LD1W_D_IMM |
| 6190 | 3621027051930330064ULL, // LD1W_IMM |
| 6191 | 80071844910572496ULL, // LD1W_Q |
| 6192 | 3621027051930624976ULL, // LD1W_Q_IMM |
| 6193 | 82817898338856357ULL, // LD1_MXIPXX_H_B |
| 6194 | 83943798245698995ULL, // LD1_MXIPXX_H_D |
| 6195 | 85069698152541633ULL, // LD1_MXIPXX_H_H |
| 6196 | 86195598059384271ULL, // LD1_MXIPXX_H_Q |
| 6197 | 87321497966226909ULL, // LD1_MXIPXX_H_S |
| 6198 | 82817898338872741ULL, // LD1_MXIPXX_V_B |
| 6199 | 83943798245715379ULL, // LD1_MXIPXX_V_D |
| 6200 | 85069698152558017ULL, // LD1_MXIPXX_V_H |
| 6201 | 86195598059400655ULL, // LD1_MXIPXX_V_Q |
| 6202 | 87321497966243293ULL, // LD1_MXIPXX_V_S |
| 6203 | 118292531ULL, // LD1i16 |
| 6204 | 120406067ULL, // LD1i16_POST |
| 6205 | 118325299ULL, // LD1i32 |
| 6206 | 122535987ULL, // LD1i32_POST |
| 6207 | 118358067ULL, // LD1i64 |
| 6208 | 124665907ULL, // LD1i64_POST |
| 6209 | 118390835ULL, // LD1i8 |
| 6210 | 126795827ULL, // LD1i8_POST |
| 6211 | 75568245282850257ULL, // LD2B |
| 6212 | 3664937148297135569ULL, // LD2B_IMM |
| 6213 | 76694145189710733ULL, // LD2D |
| 6214 | 3664937148297153421ULL, // LD2D_IMM |
| 6215 | 77820045096570461ULL, // LD2H |
| 6216 | 3664937148297170525ULL, // LD2H_IMM |
| 6217 | 87953144258468617ULL, // LD2Q |
| 6218 | 3664937148297485065ULL, // LD2Q_IMM |
| 6219 | 580478ULL, // LD2Rv16b |
| 6220 | 111745918ULL, // LD2Rv16b_POST |
| 6221 | 613246ULL, // LD2Rv1d |
| 6222 | 103390078ULL, // LD2Rv1d_POST |
| 6223 | 646014ULL, // LD2Rv2d |
| 6224 | 103422846ULL, // LD2Rv2d_POST |
| 6225 | 678782ULL, // LD2Rv2s |
| 6226 | 105552766ULL, // LD2Rv2s_POST |
| 6227 | 711550ULL, // LD2Rv4h |
| 6228 | 109779838ULL, // LD2Rv4h_POST |
| 6229 | 744318ULL, // LD2Rv4s |
| 6230 | 105618302ULL, // LD2Rv4s_POST |
| 6231 | 777086ULL, // LD2Rv8b |
| 6232 | 111942526ULL, // LD2Rv8b_POST |
| 6233 | 809854ULL, // LD2Rv8h |
| 6234 | 109878142ULL, // LD2Rv8h_POST |
| 6235 | 573624ULL, // LD2Twov16b |
| 6236 | 101253304ULL, // LD2Twov16b_POST |
| 6237 | 639160ULL, // LD2Twov2d |
| 6238 | 101318840ULL, // LD2Twov2d_POST |
| 6239 | 671928ULL, // LD2Twov2s |
| 6240 | 103448760ULL, // LD2Twov2s_POST |
| 6241 | 704696ULL, // LD2Twov4h |
| 6242 | 103481528ULL, // LD2Twov4h_POST |
| 6243 | 737464ULL, // LD2Twov4s |
| 6244 | 101417144ULL, // LD2Twov4s_POST |
| 6245 | 770232ULL, // LD2Twov8b |
| 6246 | 103547064ULL, // LD2Twov8b_POST |
| 6247 | 803000ULL, // LD2Twov8h |
| 6248 | 101482680ULL, // LD2Twov8h_POST |
| 6249 | 80071844910277636ULL, // LD2W |
| 6250 | 3664937148297192452ULL, // LD2W_IMM |
| 6251 | 118292664ULL, // LD2i16 |
| 6252 | 122503352ULL, // LD2i16_POST |
| 6253 | 118325432ULL, // LD2i32 |
| 6254 | 124633272ULL, // LD2i32_POST |
| 6255 | 118358200ULL, // LD2i64 |
| 6256 | 128860344ULL, // LD2i64_POST |
| 6257 | 118390968ULL, // LD2i8 |
| 6258 | 120504504ULL, // LD2i8_POST |
| 6259 | 75568245282850278ULL, // LD3B |
| 6260 | 89079044164961766ULL, // LD3B_IMM |
| 6261 | 76694145189710745ULL, // LD3D |
| 6262 | 89079044164979609ULL, // LD3D_IMM |
| 6263 | 77820045096570473ULL, // LD3H |
| 6264 | 89079044164996713ULL, // LD3H_IMM |
| 6265 | 87953144258468629ULL, // LD3Q |
| 6266 | 89079044165311253ULL, // LD3Q_IMM |
| 6267 | 580484ULL, // LD3Rv16b |
| 6268 | 130620292ULL, // LD3Rv16b_POST |
| 6269 | 613252ULL, // LD3Rv1d |
| 6270 | 115972996ULL, // LD3Rv1d_POST |
| 6271 | 646020ULL, // LD3Rv2d |
| 6272 | 116005764ULL, // LD3Rv2d_POST |
| 6273 | 678788ULL, // LD3Rv2s |
| 6274 | 132815748ULL, // LD3Rv2s_POST |
| 6275 | 711556ULL, // LD3Rv4h |
| 6276 | 134945668ULL, // LD3Rv4h_POST |
| 6277 | 744324ULL, // LD3Rv4s |
| 6278 | 132881284ULL, // LD3Rv4s_POST |
| 6279 | 777092ULL, // LD3Rv8b |
| 6280 | 130816900ULL, // LD3Rv8b_POST |
| 6281 | 809860ULL, // LD3Rv8h |
| 6282 | 135043972ULL, // LD3Rv8h_POST |
| 6283 | 574081ULL, // LD3Threev16b |
| 6284 | 113836673ULL, // LD3Threev16b_POST |
| 6285 | 639617ULL, // LD3Threev2d |
| 6286 | 113902209ULL, // LD3Threev2d_POST |
| 6287 | 672385ULL, // LD3Threev2s |
| 6288 | 116032129ULL, // LD3Threev2s_POST |
| 6289 | 705153ULL, // LD3Threev4h |
| 6290 | 116064897ULL, // LD3Threev4h_POST |
| 6291 | 737921ULL, // LD3Threev4s |
| 6292 | 114000513ULL, // LD3Threev4s_POST |
| 6293 | 770689ULL, // LD3Threev8b |
| 6294 | 116130433ULL, // LD3Threev8b_POST |
| 6295 | 803457ULL, // LD3Threev8h |
| 6296 | 114066049ULL, // LD3Threev8h_POST |
| 6297 | 80071844910277648ULL, // LD3W |
| 6298 | 89079044165018640ULL, // LD3W_IMM |
| 6299 | 118293121ULL, // LD3i16 |
| 6300 | 137183873ULL, // LD3i16_POST |
| 6301 | 118325889ULL, // LD3i32 |
| 6302 | 139313793ULL, // LD3i32_POST |
| 6303 | 118358657ULL, // LD3i64 |
| 6304 | 141443713ULL, // LD3i64_POST |
| 6305 | 118391425ULL, // LD3i8 |
| 6306 | 143573633ULL, // LD3i8_POST |
| 6307 | 75568245282850320ULL, // LD4B |
| 6308 | 3671692547738191376ULL, // LD4B_IMM |
| 6309 | 76694145189710757ULL, // LD4D |
| 6310 | 3671692547738209189ULL, // LD4D_IMM |
| 6311 | 574111ULL, // LD4Fourv16b |
| 6312 | 99156639ULL, // LD4Fourv16b_POST |
| 6313 | 639647ULL, // LD4Fourv2d |
| 6314 | 99222175ULL, // LD4Fourv2d_POST |
| 6315 | 672415ULL, // LD4Fourv2s |
| 6316 | 101352095ULL, // LD4Fourv2s_POST |
| 6317 | 705183ULL, // LD4Fourv4h |
| 6318 | 101384863ULL, // LD4Fourv4h_POST |
| 6319 | 737951ULL, // LD4Fourv4s |
| 6320 | 99320479ULL, // LD4Fourv4s_POST |
| 6321 | 770719ULL, // LD4Fourv8b |
| 6322 | 101450399ULL, // LD4Fourv8b_POST |
| 6323 | 803487ULL, // LD4Fourv8h |
| 6324 | 99386015ULL, // LD4Fourv8h_POST |
| 6325 | 77820045096570485ULL, // LD4H |
| 6326 | 3671692547738226293ULL, // LD4H_IMM |
| 6327 | 87953144258468641ULL, // LD4Q |
| 6328 | 3671692547738540833ULL, // LD4Q_IMM |
| 6329 | 580490ULL, // LD4Rv16b |
| 6330 | 109648778ULL, // LD4Rv16b_POST |
| 6331 | 613258ULL, // LD4Rv1d |
| 6332 | 101292938ULL, // LD4Rv1d_POST |
| 6333 | 646026ULL, // LD4Rv2d |
| 6334 | 101325706ULL, // LD4Rv2d_POST |
| 6335 | 678794ULL, // LD4Rv2s |
| 6336 | 103455626ULL, // LD4Rv2s_POST |
| 6337 | 711562ULL, // LD4Rv4h |
| 6338 | 105585546ULL, // LD4Rv4h_POST |
| 6339 | 744330ULL, // LD4Rv4s |
| 6340 | 103521162ULL, // LD4Rv4s_POST |
| 6341 | 777098ULL, // LD4Rv8b |
| 6342 | 109845386ULL, // LD4Rv8b_POST |
| 6343 | 809866ULL, // LD4Rv8h |
| 6344 | 105683850ULL, // LD4Rv8h_POST |
| 6345 | 80071844910277660ULL, // LD4W |
| 6346 | 3671692547738248220ULL, // LD4W_IMM |
| 6347 | 118293151ULL, // LD4i16 |
| 6348 | 124600991ULL, // LD4i16_POST |
| 6349 | 118325919ULL, // LD4i32 |
| 6350 | 128828063ULL, // LD4i32_POST |
| 6351 | 118358687ULL, // LD4i64 |
| 6352 | 145638047ULL, // LD4i64_POST |
| 6353 | 118391455ULL, // LD4i8 |
| 6354 | 122602143ULL, // LD4i8_POST |
| 6355 | 984570ULL, // LD64B |
| 6356 | 984562ULL, // LDA64B |
| 6357 | 16108537372ULL, // LDADDAB |
| 6358 | 16108539530ULL, // LDADDAH |
| 6359 | 16108537614ULL, // LDADDALB |
| 6360 | 16108539704ULL, // LDADDALH |
| 6361 | 16108540414ULL, // LDADDALW |
| 6362 | 16108540414ULL, // LDADDALX |
| 6363 | 16108536609ULL, // LDADDAW |
| 6364 | 16108536609ULL, // LDADDAX |
| 6365 | 16108537540ULL, // LDADDB |
| 6366 | 16108539690ULL, // LDADDH |
| 6367 | 16108537795ULL, // LDADDLB |
| 6368 | 16108539804ULL, // LDADDLH |
| 6369 | 16108540924ULL, // LDADDLW |
| 6370 | 16108540924ULL, // LDADDLX |
| 6371 | 16108538893ULL, // LDADDW |
| 6372 | 16108538893ULL, // LDADDX |
| 6373 | 118358084ULL, // LDAP1 |
| 6374 | 90134733431790085ULL, // LDAPPi |
| 6375 | 2508300765535ULL, // LDAPRB |
| 6376 | 2508300767354ULL, // LDAPRH |
| 6377 | 2508300770494ULL, // LDAPRW |
| 6378 | 2719559769278ULL, // LDAPRWpost |
| 6379 | 2508300770494ULL, // LDAPRX |
| 6380 | 2753919507646ULL, // LDAPRXpost |
| 6381 | 29335382585788810ULL, // LDAPURBi |
| 6382 | 29335382585790629ULL, // LDAPURHi |
| 6383 | 29335382585788950ULL, // LDAPURSBWi |
| 6384 | 29335382585788950ULL, // LDAPURSBXi |
| 6385 | 29335382585790756ULL, // LDAPURSHWi |
| 6386 | 29335382585790756ULL, // LDAPURSHXi |
| 6387 | 29335382585795803ULL, // LDAPURSWi |
| 6388 | 29335382585793819ULL, // LDAPURXi |
| 6389 | 29335382585793819ULL, // LDAPURbi |
| 6390 | 29335382585793819ULL, // LDAPURdi |
| 6391 | 29335382585793819ULL, // LDAPURhi |
| 6392 | 29335382585793819ULL, // LDAPURi |
| 6393 | 29335382585793819ULL, // LDAPURqi |
| 6394 | 29335382585793819ULL, // LDAPURsi |
| 6395 | 90134733431789861ULL, // LDAPi |
| 6396 | 2508300765483ULL, // LDARB |
| 6397 | 2508300767302ULL, // LDARH |
| 6398 | 2508300770192ULL, // LDARW |
| 6399 | 2508300770192ULL, // LDARX |
| 6400 | 2508300770651ULL, // LDATXRW |
| 6401 | 2508300770651ULL, // LDATXRX |
| 6402 | 29336138462288585ULL, // LDAXPW |
| 6403 | 29336138462288585ULL, // LDAXPX |
| 6404 | 2508300765594ULL, // LDAXRB |
| 6405 | 2508300767413ULL, // LDAXRH |
| 6406 | 2508300770631ULL, // LDAXRW |
| 6407 | 2508300770631ULL, // LDAXRX |
| 6408 | 16108538900ULL, // LDBFADD |
| 6409 | 16108536617ULL, // LDBFADDA |
| 6410 | 16108540423ULL, // LDBFADDAL |
| 6411 | 16108540932ULL, // LDBFADDL |
| 6412 | 16108545318ULL, // LDBFMAX |
| 6413 | 16108537167ULL, // LDBFMAXA |
| 6414 | 16108540834ULL, // LDBFMAXAL |
| 6415 | 16108541686ULL, // LDBFMAXL |
| 6416 | 16108541839ULL, // LDBFMAXNM |
| 6417 | 16108536753ULL, // LDBFMAXNMA |
| 6418 | 16108540517ULL, // LDBFMAXNMAL |
| 6419 | 16108541218ULL, // LDBFMAXNML |
| 6420 | 16108541948ULL, // LDBFMIN |
| 6421 | 16108536776ULL, // LDBFMINA |
| 6422 | 16108540542ULL, // LDBFMINAL |
| 6423 | 16108541264ULL, // LDBFMINL |
| 6424 | 16108541797ULL, // LDBFMINNM |
| 6425 | 16108536730ULL, // LDBFMINNMA |
| 6426 | 16108540492ULL, // LDBFMINNMAL |
| 6427 | 16108541172ULL, // LDBFMINNML |
| 6428 | 16108537428ULL, // LDCLRAB |
| 6429 | 16108539587ULL, // LDCLRAH |
| 6430 | 16108537689ULL, // LDCLRALB |
| 6431 | 16108539744ULL, // LDCLRALH |
| 6432 | 16108540716ULL, // LDCLRALW |
| 6433 | 16108540716ULL, // LDCLRALX |
| 6434 | 16108537006ULL, // LDCLRAW |
| 6435 | 16108537006ULL, // LDCLRAX |
| 6436 | 16108538176ULL, // LDCLRB |
| 6437 | 16108539995ULL, // LDCLRH |
| 6438 | 16108537897ULL, // LDCLRLB |
| 6439 | 16108539840ULL, // LDCLRLH |
| 6440 | 16108541456ULL, // LDCLRLW |
| 6441 | 16108541456ULL, // LDCLRLX |
| 6442 | 634502232627770ULL, // LDCLRP |
| 6443 | 634502232622147ULL, // LDCLRPA |
| 6444 | 634502232625854ULL, // LDCLRPAL |
| 6445 | 634502232626596ULL, // LDCLRPL |
| 6446 | 16108543048ULL, // LDCLRW |
| 6447 | 16108543048ULL, // LDCLRX |
| 6448 | 16108537437ULL, // LDEORAB |
| 6449 | 16108539596ULL, // LDEORAH |
| 6450 | 16108537699ULL, // LDEORALB |
| 6451 | 16108539754ULL, // LDEORALH |
| 6452 | 16108540756ULL, // LDEORALW |
| 6453 | 16108540756ULL, // LDEORALX |
| 6454 | 16108537042ULL, // LDEORAW |
| 6455 | 16108537042ULL, // LDEORAX |
| 6456 | 16108538199ULL, // LDEORB |
| 6457 | 16108540018ULL, // LDEORH |
| 6458 | 16108537906ULL, // LDEORLB |
| 6459 | 16108539849ULL, // LDEORLH |
| 6460 | 16108541492ULL, // LDEORLW |
| 6461 | 16108541492ULL, // LDEORLX |
| 6462 | 16108543149ULL, // LDEORW |
| 6463 | 16108543149ULL, // LDEORX |
| 6464 | 16108536627ULL, // LDFADDAD |
| 6465 | 16108536627ULL, // LDFADDAH |
| 6466 | 16108540434ULL, // LDFADDALD |
| 6467 | 16108540434ULL, // LDFADDALH |
| 6468 | 16108540434ULL, // LDFADDALS |
| 6469 | 16108536627ULL, // LDFADDAS |
| 6470 | 16108538918ULL, // LDFADDD |
| 6471 | 16108538918ULL, // LDFADDH |
| 6472 | 16108540952ULL, // LDFADDLD |
| 6473 | 16108540952ULL, // LDFADDLH |
| 6474 | 16108540952ULL, // LDFADDLS |
| 6475 | 16108538918ULL, // LDFADDS |
| 6476 | 75568245282850202ULL, // LDFF1B |
| 6477 | 75568245282866586ULL, // LDFF1B_D |
| 6478 | 75568245282882970ULL, // LDFF1B_H |
| 6479 | 75568245282899354ULL, // LDFF1B_S |
| 6480 | 76694145189710695ULL, // LDFF1D |
| 6481 | 77820045096570406ULL, // LDFF1H |
| 6482 | 77820045096554022ULL, // LDFF1H_D |
| 6483 | 77820045096586790ULL, // LDFF1H_S |
| 6484 | 75568245282867647ULL, // LDFF1SB_D |
| 6485 | 75568245282884031ULL, // LDFF1SB_H |
| 6486 | 75568245282900415ULL, // LDFF1SB_S |
| 6487 | 77820045096554714ULL, // LDFF1SH_D |
| 6488 | 77820045096587482ULL, // LDFF1SH_S |
| 6489 | 80071844910245018ULL, // LDFF1SW_D |
| 6490 | 80071844910277590ULL, // LDFF1W |
| 6491 | 80071844910244822ULL, // LDFF1W_D |
| 6492 | 16108537177ULL, // LDFMAXAD |
| 6493 | 16108537177ULL, // LDFMAXAH |
| 6494 | 16108540845ULL, // LDFMAXALD |
| 6495 | 16108540845ULL, // LDFMAXALH |
| 6496 | 16108540845ULL, // LDFMAXALS |
| 6497 | 16108537177ULL, // LDFMAXAS |
| 6498 | 16108545336ULL, // LDFMAXD |
| 6499 | 16108545336ULL, // LDFMAXH |
| 6500 | 16108541706ULL, // LDFMAXLD |
| 6501 | 16108541706ULL, // LDFMAXLH |
| 6502 | 16108541706ULL, // LDFMAXLS |
| 6503 | 16108536765ULL, // LDFMAXNMAD |
| 6504 | 16108536765ULL, // LDFMAXNMAH |
| 6505 | 16108540530ULL, // LDFMAXNMALD |
| 6506 | 16108540530ULL, // LDFMAXNMALH |
| 6507 | 16108540530ULL, // LDFMAXNMALS |
| 6508 | 16108536765ULL, // LDFMAXNMAS |
| 6509 | 16108541861ULL, // LDFMAXNMD |
| 6510 | 16108541861ULL, // LDFMAXNMH |
| 6511 | 16108541242ULL, // LDFMAXNMLD |
| 6512 | 16108541242ULL, // LDFMAXNMLH |
| 6513 | 16108541242ULL, // LDFMAXNMLS |
| 6514 | 16108541861ULL, // LDFMAXNMS |
| 6515 | 16108545336ULL, // LDFMAXS |
| 6516 | 16108536786ULL, // LDFMINAD |
| 6517 | 16108536786ULL, // LDFMINAH |
| 6518 | 16108540553ULL, // LDFMINALD |
| 6519 | 16108540553ULL, // LDFMINALH |
| 6520 | 16108540553ULL, // LDFMINALS |
| 6521 | 16108536786ULL, // LDFMINAS |
| 6522 | 16108541966ULL, // LDFMIND |
| 6523 | 16108541966ULL, // LDFMINH |
| 6524 | 16108541284ULL, // LDFMINLD |
| 6525 | 16108541284ULL, // LDFMINLH |
| 6526 | 16108541284ULL, // LDFMINLS |
| 6527 | 16108536742ULL, // LDFMINNMAD |
| 6528 | 16108536742ULL, // LDFMINNMAH |
| 6529 | 16108540505ULL, // LDFMINNMALD |
| 6530 | 16108540505ULL, // LDFMINNMALH |
| 6531 | 16108540505ULL, // LDFMINNMALS |
| 6532 | 16108536742ULL, // LDFMINNMAS |
| 6533 | 16108541819ULL, // LDFMINNMD |
| 6534 | 16108541819ULL, // LDFMINNMH |
| 6535 | 16108541196ULL, // LDFMINNMLD |
| 6536 | 16108541196ULL, // LDFMINNMLH |
| 6537 | 16108541196ULL, // LDFMINNMLS |
| 6538 | 16108541819ULL, // LDFMINNMS |
| 6539 | 16108541966ULL, // LDFMINS |
| 6540 | 29915929825824231ULL, // LDG |
| 6541 | 2508300769096ULL, // LDGM |
| 6542 | 29336138462288396ULL, // LDIAPPW |
| 6543 | 91586093881022988ULL, // LDIAPPWpost |
| 6544 | 29336138462288396ULL, // LDIAPPX |
| 6545 | 92711993787865612ULL, // LDIAPPXpost |
| 6546 | 2508300765490ULL, // LDLARB |
| 6547 | 2508300767309ULL, // LDLARH |
| 6548 | 2508300770198ULL, // LDLARW |
| 6549 | 2508300770198ULL, // LDLARX |
| 6550 | 3621027051930289570ULL, // LDNF1B_D_IMM |
| 6551 | 3621027051930305954ULL, // LDNF1B_H_IMM |
| 6552 | 3621027051930273186ULL, // LDNF1B_IMM |
| 6553 | 3621027051930322338ULL, // LDNF1B_S_IMM |
| 6554 | 3621027051930291055ULL, // LDNF1D_IMM |
| 6555 | 3621027051930291758ULL, // LDNF1H_D_IMM |
| 6556 | 3621027051930308142ULL, // LDNF1H_IMM |
| 6557 | 3621027051930324526ULL, // LDNF1H_S_IMM |
| 6558 | 3621027051930290632ULL, // LDNF1SB_D_IMM |
| 6559 | 3621027051930307016ULL, // LDNF1SB_H_IMM |
| 6560 | 3621027051930323400ULL, // LDNF1SB_S_IMM |
| 6561 | 3621027051930292451ULL, // LDNF1SH_D_IMM |
| 6562 | 3621027051930325219ULL, // LDNF1SH_S_IMM |
| 6563 | 3621027051930297507ULL, // LDNF1SW_D_IMM |
| 6564 | 3621027051930297310ULL, // LDNF1W_D_IMM |
| 6565 | 3621027051930330078ULL, // LDNF1W_IMM |
| 6566 | 3748183530763475414ULL, // LDNPDi |
| 6567 | 3892298718839331286ULL, // LDNPQi |
| 6568 | 4036413906915187158ULL, // LDNPSi |
| 6569 | 4036413906915187158ULL, // LDNPWi |
| 6570 | 3748183530763475414ULL, // LDNPXi |
| 6571 | 75568245373027754ULL, // LDNT1B_2Z |
| 6572 | 3664937148387313066ULL, // LDNT1B_2Z_IMM |
| 6573 | 600795865712042ULL, // LDNT1B_2Z_STRIDED |
| 6574 | 609591958734250ULL, // LDNT1B_2Z_STRIDED_IMM |
| 6575 | 75568245373027754ULL, // LDNT1B_4Z |
| 6576 | 3671692547828368810ULL, // LDNT1B_4Z_IMM |
| 6577 | 75568245373027754ULL, // LDNT1B_4Z_STRIDED |
| 6578 | 3671692547828368810ULL, // LDNT1B_4Z_STRIDED_IMM |
| 6579 | 3621027051930273194ULL, // LDNT1B_ZRI |
| 6580 | 75568245282850218ULL, // LDNT1B_ZRR |
| 6581 | 3476911692055741866ULL, // LDNT1B_ZZR_D |
| 6582 | 3476911348458390954ULL, // LDNT1B_ZZR_S |
| 6583 | 76694145279888247ULL, // LDNT1D_2Z |
| 6584 | 3664937148387330935ULL, // LDNT1D_2Z_IMM |
| 6585 | 76694145279888247ULL, // LDNT1D_2Z_STRIDED |
| 6586 | 3664937148387330935ULL, // LDNT1D_2Z_STRIDED_IMM |
| 6587 | 76694145279888247ULL, // LDNT1D_4Z |
| 6588 | 3671692547828386679ULL, // LDNT1D_4Z_IMM |
| 6589 | 76694145279888247ULL, // LDNT1D_4Z_STRIDED |
| 6590 | 3671692547828386679ULL, // LDNT1D_4Z_STRIDED_IMM |
| 6591 | 3621027051930291063ULL, // LDNT1D_ZRI |
| 6592 | 76694145189710711ULL, // LDNT1D_ZRR |
| 6593 | 3476911692055743351ULL, // LDNT1D_ZZR_D |
| 6594 | 77820045186747958ULL, // LDNT1H_2Z |
| 6595 | 3664937148387348022ULL, // LDNT1H_2Z_IMM |
| 6596 | 618388052037174ULL, // LDNT1H_2Z_STRIDED |
| 6597 | 609591959014966ULL, // LDNT1H_2Z_STRIDED_IMM |
| 6598 | 77820045186747958ULL, // LDNT1H_4Z |
| 6599 | 3671692547828403766ULL, // LDNT1H_4Z_IMM |
| 6600 | 77820045186747958ULL, // LDNT1H_4Z_STRIDED |
| 6601 | 3671692547828403766ULL, // LDNT1H_4Z_STRIDED_IMM |
| 6602 | 3621027051930308150ULL, // LDNT1H_ZRI |
| 6603 | 77820045096570422ULL, // LDNT1H_ZRR |
| 6604 | 3476911692055744054ULL, // LDNT1H_ZZR_D |
| 6605 | 3476911348458393142ULL, // LDNT1H_ZZR_S |
| 6606 | 3476911692055742929ULL, // LDNT1SB_ZZR_D |
| 6607 | 3476911348458392017ULL, // LDNT1SB_ZZR_S |
| 6608 | 3476911692055744748ULL, // LDNT1SH_ZZR_D |
| 6609 | 3476911348458393836ULL, // LDNT1SH_ZZR_S |
| 6610 | 3476911692055749804ULL, // LDNT1SW_ZZR_D |
| 6611 | 80071845000455142ULL, // LDNT1W_2Z |
| 6612 | 3664937148387369958ULL, // LDNT1W_2Z_IMM |
| 6613 | 80071845000455142ULL, // LDNT1W_2Z_STRIDED |
| 6614 | 3664937148387369958ULL, // LDNT1W_2Z_STRIDED_IMM |
| 6615 | 80071845000455142ULL, // LDNT1W_4Z |
| 6616 | 3671692547828425702ULL, // LDNT1W_4Z_IMM |
| 6617 | 80071845000455142ULL, // LDNT1W_4Z_STRIDED |
| 6618 | 3671692547828425702ULL, // LDNT1W_4Z_STRIDED_IMM |
| 6619 | 3621027051930330086ULL, // LDNT1W_ZRI |
| 6620 | 80071844910277606ULL, // LDNT1W_ZRR |
| 6621 | 3476911692055749606ULL, // LDNT1W_ZZR_D |
| 6622 | 3476911348458398694ULL, // LDNT1W_ZZR_S |
| 6623 | 3748183530763475291ULL, // LDPDi |
| 6624 | 4273178347894528347ULL, // LDPDpost |
| 6625 | 4180854555533433179ULL, // LDPDpre |
| 6626 | 3892298718839331163ULL, // LDPQi |
| 6627 | 4417293535970384219ULL, // LDPQpost |
| 6628 | 4324969743609289051ULL, // LDPQpre |
| 6629 | 4036413906915189941ULL, // LDPSWi |
| 6630 | 4561408724046242997ULL, // LDPSWpost |
| 6631 | 4469084931685147829ULL, // LDPSWpre |
| 6632 | 4036413906915187035ULL, // LDPSi |
| 6633 | 4561408724046240091ULL, // LDPSpost |
| 6634 | 4469084931685144923ULL, // LDPSpre |
| 6635 | 4036413906915187035ULL, // LDPWi |
| 6636 | 4561408724046240091ULL, // LDPWpost |
| 6637 | 4469084931685144923ULL, // LDPWpre |
| 6638 | 3748183530763475291ULL, // LDPXi |
| 6639 | 4273178347894528347ULL, // LDPXpost |
| 6640 | 4180854555533433179ULL, // LDPXpre |
| 6641 | 651323240366848ULL, // LDRAAindexed |
| 6642 | 660124433957632ULL, // LDRAAwriteback |
| 6643 | 651323240367686ULL, // LDRABindexed |
| 6644 | 660124433958470ULL, // LDRABwriteback |
| 6645 | 389816372218170ULL, // LDRBBpost |
| 6646 | 94963037725051194ULL, // LDRBBpre |
| 6647 | 4612873903342111034ULL, // LDRBBroW |
| 6648 | 4756989091417966906ULL, // LDRBBroX |
| 6649 | 668915426412858ULL, // LDRBBui |
| 6650 | 389816372222974ULL, // LDRBpost |
| 6651 | 94963037725055998ULL, // LDRBpre |
| 6652 | 4612873903342115838ULL, // LDRBroW |
| 6653 | 4756989091417971710ULL, // LDRBroX |
| 6654 | 668915426417662ULL, // LDRBui |
| 6655 | 6713007102ULL, // LDRDl |
| 6656 | 389816372222974ULL, // LDRDpost |
| 6657 | 94963037725055998ULL, // LDRDpre |
| 6658 | 4901104279493827582ULL, // LDRDroW |
| 6659 | 5045219467569683454ULL, // LDRDroX |
| 6660 | 677711519439870ULL, // LDRDui |
| 6661 | 389816372219989ULL, // LDRHHpost |
| 6662 | 94963037725053013ULL, // LDRHHpre |
| 6663 | 5189334655645536341ULL, // LDRHHroW |
| 6664 | 5333449843721392213ULL, // LDRHHroX |
| 6665 | 686507612459093ULL, // LDRHHui |
| 6666 | 389816372222974ULL, // LDRHpost |
| 6667 | 94963037725055998ULL, // LDRHpre |
| 6668 | 5189334655645539326ULL, // LDRHroW |
| 6669 | 5333449843721395198ULL, // LDRHroX |
| 6670 | 686507612462078ULL, // LDRHui |
| 6671 | 6713007102ULL, // LDRQl |
| 6672 | 389816372222974ULL, // LDRQpost |
| 6673 | 94963037725055998ULL, // LDRQpre |
| 6674 | 5477565031797251070ULL, // LDRQroW |
| 6675 | 5621680219873106942ULL, // LDRQroX |
| 6676 | 695303705484286ULL, // LDRQui |
| 6677 | 389816372218367ULL, // LDRSBWpost |
| 6678 | 94963037725051391ULL, // LDRSBWpre |
| 6679 | 4612873903342111231ULL, // LDRSBWroW |
| 6680 | 4756989091417967103ULL, // LDRSBWroX |
| 6681 | 668915426413055ULL, // LDRSBWui |
| 6682 | 389816372218367ULL, // LDRSBXpost |
| 6683 | 94963037725051391ULL, // LDRSBXpre |
| 6684 | 4612873903342111231ULL, // LDRSBXroW |
| 6685 | 4756989091417967103ULL, // LDRSBXroX |
| 6686 | 668915426413055ULL, // LDRSBXui |
| 6687 | 389816372220173ULL, // LDRSHWpost |
| 6688 | 94963037725053197ULL, // LDRSHWpre |
| 6689 | 5189334655645536525ULL, // LDRSHWroW |
| 6690 | 5333449843721392397ULL, // LDRSHWroX |
| 6691 | 686507612459277ULL, // LDRSHWui |
| 6692 | 389816372220173ULL, // LDRSHXpost |
| 6693 | 94963037725053197ULL, // LDRSHXpre |
| 6694 | 5189334655645536525ULL, // LDRSHXroW |
| 6695 | 5333449843721392397ULL, // LDRSHXroX |
| 6696 | 686507612459277ULL, // LDRSHXui |
| 6697 | 6713009348ULL, // LDRSWl |
| 6698 | 389816372225220ULL, // LDRSWpost |
| 6699 | 94963037725058244ULL, // LDRSWpre |
| 6700 | 5765795407948965060ULL, // LDRSWroW |
| 6701 | 5909910596024820932ULL, // LDRSWroX |
| 6702 | 704099798508740ULL, // LDRSWui |
| 6703 | 6713007102ULL, // LDRSl |
| 6704 | 389816372222974ULL, // LDRSpost |
| 6705 | 94963037725055998ULL, // LDRSpre |
| 6706 | 5765795407948962814ULL, // LDRSroW |
| 6707 | 5909910596024818686ULL, // LDRSroX |
| 6708 | 704099798506494ULL, // LDRSui |
| 6709 | 6713007102ULL, // LDRWl |
| 6710 | 389816372222974ULL, // LDRWpost |
| 6711 | 94963037725055998ULL, // LDRWpre |
| 6712 | 5765795407948962814ULL, // LDRWroW |
| 6713 | 5909910596024818686ULL, // LDRWroX |
| 6714 | 704099798506494ULL, // LDRWui |
| 6715 | 6713007102ULL, // LDRXl |
| 6716 | 389816372222974ULL, // LDRXpost |
| 6717 | 94963037725055998ULL, // LDRXpre |
| 6718 | 4901104279493827582ULL, // LDRXroW |
| 6719 | 5045219467569683454ULL, // LDRXroX |
| 6720 | 677711519439870ULL, // LDRXui |
| 6721 | 95763477090507774ULL, // LDR_PXI |
| 6722 | 2508300770302ULL, // LDR_TX |
| 6723 | 1039358ULL, // LDR_ZA |
| 6724 | 95763477090507774ULL, // LDR_ZXI |
| 6725 | 16108537453ULL, // LDSETAB |
| 6726 | 16108539612ULL, // LDSETAH |
| 6727 | 16108537717ULL, // LDSETALB |
| 6728 | 16108539772ULL, // LDSETALH |
| 6729 | 16108540786ULL, // LDSETALW |
| 6730 | 16108540786ULL, // LDSETALX |
| 6731 | 16108537095ULL, // LDSETAW |
| 6732 | 16108537095ULL, // LDSETAX |
| 6733 | 16108538400ULL, // LDSETB |
| 6734 | 16108540206ULL, // LDSETH |
| 6735 | 16108537957ULL, // LDSETLB |
| 6736 | 16108539865ULL, // LDSETLH |
| 6737 | 16108541562ULL, // LDSETLW |
| 6738 | 16108541562ULL, // LDSETLX |
| 6739 | 634502232627828ULL, // LDSETP |
| 6740 | 634502232622198ULL, // LDSETPA |
| 6741 | 634502232625910ULL, // LDSETPAL |
| 6742 | 634502232626655ULL, // LDSETPL |
| 6743 | 16108543832ULL, // LDSETW |
| 6744 | 16108543832ULL, // LDSETX |
| 6745 | 16108537462ULL, // LDSMAXAB |
| 6746 | 16108539621ULL, // LDSMAXAH |
| 6747 | 16108537727ULL, // LDSMAXALB |
| 6748 | 16108539782ULL, // LDSMAXALH |
| 6749 | 16108540855ULL, // LDSMAXALW |
| 6750 | 16108540855ULL, // LDSMAXALX |
| 6751 | 16108537186ULL, // LDSMAXAW |
| 6752 | 16108537186ULL, // LDSMAXAX |
| 6753 | 16108538556ULL, // LDSMAXB |
| 6754 | 16108540238ULL, // LDSMAXH |
| 6755 | 16108537966ULL, // LDSMAXLB |
| 6756 | 16108539907ULL, // LDSMAXLH |
| 6757 | 16108541724ULL, // LDSMAXLW |
| 6758 | 16108541724ULL, // LDSMAXLX |
| 6759 | 16108545352ULL, // LDSMAXW |
| 6760 | 16108545352ULL, // LDSMAXX |
| 6761 | 16108537381ULL, // LDSMINAB |
| 6762 | 16108539560ULL, // LDSMINAH |
| 6763 | 16108537659ULL, // LDSMINALB |
| 6764 | 16108539714ULL, // LDSMINALH |
| 6765 | 16108540563ULL, // LDSMINALW |
| 6766 | 16108540563ULL, // LDSMINALX |
| 6767 | 16108536795ULL, // LDSMINAW |
| 6768 | 16108536795ULL, // LDSMINAX |
| 6769 | 16108538009ULL, // LDSMINB |
| 6770 | 16108539927ULL, // LDSMINH |
| 6771 | 16108537870ULL, // LDSMINLB |
| 6772 | 16108539813ULL, // LDSMINLH |
| 6773 | 16108541302ULL, // LDSMINLW |
| 6774 | 16108541302ULL, // LDSMINLX |
| 6775 | 16108541982ULL, // LDSMINW |
| 6776 | 16108541982ULL, // LDSMINX |
| 6777 | 16108540444ULL, // LDTADDALW |
| 6778 | 16108540444ULL, // LDTADDALX |
| 6779 | 16108536636ULL, // LDTADDAW |
| 6780 | 16108536636ULL, // LDTADDAX |
| 6781 | 16108540993ULL, // LDTADDLW |
| 6782 | 16108540993ULL, // LDTADDLX |
| 6783 | 16108538995ULL, // LDTADDW |
| 6784 | 16108538995ULL, // LDTADDX |
| 6785 | 16108540736ULL, // LDTCLRALW |
| 6786 | 16108540736ULL, // LDTCLRALX |
| 6787 | 16108537024ULL, // LDTCLRAW |
| 6788 | 16108537024ULL, // LDTCLRAX |
| 6789 | 16108541474ULL, // LDTCLRLW |
| 6790 | 16108541474ULL, // LDTCLRLX |
| 6791 | 16108543064ULL, // LDTCLRW |
| 6792 | 16108543064ULL, // LDTCLRX |
| 6793 | 3892298718839331313ULL, // LDTNPQi |
| 6794 | 3748183530763475441ULL, // LDTNPXi |
| 6795 | 3892298718839331438ULL, // LDTPQi |
| 6796 | 4417293535970384494ULL, // LDTPQpost |
| 6797 | 4324969743609289326ULL, // LDTPQpre |
| 6798 | 3748183530763475566ULL, // LDTPi |
| 6799 | 4273178347894528622ULL, // LDTPpost |
| 6800 | 4180854555533433454ULL, // LDTPpre |
| 6801 | 29335382585788775ULL, // LDTRBi |
| 6802 | 29335382585790594ULL, // LDTRHi |
| 6803 | 29335382585788934ULL, // LDTRSBWi |
| 6804 | 29335382585788934ULL, // LDTRSBXi |
| 6805 | 29335382585790740ULL, // LDTRSHWi |
| 6806 | 29335382585790740ULL, // LDTRSHXi |
| 6807 | 29335382585795787ULL, // LDTRSWi |
| 6808 | 29335382585793777ULL, // LDTRWi |
| 6809 | 29335382585793777ULL, // LDTRXi |
| 6810 | 16108540806ULL, // LDTSETALW |
| 6811 | 16108540806ULL, // LDTSETALX |
| 6812 | 16108537113ULL, // LDTSETAW |
| 6813 | 16108537113ULL, // LDTSETAX |
| 6814 | 16108541580ULL, // LDTSETLW |
| 6815 | 16108541580ULL, // LDTSETLX |
| 6816 | 16108543848ULL, // LDTSETW |
| 6817 | 16108543848ULL, // LDTSETX |
| 6818 | 2508300770659ULL, // LDTXRWr |
| 6819 | 2508300770659ULL, // LDTXRXr |
| 6820 | 16108537472ULL, // LDUMAXAB |
| 6821 | 16108539631ULL, // LDUMAXAH |
| 6822 | 16108537738ULL, // LDUMAXALB |
| 6823 | 16108539793ULL, // LDUMAXALH |
| 6824 | 16108540865ULL, // LDUMAXALW |
| 6825 | 16108540865ULL, // LDUMAXALX |
| 6826 | 16108537195ULL, // LDUMAXAW |
| 6827 | 16108537195ULL, // LDUMAXAX |
| 6828 | 16108538565ULL, // LDUMAXB |
| 6829 | 16108540247ULL, // LDUMAXH |
| 6830 | 16108537976ULL, // LDUMAXLB |
| 6831 | 16108539917ULL, // LDUMAXLH |
| 6832 | 16108541733ULL, // LDUMAXLW |
| 6833 | 16108541733ULL, // LDUMAXLX |
| 6834 | 16108545360ULL, // LDUMAXW |
| 6835 | 16108545360ULL, // LDUMAXX |
| 6836 | 16108537391ULL, // LDUMINAB |
| 6837 | 16108539570ULL, // LDUMINAH |
| 6838 | 16108537670ULL, // LDUMINALB |
| 6839 | 16108539725ULL, // LDUMINALH |
| 6840 | 16108540573ULL, // LDUMINALW |
| 6841 | 16108540573ULL, // LDUMINALX |
| 6842 | 16108536804ULL, // LDUMINAW |
| 6843 | 16108536804ULL, // LDUMINAX |
| 6844 | 16108538018ULL, // LDUMINB |
| 6845 | 16108539936ULL, // LDUMINH |
| 6846 | 16108537880ULL, // LDUMINLB |
| 6847 | 16108539823ULL, // LDUMINLH |
| 6848 | 16108541311ULL, // LDUMINLW |
| 6849 | 16108541311ULL, // LDUMINLX |
| 6850 | 16108541990ULL, // LDUMINW |
| 6851 | 16108541990ULL, // LDUMINX |
| 6852 | 29335382585788795ULL, // LDURBBi |
| 6853 | 29335382585793806ULL, // LDURBi |
| 6854 | 29335382585793806ULL, // LDURDi |
| 6855 | 29335382585790614ULL, // LDURHHi |
| 6856 | 29335382585793806ULL, // LDURHi |
| 6857 | 29335382585793806ULL, // LDURQi |
| 6858 | 29335382585788942ULL, // LDURSBWi |
| 6859 | 29335382585788942ULL, // LDURSBXi |
| 6860 | 29335382585790748ULL, // LDURSHWi |
| 6861 | 29335382585790748ULL, // LDURSHXi |
| 6862 | 29335382585795795ULL, // LDURSWi |
| 6863 | 29335382585793806ULL, // LDURSi |
| 6864 | 29335382585793806ULL, // LDURWi |
| 6865 | 29335382585793806ULL, // LDURXi |
| 6866 | 29336138462288613ULL, // LDXPW |
| 6867 | 29336138462288613ULL, // LDXPX |
| 6868 | 2508300765602ULL, // LDXRB |
| 6869 | 2508300767421ULL, // LDXRH |
| 6870 | 2508300770638ULL, // LDXRW |
| 6871 | 2508300770638ULL, // LDXRX |
| 6872 | 145276307521969313ULL, // LSLR_ZPmZ_B |
| 6873 | 289400291690863777ULL, // LSLR_ZPmZ_D |
| 6874 | 439233043046145185ULL, // LSLR_ZPmZ_H |
| 6875 | 577639463935630497ULL, // LSLR_ZPmZ_S |
| 6876 | 61984970135129ULL, // LSLVWr |
| 6877 | 61984970135129ULL, // LSLVXr |
| 6878 | 289391495597823577ULL, // LSL_WIDE_ZPmZ_B |
| 6879 | 19272377793844825ULL, // LSL_WIDE_ZPmZ_H |
| 6880 | 289409087783917145ULL, // LSL_WIDE_ZPmZ_S |
| 6881 | 44396273768025ULL, // LSL_WIDE_ZZZ_B |
| 6882 | 18419263018585ULL, // LSL_WIDE_ZZZ_H |
| 6883 | 44396542252633ULL, // LSL_WIDE_ZZZ_S |
| 6884 | 1161119446111833ULL, // LSL_ZPmI_B |
| 6885 | 1169915539150425ULL, // LSL_ZPmI_D |
| 6886 | 450492042114569817ULL, // LSL_ZPmI_H |
| 6887 | 1178711632205401ULL, // LSL_ZPmI_S |
| 6888 | 145276307521967705ULL, // LSL_ZPmZ_B |
| 6889 | 289400291690862169ULL, // LSL_ZPmZ_D |
| 6890 | 439233043046143577ULL, // LSL_ZPmZ_H |
| 6891 | 577639463935628889ULL, // LSL_ZPmZ_S |
| 6892 | 61988459812441ULL, // LSL_ZZI_B |
| 6893 | 61987654522457ULL, // LSL_ZZI_D |
| 6894 | 18591061710425ULL, // LSL_ZZI_H |
| 6895 | 61988728297049ULL, // LSL_ZZI_S |
| 6896 | 145276307521969360ULL, // LSRR_ZPmZ_B |
| 6897 | 289400291690863824ULL, // LSRR_ZPmZ_D |
| 6898 | 439233043046145232ULL, // LSRR_ZPmZ_H |
| 6899 | 577639463935630544ULL, // LSRR_ZPmZ_S |
| 6900 | 61984970136801ULL, // LSRVWr |
| 6901 | 61984970136801ULL, // LSRVXr |
| 6902 | 289391495597825249ULL, // LSR_WIDE_ZPmZ_B |
| 6903 | 19272377793846497ULL, // LSR_WIDE_ZPmZ_H |
| 6904 | 289409087783918817ULL, // LSR_WIDE_ZPmZ_S |
| 6905 | 44396273769697ULL, // LSR_WIDE_ZZZ_B |
| 6906 | 18419263020257ULL, // LSR_WIDE_ZZZ_H |
| 6907 | 44396542254305ULL, // LSR_WIDE_ZZZ_S |
| 6908 | 1161119446113505ULL, // LSR_ZPmI_B |
| 6909 | 1169915539152097ULL, // LSR_ZPmI_D |
| 6910 | 450492042114571489ULL, // LSR_ZPmI_H |
| 6911 | 1178711632207073ULL, // LSR_ZPmI_S |
| 6912 | 145276307521969377ULL, // LSR_ZPmZ_B |
| 6913 | 289400291690863841ULL, // LSR_ZPmZ_D |
| 6914 | 439233043046145249ULL, // LSR_ZPmZ_H |
| 6915 | 577639463935630561ULL, // LSR_ZPmZ_S |
| 6916 | 61988459814113ULL, // LSR_ZZI_B |
| 6917 | 61987654524129ULL, // LSR_ZZI_D |
| 6918 | 18591061712097ULL, // LSR_ZZI_H |
| 6919 | 61988728298721ULL, // LSR_ZZI_S |
| 6920 | 2833881596113ULL, // LUT2_B |
| 6921 | 16661971153ULL, // LUT2_H |
| 6922 | 2833881596580ULL, // LUT4_B |
| 6923 | 16661971620ULL, // LUT4_H |
| 6924 | 337105867915473ULL, // LUTI2_2ZTZI_B |
| 6925 | 337105867948241ULL, // LUTI2_2ZTZI_H |
| 6926 | 337105867964625ULL, // LUTI2_2ZTZI_S |
| 6927 | 337105867915473ULL, // LUTI2_4ZTZI_B |
| 6928 | 337105867948241ULL, // LUTI2_4ZTZI_H |
| 6929 | 337105867964625ULL, // LUTI2_4ZTZI_S |
| 6930 | 51378391662231761ULL, // LUTI2_S_2ZTZI_B |
| 6931 | 51378391662510289ULL, // LUTI2_S_2ZTZI_H |
| 6932 | 337105867915473ULL, // LUTI2_S_4ZTZI_B |
| 6933 | 337105867948241ULL, // LUTI2_S_4ZTZI_H |
| 6934 | 51378391661707473ULL, // LUTI2_ZTZI_B |
| 6935 | 337105867833553ULL, // LUTI2_ZTZI_H |
| 6936 | 51378391661756625ULL, // LUTI2_ZTZI_S |
| 6937 | 337113595805905ULL, // LUTI2_ZZZI_B |
| 6938 | 337105842667729ULL, // LUTI2_ZZZI_H |
| 6939 | 337105867915940ULL, // LUTI4_2ZTZI_B |
| 6940 | 337105867948708ULL, // LUTI4_2ZTZI_H |
| 6941 | 337105867965092ULL, // LUTI4_2ZTZI_S |
| 6942 | 337105867948708ULL, // LUTI4_4ZTZI_H |
| 6943 | 337105867965092ULL, // LUTI4_4ZTZI_S |
| 6944 | 20480878854820ULL, // LUTI4_4ZZT2Z |
| 6945 | 51378391662232228ULL, // LUTI4_S_2ZTZI_B |
| 6946 | 51378391662510756ULL, // LUTI4_S_2ZTZI_H |
| 6947 | 337105867948708ULL, // LUTI4_S_4ZTZI_H |
| 6948 | 20480878854820ULL, // LUTI4_S_4ZZT2Z |
| 6949 | 337105842668196ULL, // LUTI4_Z2ZZI |
| 6950 | 51378391661707940ULL, // LUTI4_ZTZI_B |
| 6951 | 337105867834020ULL, // LUTI4_ZTZI_H |
| 6952 | 51378391661757092ULL, // LUTI4_ZTZI_S |
| 6953 | 337113595806372ULL, // LUTI4_ZZZI_B |
| 6954 | 337105842668196ULL, // LUTI4_ZZZI_H |
| 6955 | 337140202521279ULL, // LUTI6_4Z2Z2ZI |
| 6956 | 20480878854847ULL, // LUTI6_4ZT3Z |
| 6957 | 337140202521279ULL, // LUTI6_S_4Z2Z2ZI |
| 6958 | 20480878854847ULL, // LUTI6_S_4ZT3Z |
| 6959 | 20454247006911ULL, // LUTI6_Z2ZZ |
| 6960 | 337105842668223ULL, // LUTI6_Z2ZZI_H |
| 6961 | 712895853789887ULL, // LUTI6_ZTZ |
| 6962 | 1187884876980697ULL, // MADDPT |
| 6963 | 1187884876975189ULL, // MADDWrrr |
| 6964 | 1187884876975189ULL, // MADDXrrr |
| 6965 | 9210022650322ULL, // MAD_CPA |
| 6966 | 6053963834259966898ULL, // MAD_ZPmZZ_B |
| 6967 | 2595208116532464562ULL, // MAD_ZPmZZ_D |
| 6968 | 459499172649831346ULL, // MAD_ZPmZZ_H |
| 6969 | 2739340896794397618ULL, // MAD_ZPmZZ_S |
| 6970 | 145276376241442595ULL, // MATCH_PPzZZ_B |
| 6971 | 439233043583012643ULL, // MATCH_PPzZZ_H |
| 6972 | 9210022650307ULL, // MLA_CPA |
| 6973 | 6053963834259964784ULL, // MLA_ZPmZZ_B |
| 6974 | 2595208116532462448ULL, // MLA_ZPmZZ_D |
| 6975 | 459499172649829232ULL, // MLA_ZPmZZ_H |
| 6976 | 2739340896794395504ULL, // MLA_ZPmZZ_S |
| 6977 | 457124572200747888ULL, // MLA_ZZZI_D |
| 6978 | 369507086435184ULL, // MLA_ZZZI_H |
| 6979 | 457142164655260528ULL, // MLA_ZZZI_S |
| 6980 | 8005100714984304ULL, // MLAv16i8 |
| 6981 | 9131034983662448ULL, // MLAv2i32 |
| 6982 | 1050588448813089648ULL, // MLAv2i32_indexed |
| 6983 | 10256969254437744ULL, // MLAv4i16 |
| 6984 | 1034825884481225584ULL, // MLAv4i16_indexed |
| 6985 | 3501432376525680ULL, // MLAv4i32 |
| 6986 | 1050588345740166000ULL, // MLAv4i32_indexed |
| 6987 | 4627366645203824ULL, // MLAv8i16 |
| 6988 | 1034825781406204784ULL, // MLAv8i16_indexed |
| 6989 | 11382903527310192ULL, // MLAv8i8 |
| 6990 | 6053963834259971661ULL, // MLS_ZPmZZ_B |
| 6991 | 2595208116532469325ULL, // MLS_ZPmZZ_D |
| 6992 | 459499172649836109ULL, // MLS_ZPmZZ_H |
| 6993 | 2739340896794402381ULL, // MLS_ZPmZZ_S |
| 6994 | 457124572200754765ULL, // MLS_ZZZI_D |
| 6995 | 369507086442061ULL, // MLS_ZZZI_H |
| 6996 | 457142164655267405ULL, // MLS_ZZZI_S |
| 6997 | 8005100714991181ULL, // MLSv16i8 |
| 6998 | 9131034983669325ULL, // MLSv2i32 |
| 6999 | 1050588448813096525ULL, // MLSv2i32_indexed |
| 7000 | 10256969254444621ULL, // MLSv4i16 |
| 7001 | 1034825884481232461ULL, // MLSv4i16_indexed |
| 7002 | 3501432376532557ULL, // MLSv4i32 |
| 7003 | 1050588345740172877ULL, // MLSv4i32_indexed |
| 7004 | 4627366645210701ULL, // MLSv8i16 |
| 7005 | 1034825781406211661ULL, // MLSv8i16_indexed |
| 7006 | 11382903527317069ULL, // MLSv8i8 |
| 7007 | 17059244063ULL, // MOPSSETGE |
| 7008 | 17059244142ULL, // MOPSSETGEN |
| 7009 | 17059245102ULL, // MOPSSETGET |
| 7010 | 17059244533ULL, // MOPSSETGETN |
| 7011 | 17328924109ULL, // MOVAZ_2ZMI_H_B |
| 7012 | 17328940493ULL, // MOVAZ_2ZMI_H_D |
| 7013 | 17328956877ULL, // MOVAZ_2ZMI_H_H |
| 7014 | 17328973261ULL, // MOVAZ_2ZMI_H_S |
| 7015 | 17331021261ULL, // MOVAZ_2ZMI_V_B |
| 7016 | 17331037645ULL, // MOVAZ_2ZMI_V_D |
| 7017 | 17331054029ULL, // MOVAZ_2ZMI_V_H |
| 7018 | 17331070413ULL, // MOVAZ_2ZMI_V_S |
| 7019 | 17597359565ULL, // MOVAZ_4ZMI_H_B |
| 7020 | 17597375949ULL, // MOVAZ_4ZMI_H_D |
| 7021 | 17597392333ULL, // MOVAZ_4ZMI_H_H |
| 7022 | 17597408717ULL, // MOVAZ_4ZMI_H_S |
| 7023 | 17599456717ULL, // MOVAZ_4ZMI_V_B |
| 7024 | 17599473101ULL, // MOVAZ_4ZMI_V_D |
| 7025 | 17599489485ULL, // MOVAZ_4ZMI_V_H |
| 7026 | 17599505869ULL, // MOVAZ_4ZMI_V_S |
| 7027 | 17870005709ULL, // MOVAZ_VG2_2ZMXI |
| 7028 | 18138441165ULL, // MOVAZ_VG4_4ZMXI |
| 7029 | 18255750605ULL, // MOVAZ_ZMI_H_B |
| 7030 | 18255766989ULL, // MOVAZ_ZMI_H_D |
| 7031 | 721707400766925ULL, // MOVAZ_ZMI_H_H |
| 7032 | 721707401176525ULL, // MOVAZ_ZMI_H_Q |
| 7033 | 18255799757ULL, // MOVAZ_ZMI_H_S |
| 7034 | 18524186061ULL, // MOVAZ_ZMI_V_B |
| 7035 | 18524202445ULL, // MOVAZ_ZMI_V_D |
| 7036 | 721707402864077ULL, // MOVAZ_ZMI_V_H |
| 7037 | 721707403273677ULL, // MOVAZ_ZMI_V_Q |
| 7038 | 18524235213ULL, // MOVAZ_ZMI_V_S |
| 7039 | 730493293315401ULL, // MOVA_2ZMXI_H_B |
| 7040 | 730493293331785ULL, // MOVA_2ZMXI_H_D |
| 7041 | 730493293348169ULL, // MOVA_2ZMXI_H_H |
| 7042 | 730493293364553ULL, // MOVA_2ZMXI_H_S |
| 7043 | 730493295412553ULL, // MOVA_2ZMXI_V_B |
| 7044 | 730493295428937ULL, // MOVA_2ZMXI_V_D |
| 7045 | 730493295445321ULL, // MOVA_2ZMXI_V_H |
| 7046 | 730493295461705ULL, // MOVA_2ZMXI_V_S |
| 7047 | 739289386337609ULL, // MOVA_4ZMXI_H_B |
| 7048 | 739289386353993ULL, // MOVA_4ZMXI_H_D |
| 7049 | 739289386370377ULL, // MOVA_4ZMXI_H_H |
| 7050 | 739289386386761ULL, // MOVA_4ZMXI_H_S |
| 7051 | 739289388434761ULL, // MOVA_4ZMXI_V_B |
| 7052 | 739289388451145ULL, // MOVA_4ZMXI_V_D |
| 7053 | 739289388467529ULL, // MOVA_4ZMXI_V_H |
| 7054 | 739289388483913ULL, // MOVA_4ZMXI_V_S |
| 7055 | 750590989174089ULL, // MOVA_MXI2Z_H_B |
| 7056 | 759387082196297ULL, // MOVA_MXI2Z_H_D |
| 7057 | 768183175218505ULL, // MOVA_MXI2Z_H_H |
| 7058 | 776979268240713ULL, // MOVA_MXI2Z_H_S |
| 7059 | 750590989190473ULL, // MOVA_MXI2Z_V_B |
| 7060 | 759387082212681ULL, // MOVA_MXI2Z_V_D |
| 7061 | 768183175234889ULL, // MOVA_MXI2Z_V_H |
| 7062 | 776979268257097ULL, // MOVA_MXI2Z_V_S |
| 7063 | 750625348912457ULL, // MOVA_MXI4Z_H_B |
| 7064 | 759421441934665ULL, // MOVA_MXI4Z_H_D |
| 7065 | 768217534956873ULL, // MOVA_MXI4Z_H_H |
| 7066 | 777013627979081ULL, // MOVA_MXI4Z_H_S |
| 7067 | 750625348928841ULL, // MOVA_MXI4Z_V_B |
| 7068 | 759421441951049ULL, // MOVA_MXI4Z_V_D |
| 7069 | 768217534973257ULL, // MOVA_MXI4Z_V_H |
| 7070 | 777013627995465ULL, // MOVA_MXI4Z_V_S |
| 7071 | 17876288841ULL, // MOVA_VG2_2ZMXI |
| 7072 | 18455243998537ULL, // MOVA_VG2_MXI2Z |
| 7073 | 18144724297ULL, // MOVA_VG4_4ZMXI |
| 7074 | 18455512433993ULL, // MOVA_VG4_MXI4Z |
| 7075 | 18792600017ULL, // MOVID |
| 7076 | 19067408849ULL, // MOVIv16b_ns |
| 7077 | 18803167697ULL, // MOVIv2d_ns |
| 7078 | 3008366744017ULL, // MOVIv2i32 |
| 7079 | 3008366744017ULL, // MOVIv2s_msl |
| 7080 | 3008370938321ULL, // MOVIv4i16 |
| 7081 | 3008373035473ULL, // MOVIv4i32 |
| 7082 | 3008373035473ULL, // MOVIv4s_msl |
| 7083 | 19079991761ULL, // MOVIv8b_ns |
| 7084 | 3008375132625ULL, // MOVIv8i16 |
| 7085 | 6444569066ULL, // MOVKWi |
| 7086 | 6444569066ULL, // MOVKXi |
| 7087 | 3008358275274ULL, // MOVNWi |
| 7088 | 3008358275274ULL, // MOVNXi |
| 7089 | 34630313332ULL, // MOVPRFX_ZPmZ_B |
| 7090 | 8830723351924ULL, // MOVPRFX_ZPmZ_D |
| 7091 | 17661446661492ULL, // MOVPRFX_ZPmZ_H |
| 7092 | 26422909429108ULL, // MOVPRFX_ZPmZ_S |
| 7093 | 35288258749812ULL, // MOVPRFX_ZPzZ_B |
| 7094 | 44084351788404ULL, // MOVPRFX_ZPzZ_D |
| 7095 | 17730705106292ULL, // MOVPRFX_ZPzZ_H |
| 7096 | 52880444843380ULL, // MOVPRFX_ZPzZ_S |
| 7097 | 808428916ULL, // MOVPRFX_ZZ |
| 7098 | 19488858696ULL, // MOVT_TIX |
| 7099 | 19757294152ULL, // MOVT_TIZ |
| 7100 | 3023659098696ULL, // MOVT_XTI |
| 7101 | 3008358278682ULL, // MOVZWi |
| 7102 | 3008358278682ULL, // MOVZXi |
| 7103 | 1056465ULL, // MRRS |
| 7104 | 19866345152ULL, // MRS |
| 7105 | 6053963834259966443ULL, // MSB_ZPmZZ_B |
| 7106 | 2595208116532464107ULL, // MSB_ZPmZZ_D |
| 7107 | 459499172649830891ULL, // MSB_ZPmZZ_H |
| 7108 | 2739340896794397163ULL, // MSB_ZPmZZ_S |
| 7109 | 4891630822ULL, // MSR |
| 7110 | 164650198ULL, // MSRR |
| 7111 | 1088742ULL, // MSRpstateImm1 |
| 7112 | 1088742ULL, // MSRpstateImm4 |
| 7113 | 1105126ULL, // MSRpstatesvcrImm1 |
| 7114 | 1187884876980682ULL, // MSUBPT |
| 7115 | 1187884876974714ULL, // MSUBWrrr |
| 7116 | 1187884876974714ULL, // MSUBXrrr |
| 7117 | 61988459812544ULL, // MUL_ZI_B |
| 7118 | 61987654522560ULL, // MUL_ZI_D |
| 7119 | 18591061710528ULL, // MUL_ZI_H |
| 7120 | 61988728297152ULL, // MUL_ZI_S |
| 7121 | 145276307521967808ULL, // MUL_ZPmZ_B |
| 7122 | 289400291690862272ULL, // MUL_ZPmZ_D |
| 7123 | 439233043046143680ULL, // MUL_ZPmZ_H |
| 7124 | 577639463935628992ULL, // MUL_ZPmZ_S |
| 7125 | 50709891276396224ULL, // MUL_ZZZI_D |
| 7126 | 334391417050816ULL, // MUL_ZZZI_H |
| 7127 | 50718688443193024ULL, // MUL_ZZZI_S |
| 7128 | 35600180745920ULL, // MUL_ZZZ_B |
| 7129 | 44395468478144ULL, // MUL_ZZZ_D |
| 7130 | 17732068251328ULL, // MUL_ZZZ_H |
| 7131 | 53192635274944ULL, // MUL_ZZZ_S |
| 7132 | 7996302742886080ULL, // MULv16i8 |
| 7133 | 9122237011564224ULL, // MULv2i32 |
| 7134 | 3212307471978829504ULL, // MULv2i32_indexed |
| 7135 | 10248171282339520ULL, // MULv4i16 |
| 7136 | 3196544907646965440ULL, // MULv4i16_indexed |
| 7137 | 3492634404427456ULL, // MULv4i32 |
| 7138 | 3212307368905905856ULL, // MULv4i32_indexed |
| 7139 | 4618568673105600ULL, // MULv8i16 |
| 7140 | 3196544804571944640ULL, // MULv8i16_indexed |
| 7141 | 11374105555211968ULL, // MULv8i8 |
| 7142 | 3008366743998ULL, // MVNIv2i32 |
| 7143 | 3008366743998ULL, // MVNIv2s_msl |
| 7144 | 3008370938302ULL, // MVNIv4i16 |
| 7145 | 3008373035454ULL, // MVNIv4i32 |
| 7146 | 3008373035454ULL, // MVNIv4s_msl |
| 7147 | 3008375132606ULL, // MVNIv8i16 |
| 7148 | 145276376241446396ULL, // NANDS_PPzPP |
| 7149 | 145276376241441921ULL, // NAND_PPzPP |
| 7150 | 289400671527032399ULL, // NBSL_ZZZZ |
| 7151 | 34630307309ULL, // NEG_ZPmZ_B |
| 7152 | 8830723345901ULL, // NEG_ZPmZ_D |
| 7153 | 17661446655469ULL, // NEG_ZPmZ_H |
| 7154 | 26422909423085ULL, // NEG_ZPmZ_S |
| 7155 | 35288258743789ULL, // NEG_ZPzZ_B |
| 7156 | 44084351782381ULL, // NEG_ZPzZ_D |
| 7157 | 17730705100269ULL, // NEG_ZPzZ_H |
| 7158 | 52880444837357ULL, // NEG_ZPzZ_S |
| 7159 | 173149359597ULL, // NEGv16i8 |
| 7160 | 2117101ULL, // NEGv1i64 |
| 7161 | 207511195117ULL, // NEGv2i32 |
| 7162 | 241873030637ULL, // NEGv2i64 |
| 7163 | 276234866157ULL, // NEGv4i16 |
| 7164 | 310596701677ULL, // NEGv4i32 |
| 7165 | 344958537197ULL, // NEGv8i16 |
| 7166 | 379320372717ULL, // NEGv8i8 |
| 7167 | 145276376241442594ULL, // NMATCH_PPzZZ_B |
| 7168 | 439233043583012642ULL, // NMATCH_PPzZZ_H |
| 7169 | 9960ULL, // NOP |
| 7170 | 145276376241446603ULL, // NORS_PPzPP |
| 7171 | 145276376241446068ULL, // NOR_PPzPP |
| 7172 | 34630312382ULL, // NOT_ZPmZ_B |
| 7173 | 8830723350974ULL, // NOT_ZPmZ_D |
| 7174 | 17661446660542ULL, // NOT_ZPmZ_H |
| 7175 | 26422909428158ULL, // NOT_ZPmZ_S |
| 7176 | 35288258748862ULL, // NOT_ZPzZ_B |
| 7177 | 44084351787454ULL, // NOT_ZPzZ_D |
| 7178 | 17730705105342ULL, // NOT_ZPzZ_H |
| 7179 | 52880444842430ULL, // NOT_ZPzZ_S |
| 7180 | 173149364670ULL, // NOTv16i8 |
| 7181 | 379320377790ULL, // NOTv8i8 |
| 7182 | 145276376241446516ULL, // ORNS_PPzPP |
| 7183 | 149945900357729ULL, // ORNWrs |
| 7184 | 149945900357729ULL, // ORNXrs |
| 7185 | 145276376241444961ULL, // ORN_PPzPP |
| 7186 | 7996302742886497ULL, // ORNv16i8 |
| 7187 | 11374105555212385ULL, // ORNv8i8 |
| 7188 | 35597502751639ULL, // ORQV_VPZ_B |
| 7189 | 44393599968151ULL, // ORQV_VPZ_D |
| 7190 | 97170164392855ULL, // ORQV_VPZ_H |
| 7191 | 53189697184663ULL, // ORQV_VPZ_S |
| 7192 | 145276376241446615ULL, // ORRS_PPzPP |
| 7193 | 343459946847429ULL, // ORRWri |
| 7194 | 149945900358853ULL, // ORRWrs |
| 7195 | 352256039869637ULL, // ORRXri |
| 7196 | 149945900358853ULL, // ORRXrs |
| 7197 | 145276376241446085ULL, // ORR_PPzPP |
| 7198 | 352258724256965ULL, // ORR_ZI |
| 7199 | 145276307521969349ULL, // ORR_ZPmZ_B |
| 7200 | 289400291690863813ULL, // ORR_ZPmZ_D |
| 7201 | 439233043046145221ULL, // ORR_ZPmZ_H |
| 7202 | 577639463935630533ULL, // ORR_ZPmZ_S |
| 7203 | 44395468479685ULL, // ORR_ZZZ |
| 7204 | 7996302742887621ULL, // ORRv16i8 |
| 7205 | 6453075141ULL, // ORRv2i32 |
| 7206 | 6457269445ULL, // ORRv4i16 |
| 7207 | 6459366597ULL, // ORRv4i32 |
| 7208 | 6461463749ULL, // ORRv8i16 |
| 7209 | 11374105555213509ULL, // ORRv8i8 |
| 7210 | 254902ULL, // ORV_VPZ_B |
| 7211 | 4874052534ULL, // ORV_VPZ_D |
| 7212 | 4876166070ULL, // ORV_VPZ_H |
| 7213 | 4857308086ULL, // ORV_VPZ_S |
| 7214 | 5102682906ULL, // PACDA |
| 7215 | 5102683837ULL, // PACDB |
| 7216 | 312692ULL, // PACDZA |
| 7217 | 314062ULL, // PACDZB |
| 7218 | 61984970130252ULL, // PACGA |
| 7219 | 5102682970ULL, // PACIA |
| 7220 | 10114ULL, // PACIA1716 |
| 7221 | 10031ULL, // PACIA171615 |
| 7222 | 10079ULL, // PACIASP |
| 7223 | 11576ULL, // PACIASPPC |
| 7224 | 10022ULL, // PACIAZ |
| 7225 | 5102683882ULL, // PACIB |
| 7226 | 9968ULL, // PACIB1716 |
| 7227 | 10055ULL, // PACIB171615 |
| 7228 | 10105ULL, // PACIBSP |
| 7229 | 11598ULL, // PACIBSPPC |
| 7230 | 10088ULL, // PACIBZ |
| 7231 | 312708ULL, // PACIZA |
| 7232 | 314078ULL, // PACIZB |
| 7233 | 10140ULL, // PACM |
| 7234 | 11564ULL, // PACNBIASPPC |
| 7235 | 11586ULL, // PACNBIBSPPC |
| 7236 | 9223430779ULL, // PEXT_2PCI_B |
| 7237 | 9223447163ULL, // PEXT_2PCI_D |
| 7238 | 9223463547ULL, // PEXT_2PCI_H |
| 7239 | 9223479931ULL, // PEXT_2PCI_S |
| 7240 | 1665107272315ULL, // PEXT_PCI_B |
| 7241 | 1665107288699ULL, // PEXT_PCI_D |
| 7242 | 9223348859ULL, // PEXT_PCI_H |
| 7243 | 1665107321467ULL, // PEXT_PCI_S |
| 7244 | 36222ULL, // PFALSE |
| 7245 | 35597496394242ULL, // PFIRST_B |
| 7246 | 2029682922039ULL, // PMLAL_2ZZZ_Q |
| 7247 | 1650074886985ULL, // PMOV_PZI_B |
| 7248 | 1650074903369ULL, // PMOV_PZI_D |
| 7249 | 9133171529ULL, // PMOV_PZI_H |
| 7250 | 1650074936137ULL, // PMOV_PZI_S |
| 7251 | 13051601737ULL, // PMOV_ZIP_B |
| 7252 | 13320037193ULL, // PMOV_ZIP_D |
| 7253 | 6340715337ULL, // PMOV_ZIP_H |
| 7254 | 13588472649ULL, // PMOV_ZIP_S |
| 7255 | 53192635238390ULL, // PMULLB_ZZZ_D |
| 7256 | 792738203638ULL, // PMULLB_ZZZ_H |
| 7257 | 168249334ULL, // PMULLB_ZZZ_Q |
| 7258 | 53192635244679ULL, // PMULLT_ZZZ_D |
| 7259 | 792738209927ULL, // PMULLT_ZZZ_H |
| 7260 | 168255623ULL, // PMULLT_ZZZ_Q |
| 7261 | 168269023ULL, // PMULL_2ZZZ_Q |
| 7262 | 7996302753366356ULL, // PMULLv16i8 |
| 7263 | 20302632159ULL, // PMULLv1i64 |
| 7264 | 20571062612ULL, // PMULLv2i64 |
| 7265 | 11374105553114335ULL, // PMULLv8i8 |
| 7266 | 35600180745932ULL, // PMUL_ZZZ_B |
| 7267 | 7996302742886092ULL, // PMULv16i8 |
| 7268 | 11374105555211980ULL, // PMULv8i8 |
| 7269 | 35597496394356ULL, // PNEXT_B |
| 7270 | 44393589432948ULL, // PNEXT_D |
| 7271 | 17732047282804ULL, // PNEXT_H |
| 7272 | 53189682487924ULL, // PNEXT_S |
| 7273 | 784435285919453ULL, // PRFB_D_PZI |
| 7274 | 3060521830109ULL, // PRFB_D_SCALED |
| 7275 | 3094881568477ULL, // PRFB_D_SXTW_SCALED |
| 7276 | 3129241306845ULL, // PRFB_D_UXTW_SCALED |
| 7277 | 793231425079005ULL, // PRFB_PRI |
| 7278 | 3163601045213ULL, // PRFB_PRR |
| 7279 | 784435269142237ULL, // PRFB_S_PZI |
| 7280 | 3197960783581ULL, // PRFB_S_SXTW_SCALED |
| 7281 | 3232320521949ULL, // PRFB_S_UXTW_SCALED |
| 7282 | 3266634124411ULL, // PRFD_D_PZI |
| 7283 | 3301040000123ULL, // PRFD_D_SCALED |
| 7284 | 3335399738491ULL, // PRFD_D_SXTW_SCALED |
| 7285 | 3369759476859ULL, // PRFD_D_UXTW_SCALED |
| 7286 | 793231425080443ULL, // PRFD_PRI |
| 7287 | 3404119215227ULL, // PRFD_PRR |
| 7288 | 3266617347195ULL, // PRFD_S_PZI |
| 7289 | 3438478953595ULL, // PRFD_S_SXTW_SCALED |
| 7290 | 3472838691963ULL, // PRFD_S_UXTW_SCALED |
| 7291 | 3507152293682ULL, // PRFH_D_PZI |
| 7292 | 3541558169394ULL, // PRFH_D_SCALED |
| 7293 | 3575917907762ULL, // PRFH_D_SXTW_SCALED |
| 7294 | 3610277646130ULL, // PRFH_D_UXTW_SCALED |
| 7295 | 793231425081138ULL, // PRFH_PRI |
| 7296 | 3644637384498ULL, // PRFH_PRR |
| 7297 | 3507135516466ULL, // PRFH_S_PZI |
| 7298 | 3678997122866ULL, // PRFH_S_SXTW_SCALED |
| 7299 | 3713356861234ULL, // PRFH_S_UXTW_SCALED |
| 7300 | 6714120002ULL, // PRFMl |
| 7301 | 4901104279494940482ULL, // PRFMroW |
| 7302 | 5045219467570796354ULL, // PRFMroX |
| 7303 | 677711520552770ULL, // PRFMui |
| 7304 | 29335382586906576ULL, // PRFUMi |
| 7305 | 3747670467693ULL, // PRFW_D_PZI |
| 7306 | 3782076343405ULL, // PRFW_D_SCALED |
| 7307 | 3816436081773ULL, // PRFW_D_SXTW_SCALED |
| 7308 | 3850795820141ULL, // PRFW_D_UXTW_SCALED |
| 7309 | 793231425086573ULL, // PRFW_PRI |
| 7310 | 3885155558509ULL, // PRFW_PRR |
| 7311 | 3747653690477ULL, // PRFW_S_PZI |
| 7312 | 3919515296877ULL, // PRFW_S_SXTW_SCALED |
| 7313 | 3953875035245ULL, // PRFW_S_UXTW_SCALED |
| 7314 | 96862989485839448ULL, // PSEL_PPPRI_B |
| 7315 | 96871785578861656ULL, // PSEL_PPPRI_D |
| 7316 | 96924562136994904ULL, // PSEL_PPPRI_H |
| 7317 | 96880581671883864ULL, // PSEL_PPPRI_S |
| 7318 | 3492782587ULL, // PTEST_PP |
| 7319 | 7249894915ULL, // PTRUES_B |
| 7320 | 7249911299ULL, // PTRUES_D |
| 7321 | 172039683ULL, // PTRUES_H |
| 7322 | 7249944067ULL, // PTRUES_S |
| 7323 | 7249890719ULL, // PTRUE_B |
| 7324 | 1150367ULL, // PTRUE_C_B |
| 7325 | 1166751ULL, // PTRUE_C_D |
| 7326 | 1183135ULL, // PTRUE_C_H |
| 7327 | 1199519ULL, // PTRUE_C_S |
| 7328 | 7249907103ULL, // PTRUE_D |
| 7329 | 172035487ULL, // PTRUE_H |
| 7330 | 7249939871ULL, // PTRUE_S |
| 7331 | 4880142724ULL, // PUNPKHI_PP |
| 7332 | 4880144615ULL, // PUNPKLO_PP |
| 7333 | 97171489720464ULL, // RADDHNB_ZZZ_B |
| 7334 | 18075661437072ULL, // RADDHNB_ZZZ_H |
| 7335 | 44395468507280ULL, // RADDHNB_ZZZ_S |
| 7336 | 105968388055317ULL, // RADDHNT_ZZZ_B |
| 7337 | 517837234453ULL, // RADDHNT_ZZZ_H |
| 7338 | 9210022682901ULL, // RADDHNT_ZZZ_S |
| 7339 | 2366700131555309ULL, // RADDHNv2i64_v2i32 |
| 7340 | 2375498109944243ULL, // RADDHNv2i64_v4i32 |
| 7341 | 3492634402330605ULL, // RADDHNv4i32_v4i16 |
| 7342 | 3501432378622387ULL, // RADDHNv4i32_v8i16 |
| 7343 | 4627366634717619ULL, // RADDHNv8i16_v16i8 |
| 7344 | 4618568675203053ULL, // RADDHNv8i16_v8i8 |
| 7345 | 2366700133646507ULL, // RAX1 |
| 7346 | 44395468472491ULL, // RAX1_ZZZ_D |
| 7347 | 2121650ULL, // RBITWr |
| 7348 | 2121650ULL, // RBITXr |
| 7349 | 34630311858ULL, // RBIT_ZPmZ_B |
| 7350 | 8830723350450ULL, // RBIT_ZPmZ_D |
| 7351 | 17661446660018ULL, // RBIT_ZPmZ_H |
| 7352 | 26422909427634ULL, // RBIT_ZPmZ_S |
| 7353 | 35288258748338ULL, // RBIT_ZPzZ_B |
| 7354 | 44084351786930ULL, // RBIT_ZPzZ_D |
| 7355 | 17730705104818ULL, // RBIT_ZPzZ_H |
| 7356 | 52880444841906ULL, // RBIT_ZPzZ_S |
| 7357 | 173149364146ULL, // RBITv16i8 |
| 7358 | 379320377266ULL, // RBITv8i8 |
| 7359 | 29661599004679587ULL, // RCWCAS |
| 7360 | 29661599004673278ULL, // RCWCASA |
| 7361 | 29661599004676968ULL, // RCWCASAL |
| 7362 | 29661599004677702ULL, // RCWCASL |
| 7363 | 399967ULL, // RCWCASP |
| 7364 | 394348ULL, // RCWCASPA |
| 7365 | 398059ULL, // RCWCASPAL |
| 7366 | 398797ULL, // RCWCASPL |
| 7367 | 16108543072ULL, // RCWCLR |
| 7368 | 16108537033ULL, // RCWCLRA |
| 7369 | 16108540746ULL, // RCWCLRAL |
| 7370 | 16108541483ULL, // RCWCLRL |
| 7371 | 634502232627788ULL, // RCWCLRP |
| 7372 | 634502232622167ULL, // RCWCLRPA |
| 7373 | 634502232625876ULL, // RCWCLRPAL |
| 7374 | 634502232626616ULL, // RCWCLRPL |
| 7375 | 16108543055ULL, // RCWCLRS |
| 7376 | 16108537014ULL, // RCWCLRSA |
| 7377 | 16108540725ULL, // RCWCLRSAL |
| 7378 | 16108541464ULL, // RCWCLRSL |
| 7379 | 634502232627778ULL, // RCWCLRSP |
| 7380 | 634502232622156ULL, // RCWCLRSPA |
| 7381 | 634502232625864ULL, // RCWCLRSPAL |
| 7382 | 634502232626605ULL, // RCWCLRSPL |
| 7383 | 29661599004679578ULL, // RCWSCAS |
| 7384 | 29661599004673268ULL, // RCWSCASA |
| 7385 | 29661599004676957ULL, // RCWSCASAL |
| 7386 | 29661599004677692ULL, // RCWSCASL |
| 7387 | 399957ULL, // RCWSCASP |
| 7388 | 394337ULL, // RCWSCASPA |
| 7389 | 398047ULL, // RCWSCASPAL |
| 7390 | 398786ULL, // RCWSCASPL |
| 7391 | 16108543856ULL, // RCWSET |
| 7392 | 16108537122ULL, // RCWSETA |
| 7393 | 16108540816ULL, // RCWSETAL |
| 7394 | 16108541589ULL, // RCWSETL |
| 7395 | 634502232627846ULL, // RCWSETP |
| 7396 | 634502232622218ULL, // RCWSETPA |
| 7397 | 634502232625932ULL, // RCWSETPAL |
| 7398 | 634502232626675ULL, // RCWSETPL |
| 7399 | 16108543839ULL, // RCWSETS |
| 7400 | 16108537103ULL, // RCWSETSA |
| 7401 | 16108540795ULL, // RCWSETSAL |
| 7402 | 16108541570ULL, // RCWSETSL |
| 7403 | 634502232627836ULL, // RCWSETSP |
| 7404 | 634502232622207ULL, // RCWSETSPA |
| 7405 | 634502232625920ULL, // RCWSETSPAL |
| 7406 | 634502232626664ULL, // RCWSETSPL |
| 7407 | 16108542657ULL, // RCWSWP |
| 7408 | 16108536990ULL, // RCWSWPA |
| 7409 | 16108540706ULL, // RCWSWPAL |
| 7410 | 16108541447ULL, // RCWSWPL |
| 7411 | 634502232627742ULL, // RCWSWPP |
| 7412 | 634502232622137ULL, // RCWSWPPA |
| 7413 | 634502232625843ULL, // RCWSWPPAL |
| 7414 | 634502232626586ULL, // RCWSWPPL |
| 7415 | 16108542648ULL, // RCWSWPS |
| 7416 | 16108536980ULL, // RCWSWPSA |
| 7417 | 16108540695ULL, // RCWSWPSAL |
| 7418 | 16108541437ULL, // RCWSWPSL |
| 7419 | 634502232627732ULL, // RCWSWPSP |
| 7420 | 634502232622126ULL, // RCWSWPSPA |
| 7421 | 634502232625831ULL, // RCWSWPSPAL |
| 7422 | 634502232626575ULL, // RCWSWPSPL |
| 7423 | 3986537094840ULL, // RDFFRS_PPz |
| 7424 | 39947ULL, // RDFFR_P |
| 7425 | 3986537094155ULL, // RDFFR_PPz |
| 7426 | 2119407ULL, // RDSVLI_XI |
| 7427 | 2119393ULL, // RDVLI_XI |
| 7428 | 24403ULL, // RET |
| 7429 | 11548ULL, // RETAA |
| 7430 | 330539ULL, // RETAASPPCi |
| 7431 | 23497ULL, // RETAASPPCr |
| 7432 | 11555ULL, // RETAB |
| 7433 | 330561ULL, // RETABSPPCi |
| 7434 | 23521ULL, // RETABSPPCr |
| 7435 | 2114232ULL, // REV16Wr |
| 7436 | 2114232ULL, // REV16Xr |
| 7437 | 173149356728ULL, // REV16v16i8 |
| 7438 | 379320369848ULL, // REV16v8i8 |
| 7439 | 2113713ULL, // REV32Xr |
| 7440 | 173149356209ULL, // REV32v16i8 |
| 7441 | 276234862769ULL, // REV32v4i16 |
| 7442 | 344958533809ULL, // REV32v8i16 |
| 7443 | 379320369329ULL, // REV32v8i8 |
| 7444 | 173149356696ULL, // REV64v16i8 |
| 7445 | 207511192216ULL, // REV64v2i32 |
| 7446 | 276234863256ULL, // REV64v4i16 |
| 7447 | 310596698776ULL, // REV64v4i32 |
| 7448 | 344958534296ULL, // REV64v8i16 |
| 7449 | 379320369816ULL, // REV64v8i8 |
| 7450 | 8830723345046ULL, // REVB_ZPmZ_D |
| 7451 | 17661446654614ULL, // REVB_ZPmZ_H |
| 7452 | 26422909422230ULL, // REVB_ZPmZ_S |
| 7453 | 44084351781526ULL, // REVB_ZPzZ_D |
| 7454 | 17730705099414ULL, // REVB_ZPzZ_H |
| 7455 | 52880444836502ULL, // REVB_ZPzZ_S |
| 7456 | 4020630932664ULL, // REVD_ZPmZ |
| 7457 | 18555339230392ULL, // REVD_ZPzZ |
| 7458 | 8830723346760ULL, // REVH_ZPmZ_D |
| 7459 | 26422909423944ULL, // REVH_ZPmZ_S |
| 7460 | 44084351783240ULL, // REVH_ZPzZ_D |
| 7461 | 52880444838216ULL, // REVH_ZPzZ_S |
| 7462 | 8830723351799ULL, // REVW_ZPmZ_D |
| 7463 | 44084351788279ULL, // REVW_ZPzZ_D |
| 7464 | 2122478ULL, // REVWr |
| 7465 | 2122478ULL, // REVXr |
| 7466 | 3491799790ULL, // REV_PP_B |
| 7467 | 2686509806ULL, // REV_PP_D |
| 7468 | 4859175662ULL, // REV_PP_H |
| 7469 | 3760284398ULL, // REV_PP_S |
| 7470 | 3491799790ULL, // REV_ZZ_B |
| 7471 | 2686509806ULL, // REV_ZZ_D |
| 7472 | 4859175662ULL, // REV_ZZ_H |
| 7473 | 3760284398ULL, // REV_ZZ_S |
| 7474 | 61984970132922ULL, // RMIF |
| 7475 | 61984970136761ULL, // RORVWr |
| 7476 | 61984970136761ULL, // RORVXr |
| 7477 | 1218369ULL, // RPRFM |
| 7478 | 61987117631679ULL, // RSHRNB_ZZI_B |
| 7479 | 18591057512639ULL, // RSHRNB_ZZI_H |
| 7480 | 61987654551743ULL, // RSHRNB_ZZI_S |
| 7481 | 387443364766008ULL, // RSHRNT_ZZI_B |
| 7482 | 19175175168312ULL, // RSHRNT_ZZI_H |
| 7483 | 387442022637880ULL, // RSHRNT_ZZI_S |
| 7484 | 387649798013392ULL, // RSHRNv16i8_shift |
| 7485 | 62123759736913ULL, // RSHRNv2i32_shift |
| 7486 | 62158123669585ULL, // RSHRNv4i16_shift |
| 7487 | 387581086925264ULL, // RSHRNv4i32_shift |
| 7488 | 387615448760784ULL, // RSHRNv8i16_shift |
| 7489 | 62192489699409ULL, // RSHRNv8i8_shift |
| 7490 | 97171489720455ULL, // RSUBHNB_ZZZ_B |
| 7491 | 18075661437063ULL, // RSUBHNB_ZZZ_H |
| 7492 | 44395468507271ULL, // RSUBHNB_ZZZ_S |
| 7493 | 105968388055308ULL, // RSUBHNT_ZZZ_B |
| 7494 | 517837234444ULL, // RSUBHNT_ZZZ_H |
| 7495 | 9210022682892ULL, // RSUBHNT_ZZZ_S |
| 7496 | 2366700131555301ULL, // RSUBHNv2i64_v2i32 |
| 7497 | 2375498109944234ULL, // RSUBHNv2i64_v4i32 |
| 7498 | 3492634402330597ULL, // RSUBHNv4i32_v4i16 |
| 7499 | 3501432378622378ULL, // RSUBHNv4i32_v8i16 |
| 7500 | 4627366634717610ULL, // RSUBHNv8i16_v16i8 |
| 7501 | 4618568675203045ULL, // RSUBHNv8i16_v8i8 |
| 7502 | 26802477123326ULL, // SABALB_ZZZ_D |
| 7503 | 18797264176894ULL, // SABALB_ZZZ_H |
| 7504 | 105968388097790ULL, // SABALB_ZZZ_S |
| 7505 | 26802477129669ULL, // SABALT_ZZZ_D |
| 7506 | 18797264183237ULL, // SABALT_ZZZ_H |
| 7507 | 105968388104133ULL, // SABALT_ZZZ_S |
| 7508 | 18797264179696ULL, // SABAL_ZZZ_BtoH |
| 7509 | 105968388100592ULL, // SABAL_ZZZ_HtoS |
| 7510 | 26802477126128ULL, // SABAL_ZZZ_StoD |
| 7511 | 8005100725469400ULL, // SABALv16i8_v8i16 |
| 7512 | 9131034985763312ULL, // SABALv2i32_v2i64 |
| 7513 | 10256969256538608ULL, // SABALv4i16_v4i32 |
| 7514 | 3501432372330712ULL, // SABALv4i32_v2i64 |
| 7515 | 4627366643106008ULL, // SABALv8i16_v4i32 |
| 7516 | 11382903525216752ULL, // SABALv8i8_v8i16 |
| 7517 | 18801758339854ULL, // SABA_ZZZ_B |
| 7518 | 9210022642446ULL, // SABA_ZZZ_D |
| 7519 | 17663365546766ULL, // SABA_ZZZ_H |
| 7520 | 26802477155086ULL, // SABA_ZZZ_S |
| 7521 | 8005100714984206ULL, // SABAv16i8 |
| 7522 | 9131034983662350ULL, // SABAv2i32 |
| 7523 | 10256969254437646ULL, // SABAv4i16 |
| 7524 | 3501432376525582ULL, // SABAv4i32 |
| 7525 | 4627366645203726ULL, // SABAv8i16 |
| 7526 | 11382903527310094ULL, // SABAv8i8 |
| 7527 | 53192635238323ULL, // SABDLB_ZZZ_D |
| 7528 | 792738203571ULL, // SABDLB_ZZZ_H |
| 7529 | 97171489769395ULL, // SABDLB_ZZZ_S |
| 7530 | 53192635244589ULL, // SABDLT_ZZZ_D |
| 7531 | 792738209837ULL, // SABDLT_ZZZ_H |
| 7532 | 97171489775661ULL, // SABDLT_ZZZ_S |
| 7533 | 7996302753366298ULL, // SABDLv16i8_v8i16 |
| 7534 | 9122237013660654ULL, // SABDLv2i32_v2i64 |
| 7535 | 10248171284435950ULL, // SABDLv4i16_v4i32 |
| 7536 | 3492634400227610ULL, // SABDLv4i32_v2i64 |
| 7537 | 4618568671002906ULL, // SABDLv8i16_v4i32 |
| 7538 | 11374105553114094ULL, // SABDLv8i8_v8i16 |
| 7539 | 145276307521965003ULL, // SABD_ZPmZ_B |
| 7540 | 289400291690859467ULL, // SABD_ZPmZ_D |
| 7541 | 439233043046140875ULL, // SABD_ZPmZ_H |
| 7542 | 577639463935626187ULL, // SABD_ZPmZ_S |
| 7543 | 7996302742883275ULL, // SABDv16i8 |
| 7544 | 9122237011561419ULL, // SABDv2i32 |
| 7545 | 10248171282336715ULL, // SABDv4i16 |
| 7546 | 3492634404424651ULL, // SABDv4i32 |
| 7547 | 4618568673102795ULL, // SABDv8i16 |
| 7548 | 11374105555209163ULL, // SABDv8i8 |
| 7549 | 26423446264177ULL, // SADALP_ZPmZ_D |
| 7550 | 18795320121713ULL, // SADALP_ZPmZ_H |
| 7551 | 105588283496817ULL, // SADALP_ZPmZ_S |
| 7552 | 175038929265ULL, // SADALPv16i8_v8i16 |
| 7553 | 209553856881ULL, // SADALPv2i32_v1i64 |
| 7554 | 278109755761ULL, // SADALPv4i16_v2i32 |
| 7555 | 312471591281ULL, // SADALPv4i32_v2i64 |
| 7556 | 346835523953ULL, // SADALPv8i16_v4i32 |
| 7557 | 381193165169ULL, // SADALPv8i8_v4i16 |
| 7558 | 53192635244319ULL, // SADDLBT_ZZZ_D |
| 7559 | 792738209567ULL, // SADDLBT_ZZZ_H |
| 7560 | 97171489775391ULL, // SADDLBT_ZZZ_S |
| 7561 | 53192635238348ULL, // SADDLB_ZZZ_D |
| 7562 | 792738203596ULL, // SADDLB_ZZZ_H |
| 7563 | 97171489769420ULL, // SADDLB_ZZZ_S |
| 7564 | 173159848321ULL, // SADDLPv16i8_v8i16 |
| 7565 | 207674775937ULL, // SADDLPv2i32_v1i64 |
| 7566 | 276230674817ULL, // SADDLPv4i16_v2i32 |
| 7567 | 310592510337ULL, // SADDLPv4i32_v2i64 |
| 7568 | 344956443009ULL, // SADDLPv8i16_v4i32 |
| 7569 | 379314084225ULL, // SADDLPv8i8_v4i16 |
| 7570 | 53192635244605ULL, // SADDLT_ZZZ_D |
| 7571 | 792738209853ULL, // SADDLT_ZZZ_H |
| 7572 | 97171489775677ULL, // SADDLT_ZZZ_S |
| 7573 | 173142991621ULL, // SADDLVv16i8v |
| 7574 | 276222206725ULL, // SADDLVv4i16v |
| 7575 | 310581945093ULL, // SADDLVv4i32v |
| 7576 | 344941683461ULL, // SADDLVv8i16v |
| 7577 | 379301421829ULL, // SADDLVv8i8v |
| 7578 | 7996302753366314ULL, // SADDLv16i8_v8i16 |
| 7579 | 9122237013660730ULL, // SADDLv2i32_v2i64 |
| 7580 | 10248171284436026ULL, // SADDLv4i16_v4i32 |
| 7581 | 3492634400227626ULL, // SADDLv4i32_v2i64 |
| 7582 | 4618568671002922ULL, // SADDLv8i16_v4i32 |
| 7583 | 11374105553114170ULL, // SADDLv8i8_v8i16 |
| 7584 | 4903412442ULL, // SADDV_VPZ_B |
| 7585 | 4876149466ULL, // SADDV_VPZ_H |
| 7586 | 4857275098ULL, // SADDV_VPZ_S |
| 7587 | 53191561497260ULL, // SADDWB_ZZZ_D |
| 7588 | 792717232812ULL, // SADDWB_ZZZ_H |
| 7589 | 97173100382892ULL, // SADDWB_ZZZ_S |
| 7590 | 53191561503326ULL, // SADDWT_ZZZ_D |
| 7591 | 792717238878ULL, // SADDWT_ZZZ_H |
| 7592 | 97173100388958ULL, // SADDWT_ZZZ_S |
| 7593 | 7996268393628262ULL, // SADDWv16i8_v8i16 |
| 7594 | 9122099574711391ULL, // SADDWv2i32_v2i64 |
| 7595 | 10248033845486687ULL, // SADDWv4i16_v4i32 |
| 7596 | 3492600040489574ULL, // SADDWv4i32_v2i64 |
| 7597 | 4618534311264870ULL, // SADDWv8i16_v4i32 |
| 7598 | 11373968114164831ULL, // SADDWv8i8_v8i16 |
| 7599 | 11561ULL, // SB |
| 7600 | 9210022643621ULL, // SBCLB_ZZZ_D |
| 7601 | 26802477156261ULL, // SBCLB_ZZZ_S |
| 7602 | 9210022649887ULL, // SBCLT_ZZZ_D |
| 7603 | 26802477162527ULL, // SBCLT_ZZZ_S |
| 7604 | 61984970137060ULL, // SBCSWr |
| 7605 | 61984970137060ULL, // SBCSXr |
| 7606 | 61984970132213ULL, // SBCWr |
| 7607 | 61984970132213ULL, // SBCXr |
| 7608 | 1187884876977973ULL, // SBFMWri |
| 7609 | 1187884876977973ULL, // SBFMXri |
| 7610 | 18797264263591ULL, // SCLAMP_VG2_2Z2Z_B |
| 7611 | 2029682596263ULL, // SCLAMP_VG2_2Z2Z_D |
| 7612 | 17663365667239ULL, // SCLAMP_VG2_2Z2Z_H |
| 7613 | 517837363623ULL, // SCLAMP_VG2_2Z2Z_S |
| 7614 | 18797264263591ULL, // SCLAMP_VG4_4Z4Z_B |
| 7615 | 2029682596263ULL, // SCLAMP_VG4_4Z4Z_D |
| 7616 | 17663365667239ULL, // SCLAMP_VG4_4Z4Z_H |
| 7617 | 517837363623ULL, // SCLAMP_VG4_4Z4Z_S |
| 7618 | 18801758345639ULL, // SCLAMP_ZZZ_B |
| 7619 | 9210022648231ULL, // SCLAMP_ZZZ_D |
| 7620 | 17663365552551ULL, // SCLAMP_ZZZ_H |
| 7621 | 26802477160871ULL, // SCLAMP_ZZZ_S |
| 7622 | 2117056ULL, // SCVTFDSr |
| 7623 | 2117056ULL, // SCVTFHDr |
| 7624 | 2117056ULL, // SCVTFHSr |
| 7625 | 4880146518ULL, // SCVTFLT_ZZ_BtoH |
| 7626 | 2149670998ULL, // SCVTFLT_ZZ_HtoS |
| 7627 | 3760250966ULL, // SCVTFLT_ZZ_StoD |
| 7628 | 2117056ULL, // SCVTFSDr |
| 7629 | 61984970132928ULL, // SCVTFSWDri |
| 7630 | 61984970132928ULL, // SCVTFSWHri |
| 7631 | 61984970132928ULL, // SCVTFSWSri |
| 7632 | 61984970132928ULL, // SCVTFSXDri |
| 7633 | 61984970132928ULL, // SCVTFSXHri |
| 7634 | 61984970132928ULL, // SCVTFSXSri |
| 7635 | 2117056ULL, // SCVTFUWDri |
| 7636 | 2117056ULL, // SCVTFUWHri |
| 7637 | 2117056ULL, // SCVTFUWSri |
| 7638 | 2117056ULL, // SCVTFUXDri |
| 7639 | 2117056ULL, // SCVTFUXHri |
| 7640 | 2117056ULL, // SCVTFUXSri |
| 7641 | 4867689920ULL, // SCVTF_2Z2Z_StoS |
| 7642 | 4867689920ULL, // SCVTF_4Z4Z_StoS |
| 7643 | 8830723345856ULL, // SCVTF_ZPmZ_DtoD |
| 7644 | 2027765697984ULL, // SCVTF_ZPmZ_DtoH |
| 7645 | 8830723378624ULL, // SCVTF_ZPmZ_DtoS |
| 7646 | 17661446655424ULL, // SCVTF_ZPmZ_HtoH |
| 7647 | 26422909390272ULL, // SCVTF_ZPmZ_StoD |
| 7648 | 515937209792ULL, // SCVTF_ZPmZ_StoH |
| 7649 | 26422909423040ULL, // SCVTF_ZPmZ_StoS |
| 7650 | 44084351782336ULL, // SCVTF_ZPzZ_DtoD |
| 7651 | 18417899867584ULL, // SCVTF_ZPzZ_DtoH |
| 7652 | 44084351815104ULL, // SCVTF_ZPzZ_DtoS |
| 7653 | 17730705100224ULL, // SCVTF_ZPzZ_HtoH |
| 7654 | 52880444804544ULL, // SCVTF_ZPzZ_StoD |
| 7655 | 18074302483904ULL, // SCVTF_ZPzZ_StoH |
| 7656 | 52880444837312ULL, // SCVTF_ZPzZ_StoS |
| 7657 | 4880141760ULL, // SCVTF_ZZ_BtoH |
| 7658 | 2149666240ULL, // SCVTF_ZZ_HtoS |
| 7659 | 3760246208ULL, // SCVTF_ZZ_StoD |
| 7660 | 61984970132928ULL, // SCVTFd |
| 7661 | 61984970132928ULL, // SCVTFh |
| 7662 | 61984970132928ULL, // SCVTFs |
| 7663 | 2117056ULL, // SCVTFv1i16 |
| 7664 | 2117056ULL, // SCVTFv1i32 |
| 7665 | 2117056ULL, // SCVTFv1i64 |
| 7666 | 207511195072ULL, // SCVTFv2f32 |
| 7667 | 241873030592ULL, // SCVTFv2f64 |
| 7668 | 62261198687680ULL, // SCVTFv2i32_shift |
| 7669 | 62123761831360ULL, // SCVTFv2i64_shift |
| 7670 | 276234866112ULL, // SCVTFv4f16 |
| 7671 | 310596701632ULL, // SCVTFv4f32 |
| 7672 | 62295562620352ULL, // SCVTFv4i16_shift |
| 7673 | 62158125764032ULL, // SCVTFv4i32_shift |
| 7674 | 344958537152ULL, // SCVTFv8f16 |
| 7675 | 62192487599552ULL, // SCVTFv8i16_shift |
| 7676 | 289400291690863920ULL, // SDIVR_ZPmZ_D |
| 7677 | 577639463935630640ULL, // SDIVR_ZPmZ_S |
| 7678 | 61984970138361ULL, // SDIVWr |
| 7679 | 61984970138361ULL, // SDIVXr |
| 7680 | 289400291690865401ULL, // SDIV_ZPmZ_D |
| 7681 | 577639463935632121ULL, // SDIV_ZPmZ_S |
| 7682 | 512479562277272ULL, // SDOT_VG2_M2Z2Z_BtoS |
| 7683 | 22650974388838808ULL, // SDOT_VG2_M2Z2Z_HtoD |
| 7684 | 22650974388855192ULL, // SDOT_VG2_M2Z2Z_HtoS |
| 7685 | 43305472115319192ULL, // SDOT_VG2_M2ZZI_BToS |
| 7686 | 888468002750833048ULL, // SDOT_VG2_M2ZZI_HToS |
| 7687 | 888468002750816664ULL, // SDOT_VG2_M2ZZI_HtoD |
| 7688 | 521275655299480ULL, // SDOT_VG2_M2ZZ_BtoS |
| 7689 | 456122438523249048ULL, // SDOT_VG2_M2ZZ_HtoD |
| 7690 | 456122438523265432ULL, // SDOT_VG2_M2ZZ_HtoS |
| 7691 | 512479830712728ULL, // SDOT_VG4_M4Z4Z_BtoS |
| 7692 | 22650974657274264ULL, // SDOT_VG4_M4Z4Z_HtoD |
| 7693 | 22650974657290648ULL, // SDOT_VG4_M4Z4Z_HtoS |
| 7694 | 43305472383754648ULL, // SDOT_VG4_M4ZZI_BToS |
| 7695 | 888468003019268504ULL, // SDOT_VG4_M4ZZI_HToS |
| 7696 | 888468003019252120ULL, // SDOT_VG4_M4ZZI_HtoD |
| 7697 | 521275923734936ULL, // SDOT_VG4_M4ZZ_BtoS |
| 7698 | 456122438791684504ULL, // SDOT_VG4_M4ZZ_HtoD |
| 7699 | 456122438791700888ULL, // SDOT_VG4_M4ZZ_HtoS |
| 7700 | 370640985072024ULL, // SDOT_ZZZI_BtoH |
| 7701 | 370645479285144ULL, // SDOT_ZZZI_BtoS |
| 7702 | 457221330566177176ULL, // SDOT_ZZZI_HtoD |
| 7703 | 457221330566209944ULL, // SDOT_ZZZI_HtoS |
| 7704 | 18797264183704ULL, // SDOT_ZZZ_BtoH |
| 7705 | 18801758396824ULL, // SDOT_ZZZ_BtoS |
| 7706 | 105968388071832ULL, // SDOT_ZZZ_HtoD |
| 7707 | 105968388104600ULL, // SDOT_ZZZ_HtoS |
| 7708 | 44033897742344600ULL, // SDOTlanev16i8 |
| 7709 | 44034000815268248ULL, // SDOTlanev8i8 |
| 7710 | 8005100723380632ULL, // SDOTv16i8 |
| 7711 | 11382903516832152ULL, // SDOTv8i8 |
| 7712 | 145276685479089235ULL, // SEL_PPPP |
| 7713 | 98089290252309587ULL, // SEL_VG2_2ZC2Z2Z_B |
| 7714 | 99213094215128147ULL, // SEL_VG2_2ZC2Z2Z_D |
| 7715 | 100338100768789587ULL, // SEL_VG2_2ZC2Z2Z_H |
| 7716 | 101464928388584531ULL, // SEL_VG2_2ZC2Z2Z_S |
| 7717 | 98089290252309587ULL, // SEL_VG4_4ZC4Z4Z_B |
| 7718 | 99213094215128147ULL, // SEL_VG4_4ZC4Z4Z_D |
| 7719 | 100338100768789587ULL, // SEL_VG4_4ZC4Z4Z_H |
| 7720 | 101464928388584531ULL, // SEL_VG4_4ZC4Z4Z_S |
| 7721 | 145276685479089235ULL, // SEL_ZPZZ_B |
| 7722 | 289400669647983699ULL, // SEL_ZPZZ_D |
| 7723 | 439233044925191251ULL, // SEL_ZPZZ_H |
| 7724 | 577639841892750419ULL, // SEL_ZPZZ_S |
| 7725 | 17059244080ULL, // SETE |
| 7726 | 17059244161ULL, // SETEN |
| 7727 | 17059245121ULL, // SETET |
| 7728 | 17059244554ULL, // SETETN |
| 7729 | 17072ULL, // SETF16 |
| 7730 | 17094ULL, // SETF8 |
| 7731 | 11636ULL, // SETFFR |
| 7732 | 17059244102ULL, // SETGM |
| 7733 | 17059244186ULL, // SETGMN |
| 7734 | 17059245146ULL, // SETGMT |
| 7735 | 17059244582ULL, // SETGMTN |
| 7736 | 20817340455ULL, // SETGOE |
| 7737 | 20817340535ULL, // SETGOEN |
| 7738 | 20817341495ULL, // SETGOET |
| 7739 | 20817340927ULL, // SETGOETN |
| 7740 | 20817340494ULL, // SETGOM |
| 7741 | 20817340579ULL, // SETGOMN |
| 7742 | 20817341539ULL, // SETGOMT |
| 7743 | 20817340976ULL, // SETGOMTN |
| 7744 | 20817341454ULL, // SETGOP |
| 7745 | 20817340623ULL, // SETGOPN |
| 7746 | 20817341583ULL, // SETGOPT |
| 7747 | 20817341025ULL, // SETGOPTN |
| 7748 | 17059245062ULL, // SETGP |
| 7749 | 17059244230ULL, // SETGPN |
| 7750 | 17059245190ULL, // SETGPT |
| 7751 | 17059244631ULL, // SETGPTN |
| 7752 | 17059244119ULL, // SETM |
| 7753 | 17059244205ULL, // SETMN |
| 7754 | 17059245165ULL, // SETMT |
| 7755 | 17059244603ULL, // SETMTN |
| 7756 | 17059245079ULL, // SETP |
| 7757 | 17059244249ULL, // SETPN |
| 7758 | 17059245209ULL, // SETPT |
| 7759 | 17059244652ULL, // SETPTN |
| 7760 | 3501262442384110ULL, // SHA1Crrr |
| 7761 | 2117145ULL, // SHA1Hrr |
| 7762 | 3501262442387246ULL, // SHA1Mrrr |
| 7763 | 3501262442387742ULL, // SHA1Prrr |
| 7764 | 3501432376524801ULL, // SHA1SU0rrr |
| 7765 | 312475779201ULL, // SHA1SU1rr |
| 7766 | 3501262442381511ULL, // SHA256H2rrr |
| 7767 | 3501262442385025ULL, // SHA256Hrrr |
| 7768 | 312475779093ULL, // SHA256SU0rr |
| 7769 | 3501432376524949ULL, // SHA256SU1rrr |
| 7770 | 2375362535542348ULL, // SHA512H |
| 7771 | 2375362535538877ULL, // SHA512H2 |
| 7772 | 243752108042ULL, // SHA512SU0 |
| 7773 | 2375498105749642ULL, // SHA512SU1 |
| 7774 | 145276307521965126ULL, // SHADD_ZPmZ_B |
| 7775 | 289400291690859590ULL, // SHADD_ZPmZ_D |
| 7776 | 439233043046140998ULL, // SHADD_ZPmZ_H |
| 7777 | 577639463935626310ULL, // SHADD_ZPmZ_S |
| 7778 | 7996302742883398ULL, // SHADDv16i8 |
| 7779 | 9122237011561542ULL, // SHADDv2i32 |
| 7780 | 10248171282336838ULL, // SHADDv4i16 |
| 7781 | 3492634404424774ULL, // SHADDv4i32 |
| 7782 | 4618568673102918ULL, // SHADDv8i16 |
| 7783 | 11374105555209286ULL, // SHADDv8i8 |
| 7784 | 4090170016059ULL, // SHLLv16i8 |
| 7785 | 4124523467961ULL, // SHLLv2i32 |
| 7786 | 4158887400633ULL, // SHLLv4i16 |
| 7787 | 4193242939707ULL, // SHLLv4i32 |
| 7788 | 4227606872379ULL, // SHLLv8i16 |
| 7789 | 4261968712889ULL, // SHLLv8i8 |
| 7790 | 61984970134632ULL, // SHLd |
| 7791 | 62226836853864ULL, // SHLv16i8_shift |
| 7792 | 62261198689384ULL, // SHLv2i32_shift |
| 7793 | 62123761833064ULL, // SHLv2i64_shift |
| 7794 | 62295562622056ULL, // SHLv4i16_shift |
| 7795 | 62158125765736ULL, // SHLv4i32_shift |
| 7796 | 62192487601256ULL, // SHLv8i16_shift |
| 7797 | 62329928651880ULL, // SHLv8i8_shift |
| 7798 | 61987117631661ULL, // SHRNB_ZZI_B |
| 7799 | 18591057512621ULL, // SHRNB_ZZI_H |
| 7800 | 61987654551725ULL, // SHRNB_ZZI_S |
| 7801 | 387443364765990ULL, // SHRNT_ZZI_B |
| 7802 | 19175175168294ULL, // SHRNT_ZZI_H |
| 7803 | 387442022637862ULL, // SHRNT_ZZI_S |
| 7804 | 387649798013374ULL, // SHRNv16i8_shift |
| 7805 | 62123759736897ULL, // SHRNv2i32_shift |
| 7806 | 62158123669569ULL, // SHRNv4i16_shift |
| 7807 | 387581086925246ULL, // SHRNv4i32_shift |
| 7808 | 387615448760766ULL, // SHRNv8i16_shift |
| 7809 | 62192489699393ULL, // SHRNv8i8_shift |
| 7810 | 145276307521969065ULL, // SHSUBR_ZPmZ_B |
| 7811 | 289400291690863529ULL, // SHSUBR_ZPmZ_D |
| 7812 | 439233043046144937ULL, // SHSUBR_ZPmZ_H |
| 7813 | 577639463935630249ULL, // SHSUBR_ZPmZ_S |
| 7814 | 145276307521964651ULL, // SHSUB_ZPmZ_B |
| 7815 | 289400291690859115ULL, // SHSUB_ZPmZ_D |
| 7816 | 439233043046140523ULL, // SHSUB_ZPmZ_H |
| 7817 | 577639463935625835ULL, // SHSUB_ZPmZ_S |
| 7818 | 7996302742882923ULL, // SHSUBv16i8 |
| 7819 | 9122237011561067ULL, // SHSUBv2i32 |
| 7820 | 10248171282336363ULL, // SHSUBv4i16 |
| 7821 | 3492634404424299ULL, // SHSUBv4i32 |
| 7822 | 4618568673102443ULL, // SHSUBv8i16 |
| 7823 | 11374105555208811ULL, // SHSUBv8i8 |
| 7824 | 19179715465652ULL, // SLI_ZZI_B |
| 7825 | 387442022601140ULL, // SLI_ZZI_D |
| 7826 | 19175194038708ULL, // SLI_ZZI_H |
| 7827 | 387442291069364ULL, // SLI_ZZI_S |
| 7828 | 387445512524212ULL, // SLId |
| 7829 | 387684157755828ULL, // SLIv16i8_shift |
| 7830 | 387718519591348ULL, // SLIv2i32_shift |
| 7831 | 387581082735028ULL, // SLIv2i64_shift |
| 7832 | 387752883524020ULL, // SLIv4i16_shift |
| 7833 | 387615446667700ULL, // SLIv4i32_shift |
| 7834 | 387649808503220ULL, // SLIv8i16_shift |
| 7835 | 387787249553844ULL, // SLIv8i8_shift |
| 7836 | 3501432376524960ULL, // SM3PARTW1 |
| 7837 | 3501432376525430ULL, // SM3PARTW2 |
| 7838 | 758971471895822444ULL, // SM3SS1 |
| 7839 | 1050588345740165837ULL, // SM3TT1A |
| 7840 | 1050588345740166592ULL, // SM3TT1B |
| 7841 | 1050588345740165846ULL, // SM3TT2A |
| 7842 | 1050588345740166621ULL, // SM3TT2B |
| 7843 | 312475782334ULL, // SM4E |
| 7844 | 53192635278747ULL, // SM4EKEY_ZZZ_S |
| 7845 | 3492634404431259ULL, // SM4ENCKEY |
| 7846 | 53192635272382ULL, // SM4E_ZZZ_S |
| 7847 | 1187884876977194ULL, // SMADDLrrr |
| 7848 | 145276307521968855ULL, // SMAXP_ZPmZ_B |
| 7849 | 289400291690863319ULL, // SMAXP_ZPmZ_D |
| 7850 | 439233043046144727ULL, // SMAXP_ZPmZ_H |
| 7851 | 577639463935630039ULL, // SMAXP_ZPmZ_S |
| 7852 | 7996302742887127ULL, // SMAXPv16i8 |
| 7853 | 9122237011565271ULL, // SMAXPv2i32 |
| 7854 | 10248171282340567ULL, // SMAXPv4i16 |
| 7855 | 3492634404428503ULL, // SMAXPv4i32 |
| 7856 | 4618568673106647ULL, // SMAXPv8i16 |
| 7857 | 11374105555213015ULL, // SMAXPv8i8 |
| 7858 | 35597502751653ULL, // SMAXQV_VPZ_B |
| 7859 | 44393599968165ULL, // SMAXQV_VPZ_D |
| 7860 | 97170164392869ULL, // SMAXQV_VPZ_H |
| 7861 | 53189697184677ULL, // SMAXQV_VPZ_S |
| 7862 | 254914ULL, // SMAXV_VPZ_B |
| 7863 | 4874052546ULL, // SMAXV_VPZ_D |
| 7864 | 4876166082ULL, // SMAXV_VPZ_H |
| 7865 | 4857308098ULL, // SMAXV_VPZ_S |
| 7866 | 173142991810ULL, // SMAXVv16i8v |
| 7867 | 276222206914ULL, // SMAXVv4i16v |
| 7868 | 310581945282ULL, // SMAXVv4i32v |
| 7869 | 344941683650ULL, // SMAXVv8i16v |
| 7870 | 379301422018ULL, // SMAXVv8i8v |
| 7871 | 61984970138954ULL, // SMAXWri |
| 7872 | 61984970138954ULL, // SMAXWrr |
| 7873 | 61984970138954ULL, // SMAXXri |
| 7874 | 61984970138954ULL, // SMAXXrr |
| 7875 | 21649080608074ULL, // SMAX_VG2_2Z2Z_B |
| 7876 | 19553138681162ULL, // SMAX_VG2_2Z2Z_D |
| 7877 | 18659787597130ULL, // SMAX_VG2_2Z2Z_H |
| 7878 | 19587502646602ULL, // SMAX_VG2_2Z2Z_S |
| 7879 | 792719418698ULL, // SMAX_VG2_2ZZ_B |
| 7880 | 18419267315018ULL, // SMAX_VG2_2ZZ_D |
| 7881 | 17732074661194ULL, // SMAX_VG2_2ZZ_H |
| 7882 | 18075674158410ULL, // SMAX_VG2_2ZZ_S |
| 7883 | 21649080608074ULL, // SMAX_VG4_4Z4Z_B |
| 7884 | 19553138681162ULL, // SMAX_VG4_4Z4Z_D |
| 7885 | 18659787597130ULL, // SMAX_VG4_4Z4Z_H |
| 7886 | 19587502646602ULL, // SMAX_VG4_4Z4Z_S |
| 7887 | 792719418698ULL, // SMAX_VG4_4ZZ_B |
| 7888 | 18419267315018ULL, // SMAX_VG4_4ZZ_D |
| 7889 | 17732074661194ULL, // SMAX_VG4_4ZZ_H |
| 7890 | 18075674158410ULL, // SMAX_VG4_4ZZ_S |
| 7891 | 61988459816266ULL, // SMAX_ZI_B |
| 7892 | 61987654526282ULL, // SMAX_ZI_D |
| 7893 | 18591061714250ULL, // SMAX_ZI_H |
| 7894 | 61988728300874ULL, // SMAX_ZI_S |
| 7895 | 145276307521971530ULL, // SMAX_ZPmZ_B |
| 7896 | 289400291690865994ULL, // SMAX_ZPmZ_D |
| 7897 | 439233043046147402ULL, // SMAX_ZPmZ_H |
| 7898 | 577639463935632714ULL, // SMAX_ZPmZ_S |
| 7899 | 7996302742889802ULL, // SMAXv16i8 |
| 7900 | 9122237011567946ULL, // SMAXv2i32 |
| 7901 | 10248171282343242ULL, // SMAXv4i16 |
| 7902 | 3492634404431178ULL, // SMAXv4i32 |
| 7903 | 4618568673109322ULL, // SMAXv8i16 |
| 7904 | 11374105555215690ULL, // SMAXv8i8 |
| 7905 | 379679ULL, // SMC |
| 7906 | 145276307521968611ULL, // SMINP_ZPmZ_B |
| 7907 | 289400291690863075ULL, // SMINP_ZPmZ_D |
| 7908 | 439233043046144483ULL, // SMINP_ZPmZ_H |
| 7909 | 577639463935629795ULL, // SMINP_ZPmZ_S |
| 7910 | 7996302742886883ULL, // SMINPv16i8 |
| 7911 | 9122237011565027ULL, // SMINPv2i32 |
| 7912 | 10248171282340323ULL, // SMINPv4i16 |
| 7913 | 3492634404428259ULL, // SMINPv4i32 |
| 7914 | 4618568673106403ULL, // SMINPv8i16 |
| 7915 | 11374105555212771ULL, // SMINPv8i8 |
| 7916 | 35597502751622ULL, // SMINQV_VPZ_B |
| 7917 | 44393599968134ULL, // SMINQV_VPZ_D |
| 7918 | 97170164392838ULL, // SMINQV_VPZ_H |
| 7919 | 53189697184646ULL, // SMINQV_VPZ_S |
| 7920 | 254766ULL, // SMINV_VPZ_B |
| 7921 | 4874052398ULL, // SMINV_VPZ_D |
| 7922 | 4876165934ULL, // SMINV_VPZ_H |
| 7923 | 4857307950ULL, // SMINV_VPZ_S |
| 7924 | 173142991662ULL, // SMINVv16i8v |
| 7925 | 276222206766ULL, // SMINVv4i16v |
| 7926 | 310581945134ULL, // SMINVv4i32v |
| 7927 | 344941683502ULL, // SMINVv8i16v |
| 7928 | 379301421870ULL, // SMINVv8i8v |
| 7929 | 61984970135584ULL, // SMINWri |
| 7930 | 61984970135584ULL, // SMINWrr |
| 7931 | 61984970135584ULL, // SMINXri |
| 7932 | 61984970135584ULL, // SMINXrr |
| 7933 | 21649080604704ULL, // SMIN_VG2_2Z2Z_B |
| 7934 | 19553138677792ULL, // SMIN_VG2_2Z2Z_D |
| 7935 | 18659787593760ULL, // SMIN_VG2_2Z2Z_H |
| 7936 | 19587502643232ULL, // SMIN_VG2_2Z2Z_S |
| 7937 | 792719415328ULL, // SMIN_VG2_2ZZ_B |
| 7938 | 18419267311648ULL, // SMIN_VG2_2ZZ_D |
| 7939 | 17732074657824ULL, // SMIN_VG2_2ZZ_H |
| 7940 | 18075674155040ULL, // SMIN_VG2_2ZZ_S |
| 7941 | 21649080604704ULL, // SMIN_VG4_4Z4Z_B |
| 7942 | 19553138677792ULL, // SMIN_VG4_4Z4Z_D |
| 7943 | 18659787593760ULL, // SMIN_VG4_4Z4Z_H |
| 7944 | 19587502643232ULL, // SMIN_VG4_4Z4Z_S |
| 7945 | 792719415328ULL, // SMIN_VG4_4ZZ_B |
| 7946 | 18419267311648ULL, // SMIN_VG4_4ZZ_D |
| 7947 | 17732074657824ULL, // SMIN_VG4_4ZZ_H |
| 7948 | 18075674155040ULL, // SMIN_VG4_4ZZ_S |
| 7949 | 61988459812896ULL, // SMIN_ZI_B |
| 7950 | 61987654522912ULL, // SMIN_ZI_D |
| 7951 | 18591061710880ULL, // SMIN_ZI_H |
| 7952 | 61988728297504ULL, // SMIN_ZI_S |
| 7953 | 145276307521968160ULL, // SMIN_ZPmZ_B |
| 7954 | 289400291690862624ULL, // SMIN_ZPmZ_D |
| 7955 | 439233043046144032ULL, // SMIN_ZPmZ_H |
| 7956 | 577639463935629344ULL, // SMIN_ZPmZ_S |
| 7957 | 7996302742886432ULL, // SMINv16i8 |
| 7958 | 9122237011564576ULL, // SMINv2i32 |
| 7959 | 10248171282339872ULL, // SMINv4i16 |
| 7960 | 3492634404427808ULL, // SMINv4i32 |
| 7961 | 4618568673105952ULL, // SMINv8i16 |
| 7962 | 11374105555212320ULL, // SMINv8i8 |
| 7963 | 457142164655228715ULL, // SMLALB_ZZZI_D |
| 7964 | 457221330566203179ULL, // SMLALB_ZZZI_S |
| 7965 | 26802477123371ULL, // SMLALB_ZZZ_D |
| 7966 | 18797264176939ULL, // SMLALB_ZZZ_H |
| 7967 | 105968388097835ULL, // SMLALB_ZZZ_S |
| 7968 | 363016348734631ULL, // SMLALL_MZZI_BtoS |
| 7969 | 361745038398631ULL, // SMLALL_MZZI_HtoD |
| 7970 | 19968720868519ULL, // SMLALL_MZZ_BtoS |
| 7971 | 18697410532519ULL, // SMLALL_MZZ_HtoD |
| 7972 | 512479600022695ULL, // SMLALL_VG2_M2Z2Z_BtoS |
| 7973 | 22650974426584231ULL, // SMLALL_VG2_M2Z2Z_HtoD |
| 7974 | 43305472153064615ULL, // SMLALL_VG2_M2ZZI_BtoS |
| 7975 | 888468002788562087ULL, // SMLALL_VG2_M2ZZI_HtoD |
| 7976 | 521283209237671ULL, // SMLALL_VG2_M2ZZ_BtoS |
| 7977 | 456122446077187239ULL, // SMLALL_VG2_M2ZZ_HtoD |
| 7978 | 512479868458151ULL, // SMLALL_VG4_M4Z4Z_BtoS |
| 7979 | 22650974695019687ULL, // SMLALL_VG4_M4Z4Z_HtoD |
| 7980 | 43305472421500071ULL, // SMLALL_VG4_M4ZZI_BtoS |
| 7981 | 888468003056997543ULL, // SMLALL_VG4_M4ZZI_HtoD |
| 7982 | 521283477673127ULL, // SMLALL_VG4_M4ZZ_BtoS |
| 7983 | 456122446345622695ULL, // SMLALL_VG4_M4ZZ_HtoD |
| 7984 | 457142164655235048ULL, // SMLALT_ZZZI_D |
| 7985 | 457221330566209512ULL, // SMLALT_ZZZI_S |
| 7986 | 26802477129704ULL, // SMLALT_ZZZ_D |
| 7987 | 18797264183272ULL, // SMLALT_ZZZ_H |
| 7988 | 105968388104168ULL, // SMLALT_ZZZ_S |
| 7989 | 361745013248574ULL, // SMLAL_MZZI_HtoS |
| 7990 | 18697385382462ULL, // SMLAL_MZZ_HtoS |
| 7991 | 22650974401434174ULL, // SMLAL_VG2_M2Z2Z_HtoS |
| 7992 | 888468002763412030ULL, // SMLAL_VG2_M2ZZI_S |
| 7993 | 456122438535844414ULL, // SMLAL_VG2_M2ZZ_HtoS |
| 7994 | 22650974669869630ULL, // SMLAL_VG4_M4Z4Z_HtoS |
| 7995 | 888468003031847486ULL, // SMLAL_VG4_M4ZZI_HtoS |
| 7996 | 456122438804279870ULL, // SMLAL_VG4_M4ZZ_HtoS |
| 7997 | 8005100725469434ULL, // SMLALv16i8_v8i16 |
| 7998 | 1050588448815190590ULL, // SMLALv2i32_indexed |
| 7999 | 9131034985763390ULL, // SMLALv2i32_v2i64 |
| 8000 | 1034825884483326526ULL, // SMLALv4i16_indexed |
| 8001 | 10256969256538686ULL, // SMLALv4i16_v4i32 |
| 8002 | 1050588345735971066ULL, // SMLALv4i32_indexed |
| 8003 | 3501432372330746ULL, // SMLALv4i32_v2i64 |
| 8004 | 1034825781404107002ULL, // SMLALv8i16_indexed |
| 8005 | 4627366643106042ULL, // SMLALv8i16_v4i32 |
| 8006 | 11382903525216830ULL, // SMLALv8i8_v8i16 |
| 8007 | 457142164655229013ULL, // SMLSLB_ZZZI_D |
| 8008 | 457221330566203477ULL, // SMLSLB_ZZZI_S |
| 8009 | 26802477123669ULL, // SMLSLB_ZZZ_D |
| 8010 | 18797264177237ULL, // SMLSLB_ZZZ_H |
| 8011 | 105968388098133ULL, // SMLSLB_ZZZ_S |
| 8012 | 363016348734662ULL, // SMLSLL_MZZI_BtoS |
| 8013 | 361745038398662ULL, // SMLSLL_MZZI_HtoD |
| 8014 | 19968720868550ULL, // SMLSLL_MZZ_BtoS |
| 8015 | 18697410532550ULL, // SMLSLL_MZZ_HtoD |
| 8016 | 512479600022726ULL, // SMLSLL_VG2_M2Z2Z_BtoS |
| 8017 | 22650974426584262ULL, // SMLSLL_VG2_M2Z2Z_HtoD |
| 8018 | 43305472153064646ULL, // SMLSLL_VG2_M2ZZI_BtoS |
| 8019 | 888468002788562118ULL, // SMLSLL_VG2_M2ZZI_HtoD |
| 8020 | 521283209237702ULL, // SMLSLL_VG2_M2ZZ_BtoS |
| 8021 | 456122446077187270ULL, // SMLSLL_VG2_M2ZZ_HtoD |
| 8022 | 512479868458182ULL, // SMLSLL_VG4_M4Z4Z_BtoS |
| 8023 | 22650974695019718ULL, // SMLSLL_VG4_M4Z4Z_HtoD |
| 8024 | 43305472421500102ULL, // SMLSLL_VG4_M4ZZI_BtoS |
| 8025 | 888468003056997574ULL, // SMLSLL_VG4_M4ZZI_HtoD |
| 8026 | 521283477673158ULL, // SMLSLL_VG4_M4ZZ_BtoS |
| 8027 | 456122446345622726ULL, // SMLSLL_VG4_M4ZZ_HtoD |
| 8028 | 457142164655235279ULL, // SMLSLT_ZZZI_D |
| 8029 | 457221330566209743ULL, // SMLSLT_ZZZI_S |
| 8030 | 26802477129935ULL, // SMLSLT_ZZZ_D |
| 8031 | 18797264183503ULL, // SMLSLT_ZZZ_H |
| 8032 | 105968388104399ULL, // SMLSLT_ZZZ_S |
| 8033 | 361745013249638ULL, // SMLSL_MZZI_HtoS |
| 8034 | 18697385383526ULL, // SMLSL_MZZ_HtoS |
| 8035 | 22650974401435238ULL, // SMLSL_VG2_M2Z2Z_HtoS |
| 8036 | 888468002763413094ULL, // SMLSL_VG2_M2ZZI_S |
| 8037 | 456122438535845478ULL, // SMLSL_VG2_M2ZZ_HtoS |
| 8038 | 22650974669870694ULL, // SMLSL_VG4_M4Z4Z_HtoS |
| 8039 | 888468003031848550ULL, // SMLSL_VG4_M4ZZI_HtoS |
| 8040 | 456122438804280934ULL, // SMLSL_VG4_M4ZZ_HtoS |
| 8041 | 8005100725469566ULL, // SMLSLv16i8_v8i16 |
| 8042 | 1050588448815191654ULL, // SMLSLv2i32_indexed |
| 8043 | 9131034985764454ULL, // SMLSLv2i32_v2i64 |
| 8044 | 1034825884483327590ULL, // SMLSLv4i16_indexed |
| 8045 | 10256969256539750ULL, // SMLSLv4i16_v4i32 |
| 8046 | 1050588345735971198ULL, // SMLSLv4i32_indexed |
| 8047 | 3501432372330878ULL, // SMLSLv4i32_v2i64 |
| 8048 | 1034825781404107134ULL, // SMLSLv8i16_indexed |
| 8049 | 4627366643106174ULL, // SMLSLv8i16_v4i32 |
| 8050 | 11382903525217894ULL, // SMLSLv8i8_v8i16 |
| 8051 | 8005100723372933ULL, // SMMLA |
| 8052 | 18801758389125ULL, // SMMLA_ZZZ |
| 8053 | 12157305577ULL, // SMOP4A_M2Z2Z_BToS |
| 8054 | 5958124265ULL, // SMOP4A_M2Z2Z_HToS |
| 8055 | 5958124265ULL, // SMOP4A_M2Z2Z_HtoD |
| 8056 | 12962611945ULL, // SMOP4A_M2ZZ_BToS |
| 8057 | 6226559721ULL, // SMOP4A_M2ZZ_HToS |
| 8058 | 6226559721ULL, // SMOP4A_M2ZZ_HtoD |
| 8059 | 2407669023465ULL, // SMOP4A_MZ2Z_BToS |
| 8060 | 1136331440873ULL, // SMOP4A_MZ2Z_HToS |
| 8061 | 1136331440873ULL, // SMOP4A_MZ2Z_HtoD |
| 8062 | 18797264225001ULL, // SMOP4A_MZZ_BToS |
| 8063 | 17663365595881ULL, // SMOP4A_MZZ_HToS |
| 8064 | 17663365595881ULL, // SMOP4A_MZZ_HtoD |
| 8065 | 12157312393ULL, // SMOP4S_M2Z2Z_BToS |
| 8066 | 5958131081ULL, // SMOP4S_M2Z2Z_HToS |
| 8067 | 5958131081ULL, // SMOP4S_M2Z2Z_HtoD |
| 8068 | 12962618761ULL, // SMOP4S_M2ZZ_BToS |
| 8069 | 6226566537ULL, // SMOP4S_M2ZZ_HToS |
| 8070 | 6226566537ULL, // SMOP4S_M2ZZ_HtoD |
| 8071 | 2407669030281ULL, // SMOP4S_MZ2Z_BToS |
| 8072 | 1136331447689ULL, // SMOP4S_MZ2Z_HToS |
| 8073 | 1136331447689ULL, // SMOP4S_MZ2Z_HtoD |
| 8074 | 18797264231817ULL, // SMOP4S_MZZ_BToS |
| 8075 | 17663365602697ULL, // SMOP4S_MZZ_HToS |
| 8076 | 17663365602697ULL, // SMOP4S_MZZ_HtoD |
| 8077 | 378679217734660ULL, // SMOPA_MPPZZ_D |
| 8078 | 378679217734660ULL, // SMOPA_MPPZZ_HtoS |
| 8079 | 545804985156612ULL, // SMOPA_MPPZZ_S |
| 8080 | 378679217741473ULL, // SMOPS_MPPZZ_D |
| 8081 | 378679217741473ULL, // SMOPS_MPPZZ_HtoS |
| 8082 | 545804985163425ULL, // SMOPS_MPPZZ_S |
| 8083 | 467877901656911ULL, // SMOVvi16to32 |
| 8084 | 467877901656911ULL, // SMOVvi16to32_idx0 |
| 8085 | 467877901656911ULL, // SMOVvi16to64 |
| 8086 | 467877901656911ULL, // SMOVvi16to64_idx0 |
| 8087 | 467912261395279ULL, // SMOVvi32to64 |
| 8088 | 467912261395279ULL, // SMOVvi32to64_idx0 |
| 8089 | 467980980872015ULL, // SMOVvi8to32 |
| 8090 | 467980980872015ULL, // SMOVvi8to32_idx0 |
| 8091 | 467980980872015ULL, // SMOVvi8to64 |
| 8092 | 467980980872015ULL, // SMOVvi8to64_idx0 |
| 8093 | 1187884876977104ULL, // SMSUBLrrr |
| 8094 | 145276307521966069ULL, // SMULH_ZPmZ_B |
| 8095 | 289400291690860533ULL, // SMULH_ZPmZ_D |
| 8096 | 439233043046141941ULL, // SMULH_ZPmZ_H |
| 8097 | 577639463935627253ULL, // SMULH_ZPmZ_S |
| 8098 | 35600180744181ULL, // SMULH_ZZZ_B |
| 8099 | 44395468476405ULL, // SMULH_ZZZ_D |
| 8100 | 17732068249589ULL, // SMULH_ZZZ_H |
| 8101 | 53192635273205ULL, // SMULH_ZZZ_S |
| 8102 | 61984970133493ULL, // SMULHrr |
| 8103 | 50718688443156478ULL, // SMULLB_ZZZI_D |
| 8104 | 50762667297687550ULL, // SMULLB_ZZZI_S |
| 8105 | 53192635238398ULL, // SMULLB_ZZZ_D |
| 8106 | 792738203646ULL, // SMULLB_ZZZ_H |
| 8107 | 97171489769470ULL, // SMULLB_ZZZ_S |
| 8108 | 50718688443162767ULL, // SMULLT_ZZZI_D |
| 8109 | 50762667297693839ULL, // SMULLT_ZZZI_S |
| 8110 | 53192635244687ULL, // SMULLT_ZZZ_D |
| 8111 | 792738209935ULL, // SMULLT_ZZZ_H |
| 8112 | 97171489775759ULL, // SMULLT_ZZZ_S |
| 8113 | 7996302753366364ULL, // SMULLv16i8_v8i16 |
| 8114 | 3212307471980926182ULL, // SMULLv2i32_indexed |
| 8115 | 9122237013660902ULL, // SMULLv2i32_v2i64 |
| 8116 | 3196544907649062118ULL, // SMULLv4i16_indexed |
| 8117 | 10248171284436198ULL, // SMULLv4i16_v4i32 |
| 8118 | 3212307368901706076ULL, // SMULLv4i32_indexed |
| 8119 | 3492634400227676ULL, // SMULLv4i32_v2i64 |
| 8120 | 3196544804569842012ULL, // SMULLv8i16_indexed |
| 8121 | 4618568671002972ULL, // SMULLv8i16_v4i32 |
| 8122 | 11374105553114342ULL, // SMULLv8i8_v8i16 |
| 8123 | 800857589320900ULL, // SPLICE_ZPZZ_B |
| 8124 | 809653682359492ULL, // SPLICE_ZPZZ_D |
| 8125 | 18659760213188ULL, // SPLICE_ZPZZ_H |
| 8126 | 818449775414468ULL, // SPLICE_ZPZZ_S |
| 8127 | 145276685479087300ULL, // SPLICE_ZPZ_B |
| 8128 | 289400669647981764ULL, // SPLICE_ZPZ_D |
| 8129 | 439233044925189316ULL, // SPLICE_ZPZ_H |
| 8130 | 577639841892748484ULL, // SPLICE_ZPZ_S |
| 8131 | 34630311368ULL, // SQABS_ZPmZ_B |
| 8132 | 8830723349960ULL, // SQABS_ZPmZ_D |
| 8133 | 17661446659528ULL, // SQABS_ZPmZ_H |
| 8134 | 26422909427144ULL, // SQABS_ZPmZ_S |
| 8135 | 35288258747848ULL, // SQABS_ZPzZ_B |
| 8136 | 44084351786440ULL, // SQABS_ZPzZ_D |
| 8137 | 17730705104328ULL, // SQABS_ZPzZ_H |
| 8138 | 52880444841416ULL, // SQABS_ZPzZ_S |
| 8139 | 173149363656ULL, // SQABSv16i8 |
| 8140 | 2121160ULL, // SQABSv1i16 |
| 8141 | 2121160ULL, // SQABSv1i32 |
| 8142 | 2121160ULL, // SQABSv1i64 |
| 8143 | 2121160ULL, // SQABSv1i8 |
| 8144 | 207511199176ULL, // SQABSv2i32 |
| 8145 | 241873034696ULL, // SQABSv2i64 |
| 8146 | 276234870216ULL, // SQABSv4i16 |
| 8147 | 310596705736ULL, // SQABSv4i32 |
| 8148 | 344958541256ULL, // SQABSv8i16 |
| 8149 | 379320376776ULL, // SQABSv8i8 |
| 8150 | 167541576076388ULL, // SQADD_ZI_B |
| 8151 | 176336863808612ULL, // SQADD_ZI_D |
| 8152 | 930156186724ULL, // SQADD_ZI_H |
| 8153 | 185134030605412ULL, // SQADD_ZI_S |
| 8154 | 145276307521965156ULL, // SQADD_ZPmZ_B |
| 8155 | 289400291690859620ULL, // SQADD_ZPmZ_D |
| 8156 | 439233043046141028ULL, // SQADD_ZPmZ_H |
| 8157 | 577639463935626340ULL, // SQADD_ZPmZ_S |
| 8158 | 35600180743268ULL, // SQADD_ZZZ_B |
| 8159 | 44395468475492ULL, // SQADD_ZZZ_D |
| 8160 | 17732068248676ULL, // SQADD_ZZZ_H |
| 8161 | 53192635272292ULL, // SQADD_ZZZ_S |
| 8162 | 7996302742883428ULL, // SQADDv16i8 |
| 8163 | 61984970132580ULL, // SQADDv1i16 |
| 8164 | 61984970132580ULL, // SQADDv1i32 |
| 8165 | 61984970132580ULL, // SQADDv1i64 |
| 8166 | 61984970132580ULL, // SQADDv1i8 |
| 8167 | 9122237011561572ULL, // SQADDv2i32 |
| 8168 | 2366700133649508ULL, // SQADDv2i64 |
| 8169 | 10248171282336868ULL, // SQADDv4i16 |
| 8170 | 3492634404424804ULL, // SQADDv4i32 |
| 8171 | 4618568673102948ULL, // SQADDv8i16 |
| 8172 | 11374105555209316ULL, // SQADDv8i8 |
| 8173 | 1442313380846144517ULL, // SQCADD_ZZI_B |
| 8174 | 1442322176133876741ULL, // SQCADD_ZZI_D |
| 8175 | 28279578948602885ULL, // SQCADD_ZZI_H |
| 8176 | 1442330973300673541ULL, // SQCADD_ZZI_S |
| 8177 | 4867561599ULL, // SQCVTN_Z2Z_StoH |
| 8178 | 4863367295ULL, // SQCVTN_Z4Z_DtoH |
| 8179 | 10471118975ULL, // SQCVTN_Z4Z_StoB |
| 8180 | 4867561648ULL, // SQCVTUN_Z2Z_StoH |
| 8181 | 4863367344ULL, // SQCVTUN_Z4Z_DtoH |
| 8182 | 10471119024ULL, // SQCVTUN_Z4Z_StoB |
| 8183 | 4867564210ULL, // SQCVTU_Z2Z_StoH |
| 8184 | 4863369906ULL, // SQCVTU_Z4Z_DtoH |
| 8185 | 10471121586ULL, // SQCVTU_Z4Z_StoB |
| 8186 | 4867564090ULL, // SQCVT_Z2Z_StoH |
| 8187 | 4863369786ULL, // SQCVT_Z4Z_DtoH |
| 8188 | 10471121466ULL, // SQCVT_Z4Z_StoB |
| 8189 | 8592049821ULL, // SQDECB_XPiI |
| 8190 | 20940080797ULL, // SQDECB_XPiWdI |
| 8191 | 8592051166ULL, // SQDECD_XPiI |
| 8192 | 20940082142ULL, // SQDECD_XPiWdI |
| 8193 | 8592083934ULL, // SQDECD_ZPiI |
| 8194 | 8592051970ULL, // SQDECH_XPiI |
| 8195 | 20940082946ULL, // SQDECH_XPiWdI |
| 8196 | 54595330ULL, // SQDECH_ZPiI |
| 8197 | 827248552728884ULL, // SQDECP_XPWd_B |
| 8198 | 827247747422516ULL, // SQDECP_XPWd_D |
| 8199 | 827247210551604ULL, // SQDECP_XPWd_H |
| 8200 | 827248821164340ULL, // SQDECP_XPWd_S |
| 8201 | 3491780916ULL, // SQDECP_XP_B |
| 8202 | 2686474548ULL, // SQDECP_XP_D |
| 8203 | 2149603636ULL, // SQDECP_XP_H |
| 8204 | 3760216372ULL, // SQDECP_XP_S |
| 8205 | 1612765492ULL, // SQDECP_ZP_D |
| 8206 | 4875950388ULL, // SQDECP_ZP_H |
| 8207 | 1881233716ULL, // SQDECP_ZP_S |
| 8208 | 8592057407ULL, // SQDECW_XPiI |
| 8209 | 20940088383ULL, // SQDECW_XPiWdI |
| 8210 | 8592122943ULL, // SQDECW_ZPiI |
| 8211 | 26802477129483ULL, // SQDMLALBT_ZZZ_D |
| 8212 | 18797264183051ULL, // SQDMLALBT_ZZZ_H |
| 8213 | 105968388103947ULL, // SQDMLALBT_ZZZ_S |
| 8214 | 457142164655228696ULL, // SQDMLALB_ZZZI_D |
| 8215 | 457221330566203160ULL, // SQDMLALB_ZZZI_S |
| 8216 | 26802477123352ULL, // SQDMLALB_ZZZ_D |
| 8217 | 18797264176920ULL, // SQDMLALB_ZZZ_H |
| 8218 | 105968388097816ULL, // SQDMLALB_ZZZ_S |
| 8219 | 457142164655235029ULL, // SQDMLALT_ZZZI_D |
| 8220 | 457221330566209493ULL, // SQDMLALT_ZZZI_S |
| 8221 | 26802477129685ULL, // SQDMLALT_ZZZ_D |
| 8222 | 18797264183253ULL, // SQDMLALT_ZZZ_H |
| 8223 | 105968388104149ULL, // SQDMLALT_ZZZ_S |
| 8224 | 387445512524326ULL, // SQDMLALi16 |
| 8225 | 387445512524326ULL, // SQDMLALi32 |
| 8226 | 1034825577110229542ULL, // SQDMLALv1i32_indexed |
| 8227 | 1050588175806026278ULL, // SQDMLALv1i64_indexed |
| 8228 | 1050588448815190566ULL, // SQDMLALv2i32_indexed |
| 8229 | 9131034985763366ULL, // SQDMLALv2i32_v2i64 |
| 8230 | 1034825884483326502ULL, // SQDMLALv4i16_indexed |
| 8231 | 10256969256538662ULL, // SQDMLALv4i16_v4i32 |
| 8232 | 1050588345735971048ULL, // SQDMLALv4i32_indexed |
| 8233 | 3501432372330728ULL, // SQDMLALv4i32_v2i64 |
| 8234 | 1034825781404106984ULL, // SQDMLALv8i16_indexed |
| 8235 | 4627366643106024ULL, // SQDMLALv8i16_v4i32 |
| 8236 | 26802477129522ULL, // SQDMLSLBT_ZZZ_D |
| 8237 | 18797264183090ULL, // SQDMLSLBT_ZZZ_H |
| 8238 | 105968388103986ULL, // SQDMLSLBT_ZZZ_S |
| 8239 | 457142164655228994ULL, // SQDMLSLB_ZZZI_D |
| 8240 | 457221330566203458ULL, // SQDMLSLB_ZZZI_S |
| 8241 | 26802477123650ULL, // SQDMLSLB_ZZZ_D |
| 8242 | 18797264177218ULL, // SQDMLSLB_ZZZ_H |
| 8243 | 105968388098114ULL, // SQDMLSLB_ZZZ_S |
| 8244 | 457142164655235260ULL, // SQDMLSLT_ZZZI_D |
| 8245 | 457221330566209724ULL, // SQDMLSLT_ZZZI_S |
| 8246 | 26802477129916ULL, // SQDMLSLT_ZZZ_D |
| 8247 | 18797264183484ULL, // SQDMLSLT_ZZZ_H |
| 8248 | 105968388104380ULL, // SQDMLSLT_ZZZ_S |
| 8249 | 387445512525397ULL, // SQDMLSLi16 |
| 8250 | 387445512525397ULL, // SQDMLSLi32 |
| 8251 | 1034825577110230613ULL, // SQDMLSLv1i32_indexed |
| 8252 | 1050588175806027349ULL, // SQDMLSLv1i64_indexed |
| 8253 | 1050588448815191637ULL, // SQDMLSLv2i32_indexed |
| 8254 | 9131034985764437ULL, // SQDMLSLv2i32_v2i64 |
| 8255 | 1034825884483327573ULL, // SQDMLSLv4i16_indexed |
| 8256 | 10256969256539733ULL, // SQDMLSLv4i16_v4i32 |
| 8257 | 1050588345735971180ULL, // SQDMLSLv4i32_indexed |
| 8258 | 3501432372330860ULL, // SQDMLSLv4i32_v2i64 |
| 8259 | 1034825781404107116ULL, // SQDMLSLv8i16_indexed |
| 8260 | 4627366643106156ULL, // SQDMLSLv8i16_v4i32 |
| 8261 | 21649080602594ULL, // SQDMULH_VG2_2Z2Z_B |
| 8262 | 19553138675682ULL, // SQDMULH_VG2_2Z2Z_D |
| 8263 | 18659787591650ULL, // SQDMULH_VG2_2Z2Z_H |
| 8264 | 19587502641122ULL, // SQDMULH_VG2_2Z2Z_S |
| 8265 | 792719413218ULL, // SQDMULH_VG2_2ZZ_B |
| 8266 | 18419267309538ULL, // SQDMULH_VG2_2ZZ_D |
| 8267 | 17732074655714ULL, // SQDMULH_VG2_2ZZ_H |
| 8268 | 18075674152930ULL, // SQDMULH_VG2_2ZZ_S |
| 8269 | 21649080602594ULL, // SQDMULH_VG4_4Z4Z_B |
| 8270 | 19553138675682ULL, // SQDMULH_VG4_4Z4Z_D |
| 8271 | 18659787591650ULL, // SQDMULH_VG4_4Z4Z_H |
| 8272 | 19587502641122ULL, // SQDMULH_VG4_4Z4Z_S |
| 8273 | 792719413218ULL, // SQDMULH_VG4_4ZZ_B |
| 8274 | 18419267309538ULL, // SQDMULH_VG4_4ZZ_D |
| 8275 | 17732074655714ULL, // SQDMULH_VG4_4ZZ_H |
| 8276 | 18075674152930ULL, // SQDMULH_VG4_4ZZ_S |
| 8277 | 50709891276394466ULL, // SQDMULH_ZZZI_D |
| 8278 | 334391417049058ULL, // SQDMULH_ZZZI_H |
| 8279 | 50718688443191266ULL, // SQDMULH_ZZZI_S |
| 8280 | 35600180744162ULL, // SQDMULH_ZZZ_B |
| 8281 | 44395468476386ULL, // SQDMULH_ZZZ_D |
| 8282 | 17732068249570ULL, // SQDMULH_ZZZ_H |
| 8283 | 53192635273186ULL, // SQDMULH_ZZZ_S |
| 8284 | 61984970133474ULL, // SQDMULHv1i16 |
| 8285 | 3196544597054476258ULL, // SQDMULHv1i16_indexed |
| 8286 | 61984970133474ULL, // SQDMULHv1i32 |
| 8287 | 3212307195750272994ULL, // SQDMULHv1i32_indexed |
| 8288 | 9122237011562466ULL, // SQDMULHv2i32 |
| 8289 | 3212307471978827746ULL, // SQDMULHv2i32_indexed |
| 8290 | 10248171282337762ULL, // SQDMULHv4i16 |
| 8291 | 3196544907646963682ULL, // SQDMULHv4i16_indexed |
| 8292 | 3492634404425698ULL, // SQDMULHv4i32 |
| 8293 | 3212307368905904098ULL, // SQDMULHv4i32_indexed |
| 8294 | 4618568673103842ULL, // SQDMULHv8i16 |
| 8295 | 3196544804571942882ULL, // SQDMULHv8i16_indexed |
| 8296 | 50718688443156460ULL, // SQDMULLB_ZZZI_D |
| 8297 | 50762667297687532ULL, // SQDMULLB_ZZZI_S |
| 8298 | 53192635238380ULL, // SQDMULLB_ZZZ_D |
| 8299 | 792738203628ULL, // SQDMULLB_ZZZ_H |
| 8300 | 97171489769452ULL, // SQDMULLB_ZZZ_S |
| 8301 | 50718688443162749ULL, // SQDMULLT_ZZZI_D |
| 8302 | 50762667297693821ULL, // SQDMULLT_ZZZI_S |
| 8303 | 53192635244669ULL, // SQDMULLT_ZZZ_D |
| 8304 | 792738209917ULL, // SQDMULLT_ZZZ_H |
| 8305 | 97171489775741ULL, // SQDMULLT_ZZZ_S |
| 8306 | 61984970134742ULL, // SQDMULLi16 |
| 8307 | 61984970134742ULL, // SQDMULLi32 |
| 8308 | 3196544597054477526ULL, // SQDMULLv1i32_indexed |
| 8309 | 3212307195750274262ULL, // SQDMULLv1i64_indexed |
| 8310 | 3212307471980926166ULL, // SQDMULLv2i32_indexed |
| 8311 | 9122237013660886ULL, // SQDMULLv2i32_v2i64 |
| 8312 | 3196544907649062102ULL, // SQDMULLv4i16_indexed |
| 8313 | 10248171284436182ULL, // SQDMULLv4i16_v4i32 |
| 8314 | 3212307368901706058ULL, // SQDMULLv4i32_indexed |
| 8315 | 3492634400227658ULL, // SQDMULLv4i32_v2i64 |
| 8316 | 3196544804569841994ULL, // SQDMULLv8i16_indexed |
| 8317 | 4618568671002954ULL, // SQDMULLv8i16_v4i32 |
| 8318 | 8592049837ULL, // SQINCB_XPiI |
| 8319 | 20940080813ULL, // SQINCB_XPiWdI |
| 8320 | 8592051182ULL, // SQINCD_XPiI |
| 8321 | 20940082158ULL, // SQINCD_XPiWdI |
| 8322 | 8592083950ULL, // SQINCD_ZPiI |
| 8323 | 8592051986ULL, // SQINCH_XPiI |
| 8324 | 20940082962ULL, // SQINCH_XPiWdI |
| 8325 | 54595346ULL, // SQINCH_ZPiI |
| 8326 | 827248552728900ULL, // SQINCP_XPWd_B |
| 8327 | 827247747422532ULL, // SQINCP_XPWd_D |
| 8328 | 827247210551620ULL, // SQINCP_XPWd_H |
| 8329 | 827248821164356ULL, // SQINCP_XPWd_S |
| 8330 | 3491780932ULL, // SQINCP_XP_B |
| 8331 | 2686474564ULL, // SQINCP_XP_D |
| 8332 | 2149603652ULL, // SQINCP_XP_H |
| 8333 | 3760216388ULL, // SQINCP_XP_S |
| 8334 | 1612765508ULL, // SQINCP_ZP_D |
| 8335 | 4875950404ULL, // SQINCP_ZP_H |
| 8336 | 1881233732ULL, // SQINCP_ZP_S |
| 8337 | 8592057423ULL, // SQINCW_XPiI |
| 8338 | 20940088399ULL, // SQINCW_XPiWdI |
| 8339 | 8592122959ULL, // SQINCW_ZPiI |
| 8340 | 34630307314ULL, // SQNEG_ZPmZ_B |
| 8341 | 8830723345906ULL, // SQNEG_ZPmZ_D |
| 8342 | 17661446655474ULL, // SQNEG_ZPmZ_H |
| 8343 | 26422909423090ULL, // SQNEG_ZPmZ_S |
| 8344 | 35288258743794ULL, // SQNEG_ZPzZ_B |
| 8345 | 44084351782386ULL, // SQNEG_ZPzZ_D |
| 8346 | 17730705100274ULL, // SQNEG_ZPzZ_H |
| 8347 | 52880444837362ULL, // SQNEG_ZPzZ_S |
| 8348 | 173149359602ULL, // SQNEGv16i8 |
| 8349 | 2117106ULL, // SQNEGv1i16 |
| 8350 | 2117106ULL, // SQNEGv1i32 |
| 8351 | 2117106ULL, // SQNEGv1i64 |
| 8352 | 2117106ULL, // SQNEGv1i8 |
| 8353 | 207511195122ULL, // SQNEGv2i32 |
| 8354 | 241873030642ULL, // SQNEGv2i64 |
| 8355 | 276234866162ULL, // SQNEGv4i16 |
| 8356 | 310596701682ULL, // SQNEGv4i32 |
| 8357 | 344958537202ULL, // SQNEGv8i16 |
| 8358 | 379320372722ULL, // SQNEGv8i8 |
| 8359 | 1874992851979406995ULL, // SQRDCMLAH_ZZZI_H |
| 8360 | 1754178857337966227ULL, // SQRDCMLAH_ZZZI_S |
| 8361 | 30532448452382355ULL, // SQRDCMLAH_ZZZ_B |
| 8362 | 2018747742991470227ULL, // SQRDCMLAH_ZZZ_D |
| 8363 | 30531310059589267ULL, // SQRDCMLAH_ZZZ_H |
| 8364 | 2018765335445982867ULL, // SQRDCMLAH_ZZZ_S |
| 8365 | 457124572200750750ULL, // SQRDMLAH_ZZZI_D |
| 8366 | 369507086438046ULL, // SQRDMLAH_ZZZI_H |
| 8367 | 457142164655263390ULL, // SQRDMLAH_ZZZI_S |
| 8368 | 18801758342814ULL, // SQRDMLAH_ZZZ_B |
| 8369 | 9210022645406ULL, // SQRDMLAH_ZZZ_D |
| 8370 | 17663365549726ULL, // SQRDMLAH_ZZZ_H |
| 8371 | 26802477158046ULL, // SQRDMLAH_ZZZ_S |
| 8372 | 387445512523422ULL, // SQRDMLAHv1i16 |
| 8373 | 1034825577110228638ULL, // SQRDMLAHv1i16_indexed |
| 8374 | 387445512523422ULL, // SQRDMLAHv1i32 |
| 8375 | 1050588175806025374ULL, // SQRDMLAHv1i32_indexed |
| 8376 | 9131034983665310ULL, // SQRDMLAHv2i32 |
| 8377 | 1050588448813092510ULL, // SQRDMLAHv2i32_indexed |
| 8378 | 10256969254440606ULL, // SQRDMLAHv4i16 |
| 8379 | 1034825884481228446ULL, // SQRDMLAHv4i16_indexed |
| 8380 | 3501432376528542ULL, // SQRDMLAHv4i32 |
| 8381 | 1050588345740168862ULL, // SQRDMLAHv4i32_indexed |
| 8382 | 4627366645206686ULL, // SQRDMLAHv8i16 |
| 8383 | 1034825781406207646ULL, // SQRDMLAHv8i16_indexed |
| 8384 | 457124572200751355ULL, // SQRDMLSH_ZZZI_D |
| 8385 | 369507086438651ULL, // SQRDMLSH_ZZZI_H |
| 8386 | 457142164655263995ULL, // SQRDMLSH_ZZZI_S |
| 8387 | 18801758343419ULL, // SQRDMLSH_ZZZ_B |
| 8388 | 9210022646011ULL, // SQRDMLSH_ZZZ_D |
| 8389 | 17663365550331ULL, // SQRDMLSH_ZZZ_H |
| 8390 | 26802477158651ULL, // SQRDMLSH_ZZZ_S |
| 8391 | 387445512524027ULL, // SQRDMLSHv1i16 |
| 8392 | 1034825577110229243ULL, // SQRDMLSHv1i16_indexed |
| 8393 | 387445512524027ULL, // SQRDMLSHv1i32 |
| 8394 | 1050588175806025979ULL, // SQRDMLSHv1i32_indexed |
| 8395 | 9131034983665915ULL, // SQRDMLSHv2i32 |
| 8396 | 1050588448813093115ULL, // SQRDMLSHv2i32_indexed |
| 8397 | 10256969254441211ULL, // SQRDMLSHv4i16 |
| 8398 | 1034825884481229051ULL, // SQRDMLSHv4i16_indexed |
| 8399 | 3501432376529147ULL, // SQRDMLSHv4i32 |
| 8400 | 1050588345740169467ULL, // SQRDMLSHv4i32_indexed |
| 8401 | 4627366645207291ULL, // SQRDMLSHv8i16 |
| 8402 | 1034825781406208251ULL, // SQRDMLSHv8i16_indexed |
| 8403 | 50709891276394475ULL, // SQRDMULH_ZZZI_D |
| 8404 | 334391417049067ULL, // SQRDMULH_ZZZI_H |
| 8405 | 50718688443191275ULL, // SQRDMULH_ZZZI_S |
| 8406 | 35600180744171ULL, // SQRDMULH_ZZZ_B |
| 8407 | 44395468476395ULL, // SQRDMULH_ZZZ_D |
| 8408 | 17732068249579ULL, // SQRDMULH_ZZZ_H |
| 8409 | 53192635273195ULL, // SQRDMULH_ZZZ_S |
| 8410 | 61984970133483ULL, // SQRDMULHv1i16 |
| 8411 | 3196544597054476267ULL, // SQRDMULHv1i16_indexed |
| 8412 | 61984970133483ULL, // SQRDMULHv1i32 |
| 8413 | 3212307195750273003ULL, // SQRDMULHv1i32_indexed |
| 8414 | 9122237011562475ULL, // SQRDMULHv2i32 |
| 8415 | 3212307471978827755ULL, // SQRDMULHv2i32_indexed |
| 8416 | 10248171282337771ULL, // SQRDMULHv4i16 |
| 8417 | 3196544907646963691ULL, // SQRDMULHv4i16_indexed |
| 8418 | 3492634404425707ULL, // SQRDMULHv4i32 |
| 8419 | 3212307368905904107ULL, // SQRDMULHv4i32_indexed |
| 8420 | 4618568673103851ULL, // SQRDMULHv8i16 |
| 8421 | 3196544804571942891ULL, // SQRDMULHv8i16_indexed |
| 8422 | 145276307521969272ULL, // SQRSHLR_ZPmZ_B |
| 8423 | 289400291690863736ULL, // SQRSHLR_ZPmZ_D |
| 8424 | 439233043046145144ULL, // SQRSHLR_ZPmZ_H |
| 8425 | 577639463935630456ULL, // SQRSHLR_ZPmZ_S |
| 8426 | 145276307521967220ULL, // SQRSHL_ZPmZ_B |
| 8427 | 289400291690861684ULL, // SQRSHL_ZPmZ_D |
| 8428 | 439233043046143092ULL, // SQRSHL_ZPmZ_H |
| 8429 | 577639463935628404ULL, // SQRSHL_ZPmZ_S |
| 8430 | 7996302742885492ULL, // SQRSHLv16i8 |
| 8431 | 61984970134644ULL, // SQRSHLv1i16 |
| 8432 | 61984970134644ULL, // SQRSHLv1i32 |
| 8433 | 61984970134644ULL, // SQRSHLv1i64 |
| 8434 | 61984970134644ULL, // SQRSHLv1i8 |
| 8435 | 9122237011563636ULL, // SQRSHLv2i32 |
| 8436 | 2366700133651572ULL, // SQRSHLv2i64 |
| 8437 | 10248171282338932ULL, // SQRSHLv4i16 |
| 8438 | 3492634404426868ULL, // SQRSHLv4i32 |
| 8439 | 4618568673105012ULL, // SQRSHLv8i16 |
| 8440 | 11374105555211380ULL, // SQRSHLv8i8 |
| 8441 | 61987117631677ULL, // SQRSHRNB_ZZI_B |
| 8442 | 18591057512637ULL, // SQRSHRNB_ZZI_H |
| 8443 | 61987654551741ULL, // SQRSHRNB_ZZI_S |
| 8444 | 387443364766006ULL, // SQRSHRNT_ZZI_B |
| 8445 | 19175175168310ULL, // SQRSHRNT_ZZI_H |
| 8446 | 387442022637878ULL, // SQRSHRNT_ZZI_S |
| 8447 | 61995439134799ULL, // SQRSHRN_VG4_Z4ZI_B |
| 8448 | 18591065905231ULL, // SQRSHRN_VG4_Z4ZI_H |
| 8449 | 61990338861135ULL, // SQRSHRN_Z2ZI_HtoB |
| 8450 | 18591070099535ULL, // SQRSHRN_Z2ZI_StoH |
| 8451 | 61984970135631ULL, // SQRSHRNb |
| 8452 | 61984970135631ULL, // SQRSHRNh |
| 8453 | 61984970135631ULL, // SQRSHRNs |
| 8454 | 387649798013390ULL, // SQRSHRNv16i8_shift |
| 8455 | 62123759736911ULL, // SQRSHRNv2i32_shift |
| 8456 | 62158123669583ULL, // SQRSHRNv4i16_shift |
| 8457 | 387581086925262ULL, // SQRSHRNv4i32_shift |
| 8458 | 387615448760782ULL, // SQRSHRNv8i16_shift |
| 8459 | 62192489699407ULL, // SQRSHRNv8i8_shift |
| 8460 | 61987117631731ULL, // SQRSHRUNB_ZZI_B |
| 8461 | 18591057512691ULL, // SQRSHRUNB_ZZI_H |
| 8462 | 61987654551795ULL, // SQRSHRUNB_ZZI_S |
| 8463 | 387443364766061ULL, // SQRSHRUNT_ZZI_B |
| 8464 | 19175175168365ULL, // SQRSHRUNT_ZZI_H |
| 8465 | 387442022637933ULL, // SQRSHRUNT_ZZI_S |
| 8466 | 61995439134886ULL, // SQRSHRUN_VG4_Z4ZI_B |
| 8467 | 18591065905318ULL, // SQRSHRUN_VG4_Z4ZI_H |
| 8468 | 61990338861222ULL, // SQRSHRUN_Z2ZI_HtoB |
| 8469 | 18591070099622ULL, // SQRSHRUN_Z2ZI_StoH |
| 8470 | 61984970135718ULL, // SQRSHRUNb |
| 8471 | 61984970135718ULL, // SQRSHRUNh |
| 8472 | 61984970135718ULL, // SQRSHRUNs |
| 8473 | 387649798013451ULL, // SQRSHRUNv16i8_shift |
| 8474 | 62123759736998ULL, // SQRSHRUNv2i32_shift |
| 8475 | 62158123669670ULL, // SQRSHRUNv4i16_shift |
| 8476 | 387581086925323ULL, // SQRSHRUNv4i32_shift |
| 8477 | 387615448760843ULL, // SQRSHRUNv8i16_shift |
| 8478 | 62192489699494ULL, // SQRSHRUNv8i8_shift |
| 8479 | 18591070102185ULL, // SQRSHRU_VG2_Z2ZI_H |
| 8480 | 61995439137449ULL, // SQRSHRU_VG4_Z4ZI_B |
| 8481 | 18591065907881ULL, // SQRSHRU_VG4_Z4ZI_H |
| 8482 | 18591070100505ULL, // SQRSHR_VG2_Z2ZI_H |
| 8483 | 61995439135769ULL, // SQRSHR_VG4_Z4ZI_B |
| 8484 | 18591065906201ULL, // SQRSHR_VG4_Z4ZI_H |
| 8485 | 145276307521969256ULL, // SQSHLR_ZPmZ_B |
| 8486 | 289400291690863720ULL, // SQSHLR_ZPmZ_D |
| 8487 | 439233043046145128ULL, // SQSHLR_ZPmZ_H |
| 8488 | 577639463935630440ULL, // SQSHLR_ZPmZ_S |
| 8489 | 1161119446114953ULL, // SQSHLU_ZPmI_B |
| 8490 | 1169915539153545ULL, // SQSHLU_ZPmI_D |
| 8491 | 450492042114572937ULL, // SQSHLU_ZPmI_H |
| 8492 | 1178711632208521ULL, // SQSHLU_ZPmI_S |
| 8493 | 61984970138249ULL, // SQSHLUb |
| 8494 | 61984970138249ULL, // SQSHLUd |
| 8495 | 61984970138249ULL, // SQSHLUh |
| 8496 | 61984970138249ULL, // SQSHLUs |
| 8497 | 62226836857481ULL, // SQSHLUv16i8_shift |
| 8498 | 62261198693001ULL, // SQSHLUv2i32_shift |
| 8499 | 62123761836681ULL, // SQSHLUv2i64_shift |
| 8500 | 62295562625673ULL, // SQSHLUv4i16_shift |
| 8501 | 62158125769353ULL, // SQSHLUv4i32_shift |
| 8502 | 62192487604873ULL, // SQSHLUv8i16_shift |
| 8503 | 62329928655497ULL, // SQSHLUv8i8_shift |
| 8504 | 1161119446111334ULL, // SQSHL_ZPmI_B |
| 8505 | 1169915539149926ULL, // SQSHL_ZPmI_D |
| 8506 | 450492042114569318ULL, // SQSHL_ZPmI_H |
| 8507 | 1178711632204902ULL, // SQSHL_ZPmI_S |
| 8508 | 145276307521967206ULL, // SQSHL_ZPmZ_B |
| 8509 | 289400291690861670ULL, // SQSHL_ZPmZ_D |
| 8510 | 439233043046143078ULL, // SQSHL_ZPmZ_H |
| 8511 | 577639463935628390ULL, // SQSHL_ZPmZ_S |
| 8512 | 61984970134630ULL, // SQSHLb |
| 8513 | 61984970134630ULL, // SQSHLd |
| 8514 | 61984970134630ULL, // SQSHLh |
| 8515 | 61984970134630ULL, // SQSHLs |
| 8516 | 7996302742885478ULL, // SQSHLv16i8 |
| 8517 | 62226836853862ULL, // SQSHLv16i8_shift |
| 8518 | 61984970134630ULL, // SQSHLv1i16 |
| 8519 | 61984970134630ULL, // SQSHLv1i32 |
| 8520 | 61984970134630ULL, // SQSHLv1i64 |
| 8521 | 61984970134630ULL, // SQSHLv1i8 |
| 8522 | 9122237011563622ULL, // SQSHLv2i32 |
| 8523 | 62261198689382ULL, // SQSHLv2i32_shift |
| 8524 | 2366700133651558ULL, // SQSHLv2i64 |
| 8525 | 62123761833062ULL, // SQSHLv2i64_shift |
| 8526 | 10248171282338918ULL, // SQSHLv4i16 |
| 8527 | 62295562622054ULL, // SQSHLv4i16_shift |
| 8528 | 3492634404426854ULL, // SQSHLv4i32 |
| 8529 | 62158125765734ULL, // SQSHLv4i32_shift |
| 8530 | 4618568673104998ULL, // SQSHLv8i16 |
| 8531 | 62192487601254ULL, // SQSHLv8i16_shift |
| 8532 | 11374105555211366ULL, // SQSHLv8i8 |
| 8533 | 62329928651878ULL, // SQSHLv8i8_shift |
| 8534 | 61987117631659ULL, // SQSHRNB_ZZI_B |
| 8535 | 18591057512619ULL, // SQSHRNB_ZZI_H |
| 8536 | 61987654551723ULL, // SQSHRNB_ZZI_S |
| 8537 | 387443364765988ULL, // SQSHRNT_ZZI_B |
| 8538 | 19175175168292ULL, // SQSHRNT_ZZI_H |
| 8539 | 387442022637860ULL, // SQSHRNT_ZZI_S |
| 8540 | 61990338861119ULL, // SQSHRN_Z2ZI_HtoB |
| 8541 | 18591070099519ULL, // SQSHRN_Z2ZI_StoH |
| 8542 | 61984970135615ULL, // SQSHRNb |
| 8543 | 61984970135615ULL, // SQSHRNh |
| 8544 | 61984970135615ULL, // SQSHRNs |
| 8545 | 387649798013372ULL, // SQSHRNv16i8_shift |
| 8546 | 62123759736895ULL, // SQSHRNv2i32_shift |
| 8547 | 62158123669567ULL, // SQSHRNv4i16_shift |
| 8548 | 387581086925244ULL, // SQSHRNv4i32_shift |
| 8549 | 387615448760764ULL, // SQSHRNv8i16_shift |
| 8550 | 62192489699391ULL, // SQSHRNv8i8_shift |
| 8551 | 61987117631721ULL, // SQSHRUNB_ZZI_B |
| 8552 | 18591057512681ULL, // SQSHRUNB_ZZI_H |
| 8553 | 61987654551785ULL, // SQSHRUNB_ZZI_S |
| 8554 | 387443364766051ULL, // SQSHRUNT_ZZI_B |
| 8555 | 19175175168355ULL, // SQSHRUNT_ZZI_H |
| 8556 | 387442022637923ULL, // SQSHRUNT_ZZI_S |
| 8557 | 61990338861213ULL, // SQSHRUN_Z2ZI_HtoB |
| 8558 | 18591070099613ULL, // SQSHRUN_Z2ZI_StoH |
| 8559 | 61984970135709ULL, // SQSHRUNb |
| 8560 | 61984970135709ULL, // SQSHRUNh |
| 8561 | 61984970135709ULL, // SQSHRUNs |
| 8562 | 387649798013441ULL, // SQSHRUNv16i8_shift |
| 8563 | 62123759736989ULL, // SQSHRUNv2i32_shift |
| 8564 | 62158123669661ULL, // SQSHRUNv4i16_shift |
| 8565 | 387581086925313ULL, // SQSHRUNv4i32_shift |
| 8566 | 387615448760833ULL, // SQSHRUNv8i16_shift |
| 8567 | 62192489699485ULL, // SQSHRUNv8i8_shift |
| 8568 | 145276307521969081ULL, // SQSUBR_ZPmZ_B |
| 8569 | 289400291690863545ULL, // SQSUBR_ZPmZ_D |
| 8570 | 439233043046144953ULL, // SQSUBR_ZPmZ_H |
| 8571 | 577639463935630265ULL, // SQSUBR_ZPmZ_S |
| 8572 | 167541576075912ULL, // SQSUB_ZI_B |
| 8573 | 176336863808136ULL, // SQSUB_ZI_D |
| 8574 | 930156186248ULL, // SQSUB_ZI_H |
| 8575 | 185134030604936ULL, // SQSUB_ZI_S |
| 8576 | 145276307521964680ULL, // SQSUB_ZPmZ_B |
| 8577 | 289400291690859144ULL, // SQSUB_ZPmZ_D |
| 8578 | 439233043046140552ULL, // SQSUB_ZPmZ_H |
| 8579 | 577639463935625864ULL, // SQSUB_ZPmZ_S |
| 8580 | 35600180742792ULL, // SQSUB_ZZZ_B |
| 8581 | 44395468475016ULL, // SQSUB_ZZZ_D |
| 8582 | 17732068248200ULL, // SQSUB_ZZZ_H |
| 8583 | 53192635271816ULL, // SQSUB_ZZZ_S |
| 8584 | 7996302742882952ULL, // SQSUBv16i8 |
| 8585 | 61984970132104ULL, // SQSUBv1i16 |
| 8586 | 61984970132104ULL, // SQSUBv1i32 |
| 8587 | 61984970132104ULL, // SQSUBv1i64 |
| 8588 | 61984970132104ULL, // SQSUBv1i8 |
| 8589 | 9122237011561096ULL, // SQSUBv2i32 |
| 8590 | 2366700133649032ULL, // SQSUBv2i64 |
| 8591 | 10248171282336392ULL, // SQSUBv4i16 |
| 8592 | 3492634404424328ULL, // SQSUBv4i32 |
| 8593 | 4618568673102472ULL, // SQSUBv8i16 |
| 8594 | 11374105555208840ULL, // SQSUBv8i8 |
| 8595 | 2149615833ULL, // SQXTNB_ZZ_B |
| 8596 | 4854974681ULL, // SQXTNB_ZZ_H |
| 8597 | 2686535897ULL, // SQXTNB_ZZ_S |
| 8598 | 2954928467ULL, // SQXTNT_ZZ_B |
| 8599 | 4857078099ULL, // SQXTNT_ZZ_H |
| 8600 | 1612800339ULL, // SQXTNT_ZZ_S |
| 8601 | 346827129329ULL, // SQXTNv16i8 |
| 8602 | 2119823ULL, // SQXTNv1i16 |
| 8603 | 2119823ULL, // SQXTNv1i32 |
| 8604 | 2119823ULL, // SQXTNv1i8 |
| 8605 | 241870936207ULL, // SQXTNv2i32 |
| 8606 | 310594607247ULL, // SQXTNv4i16 |
| 8607 | 243756302833ULL, // SQXTNv4i32 |
| 8608 | 312477876721ULL, // SQXTNv8i16 |
| 8609 | 344960637071ULL, // SQXTNv8i8 |
| 8610 | 2149615870ULL, // SQXTUNB_ZZ_B |
| 8611 | 4854974718ULL, // SQXTUNB_ZZ_H |
| 8612 | 2686535934ULL, // SQXTUNB_ZZ_S |
| 8613 | 2954928504ULL, // SQXTUNT_ZZ_B |
| 8614 | 4857078136ULL, // SQXTUNT_ZZ_H |
| 8615 | 1612800376ULL, // SQXTUNT_ZZ_S |
| 8616 | 346827129366ULL, // SQXTUNv16i8 |
| 8617 | 2119865ULL, // SQXTUNv1i16 |
| 8618 | 2119865ULL, // SQXTUNv1i32 |
| 8619 | 2119865ULL, // SQXTUNv1i8 |
| 8620 | 241870936249ULL, // SQXTUNv2i32 |
| 8621 | 310594607289ULL, // SQXTUNv4i16 |
| 8622 | 243756302870ULL, // SQXTUNv4i32 |
| 8623 | 312477876758ULL, // SQXTUNv8i16 |
| 8624 | 344960637113ULL, // SQXTUNv8i8 |
| 8625 | 145276307521965110ULL, // SRHADD_ZPmZ_B |
| 8626 | 289400291690859574ULL, // SRHADD_ZPmZ_D |
| 8627 | 439233043046140982ULL, // SRHADD_ZPmZ_H |
| 8628 | 577639463935626294ULL, // SRHADD_ZPmZ_S |
| 8629 | 7996302742883382ULL, // SRHADDv16i8 |
| 8630 | 9122237011561526ULL, // SRHADDv2i32 |
| 8631 | 10248171282336822ULL, // SRHADDv4i16 |
| 8632 | 3492634404424758ULL, // SRHADDv4i32 |
| 8633 | 4618568673102902ULL, // SRHADDv8i16 |
| 8634 | 11374105555209270ULL, // SRHADDv8i8 |
| 8635 | 19179715465668ULL, // SRI_ZZI_B |
| 8636 | 387442022601156ULL, // SRI_ZZI_D |
| 8637 | 19175194038724ULL, // SRI_ZZI_H |
| 8638 | 387442291069380ULL, // SRI_ZZI_S |
| 8639 | 387445512524228ULL, // SRId |
| 8640 | 387684157755844ULL, // SRIv16i8_shift |
| 8641 | 387718519591364ULL, // SRIv2i32_shift |
| 8642 | 387581082735044ULL, // SRIv2i64_shift |
| 8643 | 387752883524036ULL, // SRIv4i16_shift |
| 8644 | 387615446667716ULL, // SRIv4i32_shift |
| 8645 | 387649808503236ULL, // SRIv8i16_shift |
| 8646 | 387787249553860ULL, // SRIv8i8_shift |
| 8647 | 145276307521969290ULL, // SRSHLR_ZPmZ_B |
| 8648 | 289400291690863754ULL, // SRSHLR_ZPmZ_D |
| 8649 | 439233043046145162ULL, // SRSHLR_ZPmZ_H |
| 8650 | 577639463935630474ULL, // SRSHLR_ZPmZ_S |
| 8651 | 21649080603780ULL, // SRSHL_VG2_2Z2Z_B |
| 8652 | 19553138676868ULL, // SRSHL_VG2_2Z2Z_D |
| 8653 | 18659787592836ULL, // SRSHL_VG2_2Z2Z_H |
| 8654 | 19587502642308ULL, // SRSHL_VG2_2Z2Z_S |
| 8655 | 792719414404ULL, // SRSHL_VG2_2ZZ_B |
| 8656 | 18419267310724ULL, // SRSHL_VG2_2ZZ_D |
| 8657 | 17732074656900ULL, // SRSHL_VG2_2ZZ_H |
| 8658 | 18075674154116ULL, // SRSHL_VG2_2ZZ_S |
| 8659 | 21649080603780ULL, // SRSHL_VG4_4Z4Z_B |
| 8660 | 19553138676868ULL, // SRSHL_VG4_4Z4Z_D |
| 8661 | 18659787592836ULL, // SRSHL_VG4_4Z4Z_H |
| 8662 | 19587502642308ULL, // SRSHL_VG4_4Z4Z_S |
| 8663 | 792719414404ULL, // SRSHL_VG4_4ZZ_B |
| 8664 | 18419267310724ULL, // SRSHL_VG4_4ZZ_D |
| 8665 | 17732074656900ULL, // SRSHL_VG4_4ZZ_H |
| 8666 | 18075674154116ULL, // SRSHL_VG4_4ZZ_S |
| 8667 | 145276307521967236ULL, // SRSHL_ZPmZ_B |
| 8668 | 289400291690861700ULL, // SRSHL_ZPmZ_D |
| 8669 | 439233043046143108ULL, // SRSHL_ZPmZ_H |
| 8670 | 577639463935628420ULL, // SRSHL_ZPmZ_S |
| 8671 | 7996302742885508ULL, // SRSHLv16i8 |
| 8672 | 61984970134660ULL, // SRSHLv1i64 |
| 8673 | 9122237011563652ULL, // SRSHLv2i32 |
| 8674 | 2366700133651588ULL, // SRSHLv2i64 |
| 8675 | 10248171282338948ULL, // SRSHLv4i16 |
| 8676 | 3492634404426884ULL, // SRSHLv4i32 |
| 8677 | 4618568673105028ULL, // SRSHLv8i16 |
| 8678 | 11374105555211396ULL, // SRSHLv8i8 |
| 8679 | 1161119446113321ULL, // SRSHR_ZPmI_B |
| 8680 | 1169915539151913ULL, // SRSHR_ZPmI_D |
| 8681 | 450492042114571305ULL, // SRSHR_ZPmI_H |
| 8682 | 1178711632206889ULL, // SRSHR_ZPmI_S |
| 8683 | 61984970136617ULL, // SRSHRd |
| 8684 | 62226836855849ULL, // SRSHRv16i8_shift |
| 8685 | 62261198691369ULL, // SRSHRv2i32_shift |
| 8686 | 62123761835049ULL, // SRSHRv2i64_shift |
| 8687 | 62295562624041ULL, // SRSHRv4i16_shift |
| 8688 | 62158125767721ULL, // SRSHRv4i32_shift |
| 8689 | 62192487603241ULL, // SRSHRv8i16_shift |
| 8690 | 62329928653865ULL, // SRSHRv8i8_shift |
| 8691 | 19179715462362ULL, // SRSRA_ZZI_B |
| 8692 | 387442022597850ULL, // SRSRA_ZZI_D |
| 8693 | 19175194035418ULL, // SRSRA_ZZI_H |
| 8694 | 387442291066074ULL, // SRSRA_ZZI_S |
| 8695 | 387445512520922ULL, // SRSRAd |
| 8696 | 387684157752538ULL, // SRSRAv16i8_shift |
| 8697 | 387718519588058ULL, // SRSRAv2i32_shift |
| 8698 | 387581082731738ULL, // SRSRAv2i64_shift |
| 8699 | 387752883520730ULL, // SRSRAv4i16_shift |
| 8700 | 387615446664410ULL, // SRSRAv4i32_shift |
| 8701 | 387649808499930ULL, // SRSRAv8i16_shift |
| 8702 | 387787249550554ULL, // SRSRAv8i8_shift |
| 8703 | 61988728260572ULL, // SSHLLB_ZZI_D |
| 8704 | 18591082678236ULL, // SSHLLB_ZZI_H |
| 8705 | 61987117680604ULL, // SSHLLB_ZZI_S |
| 8706 | 61988728266861ULL, // SSHLLT_ZZI_D |
| 8707 | 18591082684525ULL, // SSHLLT_ZZI_H |
| 8708 | 61987117686893ULL, // SSHLLT_ZZI_S |
| 8709 | 62226847334714ULL, // SSHLLv16i8_shift |
| 8710 | 62261200786616ULL, // SSHLLv2i32_shift |
| 8711 | 62295564719288ULL, // SSHLLv4i16_shift |
| 8712 | 62158121566522ULL, // SSHLLv4i32_shift |
| 8713 | 62192485499194ULL, // SSHLLv8i16_shift |
| 8714 | 62329926554808ULL, // SSHLLv8i8_shift |
| 8715 | 7996302742885522ULL, // SSHLv16i8 |
| 8716 | 61984970134674ULL, // SSHLv1i64 |
| 8717 | 9122237011563666ULL, // SSHLv2i32 |
| 8718 | 2366700133651602ULL, // SSHLv2i64 |
| 8719 | 10248171282338962ULL, // SSHLv4i16 |
| 8720 | 3492634404426898ULL, // SSHLv4i32 |
| 8721 | 4618568673105042ULL, // SSHLv8i16 |
| 8722 | 11374105555211410ULL, // SSHLv8i8 |
| 8723 | 61984970136631ULL, // SSHRd |
| 8724 | 62226836855863ULL, // SSHRv16i8_shift |
| 8725 | 62261198691383ULL, // SSHRv2i32_shift |
| 8726 | 62123761835063ULL, // SSHRv2i64_shift |
| 8727 | 62295562624055ULL, // SSHRv4i16_shift |
| 8728 | 62158125767735ULL, // SSHRv4i32_shift |
| 8729 | 62192487603255ULL, // SSHRv8i16_shift |
| 8730 | 62329928653879ULL, // SSHRv8i8_shift |
| 8731 | 19179715462376ULL, // SSRA_ZZI_B |
| 8732 | 387442022597864ULL, // SSRA_ZZI_D |
| 8733 | 19175194035432ULL, // SSRA_ZZI_H |
| 8734 | 387442291066088ULL, // SSRA_ZZI_S |
| 8735 | 387445512520936ULL, // SSRAd |
| 8736 | 387684157752552ULL, // SSRAv16i8_shift |
| 8737 | 387718519588072ULL, // SSRAv2i32_shift |
| 8738 | 387581082731752ULL, // SSRAv2i64_shift |
| 8739 | 387752883520744ULL, // SSRAv4i16_shift |
| 8740 | 387615446664424ULL, // SSRAv4i32_shift |
| 8741 | 387649808499944ULL, // SSRAv8i16_shift |
| 8742 | 387787249550568ULL, // SSRAv8i8_shift |
| 8743 | 51924354755364282ULL, // SST1B_D |
| 8744 | 3476911699571934650ULL, // SST1B_D_IMM |
| 8745 | 53050254662206906ULL, // SST1B_D_SXTW |
| 8746 | 54176154569049530ULL, // SST1B_D_UXTW |
| 8747 | 3476911355974583738ULL, // SST1B_S_IMM |
| 8748 | 55302054475924922ULL, // SST1B_S_SXTW |
| 8749 | 56427954382767546ULL, // SST1B_S_UXTW |
| 8750 | 51924354755365767ULL, // SST1D |
| 8751 | 57553682490887047ULL, // SST1D_IMM |
| 8752 | 58679754196421511ULL, // SST1D_SCALED |
| 8753 | 53050254662208391ULL, // SST1D_SXTW |
| 8754 | 59805654103264135ULL, // SST1D_SXTW_SCALED |
| 8755 | 54176154569051015ULL, // SST1D_UXTW |
| 8756 | 60931554010106759ULL, // SST1D_UXTW_SCALED |
| 8757 | 51924354755366470ULL, // SST1H_D |
| 8758 | 3520821795938799174ULL, // SST1H_D_IMM |
| 8759 | 63183353823792710ULL, // SST1H_D_SCALED |
| 8760 | 53050254662209094ULL, // SST1H_D_SXTW |
| 8761 | 64309253730635334ULL, // SST1H_D_SXTW_SCALED |
| 8762 | 54176154569051718ULL, // SST1H_D_UXTW |
| 8763 | 65435153637477958ULL, // SST1H_D_UXTW_SCALED |
| 8764 | 3520821452341448262ULL, // SST1H_S_IMM |
| 8765 | 55302054475927110ULL, // SST1H_S_SXTW |
| 8766 | 66561053544353350ULL, // SST1H_S_SXTW_SCALED |
| 8767 | 56427954382769734ULL, // SST1H_S_UXTW |
| 8768 | 67686953451195974ULL, // SST1H_S_UXTW_SCALED |
| 8769 | 3476911699572267779ULL, // SST1Q |
| 8770 | 51924354755372022ULL, // SST1W_D |
| 8771 | 3527577195379860470ULL, // SST1W_D_IMM |
| 8772 | 69938753264854006ULL, // SST1W_D_SCALED |
| 8773 | 53050254662214646ULL, // SST1W_D_SXTW |
| 8774 | 71064653171696630ULL, // SST1W_D_SXTW_SCALED |
| 8775 | 54176154569057270ULL, // SST1W_D_UXTW |
| 8776 | 72190553078539254ULL, // SST1W_D_UXTW_SCALED |
| 8777 | 3527576851782509558ULL, // SST1W_IMM |
| 8778 | 55302054475932662ULL, // SST1W_SXTW |
| 8779 | 73316452985414646ULL, // SST1W_SXTW_SCALED |
| 8780 | 56427954382775286ULL, // SST1W_UXTW |
| 8781 | 74442352892257270ULL, // SST1W_UXTW_SCALED |
| 8782 | 53192635244310ULL, // SSUBLBT_ZZZ_D |
| 8783 | 792738209558ULL, // SSUBLBT_ZZZ_H |
| 8784 | 97171489775382ULL, // SSUBLBT_ZZZ_S |
| 8785 | 53192635238293ULL, // SSUBLB_ZZZ_D |
| 8786 | 792738203541ULL, // SSUBLB_ZZZ_H |
| 8787 | 97171489769365ULL, // SSUBLB_ZZZ_S |
| 8788 | 53192635238952ULL, // SSUBLTB_ZZZ_D |
| 8789 | 792738204200ULL, // SSUBLTB_ZZZ_H |
| 8790 | 97171489770024ULL, // SSUBLTB_ZZZ_S |
| 8791 | 53192635244559ULL, // SSUBLT_ZZZ_D |
| 8792 | 792738209807ULL, // SSUBLT_ZZZ_H |
| 8793 | 97171489775631ULL, // SSUBLT_ZZZ_S |
| 8794 | 7996302753366282ULL, // SSUBLv16i8_v8i16 |
| 8795 | 9122237013660640ULL, // SSUBLv2i32_v2i64 |
| 8796 | 10248171284435936ULL, // SSUBLv4i16_v4i32 |
| 8797 | 3492634400227594ULL, // SSUBLv4i32_v2i64 |
| 8798 | 4618568671002890ULL, // SSUBLv8i16_v4i32 |
| 8799 | 11374105553114080ULL, // SSUBLv8i8_v8i16 |
| 8800 | 53191561497244ULL, // SSUBWB_ZZZ_D |
| 8801 | 792717232796ULL, // SSUBWB_ZZZ_H |
| 8802 | 97173100382876ULL, // SSUBWB_ZZZ_S |
| 8803 | 53191561503310ULL, // SSUBWT_ZZZ_D |
| 8804 | 792717238862ULL, // SSUBWT_ZZZ_H |
| 8805 | 97173100388942ULL, // SSUBWT_ZZZ_S |
| 8806 | 7996268393628246ULL, // SSUBWv16i8_v8i16 |
| 8807 | 9122099574711336ULL, // SSUBWv2i32_v2i64 |
| 8808 | 10248033845486632ULL, // SSUBWv4i16_v4i32 |
| 8809 | 3492600040489558ULL, // SSUBWv4i32_v2i64 |
| 8810 | 4618534311264854ULL, // SSUBWv8i16_v4i32 |
| 8811 | 11373968114164776ULL, // SSUBWv8i8_v8i16 |
| 8812 | 75568252799043002ULL, // ST1B |
| 8813 | 75568252889220538ULL, // ST1B_2Z |
| 8814 | 3664937155903505850ULL, // ST1B_2Z_IMM |
| 8815 | 6198141743891252666ULL, // ST1B_2Z_STRIDED |
| 8816 | 6342256931967108538ULL, // ST1B_2Z_STRIDED_IMM |
| 8817 | 75568252889220538ULL, // ST1B_4Z |
| 8818 | 3671692555344561594ULL, // ST1B_4Z_IMM |
| 8819 | 75568252889220538ULL, // ST1B_4Z_STRIDED |
| 8820 | 3671692555344561594ULL, // ST1B_4Z_STRIDED_IMM |
| 8821 | 75568252799059386ULL, // ST1B_D |
| 8822 | 3621027059446482362ULL, // ST1B_D_IMM |
| 8823 | 75568252799075770ULL, // ST1B_H |
| 8824 | 3621027059446498746ULL, // ST1B_H_IMM |
| 8825 | 3621027059446465978ULL, // ST1B_IMM |
| 8826 | 75568252799092154ULL, // ST1B_S |
| 8827 | 3621027059446515130ULL, // ST1B_S_IMM |
| 8828 | 76694152705903495ULL, // ST1D |
| 8829 | 76694152796081031ULL, // ST1D_2Z |
| 8830 | 3664937155903523719ULL, // ST1D_2Z_IMM |
| 8831 | 76694152796081031ULL, // ST1D_2Z_STRIDED |
| 8832 | 3664937155903523719ULL, // ST1D_2Z_STRIDED_IMM |
| 8833 | 76694152796081031ULL, // ST1D_4Z |
| 8834 | 3671692555344579463ULL, // ST1D_4Z_IMM |
| 8835 | 76694152796081031ULL, // ST1D_4Z_STRIDED |
| 8836 | 3671692555344579463ULL, // ST1D_4Z_STRIDED_IMM |
| 8837 | 3621027059446483847ULL, // ST1D_IMM |
| 8838 | 76694152706231175ULL, // ST1D_Q |
| 8839 | 3621027059446811527ULL, // ST1D_Q_IMM |
| 8840 | 573564ULL, // ST1Fourv16b |
| 8841 | 99156092ULL, // ST1Fourv16b_POST |
| 8842 | 606332ULL, // ST1Fourv1d |
| 8843 | 101286012ULL, // ST1Fourv1d_POST |
| 8844 | 639100ULL, // ST1Fourv2d |
| 8845 | 99221628ULL, // ST1Fourv2d_POST |
| 8846 | 671868ULL, // ST1Fourv2s |
| 8847 | 101351548ULL, // ST1Fourv2s_POST |
| 8848 | 704636ULL, // ST1Fourv4h |
| 8849 | 101384316ULL, // ST1Fourv4h_POST |
| 8850 | 737404ULL, // ST1Fourv4s |
| 8851 | 99319932ULL, // ST1Fourv4s_POST |
| 8852 | 770172ULL, // ST1Fourv8b |
| 8853 | 101449852ULL, // ST1Fourv8b_POST |
| 8854 | 802940ULL, // ST1Fourv8h |
| 8855 | 99385468ULL, // ST1Fourv8h_POST |
| 8856 | 77820052612763206ULL, // ST1H |
| 8857 | 77820052702940742ULL, // ST1H_2Z |
| 8858 | 3664937155903540806ULL, // ST1H_2Z_IMM |
| 8859 | 6486372120043245126ULL, // ST1H_2Z_STRIDED |
| 8860 | 6342256931967389254ULL, // ST1H_2Z_STRIDED_IMM |
| 8861 | 77820052702940742ULL, // ST1H_4Z |
| 8862 | 3671692555344596550ULL, // ST1H_4Z_IMM |
| 8863 | 77820052702940742ULL, // ST1H_4Z_STRIDED |
| 8864 | 3671692555344596550ULL, // ST1H_4Z_STRIDED_IMM |
| 8865 | 77820052612746822ULL, // ST1H_D |
| 8866 | 3621027059446484550ULL, // ST1H_D_IMM |
| 8867 | 3621027059446500934ULL, // ST1H_IMM |
| 8868 | 77820052612779590ULL, // ST1H_S |
| 8869 | 3621027059446517318ULL, // ST1H_S_IMM |
| 8870 | 573564ULL, // ST1Onev16b |
| 8871 | 103350396ULL, // ST1Onev16b_POST |
| 8872 | 606332ULL, // ST1Onev1d |
| 8873 | 105480316ULL, // ST1Onev1d_POST |
| 8874 | 639100ULL, // ST1Onev2d |
| 8875 | 103415932ULL, // ST1Onev2d_POST |
| 8876 | 671868ULL, // ST1Onev2s |
| 8877 | 105545852ULL, // ST1Onev2s_POST |
| 8878 | 704636ULL, // ST1Onev4h |
| 8879 | 105578620ULL, // ST1Onev4h_POST |
| 8880 | 737404ULL, // ST1Onev4s |
| 8881 | 103514236ULL, // ST1Onev4s_POST |
| 8882 | 770172ULL, // ST1Onev8b |
| 8883 | 105644156ULL, // ST1Onev8b_POST |
| 8884 | 802940ULL, // ST1Onev8h |
| 8885 | 103579772ULL, // ST1Onev8h_POST |
| 8886 | 573564ULL, // ST1Threev16b |
| 8887 | 113836156ULL, // ST1Threev16b_POST |
| 8888 | 606332ULL, // ST1Threev1d |
| 8889 | 115966076ULL, // ST1Threev1d_POST |
| 8890 | 639100ULL, // ST1Threev2d |
| 8891 | 113901692ULL, // ST1Threev2d_POST |
| 8892 | 671868ULL, // ST1Threev2s |
| 8893 | 116031612ULL, // ST1Threev2s_POST |
| 8894 | 704636ULL, // ST1Threev4h |
| 8895 | 116064380ULL, // ST1Threev4h_POST |
| 8896 | 737404ULL, // ST1Threev4s |
| 8897 | 113999996ULL, // ST1Threev4s_POST |
| 8898 | 770172ULL, // ST1Threev8b |
| 8899 | 116129916ULL, // ST1Threev8b_POST |
| 8900 | 802940ULL, // ST1Threev8h |
| 8901 | 114065532ULL, // ST1Threev8h_POST |
| 8902 | 573564ULL, // ST1Twov16b |
| 8903 | 101253244ULL, // ST1Twov16b_POST |
| 8904 | 606332ULL, // ST1Twov1d |
| 8905 | 103383164ULL, // ST1Twov1d_POST |
| 8906 | 639100ULL, // ST1Twov2d |
| 8907 | 101318780ULL, // ST1Twov2d_POST |
| 8908 | 671868ULL, // ST1Twov2s |
| 8909 | 103448700ULL, // ST1Twov2s_POST |
| 8910 | 704636ULL, // ST1Twov4h |
| 8911 | 103481468ULL, // ST1Twov4h_POST |
| 8912 | 737404ULL, // ST1Twov4s |
| 8913 | 101417084ULL, // ST1Twov4s_POST |
| 8914 | 770172ULL, // ST1Twov8b |
| 8915 | 103547004ULL, // ST1Twov8b_POST |
| 8916 | 802940ULL, // ST1Twov8h |
| 8917 | 101482620ULL, // ST1Twov8h_POST |
| 8918 | 80071852426470390ULL, // ST1W |
| 8919 | 80071852516647926ULL, // ST1W_2Z |
| 8920 | 3664937155903562742ULL, // ST1W_2Z_IMM |
| 8921 | 80071852516647926ULL, // ST1W_2Z_STRIDED |
| 8922 | 3664937155903562742ULL, // ST1W_2Z_STRIDED_IMM |
| 8923 | 80071852516647926ULL, // ST1W_4Z |
| 8924 | 3671692555344618486ULL, // ST1W_4Z_IMM |
| 8925 | 80071852516647926ULL, // ST1W_4Z_STRIDED |
| 8926 | 3671692555344618486ULL, // ST1W_4Z_STRIDED_IMM |
| 8927 | 80071852426437622ULL, // ST1W_D |
| 8928 | 3621027059446490102ULL, // ST1W_D_IMM |
| 8929 | 3621027059446522870ULL, // ST1W_IMM |
| 8930 | 80071852426765302ULL, // ST1W_Q |
| 8931 | 3621027059446817782ULL, // ST1W_Q_IMM |
| 8932 | 83029004571389356ULL, // ST1_MXIPXX_H_B |
| 8933 | 84154904478231994ULL, // ST1_MXIPXX_H_D |
| 8934 | 85280804385074632ULL, // ST1_MXIPXX_H_H |
| 8935 | 86406704291917270ULL, // ST1_MXIPXX_H_Q |
| 8936 | 87532604198759908ULL, // ST1_MXIPXX_H_S |
| 8937 | 83029004571405740ULL, // ST1_MXIPXX_V_B |
| 8938 | 84154904478248378ULL, // ST1_MXIPXX_V_D |
| 8939 | 85280804385091016ULL, // ST1_MXIPXX_V_H |
| 8940 | 86406704291933654ULL, // ST1_MXIPXX_V_Q |
| 8941 | 87532604198776292ULL, // ST1_MXIPXX_V_S |
| 8942 | 176996476ULL, // ST1i16 |
| 8943 | 21653946492ULL, // ST1i16_POST |
| 8944 | 1228924ULL, // ST1i32 |
| 8945 | 21922414716ULL, // ST1i32_POST |
| 8946 | 1245308ULL, // ST1i64 |
| 8947 | 22190882940ULL, // ST1i64_POST |
| 8948 | 176717948ULL, // ST1i8 |
| 8949 | 22459351164ULL, // ST1i8_POST |
| 8950 | 75568252799043031ULL, // ST2B |
| 8951 | 3664937155813328343ULL, // ST2B_IMM |
| 8952 | 76694152705903507ULL, // ST2D |
| 8953 | 3664937155813346195ULL, // ST2D_IMM |
| 8954 | 644903069863374ULL, // ST2GPostIndex |
| 8955 | 95218124422696398ULL, // ST2GPreIndex |
| 8956 | 29344178678812110ULL, // ST2Gi |
| 8957 | 77820052612763235ULL, // ST2H |
| 8958 | 3664937155813363299ULL, // ST2H_IMM |
| 8959 | 87953151774661391ULL, // ST2Q |
| 8960 | 3664937155813677839ULL, // ST2Q_IMM |
| 8961 | 574033ULL, // ST2Twov16b |
| 8962 | 101253713ULL, // ST2Twov16b_POST |
| 8963 | 639569ULL, // ST2Twov2d |
| 8964 | 101319249ULL, // ST2Twov2d_POST |
| 8965 | 672337ULL, // ST2Twov2s |
| 8966 | 103449169ULL, // ST2Twov2s_POST |
| 8967 | 705105ULL, // ST2Twov4h |
| 8968 | 103481937ULL, // ST2Twov4h_POST |
| 8969 | 737873ULL, // ST2Twov4s |
| 8970 | 101417553ULL, // ST2Twov4s_POST |
| 8971 | 770641ULL, // ST2Twov8b |
| 8972 | 103547473ULL, // ST2Twov8b_POST |
| 8973 | 803409ULL, // ST2Twov8h |
| 8974 | 101483089ULL, // ST2Twov8h_POST |
| 8975 | 80071852426470410ULL, // ST2W |
| 8976 | 3664937155813385226ULL, // ST2W_IMM |
| 8977 | 176996945ULL, // ST2i16 |
| 8978 | 21922382417ULL, // ST2i16_POST |
| 8979 | 1229393ULL, // ST2i32 |
| 8980 | 22190850641ULL, // ST2i32_POST |
| 8981 | 1245777ULL, // ST2i64 |
| 8982 | 22727754321ULL, // ST2i64_POST |
| 8983 | 176718417ULL, // ST2i8 |
| 8984 | 21654045265ULL, // ST2i8_POST |
| 8985 | 75568252799043052ULL, // ST3B |
| 8986 | 89079051681154540ULL, // ST3B_IMM |
| 8987 | 76694152705903519ULL, // ST3D |
| 8988 | 89079051681172383ULL, // ST3D_IMM |
| 8989 | 77820052612763247ULL, // ST3H |
| 8990 | 89079051681189487ULL, // ST3H_IMM |
| 8991 | 87953151774661403ULL, // ST3Q |
| 8992 | 89079051681504027ULL, // ST3Q_IMM |
| 8993 | 574099ULL, // ST3Threev16b |
| 8994 | 113836691ULL, // ST3Threev16b_POST |
| 8995 | 639635ULL, // ST3Threev2d |
| 8996 | 113902227ULL, // ST3Threev2d_POST |
| 8997 | 672403ULL, // ST3Threev2s |
| 8998 | 116032147ULL, // ST3Threev2s_POST |
| 8999 | 705171ULL, // ST3Threev4h |
| 9000 | 116064915ULL, // ST3Threev4h_POST |
| 9001 | 737939ULL, // ST3Threev4s |
| 9002 | 114000531ULL, // ST3Threev4s_POST |
| 9003 | 770707ULL, // ST3Threev8b |
| 9004 | 116130451ULL, // ST3Threev8b_POST |
| 9005 | 803475ULL, // ST3Threev8h |
| 9006 | 114066067ULL, // ST3Threev8h_POST |
| 9007 | 80071852426470422ULL, // ST3W |
| 9008 | 89079051681211414ULL, // ST3W_IMM |
| 9009 | 176997011ULL, // ST3i16 |
| 9010 | 22996124307ULL, // ST3i16_POST |
| 9011 | 1229459ULL, // ST3i32 |
| 9012 | 23264592531ULL, // ST3i32_POST |
| 9013 | 1245843ULL, // ST3i64 |
| 9014 | 23533060755ULL, // ST3i64_POST |
| 9015 | 176718483ULL, // ST3i8 |
| 9016 | 23801528979ULL, // ST3i8_POST |
| 9017 | 75568252799043094ULL, // ST4B |
| 9018 | 3671692555254384150ULL, // ST4B_IMM |
| 9019 | 76694152705903531ULL, // ST4D |
| 9020 | 3671692555254401963ULL, // ST4D_IMM |
| 9021 | 574123ULL, // ST4Fourv16b |
| 9022 | 99156651ULL, // ST4Fourv16b_POST |
| 9023 | 639659ULL, // ST4Fourv2d |
| 9024 | 99222187ULL, // ST4Fourv2d_POST |
| 9025 | 672427ULL, // ST4Fourv2s |
| 9026 | 101352107ULL, // ST4Fourv2s_POST |
| 9027 | 705195ULL, // ST4Fourv4h |
| 9028 | 101384875ULL, // ST4Fourv4h_POST |
| 9029 | 737963ULL, // ST4Fourv4s |
| 9030 | 99320491ULL, // ST4Fourv4s_POST |
| 9031 | 770731ULL, // ST4Fourv8b |
| 9032 | 101450411ULL, // ST4Fourv8b_POST |
| 9033 | 803499ULL, // ST4Fourv8h |
| 9034 | 99386027ULL, // ST4Fourv8h_POST |
| 9035 | 77820052612763259ULL, // ST4H |
| 9036 | 3671692555254419067ULL, // ST4H_IMM |
| 9037 | 87953151774661415ULL, // ST4Q |
| 9038 | 3671692555254733607ULL, // ST4Q_IMM |
| 9039 | 80071852426470434ULL, // ST4W |
| 9040 | 3671692555254440994ULL, // ST4W_IMM |
| 9041 | 176997035ULL, // ST4i16 |
| 9042 | 22190817963ULL, // ST4i16_POST |
| 9043 | 1229483ULL, // ST4i32 |
| 9044 | 22727721643ULL, // ST4i32_POST |
| 9045 | 1245867ULL, // ST4i64 |
| 9046 | 24069931691ULL, // ST4i64_POST |
| 9047 | 176718507ULL, // ST4i8 |
| 9048 | 21922480811ULL, // ST4i8_POST |
| 9049 | 984585ULL, // ST64B |
| 9050 | 24161313483ULL, // ST64BV |
| 9051 | 24161304618ULL, // ST64BV0 |
| 9052 | 180374557ULL, // STBFADD |
| 9053 | 180376590ULL, // STBFADDL |
| 9054 | 180380975ULL, // STBFMAX |
| 9055 | 180377344ULL, // STBFMAXL |
| 9056 | 180377498ULL, // STBFMAXNM |
| 9057 | 180376878ULL, // STBFMAXNML |
| 9058 | 180377605ULL, // STBFMIN |
| 9059 | 180376922ULL, // STBFMINL |
| 9060 | 180377456ULL, // STBFMINNM |
| 9061 | 180376832ULL, // STBFMINNML |
| 9062 | 180374574ULL, // STFADDD |
| 9063 | 180374574ULL, // STFADDH |
| 9064 | 180376609ULL, // STFADDLD |
| 9065 | 180376609ULL, // STFADDLH |
| 9066 | 180376609ULL, // STFADDLS |
| 9067 | 180374574ULL, // STFADDS |
| 9068 | 180380992ULL, // STFMAXD |
| 9069 | 180380992ULL, // STFMAXH |
| 9070 | 180377363ULL, // STFMAXLD |
| 9071 | 180377363ULL, // STFMAXLH |
| 9072 | 180377363ULL, // STFMAXLS |
| 9073 | 180377519ULL, // STFMAXNMD |
| 9074 | 180377519ULL, // STFMAXNMH |
| 9075 | 180376901ULL, // STFMAXNMLD |
| 9076 | 180376901ULL, // STFMAXNMLH |
| 9077 | 180376901ULL, // STFMAXNMLS |
| 9078 | 180377519ULL, // STFMAXNMS |
| 9079 | 180380992ULL, // STFMAXS |
| 9080 | 180377622ULL, // STFMIND |
| 9081 | 180377622ULL, // STFMINH |
| 9082 | 180376941ULL, // STFMINLD |
| 9083 | 180376941ULL, // STFMINLH |
| 9084 | 180376941ULL, // STFMINLS |
| 9085 | 180377477ULL, // STFMINNMD |
| 9086 | 180377477ULL, // STFMINNMH |
| 9087 | 180376855ULL, // STFMINNMLD |
| 9088 | 180376855ULL, // STFMINNMLH |
| 9089 | 180376855ULL, // STFMINNMLS |
| 9090 | 180377477ULL, // STFMINNMS |
| 9091 | 180377622ULL, // STFMINS |
| 9092 | 2508300769102ULL, // STGM |
| 9093 | 3892298718839331174ULL, // STGPi |
| 9094 | 644903069863438ULL, // STGPostIndex |
| 9095 | 4417293535970384230ULL, // STGPpost |
| 9096 | 4324969743609289062ULL, // STGPpre |
| 9097 | 95218124422696462ULL, // STGPreIndex |
| 9098 | 29344178678812174ULL, // STGi |
| 9099 | 29336138462288273ULL, // STILPW |
| 9100 | 102845092949449105ULL, // STILPWpre |
| 9101 | 29336138462288273ULL, // STILPX |
| 9102 | 103970992856291729ULL, // STILPXpre |
| 9103 | 1245240ULL, // STL1 |
| 9104 | 984577ULL, // STL64B |
| 9105 | 24161313474ULL, // STL64BV |
| 9106 | 24161304608ULL, // STL64BV0 |
| 9107 | 2508300765512ULL, // STLLRB |
| 9108 | 2508300767331ULL, // STLLRH |
| 9109 | 2508300770458ULL, // STLLRW |
| 9110 | 2508300770458ULL, // STLLRX |
| 9111 | 90134733431789976ULL, // STLPi |
| 9112 | 2508300765520ULL, // STLRB |
| 9113 | 2508300767339ULL, // STLRH |
| 9114 | 2508300770471ULL, // STLRW |
| 9115 | 4300107734183ULL, // STLRWpre |
| 9116 | 2508300770471ULL, // STLRX |
| 9117 | 4334467472551ULL, // STLRXpre |
| 9118 | 29336138462289258ULL, // STLTXRW |
| 9119 | 29336138462289258ULL, // STLTXRX |
| 9120 | 29335382585788802ULL, // STLURBi |
| 9121 | 29335382585790621ULL, // STLURHi |
| 9122 | 29335382585793812ULL, // STLURWi |
| 9123 | 29335382585793812ULL, // STLURXi |
| 9124 | 29335382585793812ULL, // STLURbi |
| 9125 | 29335382585793812ULL, // STLURdi |
| 9126 | 29335382585793812ULL, // STLURhi |
| 9127 | 29335382585793812ULL, // STLURqi |
| 9128 | 29335382585793812ULL, // STLURsi |
| 9129 | 104770676306500331ULL, // STLXPW |
| 9130 | 104770676306500331ULL, // STLXPX |
| 9131 | 29336138462284201ULL, // STLXRB |
| 9132 | 29336138462286020ULL, // STLXRH |
| 9133 | 29336138462289236ULL, // STLXRW |
| 9134 | 29336138462289236ULL, // STLXRX |
| 9135 | 396249465472021ULL, // STMOPA_M2ZZZI_BtoS |
| 9136 | 396242729419797ULL, // STMOPA_M2ZZZI_HtoS |
| 9137 | 3748183530763475448ULL, // STNPDi |
| 9138 | 3892298718839331320ULL, // STNPQi |
| 9139 | 4036413906915187192ULL, // STNPSi |
| 9140 | 4036413906915187192ULL, // STNPWi |
| 9141 | 3748183530763475448ULL, // STNPXi |
| 9142 | 75568252889220530ULL, // STNT1B_2Z |
| 9143 | 3664937155903505842ULL, // STNT1B_2Z_IMM |
| 9144 | 6198141743891252658ULL, // STNT1B_2Z_STRIDED |
| 9145 | 6342256931967108530ULL, // STNT1B_2Z_STRIDED_IMM |
| 9146 | 75568252889220530ULL, // STNT1B_4Z |
| 9147 | 3671692555344561586ULL, // STNT1B_4Z_IMM |
| 9148 | 75568252889220530ULL, // STNT1B_4Z_STRIDED |
| 9149 | 3671692555344561586ULL, // STNT1B_4Z_STRIDED_IMM |
| 9150 | 3621027059446465970ULL, // STNT1B_ZRI |
| 9151 | 75568252799042994ULL, // STNT1B_ZRR |
| 9152 | 3476911699571934642ULL, // STNT1B_ZZR_D |
| 9153 | 3476911355974583730ULL, // STNT1B_ZZR_S |
| 9154 | 76694152796081023ULL, // STNT1D_2Z |
| 9155 | 3664937155903523711ULL, // STNT1D_2Z_IMM |
| 9156 | 76694152796081023ULL, // STNT1D_2Z_STRIDED |
| 9157 | 3664937155903523711ULL, // STNT1D_2Z_STRIDED_IMM |
| 9158 | 76694152796081023ULL, // STNT1D_4Z |
| 9159 | 3671692555344579455ULL, // STNT1D_4Z_IMM |
| 9160 | 76694152796081023ULL, // STNT1D_4Z_STRIDED |
| 9161 | 3671692555344579455ULL, // STNT1D_4Z_STRIDED_IMM |
| 9162 | 3621027059446483839ULL, // STNT1D_ZRI |
| 9163 | 76694152705903487ULL, // STNT1D_ZRR |
| 9164 | 3476911699571936127ULL, // STNT1D_ZZR_D |
| 9165 | 77820052702940734ULL, // STNT1H_2Z |
| 9166 | 3664937155903540798ULL, // STNT1H_2Z_IMM |
| 9167 | 6486372120043245118ULL, // STNT1H_2Z_STRIDED |
| 9168 | 6342256931967389246ULL, // STNT1H_2Z_STRIDED_IMM |
| 9169 | 77820052702940734ULL, // STNT1H_4Z |
| 9170 | 3671692555344596542ULL, // STNT1H_4Z_IMM |
| 9171 | 77820052702940734ULL, // STNT1H_4Z_STRIDED |
| 9172 | 3671692555344596542ULL, // STNT1H_4Z_STRIDED_IMM |
| 9173 | 3621027059446500926ULL, // STNT1H_ZRI |
| 9174 | 77820052612763198ULL, // STNT1H_ZRR |
| 9175 | 3476911699571936830ULL, // STNT1H_ZZR_D |
| 9176 | 3476911355974585918ULL, // STNT1H_ZZR_S |
| 9177 | 80071852516647918ULL, // STNT1W_2Z |
| 9178 | 3664937155903562734ULL, // STNT1W_2Z_IMM |
| 9179 | 80071852516647918ULL, // STNT1W_2Z_STRIDED |
| 9180 | 3664937155903562734ULL, // STNT1W_2Z_STRIDED_IMM |
| 9181 | 80071852516647918ULL, // STNT1W_4Z |
| 9182 | 3671692555344618478ULL, // STNT1W_4Z_IMM |
| 9183 | 80071852516647918ULL, // STNT1W_4Z_STRIDED |
| 9184 | 3671692555344618478ULL, // STNT1W_4Z_STRIDED_IMM |
| 9185 | 3621027059446522862ULL, // STNT1W_ZRI |
| 9186 | 80071852426470382ULL, // STNT1W_ZRR |
| 9187 | 3476911699571942382ULL, // STNT1W_ZZR_D |
| 9188 | 3476911355974591470ULL, // STNT1W_ZZR_S |
| 9189 | 3748183530763475615ULL, // STPDi |
| 9190 | 4273178347894528671ULL, // STPDpost |
| 9191 | 4180854555533433503ULL, // STPDpre |
| 9192 | 3892298718839331487ULL, // STPQi |
| 9193 | 4417293535970384543ULL, // STPQpost |
| 9194 | 4324969743609289375ULL, // STPQpre |
| 9195 | 4036413906915187359ULL, // STPSi |
| 9196 | 4561408724046240415ULL, // STPSpost |
| 9197 | 4469084931685145247ULL, // STPSpre |
| 9198 | 4036413906915187359ULL, // STPWi |
| 9199 | 4561408724046240415ULL, // STPWpost |
| 9200 | 4469084931685145247ULL, // STPWpre |
| 9201 | 3748183530763475615ULL, // STPXi |
| 9202 | 4273178347894528671ULL, // STPXpost |
| 9203 | 4180854555533433503ULL, // STPXpre |
| 9204 | 389816372218222ULL, // STRBBpost |
| 9205 | 94963037725051246ULL, // STRBBpre |
| 9206 | 4612873903342111086ULL, // STRBBroW |
| 9207 | 4756989091417966958ULL, // STRBBroX |
| 9208 | 668915426412910ULL, // STRBBui |
| 9209 | 389816372223226ULL, // STRBpost |
| 9210 | 94963037725056250ULL, // STRBpre |
| 9211 | 4612873903342116090ULL, // STRBroW |
| 9212 | 4756989091417971962ULL, // STRBroX |
| 9213 | 668915426417914ULL, // STRBui |
| 9214 | 389816372223226ULL, // STRDpost |
| 9215 | 94963037725056250ULL, // STRDpre |
| 9216 | 4901104279493827834ULL, // STRDroW |
| 9217 | 5045219467569683706ULL, // STRDroX |
| 9218 | 677711519440122ULL, // STRDui |
| 9219 | 389816372220041ULL, // STRHHpost |
| 9220 | 94963037725053065ULL, // STRHHpre |
| 9221 | 5189334655645536393ULL, // STRHHroW |
| 9222 | 5333449843721392265ULL, // STRHHroX |
| 9223 | 686507612459145ULL, // STRHHui |
| 9224 | 389816372223226ULL, // STRHpost |
| 9225 | 94963037725056250ULL, // STRHpre |
| 9226 | 5189334655645539578ULL, // STRHroW |
| 9227 | 5333449843721395450ULL, // STRHroX |
| 9228 | 686507612462330ULL, // STRHui |
| 9229 | 389816372223226ULL, // STRQpost |
| 9230 | 94963037725056250ULL, // STRQpre |
| 9231 | 5477565031797251322ULL, // STRQroW |
| 9232 | 5621680219873107194ULL, // STRQroX |
| 9233 | 695303705484538ULL, // STRQui |
| 9234 | 389816372223226ULL, // STRSpost |
| 9235 | 94963037725056250ULL, // STRSpre |
| 9236 | 5765795407948963066ULL, // STRSroW |
| 9237 | 5909910596024818938ULL, // STRSroX |
| 9238 | 704099798506746ULL, // STRSui |
| 9239 | 389816372223226ULL, // STRWpost |
| 9240 | 94963037725056250ULL, // STRWpre |
| 9241 | 5765795407948963066ULL, // STRWroW |
| 9242 | 5909910596024818938ULL, // STRWroX |
| 9243 | 704099798506746ULL, // STRWui |
| 9244 | 389816372223226ULL, // STRXpost |
| 9245 | 94963037725056250ULL, // STRXpre |
| 9246 | 4901104279493827834ULL, // STRXroW |
| 9247 | 5045219467569683706ULL, // STRXroX |
| 9248 | 677711519440122ULL, // STRXui |
| 9249 | 95763477090508026ULL, // STR_PXI |
| 9250 | 2508300770554ULL, // STR_TX |
| 9251 | 1039610ULL, // STR_ZA |
| 9252 | 95763477090508026ULL, // STR_ZXI |
| 9253 | 3892298718839331326ULL, // STTNPQi |
| 9254 | 3748183530763475454ULL, // STTNPXi |
| 9255 | 3892298718839331500ULL, // STTPQi |
| 9256 | 4417293535970384556ULL, // STTPQpost |
| 9257 | 4324969743609289388ULL, // STTPQpre |
| 9258 | 3748183530763475628ULL, // STTPi |
| 9259 | 4273178347894528684ULL, // STTPpost |
| 9260 | 4180854555533433516ULL, // STTPpre |
| 9261 | 29335382585788788ULL, // STTRBi |
| 9262 | 29335382585790607ULL, // STTRHi |
| 9263 | 29335382585793794ULL, // STTRWi |
| 9264 | 29335382585793794ULL, // STTRXi |
| 9265 | 29336138462289272ULL, // STTXRWr |
| 9266 | 29336138462289272ULL, // STTXRXr |
| 9267 | 29335382585788819ULL, // STURBBi |
| 9268 | 29335382585793827ULL, // STURBi |
| 9269 | 29335382585793827ULL, // STURDi |
| 9270 | 29335382585790638ULL, // STURHHi |
| 9271 | 29335382585793827ULL, // STURHi |
| 9272 | 29335382585793827ULL, // STURQi |
| 9273 | 29335382585793827ULL, // STURSi |
| 9274 | 29335382585793827ULL, // STURWi |
| 9275 | 29335382585793827ULL, // STURXi |
| 9276 | 104770676306500338ULL, // STXPW |
| 9277 | 104770676306500338ULL, // STXPX |
| 9278 | 29336138462284209ULL, // STXRB |
| 9279 | 29336138462286028ULL, // STXRH |
| 9280 | 29336138462289266ULL, // STXRW |
| 9281 | 29336138462289266ULL, // STXRX |
| 9282 | 644903069863380ULL, // STZ2GPostIndex |
| 9283 | 95218124422696404ULL, // STZ2GPreIndex |
| 9284 | 29344178678812116ULL, // STZ2Gi |
| 9285 | 2508300769108ULL, // STZGM |
| 9286 | 644903069863443ULL, // STZGPostIndex |
| 9287 | 95218124422696467ULL, // STZGPreIndex |
| 9288 | 29344178678812179ULL, // STZGi |
| 9289 | 1196680969997787ULL, // SUBG |
| 9290 | 97171489720456ULL, // SUBHNB_ZZZ_B |
| 9291 | 18075661437064ULL, // SUBHNB_ZZZ_H |
| 9292 | 44395468507272ULL, // SUBHNB_ZZZ_S |
| 9293 | 105968388055309ULL, // SUBHNT_ZZZ_B |
| 9294 | 517837234445ULL, // SUBHNT_ZZZ_H |
| 9295 | 9210022682893ULL, // SUBHNT_ZZZ_S |
| 9296 | 2366700131555302ULL, // SUBHNv2i64_v2i32 |
| 9297 | 2375498109944235ULL, // SUBHNv2i64_v4i32 |
| 9298 | 3492634402330598ULL, // SUBHNv4i32_v4i16 |
| 9299 | 3501432378622379ULL, // SUBHNv4i32_v8i16 |
| 9300 | 4627366634717611ULL, // SUBHNv8i16_v16i8 |
| 9301 | 4618568675203046ULL, // SUBHNv8i16_v8i8 |
| 9302 | 61984970135854ULL, // SUBP |
| 9303 | 61984970137218ULL, // SUBPS |
| 9304 | 5691484504351179ULL, // SUBPT_shift |
| 9305 | 145276307521968430ULL, // SUBP_ZPmZZ_B |
| 9306 | 289400291690862894ULL, // SUBP_ZPmZZ_D |
| 9307 | 439233043046144302ULL, // SUBP_ZPmZZ_H |
| 9308 | 577639463935629614ULL, // SUBP_ZPmZZ_S |
| 9309 | 167541576080291ULL, // SUBR_ZI_B |
| 9310 | 176336863812515ULL, // SUBR_ZI_D |
| 9311 | 930156190627ULL, // SUBR_ZI_H |
| 9312 | 185134030609315ULL, // SUBR_ZI_S |
| 9313 | 145276307521969059ULL, // SUBR_ZPmZ_B |
| 9314 | 289400291690863523ULL, // SUBR_ZPmZ_D |
| 9315 | 439233043046144931ULL, // SUBR_ZPmZ_H |
| 9316 | 577639463935630243ULL, // SUBR_ZPmZ_S |
| 9317 | 141149807336926ULL, // SUBSWri |
| 9318 | 149945900359134ULL, // SUBSWrs |
| 9319 | 158741993381342ULL, // SUBSWrx |
| 9320 | 141149807336926ULL, // SUBSXri |
| 9321 | 149945900359134ULL, // SUBSXrs |
| 9322 | 158741993381342ULL, // SUBSXrx |
| 9323 | 12446883945405918ULL, // SUBSXrx64 |
| 9324 | 141149807331942ULL, // SUBWri |
| 9325 | 149945900354150ULL, // SUBWrs |
| 9326 | 158741993376358ULL, // SUBWrx |
| 9327 | 141149807331942ULL, // SUBXri |
| 9328 | 149945900354150ULL, // SUBXrs |
| 9329 | 158741993376358ULL, // SUBXrx |
| 9330 | 12446883945400934ULL, // SUBXrx64 |
| 9331 | 13643603335400038ULL, // SUB_VG2_M2Z2Z_D |
| 9332 | 14769537601997414ULL, // SUB_VG2_M2Z2Z_S |
| 9333 | 448240967376652902ULL, // SUB_VG2_M2ZZ_D |
| 9334 | 449366901643250278ULL, // SUB_VG2_M2ZZ_S |
| 9335 | 18455243999846ULL, // SUB_VG2_M2Z_D |
| 9336 | 18489603754598ULL, // SUB_VG2_M2Z_S |
| 9337 | 13643603603835494ULL, // SUB_VG4_M4Z4Z_D |
| 9338 | 14769537870432870ULL, // SUB_VG4_M4Z4Z_S |
| 9339 | 448240967645088358ULL, // SUB_VG4_M4ZZ_D |
| 9340 | 449366901911685734ULL, // SUB_VG4_M4ZZ_S |
| 9341 | 18455512435302ULL, // SUB_VG4_M4Z_D |
| 9342 | 18489872190054ULL, // SUB_VG4_M4Z_S |
| 9343 | 167541576075878ULL, // SUB_ZI_B |
| 9344 | 176336863808102ULL, // SUB_ZI_D |
| 9345 | 930156186214ULL, // SUB_ZI_H |
| 9346 | 185134030604902ULL, // SUB_ZI_S |
| 9347 | 145276307521964646ULL, // SUB_ZPmZ_B |
| 9348 | 289400291690865099ULL, // SUB_ZPmZ_CPA |
| 9349 | 289400291690859110ULL, // SUB_ZPmZ_D |
| 9350 | 439233043046140518ULL, // SUB_ZPmZ_H |
| 9351 | 577639463935625830ULL, // SUB_ZPmZ_S |
| 9352 | 35600180742758ULL, // SUB_ZZZ_B |
| 9353 | 44395468480971ULL, // SUB_ZZZ_CPA |
| 9354 | 44395468474982ULL, // SUB_ZZZ_D |
| 9355 | 17732068248166ULL, // SUB_ZZZ_H |
| 9356 | 53192635271782ULL, // SUB_ZZZ_S |
| 9357 | 7996302742882918ULL, // SUBv16i8 |
| 9358 | 61984970132070ULL, // SUBv1i64 |
| 9359 | 9122237011561062ULL, // SUBv2i32 |
| 9360 | 2366700133648998ULL, // SUBv2i64 |
| 9361 | 10248171282336358ULL, // SUBv4i16 |
| 9362 | 3492634404424294ULL, // SUBv4i32 |
| 9363 | 4618568673102438ULL, // SUBv8i16 |
| 9364 | 11374105555208806ULL, // SUBv8i8 |
| 9365 | 43305472115319198ULL, // SUDOT_VG2_M2ZZI_BToS |
| 9366 | 521275655299486ULL, // SUDOT_VG2_M2ZZ_BToS |
| 9367 | 43305472383754654ULL, // SUDOT_VG4_M4ZZI_BToS |
| 9368 | 521275923734942ULL, // SUDOT_VG4_M4ZZ_BToS |
| 9369 | 370645479285150ULL, // SUDOT_ZZZI |
| 9370 | 44033897742344606ULL, // SUDOTlanev16i8 |
| 9371 | 44034000815268254ULL, // SUDOTlanev8i8 |
| 9372 | 363016348734639ULL, // SUMLALL_MZZI_BtoS |
| 9373 | 43305472153064623ULL, // SUMLALL_VG2_M2ZZI_BtoS |
| 9374 | 521283209237679ULL, // SUMLALL_VG2_M2ZZ_BtoS |
| 9375 | 43305472421500079ULL, // SUMLALL_VG4_M4ZZI_BtoS |
| 9376 | 521283477673135ULL, // SUMLALL_VG4_M4ZZ_BtoS |
| 9377 | 12157305585ULL, // SUMOP4A_M2Z2Z_BToS |
| 9378 | 5958124273ULL, // SUMOP4A_M2Z2Z_HtoD |
| 9379 | 12962611953ULL, // SUMOP4A_M2ZZ_BToS |
| 9380 | 6226559729ULL, // SUMOP4A_M2ZZ_HtoD |
| 9381 | 2407669023473ULL, // SUMOP4A_MZ2Z_BToS |
| 9382 | 1136331440881ULL, // SUMOP4A_MZ2Z_HtoD |
| 9383 | 18797264225009ULL, // SUMOP4A_MZZ_BToS |
| 9384 | 17663365595889ULL, // SUMOP4A_MZZ_HtoD |
| 9385 | 12157312401ULL, // SUMOP4S_M2Z2Z_BToS |
| 9386 | 5958131089ULL, // SUMOP4S_M2Z2Z_HtoD |
| 9387 | 12962618769ULL, // SUMOP4S_M2ZZ_BToS |
| 9388 | 6226566545ULL, // SUMOP4S_M2ZZ_HtoD |
| 9389 | 2407669030289ULL, // SUMOP4S_MZ2Z_BToS |
| 9390 | 1136331447697ULL, // SUMOP4S_MZ2Z_HtoD |
| 9391 | 18797264231825ULL, // SUMOP4S_MZZ_BToS |
| 9392 | 17663365602705ULL, // SUMOP4S_MZZ_HtoD |
| 9393 | 378679217734694ULL, // SUMOPA_MPPZZ_D |
| 9394 | 545804985156646ULL, // SUMOPA_MPPZZ_S |
| 9395 | 378679217741480ULL, // SUMOPS_MPPZZ_D |
| 9396 | 545804985163432ULL, // SUMOPS_MPPZZ_S |
| 9397 | 3760247181ULL, // SUNPKHI_ZZ_D |
| 9398 | 4880142733ULL, // SUNPKHI_ZZ_H |
| 9399 | 2149667213ULL, // SUNPKHI_ZZ_S |
| 9400 | 3760249072ULL, // SUNPKLO_ZZ_D |
| 9401 | 4880144624ULL, // SUNPKLO_ZZ_H |
| 9402 | 2149669104ULL, // SUNPKLO_ZZ_S |
| 9403 | 4855075287ULL, // SUNPK_VG2_2ZZ_D |
| 9404 | 4880257495ULL, // SUNPK_VG2_2ZZ_H |
| 9405 | 4859302359ULL, // SUNPK_VG2_2ZZ_S |
| 9406 | 4867658199ULL, // SUNPK_VG4_4Z2Z_D |
| 9407 | 4861383127ULL, // SUNPK_VG4_4Z2Z_H |
| 9408 | 4865593815ULL, // SUNPK_VG4_4Z2Z_S |
| 9409 | 145276307521965163ULL, // SUQADD_ZPmZ_B |
| 9410 | 289400291690859627ULL, // SUQADD_ZPmZ_D |
| 9411 | 439233043046141035ULL, // SUQADD_ZPmZ_H |
| 9412 | 577639463935626347ULL, // SUQADD_ZPmZ_S |
| 9413 | 175028440171ULL, // SUQADDv16i8 |
| 9414 | 5102685291ULL, // SUQADDv1i16 |
| 9415 | 5102685291ULL, // SUQADDv1i32 |
| 9416 | 5102685291ULL, // SUQADDv1i64 |
| 9417 | 5102685291ULL, // SUQADDv1i8 |
| 9418 | 209390275691ULL, // SUQADDv2i32 |
| 9419 | 243752111211ULL, // SUQADDv2i64 |
| 9420 | 278113946731ULL, // SUQADDv4i16 |
| 9421 | 312475782251ULL, // SUQADDv4i32 |
| 9422 | 346837617771ULL, // SUQADDv8i16 |
| 9423 | 381199453291ULL, // SUQADDv8i8 |
| 9424 | 396249465472029ULL, // SUTMOPA_M2ZZZI_BtoS |
| 9425 | 43305472383754677ULL, // SUVDOT_VG4_M4ZZI_BToS |
| 9426 | 379740ULL, // SVC |
| 9427 | 888468002750833070ULL, // SVDOT_VG2_M2ZZI_HtoS |
| 9428 | 43305472383754670ULL, // SVDOT_VG4_M4ZZI_BtoS |
| 9429 | 888468003019252142ULL, // SVDOT_VG4_M4ZZI_HtoD |
| 9430 | 16108537401ULL, // SWPAB |
| 9431 | 16108539580ULL, // SWPAH |
| 9432 | 16108537681ULL, // SWPALB |
| 9433 | 16108539736ULL, // SWPALH |
| 9434 | 16108540699ULL, // SWPALW |
| 9435 | 16108540699ULL, // SWPALX |
| 9436 | 16108536984ULL, // SWPAW |
| 9437 | 16108536984ULL, // SWPAX |
| 9438 | 16108538134ULL, // SWPB |
| 9439 | 16108539953ULL, // SWPH |
| 9440 | 16108537890ULL, // SWPLB |
| 9441 | 16108539833ULL, // SWPLH |
| 9442 | 16108541441ULL, // SWPLW |
| 9443 | 16108541441ULL, // SWPLX |
| 9444 | 634502232627736ULL, // SWPP |
| 9445 | 634502232622130ULL, // SWPPA |
| 9446 | 634502232625835ULL, // SWPPAL |
| 9447 | 634502232626579ULL, // SWPPL |
| 9448 | 16108540826ULL, // SWPTALW |
| 9449 | 16108540826ULL, // SWPTALX |
| 9450 | 16108537139ULL, // SWPTAW |
| 9451 | 16108537139ULL, // SWPTAX |
| 9452 | 16108541598ULL, // SWPTLW |
| 9453 | 16108541598ULL, // SWPTLX |
| 9454 | 16108544488ULL, // SWPTW |
| 9455 | 16108544488ULL, // SWPTX |
| 9456 | 16108542652ULL, // SWPW |
| 9457 | 16108542652ULL, // SWPX |
| 9458 | 8830723344984ULL, // SXTB_ZPmZ_D |
| 9459 | 17661446654552ULL, // SXTB_ZPmZ_H |
| 9460 | 26422909422168ULL, // SXTB_ZPmZ_S |
| 9461 | 44084351781464ULL, // SXTB_ZPzZ_D |
| 9462 | 17730705099352ULL, // SXTB_ZPzZ_H |
| 9463 | 52880444836440ULL, // SXTB_ZPzZ_S |
| 9464 | 8830723346748ULL, // SXTH_ZPmZ_D |
| 9465 | 26422909423932ULL, // SXTH_ZPmZ_S |
| 9466 | 44084351783228ULL, // SXTH_ZPzZ_D |
| 9467 | 52880444838204ULL, // SXTH_ZPzZ_S |
| 9468 | 8830723351787ULL, // SXTW_ZPmZ_D |
| 9469 | 44084351788267ULL, // SXTW_ZPzZ_D |
| 9470 | 844837249111668ULL, // SYSLxt |
| 9471 | 4388116519528ULL, // SYSPxt |
| 9472 | 4422476257896ULL, // SYSPxt_XZR |
| 9473 | 4456835997414ULL, // SYSxt |
| 9474 | 800476666720ULL, // TBLQ_ZZZ_B |
| 9475 | 44403789978464ULL, // TBLQ_ZZZ_D |
| 9476 | 17732074543968ULL, // TBLQ_ZZZ_H |
| 9477 | 53199346162528ULL, // TBLQ_ZZZ_S |
| 9478 | 800476664779ULL, // TBL_ZZZZ_B |
| 9479 | 44403789976523ULL, // TBL_ZZZZ_D |
| 9480 | 17732074542027ULL, // TBL_ZZZZ_H |
| 9481 | 53199346160587ULL, // TBL_ZZZZ_S |
| 9482 | 800476664779ULL, // TBL_ZZZ_B |
| 9483 | 44403789976523ULL, // TBL_ZZZ_D |
| 9484 | 17732074542027ULL, // TBL_ZZZ_H |
| 9485 | 53199346160587ULL, // TBL_ZZZ_S |
| 9486 | 188181746635ULL, // TBLv16i8Four |
| 9487 | 188181746635ULL, // TBLv16i8One |
| 9488 | 188181746635ULL, // TBLv16i8Three |
| 9489 | 188181746635ULL, // TBLv16i8Two |
| 9490 | 394352759755ULL, // TBLv8i8Four |
| 9491 | 394352759755ULL, // TBLv8i8One |
| 9492 | 394352759755ULL, // TBLv8i8Three |
| 9493 | 394352759755ULL, // TBLv8i8Two |
| 9494 | 405032598005240ULL, // TBNZW |
| 9495 | 405032598005240ULL, // TBNZX |
| 9496 | 18801758346098ULL, // TBXQ_ZZZ_B |
| 9497 | 9210022648690ULL, // TBXQ_ZZZ_D |
| 9498 | 17663365553010ULL, // TBXQ_ZZZ_H |
| 9499 | 26802477161330ULL, // TBXQ_ZZZ_S |
| 9500 | 18801758348632ULL, // TBX_ZZZ_B |
| 9501 | 9210022651224ULL, // TBX_ZZZ_D |
| 9502 | 17663365555544ULL, // TBX_ZZZ_H |
| 9503 | 26802477163864ULL, // TBX_ZZZ_S |
| 9504 | 196503283032ULL, // TBXv16i8Four |
| 9505 | 196503283032ULL, // TBXv16i8One |
| 9506 | 196503283032ULL, // TBXv16i8Three |
| 9507 | 196503283032ULL, // TBXv16i8Two |
| 9508 | 402674296152ULL, // TBXv8i8Four |
| 9509 | 402674296152ULL, // TBXv8i8One |
| 9510 | 402674296152ULL, // TBXv8i8Three |
| 9511 | 402674296152ULL, // TBXv8i8Two |
| 9512 | 405032598005224ULL, // TBZW |
| 9513 | 405032598005224ULL, // TBZX |
| 9514 | 853652401047251ULL, // TCHANGEBri |
| 9515 | 853633342129875ULL, // TCHANGEBrr |
| 9516 | 853652401049003ULL, // TCHANGEFri |
| 9517 | 853633342131627ULL, // TCHANGEFrr |
| 9518 | 24967109635ULL, // TENTER |
| 9519 | 1269694ULL, // TEXIT |
| 9520 | 61984970139134ULL, // TFLTNZ |
| 9521 | 61984970139147ULL, // TFLTZ |
| 9522 | 35600180740158ULL, // TRN1_PPP_B |
| 9523 | 44395468472382ULL, // TRN1_PPP_D |
| 9524 | 17732068245566ULL, // TRN1_PPP_H |
| 9525 | 53192635269182ULL, // TRN1_PPP_S |
| 9526 | 35600180740158ULL, // TRN1_ZZZ_B |
| 9527 | 44395468472382ULL, // TRN1_ZZZ_D |
| 9528 | 17732068245566ULL, // TRN1_ZZZ_H |
| 9529 | 18556735930430ULL, // TRN1_ZZZ_Q |
| 9530 | 53192635269182ULL, // TRN1_ZZZ_S |
| 9531 | 7996302742880318ULL, // TRN1v16i8 |
| 9532 | 9122237011558462ULL, // TRN1v2i32 |
| 9533 | 2366700133646398ULL, // TRN1v2i64 |
| 9534 | 10248171282333758ULL, // TRN1v4i16 |
| 9535 | 3492634404421694ULL, // TRN1v4i32 |
| 9536 | 4618568673099838ULL, // TRN1v8i16 |
| 9537 | 11374105555206206ULL, // TRN1v8i8 |
| 9538 | 35600180740578ULL, // TRN2_PPP_B |
| 9539 | 44395468472802ULL, // TRN2_PPP_D |
| 9540 | 17732068245986ULL, // TRN2_PPP_H |
| 9541 | 53192635269602ULL, // TRN2_PPP_S |
| 9542 | 35600180740578ULL, // TRN2_ZZZ_B |
| 9543 | 44395468472802ULL, // TRN2_ZZZ_D |
| 9544 | 17732068245986ULL, // TRN2_ZZZ_H |
| 9545 | 18556735930850ULL, // TRN2_ZZZ_Q |
| 9546 | 53192635269602ULL, // TRN2_ZZZ_S |
| 9547 | 7996302742880738ULL, // TRN2v16i8 |
| 9548 | 9122237011558882ULL, // TRN2v2i32 |
| 9549 | 2366700133646818ULL, // TRN2v2i64 |
| 9550 | 10248171282334178ULL, // TRN2v4i16 |
| 9551 | 3492634404422114ULL, // TRN2v4i32 |
| 9552 | 4618568673100258ULL, // TRN2v8i16 |
| 9553 | 11374105555206626ULL, // TRN2v8i8 |
| 9554 | 26802477123334ULL, // UABALB_ZZZ_D |
| 9555 | 18797264176902ULL, // UABALB_ZZZ_H |
| 9556 | 105968388097798ULL, // UABALB_ZZZ_S |
| 9557 | 26802477129677ULL, // UABALT_ZZZ_D |
| 9558 | 18797264183245ULL, // UABALT_ZZZ_H |
| 9559 | 105968388104141ULL, // UABALT_ZZZ_S |
| 9560 | 18797264179703ULL, // UABAL_ZZZ_BtoH |
| 9561 | 105968388100599ULL, // UABAL_ZZZ_HtoS |
| 9562 | 26802477126135ULL, // UABAL_ZZZ_StoD |
| 9563 | 8005100725469408ULL, // UABALv16i8_v8i16 |
| 9564 | 9131034985763319ULL, // UABALv2i32_v2i64 |
| 9565 | 10256969256538615ULL, // UABALv4i16_v4i32 |
| 9566 | 3501432372330720ULL, // UABALv4i32_v2i64 |
| 9567 | 4627366643106016ULL, // UABALv8i16_v4i32 |
| 9568 | 11382903525216759ULL, // UABALv8i8_v8i16 |
| 9569 | 18801758339860ULL, // UABA_ZZZ_B |
| 9570 | 9210022642452ULL, // UABA_ZZZ_D |
| 9571 | 17663365546772ULL, // UABA_ZZZ_H |
| 9572 | 26802477155092ULL, // UABA_ZZZ_S |
| 9573 | 8005100714984212ULL, // UABAv16i8 |
| 9574 | 9131034983662356ULL, // UABAv2i32 |
| 9575 | 10256969254437652ULL, // UABAv4i16 |
| 9576 | 3501432376525588ULL, // UABAv4i32 |
| 9577 | 4627366645203732ULL, // UABAv8i16 |
| 9578 | 11382903527310100ULL, // UABAv8i8 |
| 9579 | 53192635238331ULL, // UABDLB_ZZZ_D |
| 9580 | 792738203579ULL, // UABDLB_ZZZ_H |
| 9581 | 97171489769403ULL, // UABDLB_ZZZ_S |
| 9582 | 53192635244597ULL, // UABDLT_ZZZ_D |
| 9583 | 792738209845ULL, // UABDLT_ZZZ_H |
| 9584 | 97171489775669ULL, // UABDLT_ZZZ_S |
| 9585 | 7996302753366306ULL, // UABDLv16i8_v8i16 |
| 9586 | 9122237013660661ULL, // UABDLv2i32_v2i64 |
| 9587 | 10248171284435957ULL, // UABDLv4i16_v4i32 |
| 9588 | 3492634400227618ULL, // UABDLv4i32_v2i64 |
| 9589 | 4618568671002914ULL, // UABDLv8i16_v4i32 |
| 9590 | 11374105553114101ULL, // UABDLv8i8_v8i16 |
| 9591 | 145276307521965009ULL, // UABD_ZPmZ_B |
| 9592 | 289400291690859473ULL, // UABD_ZPmZ_D |
| 9593 | 439233043046140881ULL, // UABD_ZPmZ_H |
| 9594 | 577639463935626193ULL, // UABD_ZPmZ_S |
| 9595 | 7996302742883281ULL, // UABDv16i8 |
| 9596 | 9122237011561425ULL, // UABDv2i32 |
| 9597 | 10248171282336721ULL, // UABDv4i16 |
| 9598 | 3492634404424657ULL, // UABDv4i32 |
| 9599 | 4618568673102801ULL, // UABDv8i16 |
| 9600 | 11374105555209169ULL, // UABDv8i8 |
| 9601 | 26423446264185ULL, // UADALP_ZPmZ_D |
| 9602 | 18795320121721ULL, // UADALP_ZPmZ_H |
| 9603 | 105588283496825ULL, // UADALP_ZPmZ_S |
| 9604 | 175038929273ULL, // UADALPv16i8_v8i16 |
| 9605 | 209553856889ULL, // UADALPv2i32_v1i64 |
| 9606 | 278109755769ULL, // UADALPv4i16_v2i32 |
| 9607 | 312471591289ULL, // UADALPv4i32_v2i64 |
| 9608 | 346835523961ULL, // UADALPv8i16_v4i32 |
| 9609 | 381193165177ULL, // UADALPv8i8_v4i16 |
| 9610 | 53192635238356ULL, // UADDLB_ZZZ_D |
| 9611 | 792738203604ULL, // UADDLB_ZZZ_H |
| 9612 | 97171489769428ULL, // UADDLB_ZZZ_S |
| 9613 | 173159848329ULL, // UADDLPv16i8_v8i16 |
| 9614 | 207674775945ULL, // UADDLPv2i32_v1i64 |
| 9615 | 276230674825ULL, // UADDLPv4i16_v2i32 |
| 9616 | 310592510345ULL, // UADDLPv4i32_v2i64 |
| 9617 | 344956443017ULL, // UADDLPv8i16_v4i32 |
| 9618 | 379314084233ULL, // UADDLPv8i8_v4i16 |
| 9619 | 53192635244613ULL, // UADDLT_ZZZ_D |
| 9620 | 792738209861ULL, // UADDLT_ZZZ_H |
| 9621 | 97171489775685ULL, // UADDLT_ZZZ_S |
| 9622 | 173142991629ULL, // UADDLVv16i8v |
| 9623 | 276222206733ULL, // UADDLVv4i16v |
| 9624 | 310581945101ULL, // UADDLVv4i32v |
| 9625 | 344941683469ULL, // UADDLVv8i16v |
| 9626 | 379301421837ULL, // UADDLVv8i8v |
| 9627 | 7996302753366322ULL, // UADDLv16i8_v8i16 |
| 9628 | 9122237013660746ULL, // UADDLv2i32_v2i64 |
| 9629 | 10248171284436042ULL, // UADDLv4i16_v4i32 |
| 9630 | 3492634400227634ULL, // UADDLv4i32_v2i64 |
| 9631 | 4618568671002930ULL, // UADDLv8i16_v4i32 |
| 9632 | 11374105553114186ULL, // UADDLv8i8_v8i16 |
| 9633 | 4903412449ULL, // UADDV_VPZ_B |
| 9634 | 4874052321ULL, // UADDV_VPZ_D |
| 9635 | 4876149473ULL, // UADDV_VPZ_H |
| 9636 | 4857275105ULL, // UADDV_VPZ_S |
| 9637 | 53191561497268ULL, // UADDWB_ZZZ_D |
| 9638 | 792717232820ULL, // UADDWB_ZZZ_H |
| 9639 | 97173100382900ULL, // UADDWB_ZZZ_S |
| 9640 | 53191561503334ULL, // UADDWT_ZZZ_D |
| 9641 | 792717238886ULL, // UADDWT_ZZZ_H |
| 9642 | 97173100388966ULL, // UADDWT_ZZZ_S |
| 9643 | 7996268393628270ULL, // UADDWv16i8_v8i16 |
| 9644 | 9122099574711398ULL, // UADDWv2i32_v2i64 |
| 9645 | 10248033845486694ULL, // UADDWv4i16_v4i32 |
| 9646 | 3492600040489582ULL, // UADDWv4i32_v2i64 |
| 9647 | 4618534311264878ULL, // UADDWv8i16_v4i32 |
| 9648 | 11373968114164838ULL, // UADDWv8i8_v8i16 |
| 9649 | 1187884876977979ULL, // UBFMWri |
| 9650 | 1187884876977979ULL, // UBFMXri |
| 9651 | 18797264263599ULL, // UCLAMP_VG2_2Z2Z_B |
| 9652 | 2029682596271ULL, // UCLAMP_VG2_2Z2Z_D |
| 9653 | 17663365667247ULL, // UCLAMP_VG2_2Z2Z_H |
| 9654 | 517837363631ULL, // UCLAMP_VG2_2Z2Z_S |
| 9655 | 18797264263599ULL, // UCLAMP_VG4_4Z4Z_B |
| 9656 | 2029682596271ULL, // UCLAMP_VG4_4Z4Z_D |
| 9657 | 17663365667247ULL, // UCLAMP_VG4_4Z4Z_H |
| 9658 | 517837363631ULL, // UCLAMP_VG4_4Z4Z_S |
| 9659 | 18801758345647ULL, // UCLAMP_ZZZ_B |
| 9660 | 9210022648239ULL, // UCLAMP_ZZZ_D |
| 9661 | 17663365552559ULL, // UCLAMP_ZZZ_H |
| 9662 | 26802477160879ULL, // UCLAMP_ZZZ_S |
| 9663 | 2117063ULL, // UCVTFDSr |
| 9664 | 2117063ULL, // UCVTFHDr |
| 9665 | 2117063ULL, // UCVTFHSr |
| 9666 | 4880146527ULL, // UCVTFLT_ZZ_BtoH |
| 9667 | 2149671007ULL, // UCVTFLT_ZZ_HtoS |
| 9668 | 3760250975ULL, // UCVTFLT_ZZ_StoD |
| 9669 | 2117063ULL, // UCVTFSDr |
| 9670 | 61984970132935ULL, // UCVTFSWDri |
| 9671 | 61984970132935ULL, // UCVTFSWHri |
| 9672 | 61984970132935ULL, // UCVTFSWSri |
| 9673 | 61984970132935ULL, // UCVTFSXDri |
| 9674 | 61984970132935ULL, // UCVTFSXHri |
| 9675 | 61984970132935ULL, // UCVTFSXSri |
| 9676 | 2117063ULL, // UCVTFUWDri |
| 9677 | 2117063ULL, // UCVTFUWHri |
| 9678 | 2117063ULL, // UCVTFUWSri |
| 9679 | 2117063ULL, // UCVTFUXDri |
| 9680 | 2117063ULL, // UCVTFUXHri |
| 9681 | 2117063ULL, // UCVTFUXSri |
| 9682 | 4867689927ULL, // UCVTF_2Z2Z_StoS |
| 9683 | 4867689927ULL, // UCVTF_4Z4Z_StoS |
| 9684 | 8830723345863ULL, // UCVTF_ZPmZ_DtoD |
| 9685 | 2027765697991ULL, // UCVTF_ZPmZ_DtoH |
| 9686 | 8830723378631ULL, // UCVTF_ZPmZ_DtoS |
| 9687 | 17661446655431ULL, // UCVTF_ZPmZ_HtoH |
| 9688 | 26422909390279ULL, // UCVTF_ZPmZ_StoD |
| 9689 | 515937209799ULL, // UCVTF_ZPmZ_StoH |
| 9690 | 26422909423047ULL, // UCVTF_ZPmZ_StoS |
| 9691 | 44084351782343ULL, // UCVTF_ZPzZ_DtoD |
| 9692 | 18417899867591ULL, // UCVTF_ZPzZ_DtoH |
| 9693 | 44084351815111ULL, // UCVTF_ZPzZ_DtoS |
| 9694 | 17730705100231ULL, // UCVTF_ZPzZ_HtoH |
| 9695 | 52880444804551ULL, // UCVTF_ZPzZ_StoD |
| 9696 | 18074302483911ULL, // UCVTF_ZPzZ_StoH |
| 9697 | 52880444837319ULL, // UCVTF_ZPzZ_StoS |
| 9698 | 4880141767ULL, // UCVTF_ZZ_BtoH |
| 9699 | 2149666247ULL, // UCVTF_ZZ_HtoS |
| 9700 | 3760246215ULL, // UCVTF_ZZ_StoD |
| 9701 | 61984970132935ULL, // UCVTFd |
| 9702 | 61984970132935ULL, // UCVTFh |
| 9703 | 61984970132935ULL, // UCVTFs |
| 9704 | 2117063ULL, // UCVTFv1i16 |
| 9705 | 2117063ULL, // UCVTFv1i32 |
| 9706 | 2117063ULL, // UCVTFv1i64 |
| 9707 | 207511195079ULL, // UCVTFv2f32 |
| 9708 | 241873030599ULL, // UCVTFv2f64 |
| 9709 | 62261198687687ULL, // UCVTFv2i32_shift |
| 9710 | 62123761831367ULL, // UCVTFv2i64_shift |
| 9711 | 276234866119ULL, // UCVTFv4f16 |
| 9712 | 310596701639ULL, // UCVTFv4f32 |
| 9713 | 62295562620359ULL, // UCVTFv4i16_shift |
| 9714 | 62158125764039ULL, // UCVTFv4i32_shift |
| 9715 | 344958537159ULL, // UCVTFv8f16 |
| 9716 | 62192487599559ULL, // UCVTFv8i16_shift |
| 9717 | 19878ULL, // UDF |
| 9718 | 289400291690863927ULL, // UDIVR_ZPmZ_D |
| 9719 | 577639463935630647ULL, // UDIVR_ZPmZ_S |
| 9720 | 61984970138367ULL, // UDIVWr |
| 9721 | 61984970138367ULL, // UDIVXr |
| 9722 | 289400291690865407ULL, // UDIV_ZPmZ_D |
| 9723 | 577639463935632127ULL, // UDIV_ZPmZ_S |
| 9724 | 512479562277279ULL, // UDOT_VG2_M2Z2Z_BtoS |
| 9725 | 22650974388838815ULL, // UDOT_VG2_M2Z2Z_HtoD |
| 9726 | 22650974388855199ULL, // UDOT_VG2_M2Z2Z_HtoS |
| 9727 | 43305472115319199ULL, // UDOT_VG2_M2ZZI_BToS |
| 9728 | 888468002750833055ULL, // UDOT_VG2_M2ZZI_HToS |
| 9729 | 888468002750816671ULL, // UDOT_VG2_M2ZZI_HtoD |
| 9730 | 521275655299487ULL, // UDOT_VG2_M2ZZ_BtoS |
| 9731 | 456122438523249055ULL, // UDOT_VG2_M2ZZ_HtoD |
| 9732 | 456122438523265439ULL, // UDOT_VG2_M2ZZ_HtoS |
| 9733 | 512479830712735ULL, // UDOT_VG4_M4Z4Z_BtoS |
| 9734 | 22650974657274271ULL, // UDOT_VG4_M4Z4Z_HtoD |
| 9735 | 22650974657290655ULL, // UDOT_VG4_M4Z4Z_HtoS |
| 9736 | 43305472383754655ULL, // UDOT_VG4_M4ZZI_BtoS |
| 9737 | 888468003019268511ULL, // UDOT_VG4_M4ZZI_HToS |
| 9738 | 888468003019252127ULL, // UDOT_VG4_M4ZZI_HtoD |
| 9739 | 521275923734943ULL, // UDOT_VG4_M4ZZ_BtoS |
| 9740 | 456122438791684511ULL, // UDOT_VG4_M4ZZ_HtoD |
| 9741 | 456122438791700895ULL, // UDOT_VG4_M4ZZ_HtoS |
| 9742 | 370640985072031ULL, // UDOT_ZZZI_BtoH |
| 9743 | 370645479285151ULL, // UDOT_ZZZI_BtoS |
| 9744 | 457221330566177183ULL, // UDOT_ZZZI_HtoD |
| 9745 | 457221330566209951ULL, // UDOT_ZZZI_HtoS |
| 9746 | 18797264183711ULL, // UDOT_ZZZ_BtoH |
| 9747 | 18801758396831ULL, // UDOT_ZZZ_BtoS |
| 9748 | 105968388071839ULL, // UDOT_ZZZ_HtoD |
| 9749 | 105968388104607ULL, // UDOT_ZZZ_HtoS |
| 9750 | 44033897742344607ULL, // UDOTlanev16i8 |
| 9751 | 44034000815268255ULL, // UDOTlanev8i8 |
| 9752 | 8005100723380639ULL, // UDOTv16i8 |
| 9753 | 11382903516832159ULL, // UDOTv8i8 |
| 9754 | 145276307521965133ULL, // UHADD_ZPmZ_B |
| 9755 | 289400291690859597ULL, // UHADD_ZPmZ_D |
| 9756 | 439233043046141005ULL, // UHADD_ZPmZ_H |
| 9757 | 577639463935626317ULL, // UHADD_ZPmZ_S |
| 9758 | 7996302742883405ULL, // UHADDv16i8 |
| 9759 | 9122237011561549ULL, // UHADDv2i32 |
| 9760 | 10248171282336845ULL, // UHADDv4i16 |
| 9761 | 3492634404424781ULL, // UHADDv4i32 |
| 9762 | 4618568673102925ULL, // UHADDv8i16 |
| 9763 | 11374105555209293ULL, // UHADDv8i8 |
| 9764 | 145276307521969073ULL, // UHSUBR_ZPmZ_B |
| 9765 | 289400291690863537ULL, // UHSUBR_ZPmZ_D |
| 9766 | 439233043046144945ULL, // UHSUBR_ZPmZ_H |
| 9767 | 577639463935630257ULL, // UHSUBR_ZPmZ_S |
| 9768 | 145276307521964658ULL, // UHSUB_ZPmZ_B |
| 9769 | 289400291690859122ULL, // UHSUB_ZPmZ_D |
| 9770 | 439233043046140530ULL, // UHSUB_ZPmZ_H |
| 9771 | 577639463935625842ULL, // UHSUB_ZPmZ_S |
| 9772 | 7996302742882930ULL, // UHSUBv16i8 |
| 9773 | 9122237011561074ULL, // UHSUBv2i32 |
| 9774 | 10248171282336370ULL, // UHSUBv4i16 |
| 9775 | 3492634404424306ULL, // UHSUBv4i32 |
| 9776 | 4618568673102450ULL, // UHSUBv8i16 |
| 9777 | 11374105555208818ULL, // UHSUBv8i8 |
| 9778 | 1187884876977202ULL, // UMADDLrrr |
| 9779 | 145276307521968862ULL, // UMAXP_ZPmZ_B |
| 9780 | 289400291690863326ULL, // UMAXP_ZPmZ_D |
| 9781 | 439233043046144734ULL, // UMAXP_ZPmZ_H |
| 9782 | 577639463935630046ULL, // UMAXP_ZPmZ_S |
| 9783 | 7996302742887134ULL, // UMAXPv16i8 |
| 9784 | 9122237011565278ULL, // UMAXPv2i32 |
| 9785 | 10248171282340574ULL, // UMAXPv4i16 |
| 9786 | 3492634404428510ULL, // UMAXPv4i32 |
| 9787 | 4618568673106654ULL, // UMAXPv8i16 |
| 9788 | 11374105555213022ULL, // UMAXPv8i8 |
| 9789 | 35597502751661ULL, // UMAXQV_VPZ_B |
| 9790 | 44393599968173ULL, // UMAXQV_VPZ_D |
| 9791 | 97170164392877ULL, // UMAXQV_VPZ_H |
| 9792 | 53189697184685ULL, // UMAXQV_VPZ_S |
| 9793 | 254921ULL, // UMAXV_VPZ_B |
| 9794 | 4874052553ULL, // UMAXV_VPZ_D |
| 9795 | 4876166089ULL, // UMAXV_VPZ_H |
| 9796 | 4857308105ULL, // UMAXV_VPZ_S |
| 9797 | 173142991817ULL, // UMAXVv16i8v |
| 9798 | 276222206921ULL, // UMAXVv4i16v |
| 9799 | 310581945289ULL, // UMAXVv4i32v |
| 9800 | 344941683657ULL, // UMAXVv8i16v |
| 9801 | 379301422025ULL, // UMAXVv8i8v |
| 9802 | 61984970138962ULL, // UMAXWri |
| 9803 | 61984970138962ULL, // UMAXWrr |
| 9804 | 61984970138962ULL, // UMAXXri |
| 9805 | 61984970138962ULL, // UMAXXrr |
| 9806 | 21649080608082ULL, // UMAX_VG2_2Z2Z_B |
| 9807 | 19553138681170ULL, // UMAX_VG2_2Z2Z_D |
| 9808 | 18659787597138ULL, // UMAX_VG2_2Z2Z_H |
| 9809 | 19587502646610ULL, // UMAX_VG2_2Z2Z_S |
| 9810 | 792719418706ULL, // UMAX_VG2_2ZZ_B |
| 9811 | 18419267315026ULL, // UMAX_VG2_2ZZ_D |
| 9812 | 17732074661202ULL, // UMAX_VG2_2ZZ_H |
| 9813 | 18075674158418ULL, // UMAX_VG2_2ZZ_S |
| 9814 | 21649080608082ULL, // UMAX_VG4_4Z4Z_B |
| 9815 | 19553138681170ULL, // UMAX_VG4_4Z4Z_D |
| 9816 | 18659787597138ULL, // UMAX_VG4_4Z4Z_H |
| 9817 | 19587502646610ULL, // UMAX_VG4_4Z4Z_S |
| 9818 | 792719418706ULL, // UMAX_VG4_4ZZ_B |
| 9819 | 18419267315026ULL, // UMAX_VG4_4ZZ_D |
| 9820 | 17732074661202ULL, // UMAX_VG4_4ZZ_H |
| 9821 | 18075674158418ULL, // UMAX_VG4_4ZZ_S |
| 9822 | 862432924837202ULL, // UMAX_ZI_B |
| 9823 | 862432119547218ULL, // UMAX_ZI_D |
| 9824 | 1892228867410ULL, // UMAX_ZI_H |
| 9825 | 862433193321810ULL, // UMAX_ZI_S |
| 9826 | 145276307521971538ULL, // UMAX_ZPmZ_B |
| 9827 | 289400291690866002ULL, // UMAX_ZPmZ_D |
| 9828 | 439233043046147410ULL, // UMAX_ZPmZ_H |
| 9829 | 577639463935632722ULL, // UMAX_ZPmZ_S |
| 9830 | 7996302742889810ULL, // UMAXv16i8 |
| 9831 | 9122237011567954ULL, // UMAXv2i32 |
| 9832 | 10248171282343250ULL, // UMAXv4i16 |
| 9833 | 3492634404431186ULL, // UMAXv4i32 |
| 9834 | 4618568673109330ULL, // UMAXv8i16 |
| 9835 | 11374105555215698ULL, // UMAXv8i8 |
| 9836 | 145276307521968618ULL, // UMINP_ZPmZ_B |
| 9837 | 289400291690863082ULL, // UMINP_ZPmZ_D |
| 9838 | 439233043046144490ULL, // UMINP_ZPmZ_H |
| 9839 | 577639463935629802ULL, // UMINP_ZPmZ_S |
| 9840 | 7996302742886890ULL, // UMINPv16i8 |
| 9841 | 9122237011565034ULL, // UMINPv2i32 |
| 9842 | 10248171282340330ULL, // UMINPv4i16 |
| 9843 | 3492634404428266ULL, // UMINPv4i32 |
| 9844 | 4618568673106410ULL, // UMINPv8i16 |
| 9845 | 11374105555212778ULL, // UMINPv8i8 |
| 9846 | 35597502751630ULL, // UMINQV_VPZ_B |
| 9847 | 44393599968142ULL, // UMINQV_VPZ_D |
| 9848 | 97170164392846ULL, // UMINQV_VPZ_H |
| 9849 | 53189697184654ULL, // UMINQV_VPZ_S |
| 9850 | 254773ULL, // UMINV_VPZ_B |
| 9851 | 4874052405ULL, // UMINV_VPZ_D |
| 9852 | 4876165941ULL, // UMINV_VPZ_H |
| 9853 | 4857307957ULL, // UMINV_VPZ_S |
| 9854 | 173142991669ULL, // UMINVv16i8v |
| 9855 | 276222206773ULL, // UMINVv4i16v |
| 9856 | 310581945141ULL, // UMINVv4i32v |
| 9857 | 344941683509ULL, // UMINVv8i16v |
| 9858 | 379301421877ULL, // UMINVv8i8v |
| 9859 | 61984970135592ULL, // UMINWri |
| 9860 | 61984970135592ULL, // UMINWrr |
| 9861 | 61984970135592ULL, // UMINXri |
| 9862 | 61984970135592ULL, // UMINXrr |
| 9863 | 21649080604712ULL, // UMIN_VG2_2Z2Z_B |
| 9864 | 19553138677800ULL, // UMIN_VG2_2Z2Z_D |
| 9865 | 18659787593768ULL, // UMIN_VG2_2Z2Z_H |
| 9866 | 19587502643240ULL, // UMIN_VG2_2Z2Z_S |
| 9867 | 792719415336ULL, // UMIN_VG2_2ZZ_B |
| 9868 | 18419267311656ULL, // UMIN_VG2_2ZZ_D |
| 9869 | 17732074657832ULL, // UMIN_VG2_2ZZ_H |
| 9870 | 18075674155048ULL, // UMIN_VG2_2ZZ_S |
| 9871 | 21649080604712ULL, // UMIN_VG4_4Z4Z_B |
| 9872 | 19553138677800ULL, // UMIN_VG4_4Z4Z_D |
| 9873 | 18659787593768ULL, // UMIN_VG4_4Z4Z_H |
| 9874 | 19587502643240ULL, // UMIN_VG4_4Z4Z_S |
| 9875 | 792719415336ULL, // UMIN_VG4_4ZZ_B |
| 9876 | 18419267311656ULL, // UMIN_VG4_4ZZ_D |
| 9877 | 17732074657832ULL, // UMIN_VG4_4ZZ_H |
| 9878 | 18075674155048ULL, // UMIN_VG4_4ZZ_S |
| 9879 | 862432924833832ULL, // UMIN_ZI_B |
| 9880 | 862432119543848ULL, // UMIN_ZI_D |
| 9881 | 1892228864040ULL, // UMIN_ZI_H |
| 9882 | 862433193318440ULL, // UMIN_ZI_S |
| 9883 | 145276307521968168ULL, // UMIN_ZPmZ_B |
| 9884 | 289400291690862632ULL, // UMIN_ZPmZ_D |
| 9885 | 439233043046144040ULL, // UMIN_ZPmZ_H |
| 9886 | 577639463935629352ULL, // UMIN_ZPmZ_S |
| 9887 | 7996302742886440ULL, // UMINv16i8 |
| 9888 | 9122237011564584ULL, // UMINv2i32 |
| 9889 | 10248171282339880ULL, // UMINv4i16 |
| 9890 | 3492634404427816ULL, // UMINv4i32 |
| 9891 | 4618568673105960ULL, // UMINv8i16 |
| 9892 | 11374105555212328ULL, // UMINv8i8 |
| 9893 | 457142164655228723ULL, // UMLALB_ZZZI_D |
| 9894 | 457221330566203187ULL, // UMLALB_ZZZI_S |
| 9895 | 26802477123379ULL, // UMLALB_ZZZ_D |
| 9896 | 18797264176947ULL, // UMLALB_ZZZ_H |
| 9897 | 105968388097843ULL, // UMLALB_ZZZ_S |
| 9898 | 363016348734640ULL, // UMLALL_MZZI_BtoS |
| 9899 | 361745038398640ULL, // UMLALL_MZZI_HtoD |
| 9900 | 19968720868528ULL, // UMLALL_MZZ_BtoS |
| 9901 | 18697410532528ULL, // UMLALL_MZZ_HtoD |
| 9902 | 512479600022704ULL, // UMLALL_VG2_M2Z2Z_BtoS |
| 9903 | 22650974426584240ULL, // UMLALL_VG2_M2Z2Z_HtoD |
| 9904 | 43305472153064624ULL, // UMLALL_VG2_M2ZZI_BtoS |
| 9905 | 888468002788562096ULL, // UMLALL_VG2_M2ZZI_HtoD |
| 9906 | 521283209237680ULL, // UMLALL_VG2_M2ZZ_BtoS |
| 9907 | 456122446077187248ULL, // UMLALL_VG2_M2ZZ_HtoD |
| 9908 | 512479868458160ULL, // UMLALL_VG4_M4Z4Z_BtoS |
| 9909 | 22650974695019696ULL, // UMLALL_VG4_M4Z4Z_HtoD |
| 9910 | 43305472421500080ULL, // UMLALL_VG4_M4ZZI_BtoS |
| 9911 | 888468003056997552ULL, // UMLALL_VG4_M4ZZI_HtoD |
| 9912 | 521283477673136ULL, // UMLALL_VG4_M4ZZ_BtoS |
| 9913 | 456122446345622704ULL, // UMLALL_VG4_M4ZZ_HtoD |
| 9914 | 457142164655235056ULL, // UMLALT_ZZZI_D |
| 9915 | 457221330566209520ULL, // UMLALT_ZZZI_S |
| 9916 | 26802477129712ULL, // UMLALT_ZZZ_D |
| 9917 | 18797264183280ULL, // UMLALT_ZZZ_H |
| 9918 | 105968388104176ULL, // UMLALT_ZZZ_S |
| 9919 | 361745013248581ULL, // UMLAL_MZZI_HtoS |
| 9920 | 18697385382469ULL, // UMLAL_MZZ_HtoS |
| 9921 | 22650974401434181ULL, // UMLAL_VG2_M2Z2Z_HtoS |
| 9922 | 888468002763412037ULL, // UMLAL_VG2_M2ZZI_S |
| 9923 | 456122438535844421ULL, // UMLAL_VG2_M2ZZ_HtoS |
| 9924 | 22650974669869637ULL, // UMLAL_VG4_M4Z4Z_HtoS |
| 9925 | 888468003031847493ULL, // UMLAL_VG4_M4ZZI_HtoS |
| 9926 | 456122438804279877ULL, // UMLAL_VG4_M4ZZ_HtoS |
| 9927 | 8005100725469442ULL, // UMLALv16i8_v8i16 |
| 9928 | 1050588448815190597ULL, // UMLALv2i32_indexed |
| 9929 | 9131034985763397ULL, // UMLALv2i32_v2i64 |
| 9930 | 1034825884483326533ULL, // UMLALv4i16_indexed |
| 9931 | 10256969256538693ULL, // UMLALv4i16_v4i32 |
| 9932 | 1050588345735971074ULL, // UMLALv4i32_indexed |
| 9933 | 3501432372330754ULL, // UMLALv4i32_v2i64 |
| 9934 | 1034825781404107010ULL, // UMLALv8i16_indexed |
| 9935 | 4627366643106050ULL, // UMLALv8i16_v4i32 |
| 9936 | 11382903525216837ULL, // UMLALv8i8_v8i16 |
| 9937 | 457142164655229021ULL, // UMLSLB_ZZZI_D |
| 9938 | 457221330566203485ULL, // UMLSLB_ZZZI_S |
| 9939 | 26802477123677ULL, // UMLSLB_ZZZ_D |
| 9940 | 18797264177245ULL, // UMLSLB_ZZZ_H |
| 9941 | 105968388098141ULL, // UMLSLB_ZZZ_S |
| 9942 | 363016348734670ULL, // UMLSLL_MZZI_BtoS |
| 9943 | 361745038398670ULL, // UMLSLL_MZZI_HtoD |
| 9944 | 19968720868558ULL, // UMLSLL_MZZ_BtoS |
| 9945 | 18697410532558ULL, // UMLSLL_MZZ_HtoD |
| 9946 | 512479600022734ULL, // UMLSLL_VG2_M2Z2Z_BtoS |
| 9947 | 22650974426584270ULL, // UMLSLL_VG2_M2Z2Z_HtoD |
| 9948 | 43305472153064654ULL, // UMLSLL_VG2_M2ZZI_BtoS |
| 9949 | 888468002788562126ULL, // UMLSLL_VG2_M2ZZI_HtoD |
| 9950 | 521283209237710ULL, // UMLSLL_VG2_M2ZZ_BtoS |
| 9951 | 456122446077187278ULL, // UMLSLL_VG2_M2ZZ_HtoD |
| 9952 | 512479868458190ULL, // UMLSLL_VG4_M4Z4Z_BtoS |
| 9953 | 22650974695019726ULL, // UMLSLL_VG4_M4Z4Z_HtoD |
| 9954 | 43305472421500110ULL, // UMLSLL_VG4_M4ZZI_BtoS |
| 9955 | 888468003056997582ULL, // UMLSLL_VG4_M4ZZI_HtoD |
| 9956 | 521283477673166ULL, // UMLSLL_VG4_M4ZZ_BtoS |
| 9957 | 456122446345622734ULL, // UMLSLL_VG4_M4ZZ_HtoD |
| 9958 | 457142164655235287ULL, // UMLSLT_ZZZI_D |
| 9959 | 457221330566209751ULL, // UMLSLT_ZZZI_S |
| 9960 | 26802477129943ULL, // UMLSLT_ZZZ_D |
| 9961 | 18797264183511ULL, // UMLSLT_ZZZ_H |
| 9962 | 105968388104407ULL, // UMLSLT_ZZZ_S |
| 9963 | 361745013249645ULL, // UMLSL_MZZI_HtoS |
| 9964 | 18697385383533ULL, // UMLSL_MZZ_HtoS |
| 9965 | 22650974401435245ULL, // UMLSL_VG2_M2Z2Z_HtoS |
| 9966 | 888468002763413101ULL, // UMLSL_VG2_M2ZZI_S |
| 9967 | 456122438535845485ULL, // UMLSL_VG2_M2ZZ_HtoS |
| 9968 | 22650974669870701ULL, // UMLSL_VG4_M4Z4Z_HtoS |
| 9969 | 888468003031848557ULL, // UMLSL_VG4_M4ZZI_HtoS |
| 9970 | 456122438804280941ULL, // UMLSL_VG4_M4ZZ_HtoS |
| 9971 | 8005100725469574ULL, // UMLSLv16i8_v8i16 |
| 9972 | 1050588448815191661ULL, // UMLSLv2i32_indexed |
| 9973 | 9131034985764461ULL, // UMLSLv2i32_v2i64 |
| 9974 | 1034825884483327597ULL, // UMLSLv4i16_indexed |
| 9975 | 10256969256539757ULL, // UMLSLv4i16_v4i32 |
| 9976 | 1050588345735971206ULL, // UMLSLv4i32_indexed |
| 9977 | 3501432372330886ULL, // UMLSLv4i32_v2i64 |
| 9978 | 1034825781404107142ULL, // UMLSLv8i16_indexed |
| 9979 | 4627366643106182ULL, // UMLSLv8i16_v4i32 |
| 9980 | 11382903525217901ULL, // UMLSLv8i8_v8i16 |
| 9981 | 8005100723372940ULL, // UMMLA |
| 9982 | 18801758389132ULL, // UMMLA_ZZZ |
| 9983 | 12157305586ULL, // UMOP4A_M2Z2Z_BToS |
| 9984 | 5958124274ULL, // UMOP4A_M2Z2Z_HToS |
| 9985 | 5958124274ULL, // UMOP4A_M2Z2Z_HtoD |
| 9986 | 12962611954ULL, // UMOP4A_M2ZZ_BToS |
| 9987 | 6226559730ULL, // UMOP4A_M2ZZ_HToS |
| 9988 | 6226559730ULL, // UMOP4A_M2ZZ_HtoD |
| 9989 | 2407669023474ULL, // UMOP4A_MZ2Z_BToS |
| 9990 | 1136331440882ULL, // UMOP4A_MZ2Z_HToS |
| 9991 | 1136331440882ULL, // UMOP4A_MZ2Z_HtoD |
| 9992 | 18797264225010ULL, // UMOP4A_MZZ_BToS |
| 9993 | 17663365595890ULL, // UMOP4A_MZZ_HToS |
| 9994 | 17663365595890ULL, // UMOP4A_MZZ_HtoD |
| 9995 | 12157312402ULL, // UMOP4S_M2Z2Z_BToS |
| 9996 | 5958131090ULL, // UMOP4S_M2Z2Z_HToS |
| 9997 | 5958131090ULL, // UMOP4S_M2Z2Z_HtoD |
| 9998 | 12962618770ULL, // UMOP4S_M2ZZ_BToS |
| 9999 | 6226566546ULL, // UMOP4S_M2ZZ_HToS |
| 10000 | 6226566546ULL, // UMOP4S_M2ZZ_HtoD |
| 10001 | 2407669030290ULL, // UMOP4S_MZ2Z_BToS |
| 10002 | 1136331447698ULL, // UMOP4S_MZ2Z_HToS |
| 10003 | 1136331447698ULL, // UMOP4S_MZ2Z_HtoD |
| 10004 | 18797264231826ULL, // UMOP4S_MZZ_BToS |
| 10005 | 17663365602706ULL, // UMOP4S_MZZ_HToS |
| 10006 | 17663365602706ULL, // UMOP4S_MZZ_HtoD |
| 10007 | 378679217734695ULL, // UMOPA_MPPZZ_D |
| 10008 | 378679217734695ULL, // UMOPA_MPPZZ_HtoS |
| 10009 | 545804985156647ULL, // UMOPA_MPPZZ_S |
| 10010 | 378679217741481ULL, // UMOPS_MPPZZ_D |
| 10011 | 378679217741481ULL, // UMOPS_MPPZZ_HtoS |
| 10012 | 545804985163433ULL, // UMOPS_MPPZZ_S |
| 10013 | 467877901656917ULL, // UMOVvi16 |
| 10014 | 467877901656917ULL, // UMOVvi16_idx0 |
| 10015 | 467912261395285ULL, // UMOVvi32 |
| 10016 | 467912261395285ULL, // UMOVvi32_idx0 |
| 10017 | 467946621133653ULL, // UMOVvi64 |
| 10018 | 467946621133653ULL, // UMOVvi64_idx0 |
| 10019 | 467980980872021ULL, // UMOVvi8 |
| 10020 | 467980980872021ULL, // UMOVvi8_idx0 |
| 10021 | 1187884876977112ULL, // UMSUBLrrr |
| 10022 | 145276307521966076ULL, // UMULH_ZPmZ_B |
| 10023 | 289400291690860540ULL, // UMULH_ZPmZ_D |
| 10024 | 439233043046141948ULL, // UMULH_ZPmZ_H |
| 10025 | 577639463935627260ULL, // UMULH_ZPmZ_S |
| 10026 | 35600180744188ULL, // UMULH_ZZZ_B |
| 10027 | 44395468476412ULL, // UMULH_ZZZ_D |
| 10028 | 17732068249596ULL, // UMULH_ZZZ_H |
| 10029 | 53192635273212ULL, // UMULH_ZZZ_S |
| 10030 | 61984970133500ULL, // UMULHrr |
| 10031 | 50718688443156486ULL, // UMULLB_ZZZI_D |
| 10032 | 50762667297687558ULL, // UMULLB_ZZZI_S |
| 10033 | 53192635238406ULL, // UMULLB_ZZZ_D |
| 10034 | 792738203654ULL, // UMULLB_ZZZ_H |
| 10035 | 97171489769478ULL, // UMULLB_ZZZ_S |
| 10036 | 50718688443162775ULL, // UMULLT_ZZZI_D |
| 10037 | 50762667297693847ULL, // UMULLT_ZZZI_S |
| 10038 | 53192635244695ULL, // UMULLT_ZZZ_D |
| 10039 | 792738209943ULL, // UMULLT_ZZZ_H |
| 10040 | 97171489775767ULL, // UMULLT_ZZZ_S |
| 10041 | 7996302753366372ULL, // UMULLv16i8_v8i16 |
| 10042 | 3212307471980926189ULL, // UMULLv2i32_indexed |
| 10043 | 9122237013660909ULL, // UMULLv2i32_v2i64 |
| 10044 | 3196544907649062125ULL, // UMULLv4i16_indexed |
| 10045 | 10248171284436205ULL, // UMULLv4i16_v4i32 |
| 10046 | 3212307368901706084ULL, // UMULLv4i32_indexed |
| 10047 | 3492634400227684ULL, // UMULLv4i32_v2i64 |
| 10048 | 3196544804569842020ULL, // UMULLv8i16_indexed |
| 10049 | 4618568671002980ULL, // UMULLv8i16_v4i32 |
| 10050 | 11374105553114349ULL, // UMULLv8i8_v8i16 |
| 10051 | 167541576076396ULL, // UQADD_ZI_B |
| 10052 | 176336863808620ULL, // UQADD_ZI_D |
| 10053 | 930156186732ULL, // UQADD_ZI_H |
| 10054 | 185134030605420ULL, // UQADD_ZI_S |
| 10055 | 145276307521965164ULL, // UQADD_ZPmZ_B |
| 10056 | 289400291690859628ULL, // UQADD_ZPmZ_D |
| 10057 | 439233043046141036ULL, // UQADD_ZPmZ_H |
| 10058 | 577639463935626348ULL, // UQADD_ZPmZ_S |
| 10059 | 35600180743276ULL, // UQADD_ZZZ_B |
| 10060 | 44395468475500ULL, // UQADD_ZZZ_D |
| 10061 | 17732068248684ULL, // UQADD_ZZZ_H |
| 10062 | 53192635272300ULL, // UQADD_ZZZ_S |
| 10063 | 7996302742883436ULL, // UQADDv16i8 |
| 10064 | 61984970132588ULL, // UQADDv1i16 |
| 10065 | 61984970132588ULL, // UQADDv1i32 |
| 10066 | 61984970132588ULL, // UQADDv1i64 |
| 10067 | 61984970132588ULL, // UQADDv1i8 |
| 10068 | 9122237011561580ULL, // UQADDv2i32 |
| 10069 | 2366700133649516ULL, // UQADDv2i64 |
| 10070 | 10248171282336876ULL, // UQADDv4i16 |
| 10071 | 3492634404424812ULL, // UQADDv4i32 |
| 10072 | 4618568673102956ULL, // UQADDv8i16 |
| 10073 | 11374105555209324ULL, // UQADDv8i8 |
| 10074 | 4867561607ULL, // UQCVTN_Z2Z_StoH |
| 10075 | 4863367303ULL, // UQCVTN_Z4Z_DtoH |
| 10076 | 10471118983ULL, // UQCVTN_Z4Z_StoB |
| 10077 | 4867564097ULL, // UQCVT_Z2Z_StoH |
| 10078 | 4863369793ULL, // UQCVT_Z4Z_DtoH |
| 10079 | 10471121473ULL, // UQCVT_Z4Z_StoB |
| 10080 | 8592049829ULL, // UQDECB_WPiI |
| 10081 | 8592049829ULL, // UQDECB_XPiI |
| 10082 | 8592051174ULL, // UQDECD_WPiI |
| 10083 | 8592051174ULL, // UQDECD_XPiI |
| 10084 | 8592083942ULL, // UQDECD_ZPiI |
| 10085 | 8592051978ULL, // UQDECH_WPiI |
| 10086 | 8592051978ULL, // UQDECH_XPiI |
| 10087 | 54595338ULL, // UQDECH_ZPiI |
| 10088 | 3491780924ULL, // UQDECP_WP_B |
| 10089 | 2686474556ULL, // UQDECP_WP_D |
| 10090 | 2149603644ULL, // UQDECP_WP_H |
| 10091 | 3760216380ULL, // UQDECP_WP_S |
| 10092 | 3491780924ULL, // UQDECP_XP_B |
| 10093 | 2686474556ULL, // UQDECP_XP_D |
| 10094 | 2149603644ULL, // UQDECP_XP_H |
| 10095 | 3760216380ULL, // UQDECP_XP_S |
| 10096 | 1612765500ULL, // UQDECP_ZP_D |
| 10097 | 4875950396ULL, // UQDECP_ZP_H |
| 10098 | 1881233724ULL, // UQDECP_ZP_S |
| 10099 | 8592057415ULL, // UQDECW_WPiI |
| 10100 | 8592057415ULL, // UQDECW_XPiI |
| 10101 | 8592122951ULL, // UQDECW_ZPiI |
| 10102 | 8592049845ULL, // UQINCB_WPiI |
| 10103 | 8592049845ULL, // UQINCB_XPiI |
| 10104 | 8592051190ULL, // UQINCD_WPiI |
| 10105 | 8592051190ULL, // UQINCD_XPiI |
| 10106 | 8592083958ULL, // UQINCD_ZPiI |
| 10107 | 8592051994ULL, // UQINCH_WPiI |
| 10108 | 8592051994ULL, // UQINCH_XPiI |
| 10109 | 54595354ULL, // UQINCH_ZPiI |
| 10110 | 3491780940ULL, // UQINCP_WP_B |
| 10111 | 2686474572ULL, // UQINCP_WP_D |
| 10112 | 2149603660ULL, // UQINCP_WP_H |
| 10113 | 3760216396ULL, // UQINCP_WP_S |
| 10114 | 3491780940ULL, // UQINCP_XP_B |
| 10115 | 2686474572ULL, // UQINCP_XP_D |
| 10116 | 2149603660ULL, // UQINCP_XP_H |
| 10117 | 3760216396ULL, // UQINCP_XP_S |
| 10118 | 1612765516ULL, // UQINCP_ZP_D |
| 10119 | 4875950412ULL, // UQINCP_ZP_H |
| 10120 | 1881233740ULL, // UQINCP_ZP_S |
| 10121 | 8592057431ULL, // UQINCW_WPiI |
| 10122 | 8592057431ULL, // UQINCW_XPiI |
| 10123 | 8592122967ULL, // UQINCW_ZPiI |
| 10124 | 145276307521969281ULL, // UQRSHLR_ZPmZ_B |
| 10125 | 289400291690863745ULL, // UQRSHLR_ZPmZ_D |
| 10126 | 439233043046145153ULL, // UQRSHLR_ZPmZ_H |
| 10127 | 577639463935630465ULL, // UQRSHLR_ZPmZ_S |
| 10128 | 145276307521967228ULL, // UQRSHL_ZPmZ_B |
| 10129 | 289400291690861692ULL, // UQRSHL_ZPmZ_D |
| 10130 | 439233043046143100ULL, // UQRSHL_ZPmZ_H |
| 10131 | 577639463935628412ULL, // UQRSHL_ZPmZ_S |
| 10132 | 7996302742885500ULL, // UQRSHLv16i8 |
| 10133 | 61984970134652ULL, // UQRSHLv1i16 |
| 10134 | 61984970134652ULL, // UQRSHLv1i32 |
| 10135 | 61984970134652ULL, // UQRSHLv1i64 |
| 10136 | 61984970134652ULL, // UQRSHLv1i8 |
| 10137 | 9122237011563644ULL, // UQRSHLv2i32 |
| 10138 | 2366700133651580ULL, // UQRSHLv2i64 |
| 10139 | 10248171282338940ULL, // UQRSHLv4i16 |
| 10140 | 3492634404426876ULL, // UQRSHLv4i32 |
| 10141 | 4618568673105020ULL, // UQRSHLv8i16 |
| 10142 | 11374105555211388ULL, // UQRSHLv8i8 |
| 10143 | 61987117631687ULL, // UQRSHRNB_ZZI_B |
| 10144 | 18591057512647ULL, // UQRSHRNB_ZZI_H |
| 10145 | 61987654551751ULL, // UQRSHRNB_ZZI_S |
| 10146 | 387443364766016ULL, // UQRSHRNT_ZZI_B |
| 10147 | 19175175168320ULL, // UQRSHRNT_ZZI_H |
| 10148 | 387442022637888ULL, // UQRSHRNT_ZZI_S |
| 10149 | 61995439134808ULL, // UQRSHRN_VG4_Z4ZI_B |
| 10150 | 18591065905240ULL, // UQRSHRN_VG4_Z4ZI_H |
| 10151 | 61990338861144ULL, // UQRSHRN_Z2ZI_HtoB |
| 10152 | 18591070099544ULL, // UQRSHRN_Z2ZI_StoH |
| 10153 | 61984970135640ULL, // UQRSHRNb |
| 10154 | 61984970135640ULL, // UQRSHRNh |
| 10155 | 61984970135640ULL, // UQRSHRNs |
| 10156 | 387649798013400ULL, // UQRSHRNv16i8_shift |
| 10157 | 62123759736920ULL, // UQRSHRNv2i32_shift |
| 10158 | 62158123669592ULL, // UQRSHRNv4i16_shift |
| 10159 | 387581086925272ULL, // UQRSHRNv4i32_shift |
| 10160 | 387615448760792ULL, // UQRSHRNv8i16_shift |
| 10161 | 62192489699416ULL, // UQRSHRNv8i8_shift |
| 10162 | 18591070100513ULL, // UQRSHR_VG2_Z2ZI_H |
| 10163 | 61995439135777ULL, // UQRSHR_VG4_Z4ZI_B |
| 10164 | 18591065906209ULL, // UQRSHR_VG4_Z4ZI_H |
| 10165 | 145276307521969264ULL, // UQSHLR_ZPmZ_B |
| 10166 | 289400291690863728ULL, // UQSHLR_ZPmZ_D |
| 10167 | 439233043046145136ULL, // UQSHLR_ZPmZ_H |
| 10168 | 577639463935630448ULL, // UQSHLR_ZPmZ_S |
| 10169 | 1161119446111341ULL, // UQSHL_ZPmI_B |
| 10170 | 1169915539149933ULL, // UQSHL_ZPmI_D |
| 10171 | 450492042114569325ULL, // UQSHL_ZPmI_H |
| 10172 | 1178711632204909ULL, // UQSHL_ZPmI_S |
| 10173 | 145276307521967213ULL, // UQSHL_ZPmZ_B |
| 10174 | 289400291690861677ULL, // UQSHL_ZPmZ_D |
| 10175 | 439233043046143085ULL, // UQSHL_ZPmZ_H |
| 10176 | 577639463935628397ULL, // UQSHL_ZPmZ_S |
| 10177 | 61984970134637ULL, // UQSHLb |
| 10178 | 61984970134637ULL, // UQSHLd |
| 10179 | 61984970134637ULL, // UQSHLh |
| 10180 | 61984970134637ULL, // UQSHLs |
| 10181 | 7996302742885485ULL, // UQSHLv16i8 |
| 10182 | 62226836853869ULL, // UQSHLv16i8_shift |
| 10183 | 61984970134637ULL, // UQSHLv1i16 |
| 10184 | 61984970134637ULL, // UQSHLv1i32 |
| 10185 | 61984970134637ULL, // UQSHLv1i64 |
| 10186 | 61984970134637ULL, // UQSHLv1i8 |
| 10187 | 9122237011563629ULL, // UQSHLv2i32 |
| 10188 | 62261198689389ULL, // UQSHLv2i32_shift |
| 10189 | 2366700133651565ULL, // UQSHLv2i64 |
| 10190 | 62123761833069ULL, // UQSHLv2i64_shift |
| 10191 | 10248171282338925ULL, // UQSHLv4i16 |
| 10192 | 62295562622061ULL, // UQSHLv4i16_shift |
| 10193 | 3492634404426861ULL, // UQSHLv4i32 |
| 10194 | 62158125765741ULL, // UQSHLv4i32_shift |
| 10195 | 4618568673105005ULL, // UQSHLv8i16 |
| 10196 | 62192487601261ULL, // UQSHLv8i16_shift |
| 10197 | 11374105555211373ULL, // UQSHLv8i8 |
| 10198 | 62329928651885ULL, // UQSHLv8i8_shift |
| 10199 | 61987117631668ULL, // UQSHRNB_ZZI_B |
| 10200 | 18591057512628ULL, // UQSHRNB_ZZI_H |
| 10201 | 61987654551732ULL, // UQSHRNB_ZZI_S |
| 10202 | 387443364765997ULL, // UQSHRNT_ZZI_B |
| 10203 | 19175175168301ULL, // UQSHRNT_ZZI_H |
| 10204 | 387442022637869ULL, // UQSHRNT_ZZI_S |
| 10205 | 61990338861127ULL, // UQSHRN_Z2ZI_HtoB |
| 10206 | 18591070099527ULL, // UQSHRN_Z2ZI_StoH |
| 10207 | 61984970135623ULL, // UQSHRNb |
| 10208 | 61984970135623ULL, // UQSHRNh |
| 10209 | 61984970135623ULL, // UQSHRNs |
| 10210 | 387649798013381ULL, // UQSHRNv16i8_shift |
| 10211 | 62123759736903ULL, // UQSHRNv2i32_shift |
| 10212 | 62158123669575ULL, // UQSHRNv4i16_shift |
| 10213 | 387581086925253ULL, // UQSHRNv4i32_shift |
| 10214 | 387615448760773ULL, // UQSHRNv8i16_shift |
| 10215 | 62192489699399ULL, // UQSHRNv8i8_shift |
| 10216 | 145276307521969089ULL, // UQSUBR_ZPmZ_B |
| 10217 | 289400291690863553ULL, // UQSUBR_ZPmZ_D |
| 10218 | 439233043046144961ULL, // UQSUBR_ZPmZ_H |
| 10219 | 577639463935630273ULL, // UQSUBR_ZPmZ_S |
| 10220 | 167541576075919ULL, // UQSUB_ZI_B |
| 10221 | 176336863808143ULL, // UQSUB_ZI_D |
| 10222 | 930156186255ULL, // UQSUB_ZI_H |
| 10223 | 185134030604943ULL, // UQSUB_ZI_S |
| 10224 | 145276307521964687ULL, // UQSUB_ZPmZ_B |
| 10225 | 289400291690859151ULL, // UQSUB_ZPmZ_D |
| 10226 | 439233043046140559ULL, // UQSUB_ZPmZ_H |
| 10227 | 577639463935625871ULL, // UQSUB_ZPmZ_S |
| 10228 | 35600180742799ULL, // UQSUB_ZZZ_B |
| 10229 | 44395468475023ULL, // UQSUB_ZZZ_D |
| 10230 | 17732068248207ULL, // UQSUB_ZZZ_H |
| 10231 | 53192635271823ULL, // UQSUB_ZZZ_S |
| 10232 | 7996302742882959ULL, // UQSUBv16i8 |
| 10233 | 61984970132111ULL, // UQSUBv1i16 |
| 10234 | 61984970132111ULL, // UQSUBv1i32 |
| 10235 | 61984970132111ULL, // UQSUBv1i64 |
| 10236 | 61984970132111ULL, // UQSUBv1i8 |
| 10237 | 9122237011561103ULL, // UQSUBv2i32 |
| 10238 | 2366700133649039ULL, // UQSUBv2i64 |
| 10239 | 10248171282336399ULL, // UQSUBv4i16 |
| 10240 | 3492634404424335ULL, // UQSUBv4i32 |
| 10241 | 4618568673102479ULL, // UQSUBv8i16 |
| 10242 | 11374105555208847ULL, // UQSUBv8i8 |
| 10243 | 2149615841ULL, // UQXTNB_ZZ_B |
| 10244 | 4854974689ULL, // UQXTNB_ZZ_H |
| 10245 | 2686535905ULL, // UQXTNB_ZZ_S |
| 10246 | 2954928475ULL, // UQXTNT_ZZ_B |
| 10247 | 4857078107ULL, // UQXTNT_ZZ_H |
| 10248 | 1612800347ULL, // UQXTNT_ZZ_S |
| 10249 | 346827129337ULL, // UQXTNv16i8 |
| 10250 | 2119830ULL, // UQXTNv1i16 |
| 10251 | 2119830ULL, // UQXTNv1i32 |
| 10252 | 2119830ULL, // UQXTNv1i8 |
| 10253 | 241870936214ULL, // UQXTNv2i32 |
| 10254 | 310594607254ULL, // UQXTNv4i16 |
| 10255 | 243756302841ULL, // UQXTNv4i32 |
| 10256 | 312477876729ULL, // UQXTNv8i16 |
| 10257 | 344960637078ULL, // UQXTNv8i8 |
| 10258 | 26422909422945ULL, // URECPE_ZPmZ_S |
| 10259 | 52880444837217ULL, // URECPE_ZPzZ_S |
| 10260 | 207511194977ULL, // URECPEv2i32 |
| 10261 | 310596701537ULL, // URECPEv4i32 |
| 10262 | 145276307521965118ULL, // URHADD_ZPmZ_B |
| 10263 | 289400291690859582ULL, // URHADD_ZPmZ_D |
| 10264 | 439233043046140990ULL, // URHADD_ZPmZ_H |
| 10265 | 577639463935626302ULL, // URHADD_ZPmZ_S |
| 10266 | 7996302742883390ULL, // URHADDv16i8 |
| 10267 | 9122237011561534ULL, // URHADDv2i32 |
| 10268 | 10248171282336830ULL, // URHADDv4i16 |
| 10269 | 3492634404424766ULL, // URHADDv4i32 |
| 10270 | 4618568673102910ULL, // URHADDv8i16 |
| 10271 | 11374105555209278ULL, // URHADDv8i8 |
| 10272 | 145276307521969298ULL, // URSHLR_ZPmZ_B |
| 10273 | 289400291690863762ULL, // URSHLR_ZPmZ_D |
| 10274 | 439233043046145170ULL, // URSHLR_ZPmZ_H |
| 10275 | 577639463935630482ULL, // URSHLR_ZPmZ_S |
| 10276 | 21649080603787ULL, // URSHL_VG2_2Z2Z_B |
| 10277 | 19553138676875ULL, // URSHL_VG2_2Z2Z_D |
| 10278 | 18659787592843ULL, // URSHL_VG2_2Z2Z_H |
| 10279 | 19587502642315ULL, // URSHL_VG2_2Z2Z_S |
| 10280 | 792719414411ULL, // URSHL_VG2_2ZZ_B |
| 10281 | 18419267310731ULL, // URSHL_VG2_2ZZ_D |
| 10282 | 17732074656907ULL, // URSHL_VG2_2ZZ_H |
| 10283 | 18075674154123ULL, // URSHL_VG2_2ZZ_S |
| 10284 | 21649080603787ULL, // URSHL_VG4_4Z4Z_B |
| 10285 | 19553138676875ULL, // URSHL_VG4_4Z4Z_D |
| 10286 | 18659787592843ULL, // URSHL_VG4_4Z4Z_H |
| 10287 | 19587502642315ULL, // URSHL_VG4_4Z4Z_S |
| 10288 | 792719414411ULL, // URSHL_VG4_4ZZ_B |
| 10289 | 18419267310731ULL, // URSHL_VG4_4ZZ_D |
| 10290 | 17732074656907ULL, // URSHL_VG4_4ZZ_H |
| 10291 | 18075674154123ULL, // URSHL_VG4_4ZZ_S |
| 10292 | 145276307521967243ULL, // URSHL_ZPmZ_B |
| 10293 | 289400291690861707ULL, // URSHL_ZPmZ_D |
| 10294 | 439233043046143115ULL, // URSHL_ZPmZ_H |
| 10295 | 577639463935628427ULL, // URSHL_ZPmZ_S |
| 10296 | 7996302742885515ULL, // URSHLv16i8 |
| 10297 | 61984970134667ULL, // URSHLv1i64 |
| 10298 | 9122237011563659ULL, // URSHLv2i32 |
| 10299 | 2366700133651595ULL, // URSHLv2i64 |
| 10300 | 10248171282338955ULL, // URSHLv4i16 |
| 10301 | 3492634404426891ULL, // URSHLv4i32 |
| 10302 | 4618568673105035ULL, // URSHLv8i16 |
| 10303 | 11374105555211403ULL, // URSHLv8i8 |
| 10304 | 1161119446113328ULL, // URSHR_ZPmI_B |
| 10305 | 1169915539151920ULL, // URSHR_ZPmI_D |
| 10306 | 450492042114571312ULL, // URSHR_ZPmI_H |
| 10307 | 1178711632206896ULL, // URSHR_ZPmI_S |
| 10308 | 61984970136624ULL, // URSHRd |
| 10309 | 62226836855856ULL, // URSHRv16i8_shift |
| 10310 | 62261198691376ULL, // URSHRv2i32_shift |
| 10311 | 62123761835056ULL, // URSHRv2i64_shift |
| 10312 | 62295562624048ULL, // URSHRv4i16_shift |
| 10313 | 62158125767728ULL, // URSHRv4i32_shift |
| 10314 | 62192487603248ULL, // URSHRv8i16_shift |
| 10315 | 62329928653872ULL, // URSHRv8i8_shift |
| 10316 | 26422909422998ULL, // URSQRTE_ZPmZ_S |
| 10317 | 52880444837270ULL, // URSQRTE_ZPzZ_S |
| 10318 | 207511195030ULL, // URSQRTEv2i32 |
| 10319 | 310596701590ULL, // URSQRTEv4i32 |
| 10320 | 19179715462369ULL, // URSRA_ZZI_B |
| 10321 | 387442022597857ULL, // URSRA_ZZI_D |
| 10322 | 19175194035425ULL, // URSRA_ZZI_H |
| 10323 | 387442291066081ULL, // URSRA_ZZI_S |
| 10324 | 387445512520929ULL, // URSRAd |
| 10325 | 387684157752545ULL, // URSRAv16i8_shift |
| 10326 | 387718519588065ULL, // URSRAv2i32_shift |
| 10327 | 387581082731745ULL, // URSRAv2i64_shift |
| 10328 | 387752883520737ULL, // URSRAv4i16_shift |
| 10329 | 387615446664417ULL, // URSRAv4i32_shift |
| 10330 | 387649808499937ULL, // URSRAv8i16_shift |
| 10331 | 387787249550561ULL, // URSRAv8i8_shift |
| 10332 | 512479562277271ULL, // USDOT_VG2_M2Z2Z_BToS |
| 10333 | 43305472115319191ULL, // USDOT_VG2_M2ZZI_BToS |
| 10334 | 521275655299479ULL, // USDOT_VG2_M2ZZ_BToS |
| 10335 | 512479830712727ULL, // USDOT_VG4_M4Z4Z_BToS |
| 10336 | 43305472383754647ULL, // USDOT_VG4_M4ZZI_BToS |
| 10337 | 521275923734935ULL, // USDOT_VG4_M4ZZ_BToS |
| 10338 | 18801758396823ULL, // USDOT_ZZZ |
| 10339 | 370645479285143ULL, // USDOT_ZZZI |
| 10340 | 44033897742344599ULL, // USDOTlanev16i8 |
| 10341 | 44034000815268247ULL, // USDOTlanev8i8 |
| 10342 | 8005100723380631ULL, // USDOTv16i8 |
| 10343 | 11382903516832151ULL, // USDOTv8i8 |
| 10344 | 61988728260580ULL, // USHLLB_ZZI_D |
| 10345 | 18591082678244ULL, // USHLLB_ZZI_H |
| 10346 | 61987117680612ULL, // USHLLB_ZZI_S |
| 10347 | 61988728266869ULL, // USHLLT_ZZI_D |
| 10348 | 18591082684533ULL, // USHLLT_ZZI_H |
| 10349 | 61987117686901ULL, // USHLLT_ZZI_S |
| 10350 | 62226847334722ULL, // USHLLv16i8_shift |
| 10351 | 62261200786623ULL, // USHLLv2i32_shift |
| 10352 | 62295564719295ULL, // USHLLv4i16_shift |
| 10353 | 62158121566530ULL, // USHLLv4i32_shift |
| 10354 | 62192485499202ULL, // USHLLv8i16_shift |
| 10355 | 62329926554815ULL, // USHLLv8i8_shift |
| 10356 | 7996302742885528ULL, // USHLv16i8 |
| 10357 | 61984970134680ULL, // USHLv1i64 |
| 10358 | 9122237011563672ULL, // USHLv2i32 |
| 10359 | 2366700133651608ULL, // USHLv2i64 |
| 10360 | 10248171282338968ULL, // USHLv4i16 |
| 10361 | 3492634404426904ULL, // USHLv4i32 |
| 10362 | 4618568673105048ULL, // USHLv8i16 |
| 10363 | 11374105555211416ULL, // USHLv8i8 |
| 10364 | 61984970136637ULL, // USHRd |
| 10365 | 62226836855869ULL, // USHRv16i8_shift |
| 10366 | 62261198691389ULL, // USHRv2i32_shift |
| 10367 | 62123761835069ULL, // USHRv2i64_shift |
| 10368 | 62295562624061ULL, // USHRv4i16_shift |
| 10369 | 62158125767741ULL, // USHRv4i32_shift |
| 10370 | 62192487603261ULL, // USHRv8i16_shift |
| 10371 | 62329928653885ULL, // USHRv8i8_shift |
| 10372 | 363016348734630ULL, // USMLALL_MZZI_BtoS |
| 10373 | 19968720868518ULL, // USMLALL_MZZ_BtoS |
| 10374 | 512479600022694ULL, // USMLALL_VG2_M2Z2Z_BtoS |
| 10375 | 43305472153064614ULL, // USMLALL_VG2_M2ZZI_BtoS |
| 10376 | 521283209237670ULL, // USMLALL_VG2_M2ZZ_BtoS |
| 10377 | 512479868458150ULL, // USMLALL_VG4_M4Z4Z_BtoS |
| 10378 | 43305472421500070ULL, // USMLALL_VG4_M4ZZI_BtoS |
| 10379 | 521283477673126ULL, // USMLALL_VG4_M4ZZ_BtoS |
| 10380 | 8005100723372932ULL, // USMMLA |
| 10381 | 18801758389124ULL, // USMMLA_ZZZ |
| 10382 | 12157305576ULL, // USMOP4A_M2Z2Z_BToS |
| 10383 | 5958124264ULL, // USMOP4A_M2Z2Z_HtoD |
| 10384 | 12962611944ULL, // USMOP4A_M2ZZ_BToS |
| 10385 | 6226559720ULL, // USMOP4A_M2ZZ_HtoD |
| 10386 | 2407669023464ULL, // USMOP4A_MZ2Z_BToS |
| 10387 | 1136331440872ULL, // USMOP4A_MZ2Z_HtoD |
| 10388 | 18797264225000ULL, // USMOP4A_MZZ_BToS |
| 10389 | 17663365595880ULL, // USMOP4A_MZZ_HtoD |
| 10390 | 12157312392ULL, // USMOP4S_M2Z2Z_BToS |
| 10391 | 5958131080ULL, // USMOP4S_M2Z2Z_HtoD |
| 10392 | 12962618760ULL, // USMOP4S_M2ZZ_BToS |
| 10393 | 6226566536ULL, // USMOP4S_M2ZZ_HtoD |
| 10394 | 2407669030280ULL, // USMOP4S_MZ2Z_BToS |
| 10395 | 1136331447688ULL, // USMOP4S_MZ2Z_HtoD |
| 10396 | 18797264231816ULL, // USMOP4S_MZZ_BToS |
| 10397 | 17663365602696ULL, // USMOP4S_MZZ_HtoD |
| 10398 | 378679217734659ULL, // USMOPA_MPPZZ_D |
| 10399 | 545804985156611ULL, // USMOPA_MPPZZ_S |
| 10400 | 378679217741472ULL, // USMOPS_MPPZZ_D |
| 10401 | 545804985163424ULL, // USMOPS_MPPZZ_S |
| 10402 | 145276307521965155ULL, // USQADD_ZPmZ_B |
| 10403 | 289400291690859619ULL, // USQADD_ZPmZ_D |
| 10404 | 439233043046141027ULL, // USQADD_ZPmZ_H |
| 10405 | 577639463935626339ULL, // USQADD_ZPmZ_S |
| 10406 | 175028440163ULL, // USQADDv16i8 |
| 10407 | 5102685283ULL, // USQADDv1i16 |
| 10408 | 5102685283ULL, // USQADDv1i32 |
| 10409 | 5102685283ULL, // USQADDv1i64 |
| 10410 | 5102685283ULL, // USQADDv1i8 |
| 10411 | 209390275683ULL, // USQADDv2i32 |
| 10412 | 243752111203ULL, // USQADDv2i64 |
| 10413 | 278113946723ULL, // USQADDv4i16 |
| 10414 | 312475782243ULL, // USQADDv4i32 |
| 10415 | 346837617763ULL, // USQADDv8i16 |
| 10416 | 381199453283ULL, // USQADDv8i8 |
| 10417 | 19179715462382ULL, // USRA_ZZI_B |
| 10418 | 387442022597870ULL, // USRA_ZZI_D |
| 10419 | 19175194035438ULL, // USRA_ZZI_H |
| 10420 | 387442291066094ULL, // USRA_ZZI_S |
| 10421 | 387445512520942ULL, // USRAd |
| 10422 | 387684157752558ULL, // USRAv16i8_shift |
| 10423 | 387718519588078ULL, // USRAv2i32_shift |
| 10424 | 387581082731758ULL, // USRAv2i64_shift |
| 10425 | 387752883520750ULL, // USRAv4i16_shift |
| 10426 | 387615446664430ULL, // USRAv4i32_shift |
| 10427 | 387649808499950ULL, // USRAv8i16_shift |
| 10428 | 387787249550574ULL, // USRAv8i8_shift |
| 10429 | 396249465472020ULL, // USTMOPA_M2ZZZI_BtoS |
| 10430 | 53192635238301ULL, // USUBLB_ZZZ_D |
| 10431 | 792738203549ULL, // USUBLB_ZZZ_H |
| 10432 | 97171489769373ULL, // USUBLB_ZZZ_S |
| 10433 | 53192635244567ULL, // USUBLT_ZZZ_D |
| 10434 | 792738209815ULL, // USUBLT_ZZZ_H |
| 10435 | 97171489775639ULL, // USUBLT_ZZZ_S |
| 10436 | 7996302753366290ULL, // USUBLv16i8_v8i16 |
| 10437 | 9122237013660647ULL, // USUBLv2i32_v2i64 |
| 10438 | 10248171284435943ULL, // USUBLv4i16_v4i32 |
| 10439 | 3492634400227602ULL, // USUBLv4i32_v2i64 |
| 10440 | 4618568671002898ULL, // USUBLv8i16_v4i32 |
| 10441 | 11374105553114087ULL, // USUBLv8i8_v8i16 |
| 10442 | 53191561497252ULL, // USUBWB_ZZZ_D |
| 10443 | 792717232804ULL, // USUBWB_ZZZ_H |
| 10444 | 97173100382884ULL, // USUBWB_ZZZ_S |
| 10445 | 53191561503318ULL, // USUBWT_ZZZ_D |
| 10446 | 792717238870ULL, // USUBWT_ZZZ_H |
| 10447 | 97173100388950ULL, // USUBWT_ZZZ_S |
| 10448 | 7996268393628254ULL, // USUBWv16i8_v8i16 |
| 10449 | 9122099574711343ULL, // USUBWv2i32_v2i64 |
| 10450 | 10248033845486639ULL, // USUBWv4i16_v4i32 |
| 10451 | 3492600040489566ULL, // USUBWv4i32_v2i64 |
| 10452 | 4618534311264862ULL, // USUBWv8i16_v4i32 |
| 10453 | 11373968114164783ULL, // USUBWv8i8_v8i16 |
| 10454 | 43305472383754669ULL, // USVDOT_VG4_M4ZZI_BToS |
| 10455 | 396249465472030ULL, // UTMOPA_M2ZZZI_BtoS |
| 10456 | 396242729419806ULL, // UTMOPA_M2ZZZI_HtoS |
| 10457 | 3760247190ULL, // UUNPKHI_ZZ_D |
| 10458 | 4880142742ULL, // UUNPKHI_ZZ_H |
| 10459 | 2149667222ULL, // UUNPKHI_ZZ_S |
| 10460 | 3760249081ULL, // UUNPKLO_ZZ_D |
| 10461 | 4880144633ULL, // UUNPKLO_ZZ_H |
| 10462 | 2149669113ULL, // UUNPKLO_ZZ_S |
| 10463 | 4855075294ULL, // UUNPK_VG2_2ZZ_D |
| 10464 | 4880257502ULL, // UUNPK_VG2_2ZZ_H |
| 10465 | 4859302366ULL, // UUNPK_VG2_2ZZ_S |
| 10466 | 4867658206ULL, // UUNPK_VG4_4Z2Z_D |
| 10467 | 4861383134ULL, // UUNPK_VG4_4Z2Z_H |
| 10468 | 4865593822ULL, // UUNPK_VG4_4Z2Z_S |
| 10469 | 888468002750833078ULL, // UVDOT_VG2_M2ZZI_HtoS |
| 10470 | 43305472383754678ULL, // UVDOT_VG4_M4ZZI_BtoS |
| 10471 | 888468003019252150ULL, // UVDOT_VG4_M4ZZI_HtoD |
| 10472 | 8830723344990ULL, // UXTB_ZPmZ_D |
| 10473 | 17661446654558ULL, // UXTB_ZPmZ_H |
| 10474 | 26422909422174ULL, // UXTB_ZPmZ_S |
| 10475 | 44084351781470ULL, // UXTB_ZPzZ_D |
| 10476 | 17730705099358ULL, // UXTB_ZPzZ_H |
| 10477 | 52880444836446ULL, // UXTB_ZPzZ_S |
| 10478 | 8830723346754ULL, // UXTH_ZPmZ_D |
| 10479 | 26422909423938ULL, // UXTH_ZPmZ_S |
| 10480 | 44084351783234ULL, // UXTH_ZPzZ_D |
| 10481 | 52880444838210ULL, // UXTH_ZPzZ_S |
| 10482 | 8830723351793ULL, // UXTW_ZPmZ_D |
| 10483 | 44084351788273ULL, // UXTW_ZPzZ_D |
| 10484 | 35600180740177ULL, // UZP1_PPP_B |
| 10485 | 44395468472401ULL, // UZP1_PPP_D |
| 10486 | 17732068245585ULL, // UZP1_PPP_H |
| 10487 | 53192635269201ULL, // UZP1_PPP_S |
| 10488 | 35600180740177ULL, // UZP1_ZZZ_B |
| 10489 | 44395468472401ULL, // UZP1_ZZZ_D |
| 10490 | 17732068245585ULL, // UZP1_ZZZ_H |
| 10491 | 18556735930449ULL, // UZP1_ZZZ_Q |
| 10492 | 53192635269201ULL, // UZP1_ZZZ_S |
| 10493 | 7996302742880337ULL, // UZP1v16i8 |
| 10494 | 9122237011558481ULL, // UZP1v2i32 |
| 10495 | 2366700133646417ULL, // UZP1v2i64 |
| 10496 | 10248171282333777ULL, // UZP1v4i16 |
| 10497 | 3492634404421713ULL, // UZP1v4i32 |
| 10498 | 4618568673099857ULL, // UZP1v8i16 |
| 10499 | 11374105555206225ULL, // UZP1v8i8 |
| 10500 | 35600180740654ULL, // UZP2_PPP_B |
| 10501 | 44395468472878ULL, // UZP2_PPP_D |
| 10502 | 17732068246062ULL, // UZP2_PPP_H |
| 10503 | 53192635269678ULL, // UZP2_PPP_S |
| 10504 | 35600180740654ULL, // UZP2_ZZZ_B |
| 10505 | 44395468472878ULL, // UZP2_ZZZ_D |
| 10506 | 17732068246062ULL, // UZP2_ZZZ_H |
| 10507 | 18556735930926ULL, // UZP2_ZZZ_Q |
| 10508 | 53192635269678ULL, // UZP2_ZZZ_S |
| 10509 | 7996302742880814ULL, // UZP2v16i8 |
| 10510 | 9122237011558958ULL, // UZP2v2i32 |
| 10511 | 2366700133646894ULL, // UZP2v2i64 |
| 10512 | 10248171282334254ULL, // UZP2v4i16 |
| 10513 | 3492634404422190ULL, // UZP2v4i32 |
| 10514 | 4618568673100334ULL, // UZP2v8i16 |
| 10515 | 11374105555206702ULL, // UZP2v8i8 |
| 10516 | 35600180740190ULL, // UZPQ1_ZZZ_B |
| 10517 | 44395468472414ULL, // UZPQ1_ZZZ_D |
| 10518 | 17732068245598ULL, // UZPQ1_ZZZ_H |
| 10519 | 53192635269214ULL, // UZPQ1_ZZZ_S |
| 10520 | 35600180740667ULL, // UZPQ2_ZZZ_B |
| 10521 | 44395468472891ULL, // UZPQ2_ZZZ_D |
| 10522 | 17732068246075ULL, // UZPQ2_ZZZ_H |
| 10523 | 53192635269691ULL, // UZPQ2_ZZZ_S |
| 10524 | 792738290424ULL, // UZP_VG2_2ZZZ_B |
| 10525 | 167942904ULL, // UZP_VG2_2ZZZ_D |
| 10526 | 17732068367096ULL, // UZP_VG2_2ZZZ_H |
| 10527 | 18556735953656ULL, // UZP_VG2_2ZZZ_Q |
| 10528 | 18075661572856ULL, // UZP_VG2_2ZZZ_S |
| 10529 | 4861352696ULL, // UZP_VG4_4Z4Z_B |
| 10530 | 4863466232ULL, // UZP_VG4_4Z4Z_D |
| 10531 | 4865579768ULL, // UZP_VG4_4Z4Z_H |
| 10532 | 182950648ULL, // UZP_VG4_4Z4Z_Q |
| 10533 | 4867693304ULL, // UZP_VG4_4Z4Z_S |
| 10534 | 24397ULL, // WFET |
| 10535 | 24504ULL, // WFIT |
| 10536 | 18591093247200ULL, // WHILEGE_2PXX_B |
| 10537 | 18591093263584ULL, // WHILEGE_2PXX_D |
| 10538 | 18591093279968ULL, // WHILEGE_2PXX_H |
| 10539 | 18591093296352ULL, // WHILEGE_2PXX_S |
| 10540 | 6630486536367475936ULL, // WHILEGE_CXX_B |
| 10541 | 6630486536367492320ULL, // WHILEGE_CXX_D |
| 10542 | 6630486536367508704ULL, // WHILEGE_CXX_H |
| 10543 | 6630486536367525088ULL, // WHILEGE_CXX_S |
| 10544 | 61984970149088ULL, // WHILEGE_PWW_B |
| 10545 | 61984970165472ULL, // WHILEGE_PWW_D |
| 10546 | 18591093165280ULL, // WHILEGE_PWW_H |
| 10547 | 61984970198240ULL, // WHILEGE_PWW_S |
| 10548 | 61984970149088ULL, // WHILEGE_PXX_B |
| 10549 | 61984970165472ULL, // WHILEGE_PXX_D |
| 10550 | 18591093165280ULL, // WHILEGE_PXX_H |
| 10551 | 61984970198240ULL, // WHILEGE_PXX_S |
| 10552 | 18591093251980ULL, // WHILEGT_2PXX_B |
| 10553 | 18591093268364ULL, // WHILEGT_2PXX_D |
| 10554 | 18591093284748ULL, // WHILEGT_2PXX_H |
| 10555 | 18591093301132ULL, // WHILEGT_2PXX_S |
| 10556 | 6630486536367480716ULL, // WHILEGT_CXX_B |
| 10557 | 6630486536367497100ULL, // WHILEGT_CXX_D |
| 10558 | 6630486536367513484ULL, // WHILEGT_CXX_H |
| 10559 | 6630486536367529868ULL, // WHILEGT_CXX_S |
| 10560 | 61984970153868ULL, // WHILEGT_PWW_B |
| 10561 | 61984970170252ULL, // WHILEGT_PWW_D |
| 10562 | 18591093170060ULL, // WHILEGT_PWW_H |
| 10563 | 61984970203020ULL, // WHILEGT_PWW_S |
| 10564 | 61984970153868ULL, // WHILEGT_PXX_B |
| 10565 | 61984970170252ULL, // WHILEGT_PXX_D |
| 10566 | 18591093170060ULL, // WHILEGT_PXX_H |
| 10567 | 61984970203020ULL, // WHILEGT_PXX_S |
| 10568 | 18591093248372ULL, // WHILEHI_2PXX_B |
| 10569 | 18591093264756ULL, // WHILEHI_2PXX_D |
| 10570 | 18591093281140ULL, // WHILEHI_2PXX_H |
| 10571 | 18591093297524ULL, // WHILEHI_2PXX_S |
| 10572 | 6630486536367477108ULL, // WHILEHI_CXX_B |
| 10573 | 6630486536367493492ULL, // WHILEHI_CXX_D |
| 10574 | 6630486536367509876ULL, // WHILEHI_CXX_H |
| 10575 | 6630486536367526260ULL, // WHILEHI_CXX_S |
| 10576 | 61984970150260ULL, // WHILEHI_PWW_B |
| 10577 | 61984970166644ULL, // WHILEHI_PWW_D |
| 10578 | 18591093166452ULL, // WHILEHI_PWW_H |
| 10579 | 61984970199412ULL, // WHILEHI_PWW_S |
| 10580 | 61984970150260ULL, // WHILEHI_PXX_B |
| 10581 | 61984970166644ULL, // WHILEHI_PXX_D |
| 10582 | 18591093166452ULL, // WHILEHI_PXX_H |
| 10583 | 61984970199412ULL, // WHILEHI_PXX_S |
| 10584 | 18591093251608ULL, // WHILEHS_2PXX_B |
| 10585 | 18591093267992ULL, // WHILEHS_2PXX_D |
| 10586 | 18591093284376ULL, // WHILEHS_2PXX_H |
| 10587 | 18591093300760ULL, // WHILEHS_2PXX_S |
| 10588 | 6630486536367480344ULL, // WHILEHS_CXX_B |
| 10589 | 6630486536367496728ULL, // WHILEHS_CXX_D |
| 10590 | 6630486536367513112ULL, // WHILEHS_CXX_H |
| 10591 | 6630486536367529496ULL, // WHILEHS_CXX_S |
| 10592 | 61984970153496ULL, // WHILEHS_PWW_B |
| 10593 | 61984970169880ULL, // WHILEHS_PWW_D |
| 10594 | 18591093169688ULL, // WHILEHS_PWW_H |
| 10595 | 61984970202648ULL, // WHILEHS_PWW_S |
| 10596 | 61984970153496ULL, // WHILEHS_PXX_B |
| 10597 | 61984970169880ULL, // WHILEHS_PXX_D |
| 10598 | 18591093169688ULL, // WHILEHS_PXX_H |
| 10599 | 61984970202648ULL, // WHILEHS_PXX_S |
| 10600 | 18591093247247ULL, // WHILELE_2PXX_B |
| 10601 | 18591093263631ULL, // WHILELE_2PXX_D |
| 10602 | 18591093280015ULL, // WHILELE_2PXX_H |
| 10603 | 18591093296399ULL, // WHILELE_2PXX_S |
| 10604 | 6630486536367475983ULL, // WHILELE_CXX_B |
| 10605 | 6630486536367492367ULL, // WHILELE_CXX_D |
| 10606 | 6630486536367508751ULL, // WHILELE_CXX_H |
| 10607 | 6630486536367525135ULL, // WHILELE_CXX_S |
| 10608 | 61984970149135ULL, // WHILELE_PWW_B |
| 10609 | 61984970165519ULL, // WHILELE_PWW_D |
| 10610 | 18591093165327ULL, // WHILELE_PWW_H |
| 10611 | 61984970198287ULL, // WHILELE_PWW_S |
| 10612 | 61984970149135ULL, // WHILELE_PXX_B |
| 10613 | 61984970165519ULL, // WHILELE_PXX_D |
| 10614 | 18591093165327ULL, // WHILELE_PXX_H |
| 10615 | 61984970198287ULL, // WHILELE_PXX_S |
| 10616 | 18591093250270ULL, // WHILELO_2PXX_B |
| 10617 | 18591093266654ULL, // WHILELO_2PXX_D |
| 10618 | 18591093283038ULL, // WHILELO_2PXX_H |
| 10619 | 18591093299422ULL, // WHILELO_2PXX_S |
| 10620 | 6630486536367479006ULL, // WHILELO_CXX_B |
| 10621 | 6630486536367495390ULL, // WHILELO_CXX_D |
| 10622 | 6630486536367511774ULL, // WHILELO_CXX_H |
| 10623 | 6630486536367528158ULL, // WHILELO_CXX_S |
| 10624 | 61984970152158ULL, // WHILELO_PWW_B |
| 10625 | 61984970168542ULL, // WHILELO_PWW_D |
| 10626 | 18591093168350ULL, // WHILELO_PWW_H |
| 10627 | 61984970201310ULL, // WHILELO_PWW_S |
| 10628 | 61984970152158ULL, // WHILELO_PXX_B |
| 10629 | 61984970168542ULL, // WHILELO_PXX_D |
| 10630 | 18591093168350ULL, // WHILELO_PXX_H |
| 10631 | 61984970201310ULL, // WHILELO_PXX_S |
| 10632 | 18591093251650ULL, // WHILELS_2PXX_B |
| 10633 | 18591093268034ULL, // WHILELS_2PXX_D |
| 10634 | 18591093284418ULL, // WHILELS_2PXX_H |
| 10635 | 18591093300802ULL, // WHILELS_2PXX_S |
| 10636 | 6630486536367480386ULL, // WHILELS_CXX_B |
| 10637 | 6630486536367496770ULL, // WHILELS_CXX_D |
| 10638 | 6630486536367513154ULL, // WHILELS_CXX_H |
| 10639 | 6630486536367529538ULL, // WHILELS_CXX_S |
| 10640 | 61984970153538ULL, // WHILELS_PWW_B |
| 10641 | 61984970169922ULL, // WHILELS_PWW_D |
| 10642 | 18591093169730ULL, // WHILELS_PWW_H |
| 10643 | 61984970202690ULL, // WHILELS_PWW_S |
| 10644 | 61984970153538ULL, // WHILELS_PXX_B |
| 10645 | 61984970169922ULL, // WHILELS_PXX_D |
| 10646 | 18591093169730ULL, // WHILELS_PXX_H |
| 10647 | 61984970202690ULL, // WHILELS_PXX_S |
| 10648 | 18591093252173ULL, // WHILELT_2PXX_B |
| 10649 | 18591093268557ULL, // WHILELT_2PXX_D |
| 10650 | 18591093284941ULL, // WHILELT_2PXX_H |
| 10651 | 18591093301325ULL, // WHILELT_2PXX_S |
| 10652 | 6630486536367480909ULL, // WHILELT_CXX_B |
| 10653 | 6630486536367497293ULL, // WHILELT_CXX_D |
| 10654 | 6630486536367513677ULL, // WHILELT_CXX_H |
| 10655 | 6630486536367530061ULL, // WHILELT_CXX_S |
| 10656 | 61984970154061ULL, // WHILELT_PWW_B |
| 10657 | 61984970170445ULL, // WHILELT_PWW_D |
| 10658 | 18591093170253ULL, // WHILELT_PWW_H |
| 10659 | 61984970203213ULL, // WHILELT_PWW_S |
| 10660 | 61984970154061ULL, // WHILELT_PXX_B |
| 10661 | 61984970170445ULL, // WHILELT_PXX_D |
| 10662 | 18591093170253ULL, // WHILELT_PXX_H |
| 10663 | 61984970203213ULL, // WHILELT_PXX_S |
| 10664 | 61984970155146ULL, // WHILERW_PXX_B |
| 10665 | 61984970171530ULL, // WHILERW_PXX_D |
| 10666 | 18591093171338ULL, // WHILERW_PXX_H |
| 10667 | 61984970204298ULL, // WHILERW_PXX_S |
| 10668 | 61984970153278ULL, // WHILEWR_PXX_B |
| 10669 | 61984970169662ULL, // WHILEWR_PXX_D |
| 10670 | 18591093169470ULL, // WHILEWR_PXX_H |
| 10671 | 61984970202430ULL, // WHILEWR_PXX_S |
| 10672 | 39954ULL, // WRFFR |
| 10673 | 11608ULL, // XAFLAG |
| 10674 | 36143697338932125ULL, // XAR |
| 10675 | 1161500087589789ULL, // XAR_ZZZI_B |
| 10676 | 1170295375322013ULL, // XAR_ZZZI_D |
| 10677 | 450492044014590877ULL, // XAR_ZZZI_H |
| 10678 | 1179092542118813ULL, // XAR_ZZZI_S |
| 10679 | 19415ULL, // XPACD |
| 10680 | 20832ULL, // XPACI |
| 10681 | 10097ULL, // XPACLRI |
| 10682 | 346827129331ULL, // XTNv16i8 |
| 10683 | 241870936209ULL, // XTNv2i32 |
| 10684 | 310594607249ULL, // XTNv4i16 |
| 10685 | 243756302835ULL, // XTNv4i32 |
| 10686 | 312477876723ULL, // XTNv8i16 |
| 10687 | 344960637073ULL, // XTNv8i8 |
| 10688 | 1284369ULL, // ZERO_M |
| 10689 | 25283483921ULL, // ZERO_MXI_2Z |
| 10690 | 25308649745ULL, // ZERO_MXI_4Z |
| 10691 | 17767291153ULL, // ZERO_MXI_VG2_2Z |
| 10692 | 17792456977ULL, // ZERO_MXI_VG2_4Z |
| 10693 | 17754708241ULL, // ZERO_MXI_VG2_Z |
| 10694 | 18035726609ULL, // ZERO_MXI_VG4_2Z |
| 10695 | 18060892433ULL, // ZERO_MXI_VG4_4Z |
| 10696 | 18023143697ULL, // ZERO_MXI_VG4_Z |
| 10697 | 184575552ULL, // ZERO_T |
| 10698 | 35600180740171ULL, // ZIP1_PPP_B |
| 10699 | 44395468472395ULL, // ZIP1_PPP_D |
| 10700 | 17732068245579ULL, // ZIP1_PPP_H |
| 10701 | 53192635269195ULL, // ZIP1_PPP_S |
| 10702 | 35600180740171ULL, // ZIP1_ZZZ_B |
| 10703 | 44395468472395ULL, // ZIP1_ZZZ_D |
| 10704 | 17732068245579ULL, // ZIP1_ZZZ_H |
| 10705 | 18556735930443ULL, // ZIP1_ZZZ_Q |
| 10706 | 53192635269195ULL, // ZIP1_ZZZ_S |
| 10707 | 7996302742880331ULL, // ZIP1v16i8 |
| 10708 | 9122237011558475ULL, // ZIP1v2i32 |
| 10709 | 2366700133646411ULL, // ZIP1v2i64 |
| 10710 | 10248171282333771ULL, // ZIP1v4i16 |
| 10711 | 3492634404421707ULL, // ZIP1v4i32 |
| 10712 | 4618568673099851ULL, // ZIP1v8i16 |
| 10713 | 11374105555206219ULL, // ZIP1v8i8 |
| 10714 | 35600180740648ULL, // ZIP2_PPP_B |
| 10715 | 44395468472872ULL, // ZIP2_PPP_D |
| 10716 | 17732068246056ULL, // ZIP2_PPP_H |
| 10717 | 53192635269672ULL, // ZIP2_PPP_S |
| 10718 | 35600180740648ULL, // ZIP2_ZZZ_B |
| 10719 | 44395468472872ULL, // ZIP2_ZZZ_D |
| 10720 | 17732068246056ULL, // ZIP2_ZZZ_H |
| 10721 | 18556735930920ULL, // ZIP2_ZZZ_Q |
| 10722 | 53192635269672ULL, // ZIP2_ZZZ_S |
| 10723 | 7996302742880808ULL, // ZIP2v16i8 |
| 10724 | 9122237011558952ULL, // ZIP2v2i32 |
| 10725 | 2366700133646888ULL, // ZIP2v2i64 |
| 10726 | 10248171282334248ULL, // ZIP2v4i16 |
| 10727 | 3492634404422184ULL, // ZIP2v4i32 |
| 10728 | 4618568673100328ULL, // ZIP2v8i16 |
| 10729 | 11374105555206696ULL, // ZIP2v8i8 |
| 10730 | 35600180740183ULL, // ZIPQ1_ZZZ_B |
| 10731 | 44395468472407ULL, // ZIPQ1_ZZZ_D |
| 10732 | 17732068245591ULL, // ZIPQ1_ZZZ_H |
| 10733 | 53192635269207ULL, // ZIPQ1_ZZZ_S |
| 10734 | 35600180740660ULL, // ZIPQ2_ZZZ_B |
| 10735 | 44395468472884ULL, // ZIPQ2_ZZZ_D |
| 10736 | 17732068246068ULL, // ZIPQ2_ZZZ_H |
| 10737 | 53192635269684ULL, // ZIPQ2_ZZZ_S |
| 10738 | 792738290028ULL, // ZIP_VG2_2ZZZ_B |
| 10739 | 167942508ULL, // ZIP_VG2_2ZZZ_D |
| 10740 | 17732068366700ULL, // ZIP_VG2_2ZZZ_H |
| 10741 | 18556735953260ULL, // ZIP_VG2_2ZZZ_Q |
| 10742 | 18075661572460ULL, // ZIP_VG2_2ZZZ_S |
| 10743 | 4861352300ULL, // ZIP_VG4_4Z4Z_B |
| 10744 | 4863465836ULL, // ZIP_VG4_4Z4Z_D |
| 10745 | 4865579372ULL, // ZIP_VG4_4Z4Z_H |
| 10746 | 182950252ULL, // ZIP_VG4_4Z4Z_Q |
| 10747 | 4867692908ULL, // ZIP_VG4_4Z4Z_S |
| 10748 | }; |
| 10749 | |
| 10750 | // Emit the opcode for the instruction. |
| 10751 | uint64_t Bits = 0; |
| 10752 | Bits |= (uint64_t)OpInfo0[MI.getOpcode()] << 0; |
| 10753 | if (Bits == 0) |
| 10754 | return {nullptr, Bits}; |
| 10755 | return {AsmStrs+(Bits & 16383)-1, Bits}; |
| 10756 | |
| 10757 | } |
| 10758 | /// printInstruction - This method is automatically generated by tablegen |
| 10759 | /// from the instruction set description. |
| 10760 | LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
| 10761 | void AArch64InstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| 10762 | O << "\t"; |
| 10763 | |
| 10764 | auto MnemonicInfo = getMnemonic(MI: *MI); |
| 10765 | |
| 10766 | O << MnemonicInfo.first; |
| 10767 | |
| 10768 | uint64_t Bits = MnemonicInfo.second; |
| 10769 | assert(Bits != 0 && "Cannot print this instruction."); |
| 10770 | |
| 10771 | // Fragment 0 encoded into 7 bits for 79 unique commands. |
| 10772 | switch ((Bits >> 14) & 127) { |
| 10773 | default: llvm_unreachable("Invalid command number."); |
| 10774 | case 0: |
| 10775 | // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
| 10776 | return; |
| 10777 | break; |
| 10778 | case 1: |
| 10779 | // TLSAUTHDESCCALL, TLSDESCCALL, ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ... |
| 10780 | printOperand(MI, OpNo: 0, STI, O); |
| 10781 | break; |
| 10782 | case 2: |
| 10783 | // ABS_ZPmZ_B, ABS_ZPzZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADDQP... |
| 10784 | printSVERegOp<'b'>(MI, OpNum: 0, STI, O); |
| 10785 | break; |
| 10786 | case 3: |
| 10787 | // ABS_ZPmZ_D, ABS_ZPzZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADDQP_Z... |
| 10788 | printSVERegOp<'d'>(MI, OpNum: 0, STI, O); |
| 10789 | break; |
| 10790 | case 4: |
| 10791 | // ABS_ZPmZ_H, ABS_ZPzZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADDQP... |
| 10792 | printSVERegOp<'h'>(MI, OpNum: 0, STI, O); |
| 10793 | O << ", "; |
| 10794 | break; |
| 10795 | case 5: |
| 10796 | // ABS_ZPmZ_S, ABS_ZPzZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT... |
| 10797 | printSVERegOp<'s'>(MI, OpNum: 0, STI, O); |
| 10798 | break; |
| 10799 | case 6: |
| 10800 | // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| 10801 | printVRegOperand(MI, OpNo: 0, STI, O); |
| 10802 | break; |
| 10803 | case 7: |
| 10804 | // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, BFMOP4A_M2Z2Z_... |
| 10805 | printMatrixTile(MI, OpNum: 0, STI, O); |
| 10806 | O << ", "; |
| 10807 | break; |
| 10808 | case 8: |
| 10809 | // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| 10810 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 10811 | break; |
| 10812 | case 9: |
| 10813 | // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, AESDIMC_2ZZI_B, AESDIMC_4ZZI_B, AESD_2ZZ... |
| 10814 | printTypedVectorList<0,'b'>(MI, OpNum: 0, STI, O); |
| 10815 | O << ", "; |
| 10816 | break; |
| 10817 | case 10: |
| 10818 | // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D... |
| 10819 | printTypedVectorList<0,'d'>(MI, OpNum: 0, STI, O); |
| 10820 | O << ", "; |
| 10821 | break; |
| 10822 | case 11: |
| 10823 | // ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BF1CVTL_2ZZ_BtoH, BF1CVT_2ZZ_BtoH, BF2CV... |
| 10824 | printTypedVectorList<0,'h'>(MI, OpNum: 0, STI, O); |
| 10825 | O << ", "; |
| 10826 | break; |
| 10827 | case 12: |
| 10828 | // ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, FAMAX_2Z2Z_S, FAMAX_4Z4Z_S, FAMIN_2Z2Z_S... |
| 10829 | printTypedVectorList<0,'s'>(MI, OpNum: 0, STI, O); |
| 10830 | O << ", "; |
| 10831 | break; |
| 10832 | case 13: |
| 10833 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V... |
| 10834 | printMatrix<64>(MI, OpNum: 0, STI, O); |
| 10835 | O << '['; |
| 10836 | printOperand(MI, OpNo: 2, STI, O); |
| 10837 | O << ", "; |
| 10838 | break; |
| 10839 | case 14: |
| 10840 | // ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V... |
| 10841 | printMatrix<32>(MI, OpNum: 0, STI, O); |
| 10842 | O << '['; |
| 10843 | printOperand(MI, OpNo: 2, STI, O); |
| 10844 | O << ", "; |
| 10845 | break; |
| 10846 | case 15: |
| 10847 | // ANDV_VPZ_B, EORV_VPZ_B, ORV_VPZ_B, SMAXV_VPZ_B, SMINV_VPZ_B, UMAXV_VPZ... |
| 10848 | printZPRasFPR<8>(MI, OpNum: 0, STI, O); |
| 10849 | O << ", "; |
| 10850 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 10851 | O << ", "; |
| 10852 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 10853 | return; |
| 10854 | break; |
| 10855 | case 16: |
| 10856 | // ANDV_VPZ_D, EORV_VPZ_D, FADDA_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV... |
| 10857 | printZPRasFPR<64>(MI, OpNum: 0, STI, O); |
| 10858 | O << ", "; |
| 10859 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 10860 | O << ", "; |
| 10861 | break; |
| 10862 | case 17: |
| 10863 | // ANDV_VPZ_H, EORV_VPZ_H, FADDA_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV... |
| 10864 | printZPRasFPR<16>(MI, OpNum: 0, STI, O); |
| 10865 | O << ", "; |
| 10866 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 10867 | O << ", "; |
| 10868 | break; |
| 10869 | case 18: |
| 10870 | // ANDV_VPZ_S, EORV_VPZ_S, FADDA_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAXV... |
| 10871 | printZPRasFPR<32>(MI, OpNum: 0, STI, O); |
| 10872 | O << ", "; |
| 10873 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 10874 | O << ", "; |
| 10875 | break; |
| 10876 | case 19: |
| 10877 | // AUTDA, AUTDB, AUTDZA, AUTDZB, AUTIA, AUTIB, AUTIZA, AUTIZB, CASAB, CAS... |
| 10878 | printOperand(MI, OpNo: 1, STI, O); |
| 10879 | break; |
| 10880 | case 20: |
| 10881 | // AUTIASPPCi, AUTIBSPPCi, B, BL, RETAASPPCi, RETABSPPCi |
| 10882 | printAlignedLabel(MI, Address, OpNum: 0, STI, O); |
| 10883 | return; |
| 10884 | break; |
| 10885 | case 21: |
| 10886 | // BCcc, Bcc, FLTcc |
| 10887 | printCondCode(MI, OpNum: 0, STI, O); |
| 10888 | O << "\t"; |
| 10889 | break; |
| 10890 | case 22: |
| 10891 | // BFADD_VG2_M2Z_H, BFADD_VG4_M4Z_H, BFMLA_VG2_M2Z2Z, BFMLA_VG2_M2ZZ, BFM... |
| 10892 | printMatrix<16>(MI, OpNum: 0, STI, O); |
| 10893 | O << '['; |
| 10894 | printOperand(MI, OpNo: 2, STI, O); |
| 10895 | O << ", "; |
| 10896 | break; |
| 10897 | case 23: |
| 10898 | // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC |
| 10899 | printImmHex(MI, OpNo: 0, STI, O); |
| 10900 | return; |
| 10901 | break; |
| 10902 | case 24: |
| 10903 | // CASPALTX, CASPALX, CASPATX, CASPAX, CASPLTX, CASPLX, CASPTX, CASPX, RC... |
| 10904 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 1, STI, O); |
| 10905 | O << ", "; |
| 10906 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 2, STI, O); |
| 10907 | O << ", ["; |
| 10908 | printOperand(MI, OpNo: 3, STI, O); |
| 10909 | O << ']'; |
| 10910 | return; |
| 10911 | break; |
| 10912 | case 25: |
| 10913 | // CASPALW, CASPAW, CASPLW, CASPW |
| 10914 | printGPRSeqPairsClassOperand<32>(MI, OpNum: 1, STI, O); |
| 10915 | O << ", "; |
| 10916 | printGPRSeqPairsClassOperand<32>(MI, OpNum: 2, STI, O); |
| 10917 | O << ", ["; |
| 10918 | printOperand(MI, OpNo: 3, STI, O); |
| 10919 | O << ']'; |
| 10920 | return; |
| 10921 | break; |
| 10922 | case 26: |
| 10923 | // CPYE, CPYEN, CPYERN, CPYERT, CPYERTN, CPYERTRN, CPYERTWN, CPYET, CPYET... |
| 10924 | printOperand(MI, OpNo: 3, STI, O); |
| 10925 | O << "]!, ["; |
| 10926 | printOperand(MI, OpNo: 4, STI, O); |
| 10927 | O << "]!, "; |
| 10928 | printOperand(MI, OpNo: 5, STI, O); |
| 10929 | O << '!'; |
| 10930 | return; |
| 10931 | break; |
| 10932 | case 27: |
| 10933 | // DMB, DSB, ISB |
| 10934 | printBarrierOption(MI, OpNum: 0, STI, O); |
| 10935 | return; |
| 10936 | break; |
| 10937 | case 28: |
| 10938 | // DSBnXS |
| 10939 | printBarriernXSOption(MI, OpNum: 0, STI, O); |
| 10940 | return; |
| 10941 | break; |
| 10942 | case 29: |
| 10943 | // DUP_ZZI_Q, EXTRACT_ZPMXI_H_Q, EXTRACT_ZPMXI_V_Q, MOVAZ_ZMI_H_Q, MOVAZ_... |
| 10944 | printSVERegOp<'q'>(MI, OpNum: 0, STI, O); |
| 10945 | O << ", "; |
| 10946 | break; |
| 10947 | case 30: |
| 10948 | // GLD1Q, LD1D_Q, LD1D_Q_IMM, LD1W_Q, LD1W_Q_IMM, LD2Q, LD2Q_IMM, LD3Q, L... |
| 10949 | printTypedVectorList<0,'q'>(MI, OpNum: 0, STI, O); |
| 10950 | O << ", "; |
| 10951 | break; |
| 10952 | case 31: |
| 10953 | // HINT, TENTER |
| 10954 | printImm(MI, OpNo: 0, STI, O); |
| 10955 | break; |
| 10956 | case 32: |
| 10957 | // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| 10958 | printMatrixTileVector<0>(MI, OpNum: 0, STI, O); |
| 10959 | O << '['; |
| 10960 | break; |
| 10961 | case 33: |
| 10962 | // INSERT_MXIPZ_V_B, INSERT_MXIPZ_V_D, INSERT_MXIPZ_V_H, INSERT_MXIPZ_V_Q... |
| 10963 | printMatrixTileVector<1>(MI, OpNum: 0, STI, O); |
| 10964 | O << '['; |
| 10965 | break; |
| 10966 | case 34: |
| 10967 | // LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LDNT1B_2Z_STRIDED, LDNT1B_2Z_STR... |
| 10968 | printTypedVectorList<0, 'b'>(MI, OpNum: 0, STI, O); |
| 10969 | break; |
| 10970 | case 35: |
| 10971 | // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... |
| 10972 | printTypedVectorList<16, 'b'>(MI, OpNum: 0, STI, O); |
| 10973 | O << ", ["; |
| 10974 | printOperand(MI, OpNo: 1, STI, O); |
| 10975 | O << ']'; |
| 10976 | return; |
| 10977 | break; |
| 10978 | case 36: |
| 10979 | // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... |
| 10980 | printTypedVectorList<16, 'b'>(MI, OpNum: 1, STI, O); |
| 10981 | O << ", ["; |
| 10982 | printOperand(MI, OpNo: 2, STI, O); |
| 10983 | O << "], "; |
| 10984 | break; |
| 10985 | case 37: |
| 10986 | // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... |
| 10987 | printTypedVectorList<1, 'd'>(MI, OpNum: 0, STI, O); |
| 10988 | O << ", ["; |
| 10989 | printOperand(MI, OpNo: 1, STI, O); |
| 10990 | O << ']'; |
| 10991 | return; |
| 10992 | break; |
| 10993 | case 38: |
| 10994 | // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... |
| 10995 | printTypedVectorList<1, 'd'>(MI, OpNum: 1, STI, O); |
| 10996 | O << ", ["; |
| 10997 | printOperand(MI, OpNo: 2, STI, O); |
| 10998 | O << "], "; |
| 10999 | break; |
| 11000 | case 39: |
| 11001 | // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... |
| 11002 | printTypedVectorList<2, 'd'>(MI, OpNum: 0, STI, O); |
| 11003 | O << ", ["; |
| 11004 | printOperand(MI, OpNo: 1, STI, O); |
| 11005 | O << ']'; |
| 11006 | return; |
| 11007 | break; |
| 11008 | case 40: |
| 11009 | // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... |
| 11010 | printTypedVectorList<2, 'd'>(MI, OpNum: 1, STI, O); |
| 11011 | O << ", ["; |
| 11012 | printOperand(MI, OpNo: 2, STI, O); |
| 11013 | O << "], "; |
| 11014 | break; |
| 11015 | case 41: |
| 11016 | // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... |
| 11017 | printTypedVectorList<2, 's'>(MI, OpNum: 0, STI, O); |
| 11018 | O << ", ["; |
| 11019 | printOperand(MI, OpNo: 1, STI, O); |
| 11020 | O << ']'; |
| 11021 | return; |
| 11022 | break; |
| 11023 | case 42: |
| 11024 | // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... |
| 11025 | printTypedVectorList<2, 's'>(MI, OpNum: 1, STI, O); |
| 11026 | O << ", ["; |
| 11027 | printOperand(MI, OpNo: 2, STI, O); |
| 11028 | O << "], "; |
| 11029 | break; |
| 11030 | case 43: |
| 11031 | // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... |
| 11032 | printTypedVectorList<4, 'h'>(MI, OpNum: 0, STI, O); |
| 11033 | O << ", ["; |
| 11034 | printOperand(MI, OpNo: 1, STI, O); |
| 11035 | O << ']'; |
| 11036 | return; |
| 11037 | break; |
| 11038 | case 44: |
| 11039 | // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... |
| 11040 | printTypedVectorList<4, 'h'>(MI, OpNum: 1, STI, O); |
| 11041 | O << ", ["; |
| 11042 | printOperand(MI, OpNo: 2, STI, O); |
| 11043 | O << "], "; |
| 11044 | break; |
| 11045 | case 45: |
| 11046 | // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... |
| 11047 | printTypedVectorList<4, 's'>(MI, OpNum: 0, STI, O); |
| 11048 | O << ", ["; |
| 11049 | printOperand(MI, OpNo: 1, STI, O); |
| 11050 | O << ']'; |
| 11051 | return; |
| 11052 | break; |
| 11053 | case 46: |
| 11054 | // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... |
| 11055 | printTypedVectorList<4, 's'>(MI, OpNum: 1, STI, O); |
| 11056 | O << ", ["; |
| 11057 | printOperand(MI, OpNo: 2, STI, O); |
| 11058 | O << "], "; |
| 11059 | break; |
| 11060 | case 47: |
| 11061 | // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... |
| 11062 | printTypedVectorList<8, 'b'>(MI, OpNum: 0, STI, O); |
| 11063 | O << ", ["; |
| 11064 | printOperand(MI, OpNo: 1, STI, O); |
| 11065 | O << ']'; |
| 11066 | return; |
| 11067 | break; |
| 11068 | case 48: |
| 11069 | // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... |
| 11070 | printTypedVectorList<8, 'b'>(MI, OpNum: 1, STI, O); |
| 11071 | O << ", ["; |
| 11072 | printOperand(MI, OpNo: 2, STI, O); |
| 11073 | O << "], "; |
| 11074 | break; |
| 11075 | case 49: |
| 11076 | // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... |
| 11077 | printTypedVectorList<8, 'h'>(MI, OpNum: 0, STI, O); |
| 11078 | O << ", ["; |
| 11079 | printOperand(MI, OpNo: 1, STI, O); |
| 11080 | O << ']'; |
| 11081 | return; |
| 11082 | break; |
| 11083 | case 50: |
| 11084 | // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... |
| 11085 | printTypedVectorList<8, 'h'>(MI, OpNum: 1, STI, O); |
| 11086 | O << ", ["; |
| 11087 | printOperand(MI, OpNo: 2, STI, O); |
| 11088 | O << "], "; |
| 11089 | break; |
| 11090 | case 51: |
| 11091 | // LD1H_2Z_STRIDED, LD1H_2Z_STRIDED_IMM, LDNT1H_2Z_STRIDED, LDNT1H_2Z_STR... |
| 11092 | printTypedVectorList<0, 'h'>(MI, OpNum: 0, STI, O); |
| 11093 | break; |
| 11094 | case 52: |
| 11095 | // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... |
| 11096 | printTypedVectorList<0, 'h'>(MI, OpNum: 1, STI, O); |
| 11097 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11098 | O << ", ["; |
| 11099 | printOperand(MI, OpNo: 3, STI, O); |
| 11100 | break; |
| 11101 | case 53: |
| 11102 | // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST |
| 11103 | printTypedVectorList<0, 'h'>(MI, OpNum: 2, STI, O); |
| 11104 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 11105 | O << ", ["; |
| 11106 | printOperand(MI, OpNo: 4, STI, O); |
| 11107 | O << "], "; |
| 11108 | break; |
| 11109 | case 54: |
| 11110 | // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... |
| 11111 | printTypedVectorList<0, 's'>(MI, OpNum: 1, STI, O); |
| 11112 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11113 | O << ", ["; |
| 11114 | printOperand(MI, OpNo: 3, STI, O); |
| 11115 | break; |
| 11116 | case 55: |
| 11117 | // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST |
| 11118 | printTypedVectorList<0, 's'>(MI, OpNum: 2, STI, O); |
| 11119 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 11120 | O << ", ["; |
| 11121 | printOperand(MI, OpNo: 4, STI, O); |
| 11122 | O << "], "; |
| 11123 | break; |
| 11124 | case 56: |
| 11125 | // LD1i64, LD2i64, LD3i64, LD4i64, LDAP1, ST1i64_POST, ST2i64_POST, ST3i6... |
| 11126 | printTypedVectorList<0, 'd'>(MI, OpNum: 1, STI, O); |
| 11127 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11128 | O << ", ["; |
| 11129 | printOperand(MI, OpNo: 3, STI, O); |
| 11130 | break; |
| 11131 | case 57: |
| 11132 | // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST |
| 11133 | printTypedVectorList<0, 'd'>(MI, OpNum: 2, STI, O); |
| 11134 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 11135 | O << ", ["; |
| 11136 | printOperand(MI, OpNo: 4, STI, O); |
| 11137 | O << "], "; |
| 11138 | break; |
| 11139 | case 58: |
| 11140 | // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... |
| 11141 | printTypedVectorList<0, 'b'>(MI, OpNum: 1, STI, O); |
| 11142 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11143 | O << ", ["; |
| 11144 | printOperand(MI, OpNo: 3, STI, O); |
| 11145 | break; |
| 11146 | case 59: |
| 11147 | // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST |
| 11148 | printTypedVectorList<0, 'b'>(MI, OpNum: 2, STI, O); |
| 11149 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 11150 | O << ", ["; |
| 11151 | printOperand(MI, OpNo: 4, STI, O); |
| 11152 | O << "], "; |
| 11153 | break; |
| 11154 | case 60: |
| 11155 | // LD64B, LDA64B, ST64B, STL64B |
| 11156 | printGPR64x8(MI, OpNum: 0, STI, O); |
| 11157 | O << ", ["; |
| 11158 | printOperand(MI, OpNo: 1, STI, O); |
| 11159 | O << ']'; |
| 11160 | return; |
| 11161 | break; |
| 11162 | case 61: |
| 11163 | // LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL... |
| 11164 | printOperand(MI, OpNo: 2, STI, O); |
| 11165 | break; |
| 11166 | case 62: |
| 11167 | // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PMOV_ZIP_B, PMOV_ZIP_D, PMOV_ZIP_H, PMOV... |
| 11168 | printSVERegOp<>(MI, OpNum: 0, STI, O); |
| 11169 | break; |
| 11170 | case 63: |
| 11171 | // LDR_ZA, STR_ZA |
| 11172 | printMatrix<0>(MI, OpNum: 0, STI, O); |
| 11173 | O << '['; |
| 11174 | printOperand(MI, OpNo: 1, STI, O); |
| 11175 | O << ", "; |
| 11176 | printMatrixIndex(MI, OpNum: 2, STI, O); |
| 11177 | O << "], ["; |
| 11178 | printOperand(MI, OpNo: 3, STI, O); |
| 11179 | O << ", "; |
| 11180 | printOperand(MI, OpNo: 4, STI, O); |
| 11181 | O << ", mul vl]"; |
| 11182 | return; |
| 11183 | break; |
| 11184 | case 64: |
| 11185 | // MRRS |
| 11186 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 0, STI, O); |
| 11187 | O << ", "; |
| 11188 | printMRSSystemRegister(MI, OpNum: 1, STI, O); |
| 11189 | return; |
| 11190 | break; |
| 11191 | case 65: |
| 11192 | // MSR, MSRR |
| 11193 | printMSRSystemRegister(MI, OpNum: 0, STI, O); |
| 11194 | O << ", "; |
| 11195 | break; |
| 11196 | case 66: |
| 11197 | // MSRpstateImm1, MSRpstateImm4 |
| 11198 | printSystemPStateField(MI, OpNum: 0, STI, O); |
| 11199 | O << ", "; |
| 11200 | printOperand(MI, OpNo: 1, STI, O); |
| 11201 | return; |
| 11202 | break; |
| 11203 | case 67: |
| 11204 | // MSRpstatesvcrImm1 |
| 11205 | printSVCROp(MI, OpNum: 0, STI, O); |
| 11206 | O << ", "; |
| 11207 | printOperand(MI, OpNo: 1, STI, O); |
| 11208 | return; |
| 11209 | break; |
| 11210 | case 68: |
| 11211 | // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... |
| 11212 | printPrefetchOp<true>(MI, OpNum: 0, STI, O); |
| 11213 | O << ", "; |
| 11214 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 11215 | O << ", ["; |
| 11216 | break; |
| 11217 | case 69: |
| 11218 | // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi |
| 11219 | printPrefetchOp(MI, OpNum: 0, STI, O); |
| 11220 | break; |
| 11221 | case 70: |
| 11222 | // PTRUE_C_B, WHILEGE_CXX_B, WHILEGT_CXX_B, WHILEHI_CXX_B, WHILEHS_CXX_B,... |
| 11223 | printPredicateAsCounter<8>(MI, OpNum: 0, STI, O); |
| 11224 | break; |
| 11225 | case 71: |
| 11226 | // PTRUE_C_D, WHILEGE_CXX_D, WHILEGT_CXX_D, WHILEHI_CXX_D, WHILEHS_CXX_D,... |
| 11227 | printPredicateAsCounter<64>(MI, OpNum: 0, STI, O); |
| 11228 | break; |
| 11229 | case 72: |
| 11230 | // PTRUE_C_H, WHILEGE_CXX_H, WHILEGT_CXX_H, WHILEHI_CXX_H, WHILEHS_CXX_H,... |
| 11231 | printPredicateAsCounter<16>(MI, OpNum: 0, STI, O); |
| 11232 | break; |
| 11233 | case 73: |
| 11234 | // PTRUE_C_S, WHILEGE_CXX_S, WHILEGT_CXX_S, WHILEHI_CXX_S, WHILEHS_CXX_S,... |
| 11235 | printPredicateAsCounter<32>(MI, OpNum: 0, STI, O); |
| 11236 | break; |
| 11237 | case 74: |
| 11238 | // RPRFM |
| 11239 | printRPRFMOperand(MI, OpNum: 0, STI, O); |
| 11240 | O << ", "; |
| 11241 | printOperand(MI, OpNo: 1, STI, O); |
| 11242 | O << ", ["; |
| 11243 | printOperand(MI, OpNo: 2, STI, O); |
| 11244 | O << ']'; |
| 11245 | return; |
| 11246 | break; |
| 11247 | case 75: |
| 11248 | // ST1i32, ST2i32, ST3i32, ST4i32 |
| 11249 | printTypedVectorList<0, 's'>(MI, OpNum: 0, STI, O); |
| 11250 | printVectorIndex(MI, OpNum: 1, STI, O); |
| 11251 | O << ", ["; |
| 11252 | printOperand(MI, OpNo: 2, STI, O); |
| 11253 | O << ']'; |
| 11254 | return; |
| 11255 | break; |
| 11256 | case 76: |
| 11257 | // ST1i64, ST2i64, ST3i64, ST4i64, STL1 |
| 11258 | printTypedVectorList<0, 'd'>(MI, OpNum: 0, STI, O); |
| 11259 | printVectorIndex(MI, OpNum: 1, STI, O); |
| 11260 | O << ", ["; |
| 11261 | printOperand(MI, OpNo: 2, STI, O); |
| 11262 | O << ']'; |
| 11263 | return; |
| 11264 | break; |
| 11265 | case 77: |
| 11266 | // TEXIT |
| 11267 | printTIndexHintOp(MI, OpNum: 0, STI, O); |
| 11268 | return; |
| 11269 | break; |
| 11270 | case 78: |
| 11271 | // ZERO_M |
| 11272 | printMatrixTileList(MI, OpNum: 0, STI, O); |
| 11273 | return; |
| 11274 | break; |
| 11275 | } |
| 11276 | |
| 11277 | |
| 11278 | // Fragment 1 encoded into 7 bits for 89 unique commands. |
| 11279 | switch ((Bits >> 21) & 127) { |
| 11280 | default: llvm_unreachable("Invalid command number."); |
| 11281 | case 0: |
| 11282 | // TLSAUTHDESCCALL, TLSDESCCALL, AUTDZA, AUTDZB, AUTIASPPCr, AUTIBSPPCr, ... |
| 11283 | return; |
| 11284 | break; |
| 11285 | case 1: |
| 11286 | // ABSWr, ABSXr, ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABS_ZPzZ_B, ABS_ZPzZ... |
| 11287 | O << ", "; |
| 11288 | break; |
| 11289 | case 2: |
| 11290 | // ABS_ZPmZ_H, ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, BF... |
| 11291 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 11292 | break; |
| 11293 | case 3: |
| 11294 | // ABS_ZPzZ_H, ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPm... |
| 11295 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 11296 | break; |
| 11297 | case 4: |
| 11298 | // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDQV_VPZ_B, ADDv16i8, AESDrr, ... |
| 11299 | O << ".16b, "; |
| 11300 | break; |
| 11301 | case 5: |
| 11302 | // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BF16DOTlanev4bf16, BF... |
| 11303 | O << ".2s, "; |
| 11304 | break; |
| 11305 | case 6: |
| 11306 | // ABSv2i64, ADDPv2i64, ADDQV_VPZ_D, ADDv2i64, ANDQV_VPZ_D, CMEQv2i64, CM... |
| 11307 | O << ".2d, "; |
| 11308 | break; |
| 11309 | case 7: |
| 11310 | // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BFCVTN, BICv4i16, CLS... |
| 11311 | O << ".4h, "; |
| 11312 | break; |
| 11313 | case 8: |
| 11314 | // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDQV_VPZ_S, ADDv4i32, ANDQV_VP... |
| 11315 | O << ".4s, "; |
| 11316 | break; |
| 11317 | case 9: |
| 11318 | // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDQV_VPZ_H, ADDv8i16, ANDQV_VP... |
| 11319 | O << ".8h, "; |
| 11320 | break; |
| 11321 | case 10: |
| 11322 | // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... |
| 11323 | O << ".8b, "; |
| 11324 | break; |
| 11325 | case 11: |
| 11326 | // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,... |
| 11327 | printSVERegOp<'s'>(MI, OpNum: 1, STI, O); |
| 11328 | break; |
| 11329 | case 12: |
| 11330 | // ADDHNT_ZZZ_H, ANDV_VPZ_S, EORV_VPZ_S, FADDV_VPZ_S, FCLAMP_VG2_2Z2Z_S, ... |
| 11331 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 11332 | break; |
| 11333 | case 13: |
| 11334 | // ADDQP_ZZZ_H, ADDSUBP_ZZZ_H, ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_Z... |
| 11335 | printSVERegOp<'h'>(MI, OpNum: 1, STI, O); |
| 11336 | break; |
| 11337 | case 14: |
| 11338 | // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, AESDIMC_2ZZI_B, AESDIMC_4ZZI_B, AESD_2ZZ... |
| 11339 | printTypedVectorList<0,'b'>(MI, OpNum: 1, STI, O); |
| 11340 | break; |
| 11341 | case 15: |
| 11342 | // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D... |
| 11343 | printTypedVectorList<0,'d'>(MI, OpNum: 1, STI, O); |
| 11344 | break; |
| 11345 | case 16: |
| 11346 | // ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG2_2ZZ_H, B... |
| 11347 | printTypedVectorList<0,'h'>(MI, OpNum: 1, STI, O); |
| 11348 | break; |
| 11349 | case 17: |
| 11350 | // ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, BFCVTN_Z2Z_StoH, BFCVT_Z2Z_StoH, FAMAX_2... |
| 11351 | printTypedVectorList<0,'s'>(MI, OpNum: 1, STI, O); |
| 11352 | break; |
| 11353 | case 18: |
| 11354 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_... |
| 11355 | printMatrixIndex(MI, OpNum: 3, STI, O); |
| 11356 | break; |
| 11357 | case 19: |
| 11358 | // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... |
| 11359 | O << ", ["; |
| 11360 | break; |
| 11361 | case 20: |
| 11362 | // ANDV_VPZ_D, EORV_VPZ_D, FADDV_VPZ_D, FCLAMP_VG2_2Z2Z_D, FCLAMP_VG4_4Z4... |
| 11363 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 11364 | break; |
| 11365 | case 21: |
| 11366 | // ANDV_VPZ_H, BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA... |
| 11367 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 11368 | break; |
| 11369 | case 22: |
| 11370 | // BCcc, Bcc |
| 11371 | printAlignedLabel(MI, Address, OpNum: 1, STI, O); |
| 11372 | return; |
| 11373 | break; |
| 11374 | case 23: |
| 11375 | // BF1CVTLT_ZZ_BtoH, BF1CVTL_2ZZ_BtoH, BF1CVT_2ZZ_BtoH, BF1CVT_ZZ_BtoH, B... |
| 11376 | printSVERegOp<'b'>(MI, OpNum: 1, STI, O); |
| 11377 | break; |
| 11378 | case 24: |
| 11379 | // BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLAL_VG2_M2Z2Z_HtoS, BFMLAL_VG2_M... |
| 11380 | printImmRangeScale<2, 1>(MI, OpNum: 3, STI, O); |
| 11381 | break; |
| 11382 | case 25: |
| 11383 | // BFMOP4A_M2Z2Z_H, BFMOP4A_M2Z2Z_S, BFMOP4A_M2ZZ_H, BFMOP4A_M2ZZ_S, BFMO... |
| 11384 | printTypedVectorList<0,'h'>(MI, OpNum: 2, STI, O); |
| 11385 | O << ", "; |
| 11386 | break; |
| 11387 | case 26: |
| 11388 | // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... |
| 11389 | printSVEPattern(MI, OpNum: 2, STI, O); |
| 11390 | O << ", mul "; |
| 11391 | printOperand(MI, OpNo: 3, STI, O); |
| 11392 | return; |
| 11393 | break; |
| 11394 | case 27: |
| 11395 | // DUP_ZI_H |
| 11396 | printImm8OptLsl<int16_t>(MI, OpNum: 1, STI, O); |
| 11397 | return; |
| 11398 | break; |
| 11399 | case 28: |
| 11400 | // DUP_ZR_H, FLTcc, INDEX_RI_H, INDEX_RR_H, LD1_MXIPXX_H_B, LD1_MXIPXX_H_... |
| 11401 | printOperand(MI, OpNo: 1, STI, O); |
| 11402 | break; |
| 11403 | case 29: |
| 11404 | // DUP_ZZI_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, UZP_VG2_2ZZ... |
| 11405 | printSVERegOp<'q'>(MI, OpNum: 1, STI, O); |
| 11406 | break; |
| 11407 | case 30: |
| 11408 | // FADDA_VPZ_D |
| 11409 | printZPRasFPR<64>(MI, OpNum: 2, STI, O); |
| 11410 | O << ", "; |
| 11411 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 11412 | return; |
| 11413 | break; |
| 11414 | case 31: |
| 11415 | // FADDA_VPZ_H, INSR_ZV_H |
| 11416 | printZPRasFPR<16>(MI, OpNum: 2, STI, O); |
| 11417 | break; |
| 11418 | case 32: |
| 11419 | // FADDA_VPZ_S |
| 11420 | printZPRasFPR<32>(MI, OpNum: 2, STI, O); |
| 11421 | O << ", "; |
| 11422 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 11423 | return; |
| 11424 | break; |
| 11425 | case 33: |
| 11426 | // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri |
| 11427 | O << ", #0.0"; |
| 11428 | return; |
| 11429 | break; |
| 11430 | case 34: |
| 11431 | // FDOT_ZZZI_BtoH, FDOT_ZZZ_BtoH, FMLALB_ZZZ, FMLALB_ZZZI, FMLALT_ZZZ, FM... |
| 11432 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 11433 | break; |
| 11434 | case 35: |
| 11435 | // FDUP_ZI_H |
| 11436 | printFPImmOperand(MI, OpNum: 1, STI, O); |
| 11437 | return; |
| 11438 | break; |
| 11439 | case 36: |
| 11440 | // FMLALL_MZZI_BtoS, FMLALL_MZZ_BtoS, FMLALL_VG2_M2Z2Z_BtoS, FMLALL_VG2_M... |
| 11441 | printImmRangeScale<4, 3>(MI, OpNum: 3, STI, O); |
| 11442 | break; |
| 11443 | case 37: |
| 11444 | // FMOP4A_M2Z2Z_BtoH, FMOP4A_M2Z2Z_BtoS, FMOP4A_M2ZZ_BtoH, FMOP4A_M2ZZ_Bt... |
| 11445 | printTypedVectorList<0,'b'>(MI, OpNum: 2, STI, O); |
| 11446 | O << ", "; |
| 11447 | break; |
| 11448 | case 38: |
| 11449 | // FMOP4A_M2Z2Z_D, FMOP4A_M2ZZ_D, FMOP4S_M2Z2Z_D, FMOP4S_M2ZZ_D |
| 11450 | printTypedVectorList<0,'d'>(MI, OpNum: 2, STI, O); |
| 11451 | O << ", "; |
| 11452 | break; |
| 11453 | case 39: |
| 11454 | // FMOP4A_M2Z2Z_S, FMOP4A_M2ZZ_S, FMOP4S_M2Z2Z_S, FMOP4S_M2ZZ_S, FTMOPA_M... |
| 11455 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 11456 | O << ", "; |
| 11457 | break; |
| 11458 | case 40: |
| 11459 | // FMOVXDHighr, INSvi64gpr, INSvi64lane |
| 11460 | O << ".d"; |
| 11461 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11462 | O << ", "; |
| 11463 | break; |
| 11464 | case 41: |
| 11465 | // INDEX_II_H, INDEX_IR_H |
| 11466 | printSImm<16>(MI, OpNo: 1, STI, O); |
| 11467 | O << ", "; |
| 11468 | break; |
| 11469 | case 42: |
| 11470 | // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| 11471 | printOperand(MI, OpNo: 2, STI, O); |
| 11472 | break; |
| 11473 | case 43: |
| 11474 | // INSvi16gpr, INSvi16lane |
| 11475 | O << ".h"; |
| 11476 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11477 | O << ", "; |
| 11478 | break; |
| 11479 | case 44: |
| 11480 | // INSvi32gpr, INSvi32lane |
| 11481 | O << ".s"; |
| 11482 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11483 | O << ", "; |
| 11484 | break; |
| 11485 | case 45: |
| 11486 | // INSvi8gpr, INSvi8lane |
| 11487 | O << ".b"; |
| 11488 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11489 | O << ", "; |
| 11490 | break; |
| 11491 | case 46: |
| 11492 | // LD1B_2Z, LD1B_2Z_IMM, LD1B_4Z, LD1B_4Z_IMM, LD1B_4Z_STRIDED, LD1B_4Z_S... |
| 11493 | printPredicateAsCounter<0>(MI, OpNum: 1, STI, O); |
| 11494 | break; |
| 11495 | case 47: |
| 11496 | // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... |
| 11497 | printPostIncOperand<64>(MI, OpNo: 3, STI, O); |
| 11498 | return; |
| 11499 | break; |
| 11500 | case 48: |
| 11501 | // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... |
| 11502 | printPostIncOperand<32>(MI, OpNo: 3, STI, O); |
| 11503 | return; |
| 11504 | break; |
| 11505 | case 49: |
| 11506 | // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... |
| 11507 | printPostIncOperand<16>(MI, OpNo: 3, STI, O); |
| 11508 | return; |
| 11509 | break; |
| 11510 | case 50: |
| 11511 | // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... |
| 11512 | printPostIncOperand<8>(MI, OpNo: 3, STI, O); |
| 11513 | return; |
| 11514 | break; |
| 11515 | case 51: |
| 11516 | // LD1Rv16b_POST, LD1Rv8b_POST |
| 11517 | printPostIncOperand<1>(MI, OpNo: 3, STI, O); |
| 11518 | return; |
| 11519 | break; |
| 11520 | case 52: |
| 11521 | // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... |
| 11522 | printPostIncOperand<4>(MI, OpNo: 3, STI, O); |
| 11523 | return; |
| 11524 | break; |
| 11525 | case 53: |
| 11526 | // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST |
| 11527 | printPostIncOperand<2>(MI, OpNo: 3, STI, O); |
| 11528 | return; |
| 11529 | break; |
| 11530 | case 54: |
| 11531 | // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... |
| 11532 | printPostIncOperand<48>(MI, OpNo: 3, STI, O); |
| 11533 | return; |
| 11534 | break; |
| 11535 | case 55: |
| 11536 | // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... |
| 11537 | printPostIncOperand<24>(MI, OpNo: 3, STI, O); |
| 11538 | return; |
| 11539 | break; |
| 11540 | case 56: |
| 11541 | // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... |
| 11542 | O << ']'; |
| 11543 | return; |
| 11544 | break; |
| 11545 | case 57: |
| 11546 | // LD1i16_POST, LD2i8_POST |
| 11547 | printPostIncOperand<2>(MI, OpNo: 5, STI, O); |
| 11548 | return; |
| 11549 | break; |
| 11550 | case 58: |
| 11551 | // LD1i32_POST, LD2i16_POST, LD4i8_POST |
| 11552 | printPostIncOperand<4>(MI, OpNo: 5, STI, O); |
| 11553 | return; |
| 11554 | break; |
| 11555 | case 59: |
| 11556 | // LD1i64_POST, LD2i32_POST, LD4i16_POST |
| 11557 | printPostIncOperand<8>(MI, OpNo: 5, STI, O); |
| 11558 | return; |
| 11559 | break; |
| 11560 | case 60: |
| 11561 | // LD1i8_POST |
| 11562 | printPostIncOperand<1>(MI, OpNo: 5, STI, O); |
| 11563 | return; |
| 11564 | break; |
| 11565 | case 61: |
| 11566 | // LD2i64_POST, LD4i32_POST |
| 11567 | printPostIncOperand<16>(MI, OpNo: 5, STI, O); |
| 11568 | return; |
| 11569 | break; |
| 11570 | case 62: |
| 11571 | // LD3Rv16b_POST, LD3Rv8b_POST |
| 11572 | printPostIncOperand<3>(MI, OpNo: 3, STI, O); |
| 11573 | return; |
| 11574 | break; |
| 11575 | case 63: |
| 11576 | // LD3Rv2s_POST, LD3Rv4s_POST |
| 11577 | printPostIncOperand<12>(MI, OpNo: 3, STI, O); |
| 11578 | return; |
| 11579 | break; |
| 11580 | case 64: |
| 11581 | // LD3Rv4h_POST, LD3Rv8h_POST |
| 11582 | printPostIncOperand<6>(MI, OpNo: 3, STI, O); |
| 11583 | return; |
| 11584 | break; |
| 11585 | case 65: |
| 11586 | // LD3i16_POST |
| 11587 | printPostIncOperand<6>(MI, OpNo: 5, STI, O); |
| 11588 | return; |
| 11589 | break; |
| 11590 | case 66: |
| 11591 | // LD3i32_POST |
| 11592 | printPostIncOperand<12>(MI, OpNo: 5, STI, O); |
| 11593 | return; |
| 11594 | break; |
| 11595 | case 67: |
| 11596 | // LD3i64_POST |
| 11597 | printPostIncOperand<24>(MI, OpNo: 5, STI, O); |
| 11598 | return; |
| 11599 | break; |
| 11600 | case 68: |
| 11601 | // LD3i8_POST |
| 11602 | printPostIncOperand<3>(MI, OpNo: 5, STI, O); |
| 11603 | return; |
| 11604 | break; |
| 11605 | case 69: |
| 11606 | // LD4i64_POST |
| 11607 | printPostIncOperand<32>(MI, OpNo: 5, STI, O); |
| 11608 | return; |
| 11609 | break; |
| 11610 | case 70: |
| 11611 | // MOPSSETGE, MOPSSETGEN, MOPSSETGET, MOPSSETGETN, SETE, SETEN, SETET, SE... |
| 11612 | O << "]!, "; |
| 11613 | printOperand(MI, OpNo: 3, STI, O); |
| 11614 | break; |
| 11615 | case 71: |
| 11616 | // MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_... |
| 11617 | printMatrixTileVector<0>(MI, OpNum: 2, STI, O); |
| 11618 | O << '['; |
| 11619 | printOperand(MI, OpNo: 3, STI, O); |
| 11620 | O << ", "; |
| 11621 | break; |
| 11622 | case 72: |
| 11623 | // MOVAZ_2ZMI_V_B, MOVAZ_2ZMI_V_D, MOVAZ_2ZMI_V_H, MOVAZ_2ZMI_V_S, MOVAZ_... |
| 11624 | printMatrixTileVector<1>(MI, OpNum: 2, STI, O); |
| 11625 | O << '['; |
| 11626 | printOperand(MI, OpNo: 3, STI, O); |
| 11627 | O << ", "; |
| 11628 | break; |
| 11629 | case 73: |
| 11630 | // MOVAZ_VG2_2ZMXI, MOVAZ_VG4_4ZMXI |
| 11631 | printMatrix<64>(MI, OpNum: 2, STI, O); |
| 11632 | O << '['; |
| 11633 | printOperand(MI, OpNo: 3, STI, O); |
| 11634 | O << ", "; |
| 11635 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 11636 | break; |
| 11637 | case 74: |
| 11638 | // MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZM... |
| 11639 | printMatrixTileVector<0>(MI, OpNum: 1, STI, O); |
| 11640 | O << '['; |
| 11641 | break; |
| 11642 | case 75: |
| 11643 | // MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q, MOVA_2ZMXI_V_B, MOVA_2ZMXI_V_D, MOVA_2ZM... |
| 11644 | printMatrixTileVector<1>(MI, OpNum: 1, STI, O); |
| 11645 | O << '['; |
| 11646 | break; |
| 11647 | case 76: |
| 11648 | // MOVA_VG2_2ZMXI, MOVA_VG4_4ZMXI |
| 11649 | printMatrix<64>(MI, OpNum: 1, STI, O); |
| 11650 | O << '['; |
| 11651 | printOperand(MI, OpNo: 2, STI, O); |
| 11652 | O << ", "; |
| 11653 | printMatrixIndex(MI, OpNum: 3, STI, O); |
| 11654 | break; |
| 11655 | case 77: |
| 11656 | // MOVT_TIX, MOVT_TIZ |
| 11657 | O << '['; |
| 11658 | break; |
| 11659 | case 78: |
| 11660 | // MSRR |
| 11661 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 1, STI, O); |
| 11662 | return; |
| 11663 | break; |
| 11664 | case 79: |
| 11665 | // PMOV_ZIP_B, PMOV_ZIP_D, PMOV_ZIP_H, PMOV_ZIP_S |
| 11666 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11667 | O << ", "; |
| 11668 | break; |
| 11669 | case 80: |
| 11670 | // PMULLB_ZZZ_Q, PMULLT_ZZZ_Q, PMULL_2ZZZ_Q, UZP_VG2_2ZZZ_D, ZIP_VG2_2ZZZ... |
| 11671 | printSVERegOp<'d'>(MI, OpNum: 1, STI, O); |
| 11672 | O << ", "; |
| 11673 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 11674 | return; |
| 11675 | break; |
| 11676 | case 81: |
| 11677 | // PMULLv1i64, PMULLv2i64 |
| 11678 | O << ".1q, "; |
| 11679 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 11680 | break; |
| 11681 | case 82: |
| 11682 | // PTRUES_H, PTRUE_H |
| 11683 | printSVEPattern(MI, OpNum: 1, STI, O); |
| 11684 | return; |
| 11685 | break; |
| 11686 | case 83: |
| 11687 | // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... |
| 11688 | O << ".1d, "; |
| 11689 | break; |
| 11690 | case 84: |
| 11691 | // ST1i16, ST1i8, ST2i16, ST2i8, ST3i16, ST3i8, ST4i16, ST4i8 |
| 11692 | printVectorIndex(MI, OpNum: 1, STI, O); |
| 11693 | O << ", ["; |
| 11694 | printOperand(MI, OpNo: 2, STI, O); |
| 11695 | O << ']'; |
| 11696 | return; |
| 11697 | break; |
| 11698 | case 85: |
| 11699 | // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... |
| 11700 | O << "], "; |
| 11701 | break; |
| 11702 | case 86: |
| 11703 | // STBFADD, STBFADDL, STBFMAX, STBFMAXL, STBFMAXNM, STBFMAXNML, STBFMIN, ... |
| 11704 | O << ", ["; |
| 11705 | printOperand(MI, OpNo: 1, STI, O); |
| 11706 | O << ']'; |
| 11707 | return; |
| 11708 | break; |
| 11709 | case 87: |
| 11710 | // UZP_VG4_4Z4Z_Q, ZIP_VG4_4Z4Z_Q |
| 11711 | printTypedVectorList<0,'q'>(MI, OpNum: 1, STI, O); |
| 11712 | return; |
| 11713 | break; |
| 11714 | case 88: |
| 11715 | // ZERO_T |
| 11716 | O << " }"; |
| 11717 | return; |
| 11718 | break; |
| 11719 | } |
| 11720 | |
| 11721 | |
| 11722 | // Fragment 2 encoded into 7 bits for 95 unique commands. |
| 11723 | switch ((Bits >> 28) & 127) { |
| 11724 | default: llvm_unreachable("Invalid command number."); |
| 11725 | case 0: |
| 11726 | // ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI,... |
| 11727 | printOperand(MI, OpNo: 1, STI, O); |
| 11728 | break; |
| 11729 | case 1: |
| 11730 | // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... |
| 11731 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 11732 | break; |
| 11733 | case 2: |
| 11734 | // ABS_ZPmZ_H, ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDP_ZPmZ_H, ADDVA_MPPZ_D, ADD... |
| 11735 | O << "/m, "; |
| 11736 | break; |
| 11737 | case 3: |
| 11738 | // ABS_ZPzZ_B, ABS_ZPzZ_D, ABS_ZPzZ_S, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPm... |
| 11739 | printSVERegOp<>(MI, OpNum: 1, STI, O); |
| 11740 | break; |
| 11741 | case 4: |
| 11742 | // ABS_ZPzZ_H, BFCVTNT_ZPzZ_StoH, BFCVT_ZPzZ_StoH, CLS_ZPzZ_H, CLZ_ZPzZ_H... |
| 11743 | O << "/z, "; |
| 11744 | break; |
| 11745 | case 5: |
| 11746 | // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| 11747 | printVRegOperand(MI, OpNo: 1, STI, O); |
| 11748 | break; |
| 11749 | case 6: |
| 11750 | // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z... |
| 11751 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 11752 | break; |
| 11753 | case 7: |
| 11754 | // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ... |
| 11755 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 11756 | break; |
| 11757 | case 8: |
| 11758 | // ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH... |
| 11759 | printSVERegOp<'h'>(MI, OpNum: 1, STI, O); |
| 11760 | break; |
| 11761 | case 9: |
| 11762 | // ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDQP_ZZZ_H, ADDSUBP_ZZZ_H, ADD_VG2_2ZZ_B,... |
| 11763 | O << ", "; |
| 11764 | break; |
| 11765 | case 10: |
| 11766 | // ADDHNB_ZZZ_S, ADDQP_ZZZ_D, ADDSUBP_ZZZ_D, ADD_ZI_D, ADD_ZZZ_CPA, ADD_Z... |
| 11767 | printSVERegOp<'d'>(MI, OpNum: 1, STI, O); |
| 11768 | break; |
| 11769 | case 11: |
| 11770 | // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT... |
| 11771 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 11772 | break; |
| 11773 | case 12: |
| 11774 | // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| 11775 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 11776 | break; |
| 11777 | case 13: |
| 11778 | // ADDQP_ZZZ_B, ADDSUBP_ZZZ_B, ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_... |
| 11779 | printSVERegOp<'b'>(MI, OpNum: 1, STI, O); |
| 11780 | break; |
| 11781 | case 14: |
| 11782 | // ADDQP_ZZZ_S, ADDSUBP_ZZZ_S, ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_... |
| 11783 | printSVERegOp<'s'>(MI, OpNum: 1, STI, O); |
| 11784 | break; |
| 11785 | case 15: |
| 11786 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_... |
| 11787 | O << ", vgx2], "; |
| 11788 | break; |
| 11789 | case 16: |
| 11790 | // ADD_VG4_M4Z4Z_D, ADD_VG4_M4Z4Z_S, ADD_VG4_M4ZZ_D, ADD_VG4_M4ZZ_S, ADD_... |
| 11791 | O << ", vgx4], "; |
| 11792 | break; |
| 11793 | case 17: |
| 11794 | // ADR, ADRP |
| 11795 | printAdrAdrpLabel(MI, Address, OpNum: 1, STI, O); |
| 11796 | return; |
| 11797 | break; |
| 11798 | case 18: |
| 11799 | // ANDV_VPZ_D, ANDV_VPZ_H, ANDV_VPZ_S, BF1CVTLT_ZZ_BtoH, BF1CVTL_2ZZ_BtoH... |
| 11800 | return; |
| 11801 | break; |
| 11802 | case 19: |
| 11803 | // AUTDA, AUTDB, AUTIA, AUTIB, BFMWri, BFMXri, CASAB, CASAH, CASALB, CASA... |
| 11804 | printOperand(MI, OpNo: 2, STI, O); |
| 11805 | break; |
| 11806 | case 20: |
| 11807 | // BFCVTN_Z2Z_HtoB, BFCVT_Z2Z_HtoB, FCVTN_Z2Z_HtoB, FCVTZSN_Z2Z_HtoB, FCV... |
| 11808 | printTypedVectorList<0,'h'>(MI, OpNum: 1, STI, O); |
| 11809 | break; |
| 11810 | case 21: |
| 11811 | // BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLSL_MZZI_HtoS, BFMLSL_MZZ_HtoS, ... |
| 11812 | O << "], "; |
| 11813 | break; |
| 11814 | case 22: |
| 11815 | // BFMOP4A_M2Z2Z_H, BFMOP4A_M2Z2Z_S, BFMOP4S_M2Z2Z_H, BFMOP4S_M2Z2Z_S, FM... |
| 11816 | printTypedVectorList<0,'h'>(MI, OpNum: 3, STI, O); |
| 11817 | return; |
| 11818 | break; |
| 11819 | case 23: |
| 11820 | // BFMOP4A_M2ZZ_H, BFMOP4A_M2ZZ_S, BFMOP4S_M2ZZ_H, BFMOP4S_M2ZZ_S, BFTMOP... |
| 11821 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 11822 | break; |
| 11823 | case 24: |
| 11824 | // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... |
| 11825 | printImm(MI, OpNo: 2, STI, O); |
| 11826 | printShifter(MI, OpNum: 3, STI, O); |
| 11827 | return; |
| 11828 | break; |
| 11829 | case 25: |
| 11830 | // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... |
| 11831 | printAlignedLabel(MI, Address, OpNum: 1, STI, O); |
| 11832 | return; |
| 11833 | break; |
| 11834 | case 26: |
| 11835 | // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, FDOT_ZZ... |
| 11836 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 11837 | O << ", "; |
| 11838 | break; |
| 11839 | case 27: |
| 11840 | // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... |
| 11841 | printSVEPattern(MI, OpNum: 1, STI, O); |
| 11842 | break; |
| 11843 | case 28: |
| 11844 | // CNTP_XCI_B |
| 11845 | printPredicateAsCounter<8>(MI, OpNum: 1, STI, O); |
| 11846 | O << ", "; |
| 11847 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 11848 | return; |
| 11849 | break; |
| 11850 | case 29: |
| 11851 | // CNTP_XCI_D |
| 11852 | printPredicateAsCounter<64>(MI, OpNum: 1, STI, O); |
| 11853 | O << ", "; |
| 11854 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 11855 | return; |
| 11856 | break; |
| 11857 | case 30: |
| 11858 | // CNTP_XCI_H |
| 11859 | printPredicateAsCounter<16>(MI, OpNum: 1, STI, O); |
| 11860 | O << ", "; |
| 11861 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 11862 | return; |
| 11863 | break; |
| 11864 | case 31: |
| 11865 | // CNTP_XCI_S |
| 11866 | printPredicateAsCounter<32>(MI, OpNum: 1, STI, O); |
| 11867 | O << ", "; |
| 11868 | printSVEVecLenSpecifier(MI, OpNum: 2, STI, O); |
| 11869 | return; |
| 11870 | break; |
| 11871 | case 32: |
| 11872 | // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... |
| 11873 | printSVEPattern(MI, OpNum: 2, STI, O); |
| 11874 | O << ", mul "; |
| 11875 | printOperand(MI, OpNo: 3, STI, O); |
| 11876 | return; |
| 11877 | break; |
| 11878 | case 33: |
| 11879 | // DUPM_ZI |
| 11880 | printLogicalImm<int64_t>(MI, OpNum: 1, STI, O); |
| 11881 | return; |
| 11882 | break; |
| 11883 | case 34: |
| 11884 | // DUPQ_ZZI_H, DUP_ZZI_H, DUP_ZZI_Q, PEXT_2PCI_B, PEXT_2PCI_D, PEXT_2PCI_... |
| 11885 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 11886 | return; |
| 11887 | break; |
| 11888 | case 35: |
| 11889 | // DUP_ZI_B |
| 11890 | printImm8OptLsl<int8_t>(MI, OpNum: 1, STI, O); |
| 11891 | return; |
| 11892 | break; |
| 11893 | case 36: |
| 11894 | // DUP_ZI_D |
| 11895 | printImm8OptLsl<int64_t>(MI, OpNum: 1, STI, O); |
| 11896 | return; |
| 11897 | break; |
| 11898 | case 37: |
| 11899 | // DUP_ZI_S |
| 11900 | printImm8OptLsl<int32_t>(MI, OpNum: 1, STI, O); |
| 11901 | return; |
| 11902 | break; |
| 11903 | case 38: |
| 11904 | // EXT_ZZI_B, LUTI2_ZZZI_B, LUTI4_ZZZI_B, LUTI6_Z2ZZ, TBLQ_ZZZ_B, TBL_ZZZ... |
| 11905 | printTypedVectorList<0,'b'>(MI, OpNum: 1, STI, O); |
| 11906 | O << ", "; |
| 11907 | break; |
| 11908 | case 39: |
| 11909 | // FCVTNB_Z2Z_StoB, FCVTN_Z4Z_StoB, FCVT_Z4Z_StoB, SQCVTN_Z4Z_StoB, SQCVT... |
| 11910 | printTypedVectorList<0,'s'>(MI, OpNum: 1, STI, O); |
| 11911 | break; |
| 11912 | case 40: |
| 11913 | // FCVTNT_Z2Z_StoB |
| 11914 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 11915 | return; |
| 11916 | break; |
| 11917 | case 41: |
| 11918 | // FCVTZSN_Z2Z_DtoS, FCVTZUN_Z2Z_DtoS, TBLQ_ZZZ_D, TBL_ZZZZ_D, TBL_ZZZ_D |
| 11919 | printTypedVectorList<0,'d'>(MI, OpNum: 1, STI, O); |
| 11920 | break; |
| 11921 | case 42: |
| 11922 | // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... |
| 11923 | printFPImmOperand(MI, OpNum: 1, STI, O); |
| 11924 | return; |
| 11925 | break; |
| 11926 | case 43: |
| 11927 | // FMLALL_VG2_M2ZZ_BtoS, SMLALL_VG2_M2ZZ_BtoS, SMLALL_VG2_M2ZZ_HtoD, SMLS... |
| 11928 | O << ", vgx2], "; |
| 11929 | break; |
| 11930 | case 44: |
| 11931 | // FMLALL_VG4_M4ZZ_BtoS, SMLALL_VG4_M4ZZ_BtoS, SMLALL_VG4_M4ZZ_HtoD, SMLS... |
| 11932 | O << ", vgx4], "; |
| 11933 | break; |
| 11934 | case 45: |
| 11935 | // FMOP4A_M2Z2Z_BtoH, FMOP4A_M2Z2Z_BtoS, SMOP4A_M2Z2Z_BToS, SMOP4S_M2Z2Z_... |
| 11936 | printTypedVectorList<0,'b'>(MI, OpNum: 3, STI, O); |
| 11937 | return; |
| 11938 | break; |
| 11939 | case 46: |
| 11940 | // FMOP4A_M2Z2Z_D, FMOP4S_M2Z2Z_D |
| 11941 | printTypedVectorList<0,'d'>(MI, OpNum: 3, STI, O); |
| 11942 | return; |
| 11943 | break; |
| 11944 | case 47: |
| 11945 | // FMOP4A_M2Z2Z_S, FMOP4S_M2Z2Z_S |
| 11946 | printTypedVectorList<0,'s'>(MI, OpNum: 3, STI, O); |
| 11947 | return; |
| 11948 | break; |
| 11949 | case 48: |
| 11950 | // FMOP4A_M2ZZ_BtoH, FMOP4A_M2ZZ_BtoS, FTMOPA_M2ZZZI_BtoH, FTMOPA_M2ZZZI_... |
| 11951 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 11952 | break; |
| 11953 | case 49: |
| 11954 | // FMOP4A_M2ZZ_D, FMOP4S_M2ZZ_D, PMOV_ZIP_D |
| 11955 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 11956 | return; |
| 11957 | break; |
| 11958 | case 50: |
| 11959 | // FMOP4A_M2ZZ_S, FMOP4S_M2ZZ_S, FTMOPA_M2ZZZI_StoS, PMOV_ZIP_S |
| 11960 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 11961 | break; |
| 11962 | case 51: |
| 11963 | // GLD1B_D, GLD1B_D_IMM, GLD1B_D_SXTW, GLD1B_D_UXTW, GLD1B_S_IMM, GLD1B_S... |
| 11964 | O << "/z, ["; |
| 11965 | break; |
| 11966 | case 52: |
| 11967 | // INDEX_II_B, INDEX_IR_B |
| 11968 | printSImm<8>(MI, OpNo: 1, STI, O); |
| 11969 | O << ", "; |
| 11970 | break; |
| 11971 | case 53: |
| 11972 | // INDEX_II_H |
| 11973 | printSImm<16>(MI, OpNo: 2, STI, O); |
| 11974 | return; |
| 11975 | break; |
| 11976 | case 54: |
| 11977 | // INSR_ZV_B |
| 11978 | printZPRasFPR<8>(MI, OpNum: 2, STI, O); |
| 11979 | return; |
| 11980 | break; |
| 11981 | case 55: |
| 11982 | // INSR_ZV_D |
| 11983 | printZPRasFPR<64>(MI, OpNum: 2, STI, O); |
| 11984 | return; |
| 11985 | break; |
| 11986 | case 56: |
| 11987 | // INSR_ZV_S |
| 11988 | printZPRasFPR<32>(MI, OpNum: 2, STI, O); |
| 11989 | return; |
| 11990 | break; |
| 11991 | case 57: |
| 11992 | // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr, LDCLRP, LDCLRPA, LDCLRP... |
| 11993 | printOperand(MI, OpNo: 3, STI, O); |
| 11994 | break; |
| 11995 | case 58: |
| 11996 | // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane |
| 11997 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 11998 | break; |
| 11999 | case 59: |
| 12000 | // LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED, LD1H_2Z_STRIDED... |
| 12001 | printPredicateAsCounter<0>(MI, OpNum: 1, STI, O); |
| 12002 | break; |
| 12003 | case 60: |
| 12004 | // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... |
| 12005 | printOperand(MI, OpNo: 0, STI, O); |
| 12006 | O << ", ["; |
| 12007 | printOperand(MI, OpNo: 2, STI, O); |
| 12008 | O << ']'; |
| 12009 | return; |
| 12010 | break; |
| 12011 | case 61: |
| 12012 | // LUT2_B, LUT4_B, TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two,... |
| 12013 | printTypedVectorList<16, 'b'>(MI, OpNum: 1, STI, O); |
| 12014 | O << ", "; |
| 12015 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 12016 | break; |
| 12017 | case 62: |
| 12018 | // LUT2_H, LUT4_H |
| 12019 | printTypedVectorList<8, 'h'>(MI, OpNum: 1, STI, O); |
| 12020 | O << ", "; |
| 12021 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 12022 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 12023 | return; |
| 12024 | break; |
| 12025 | case 63: |
| 12026 | // MOPSSETGE, MOPSSETGEN, MOPSSETGET, MOPSSETGETN, SETE, SETEN, SETET, SE... |
| 12027 | O << "!, "; |
| 12028 | printOperand(MI, OpNo: 4, STI, O); |
| 12029 | return; |
| 12030 | break; |
| 12031 | case 64: |
| 12032 | // MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_... |
| 12033 | printImmRangeScale<2, 1>(MI, OpNum: 4, STI, O); |
| 12034 | O << ']'; |
| 12035 | return; |
| 12036 | break; |
| 12037 | case 65: |
| 12038 | // MOVAZ_4ZMI_H_B, MOVAZ_4ZMI_H_D, MOVAZ_4ZMI_H_H, MOVAZ_4ZMI_H_S, MOVAZ_... |
| 12039 | printImmRangeScale<4, 3>(MI, OpNum: 4, STI, O); |
| 12040 | O << ']'; |
| 12041 | return; |
| 12042 | break; |
| 12043 | case 66: |
| 12044 | // MOVAZ_VG2_2ZMXI, MOVA_VG2_2ZMXI, ZERO_MXI_VG2_2Z, ZERO_MXI_VG2_4Z, ZER... |
| 12045 | O << ", vgx2]"; |
| 12046 | return; |
| 12047 | break; |
| 12048 | case 67: |
| 12049 | // MOVAZ_VG4_4ZMXI, MOVA_VG4_4ZMXI, ZERO_MXI_VG4_2Z, ZERO_MXI_VG4_4Z, ZER... |
| 12050 | O << ", vgx4]"; |
| 12051 | return; |
| 12052 | break; |
| 12053 | case 68: |
| 12054 | // MOVAZ_ZMI_H_B, MOVAZ_ZMI_H_D, MOVAZ_ZMI_H_S |
| 12055 | printMatrixTileVector<0>(MI, OpNum: 1, STI, O); |
| 12056 | O << '['; |
| 12057 | printOperand(MI, OpNo: 3, STI, O); |
| 12058 | O << ", "; |
| 12059 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 12060 | O << ']'; |
| 12061 | return; |
| 12062 | break; |
| 12063 | case 69: |
| 12064 | // MOVAZ_ZMI_V_B, MOVAZ_ZMI_V_D, MOVAZ_ZMI_V_S |
| 12065 | printMatrixTileVector<1>(MI, OpNum: 1, STI, O); |
| 12066 | O << '['; |
| 12067 | printOperand(MI, OpNo: 3, STI, O); |
| 12068 | O << ", "; |
| 12069 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 12070 | O << ']'; |
| 12071 | return; |
| 12072 | break; |
| 12073 | case 70: |
| 12074 | // MOVID, MOVIv2d_ns |
| 12075 | printSIMDType10Operand(MI, OpNum: 1, STI, O); |
| 12076 | return; |
| 12077 | break; |
| 12078 | case 71: |
| 12079 | // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... |
| 12080 | printImm(MI, OpNo: 1, STI, O); |
| 12081 | break; |
| 12082 | case 72: |
| 12083 | // MOVT_TIX |
| 12084 | printMatrixIndex<8>(MI, OpNum: 1, STI, O); |
| 12085 | O << "], "; |
| 12086 | printOperand(MI, OpNo: 2, STI, O); |
| 12087 | return; |
| 12088 | break; |
| 12089 | case 73: |
| 12090 | // MOVT_TIZ |
| 12091 | printMatrixIndex(MI, OpNum: 1, STI, O); |
| 12092 | O << ", mul vl], "; |
| 12093 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 12094 | return; |
| 12095 | break; |
| 12096 | case 74: |
| 12097 | // MRS |
| 12098 | printMRSSystemRegister(MI, OpNum: 1, STI, O); |
| 12099 | return; |
| 12100 | break; |
| 12101 | case 75: |
| 12102 | // PMULLv1i64 |
| 12103 | O << ".1d, "; |
| 12104 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 12105 | O << ".1d"; |
| 12106 | return; |
| 12107 | break; |
| 12108 | case 76: |
| 12109 | // PMULLv2i64 |
| 12110 | O << ".2d, "; |
| 12111 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 12112 | O << ".2d"; |
| 12113 | return; |
| 12114 | break; |
| 12115 | case 77: |
| 12116 | // SETGOE, SETGOEN, SETGOET, SETGOETN, SETGOM, SETGOMN, SETGOMT, SETGOMTN... |
| 12117 | O << '!'; |
| 12118 | return; |
| 12119 | break; |
| 12120 | case 78: |
| 12121 | // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... |
| 12122 | printGPR64as32(MI, OpNum: 1, STI, O); |
| 12123 | O << ", "; |
| 12124 | printSVEPattern(MI, OpNum: 2, STI, O); |
| 12125 | O << ", mul "; |
| 12126 | printOperand(MI, OpNo: 3, STI, O); |
| 12127 | return; |
| 12128 | break; |
| 12129 | case 79: |
| 12130 | // SST1B_D, SST1B_D_IMM, SST1B_D_SXTW, SST1B_D_UXTW, SST1B_S_IMM, SST1B_S... |
| 12131 | O << ", ["; |
| 12132 | break; |
| 12133 | case 80: |
| 12134 | // ST1i16_POST, ST2i8_POST |
| 12135 | printPostIncOperand<2>(MI, OpNo: 4, STI, O); |
| 12136 | return; |
| 12137 | break; |
| 12138 | case 81: |
| 12139 | // ST1i32_POST, ST2i16_POST, ST4i8_POST |
| 12140 | printPostIncOperand<4>(MI, OpNo: 4, STI, O); |
| 12141 | return; |
| 12142 | break; |
| 12143 | case 82: |
| 12144 | // ST1i64_POST, ST2i32_POST, ST4i16_POST |
| 12145 | printPostIncOperand<8>(MI, OpNo: 4, STI, O); |
| 12146 | return; |
| 12147 | break; |
| 12148 | case 83: |
| 12149 | // ST1i8_POST |
| 12150 | printPostIncOperand<1>(MI, OpNo: 4, STI, O); |
| 12151 | return; |
| 12152 | break; |
| 12153 | case 84: |
| 12154 | // ST2i64_POST, ST4i32_POST |
| 12155 | printPostIncOperand<16>(MI, OpNo: 4, STI, O); |
| 12156 | return; |
| 12157 | break; |
| 12158 | case 85: |
| 12159 | // ST3i16_POST |
| 12160 | printPostIncOperand<6>(MI, OpNo: 4, STI, O); |
| 12161 | return; |
| 12162 | break; |
| 12163 | case 86: |
| 12164 | // ST3i32_POST |
| 12165 | printPostIncOperand<12>(MI, OpNo: 4, STI, O); |
| 12166 | return; |
| 12167 | break; |
| 12168 | case 87: |
| 12169 | // ST3i64_POST |
| 12170 | printPostIncOperand<24>(MI, OpNo: 4, STI, O); |
| 12171 | return; |
| 12172 | break; |
| 12173 | case 88: |
| 12174 | // ST3i8_POST |
| 12175 | printPostIncOperand<3>(MI, OpNo: 4, STI, O); |
| 12176 | return; |
| 12177 | break; |
| 12178 | case 89: |
| 12179 | // ST4i64_POST |
| 12180 | printPostIncOperand<32>(MI, OpNo: 4, STI, O); |
| 12181 | return; |
| 12182 | break; |
| 12183 | case 90: |
| 12184 | // ST64BV, ST64BV0, STL64BV, STL64BV0 |
| 12185 | printGPR64x8(MI, OpNum: 1, STI, O); |
| 12186 | O << ", ["; |
| 12187 | printOperand(MI, OpNo: 2, STI, O); |
| 12188 | O << ']'; |
| 12189 | return; |
| 12190 | break; |
| 12191 | case 91: |
| 12192 | // SYSPxt, SYSPxt_XZR, SYSxt |
| 12193 | printSysCROperand(MI, OpNo: 1, STI, O); |
| 12194 | O << ", "; |
| 12195 | printSysCROperand(MI, OpNo: 2, STI, O); |
| 12196 | O << ", "; |
| 12197 | printOperand(MI, OpNo: 3, STI, O); |
| 12198 | O << ", "; |
| 12199 | break; |
| 12200 | case 92: |
| 12201 | // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... |
| 12202 | printTypedVectorList<16, 'b'>(MI, OpNum: 2, STI, O); |
| 12203 | O << ", "; |
| 12204 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 12205 | break; |
| 12206 | case 93: |
| 12207 | // TENTER |
| 12208 | printTIndexHintOp(MI, OpNum: 1, STI, O); |
| 12209 | return; |
| 12210 | break; |
| 12211 | case 94: |
| 12212 | // ZERO_MXI_2Z, ZERO_MXI_4Z |
| 12213 | O << ']'; |
| 12214 | return; |
| 12215 | break; |
| 12216 | } |
| 12217 | |
| 12218 | |
| 12219 | // Fragment 3 encoded into 8 bits for 130 unique commands. |
| 12220 | switch ((Bits >> 35) & 255) { |
| 12221 | default: llvm_unreachable("Invalid command number."); |
| 12222 | case 0: |
| 12223 | // ABSWr, ABSXr, ABSv1i64, AESIMC_ZZ_B, AESMC_ZZ_B, AUTDA, AUTDB, AUTIA, ... |
| 12224 | return; |
| 12225 | break; |
| 12226 | case 1: |
| 12227 | // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPm... |
| 12228 | O << "/m, "; |
| 12229 | break; |
| 12230 | case 2: |
| 12231 | // ABS_ZPmZ_H, BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA... |
| 12232 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 12233 | break; |
| 12234 | case 3: |
| 12235 | // ABS_ZPzZ_B, ABS_ZPzZ_D, ABS_ZPzZ_S, ANDS_PPzPP, AND_PPzPP, BICS_PPzPP,... |
| 12236 | O << "/z, "; |
| 12237 | break; |
| 12238 | case 4: |
| 12239 | // ABS_ZPzZ_H, ADDP_ZPmZ_H, ADDQP_ZZZ_H, ADDSUBP_ZZZ_H, ADD_VG2_2ZZ_H, AD... |
| 12240 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 12241 | break; |
| 12242 | case 5: |
| 12243 | // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, BF1CVTL2, BF2... |
| 12244 | O << ".16b"; |
| 12245 | return; |
| 12246 | break; |
| 12247 | case 6: |
| 12248 | // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... |
| 12249 | O << ".2s"; |
| 12250 | return; |
| 12251 | break; |
| 12252 | case 7: |
| 12253 | // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... |
| 12254 | O << ".2d"; |
| 12255 | return; |
| 12256 | break; |
| 12257 | case 8: |
| 12258 | // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT... |
| 12259 | O << ".4h"; |
| 12260 | return; |
| 12261 | break; |
| 12262 | case 9: |
| 12263 | // ABSv4i32, ADDVv4i32v, BFCVTN, BFCVTN2, CLSv4i32, CLZv4i32, FABSv4f32, ... |
| 12264 | O << ".4s"; |
| 12265 | return; |
| 12266 | break; |
| 12267 | case 10: |
| 12268 | // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT... |
| 12269 | O << ".8h"; |
| 12270 | return; |
| 12271 | break; |
| 12272 | case 11: |
| 12273 | // ABSv8i8, ADDVv8i8v, BF1CVTL, BF2CVTL, CLSv8i8, CLZv8i8, CNTv8i8, F1CVT... |
| 12274 | O << ".8b"; |
| 12275 | return; |
| 12276 | break; |
| 12277 | case 12: |
| 12278 | // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... |
| 12279 | O << ", "; |
| 12280 | break; |
| 12281 | case 13: |
| 12282 | // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, BFMOPA_MPPZZ, ... |
| 12283 | printSVERegOp<>(MI, OpNum: 3, STI, O); |
| 12284 | O << "/m, "; |
| 12285 | break; |
| 12286 | case 14: |
| 12287 | // ADDHNB_ZZZ_H, ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, BFCVT_ZPzZ_StoH, FCVT_ZPzZ... |
| 12288 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 12289 | break; |
| 12290 | case 15: |
| 12291 | // ADDHNT_ZZZ_H, BFCVTNT_ZPmZ, BFCVTNT_ZPzZ_StoH, BFCVT_ZPmZ, FCLAMP_VG2_... |
| 12292 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 12293 | return; |
| 12294 | break; |
| 12295 | case 16: |
| 12296 | // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... |
| 12297 | O << ".2d, "; |
| 12298 | break; |
| 12299 | case 17: |
| 12300 | // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... |
| 12301 | O << ".4s, "; |
| 12302 | break; |
| 12303 | case 18: |
| 12304 | // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BF16DOTlanev8b... |
| 12305 | O << ".8h, "; |
| 12306 | break; |
| 12307 | case 19: |
| 12308 | // ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL... |
| 12309 | O << ".16b, "; |
| 12310 | break; |
| 12311 | case 20: |
| 12312 | // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... |
| 12313 | O << ".2s, "; |
| 12314 | break; |
| 12315 | case 21: |
| 12316 | // ADDPv4i16, ADDv4i16, BF16DOTlanev4bf16, BFDOTv4bf16, CMEQv4i16, CMGEv4... |
| 12317 | O << ".4h, "; |
| 12318 | break; |
| 12319 | case 22: |
| 12320 | // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... |
| 12321 | O << ".8b, "; |
| 12322 | break; |
| 12323 | case 23: |
| 12324 | // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H... |
| 12325 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 12326 | return; |
| 12327 | break; |
| 12328 | case 24: |
| 12329 | // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, ASR_WIDE_ZZZ_H, FCVT_ZPzZ_DtoH, FMAXNM_V... |
| 12330 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 12331 | break; |
| 12332 | case 25: |
| 12333 | // ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V... |
| 12334 | printTypedVectorList<0,'d'>(MI, OpNum: 4, STI, O); |
| 12335 | break; |
| 12336 | case 26: |
| 12337 | // ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V... |
| 12338 | printTypedVectorList<0,'s'>(MI, OpNum: 4, STI, O); |
| 12339 | break; |
| 12340 | case 27: |
| 12341 | // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... |
| 12342 | printImm8OptLsl<uint16_t>(MI, OpNum: 2, STI, O); |
| 12343 | return; |
| 12344 | break; |
| 12345 | case 28: |
| 12346 | // AESDIMC_2ZZI_B, AESDIMC_4ZZI_B, AESD_2ZZI_B, AESD_4ZZI_B, AESEMC_2ZZI_... |
| 12347 | printSVERegOp<'q'>(MI, OpNum: 2, STI, O); |
| 12348 | break; |
| 12349 | case 29: |
| 12350 | // ASR_ZZI_H, GLD1B_D, GLD1B_D_SXTW, GLD1B_D_UXTW, GLD1B_S_SXTW, GLD1B_S_... |
| 12351 | printOperand(MI, OpNo: 2, STI, O); |
| 12352 | break; |
| 12353 | case 30: |
| 12354 | // BFADD_VG2_M2Z_H, BFADD_VG4_M4Z_H, BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG2_M2ZZ... |
| 12355 | printTypedVectorList<0,'h'>(MI, OpNum: 4, STI, O); |
| 12356 | break; |
| 12357 | case 31: |
| 12358 | // BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG4_4Z2Z_H, BFMAX_VG2_2Z2Z_H, BFMAX_VG4_4Z... |
| 12359 | printTypedVectorList<0,'h'>(MI, OpNum: 2, STI, O); |
| 12360 | break; |
| 12361 | case 32: |
| 12362 | // BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLSL_MZZI_HtoS, BFMLSL_MZZ_HtoS, ... |
| 12363 | printSVERegOp<'h'>(MI, OpNum: 4, STI, O); |
| 12364 | O << ", "; |
| 12365 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 12366 | break; |
| 12367 | case 33: |
| 12368 | // BFMOP4A_MZ2Z_H, BFMOP4A_MZ2Z_S, BFMOP4S_MZ2Z_H, BFMOP4S_MZ2Z_S, FMOP4A... |
| 12369 | printTypedVectorList<0,'h'>(MI, OpNum: 3, STI, O); |
| 12370 | return; |
| 12371 | break; |
| 12372 | case 34: |
| 12373 | // CASAB, CASAH, CASALB, CASALH, CASALTX, CASALW, CASALX, CASATX, CASAW, ... |
| 12374 | O << ", ["; |
| 12375 | break; |
| 12376 | case 35: |
| 12377 | // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, FDOT_ZZ... |
| 12378 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 12379 | break; |
| 12380 | case 36: |
| 12381 | // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz |
| 12382 | O << ".16b, #0"; |
| 12383 | return; |
| 12384 | break; |
| 12385 | case 37: |
| 12386 | // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz |
| 12387 | O << ", #0"; |
| 12388 | return; |
| 12389 | break; |
| 12390 | case 38: |
| 12391 | // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz |
| 12392 | O << ".2s, #0"; |
| 12393 | return; |
| 12394 | break; |
| 12395 | case 39: |
| 12396 | // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz |
| 12397 | O << ".2d, #0"; |
| 12398 | return; |
| 12399 | break; |
| 12400 | case 40: |
| 12401 | // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz |
| 12402 | O << ".4h, #0"; |
| 12403 | return; |
| 12404 | break; |
| 12405 | case 41: |
| 12406 | // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz |
| 12407 | O << ".4s, #0"; |
| 12408 | return; |
| 12409 | break; |
| 12410 | case 42: |
| 12411 | // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz |
| 12412 | O << ".8h, #0"; |
| 12413 | return; |
| 12414 | break; |
| 12415 | case 43: |
| 12416 | // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz |
| 12417 | O << ".8b, #0"; |
| 12418 | return; |
| 12419 | break; |
| 12420 | case 44: |
| 12421 | // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI |
| 12422 | O << ", mul "; |
| 12423 | printOperand(MI, OpNo: 2, STI, O); |
| 12424 | return; |
| 12425 | break; |
| 12426 | case 45: |
| 12427 | // CPY_ZPmI_H |
| 12428 | printImm8OptLsl<int16_t>(MI, OpNum: 3, STI, O); |
| 12429 | return; |
| 12430 | break; |
| 12431 | case 46: |
| 12432 | // CPY_ZPmR_H, CPY_ZPmV_H, PRFB_D_PZI, PRFB_PRI, PRFB_S_PZI, PRFD_PRI, PR... |
| 12433 | printOperand(MI, OpNo: 3, STI, O); |
| 12434 | break; |
| 12435 | case 47: |
| 12436 | // CPY_ZPzI_H |
| 12437 | printImm8OptLsl<int16_t>(MI, OpNum: 2, STI, O); |
| 12438 | return; |
| 12439 | break; |
| 12440 | case 48: |
| 12441 | // DUPQ_ZZI_B, DUPQ_ZZI_D, DUPQ_ZZI_S, DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S, P... |
| 12442 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 12443 | return; |
| 12444 | break; |
| 12445 | case 49: |
| 12446 | // DUPi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... |
| 12447 | O << ".h"; |
| 12448 | break; |
| 12449 | case 50: |
| 12450 | // DUPi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, SMOVvi3... |
| 12451 | O << ".s"; |
| 12452 | break; |
| 12453 | case 51: |
| 12454 | // DUPi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64, UMOVvi64_idx... |
| 12455 | O << ".d"; |
| 12456 | break; |
| 12457 | case 52: |
| 12458 | // DUPi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to32... |
| 12459 | O << ".b"; |
| 12460 | break; |
| 12461 | case 53: |
| 12462 | // EXTRACT_ZPMXI_H_H, EXTRACT_ZPMXI_H_Q |
| 12463 | printMatrixTileVector<0>(MI, OpNum: 3, STI, O); |
| 12464 | O << '['; |
| 12465 | printOperand(MI, OpNo: 4, STI, O); |
| 12466 | O << ", "; |
| 12467 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 12468 | O << ']'; |
| 12469 | return; |
| 12470 | break; |
| 12471 | case 54: |
| 12472 | // EXTRACT_ZPMXI_V_H, EXTRACT_ZPMXI_V_Q |
| 12473 | printMatrixTileVector<1>(MI, OpNum: 3, STI, O); |
| 12474 | O << '['; |
| 12475 | printOperand(MI, OpNo: 4, STI, O); |
| 12476 | O << ", "; |
| 12477 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 12478 | O << ']'; |
| 12479 | return; |
| 12480 | break; |
| 12481 | case 55: |
| 12482 | // EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H |
| 12483 | printImm(MI, OpNo: 2, STI, O); |
| 12484 | return; |
| 12485 | break; |
| 12486 | case 56: |
| 12487 | // FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p |
| 12488 | O << ".2h"; |
| 12489 | return; |
| 12490 | break; |
| 12491 | case 57: |
| 12492 | // FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D, FAMIN_4Z4Z_D, FMAXNM_VG2_2Z2... |
| 12493 | printTypedVectorList<0,'d'>(MI, OpNum: 2, STI, O); |
| 12494 | break; |
| 12495 | case 58: |
| 12496 | // FAMAX_2Z2Z_S, FAMAX_4Z4Z_S, FAMIN_2Z2Z_S, FAMIN_4Z4Z_S, FMAXNM_VG2_2Z2... |
| 12497 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 12498 | break; |
| 12499 | case 59: |
| 12500 | // FCLAMP_VG2_2Z2Z_D, FCLAMP_VG4_4Z4Z_D, FCVT_ZPmZ_DtoH, FMOP4A_MZZ_D, FM... |
| 12501 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 12502 | return; |
| 12503 | break; |
| 12504 | case 60: |
| 12505 | // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ... |
| 12506 | O << ", #0.0"; |
| 12507 | return; |
| 12508 | break; |
| 12509 | case 61: |
| 12510 | // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz |
| 12511 | O << ".2s, #0.0"; |
| 12512 | return; |
| 12513 | break; |
| 12514 | case 62: |
| 12515 | // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz |
| 12516 | O << ".2d, #0.0"; |
| 12517 | return; |
| 12518 | break; |
| 12519 | case 63: |
| 12520 | // FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz |
| 12521 | O << ".4h, #0.0"; |
| 12522 | return; |
| 12523 | break; |
| 12524 | case 64: |
| 12525 | // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz |
| 12526 | O << ".4s, #0.0"; |
| 12527 | return; |
| 12528 | break; |
| 12529 | case 65: |
| 12530 | // FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz |
| 12531 | O << ".8h, #0.0"; |
| 12532 | return; |
| 12533 | break; |
| 12534 | case 66: |
| 12535 | // FCPY_ZPmI_H |
| 12536 | printFPImmOperand(MI, OpNum: 3, STI, O); |
| 12537 | return; |
| 12538 | break; |
| 12539 | case 67: |
| 12540 | // FDOT_VG2_M2Z2Z_BtoH, FDOT_VG2_M2Z2Z_BtoS, FDOT_VG2_M2ZZI_BtoH, FDOT_VG... |
| 12541 | printTypedVectorList<0,'b'>(MI, OpNum: 4, STI, O); |
| 12542 | O << ", "; |
| 12543 | break; |
| 12544 | case 68: |
| 12545 | // FMLAL2lanev4f16, FMLAL2v4f16, FMLALlanev4f16, FMLALv4f16, FMLSL2lanev4... |
| 12546 | O << ".2h, "; |
| 12547 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 12548 | break; |
| 12549 | case 69: |
| 12550 | // FMLALL_MZZI_BtoS, FMLALL_MZZ_BtoS, FMLAL_MZZI_BtoH, FMLAL_VG2_MZZ_BtoH... |
| 12551 | printSVERegOp<'b'>(MI, OpNum: 4, STI, O); |
| 12552 | O << ", "; |
| 12553 | printSVERegOp<'b'>(MI, OpNum: 5, STI, O); |
| 12554 | break; |
| 12555 | case 70: |
| 12556 | // FMOP4A_MZ2Z_BtoH, FMOP4A_MZ2Z_BtoS, SMOP4A_MZ2Z_BToS, SMOP4S_MZ2Z_BToS... |
| 12557 | printTypedVectorList<0,'b'>(MI, OpNum: 3, STI, O); |
| 12558 | return; |
| 12559 | break; |
| 12560 | case 71: |
| 12561 | // FMOP4A_MZ2Z_D, FMOP4S_MZ2Z_D |
| 12562 | printTypedVectorList<0,'d'>(MI, OpNum: 3, STI, O); |
| 12563 | return; |
| 12564 | break; |
| 12565 | case 72: |
| 12566 | // FMOP4A_MZ2Z_S, FMOP4S_MZ2Z_S |
| 12567 | printTypedVectorList<0,'s'>(MI, OpNum: 3, STI, O); |
| 12568 | return; |
| 12569 | break; |
| 12570 | case 73: |
| 12571 | // GCSSTR, GCSSTTR, LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, ... |
| 12572 | O << ']'; |
| 12573 | return; |
| 12574 | break; |
| 12575 | case 74: |
| 12576 | // INDEX_II_B |
| 12577 | printSImm<8>(MI, OpNo: 2, STI, O); |
| 12578 | return; |
| 12579 | break; |
| 12580 | case 75: |
| 12581 | // INDEX_RI_H |
| 12582 | printSImm<16>(MI, OpNo: 2, STI, O); |
| 12583 | return; |
| 12584 | break; |
| 12585 | case 76: |
| 12586 | // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| 12587 | printMatrixIndex(MI, OpNum: 3, STI, O); |
| 12588 | O << "], "; |
| 12589 | printSVERegOp<>(MI, OpNum: 4, STI, O); |
| 12590 | O << "/m, "; |
| 12591 | break; |
| 12592 | case 77: |
| 12593 | // LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED, LD1H_2Z_STRIDED... |
| 12594 | O << "/z, ["; |
| 12595 | printOperand(MI, OpNo: 2, STI, O); |
| 12596 | O << ", "; |
| 12597 | break; |
| 12598 | case 78: |
| 12599 | // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... |
| 12600 | printMatrixIndex(MI, OpNum: 2, STI, O); |
| 12601 | O << "]}, "; |
| 12602 | printSVERegOp<>(MI, OpNum: 3, STI, O); |
| 12603 | break; |
| 12604 | case 79: |
| 12605 | // LDAPRWpost |
| 12606 | O << "], #4"; |
| 12607 | return; |
| 12608 | break; |
| 12609 | case 80: |
| 12610 | // LDAPRXpost |
| 12611 | O << "], #8"; |
| 12612 | return; |
| 12613 | break; |
| 12614 | case 81: |
| 12615 | // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... |
| 12616 | O << "], "; |
| 12617 | break; |
| 12618 | case 82: |
| 12619 | // LUT2_B, LUT4_B |
| 12620 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 12621 | return; |
| 12622 | break; |
| 12623 | case 83: |
| 12624 | // LUTI2_2ZTZI_B, LUTI2_2ZTZI_H, LUTI2_2ZTZI_S, LUTI2_4ZTZI_B, LUTI2_4ZTZ... |
| 12625 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 12626 | break; |
| 12627 | case 84: |
| 12628 | // LUTI4_4ZZT2Z, LUTI4_S_4ZZT2Z, LUTI6_4Z2Z2ZI, LUTI6_4ZT3Z, LUTI6_S_4Z2Z... |
| 12629 | printTypedVectorList<0,0>(MI, OpNum: 2, STI, O); |
| 12630 | break; |
| 12631 | case 85: |
| 12632 | // MOVA_MXI2Z_H_B, MOVA_MXI2Z_H_D, MOVA_MXI2Z_H_H, MOVA_MXI2Z_H_S, MOVA_M... |
| 12633 | printImmRangeScale<2, 1>(MI, OpNum: 3, STI, O); |
| 12634 | O << "], "; |
| 12635 | break; |
| 12636 | case 86: |
| 12637 | // MOVA_MXI4Z_H_B, MOVA_MXI4Z_H_D, MOVA_MXI4Z_H_H, MOVA_MXI4Z_H_S, MOVA_M... |
| 12638 | printImmRangeScale<4, 3>(MI, OpNum: 3, STI, O); |
| 12639 | O << "], "; |
| 12640 | break; |
| 12641 | case 87: |
| 12642 | // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... |
| 12643 | printShifter(MI, OpNum: 2, STI, O); |
| 12644 | return; |
| 12645 | break; |
| 12646 | case 88: |
| 12647 | // MOVT_XTI |
| 12648 | O << '['; |
| 12649 | printMatrixIndex<8>(MI, OpNum: 2, STI, O); |
| 12650 | O << ']'; |
| 12651 | return; |
| 12652 | break; |
| 12653 | case 89: |
| 12654 | // PRFB_D_SCALED |
| 12655 | printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 12656 | O << ']'; |
| 12657 | return; |
| 12658 | break; |
| 12659 | case 90: |
| 12660 | // PRFB_D_SXTW_SCALED |
| 12661 | printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 12662 | O << ']'; |
| 12663 | return; |
| 12664 | break; |
| 12665 | case 91: |
| 12666 | // PRFB_D_UXTW_SCALED |
| 12667 | printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 12668 | O << ']'; |
| 12669 | return; |
| 12670 | break; |
| 12671 | case 92: |
| 12672 | // PRFB_PRR |
| 12673 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 12674 | O << ']'; |
| 12675 | return; |
| 12676 | break; |
| 12677 | case 93: |
| 12678 | // PRFB_S_SXTW_SCALED |
| 12679 | printRegWithShiftExtend<true, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 12680 | O << ']'; |
| 12681 | return; |
| 12682 | break; |
| 12683 | case 94: |
| 12684 | // PRFB_S_UXTW_SCALED |
| 12685 | printRegWithShiftExtend<false, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 12686 | O << ']'; |
| 12687 | return; |
| 12688 | break; |
| 12689 | case 95: |
| 12690 | // PRFD_D_PZI, PRFD_S_PZI |
| 12691 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 12692 | O << ']'; |
| 12693 | return; |
| 12694 | break; |
| 12695 | case 96: |
| 12696 | // PRFD_D_SCALED |
| 12697 | printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 12698 | O << ']'; |
| 12699 | return; |
| 12700 | break; |
| 12701 | case 97: |
| 12702 | // PRFD_D_SXTW_SCALED |
| 12703 | printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 12704 | O << ']'; |
| 12705 | return; |
| 12706 | break; |
| 12707 | case 98: |
| 12708 | // PRFD_D_UXTW_SCALED |
| 12709 | printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 12710 | O << ']'; |
| 12711 | return; |
| 12712 | break; |
| 12713 | case 99: |
| 12714 | // PRFD_PRR |
| 12715 | printRegWithShiftExtend<false, 64, 'x', 0>(MI, OpNum: 3, STI, O); |
| 12716 | O << ']'; |
| 12717 | return; |
| 12718 | break; |
| 12719 | case 100: |
| 12720 | // PRFD_S_SXTW_SCALED |
| 12721 | printRegWithShiftExtend<true, 64, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 12722 | O << ']'; |
| 12723 | return; |
| 12724 | break; |
| 12725 | case 101: |
| 12726 | // PRFD_S_UXTW_SCALED |
| 12727 | printRegWithShiftExtend<false, 64, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 12728 | O << ']'; |
| 12729 | return; |
| 12730 | break; |
| 12731 | case 102: |
| 12732 | // PRFH_D_PZI, PRFH_S_PZI |
| 12733 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 12734 | O << ']'; |
| 12735 | return; |
| 12736 | break; |
| 12737 | case 103: |
| 12738 | // PRFH_D_SCALED |
| 12739 | printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 12740 | O << ']'; |
| 12741 | return; |
| 12742 | break; |
| 12743 | case 104: |
| 12744 | // PRFH_D_SXTW_SCALED |
| 12745 | printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 12746 | O << ']'; |
| 12747 | return; |
| 12748 | break; |
| 12749 | case 105: |
| 12750 | // PRFH_D_UXTW_SCALED |
| 12751 | printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 12752 | O << ']'; |
| 12753 | return; |
| 12754 | break; |
| 12755 | case 106: |
| 12756 | // PRFH_PRR |
| 12757 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 12758 | O << ']'; |
| 12759 | return; |
| 12760 | break; |
| 12761 | case 107: |
| 12762 | // PRFH_S_SXTW_SCALED |
| 12763 | printRegWithShiftExtend<true, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 12764 | O << ']'; |
| 12765 | return; |
| 12766 | break; |
| 12767 | case 108: |
| 12768 | // PRFH_S_UXTW_SCALED |
| 12769 | printRegWithShiftExtend<false, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 12770 | O << ']'; |
| 12771 | return; |
| 12772 | break; |
| 12773 | case 109: |
| 12774 | // PRFW_D_PZI, PRFW_S_PZI |
| 12775 | printImmScale<4>(MI, OpNum: 3, STI, O); |
| 12776 | O << ']'; |
| 12777 | return; |
| 12778 | break; |
| 12779 | case 110: |
| 12780 | // PRFW_D_SCALED |
| 12781 | printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 12782 | O << ']'; |
| 12783 | return; |
| 12784 | break; |
| 12785 | case 111: |
| 12786 | // PRFW_D_SXTW_SCALED |
| 12787 | printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 12788 | O << ']'; |
| 12789 | return; |
| 12790 | break; |
| 12791 | case 112: |
| 12792 | // PRFW_D_UXTW_SCALED |
| 12793 | printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 12794 | O << ']'; |
| 12795 | return; |
| 12796 | break; |
| 12797 | case 113: |
| 12798 | // PRFW_PRR |
| 12799 | printRegWithShiftExtend<false, 32, 'x', 0>(MI, OpNum: 3, STI, O); |
| 12800 | O << ']'; |
| 12801 | return; |
| 12802 | break; |
| 12803 | case 114: |
| 12804 | // PRFW_S_SXTW_SCALED |
| 12805 | printRegWithShiftExtend<true, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 12806 | O << ']'; |
| 12807 | return; |
| 12808 | break; |
| 12809 | case 115: |
| 12810 | // PRFW_S_UXTW_SCALED |
| 12811 | printRegWithShiftExtend<false, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 12812 | O << ']'; |
| 12813 | return; |
| 12814 | break; |
| 12815 | case 116: |
| 12816 | // RDFFRS_PPz, RDFFR_PPz |
| 12817 | O << "/z"; |
| 12818 | return; |
| 12819 | break; |
| 12820 | case 117: |
| 12821 | // REVD_ZPmZ |
| 12822 | printSVERegOp<'q'>(MI, OpNum: 3, STI, O); |
| 12823 | return; |
| 12824 | break; |
| 12825 | case 118: |
| 12826 | // SEL_VG2_2ZC2Z2Z_B, SEL_VG4_4ZC4Z4Z_B, SMAX_VG2_2Z2Z_B, SMAX_VG4_4Z4Z_B... |
| 12827 | printTypedVectorList<0,'b'>(MI, OpNum: 2, STI, O); |
| 12828 | break; |
| 12829 | case 119: |
| 12830 | // SHLLv16i8 |
| 12831 | O << ".16b, #8"; |
| 12832 | return; |
| 12833 | break; |
| 12834 | case 120: |
| 12835 | // SHLLv2i32 |
| 12836 | O << ".2s, #32"; |
| 12837 | return; |
| 12838 | break; |
| 12839 | case 121: |
| 12840 | // SHLLv4i16 |
| 12841 | O << ".4h, #16"; |
| 12842 | return; |
| 12843 | break; |
| 12844 | case 122: |
| 12845 | // SHLLv4i32 |
| 12846 | O << ".4s, #32"; |
| 12847 | return; |
| 12848 | break; |
| 12849 | case 123: |
| 12850 | // SHLLv8i16 |
| 12851 | O << ".8h, #16"; |
| 12852 | return; |
| 12853 | break; |
| 12854 | case 124: |
| 12855 | // SHLLv8i8 |
| 12856 | O << ".8b, #8"; |
| 12857 | return; |
| 12858 | break; |
| 12859 | case 125: |
| 12860 | // STLRWpre |
| 12861 | O << ", #-4]!"; |
| 12862 | return; |
| 12863 | break; |
| 12864 | case 126: |
| 12865 | // STLRXpre |
| 12866 | O << ", #-8]!"; |
| 12867 | return; |
| 12868 | break; |
| 12869 | case 127: |
| 12870 | // SYSPxt |
| 12871 | printGPRSeqPairsClassOperand<64>(MI, OpNum: 4, STI, O); |
| 12872 | return; |
| 12873 | break; |
| 12874 | case 128: |
| 12875 | // SYSPxt_XZR |
| 12876 | printSyspXzrPair(MI, OpNum: 4, STI, O); |
| 12877 | return; |
| 12878 | break; |
| 12879 | case 129: |
| 12880 | // SYSxt |
| 12881 | printOperand(MI, OpNo: 4, STI, O); |
| 12882 | return; |
| 12883 | break; |
| 12884 | } |
| 12885 | |
| 12886 | |
| 12887 | // Fragment 4 encoded into 7 bits for 99 unique commands. |
| 12888 | switch ((Bits >> 43) & 127) { |
| 12889 | default: llvm_unreachable("Invalid command number."); |
| 12890 | case 0: |
| 12891 | // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, CLZ_ZPmZ_B, CNOT_ZPmZ_B,... |
| 12892 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 12893 | break; |
| 12894 | case 1: |
| 12895 | // ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CLS_ZPmZ_D, CLZ_ZP... |
| 12896 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 12897 | break; |
| 12898 | case 2: |
| 12899 | // ABS_ZPmZ_H, ABS_ZPzZ_H, ADDHNB_ZZZ_H, ADDQP_ZZZ_H, ADDSUBP_ZZZ_H, ADD_... |
| 12900 | return; |
| 12901 | break; |
| 12902 | case 3: |
| 12903 | // ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, CLS_ZPmZ_S, CLZ_ZPmZ_S, CMLA_ZZZ... |
| 12904 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 12905 | break; |
| 12906 | case 4: |
| 12907 | // ABS_ZPzZ_B, ADDP_ZPmZ_B, ADDQP_ZZZ_B, ADDQV_VPZ_B, ADDSUBP_ZZZ_B, ADD_... |
| 12908 | printSVERegOp<'b'>(MI, OpNum: 2, STI, O); |
| 12909 | break; |
| 12910 | case 5: |
| 12911 | // ABS_ZPzZ_D, ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADDQP_ZZZ_D, ADDQV_VPZ_D, ADDSU... |
| 12912 | printSVERegOp<'d'>(MI, OpNum: 2, STI, O); |
| 12913 | break; |
| 12914 | case 6: |
| 12915 | // ABS_ZPzZ_S, ADDP_ZPmZ_S, ADDQP_ZZZ_S, ADDQV_VPZ_S, ADDSUBP_ZZZ_S, ADD_... |
| 12916 | printSVERegOp<'s'>(MI, OpNum: 2, STI, O); |
| 12917 | break; |
| 12918 | case 7: |
| 12919 | // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDPT_shift, ADDSPL_XXI, ADDS... |
| 12920 | printOperand(MI, OpNo: 2, STI, O); |
| 12921 | break; |
| 12922 | case 8: |
| 12923 | // ADDG, ST2Gi, STGi, STZ2Gi, STZGi, SUBG |
| 12924 | printImmScale<16>(MI, OpNum: 2, STI, O); |
| 12925 | break; |
| 12926 | case 9: |
| 12927 | // ADDHA_MPPZ_D, ADDVA_MPPZ_D, FMOPA_MPPZZ_D, FMOPS_MPPZZ_D |
| 12928 | printSVERegOp<'d'>(MI, OpNum: 4, STI, O); |
| 12929 | break; |
| 12930 | case 10: |
| 12931 | // ADDHA_MPPZ_S, ADDVA_MPPZ_S, BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_... |
| 12932 | printSVERegOp<'s'>(MI, OpNum: 4, STI, O); |
| 12933 | break; |
| 12934 | case 11: |
| 12935 | // ADDHNB_ZZZ_B, ADDQV_VPZ_H, ANDQV_VPZ_H, CNTP_XPP_H, EORQV_VPZ_H, FADDQ... |
| 12936 | printSVERegOp<'h'>(MI, OpNum: 2, STI, O); |
| 12937 | break; |
| 12938 | case 12: |
| 12939 | // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT... |
| 12940 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 12941 | break; |
| 12942 | case 13: |
| 12943 | // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... |
| 12944 | printVRegOperand(MI, OpNo: 2, STI, O); |
| 12945 | break; |
| 12946 | case 14: |
| 12947 | // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BF16DOTlanev4bf1... |
| 12948 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 12949 | break; |
| 12950 | case 15: |
| 12951 | // ADDP_ZPmZ_H, ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2... |
| 12952 | O << ", "; |
| 12953 | break; |
| 12954 | case 16: |
| 12955 | // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri |
| 12956 | printAddSubImm(MI, OpNum: 2, STI, O); |
| 12957 | return; |
| 12958 | break; |
| 12959 | case 17: |
| 12960 | // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... |
| 12961 | printShiftedRegister(MI, OpNum: 2, STI, O); |
| 12962 | return; |
| 12963 | break; |
| 12964 | case 18: |
| 12965 | // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx |
| 12966 | printExtendedRegister(MI, OpNum: 2, STI, O); |
| 12967 | return; |
| 12968 | break; |
| 12969 | case 19: |
| 12970 | // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... |
| 12971 | printImm8OptLsl<uint8_t>(MI, OpNum: 2, STI, O); |
| 12972 | return; |
| 12973 | break; |
| 12974 | case 20: |
| 12975 | // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... |
| 12976 | printImm8OptLsl<uint64_t>(MI, OpNum: 2, STI, O); |
| 12977 | return; |
| 12978 | break; |
| 12979 | case 21: |
| 12980 | // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... |
| 12981 | printImm8OptLsl<uint32_t>(MI, OpNum: 2, STI, O); |
| 12982 | return; |
| 12983 | break; |
| 12984 | case 22: |
| 12985 | // ADR_LSL_ZZZ_D_0 |
| 12986 | printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 12987 | O << ']'; |
| 12988 | return; |
| 12989 | break; |
| 12990 | case 23: |
| 12991 | // ADR_LSL_ZZZ_D_1 |
| 12992 | printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 12993 | O << ']'; |
| 12994 | return; |
| 12995 | break; |
| 12996 | case 24: |
| 12997 | // ADR_LSL_ZZZ_D_2 |
| 12998 | printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 12999 | O << ']'; |
| 13000 | return; |
| 13001 | break; |
| 13002 | case 25: |
| 13003 | // ADR_LSL_ZZZ_D_3 |
| 13004 | printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, OpNum: 2, STI, O); |
| 13005 | O << ']'; |
| 13006 | return; |
| 13007 | break; |
| 13008 | case 26: |
| 13009 | // ADR_LSL_ZZZ_S_0 |
| 13010 | printRegWithShiftExtend<false, 8, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 13011 | O << ']'; |
| 13012 | return; |
| 13013 | break; |
| 13014 | case 27: |
| 13015 | // ADR_LSL_ZZZ_S_1 |
| 13016 | printRegWithShiftExtend<false, 16, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 13017 | O << ']'; |
| 13018 | return; |
| 13019 | break; |
| 13020 | case 28: |
| 13021 | // ADR_LSL_ZZZ_S_2 |
| 13022 | printRegWithShiftExtend<false, 32, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 13023 | O << ']'; |
| 13024 | return; |
| 13025 | break; |
| 13026 | case 29: |
| 13027 | // ADR_LSL_ZZZ_S_3 |
| 13028 | printRegWithShiftExtend<false, 64, 'x', 's'>(MI, OpNum: 2, STI, O); |
| 13029 | O << ']'; |
| 13030 | return; |
| 13031 | break; |
| 13032 | case 30: |
| 13033 | // ADR_SXTW_ZZZ_D_0 |
| 13034 | printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 13035 | O << ']'; |
| 13036 | return; |
| 13037 | break; |
| 13038 | case 31: |
| 13039 | // ADR_SXTW_ZZZ_D_1 |
| 13040 | printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 13041 | O << ']'; |
| 13042 | return; |
| 13043 | break; |
| 13044 | case 32: |
| 13045 | // ADR_SXTW_ZZZ_D_2 |
| 13046 | printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 13047 | O << ']'; |
| 13048 | return; |
| 13049 | break; |
| 13050 | case 33: |
| 13051 | // ADR_SXTW_ZZZ_D_3 |
| 13052 | printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 13053 | O << ']'; |
| 13054 | return; |
| 13055 | break; |
| 13056 | case 34: |
| 13057 | // ADR_UXTW_ZZZ_D_0 |
| 13058 | printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 13059 | O << ']'; |
| 13060 | return; |
| 13061 | break; |
| 13062 | case 35: |
| 13063 | // ADR_UXTW_ZZZ_D_1 |
| 13064 | printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 13065 | O << ']'; |
| 13066 | return; |
| 13067 | break; |
| 13068 | case 36: |
| 13069 | // ADR_UXTW_ZZZ_D_2 |
| 13070 | printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 13071 | O << ']'; |
| 13072 | return; |
| 13073 | break; |
| 13074 | case 37: |
| 13075 | // ADR_UXTW_ZZZ_D_3 |
| 13076 | printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, OpNum: 2, STI, O); |
| 13077 | O << ']'; |
| 13078 | return; |
| 13079 | break; |
| 13080 | case 38: |
| 13081 | // AESDIMC_2ZZI_B, AESDIMC_4ZZI_B, AESD_2ZZI_B, AESD_4ZZI_B, AESEMC_2ZZI_... |
| 13082 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 13083 | return; |
| 13084 | break; |
| 13085 | case 39: |
| 13086 | // ANDSWri, ANDWri, EORWri, ORRWri |
| 13087 | printLogicalImm<int32_t>(MI, OpNum: 2, STI, O); |
| 13088 | return; |
| 13089 | break; |
| 13090 | case 40: |
| 13091 | // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI |
| 13092 | printLogicalImm<int64_t>(MI, OpNum: 2, STI, O); |
| 13093 | return; |
| 13094 | break; |
| 13095 | case 41: |
| 13096 | // BFMLAL_MZZI_HtoS, BFMLSL_MZZI_HtoS, FMLALL_MZZI_BtoS, FMLAL_MZZI_BtoH,... |
| 13097 | printVectorIndex(MI, OpNum: 6, STI, O); |
| 13098 | return; |
| 13099 | break; |
| 13100 | case 42: |
| 13101 | // BFMLA_ZZZI, BFMLS_ZZZI, CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FDOT_Z... |
| 13102 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 13103 | break; |
| 13104 | case 43: |
| 13105 | // BFMOPA_MPPZZ, BFMOPA_MPPZZ_H, BFMOPS_MPPZZ, BFMOPS_MPPZZ_H, FMOPAL_MPP... |
| 13106 | printSVERegOp<'h'>(MI, OpNum: 4, STI, O); |
| 13107 | O << ", "; |
| 13108 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 13109 | return; |
| 13110 | break; |
| 13111 | case 44: |
| 13112 | // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALTX, CASALW, CASALX,... |
| 13113 | printOperand(MI, OpNo: 3, STI, O); |
| 13114 | break; |
| 13115 | case 45: |
| 13116 | // BFTMOPA_M2ZZZI_HtoH, BFTMOPA_M2ZZZI_HtoS, FTMOPA_M2ZZZI_BtoH, FTMOPA_M... |
| 13117 | printSVERegOp<>(MI, OpNum: 4, STI, O); |
| 13118 | printVectorIndex(MI, OpNum: 5, STI, O); |
| 13119 | return; |
| 13120 | break; |
| 13121 | case 46: |
| 13122 | // CBBEQWrr, CBBGEWrr, CBBGTWrr, CBBHIWrr, CBBHSWrr, CBBNEWrr, CBEQWri, C... |
| 13123 | printAlignedLabel(MI, Address, OpNum: 2, STI, O); |
| 13124 | return; |
| 13125 | break; |
| 13126 | case 47: |
| 13127 | // CPY_ZPmI_B |
| 13128 | printImm8OptLsl<int8_t>(MI, OpNum: 3, STI, O); |
| 13129 | return; |
| 13130 | break; |
| 13131 | case 48: |
| 13132 | // CPY_ZPmI_D |
| 13133 | printImm8OptLsl<int64_t>(MI, OpNum: 3, STI, O); |
| 13134 | return; |
| 13135 | break; |
| 13136 | case 49: |
| 13137 | // CPY_ZPmI_S |
| 13138 | printImm8OptLsl<int32_t>(MI, OpNum: 3, STI, O); |
| 13139 | return; |
| 13140 | break; |
| 13141 | case 50: |
| 13142 | // CPY_ZPzI_B |
| 13143 | printImm8OptLsl<int8_t>(MI, OpNum: 2, STI, O); |
| 13144 | return; |
| 13145 | break; |
| 13146 | case 51: |
| 13147 | // CPY_ZPzI_D |
| 13148 | printImm8OptLsl<int64_t>(MI, OpNum: 2, STI, O); |
| 13149 | return; |
| 13150 | break; |
| 13151 | case 52: |
| 13152 | // CPY_ZPzI_S |
| 13153 | printImm8OptLsl<int32_t>(MI, OpNum: 2, STI, O); |
| 13154 | return; |
| 13155 | break; |
| 13156 | case 53: |
| 13157 | // DUPi16, DUPi32, DUPi64, DUPi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... |
| 13158 | printVectorIndex(MI, OpNum: 2, STI, O); |
| 13159 | return; |
| 13160 | break; |
| 13161 | case 54: |
| 13162 | // EXTRACT_ZPMXI_H_B, EXTRACT_ZPMXI_H_D, EXTRACT_ZPMXI_H_S |
| 13163 | printMatrixTileVector<0>(MI, OpNum: 3, STI, O); |
| 13164 | O << '['; |
| 13165 | printOperand(MI, OpNo: 4, STI, O); |
| 13166 | O << ", "; |
| 13167 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 13168 | O << ']'; |
| 13169 | return; |
| 13170 | break; |
| 13171 | case 55: |
| 13172 | // EXTRACT_ZPMXI_V_B, EXTRACT_ZPMXI_V_D, EXTRACT_ZPMXI_V_S |
| 13173 | printMatrixTileVector<1>(MI, OpNum: 3, STI, O); |
| 13174 | O << '['; |
| 13175 | printOperand(MI, OpNo: 4, STI, O); |
| 13176 | O << ", "; |
| 13177 | printMatrixIndex(MI, OpNum: 5, STI, O); |
| 13178 | O << ']'; |
| 13179 | return; |
| 13180 | break; |
| 13181 | case 56: |
| 13182 | // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... |
| 13183 | O << ", #0.0"; |
| 13184 | return; |
| 13185 | break; |
| 13186 | case 57: |
| 13187 | // FCPY_ZPmI_D, FCPY_ZPmI_S |
| 13188 | printFPImmOperand(MI, OpNum: 3, STI, O); |
| 13189 | return; |
| 13190 | break; |
| 13191 | case 58: |
| 13192 | // FDOT_VG2_M2Z2Z_BtoH, FDOT_VG2_M2Z2Z_BtoS, FDOT_VG4_M4Z4Z_BtoH, FDOT_VG... |
| 13193 | printTypedVectorList<0,'b'>(MI, OpNum: 5, STI, O); |
| 13194 | return; |
| 13195 | break; |
| 13196 | case 59: |
| 13197 | // FDOT_VG2_M2ZZI_BtoH, FDOT_VG2_M2ZZI_BtoS, FDOT_VG2_M2ZZ_BtoH, FDOT_VG2... |
| 13198 | printSVERegOp<'b'>(MI, OpNum: 5, STI, O); |
| 13199 | break; |
| 13200 | case 60: |
| 13201 | // FMLAL2lanev4f16, FMLALlanev4f16, FMLSL2lanev4f16, FMLSLlanev4f16 |
| 13202 | O << ".h"; |
| 13203 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 13204 | return; |
| 13205 | break; |
| 13206 | case 61: |
| 13207 | // FMLAL2v4f16, FMLALv4f16, FMLSL2v4f16, FMLSLv4f16 |
| 13208 | O << ".2h"; |
| 13209 | return; |
| 13210 | break; |
| 13211 | case 62: |
| 13212 | // FMOPA_MPPZZ_BtoH, FMOPA_MPPZZ_BtoS, SMOPA_MPPZZ_S, SMOPS_MPPZZ_S, SUMO... |
| 13213 | printSVERegOp<'b'>(MI, OpNum: 4, STI, O); |
| 13214 | O << ", "; |
| 13215 | printSVERegOp<'b'>(MI, OpNum: 5, STI, O); |
| 13216 | return; |
| 13217 | break; |
| 13218 | case 63: |
| 13219 | // INDEX_RI_B |
| 13220 | printSImm<8>(MI, OpNo: 2, STI, O); |
| 13221 | return; |
| 13222 | break; |
| 13223 | case 64: |
| 13224 | // INSERT_MXIPZ_H_D, INSERT_MXIPZ_V_D |
| 13225 | printSVERegOp<'d'>(MI, OpNum: 5, STI, O); |
| 13226 | return; |
| 13227 | break; |
| 13228 | case 65: |
| 13229 | // INSERT_MXIPZ_H_H, INSERT_MXIPZ_V_H |
| 13230 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 13231 | return; |
| 13232 | break; |
| 13233 | case 66: |
| 13234 | // INSERT_MXIPZ_H_Q, INSERT_MXIPZ_V_Q |
| 13235 | printSVERegOp<'q'>(MI, OpNum: 5, STI, O); |
| 13236 | return; |
| 13237 | break; |
| 13238 | case 67: |
| 13239 | // INSERT_MXIPZ_H_S, INSERT_MXIPZ_V_S |
| 13240 | printSVERegOp<'s'>(MI, OpNum: 5, STI, O); |
| 13241 | return; |
| 13242 | break; |
| 13243 | case 68: |
| 13244 | // LD1B_2Z_STRIDED, LDNT1B_2Z_STRIDED |
| 13245 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 13246 | O << ']'; |
| 13247 | return; |
| 13248 | break; |
| 13249 | case 69: |
| 13250 | // LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED_IMM, LDNT1B_2Z_STRIDED_IMM, LDNT1... |
| 13251 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 13252 | O << ", mul vl]"; |
| 13253 | return; |
| 13254 | break; |
| 13255 | case 70: |
| 13256 | // LD1H_2Z_STRIDED, LDNT1H_2Z_STRIDED |
| 13257 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 13258 | O << ']'; |
| 13259 | return; |
| 13260 | break; |
| 13261 | case 71: |
| 13262 | // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... |
| 13263 | O << "/z, ["; |
| 13264 | printOperand(MI, OpNo: 4, STI, O); |
| 13265 | O << ", "; |
| 13266 | break; |
| 13267 | case 72: |
| 13268 | // LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL... |
| 13269 | printOperand(MI, OpNo: 4, STI, O); |
| 13270 | O << ']'; |
| 13271 | return; |
| 13272 | break; |
| 13273 | case 73: |
| 13274 | // LDG, ST2GPostIndex, ST2GPreIndex, STGPostIndex, STGPreIndex, STZ2GPost... |
| 13275 | printImmScale<16>(MI, OpNum: 3, STI, O); |
| 13276 | break; |
| 13277 | case 74: |
| 13278 | // LDRAAindexed, LDRABindexed |
| 13279 | printImmScale<8>(MI, OpNum: 2, STI, O); |
| 13280 | O << ']'; |
| 13281 | return; |
| 13282 | break; |
| 13283 | case 75: |
| 13284 | // LDRAAwriteback, LDRABwriteback |
| 13285 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 13286 | O << "]!"; |
| 13287 | return; |
| 13288 | break; |
| 13289 | case 76: |
| 13290 | // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui |
| 13291 | printUImm12Offset<1>(MI, OpNum: 2, STI, O); |
| 13292 | O << ']'; |
| 13293 | return; |
| 13294 | break; |
| 13295 | case 77: |
| 13296 | // LDRDui, LDRXui, PRFMui, STRDui, STRXui |
| 13297 | printUImm12Offset<8>(MI, OpNum: 2, STI, O); |
| 13298 | O << ']'; |
| 13299 | return; |
| 13300 | break; |
| 13301 | case 78: |
| 13302 | // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui |
| 13303 | printUImm12Offset<2>(MI, OpNum: 2, STI, O); |
| 13304 | O << ']'; |
| 13305 | return; |
| 13306 | break; |
| 13307 | case 79: |
| 13308 | // LDRQui, STRQui |
| 13309 | printUImm12Offset<16>(MI, OpNum: 2, STI, O); |
| 13310 | O << ']'; |
| 13311 | return; |
| 13312 | break; |
| 13313 | case 80: |
| 13314 | // LDRSWui, LDRSui, LDRWui, STRSui, STRWui |
| 13315 | printUImm12Offset<4>(MI, OpNum: 2, STI, O); |
| 13316 | O << ']'; |
| 13317 | return; |
| 13318 | break; |
| 13319 | case 81: |
| 13320 | // LUTI2_S_2ZTZI_B, LUTI2_S_2ZTZI_H, LUTI2_ZTZI_B, LUTI2_ZTZI_S, LUTI4_S_... |
| 13321 | printSVERegOp<>(MI, OpNum: 2, STI, O); |
| 13322 | break; |
| 13323 | case 82: |
| 13324 | // MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q |
| 13325 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 13326 | O << ']'; |
| 13327 | return; |
| 13328 | break; |
| 13329 | case 83: |
| 13330 | // MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZMXI_H_H, MOVA_2ZMXI_H_S, MOVA_2... |
| 13331 | printImmRangeScale<2, 1>(MI, OpNum: 3, STI, O); |
| 13332 | O << ']'; |
| 13333 | return; |
| 13334 | break; |
| 13335 | case 84: |
| 13336 | // MOVA_4ZMXI_H_B, MOVA_4ZMXI_H_D, MOVA_4ZMXI_H_H, MOVA_4ZMXI_H_S, MOVA_4... |
| 13337 | printImmRangeScale<4, 3>(MI, OpNum: 3, STI, O); |
| 13338 | O << ']'; |
| 13339 | return; |
| 13340 | break; |
| 13341 | case 85: |
| 13342 | // MOVA_MXI2Z_H_B, MOVA_MXI2Z_V_B, MOVA_MXI4Z_H_B, MOVA_MXI4Z_V_B |
| 13343 | printTypedVectorList<0,'b'>(MI, OpNum: 4, STI, O); |
| 13344 | return; |
| 13345 | break; |
| 13346 | case 86: |
| 13347 | // MOVA_MXI2Z_H_D, MOVA_MXI2Z_V_D, MOVA_MXI4Z_H_D, MOVA_MXI4Z_V_D |
| 13348 | printTypedVectorList<0,'d'>(MI, OpNum: 4, STI, O); |
| 13349 | return; |
| 13350 | break; |
| 13351 | case 87: |
| 13352 | // MOVA_MXI2Z_H_H, MOVA_MXI2Z_V_H, MOVA_MXI4Z_H_H, MOVA_MXI4Z_V_H |
| 13353 | printTypedVectorList<0,'h'>(MI, OpNum: 4, STI, O); |
| 13354 | return; |
| 13355 | break; |
| 13356 | case 88: |
| 13357 | // MOVA_MXI2Z_H_S, MOVA_MXI2Z_V_S, MOVA_MXI4Z_H_S, MOVA_MXI4Z_V_S |
| 13358 | printTypedVectorList<0,'s'>(MI, OpNum: 4, STI, O); |
| 13359 | return; |
| 13360 | break; |
| 13361 | case 89: |
| 13362 | // PRFB_D_PZI, PRFB_S_PZI |
| 13363 | O << ']'; |
| 13364 | return; |
| 13365 | break; |
| 13366 | case 90: |
| 13367 | // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI |
| 13368 | O << ", mul vl]"; |
| 13369 | return; |
| 13370 | break; |
| 13371 | case 91: |
| 13372 | // SPLICE_ZPZZ_B |
| 13373 | printTypedVectorList<0,'b'>(MI, OpNum: 2, STI, O); |
| 13374 | return; |
| 13375 | break; |
| 13376 | case 92: |
| 13377 | // SPLICE_ZPZZ_D |
| 13378 | printTypedVectorList<0,'d'>(MI, OpNum: 2, STI, O); |
| 13379 | return; |
| 13380 | break; |
| 13381 | case 93: |
| 13382 | // SPLICE_ZPZZ_S |
| 13383 | printTypedVectorList<0,'s'>(MI, OpNum: 2, STI, O); |
| 13384 | return; |
| 13385 | break; |
| 13386 | case 94: |
| 13387 | // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... |
| 13388 | printGPR64as32(MI, OpNum: 2, STI, O); |
| 13389 | return; |
| 13390 | break; |
| 13391 | case 95: |
| 13392 | // ST1_MXIPXX_H_B, ST1_MXIPXX_H_D, ST1_MXIPXX_H_H, ST1_MXIPXX_H_Q, ST1_MX... |
| 13393 | O << ", ["; |
| 13394 | printOperand(MI, OpNo: 4, STI, O); |
| 13395 | O << ", "; |
| 13396 | break; |
| 13397 | case 96: |
| 13398 | // SYSLxt |
| 13399 | printSysCROperand(MI, OpNo: 2, STI, O); |
| 13400 | O << ", "; |
| 13401 | printSysCROperand(MI, OpNo: 3, STI, O); |
| 13402 | O << ", "; |
| 13403 | printOperand(MI, OpNo: 4, STI, O); |
| 13404 | return; |
| 13405 | break; |
| 13406 | case 97: |
| 13407 | // TCHANGEBri, TCHANGEBrr, TCHANGEFri, TCHANGEFrr |
| 13408 | printTIndexHintOp(MI, OpNum: 2, STI, O); |
| 13409 | return; |
| 13410 | break; |
| 13411 | case 98: |
| 13412 | // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S |
| 13413 | printImm(MI, OpNo: 2, STI, O); |
| 13414 | return; |
| 13415 | break; |
| 13416 | } |
| 13417 | |
| 13418 | |
| 13419 | // Fragment 5 encoded into 7 bits for 94 unique commands. |
| 13420 | switch ((Bits >> 50) & 127) { |
| 13421 | default: llvm_unreachable("Invalid command number."); |
| 13422 | case 0: |
| 13423 | // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABS_ZPzZ_B, ABS_ZPzZ_D, ABS_ZPzZ_S... |
| 13424 | return; |
| 13425 | break; |
| 13426 | case 1: |
| 13427 | // ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_CPA,... |
| 13428 | O << ", "; |
| 13429 | break; |
| 13430 | case 2: |
| 13431 | // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... |
| 13432 | O << ".2d"; |
| 13433 | return; |
| 13434 | break; |
| 13435 | case 3: |
| 13436 | // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... |
| 13437 | O << ".4s"; |
| 13438 | return; |
| 13439 | break; |
| 13440 | case 4: |
| 13441 | // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BFDOTv8bf16, B... |
| 13442 | O << ".8h"; |
| 13443 | return; |
| 13444 | break; |
| 13445 | case 5: |
| 13446 | // ADDPT_shift, SUBPT_shift |
| 13447 | printShifter(MI, OpNum: 3, STI, O); |
| 13448 | return; |
| 13449 | break; |
| 13450 | case 6: |
| 13451 | // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BFADD_ZP... |
| 13452 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 13453 | break; |
| 13454 | case 7: |
| 13455 | // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... |
| 13456 | O << ".16b"; |
| 13457 | return; |
| 13458 | break; |
| 13459 | case 8: |
| 13460 | // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... |
| 13461 | O << ".2s"; |
| 13462 | return; |
| 13463 | break; |
| 13464 | case 9: |
| 13465 | // ADDPv4i16, ADDv4i16, BFDOTv4bf16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMH... |
| 13466 | O << ".4h"; |
| 13467 | return; |
| 13468 | break; |
| 13469 | case 10: |
| 13470 | // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... |
| 13471 | O << ".8b"; |
| 13472 | return; |
| 13473 | break; |
| 13474 | case 11: |
| 13475 | // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 |
| 13476 | printArithExtend(MI, OpNum: 3, STI, O); |
| 13477 | return; |
| 13478 | break; |
| 13479 | case 12: |
| 13480 | // ADD_VG2_M2Z2Z_D, ADD_VG4_M4Z4Z_D, FMLA_VG2_M2Z2Z_D, FMLA_VG4_M4Z4Z_D, ... |
| 13481 | printTypedVectorList<0,'d'>(MI, OpNum: 5, STI, O); |
| 13482 | return; |
| 13483 | break; |
| 13484 | case 13: |
| 13485 | // ADD_VG2_M2Z2Z_S, ADD_VG4_M4Z4Z_S, FMLA_VG2_M2Z2Z_S, FMLA_VG4_M4Z4Z_S, ... |
| 13486 | printTypedVectorList<0,'s'>(MI, OpNum: 5, STI, O); |
| 13487 | return; |
| 13488 | break; |
| 13489 | case 14: |
| 13490 | // ADD_VG2_M2ZZ_D, ADD_VG4_M4ZZ_D, FMLA_VG2_M2ZZI_D, FMLA_VG2_M2ZZ_D, FML... |
| 13491 | printSVERegOp<'d'>(MI, OpNum: 5, STI, O); |
| 13492 | break; |
| 13493 | case 15: |
| 13494 | // ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_S, FMLA_VG2_M2ZZI_S, FMLA_VG2_M2ZZ_S, FML... |
| 13495 | printSVERegOp<'s'>(MI, OpNum: 5, STI, O); |
| 13496 | break; |
| 13497 | case 16: |
| 13498 | // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... |
| 13499 | printOperand(MI, OpNo: 3, STI, O); |
| 13500 | break; |
| 13501 | case 17: |
| 13502 | // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... |
| 13503 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 13504 | return; |
| 13505 | break; |
| 13506 | case 18: |
| 13507 | // BCAX, EOR3, EXTv16i8 |
| 13508 | O << ".16b, "; |
| 13509 | break; |
| 13510 | case 19: |
| 13511 | // BF16DOTlanev4bf16, BF16DOTlanev8bf16, FDOTlanev4f16_v2f32, FDOTlanev8f... |
| 13512 | O << ".2h"; |
| 13513 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 13514 | return; |
| 13515 | break; |
| 13516 | case 20: |
| 13517 | // BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG4_M4Z4Z_HtoS, BFMLAL_VG2_M2Z2Z_HtoS, BFM... |
| 13518 | printTypedVectorList<0,'h'>(MI, OpNum: 5, STI, O); |
| 13519 | return; |
| 13520 | break; |
| 13521 | case 21: |
| 13522 | // BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG2_M2ZZ_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFDOT... |
| 13523 | printSVERegOp<'h'>(MI, OpNum: 5, STI, O); |
| 13524 | break; |
| 13525 | case 22: |
| 13526 | // BFDOT_ZZI, BFMLALB_ZZZI, BFMLALT_ZZZI, BFMLSLB_ZZZI_S, BFMLSLT_ZZZI_S,... |
| 13527 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 13528 | break; |
| 13529 | case 23: |
| 13530 | // BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAL2... |
| 13531 | O << ".h"; |
| 13532 | break; |
| 13533 | case 24: |
| 13534 | // BFMLA_ZPmZZ, BFMLS_ZPmZZ, FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, F... |
| 13535 | printSVERegOp<'h'>(MI, OpNum: 4, STI, O); |
| 13536 | break; |
| 13537 | case 25: |
| 13538 | // CADD_ZZI_H, SQCADD_ZZI_H |
| 13539 | printComplexRotationOp<180, 90>(MI, OpNo: 3, STI, O); |
| 13540 | return; |
| 13541 | break; |
| 13542 | case 26: |
| 13543 | // CASAB, CASAH, CASALB, CASALH, CASALTX, CASALW, CASALX, CASATX, CASAW, ... |
| 13544 | O << ']'; |
| 13545 | return; |
| 13546 | break; |
| 13547 | case 27: |
| 13548 | // CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H |
| 13549 | printComplexRotationOp<90, 0>(MI, OpNo: 4, STI, O); |
| 13550 | return; |
| 13551 | break; |
| 13552 | case 28: |
| 13553 | // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H |
| 13554 | printImm(MI, OpNo: 3, STI, O); |
| 13555 | return; |
| 13556 | break; |
| 13557 | case 29: |
| 13558 | // EXTv8i8 |
| 13559 | O << ".8b, "; |
| 13560 | printOperand(MI, OpNo: 3, STI, O); |
| 13561 | return; |
| 13562 | break; |
| 13563 | case 30: |
| 13564 | // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H |
| 13565 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 13566 | return; |
| 13567 | break; |
| 13568 | case 31: |
| 13569 | // FCADDv2f32, FCMLAv2f32 |
| 13570 | O << ".2s, "; |
| 13571 | break; |
| 13572 | case 32: |
| 13573 | // FCADDv2f64, FCMLAv2f64, XAR |
| 13574 | O << ".2d, "; |
| 13575 | break; |
| 13576 | case 33: |
| 13577 | // FCADDv4f16, FCMLAv4f16 |
| 13578 | O << ".4h, "; |
| 13579 | break; |
| 13580 | case 34: |
| 13581 | // FCADDv4f32, FCMLAv4f32, SM3SS1 |
| 13582 | O << ".4s, "; |
| 13583 | break; |
| 13584 | case 35: |
| 13585 | // FCADDv8f16, FCMLAv8f16 |
| 13586 | O << ".8h, "; |
| 13587 | break; |
| 13588 | case 36: |
| 13589 | // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... |
| 13590 | O << ", #0.0"; |
| 13591 | return; |
| 13592 | break; |
| 13593 | case 37: |
| 13594 | // FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in... |
| 13595 | O << ".s"; |
| 13596 | break; |
| 13597 | case 38: |
| 13598 | // FDOT_VG2_M2ZZI_BtoH, FDOT_VG2_M2ZZI_BtoS, FDOT_VG4_M4ZZI_BtoH, FDOT_VG... |
| 13599 | printVectorIndex(MI, OpNum: 6, STI, O); |
| 13600 | return; |
| 13601 | break; |
| 13602 | case 39: |
| 13603 | // FDOTlanev2f32, FDOTlanev4f32, SDOTlanev16i8, SDOTlanev8i8, SUDOTlanev1... |
| 13604 | O << ".4b"; |
| 13605 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 13606 | return; |
| 13607 | break; |
| 13608 | case 40: |
| 13609 | // FDOTlanev4f16, FDOTlanev8f16 |
| 13610 | O << ".2b"; |
| 13611 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 13612 | return; |
| 13613 | break; |
| 13614 | case 41: |
| 13615 | // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H |
| 13616 | printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 13617 | return; |
| 13618 | break; |
| 13619 | case 42: |
| 13620 | // FMLALBlanev8f16, FMLALLBBlanev4f32, FMLALLBTlanev4f32, FMLALLTBlanev4f... |
| 13621 | O << ".b"; |
| 13622 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 13623 | return; |
| 13624 | break; |
| 13625 | case 43: |
| 13626 | // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... |
| 13627 | O << ".d"; |
| 13628 | break; |
| 13629 | case 44: |
| 13630 | // FMUL_ZPmI_H |
| 13631 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, OpNum: 3, STI, O); |
| 13632 | return; |
| 13633 | break; |
| 13634 | case 45: |
| 13635 | // FMUL_ZZZI_D, FMUL_ZZZI_S, LUTI2_S_2ZTZI_B, LUTI2_S_2ZTZI_H, LUTI2_ZTZI... |
| 13636 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 13637 | return; |
| 13638 | break; |
| 13639 | case 46: |
| 13640 | // GLD1B_D, GLD1D, GLD1H_D, GLD1SB_D, GLD1SH_D, GLD1SW_D, GLD1W_D, GLDFF1... |
| 13641 | printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 13642 | O << ']'; |
| 13643 | return; |
| 13644 | break; |
| 13645 | case 47: |
| 13646 | // GLD1B_D_SXTW, GLD1D_SXTW, GLD1H_D_SXTW, GLD1SB_D_SXTW, GLD1SH_D_SXTW, ... |
| 13647 | printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 13648 | O << ']'; |
| 13649 | return; |
| 13650 | break; |
| 13651 | case 48: |
| 13652 | // GLD1B_D_UXTW, GLD1D_UXTW, GLD1H_D_UXTW, GLD1SB_D_UXTW, GLD1SH_D_UXTW, ... |
| 13653 | printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 13654 | O << ']'; |
| 13655 | return; |
| 13656 | break; |
| 13657 | case 49: |
| 13658 | // GLD1B_S_SXTW, GLD1H_S_SXTW, GLD1SB_S_SXTW, GLD1SH_S_SXTW, GLD1W_SXTW, ... |
| 13659 | printRegWithShiftExtend<true, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 13660 | O << ']'; |
| 13661 | return; |
| 13662 | break; |
| 13663 | case 50: |
| 13664 | // GLD1B_S_UXTW, GLD1H_S_UXTW, GLD1SB_S_UXTW, GLD1SH_S_UXTW, GLD1W_UXTW, ... |
| 13665 | printRegWithShiftExtend<false, 8, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 13666 | O << ']'; |
| 13667 | return; |
| 13668 | break; |
| 13669 | case 51: |
| 13670 | // GLD1D_IMM, GLDFF1D_IMM, LD1RD_IMM, SST1D_IMM |
| 13671 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 13672 | O << ']'; |
| 13673 | return; |
| 13674 | break; |
| 13675 | case 52: |
| 13676 | // GLD1D_SCALED, GLDFF1D_SCALED, SST1D_SCALED |
| 13677 | printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 13678 | O << ']'; |
| 13679 | return; |
| 13680 | break; |
| 13681 | case 53: |
| 13682 | // GLD1D_SXTW_SCALED, GLDFF1D_SXTW_SCALED, SST1D_SXTW_SCALED |
| 13683 | printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 13684 | O << ']'; |
| 13685 | return; |
| 13686 | break; |
| 13687 | case 54: |
| 13688 | // GLD1D_UXTW_SCALED, GLDFF1D_UXTW_SCALED, SST1D_UXTW_SCALED |
| 13689 | printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 13690 | O << ']'; |
| 13691 | return; |
| 13692 | break; |
| 13693 | case 55: |
| 13694 | // GLD1H_D_IMM, GLD1H_S_IMM, GLD1SH_D_IMM, GLD1SH_S_IMM, GLDFF1H_D_IMM, G... |
| 13695 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 13696 | break; |
| 13697 | case 56: |
| 13698 | // GLD1H_D_SCALED, GLD1SH_D_SCALED, GLDFF1H_D_SCALED, GLDFF1SH_D_SCALED, ... |
| 13699 | printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 13700 | O << ']'; |
| 13701 | return; |
| 13702 | break; |
| 13703 | case 57: |
| 13704 | // GLD1H_D_SXTW_SCALED, GLD1SH_D_SXTW_SCALED, GLDFF1H_D_SXTW_SCALED, GLDF... |
| 13705 | printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 13706 | O << ']'; |
| 13707 | return; |
| 13708 | break; |
| 13709 | case 58: |
| 13710 | // GLD1H_D_UXTW_SCALED, GLD1SH_D_UXTW_SCALED, GLDFF1H_D_UXTW_SCALED, GLDF... |
| 13711 | printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 13712 | O << ']'; |
| 13713 | return; |
| 13714 | break; |
| 13715 | case 59: |
| 13716 | // GLD1H_S_SXTW_SCALED, GLD1SH_S_SXTW_SCALED, GLDFF1H_S_SXTW_SCALED, GLDF... |
| 13717 | printRegWithShiftExtend<true, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 13718 | O << ']'; |
| 13719 | return; |
| 13720 | break; |
| 13721 | case 60: |
| 13722 | // GLD1H_S_UXTW_SCALED, GLD1SH_S_UXTW_SCALED, GLDFF1H_S_UXTW_SCALED, GLDF... |
| 13723 | printRegWithShiftExtend<false, 16, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 13724 | O << ']'; |
| 13725 | return; |
| 13726 | break; |
| 13727 | case 61: |
| 13728 | // GLD1SW_D_IMM, GLD1W_D_IMM, GLD1W_IMM, GLDFF1SW_D_IMM, GLDFF1W_D_IMM, G... |
| 13729 | printImmScale<4>(MI, OpNum: 3, STI, O); |
| 13730 | break; |
| 13731 | case 62: |
| 13732 | // GLD1SW_D_SCALED, GLD1W_D_SCALED, GLDFF1SW_D_SCALED, GLDFF1W_D_SCALED, ... |
| 13733 | printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, OpNum: 3, STI, O); |
| 13734 | O << ']'; |
| 13735 | return; |
| 13736 | break; |
| 13737 | case 63: |
| 13738 | // GLD1SW_D_SXTW_SCALED, GLD1W_D_SXTW_SCALED, GLDFF1SW_D_SXTW_SCALED, GLD... |
| 13739 | printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 13740 | O << ']'; |
| 13741 | return; |
| 13742 | break; |
| 13743 | case 64: |
| 13744 | // GLD1SW_D_UXTW_SCALED, GLD1W_D_UXTW_SCALED, GLDFF1SW_D_UXTW_SCALED, GLD... |
| 13745 | printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, OpNum: 3, STI, O); |
| 13746 | O << ']'; |
| 13747 | return; |
| 13748 | break; |
| 13749 | case 65: |
| 13750 | // GLD1W_SXTW_SCALED, GLDFF1W_SXTW_SCALED, SST1W_SXTW_SCALED |
| 13751 | printRegWithShiftExtend<true, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 13752 | O << ']'; |
| 13753 | return; |
| 13754 | break; |
| 13755 | case 66: |
| 13756 | // GLD1W_UXTW_SCALED, GLDFF1W_UXTW_SCALED, SST1W_UXTW_SCALED |
| 13757 | printRegWithShiftExtend<false, 32, 'w', 's'>(MI, OpNum: 3, STI, O); |
| 13758 | O << ']'; |
| 13759 | return; |
| 13760 | break; |
| 13761 | case 67: |
| 13762 | // LD1B, LD1B_2Z, LD1B_4Z, LD1B_4Z_STRIDED, LD1B_D, LD1B_H, LD1B_S, LD1RO... |
| 13763 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 13764 | O << ']'; |
| 13765 | return; |
| 13766 | break; |
| 13767 | case 68: |
| 13768 | // LD1D, LD1D_2Z, LD1D_2Z_STRIDED, LD1D_4Z, LD1D_4Z_STRIDED, LD1D_Q, LD1R... |
| 13769 | printRegWithShiftExtend<false, 64, 'x', 0>(MI, OpNum: 3, STI, O); |
| 13770 | O << ']'; |
| 13771 | return; |
| 13772 | break; |
| 13773 | case 69: |
| 13774 | // LD1H, LD1H_2Z, LD1H_4Z, LD1H_4Z_STRIDED, LD1H_D, LD1H_S, LD1RO_H, LD1R... |
| 13775 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 13776 | O << ']'; |
| 13777 | return; |
| 13778 | break; |
| 13779 | case 70: |
| 13780 | // LD1RO_B_IMM, LD1RO_D_IMM, LD1RO_H_IMM, LD1RO_W_IMM |
| 13781 | printImmScale<32>(MI, OpNum: 3, STI, O); |
| 13782 | O << ']'; |
| 13783 | return; |
| 13784 | break; |
| 13785 | case 71: |
| 13786 | // LD1RO_W, LD1RQ_W, LD1SW_D, LD1W, LD1W_2Z, LD1W_2Z_STRIDED, LD1W_4Z, LD... |
| 13787 | printRegWithShiftExtend<false, 32, 'x', 0>(MI, OpNum: 3, STI, O); |
| 13788 | O << ']'; |
| 13789 | return; |
| 13790 | break; |
| 13791 | case 72: |
| 13792 | // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM |
| 13793 | printImmScale<16>(MI, OpNum: 3, STI, O); |
| 13794 | O << ']'; |
| 13795 | return; |
| 13796 | break; |
| 13797 | case 73: |
| 13798 | // LD1_MXIPXX_H_B, LD1_MXIPXX_V_B, ST1_MXIPXX_H_B, ST1_MXIPXX_V_B |
| 13799 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 5, STI, O); |
| 13800 | O << ']'; |
| 13801 | return; |
| 13802 | break; |
| 13803 | case 74: |
| 13804 | // LD1_MXIPXX_H_D, LD1_MXIPXX_V_D, ST1_MXIPXX_H_D, ST1_MXIPXX_V_D |
| 13805 | printRegWithShiftExtend<false, 64, 'x', 0>(MI, OpNum: 5, STI, O); |
| 13806 | O << ']'; |
| 13807 | return; |
| 13808 | break; |
| 13809 | case 75: |
| 13810 | // LD1_MXIPXX_H_H, LD1_MXIPXX_V_H, ST1_MXIPXX_H_H, ST1_MXIPXX_V_H |
| 13811 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 5, STI, O); |
| 13812 | O << ']'; |
| 13813 | return; |
| 13814 | break; |
| 13815 | case 76: |
| 13816 | // LD1_MXIPXX_H_Q, LD1_MXIPXX_V_Q, ST1_MXIPXX_H_Q, ST1_MXIPXX_V_Q |
| 13817 | printRegWithShiftExtend<false, 128, 'x', 0>(MI, OpNum: 5, STI, O); |
| 13818 | O << ']'; |
| 13819 | return; |
| 13820 | break; |
| 13821 | case 77: |
| 13822 | // LD1_MXIPXX_H_S, LD1_MXIPXX_V_S, ST1_MXIPXX_H_S, ST1_MXIPXX_V_S |
| 13823 | printRegWithShiftExtend<false, 32, 'x', 0>(MI, OpNum: 5, STI, O); |
| 13824 | O << ']'; |
| 13825 | return; |
| 13826 | break; |
| 13827 | case 78: |
| 13828 | // LD2Q, LD3Q, LD4Q, ST2Q, ST3Q, ST4Q |
| 13829 | printRegWithShiftExtend<false, 128, 'x', 0>(MI, OpNum: 3, STI, O); |
| 13830 | O << ']'; |
| 13831 | return; |
| 13832 | break; |
| 13833 | case 79: |
| 13834 | // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3Q_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ... |
| 13835 | printImmScale<3>(MI, OpNum: 3, STI, O); |
| 13836 | O << ", mul vl]"; |
| 13837 | return; |
| 13838 | break; |
| 13839 | case 80: |
| 13840 | // LDAPPi, LDAPi, STLPi |
| 13841 | O << ", #0]"; |
| 13842 | return; |
| 13843 | break; |
| 13844 | case 81: |
| 13845 | // LDIAPPWpost |
| 13846 | O << "], #8"; |
| 13847 | return; |
| 13848 | break; |
| 13849 | case 82: |
| 13850 | // LDIAPPXpost |
| 13851 | O << "], #16"; |
| 13852 | return; |
| 13853 | break; |
| 13854 | case 83: |
| 13855 | // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, LDTPQpost... |
| 13856 | O << "], "; |
| 13857 | break; |
| 13858 | case 84: |
| 13859 | // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR... |
| 13860 | O << "]!"; |
| 13861 | return; |
| 13862 | break; |
| 13863 | case 85: |
| 13864 | // LDR_PXI, LDR_ZXI, STR_PXI, STR_ZXI |
| 13865 | O << ", mul vl]"; |
| 13866 | return; |
| 13867 | break; |
| 13868 | case 86: |
| 13869 | // PSEL_PPPRI_B, PSEL_PPPRI_D, PSEL_PPPRI_H, PSEL_PPPRI_S |
| 13870 | O << '['; |
| 13871 | printOperand(MI, OpNo: 3, STI, O); |
| 13872 | O << ", "; |
| 13873 | printMatrixIndex(MI, OpNum: 4, STI, O); |
| 13874 | O << ']'; |
| 13875 | return; |
| 13876 | break; |
| 13877 | case 87: |
| 13878 | // SEL_VG2_2ZC2Z2Z_B, SEL_VG4_4ZC4Z4Z_B |
| 13879 | printTypedVectorList<0,'b'>(MI, OpNum: 3, STI, O); |
| 13880 | return; |
| 13881 | break; |
| 13882 | case 88: |
| 13883 | // SEL_VG2_2ZC2Z2Z_D, SEL_VG4_4ZC4Z4Z_D |
| 13884 | printTypedVectorList<0,'d'>(MI, OpNum: 3, STI, O); |
| 13885 | return; |
| 13886 | break; |
| 13887 | case 89: |
| 13888 | // SEL_VG2_2ZC2Z2Z_H, SEL_VG4_4ZC4Z4Z_H |
| 13889 | printTypedVectorList<0,'h'>(MI, OpNum: 3, STI, O); |
| 13890 | return; |
| 13891 | break; |
| 13892 | case 90: |
| 13893 | // SEL_VG2_2ZC2Z2Z_S, SEL_VG4_4ZC4Z4Z_S |
| 13894 | printTypedVectorList<0,'s'>(MI, OpNum: 3, STI, O); |
| 13895 | return; |
| 13896 | break; |
| 13897 | case 91: |
| 13898 | // STILPWpre |
| 13899 | O << ", #-8]!"; |
| 13900 | return; |
| 13901 | break; |
| 13902 | case 92: |
| 13903 | // STILPXpre |
| 13904 | O << ", #-16]!"; |
| 13905 | return; |
| 13906 | break; |
| 13907 | case 93: |
| 13908 | // STLXPW, STLXPX, STXPW, STXPX |
| 13909 | O << ", ["; |
| 13910 | printOperand(MI, OpNo: 3, STI, O); |
| 13911 | O << ']'; |
| 13912 | return; |
| 13913 | break; |
| 13914 | } |
| 13915 | |
| 13916 | |
| 13917 | // Fragment 6 encoded into 6 bits for 47 unique commands. |
| 13918 | switch ((Bits >> 57) & 63) { |
| 13919 | default: llvm_unreachable("Invalid command number."); |
| 13920 | case 0: |
| 13921 | // ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A... |
| 13922 | printOperand(MI, OpNo: 3, STI, O); |
| 13923 | return; |
| 13924 | break; |
| 13925 | case 1: |
| 13926 | // ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_... |
| 13927 | printSVERegOp<'b'>(MI, OpNum: 3, STI, O); |
| 13928 | return; |
| 13929 | break; |
| 13930 | case 2: |
| 13931 | // ADDP_ZPmZ_D, ADD_ZPmZ_CPA, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WI... |
| 13932 | printSVERegOp<'d'>(MI, OpNum: 3, STI, O); |
| 13933 | break; |
| 13934 | case 3: |
| 13935 | // ADDP_ZPmZ_H, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_D, ADD_VG4_M... |
| 13936 | return; |
| 13937 | break; |
| 13938 | case 4: |
| 13939 | // ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ... |
| 13940 | printSVERegOp<'s'>(MI, OpNum: 3, STI, O); |
| 13941 | break; |
| 13942 | case 5: |
| 13943 | // BCAX, EOR3, SM3SS1 |
| 13944 | printVRegOperand(MI, OpNo: 3, STI, O); |
| 13945 | break; |
| 13946 | case 6: |
| 13947 | // BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFMLAL_VG2_M2ZZI_HtoS, BFM... |
| 13948 | printVectorIndex(MI, OpNum: 6, STI, O); |
| 13949 | return; |
| 13950 | break; |
| 13951 | case 7: |
| 13952 | // BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv... |
| 13953 | printVectorIndex(MI, OpNum: 4, STI, O); |
| 13954 | break; |
| 13955 | case 8: |
| 13956 | // BFMWri, BFMXri |
| 13957 | printOperand(MI, OpNo: 4, STI, O); |
| 13958 | return; |
| 13959 | break; |
| 13960 | case 9: |
| 13961 | // BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_S, FMOPS_MPPZZ_S |
| 13962 | printSVERegOp<'s'>(MI, OpNum: 5, STI, O); |
| 13963 | return; |
| 13964 | break; |
| 13965 | case 10: |
| 13966 | // CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16... |
| 13967 | printComplexRotationOp<180, 90>(MI, OpNo: 3, STI, O); |
| 13968 | return; |
| 13969 | break; |
| 13970 | case 11: |
| 13971 | // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... |
| 13972 | printCondCode(MI, OpNum: 3, STI, O); |
| 13973 | return; |
| 13974 | break; |
| 13975 | case 12: |
| 13976 | // CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, S... |
| 13977 | O << ", "; |
| 13978 | break; |
| 13979 | case 13: |
| 13980 | // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H |
| 13981 | printComplexRotationOp<90, 0>(MI, OpNo: 5, STI, O); |
| 13982 | return; |
| 13983 | break; |
| 13984 | case 14: |
| 13985 | // CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16... |
| 13986 | printComplexRotationOp<90, 0>(MI, OpNo: 4, STI, O); |
| 13987 | return; |
| 13988 | break; |
| 13989 | case 15: |
| 13990 | // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H |
| 13991 | printSVERegOp<'h'>(MI, OpNum: 3, STI, O); |
| 13992 | return; |
| 13993 | break; |
| 13994 | case 16: |
| 13995 | // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... |
| 13996 | printImm(MI, OpNo: 3, STI, O); |
| 13997 | return; |
| 13998 | break; |
| 13999 | case 17: |
| 14000 | // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... |
| 14001 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 14002 | return; |
| 14003 | break; |
| 14004 | case 18: |
| 14005 | // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... |
| 14006 | printSVERegOp<'d'>(MI, OpNum: 4, STI, O); |
| 14007 | break; |
| 14008 | case 19: |
| 14009 | // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... |
| 14010 | printSVERegOp<'s'>(MI, OpNum: 4, STI, O); |
| 14011 | break; |
| 14012 | case 20: |
| 14013 | // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... |
| 14014 | printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, OpNum: 3, STI, O); |
| 14015 | return; |
| 14016 | break; |
| 14017 | case 21: |
| 14018 | // FMOPA_MPPZZ_D, FMOPS_MPPZZ_D |
| 14019 | printSVERegOp<'d'>(MI, OpNum: 5, STI, O); |
| 14020 | return; |
| 14021 | break; |
| 14022 | case 22: |
| 14023 | // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... |
| 14024 | printVectorIndex(MI, OpNum: 3, STI, O); |
| 14025 | return; |
| 14026 | break; |
| 14027 | case 23: |
| 14028 | // FMUL_ZPmI_D, FMUL_ZPmI_S |
| 14029 | printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, OpNum: 3, STI, O); |
| 14030 | return; |
| 14031 | break; |
| 14032 | case 24: |
| 14033 | // GLD1B_D_IMM, GLD1B_S_IMM, GLD1H_D_IMM, GLD1H_S_IMM, GLD1Q, GLD1SB_D_IM... |
| 14034 | O << ']'; |
| 14035 | return; |
| 14036 | break; |
| 14037 | case 25: |
| 14038 | // LD1B_2Z_IMM, LD1B_4Z_IMM, LD1B_4Z_STRIDED_IMM, LD1B_D_IMM, LD1B_H_IMM,... |
| 14039 | O << ", mul vl]"; |
| 14040 | return; |
| 14041 | break; |
| 14042 | case 26: |
| 14043 | // LDNPDi, LDNPXi, LDPDi, LDPXi, LDTNPXi, LDTPi, STNPDi, STNPXi, STPDi, S... |
| 14044 | printImmScale<8>(MI, OpNum: 3, STI, O); |
| 14045 | O << ']'; |
| 14046 | return; |
| 14047 | break; |
| 14048 | case 27: |
| 14049 | // LDNPQi, LDPQi, LDTNPQi, LDTPQi, STGPi, STNPQi, STPQi, STTNPQi, STTPQi |
| 14050 | printImmScale<16>(MI, OpNum: 3, STI, O); |
| 14051 | O << ']'; |
| 14052 | return; |
| 14053 | break; |
| 14054 | case 28: |
| 14055 | // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi |
| 14056 | printImmScale<4>(MI, OpNum: 3, STI, O); |
| 14057 | O << ']'; |
| 14058 | return; |
| 14059 | break; |
| 14060 | case 29: |
| 14061 | // LDPDpost, LDPDpre, LDPXpost, LDPXpre, LDTPpost, LDTPpre, STPDpost, STP... |
| 14062 | printImmScale<8>(MI, OpNum: 4, STI, O); |
| 14063 | break; |
| 14064 | case 30: |
| 14065 | // LDPQpost, LDPQpre, LDTPQpost, LDTPQpre, STGPpost, STGPpre, STPQpost, S... |
| 14066 | printImmScale<16>(MI, OpNum: 4, STI, O); |
| 14067 | break; |
| 14068 | case 31: |
| 14069 | // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... |
| 14070 | printImmScale<4>(MI, OpNum: 4, STI, O); |
| 14071 | break; |
| 14072 | case 32: |
| 14073 | // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW |
| 14074 | printMemExtend<'w', 8>(MI, OpNum: 3, STI, O); |
| 14075 | O << ']'; |
| 14076 | return; |
| 14077 | break; |
| 14078 | case 33: |
| 14079 | // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX |
| 14080 | printMemExtend<'x', 8>(MI, OpNum: 3, STI, O); |
| 14081 | O << ']'; |
| 14082 | return; |
| 14083 | break; |
| 14084 | case 34: |
| 14085 | // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW |
| 14086 | printMemExtend<'w', 64>(MI, OpNum: 3, STI, O); |
| 14087 | O << ']'; |
| 14088 | return; |
| 14089 | break; |
| 14090 | case 35: |
| 14091 | // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX |
| 14092 | printMemExtend<'x', 64>(MI, OpNum: 3, STI, O); |
| 14093 | O << ']'; |
| 14094 | return; |
| 14095 | break; |
| 14096 | case 36: |
| 14097 | // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW |
| 14098 | printMemExtend<'w', 16>(MI, OpNum: 3, STI, O); |
| 14099 | O << ']'; |
| 14100 | return; |
| 14101 | break; |
| 14102 | case 37: |
| 14103 | // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX |
| 14104 | printMemExtend<'x', 16>(MI, OpNum: 3, STI, O); |
| 14105 | O << ']'; |
| 14106 | return; |
| 14107 | break; |
| 14108 | case 38: |
| 14109 | // LDRQroW, STRQroW |
| 14110 | printMemExtend<'w', 128>(MI, OpNum: 3, STI, O); |
| 14111 | O << ']'; |
| 14112 | return; |
| 14113 | break; |
| 14114 | case 39: |
| 14115 | // LDRQroX, STRQroX |
| 14116 | printMemExtend<'x', 128>(MI, OpNum: 3, STI, O); |
| 14117 | O << ']'; |
| 14118 | return; |
| 14119 | break; |
| 14120 | case 40: |
| 14121 | // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW |
| 14122 | printMemExtend<'w', 32>(MI, OpNum: 3, STI, O); |
| 14123 | O << ']'; |
| 14124 | return; |
| 14125 | break; |
| 14126 | case 41: |
| 14127 | // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX |
| 14128 | printMemExtend<'x', 32>(MI, OpNum: 3, STI, O); |
| 14129 | O << ']'; |
| 14130 | return; |
| 14131 | break; |
| 14132 | case 42: |
| 14133 | // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B |
| 14134 | printSVERegOp<'b'>(MI, OpNum: 4, STI, O); |
| 14135 | return; |
| 14136 | break; |
| 14137 | case 43: |
| 14138 | // ST1B_2Z_STRIDED, STNT1B_2Z_STRIDED |
| 14139 | printRegWithShiftExtend<false, 8, 'x', 0>(MI, OpNum: 3, STI, O); |
| 14140 | O << ']'; |
| 14141 | return; |
| 14142 | break; |
| 14143 | case 44: |
| 14144 | // ST1B_2Z_STRIDED_IMM, ST1H_2Z_STRIDED_IMM, STNT1B_2Z_STRIDED_IMM, STNT1... |
| 14145 | printImmScale<2>(MI, OpNum: 3, STI, O); |
| 14146 | O << ", mul vl]"; |
| 14147 | return; |
| 14148 | break; |
| 14149 | case 45: |
| 14150 | // ST1H_2Z_STRIDED, STNT1H_2Z_STRIDED |
| 14151 | printRegWithShiftExtend<false, 16, 'x', 0>(MI, OpNum: 3, STI, O); |
| 14152 | O << ']'; |
| 14153 | return; |
| 14154 | break; |
| 14155 | case 46: |
| 14156 | // WHILEGE_CXX_B, WHILEGE_CXX_D, WHILEGE_CXX_H, WHILEGE_CXX_S, WHILEGT_CX... |
| 14157 | printSVEVecLenSpecifier(MI, OpNum: 3, STI, O); |
| 14158 | return; |
| 14159 | break; |
| 14160 | } |
| 14161 | |
| 14162 | switch (MI->getOpcode()) { |
| 14163 | default: llvm_unreachable("Unexpected opcode."); |
| 14164 | case AArch64::ADDP_ZPmZ_D: |
| 14165 | case AArch64::ADDP_ZPmZ_S: |
| 14166 | case AArch64::ADD_ZPmZ_CPA: |
| 14167 | case AArch64::ADD_ZPmZ_D: |
| 14168 | case AArch64::ADD_ZPmZ_S: |
| 14169 | case AArch64::AND_ZPmZ_D: |
| 14170 | case AArch64::AND_ZPmZ_S: |
| 14171 | case AArch64::ASRR_ZPmZ_D: |
| 14172 | case AArch64::ASRR_ZPmZ_S: |
| 14173 | case AArch64::ASR_WIDE_ZPmZ_B: |
| 14174 | case AArch64::ASR_WIDE_ZPmZ_S: |
| 14175 | case AArch64::ASR_ZPmZ_D: |
| 14176 | case AArch64::ASR_ZPmZ_S: |
| 14177 | case AArch64::BCAX_ZZZZ: |
| 14178 | case AArch64::BFMLALBIdx: |
| 14179 | case AArch64::BFMLALTIdx: |
| 14180 | case AArch64::BIC_ZPmZ_D: |
| 14181 | case AArch64::BIC_ZPmZ_S: |
| 14182 | case AArch64::BSL1N_ZZZZ: |
| 14183 | case AArch64::BSL2N_ZZZZ: |
| 14184 | case AArch64::BSL_ZZZZ: |
| 14185 | case AArch64::CLASTA_RPZ_D: |
| 14186 | case AArch64::CLASTA_RPZ_S: |
| 14187 | case AArch64::CLASTA_VPZ_D: |
| 14188 | case AArch64::CLASTA_VPZ_S: |
| 14189 | case AArch64::CLASTA_ZPZ_D: |
| 14190 | case AArch64::CLASTA_ZPZ_S: |
| 14191 | case AArch64::CLASTB_RPZ_D: |
| 14192 | case AArch64::CLASTB_RPZ_S: |
| 14193 | case AArch64::CLASTB_VPZ_D: |
| 14194 | case AArch64::CLASTB_VPZ_S: |
| 14195 | case AArch64::CLASTB_ZPZ_D: |
| 14196 | case AArch64::CLASTB_ZPZ_S: |
| 14197 | case AArch64::CMPEQ_PPzZZ_D: |
| 14198 | case AArch64::CMPEQ_PPzZZ_S: |
| 14199 | case AArch64::CMPEQ_WIDE_PPzZZ_B: |
| 14200 | case AArch64::CMPEQ_WIDE_PPzZZ_S: |
| 14201 | case AArch64::CMPGE_PPzZZ_D: |
| 14202 | case AArch64::CMPGE_PPzZZ_S: |
| 14203 | case AArch64::CMPGE_WIDE_PPzZZ_B: |
| 14204 | case AArch64::CMPGE_WIDE_PPzZZ_S: |
| 14205 | case AArch64::CMPGT_PPzZZ_D: |
| 14206 | case AArch64::CMPGT_PPzZZ_S: |
| 14207 | case AArch64::CMPGT_WIDE_PPzZZ_B: |
| 14208 | case AArch64::CMPGT_WIDE_PPzZZ_S: |
| 14209 | case AArch64::CMPHI_PPzZZ_D: |
| 14210 | case AArch64::CMPHI_PPzZZ_S: |
| 14211 | case AArch64::CMPHI_WIDE_PPzZZ_B: |
| 14212 | case AArch64::CMPHI_WIDE_PPzZZ_S: |
| 14213 | case AArch64::CMPHS_PPzZZ_D: |
| 14214 | case AArch64::CMPHS_PPzZZ_S: |
| 14215 | case AArch64::CMPHS_WIDE_PPzZZ_B: |
| 14216 | case AArch64::CMPHS_WIDE_PPzZZ_S: |
| 14217 | case AArch64::CMPLE_WIDE_PPzZZ_B: |
| 14218 | case AArch64::CMPLE_WIDE_PPzZZ_S: |
| 14219 | case AArch64::CMPLO_WIDE_PPzZZ_B: |
| 14220 | case AArch64::CMPLO_WIDE_PPzZZ_S: |
| 14221 | case AArch64::CMPLS_WIDE_PPzZZ_B: |
| 14222 | case AArch64::CMPLS_WIDE_PPzZZ_S: |
| 14223 | case AArch64::CMPLT_WIDE_PPzZZ_B: |
| 14224 | case AArch64::CMPLT_WIDE_PPzZZ_S: |
| 14225 | case AArch64::CMPNE_PPzZZ_D: |
| 14226 | case AArch64::CMPNE_PPzZZ_S: |
| 14227 | case AArch64::CMPNE_WIDE_PPzZZ_B: |
| 14228 | case AArch64::CMPNE_WIDE_PPzZZ_S: |
| 14229 | case AArch64::EOR3_ZZZZ: |
| 14230 | case AArch64::EOR_ZPmZ_D: |
| 14231 | case AArch64::EOR_ZPmZ_S: |
| 14232 | case AArch64::FABD_ZPmZ_D: |
| 14233 | case AArch64::FABD_ZPmZ_S: |
| 14234 | case AArch64::FACGE_PPzZZ_D: |
| 14235 | case AArch64::FACGE_PPzZZ_S: |
| 14236 | case AArch64::FACGT_PPzZZ_D: |
| 14237 | case AArch64::FACGT_PPzZZ_S: |
| 14238 | case AArch64::FADDP_ZPmZZ_D: |
| 14239 | case AArch64::FADDP_ZPmZZ_S: |
| 14240 | case AArch64::FADD_ZPmZ_D: |
| 14241 | case AArch64::FADD_ZPmZ_S: |
| 14242 | case AArch64::FAMAX_ZPmZ_D: |
| 14243 | case AArch64::FAMAX_ZPmZ_S: |
| 14244 | case AArch64::FAMIN_ZPmZ_D: |
| 14245 | case AArch64::FAMIN_ZPmZ_S: |
| 14246 | case AArch64::FCMEQ_PPzZZ_D: |
| 14247 | case AArch64::FCMEQ_PPzZZ_S: |
| 14248 | case AArch64::FCMGE_PPzZZ_D: |
| 14249 | case AArch64::FCMGE_PPzZZ_S: |
| 14250 | case AArch64::FCMGT_PPzZZ_D: |
| 14251 | case AArch64::FCMGT_PPzZZ_S: |
| 14252 | case AArch64::FCMNE_PPzZZ_D: |
| 14253 | case AArch64::FCMNE_PPzZZ_S: |
| 14254 | case AArch64::FCMUO_PPzZZ_D: |
| 14255 | case AArch64::FCMUO_PPzZZ_S: |
| 14256 | case AArch64::FDIVR_ZPmZ_D: |
| 14257 | case AArch64::FDIVR_ZPmZ_S: |
| 14258 | case AArch64::FDIV_ZPmZ_D: |
| 14259 | case AArch64::FDIV_ZPmZ_S: |
| 14260 | case AArch64::FMAD_ZPmZZ_D: |
| 14261 | case AArch64::FMAD_ZPmZZ_S: |
| 14262 | case AArch64::FMAXNMP_ZPmZZ_D: |
| 14263 | case AArch64::FMAXNMP_ZPmZZ_S: |
| 14264 | case AArch64::FMAXNM_ZPmZ_D: |
| 14265 | case AArch64::FMAXNM_ZPmZ_S: |
| 14266 | case AArch64::FMAXP_ZPmZZ_D: |
| 14267 | case AArch64::FMAXP_ZPmZZ_S: |
| 14268 | case AArch64::FMAX_ZPmZ_D: |
| 14269 | case AArch64::FMAX_ZPmZ_S: |
| 14270 | case AArch64::FMINNMP_ZPmZZ_D: |
| 14271 | case AArch64::FMINNMP_ZPmZZ_S: |
| 14272 | case AArch64::FMINNM_ZPmZ_D: |
| 14273 | case AArch64::FMINNM_ZPmZ_S: |
| 14274 | case AArch64::FMINP_ZPmZZ_D: |
| 14275 | case AArch64::FMINP_ZPmZZ_S: |
| 14276 | case AArch64::FMIN_ZPmZ_D: |
| 14277 | case AArch64::FMIN_ZPmZ_S: |
| 14278 | case AArch64::FMLAL2lanev8f16: |
| 14279 | case AArch64::FMLALlanev8f16: |
| 14280 | case AArch64::FMLA_ZPmZZ_D: |
| 14281 | case AArch64::FMLA_ZPmZZ_S: |
| 14282 | case AArch64::FMLAv1i16_indexed: |
| 14283 | case AArch64::FMLAv1i32_indexed: |
| 14284 | case AArch64::FMLAv1i64_indexed: |
| 14285 | case AArch64::FMLAv2i32_indexed: |
| 14286 | case AArch64::FMLAv2i64_indexed: |
| 14287 | case AArch64::FMLAv4i16_indexed: |
| 14288 | case AArch64::FMLAv4i32_indexed: |
| 14289 | case AArch64::FMLAv8i16_indexed: |
| 14290 | case AArch64::FMLSL2lanev8f16: |
| 14291 | case AArch64::FMLSLlanev8f16: |
| 14292 | case AArch64::FMLS_ZPmZZ_D: |
| 14293 | case AArch64::FMLS_ZPmZZ_S: |
| 14294 | case AArch64::FMLSv1i16_indexed: |
| 14295 | case AArch64::FMLSv1i32_indexed: |
| 14296 | case AArch64::FMLSv1i64_indexed: |
| 14297 | case AArch64::FMLSv2i32_indexed: |
| 14298 | case AArch64::FMLSv2i64_indexed: |
| 14299 | case AArch64::FMLSv4i16_indexed: |
| 14300 | case AArch64::FMLSv4i32_indexed: |
| 14301 | case AArch64::FMLSv8i16_indexed: |
| 14302 | case AArch64::FMSB_ZPmZZ_D: |
| 14303 | case AArch64::FMSB_ZPmZZ_S: |
| 14304 | case AArch64::FMULX_ZPmZ_D: |
| 14305 | case AArch64::FMULX_ZPmZ_S: |
| 14306 | case AArch64::FMUL_ZPmZ_D: |
| 14307 | case AArch64::FMUL_ZPmZ_S: |
| 14308 | case AArch64::FNMAD_ZPmZZ_D: |
| 14309 | case AArch64::FNMAD_ZPmZZ_S: |
| 14310 | case AArch64::FNMLA_ZPmZZ_D: |
| 14311 | case AArch64::FNMLA_ZPmZZ_S: |
| 14312 | case AArch64::FNMLS_ZPmZZ_D: |
| 14313 | case AArch64::FNMLS_ZPmZZ_S: |
| 14314 | case AArch64::FNMSB_ZPmZZ_D: |
| 14315 | case AArch64::FNMSB_ZPmZZ_S: |
| 14316 | case AArch64::FSCALE_ZPmZ_D: |
| 14317 | case AArch64::FSCALE_ZPmZ_S: |
| 14318 | case AArch64::FSUBR_ZPmZ_D: |
| 14319 | case AArch64::FSUBR_ZPmZ_S: |
| 14320 | case AArch64::FSUB_ZPmZ_D: |
| 14321 | case AArch64::FSUB_ZPmZ_S: |
| 14322 | case AArch64::HISTCNT_ZPzZZ_D: |
| 14323 | case AArch64::HISTCNT_ZPzZZ_S: |
| 14324 | case AArch64::LDPDpost: |
| 14325 | case AArch64::LDPQpost: |
| 14326 | case AArch64::LDPSWpost: |
| 14327 | case AArch64::LDPSpost: |
| 14328 | case AArch64::LDPWpost: |
| 14329 | case AArch64::LDPXpost: |
| 14330 | case AArch64::LDTPQpost: |
| 14331 | case AArch64::LDTPpost: |
| 14332 | case AArch64::LSLR_ZPmZ_D: |
| 14333 | case AArch64::LSLR_ZPmZ_S: |
| 14334 | case AArch64::LSL_WIDE_ZPmZ_B: |
| 14335 | case AArch64::LSL_WIDE_ZPmZ_S: |
| 14336 | case AArch64::LSL_ZPmZ_D: |
| 14337 | case AArch64::LSL_ZPmZ_S: |
| 14338 | case AArch64::LSRR_ZPmZ_D: |
| 14339 | case AArch64::LSRR_ZPmZ_S: |
| 14340 | case AArch64::LSR_WIDE_ZPmZ_B: |
| 14341 | case AArch64::LSR_WIDE_ZPmZ_S: |
| 14342 | case AArch64::LSR_ZPmZ_D: |
| 14343 | case AArch64::LSR_ZPmZ_S: |
| 14344 | case AArch64::MAD_ZPmZZ_D: |
| 14345 | case AArch64::MAD_ZPmZZ_S: |
| 14346 | case AArch64::MLA_ZPmZZ_D: |
| 14347 | case AArch64::MLA_ZPmZZ_S: |
| 14348 | case AArch64::MLAv2i32_indexed: |
| 14349 | case AArch64::MLAv4i16_indexed: |
| 14350 | case AArch64::MLAv4i32_indexed: |
| 14351 | case AArch64::MLAv8i16_indexed: |
| 14352 | case AArch64::MLS_ZPmZZ_D: |
| 14353 | case AArch64::MLS_ZPmZZ_S: |
| 14354 | case AArch64::MLSv2i32_indexed: |
| 14355 | case AArch64::MLSv4i16_indexed: |
| 14356 | case AArch64::MLSv4i32_indexed: |
| 14357 | case AArch64::MLSv8i16_indexed: |
| 14358 | case AArch64::MSB_ZPmZZ_D: |
| 14359 | case AArch64::MSB_ZPmZZ_S: |
| 14360 | case AArch64::MUL_ZPmZ_D: |
| 14361 | case AArch64::MUL_ZPmZ_S: |
| 14362 | case AArch64::NBSL_ZZZZ: |
| 14363 | case AArch64::ORR_ZPmZ_D: |
| 14364 | case AArch64::ORR_ZPmZ_S: |
| 14365 | case AArch64::SABD_ZPmZ_D: |
| 14366 | case AArch64::SABD_ZPmZ_S: |
| 14367 | case AArch64::SDIVR_ZPmZ_D: |
| 14368 | case AArch64::SDIVR_ZPmZ_S: |
| 14369 | case AArch64::SDIV_ZPmZ_D: |
| 14370 | case AArch64::SDIV_ZPmZ_S: |
| 14371 | case AArch64::SEL_ZPZZ_D: |
| 14372 | case AArch64::SEL_ZPZZ_S: |
| 14373 | case AArch64::SHADD_ZPmZ_D: |
| 14374 | case AArch64::SHADD_ZPmZ_S: |
| 14375 | case AArch64::SHSUBR_ZPmZ_D: |
| 14376 | case AArch64::SHSUBR_ZPmZ_S: |
| 14377 | case AArch64::SHSUB_ZPmZ_D: |
| 14378 | case AArch64::SHSUB_ZPmZ_S: |
| 14379 | case AArch64::SM3TT1A: |
| 14380 | case AArch64::SM3TT1B: |
| 14381 | case AArch64::SM3TT2A: |
| 14382 | case AArch64::SM3TT2B: |
| 14383 | case AArch64::SMAXP_ZPmZ_D: |
| 14384 | case AArch64::SMAXP_ZPmZ_S: |
| 14385 | case AArch64::SMAX_ZPmZ_D: |
| 14386 | case AArch64::SMAX_ZPmZ_S: |
| 14387 | case AArch64::SMINP_ZPmZ_D: |
| 14388 | case AArch64::SMINP_ZPmZ_S: |
| 14389 | case AArch64::SMIN_ZPmZ_D: |
| 14390 | case AArch64::SMIN_ZPmZ_S: |
| 14391 | case AArch64::SMLALv2i32_indexed: |
| 14392 | case AArch64::SMLALv4i16_indexed: |
| 14393 | case AArch64::SMLALv4i32_indexed: |
| 14394 | case AArch64::SMLALv8i16_indexed: |
| 14395 | case AArch64::SMLSLv2i32_indexed: |
| 14396 | case AArch64::SMLSLv4i16_indexed: |
| 14397 | case AArch64::SMLSLv4i32_indexed: |
| 14398 | case AArch64::SMLSLv8i16_indexed: |
| 14399 | case AArch64::SMULH_ZPmZ_D: |
| 14400 | case AArch64::SMULH_ZPmZ_S: |
| 14401 | case AArch64::SPLICE_ZPZ_D: |
| 14402 | case AArch64::SPLICE_ZPZ_S: |
| 14403 | case AArch64::SQADD_ZPmZ_D: |
| 14404 | case AArch64::SQADD_ZPmZ_S: |
| 14405 | case AArch64::SQDMLALv1i32_indexed: |
| 14406 | case AArch64::SQDMLALv1i64_indexed: |
| 14407 | case AArch64::SQDMLALv2i32_indexed: |
| 14408 | case AArch64::SQDMLALv4i16_indexed: |
| 14409 | case AArch64::SQDMLALv4i32_indexed: |
| 14410 | case AArch64::SQDMLALv8i16_indexed: |
| 14411 | case AArch64::SQDMLSLv1i32_indexed: |
| 14412 | case AArch64::SQDMLSLv1i64_indexed: |
| 14413 | case AArch64::SQDMLSLv2i32_indexed: |
| 14414 | case AArch64::SQDMLSLv4i16_indexed: |
| 14415 | case AArch64::SQDMLSLv4i32_indexed: |
| 14416 | case AArch64::SQDMLSLv8i16_indexed: |
| 14417 | case AArch64::SQRDMLAHv1i16_indexed: |
| 14418 | case AArch64::SQRDMLAHv1i32_indexed: |
| 14419 | case AArch64::SQRDMLAHv2i32_indexed: |
| 14420 | case AArch64::SQRDMLAHv4i16_indexed: |
| 14421 | case AArch64::SQRDMLAHv4i32_indexed: |
| 14422 | case AArch64::SQRDMLAHv8i16_indexed: |
| 14423 | case AArch64::SQRDMLSHv1i16_indexed: |
| 14424 | case AArch64::SQRDMLSHv1i32_indexed: |
| 14425 | case AArch64::SQRDMLSHv2i32_indexed: |
| 14426 | case AArch64::SQRDMLSHv4i16_indexed: |
| 14427 | case AArch64::SQRDMLSHv4i32_indexed: |
| 14428 | case AArch64::SQRDMLSHv8i16_indexed: |
| 14429 | case AArch64::SQRSHLR_ZPmZ_D: |
| 14430 | case AArch64::SQRSHLR_ZPmZ_S: |
| 14431 | case AArch64::SQRSHL_ZPmZ_D: |
| 14432 | case AArch64::SQRSHL_ZPmZ_S: |
| 14433 | case AArch64::SQSHLR_ZPmZ_D: |
| 14434 | case AArch64::SQSHLR_ZPmZ_S: |
| 14435 | case AArch64::SQSHL_ZPmZ_D: |
| 14436 | case AArch64::SQSHL_ZPmZ_S: |
| 14437 | case AArch64::SQSUBR_ZPmZ_D: |
| 14438 | case AArch64::SQSUBR_ZPmZ_S: |
| 14439 | case AArch64::SQSUB_ZPmZ_D: |
| 14440 | case AArch64::SQSUB_ZPmZ_S: |
| 14441 | case AArch64::SRHADD_ZPmZ_D: |
| 14442 | case AArch64::SRHADD_ZPmZ_S: |
| 14443 | case AArch64::SRSHLR_ZPmZ_D: |
| 14444 | case AArch64::SRSHLR_ZPmZ_S: |
| 14445 | case AArch64::SRSHL_ZPmZ_D: |
| 14446 | case AArch64::SRSHL_ZPmZ_S: |
| 14447 | case AArch64::STGPpost: |
| 14448 | case AArch64::STPDpost: |
| 14449 | case AArch64::STPQpost: |
| 14450 | case AArch64::STPSpost: |
| 14451 | case AArch64::STPWpost: |
| 14452 | case AArch64::STPXpost: |
| 14453 | case AArch64::STTPQpost: |
| 14454 | case AArch64::STTPpost: |
| 14455 | case AArch64::SUBP_ZPmZZ_D: |
| 14456 | case AArch64::SUBP_ZPmZZ_S: |
| 14457 | case AArch64::SUBR_ZPmZ_D: |
| 14458 | case AArch64::SUBR_ZPmZ_S: |
| 14459 | case AArch64::SUB_ZPmZ_CPA: |
| 14460 | case AArch64::SUB_ZPmZ_D: |
| 14461 | case AArch64::SUB_ZPmZ_S: |
| 14462 | case AArch64::SUQADD_ZPmZ_D: |
| 14463 | case AArch64::SUQADD_ZPmZ_S: |
| 14464 | case AArch64::UABD_ZPmZ_D: |
| 14465 | case AArch64::UABD_ZPmZ_S: |
| 14466 | case AArch64::UDIVR_ZPmZ_D: |
| 14467 | case AArch64::UDIVR_ZPmZ_S: |
| 14468 | case AArch64::UDIV_ZPmZ_D: |
| 14469 | case AArch64::UDIV_ZPmZ_S: |
| 14470 | case AArch64::UHADD_ZPmZ_D: |
| 14471 | case AArch64::UHADD_ZPmZ_S: |
| 14472 | case AArch64::UHSUBR_ZPmZ_D: |
| 14473 | case AArch64::UHSUBR_ZPmZ_S: |
| 14474 | case AArch64::UHSUB_ZPmZ_D: |
| 14475 | case AArch64::UHSUB_ZPmZ_S: |
| 14476 | case AArch64::UMAXP_ZPmZ_D: |
| 14477 | case AArch64::UMAXP_ZPmZ_S: |
| 14478 | case AArch64::UMAX_ZPmZ_D: |
| 14479 | case AArch64::UMAX_ZPmZ_S: |
| 14480 | case AArch64::UMINP_ZPmZ_D: |
| 14481 | case AArch64::UMINP_ZPmZ_S: |
| 14482 | case AArch64::UMIN_ZPmZ_D: |
| 14483 | case AArch64::UMIN_ZPmZ_S: |
| 14484 | case AArch64::UMLALv2i32_indexed: |
| 14485 | case AArch64::UMLALv4i16_indexed: |
| 14486 | case AArch64::UMLALv4i32_indexed: |
| 14487 | case AArch64::UMLALv8i16_indexed: |
| 14488 | case AArch64::UMLSLv2i32_indexed: |
| 14489 | case AArch64::UMLSLv4i16_indexed: |
| 14490 | case AArch64::UMLSLv4i32_indexed: |
| 14491 | case AArch64::UMLSLv8i16_indexed: |
| 14492 | case AArch64::UMULH_ZPmZ_D: |
| 14493 | case AArch64::UMULH_ZPmZ_S: |
| 14494 | case AArch64::UQADD_ZPmZ_D: |
| 14495 | case AArch64::UQADD_ZPmZ_S: |
| 14496 | case AArch64::UQRSHLR_ZPmZ_D: |
| 14497 | case AArch64::UQRSHLR_ZPmZ_S: |
| 14498 | case AArch64::UQRSHL_ZPmZ_D: |
| 14499 | case AArch64::UQRSHL_ZPmZ_S: |
| 14500 | case AArch64::UQSHLR_ZPmZ_D: |
| 14501 | case AArch64::UQSHLR_ZPmZ_S: |
| 14502 | case AArch64::UQSHL_ZPmZ_D: |
| 14503 | case AArch64::UQSHL_ZPmZ_S: |
| 14504 | case AArch64::UQSUBR_ZPmZ_D: |
| 14505 | case AArch64::UQSUBR_ZPmZ_S: |
| 14506 | case AArch64::UQSUB_ZPmZ_D: |
| 14507 | case AArch64::UQSUB_ZPmZ_S: |
| 14508 | case AArch64::URHADD_ZPmZ_D: |
| 14509 | case AArch64::URHADD_ZPmZ_S: |
| 14510 | case AArch64::URSHLR_ZPmZ_D: |
| 14511 | case AArch64::URSHLR_ZPmZ_S: |
| 14512 | case AArch64::URSHL_ZPmZ_D: |
| 14513 | case AArch64::URSHL_ZPmZ_S: |
| 14514 | case AArch64::USQADD_ZPmZ_D: |
| 14515 | case AArch64::USQADD_ZPmZ_S: |
| 14516 | return; |
| 14517 | break; |
| 14518 | case AArch64::BCAX: |
| 14519 | case AArch64::CDOT_ZZZI_D: |
| 14520 | case AArch64::CMLA_ZZZI_S: |
| 14521 | case AArch64::EOR3: |
| 14522 | case AArch64::FCADD_ZPmZ_H: |
| 14523 | case AArch64::FCMLA_ZPmZZ_H: |
| 14524 | case AArch64::FCMLA_ZZZI_S: |
| 14525 | case AArch64::LDPDpre: |
| 14526 | case AArch64::LDPQpre: |
| 14527 | case AArch64::LDPSWpre: |
| 14528 | case AArch64::LDPSpre: |
| 14529 | case AArch64::LDPWpre: |
| 14530 | case AArch64::LDPXpre: |
| 14531 | case AArch64::LDTPQpre: |
| 14532 | case AArch64::LDTPpre: |
| 14533 | case AArch64::SM3SS1: |
| 14534 | case AArch64::SQRDCMLAH_ZZZI_S: |
| 14535 | case AArch64::STGPpre: |
| 14536 | case AArch64::STPDpre: |
| 14537 | case AArch64::STPQpre: |
| 14538 | case AArch64::STPSpre: |
| 14539 | case AArch64::STPWpre: |
| 14540 | case AArch64::STPXpre: |
| 14541 | case AArch64::STTPQpre: |
| 14542 | case AArch64::STTPpre: |
| 14543 | switch (MI->getOpcode()) { |
| 14544 | default: llvm_unreachable("Unexpected opcode."); |
| 14545 | case AArch64::BCAX: |
| 14546 | case AArch64::EOR3: |
| 14547 | O << ".16b"; |
| 14548 | break; |
| 14549 | case AArch64::CDOT_ZZZI_D: |
| 14550 | case AArch64::CMLA_ZZZI_S: |
| 14551 | case AArch64::FCMLA_ZPmZZ_H: |
| 14552 | case AArch64::FCMLA_ZZZI_S: |
| 14553 | case AArch64::SQRDCMLAH_ZZZI_S: |
| 14554 | printComplexRotationOp<90, 0>(MI, OpNo: 5, STI, O); |
| 14555 | break; |
| 14556 | case AArch64::FCADD_ZPmZ_H: |
| 14557 | printComplexRotationOp<180, 90>(MI, OpNo: 4, STI, O); |
| 14558 | break; |
| 14559 | case AArch64::LDPDpre: |
| 14560 | case AArch64::LDPQpre: |
| 14561 | case AArch64::LDPSWpre: |
| 14562 | case AArch64::LDPSpre: |
| 14563 | case AArch64::LDPWpre: |
| 14564 | case AArch64::LDPXpre: |
| 14565 | case AArch64::LDTPQpre: |
| 14566 | case AArch64::LDTPpre: |
| 14567 | case AArch64::STGPpre: |
| 14568 | case AArch64::STPDpre: |
| 14569 | case AArch64::STPQpre: |
| 14570 | case AArch64::STPSpre: |
| 14571 | case AArch64::STPWpre: |
| 14572 | case AArch64::STPXpre: |
| 14573 | case AArch64::STTPQpre: |
| 14574 | case AArch64::STTPpre: |
| 14575 | O << "]!"; |
| 14576 | break; |
| 14577 | case AArch64::SM3SS1: |
| 14578 | O << ".4s"; |
| 14579 | break; |
| 14580 | } |
| 14581 | return; |
| 14582 | break; |
| 14583 | case AArch64::FCADD_ZPmZ_D: |
| 14584 | case AArch64::FCADD_ZPmZ_S: |
| 14585 | case AArch64::FCMLA_ZPmZZ_D: |
| 14586 | case AArch64::FCMLA_ZPmZZ_S: |
| 14587 | case AArch64::FCMLAv4f16_indexed: |
| 14588 | case AArch64::FCMLAv4f32_indexed: |
| 14589 | case AArch64::FCMLAv8f16_indexed: |
| 14590 | O << ", "; |
| 14591 | switch (MI->getOpcode()) { |
| 14592 | default: llvm_unreachable("Unexpected opcode."); |
| 14593 | case AArch64::FCADD_ZPmZ_D: |
| 14594 | case AArch64::FCADD_ZPmZ_S: |
| 14595 | printComplexRotationOp<180, 90>(MI, OpNo: 4, STI, O); |
| 14596 | break; |
| 14597 | case AArch64::FCMLA_ZPmZZ_D: |
| 14598 | case AArch64::FCMLA_ZPmZZ_S: |
| 14599 | case AArch64::FCMLAv4f16_indexed: |
| 14600 | case AArch64::FCMLAv4f32_indexed: |
| 14601 | case AArch64::FCMLAv8f16_indexed: |
| 14602 | printComplexRotationOp<90, 0>(MI, OpNo: 5, STI, O); |
| 14603 | break; |
| 14604 | } |
| 14605 | return; |
| 14606 | break; |
| 14607 | } |
| 14608 | } |
| 14609 | |
| 14610 | |
| 14611 | /// getRegisterName - This method is automatically generated by tblgen |
| 14612 | /// from the register set description. This returns the assembler name |
| 14613 | /// for the specified register. |
| 14614 | const char *AArch64InstPrinter:: |
| 14615 | getRegisterName(MCRegister Reg, unsigned AltIdx) { |
| 14616 | unsigned RegNo = Reg.id(); |
| 14617 | assert(RegNo && RegNo < 895 && "Invalid register number!"); |
| 14618 | |
| 14619 | |
| 14620 | #ifdef __GNUC__ |
| 14621 | #pragma GCC diagnostic push |
| 14622 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 14623 | #endif |
| 14624 | static const char AsmStrsNoRegAltName[] = { |
| 14625 | /* 0 */ "D7_D8_D9_D10\000" |
| 14626 | /* 13 */ "P9_P10\000" |
| 14627 | /* 20 */ "Q7_Q8_Q9_Q10\000" |
| 14628 | /* 33 */ "Z2_Z10\000" |
| 14629 | /* 40 */ "Z7_Z8_Z9_Z10\000" |
| 14630 | /* 53 */ "b10\000" |
| 14631 | /* 57 */ "d10\000" |
| 14632 | /* 61 */ "h10\000" |
| 14633 | /* 65 */ "pn10\000" |
| 14634 | /* 70 */ "p10\000" |
| 14635 | /* 74 */ "q10\000" |
| 14636 | /* 78 */ "s10\000" |
| 14637 | /* 82 */ "w10\000" |
| 14638 | /* 86 */ "x10\000" |
| 14639 | /* 90 */ "z10\000" |
| 14640 | /* 94 */ "D17_D18_D19_D20\000" |
| 14641 | /* 110 */ "Q17_Q18_Q19_Q20\000" |
| 14642 | /* 126 */ "Z17_Z18_Z19_Z20\000" |
| 14643 | /* 142 */ "b20\000" |
| 14644 | /* 146 */ "d20\000" |
| 14645 | /* 150 */ "h20\000" |
| 14646 | /* 154 */ "q20\000" |
| 14647 | /* 158 */ "s20\000" |
| 14648 | /* 162 */ "w20\000" |
| 14649 | /* 166 */ "x20\000" |
| 14650 | /* 170 */ "z20\000" |
| 14651 | /* 174 */ "D27_D28_D29_D30\000" |
| 14652 | /* 190 */ "Q27_Q28_Q29_Q30\000" |
| 14653 | /* 206 */ "Z22_Z30\000" |
| 14654 | /* 214 */ "Z18_Z22_Z26_Z30\000" |
| 14655 | /* 230 */ "Z27_Z28_Z29_Z30\000" |
| 14656 | /* 246 */ "b30\000" |
| 14657 | /* 250 */ "d30\000" |
| 14658 | /* 254 */ "h30\000" |
| 14659 | /* 258 */ "q30\000" |
| 14660 | /* 262 */ "s30\000" |
| 14661 | /* 266 */ "w30\000" |
| 14662 | /* 270 */ "x30\000" |
| 14663 | /* 274 */ "z30\000" |
| 14664 | /* 278 */ "D29_D30_D31_D0\000" |
| 14665 | /* 293 */ "P15_P0\000" |
| 14666 | /* 300 */ "Q29_Q30_Q31_Q0\000" |
| 14667 | /* 315 */ "Z29_Z30_Z31_Z0\000" |
| 14668 | /* 330 */ "b0\000" |
| 14669 | /* 333 */ "d0\000" |
| 14670 | /* 336 */ "h0\000" |
| 14671 | /* 339 */ "pn0\000" |
| 14672 | /* 343 */ "p0\000" |
| 14673 | /* 346 */ "q0\000" |
| 14674 | /* 349 */ "s0\000" |
| 14675 | /* 352 */ "zt0\000" |
| 14676 | /* 356 */ "w0\000" |
| 14677 | /* 359 */ "x0\000" |
| 14678 | /* 362 */ "z0\000" |
| 14679 | /* 365 */ "D8_D9_D10_D11\000" |
| 14680 | /* 379 */ "P10_P11\000" |
| 14681 | /* 387 */ "Q8_Q9_Q10_Q11\000" |
| 14682 | /* 401 */ "W10_W11\000" |
| 14683 | /* 409 */ "X4_X5_X6_X7_X8_X9_X10_X11\000" |
| 14684 | /* 435 */ "Z8_Z9_Z10_Z11\000" |
| 14685 | /* 449 */ "Z3_Z11\000" |
| 14686 | /* 456 */ "b11\000" |
| 14687 | /* 460 */ "d11\000" |
| 14688 | /* 464 */ "h11\000" |
| 14689 | /* 468 */ "pn11\000" |
| 14690 | /* 473 */ "p11\000" |
| 14691 | /* 477 */ "q11\000" |
| 14692 | /* 481 */ "s11\000" |
| 14693 | /* 485 */ "w11\000" |
| 14694 | /* 489 */ "x11\000" |
| 14695 | /* 493 */ "z11\000" |
| 14696 | /* 497 */ "D18_D19_D20_D21\000" |
| 14697 | /* 513 */ "Q18_Q19_Q20_Q21\000" |
| 14698 | /* 529 */ "W20_W21\000" |
| 14699 | /* 537 */ "X14_X15_X16_X17_X18_X19_X20_X21\000" |
| 14700 | /* 569 */ "Z18_Z19_Z20_Z21\000" |
| 14701 | /* 585 */ "b21\000" |
| 14702 | /* 589 */ "d21\000" |
| 14703 | /* 593 */ "h21\000" |
| 14704 | /* 597 */ "q21\000" |
| 14705 | /* 601 */ "s21\000" |
| 14706 | /* 605 */ "w21\000" |
| 14707 | /* 609 */ "x21\000" |
| 14708 | /* 613 */ "z21\000" |
| 14709 | /* 617 */ "D28_D29_D30_D31\000" |
| 14710 | /* 633 */ "Q28_Q29_Q30_Q31\000" |
| 14711 | /* 649 */ "Z28_Z29_Z30_Z31\000" |
| 14712 | /* 665 */ "Z23_Z31\000" |
| 14713 | /* 673 */ "Z19_Z23_Z27_Z31\000" |
| 14714 | /* 689 */ "b31\000" |
| 14715 | /* 693 */ "d31\000" |
| 14716 | /* 697 */ "h31\000" |
| 14717 | /* 701 */ "q31\000" |
| 14718 | /* 705 */ "s31\000" |
| 14719 | /* 709 */ "z31\000" |
| 14720 | /* 713 */ "D30_D31_D0_D1\000" |
| 14721 | /* 727 */ "P0_P1\000" |
| 14722 | /* 733 */ "Q30_Q31_Q0_Q1\000" |
| 14723 | /* 747 */ "W0_W1\000" |
| 14724 | /* 753 */ "X0_X1\000" |
| 14725 | /* 759 */ "Z30_Z31_Z0_Z1\000" |
| 14726 | /* 773 */ "b1\000" |
| 14727 | /* 776 */ "d1\000" |
| 14728 | /* 779 */ "h1\000" |
| 14729 | /* 782 */ "pn1\000" |
| 14730 | /* 786 */ "p1\000" |
| 14731 | /* 789 */ "q1\000" |
| 14732 | /* 792 */ "s1\000" |
| 14733 | /* 795 */ "w1\000" |
| 14734 | /* 798 */ "x1\000" |
| 14735 | /* 801 */ "z1\000" |
| 14736 | /* 804 */ "D9_D10_D11_D12\000" |
| 14737 | /* 819 */ "P11_P12\000" |
| 14738 | /* 827 */ "Q9_Q10_Q11_Q12\000" |
| 14739 | /* 842 */ "Z9_Z10_Z11_Z12\000" |
| 14740 | /* 857 */ "Z4_Z12\000" |
| 14741 | /* 864 */ "Z0_Z4_Z8_Z12\000" |
| 14742 | /* 877 */ "b12\000" |
| 14743 | /* 881 */ "d12\000" |
| 14744 | /* 885 */ "h12\000" |
| 14745 | /* 889 */ "pn12\000" |
| 14746 | /* 894 */ "p12\000" |
| 14747 | /* 898 */ "q12\000" |
| 14748 | /* 902 */ "s12\000" |
| 14749 | /* 906 */ "w12\000" |
| 14750 | /* 910 */ "x12\000" |
| 14751 | /* 914 */ "z12\000" |
| 14752 | /* 918 */ "D19_D20_D21_D22\000" |
| 14753 | /* 934 */ "Q19_Q20_Q21_Q22\000" |
| 14754 | /* 950 */ "Z19_Z20_Z21_Z22\000" |
| 14755 | /* 966 */ "b22\000" |
| 14756 | /* 970 */ "d22\000" |
| 14757 | /* 974 */ "h22\000" |
| 14758 | /* 978 */ "q22\000" |
| 14759 | /* 982 */ "s22\000" |
| 14760 | /* 986 */ "w22\000" |
| 14761 | /* 990 */ "x22\000" |
| 14762 | /* 994 */ "z22\000" |
| 14763 | /* 998 */ "D31_D0_D1_D2\000" |
| 14764 | /* 1011 */ "P1_P2\000" |
| 14765 | /* 1017 */ "Q31_Q0_Q1_Q2\000" |
| 14766 | /* 1030 */ "Z31_Z0_Z1_Z2\000" |
| 14767 | /* 1043 */ "b2\000" |
| 14768 | /* 1046 */ "d2\000" |
| 14769 | /* 1049 */ "h2\000" |
| 14770 | /* 1052 */ "pn2\000" |
| 14771 | /* 1056 */ "p2\000" |
| 14772 | /* 1059 */ "q2\000" |
| 14773 | /* 1062 */ "s2\000" |
| 14774 | /* 1065 */ "w2\000" |
| 14775 | /* 1068 */ "x2\000" |
| 14776 | /* 1071 */ "z2\000" |
| 14777 | /* 1074 */ "D10_D11_D12_D13\000" |
| 14778 | /* 1090 */ "P12_P13\000" |
| 14779 | /* 1098 */ "Q10_Q11_Q12_Q13\000" |
| 14780 | /* 1114 */ "W12_W13\000" |
| 14781 | /* 1122 */ "X6_X7_X8_X9_X10_X11_X12_X13\000" |
| 14782 | /* 1150 */ "Z10_Z11_Z12_Z13\000" |
| 14783 | /* 1166 */ "Z5_Z13\000" |
| 14784 | /* 1173 */ "Z1_Z5_Z9_Z13\000" |
| 14785 | /* 1186 */ "b13\000" |
| 14786 | /* 1190 */ "d13\000" |
| 14787 | /* 1194 */ "h13\000" |
| 14788 | /* 1198 */ "pn13\000" |
| 14789 | /* 1203 */ "p13\000" |
| 14790 | /* 1207 */ "q13\000" |
| 14791 | /* 1211 */ "s13\000" |
| 14792 | /* 1215 */ "w13\000" |
| 14793 | /* 1219 */ "x13\000" |
| 14794 | /* 1223 */ "z13\000" |
| 14795 | /* 1227 */ "D20_D21_D22_D23\000" |
| 14796 | /* 1243 */ "Q20_Q21_Q22_Q23\000" |
| 14797 | /* 1259 */ "W22_W23\000" |
| 14798 | /* 1267 */ "X16_X17_X18_X19_X20_X21_X22_X23\000" |
| 14799 | /* 1299 */ "Z20_Z21_Z22_Z23\000" |
| 14800 | /* 1315 */ "b23\000" |
| 14801 | /* 1319 */ "d23\000" |
| 14802 | /* 1323 */ "h23\000" |
| 14803 | /* 1327 */ "q23\000" |
| 14804 | /* 1331 */ "s23\000" |
| 14805 | /* 1335 */ "w23\000" |
| 14806 | /* 1339 */ "x23\000" |
| 14807 | /* 1343 */ "z23\000" |
| 14808 | /* 1347 */ "D0_D1_D2_D3\000" |
| 14809 | /* 1359 */ "P2_P3\000" |
| 14810 | /* 1365 */ "Q0_Q1_Q2_Q3\000" |
| 14811 | /* 1377 */ "W2_W3\000" |
| 14812 | /* 1383 */ "X2_X3\000" |
| 14813 | /* 1389 */ "Z0_Z1_Z2_Z3\000" |
| 14814 | /* 1401 */ "b3\000" |
| 14815 | /* 1404 */ "d3\000" |
| 14816 | /* 1407 */ "h3\000" |
| 14817 | /* 1410 */ "pn3\000" |
| 14818 | /* 1414 */ "p3\000" |
| 14819 | /* 1417 */ "q3\000" |
| 14820 | /* 1420 */ "s3\000" |
| 14821 | /* 1423 */ "w3\000" |
| 14822 | /* 1426 */ "x3\000" |
| 14823 | /* 1429 */ "z3\000" |
| 14824 | /* 1432 */ "D11_D12_D13_D14\000" |
| 14825 | /* 1448 */ "P13_P14\000" |
| 14826 | /* 1456 */ "Q11_Q12_Q13_Q14\000" |
| 14827 | /* 1472 */ "Z2_Z6_Z10_Z14\000" |
| 14828 | /* 1486 */ "Z11_Z12_Z13_Z14\000" |
| 14829 | /* 1502 */ "Z6_Z14\000" |
| 14830 | /* 1509 */ "b14\000" |
| 14831 | /* 1513 */ "d14\000" |
| 14832 | /* 1517 */ "h14\000" |
| 14833 | /* 1521 */ "pn14\000" |
| 14834 | /* 1526 */ "p14\000" |
| 14835 | /* 1530 */ "q14\000" |
| 14836 | /* 1534 */ "s14\000" |
| 14837 | /* 1538 */ "w14\000" |
| 14838 | /* 1542 */ "x14\000" |
| 14839 | /* 1546 */ "z14\000" |
| 14840 | /* 1550 */ "D21_D22_D23_D24\000" |
| 14841 | /* 1566 */ "Q21_Q22_Q23_Q24\000" |
| 14842 | /* 1582 */ "Z21_Z22_Z23_Z24\000" |
| 14843 | /* 1598 */ "Z16_Z24\000" |
| 14844 | /* 1606 */ "b24\000" |
| 14845 | /* 1610 */ "d24\000" |
| 14846 | /* 1614 */ "h24\000" |
| 14847 | /* 1618 */ "q24\000" |
| 14848 | /* 1622 */ "s24\000" |
| 14849 | /* 1626 */ "w24\000" |
| 14850 | /* 1630 */ "x24\000" |
| 14851 | /* 1634 */ "z24\000" |
| 14852 | /* 1638 */ "D1_D2_D3_D4\000" |
| 14853 | /* 1650 */ "P3_P4\000" |
| 14854 | /* 1656 */ "Q1_Q2_Q3_Q4\000" |
| 14855 | /* 1668 */ "Z1_Z2_Z3_Z4\000" |
| 14856 | /* 1680 */ "b4\000" |
| 14857 | /* 1683 */ "d4\000" |
| 14858 | /* 1686 */ "h4\000" |
| 14859 | /* 1689 */ "pn4\000" |
| 14860 | /* 1693 */ "p4\000" |
| 14861 | /* 1696 */ "q4\000" |
| 14862 | /* 1699 */ "s4\000" |
| 14863 | /* 1702 */ "w4\000" |
| 14864 | /* 1705 */ "x4\000" |
| 14865 | /* 1708 */ "z4\000" |
| 14866 | /* 1711 */ "D12_D13_D14_D15\000" |
| 14867 | /* 1727 */ "P14_P15\000" |
| 14868 | /* 1735 */ "Q12_Q13_Q14_Q15\000" |
| 14869 | /* 1751 */ "W14_W15\000" |
| 14870 | /* 1759 */ "X8_X9_X10_X11_X12_X13_X14_X15\000" |
| 14871 | /* 1789 */ "Z3_Z7_Z11_Z15\000" |
| 14872 | /* 1803 */ "Z12_Z13_Z14_Z15\000" |
| 14873 | /* 1819 */ "Z7_Z15\000" |
| 14874 | /* 1826 */ "b15\000" |
| 14875 | /* 1830 */ "d15\000" |
| 14876 | /* 1834 */ "h15\000" |
| 14877 | /* 1838 */ "pn15\000" |
| 14878 | /* 1843 */ "p15\000" |
| 14879 | /* 1847 */ "q15\000" |
| 14880 | /* 1851 */ "s15\000" |
| 14881 | /* 1855 */ "w15\000" |
| 14882 | /* 1859 */ "x15\000" |
| 14883 | /* 1863 */ "z15\000" |
| 14884 | /* 1867 */ "D22_D23_D24_D25\000" |
| 14885 | /* 1883 */ "Q22_Q23_Q24_Q25\000" |
| 14886 | /* 1899 */ "W24_W25\000" |
| 14887 | /* 1907 */ "X18_X19_X20_X21_X22_X23_X24_X25\000" |
| 14888 | /* 1939 */ "Z22_Z23_Z24_Z25\000" |
| 14889 | /* 1955 */ "Z17_Z25\000" |
| 14890 | /* 1963 */ "b25\000" |
| 14891 | /* 1967 */ "d25\000" |
| 14892 | /* 1971 */ "h25\000" |
| 14893 | /* 1975 */ "q25\000" |
| 14894 | /* 1979 */ "s25\000" |
| 14895 | /* 1983 */ "w25\000" |
| 14896 | /* 1987 */ "x25\000" |
| 14897 | /* 1991 */ "z25\000" |
| 14898 | /* 1995 */ "D2_D3_D4_D5\000" |
| 14899 | /* 2007 */ "P4_P5\000" |
| 14900 | /* 2013 */ "Q2_Q3_Q4_Q5\000" |
| 14901 | /* 2025 */ "W4_W5\000" |
| 14902 | /* 2031 */ "X4_X5\000" |
| 14903 | /* 2037 */ "Z2_Z3_Z4_Z5\000" |
| 14904 | /* 2049 */ "b5\000" |
| 14905 | /* 2052 */ "d5\000" |
| 14906 | /* 2055 */ "h5\000" |
| 14907 | /* 2058 */ "pn5\000" |
| 14908 | /* 2062 */ "p5\000" |
| 14909 | /* 2065 */ "q5\000" |
| 14910 | /* 2068 */ "s5\000" |
| 14911 | /* 2071 */ "w5\000" |
| 14912 | /* 2074 */ "x5\000" |
| 14913 | /* 2077 */ "z5\000" |
| 14914 | /* 2080 */ "D13_D14_D15_D16\000" |
| 14915 | /* 2096 */ "Q13_Q14_Q15_Q16\000" |
| 14916 | /* 2112 */ "Z13_Z14_Z15_Z16\000" |
| 14917 | /* 2128 */ "b16\000" |
| 14918 | /* 2132 */ "d16\000" |
| 14919 | /* 2136 */ "h16\000" |
| 14920 | /* 2140 */ "q16\000" |
| 14921 | /* 2144 */ "s16\000" |
| 14922 | /* 2148 */ "w16\000" |
| 14923 | /* 2152 */ "x16\000" |
| 14924 | /* 2156 */ "z16\000" |
| 14925 | /* 2160 */ "D23_D24_D25_D26\000" |
| 14926 | /* 2176 */ "Q23_Q24_Q25_Q26\000" |
| 14927 | /* 2192 */ "Z23_Z24_Z25_Z26\000" |
| 14928 | /* 2208 */ "Z18_Z26\000" |
| 14929 | /* 2216 */ "b26\000" |
| 14930 | /* 2220 */ "d26\000" |
| 14931 | /* 2224 */ "h26\000" |
| 14932 | /* 2228 */ "q26\000" |
| 14933 | /* 2232 */ "s26\000" |
| 14934 | /* 2236 */ "w26\000" |
| 14935 | /* 2240 */ "x26\000" |
| 14936 | /* 2244 */ "z26\000" |
| 14937 | /* 2248 */ "D3_D4_D5_D6\000" |
| 14938 | /* 2260 */ "P5_P6\000" |
| 14939 | /* 2266 */ "Q3_Q4_Q5_Q6\000" |
| 14940 | /* 2278 */ "Z3_Z4_Z5_Z6\000" |
| 14941 | /* 2290 */ "b6\000" |
| 14942 | /* 2293 */ "d6\000" |
| 14943 | /* 2296 */ "h6\000" |
| 14944 | /* 2299 */ "pn6\000" |
| 14945 | /* 2303 */ "p6\000" |
| 14946 | /* 2306 */ "q6\000" |
| 14947 | /* 2309 */ "s6\000" |
| 14948 | /* 2312 */ "w6\000" |
| 14949 | /* 2315 */ "x6\000" |
| 14950 | /* 2318 */ "z6\000" |
| 14951 | /* 2321 */ "D14_D15_D16_D17\000" |
| 14952 | /* 2337 */ "Q14_Q15_Q16_Q17\000" |
| 14953 | /* 2353 */ "W16_W17\000" |
| 14954 | /* 2361 */ "X10_X11_X12_X13_X14_X15_X16_X17\000" |
| 14955 | /* 2393 */ "Z14_Z15_Z16_Z17\000" |
| 14956 | /* 2409 */ "b17\000" |
| 14957 | /* 2413 */ "d17\000" |
| 14958 | /* 2417 */ "h17\000" |
| 14959 | /* 2421 */ "q17\000" |
| 14960 | /* 2425 */ "s17\000" |
| 14961 | /* 2429 */ "w17\000" |
| 14962 | /* 2433 */ "x17\000" |
| 14963 | /* 2437 */ "z17\000" |
| 14964 | /* 2441 */ "D24_D25_D26_D27\000" |
| 14965 | /* 2457 */ "Q24_Q25_Q26_Q27\000" |
| 14966 | /* 2473 */ "W26_W27\000" |
| 14967 | /* 2481 */ "X20_X21_X22_X23_X24_X25_X26_X27\000" |
| 14968 | /* 2513 */ "Z24_Z25_Z26_Z27\000" |
| 14969 | /* 2529 */ "Z19_Z27\000" |
| 14970 | /* 2537 */ "b27\000" |
| 14971 | /* 2541 */ "d27\000" |
| 14972 | /* 2545 */ "h27\000" |
| 14973 | /* 2549 */ "q27\000" |
| 14974 | /* 2553 */ "s27\000" |
| 14975 | /* 2557 */ "w27\000" |
| 14976 | /* 2561 */ "x27\000" |
| 14977 | /* 2565 */ "z27\000" |
| 14978 | /* 2569 */ "D4_D5_D6_D7\000" |
| 14979 | /* 2581 */ "P6_P7\000" |
| 14980 | /* 2587 */ "Q4_Q5_Q6_Q7\000" |
| 14981 | /* 2599 */ "W6_W7\000" |
| 14982 | /* 2605 */ "X0_X1_X2_X3_X4_X5_X6_X7\000" |
| 14983 | /* 2629 */ "Z4_Z5_Z6_Z7\000" |
| 14984 | /* 2641 */ "b7\000" |
| 14985 | /* 2644 */ "d7\000" |
| 14986 | /* 2647 */ "h7\000" |
| 14987 | /* 2650 */ "pn7\000" |
| 14988 | /* 2654 */ "p7\000" |
| 14989 | /* 2657 */ "q7\000" |
| 14990 | /* 2660 */ "s7\000" |
| 14991 | /* 2663 */ "w7\000" |
| 14992 | /* 2666 */ "x7\000" |
| 14993 | /* 2669 */ "z7\000" |
| 14994 | /* 2672 */ "D15_D16_D17_D18\000" |
| 14995 | /* 2688 */ "Q15_Q16_Q17_Q18\000" |
| 14996 | /* 2704 */ "Z15_Z16_Z17_Z18\000" |
| 14997 | /* 2720 */ "b18\000" |
| 14998 | /* 2724 */ "d18\000" |
| 14999 | /* 2728 */ "h18\000" |
| 15000 | /* 2732 */ "q18\000" |
| 15001 | /* 2736 */ "s18\000" |
| 15002 | /* 2740 */ "w18\000" |
| 15003 | /* 2744 */ "x18\000" |
| 15004 | /* 2748 */ "z18\000" |
| 15005 | /* 2752 */ "D25_D26_D27_D28\000" |
| 15006 | /* 2768 */ "Q25_Q26_Q27_Q28\000" |
| 15007 | /* 2784 */ "Z20_Z28\000" |
| 15008 | /* 2792 */ "Z16_Z20_Z24_Z28\000" |
| 15009 | /* 2808 */ "Z25_Z26_Z27_Z28\000" |
| 15010 | /* 2824 */ "b28\000" |
| 15011 | /* 2828 */ "d28\000" |
| 15012 | /* 2832 */ "h28\000" |
| 15013 | /* 2836 */ "q28\000" |
| 15014 | /* 2840 */ "s28\000" |
| 15015 | /* 2844 */ "w28\000" |
| 15016 | /* 2848 */ "x28\000" |
| 15017 | /* 2852 */ "z28\000" |
| 15018 | /* 2856 */ "D5_D6_D7_D8\000" |
| 15019 | /* 2868 */ "P7_P8\000" |
| 15020 | /* 2874 */ "Q5_Q6_Q7_Q8\000" |
| 15021 | /* 2886 */ "Z0_Z8\000" |
| 15022 | /* 2892 */ "Z5_Z6_Z7_Z8\000" |
| 15023 | /* 2904 */ "b8\000" |
| 15024 | /* 2907 */ "d8\000" |
| 15025 | /* 2910 */ "h8\000" |
| 15026 | /* 2913 */ "pn8\000" |
| 15027 | /* 2917 */ "p8\000" |
| 15028 | /* 2920 */ "q8\000" |
| 15029 | /* 2923 */ "s8\000" |
| 15030 | /* 2926 */ "w8\000" |
| 15031 | /* 2929 */ "x8\000" |
| 15032 | /* 2932 */ "z8\000" |
| 15033 | /* 2935 */ "D16_D17_D18_D19\000" |
| 15034 | /* 2951 */ "Q16_Q17_Q18_Q19\000" |
| 15035 | /* 2967 */ "W18_W19\000" |
| 15036 | /* 2975 */ "X12_X13_X14_X15_X16_X17_X18_X19\000" |
| 15037 | /* 3007 */ "Z16_Z17_Z18_Z19\000" |
| 15038 | /* 3023 */ "b19\000" |
| 15039 | /* 3027 */ "d19\000" |
| 15040 | /* 3031 */ "h19\000" |
| 15041 | /* 3035 */ "q19\000" |
| 15042 | /* 3039 */ "s19\000" |
| 15043 | /* 3043 */ "w19\000" |
| 15044 | /* 3047 */ "x19\000" |
| 15045 | /* 3051 */ "z19\000" |
| 15046 | /* 3055 */ "D26_D27_D28_D29\000" |
| 15047 | /* 3071 */ "Q26_Q27_Q28_Q29\000" |
| 15048 | /* 3087 */ "W28_W29\000" |
| 15049 | /* 3095 */ "Z21_Z29\000" |
| 15050 | /* 3103 */ "Z17_Z21_Z25_Z29\000" |
| 15051 | /* 3119 */ "Z26_Z27_Z28_Z29\000" |
| 15052 | /* 3135 */ "b29\000" |
| 15053 | /* 3139 */ "d29\000" |
| 15054 | /* 3143 */ "h29\000" |
| 15055 | /* 3147 */ "q29\000" |
| 15056 | /* 3151 */ "s29\000" |
| 15057 | /* 3155 */ "w29\000" |
| 15058 | /* 3159 */ "x29\000" |
| 15059 | /* 3163 */ "z29\000" |
| 15060 | /* 3167 */ "D6_D7_D8_D9\000" |
| 15061 | /* 3179 */ "P8_P9\000" |
| 15062 | /* 3185 */ "Q6_Q7_Q8_Q9\000" |
| 15063 | /* 3197 */ "W8_W9\000" |
| 15064 | /* 3203 */ "X2_X3_X4_X5_X6_X7_X8_X9\000" |
| 15065 | /* 3227 */ "Z1_Z9\000" |
| 15066 | /* 3233 */ "Z6_Z7_Z8_Z9\000" |
| 15067 | /* 3245 */ "b9\000" |
| 15068 | /* 3248 */ "d9\000" |
| 15069 | /* 3251 */ "h9\000" |
| 15070 | /* 3254 */ "pn9\000" |
| 15071 | /* 3258 */ "p9\000" |
| 15072 | /* 3261 */ "q9\000" |
| 15073 | /* 3264 */ "s9\000" |
| 15074 | /* 3267 */ "w9\000" |
| 15075 | /* 3270 */ "x9\000" |
| 15076 | /* 3273 */ "z9\000" |
| 15077 | /* 3276 */ "X22_X23_X24_X25_X26_X27_X28_FP\000" |
| 15078 | /* 3307 */ "W30_WZR\000" |
| 15079 | /* 3315 */ "LR_XZR\000" |
| 15080 | /* 3322 */ "za\000" |
| 15081 | /* 3325 */ "za0.b\000" |
| 15082 | /* 3331 */ "za0.d\000" |
| 15083 | /* 3337 */ "za1.d\000" |
| 15084 | /* 3343 */ "za2.d\000" |
| 15085 | /* 3349 */ "za3.d\000" |
| 15086 | /* 3355 */ "za4.d\000" |
| 15087 | /* 3361 */ "za5.d\000" |
| 15088 | /* 3367 */ "za6.d\000" |
| 15089 | /* 3373 */ "za7.d\000" |
| 15090 | /* 3379 */ "vg\000" |
| 15091 | /* 3382 */ "za0.h\000" |
| 15092 | /* 3388 */ "za1.h\000" |
| 15093 | /* 3394 */ "b10_hi\000" |
| 15094 | /* 3401 */ "d10_hi\000" |
| 15095 | /* 3408 */ "h10_hi\000" |
| 15096 | /* 3415 */ "q10_hi\000" |
| 15097 | /* 3422 */ "s10_hi\000" |
| 15098 | /* 3429 */ "w10_hi\000" |
| 15099 | /* 3436 */ "b20_hi\000" |
| 15100 | /* 3443 */ "d20_hi\000" |
| 15101 | /* 3450 */ "h20_hi\000" |
| 15102 | /* 3457 */ "q20_hi\000" |
| 15103 | /* 3464 */ "s20_hi\000" |
| 15104 | /* 3471 */ "w20_hi\000" |
| 15105 | /* 3478 */ "b30_hi\000" |
| 15106 | /* 3485 */ "d30_hi\000" |
| 15107 | /* 3492 */ "h30_hi\000" |
| 15108 | /* 3499 */ "q30_hi\000" |
| 15109 | /* 3506 */ "s30_hi\000" |
| 15110 | /* 3513 */ "w30_hi\000" |
| 15111 | /* 3520 */ "b0_hi\000" |
| 15112 | /* 3526 */ "d0_hi\000" |
| 15113 | /* 3532 */ "h0_hi\000" |
| 15114 | /* 3538 */ "q0_hi\000" |
| 15115 | /* 3544 */ "s0_hi\000" |
| 15116 | /* 3550 */ "w0_hi\000" |
| 15117 | /* 3556 */ "b11_hi\000" |
| 15118 | /* 3563 */ "d11_hi\000" |
| 15119 | /* 3570 */ "h11_hi\000" |
| 15120 | /* 3577 */ "q11_hi\000" |
| 15121 | /* 3584 */ "s11_hi\000" |
| 15122 | /* 3591 */ "w11_hi\000" |
| 15123 | /* 3598 */ "b21_hi\000" |
| 15124 | /* 3605 */ "d21_hi\000" |
| 15125 | /* 3612 */ "h21_hi\000" |
| 15126 | /* 3619 */ "q21_hi\000" |
| 15127 | /* 3626 */ "s21_hi\000" |
| 15128 | /* 3633 */ "w21_hi\000" |
| 15129 | /* 3640 */ "b31_hi\000" |
| 15130 | /* 3647 */ "d31_hi\000" |
| 15131 | /* 3654 */ "h31_hi\000" |
| 15132 | /* 3661 */ "q31_hi\000" |
| 15133 | /* 3668 */ "s31_hi\000" |
| 15134 | /* 3675 */ "b1_hi\000" |
| 15135 | /* 3681 */ "d1_hi\000" |
| 15136 | /* 3687 */ "h1_hi\000" |
| 15137 | /* 3693 */ "q1_hi\000" |
| 15138 | /* 3699 */ "s1_hi\000" |
| 15139 | /* 3705 */ "w1_hi\000" |
| 15140 | /* 3711 */ "b12_hi\000" |
| 15141 | /* 3718 */ "d12_hi\000" |
| 15142 | /* 3725 */ "h12_hi\000" |
| 15143 | /* 3732 */ "q12_hi\000" |
| 15144 | /* 3739 */ "s12_hi\000" |
| 15145 | /* 3746 */ "w12_hi\000" |
| 15146 | /* 3753 */ "b22_hi\000" |
| 15147 | /* 3760 */ "d22_hi\000" |
| 15148 | /* 3767 */ "h22_hi\000" |
| 15149 | /* 3774 */ "q22_hi\000" |
| 15150 | /* 3781 */ "s22_hi\000" |
| 15151 | /* 3788 */ "w22_hi\000" |
| 15152 | /* 3795 */ "b2_hi\000" |
| 15153 | /* 3801 */ "d2_hi\000" |
| 15154 | /* 3807 */ "h2_hi\000" |
| 15155 | /* 3813 */ "q2_hi\000" |
| 15156 | /* 3819 */ "s2_hi\000" |
| 15157 | /* 3825 */ "w2_hi\000" |
| 15158 | /* 3831 */ "b13_hi\000" |
| 15159 | /* 3838 */ "d13_hi\000" |
| 15160 | /* 3845 */ "h13_hi\000" |
| 15161 | /* 3852 */ "q13_hi\000" |
| 15162 | /* 3859 */ "s13_hi\000" |
| 15163 | /* 3866 */ "w13_hi\000" |
| 15164 | /* 3873 */ "b23_hi\000" |
| 15165 | /* 3880 */ "d23_hi\000" |
| 15166 | /* 3887 */ "h23_hi\000" |
| 15167 | /* 3894 */ "q23_hi\000" |
| 15168 | /* 3901 */ "s23_hi\000" |
| 15169 | /* 3908 */ "w23_hi\000" |
| 15170 | /* 3915 */ "b3_hi\000" |
| 15171 | /* 3921 */ "d3_hi\000" |
| 15172 | /* 3927 */ "h3_hi\000" |
| 15173 | /* 3933 */ "q3_hi\000" |
| 15174 | /* 3939 */ "s3_hi\000" |
| 15175 | /* 3945 */ "w3_hi\000" |
| 15176 | /* 3951 */ "b14_hi\000" |
| 15177 | /* 3958 */ "d14_hi\000" |
| 15178 | /* 3965 */ "h14_hi\000" |
| 15179 | /* 3972 */ "q14_hi\000" |
| 15180 | /* 3979 */ "s14_hi\000" |
| 15181 | /* 3986 */ "w14_hi\000" |
| 15182 | /* 3993 */ "b24_hi\000" |
| 15183 | /* 4000 */ "d24_hi\000" |
| 15184 | /* 4007 */ "h24_hi\000" |
| 15185 | /* 4014 */ "q24_hi\000" |
| 15186 | /* 4021 */ "s24_hi\000" |
| 15187 | /* 4028 */ "w24_hi\000" |
| 15188 | /* 4035 */ "b4_hi\000" |
| 15189 | /* 4041 */ "d4_hi\000" |
| 15190 | /* 4047 */ "h4_hi\000" |
| 15191 | /* 4053 */ "q4_hi\000" |
| 15192 | /* 4059 */ "s4_hi\000" |
| 15193 | /* 4065 */ "w4_hi\000" |
| 15194 | /* 4071 */ "b15_hi\000" |
| 15195 | /* 4078 */ "d15_hi\000" |
| 15196 | /* 4085 */ "h15_hi\000" |
| 15197 | /* 4092 */ "q15_hi\000" |
| 15198 | /* 4099 */ "s15_hi\000" |
| 15199 | /* 4106 */ "w15_hi\000" |
| 15200 | /* 4113 */ "b25_hi\000" |
| 15201 | /* 4120 */ "d25_hi\000" |
| 15202 | /* 4127 */ "h25_hi\000" |
| 15203 | /* 4134 */ "q25_hi\000" |
| 15204 | /* 4141 */ "s25_hi\000" |
| 15205 | /* 4148 */ "w25_hi\000" |
| 15206 | /* 4155 */ "b5_hi\000" |
| 15207 | /* 4161 */ "d5_hi\000" |
| 15208 | /* 4167 */ "h5_hi\000" |
| 15209 | /* 4173 */ "q5_hi\000" |
| 15210 | /* 4179 */ "s5_hi\000" |
| 15211 | /* 4185 */ "w5_hi\000" |
| 15212 | /* 4191 */ "b16_hi\000" |
| 15213 | /* 4198 */ "d16_hi\000" |
| 15214 | /* 4205 */ "h16_hi\000" |
| 15215 | /* 4212 */ "q16_hi\000" |
| 15216 | /* 4219 */ "s16_hi\000" |
| 15217 | /* 4226 */ "w16_hi\000" |
| 15218 | /* 4233 */ "b26_hi\000" |
| 15219 | /* 4240 */ "d26_hi\000" |
| 15220 | /* 4247 */ "h26_hi\000" |
| 15221 | /* 4254 */ "q26_hi\000" |
| 15222 | /* 4261 */ "s26_hi\000" |
| 15223 | /* 4268 */ "w26_hi\000" |
| 15224 | /* 4275 */ "b6_hi\000" |
| 15225 | /* 4281 */ "d6_hi\000" |
| 15226 | /* 4287 */ "h6_hi\000" |
| 15227 | /* 4293 */ "q6_hi\000" |
| 15228 | /* 4299 */ "s6_hi\000" |
| 15229 | /* 4305 */ "w6_hi\000" |
| 15230 | /* 4311 */ "b17_hi\000" |
| 15231 | /* 4318 */ "d17_hi\000" |
| 15232 | /* 4325 */ "h17_hi\000" |
| 15233 | /* 4332 */ "q17_hi\000" |
| 15234 | /* 4339 */ "s17_hi\000" |
| 15235 | /* 4346 */ "w17_hi\000" |
| 15236 | /* 4353 */ "b27_hi\000" |
| 15237 | /* 4360 */ "d27_hi\000" |
| 15238 | /* 4367 */ "h27_hi\000" |
| 15239 | /* 4374 */ "q27_hi\000" |
| 15240 | /* 4381 */ "s27_hi\000" |
| 15241 | /* 4388 */ "w27_hi\000" |
| 15242 | /* 4395 */ "b7_hi\000" |
| 15243 | /* 4401 */ "d7_hi\000" |
| 15244 | /* 4407 */ "h7_hi\000" |
| 15245 | /* 4413 */ "q7_hi\000" |
| 15246 | /* 4419 */ "s7_hi\000" |
| 15247 | /* 4425 */ "w7_hi\000" |
| 15248 | /* 4431 */ "b18_hi\000" |
| 15249 | /* 4438 */ "d18_hi\000" |
| 15250 | /* 4445 */ "h18_hi\000" |
| 15251 | /* 4452 */ "q18_hi\000" |
| 15252 | /* 4459 */ "s18_hi\000" |
| 15253 | /* 4466 */ "w18_hi\000" |
| 15254 | /* 4473 */ "b28_hi\000" |
| 15255 | /* 4480 */ "d28_hi\000" |
| 15256 | /* 4487 */ "h28_hi\000" |
| 15257 | /* 4494 */ "q28_hi\000" |
| 15258 | /* 4501 */ "s28_hi\000" |
| 15259 | /* 4508 */ "w28_hi\000" |
| 15260 | /* 4515 */ "b8_hi\000" |
| 15261 | /* 4521 */ "d8_hi\000" |
| 15262 | /* 4527 */ "h8_hi\000" |
| 15263 | /* 4533 */ "q8_hi\000" |
| 15264 | /* 4539 */ "s8_hi\000" |
| 15265 | /* 4545 */ "w8_hi\000" |
| 15266 | /* 4551 */ "b19_hi\000" |
| 15267 | /* 4558 */ "d19_hi\000" |
| 15268 | /* 4565 */ "h19_hi\000" |
| 15269 | /* 4572 */ "q19_hi\000" |
| 15270 | /* 4579 */ "s19_hi\000" |
| 15271 | /* 4586 */ "w19_hi\000" |
| 15272 | /* 4593 */ "b29_hi\000" |
| 15273 | /* 4600 */ "d29_hi\000" |
| 15274 | /* 4607 */ "h29_hi\000" |
| 15275 | /* 4614 */ "q29_hi\000" |
| 15276 | /* 4621 */ "s29_hi\000" |
| 15277 | /* 4628 */ "w29_hi\000" |
| 15278 | /* 4635 */ "b9_hi\000" |
| 15279 | /* 4641 */ "d9_hi\000" |
| 15280 | /* 4647 */ "h9_hi\000" |
| 15281 | /* 4653 */ "q9_hi\000" |
| 15282 | /* 4659 */ "s9_hi\000" |
| 15283 | /* 4665 */ "w9_hi\000" |
| 15284 | /* 4671 */ "wsp_hi\000" |
| 15285 | /* 4678 */ "wzr_hi\000" |
| 15286 | /* 4685 */ "wsp\000" |
| 15287 | /* 4689 */ "za10.q\000" |
| 15288 | /* 4696 */ "za0.q\000" |
| 15289 | /* 4702 */ "za11.q\000" |
| 15290 | /* 4709 */ "za1.q\000" |
| 15291 | /* 4715 */ "za12.q\000" |
| 15292 | /* 4722 */ "za2.q\000" |
| 15293 | /* 4728 */ "za13.q\000" |
| 15294 | /* 4735 */ "za3.q\000" |
| 15295 | /* 4741 */ "za14.q\000" |
| 15296 | /* 4748 */ "za4.q\000" |
| 15297 | /* 4754 */ "za15.q\000" |
| 15298 | /* 4761 */ "za5.q\000" |
| 15299 | /* 4767 */ "za6.q\000" |
| 15300 | /* 4773 */ "za7.q\000" |
| 15301 | /* 4779 */ "za8.q\000" |
| 15302 | /* 4785 */ "za9.q\000" |
| 15303 | /* 4791 */ "fpcr\000" |
| 15304 | /* 4796 */ "ffr\000" |
| 15305 | /* 4800 */ "fpmr\000" |
| 15306 | /* 4805 */ "fpsr\000" |
| 15307 | /* 4810 */ "wzr\000" |
| 15308 | /* 4814 */ "xzr\000" |
| 15309 | /* 4818 */ "za0.s\000" |
| 15310 | /* 4824 */ "za1.s\000" |
| 15311 | /* 4830 */ "za2.s\000" |
| 15312 | /* 4836 */ "za3.s\000" |
| 15313 | /* 4842 */ "nzcv\000" |
| 15314 | }; |
| 15315 | #ifdef __GNUC__ |
| 15316 | #pragma GCC diagnostic pop |
| 15317 | #endif |
| 15318 | |
| 15319 | static const uint16_t RegAsmOffsetNoRegAltName[] = { |
| 15320 | 4796, 3159, 4791, 4800, 4805, 270, 4842, 4686, 3379, 4685, 4671, 4810, 4678, 4814, |
| 15321 | 3322, 330, 773, 1043, 1401, 1680, 2049, 2290, 2641, 2904, 3245, 53, 456, 877, |
| 15322 | 1186, 1509, 1826, 2128, 2409, 2720, 3023, 142, 585, 966, 1315, 1606, 1963, 2216, |
| 15323 | 2537, 2824, 3135, 246, 689, 333, 776, 1046, 1404, 1683, 2052, 2293, 2644, 2907, |
| 15324 | 3248, 57, 460, 881, 1190, 1513, 1830, 2132, 2413, 2724, 3027, 146, 589, 970, |
| 15325 | 1319, 1610, 1967, 2220, 2541, 2828, 3139, 250, 693, 336, 779, 1049, 1407, 1686, |
| 15326 | 2055, 2296, 2647, 2910, 3251, 61, 464, 885, 1194, 1517, 1834, 2136, 2417, 2728, |
| 15327 | 3031, 150, 593, 974, 1323, 1614, 1971, 2224, 2545, 2832, 3143, 254, 697, 343, |
| 15328 | 786, 1056, 1414, 1693, 2062, 2303, 2654, 2917, 3258, 70, 473, 894, 1203, 1526, |
| 15329 | 1843, 339, 782, 1052, 1410, 1689, 2058, 2299, 2650, 2913, 3254, 65, 468, 889, |
| 15330 | 1198, 1521, 1838, 346, 789, 1059, 1417, 1696, 2065, 2306, 2657, 2920, 3261, 74, |
| 15331 | 477, 898, 1207, 1530, 1847, 2140, 2421, 2732, 3035, 154, 597, 978, 1327, 1618, |
| 15332 | 1975, 2228, 2549, 2836, 3147, 258, 701, 349, 792, 1062, 1420, 1699, 2068, 2309, |
| 15333 | 2660, 2923, 3264, 78, 481, 902, 1211, 1534, 1851, 2144, 2425, 2736, 3039, 158, |
| 15334 | 601, 982, 1331, 1622, 1979, 2232, 2553, 2840, 3151, 262, 705, 356, 795, 1065, |
| 15335 | 1423, 1702, 2071, 2312, 2663, 2926, 3267, 82, 485, 906, 1215, 1538, 1855, 2148, |
| 15336 | 2429, 2740, 3043, 162, 605, 986, 1335, 1626, 1983, 2236, 2557, 2844, 3155, 266, |
| 15337 | 359, 798, 1068, 1426, 1705, 2074, 2315, 2666, 2929, 3270, 86, 489, 910, 1219, |
| 15338 | 1542, 1859, 2152, 2433, 2744, 3047, 166, 609, 990, 1339, 1630, 1987, 2240, 2561, |
| 15339 | 2848, 362, 801, 1071, 1429, 1708, 2077, 2318, 2669, 2932, 3273, 90, 493, 914, |
| 15340 | 1223, 1546, 1863, 2156, 2437, 2748, 3051, 170, 613, 994, 1343, 1634, 1991, 2244, |
| 15341 | 2565, 2852, 3163, 274, 709, 3325, 3331, 3337, 3343, 3349, 3355, 3361, 3367, 3373, |
| 15342 | 3382, 3388, 4696, 4709, 4722, 4735, 4748, 4761, 4767, 4773, 4779, 4785, 4689, 4702, |
| 15343 | 4715, 4728, 4741, 4754, 4818, 4824, 4830, 4836, 352, 3520, 3675, 3795, 3915, 4035, |
| 15344 | 4155, 4275, 4395, 4515, 4635, 3394, 3556, 3711, 3831, 3951, 4071, 4191, 4311, 4431, |
| 15345 | 4551, 3436, 3598, 3753, 3873, 3993, 4113, 4233, 4353, 4473, 4593, 3478, 3640, 3526, |
| 15346 | 3681, 3801, 3921, 4041, 4161, 4281, 4401, 4521, 4641, 3401, 3563, 3718, 3838, 3958, |
| 15347 | 4078, 4198, 4318, 4438, 4558, 3443, 3605, 3760, 3880, 4000, 4120, 4240, 4360, 4480, |
| 15348 | 4600, 3485, 3647, 3532, 3687, 3807, 3927, 4047, 4167, 4287, 4407, 4527, 4647, 3408, |
| 15349 | 3570, 3725, 3845, 3965, 4085, 4205, 4325, 4445, 4565, 3450, 3612, 3767, 3887, 4007, |
| 15350 | 4127, 4247, 4367, 4487, 4607, 3492, 3654, 3538, 3693, 3813, 3933, 4053, 4173, 4293, |
| 15351 | 4413, 4533, 4653, 3415, 3577, 3732, 3852, 3972, 4092, 4212, 4332, 4452, 4572, 3457, |
| 15352 | 3619, 3774, 3894, 4014, 4134, 4254, 4374, 4494, 4614, 3499, 3661, 3544, 3699, 3819, |
| 15353 | 3939, 4059, 4179, 4299, 4419, 4539, 4659, 3422, 3584, 3739, 3859, 3979, 4099, 4219, |
| 15354 | 4339, 4459, 4579, 3464, 3626, 3781, 3901, 4021, 4141, 4261, 4381, 4501, 4621, 3506, |
| 15355 | 3668, 3550, 3705, 3825, 3945, 4065, 4185, 4305, 4425, 4545, 4665, 3429, 3591, 3746, |
| 15356 | 3866, 3986, 4106, 4226, 4346, 4466, 4586, 3471, 3633, 3788, 3908, 4028, 4148, 4268, |
| 15357 | 4388, 4508, 4628, 3513, 721, 1005, 1353, 1644, 2001, 2254, 2575, 2862, 3173, 6, |
| 15358 | 371, 811, 1082, 1440, 1719, 2088, 2329, 2680, 2943, 102, 505, 926, 1235, 1558, |
| 15359 | 1875, 2168, 2449, 2760, 3063, 182, 625, 286, 1347, 1638, 1995, 2248, 2569, 2856, |
| 15360 | 3167, 0, 365, 804, 1074, 1432, 1711, 2080, 2321, 2672, 2935, 94, 497, 918, |
| 15361 | 1227, 1550, 1867, 2160, 2441, 2752, 3055, 174, 617, 278, 713, 998, 1002, 1350, |
| 15362 | 1641, 1998, 2251, 2572, 2859, 3170, 3, 368, 807, 1078, 1436, 1715, 2084, 2325, |
| 15363 | 2676, 2939, 98, 501, 922, 1231, 1554, 1871, 2164, 2445, 2756, 3059, 178, 621, |
| 15364 | 282, 717, 727, 1011, 1359, 1650, 2007, 2260, 2581, 2868, 3179, 13, 379, 819, |
| 15365 | 1090, 1448, 1727, 293, 741, 1024, 1371, 1662, 2019, 2272, 2593, 2880, 3191, 26, |
| 15366 | 393, 834, 1106, 1464, 1743, 2104, 2345, 2696, 2959, 118, 521, 942, 1251, 1574, |
| 15367 | 1891, 2184, 2465, 2776, 3079, 198, 641, 308, 1365, 1656, 2013, 2266, 2587, 2874, |
| 15368 | 3185, 20, 387, 827, 1098, 1456, 1735, 2096, 2337, 2688, 2951, 110, 513, 934, |
| 15369 | 1243, 1566, 1883, 2176, 2457, 2768, 3071, 190, 633, 300, 733, 1017, 1021, 1368, |
| 15370 | 1659, 2016, 2269, 2590, 2877, 3188, 23, 390, 830, 1102, 1460, 1739, 2100, 2341, |
| 15371 | 2692, 2955, 114, 517, 938, 1247, 1570, 1887, 2180, 2461, 2772, 3075, 194, 637, |
| 15372 | 304, 737, 3276, 2605, 3203, 409, 1122, 1759, 2361, 2975, 537, 1267, 1907, 2481, |
| 15373 | 3307, 747, 1377, 2025, 2599, 3197, 401, 1114, 1751, 2353, 2967, 529, 1259, 1899, |
| 15374 | 2473, 3087, 3315, 3300, 753, 1383, 2031, 2623, 3221, 427, 1142, 1781, 2385, 2999, |
| 15375 | 561, 1291, 1931, 2505, 767, 1037, 1395, 1674, 2043, 2284, 2635, 2898, 3239, 46, |
| 15376 | 441, 849, 1158, 1494, 1811, 2120, 2401, 2712, 3015, 134, 577, 958, 1307, 1590, |
| 15377 | 1947, 2200, 2521, 2816, 3127, 238, 657, 323, 1389, 1668, 2037, 2278, 2629, 2892, |
| 15378 | 3233, 40, 435, 842, 1150, 1486, 1803, 2112, 2393, 2704, 3007, 126, 569, 950, |
| 15379 | 1299, 1582, 1939, 2192, 2513, 2808, 3119, 230, 649, 315, 759, 1030, 1034, 1392, |
| 15380 | 1671, 2040, 2281, 2632, 2895, 3236, 43, 438, 845, 1154, 1490, 1807, 2116, 2397, |
| 15381 | 2708, 3011, 130, 573, 954, 1303, 1586, 1943, 2196, 2517, 2812, 3123, 234, 653, |
| 15382 | 319, 763, 1598, 1955, 2208, 2529, 2784, 3095, 206, 665, 2886, 3227, 33, 449, |
| 15383 | 857, 1166, 1502, 1819, 2792, 3103, 214, 673, 864, 1173, 1472, 1789, |
| 15384 | }; |
| 15385 | |
| 15386 | |
| 15387 | #ifdef __GNUC__ |
| 15388 | #pragma GCC diagnostic push |
| 15389 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 15390 | #endif |
| 15391 | static const char AsmStrsvlist1[] = { |
| 15392 | /* 0 */ "\000" |
| 15393 | }; |
| 15394 | #ifdef __GNUC__ |
| 15395 | #pragma GCC diagnostic pop |
| 15396 | #endif |
| 15397 | |
| 15398 | static const uint8_t RegAsmOffsetvlist1[] = { |
| 15399 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15400 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15401 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15402 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15403 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15404 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15405 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15406 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15407 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15408 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15409 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15410 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15411 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15412 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15413 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15414 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15415 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15416 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15417 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15418 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15419 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15420 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15421 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15422 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15423 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15424 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15425 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15426 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15427 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15428 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15429 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15430 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15431 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15432 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15433 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15434 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15435 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15436 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15437 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15438 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15439 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15440 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15441 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15442 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15443 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15444 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15445 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15446 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15447 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15448 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15449 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15450 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15451 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15452 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15453 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15454 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15455 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15456 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15457 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15458 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15459 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15460 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15461 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15462 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 15463 | }; |
| 15464 | |
| 15465 | |
| 15466 | #ifdef __GNUC__ |
| 15467 | #pragma GCC diagnostic push |
| 15468 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 15469 | #endif |
| 15470 | static const char AsmStrsvreg[] = { |
| 15471 | /* 0 */ "v10\000" |
| 15472 | /* 4 */ "v20\000" |
| 15473 | /* 8 */ "v30\000" |
| 15474 | /* 12 */ "v0\000" |
| 15475 | /* 15 */ "v11\000" |
| 15476 | /* 19 */ "v21\000" |
| 15477 | /* 23 */ "v31\000" |
| 15478 | /* 27 */ "v1\000" |
| 15479 | /* 30 */ "v12\000" |
| 15480 | /* 34 */ "v22\000" |
| 15481 | /* 38 */ "v2\000" |
| 15482 | /* 41 */ "v13\000" |
| 15483 | /* 45 */ "v23\000" |
| 15484 | /* 49 */ "v3\000" |
| 15485 | /* 52 */ "v14\000" |
| 15486 | /* 56 */ "v24\000" |
| 15487 | /* 60 */ "v4\000" |
| 15488 | /* 63 */ "v15\000" |
| 15489 | /* 67 */ "v25\000" |
| 15490 | /* 71 */ "v5\000" |
| 15491 | /* 74 */ "v16\000" |
| 15492 | /* 78 */ "v26\000" |
| 15493 | /* 82 */ "v6\000" |
| 15494 | /* 85 */ "v17\000" |
| 15495 | /* 89 */ "v27\000" |
| 15496 | /* 93 */ "v7\000" |
| 15497 | /* 96 */ "v18\000" |
| 15498 | /* 100 */ "v28\000" |
| 15499 | /* 104 */ "v8\000" |
| 15500 | /* 107 */ "v19\000" |
| 15501 | /* 111 */ "v29\000" |
| 15502 | /* 115 */ "v9\000" |
| 15503 | }; |
| 15504 | #ifdef __GNUC__ |
| 15505 | #pragma GCC diagnostic pop |
| 15506 | #endif |
| 15507 | |
| 15508 | static const uint8_t RegAsmOffsetvreg[] = { |
| 15509 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15510 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15511 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15512 | 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, |
| 15513 | 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, |
| 15514 | 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, |
| 15515 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15516 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15517 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15518 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15519 | 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, |
| 15520 | 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, |
| 15521 | 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, |
| 15522 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15523 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15524 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15525 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15526 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15527 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15528 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15529 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15530 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15531 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15532 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15533 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15534 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15535 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15536 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15537 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15538 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15539 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15540 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15541 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15542 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15543 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15544 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15545 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15546 | 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, |
| 15547 | 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, |
| 15548 | 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, |
| 15549 | 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 15550 | 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, |
| 15551 | 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 15552 | 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 15553 | 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15554 | 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, |
| 15555 | 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, |
| 15556 | 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, |
| 15557 | 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 15558 | 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, |
| 15559 | 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 15560 | 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 15561 | 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15562 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15563 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15564 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15565 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15566 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15567 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15568 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15569 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15570 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15571 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15572 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 15573 | }; |
| 15574 | |
| 15575 | switch(AltIdx) { |
| 15576 | default: llvm_unreachable("Invalid register alt name index!"); |
| 15577 | case AArch64::NoRegAltName: |
| 15578 | assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| 15579 | "Invalid alt name index for register!"); |
| 15580 | return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| 15581 | case AArch64::vlist1: |
| 15582 | assert(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) && |
| 15583 | "Invalid alt name index for register!"); |
| 15584 | return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]; |
| 15585 | case AArch64::vreg: |
| 15586 | assert(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) && |
| 15587 | "Invalid alt name index for register!"); |
| 15588 | return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]; |
| 15589 | } |
| 15590 | } |
| 15591 | |
| 15592 | #ifdef PRINT_ALIAS_INSTR |
| 15593 | #undef PRINT_ALIAS_INSTR |
| 15594 | |
| 15595 | static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp, |
| 15596 | const MCSubtargetInfo &STI, |
| 15597 | unsigned PredicateIndex); |
| 15598 | bool AArch64InstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| 15599 | static const PatternsForOpcode OpToPatterns[] = { |
| 15600 | {.Opcode: AArch64::ADDPT_shift, .PatternStart: 0, .NumPatterns: 1 }, |
| 15601 | {.Opcode: AArch64::ADDSWri, .PatternStart: 1, .NumPatterns: 1 }, |
| 15602 | {.Opcode: AArch64::ADDSWrs, .PatternStart: 2, .NumPatterns: 3 }, |
| 15603 | {.Opcode: AArch64::ADDSWrx, .PatternStart: 5, .NumPatterns: 3 }, |
| 15604 | {.Opcode: AArch64::ADDSXri, .PatternStart: 8, .NumPatterns: 1 }, |
| 15605 | {.Opcode: AArch64::ADDSXrs, .PatternStart: 9, .NumPatterns: 3 }, |
| 15606 | {.Opcode: AArch64::ADDSXrx, .PatternStart: 12, .NumPatterns: 1 }, |
| 15607 | {.Opcode: AArch64::ADDSXrx64, .PatternStart: 13, .NumPatterns: 3 }, |
| 15608 | {.Opcode: AArch64::ADDWri, .PatternStart: 16, .NumPatterns: 2 }, |
| 15609 | {.Opcode: AArch64::ADDWrs, .PatternStart: 18, .NumPatterns: 1 }, |
| 15610 | {.Opcode: AArch64::ADDWrx, .PatternStart: 19, .NumPatterns: 2 }, |
| 15611 | {.Opcode: AArch64::ADDXri, .PatternStart: 21, .NumPatterns: 2 }, |
| 15612 | {.Opcode: AArch64::ADDXrs, .PatternStart: 23, .NumPatterns: 1 }, |
| 15613 | {.Opcode: AArch64::ADDXrx64, .PatternStart: 24, .NumPatterns: 2 }, |
| 15614 | {.Opcode: AArch64::ANDSWri, .PatternStart: 26, .NumPatterns: 1 }, |
| 15615 | {.Opcode: AArch64::ANDSWrs, .PatternStart: 27, .NumPatterns: 3 }, |
| 15616 | {.Opcode: AArch64::ANDSXri, .PatternStart: 30, .NumPatterns: 1 }, |
| 15617 | {.Opcode: AArch64::ANDSXrs, .PatternStart: 31, .NumPatterns: 3 }, |
| 15618 | {.Opcode: AArch64::ANDS_PPzPP, .PatternStart: 34, .NumPatterns: 1 }, |
| 15619 | {.Opcode: AArch64::ANDWrs, .PatternStart: 35, .NumPatterns: 1 }, |
| 15620 | {.Opcode: AArch64::ANDXrs, .PatternStart: 36, .NumPatterns: 1 }, |
| 15621 | {.Opcode: AArch64::AND_PPzPP, .PatternStart: 37, .NumPatterns: 1 }, |
| 15622 | {.Opcode: AArch64::AND_ZI, .PatternStart: 38, .NumPatterns: 3 }, |
| 15623 | {.Opcode: AArch64::AUTIA1716, .PatternStart: 41, .NumPatterns: 1 }, |
| 15624 | {.Opcode: AArch64::AUTIASP, .PatternStart: 42, .NumPatterns: 1 }, |
| 15625 | {.Opcode: AArch64::AUTIAZ, .PatternStart: 43, .NumPatterns: 1 }, |
| 15626 | {.Opcode: AArch64::AUTIB1716, .PatternStart: 44, .NumPatterns: 1 }, |
| 15627 | {.Opcode: AArch64::AUTIBSP, .PatternStart: 45, .NumPatterns: 1 }, |
| 15628 | {.Opcode: AArch64::AUTIBZ, .PatternStart: 46, .NumPatterns: 1 }, |
| 15629 | {.Opcode: AArch64::BICSWrs, .PatternStart: 47, .NumPatterns: 1 }, |
| 15630 | {.Opcode: AArch64::BICSXrs, .PatternStart: 48, .NumPatterns: 1 }, |
| 15631 | {.Opcode: AArch64::BICWrs, .PatternStart: 49, .NumPatterns: 1 }, |
| 15632 | {.Opcode: AArch64::BICXrs, .PatternStart: 50, .NumPatterns: 1 }, |
| 15633 | {.Opcode: AArch64::CHKFEAT, .PatternStart: 51, .NumPatterns: 1 }, |
| 15634 | {.Opcode: AArch64::CLREX, .PatternStart: 52, .NumPatterns: 1 }, |
| 15635 | {.Opcode: AArch64::CNTB_XPiI, .PatternStart: 53, .NumPatterns: 2 }, |
| 15636 | {.Opcode: AArch64::CNTD_XPiI, .PatternStart: 55, .NumPatterns: 2 }, |
| 15637 | {.Opcode: AArch64::CNTH_XPiI, .PatternStart: 57, .NumPatterns: 2 }, |
| 15638 | {.Opcode: AArch64::CNTW_XPiI, .PatternStart: 59, .NumPatterns: 2 }, |
| 15639 | {.Opcode: AArch64::CPY_ZPmI_B, .PatternStart: 61, .NumPatterns: 1 }, |
| 15640 | {.Opcode: AArch64::CPY_ZPmI_D, .PatternStart: 62, .NumPatterns: 1 }, |
| 15641 | {.Opcode: AArch64::CPY_ZPmI_H, .PatternStart: 63, .NumPatterns: 1 }, |
| 15642 | {.Opcode: AArch64::CPY_ZPmI_S, .PatternStart: 64, .NumPatterns: 1 }, |
| 15643 | {.Opcode: AArch64::CPY_ZPmR_B, .PatternStart: 65, .NumPatterns: 1 }, |
| 15644 | {.Opcode: AArch64::CPY_ZPmR_D, .PatternStart: 66, .NumPatterns: 1 }, |
| 15645 | {.Opcode: AArch64::CPY_ZPmR_H, .PatternStart: 67, .NumPatterns: 1 }, |
| 15646 | {.Opcode: AArch64::CPY_ZPmR_S, .PatternStart: 68, .NumPatterns: 1 }, |
| 15647 | {.Opcode: AArch64::CPY_ZPmV_B, .PatternStart: 69, .NumPatterns: 1 }, |
| 15648 | {.Opcode: AArch64::CPY_ZPmV_D, .PatternStart: 70, .NumPatterns: 1 }, |
| 15649 | {.Opcode: AArch64::CPY_ZPmV_H, .PatternStart: 71, .NumPatterns: 1 }, |
| 15650 | {.Opcode: AArch64::CPY_ZPmV_S, .PatternStart: 72, .NumPatterns: 1 }, |
| 15651 | {.Opcode: AArch64::CPY_ZPzI_B, .PatternStart: 73, .NumPatterns: 1 }, |
| 15652 | {.Opcode: AArch64::CPY_ZPzI_D, .PatternStart: 74, .NumPatterns: 1 }, |
| 15653 | {.Opcode: AArch64::CPY_ZPzI_H, .PatternStart: 75, .NumPatterns: 1 }, |
| 15654 | {.Opcode: AArch64::CPY_ZPzI_S, .PatternStart: 76, .NumPatterns: 1 }, |
| 15655 | {.Opcode: AArch64::CSINCWr, .PatternStart: 77, .NumPatterns: 2 }, |
| 15656 | {.Opcode: AArch64::CSINCXr, .PatternStart: 79, .NumPatterns: 2 }, |
| 15657 | {.Opcode: AArch64::CSINVWr, .PatternStart: 81, .NumPatterns: 2 }, |
| 15658 | {.Opcode: AArch64::CSINVXr, .PatternStart: 83, .NumPatterns: 2 }, |
| 15659 | {.Opcode: AArch64::CSNEGWr, .PatternStart: 85, .NumPatterns: 1 }, |
| 15660 | {.Opcode: AArch64::CSNEGXr, .PatternStart: 86, .NumPatterns: 1 }, |
| 15661 | {.Opcode: AArch64::DCPS1, .PatternStart: 87, .NumPatterns: 1 }, |
| 15662 | {.Opcode: AArch64::DCPS2, .PatternStart: 88, .NumPatterns: 1 }, |
| 15663 | {.Opcode: AArch64::DCPS3, .PatternStart: 89, .NumPatterns: 1 }, |
| 15664 | {.Opcode: AArch64::DECB_XPiI, .PatternStart: 90, .NumPatterns: 2 }, |
| 15665 | {.Opcode: AArch64::DECD_XPiI, .PatternStart: 92, .NumPatterns: 2 }, |
| 15666 | {.Opcode: AArch64::DECD_ZPiI, .PatternStart: 94, .NumPatterns: 2 }, |
| 15667 | {.Opcode: AArch64::DECH_XPiI, .PatternStart: 96, .NumPatterns: 2 }, |
| 15668 | {.Opcode: AArch64::DECH_ZPiI, .PatternStart: 98, .NumPatterns: 2 }, |
| 15669 | {.Opcode: AArch64::DECW_XPiI, .PatternStart: 100, .NumPatterns: 2 }, |
| 15670 | {.Opcode: AArch64::DECW_ZPiI, .PatternStart: 102, .NumPatterns: 2 }, |
| 15671 | {.Opcode: AArch64::DSB, .PatternStart: 104, .NumPatterns: 3 }, |
| 15672 | {.Opcode: AArch64::DUPM_ZI, .PatternStart: 107, .NumPatterns: 6 }, |
| 15673 | {.Opcode: AArch64::DUP_ZI_B, .PatternStart: 113, .NumPatterns: 1 }, |
| 15674 | {.Opcode: AArch64::DUP_ZI_D, .PatternStart: 114, .NumPatterns: 2 }, |
| 15675 | {.Opcode: AArch64::DUP_ZI_H, .PatternStart: 116, .NumPatterns: 2 }, |
| 15676 | {.Opcode: AArch64::DUP_ZI_S, .PatternStart: 118, .NumPatterns: 2 }, |
| 15677 | {.Opcode: AArch64::DUP_ZR_B, .PatternStart: 120, .NumPatterns: 1 }, |
| 15678 | {.Opcode: AArch64::DUP_ZR_D, .PatternStart: 121, .NumPatterns: 1 }, |
| 15679 | {.Opcode: AArch64::DUP_ZR_H, .PatternStart: 122, .NumPatterns: 1 }, |
| 15680 | {.Opcode: AArch64::DUP_ZR_S, .PatternStart: 123, .NumPatterns: 1 }, |
| 15681 | {.Opcode: AArch64::DUP_ZZI_B, .PatternStart: 124, .NumPatterns: 2 }, |
| 15682 | {.Opcode: AArch64::DUP_ZZI_D, .PatternStart: 126, .NumPatterns: 2 }, |
| 15683 | {.Opcode: AArch64::DUP_ZZI_H, .PatternStart: 128, .NumPatterns: 2 }, |
| 15684 | {.Opcode: AArch64::DUP_ZZI_Q, .PatternStart: 130, .NumPatterns: 2 }, |
| 15685 | {.Opcode: AArch64::DUP_ZZI_S, .PatternStart: 132, .NumPatterns: 2 }, |
| 15686 | {.Opcode: AArch64::EONWrs, .PatternStart: 134, .NumPatterns: 1 }, |
| 15687 | {.Opcode: AArch64::EONXrs, .PatternStart: 135, .NumPatterns: 1 }, |
| 15688 | {.Opcode: AArch64::EORS_PPzPP, .PatternStart: 136, .NumPatterns: 1 }, |
| 15689 | {.Opcode: AArch64::EORWrs, .PatternStart: 137, .NumPatterns: 1 }, |
| 15690 | {.Opcode: AArch64::EORXrs, .PatternStart: 138, .NumPatterns: 1 }, |
| 15691 | {.Opcode: AArch64::EOR_PPzPP, .PatternStart: 139, .NumPatterns: 1 }, |
| 15692 | {.Opcode: AArch64::EOR_ZI, .PatternStart: 140, .NumPatterns: 3 }, |
| 15693 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_B, .PatternStart: 143, .NumPatterns: 1 }, |
| 15694 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_D, .PatternStart: 144, .NumPatterns: 1 }, |
| 15695 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_H, .PatternStart: 145, .NumPatterns: 1 }, |
| 15696 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_Q, .PatternStart: 146, .NumPatterns: 1 }, |
| 15697 | {.Opcode: AArch64::EXTRACT_ZPMXI_H_S, .PatternStart: 147, .NumPatterns: 1 }, |
| 15698 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_B, .PatternStart: 148, .NumPatterns: 1 }, |
| 15699 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_D, .PatternStart: 149, .NumPatterns: 1 }, |
| 15700 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_H, .PatternStart: 150, .NumPatterns: 1 }, |
| 15701 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_Q, .PatternStart: 151, .NumPatterns: 1 }, |
| 15702 | {.Opcode: AArch64::EXTRACT_ZPMXI_V_S, .PatternStart: 152, .NumPatterns: 1 }, |
| 15703 | {.Opcode: AArch64::EXTRWrri, .PatternStart: 153, .NumPatterns: 1 }, |
| 15704 | {.Opcode: AArch64::EXTRXrri, .PatternStart: 154, .NumPatterns: 1 }, |
| 15705 | {.Opcode: AArch64::FCPY_ZPmI_D, .PatternStart: 155, .NumPatterns: 1 }, |
| 15706 | {.Opcode: AArch64::FCPY_ZPmI_H, .PatternStart: 156, .NumPatterns: 1 }, |
| 15707 | {.Opcode: AArch64::FCPY_ZPmI_S, .PatternStart: 157, .NumPatterns: 1 }, |
| 15708 | {.Opcode: AArch64::FDUP_ZI_D, .PatternStart: 158, .NumPatterns: 1 }, |
| 15709 | {.Opcode: AArch64::FDUP_ZI_H, .PatternStart: 159, .NumPatterns: 1 }, |
| 15710 | {.Opcode: AArch64::FDUP_ZI_S, .PatternStart: 160, .NumPatterns: 1 }, |
| 15711 | {.Opcode: AArch64::GCSPOPM, .PatternStart: 161, .NumPatterns: 1 }, |
| 15712 | {.Opcode: AArch64::GLD1B_D_IMM, .PatternStart: 162, .NumPatterns: 1 }, |
| 15713 | {.Opcode: AArch64::GLD1B_S_IMM, .PatternStart: 163, .NumPatterns: 1 }, |
| 15714 | {.Opcode: AArch64::GLD1D_IMM, .PatternStart: 164, .NumPatterns: 1 }, |
| 15715 | {.Opcode: AArch64::GLD1H_D_IMM, .PatternStart: 165, .NumPatterns: 1 }, |
| 15716 | {.Opcode: AArch64::GLD1H_S_IMM, .PatternStart: 166, .NumPatterns: 1 }, |
| 15717 | {.Opcode: AArch64::GLD1Q, .PatternStart: 167, .NumPatterns: 1 }, |
| 15718 | {.Opcode: AArch64::GLD1SB_D_IMM, .PatternStart: 168, .NumPatterns: 1 }, |
| 15719 | {.Opcode: AArch64::GLD1SB_S_IMM, .PatternStart: 169, .NumPatterns: 1 }, |
| 15720 | {.Opcode: AArch64::GLD1SH_D_IMM, .PatternStart: 170, .NumPatterns: 1 }, |
| 15721 | {.Opcode: AArch64::GLD1SH_S_IMM, .PatternStart: 171, .NumPatterns: 1 }, |
| 15722 | {.Opcode: AArch64::GLD1SW_D_IMM, .PatternStart: 172, .NumPatterns: 1 }, |
| 15723 | {.Opcode: AArch64::GLD1W_D_IMM, .PatternStart: 173, .NumPatterns: 1 }, |
| 15724 | {.Opcode: AArch64::GLD1W_IMM, .PatternStart: 174, .NumPatterns: 1 }, |
| 15725 | {.Opcode: AArch64::GLDFF1B_D_IMM, .PatternStart: 175, .NumPatterns: 1 }, |
| 15726 | {.Opcode: AArch64::GLDFF1B_S_IMM, .PatternStart: 176, .NumPatterns: 1 }, |
| 15727 | {.Opcode: AArch64::GLDFF1D_IMM, .PatternStart: 177, .NumPatterns: 1 }, |
| 15728 | {.Opcode: AArch64::GLDFF1H_D_IMM, .PatternStart: 178, .NumPatterns: 1 }, |
| 15729 | {.Opcode: AArch64::GLDFF1H_S_IMM, .PatternStart: 179, .NumPatterns: 1 }, |
| 15730 | {.Opcode: AArch64::GLDFF1SB_D_IMM, .PatternStart: 180, .NumPatterns: 1 }, |
| 15731 | {.Opcode: AArch64::GLDFF1SB_S_IMM, .PatternStart: 181, .NumPatterns: 1 }, |
| 15732 | {.Opcode: AArch64::GLDFF1SH_D_IMM, .PatternStart: 182, .NumPatterns: 1 }, |
| 15733 | {.Opcode: AArch64::GLDFF1SH_S_IMM, .PatternStart: 183, .NumPatterns: 1 }, |
| 15734 | {.Opcode: AArch64::GLDFF1SW_D_IMM, .PatternStart: 184, .NumPatterns: 1 }, |
| 15735 | {.Opcode: AArch64::GLDFF1W_D_IMM, .PatternStart: 185, .NumPatterns: 1 }, |
| 15736 | {.Opcode: AArch64::GLDFF1W_IMM, .PatternStart: 186, .NumPatterns: 1 }, |
| 15737 | {.Opcode: AArch64::HINT, .PatternStart: 187, .NumPatterns: 25 }, |
| 15738 | {.Opcode: AArch64::INCB_XPiI, .PatternStart: 212, .NumPatterns: 2 }, |
| 15739 | {.Opcode: AArch64::INCD_XPiI, .PatternStart: 214, .NumPatterns: 2 }, |
| 15740 | {.Opcode: AArch64::INCD_ZPiI, .PatternStart: 216, .NumPatterns: 2 }, |
| 15741 | {.Opcode: AArch64::INCH_XPiI, .PatternStart: 218, .NumPatterns: 2 }, |
| 15742 | {.Opcode: AArch64::INCH_ZPiI, .PatternStart: 220, .NumPatterns: 2 }, |
| 15743 | {.Opcode: AArch64::INCW_XPiI, .PatternStart: 222, .NumPatterns: 2 }, |
| 15744 | {.Opcode: AArch64::INCW_ZPiI, .PatternStart: 224, .NumPatterns: 2 }, |
| 15745 | {.Opcode: AArch64::INSERT_MXIPZ_H_B, .PatternStart: 226, .NumPatterns: 1 }, |
| 15746 | {.Opcode: AArch64::INSERT_MXIPZ_H_D, .PatternStart: 227, .NumPatterns: 1 }, |
| 15747 | {.Opcode: AArch64::INSERT_MXIPZ_H_H, .PatternStart: 228, .NumPatterns: 1 }, |
| 15748 | {.Opcode: AArch64::INSERT_MXIPZ_H_Q, .PatternStart: 229, .NumPatterns: 1 }, |
| 15749 | {.Opcode: AArch64::INSERT_MXIPZ_H_S, .PatternStart: 230, .NumPatterns: 1 }, |
| 15750 | {.Opcode: AArch64::INSERT_MXIPZ_V_B, .PatternStart: 231, .NumPatterns: 1 }, |
| 15751 | {.Opcode: AArch64::INSERT_MXIPZ_V_D, .PatternStart: 232, .NumPatterns: 1 }, |
| 15752 | {.Opcode: AArch64::INSERT_MXIPZ_V_H, .PatternStart: 233, .NumPatterns: 1 }, |
| 15753 | {.Opcode: AArch64::INSERT_MXIPZ_V_Q, .PatternStart: 234, .NumPatterns: 1 }, |
| 15754 | {.Opcode: AArch64::INSERT_MXIPZ_V_S, .PatternStart: 235, .NumPatterns: 1 }, |
| 15755 | {.Opcode: AArch64::INSvi16gpr, .PatternStart: 236, .NumPatterns: 1 }, |
| 15756 | {.Opcode: AArch64::INSvi16lane, .PatternStart: 237, .NumPatterns: 1 }, |
| 15757 | {.Opcode: AArch64::INSvi32gpr, .PatternStart: 238, .NumPatterns: 1 }, |
| 15758 | {.Opcode: AArch64::INSvi32lane, .PatternStart: 239, .NumPatterns: 1 }, |
| 15759 | {.Opcode: AArch64::INSvi64gpr, .PatternStart: 240, .NumPatterns: 1 }, |
| 15760 | {.Opcode: AArch64::INSvi64lane, .PatternStart: 241, .NumPatterns: 1 }, |
| 15761 | {.Opcode: AArch64::INSvi8gpr, .PatternStart: 242, .NumPatterns: 1 }, |
| 15762 | {.Opcode: AArch64::INSvi8lane, .PatternStart: 243, .NumPatterns: 1 }, |
| 15763 | {.Opcode: AArch64::IRG, .PatternStart: 244, .NumPatterns: 1 }, |
| 15764 | {.Opcode: AArch64::ISB, .PatternStart: 245, .NumPatterns: 1 }, |
| 15765 | {.Opcode: AArch64::LD1B_2Z_IMM, .PatternStart: 246, .NumPatterns: 1 }, |
| 15766 | {.Opcode: AArch64::LD1B_2Z_STRIDED_IMM, .PatternStart: 247, .NumPatterns: 1 }, |
| 15767 | {.Opcode: AArch64::LD1B_4Z_IMM, .PatternStart: 248, .NumPatterns: 1 }, |
| 15768 | {.Opcode: AArch64::LD1B_4Z_STRIDED_IMM, .PatternStart: 249, .NumPatterns: 1 }, |
| 15769 | {.Opcode: AArch64::LD1B_D_IMM, .PatternStart: 250, .NumPatterns: 1 }, |
| 15770 | {.Opcode: AArch64::LD1B_H_IMM, .PatternStart: 251, .NumPatterns: 1 }, |
| 15771 | {.Opcode: AArch64::LD1B_IMM, .PatternStart: 252, .NumPatterns: 1 }, |
| 15772 | {.Opcode: AArch64::LD1B_S_IMM, .PatternStart: 253, .NumPatterns: 1 }, |
| 15773 | {.Opcode: AArch64::LD1D_2Z_IMM, .PatternStart: 254, .NumPatterns: 1 }, |
| 15774 | {.Opcode: AArch64::LD1D_2Z_STRIDED_IMM, .PatternStart: 255, .NumPatterns: 1 }, |
| 15775 | {.Opcode: AArch64::LD1D_4Z_IMM, .PatternStart: 256, .NumPatterns: 1 }, |
| 15776 | {.Opcode: AArch64::LD1D_4Z_STRIDED_IMM, .PatternStart: 257, .NumPatterns: 1 }, |
| 15777 | {.Opcode: AArch64::LD1D_IMM, .PatternStart: 258, .NumPatterns: 1 }, |
| 15778 | {.Opcode: AArch64::LD1D_Q_IMM, .PatternStart: 259, .NumPatterns: 1 }, |
| 15779 | {.Opcode: AArch64::LD1Fourv16b_POST, .PatternStart: 260, .NumPatterns: 1 }, |
| 15780 | {.Opcode: AArch64::LD1Fourv1d_POST, .PatternStart: 261, .NumPatterns: 1 }, |
| 15781 | {.Opcode: AArch64::LD1Fourv2d_POST, .PatternStart: 262, .NumPatterns: 1 }, |
| 15782 | {.Opcode: AArch64::LD1Fourv2s_POST, .PatternStart: 263, .NumPatterns: 1 }, |
| 15783 | {.Opcode: AArch64::LD1Fourv4h_POST, .PatternStart: 264, .NumPatterns: 1 }, |
| 15784 | {.Opcode: AArch64::LD1Fourv4s_POST, .PatternStart: 265, .NumPatterns: 1 }, |
| 15785 | {.Opcode: AArch64::LD1Fourv8b_POST, .PatternStart: 266, .NumPatterns: 1 }, |
| 15786 | {.Opcode: AArch64::LD1Fourv8h_POST, .PatternStart: 267, .NumPatterns: 1 }, |
| 15787 | {.Opcode: AArch64::LD1H_2Z_IMM, .PatternStart: 268, .NumPatterns: 1 }, |
| 15788 | {.Opcode: AArch64::LD1H_2Z_STRIDED_IMM, .PatternStart: 269, .NumPatterns: 1 }, |
| 15789 | {.Opcode: AArch64::LD1H_4Z_IMM, .PatternStart: 270, .NumPatterns: 1 }, |
| 15790 | {.Opcode: AArch64::LD1H_4Z_STRIDED_IMM, .PatternStart: 271, .NumPatterns: 1 }, |
| 15791 | {.Opcode: AArch64::LD1H_D_IMM, .PatternStart: 272, .NumPatterns: 1 }, |
| 15792 | {.Opcode: AArch64::LD1H_IMM, .PatternStart: 273, .NumPatterns: 1 }, |
| 15793 | {.Opcode: AArch64::LD1H_S_IMM, .PatternStart: 274, .NumPatterns: 1 }, |
| 15794 | {.Opcode: AArch64::LD1Onev16b_POST, .PatternStart: 275, .NumPatterns: 1 }, |
| 15795 | {.Opcode: AArch64::LD1Onev1d_POST, .PatternStart: 276, .NumPatterns: 1 }, |
| 15796 | {.Opcode: AArch64::LD1Onev2d_POST, .PatternStart: 277, .NumPatterns: 1 }, |
| 15797 | {.Opcode: AArch64::LD1Onev2s_POST, .PatternStart: 278, .NumPatterns: 1 }, |
| 15798 | {.Opcode: AArch64::LD1Onev4h_POST, .PatternStart: 279, .NumPatterns: 1 }, |
| 15799 | {.Opcode: AArch64::LD1Onev4s_POST, .PatternStart: 280, .NumPatterns: 1 }, |
| 15800 | {.Opcode: AArch64::LD1Onev8b_POST, .PatternStart: 281, .NumPatterns: 1 }, |
| 15801 | {.Opcode: AArch64::LD1Onev8h_POST, .PatternStart: 282, .NumPatterns: 1 }, |
| 15802 | {.Opcode: AArch64::LD1RB_D_IMM, .PatternStart: 283, .NumPatterns: 1 }, |
| 15803 | {.Opcode: AArch64::LD1RB_H_IMM, .PatternStart: 284, .NumPatterns: 1 }, |
| 15804 | {.Opcode: AArch64::LD1RB_IMM, .PatternStart: 285, .NumPatterns: 1 }, |
| 15805 | {.Opcode: AArch64::LD1RB_S_IMM, .PatternStart: 286, .NumPatterns: 1 }, |
| 15806 | {.Opcode: AArch64::LD1RD_IMM, .PatternStart: 287, .NumPatterns: 1 }, |
| 15807 | {.Opcode: AArch64::LD1RH_D_IMM, .PatternStart: 288, .NumPatterns: 1 }, |
| 15808 | {.Opcode: AArch64::LD1RH_IMM, .PatternStart: 289, .NumPatterns: 1 }, |
| 15809 | {.Opcode: AArch64::LD1RH_S_IMM, .PatternStart: 290, .NumPatterns: 1 }, |
| 15810 | {.Opcode: AArch64::LD1RO_B_IMM, .PatternStart: 291, .NumPatterns: 1 }, |
| 15811 | {.Opcode: AArch64::LD1RO_D_IMM, .PatternStart: 292, .NumPatterns: 1 }, |
| 15812 | {.Opcode: AArch64::LD1RO_H_IMM, .PatternStart: 293, .NumPatterns: 1 }, |
| 15813 | {.Opcode: AArch64::LD1RO_W_IMM, .PatternStart: 294, .NumPatterns: 1 }, |
| 15814 | {.Opcode: AArch64::LD1RQ_B_IMM, .PatternStart: 295, .NumPatterns: 1 }, |
| 15815 | {.Opcode: AArch64::LD1RQ_D_IMM, .PatternStart: 296, .NumPatterns: 1 }, |
| 15816 | {.Opcode: AArch64::LD1RQ_H_IMM, .PatternStart: 297, .NumPatterns: 1 }, |
| 15817 | {.Opcode: AArch64::LD1RQ_W_IMM, .PatternStart: 298, .NumPatterns: 1 }, |
| 15818 | {.Opcode: AArch64::LD1RSB_D_IMM, .PatternStart: 299, .NumPatterns: 1 }, |
| 15819 | {.Opcode: AArch64::LD1RSB_H_IMM, .PatternStart: 300, .NumPatterns: 1 }, |
| 15820 | {.Opcode: AArch64::LD1RSB_S_IMM, .PatternStart: 301, .NumPatterns: 1 }, |
| 15821 | {.Opcode: AArch64::LD1RSH_D_IMM, .PatternStart: 302, .NumPatterns: 1 }, |
| 15822 | {.Opcode: AArch64::LD1RSH_S_IMM, .PatternStart: 303, .NumPatterns: 1 }, |
| 15823 | {.Opcode: AArch64::LD1RSW_IMM, .PatternStart: 304, .NumPatterns: 1 }, |
| 15824 | {.Opcode: AArch64::LD1RW_D_IMM, .PatternStart: 305, .NumPatterns: 1 }, |
| 15825 | {.Opcode: AArch64::LD1RW_IMM, .PatternStart: 306, .NumPatterns: 1 }, |
| 15826 | {.Opcode: AArch64::LD1Rv16b_POST, .PatternStart: 307, .NumPatterns: 1 }, |
| 15827 | {.Opcode: AArch64::LD1Rv1d_POST, .PatternStart: 308, .NumPatterns: 1 }, |
| 15828 | {.Opcode: AArch64::LD1Rv2d_POST, .PatternStart: 309, .NumPatterns: 1 }, |
| 15829 | {.Opcode: AArch64::LD1Rv2s_POST, .PatternStart: 310, .NumPatterns: 1 }, |
| 15830 | {.Opcode: AArch64::LD1Rv4h_POST, .PatternStart: 311, .NumPatterns: 1 }, |
| 15831 | {.Opcode: AArch64::LD1Rv4s_POST, .PatternStart: 312, .NumPatterns: 1 }, |
| 15832 | {.Opcode: AArch64::LD1Rv8b_POST, .PatternStart: 313, .NumPatterns: 1 }, |
| 15833 | {.Opcode: AArch64::LD1Rv8h_POST, .PatternStart: 314, .NumPatterns: 1 }, |
| 15834 | {.Opcode: AArch64::LD1SB_D_IMM, .PatternStart: 315, .NumPatterns: 1 }, |
| 15835 | {.Opcode: AArch64::LD1SB_H_IMM, .PatternStart: 316, .NumPatterns: 1 }, |
| 15836 | {.Opcode: AArch64::LD1SB_S_IMM, .PatternStart: 317, .NumPatterns: 1 }, |
| 15837 | {.Opcode: AArch64::LD1SH_D_IMM, .PatternStart: 318, .NumPatterns: 1 }, |
| 15838 | {.Opcode: AArch64::LD1SH_S_IMM, .PatternStart: 319, .NumPatterns: 1 }, |
| 15839 | {.Opcode: AArch64::LD1SW_D_IMM, .PatternStart: 320, .NumPatterns: 1 }, |
| 15840 | {.Opcode: AArch64::LD1Threev16b_POST, .PatternStart: 321, .NumPatterns: 1 }, |
| 15841 | {.Opcode: AArch64::LD1Threev1d_POST, .PatternStart: 322, .NumPatterns: 1 }, |
| 15842 | {.Opcode: AArch64::LD1Threev2d_POST, .PatternStart: 323, .NumPatterns: 1 }, |
| 15843 | {.Opcode: AArch64::LD1Threev2s_POST, .PatternStart: 324, .NumPatterns: 1 }, |
| 15844 | {.Opcode: AArch64::LD1Threev4h_POST, .PatternStart: 325, .NumPatterns: 1 }, |
| 15845 | {.Opcode: AArch64::LD1Threev4s_POST, .PatternStart: 326, .NumPatterns: 1 }, |
| 15846 | {.Opcode: AArch64::LD1Threev8b_POST, .PatternStart: 327, .NumPatterns: 1 }, |
| 15847 | {.Opcode: AArch64::LD1Threev8h_POST, .PatternStart: 328, .NumPatterns: 1 }, |
| 15848 | {.Opcode: AArch64::LD1Twov16b_POST, .PatternStart: 329, .NumPatterns: 1 }, |
| 15849 | {.Opcode: AArch64::LD1Twov1d_POST, .PatternStart: 330, .NumPatterns: 1 }, |
| 15850 | {.Opcode: AArch64::LD1Twov2d_POST, .PatternStart: 331, .NumPatterns: 1 }, |
| 15851 | {.Opcode: AArch64::LD1Twov2s_POST, .PatternStart: 332, .NumPatterns: 1 }, |
| 15852 | {.Opcode: AArch64::LD1Twov4h_POST, .PatternStart: 333, .NumPatterns: 1 }, |
| 15853 | {.Opcode: AArch64::LD1Twov4s_POST, .PatternStart: 334, .NumPatterns: 1 }, |
| 15854 | {.Opcode: AArch64::LD1Twov8b_POST, .PatternStart: 335, .NumPatterns: 1 }, |
| 15855 | {.Opcode: AArch64::LD1Twov8h_POST, .PatternStart: 336, .NumPatterns: 1 }, |
| 15856 | {.Opcode: AArch64::LD1W_2Z_IMM, .PatternStart: 337, .NumPatterns: 1 }, |
| 15857 | {.Opcode: AArch64::LD1W_2Z_STRIDED_IMM, .PatternStart: 338, .NumPatterns: 1 }, |
| 15858 | {.Opcode: AArch64::LD1W_4Z_IMM, .PatternStart: 339, .NumPatterns: 1 }, |
| 15859 | {.Opcode: AArch64::LD1W_4Z_STRIDED_IMM, .PatternStart: 340, .NumPatterns: 1 }, |
| 15860 | {.Opcode: AArch64::LD1W_D_IMM, .PatternStart: 341, .NumPatterns: 1 }, |
| 15861 | {.Opcode: AArch64::LD1W_IMM, .PatternStart: 342, .NumPatterns: 1 }, |
| 15862 | {.Opcode: AArch64::LD1W_Q_IMM, .PatternStart: 343, .NumPatterns: 1 }, |
| 15863 | {.Opcode: AArch64::LD1_MXIPXX_H_B, .PatternStart: 344, .NumPatterns: 1 }, |
| 15864 | {.Opcode: AArch64::LD1_MXIPXX_H_D, .PatternStart: 345, .NumPatterns: 1 }, |
| 15865 | {.Opcode: AArch64::LD1_MXIPXX_H_H, .PatternStart: 346, .NumPatterns: 1 }, |
| 15866 | {.Opcode: AArch64::LD1_MXIPXX_H_Q, .PatternStart: 347, .NumPatterns: 1 }, |
| 15867 | {.Opcode: AArch64::LD1_MXIPXX_H_S, .PatternStart: 348, .NumPatterns: 1 }, |
| 15868 | {.Opcode: AArch64::LD1_MXIPXX_V_B, .PatternStart: 349, .NumPatterns: 1 }, |
| 15869 | {.Opcode: AArch64::LD1_MXIPXX_V_D, .PatternStart: 350, .NumPatterns: 1 }, |
| 15870 | {.Opcode: AArch64::LD1_MXIPXX_V_H, .PatternStart: 351, .NumPatterns: 1 }, |
| 15871 | {.Opcode: AArch64::LD1_MXIPXX_V_Q, .PatternStart: 352, .NumPatterns: 1 }, |
| 15872 | {.Opcode: AArch64::LD1_MXIPXX_V_S, .PatternStart: 353, .NumPatterns: 1 }, |
| 15873 | {.Opcode: AArch64::LD1i16_POST, .PatternStart: 354, .NumPatterns: 1 }, |
| 15874 | {.Opcode: AArch64::LD1i32_POST, .PatternStart: 355, .NumPatterns: 1 }, |
| 15875 | {.Opcode: AArch64::LD1i64_POST, .PatternStart: 356, .NumPatterns: 1 }, |
| 15876 | {.Opcode: AArch64::LD1i8_POST, .PatternStart: 357, .NumPatterns: 1 }, |
| 15877 | {.Opcode: AArch64::LD2B_IMM, .PatternStart: 358, .NumPatterns: 1 }, |
| 15878 | {.Opcode: AArch64::LD2D_IMM, .PatternStart: 359, .NumPatterns: 1 }, |
| 15879 | {.Opcode: AArch64::LD2H_IMM, .PatternStart: 360, .NumPatterns: 1 }, |
| 15880 | {.Opcode: AArch64::LD2Q_IMM, .PatternStart: 361, .NumPatterns: 1 }, |
| 15881 | {.Opcode: AArch64::LD2Rv16b_POST, .PatternStart: 362, .NumPatterns: 1 }, |
| 15882 | {.Opcode: AArch64::LD2Rv1d_POST, .PatternStart: 363, .NumPatterns: 1 }, |
| 15883 | {.Opcode: AArch64::LD2Rv2d_POST, .PatternStart: 364, .NumPatterns: 1 }, |
| 15884 | {.Opcode: AArch64::LD2Rv2s_POST, .PatternStart: 365, .NumPatterns: 1 }, |
| 15885 | {.Opcode: AArch64::LD2Rv4h_POST, .PatternStart: 366, .NumPatterns: 1 }, |
| 15886 | {.Opcode: AArch64::LD2Rv4s_POST, .PatternStart: 367, .NumPatterns: 1 }, |
| 15887 | {.Opcode: AArch64::LD2Rv8b_POST, .PatternStart: 368, .NumPatterns: 1 }, |
| 15888 | {.Opcode: AArch64::LD2Rv8h_POST, .PatternStart: 369, .NumPatterns: 1 }, |
| 15889 | {.Opcode: AArch64::LD2Twov16b_POST, .PatternStart: 370, .NumPatterns: 1 }, |
| 15890 | {.Opcode: AArch64::LD2Twov2d_POST, .PatternStart: 371, .NumPatterns: 1 }, |
| 15891 | {.Opcode: AArch64::LD2Twov2s_POST, .PatternStart: 372, .NumPatterns: 1 }, |
| 15892 | {.Opcode: AArch64::LD2Twov4h_POST, .PatternStart: 373, .NumPatterns: 1 }, |
| 15893 | {.Opcode: AArch64::LD2Twov4s_POST, .PatternStart: 374, .NumPatterns: 1 }, |
| 15894 | {.Opcode: AArch64::LD2Twov8b_POST, .PatternStart: 375, .NumPatterns: 1 }, |
| 15895 | {.Opcode: AArch64::LD2Twov8h_POST, .PatternStart: 376, .NumPatterns: 1 }, |
| 15896 | {.Opcode: AArch64::LD2W_IMM, .PatternStart: 377, .NumPatterns: 1 }, |
| 15897 | {.Opcode: AArch64::LD2i16_POST, .PatternStart: 378, .NumPatterns: 1 }, |
| 15898 | {.Opcode: AArch64::LD2i32_POST, .PatternStart: 379, .NumPatterns: 1 }, |
| 15899 | {.Opcode: AArch64::LD2i64_POST, .PatternStart: 380, .NumPatterns: 1 }, |
| 15900 | {.Opcode: AArch64::LD2i8_POST, .PatternStart: 381, .NumPatterns: 1 }, |
| 15901 | {.Opcode: AArch64::LD3B_IMM, .PatternStart: 382, .NumPatterns: 1 }, |
| 15902 | {.Opcode: AArch64::LD3D_IMM, .PatternStart: 383, .NumPatterns: 1 }, |
| 15903 | {.Opcode: AArch64::LD3H_IMM, .PatternStart: 384, .NumPatterns: 1 }, |
| 15904 | {.Opcode: AArch64::LD3Q_IMM, .PatternStart: 385, .NumPatterns: 1 }, |
| 15905 | {.Opcode: AArch64::LD3Rv16b_POST, .PatternStart: 386, .NumPatterns: 1 }, |
| 15906 | {.Opcode: AArch64::LD3Rv1d_POST, .PatternStart: 387, .NumPatterns: 1 }, |
| 15907 | {.Opcode: AArch64::LD3Rv2d_POST, .PatternStart: 388, .NumPatterns: 1 }, |
| 15908 | {.Opcode: AArch64::LD3Rv2s_POST, .PatternStart: 389, .NumPatterns: 1 }, |
| 15909 | {.Opcode: AArch64::LD3Rv4h_POST, .PatternStart: 390, .NumPatterns: 1 }, |
| 15910 | {.Opcode: AArch64::LD3Rv4s_POST, .PatternStart: 391, .NumPatterns: 1 }, |
| 15911 | {.Opcode: AArch64::LD3Rv8b_POST, .PatternStart: 392, .NumPatterns: 1 }, |
| 15912 | {.Opcode: AArch64::LD3Rv8h_POST, .PatternStart: 393, .NumPatterns: 1 }, |
| 15913 | {.Opcode: AArch64::LD3Threev16b_POST, .PatternStart: 394, .NumPatterns: 1 }, |
| 15914 | {.Opcode: AArch64::LD3Threev2d_POST, .PatternStart: 395, .NumPatterns: 1 }, |
| 15915 | {.Opcode: AArch64::LD3Threev2s_POST, .PatternStart: 396, .NumPatterns: 1 }, |
| 15916 | {.Opcode: AArch64::LD3Threev4h_POST, .PatternStart: 397, .NumPatterns: 1 }, |
| 15917 | {.Opcode: AArch64::LD3Threev4s_POST, .PatternStart: 398, .NumPatterns: 1 }, |
| 15918 | {.Opcode: AArch64::LD3Threev8b_POST, .PatternStart: 399, .NumPatterns: 1 }, |
| 15919 | {.Opcode: AArch64::LD3Threev8h_POST, .PatternStart: 400, .NumPatterns: 1 }, |
| 15920 | {.Opcode: AArch64::LD3W_IMM, .PatternStart: 401, .NumPatterns: 1 }, |
| 15921 | {.Opcode: AArch64::LD3i16_POST, .PatternStart: 402, .NumPatterns: 1 }, |
| 15922 | {.Opcode: AArch64::LD3i32_POST, .PatternStart: 403, .NumPatterns: 1 }, |
| 15923 | {.Opcode: AArch64::LD3i64_POST, .PatternStart: 404, .NumPatterns: 1 }, |
| 15924 | {.Opcode: AArch64::LD3i8_POST, .PatternStart: 405, .NumPatterns: 1 }, |
| 15925 | {.Opcode: AArch64::LD4B_IMM, .PatternStart: 406, .NumPatterns: 1 }, |
| 15926 | {.Opcode: AArch64::LD4D_IMM, .PatternStart: 407, .NumPatterns: 1 }, |
| 15927 | {.Opcode: AArch64::LD4Fourv16b_POST, .PatternStart: 408, .NumPatterns: 1 }, |
| 15928 | {.Opcode: AArch64::LD4Fourv2d_POST, .PatternStart: 409, .NumPatterns: 1 }, |
| 15929 | {.Opcode: AArch64::LD4Fourv2s_POST, .PatternStart: 410, .NumPatterns: 1 }, |
| 15930 | {.Opcode: AArch64::LD4Fourv4h_POST, .PatternStart: 411, .NumPatterns: 1 }, |
| 15931 | {.Opcode: AArch64::LD4Fourv4s_POST, .PatternStart: 412, .NumPatterns: 1 }, |
| 15932 | {.Opcode: AArch64::LD4Fourv8b_POST, .PatternStart: 413, .NumPatterns: 1 }, |
| 15933 | {.Opcode: AArch64::LD4Fourv8h_POST, .PatternStart: 414, .NumPatterns: 1 }, |
| 15934 | {.Opcode: AArch64::LD4H_IMM, .PatternStart: 415, .NumPatterns: 1 }, |
| 15935 | {.Opcode: AArch64::LD4Q_IMM, .PatternStart: 416, .NumPatterns: 1 }, |
| 15936 | {.Opcode: AArch64::LD4Rv16b_POST, .PatternStart: 417, .NumPatterns: 1 }, |
| 15937 | {.Opcode: AArch64::LD4Rv1d_POST, .PatternStart: 418, .NumPatterns: 1 }, |
| 15938 | {.Opcode: AArch64::LD4Rv2d_POST, .PatternStart: 419, .NumPatterns: 1 }, |
| 15939 | {.Opcode: AArch64::LD4Rv2s_POST, .PatternStart: 420, .NumPatterns: 1 }, |
| 15940 | {.Opcode: AArch64::LD4Rv4h_POST, .PatternStart: 421, .NumPatterns: 1 }, |
| 15941 | {.Opcode: AArch64::LD4Rv4s_POST, .PatternStart: 422, .NumPatterns: 1 }, |
| 15942 | {.Opcode: AArch64::LD4Rv8b_POST, .PatternStart: 423, .NumPatterns: 1 }, |
| 15943 | {.Opcode: AArch64::LD4Rv8h_POST, .PatternStart: 424, .NumPatterns: 1 }, |
| 15944 | {.Opcode: AArch64::LD4W_IMM, .PatternStart: 425, .NumPatterns: 1 }, |
| 15945 | {.Opcode: AArch64::LD4i16_POST, .PatternStart: 426, .NumPatterns: 1 }, |
| 15946 | {.Opcode: AArch64::LD4i32_POST, .PatternStart: 427, .NumPatterns: 1 }, |
| 15947 | {.Opcode: AArch64::LD4i64_POST, .PatternStart: 428, .NumPatterns: 1 }, |
| 15948 | {.Opcode: AArch64::LD4i8_POST, .PatternStart: 429, .NumPatterns: 1 }, |
| 15949 | {.Opcode: AArch64::LDADDB, .PatternStart: 430, .NumPatterns: 1 }, |
| 15950 | {.Opcode: AArch64::LDADDH, .PatternStart: 431, .NumPatterns: 1 }, |
| 15951 | {.Opcode: AArch64::LDADDLB, .PatternStart: 432, .NumPatterns: 1 }, |
| 15952 | {.Opcode: AArch64::LDADDLH, .PatternStart: 433, .NumPatterns: 1 }, |
| 15953 | {.Opcode: AArch64::LDADDLW, .PatternStart: 434, .NumPatterns: 1 }, |
| 15954 | {.Opcode: AArch64::LDADDLX, .PatternStart: 435, .NumPatterns: 1 }, |
| 15955 | {.Opcode: AArch64::LDADDW, .PatternStart: 436, .NumPatterns: 1 }, |
| 15956 | {.Opcode: AArch64::LDADDX, .PatternStart: 437, .NumPatterns: 1 }, |
| 15957 | {.Opcode: AArch64::LDAPPi, .PatternStart: 438, .NumPatterns: 1 }, |
| 15958 | {.Opcode: AArch64::LDAPURBi, .PatternStart: 439, .NumPatterns: 1 }, |
| 15959 | {.Opcode: AArch64::LDAPURHi, .PatternStart: 440, .NumPatterns: 1 }, |
| 15960 | {.Opcode: AArch64::LDAPURSBWi, .PatternStart: 441, .NumPatterns: 1 }, |
| 15961 | {.Opcode: AArch64::LDAPURSBXi, .PatternStart: 442, .NumPatterns: 1 }, |
| 15962 | {.Opcode: AArch64::LDAPURSHWi, .PatternStart: 443, .NumPatterns: 1 }, |
| 15963 | {.Opcode: AArch64::LDAPURSHXi, .PatternStart: 444, .NumPatterns: 1 }, |
| 15964 | {.Opcode: AArch64::LDAPURSWi, .PatternStart: 445, .NumPatterns: 1 }, |
| 15965 | {.Opcode: AArch64::LDAPURXi, .PatternStart: 446, .NumPatterns: 1 }, |
| 15966 | {.Opcode: AArch64::LDAPURbi, .PatternStart: 447, .NumPatterns: 1 }, |
| 15967 | {.Opcode: AArch64::LDAPURdi, .PatternStart: 448, .NumPatterns: 1 }, |
| 15968 | {.Opcode: AArch64::LDAPURhi, .PatternStart: 449, .NumPatterns: 1 }, |
| 15969 | {.Opcode: AArch64::LDAPURi, .PatternStart: 450, .NumPatterns: 1 }, |
| 15970 | {.Opcode: AArch64::LDAPURqi, .PatternStart: 451, .NumPatterns: 1 }, |
| 15971 | {.Opcode: AArch64::LDAPURsi, .PatternStart: 452, .NumPatterns: 1 }, |
| 15972 | {.Opcode: AArch64::LDAPi, .PatternStart: 453, .NumPatterns: 1 }, |
| 15973 | {.Opcode: AArch64::LDCLRB, .PatternStart: 454, .NumPatterns: 1 }, |
| 15974 | {.Opcode: AArch64::LDCLRH, .PatternStart: 455, .NumPatterns: 1 }, |
| 15975 | {.Opcode: AArch64::LDCLRLB, .PatternStart: 456, .NumPatterns: 1 }, |
| 15976 | {.Opcode: AArch64::LDCLRLH, .PatternStart: 457, .NumPatterns: 1 }, |
| 15977 | {.Opcode: AArch64::LDCLRLW, .PatternStart: 458, .NumPatterns: 1 }, |
| 15978 | {.Opcode: AArch64::LDCLRLX, .PatternStart: 459, .NumPatterns: 1 }, |
| 15979 | {.Opcode: AArch64::LDCLRW, .PatternStart: 460, .NumPatterns: 1 }, |
| 15980 | {.Opcode: AArch64::LDCLRX, .PatternStart: 461, .NumPatterns: 1 }, |
| 15981 | {.Opcode: AArch64::LDEORB, .PatternStart: 462, .NumPatterns: 1 }, |
| 15982 | {.Opcode: AArch64::LDEORH, .PatternStart: 463, .NumPatterns: 1 }, |
| 15983 | {.Opcode: AArch64::LDEORLB, .PatternStart: 464, .NumPatterns: 1 }, |
| 15984 | {.Opcode: AArch64::LDEORLH, .PatternStart: 465, .NumPatterns: 1 }, |
| 15985 | {.Opcode: AArch64::LDEORLW, .PatternStart: 466, .NumPatterns: 1 }, |
| 15986 | {.Opcode: AArch64::LDEORLX, .PatternStart: 467, .NumPatterns: 1 }, |
| 15987 | {.Opcode: AArch64::LDEORW, .PatternStart: 468, .NumPatterns: 1 }, |
| 15988 | {.Opcode: AArch64::LDEORX, .PatternStart: 469, .NumPatterns: 1 }, |
| 15989 | {.Opcode: AArch64::LDFF1B, .PatternStart: 470, .NumPatterns: 1 }, |
| 15990 | {.Opcode: AArch64::LDFF1B_D, .PatternStart: 471, .NumPatterns: 1 }, |
| 15991 | {.Opcode: AArch64::LDFF1B_H, .PatternStart: 472, .NumPatterns: 1 }, |
| 15992 | {.Opcode: AArch64::LDFF1B_S, .PatternStart: 473, .NumPatterns: 1 }, |
| 15993 | {.Opcode: AArch64::LDFF1D, .PatternStart: 474, .NumPatterns: 1 }, |
| 15994 | {.Opcode: AArch64::LDFF1H, .PatternStart: 475, .NumPatterns: 1 }, |
| 15995 | {.Opcode: AArch64::LDFF1H_D, .PatternStart: 476, .NumPatterns: 1 }, |
| 15996 | {.Opcode: AArch64::LDFF1H_S, .PatternStart: 477, .NumPatterns: 1 }, |
| 15997 | {.Opcode: AArch64::LDFF1SB_D, .PatternStart: 478, .NumPatterns: 1 }, |
| 15998 | {.Opcode: AArch64::LDFF1SB_H, .PatternStart: 479, .NumPatterns: 1 }, |
| 15999 | {.Opcode: AArch64::LDFF1SB_S, .PatternStart: 480, .NumPatterns: 1 }, |
| 16000 | {.Opcode: AArch64::LDFF1SH_D, .PatternStart: 481, .NumPatterns: 1 }, |
| 16001 | {.Opcode: AArch64::LDFF1SH_S, .PatternStart: 482, .NumPatterns: 1 }, |
| 16002 | {.Opcode: AArch64::LDFF1SW_D, .PatternStart: 483, .NumPatterns: 1 }, |
| 16003 | {.Opcode: AArch64::LDFF1W, .PatternStart: 484, .NumPatterns: 1 }, |
| 16004 | {.Opcode: AArch64::LDFF1W_D, .PatternStart: 485, .NumPatterns: 1 }, |
| 16005 | {.Opcode: AArch64::LDG, .PatternStart: 486, .NumPatterns: 1 }, |
| 16006 | {.Opcode: AArch64::LDNF1B_D_IMM, .PatternStart: 487, .NumPatterns: 1 }, |
| 16007 | {.Opcode: AArch64::LDNF1B_H_IMM, .PatternStart: 488, .NumPatterns: 1 }, |
| 16008 | {.Opcode: AArch64::LDNF1B_IMM, .PatternStart: 489, .NumPatterns: 1 }, |
| 16009 | {.Opcode: AArch64::LDNF1B_S_IMM, .PatternStart: 490, .NumPatterns: 1 }, |
| 16010 | {.Opcode: AArch64::LDNF1D_IMM, .PatternStart: 491, .NumPatterns: 1 }, |
| 16011 | {.Opcode: AArch64::LDNF1H_D_IMM, .PatternStart: 492, .NumPatterns: 1 }, |
| 16012 | {.Opcode: AArch64::LDNF1H_IMM, .PatternStart: 493, .NumPatterns: 1 }, |
| 16013 | {.Opcode: AArch64::LDNF1H_S_IMM, .PatternStart: 494, .NumPatterns: 1 }, |
| 16014 | {.Opcode: AArch64::LDNF1SB_D_IMM, .PatternStart: 495, .NumPatterns: 1 }, |
| 16015 | {.Opcode: AArch64::LDNF1SB_H_IMM, .PatternStart: 496, .NumPatterns: 1 }, |
| 16016 | {.Opcode: AArch64::LDNF1SB_S_IMM, .PatternStart: 497, .NumPatterns: 1 }, |
| 16017 | {.Opcode: AArch64::LDNF1SH_D_IMM, .PatternStart: 498, .NumPatterns: 1 }, |
| 16018 | {.Opcode: AArch64::LDNF1SH_S_IMM, .PatternStart: 499, .NumPatterns: 1 }, |
| 16019 | {.Opcode: AArch64::LDNF1SW_D_IMM, .PatternStart: 500, .NumPatterns: 1 }, |
| 16020 | {.Opcode: AArch64::LDNF1W_D_IMM, .PatternStart: 501, .NumPatterns: 1 }, |
| 16021 | {.Opcode: AArch64::LDNF1W_IMM, .PatternStart: 502, .NumPatterns: 1 }, |
| 16022 | {.Opcode: AArch64::LDNPDi, .PatternStart: 503, .NumPatterns: 1 }, |
| 16023 | {.Opcode: AArch64::LDNPQi, .PatternStart: 504, .NumPatterns: 1 }, |
| 16024 | {.Opcode: AArch64::LDNPSi, .PatternStart: 505, .NumPatterns: 1 }, |
| 16025 | {.Opcode: AArch64::LDNPWi, .PatternStart: 506, .NumPatterns: 1 }, |
| 16026 | {.Opcode: AArch64::LDNPXi, .PatternStart: 507, .NumPatterns: 1 }, |
| 16027 | {.Opcode: AArch64::LDNT1B_2Z_IMM, .PatternStart: 508, .NumPatterns: 1 }, |
| 16028 | {.Opcode: AArch64::LDNT1B_2Z_STRIDED_IMM, .PatternStart: 509, .NumPatterns: 1 }, |
| 16029 | {.Opcode: AArch64::LDNT1B_4Z_IMM, .PatternStart: 510, .NumPatterns: 1 }, |
| 16030 | {.Opcode: AArch64::LDNT1B_4Z_STRIDED_IMM, .PatternStart: 511, .NumPatterns: 1 }, |
| 16031 | {.Opcode: AArch64::LDNT1B_ZRI, .PatternStart: 512, .NumPatterns: 1 }, |
| 16032 | {.Opcode: AArch64::LDNT1B_ZZR_D, .PatternStart: 513, .NumPatterns: 1 }, |
| 16033 | {.Opcode: AArch64::LDNT1B_ZZR_S, .PatternStart: 514, .NumPatterns: 1 }, |
| 16034 | {.Opcode: AArch64::LDNT1D_2Z_IMM, .PatternStart: 515, .NumPatterns: 1 }, |
| 16035 | {.Opcode: AArch64::LDNT1D_2Z_STRIDED_IMM, .PatternStart: 516, .NumPatterns: 1 }, |
| 16036 | {.Opcode: AArch64::LDNT1D_4Z_IMM, .PatternStart: 517, .NumPatterns: 1 }, |
| 16037 | {.Opcode: AArch64::LDNT1D_4Z_STRIDED_IMM, .PatternStart: 518, .NumPatterns: 1 }, |
| 16038 | {.Opcode: AArch64::LDNT1D_ZRI, .PatternStart: 519, .NumPatterns: 1 }, |
| 16039 | {.Opcode: AArch64::LDNT1D_ZZR_D, .PatternStart: 520, .NumPatterns: 1 }, |
| 16040 | {.Opcode: AArch64::LDNT1H_2Z_IMM, .PatternStart: 521, .NumPatterns: 1 }, |
| 16041 | {.Opcode: AArch64::LDNT1H_2Z_STRIDED_IMM, .PatternStart: 522, .NumPatterns: 1 }, |
| 16042 | {.Opcode: AArch64::LDNT1H_4Z_IMM, .PatternStart: 523, .NumPatterns: 1 }, |
| 16043 | {.Opcode: AArch64::LDNT1H_4Z_STRIDED_IMM, .PatternStart: 524, .NumPatterns: 1 }, |
| 16044 | {.Opcode: AArch64::LDNT1H_ZRI, .PatternStart: 525, .NumPatterns: 1 }, |
| 16045 | {.Opcode: AArch64::LDNT1H_ZZR_D, .PatternStart: 526, .NumPatterns: 1 }, |
| 16046 | {.Opcode: AArch64::LDNT1H_ZZR_S, .PatternStart: 527, .NumPatterns: 1 }, |
| 16047 | {.Opcode: AArch64::LDNT1SB_ZZR_D, .PatternStart: 528, .NumPatterns: 1 }, |
| 16048 | {.Opcode: AArch64::LDNT1SB_ZZR_S, .PatternStart: 529, .NumPatterns: 1 }, |
| 16049 | {.Opcode: AArch64::LDNT1SH_ZZR_D, .PatternStart: 530, .NumPatterns: 1 }, |
| 16050 | {.Opcode: AArch64::LDNT1SH_ZZR_S, .PatternStart: 531, .NumPatterns: 1 }, |
| 16051 | {.Opcode: AArch64::LDNT1SW_ZZR_D, .PatternStart: 532, .NumPatterns: 1 }, |
| 16052 | {.Opcode: AArch64::LDNT1W_2Z_IMM, .PatternStart: 533, .NumPatterns: 1 }, |
| 16053 | {.Opcode: AArch64::LDNT1W_2Z_STRIDED_IMM, .PatternStart: 534, .NumPatterns: 1 }, |
| 16054 | {.Opcode: AArch64::LDNT1W_4Z_IMM, .PatternStart: 535, .NumPatterns: 1 }, |
| 16055 | {.Opcode: AArch64::LDNT1W_4Z_STRIDED_IMM, .PatternStart: 536, .NumPatterns: 1 }, |
| 16056 | {.Opcode: AArch64::LDNT1W_ZRI, .PatternStart: 537, .NumPatterns: 1 }, |
| 16057 | {.Opcode: AArch64::LDNT1W_ZZR_D, .PatternStart: 538, .NumPatterns: 1 }, |
| 16058 | {.Opcode: AArch64::LDNT1W_ZZR_S, .PatternStart: 539, .NumPatterns: 1 }, |
| 16059 | {.Opcode: AArch64::LDPDi, .PatternStart: 540, .NumPatterns: 1 }, |
| 16060 | {.Opcode: AArch64::LDPQi, .PatternStart: 541, .NumPatterns: 1 }, |
| 16061 | {.Opcode: AArch64::LDPSWi, .PatternStart: 542, .NumPatterns: 1 }, |
| 16062 | {.Opcode: AArch64::LDPSi, .PatternStart: 543, .NumPatterns: 1 }, |
| 16063 | {.Opcode: AArch64::LDPWi, .PatternStart: 544, .NumPatterns: 1 }, |
| 16064 | {.Opcode: AArch64::LDPXi, .PatternStart: 545, .NumPatterns: 1 }, |
| 16065 | {.Opcode: AArch64::LDRAAindexed, .PatternStart: 546, .NumPatterns: 1 }, |
| 16066 | {.Opcode: AArch64::LDRABindexed, .PatternStart: 547, .NumPatterns: 1 }, |
| 16067 | {.Opcode: AArch64::LDRBBroX, .PatternStart: 548, .NumPatterns: 1 }, |
| 16068 | {.Opcode: AArch64::LDRBBui, .PatternStart: 549, .NumPatterns: 1 }, |
| 16069 | {.Opcode: AArch64::LDRBroX, .PatternStart: 550, .NumPatterns: 1 }, |
| 16070 | {.Opcode: AArch64::LDRBui, .PatternStart: 551, .NumPatterns: 1 }, |
| 16071 | {.Opcode: AArch64::LDRDroX, .PatternStart: 552, .NumPatterns: 1 }, |
| 16072 | {.Opcode: AArch64::LDRDui, .PatternStart: 553, .NumPatterns: 1 }, |
| 16073 | {.Opcode: AArch64::LDRHHroX, .PatternStart: 554, .NumPatterns: 1 }, |
| 16074 | {.Opcode: AArch64::LDRHHui, .PatternStart: 555, .NumPatterns: 1 }, |
| 16075 | {.Opcode: AArch64::LDRHroX, .PatternStart: 556, .NumPatterns: 1 }, |
| 16076 | {.Opcode: AArch64::LDRHui, .PatternStart: 557, .NumPatterns: 1 }, |
| 16077 | {.Opcode: AArch64::LDRQroX, .PatternStart: 558, .NumPatterns: 1 }, |
| 16078 | {.Opcode: AArch64::LDRQui, .PatternStart: 559, .NumPatterns: 1 }, |
| 16079 | {.Opcode: AArch64::LDRSBWroX, .PatternStart: 560, .NumPatterns: 1 }, |
| 16080 | {.Opcode: AArch64::LDRSBWui, .PatternStart: 561, .NumPatterns: 1 }, |
| 16081 | {.Opcode: AArch64::LDRSBXroX, .PatternStart: 562, .NumPatterns: 1 }, |
| 16082 | {.Opcode: AArch64::LDRSBXui, .PatternStart: 563, .NumPatterns: 1 }, |
| 16083 | {.Opcode: AArch64::LDRSHWroX, .PatternStart: 564, .NumPatterns: 1 }, |
| 16084 | {.Opcode: AArch64::LDRSHWui, .PatternStart: 565, .NumPatterns: 1 }, |
| 16085 | {.Opcode: AArch64::LDRSHXroX, .PatternStart: 566, .NumPatterns: 1 }, |
| 16086 | {.Opcode: AArch64::LDRSHXui, .PatternStart: 567, .NumPatterns: 1 }, |
| 16087 | {.Opcode: AArch64::LDRSWroX, .PatternStart: 568, .NumPatterns: 1 }, |
| 16088 | {.Opcode: AArch64::LDRSWui, .PatternStart: 569, .NumPatterns: 1 }, |
| 16089 | {.Opcode: AArch64::LDRSroX, .PatternStart: 570, .NumPatterns: 1 }, |
| 16090 | {.Opcode: AArch64::LDRSui, .PatternStart: 571, .NumPatterns: 1 }, |
| 16091 | {.Opcode: AArch64::LDRWroX, .PatternStart: 572, .NumPatterns: 1 }, |
| 16092 | {.Opcode: AArch64::LDRWui, .PatternStart: 573, .NumPatterns: 1 }, |
| 16093 | {.Opcode: AArch64::LDRXroX, .PatternStart: 574, .NumPatterns: 1 }, |
| 16094 | {.Opcode: AArch64::LDRXui, .PatternStart: 575, .NumPatterns: 1 }, |
| 16095 | {.Opcode: AArch64::LDR_PXI, .PatternStart: 576, .NumPatterns: 1 }, |
| 16096 | {.Opcode: AArch64::LDR_ZA, .PatternStart: 577, .NumPatterns: 1 }, |
| 16097 | {.Opcode: AArch64::LDR_ZXI, .PatternStart: 578, .NumPatterns: 1 }, |
| 16098 | {.Opcode: AArch64::LDSETB, .PatternStart: 579, .NumPatterns: 1 }, |
| 16099 | {.Opcode: AArch64::LDSETH, .PatternStart: 580, .NumPatterns: 1 }, |
| 16100 | {.Opcode: AArch64::LDSETLB, .PatternStart: 581, .NumPatterns: 1 }, |
| 16101 | {.Opcode: AArch64::LDSETLH, .PatternStart: 582, .NumPatterns: 1 }, |
| 16102 | {.Opcode: AArch64::LDSETLW, .PatternStart: 583, .NumPatterns: 1 }, |
| 16103 | {.Opcode: AArch64::LDSETLX, .PatternStart: 584, .NumPatterns: 1 }, |
| 16104 | {.Opcode: AArch64::LDSETW, .PatternStart: 585, .NumPatterns: 1 }, |
| 16105 | {.Opcode: AArch64::LDSETX, .PatternStart: 586, .NumPatterns: 1 }, |
| 16106 | {.Opcode: AArch64::LDSMAXB, .PatternStart: 587, .NumPatterns: 1 }, |
| 16107 | {.Opcode: AArch64::LDSMAXH, .PatternStart: 588, .NumPatterns: 1 }, |
| 16108 | {.Opcode: AArch64::LDSMAXLB, .PatternStart: 589, .NumPatterns: 1 }, |
| 16109 | {.Opcode: AArch64::LDSMAXLH, .PatternStart: 590, .NumPatterns: 1 }, |
| 16110 | {.Opcode: AArch64::LDSMAXLW, .PatternStart: 591, .NumPatterns: 1 }, |
| 16111 | {.Opcode: AArch64::LDSMAXLX, .PatternStart: 592, .NumPatterns: 1 }, |
| 16112 | {.Opcode: AArch64::LDSMAXW, .PatternStart: 593, .NumPatterns: 1 }, |
| 16113 | {.Opcode: AArch64::LDSMAXX, .PatternStart: 594, .NumPatterns: 1 }, |
| 16114 | {.Opcode: AArch64::LDSMINB, .PatternStart: 595, .NumPatterns: 1 }, |
| 16115 | {.Opcode: AArch64::LDSMINH, .PatternStart: 596, .NumPatterns: 1 }, |
| 16116 | {.Opcode: AArch64::LDSMINLB, .PatternStart: 597, .NumPatterns: 1 }, |
| 16117 | {.Opcode: AArch64::LDSMINLH, .PatternStart: 598, .NumPatterns: 1 }, |
| 16118 | {.Opcode: AArch64::LDSMINLW, .PatternStart: 599, .NumPatterns: 1 }, |
| 16119 | {.Opcode: AArch64::LDSMINLX, .PatternStart: 600, .NumPatterns: 1 }, |
| 16120 | {.Opcode: AArch64::LDSMINW, .PatternStart: 601, .NumPatterns: 1 }, |
| 16121 | {.Opcode: AArch64::LDSMINX, .PatternStart: 602, .NumPatterns: 1 }, |
| 16122 | {.Opcode: AArch64::LDTADDLW, .PatternStart: 603, .NumPatterns: 1 }, |
| 16123 | {.Opcode: AArch64::LDTADDLX, .PatternStart: 604, .NumPatterns: 1 }, |
| 16124 | {.Opcode: AArch64::LDTADDW, .PatternStart: 605, .NumPatterns: 1 }, |
| 16125 | {.Opcode: AArch64::LDTADDX, .PatternStart: 606, .NumPatterns: 1 }, |
| 16126 | {.Opcode: AArch64::LDTCLRLW, .PatternStart: 607, .NumPatterns: 1 }, |
| 16127 | {.Opcode: AArch64::LDTCLRLX, .PatternStart: 608, .NumPatterns: 1 }, |
| 16128 | {.Opcode: AArch64::LDTCLRW, .PatternStart: 609, .NumPatterns: 1 }, |
| 16129 | {.Opcode: AArch64::LDTCLRX, .PatternStart: 610, .NumPatterns: 1 }, |
| 16130 | {.Opcode: AArch64::LDTNPQi, .PatternStart: 611, .NumPatterns: 1 }, |
| 16131 | {.Opcode: AArch64::LDTNPXi, .PatternStart: 612, .NumPatterns: 1 }, |
| 16132 | {.Opcode: AArch64::LDTPQi, .PatternStart: 613, .NumPatterns: 1 }, |
| 16133 | {.Opcode: AArch64::LDTPi, .PatternStart: 614, .NumPatterns: 1 }, |
| 16134 | {.Opcode: AArch64::LDTRBi, .PatternStart: 615, .NumPatterns: 1 }, |
| 16135 | {.Opcode: AArch64::LDTRHi, .PatternStart: 616, .NumPatterns: 1 }, |
| 16136 | {.Opcode: AArch64::LDTRSBWi, .PatternStart: 617, .NumPatterns: 1 }, |
| 16137 | {.Opcode: AArch64::LDTRSBXi, .PatternStart: 618, .NumPatterns: 1 }, |
| 16138 | {.Opcode: AArch64::LDTRSHWi, .PatternStart: 619, .NumPatterns: 1 }, |
| 16139 | {.Opcode: AArch64::LDTRSHXi, .PatternStart: 620, .NumPatterns: 1 }, |
| 16140 | {.Opcode: AArch64::LDTRSWi, .PatternStart: 621, .NumPatterns: 1 }, |
| 16141 | {.Opcode: AArch64::LDTRWi, .PatternStart: 622, .NumPatterns: 1 }, |
| 16142 | {.Opcode: AArch64::LDTRXi, .PatternStart: 623, .NumPatterns: 1 }, |
| 16143 | {.Opcode: AArch64::LDTSETLW, .PatternStart: 624, .NumPatterns: 1 }, |
| 16144 | {.Opcode: AArch64::LDTSETLX, .PatternStart: 625, .NumPatterns: 1 }, |
| 16145 | {.Opcode: AArch64::LDTSETW, .PatternStart: 626, .NumPatterns: 1 }, |
| 16146 | {.Opcode: AArch64::LDTSETX, .PatternStart: 627, .NumPatterns: 1 }, |
| 16147 | {.Opcode: AArch64::LDUMAXB, .PatternStart: 628, .NumPatterns: 1 }, |
| 16148 | {.Opcode: AArch64::LDUMAXH, .PatternStart: 629, .NumPatterns: 1 }, |
| 16149 | {.Opcode: AArch64::LDUMAXLB, .PatternStart: 630, .NumPatterns: 1 }, |
| 16150 | {.Opcode: AArch64::LDUMAXLH, .PatternStart: 631, .NumPatterns: 1 }, |
| 16151 | {.Opcode: AArch64::LDUMAXLW, .PatternStart: 632, .NumPatterns: 1 }, |
| 16152 | {.Opcode: AArch64::LDUMAXLX, .PatternStart: 633, .NumPatterns: 1 }, |
| 16153 | {.Opcode: AArch64::LDUMAXW, .PatternStart: 634, .NumPatterns: 1 }, |
| 16154 | {.Opcode: AArch64::LDUMAXX, .PatternStart: 635, .NumPatterns: 1 }, |
| 16155 | {.Opcode: AArch64::LDUMINB, .PatternStart: 636, .NumPatterns: 1 }, |
| 16156 | {.Opcode: AArch64::LDUMINH, .PatternStart: 637, .NumPatterns: 1 }, |
| 16157 | {.Opcode: AArch64::LDUMINLB, .PatternStart: 638, .NumPatterns: 1 }, |
| 16158 | {.Opcode: AArch64::LDUMINLH, .PatternStart: 639, .NumPatterns: 1 }, |
| 16159 | {.Opcode: AArch64::LDUMINLW, .PatternStart: 640, .NumPatterns: 1 }, |
| 16160 | {.Opcode: AArch64::LDUMINLX, .PatternStart: 641, .NumPatterns: 1 }, |
| 16161 | {.Opcode: AArch64::LDUMINW, .PatternStart: 642, .NumPatterns: 1 }, |
| 16162 | {.Opcode: AArch64::LDUMINX, .PatternStart: 643, .NumPatterns: 1 }, |
| 16163 | {.Opcode: AArch64::LDURBBi, .PatternStart: 644, .NumPatterns: 1 }, |
| 16164 | {.Opcode: AArch64::LDURBi, .PatternStart: 645, .NumPatterns: 1 }, |
| 16165 | {.Opcode: AArch64::LDURDi, .PatternStart: 646, .NumPatterns: 1 }, |
| 16166 | {.Opcode: AArch64::LDURHHi, .PatternStart: 647, .NumPatterns: 1 }, |
| 16167 | {.Opcode: AArch64::LDURHi, .PatternStart: 648, .NumPatterns: 1 }, |
| 16168 | {.Opcode: AArch64::LDURQi, .PatternStart: 649, .NumPatterns: 1 }, |
| 16169 | {.Opcode: AArch64::LDURSBWi, .PatternStart: 650, .NumPatterns: 1 }, |
| 16170 | {.Opcode: AArch64::LDURSBXi, .PatternStart: 651, .NumPatterns: 1 }, |
| 16171 | {.Opcode: AArch64::LDURSHWi, .PatternStart: 652, .NumPatterns: 1 }, |
| 16172 | {.Opcode: AArch64::LDURSHXi, .PatternStart: 653, .NumPatterns: 1 }, |
| 16173 | {.Opcode: AArch64::LDURSWi, .PatternStart: 654, .NumPatterns: 1 }, |
| 16174 | {.Opcode: AArch64::LDURSi, .PatternStart: 655, .NumPatterns: 1 }, |
| 16175 | {.Opcode: AArch64::LDURWi, .PatternStart: 656, .NumPatterns: 1 }, |
| 16176 | {.Opcode: AArch64::LDURXi, .PatternStart: 657, .NumPatterns: 1 }, |
| 16177 | {.Opcode: AArch64::MADDWrrr, .PatternStart: 658, .NumPatterns: 1 }, |
| 16178 | {.Opcode: AArch64::MADDXrrr, .PatternStart: 659, .NumPatterns: 1 }, |
| 16179 | {.Opcode: AArch64::MOVA_2ZMXI_H_B, .PatternStart: 660, .NumPatterns: 1 }, |
| 16180 | {.Opcode: AArch64::MOVA_2ZMXI_H_D, .PatternStart: 661, .NumPatterns: 1 }, |
| 16181 | {.Opcode: AArch64::MOVA_2ZMXI_H_H, .PatternStart: 662, .NumPatterns: 1 }, |
| 16182 | {.Opcode: AArch64::MOVA_2ZMXI_H_S, .PatternStart: 663, .NumPatterns: 1 }, |
| 16183 | {.Opcode: AArch64::MOVA_2ZMXI_V_B, .PatternStart: 664, .NumPatterns: 1 }, |
| 16184 | {.Opcode: AArch64::MOVA_2ZMXI_V_D, .PatternStart: 665, .NumPatterns: 1 }, |
| 16185 | {.Opcode: AArch64::MOVA_2ZMXI_V_H, .PatternStart: 666, .NumPatterns: 1 }, |
| 16186 | {.Opcode: AArch64::MOVA_2ZMXI_V_S, .PatternStart: 667, .NumPatterns: 1 }, |
| 16187 | {.Opcode: AArch64::MOVA_4ZMXI_H_B, .PatternStart: 668, .NumPatterns: 1 }, |
| 16188 | {.Opcode: AArch64::MOVA_4ZMXI_H_D, .PatternStart: 669, .NumPatterns: 1 }, |
| 16189 | {.Opcode: AArch64::MOVA_4ZMXI_H_H, .PatternStart: 670, .NumPatterns: 1 }, |
| 16190 | {.Opcode: AArch64::MOVA_4ZMXI_H_S, .PatternStart: 671, .NumPatterns: 1 }, |
| 16191 | {.Opcode: AArch64::MOVA_4ZMXI_V_B, .PatternStart: 672, .NumPatterns: 1 }, |
| 16192 | {.Opcode: AArch64::MOVA_4ZMXI_V_D, .PatternStart: 673, .NumPatterns: 1 }, |
| 16193 | {.Opcode: AArch64::MOVA_4ZMXI_V_H, .PatternStart: 674, .NumPatterns: 1 }, |
| 16194 | {.Opcode: AArch64::MOVA_4ZMXI_V_S, .PatternStart: 675, .NumPatterns: 1 }, |
| 16195 | {.Opcode: AArch64::MOVA_MXI2Z_H_B, .PatternStart: 676, .NumPatterns: 1 }, |
| 16196 | {.Opcode: AArch64::MOVA_MXI2Z_H_D, .PatternStart: 677, .NumPatterns: 1 }, |
| 16197 | {.Opcode: AArch64::MOVA_MXI2Z_H_H, .PatternStart: 678, .NumPatterns: 1 }, |
| 16198 | {.Opcode: AArch64::MOVA_MXI2Z_H_S, .PatternStart: 679, .NumPatterns: 1 }, |
| 16199 | {.Opcode: AArch64::MOVA_MXI2Z_V_B, .PatternStart: 680, .NumPatterns: 1 }, |
| 16200 | {.Opcode: AArch64::MOVA_MXI2Z_V_D, .PatternStart: 681, .NumPatterns: 1 }, |
| 16201 | {.Opcode: AArch64::MOVA_MXI2Z_V_H, .PatternStart: 682, .NumPatterns: 1 }, |
| 16202 | {.Opcode: AArch64::MOVA_MXI2Z_V_S, .PatternStart: 683, .NumPatterns: 1 }, |
| 16203 | {.Opcode: AArch64::MOVA_MXI4Z_H_B, .PatternStart: 684, .NumPatterns: 1 }, |
| 16204 | {.Opcode: AArch64::MOVA_MXI4Z_H_D, .PatternStart: 685, .NumPatterns: 1 }, |
| 16205 | {.Opcode: AArch64::MOVA_MXI4Z_H_H, .PatternStart: 686, .NumPatterns: 1 }, |
| 16206 | {.Opcode: AArch64::MOVA_MXI4Z_H_S, .PatternStart: 687, .NumPatterns: 1 }, |
| 16207 | {.Opcode: AArch64::MOVA_MXI4Z_V_B, .PatternStart: 688, .NumPatterns: 1 }, |
| 16208 | {.Opcode: AArch64::MOVA_MXI4Z_V_D, .PatternStart: 689, .NumPatterns: 1 }, |
| 16209 | {.Opcode: AArch64::MOVA_MXI4Z_V_H, .PatternStart: 690, .NumPatterns: 1 }, |
| 16210 | {.Opcode: AArch64::MOVA_MXI4Z_V_S, .PatternStart: 691, .NumPatterns: 1 }, |
| 16211 | {.Opcode: AArch64::MOVA_VG2_2ZMXI, .PatternStart: 692, .NumPatterns: 1 }, |
| 16212 | {.Opcode: AArch64::MOVA_VG2_MXI2Z, .PatternStart: 693, .NumPatterns: 1 }, |
| 16213 | {.Opcode: AArch64::MOVA_VG4_4ZMXI, .PatternStart: 694, .NumPatterns: 1 }, |
| 16214 | {.Opcode: AArch64::MOVA_VG4_MXI4Z, .PatternStart: 695, .NumPatterns: 1 }, |
| 16215 | {.Opcode: AArch64::MOVT_TIZ, .PatternStart: 696, .NumPatterns: 1 }, |
| 16216 | {.Opcode: AArch64::MSRpstatesvcrImm1, .PatternStart: 697, .NumPatterns: 6 }, |
| 16217 | {.Opcode: AArch64::MSUBWrrr, .PatternStart: 703, .NumPatterns: 1 }, |
| 16218 | {.Opcode: AArch64::MSUBXrrr, .PatternStart: 704, .NumPatterns: 1 }, |
| 16219 | {.Opcode: AArch64::NOP, .PatternStart: 705, .NumPatterns: 1 }, |
| 16220 | {.Opcode: AArch64::NOTv16i8, .PatternStart: 706, .NumPatterns: 1 }, |
| 16221 | {.Opcode: AArch64::NOTv8i8, .PatternStart: 707, .NumPatterns: 1 }, |
| 16222 | {.Opcode: AArch64::ORNWrs, .PatternStart: 708, .NumPatterns: 3 }, |
| 16223 | {.Opcode: AArch64::ORNXrs, .PatternStart: 711, .NumPatterns: 3 }, |
| 16224 | {.Opcode: AArch64::ORRS_PPzPP, .PatternStart: 714, .NumPatterns: 1 }, |
| 16225 | {.Opcode: AArch64::ORRWrs, .PatternStart: 715, .NumPatterns: 2 }, |
| 16226 | {.Opcode: AArch64::ORRXrs, .PatternStart: 717, .NumPatterns: 2 }, |
| 16227 | {.Opcode: AArch64::ORR_PPzPP, .PatternStart: 719, .NumPatterns: 1 }, |
| 16228 | {.Opcode: AArch64::ORR_ZI, .PatternStart: 720, .NumPatterns: 3 }, |
| 16229 | {.Opcode: AArch64::ORR_ZZZ, .PatternStart: 723, .NumPatterns: 1 }, |
| 16230 | {.Opcode: AArch64::ORRv16i8, .PatternStart: 724, .NumPatterns: 1 }, |
| 16231 | {.Opcode: AArch64::ORRv8i8, .PatternStart: 725, .NumPatterns: 1 }, |
| 16232 | {.Opcode: AArch64::PACIA1716, .PatternStart: 726, .NumPatterns: 1 }, |
| 16233 | {.Opcode: AArch64::PACIASP, .PatternStart: 727, .NumPatterns: 1 }, |
| 16234 | {.Opcode: AArch64::PACIAZ, .PatternStart: 728, .NumPatterns: 1 }, |
| 16235 | {.Opcode: AArch64::PACIB1716, .PatternStart: 729, .NumPatterns: 1 }, |
| 16236 | {.Opcode: AArch64::PACIBSP, .PatternStart: 730, .NumPatterns: 1 }, |
| 16237 | {.Opcode: AArch64::PACIBZ, .PatternStart: 731, .NumPatterns: 1 }, |
| 16238 | {.Opcode: AArch64::PACM, .PatternStart: 732, .NumPatterns: 1 }, |
| 16239 | {.Opcode: AArch64::PMOV_PZI_B, .PatternStart: 733, .NumPatterns: 1 }, |
| 16240 | {.Opcode: AArch64::PMOV_ZIP_B, .PatternStart: 734, .NumPatterns: 1 }, |
| 16241 | {.Opcode: AArch64::PRFB_D_PZI, .PatternStart: 735, .NumPatterns: 1 }, |
| 16242 | {.Opcode: AArch64::PRFB_PRI, .PatternStart: 736, .NumPatterns: 1 }, |
| 16243 | {.Opcode: AArch64::PRFB_S_PZI, .PatternStart: 737, .NumPatterns: 1 }, |
| 16244 | {.Opcode: AArch64::PRFD_D_PZI, .PatternStart: 738, .NumPatterns: 1 }, |
| 16245 | {.Opcode: AArch64::PRFD_PRI, .PatternStart: 739, .NumPatterns: 1 }, |
| 16246 | {.Opcode: AArch64::PRFD_S_PZI, .PatternStart: 740, .NumPatterns: 1 }, |
| 16247 | {.Opcode: AArch64::PRFH_D_PZI, .PatternStart: 741, .NumPatterns: 1 }, |
| 16248 | {.Opcode: AArch64::PRFH_PRI, .PatternStart: 742, .NumPatterns: 1 }, |
| 16249 | {.Opcode: AArch64::PRFH_S_PZI, .PatternStart: 743, .NumPatterns: 1 }, |
| 16250 | {.Opcode: AArch64::PRFMroX, .PatternStart: 744, .NumPatterns: 1 }, |
| 16251 | {.Opcode: AArch64::PRFMui, .PatternStart: 745, .NumPatterns: 1 }, |
| 16252 | {.Opcode: AArch64::PRFUMi, .PatternStart: 746, .NumPatterns: 1 }, |
| 16253 | {.Opcode: AArch64::PRFW_D_PZI, .PatternStart: 747, .NumPatterns: 1 }, |
| 16254 | {.Opcode: AArch64::PRFW_PRI, .PatternStart: 748, .NumPatterns: 1 }, |
| 16255 | {.Opcode: AArch64::PRFW_S_PZI, .PatternStart: 749, .NumPatterns: 1 }, |
| 16256 | {.Opcode: AArch64::PTRUES_B, .PatternStart: 750, .NumPatterns: 1 }, |
| 16257 | {.Opcode: AArch64::PTRUES_D, .PatternStart: 751, .NumPatterns: 1 }, |
| 16258 | {.Opcode: AArch64::PTRUES_H, .PatternStart: 752, .NumPatterns: 1 }, |
| 16259 | {.Opcode: AArch64::PTRUES_S, .PatternStart: 753, .NumPatterns: 1 }, |
| 16260 | {.Opcode: AArch64::PTRUE_B, .PatternStart: 754, .NumPatterns: 1 }, |
| 16261 | {.Opcode: AArch64::PTRUE_D, .PatternStart: 755, .NumPatterns: 1 }, |
| 16262 | {.Opcode: AArch64::PTRUE_H, .PatternStart: 756, .NumPatterns: 1 }, |
| 16263 | {.Opcode: AArch64::PTRUE_S, .PatternStart: 757, .NumPatterns: 1 }, |
| 16264 | {.Opcode: AArch64::RET, .PatternStart: 758, .NumPatterns: 1 }, |
| 16265 | {.Opcode: AArch64::SBCSWr, .PatternStart: 759, .NumPatterns: 1 }, |
| 16266 | {.Opcode: AArch64::SBCSXr, .PatternStart: 760, .NumPatterns: 1 }, |
| 16267 | {.Opcode: AArch64::SBCWr, .PatternStart: 761, .NumPatterns: 1 }, |
| 16268 | {.Opcode: AArch64::SBCXr, .PatternStart: 762, .NumPatterns: 1 }, |
| 16269 | {.Opcode: AArch64::SBFMWri, .PatternStart: 763, .NumPatterns: 3 }, |
| 16270 | {.Opcode: AArch64::SBFMXri, .PatternStart: 766, .NumPatterns: 4 }, |
| 16271 | {.Opcode: AArch64::SEL_PPPP, .PatternStart: 770, .NumPatterns: 1 }, |
| 16272 | {.Opcode: AArch64::SEL_ZPZZ_B, .PatternStart: 771, .NumPatterns: 1 }, |
| 16273 | {.Opcode: AArch64::SEL_ZPZZ_D, .PatternStart: 772, .NumPatterns: 1 }, |
| 16274 | {.Opcode: AArch64::SEL_ZPZZ_H, .PatternStart: 773, .NumPatterns: 1 }, |
| 16275 | {.Opcode: AArch64::SEL_ZPZZ_S, .PatternStart: 774, .NumPatterns: 1 }, |
| 16276 | {.Opcode: AArch64::SMADDLrrr, .PatternStart: 775, .NumPatterns: 1 }, |
| 16277 | {.Opcode: AArch64::SMSUBLrrr, .PatternStart: 776, .NumPatterns: 1 }, |
| 16278 | {.Opcode: AArch64::SQDECB_XPiI, .PatternStart: 777, .NumPatterns: 2 }, |
| 16279 | {.Opcode: AArch64::SQDECB_XPiWdI, .PatternStart: 779, .NumPatterns: 2 }, |
| 16280 | {.Opcode: AArch64::SQDECD_XPiI, .PatternStart: 781, .NumPatterns: 2 }, |
| 16281 | {.Opcode: AArch64::SQDECD_XPiWdI, .PatternStart: 783, .NumPatterns: 2 }, |
| 16282 | {.Opcode: AArch64::SQDECD_ZPiI, .PatternStart: 785, .NumPatterns: 2 }, |
| 16283 | {.Opcode: AArch64::SQDECH_XPiI, .PatternStart: 787, .NumPatterns: 2 }, |
| 16284 | {.Opcode: AArch64::SQDECH_XPiWdI, .PatternStart: 789, .NumPatterns: 2 }, |
| 16285 | {.Opcode: AArch64::SQDECH_ZPiI, .PatternStart: 791, .NumPatterns: 2 }, |
| 16286 | {.Opcode: AArch64::SQDECW_XPiI, .PatternStart: 793, .NumPatterns: 2 }, |
| 16287 | {.Opcode: AArch64::SQDECW_XPiWdI, .PatternStart: 795, .NumPatterns: 2 }, |
| 16288 | {.Opcode: AArch64::SQDECW_ZPiI, .PatternStart: 797, .NumPatterns: 2 }, |
| 16289 | {.Opcode: AArch64::SQINCB_XPiI, .PatternStart: 799, .NumPatterns: 2 }, |
| 16290 | {.Opcode: AArch64::SQINCB_XPiWdI, .PatternStart: 801, .NumPatterns: 2 }, |
| 16291 | {.Opcode: AArch64::SQINCD_XPiI, .PatternStart: 803, .NumPatterns: 2 }, |
| 16292 | {.Opcode: AArch64::SQINCD_XPiWdI, .PatternStart: 805, .NumPatterns: 2 }, |
| 16293 | {.Opcode: AArch64::SQINCD_ZPiI, .PatternStart: 807, .NumPatterns: 2 }, |
| 16294 | {.Opcode: AArch64::SQINCH_XPiI, .PatternStart: 809, .NumPatterns: 2 }, |
| 16295 | {.Opcode: AArch64::SQINCH_XPiWdI, .PatternStart: 811, .NumPatterns: 2 }, |
| 16296 | {.Opcode: AArch64::SQINCH_ZPiI, .PatternStart: 813, .NumPatterns: 2 }, |
| 16297 | {.Opcode: AArch64::SQINCW_XPiI, .PatternStart: 815, .NumPatterns: 2 }, |
| 16298 | {.Opcode: AArch64::SQINCW_XPiWdI, .PatternStart: 817, .NumPatterns: 2 }, |
| 16299 | {.Opcode: AArch64::SQINCW_ZPiI, .PatternStart: 819, .NumPatterns: 2 }, |
| 16300 | {.Opcode: AArch64::SST1B_D_IMM, .PatternStart: 821, .NumPatterns: 1 }, |
| 16301 | {.Opcode: AArch64::SST1B_S_IMM, .PatternStart: 822, .NumPatterns: 1 }, |
| 16302 | {.Opcode: AArch64::SST1D_IMM, .PatternStart: 823, .NumPatterns: 1 }, |
| 16303 | {.Opcode: AArch64::SST1H_D_IMM, .PatternStart: 824, .NumPatterns: 1 }, |
| 16304 | {.Opcode: AArch64::SST1H_S_IMM, .PatternStart: 825, .NumPatterns: 1 }, |
| 16305 | {.Opcode: AArch64::SST1Q, .PatternStart: 826, .NumPatterns: 1 }, |
| 16306 | {.Opcode: AArch64::SST1W_D_IMM, .PatternStart: 827, .NumPatterns: 1 }, |
| 16307 | {.Opcode: AArch64::SST1W_IMM, .PatternStart: 828, .NumPatterns: 1 }, |
| 16308 | {.Opcode: AArch64::ST1B_2Z_IMM, .PatternStart: 829, .NumPatterns: 1 }, |
| 16309 | {.Opcode: AArch64::ST1B_2Z_STRIDED_IMM, .PatternStart: 830, .NumPatterns: 1 }, |
| 16310 | {.Opcode: AArch64::ST1B_4Z_IMM, .PatternStart: 831, .NumPatterns: 1 }, |
| 16311 | {.Opcode: AArch64::ST1B_4Z_STRIDED_IMM, .PatternStart: 832, .NumPatterns: 1 }, |
| 16312 | {.Opcode: AArch64::ST1B_D_IMM, .PatternStart: 833, .NumPatterns: 1 }, |
| 16313 | {.Opcode: AArch64::ST1B_H_IMM, .PatternStart: 834, .NumPatterns: 1 }, |
| 16314 | {.Opcode: AArch64::ST1B_IMM, .PatternStart: 835, .NumPatterns: 1 }, |
| 16315 | {.Opcode: AArch64::ST1B_S_IMM, .PatternStart: 836, .NumPatterns: 1 }, |
| 16316 | {.Opcode: AArch64::ST1D_2Z_IMM, .PatternStart: 837, .NumPatterns: 1 }, |
| 16317 | {.Opcode: AArch64::ST1D_2Z_STRIDED_IMM, .PatternStart: 838, .NumPatterns: 1 }, |
| 16318 | {.Opcode: AArch64::ST1D_4Z_IMM, .PatternStart: 839, .NumPatterns: 1 }, |
| 16319 | {.Opcode: AArch64::ST1D_4Z_STRIDED_IMM, .PatternStart: 840, .NumPatterns: 1 }, |
| 16320 | {.Opcode: AArch64::ST1D_IMM, .PatternStart: 841, .NumPatterns: 1 }, |
| 16321 | {.Opcode: AArch64::ST1D_Q_IMM, .PatternStart: 842, .NumPatterns: 1 }, |
| 16322 | {.Opcode: AArch64::ST1Fourv16b_POST, .PatternStart: 843, .NumPatterns: 1 }, |
| 16323 | {.Opcode: AArch64::ST1Fourv1d_POST, .PatternStart: 844, .NumPatterns: 1 }, |
| 16324 | {.Opcode: AArch64::ST1Fourv2d_POST, .PatternStart: 845, .NumPatterns: 1 }, |
| 16325 | {.Opcode: AArch64::ST1Fourv2s_POST, .PatternStart: 846, .NumPatterns: 1 }, |
| 16326 | {.Opcode: AArch64::ST1Fourv4h_POST, .PatternStart: 847, .NumPatterns: 1 }, |
| 16327 | {.Opcode: AArch64::ST1Fourv4s_POST, .PatternStart: 848, .NumPatterns: 1 }, |
| 16328 | {.Opcode: AArch64::ST1Fourv8b_POST, .PatternStart: 849, .NumPatterns: 1 }, |
| 16329 | {.Opcode: AArch64::ST1Fourv8h_POST, .PatternStart: 850, .NumPatterns: 1 }, |
| 16330 | {.Opcode: AArch64::ST1H_2Z_IMM, .PatternStart: 851, .NumPatterns: 1 }, |
| 16331 | {.Opcode: AArch64::ST1H_2Z_STRIDED_IMM, .PatternStart: 852, .NumPatterns: 1 }, |
| 16332 | {.Opcode: AArch64::ST1H_4Z_IMM, .PatternStart: 853, .NumPatterns: 1 }, |
| 16333 | {.Opcode: AArch64::ST1H_4Z_STRIDED_IMM, .PatternStart: 854, .NumPatterns: 1 }, |
| 16334 | {.Opcode: AArch64::ST1H_D_IMM, .PatternStart: 855, .NumPatterns: 1 }, |
| 16335 | {.Opcode: AArch64::ST1H_IMM, .PatternStart: 856, .NumPatterns: 1 }, |
| 16336 | {.Opcode: AArch64::ST1H_S_IMM, .PatternStart: 857, .NumPatterns: 1 }, |
| 16337 | {.Opcode: AArch64::ST1Onev16b_POST, .PatternStart: 858, .NumPatterns: 1 }, |
| 16338 | {.Opcode: AArch64::ST1Onev1d_POST, .PatternStart: 859, .NumPatterns: 1 }, |
| 16339 | {.Opcode: AArch64::ST1Onev2d_POST, .PatternStart: 860, .NumPatterns: 1 }, |
| 16340 | {.Opcode: AArch64::ST1Onev2s_POST, .PatternStart: 861, .NumPatterns: 1 }, |
| 16341 | {.Opcode: AArch64::ST1Onev4h_POST, .PatternStart: 862, .NumPatterns: 1 }, |
| 16342 | {.Opcode: AArch64::ST1Onev4s_POST, .PatternStart: 863, .NumPatterns: 1 }, |
| 16343 | {.Opcode: AArch64::ST1Onev8b_POST, .PatternStart: 864, .NumPatterns: 1 }, |
| 16344 | {.Opcode: AArch64::ST1Onev8h_POST, .PatternStart: 865, .NumPatterns: 1 }, |
| 16345 | {.Opcode: AArch64::ST1Threev16b_POST, .PatternStart: 866, .NumPatterns: 1 }, |
| 16346 | {.Opcode: AArch64::ST1Threev1d_POST, .PatternStart: 867, .NumPatterns: 1 }, |
| 16347 | {.Opcode: AArch64::ST1Threev2d_POST, .PatternStart: 868, .NumPatterns: 1 }, |
| 16348 | {.Opcode: AArch64::ST1Threev2s_POST, .PatternStart: 869, .NumPatterns: 1 }, |
| 16349 | {.Opcode: AArch64::ST1Threev4h_POST, .PatternStart: 870, .NumPatterns: 1 }, |
| 16350 | {.Opcode: AArch64::ST1Threev4s_POST, .PatternStart: 871, .NumPatterns: 1 }, |
| 16351 | {.Opcode: AArch64::ST1Threev8b_POST, .PatternStart: 872, .NumPatterns: 1 }, |
| 16352 | {.Opcode: AArch64::ST1Threev8h_POST, .PatternStart: 873, .NumPatterns: 1 }, |
| 16353 | {.Opcode: AArch64::ST1Twov16b_POST, .PatternStart: 874, .NumPatterns: 1 }, |
| 16354 | {.Opcode: AArch64::ST1Twov1d_POST, .PatternStart: 875, .NumPatterns: 1 }, |
| 16355 | {.Opcode: AArch64::ST1Twov2d_POST, .PatternStart: 876, .NumPatterns: 1 }, |
| 16356 | {.Opcode: AArch64::ST1Twov2s_POST, .PatternStart: 877, .NumPatterns: 1 }, |
| 16357 | {.Opcode: AArch64::ST1Twov4h_POST, .PatternStart: 878, .NumPatterns: 1 }, |
| 16358 | {.Opcode: AArch64::ST1Twov4s_POST, .PatternStart: 879, .NumPatterns: 1 }, |
| 16359 | {.Opcode: AArch64::ST1Twov8b_POST, .PatternStart: 880, .NumPatterns: 1 }, |
| 16360 | {.Opcode: AArch64::ST1Twov8h_POST, .PatternStart: 881, .NumPatterns: 1 }, |
| 16361 | {.Opcode: AArch64::ST1W_2Z_IMM, .PatternStart: 882, .NumPatterns: 1 }, |
| 16362 | {.Opcode: AArch64::ST1W_2Z_STRIDED_IMM, .PatternStart: 883, .NumPatterns: 1 }, |
| 16363 | {.Opcode: AArch64::ST1W_4Z_IMM, .PatternStart: 884, .NumPatterns: 1 }, |
| 16364 | {.Opcode: AArch64::ST1W_4Z_STRIDED_IMM, .PatternStart: 885, .NumPatterns: 1 }, |
| 16365 | {.Opcode: AArch64::ST1W_D_IMM, .PatternStart: 886, .NumPatterns: 1 }, |
| 16366 | {.Opcode: AArch64::ST1W_IMM, .PatternStart: 887, .NumPatterns: 1 }, |
| 16367 | {.Opcode: AArch64::ST1W_Q_IMM, .PatternStart: 888, .NumPatterns: 1 }, |
| 16368 | {.Opcode: AArch64::ST1_MXIPXX_H_B, .PatternStart: 889, .NumPatterns: 1 }, |
| 16369 | {.Opcode: AArch64::ST1_MXIPXX_H_D, .PatternStart: 890, .NumPatterns: 1 }, |
| 16370 | {.Opcode: AArch64::ST1_MXIPXX_H_H, .PatternStart: 891, .NumPatterns: 1 }, |
| 16371 | {.Opcode: AArch64::ST1_MXIPXX_H_Q, .PatternStart: 892, .NumPatterns: 1 }, |
| 16372 | {.Opcode: AArch64::ST1_MXIPXX_H_S, .PatternStart: 893, .NumPatterns: 1 }, |
| 16373 | {.Opcode: AArch64::ST1_MXIPXX_V_B, .PatternStart: 894, .NumPatterns: 1 }, |
| 16374 | {.Opcode: AArch64::ST1_MXIPXX_V_D, .PatternStart: 895, .NumPatterns: 1 }, |
| 16375 | {.Opcode: AArch64::ST1_MXIPXX_V_H, .PatternStart: 896, .NumPatterns: 1 }, |
| 16376 | {.Opcode: AArch64::ST1_MXIPXX_V_Q, .PatternStart: 897, .NumPatterns: 1 }, |
| 16377 | {.Opcode: AArch64::ST1_MXIPXX_V_S, .PatternStart: 898, .NumPatterns: 1 }, |
| 16378 | {.Opcode: AArch64::ST1i16_POST, .PatternStart: 899, .NumPatterns: 1 }, |
| 16379 | {.Opcode: AArch64::ST1i32_POST, .PatternStart: 900, .NumPatterns: 1 }, |
| 16380 | {.Opcode: AArch64::ST1i64_POST, .PatternStart: 901, .NumPatterns: 1 }, |
| 16381 | {.Opcode: AArch64::ST1i8_POST, .PatternStart: 902, .NumPatterns: 1 }, |
| 16382 | {.Opcode: AArch64::ST2B_IMM, .PatternStart: 903, .NumPatterns: 1 }, |
| 16383 | {.Opcode: AArch64::ST2D_IMM, .PatternStart: 904, .NumPatterns: 1 }, |
| 16384 | {.Opcode: AArch64::ST2Gi, .PatternStart: 905, .NumPatterns: 1 }, |
| 16385 | {.Opcode: AArch64::ST2H_IMM, .PatternStart: 906, .NumPatterns: 1 }, |
| 16386 | {.Opcode: AArch64::ST2Q_IMM, .PatternStart: 907, .NumPatterns: 1 }, |
| 16387 | {.Opcode: AArch64::ST2Twov16b_POST, .PatternStart: 908, .NumPatterns: 1 }, |
| 16388 | {.Opcode: AArch64::ST2Twov2d_POST, .PatternStart: 909, .NumPatterns: 1 }, |
| 16389 | {.Opcode: AArch64::ST2Twov2s_POST, .PatternStart: 910, .NumPatterns: 1 }, |
| 16390 | {.Opcode: AArch64::ST2Twov4h_POST, .PatternStart: 911, .NumPatterns: 1 }, |
| 16391 | {.Opcode: AArch64::ST2Twov4s_POST, .PatternStart: 912, .NumPatterns: 1 }, |
| 16392 | {.Opcode: AArch64::ST2Twov8b_POST, .PatternStart: 913, .NumPatterns: 1 }, |
| 16393 | {.Opcode: AArch64::ST2Twov8h_POST, .PatternStart: 914, .NumPatterns: 1 }, |
| 16394 | {.Opcode: AArch64::ST2W_IMM, .PatternStart: 915, .NumPatterns: 1 }, |
| 16395 | {.Opcode: AArch64::ST2i16_POST, .PatternStart: 916, .NumPatterns: 1 }, |
| 16396 | {.Opcode: AArch64::ST2i32_POST, .PatternStart: 917, .NumPatterns: 1 }, |
| 16397 | {.Opcode: AArch64::ST2i64_POST, .PatternStart: 918, .NumPatterns: 1 }, |
| 16398 | {.Opcode: AArch64::ST2i8_POST, .PatternStart: 919, .NumPatterns: 1 }, |
| 16399 | {.Opcode: AArch64::ST3B_IMM, .PatternStart: 920, .NumPatterns: 1 }, |
| 16400 | {.Opcode: AArch64::ST3D_IMM, .PatternStart: 921, .NumPatterns: 1 }, |
| 16401 | {.Opcode: AArch64::ST3H_IMM, .PatternStart: 922, .NumPatterns: 1 }, |
| 16402 | {.Opcode: AArch64::ST3Q_IMM, .PatternStart: 923, .NumPatterns: 1 }, |
| 16403 | {.Opcode: AArch64::ST3Threev16b_POST, .PatternStart: 924, .NumPatterns: 1 }, |
| 16404 | {.Opcode: AArch64::ST3Threev2d_POST, .PatternStart: 925, .NumPatterns: 1 }, |
| 16405 | {.Opcode: AArch64::ST3Threev2s_POST, .PatternStart: 926, .NumPatterns: 1 }, |
| 16406 | {.Opcode: AArch64::ST3Threev4h_POST, .PatternStart: 927, .NumPatterns: 1 }, |
| 16407 | {.Opcode: AArch64::ST3Threev4s_POST, .PatternStart: 928, .NumPatterns: 1 }, |
| 16408 | {.Opcode: AArch64::ST3Threev8b_POST, .PatternStart: 929, .NumPatterns: 1 }, |
| 16409 | {.Opcode: AArch64::ST3Threev8h_POST, .PatternStart: 930, .NumPatterns: 1 }, |
| 16410 | {.Opcode: AArch64::ST3W_IMM, .PatternStart: 931, .NumPatterns: 1 }, |
| 16411 | {.Opcode: AArch64::ST3i16_POST, .PatternStart: 932, .NumPatterns: 1 }, |
| 16412 | {.Opcode: AArch64::ST3i32_POST, .PatternStart: 933, .NumPatterns: 1 }, |
| 16413 | {.Opcode: AArch64::ST3i64_POST, .PatternStart: 934, .NumPatterns: 1 }, |
| 16414 | {.Opcode: AArch64::ST3i8_POST, .PatternStart: 935, .NumPatterns: 1 }, |
| 16415 | {.Opcode: AArch64::ST4B_IMM, .PatternStart: 936, .NumPatterns: 1 }, |
| 16416 | {.Opcode: AArch64::ST4D_IMM, .PatternStart: 937, .NumPatterns: 1 }, |
| 16417 | {.Opcode: AArch64::ST4Fourv16b_POST, .PatternStart: 938, .NumPatterns: 1 }, |
| 16418 | {.Opcode: AArch64::ST4Fourv2d_POST, .PatternStart: 939, .NumPatterns: 1 }, |
| 16419 | {.Opcode: AArch64::ST4Fourv2s_POST, .PatternStart: 940, .NumPatterns: 1 }, |
| 16420 | {.Opcode: AArch64::ST4Fourv4h_POST, .PatternStart: 941, .NumPatterns: 1 }, |
| 16421 | {.Opcode: AArch64::ST4Fourv4s_POST, .PatternStart: 942, .NumPatterns: 1 }, |
| 16422 | {.Opcode: AArch64::ST4Fourv8b_POST, .PatternStart: 943, .NumPatterns: 1 }, |
| 16423 | {.Opcode: AArch64::ST4Fourv8h_POST, .PatternStart: 944, .NumPatterns: 1 }, |
| 16424 | {.Opcode: AArch64::ST4H_IMM, .PatternStart: 945, .NumPatterns: 1 }, |
| 16425 | {.Opcode: AArch64::ST4Q_IMM, .PatternStart: 946, .NumPatterns: 1 }, |
| 16426 | {.Opcode: AArch64::ST4W_IMM, .PatternStart: 947, .NumPatterns: 1 }, |
| 16427 | {.Opcode: AArch64::ST4i16_POST, .PatternStart: 948, .NumPatterns: 1 }, |
| 16428 | {.Opcode: AArch64::ST4i32_POST, .PatternStart: 949, .NumPatterns: 1 }, |
| 16429 | {.Opcode: AArch64::ST4i64_POST, .PatternStart: 950, .NumPatterns: 1 }, |
| 16430 | {.Opcode: AArch64::ST4i8_POST, .PatternStart: 951, .NumPatterns: 1 }, |
| 16431 | {.Opcode: AArch64::STGPi, .PatternStart: 952, .NumPatterns: 1 }, |
| 16432 | {.Opcode: AArch64::STGi, .PatternStart: 953, .NumPatterns: 1 }, |
| 16433 | {.Opcode: AArch64::STLPi, .PatternStart: 954, .NumPatterns: 1 }, |
| 16434 | {.Opcode: AArch64::STLURBi, .PatternStart: 955, .NumPatterns: 1 }, |
| 16435 | {.Opcode: AArch64::STLURHi, .PatternStart: 956, .NumPatterns: 1 }, |
| 16436 | {.Opcode: AArch64::STLURWi, .PatternStart: 957, .NumPatterns: 1 }, |
| 16437 | {.Opcode: AArch64::STLURXi, .PatternStart: 958, .NumPatterns: 1 }, |
| 16438 | {.Opcode: AArch64::STLURbi, .PatternStart: 959, .NumPatterns: 1 }, |
| 16439 | {.Opcode: AArch64::STLURdi, .PatternStart: 960, .NumPatterns: 1 }, |
| 16440 | {.Opcode: AArch64::STLURhi, .PatternStart: 961, .NumPatterns: 1 }, |
| 16441 | {.Opcode: AArch64::STLURqi, .PatternStart: 962, .NumPatterns: 1 }, |
| 16442 | {.Opcode: AArch64::STLURsi, .PatternStart: 963, .NumPatterns: 1 }, |
| 16443 | {.Opcode: AArch64::STNPDi, .PatternStart: 964, .NumPatterns: 1 }, |
| 16444 | {.Opcode: AArch64::STNPQi, .PatternStart: 965, .NumPatterns: 1 }, |
| 16445 | {.Opcode: AArch64::STNPSi, .PatternStart: 966, .NumPatterns: 1 }, |
| 16446 | {.Opcode: AArch64::STNPWi, .PatternStart: 967, .NumPatterns: 1 }, |
| 16447 | {.Opcode: AArch64::STNPXi, .PatternStart: 968, .NumPatterns: 1 }, |
| 16448 | {.Opcode: AArch64::STNT1B_2Z_IMM, .PatternStart: 969, .NumPatterns: 1 }, |
| 16449 | {.Opcode: AArch64::STNT1B_2Z_STRIDED_IMM, .PatternStart: 970, .NumPatterns: 1 }, |
| 16450 | {.Opcode: AArch64::STNT1B_4Z_IMM, .PatternStart: 971, .NumPatterns: 1 }, |
| 16451 | {.Opcode: AArch64::STNT1B_4Z_STRIDED_IMM, .PatternStart: 972, .NumPatterns: 1 }, |
| 16452 | {.Opcode: AArch64::STNT1B_ZRI, .PatternStart: 973, .NumPatterns: 1 }, |
| 16453 | {.Opcode: AArch64::STNT1B_ZZR_D, .PatternStart: 974, .NumPatterns: 1 }, |
| 16454 | {.Opcode: AArch64::STNT1B_ZZR_S, .PatternStart: 975, .NumPatterns: 1 }, |
| 16455 | {.Opcode: AArch64::STNT1D_2Z_IMM, .PatternStart: 976, .NumPatterns: 1 }, |
| 16456 | {.Opcode: AArch64::STNT1D_2Z_STRIDED_IMM, .PatternStart: 977, .NumPatterns: 1 }, |
| 16457 | {.Opcode: AArch64::STNT1D_4Z_IMM, .PatternStart: 978, .NumPatterns: 1 }, |
| 16458 | {.Opcode: AArch64::STNT1D_4Z_STRIDED_IMM, .PatternStart: 979, .NumPatterns: 1 }, |
| 16459 | {.Opcode: AArch64::STNT1D_ZRI, .PatternStart: 980, .NumPatterns: 1 }, |
| 16460 | {.Opcode: AArch64::STNT1D_ZZR_D, .PatternStart: 981, .NumPatterns: 1 }, |
| 16461 | {.Opcode: AArch64::STNT1H_2Z_IMM, .PatternStart: 982, .NumPatterns: 1 }, |
| 16462 | {.Opcode: AArch64::STNT1H_2Z_STRIDED_IMM, .PatternStart: 983, .NumPatterns: 1 }, |
| 16463 | {.Opcode: AArch64::STNT1H_4Z_IMM, .PatternStart: 984, .NumPatterns: 1 }, |
| 16464 | {.Opcode: AArch64::STNT1H_4Z_STRIDED_IMM, .PatternStart: 985, .NumPatterns: 1 }, |
| 16465 | {.Opcode: AArch64::STNT1H_ZRI, .PatternStart: 986, .NumPatterns: 1 }, |
| 16466 | {.Opcode: AArch64::STNT1H_ZZR_D, .PatternStart: 987, .NumPatterns: 1 }, |
| 16467 | {.Opcode: AArch64::STNT1H_ZZR_S, .PatternStart: 988, .NumPatterns: 1 }, |
| 16468 | {.Opcode: AArch64::STNT1W_2Z_IMM, .PatternStart: 989, .NumPatterns: 1 }, |
| 16469 | {.Opcode: AArch64::STNT1W_2Z_STRIDED_IMM, .PatternStart: 990, .NumPatterns: 1 }, |
| 16470 | {.Opcode: AArch64::STNT1W_4Z_IMM, .PatternStart: 991, .NumPatterns: 1 }, |
| 16471 | {.Opcode: AArch64::STNT1W_4Z_STRIDED_IMM, .PatternStart: 992, .NumPatterns: 1 }, |
| 16472 | {.Opcode: AArch64::STNT1W_ZRI, .PatternStart: 993, .NumPatterns: 1 }, |
| 16473 | {.Opcode: AArch64::STNT1W_ZZR_D, .PatternStart: 994, .NumPatterns: 1 }, |
| 16474 | {.Opcode: AArch64::STNT1W_ZZR_S, .PatternStart: 995, .NumPatterns: 1 }, |
| 16475 | {.Opcode: AArch64::STPDi, .PatternStart: 996, .NumPatterns: 1 }, |
| 16476 | {.Opcode: AArch64::STPQi, .PatternStart: 997, .NumPatterns: 1 }, |
| 16477 | {.Opcode: AArch64::STPSi, .PatternStart: 998, .NumPatterns: 1 }, |
| 16478 | {.Opcode: AArch64::STPWi, .PatternStart: 999, .NumPatterns: 1 }, |
| 16479 | {.Opcode: AArch64::STPXi, .PatternStart: 1000, .NumPatterns: 1 }, |
| 16480 | {.Opcode: AArch64::STRBBroX, .PatternStart: 1001, .NumPatterns: 1 }, |
| 16481 | {.Opcode: AArch64::STRBBui, .PatternStart: 1002, .NumPatterns: 1 }, |
| 16482 | {.Opcode: AArch64::STRBroX, .PatternStart: 1003, .NumPatterns: 1 }, |
| 16483 | {.Opcode: AArch64::STRBui, .PatternStart: 1004, .NumPatterns: 1 }, |
| 16484 | {.Opcode: AArch64::STRDroX, .PatternStart: 1005, .NumPatterns: 1 }, |
| 16485 | {.Opcode: AArch64::STRDui, .PatternStart: 1006, .NumPatterns: 1 }, |
| 16486 | {.Opcode: AArch64::STRHHroX, .PatternStart: 1007, .NumPatterns: 1 }, |
| 16487 | {.Opcode: AArch64::STRHHui, .PatternStart: 1008, .NumPatterns: 1 }, |
| 16488 | {.Opcode: AArch64::STRHroX, .PatternStart: 1009, .NumPatterns: 1 }, |
| 16489 | {.Opcode: AArch64::STRHui, .PatternStart: 1010, .NumPatterns: 1 }, |
| 16490 | {.Opcode: AArch64::STRQroX, .PatternStart: 1011, .NumPatterns: 1 }, |
| 16491 | {.Opcode: AArch64::STRQui, .PatternStart: 1012, .NumPatterns: 1 }, |
| 16492 | {.Opcode: AArch64::STRSroX, .PatternStart: 1013, .NumPatterns: 1 }, |
| 16493 | {.Opcode: AArch64::STRSui, .PatternStart: 1014, .NumPatterns: 1 }, |
| 16494 | {.Opcode: AArch64::STRWroX, .PatternStart: 1015, .NumPatterns: 1 }, |
| 16495 | {.Opcode: AArch64::STRWui, .PatternStart: 1016, .NumPatterns: 1 }, |
| 16496 | {.Opcode: AArch64::STRXroX, .PatternStart: 1017, .NumPatterns: 1 }, |
| 16497 | {.Opcode: AArch64::STRXui, .PatternStart: 1018, .NumPatterns: 1 }, |
| 16498 | {.Opcode: AArch64::STR_PXI, .PatternStart: 1019, .NumPatterns: 1 }, |
| 16499 | {.Opcode: AArch64::STR_ZA, .PatternStart: 1020, .NumPatterns: 1 }, |
| 16500 | {.Opcode: AArch64::STR_ZXI, .PatternStart: 1021, .NumPatterns: 1 }, |
| 16501 | {.Opcode: AArch64::STTNPQi, .PatternStart: 1022, .NumPatterns: 1 }, |
| 16502 | {.Opcode: AArch64::STTNPXi, .PatternStart: 1023, .NumPatterns: 1 }, |
| 16503 | {.Opcode: AArch64::STTPQi, .PatternStart: 1024, .NumPatterns: 1 }, |
| 16504 | {.Opcode: AArch64::STTPi, .PatternStart: 1025, .NumPatterns: 1 }, |
| 16505 | {.Opcode: AArch64::STTRBi, .PatternStart: 1026, .NumPatterns: 1 }, |
| 16506 | {.Opcode: AArch64::STTRHi, .PatternStart: 1027, .NumPatterns: 1 }, |
| 16507 | {.Opcode: AArch64::STTRWi, .PatternStart: 1028, .NumPatterns: 1 }, |
| 16508 | {.Opcode: AArch64::STTRXi, .PatternStart: 1029, .NumPatterns: 1 }, |
| 16509 | {.Opcode: AArch64::STURBBi, .PatternStart: 1030, .NumPatterns: 1 }, |
| 16510 | {.Opcode: AArch64::STURBi, .PatternStart: 1031, .NumPatterns: 1 }, |
| 16511 | {.Opcode: AArch64::STURDi, .PatternStart: 1032, .NumPatterns: 1 }, |
| 16512 | {.Opcode: AArch64::STURHHi, .PatternStart: 1033, .NumPatterns: 1 }, |
| 16513 | {.Opcode: AArch64::STURHi, .PatternStart: 1034, .NumPatterns: 1 }, |
| 16514 | {.Opcode: AArch64::STURQi, .PatternStart: 1035, .NumPatterns: 1 }, |
| 16515 | {.Opcode: AArch64::STURSi, .PatternStart: 1036, .NumPatterns: 1 }, |
| 16516 | {.Opcode: AArch64::STURWi, .PatternStart: 1037, .NumPatterns: 1 }, |
| 16517 | {.Opcode: AArch64::STURXi, .PatternStart: 1038, .NumPatterns: 1 }, |
| 16518 | {.Opcode: AArch64::STZ2Gi, .PatternStart: 1039, .NumPatterns: 1 }, |
| 16519 | {.Opcode: AArch64::STZGi, .PatternStart: 1040, .NumPatterns: 1 }, |
| 16520 | {.Opcode: AArch64::SUBPT_shift, .PatternStart: 1041, .NumPatterns: 1 }, |
| 16521 | {.Opcode: AArch64::SUBSWri, .PatternStart: 1042, .NumPatterns: 1 }, |
| 16522 | {.Opcode: AArch64::SUBSWrs, .PatternStart: 1043, .NumPatterns: 5 }, |
| 16523 | {.Opcode: AArch64::SUBSWrx, .PatternStart: 1048, .NumPatterns: 3 }, |
| 16524 | {.Opcode: AArch64::SUBSXri, .PatternStart: 1051, .NumPatterns: 1 }, |
| 16525 | {.Opcode: AArch64::SUBSXrs, .PatternStart: 1052, .NumPatterns: 5 }, |
| 16526 | {.Opcode: AArch64::SUBSXrx, .PatternStart: 1057, .NumPatterns: 1 }, |
| 16527 | {.Opcode: AArch64::SUBSXrx64, .PatternStart: 1058, .NumPatterns: 3 }, |
| 16528 | {.Opcode: AArch64::SUBWrs, .PatternStart: 1061, .NumPatterns: 3 }, |
| 16529 | {.Opcode: AArch64::SUBWrx, .PatternStart: 1064, .NumPatterns: 2 }, |
| 16530 | {.Opcode: AArch64::SUBXrs, .PatternStart: 1066, .NumPatterns: 3 }, |
| 16531 | {.Opcode: AArch64::SUBXrx64, .PatternStart: 1069, .NumPatterns: 2 }, |
| 16532 | {.Opcode: AArch64::SYSPxt_XZR, .PatternStart: 1071, .NumPatterns: 1 }, |
| 16533 | {.Opcode: AArch64::SYSxt, .PatternStart: 1072, .NumPatterns: 5 }, |
| 16534 | {.Opcode: AArch64::TCHANGEBri, .PatternStart: 1077, .NumPatterns: 1 }, |
| 16535 | {.Opcode: AArch64::TCHANGEBrr, .PatternStart: 1078, .NumPatterns: 1 }, |
| 16536 | {.Opcode: AArch64::TCHANGEFri, .PatternStart: 1079, .NumPatterns: 1 }, |
| 16537 | {.Opcode: AArch64::TCHANGEFrr, .PatternStart: 1080, .NumPatterns: 1 }, |
| 16538 | {.Opcode: AArch64::TENTER, .PatternStart: 1081, .NumPatterns: 1 }, |
| 16539 | {.Opcode: AArch64::TEXIT, .PatternStart: 1082, .NumPatterns: 1 }, |
| 16540 | {.Opcode: AArch64::TFLTNZ, .PatternStart: 1083, .NumPatterns: 1 }, |
| 16541 | {.Opcode: AArch64::TFLTZ, .PatternStart: 1084, .NumPatterns: 1 }, |
| 16542 | {.Opcode: AArch64::UBFMWri, .PatternStart: 1085, .NumPatterns: 3 }, |
| 16543 | {.Opcode: AArch64::UBFMXri, .PatternStart: 1088, .NumPatterns: 4 }, |
| 16544 | {.Opcode: AArch64::UMADDLrrr, .PatternStart: 1092, .NumPatterns: 1 }, |
| 16545 | {.Opcode: AArch64::UMOVvi32, .PatternStart: 1093, .NumPatterns: 1 }, |
| 16546 | {.Opcode: AArch64::UMOVvi32_idx0, .PatternStart: 1094, .NumPatterns: 1 }, |
| 16547 | {.Opcode: AArch64::UMOVvi64, .PatternStart: 1095, .NumPatterns: 1 }, |
| 16548 | {.Opcode: AArch64::UMOVvi64_idx0, .PatternStart: 1096, .NumPatterns: 1 }, |
| 16549 | {.Opcode: AArch64::UMSUBLrrr, .PatternStart: 1097, .NumPatterns: 1 }, |
| 16550 | {.Opcode: AArch64::UQDECB_WPiI, .PatternStart: 1098, .NumPatterns: 2 }, |
| 16551 | {.Opcode: AArch64::UQDECB_XPiI, .PatternStart: 1100, .NumPatterns: 2 }, |
| 16552 | {.Opcode: AArch64::UQDECD_WPiI, .PatternStart: 1102, .NumPatterns: 2 }, |
| 16553 | {.Opcode: AArch64::UQDECD_XPiI, .PatternStart: 1104, .NumPatterns: 2 }, |
| 16554 | {.Opcode: AArch64::UQDECD_ZPiI, .PatternStart: 1106, .NumPatterns: 2 }, |
| 16555 | {.Opcode: AArch64::UQDECH_WPiI, .PatternStart: 1108, .NumPatterns: 2 }, |
| 16556 | {.Opcode: AArch64::UQDECH_XPiI, .PatternStart: 1110, .NumPatterns: 2 }, |
| 16557 | {.Opcode: AArch64::UQDECH_ZPiI, .PatternStart: 1112, .NumPatterns: 2 }, |
| 16558 | {.Opcode: AArch64::UQDECW_WPiI, .PatternStart: 1114, .NumPatterns: 2 }, |
| 16559 | {.Opcode: AArch64::UQDECW_XPiI, .PatternStart: 1116, .NumPatterns: 2 }, |
| 16560 | {.Opcode: AArch64::UQDECW_ZPiI, .PatternStart: 1118, .NumPatterns: 2 }, |
| 16561 | {.Opcode: AArch64::UQINCB_WPiI, .PatternStart: 1120, .NumPatterns: 2 }, |
| 16562 | {.Opcode: AArch64::UQINCB_XPiI, .PatternStart: 1122, .NumPatterns: 2 }, |
| 16563 | {.Opcode: AArch64::UQINCD_WPiI, .PatternStart: 1124, .NumPatterns: 2 }, |
| 16564 | {.Opcode: AArch64::UQINCD_XPiI, .PatternStart: 1126, .NumPatterns: 2 }, |
| 16565 | {.Opcode: AArch64::UQINCD_ZPiI, .PatternStart: 1128, .NumPatterns: 2 }, |
| 16566 | {.Opcode: AArch64::UQINCH_WPiI, .PatternStart: 1130, .NumPatterns: 2 }, |
| 16567 | {.Opcode: AArch64::UQINCH_XPiI, .PatternStart: 1132, .NumPatterns: 2 }, |
| 16568 | {.Opcode: AArch64::UQINCH_ZPiI, .PatternStart: 1134, .NumPatterns: 2 }, |
| 16569 | {.Opcode: AArch64::UQINCW_WPiI, .PatternStart: 1136, .NumPatterns: 2 }, |
| 16570 | {.Opcode: AArch64::UQINCW_XPiI, .PatternStart: 1138, .NumPatterns: 2 }, |
| 16571 | {.Opcode: AArch64::UQINCW_ZPiI, .PatternStart: 1140, .NumPatterns: 2 }, |
| 16572 | {.Opcode: AArch64::XPACLRI, .PatternStart: 1142, .NumPatterns: 1 }, |
| 16573 | {.Opcode: AArch64::ZERO_M, .PatternStart: 1143, .NumPatterns: 15 }, |
| 16574 | }; |
| 16575 | |
| 16576 | static const AliasPattern Patterns[] = { |
| 16577 | // AArch64::ADDPT_shift - 0 |
| 16578 | {.AsmStrOffset: 0, .AliasCondStart: 0, .NumOperands: 4, .NumConds: 7 }, |
| 16579 | // AArch64::ADDSWri - 1 |
| 16580 | {.AsmStrOffset: 17, .AliasCondStart: 7, .NumOperands: 4, .NumConds: 2 }, |
| 16581 | // AArch64::ADDSWrs - 2 |
| 16582 | {.AsmStrOffset: 30, .AliasCondStart: 9, .NumOperands: 4, .NumConds: 4 }, |
| 16583 | {.AsmStrOffset: 41, .AliasCondStart: 13, .NumOperands: 4, .NumConds: 3 }, |
| 16584 | {.AsmStrOffset: 56, .AliasCondStart: 16, .NumOperands: 4, .NumConds: 4 }, |
| 16585 | // AArch64::ADDSWrx - 5 |
| 16586 | {.AsmStrOffset: 30, .AliasCondStart: 20, .NumOperands: 4, .NumConds: 4 }, |
| 16587 | {.AsmStrOffset: 72, .AliasCondStart: 24, .NumOperands: 4, .NumConds: 3 }, |
| 16588 | {.AsmStrOffset: 56, .AliasCondStart: 27, .NumOperands: 4, .NumConds: 4 }, |
| 16589 | // AArch64::ADDSXri - 8 |
| 16590 | {.AsmStrOffset: 17, .AliasCondStart: 31, .NumOperands: 4, .NumConds: 2 }, |
| 16591 | // AArch64::ADDSXrs - 9 |
| 16592 | {.AsmStrOffset: 30, .AliasCondStart: 33, .NumOperands: 4, .NumConds: 4 }, |
| 16593 | {.AsmStrOffset: 41, .AliasCondStart: 37, .NumOperands: 4, .NumConds: 3 }, |
| 16594 | {.AsmStrOffset: 56, .AliasCondStart: 40, .NumOperands: 4, .NumConds: 4 }, |
| 16595 | // AArch64::ADDSXrx - 12 |
| 16596 | {.AsmStrOffset: 72, .AliasCondStart: 44, .NumOperands: 4, .NumConds: 3 }, |
| 16597 | // AArch64::ADDSXrx64 - 13 |
| 16598 | {.AsmStrOffset: 30, .AliasCondStart: 47, .NumOperands: 4, .NumConds: 4 }, |
| 16599 | {.AsmStrOffset: 72, .AliasCondStart: 51, .NumOperands: 4, .NumConds: 3 }, |
| 16600 | {.AsmStrOffset: 56, .AliasCondStart: 54, .NumOperands: 4, .NumConds: 4 }, |
| 16601 | // AArch64::ADDWri - 16 |
| 16602 | {.AsmStrOffset: 87, .AliasCondStart: 58, .NumOperands: 4, .NumConds: 4 }, |
| 16603 | {.AsmStrOffset: 87, .AliasCondStart: 62, .NumOperands: 4, .NumConds: 4 }, |
| 16604 | // AArch64::ADDWrs - 18 |
| 16605 | {.AsmStrOffset: 98, .AliasCondStart: 66, .NumOperands: 4, .NumConds: 4 }, |
| 16606 | // AArch64::ADDWrx - 19 |
| 16607 | {.AsmStrOffset: 98, .AliasCondStart: 70, .NumOperands: 4, .NumConds: 4 }, |
| 16608 | {.AsmStrOffset: 98, .AliasCondStart: 74, .NumOperands: 4, .NumConds: 4 }, |
| 16609 | // AArch64::ADDXri - 21 |
| 16610 | {.AsmStrOffset: 87, .AliasCondStart: 78, .NumOperands: 4, .NumConds: 4 }, |
| 16611 | {.AsmStrOffset: 87, .AliasCondStart: 82, .NumOperands: 4, .NumConds: 4 }, |
| 16612 | // AArch64::ADDXrs - 23 |
| 16613 | {.AsmStrOffset: 98, .AliasCondStart: 86, .NumOperands: 4, .NumConds: 4 }, |
| 16614 | // AArch64::ADDXrx64 - 24 |
| 16615 | {.AsmStrOffset: 98, .AliasCondStart: 90, .NumOperands: 4, .NumConds: 4 }, |
| 16616 | {.AsmStrOffset: 98, .AliasCondStart: 94, .NumOperands: 4, .NumConds: 4 }, |
| 16617 | // AArch64::ANDSWri - 26 |
| 16618 | {.AsmStrOffset: 113, .AliasCondStart: 98, .NumOperands: 3, .NumConds: 2 }, |
| 16619 | // AArch64::ANDSWrs - 27 |
| 16620 | {.AsmStrOffset: 126, .AliasCondStart: 100, .NumOperands: 4, .NumConds: 4 }, |
| 16621 | {.AsmStrOffset: 137, .AliasCondStart: 104, .NumOperands: 4, .NumConds: 3 }, |
| 16622 | {.AsmStrOffset: 152, .AliasCondStart: 107, .NumOperands: 4, .NumConds: 4 }, |
| 16623 | // AArch64::ANDSXri - 30 |
| 16624 | {.AsmStrOffset: 168, .AliasCondStart: 111, .NumOperands: 3, .NumConds: 2 }, |
| 16625 | // AArch64::ANDSXrs - 31 |
| 16626 | {.AsmStrOffset: 126, .AliasCondStart: 113, .NumOperands: 4, .NumConds: 4 }, |
| 16627 | {.AsmStrOffset: 137, .AliasCondStart: 117, .NumOperands: 4, .NumConds: 3 }, |
| 16628 | {.AsmStrOffset: 152, .AliasCondStart: 120, .NumOperands: 4, .NumConds: 4 }, |
| 16629 | // AArch64::ANDS_PPzPP - 34 |
| 16630 | {.AsmStrOffset: 181, .AliasCondStart: 124, .NumOperands: 4, .NumConds: 8 }, |
| 16631 | // AArch64::ANDWrs - 35 |
| 16632 | {.AsmStrOffset: 205, .AliasCondStart: 132, .NumOperands: 4, .NumConds: 4 }, |
| 16633 | // AArch64::ANDXrs - 36 |
| 16634 | {.AsmStrOffset: 205, .AliasCondStart: 136, .NumOperands: 4, .NumConds: 4 }, |
| 16635 | // AArch64::AND_PPzPP - 37 |
| 16636 | {.AsmStrOffset: 220, .AliasCondStart: 140, .NumOperands: 4, .NumConds: 8 }, |
| 16637 | // AArch64::AND_ZI - 38 |
| 16638 | {.AsmStrOffset: 243, .AliasCondStart: 148, .NumOperands: 3, .NumConds: 7 }, |
| 16639 | {.AsmStrOffset: 264, .AliasCondStart: 155, .NumOperands: 3, .NumConds: 7 }, |
| 16640 | {.AsmStrOffset: 285, .AliasCondStart: 162, .NumOperands: 3, .NumConds: 7 }, |
| 16641 | // AArch64::AUTIA1716 - 41 |
| 16642 | {.AsmStrOffset: 306, .AliasCondStart: 169, .NumOperands: 0, .NumConds: 3 }, |
| 16643 | // AArch64::AUTIASP - 42 |
| 16644 | {.AsmStrOffset: 316, .AliasCondStart: 172, .NumOperands: 0, .NumConds: 3 }, |
| 16645 | // AArch64::AUTIAZ - 43 |
| 16646 | {.AsmStrOffset: 324, .AliasCondStart: 175, .NumOperands: 0, .NumConds: 3 }, |
| 16647 | // AArch64::AUTIB1716 - 44 |
| 16648 | {.AsmStrOffset: 331, .AliasCondStart: 178, .NumOperands: 0, .NumConds: 3 }, |
| 16649 | // AArch64::AUTIBSP - 45 |
| 16650 | {.AsmStrOffset: 341, .AliasCondStart: 181, .NumOperands: 0, .NumConds: 3 }, |
| 16651 | // AArch64::AUTIBZ - 46 |
| 16652 | {.AsmStrOffset: 349, .AliasCondStart: 184, .NumOperands: 0, .NumConds: 3 }, |
| 16653 | // AArch64::BICSWrs - 47 |
| 16654 | {.AsmStrOffset: 356, .AliasCondStart: 187, .NumOperands: 4, .NumConds: 4 }, |
| 16655 | // AArch64::BICSXrs - 48 |
| 16656 | {.AsmStrOffset: 356, .AliasCondStart: 191, .NumOperands: 4, .NumConds: 4 }, |
| 16657 | // AArch64::BICWrs - 49 |
| 16658 | {.AsmStrOffset: 372, .AliasCondStart: 195, .NumOperands: 4, .NumConds: 4 }, |
| 16659 | // AArch64::BICXrs - 50 |
| 16660 | {.AsmStrOffset: 372, .AliasCondStart: 199, .NumOperands: 4, .NumConds: 4 }, |
| 16661 | // AArch64::CHKFEAT - 51 |
| 16662 | {.AsmStrOffset: 387, .AliasCondStart: 203, .NumOperands: 0, .NumConds: 3 }, |
| 16663 | // AArch64::CLREX - 52 |
| 16664 | {.AsmStrOffset: 399, .AliasCondStart: 206, .NumOperands: 1, .NumConds: 1 }, |
| 16665 | // AArch64::CNTB_XPiI - 53 |
| 16666 | {.AsmStrOffset: 405, .AliasCondStart: 207, .NumOperands: 3, .NumConds: 7 }, |
| 16667 | {.AsmStrOffset: 413, .AliasCondStart: 214, .NumOperands: 3, .NumConds: 7 }, |
| 16668 | // AArch64::CNTD_XPiI - 55 |
| 16669 | {.AsmStrOffset: 427, .AliasCondStart: 221, .NumOperands: 3, .NumConds: 7 }, |
| 16670 | {.AsmStrOffset: 435, .AliasCondStart: 228, .NumOperands: 3, .NumConds: 7 }, |
| 16671 | // AArch64::CNTH_XPiI - 57 |
| 16672 | {.AsmStrOffset: 449, .AliasCondStart: 235, .NumOperands: 3, .NumConds: 7 }, |
| 16673 | {.AsmStrOffset: 457, .AliasCondStart: 242, .NumOperands: 3, .NumConds: 7 }, |
| 16674 | // AArch64::CNTW_XPiI - 59 |
| 16675 | {.AsmStrOffset: 471, .AliasCondStart: 249, .NumOperands: 3, .NumConds: 7 }, |
| 16676 | {.AsmStrOffset: 479, .AliasCondStart: 256, .NumOperands: 3, .NumConds: 7 }, |
| 16677 | // AArch64::CPY_ZPmI_B - 61 |
| 16678 | {.AsmStrOffset: 493, .AliasCondStart: 263, .NumOperands: 5, .NumConds: 7 }, |
| 16679 | // AArch64::CPY_ZPmI_D - 62 |
| 16680 | {.AsmStrOffset: 516, .AliasCondStart: 270, .NumOperands: 5, .NumConds: 7 }, |
| 16681 | // AArch64::CPY_ZPmI_H - 63 |
| 16682 | {.AsmStrOffset: 539, .AliasCondStart: 277, .NumOperands: 5, .NumConds: 7 }, |
| 16683 | // AArch64::CPY_ZPmI_S - 64 |
| 16684 | {.AsmStrOffset: 562, .AliasCondStart: 284, .NumOperands: 5, .NumConds: 7 }, |
| 16685 | // AArch64::CPY_ZPmR_B - 65 |
| 16686 | {.AsmStrOffset: 585, .AliasCondStart: 291, .NumOperands: 4, .NumConds: 8 }, |
| 16687 | // AArch64::CPY_ZPmR_D - 66 |
| 16688 | {.AsmStrOffset: 606, .AliasCondStart: 299, .NumOperands: 4, .NumConds: 8 }, |
| 16689 | // AArch64::CPY_ZPmR_H - 67 |
| 16690 | {.AsmStrOffset: 627, .AliasCondStart: 307, .NumOperands: 4, .NumConds: 8 }, |
| 16691 | // AArch64::CPY_ZPmR_S - 68 |
| 16692 | {.AsmStrOffset: 648, .AliasCondStart: 315, .NumOperands: 4, .NumConds: 8 }, |
| 16693 | // AArch64::CPY_ZPmV_B - 69 |
| 16694 | {.AsmStrOffset: 585, .AliasCondStart: 323, .NumOperands: 4, .NumConds: 8 }, |
| 16695 | // AArch64::CPY_ZPmV_D - 70 |
| 16696 | {.AsmStrOffset: 606, .AliasCondStart: 331, .NumOperands: 4, .NumConds: 8 }, |
| 16697 | // AArch64::CPY_ZPmV_H - 71 |
| 16698 | {.AsmStrOffset: 627, .AliasCondStart: 339, .NumOperands: 4, .NumConds: 8 }, |
| 16699 | // AArch64::CPY_ZPmV_S - 72 |
| 16700 | {.AsmStrOffset: 648, .AliasCondStart: 347, .NumOperands: 4, .NumConds: 8 }, |
| 16701 | // AArch64::CPY_ZPzI_B - 73 |
| 16702 | {.AsmStrOffset: 669, .AliasCondStart: 355, .NumOperands: 4, .NumConds: 6 }, |
| 16703 | // AArch64::CPY_ZPzI_D - 74 |
| 16704 | {.AsmStrOffset: 692, .AliasCondStart: 361, .NumOperands: 4, .NumConds: 6 }, |
| 16705 | // AArch64::CPY_ZPzI_H - 75 |
| 16706 | {.AsmStrOffset: 715, .AliasCondStart: 367, .NumOperands: 4, .NumConds: 6 }, |
| 16707 | // AArch64::CPY_ZPzI_S - 76 |
| 16708 | {.AsmStrOffset: 738, .AliasCondStart: 373, .NumOperands: 4, .NumConds: 6 }, |
| 16709 | // AArch64::CSINCWr - 77 |
| 16710 | {.AsmStrOffset: 761, .AliasCondStart: 379, .NumOperands: 4, .NumConds: 4 }, |
| 16711 | {.AsmStrOffset: 775, .AliasCondStart: 383, .NumOperands: 4, .NumConds: 4 }, |
| 16712 | // AArch64::CSINCXr - 79 |
| 16713 | {.AsmStrOffset: 761, .AliasCondStart: 387, .NumOperands: 4, .NumConds: 4 }, |
| 16714 | {.AsmStrOffset: 775, .AliasCondStart: 391, .NumOperands: 4, .NumConds: 4 }, |
| 16715 | // AArch64::CSINVWr - 81 |
| 16716 | {.AsmStrOffset: 793, .AliasCondStart: 395, .NumOperands: 4, .NumConds: 4 }, |
| 16717 | {.AsmStrOffset: 808, .AliasCondStart: 399, .NumOperands: 4, .NumConds: 4 }, |
| 16718 | // AArch64::CSINVXr - 83 |
| 16719 | {.AsmStrOffset: 793, .AliasCondStart: 403, .NumOperands: 4, .NumConds: 4 }, |
| 16720 | {.AsmStrOffset: 808, .AliasCondStart: 407, .NumOperands: 4, .NumConds: 4 }, |
| 16721 | // AArch64::CSNEGWr - 85 |
| 16722 | {.AsmStrOffset: 826, .AliasCondStart: 411, .NumOperands: 4, .NumConds: 4 }, |
| 16723 | // AArch64::CSNEGXr - 86 |
| 16724 | {.AsmStrOffset: 826, .AliasCondStart: 415, .NumOperands: 4, .NumConds: 4 }, |
| 16725 | // AArch64::DCPS1 - 87 |
| 16726 | {.AsmStrOffset: 844, .AliasCondStart: 419, .NumOperands: 1, .NumConds: 1 }, |
| 16727 | // AArch64::DCPS2 - 88 |
| 16728 | {.AsmStrOffset: 850, .AliasCondStart: 420, .NumOperands: 1, .NumConds: 1 }, |
| 16729 | // AArch64::DCPS3 - 89 |
| 16730 | {.AsmStrOffset: 856, .AliasCondStart: 421, .NumOperands: 1, .NumConds: 4 }, |
| 16731 | // AArch64::DECB_XPiI - 90 |
| 16732 | {.AsmStrOffset: 862, .AliasCondStart: 425, .NumOperands: 4, .NumConds: 8 }, |
| 16733 | {.AsmStrOffset: 870, .AliasCondStart: 433, .NumOperands: 4, .NumConds: 8 }, |
| 16734 | // AArch64::DECD_XPiI - 92 |
| 16735 | {.AsmStrOffset: 884, .AliasCondStart: 441, .NumOperands: 4, .NumConds: 8 }, |
| 16736 | {.AsmStrOffset: 892, .AliasCondStart: 449, .NumOperands: 4, .NumConds: 8 }, |
| 16737 | // AArch64::DECD_ZPiI - 94 |
| 16738 | {.AsmStrOffset: 906, .AliasCondStart: 457, .NumOperands: 4, .NumConds: 8 }, |
| 16739 | {.AsmStrOffset: 916, .AliasCondStart: 465, .NumOperands: 4, .NumConds: 8 }, |
| 16740 | // AArch64::DECH_XPiI - 96 |
| 16741 | {.AsmStrOffset: 932, .AliasCondStart: 473, .NumOperands: 4, .NumConds: 8 }, |
| 16742 | {.AsmStrOffset: 940, .AliasCondStart: 481, .NumOperands: 4, .NumConds: 8 }, |
| 16743 | // AArch64::DECH_ZPiI - 98 |
| 16744 | {.AsmStrOffset: 954, .AliasCondStart: 489, .NumOperands: 4, .NumConds: 8 }, |
| 16745 | {.AsmStrOffset: 964, .AliasCondStart: 497, .NumOperands: 4, .NumConds: 8 }, |
| 16746 | // AArch64::DECW_XPiI - 100 |
| 16747 | {.AsmStrOffset: 980, .AliasCondStart: 505, .NumOperands: 4, .NumConds: 8 }, |
| 16748 | {.AsmStrOffset: 988, .AliasCondStart: 513, .NumOperands: 4, .NumConds: 8 }, |
| 16749 | // AArch64::DECW_ZPiI - 102 |
| 16750 | {.AsmStrOffset: 1002, .AliasCondStart: 521, .NumOperands: 4, .NumConds: 8 }, |
| 16751 | {.AsmStrOffset: 1012, .AliasCondStart: 529, .NumOperands: 4, .NumConds: 8 }, |
| 16752 | // AArch64::DSB - 104 |
| 16753 | {.AsmStrOffset: 1028, .AliasCondStart: 537, .NumOperands: 1, .NumConds: 1 }, |
| 16754 | {.AsmStrOffset: 1033, .AliasCondStart: 538, .NumOperands: 1, .NumConds: 1 }, |
| 16755 | {.AsmStrOffset: 1039, .AliasCondStart: 539, .NumOperands: 1, .NumConds: 4 }, |
| 16756 | // AArch64::DUPM_ZI - 107 |
| 16757 | {.AsmStrOffset: 1043, .AliasCondStart: 543, .NumOperands: 2, .NumConds: 6 }, |
| 16758 | {.AsmStrOffset: 1058, .AliasCondStart: 549, .NumOperands: 2, .NumConds: 6 }, |
| 16759 | {.AsmStrOffset: 1073, .AliasCondStart: 555, .NumOperands: 2, .NumConds: 6 }, |
| 16760 | {.AsmStrOffset: 1088, .AliasCondStart: 561, .NumOperands: 2, .NumConds: 6 }, |
| 16761 | {.AsmStrOffset: 1104, .AliasCondStart: 567, .NumOperands: 2, .NumConds: 6 }, |
| 16762 | {.AsmStrOffset: 1120, .AliasCondStart: 573, .NumOperands: 2, .NumConds: 6 }, |
| 16763 | // AArch64::DUP_ZI_B - 113 |
| 16764 | {.AsmStrOffset: 1136, .AliasCondStart: 579, .NumOperands: 3, .NumConds: 5 }, |
| 16765 | // AArch64::DUP_ZI_D - 114 |
| 16766 | {.AsmStrOffset: 1151, .AliasCondStart: 584, .NumOperands: 3, .NumConds: 5 }, |
| 16767 | {.AsmStrOffset: 1166, .AliasCondStart: 589, .NumOperands: 3, .NumConds: 7 }, |
| 16768 | // AArch64::DUP_ZI_H - 116 |
| 16769 | {.AsmStrOffset: 1182, .AliasCondStart: 596, .NumOperands: 3, .NumConds: 5 }, |
| 16770 | {.AsmStrOffset: 1197, .AliasCondStart: 601, .NumOperands: 3, .NumConds: 7 }, |
| 16771 | // AArch64::DUP_ZI_S - 118 |
| 16772 | {.AsmStrOffset: 1213, .AliasCondStart: 608, .NumOperands: 3, .NumConds: 5 }, |
| 16773 | {.AsmStrOffset: 1228, .AliasCondStart: 613, .NumOperands: 3, .NumConds: 7 }, |
| 16774 | // AArch64::DUP_ZR_B - 120 |
| 16775 | {.AsmStrOffset: 1244, .AliasCondStart: 620, .NumOperands: 2, .NumConds: 6 }, |
| 16776 | // AArch64::DUP_ZR_D - 121 |
| 16777 | {.AsmStrOffset: 1257, .AliasCondStart: 626, .NumOperands: 2, .NumConds: 6 }, |
| 16778 | // AArch64::DUP_ZR_H - 122 |
| 16779 | {.AsmStrOffset: 1270, .AliasCondStart: 632, .NumOperands: 2, .NumConds: 6 }, |
| 16780 | // AArch64::DUP_ZR_S - 123 |
| 16781 | {.AsmStrOffset: 1283, .AliasCondStart: 638, .NumOperands: 2, .NumConds: 6 }, |
| 16782 | // AArch64::DUP_ZZI_B - 124 |
| 16783 | {.AsmStrOffset: 1296, .AliasCondStart: 644, .NumOperands: 3, .NumConds: 7 }, |
| 16784 | {.AsmStrOffset: 1311, .AliasCondStart: 651, .NumOperands: 3, .NumConds: 6 }, |
| 16785 | // AArch64::DUP_ZZI_D - 126 |
| 16786 | {.AsmStrOffset: 1330, .AliasCondStart: 657, .NumOperands: 3, .NumConds: 7 }, |
| 16787 | {.AsmStrOffset: 1345, .AliasCondStart: 664, .NumOperands: 3, .NumConds: 6 }, |
| 16788 | // AArch64::DUP_ZZI_H - 128 |
| 16789 | {.AsmStrOffset: 1364, .AliasCondStart: 670, .NumOperands: 3, .NumConds: 7 }, |
| 16790 | {.AsmStrOffset: 1379, .AliasCondStart: 677, .NumOperands: 3, .NumConds: 6 }, |
| 16791 | // AArch64::DUP_ZZI_Q - 130 |
| 16792 | {.AsmStrOffset: 1398, .AliasCondStart: 683, .NumOperands: 3, .NumConds: 7 }, |
| 16793 | {.AsmStrOffset: 1413, .AliasCondStart: 690, .NumOperands: 3, .NumConds: 6 }, |
| 16794 | // AArch64::DUP_ZZI_S - 132 |
| 16795 | {.AsmStrOffset: 1432, .AliasCondStart: 696, .NumOperands: 3, .NumConds: 7 }, |
| 16796 | {.AsmStrOffset: 1447, .AliasCondStart: 703, .NumOperands: 3, .NumConds: 6 }, |
| 16797 | // AArch64::EONWrs - 134 |
| 16798 | {.AsmStrOffset: 1466, .AliasCondStart: 709, .NumOperands: 4, .NumConds: 4 }, |
| 16799 | // AArch64::EONXrs - 135 |
| 16800 | {.AsmStrOffset: 1466, .AliasCondStart: 713, .NumOperands: 4, .NumConds: 4 }, |
| 16801 | // AArch64::EORS_PPzPP - 136 |
| 16802 | {.AsmStrOffset: 1481, .AliasCondStart: 717, .NumOperands: 4, .NumConds: 8 }, |
| 16803 | // AArch64::EORWrs - 137 |
| 16804 | {.AsmStrOffset: 1505, .AliasCondStart: 725, .NumOperands: 4, .NumConds: 4 }, |
| 16805 | // AArch64::EORXrs - 138 |
| 16806 | {.AsmStrOffset: 1505, .AliasCondStart: 729, .NumOperands: 4, .NumConds: 4 }, |
| 16807 | // AArch64::EOR_PPzPP - 139 |
| 16808 | {.AsmStrOffset: 1520, .AliasCondStart: 733, .NumOperands: 4, .NumConds: 8 }, |
| 16809 | // AArch64::EOR_ZI - 140 |
| 16810 | {.AsmStrOffset: 1543, .AliasCondStart: 741, .NumOperands: 3, .NumConds: 7 }, |
| 16811 | {.AsmStrOffset: 1564, .AliasCondStart: 748, .NumOperands: 3, .NumConds: 7 }, |
| 16812 | {.AsmStrOffset: 1585, .AliasCondStart: 755, .NumOperands: 3, .NumConds: 7 }, |
| 16813 | // AArch64::EXTRACT_ZPMXI_H_B - 143 |
| 16814 | {.AsmStrOffset: 1606, .AliasCondStart: 762, .NumOperands: 6, .NumConds: 8 }, |
| 16815 | // AArch64::EXTRACT_ZPMXI_H_D - 144 |
| 16816 | {.AsmStrOffset: 1639, .AliasCondStart: 770, .NumOperands: 6, .NumConds: 8 }, |
| 16817 | // AArch64::EXTRACT_ZPMXI_H_H - 145 |
| 16818 | {.AsmStrOffset: 1672, .AliasCondStart: 778, .NumOperands: 6, .NumConds: 8 }, |
| 16819 | // AArch64::EXTRACT_ZPMXI_H_Q - 146 |
| 16820 | {.AsmStrOffset: 1705, .AliasCondStart: 786, .NumOperands: 6, .NumConds: 8 }, |
| 16821 | // AArch64::EXTRACT_ZPMXI_H_S - 147 |
| 16822 | {.AsmStrOffset: 1738, .AliasCondStart: 794, .NumOperands: 6, .NumConds: 8 }, |
| 16823 | // AArch64::EXTRACT_ZPMXI_V_B - 148 |
| 16824 | {.AsmStrOffset: 1771, .AliasCondStart: 802, .NumOperands: 6, .NumConds: 8 }, |
| 16825 | // AArch64::EXTRACT_ZPMXI_V_D - 149 |
| 16826 | {.AsmStrOffset: 1804, .AliasCondStart: 810, .NumOperands: 6, .NumConds: 8 }, |
| 16827 | // AArch64::EXTRACT_ZPMXI_V_H - 150 |
| 16828 | {.AsmStrOffset: 1837, .AliasCondStart: 818, .NumOperands: 6, .NumConds: 8 }, |
| 16829 | // AArch64::EXTRACT_ZPMXI_V_Q - 151 |
| 16830 | {.AsmStrOffset: 1870, .AliasCondStart: 826, .NumOperands: 6, .NumConds: 8 }, |
| 16831 | // AArch64::EXTRACT_ZPMXI_V_S - 152 |
| 16832 | {.AsmStrOffset: 1903, .AliasCondStart: 834, .NumOperands: 6, .NumConds: 8 }, |
| 16833 | // AArch64::EXTRWrri - 153 |
| 16834 | {.AsmStrOffset: 1936, .AliasCondStart: 842, .NumOperands: 4, .NumConds: 4 }, |
| 16835 | // AArch64::EXTRXrri - 154 |
| 16836 | {.AsmStrOffset: 1936, .AliasCondStart: 846, .NumOperands: 4, .NumConds: 3 }, |
| 16837 | // AArch64::FCPY_ZPmI_D - 155 |
| 16838 | {.AsmStrOffset: 1951, .AliasCondStart: 849, .NumOperands: 4, .NumConds: 7 }, |
| 16839 | // AArch64::FCPY_ZPmI_H - 156 |
| 16840 | {.AsmStrOffset: 1975, .AliasCondStart: 856, .NumOperands: 4, .NumConds: 7 }, |
| 16841 | // AArch64::FCPY_ZPmI_S - 157 |
| 16842 | {.AsmStrOffset: 1999, .AliasCondStart: 863, .NumOperands: 4, .NumConds: 7 }, |
| 16843 | // AArch64::FDUP_ZI_D - 158 |
| 16844 | {.AsmStrOffset: 2023, .AliasCondStart: 870, .NumOperands: 2, .NumConds: 5 }, |
| 16845 | // AArch64::FDUP_ZI_H - 159 |
| 16846 | {.AsmStrOffset: 2039, .AliasCondStart: 875, .NumOperands: 2, .NumConds: 5 }, |
| 16847 | // AArch64::FDUP_ZI_S - 160 |
| 16848 | {.AsmStrOffset: 2055, .AliasCondStart: 880, .NumOperands: 2, .NumConds: 5 }, |
| 16849 | // AArch64::GCSPOPM - 161 |
| 16850 | {.AsmStrOffset: 2071, .AliasCondStart: 885, .NumOperands: 2, .NumConds: 4 }, |
| 16851 | // AArch64::GLD1B_D_IMM - 162 |
| 16852 | {.AsmStrOffset: 2079, .AliasCondStart: 889, .NumOperands: 4, .NumConds: 7 }, |
| 16853 | // AArch64::GLD1B_S_IMM - 163 |
| 16854 | {.AsmStrOffset: 2105, .AliasCondStart: 896, .NumOperands: 4, .NumConds: 7 }, |
| 16855 | // AArch64::GLD1D_IMM - 164 |
| 16856 | {.AsmStrOffset: 2131, .AliasCondStart: 903, .NumOperands: 4, .NumConds: 7 }, |
| 16857 | // AArch64::GLD1H_D_IMM - 165 |
| 16858 | {.AsmStrOffset: 2157, .AliasCondStart: 910, .NumOperands: 4, .NumConds: 7 }, |
| 16859 | // AArch64::GLD1H_S_IMM - 166 |
| 16860 | {.AsmStrOffset: 2183, .AliasCondStart: 917, .NumOperands: 4, .NumConds: 7 }, |
| 16861 | // AArch64::GLD1Q - 167 |
| 16862 | {.AsmStrOffset: 2209, .AliasCondStart: 924, .NumOperands: 4, .NumConds: 7 }, |
| 16863 | // AArch64::GLD1SB_D_IMM - 168 |
| 16864 | {.AsmStrOffset: 2235, .AliasCondStart: 931, .NumOperands: 4, .NumConds: 7 }, |
| 16865 | // AArch64::GLD1SB_S_IMM - 169 |
| 16866 | {.AsmStrOffset: 2262, .AliasCondStart: 938, .NumOperands: 4, .NumConds: 7 }, |
| 16867 | // AArch64::GLD1SH_D_IMM - 170 |
| 16868 | {.AsmStrOffset: 2289, .AliasCondStart: 945, .NumOperands: 4, .NumConds: 7 }, |
| 16869 | // AArch64::GLD1SH_S_IMM - 171 |
| 16870 | {.AsmStrOffset: 2316, .AliasCondStart: 952, .NumOperands: 4, .NumConds: 7 }, |
| 16871 | // AArch64::GLD1SW_D_IMM - 172 |
| 16872 | {.AsmStrOffset: 2343, .AliasCondStart: 959, .NumOperands: 4, .NumConds: 7 }, |
| 16873 | // AArch64::GLD1W_D_IMM - 173 |
| 16874 | {.AsmStrOffset: 2370, .AliasCondStart: 966, .NumOperands: 4, .NumConds: 7 }, |
| 16875 | // AArch64::GLD1W_IMM - 174 |
| 16876 | {.AsmStrOffset: 2396, .AliasCondStart: 973, .NumOperands: 4, .NumConds: 7 }, |
| 16877 | // AArch64::GLDFF1B_D_IMM - 175 |
| 16878 | {.AsmStrOffset: 2422, .AliasCondStart: 980, .NumOperands: 4, .NumConds: 7 }, |
| 16879 | // AArch64::GLDFF1B_S_IMM - 176 |
| 16880 | {.AsmStrOffset: 2450, .AliasCondStart: 987, .NumOperands: 4, .NumConds: 7 }, |
| 16881 | // AArch64::GLDFF1D_IMM - 177 |
| 16882 | {.AsmStrOffset: 2478, .AliasCondStart: 994, .NumOperands: 4, .NumConds: 7 }, |
| 16883 | // AArch64::GLDFF1H_D_IMM - 178 |
| 16884 | {.AsmStrOffset: 2506, .AliasCondStart: 1001, .NumOperands: 4, .NumConds: 7 }, |
| 16885 | // AArch64::GLDFF1H_S_IMM - 179 |
| 16886 | {.AsmStrOffset: 2534, .AliasCondStart: 1008, .NumOperands: 4, .NumConds: 7 }, |
| 16887 | // AArch64::GLDFF1SB_D_IMM - 180 |
| 16888 | {.AsmStrOffset: 2562, .AliasCondStart: 1015, .NumOperands: 4, .NumConds: 7 }, |
| 16889 | // AArch64::GLDFF1SB_S_IMM - 181 |
| 16890 | {.AsmStrOffset: 2591, .AliasCondStart: 1022, .NumOperands: 4, .NumConds: 7 }, |
| 16891 | // AArch64::GLDFF1SH_D_IMM - 182 |
| 16892 | {.AsmStrOffset: 2620, .AliasCondStart: 1029, .NumOperands: 4, .NumConds: 7 }, |
| 16893 | // AArch64::GLDFF1SH_S_IMM - 183 |
| 16894 | {.AsmStrOffset: 2649, .AliasCondStart: 1036, .NumOperands: 4, .NumConds: 7 }, |
| 16895 | // AArch64::GLDFF1SW_D_IMM - 184 |
| 16896 | {.AsmStrOffset: 2678, .AliasCondStart: 1043, .NumOperands: 4, .NumConds: 7 }, |
| 16897 | // AArch64::GLDFF1W_D_IMM - 185 |
| 16898 | {.AsmStrOffset: 2707, .AliasCondStart: 1050, .NumOperands: 4, .NumConds: 7 }, |
| 16899 | // AArch64::GLDFF1W_IMM - 186 |
| 16900 | {.AsmStrOffset: 2735, .AliasCondStart: 1057, .NumOperands: 4, .NumConds: 7 }, |
| 16901 | // AArch64::HINT - 187 |
| 16902 | {.AsmStrOffset: 2763, .AliasCondStart: 1064, .NumOperands: 1, .NumConds: 1 }, |
| 16903 | {.AsmStrOffset: 2769, .AliasCondStart: 1065, .NumOperands: 1, .NumConds: 1 }, |
| 16904 | {.AsmStrOffset: 2773, .AliasCondStart: 1066, .NumOperands: 1, .NumConds: 1 }, |
| 16905 | {.AsmStrOffset: 2777, .AliasCondStart: 1067, .NumOperands: 1, .NumConds: 1 }, |
| 16906 | {.AsmStrOffset: 2781, .AliasCondStart: 1068, .NumOperands: 1, .NumConds: 1 }, |
| 16907 | {.AsmStrOffset: 2786, .AliasCondStart: 1069, .NumOperands: 1, .NumConds: 1 }, |
| 16908 | {.AsmStrOffset: 2790, .AliasCondStart: 1070, .NumOperands: 1, .NumConds: 4 }, |
| 16909 | {.AsmStrOffset: 2794, .AliasCondStart: 1074, .NumOperands: 1, .NumConds: 1 }, |
| 16910 | {.AsmStrOffset: 2799, .AliasCondStart: 1075, .NumOperands: 1, .NumConds: 1 }, |
| 16911 | {.AsmStrOffset: 2810, .AliasCondStart: 1076, .NumOperands: 1, .NumConds: 1 }, |
| 16912 | {.AsmStrOffset: 2821, .AliasCondStart: 1077, .NumOperands: 1, .NumConds: 1 }, |
| 16913 | {.AsmStrOffset: 2826, .AliasCondStart: 1078, .NumOperands: 1, .NumConds: 1 }, |
| 16914 | {.AsmStrOffset: 2834, .AliasCondStart: 1079, .NumOperands: 1, .NumConds: 1 }, |
| 16915 | {.AsmStrOffset: 2840, .AliasCondStart: 1080, .NumOperands: 1, .NumConds: 1 }, |
| 16916 | {.AsmStrOffset: 2845, .AliasCondStart: 1081, .NumOperands: 1, .NumConds: 1 }, |
| 16917 | {.AsmStrOffset: 2859, .AliasCondStart: 1082, .NumOperands: 1, .NumConds: 1 }, |
| 16918 | {.AsmStrOffset: 2865, .AliasCondStart: 1083, .NumOperands: 1, .NumConds: 4 }, |
| 16919 | {.AsmStrOffset: 2871, .AliasCondStart: 1087, .NumOperands: 1, .NumConds: 4 }, |
| 16920 | {.AsmStrOffset: 2875, .AliasCondStart: 1091, .NumOperands: 1, .NumConds: 4 }, |
| 16921 | {.AsmStrOffset: 2881, .AliasCondStart: 1095, .NumOperands: 1, .NumConds: 4 }, |
| 16922 | {.AsmStrOffset: 2887, .AliasCondStart: 1099, .NumOperands: 1, .NumConds: 4 }, |
| 16923 | {.AsmStrOffset: 2894, .AliasCondStart: 1103, .NumOperands: 1, .NumConds: 4 }, |
| 16924 | {.AsmStrOffset: 2904, .AliasCondStart: 1107, .NumOperands: 1, .NumConds: 4 }, |
| 16925 | {.AsmStrOffset: 2914, .AliasCondStart: 1111, .NumOperands: 1, .NumConds: 4 }, |
| 16926 | {.AsmStrOffset: 2925, .AliasCondStart: 1115, .NumOperands: 1, .NumConds: 4 }, |
| 16927 | // AArch64::INCB_XPiI - 212 |
| 16928 | {.AsmStrOffset: 2932, .AliasCondStart: 1119, .NumOperands: 4, .NumConds: 8 }, |
| 16929 | {.AsmStrOffset: 2940, .AliasCondStart: 1127, .NumOperands: 4, .NumConds: 8 }, |
| 16930 | // AArch64::INCD_XPiI - 214 |
| 16931 | {.AsmStrOffset: 2954, .AliasCondStart: 1135, .NumOperands: 4, .NumConds: 8 }, |
| 16932 | {.AsmStrOffset: 2962, .AliasCondStart: 1143, .NumOperands: 4, .NumConds: 8 }, |
| 16933 | // AArch64::INCD_ZPiI - 216 |
| 16934 | {.AsmStrOffset: 2976, .AliasCondStart: 1151, .NumOperands: 4, .NumConds: 8 }, |
| 16935 | {.AsmStrOffset: 2986, .AliasCondStart: 1159, .NumOperands: 4, .NumConds: 8 }, |
| 16936 | // AArch64::INCH_XPiI - 218 |
| 16937 | {.AsmStrOffset: 3002, .AliasCondStart: 1167, .NumOperands: 4, .NumConds: 8 }, |
| 16938 | {.AsmStrOffset: 3010, .AliasCondStart: 1175, .NumOperands: 4, .NumConds: 8 }, |
| 16939 | // AArch64::INCH_ZPiI - 220 |
| 16940 | {.AsmStrOffset: 3024, .AliasCondStart: 1183, .NumOperands: 4, .NumConds: 8 }, |
| 16941 | {.AsmStrOffset: 3034, .AliasCondStart: 1191, .NumOperands: 4, .NumConds: 8 }, |
| 16942 | // AArch64::INCW_XPiI - 222 |
| 16943 | {.AsmStrOffset: 3050, .AliasCondStart: 1199, .NumOperands: 4, .NumConds: 8 }, |
| 16944 | {.AsmStrOffset: 3058, .AliasCondStart: 1207, .NumOperands: 4, .NumConds: 8 }, |
| 16945 | // AArch64::INCW_ZPiI - 224 |
| 16946 | {.AsmStrOffset: 3072, .AliasCondStart: 1215, .NumOperands: 4, .NumConds: 8 }, |
| 16947 | {.AsmStrOffset: 3082, .AliasCondStart: 1223, .NumOperands: 4, .NumConds: 8 }, |
| 16948 | // AArch64::INSERT_MXIPZ_H_B - 226 |
| 16949 | {.AsmStrOffset: 3098, .AliasCondStart: 1231, .NumOperands: 6, .NumConds: 9 }, |
| 16950 | // AArch64::INSERT_MXIPZ_H_D - 227 |
| 16951 | {.AsmStrOffset: 3131, .AliasCondStart: 1240, .NumOperands: 6, .NumConds: 9 }, |
| 16952 | // AArch64::INSERT_MXIPZ_H_H - 228 |
| 16953 | {.AsmStrOffset: 3164, .AliasCondStart: 1249, .NumOperands: 6, .NumConds: 9 }, |
| 16954 | // AArch64::INSERT_MXIPZ_H_Q - 229 |
| 16955 | {.AsmStrOffset: 3197, .AliasCondStart: 1258, .NumOperands: 6, .NumConds: 9 }, |
| 16956 | // AArch64::INSERT_MXIPZ_H_S - 230 |
| 16957 | {.AsmStrOffset: 3230, .AliasCondStart: 1267, .NumOperands: 6, .NumConds: 9 }, |
| 16958 | // AArch64::INSERT_MXIPZ_V_B - 231 |
| 16959 | {.AsmStrOffset: 3263, .AliasCondStart: 1276, .NumOperands: 6, .NumConds: 9 }, |
| 16960 | // AArch64::INSERT_MXIPZ_V_D - 232 |
| 16961 | {.AsmStrOffset: 3296, .AliasCondStart: 1285, .NumOperands: 6, .NumConds: 9 }, |
| 16962 | // AArch64::INSERT_MXIPZ_V_H - 233 |
| 16963 | {.AsmStrOffset: 3329, .AliasCondStart: 1294, .NumOperands: 6, .NumConds: 9 }, |
| 16964 | // AArch64::INSERT_MXIPZ_V_Q - 234 |
| 16965 | {.AsmStrOffset: 3362, .AliasCondStart: 1303, .NumOperands: 6, .NumConds: 9 }, |
| 16966 | // AArch64::INSERT_MXIPZ_V_S - 235 |
| 16967 | {.AsmStrOffset: 3395, .AliasCondStart: 1312, .NumOperands: 6, .NumConds: 9 }, |
| 16968 | // AArch64::INSvi16gpr - 236 |
| 16969 | {.AsmStrOffset: 3428, .AliasCondStart: 1321, .NumOperands: 4, .NumConds: 7 }, |
| 16970 | // AArch64::INSvi16lane - 237 |
| 16971 | {.AsmStrOffset: 3447, .AliasCondStart: 1328, .NumOperands: 5, .NumConds: 7 }, |
| 16972 | // AArch64::INSvi32gpr - 238 |
| 16973 | {.AsmStrOffset: 3474, .AliasCondStart: 1335, .NumOperands: 4, .NumConds: 7 }, |
| 16974 | // AArch64::INSvi32lane - 239 |
| 16975 | {.AsmStrOffset: 3493, .AliasCondStart: 1342, .NumOperands: 5, .NumConds: 7 }, |
| 16976 | // AArch64::INSvi64gpr - 240 |
| 16977 | {.AsmStrOffset: 3520, .AliasCondStart: 1349, .NumOperands: 4, .NumConds: 7 }, |
| 16978 | // AArch64::INSvi64lane - 241 |
| 16979 | {.AsmStrOffset: 3539, .AliasCondStart: 1356, .NumOperands: 5, .NumConds: 7 }, |
| 16980 | // AArch64::INSvi8gpr - 242 |
| 16981 | {.AsmStrOffset: 3566, .AliasCondStart: 1363, .NumOperands: 4, .NumConds: 7 }, |
| 16982 | // AArch64::INSvi8lane - 243 |
| 16983 | {.AsmStrOffset: 3585, .AliasCondStart: 1370, .NumOperands: 5, .NumConds: 7 }, |
| 16984 | // AArch64::IRG - 244 |
| 16985 | {.AsmStrOffset: 3612, .AliasCondStart: 1377, .NumOperands: 3, .NumConds: 6 }, |
| 16986 | // AArch64::ISB - 245 |
| 16987 | {.AsmStrOffset: 3623, .AliasCondStart: 1383, .NumOperands: 1, .NumConds: 1 }, |
| 16988 | // AArch64::LD1B_2Z_IMM - 246 |
| 16989 | {.AsmStrOffset: 3627, .AliasCondStart: 1384, .NumOperands: 4, .NumConds: 8 }, |
| 16990 | // AArch64::LD1B_2Z_STRIDED_IMM - 247 |
| 16991 | {.AsmStrOffset: 3651, .AliasCondStart: 1392, .NumOperands: 4, .NumConds: 7 }, |
| 16992 | // AArch64::LD1B_4Z_IMM - 248 |
| 16993 | {.AsmStrOffset: 3627, .AliasCondStart: 1399, .NumOperands: 4, .NumConds: 8 }, |
| 16994 | // AArch64::LD1B_4Z_STRIDED_IMM - 249 |
| 16995 | {.AsmStrOffset: 3675, .AliasCondStart: 1407, .NumOperands: 4, .NumConds: 7 }, |
| 16996 | // AArch64::LD1B_D_IMM - 250 |
| 16997 | {.AsmStrOffset: 3699, .AliasCondStart: 1414, .NumOperands: 4, .NumConds: 8 }, |
| 16998 | // AArch64::LD1B_H_IMM - 251 |
| 16999 | {.AsmStrOffset: 3723, .AliasCondStart: 1422, .NumOperands: 4, .NumConds: 8 }, |
| 17000 | // AArch64::LD1B_IMM - 252 |
| 17001 | {.AsmStrOffset: 3747, .AliasCondStart: 1430, .NumOperands: 4, .NumConds: 8 }, |
| 17002 | // AArch64::LD1B_S_IMM - 253 |
| 17003 | {.AsmStrOffset: 3771, .AliasCondStart: 1438, .NumOperands: 4, .NumConds: 8 }, |
| 17004 | // AArch64::LD1D_2Z_IMM - 254 |
| 17005 | {.AsmStrOffset: 3795, .AliasCondStart: 1446, .NumOperands: 4, .NumConds: 8 }, |
| 17006 | // AArch64::LD1D_2Z_STRIDED_IMM - 255 |
| 17007 | {.AsmStrOffset: 3819, .AliasCondStart: 1454, .NumOperands: 4, .NumConds: 7 }, |
| 17008 | // AArch64::LD1D_4Z_IMM - 256 |
| 17009 | {.AsmStrOffset: 3795, .AliasCondStart: 1461, .NumOperands: 4, .NumConds: 8 }, |
| 17010 | // AArch64::LD1D_4Z_STRIDED_IMM - 257 |
| 17011 | {.AsmStrOffset: 3819, .AliasCondStart: 1469, .NumOperands: 4, .NumConds: 7 }, |
| 17012 | // AArch64::LD1D_IMM - 258 |
| 17013 | {.AsmStrOffset: 3843, .AliasCondStart: 1476, .NumOperands: 4, .NumConds: 8 }, |
| 17014 | // AArch64::LD1D_Q_IMM - 259 |
| 17015 | {.AsmStrOffset: 3867, .AliasCondStart: 1484, .NumOperands: 4, .NumConds: 7 }, |
| 17016 | // AArch64::LD1Fourv16b_POST - 260 |
| 17017 | {.AsmStrOffset: 3891, .AliasCondStart: 1491, .NumOperands: 4, .NumConds: 7 }, |
| 17018 | // AArch64::LD1Fourv1d_POST - 261 |
| 17019 | {.AsmStrOffset: 3911, .AliasCondStart: 1498, .NumOperands: 4, .NumConds: 7 }, |
| 17020 | // AArch64::LD1Fourv2d_POST - 262 |
| 17021 | {.AsmStrOffset: 3931, .AliasCondStart: 1505, .NumOperands: 4, .NumConds: 7 }, |
| 17022 | // AArch64::LD1Fourv2s_POST - 263 |
| 17023 | {.AsmStrOffset: 3951, .AliasCondStart: 1512, .NumOperands: 4, .NumConds: 7 }, |
| 17024 | // AArch64::LD1Fourv4h_POST - 264 |
| 17025 | {.AsmStrOffset: 3971, .AliasCondStart: 1519, .NumOperands: 4, .NumConds: 7 }, |
| 17026 | // AArch64::LD1Fourv4s_POST - 265 |
| 17027 | {.AsmStrOffset: 3991, .AliasCondStart: 1526, .NumOperands: 4, .NumConds: 7 }, |
| 17028 | // AArch64::LD1Fourv8b_POST - 266 |
| 17029 | {.AsmStrOffset: 4011, .AliasCondStart: 1533, .NumOperands: 4, .NumConds: 7 }, |
| 17030 | // AArch64::LD1Fourv8h_POST - 267 |
| 17031 | {.AsmStrOffset: 4031, .AliasCondStart: 1540, .NumOperands: 4, .NumConds: 7 }, |
| 17032 | // AArch64::LD1H_2Z_IMM - 268 |
| 17033 | {.AsmStrOffset: 4051, .AliasCondStart: 1547, .NumOperands: 4, .NumConds: 8 }, |
| 17034 | // AArch64::LD1H_2Z_STRIDED_IMM - 269 |
| 17035 | {.AsmStrOffset: 4075, .AliasCondStart: 1555, .NumOperands: 4, .NumConds: 7 }, |
| 17036 | // AArch64::LD1H_4Z_IMM - 270 |
| 17037 | {.AsmStrOffset: 4051, .AliasCondStart: 1562, .NumOperands: 4, .NumConds: 8 }, |
| 17038 | // AArch64::LD1H_4Z_STRIDED_IMM - 271 |
| 17039 | {.AsmStrOffset: 4099, .AliasCondStart: 1570, .NumOperands: 4, .NumConds: 7 }, |
| 17040 | // AArch64::LD1H_D_IMM - 272 |
| 17041 | {.AsmStrOffset: 4123, .AliasCondStart: 1577, .NumOperands: 4, .NumConds: 8 }, |
| 17042 | // AArch64::LD1H_IMM - 273 |
| 17043 | {.AsmStrOffset: 4147, .AliasCondStart: 1585, .NumOperands: 4, .NumConds: 8 }, |
| 17044 | // AArch64::LD1H_S_IMM - 274 |
| 17045 | {.AsmStrOffset: 4171, .AliasCondStart: 1593, .NumOperands: 4, .NumConds: 8 }, |
| 17046 | // AArch64::LD1Onev16b_POST - 275 |
| 17047 | {.AsmStrOffset: 4195, .AliasCondStart: 1601, .NumOperands: 4, .NumConds: 7 }, |
| 17048 | // AArch64::LD1Onev1d_POST - 276 |
| 17049 | {.AsmStrOffset: 4215, .AliasCondStart: 1608, .NumOperands: 4, .NumConds: 7 }, |
| 17050 | // AArch64::LD1Onev2d_POST - 277 |
| 17051 | {.AsmStrOffset: 4234, .AliasCondStart: 1615, .NumOperands: 4, .NumConds: 7 }, |
| 17052 | // AArch64::LD1Onev2s_POST - 278 |
| 17053 | {.AsmStrOffset: 4254, .AliasCondStart: 1622, .NumOperands: 4, .NumConds: 7 }, |
| 17054 | // AArch64::LD1Onev4h_POST - 279 |
| 17055 | {.AsmStrOffset: 4273, .AliasCondStart: 1629, .NumOperands: 4, .NumConds: 7 }, |
| 17056 | // AArch64::LD1Onev4s_POST - 280 |
| 17057 | {.AsmStrOffset: 4292, .AliasCondStart: 1636, .NumOperands: 4, .NumConds: 7 }, |
| 17058 | // AArch64::LD1Onev8b_POST - 281 |
| 17059 | {.AsmStrOffset: 4312, .AliasCondStart: 1643, .NumOperands: 4, .NumConds: 7 }, |
| 17060 | // AArch64::LD1Onev8h_POST - 282 |
| 17061 | {.AsmStrOffset: 4331, .AliasCondStart: 1650, .NumOperands: 4, .NumConds: 7 }, |
| 17062 | // AArch64::LD1RB_D_IMM - 283 |
| 17063 | {.AsmStrOffset: 4351, .AliasCondStart: 1657, .NumOperands: 4, .NumConds: 8 }, |
| 17064 | // AArch64::LD1RB_H_IMM - 284 |
| 17065 | {.AsmStrOffset: 4376, .AliasCondStart: 1665, .NumOperands: 4, .NumConds: 8 }, |
| 17066 | // AArch64::LD1RB_IMM - 285 |
| 17067 | {.AsmStrOffset: 4401, .AliasCondStart: 1673, .NumOperands: 4, .NumConds: 8 }, |
| 17068 | // AArch64::LD1RB_S_IMM - 286 |
| 17069 | {.AsmStrOffset: 4426, .AliasCondStart: 1681, .NumOperands: 4, .NumConds: 8 }, |
| 17070 | // AArch64::LD1RD_IMM - 287 |
| 17071 | {.AsmStrOffset: 4451, .AliasCondStart: 1689, .NumOperands: 4, .NumConds: 8 }, |
| 17072 | // AArch64::LD1RH_D_IMM - 288 |
| 17073 | {.AsmStrOffset: 4476, .AliasCondStart: 1697, .NumOperands: 4, .NumConds: 8 }, |
| 17074 | // AArch64::LD1RH_IMM - 289 |
| 17075 | {.AsmStrOffset: 4501, .AliasCondStart: 1705, .NumOperands: 4, .NumConds: 8 }, |
| 17076 | // AArch64::LD1RH_S_IMM - 290 |
| 17077 | {.AsmStrOffset: 4526, .AliasCondStart: 1713, .NumOperands: 4, .NumConds: 8 }, |
| 17078 | // AArch64::LD1RO_B_IMM - 291 |
| 17079 | {.AsmStrOffset: 4551, .AliasCondStart: 1721, .NumOperands: 4, .NumConds: 10 }, |
| 17080 | // AArch64::LD1RO_D_IMM - 292 |
| 17081 | {.AsmStrOffset: 4577, .AliasCondStart: 1731, .NumOperands: 4, .NumConds: 10 }, |
| 17082 | // AArch64::LD1RO_H_IMM - 293 |
| 17083 | {.AsmStrOffset: 4603, .AliasCondStart: 1741, .NumOperands: 4, .NumConds: 10 }, |
| 17084 | // AArch64::LD1RO_W_IMM - 294 |
| 17085 | {.AsmStrOffset: 4629, .AliasCondStart: 1751, .NumOperands: 4, .NumConds: 10 }, |
| 17086 | // AArch64::LD1RQ_B_IMM - 295 |
| 17087 | {.AsmStrOffset: 4655, .AliasCondStart: 1761, .NumOperands: 4, .NumConds: 8 }, |
| 17088 | // AArch64::LD1RQ_D_IMM - 296 |
| 17089 | {.AsmStrOffset: 4681, .AliasCondStart: 1769, .NumOperands: 4, .NumConds: 8 }, |
| 17090 | // AArch64::LD1RQ_H_IMM - 297 |
| 17091 | {.AsmStrOffset: 4707, .AliasCondStart: 1777, .NumOperands: 4, .NumConds: 8 }, |
| 17092 | // AArch64::LD1RQ_W_IMM - 298 |
| 17093 | {.AsmStrOffset: 4733, .AliasCondStart: 1785, .NumOperands: 4, .NumConds: 8 }, |
| 17094 | // AArch64::LD1RSB_D_IMM - 299 |
| 17095 | {.AsmStrOffset: 4759, .AliasCondStart: 1793, .NumOperands: 4, .NumConds: 8 }, |
| 17096 | // AArch64::LD1RSB_H_IMM - 300 |
| 17097 | {.AsmStrOffset: 4785, .AliasCondStart: 1801, .NumOperands: 4, .NumConds: 8 }, |
| 17098 | // AArch64::LD1RSB_S_IMM - 301 |
| 17099 | {.AsmStrOffset: 4811, .AliasCondStart: 1809, .NumOperands: 4, .NumConds: 8 }, |
| 17100 | // AArch64::LD1RSH_D_IMM - 302 |
| 17101 | {.AsmStrOffset: 4837, .AliasCondStart: 1817, .NumOperands: 4, .NumConds: 8 }, |
| 17102 | // AArch64::LD1RSH_S_IMM - 303 |
| 17103 | {.AsmStrOffset: 4863, .AliasCondStart: 1825, .NumOperands: 4, .NumConds: 8 }, |
| 17104 | // AArch64::LD1RSW_IMM - 304 |
| 17105 | {.AsmStrOffset: 4889, .AliasCondStart: 1833, .NumOperands: 4, .NumConds: 8 }, |
| 17106 | // AArch64::LD1RW_D_IMM - 305 |
| 17107 | {.AsmStrOffset: 4915, .AliasCondStart: 1841, .NumOperands: 4, .NumConds: 8 }, |
| 17108 | // AArch64::LD1RW_IMM - 306 |
| 17109 | {.AsmStrOffset: 4940, .AliasCondStart: 1849, .NumOperands: 4, .NumConds: 8 }, |
| 17110 | // AArch64::LD1Rv16b_POST - 307 |
| 17111 | {.AsmStrOffset: 4965, .AliasCondStart: 1857, .NumOperands: 4, .NumConds: 7 }, |
| 17112 | // AArch64::LD1Rv1d_POST - 308 |
| 17113 | {.AsmStrOffset: 4985, .AliasCondStart: 1864, .NumOperands: 4, .NumConds: 7 }, |
| 17114 | // AArch64::LD1Rv2d_POST - 309 |
| 17115 | {.AsmStrOffset: 5005, .AliasCondStart: 1871, .NumOperands: 4, .NumConds: 7 }, |
| 17116 | // AArch64::LD1Rv2s_POST - 310 |
| 17117 | {.AsmStrOffset: 5025, .AliasCondStart: 1878, .NumOperands: 4, .NumConds: 7 }, |
| 17118 | // AArch64::LD1Rv4h_POST - 311 |
| 17119 | {.AsmStrOffset: 5045, .AliasCondStart: 1885, .NumOperands: 4, .NumConds: 7 }, |
| 17120 | // AArch64::LD1Rv4s_POST - 312 |
| 17121 | {.AsmStrOffset: 5065, .AliasCondStart: 1892, .NumOperands: 4, .NumConds: 7 }, |
| 17122 | // AArch64::LD1Rv8b_POST - 313 |
| 17123 | {.AsmStrOffset: 5085, .AliasCondStart: 1899, .NumOperands: 4, .NumConds: 7 }, |
| 17124 | // AArch64::LD1Rv8h_POST - 314 |
| 17125 | {.AsmStrOffset: 5105, .AliasCondStart: 1906, .NumOperands: 4, .NumConds: 7 }, |
| 17126 | // AArch64::LD1SB_D_IMM - 315 |
| 17127 | {.AsmStrOffset: 5125, .AliasCondStart: 1913, .NumOperands: 4, .NumConds: 8 }, |
| 17128 | // AArch64::LD1SB_H_IMM - 316 |
| 17129 | {.AsmStrOffset: 5150, .AliasCondStart: 1921, .NumOperands: 4, .NumConds: 8 }, |
| 17130 | // AArch64::LD1SB_S_IMM - 317 |
| 17131 | {.AsmStrOffset: 5175, .AliasCondStart: 1929, .NumOperands: 4, .NumConds: 8 }, |
| 17132 | // AArch64::LD1SH_D_IMM - 318 |
| 17133 | {.AsmStrOffset: 5200, .AliasCondStart: 1937, .NumOperands: 4, .NumConds: 8 }, |
| 17134 | // AArch64::LD1SH_S_IMM - 319 |
| 17135 | {.AsmStrOffset: 5225, .AliasCondStart: 1945, .NumOperands: 4, .NumConds: 8 }, |
| 17136 | // AArch64::LD1SW_D_IMM - 320 |
| 17137 | {.AsmStrOffset: 5250, .AliasCondStart: 1953, .NumOperands: 4, .NumConds: 8 }, |
| 17138 | // AArch64::LD1Threev16b_POST - 321 |
| 17139 | {.AsmStrOffset: 5275, .AliasCondStart: 1961, .NumOperands: 4, .NumConds: 7 }, |
| 17140 | // AArch64::LD1Threev1d_POST - 322 |
| 17141 | {.AsmStrOffset: 5295, .AliasCondStart: 1968, .NumOperands: 4, .NumConds: 7 }, |
| 17142 | // AArch64::LD1Threev2d_POST - 323 |
| 17143 | {.AsmStrOffset: 5315, .AliasCondStart: 1975, .NumOperands: 4, .NumConds: 7 }, |
| 17144 | // AArch64::LD1Threev2s_POST - 324 |
| 17145 | {.AsmStrOffset: 5335, .AliasCondStart: 1982, .NumOperands: 4, .NumConds: 7 }, |
| 17146 | // AArch64::LD1Threev4h_POST - 325 |
| 17147 | {.AsmStrOffset: 5355, .AliasCondStart: 1989, .NumOperands: 4, .NumConds: 7 }, |
| 17148 | // AArch64::LD1Threev4s_POST - 326 |
| 17149 | {.AsmStrOffset: 5375, .AliasCondStart: 1996, .NumOperands: 4, .NumConds: 7 }, |
| 17150 | // AArch64::LD1Threev8b_POST - 327 |
| 17151 | {.AsmStrOffset: 5395, .AliasCondStart: 2003, .NumOperands: 4, .NumConds: 7 }, |
| 17152 | // AArch64::LD1Threev8h_POST - 328 |
| 17153 | {.AsmStrOffset: 5415, .AliasCondStart: 2010, .NumOperands: 4, .NumConds: 7 }, |
| 17154 | // AArch64::LD1Twov16b_POST - 329 |
| 17155 | {.AsmStrOffset: 5435, .AliasCondStart: 2017, .NumOperands: 4, .NumConds: 7 }, |
| 17156 | // AArch64::LD1Twov1d_POST - 330 |
| 17157 | {.AsmStrOffset: 5455, .AliasCondStart: 2024, .NumOperands: 4, .NumConds: 7 }, |
| 17158 | // AArch64::LD1Twov2d_POST - 331 |
| 17159 | {.AsmStrOffset: 5475, .AliasCondStart: 2031, .NumOperands: 4, .NumConds: 7 }, |
| 17160 | // AArch64::LD1Twov2s_POST - 332 |
| 17161 | {.AsmStrOffset: 5495, .AliasCondStart: 2038, .NumOperands: 4, .NumConds: 7 }, |
| 17162 | // AArch64::LD1Twov4h_POST - 333 |
| 17163 | {.AsmStrOffset: 5515, .AliasCondStart: 2045, .NumOperands: 4, .NumConds: 7 }, |
| 17164 | // AArch64::LD1Twov4s_POST - 334 |
| 17165 | {.AsmStrOffset: 5535, .AliasCondStart: 2052, .NumOperands: 4, .NumConds: 7 }, |
| 17166 | // AArch64::LD1Twov8b_POST - 335 |
| 17167 | {.AsmStrOffset: 5555, .AliasCondStart: 2059, .NumOperands: 4, .NumConds: 7 }, |
| 17168 | // AArch64::LD1Twov8h_POST - 336 |
| 17169 | {.AsmStrOffset: 5575, .AliasCondStart: 2066, .NumOperands: 4, .NumConds: 7 }, |
| 17170 | // AArch64::LD1W_2Z_IMM - 337 |
| 17171 | {.AsmStrOffset: 5595, .AliasCondStart: 2073, .NumOperands: 4, .NumConds: 8 }, |
| 17172 | // AArch64::LD1W_2Z_STRIDED_IMM - 338 |
| 17173 | {.AsmStrOffset: 5619, .AliasCondStart: 2081, .NumOperands: 4, .NumConds: 7 }, |
| 17174 | // AArch64::LD1W_4Z_IMM - 339 |
| 17175 | {.AsmStrOffset: 5595, .AliasCondStart: 2088, .NumOperands: 4, .NumConds: 8 }, |
| 17176 | // AArch64::LD1W_4Z_STRIDED_IMM - 340 |
| 17177 | {.AsmStrOffset: 5619, .AliasCondStart: 2096, .NumOperands: 4, .NumConds: 7 }, |
| 17178 | // AArch64::LD1W_D_IMM - 341 |
| 17179 | {.AsmStrOffset: 5643, .AliasCondStart: 2103, .NumOperands: 4, .NumConds: 8 }, |
| 17180 | // AArch64::LD1W_IMM - 342 |
| 17181 | {.AsmStrOffset: 5667, .AliasCondStart: 2111, .NumOperands: 4, .NumConds: 8 }, |
| 17182 | // AArch64::LD1W_Q_IMM - 343 |
| 17183 | {.AsmStrOffset: 5691, .AliasCondStart: 2119, .NumOperands: 4, .NumConds: 7 }, |
| 17184 | // AArch64::LD1_MXIPXX_H_B - 344 |
| 17185 | {.AsmStrOffset: 5715, .AliasCondStart: 2126, .NumOperands: 6, .NumConds: 9 }, |
| 17186 | // AArch64::LD1_MXIPXX_H_D - 345 |
| 17187 | {.AsmStrOffset: 5751, .AliasCondStart: 2135, .NumOperands: 6, .NumConds: 9 }, |
| 17188 | // AArch64::LD1_MXIPXX_H_H - 346 |
| 17189 | {.AsmStrOffset: 5787, .AliasCondStart: 2144, .NumOperands: 6, .NumConds: 9 }, |
| 17190 | // AArch64::LD1_MXIPXX_H_Q - 347 |
| 17191 | {.AsmStrOffset: 5823, .AliasCondStart: 2153, .NumOperands: 6, .NumConds: 9 }, |
| 17192 | // AArch64::LD1_MXIPXX_H_S - 348 |
| 17193 | {.AsmStrOffset: 5859, .AliasCondStart: 2162, .NumOperands: 6, .NumConds: 9 }, |
| 17194 | // AArch64::LD1_MXIPXX_V_B - 349 |
| 17195 | {.AsmStrOffset: 5895, .AliasCondStart: 2171, .NumOperands: 6, .NumConds: 9 }, |
| 17196 | // AArch64::LD1_MXIPXX_V_D - 350 |
| 17197 | {.AsmStrOffset: 5931, .AliasCondStart: 2180, .NumOperands: 6, .NumConds: 9 }, |
| 17198 | // AArch64::LD1_MXIPXX_V_H - 351 |
| 17199 | {.AsmStrOffset: 5967, .AliasCondStart: 2189, .NumOperands: 6, .NumConds: 9 }, |
| 17200 | // AArch64::LD1_MXIPXX_V_Q - 352 |
| 17201 | {.AsmStrOffset: 6003, .AliasCondStart: 2198, .NumOperands: 6, .NumConds: 9 }, |
| 17202 | // AArch64::LD1_MXIPXX_V_S - 353 |
| 17203 | {.AsmStrOffset: 6039, .AliasCondStart: 2207, .NumOperands: 6, .NumConds: 9 }, |
| 17204 | // AArch64::LD1i16_POST - 354 |
| 17205 | {.AsmStrOffset: 6075, .AliasCondStart: 2216, .NumOperands: 6, .NumConds: 9 }, |
| 17206 | // AArch64::LD1i32_POST - 355 |
| 17207 | {.AsmStrOffset: 6098, .AliasCondStart: 2225, .NumOperands: 6, .NumConds: 9 }, |
| 17208 | // AArch64::LD1i64_POST - 356 |
| 17209 | {.AsmStrOffset: 6121, .AliasCondStart: 2234, .NumOperands: 6, .NumConds: 9 }, |
| 17210 | // AArch64::LD1i8_POST - 357 |
| 17211 | {.AsmStrOffset: 6144, .AliasCondStart: 2243, .NumOperands: 6, .NumConds: 9 }, |
| 17212 | // AArch64::LD2B_IMM - 358 |
| 17213 | {.AsmStrOffset: 6167, .AliasCondStart: 2252, .NumOperands: 4, .NumConds: 8 }, |
| 17214 | // AArch64::LD2D_IMM - 359 |
| 17215 | {.AsmStrOffset: 6191, .AliasCondStart: 2260, .NumOperands: 4, .NumConds: 8 }, |
| 17216 | // AArch64::LD2H_IMM - 360 |
| 17217 | {.AsmStrOffset: 6215, .AliasCondStart: 2268, .NumOperands: 4, .NumConds: 8 }, |
| 17218 | // AArch64::LD2Q_IMM - 361 |
| 17219 | {.AsmStrOffset: 6239, .AliasCondStart: 2276, .NumOperands: 4, .NumConds: 8 }, |
| 17220 | // AArch64::LD2Rv16b_POST - 362 |
| 17221 | {.AsmStrOffset: 6263, .AliasCondStart: 2284, .NumOperands: 4, .NumConds: 7 }, |
| 17222 | // AArch64::LD2Rv1d_POST - 363 |
| 17223 | {.AsmStrOffset: 6283, .AliasCondStart: 2291, .NumOperands: 4, .NumConds: 7 }, |
| 17224 | // AArch64::LD2Rv2d_POST - 364 |
| 17225 | {.AsmStrOffset: 6304, .AliasCondStart: 2298, .NumOperands: 4, .NumConds: 7 }, |
| 17226 | // AArch64::LD2Rv2s_POST - 365 |
| 17227 | {.AsmStrOffset: 6325, .AliasCondStart: 2305, .NumOperands: 4, .NumConds: 7 }, |
| 17228 | // AArch64::LD2Rv4h_POST - 366 |
| 17229 | {.AsmStrOffset: 6345, .AliasCondStart: 2312, .NumOperands: 4, .NumConds: 7 }, |
| 17230 | // AArch64::LD2Rv4s_POST - 367 |
| 17231 | {.AsmStrOffset: 6365, .AliasCondStart: 2319, .NumOperands: 4, .NumConds: 7 }, |
| 17232 | // AArch64::LD2Rv8b_POST - 368 |
| 17233 | {.AsmStrOffset: 6385, .AliasCondStart: 2326, .NumOperands: 4, .NumConds: 7 }, |
| 17234 | // AArch64::LD2Rv8h_POST - 369 |
| 17235 | {.AsmStrOffset: 6405, .AliasCondStart: 2333, .NumOperands: 4, .NumConds: 7 }, |
| 17236 | // AArch64::LD2Twov16b_POST - 370 |
| 17237 | {.AsmStrOffset: 6425, .AliasCondStart: 2340, .NumOperands: 4, .NumConds: 7 }, |
| 17238 | // AArch64::LD2Twov2d_POST - 371 |
| 17239 | {.AsmStrOffset: 6445, .AliasCondStart: 2347, .NumOperands: 4, .NumConds: 7 }, |
| 17240 | // AArch64::LD2Twov2s_POST - 372 |
| 17241 | {.AsmStrOffset: 6465, .AliasCondStart: 2354, .NumOperands: 4, .NumConds: 7 }, |
| 17242 | // AArch64::LD2Twov4h_POST - 373 |
| 17243 | {.AsmStrOffset: 6485, .AliasCondStart: 2361, .NumOperands: 4, .NumConds: 7 }, |
| 17244 | // AArch64::LD2Twov4s_POST - 374 |
| 17245 | {.AsmStrOffset: 6505, .AliasCondStart: 2368, .NumOperands: 4, .NumConds: 7 }, |
| 17246 | // AArch64::LD2Twov8b_POST - 375 |
| 17247 | {.AsmStrOffset: 6525, .AliasCondStart: 2375, .NumOperands: 4, .NumConds: 7 }, |
| 17248 | // AArch64::LD2Twov8h_POST - 376 |
| 17249 | {.AsmStrOffset: 6545, .AliasCondStart: 2382, .NumOperands: 4, .NumConds: 7 }, |
| 17250 | // AArch64::LD2W_IMM - 377 |
| 17251 | {.AsmStrOffset: 6565, .AliasCondStart: 2389, .NumOperands: 4, .NumConds: 8 }, |
| 17252 | // AArch64::LD2i16_POST - 378 |
| 17253 | {.AsmStrOffset: 6589, .AliasCondStart: 2397, .NumOperands: 6, .NumConds: 9 }, |
| 17254 | // AArch64::LD2i32_POST - 379 |
| 17255 | {.AsmStrOffset: 6612, .AliasCondStart: 2406, .NumOperands: 6, .NumConds: 9 }, |
| 17256 | // AArch64::LD2i64_POST - 380 |
| 17257 | {.AsmStrOffset: 6635, .AliasCondStart: 2415, .NumOperands: 6, .NumConds: 9 }, |
| 17258 | // AArch64::LD2i8_POST - 381 |
| 17259 | {.AsmStrOffset: 6659, .AliasCondStart: 2424, .NumOperands: 6, .NumConds: 9 }, |
| 17260 | // AArch64::LD3B_IMM - 382 |
| 17261 | {.AsmStrOffset: 6682, .AliasCondStart: 2433, .NumOperands: 4, .NumConds: 8 }, |
| 17262 | // AArch64::LD3D_IMM - 383 |
| 17263 | {.AsmStrOffset: 6706, .AliasCondStart: 2441, .NumOperands: 4, .NumConds: 8 }, |
| 17264 | // AArch64::LD3H_IMM - 384 |
| 17265 | {.AsmStrOffset: 6730, .AliasCondStart: 2449, .NumOperands: 4, .NumConds: 8 }, |
| 17266 | // AArch64::LD3Q_IMM - 385 |
| 17267 | {.AsmStrOffset: 6754, .AliasCondStart: 2457, .NumOperands: 4, .NumConds: 8 }, |
| 17268 | // AArch64::LD3Rv16b_POST - 386 |
| 17269 | {.AsmStrOffset: 6778, .AliasCondStart: 2465, .NumOperands: 4, .NumConds: 7 }, |
| 17270 | // AArch64::LD3Rv1d_POST - 387 |
| 17271 | {.AsmStrOffset: 6798, .AliasCondStart: 2472, .NumOperands: 4, .NumConds: 7 }, |
| 17272 | // AArch64::LD3Rv2d_POST - 388 |
| 17273 | {.AsmStrOffset: 6819, .AliasCondStart: 2479, .NumOperands: 4, .NumConds: 7 }, |
| 17274 | // AArch64::LD3Rv2s_POST - 389 |
| 17275 | {.AsmStrOffset: 6840, .AliasCondStart: 2486, .NumOperands: 4, .NumConds: 7 }, |
| 17276 | // AArch64::LD3Rv4h_POST - 390 |
| 17277 | {.AsmStrOffset: 6861, .AliasCondStart: 2493, .NumOperands: 4, .NumConds: 7 }, |
| 17278 | // AArch64::LD3Rv4s_POST - 391 |
| 17279 | {.AsmStrOffset: 6881, .AliasCondStart: 2500, .NumOperands: 4, .NumConds: 7 }, |
| 17280 | // AArch64::LD3Rv8b_POST - 392 |
| 17281 | {.AsmStrOffset: 6902, .AliasCondStart: 2507, .NumOperands: 4, .NumConds: 7 }, |
| 17282 | // AArch64::LD3Rv8h_POST - 393 |
| 17283 | {.AsmStrOffset: 6922, .AliasCondStart: 2514, .NumOperands: 4, .NumConds: 7 }, |
| 17284 | // AArch64::LD3Threev16b_POST - 394 |
| 17285 | {.AsmStrOffset: 6942, .AliasCondStart: 2521, .NumOperands: 4, .NumConds: 7 }, |
| 17286 | // AArch64::LD3Threev2d_POST - 395 |
| 17287 | {.AsmStrOffset: 6962, .AliasCondStart: 2528, .NumOperands: 4, .NumConds: 7 }, |
| 17288 | // AArch64::LD3Threev2s_POST - 396 |
| 17289 | {.AsmStrOffset: 6982, .AliasCondStart: 2535, .NumOperands: 4, .NumConds: 7 }, |
| 17290 | // AArch64::LD3Threev4h_POST - 397 |
| 17291 | {.AsmStrOffset: 7002, .AliasCondStart: 2542, .NumOperands: 4, .NumConds: 7 }, |
| 17292 | // AArch64::LD3Threev4s_POST - 398 |
| 17293 | {.AsmStrOffset: 7022, .AliasCondStart: 2549, .NumOperands: 4, .NumConds: 7 }, |
| 17294 | // AArch64::LD3Threev8b_POST - 399 |
| 17295 | {.AsmStrOffset: 7042, .AliasCondStart: 2556, .NumOperands: 4, .NumConds: 7 }, |
| 17296 | // AArch64::LD3Threev8h_POST - 400 |
| 17297 | {.AsmStrOffset: 7062, .AliasCondStart: 2563, .NumOperands: 4, .NumConds: 7 }, |
| 17298 | // AArch64::LD3W_IMM - 401 |
| 17299 | {.AsmStrOffset: 7082, .AliasCondStart: 2570, .NumOperands: 4, .NumConds: 8 }, |
| 17300 | // AArch64::LD3i16_POST - 402 |
| 17301 | {.AsmStrOffset: 7106, .AliasCondStart: 2578, .NumOperands: 6, .NumConds: 9 }, |
| 17302 | // AArch64::LD3i32_POST - 403 |
| 17303 | {.AsmStrOffset: 7129, .AliasCondStart: 2587, .NumOperands: 6, .NumConds: 9 }, |
| 17304 | // AArch64::LD3i64_POST - 404 |
| 17305 | {.AsmStrOffset: 7153, .AliasCondStart: 2596, .NumOperands: 6, .NumConds: 9 }, |
| 17306 | // AArch64::LD3i8_POST - 405 |
| 17307 | {.AsmStrOffset: 7177, .AliasCondStart: 2605, .NumOperands: 6, .NumConds: 9 }, |
| 17308 | // AArch64::LD4B_IMM - 406 |
| 17309 | {.AsmStrOffset: 7200, .AliasCondStart: 2614, .NumOperands: 4, .NumConds: 8 }, |
| 17310 | // AArch64::LD4D_IMM - 407 |
| 17311 | {.AsmStrOffset: 7224, .AliasCondStart: 2622, .NumOperands: 4, .NumConds: 8 }, |
| 17312 | // AArch64::LD4Fourv16b_POST - 408 |
| 17313 | {.AsmStrOffset: 7248, .AliasCondStart: 2630, .NumOperands: 4, .NumConds: 7 }, |
| 17314 | // AArch64::LD4Fourv2d_POST - 409 |
| 17315 | {.AsmStrOffset: 7268, .AliasCondStart: 2637, .NumOperands: 4, .NumConds: 7 }, |
| 17316 | // AArch64::LD4Fourv2s_POST - 410 |
| 17317 | {.AsmStrOffset: 7288, .AliasCondStart: 2644, .NumOperands: 4, .NumConds: 7 }, |
| 17318 | // AArch64::LD4Fourv4h_POST - 411 |
| 17319 | {.AsmStrOffset: 7308, .AliasCondStart: 2651, .NumOperands: 4, .NumConds: 7 }, |
| 17320 | // AArch64::LD4Fourv4s_POST - 412 |
| 17321 | {.AsmStrOffset: 7328, .AliasCondStart: 2658, .NumOperands: 4, .NumConds: 7 }, |
| 17322 | // AArch64::LD4Fourv8b_POST - 413 |
| 17323 | {.AsmStrOffset: 7348, .AliasCondStart: 2665, .NumOperands: 4, .NumConds: 7 }, |
| 17324 | // AArch64::LD4Fourv8h_POST - 414 |
| 17325 | {.AsmStrOffset: 7368, .AliasCondStart: 2672, .NumOperands: 4, .NumConds: 7 }, |
| 17326 | // AArch64::LD4H_IMM - 415 |
| 17327 | {.AsmStrOffset: 7388, .AliasCondStart: 2679, .NumOperands: 4, .NumConds: 8 }, |
| 17328 | // AArch64::LD4Q_IMM - 416 |
| 17329 | {.AsmStrOffset: 7412, .AliasCondStart: 2687, .NumOperands: 4, .NumConds: 8 }, |
| 17330 | // AArch64::LD4Rv16b_POST - 417 |
| 17331 | {.AsmStrOffset: 7436, .AliasCondStart: 2695, .NumOperands: 4, .NumConds: 7 }, |
| 17332 | // AArch64::LD4Rv1d_POST - 418 |
| 17333 | {.AsmStrOffset: 7456, .AliasCondStart: 2702, .NumOperands: 4, .NumConds: 7 }, |
| 17334 | // AArch64::LD4Rv2d_POST - 419 |
| 17335 | {.AsmStrOffset: 7477, .AliasCondStart: 2709, .NumOperands: 4, .NumConds: 7 }, |
| 17336 | // AArch64::LD4Rv2s_POST - 420 |
| 17337 | {.AsmStrOffset: 7498, .AliasCondStart: 2716, .NumOperands: 4, .NumConds: 7 }, |
| 17338 | // AArch64::LD4Rv4h_POST - 421 |
| 17339 | {.AsmStrOffset: 7519, .AliasCondStart: 2723, .NumOperands: 4, .NumConds: 7 }, |
| 17340 | // AArch64::LD4Rv4s_POST - 422 |
| 17341 | {.AsmStrOffset: 7539, .AliasCondStart: 2730, .NumOperands: 4, .NumConds: 7 }, |
| 17342 | // AArch64::LD4Rv8b_POST - 423 |
| 17343 | {.AsmStrOffset: 7560, .AliasCondStart: 2737, .NumOperands: 4, .NumConds: 7 }, |
| 17344 | // AArch64::LD4Rv8h_POST - 424 |
| 17345 | {.AsmStrOffset: 7580, .AliasCondStart: 2744, .NumOperands: 4, .NumConds: 7 }, |
| 17346 | // AArch64::LD4W_IMM - 425 |
| 17347 | {.AsmStrOffset: 7600, .AliasCondStart: 2751, .NumOperands: 4, .NumConds: 8 }, |
| 17348 | // AArch64::LD4i16_POST - 426 |
| 17349 | {.AsmStrOffset: 7624, .AliasCondStart: 2759, .NumOperands: 6, .NumConds: 9 }, |
| 17350 | // AArch64::LD4i32_POST - 427 |
| 17351 | {.AsmStrOffset: 7647, .AliasCondStart: 2768, .NumOperands: 6, .NumConds: 9 }, |
| 17352 | // AArch64::LD4i64_POST - 428 |
| 17353 | {.AsmStrOffset: 7671, .AliasCondStart: 2777, .NumOperands: 6, .NumConds: 9 }, |
| 17354 | // AArch64::LD4i8_POST - 429 |
| 17355 | {.AsmStrOffset: 7695, .AliasCondStart: 2786, .NumOperands: 6, .NumConds: 9 }, |
| 17356 | // AArch64::LDADDB - 430 |
| 17357 | {.AsmStrOffset: 7718, .AliasCondStart: 2795, .NumOperands: 3, .NumConds: 6 }, |
| 17358 | // AArch64::LDADDH - 431 |
| 17359 | {.AsmStrOffset: 7734, .AliasCondStart: 2801, .NumOperands: 3, .NumConds: 6 }, |
| 17360 | // AArch64::LDADDLB - 432 |
| 17361 | {.AsmStrOffset: 7750, .AliasCondStart: 2807, .NumOperands: 3, .NumConds: 6 }, |
| 17362 | // AArch64::LDADDLH - 433 |
| 17363 | {.AsmStrOffset: 7767, .AliasCondStart: 2813, .NumOperands: 3, .NumConds: 6 }, |
| 17364 | // AArch64::LDADDLW - 434 |
| 17365 | {.AsmStrOffset: 7784, .AliasCondStart: 2819, .NumOperands: 3, .NumConds: 6 }, |
| 17366 | // AArch64::LDADDLX - 435 |
| 17367 | {.AsmStrOffset: 7784, .AliasCondStart: 2825, .NumOperands: 3, .NumConds: 6 }, |
| 17368 | // AArch64::LDADDW - 436 |
| 17369 | {.AsmStrOffset: 7800, .AliasCondStart: 2831, .NumOperands: 3, .NumConds: 6 }, |
| 17370 | // AArch64::LDADDX - 437 |
| 17371 | {.AsmStrOffset: 7800, .AliasCondStart: 2837, .NumOperands: 3, .NumConds: 6 }, |
| 17372 | // AArch64::LDAPPi - 438 |
| 17373 | {.AsmStrOffset: 7815, .AliasCondStart: 2843, .NumOperands: 3, .NumConds: 6 }, |
| 17374 | // AArch64::LDAPURBi - 439 |
| 17375 | {.AsmStrOffset: 7834, .AliasCondStart: 2849, .NumOperands: 3, .NumConds: 6 }, |
| 17376 | // AArch64::LDAPURHi - 440 |
| 17377 | {.AsmStrOffset: 7851, .AliasCondStart: 2855, .NumOperands: 3, .NumConds: 6 }, |
| 17378 | // AArch64::LDAPURSBWi - 441 |
| 17379 | {.AsmStrOffset: 7868, .AliasCondStart: 2861, .NumOperands: 3, .NumConds: 6 }, |
| 17380 | // AArch64::LDAPURSBXi - 442 |
| 17381 | {.AsmStrOffset: 7868, .AliasCondStart: 2867, .NumOperands: 3, .NumConds: 6 }, |
| 17382 | // AArch64::LDAPURSHWi - 443 |
| 17383 | {.AsmStrOffset: 7886, .AliasCondStart: 2873, .NumOperands: 3, .NumConds: 6 }, |
| 17384 | // AArch64::LDAPURSHXi - 444 |
| 17385 | {.AsmStrOffset: 7886, .AliasCondStart: 2879, .NumOperands: 3, .NumConds: 6 }, |
| 17386 | // AArch64::LDAPURSWi - 445 |
| 17387 | {.AsmStrOffset: 7904, .AliasCondStart: 2885, .NumOperands: 3, .NumConds: 6 }, |
| 17388 | // AArch64::LDAPURXi - 446 |
| 17389 | {.AsmStrOffset: 7922, .AliasCondStart: 2891, .NumOperands: 3, .NumConds: 6 }, |
| 17390 | // AArch64::LDAPURbi - 447 |
| 17391 | {.AsmStrOffset: 7922, .AliasCondStart: 2897, .NumOperands: 3, .NumConds: 9 }, |
| 17392 | // AArch64::LDAPURdi - 448 |
| 17393 | {.AsmStrOffset: 7922, .AliasCondStart: 2906, .NumOperands: 3, .NumConds: 9 }, |
| 17394 | // AArch64::LDAPURhi - 449 |
| 17395 | {.AsmStrOffset: 7922, .AliasCondStart: 2915, .NumOperands: 3, .NumConds: 9 }, |
| 17396 | // AArch64::LDAPURi - 450 |
| 17397 | {.AsmStrOffset: 7922, .AliasCondStart: 2924, .NumOperands: 3, .NumConds: 6 }, |
| 17398 | // AArch64::LDAPURqi - 451 |
| 17399 | {.AsmStrOffset: 7922, .AliasCondStart: 2930, .NumOperands: 3, .NumConds: 9 }, |
| 17400 | // AArch64::LDAPURsi - 452 |
| 17401 | {.AsmStrOffset: 7922, .AliasCondStart: 2939, .NumOperands: 3, .NumConds: 9 }, |
| 17402 | // AArch64::LDAPi - 453 |
| 17403 | {.AsmStrOffset: 7938, .AliasCondStart: 2948, .NumOperands: 3, .NumConds: 6 }, |
| 17404 | // AArch64::LDCLRB - 454 |
| 17405 | {.AsmStrOffset: 7956, .AliasCondStart: 2954, .NumOperands: 3, .NumConds: 6 }, |
| 17406 | // AArch64::LDCLRH - 455 |
| 17407 | {.AsmStrOffset: 7972, .AliasCondStart: 2960, .NumOperands: 3, .NumConds: 6 }, |
| 17408 | // AArch64::LDCLRLB - 456 |
| 17409 | {.AsmStrOffset: 7988, .AliasCondStart: 2966, .NumOperands: 3, .NumConds: 6 }, |
| 17410 | // AArch64::LDCLRLH - 457 |
| 17411 | {.AsmStrOffset: 8005, .AliasCondStart: 2972, .NumOperands: 3, .NumConds: 6 }, |
| 17412 | // AArch64::LDCLRLW - 458 |
| 17413 | {.AsmStrOffset: 8022, .AliasCondStart: 2978, .NumOperands: 3, .NumConds: 6 }, |
| 17414 | // AArch64::LDCLRLX - 459 |
| 17415 | {.AsmStrOffset: 8022, .AliasCondStart: 2984, .NumOperands: 3, .NumConds: 6 }, |
| 17416 | // AArch64::LDCLRW - 460 |
| 17417 | {.AsmStrOffset: 8038, .AliasCondStart: 2990, .NumOperands: 3, .NumConds: 6 }, |
| 17418 | // AArch64::LDCLRX - 461 |
| 17419 | {.AsmStrOffset: 8038, .AliasCondStart: 2996, .NumOperands: 3, .NumConds: 6 }, |
| 17420 | // AArch64::LDEORB - 462 |
| 17421 | {.AsmStrOffset: 8053, .AliasCondStart: 3002, .NumOperands: 3, .NumConds: 6 }, |
| 17422 | // AArch64::LDEORH - 463 |
| 17423 | {.AsmStrOffset: 8069, .AliasCondStart: 3008, .NumOperands: 3, .NumConds: 6 }, |
| 17424 | // AArch64::LDEORLB - 464 |
| 17425 | {.AsmStrOffset: 8085, .AliasCondStart: 3014, .NumOperands: 3, .NumConds: 6 }, |
| 17426 | // AArch64::LDEORLH - 465 |
| 17427 | {.AsmStrOffset: 8102, .AliasCondStart: 3020, .NumOperands: 3, .NumConds: 6 }, |
| 17428 | // AArch64::LDEORLW - 466 |
| 17429 | {.AsmStrOffset: 8119, .AliasCondStart: 3026, .NumOperands: 3, .NumConds: 6 }, |
| 17430 | // AArch64::LDEORLX - 467 |
| 17431 | {.AsmStrOffset: 8119, .AliasCondStart: 3032, .NumOperands: 3, .NumConds: 6 }, |
| 17432 | // AArch64::LDEORW - 468 |
| 17433 | {.AsmStrOffset: 8135, .AliasCondStart: 3038, .NumOperands: 3, .NumConds: 6 }, |
| 17434 | // AArch64::LDEORX - 469 |
| 17435 | {.AsmStrOffset: 8135, .AliasCondStart: 3044, .NumOperands: 3, .NumConds: 6 }, |
| 17436 | // AArch64::LDFF1B - 470 |
| 17437 | {.AsmStrOffset: 8150, .AliasCondStart: 3050, .NumOperands: 4, .NumConds: 7 }, |
| 17438 | // AArch64::LDFF1B_D - 471 |
| 17439 | {.AsmStrOffset: 8176, .AliasCondStart: 3057, .NumOperands: 4, .NumConds: 7 }, |
| 17440 | // AArch64::LDFF1B_H - 472 |
| 17441 | {.AsmStrOffset: 8202, .AliasCondStart: 3064, .NumOperands: 4, .NumConds: 7 }, |
| 17442 | // AArch64::LDFF1B_S - 473 |
| 17443 | {.AsmStrOffset: 8228, .AliasCondStart: 3071, .NumOperands: 4, .NumConds: 7 }, |
| 17444 | // AArch64::LDFF1D - 474 |
| 17445 | {.AsmStrOffset: 8254, .AliasCondStart: 3078, .NumOperands: 4, .NumConds: 7 }, |
| 17446 | // AArch64::LDFF1H - 475 |
| 17447 | {.AsmStrOffset: 8280, .AliasCondStart: 3085, .NumOperands: 4, .NumConds: 7 }, |
| 17448 | // AArch64::LDFF1H_D - 476 |
| 17449 | {.AsmStrOffset: 8306, .AliasCondStart: 3092, .NumOperands: 4, .NumConds: 7 }, |
| 17450 | // AArch64::LDFF1H_S - 477 |
| 17451 | {.AsmStrOffset: 8332, .AliasCondStart: 3099, .NumOperands: 4, .NumConds: 7 }, |
| 17452 | // AArch64::LDFF1SB_D - 478 |
| 17453 | {.AsmStrOffset: 8358, .AliasCondStart: 3106, .NumOperands: 4, .NumConds: 7 }, |
| 17454 | // AArch64::LDFF1SB_H - 479 |
| 17455 | {.AsmStrOffset: 8385, .AliasCondStart: 3113, .NumOperands: 4, .NumConds: 7 }, |
| 17456 | // AArch64::LDFF1SB_S - 480 |
| 17457 | {.AsmStrOffset: 8412, .AliasCondStart: 3120, .NumOperands: 4, .NumConds: 7 }, |
| 17458 | // AArch64::LDFF1SH_D - 481 |
| 17459 | {.AsmStrOffset: 8439, .AliasCondStart: 3127, .NumOperands: 4, .NumConds: 7 }, |
| 17460 | // AArch64::LDFF1SH_S - 482 |
| 17461 | {.AsmStrOffset: 8466, .AliasCondStart: 3134, .NumOperands: 4, .NumConds: 7 }, |
| 17462 | // AArch64::LDFF1SW_D - 483 |
| 17463 | {.AsmStrOffset: 8493, .AliasCondStart: 3141, .NumOperands: 4, .NumConds: 7 }, |
| 17464 | // AArch64::LDFF1W - 484 |
| 17465 | {.AsmStrOffset: 8520, .AliasCondStart: 3148, .NumOperands: 4, .NumConds: 7 }, |
| 17466 | // AArch64::LDFF1W_D - 485 |
| 17467 | {.AsmStrOffset: 8546, .AliasCondStart: 3155, .NumOperands: 4, .NumConds: 7 }, |
| 17468 | // AArch64::LDG - 486 |
| 17469 | {.AsmStrOffset: 8572, .AliasCondStart: 3162, .NumOperands: 4, .NumConds: 7 }, |
| 17470 | // AArch64::LDNF1B_D_IMM - 487 |
| 17471 | {.AsmStrOffset: 8585, .AliasCondStart: 3169, .NumOperands: 4, .NumConds: 7 }, |
| 17472 | // AArch64::LDNF1B_H_IMM - 488 |
| 17473 | {.AsmStrOffset: 8611, .AliasCondStart: 3176, .NumOperands: 4, .NumConds: 7 }, |
| 17474 | // AArch64::LDNF1B_IMM - 489 |
| 17475 | {.AsmStrOffset: 8637, .AliasCondStart: 3183, .NumOperands: 4, .NumConds: 7 }, |
| 17476 | // AArch64::LDNF1B_S_IMM - 490 |
| 17477 | {.AsmStrOffset: 8663, .AliasCondStart: 3190, .NumOperands: 4, .NumConds: 7 }, |
| 17478 | // AArch64::LDNF1D_IMM - 491 |
| 17479 | {.AsmStrOffset: 8689, .AliasCondStart: 3197, .NumOperands: 4, .NumConds: 7 }, |
| 17480 | // AArch64::LDNF1H_D_IMM - 492 |
| 17481 | {.AsmStrOffset: 8715, .AliasCondStart: 3204, .NumOperands: 4, .NumConds: 7 }, |
| 17482 | // AArch64::LDNF1H_IMM - 493 |
| 17483 | {.AsmStrOffset: 8741, .AliasCondStart: 3211, .NumOperands: 4, .NumConds: 7 }, |
| 17484 | // AArch64::LDNF1H_S_IMM - 494 |
| 17485 | {.AsmStrOffset: 8767, .AliasCondStart: 3218, .NumOperands: 4, .NumConds: 7 }, |
| 17486 | // AArch64::LDNF1SB_D_IMM - 495 |
| 17487 | {.AsmStrOffset: 8793, .AliasCondStart: 3225, .NumOperands: 4, .NumConds: 7 }, |
| 17488 | // AArch64::LDNF1SB_H_IMM - 496 |
| 17489 | {.AsmStrOffset: 8820, .AliasCondStart: 3232, .NumOperands: 4, .NumConds: 7 }, |
| 17490 | // AArch64::LDNF1SB_S_IMM - 497 |
| 17491 | {.AsmStrOffset: 8847, .AliasCondStart: 3239, .NumOperands: 4, .NumConds: 7 }, |
| 17492 | // AArch64::LDNF1SH_D_IMM - 498 |
| 17493 | {.AsmStrOffset: 8874, .AliasCondStart: 3246, .NumOperands: 4, .NumConds: 7 }, |
| 17494 | // AArch64::LDNF1SH_S_IMM - 499 |
| 17495 | {.AsmStrOffset: 8901, .AliasCondStart: 3253, .NumOperands: 4, .NumConds: 7 }, |
| 17496 | // AArch64::LDNF1SW_D_IMM - 500 |
| 17497 | {.AsmStrOffset: 8928, .AliasCondStart: 3260, .NumOperands: 4, .NumConds: 7 }, |
| 17498 | // AArch64::LDNF1W_D_IMM - 501 |
| 17499 | {.AsmStrOffset: 8955, .AliasCondStart: 3267, .NumOperands: 4, .NumConds: 7 }, |
| 17500 | // AArch64::LDNF1W_IMM - 502 |
| 17501 | {.AsmStrOffset: 8981, .AliasCondStart: 3274, .NumOperands: 4, .NumConds: 7 }, |
| 17502 | // AArch64::LDNPDi - 503 |
| 17503 | {.AsmStrOffset: 9007, .AliasCondStart: 3281, .NumOperands: 4, .NumConds: 7 }, |
| 17504 | // AArch64::LDNPQi - 504 |
| 17505 | {.AsmStrOffset: 9007, .AliasCondStart: 3288, .NumOperands: 4, .NumConds: 7 }, |
| 17506 | // AArch64::LDNPSi - 505 |
| 17507 | {.AsmStrOffset: 9007, .AliasCondStart: 3295, .NumOperands: 4, .NumConds: 7 }, |
| 17508 | // AArch64::LDNPWi - 506 |
| 17509 | {.AsmStrOffset: 9007, .AliasCondStart: 3302, .NumOperands: 4, .NumConds: 4 }, |
| 17510 | // AArch64::LDNPXi - 507 |
| 17511 | {.AsmStrOffset: 9007, .AliasCondStart: 3306, .NumOperands: 4, .NumConds: 4 }, |
| 17512 | // AArch64::LDNT1B_2Z_IMM - 508 |
| 17513 | {.AsmStrOffset: 9025, .AliasCondStart: 3310, .NumOperands: 4, .NumConds: 8 }, |
| 17514 | // AArch64::LDNT1B_2Z_STRIDED_IMM - 509 |
| 17515 | {.AsmStrOffset: 9051, .AliasCondStart: 3318, .NumOperands: 4, .NumConds: 7 }, |
| 17516 | // AArch64::LDNT1B_4Z_IMM - 510 |
| 17517 | {.AsmStrOffset: 9025, .AliasCondStart: 3325, .NumOperands: 4, .NumConds: 8 }, |
| 17518 | // AArch64::LDNT1B_4Z_STRIDED_IMM - 511 |
| 17519 | {.AsmStrOffset: 9077, .AliasCondStart: 3333, .NumOperands: 4, .NumConds: 7 }, |
| 17520 | // AArch64::LDNT1B_ZRI - 512 |
| 17521 | {.AsmStrOffset: 9103, .AliasCondStart: 3340, .NumOperands: 4, .NumConds: 8 }, |
| 17522 | // AArch64::LDNT1B_ZZR_D - 513 |
| 17523 | {.AsmStrOffset: 9129, .AliasCondStart: 3348, .NumOperands: 4, .NumConds: 7 }, |
| 17524 | // AArch64::LDNT1B_ZZR_S - 514 |
| 17525 | {.AsmStrOffset: 9157, .AliasCondStart: 3355, .NumOperands: 4, .NumConds: 7 }, |
| 17526 | // AArch64::LDNT1D_2Z_IMM - 515 |
| 17527 | {.AsmStrOffset: 9185, .AliasCondStart: 3362, .NumOperands: 4, .NumConds: 8 }, |
| 17528 | // AArch64::LDNT1D_2Z_STRIDED_IMM - 516 |
| 17529 | {.AsmStrOffset: 9211, .AliasCondStart: 3370, .NumOperands: 4, .NumConds: 7 }, |
| 17530 | // AArch64::LDNT1D_4Z_IMM - 517 |
| 17531 | {.AsmStrOffset: 9185, .AliasCondStart: 3377, .NumOperands: 4, .NumConds: 8 }, |
| 17532 | // AArch64::LDNT1D_4Z_STRIDED_IMM - 518 |
| 17533 | {.AsmStrOffset: 9211, .AliasCondStart: 3385, .NumOperands: 4, .NumConds: 7 }, |
| 17534 | // AArch64::LDNT1D_ZRI - 519 |
| 17535 | {.AsmStrOffset: 9237, .AliasCondStart: 3392, .NumOperands: 4, .NumConds: 8 }, |
| 17536 | // AArch64::LDNT1D_ZZR_D - 520 |
| 17537 | {.AsmStrOffset: 9263, .AliasCondStart: 3400, .NumOperands: 4, .NumConds: 7 }, |
| 17538 | // AArch64::LDNT1H_2Z_IMM - 521 |
| 17539 | {.AsmStrOffset: 9291, .AliasCondStart: 3407, .NumOperands: 4, .NumConds: 8 }, |
| 17540 | // AArch64::LDNT1H_2Z_STRIDED_IMM - 522 |
| 17541 | {.AsmStrOffset: 9317, .AliasCondStart: 3415, .NumOperands: 4, .NumConds: 7 }, |
| 17542 | // AArch64::LDNT1H_4Z_IMM - 523 |
| 17543 | {.AsmStrOffset: 9291, .AliasCondStart: 3422, .NumOperands: 4, .NumConds: 8 }, |
| 17544 | // AArch64::LDNT1H_4Z_STRIDED_IMM - 524 |
| 17545 | {.AsmStrOffset: 9343, .AliasCondStart: 3430, .NumOperands: 4, .NumConds: 7 }, |
| 17546 | // AArch64::LDNT1H_ZRI - 525 |
| 17547 | {.AsmStrOffset: 9369, .AliasCondStart: 3437, .NumOperands: 4, .NumConds: 8 }, |
| 17548 | // AArch64::LDNT1H_ZZR_D - 526 |
| 17549 | {.AsmStrOffset: 9395, .AliasCondStart: 3445, .NumOperands: 4, .NumConds: 7 }, |
| 17550 | // AArch64::LDNT1H_ZZR_S - 527 |
| 17551 | {.AsmStrOffset: 9423, .AliasCondStart: 3452, .NumOperands: 4, .NumConds: 7 }, |
| 17552 | // AArch64::LDNT1SB_ZZR_D - 528 |
| 17553 | {.AsmStrOffset: 9451, .AliasCondStart: 3459, .NumOperands: 4, .NumConds: 7 }, |
| 17554 | // AArch64::LDNT1SB_ZZR_S - 529 |
| 17555 | {.AsmStrOffset: 9480, .AliasCondStart: 3466, .NumOperands: 4, .NumConds: 7 }, |
| 17556 | // AArch64::LDNT1SH_ZZR_D - 530 |
| 17557 | {.AsmStrOffset: 9509, .AliasCondStart: 3473, .NumOperands: 4, .NumConds: 7 }, |
| 17558 | // AArch64::LDNT1SH_ZZR_S - 531 |
| 17559 | {.AsmStrOffset: 9538, .AliasCondStart: 3480, .NumOperands: 4, .NumConds: 7 }, |
| 17560 | // AArch64::LDNT1SW_ZZR_D - 532 |
| 17561 | {.AsmStrOffset: 9567, .AliasCondStart: 3487, .NumOperands: 4, .NumConds: 7 }, |
| 17562 | // AArch64::LDNT1W_2Z_IMM - 533 |
| 17563 | {.AsmStrOffset: 9596, .AliasCondStart: 3494, .NumOperands: 4, .NumConds: 8 }, |
| 17564 | // AArch64::LDNT1W_2Z_STRIDED_IMM - 534 |
| 17565 | {.AsmStrOffset: 9622, .AliasCondStart: 3502, .NumOperands: 4, .NumConds: 7 }, |
| 17566 | // AArch64::LDNT1W_4Z_IMM - 535 |
| 17567 | {.AsmStrOffset: 9596, .AliasCondStart: 3509, .NumOperands: 4, .NumConds: 8 }, |
| 17568 | // AArch64::LDNT1W_4Z_STRIDED_IMM - 536 |
| 17569 | {.AsmStrOffset: 9622, .AliasCondStart: 3517, .NumOperands: 4, .NumConds: 7 }, |
| 17570 | // AArch64::LDNT1W_ZRI - 537 |
| 17571 | {.AsmStrOffset: 9648, .AliasCondStart: 3524, .NumOperands: 4, .NumConds: 8 }, |
| 17572 | // AArch64::LDNT1W_ZZR_D - 538 |
| 17573 | {.AsmStrOffset: 9674, .AliasCondStart: 3532, .NumOperands: 4, .NumConds: 7 }, |
| 17574 | // AArch64::LDNT1W_ZZR_S - 539 |
| 17575 | {.AsmStrOffset: 9702, .AliasCondStart: 3539, .NumOperands: 4, .NumConds: 7 }, |
| 17576 | // AArch64::LDPDi - 540 |
| 17577 | {.AsmStrOffset: 9730, .AliasCondStart: 3546, .NumOperands: 4, .NumConds: 7 }, |
| 17578 | // AArch64::LDPQi - 541 |
| 17579 | {.AsmStrOffset: 9730, .AliasCondStart: 3553, .NumOperands: 4, .NumConds: 7 }, |
| 17580 | // AArch64::LDPSWi - 542 |
| 17581 | {.AsmStrOffset: 9747, .AliasCondStart: 3560, .NumOperands: 4, .NumConds: 4 }, |
| 17582 | // AArch64::LDPSi - 543 |
| 17583 | {.AsmStrOffset: 9730, .AliasCondStart: 3564, .NumOperands: 4, .NumConds: 7 }, |
| 17584 | // AArch64::LDPWi - 544 |
| 17585 | {.AsmStrOffset: 9730, .AliasCondStart: 3571, .NumOperands: 4, .NumConds: 4 }, |
| 17586 | // AArch64::LDPXi - 545 |
| 17587 | {.AsmStrOffset: 9730, .AliasCondStart: 3575, .NumOperands: 4, .NumConds: 4 }, |
| 17588 | // AArch64::LDRAAindexed - 546 |
| 17589 | {.AsmStrOffset: 9766, .AliasCondStart: 3579, .NumOperands: 3, .NumConds: 6 }, |
| 17590 | // AArch64::LDRABindexed - 547 |
| 17591 | {.AsmStrOffset: 9781, .AliasCondStart: 3585, .NumOperands: 3, .NumConds: 6 }, |
| 17592 | // AArch64::LDRBBroX - 548 |
| 17593 | {.AsmStrOffset: 9796, .AliasCondStart: 3591, .NumOperands: 5, .NumConds: 5 }, |
| 17594 | // AArch64::LDRBBui - 549 |
| 17595 | {.AsmStrOffset: 9814, .AliasCondStart: 3596, .NumOperands: 3, .NumConds: 3 }, |
| 17596 | // AArch64::LDRBroX - 550 |
| 17597 | {.AsmStrOffset: 9828, .AliasCondStart: 3599, .NumOperands: 5, .NumConds: 8 }, |
| 17598 | // AArch64::LDRBui - 551 |
| 17599 | {.AsmStrOffset: 9845, .AliasCondStart: 3607, .NumOperands: 3, .NumConds: 6 }, |
| 17600 | // AArch64::LDRDroX - 552 |
| 17601 | {.AsmStrOffset: 9828, .AliasCondStart: 3613, .NumOperands: 5, .NumConds: 8 }, |
| 17602 | // AArch64::LDRDui - 553 |
| 17603 | {.AsmStrOffset: 9845, .AliasCondStart: 3621, .NumOperands: 3, .NumConds: 6 }, |
| 17604 | // AArch64::LDRHHroX - 554 |
| 17605 | {.AsmStrOffset: 9858, .AliasCondStart: 3627, .NumOperands: 5, .NumConds: 5 }, |
| 17606 | // AArch64::LDRHHui - 555 |
| 17607 | {.AsmStrOffset: 9876, .AliasCondStart: 3632, .NumOperands: 3, .NumConds: 3 }, |
| 17608 | // AArch64::LDRHroX - 556 |
| 17609 | {.AsmStrOffset: 9828, .AliasCondStart: 3635, .NumOperands: 5, .NumConds: 8 }, |
| 17610 | // AArch64::LDRHui - 557 |
| 17611 | {.AsmStrOffset: 9845, .AliasCondStart: 3643, .NumOperands: 3, .NumConds: 6 }, |
| 17612 | // AArch64::LDRQroX - 558 |
| 17613 | {.AsmStrOffset: 9828, .AliasCondStart: 3649, .NumOperands: 5, .NumConds: 8 }, |
| 17614 | // AArch64::LDRQui - 559 |
| 17615 | {.AsmStrOffset: 9845, .AliasCondStart: 3657, .NumOperands: 3, .NumConds: 6 }, |
| 17616 | // AArch64::LDRSBWroX - 560 |
| 17617 | {.AsmStrOffset: 9890, .AliasCondStart: 3663, .NumOperands: 5, .NumConds: 5 }, |
| 17618 | // AArch64::LDRSBWui - 561 |
| 17619 | {.AsmStrOffset: 9909, .AliasCondStart: 3668, .NumOperands: 3, .NumConds: 3 }, |
| 17620 | // AArch64::LDRSBXroX - 562 |
| 17621 | {.AsmStrOffset: 9890, .AliasCondStart: 3671, .NumOperands: 5, .NumConds: 5 }, |
| 17622 | // AArch64::LDRSBXui - 563 |
| 17623 | {.AsmStrOffset: 9909, .AliasCondStart: 3676, .NumOperands: 3, .NumConds: 3 }, |
| 17624 | // AArch64::LDRSHWroX - 564 |
| 17625 | {.AsmStrOffset: 9924, .AliasCondStart: 3679, .NumOperands: 5, .NumConds: 5 }, |
| 17626 | // AArch64::LDRSHWui - 565 |
| 17627 | {.AsmStrOffset: 9943, .AliasCondStart: 3684, .NumOperands: 3, .NumConds: 3 }, |
| 17628 | // AArch64::LDRSHXroX - 566 |
| 17629 | {.AsmStrOffset: 9924, .AliasCondStart: 3687, .NumOperands: 5, .NumConds: 5 }, |
| 17630 | // AArch64::LDRSHXui - 567 |
| 17631 | {.AsmStrOffset: 9943, .AliasCondStart: 3692, .NumOperands: 3, .NumConds: 3 }, |
| 17632 | // AArch64::LDRSWroX - 568 |
| 17633 | {.AsmStrOffset: 9958, .AliasCondStart: 3695, .NumOperands: 5, .NumConds: 5 }, |
| 17634 | // AArch64::LDRSWui - 569 |
| 17635 | {.AsmStrOffset: 9977, .AliasCondStart: 3700, .NumOperands: 3, .NumConds: 3 }, |
| 17636 | // AArch64::LDRSroX - 570 |
| 17637 | {.AsmStrOffset: 9828, .AliasCondStart: 3703, .NumOperands: 5, .NumConds: 8 }, |
| 17638 | // AArch64::LDRSui - 571 |
| 17639 | {.AsmStrOffset: 9845, .AliasCondStart: 3711, .NumOperands: 3, .NumConds: 6 }, |
| 17640 | // AArch64::LDRWroX - 572 |
| 17641 | {.AsmStrOffset: 9828, .AliasCondStart: 3717, .NumOperands: 5, .NumConds: 5 }, |
| 17642 | // AArch64::LDRWui - 573 |
| 17643 | {.AsmStrOffset: 9845, .AliasCondStart: 3722, .NumOperands: 3, .NumConds: 3 }, |
| 17644 | // AArch64::LDRXroX - 574 |
| 17645 | {.AsmStrOffset: 9828, .AliasCondStart: 3725, .NumOperands: 5, .NumConds: 5 }, |
| 17646 | // AArch64::LDRXui - 575 |
| 17647 | {.AsmStrOffset: 9845, .AliasCondStart: 3730, .NumOperands: 3, .NumConds: 3 }, |
| 17648 | // AArch64::LDR_PXI - 576 |
| 17649 | {.AsmStrOffset: 9992, .AliasCondStart: 3733, .NumOperands: 3, .NumConds: 7 }, |
| 17650 | // AArch64::LDR_ZA - 577 |
| 17651 | {.AsmStrOffset: 10007, .AliasCondStart: 3740, .NumOperands: 5, .NumConds: 8 }, |
| 17652 | // AArch64::LDR_ZXI - 578 |
| 17653 | {.AsmStrOffset: 9992, .AliasCondStart: 3748, .NumOperands: 3, .NumConds: 7 }, |
| 17654 | // AArch64::LDSETB - 579 |
| 17655 | {.AsmStrOffset: 10032, .AliasCondStart: 3755, .NumOperands: 3, .NumConds: 6 }, |
| 17656 | // AArch64::LDSETH - 580 |
| 17657 | {.AsmStrOffset: 10048, .AliasCondStart: 3761, .NumOperands: 3, .NumConds: 6 }, |
| 17658 | // AArch64::LDSETLB - 581 |
| 17659 | {.AsmStrOffset: 10064, .AliasCondStart: 3767, .NumOperands: 3, .NumConds: 6 }, |
| 17660 | // AArch64::LDSETLH - 582 |
| 17661 | {.AsmStrOffset: 10081, .AliasCondStart: 3773, .NumOperands: 3, .NumConds: 6 }, |
| 17662 | // AArch64::LDSETLW - 583 |
| 17663 | {.AsmStrOffset: 10098, .AliasCondStart: 3779, .NumOperands: 3, .NumConds: 6 }, |
| 17664 | // AArch64::LDSETLX - 584 |
| 17665 | {.AsmStrOffset: 10098, .AliasCondStart: 3785, .NumOperands: 3, .NumConds: 6 }, |
| 17666 | // AArch64::LDSETW - 585 |
| 17667 | {.AsmStrOffset: 10114, .AliasCondStart: 3791, .NumOperands: 3, .NumConds: 6 }, |
| 17668 | // AArch64::LDSETX - 586 |
| 17669 | {.AsmStrOffset: 10114, .AliasCondStart: 3797, .NumOperands: 3, .NumConds: 6 }, |
| 17670 | // AArch64::LDSMAXB - 587 |
| 17671 | {.AsmStrOffset: 10129, .AliasCondStart: 3803, .NumOperands: 3, .NumConds: 6 }, |
| 17672 | // AArch64::LDSMAXH - 588 |
| 17673 | {.AsmStrOffset: 10146, .AliasCondStart: 3809, .NumOperands: 3, .NumConds: 6 }, |
| 17674 | // AArch64::LDSMAXLB - 589 |
| 17675 | {.AsmStrOffset: 10163, .AliasCondStart: 3815, .NumOperands: 3, .NumConds: 6 }, |
| 17676 | // AArch64::LDSMAXLH - 590 |
| 17677 | {.AsmStrOffset: 10181, .AliasCondStart: 3821, .NumOperands: 3, .NumConds: 6 }, |
| 17678 | // AArch64::LDSMAXLW - 591 |
| 17679 | {.AsmStrOffset: 10199, .AliasCondStart: 3827, .NumOperands: 3, .NumConds: 6 }, |
| 17680 | // AArch64::LDSMAXLX - 592 |
| 17681 | {.AsmStrOffset: 10199, .AliasCondStart: 3833, .NumOperands: 3, .NumConds: 6 }, |
| 17682 | // AArch64::LDSMAXW - 593 |
| 17683 | {.AsmStrOffset: 10216, .AliasCondStart: 3839, .NumOperands: 3, .NumConds: 6 }, |
| 17684 | // AArch64::LDSMAXX - 594 |
| 17685 | {.AsmStrOffset: 10216, .AliasCondStart: 3845, .NumOperands: 3, .NumConds: 6 }, |
| 17686 | // AArch64::LDSMINB - 595 |
| 17687 | {.AsmStrOffset: 10232, .AliasCondStart: 3851, .NumOperands: 3, .NumConds: 6 }, |
| 17688 | // AArch64::LDSMINH - 596 |
| 17689 | {.AsmStrOffset: 10249, .AliasCondStart: 3857, .NumOperands: 3, .NumConds: 6 }, |
| 17690 | // AArch64::LDSMINLB - 597 |
| 17691 | {.AsmStrOffset: 10266, .AliasCondStart: 3863, .NumOperands: 3, .NumConds: 6 }, |
| 17692 | // AArch64::LDSMINLH - 598 |
| 17693 | {.AsmStrOffset: 10284, .AliasCondStart: 3869, .NumOperands: 3, .NumConds: 6 }, |
| 17694 | // AArch64::LDSMINLW - 599 |
| 17695 | {.AsmStrOffset: 10302, .AliasCondStart: 3875, .NumOperands: 3, .NumConds: 6 }, |
| 17696 | // AArch64::LDSMINLX - 600 |
| 17697 | {.AsmStrOffset: 10302, .AliasCondStart: 3881, .NumOperands: 3, .NumConds: 6 }, |
| 17698 | // AArch64::LDSMINW - 601 |
| 17699 | {.AsmStrOffset: 10319, .AliasCondStart: 3887, .NumOperands: 3, .NumConds: 6 }, |
| 17700 | // AArch64::LDSMINX - 602 |
| 17701 | {.AsmStrOffset: 10319, .AliasCondStart: 3893, .NumOperands: 3, .NumConds: 6 }, |
| 17702 | // AArch64::LDTADDLW - 603 |
| 17703 | {.AsmStrOffset: 10335, .AliasCondStart: 3899, .NumOperands: 3, .NumConds: 6 }, |
| 17704 | // AArch64::LDTADDLX - 604 |
| 17705 | {.AsmStrOffset: 10335, .AliasCondStart: 3905, .NumOperands: 3, .NumConds: 6 }, |
| 17706 | // AArch64::LDTADDW - 605 |
| 17707 | {.AsmStrOffset: 10352, .AliasCondStart: 3911, .NumOperands: 3, .NumConds: 6 }, |
| 17708 | // AArch64::LDTADDX - 606 |
| 17709 | {.AsmStrOffset: 10352, .AliasCondStart: 3917, .NumOperands: 3, .NumConds: 6 }, |
| 17710 | // AArch64::LDTCLRLW - 607 |
| 17711 | {.AsmStrOffset: 10368, .AliasCondStart: 3923, .NumOperands: 3, .NumConds: 6 }, |
| 17712 | // AArch64::LDTCLRLX - 608 |
| 17713 | {.AsmStrOffset: 10368, .AliasCondStart: 3929, .NumOperands: 3, .NumConds: 6 }, |
| 17714 | // AArch64::LDTCLRW - 609 |
| 17715 | {.AsmStrOffset: 10385, .AliasCondStart: 3935, .NumOperands: 3, .NumConds: 6 }, |
| 17716 | // AArch64::LDTCLRX - 610 |
| 17717 | {.AsmStrOffset: 10385, .AliasCondStart: 3941, .NumOperands: 3, .NumConds: 6 }, |
| 17718 | // AArch64::LDTNPQi - 611 |
| 17719 | {.AsmStrOffset: 10401, .AliasCondStart: 3947, .NumOperands: 4, .NumConds: 10 }, |
| 17720 | // AArch64::LDTNPXi - 612 |
| 17721 | {.AsmStrOffset: 10401, .AliasCondStart: 3957, .NumOperands: 4, .NumConds: 7 }, |
| 17722 | // AArch64::LDTPQi - 613 |
| 17723 | {.AsmStrOffset: 10420, .AliasCondStart: 3964, .NumOperands: 4, .NumConds: 10 }, |
| 17724 | // AArch64::LDTPi - 614 |
| 17725 | {.AsmStrOffset: 10420, .AliasCondStart: 3974, .NumOperands: 4, .NumConds: 7 }, |
| 17726 | // AArch64::LDTRBi - 615 |
| 17727 | {.AsmStrOffset: 10438, .AliasCondStart: 3981, .NumOperands: 3, .NumConds: 3 }, |
| 17728 | // AArch64::LDTRHi - 616 |
| 17729 | {.AsmStrOffset: 10453, .AliasCondStart: 3984, .NumOperands: 3, .NumConds: 3 }, |
| 17730 | // AArch64::LDTRSBWi - 617 |
| 17731 | {.AsmStrOffset: 10468, .AliasCondStart: 3987, .NumOperands: 3, .NumConds: 3 }, |
| 17732 | // AArch64::LDTRSBXi - 618 |
| 17733 | {.AsmStrOffset: 10468, .AliasCondStart: 3990, .NumOperands: 3, .NumConds: 3 }, |
| 17734 | // AArch64::LDTRSHWi - 619 |
| 17735 | {.AsmStrOffset: 10484, .AliasCondStart: 3993, .NumOperands: 3, .NumConds: 3 }, |
| 17736 | // AArch64::LDTRSHXi - 620 |
| 17737 | {.AsmStrOffset: 10484, .AliasCondStart: 3996, .NumOperands: 3, .NumConds: 3 }, |
| 17738 | // AArch64::LDTRSWi - 621 |
| 17739 | {.AsmStrOffset: 10500, .AliasCondStart: 3999, .NumOperands: 3, .NumConds: 3 }, |
| 17740 | // AArch64::LDTRWi - 622 |
| 17741 | {.AsmStrOffset: 10516, .AliasCondStart: 4002, .NumOperands: 3, .NumConds: 3 }, |
| 17742 | // AArch64::LDTRXi - 623 |
| 17743 | {.AsmStrOffset: 10516, .AliasCondStart: 4005, .NumOperands: 3, .NumConds: 3 }, |
| 17744 | // AArch64::LDTSETLW - 624 |
| 17745 | {.AsmStrOffset: 10530, .AliasCondStart: 4008, .NumOperands: 3, .NumConds: 6 }, |
| 17746 | // AArch64::LDTSETLX - 625 |
| 17747 | {.AsmStrOffset: 10530, .AliasCondStart: 4014, .NumOperands: 3, .NumConds: 6 }, |
| 17748 | // AArch64::LDTSETW - 626 |
| 17749 | {.AsmStrOffset: 10547, .AliasCondStart: 4020, .NumOperands: 3, .NumConds: 6 }, |
| 17750 | // AArch64::LDTSETX - 627 |
| 17751 | {.AsmStrOffset: 10547, .AliasCondStart: 4026, .NumOperands: 3, .NumConds: 6 }, |
| 17752 | // AArch64::LDUMAXB - 628 |
| 17753 | {.AsmStrOffset: 10563, .AliasCondStart: 4032, .NumOperands: 3, .NumConds: 6 }, |
| 17754 | // AArch64::LDUMAXH - 629 |
| 17755 | {.AsmStrOffset: 10580, .AliasCondStart: 4038, .NumOperands: 3, .NumConds: 6 }, |
| 17756 | // AArch64::LDUMAXLB - 630 |
| 17757 | {.AsmStrOffset: 10597, .AliasCondStart: 4044, .NumOperands: 3, .NumConds: 6 }, |
| 17758 | // AArch64::LDUMAXLH - 631 |
| 17759 | {.AsmStrOffset: 10615, .AliasCondStart: 4050, .NumOperands: 3, .NumConds: 6 }, |
| 17760 | // AArch64::LDUMAXLW - 632 |
| 17761 | {.AsmStrOffset: 10633, .AliasCondStart: 4056, .NumOperands: 3, .NumConds: 6 }, |
| 17762 | // AArch64::LDUMAXLX - 633 |
| 17763 | {.AsmStrOffset: 10633, .AliasCondStart: 4062, .NumOperands: 3, .NumConds: 6 }, |
| 17764 | // AArch64::LDUMAXW - 634 |
| 17765 | {.AsmStrOffset: 10650, .AliasCondStart: 4068, .NumOperands: 3, .NumConds: 6 }, |
| 17766 | // AArch64::LDUMAXX - 635 |
| 17767 | {.AsmStrOffset: 10650, .AliasCondStart: 4074, .NumOperands: 3, .NumConds: 6 }, |
| 17768 | // AArch64::LDUMINB - 636 |
| 17769 | {.AsmStrOffset: 10666, .AliasCondStart: 4080, .NumOperands: 3, .NumConds: 6 }, |
| 17770 | // AArch64::LDUMINH - 637 |
| 17771 | {.AsmStrOffset: 10683, .AliasCondStart: 4086, .NumOperands: 3, .NumConds: 6 }, |
| 17772 | // AArch64::LDUMINLB - 638 |
| 17773 | {.AsmStrOffset: 10700, .AliasCondStart: 4092, .NumOperands: 3, .NumConds: 6 }, |
| 17774 | // AArch64::LDUMINLH - 639 |
| 17775 | {.AsmStrOffset: 10718, .AliasCondStart: 4098, .NumOperands: 3, .NumConds: 6 }, |
| 17776 | // AArch64::LDUMINLW - 640 |
| 17777 | {.AsmStrOffset: 10736, .AliasCondStart: 4104, .NumOperands: 3, .NumConds: 6 }, |
| 17778 | // AArch64::LDUMINLX - 641 |
| 17779 | {.AsmStrOffset: 10736, .AliasCondStart: 4110, .NumOperands: 3, .NumConds: 6 }, |
| 17780 | // AArch64::LDUMINW - 642 |
| 17781 | {.AsmStrOffset: 10753, .AliasCondStart: 4116, .NumOperands: 3, .NumConds: 6 }, |
| 17782 | // AArch64::LDUMINX - 643 |
| 17783 | {.AsmStrOffset: 10753, .AliasCondStart: 4122, .NumOperands: 3, .NumConds: 6 }, |
| 17784 | // AArch64::LDURBBi - 644 |
| 17785 | {.AsmStrOffset: 10769, .AliasCondStart: 4128, .NumOperands: 3, .NumConds: 3 }, |
| 17786 | // AArch64::LDURBi - 645 |
| 17787 | {.AsmStrOffset: 10784, .AliasCondStart: 4131, .NumOperands: 3, .NumConds: 6 }, |
| 17788 | // AArch64::LDURDi - 646 |
| 17789 | {.AsmStrOffset: 10784, .AliasCondStart: 4137, .NumOperands: 3, .NumConds: 6 }, |
| 17790 | // AArch64::LDURHHi - 647 |
| 17791 | {.AsmStrOffset: 10798, .AliasCondStart: 4143, .NumOperands: 3, .NumConds: 3 }, |
| 17792 | // AArch64::LDURHi - 648 |
| 17793 | {.AsmStrOffset: 10784, .AliasCondStart: 4146, .NumOperands: 3, .NumConds: 6 }, |
| 17794 | // AArch64::LDURQi - 649 |
| 17795 | {.AsmStrOffset: 10784, .AliasCondStart: 4152, .NumOperands: 3, .NumConds: 6 }, |
| 17796 | // AArch64::LDURSBWi - 650 |
| 17797 | {.AsmStrOffset: 10813, .AliasCondStart: 4158, .NumOperands: 3, .NumConds: 3 }, |
| 17798 | // AArch64::LDURSBXi - 651 |
| 17799 | {.AsmStrOffset: 10813, .AliasCondStart: 4161, .NumOperands: 3, .NumConds: 3 }, |
| 17800 | // AArch64::LDURSHWi - 652 |
| 17801 | {.AsmStrOffset: 10829, .AliasCondStart: 4164, .NumOperands: 3, .NumConds: 3 }, |
| 17802 | // AArch64::LDURSHXi - 653 |
| 17803 | {.AsmStrOffset: 10829, .AliasCondStart: 4167, .NumOperands: 3, .NumConds: 3 }, |
| 17804 | // AArch64::LDURSWi - 654 |
| 17805 | {.AsmStrOffset: 10845, .AliasCondStart: 4170, .NumOperands: 3, .NumConds: 3 }, |
| 17806 | // AArch64::LDURSi - 655 |
| 17807 | {.AsmStrOffset: 10784, .AliasCondStart: 4173, .NumOperands: 3, .NumConds: 6 }, |
| 17808 | // AArch64::LDURWi - 656 |
| 17809 | {.AsmStrOffset: 10784, .AliasCondStart: 4179, .NumOperands: 3, .NumConds: 3 }, |
| 17810 | // AArch64::LDURXi - 657 |
| 17811 | {.AsmStrOffset: 10784, .AliasCondStart: 4182, .NumOperands: 3, .NumConds: 3 }, |
| 17812 | // AArch64::MADDWrrr - 658 |
| 17813 | {.AsmStrOffset: 10861, .AliasCondStart: 4185, .NumOperands: 4, .NumConds: 4 }, |
| 17814 | // AArch64::MADDXrrr - 659 |
| 17815 | {.AsmStrOffset: 10861, .AliasCondStart: 4189, .NumOperands: 4, .NumConds: 4 }, |
| 17816 | // AArch64::MOVA_2ZMXI_H_B - 660 |
| 17817 | {.AsmStrOffset: 10876, .AliasCondStart: 4193, .NumOperands: 4, .NumConds: 6 }, |
| 17818 | // AArch64::MOVA_2ZMXI_H_D - 661 |
| 17819 | {.AsmStrOffset: 10901, .AliasCondStart: 4199, .NumOperands: 4, .NumConds: 6 }, |
| 17820 | // AArch64::MOVA_2ZMXI_H_H - 662 |
| 17821 | {.AsmStrOffset: 10926, .AliasCondStart: 4205, .NumOperands: 4, .NumConds: 6 }, |
| 17822 | // AArch64::MOVA_2ZMXI_H_S - 663 |
| 17823 | {.AsmStrOffset: 10951, .AliasCondStart: 4211, .NumOperands: 4, .NumConds: 6 }, |
| 17824 | // AArch64::MOVA_2ZMXI_V_B - 664 |
| 17825 | {.AsmStrOffset: 10976, .AliasCondStart: 4217, .NumOperands: 4, .NumConds: 6 }, |
| 17826 | // AArch64::MOVA_2ZMXI_V_D - 665 |
| 17827 | {.AsmStrOffset: 11001, .AliasCondStart: 4223, .NumOperands: 4, .NumConds: 6 }, |
| 17828 | // AArch64::MOVA_2ZMXI_V_H - 666 |
| 17829 | {.AsmStrOffset: 11026, .AliasCondStart: 4229, .NumOperands: 4, .NumConds: 6 }, |
| 17830 | // AArch64::MOVA_2ZMXI_V_S - 667 |
| 17831 | {.AsmStrOffset: 11051, .AliasCondStart: 4235, .NumOperands: 4, .NumConds: 6 }, |
| 17832 | // AArch64::MOVA_4ZMXI_H_B - 668 |
| 17833 | {.AsmStrOffset: 11076, .AliasCondStart: 4241, .NumOperands: 4, .NumConds: 6 }, |
| 17834 | // AArch64::MOVA_4ZMXI_H_D - 669 |
| 17835 | {.AsmStrOffset: 11101, .AliasCondStart: 4247, .NumOperands: 4, .NumConds: 6 }, |
| 17836 | // AArch64::MOVA_4ZMXI_H_H - 670 |
| 17837 | {.AsmStrOffset: 11126, .AliasCondStart: 4253, .NumOperands: 4, .NumConds: 6 }, |
| 17838 | // AArch64::MOVA_4ZMXI_H_S - 671 |
| 17839 | {.AsmStrOffset: 11151, .AliasCondStart: 4259, .NumOperands: 4, .NumConds: 6 }, |
| 17840 | // AArch64::MOVA_4ZMXI_V_B - 672 |
| 17841 | {.AsmStrOffset: 11176, .AliasCondStart: 4265, .NumOperands: 4, .NumConds: 6 }, |
| 17842 | // AArch64::MOVA_4ZMXI_V_D - 673 |
| 17843 | {.AsmStrOffset: 11201, .AliasCondStart: 4271, .NumOperands: 4, .NumConds: 6 }, |
| 17844 | // AArch64::MOVA_4ZMXI_V_H - 674 |
| 17845 | {.AsmStrOffset: 11226, .AliasCondStart: 4277, .NumOperands: 4, .NumConds: 6 }, |
| 17846 | // AArch64::MOVA_4ZMXI_V_S - 675 |
| 17847 | {.AsmStrOffset: 11251, .AliasCondStart: 4283, .NumOperands: 4, .NumConds: 6 }, |
| 17848 | // AArch64::MOVA_MXI2Z_H_B - 676 |
| 17849 | {.AsmStrOffset: 11276, .AliasCondStart: 4289, .NumOperands: 5, .NumConds: 8 }, |
| 17850 | // AArch64::MOVA_MXI2Z_H_D - 677 |
| 17851 | {.AsmStrOffset: 11301, .AliasCondStart: 4297, .NumOperands: 5, .NumConds: 8 }, |
| 17852 | // AArch64::MOVA_MXI2Z_H_H - 678 |
| 17853 | {.AsmStrOffset: 11326, .AliasCondStart: 4305, .NumOperands: 5, .NumConds: 8 }, |
| 17854 | // AArch64::MOVA_MXI2Z_H_S - 679 |
| 17855 | {.AsmStrOffset: 11351, .AliasCondStart: 4313, .NumOperands: 5, .NumConds: 8 }, |
| 17856 | // AArch64::MOVA_MXI2Z_V_B - 680 |
| 17857 | {.AsmStrOffset: 11376, .AliasCondStart: 4321, .NumOperands: 5, .NumConds: 8 }, |
| 17858 | // AArch64::MOVA_MXI2Z_V_D - 681 |
| 17859 | {.AsmStrOffset: 11401, .AliasCondStart: 4329, .NumOperands: 5, .NumConds: 8 }, |
| 17860 | // AArch64::MOVA_MXI2Z_V_H - 682 |
| 17861 | {.AsmStrOffset: 11426, .AliasCondStart: 4337, .NumOperands: 5, .NumConds: 8 }, |
| 17862 | // AArch64::MOVA_MXI2Z_V_S - 683 |
| 17863 | {.AsmStrOffset: 11451, .AliasCondStart: 4345, .NumOperands: 5, .NumConds: 8 }, |
| 17864 | // AArch64::MOVA_MXI4Z_H_B - 684 |
| 17865 | {.AsmStrOffset: 11476, .AliasCondStart: 4353, .NumOperands: 5, .NumConds: 8 }, |
| 17866 | // AArch64::MOVA_MXI4Z_H_D - 685 |
| 17867 | {.AsmStrOffset: 11501, .AliasCondStart: 4361, .NumOperands: 5, .NumConds: 8 }, |
| 17868 | // AArch64::MOVA_MXI4Z_H_H - 686 |
| 17869 | {.AsmStrOffset: 11526, .AliasCondStart: 4369, .NumOperands: 5, .NumConds: 8 }, |
| 17870 | // AArch64::MOVA_MXI4Z_H_S - 687 |
| 17871 | {.AsmStrOffset: 11551, .AliasCondStart: 4377, .NumOperands: 5, .NumConds: 8 }, |
| 17872 | // AArch64::MOVA_MXI4Z_V_B - 688 |
| 17873 | {.AsmStrOffset: 11576, .AliasCondStart: 4385, .NumOperands: 5, .NumConds: 8 }, |
| 17874 | // AArch64::MOVA_MXI4Z_V_D - 689 |
| 17875 | {.AsmStrOffset: 11601, .AliasCondStart: 4393, .NumOperands: 5, .NumConds: 8 }, |
| 17876 | // AArch64::MOVA_MXI4Z_V_H - 690 |
| 17877 | {.AsmStrOffset: 11626, .AliasCondStart: 4401, .NumOperands: 5, .NumConds: 8 }, |
| 17878 | // AArch64::MOVA_MXI4Z_V_S - 691 |
| 17879 | {.AsmStrOffset: 11651, .AliasCondStart: 4409, .NumOperands: 5, .NumConds: 8 }, |
| 17880 | // AArch64::MOVA_VG2_2ZMXI - 692 |
| 17881 | {.AsmStrOffset: 11676, .AliasCondStart: 4417, .NumOperands: 4, .NumConds: 6 }, |
| 17882 | // AArch64::MOVA_VG2_MXI2Z - 693 |
| 17883 | {.AsmStrOffset: 11707, .AliasCondStart: 4423, .NumOperands: 5, .NumConds: 8 }, |
| 17884 | // AArch64::MOVA_VG4_4ZMXI - 694 |
| 17885 | {.AsmStrOffset: 11738, .AliasCondStart: 4431, .NumOperands: 4, .NumConds: 6 }, |
| 17886 | // AArch64::MOVA_VG4_MXI4Z - 695 |
| 17887 | {.AsmStrOffset: 11769, .AliasCondStart: 4437, .NumOperands: 5, .NumConds: 8 }, |
| 17888 | // AArch64::MOVT_TIZ - 696 |
| 17889 | {.AsmStrOffset: 11800, .AliasCondStart: 4445, .NumOperands: 3, .NumConds: 6 }, |
| 17890 | // AArch64::MSRpstatesvcrImm1 - 697 |
| 17891 | {.AsmStrOffset: 11814, .AliasCondStart: 4451, .NumOperands: 2, .NumConds: 2 }, |
| 17892 | {.AsmStrOffset: 11822, .AliasCondStart: 4453, .NumOperands: 2, .NumConds: 2 }, |
| 17893 | {.AsmStrOffset: 11833, .AliasCondStart: 4455, .NumOperands: 2, .NumConds: 2 }, |
| 17894 | {.AsmStrOffset: 11844, .AliasCondStart: 4457, .NumOperands: 2, .NumConds: 2 }, |
| 17895 | {.AsmStrOffset: 11851, .AliasCondStart: 4459, .NumOperands: 2, .NumConds: 2 }, |
| 17896 | {.AsmStrOffset: 11861, .AliasCondStart: 4461, .NumOperands: 2, .NumConds: 2 }, |
| 17897 | // AArch64::MSUBWrrr - 703 |
| 17898 | {.AsmStrOffset: 11871, .AliasCondStart: 4463, .NumOperands: 4, .NumConds: 4 }, |
| 17899 | // AArch64::MSUBXrrr - 704 |
| 17900 | {.AsmStrOffset: 11871, .AliasCondStart: 4467, .NumOperands: 4, .NumConds: 4 }, |
| 17901 | // AArch64::NOP - 705 |
| 17902 | {.AsmStrOffset: 11887, .AliasCondStart: 4471, .NumOperands: 0, .NumConds: 0 }, |
| 17903 | // AArch64::NOTv16i8 - 706 |
| 17904 | {.AsmStrOffset: 11891, .AliasCondStart: 4471, .NumOperands: 2, .NumConds: 5 }, |
| 17905 | // AArch64::NOTv8i8 - 707 |
| 17906 | {.AsmStrOffset: 11914, .AliasCondStart: 4476, .NumOperands: 2, .NumConds: 5 }, |
| 17907 | // AArch64::ORNWrs - 708 |
| 17908 | {.AsmStrOffset: 11935, .AliasCondStart: 4481, .NumOperands: 4, .NumConds: 4 }, |
| 17909 | {.AsmStrOffset: 11946, .AliasCondStart: 4485, .NumOperands: 4, .NumConds: 3 }, |
| 17910 | {.AsmStrOffset: 11961, .AliasCondStart: 4488, .NumOperands: 4, .NumConds: 4 }, |
| 17911 | // AArch64::ORNXrs - 711 |
| 17912 | {.AsmStrOffset: 11935, .AliasCondStart: 4492, .NumOperands: 4, .NumConds: 4 }, |
| 17913 | {.AsmStrOffset: 11946, .AliasCondStart: 4496, .NumOperands: 4, .NumConds: 3 }, |
| 17914 | {.AsmStrOffset: 11961, .AliasCondStart: 4499, .NumOperands: 4, .NumConds: 4 }, |
| 17915 | // AArch64::ORRS_PPzPP - 714 |
| 17916 | {.AsmStrOffset: 11976, .AliasCondStart: 4503, .NumOperands: 4, .NumConds: 8 }, |
| 17917 | // AArch64::ORRWrs - 715 |
| 17918 | {.AsmStrOffset: 11992, .AliasCondStart: 4511, .NumOperands: 4, .NumConds: 4 }, |
| 17919 | {.AsmStrOffset: 12003, .AliasCondStart: 4515, .NumOperands: 4, .NumConds: 4 }, |
| 17920 | // AArch64::ORRXrs - 717 |
| 17921 | {.AsmStrOffset: 11992, .AliasCondStart: 4519, .NumOperands: 4, .NumConds: 4 }, |
| 17922 | {.AsmStrOffset: 12003, .AliasCondStart: 4523, .NumOperands: 4, .NumConds: 4 }, |
| 17923 | // AArch64::ORR_PPzPP - 719 |
| 17924 | {.AsmStrOffset: 12018, .AliasCondStart: 4527, .NumOperands: 4, .NumConds: 8 }, |
| 17925 | // AArch64::ORR_ZI - 720 |
| 17926 | {.AsmStrOffset: 12033, .AliasCondStart: 4535, .NumOperands: 3, .NumConds: 7 }, |
| 17927 | {.AsmStrOffset: 12054, .AliasCondStart: 4542, .NumOperands: 3, .NumConds: 7 }, |
| 17928 | {.AsmStrOffset: 12075, .AliasCondStart: 4549, .NumOperands: 3, .NumConds: 7 }, |
| 17929 | // AArch64::ORR_ZZZ - 723 |
| 17930 | {.AsmStrOffset: 12096, .AliasCondStart: 4556, .NumOperands: 3, .NumConds: 7 }, |
| 17931 | // AArch64::ORRv16i8 - 724 |
| 17932 | {.AsmStrOffset: 12111, .AliasCondStart: 4563, .NumOperands: 3, .NumConds: 6 }, |
| 17933 | // AArch64::ORRv8i8 - 725 |
| 17934 | {.AsmStrOffset: 12134, .AliasCondStart: 4569, .NumOperands: 3, .NumConds: 6 }, |
| 17935 | // AArch64::PACIA1716 - 726 |
| 17936 | {.AsmStrOffset: 12155, .AliasCondStart: 4575, .NumOperands: 0, .NumConds: 3 }, |
| 17937 | // AArch64::PACIASP - 727 |
| 17938 | {.AsmStrOffset: 12165, .AliasCondStart: 4578, .NumOperands: 0, .NumConds: 3 }, |
| 17939 | // AArch64::PACIAZ - 728 |
| 17940 | {.AsmStrOffset: 12173, .AliasCondStart: 4581, .NumOperands: 0, .NumConds: 3 }, |
| 17941 | // AArch64::PACIB1716 - 729 |
| 17942 | {.AsmStrOffset: 12180, .AliasCondStart: 4584, .NumOperands: 0, .NumConds: 3 }, |
| 17943 | // AArch64::PACIBSP - 730 |
| 17944 | {.AsmStrOffset: 12190, .AliasCondStart: 4587, .NumOperands: 0, .NumConds: 3 }, |
| 17945 | // AArch64::PACIBZ - 731 |
| 17946 | {.AsmStrOffset: 12198, .AliasCondStart: 4590, .NumOperands: 0, .NumConds: 3 }, |
| 17947 | // AArch64::PACM - 732 |
| 17948 | {.AsmStrOffset: 12205, .AliasCondStart: 4593, .NumOperands: 0, .NumConds: 3 }, |
| 17949 | // AArch64::PMOV_PZI_B - 733 |
| 17950 | {.AsmStrOffset: 12210, .AliasCondStart: 4596, .NumOperands: 3, .NumConds: 7 }, |
| 17951 | // AArch64::PMOV_ZIP_B - 734 |
| 17952 | {.AsmStrOffset: 12226, .AliasCondStart: 4603, .NumOperands: 4, .NumConds: 8 }, |
| 17953 | // AArch64::PRFB_D_PZI - 735 |
| 17954 | {.AsmStrOffset: 12242, .AliasCondStart: 4611, .NumOperands: 4, .NumConds: 7 }, |
| 17955 | // AArch64::PRFB_PRI - 736 |
| 17956 | {.AsmStrOffset: 12266, .AliasCondStart: 4618, .NumOperands: 4, .NumConds: 8 }, |
| 17957 | // AArch64::PRFB_S_PZI - 737 |
| 17958 | {.AsmStrOffset: 12288, .AliasCondStart: 4626, .NumOperands: 4, .NumConds: 7 }, |
| 17959 | // AArch64::PRFD_D_PZI - 738 |
| 17960 | {.AsmStrOffset: 12312, .AliasCondStart: 4633, .NumOperands: 4, .NumConds: 7 }, |
| 17961 | // AArch64::PRFD_PRI - 739 |
| 17962 | {.AsmStrOffset: 12336, .AliasCondStart: 4640, .NumOperands: 4, .NumConds: 8 }, |
| 17963 | // AArch64::PRFD_S_PZI - 740 |
| 17964 | {.AsmStrOffset: 12358, .AliasCondStart: 4648, .NumOperands: 4, .NumConds: 7 }, |
| 17965 | // AArch64::PRFH_D_PZI - 741 |
| 17966 | {.AsmStrOffset: 12382, .AliasCondStart: 4655, .NumOperands: 4, .NumConds: 7 }, |
| 17967 | // AArch64::PRFH_PRI - 742 |
| 17968 | {.AsmStrOffset: 12406, .AliasCondStart: 4662, .NumOperands: 4, .NumConds: 8 }, |
| 17969 | // AArch64::PRFH_S_PZI - 743 |
| 17970 | {.AsmStrOffset: 12428, .AliasCondStart: 4670, .NumOperands: 4, .NumConds: 7 }, |
| 17971 | // AArch64::PRFMroX - 744 |
| 17972 | {.AsmStrOffset: 12452, .AliasCondStart: 4677, .NumOperands: 5, .NumConds: 5 }, |
| 17973 | // AArch64::PRFMui - 745 |
| 17974 | {.AsmStrOffset: 12472, .AliasCondStart: 4682, .NumOperands: 3, .NumConds: 3 }, |
| 17975 | // AArch64::PRFUMi - 746 |
| 17976 | {.AsmStrOffset: 12488, .AliasCondStart: 4685, .NumOperands: 3, .NumConds: 3 }, |
| 17977 | // AArch64::PRFW_D_PZI - 747 |
| 17978 | {.AsmStrOffset: 12505, .AliasCondStart: 4688, .NumOperands: 4, .NumConds: 7 }, |
| 17979 | // AArch64::PRFW_PRI - 748 |
| 17980 | {.AsmStrOffset: 12529, .AliasCondStart: 4695, .NumOperands: 4, .NumConds: 8 }, |
| 17981 | // AArch64::PRFW_S_PZI - 749 |
| 17982 | {.AsmStrOffset: 12551, .AliasCondStart: 4703, .NumOperands: 4, .NumConds: 7 }, |
| 17983 | // AArch64::PTRUES_B - 750 |
| 17984 | {.AsmStrOffset: 12575, .AliasCondStart: 4710, .NumOperands: 2, .NumConds: 6 }, |
| 17985 | // AArch64::PTRUES_D - 751 |
| 17986 | {.AsmStrOffset: 12587, .AliasCondStart: 4716, .NumOperands: 2, .NumConds: 6 }, |
| 17987 | // AArch64::PTRUES_H - 752 |
| 17988 | {.AsmStrOffset: 12599, .AliasCondStart: 4722, .NumOperands: 2, .NumConds: 6 }, |
| 17989 | // AArch64::PTRUES_S - 753 |
| 17990 | {.AsmStrOffset: 12611, .AliasCondStart: 4728, .NumOperands: 2, .NumConds: 6 }, |
| 17991 | // AArch64::PTRUE_B - 754 |
| 17992 | {.AsmStrOffset: 12623, .AliasCondStart: 4734, .NumOperands: 2, .NumConds: 6 }, |
| 17993 | // AArch64::PTRUE_D - 755 |
| 17994 | {.AsmStrOffset: 12634, .AliasCondStart: 4740, .NumOperands: 2, .NumConds: 6 }, |
| 17995 | // AArch64::PTRUE_H - 756 |
| 17996 | {.AsmStrOffset: 12645, .AliasCondStart: 4746, .NumOperands: 2, .NumConds: 6 }, |
| 17997 | // AArch64::PTRUE_S - 757 |
| 17998 | {.AsmStrOffset: 12656, .AliasCondStart: 4752, .NumOperands: 2, .NumConds: 6 }, |
| 17999 | // AArch64::RET - 758 |
| 18000 | {.AsmStrOffset: 12667, .AliasCondStart: 4758, .NumOperands: 1, .NumConds: 1 }, |
| 18001 | // AArch64::SBCSWr - 759 |
| 18002 | {.AsmStrOffset: 12671, .AliasCondStart: 4759, .NumOperands: 3, .NumConds: 3 }, |
| 18003 | // AArch64::SBCSXr - 760 |
| 18004 | {.AsmStrOffset: 12671, .AliasCondStart: 4762, .NumOperands: 3, .NumConds: 3 }, |
| 18005 | // AArch64::SBCWr - 761 |
| 18006 | {.AsmStrOffset: 12683, .AliasCondStart: 4765, .NumOperands: 3, .NumConds: 3 }, |
| 18007 | // AArch64::SBCXr - 762 |
| 18008 | {.AsmStrOffset: 12683, .AliasCondStart: 4768, .NumOperands: 3, .NumConds: 3 }, |
| 18009 | // AArch64::SBFMWri - 763 |
| 18010 | {.AsmStrOffset: 12694, .AliasCondStart: 4771, .NumOperands: 4, .NumConds: 4 }, |
| 18011 | {.AsmStrOffset: 12709, .AliasCondStart: 4775, .NumOperands: 4, .NumConds: 4 }, |
| 18012 | {.AsmStrOffset: 12721, .AliasCondStart: 4779, .NumOperands: 4, .NumConds: 4 }, |
| 18013 | // AArch64::SBFMXri - 766 |
| 18014 | {.AsmStrOffset: 12694, .AliasCondStart: 4783, .NumOperands: 4, .NumConds: 4 }, |
| 18015 | {.AsmStrOffset: 12709, .AliasCondStart: 4787, .NumOperands: 4, .NumConds: 4 }, |
| 18016 | {.AsmStrOffset: 12721, .AliasCondStart: 4791, .NumOperands: 4, .NumConds: 4 }, |
| 18017 | {.AsmStrOffset: 12733, .AliasCondStart: 4795, .NumOperands: 4, .NumConds: 4 }, |
| 18018 | // AArch64::SEL_PPPP - 770 |
| 18019 | {.AsmStrOffset: 12745, .AliasCondStart: 4799, .NumOperands: 4, .NumConds: 8 }, |
| 18020 | // AArch64::SEL_ZPZZ_B - 771 |
| 18021 | {.AsmStrOffset: 12745, .AliasCondStart: 4807, .NumOperands: 4, .NumConds: 8 }, |
| 18022 | // AArch64::SEL_ZPZZ_D - 772 |
| 18023 | {.AsmStrOffset: 12768, .AliasCondStart: 4815, .NumOperands: 4, .NumConds: 8 }, |
| 18024 | // AArch64::SEL_ZPZZ_H - 773 |
| 18025 | {.AsmStrOffset: 12791, .AliasCondStart: 4823, .NumOperands: 4, .NumConds: 8 }, |
| 18026 | // AArch64::SEL_ZPZZ_S - 774 |
| 18027 | {.AsmStrOffset: 12814, .AliasCondStart: 4831, .NumOperands: 4, .NumConds: 8 }, |
| 18028 | // AArch64::SMADDLrrr - 775 |
| 18029 | {.AsmStrOffset: 12837, .AliasCondStart: 4839, .NumOperands: 4, .NumConds: 4 }, |
| 18030 | // AArch64::SMSUBLrrr - 776 |
| 18031 | {.AsmStrOffset: 12854, .AliasCondStart: 4843, .NumOperands: 4, .NumConds: 4 }, |
| 18032 | // AArch64::SQDECB_XPiI - 777 |
| 18033 | {.AsmStrOffset: 12872, .AliasCondStart: 4847, .NumOperands: 4, .NumConds: 8 }, |
| 18034 | {.AsmStrOffset: 12882, .AliasCondStart: 4855, .NumOperands: 4, .NumConds: 8 }, |
| 18035 | // AArch64::SQDECB_XPiWdI - 779 |
| 18036 | {.AsmStrOffset: 12898, .AliasCondStart: 4863, .NumOperands: 4, .NumConds: 8 }, |
| 18037 | {.AsmStrOffset: 12914, .AliasCondStart: 4871, .NumOperands: 4, .NumConds: 8 }, |
| 18038 | // AArch64::SQDECD_XPiI - 781 |
| 18039 | {.AsmStrOffset: 12936, .AliasCondStart: 4879, .NumOperands: 4, .NumConds: 8 }, |
| 18040 | {.AsmStrOffset: 12946, .AliasCondStart: 4887, .NumOperands: 4, .NumConds: 8 }, |
| 18041 | // AArch64::SQDECD_XPiWdI - 783 |
| 18042 | {.AsmStrOffset: 12962, .AliasCondStart: 4895, .NumOperands: 4, .NumConds: 8 }, |
| 18043 | {.AsmStrOffset: 12978, .AliasCondStart: 4903, .NumOperands: 4, .NumConds: 8 }, |
| 18044 | // AArch64::SQDECD_ZPiI - 785 |
| 18045 | {.AsmStrOffset: 13000, .AliasCondStart: 4911, .NumOperands: 4, .NumConds: 8 }, |
| 18046 | {.AsmStrOffset: 13012, .AliasCondStart: 4919, .NumOperands: 4, .NumConds: 8 }, |
| 18047 | // AArch64::SQDECH_XPiI - 787 |
| 18048 | {.AsmStrOffset: 13030, .AliasCondStart: 4927, .NumOperands: 4, .NumConds: 8 }, |
| 18049 | {.AsmStrOffset: 13040, .AliasCondStart: 4935, .NumOperands: 4, .NumConds: 8 }, |
| 18050 | // AArch64::SQDECH_XPiWdI - 789 |
| 18051 | {.AsmStrOffset: 13056, .AliasCondStart: 4943, .NumOperands: 4, .NumConds: 8 }, |
| 18052 | {.AsmStrOffset: 13072, .AliasCondStart: 4951, .NumOperands: 4, .NumConds: 8 }, |
| 18053 | // AArch64::SQDECH_ZPiI - 791 |
| 18054 | {.AsmStrOffset: 13094, .AliasCondStart: 4959, .NumOperands: 4, .NumConds: 8 }, |
| 18055 | {.AsmStrOffset: 13106, .AliasCondStart: 4967, .NumOperands: 4, .NumConds: 8 }, |
| 18056 | // AArch64::SQDECW_XPiI - 793 |
| 18057 | {.AsmStrOffset: 13124, .AliasCondStart: 4975, .NumOperands: 4, .NumConds: 8 }, |
| 18058 | {.AsmStrOffset: 13134, .AliasCondStart: 4983, .NumOperands: 4, .NumConds: 8 }, |
| 18059 | // AArch64::SQDECW_XPiWdI - 795 |
| 18060 | {.AsmStrOffset: 13150, .AliasCondStart: 4991, .NumOperands: 4, .NumConds: 8 }, |
| 18061 | {.AsmStrOffset: 13166, .AliasCondStart: 4999, .NumOperands: 4, .NumConds: 8 }, |
| 18062 | // AArch64::SQDECW_ZPiI - 797 |
| 18063 | {.AsmStrOffset: 13188, .AliasCondStart: 5007, .NumOperands: 4, .NumConds: 8 }, |
| 18064 | {.AsmStrOffset: 13200, .AliasCondStart: 5015, .NumOperands: 4, .NumConds: 8 }, |
| 18065 | // AArch64::SQINCB_XPiI - 799 |
| 18066 | {.AsmStrOffset: 13218, .AliasCondStart: 5023, .NumOperands: 4, .NumConds: 8 }, |
| 18067 | {.AsmStrOffset: 13228, .AliasCondStart: 5031, .NumOperands: 4, .NumConds: 8 }, |
| 18068 | // AArch64::SQINCB_XPiWdI - 801 |
| 18069 | {.AsmStrOffset: 13244, .AliasCondStart: 5039, .NumOperands: 4, .NumConds: 8 }, |
| 18070 | {.AsmStrOffset: 13260, .AliasCondStart: 5047, .NumOperands: 4, .NumConds: 8 }, |
| 18071 | // AArch64::SQINCD_XPiI - 803 |
| 18072 | {.AsmStrOffset: 13282, .AliasCondStart: 5055, .NumOperands: 4, .NumConds: 8 }, |
| 18073 | {.AsmStrOffset: 13292, .AliasCondStart: 5063, .NumOperands: 4, .NumConds: 8 }, |
| 18074 | // AArch64::SQINCD_XPiWdI - 805 |
| 18075 | {.AsmStrOffset: 13308, .AliasCondStart: 5071, .NumOperands: 4, .NumConds: 8 }, |
| 18076 | {.AsmStrOffset: 13324, .AliasCondStart: 5079, .NumOperands: 4, .NumConds: 8 }, |
| 18077 | // AArch64::SQINCD_ZPiI - 807 |
| 18078 | {.AsmStrOffset: 13346, .AliasCondStart: 5087, .NumOperands: 4, .NumConds: 8 }, |
| 18079 | {.AsmStrOffset: 13358, .AliasCondStart: 5095, .NumOperands: 4, .NumConds: 8 }, |
| 18080 | // AArch64::SQINCH_XPiI - 809 |
| 18081 | {.AsmStrOffset: 13376, .AliasCondStart: 5103, .NumOperands: 4, .NumConds: 8 }, |
| 18082 | {.AsmStrOffset: 13386, .AliasCondStart: 5111, .NumOperands: 4, .NumConds: 8 }, |
| 18083 | // AArch64::SQINCH_XPiWdI - 811 |
| 18084 | {.AsmStrOffset: 13402, .AliasCondStart: 5119, .NumOperands: 4, .NumConds: 8 }, |
| 18085 | {.AsmStrOffset: 13418, .AliasCondStart: 5127, .NumOperands: 4, .NumConds: 8 }, |
| 18086 | // AArch64::SQINCH_ZPiI - 813 |
| 18087 | {.AsmStrOffset: 13440, .AliasCondStart: 5135, .NumOperands: 4, .NumConds: 8 }, |
| 18088 | {.AsmStrOffset: 13452, .AliasCondStart: 5143, .NumOperands: 4, .NumConds: 8 }, |
| 18089 | // AArch64::SQINCW_XPiI - 815 |
| 18090 | {.AsmStrOffset: 13470, .AliasCondStart: 5151, .NumOperands: 4, .NumConds: 8 }, |
| 18091 | {.AsmStrOffset: 13480, .AliasCondStart: 5159, .NumOperands: 4, .NumConds: 8 }, |
| 18092 | // AArch64::SQINCW_XPiWdI - 817 |
| 18093 | {.AsmStrOffset: 13496, .AliasCondStart: 5167, .NumOperands: 4, .NumConds: 8 }, |
| 18094 | {.AsmStrOffset: 13512, .AliasCondStart: 5175, .NumOperands: 4, .NumConds: 8 }, |
| 18095 | // AArch64::SQINCW_ZPiI - 819 |
| 18096 | {.AsmStrOffset: 13534, .AliasCondStart: 5183, .NumOperands: 4, .NumConds: 8 }, |
| 18097 | {.AsmStrOffset: 13546, .AliasCondStart: 5191, .NumOperands: 4, .NumConds: 8 }, |
| 18098 | // AArch64::SST1B_D_IMM - 821 |
| 18099 | {.AsmStrOffset: 13564, .AliasCondStart: 5199, .NumOperands: 4, .NumConds: 7 }, |
| 18100 | // AArch64::SST1B_S_IMM - 822 |
| 18101 | {.AsmStrOffset: 13588, .AliasCondStart: 5206, .NumOperands: 4, .NumConds: 7 }, |
| 18102 | // AArch64::SST1D_IMM - 823 |
| 18103 | {.AsmStrOffset: 13612, .AliasCondStart: 5213, .NumOperands: 4, .NumConds: 7 }, |
| 18104 | // AArch64::SST1H_D_IMM - 824 |
| 18105 | {.AsmStrOffset: 13636, .AliasCondStart: 5220, .NumOperands: 4, .NumConds: 7 }, |
| 18106 | // AArch64::SST1H_S_IMM - 825 |
| 18107 | {.AsmStrOffset: 13660, .AliasCondStart: 5227, .NumOperands: 4, .NumConds: 7 }, |
| 18108 | // AArch64::SST1Q - 826 |
| 18109 | {.AsmStrOffset: 13684, .AliasCondStart: 5234, .NumOperands: 4, .NumConds: 7 }, |
| 18110 | // AArch64::SST1W_D_IMM - 827 |
| 18111 | {.AsmStrOffset: 13708, .AliasCondStart: 5241, .NumOperands: 4, .NumConds: 7 }, |
| 18112 | // AArch64::SST1W_IMM - 828 |
| 18113 | {.AsmStrOffset: 13732, .AliasCondStart: 5248, .NumOperands: 4, .NumConds: 7 }, |
| 18114 | // AArch64::ST1B_2Z_IMM - 829 |
| 18115 | {.AsmStrOffset: 13756, .AliasCondStart: 5255, .NumOperands: 4, .NumConds: 8 }, |
| 18116 | // AArch64::ST1B_2Z_STRIDED_IMM - 830 |
| 18117 | {.AsmStrOffset: 13778, .AliasCondStart: 5263, .NumOperands: 4, .NumConds: 7 }, |
| 18118 | // AArch64::ST1B_4Z_IMM - 831 |
| 18119 | {.AsmStrOffset: 13756, .AliasCondStart: 5270, .NumOperands: 4, .NumConds: 8 }, |
| 18120 | // AArch64::ST1B_4Z_STRIDED_IMM - 832 |
| 18121 | {.AsmStrOffset: 13800, .AliasCondStart: 5278, .NumOperands: 4, .NumConds: 7 }, |
| 18122 | // AArch64::ST1B_D_IMM - 833 |
| 18123 | {.AsmStrOffset: 13822, .AliasCondStart: 5285, .NumOperands: 4, .NumConds: 8 }, |
| 18124 | // AArch64::ST1B_H_IMM - 834 |
| 18125 | {.AsmStrOffset: 13844, .AliasCondStart: 5293, .NumOperands: 4, .NumConds: 8 }, |
| 18126 | // AArch64::ST1B_IMM - 835 |
| 18127 | {.AsmStrOffset: 13866, .AliasCondStart: 5301, .NumOperands: 4, .NumConds: 8 }, |
| 18128 | // AArch64::ST1B_S_IMM - 836 |
| 18129 | {.AsmStrOffset: 13888, .AliasCondStart: 5309, .NumOperands: 4, .NumConds: 8 }, |
| 18130 | // AArch64::ST1D_2Z_IMM - 837 |
| 18131 | {.AsmStrOffset: 13910, .AliasCondStart: 5317, .NumOperands: 4, .NumConds: 8 }, |
| 18132 | // AArch64::ST1D_2Z_STRIDED_IMM - 838 |
| 18133 | {.AsmStrOffset: 13932, .AliasCondStart: 5325, .NumOperands: 4, .NumConds: 7 }, |
| 18134 | // AArch64::ST1D_4Z_IMM - 839 |
| 18135 | {.AsmStrOffset: 13910, .AliasCondStart: 5332, .NumOperands: 4, .NumConds: 8 }, |
| 18136 | // AArch64::ST1D_4Z_STRIDED_IMM - 840 |
| 18137 | {.AsmStrOffset: 13932, .AliasCondStart: 5340, .NumOperands: 4, .NumConds: 7 }, |
| 18138 | // AArch64::ST1D_IMM - 841 |
| 18139 | {.AsmStrOffset: 13954, .AliasCondStart: 5347, .NumOperands: 4, .NumConds: 8 }, |
| 18140 | // AArch64::ST1D_Q_IMM - 842 |
| 18141 | {.AsmStrOffset: 13976, .AliasCondStart: 5355, .NumOperands: 4, .NumConds: 7 }, |
| 18142 | // AArch64::ST1Fourv16b_POST - 843 |
| 18143 | {.AsmStrOffset: 13998, .AliasCondStart: 5362, .NumOperands: 4, .NumConds: 7 }, |
| 18144 | // AArch64::ST1Fourv1d_POST - 844 |
| 18145 | {.AsmStrOffset: 14018, .AliasCondStart: 5369, .NumOperands: 4, .NumConds: 7 }, |
| 18146 | // AArch64::ST1Fourv2d_POST - 845 |
| 18147 | {.AsmStrOffset: 14038, .AliasCondStart: 5376, .NumOperands: 4, .NumConds: 7 }, |
| 18148 | // AArch64::ST1Fourv2s_POST - 846 |
| 18149 | {.AsmStrOffset: 14058, .AliasCondStart: 5383, .NumOperands: 4, .NumConds: 7 }, |
| 18150 | // AArch64::ST1Fourv4h_POST - 847 |
| 18151 | {.AsmStrOffset: 14078, .AliasCondStart: 5390, .NumOperands: 4, .NumConds: 7 }, |
| 18152 | // AArch64::ST1Fourv4s_POST - 848 |
| 18153 | {.AsmStrOffset: 14098, .AliasCondStart: 5397, .NumOperands: 4, .NumConds: 7 }, |
| 18154 | // AArch64::ST1Fourv8b_POST - 849 |
| 18155 | {.AsmStrOffset: 14118, .AliasCondStart: 5404, .NumOperands: 4, .NumConds: 7 }, |
| 18156 | // AArch64::ST1Fourv8h_POST - 850 |
| 18157 | {.AsmStrOffset: 14138, .AliasCondStart: 5411, .NumOperands: 4, .NumConds: 7 }, |
| 18158 | // AArch64::ST1H_2Z_IMM - 851 |
| 18159 | {.AsmStrOffset: 14158, .AliasCondStart: 5418, .NumOperands: 4, .NumConds: 8 }, |
| 18160 | // AArch64::ST1H_2Z_STRIDED_IMM - 852 |
| 18161 | {.AsmStrOffset: 14180, .AliasCondStart: 5426, .NumOperands: 4, .NumConds: 7 }, |
| 18162 | // AArch64::ST1H_4Z_IMM - 853 |
| 18163 | {.AsmStrOffset: 14158, .AliasCondStart: 5433, .NumOperands: 4, .NumConds: 8 }, |
| 18164 | // AArch64::ST1H_4Z_STRIDED_IMM - 854 |
| 18165 | {.AsmStrOffset: 14202, .AliasCondStart: 5441, .NumOperands: 4, .NumConds: 7 }, |
| 18166 | // AArch64::ST1H_D_IMM - 855 |
| 18167 | {.AsmStrOffset: 14224, .AliasCondStart: 5448, .NumOperands: 4, .NumConds: 8 }, |
| 18168 | // AArch64::ST1H_IMM - 856 |
| 18169 | {.AsmStrOffset: 14246, .AliasCondStart: 5456, .NumOperands: 4, .NumConds: 8 }, |
| 18170 | // AArch64::ST1H_S_IMM - 857 |
| 18171 | {.AsmStrOffset: 14268, .AliasCondStart: 5464, .NumOperands: 4, .NumConds: 8 }, |
| 18172 | // AArch64::ST1Onev16b_POST - 858 |
| 18173 | {.AsmStrOffset: 14290, .AliasCondStart: 5472, .NumOperands: 4, .NumConds: 7 }, |
| 18174 | // AArch64::ST1Onev1d_POST - 859 |
| 18175 | {.AsmStrOffset: 14310, .AliasCondStart: 5479, .NumOperands: 4, .NumConds: 7 }, |
| 18176 | // AArch64::ST1Onev2d_POST - 860 |
| 18177 | {.AsmStrOffset: 14329, .AliasCondStart: 5486, .NumOperands: 4, .NumConds: 7 }, |
| 18178 | // AArch64::ST1Onev2s_POST - 861 |
| 18179 | {.AsmStrOffset: 14349, .AliasCondStart: 5493, .NumOperands: 4, .NumConds: 7 }, |
| 18180 | // AArch64::ST1Onev4h_POST - 862 |
| 18181 | {.AsmStrOffset: 14368, .AliasCondStart: 5500, .NumOperands: 4, .NumConds: 7 }, |
| 18182 | // AArch64::ST1Onev4s_POST - 863 |
| 18183 | {.AsmStrOffset: 14387, .AliasCondStart: 5507, .NumOperands: 4, .NumConds: 7 }, |
| 18184 | // AArch64::ST1Onev8b_POST - 864 |
| 18185 | {.AsmStrOffset: 14407, .AliasCondStart: 5514, .NumOperands: 4, .NumConds: 7 }, |
| 18186 | // AArch64::ST1Onev8h_POST - 865 |
| 18187 | {.AsmStrOffset: 14426, .AliasCondStart: 5521, .NumOperands: 4, .NumConds: 7 }, |
| 18188 | // AArch64::ST1Threev16b_POST - 866 |
| 18189 | {.AsmStrOffset: 14446, .AliasCondStart: 5528, .NumOperands: 4, .NumConds: 7 }, |
| 18190 | // AArch64::ST1Threev1d_POST - 867 |
| 18191 | {.AsmStrOffset: 14466, .AliasCondStart: 5535, .NumOperands: 4, .NumConds: 7 }, |
| 18192 | // AArch64::ST1Threev2d_POST - 868 |
| 18193 | {.AsmStrOffset: 14486, .AliasCondStart: 5542, .NumOperands: 4, .NumConds: 7 }, |
| 18194 | // AArch64::ST1Threev2s_POST - 869 |
| 18195 | {.AsmStrOffset: 14506, .AliasCondStart: 5549, .NumOperands: 4, .NumConds: 7 }, |
| 18196 | // AArch64::ST1Threev4h_POST - 870 |
| 18197 | {.AsmStrOffset: 14526, .AliasCondStart: 5556, .NumOperands: 4, .NumConds: 7 }, |
| 18198 | // AArch64::ST1Threev4s_POST - 871 |
| 18199 | {.AsmStrOffset: 14546, .AliasCondStart: 5563, .NumOperands: 4, .NumConds: 7 }, |
| 18200 | // AArch64::ST1Threev8b_POST - 872 |
| 18201 | {.AsmStrOffset: 14566, .AliasCondStart: 5570, .NumOperands: 4, .NumConds: 7 }, |
| 18202 | // AArch64::ST1Threev8h_POST - 873 |
| 18203 | {.AsmStrOffset: 14586, .AliasCondStart: 5577, .NumOperands: 4, .NumConds: 7 }, |
| 18204 | // AArch64::ST1Twov16b_POST - 874 |
| 18205 | {.AsmStrOffset: 14606, .AliasCondStart: 5584, .NumOperands: 4, .NumConds: 7 }, |
| 18206 | // AArch64::ST1Twov1d_POST - 875 |
| 18207 | {.AsmStrOffset: 14626, .AliasCondStart: 5591, .NumOperands: 4, .NumConds: 7 }, |
| 18208 | // AArch64::ST1Twov2d_POST - 876 |
| 18209 | {.AsmStrOffset: 14646, .AliasCondStart: 5598, .NumOperands: 4, .NumConds: 7 }, |
| 18210 | // AArch64::ST1Twov2s_POST - 877 |
| 18211 | {.AsmStrOffset: 14666, .AliasCondStart: 5605, .NumOperands: 4, .NumConds: 7 }, |
| 18212 | // AArch64::ST1Twov4h_POST - 878 |
| 18213 | {.AsmStrOffset: 14686, .AliasCondStart: 5612, .NumOperands: 4, .NumConds: 7 }, |
| 18214 | // AArch64::ST1Twov4s_POST - 879 |
| 18215 | {.AsmStrOffset: 14706, .AliasCondStart: 5619, .NumOperands: 4, .NumConds: 7 }, |
| 18216 | // AArch64::ST1Twov8b_POST - 880 |
| 18217 | {.AsmStrOffset: 14726, .AliasCondStart: 5626, .NumOperands: 4, .NumConds: 7 }, |
| 18218 | // AArch64::ST1Twov8h_POST - 881 |
| 18219 | {.AsmStrOffset: 14746, .AliasCondStart: 5633, .NumOperands: 4, .NumConds: 7 }, |
| 18220 | // AArch64::ST1W_2Z_IMM - 882 |
| 18221 | {.AsmStrOffset: 14766, .AliasCondStart: 5640, .NumOperands: 4, .NumConds: 8 }, |
| 18222 | // AArch64::ST1W_2Z_STRIDED_IMM - 883 |
| 18223 | {.AsmStrOffset: 14788, .AliasCondStart: 5648, .NumOperands: 4, .NumConds: 7 }, |
| 18224 | // AArch64::ST1W_4Z_IMM - 884 |
| 18225 | {.AsmStrOffset: 14766, .AliasCondStart: 5655, .NumOperands: 4, .NumConds: 8 }, |
| 18226 | // AArch64::ST1W_4Z_STRIDED_IMM - 885 |
| 18227 | {.AsmStrOffset: 14788, .AliasCondStart: 5663, .NumOperands: 4, .NumConds: 7 }, |
| 18228 | // AArch64::ST1W_D_IMM - 886 |
| 18229 | {.AsmStrOffset: 14810, .AliasCondStart: 5670, .NumOperands: 4, .NumConds: 8 }, |
| 18230 | // AArch64::ST1W_IMM - 887 |
| 18231 | {.AsmStrOffset: 14832, .AliasCondStart: 5678, .NumOperands: 4, .NumConds: 8 }, |
| 18232 | // AArch64::ST1W_Q_IMM - 888 |
| 18233 | {.AsmStrOffset: 14854, .AliasCondStart: 5686, .NumOperands: 4, .NumConds: 7 }, |
| 18234 | // AArch64::ST1_MXIPXX_H_B - 889 |
| 18235 | {.AsmStrOffset: 14876, .AliasCondStart: 5693, .NumOperands: 6, .NumConds: 9 }, |
| 18236 | // AArch64::ST1_MXIPXX_H_D - 890 |
| 18237 | {.AsmStrOffset: 14910, .AliasCondStart: 5702, .NumOperands: 6, .NumConds: 9 }, |
| 18238 | // AArch64::ST1_MXIPXX_H_H - 891 |
| 18239 | {.AsmStrOffset: 14944, .AliasCondStart: 5711, .NumOperands: 6, .NumConds: 9 }, |
| 18240 | // AArch64::ST1_MXIPXX_H_Q - 892 |
| 18241 | {.AsmStrOffset: 14978, .AliasCondStart: 5720, .NumOperands: 6, .NumConds: 9 }, |
| 18242 | // AArch64::ST1_MXIPXX_H_S - 893 |
| 18243 | {.AsmStrOffset: 15012, .AliasCondStart: 5729, .NumOperands: 6, .NumConds: 9 }, |
| 18244 | // AArch64::ST1_MXIPXX_V_B - 894 |
| 18245 | {.AsmStrOffset: 15046, .AliasCondStart: 5738, .NumOperands: 6, .NumConds: 9 }, |
| 18246 | // AArch64::ST1_MXIPXX_V_D - 895 |
| 18247 | {.AsmStrOffset: 15080, .AliasCondStart: 5747, .NumOperands: 6, .NumConds: 9 }, |
| 18248 | // AArch64::ST1_MXIPXX_V_H - 896 |
| 18249 | {.AsmStrOffset: 15114, .AliasCondStart: 5756, .NumOperands: 6, .NumConds: 9 }, |
| 18250 | // AArch64::ST1_MXIPXX_V_Q - 897 |
| 18251 | {.AsmStrOffset: 15148, .AliasCondStart: 5765, .NumOperands: 6, .NumConds: 9 }, |
| 18252 | // AArch64::ST1_MXIPXX_V_S - 898 |
| 18253 | {.AsmStrOffset: 15182, .AliasCondStart: 5774, .NumOperands: 6, .NumConds: 9 }, |
| 18254 | // AArch64::ST1i16_POST - 899 |
| 18255 | {.AsmStrOffset: 15216, .AliasCondStart: 5783, .NumOperands: 5, .NumConds: 8 }, |
| 18256 | // AArch64::ST1i32_POST - 900 |
| 18257 | {.AsmStrOffset: 15239, .AliasCondStart: 5791, .NumOperands: 5, .NumConds: 8 }, |
| 18258 | // AArch64::ST1i64_POST - 901 |
| 18259 | {.AsmStrOffset: 15262, .AliasCondStart: 5799, .NumOperands: 5, .NumConds: 8 }, |
| 18260 | // AArch64::ST1i8_POST - 902 |
| 18261 | {.AsmStrOffset: 15285, .AliasCondStart: 5807, .NumOperands: 5, .NumConds: 8 }, |
| 18262 | // AArch64::ST2B_IMM - 903 |
| 18263 | {.AsmStrOffset: 15308, .AliasCondStart: 5815, .NumOperands: 4, .NumConds: 8 }, |
| 18264 | // AArch64::ST2D_IMM - 904 |
| 18265 | {.AsmStrOffset: 15330, .AliasCondStart: 5823, .NumOperands: 4, .NumConds: 8 }, |
| 18266 | // AArch64::ST2Gi - 905 |
| 18267 | {.AsmStrOffset: 15352, .AliasCondStart: 5831, .NumOperands: 3, .NumConds: 6 }, |
| 18268 | // AArch64::ST2H_IMM - 906 |
| 18269 | {.AsmStrOffset: 15366, .AliasCondStart: 5837, .NumOperands: 4, .NumConds: 8 }, |
| 18270 | // AArch64::ST2Q_IMM - 907 |
| 18271 | {.AsmStrOffset: 15388, .AliasCondStart: 5845, .NumOperands: 4, .NumConds: 8 }, |
| 18272 | // AArch64::ST2Twov16b_POST - 908 |
| 18273 | {.AsmStrOffset: 15410, .AliasCondStart: 5853, .NumOperands: 4, .NumConds: 7 }, |
| 18274 | // AArch64::ST2Twov2d_POST - 909 |
| 18275 | {.AsmStrOffset: 15430, .AliasCondStart: 5860, .NumOperands: 4, .NumConds: 7 }, |
| 18276 | // AArch64::ST2Twov2s_POST - 910 |
| 18277 | {.AsmStrOffset: 15450, .AliasCondStart: 5867, .NumOperands: 4, .NumConds: 7 }, |
| 18278 | // AArch64::ST2Twov4h_POST - 911 |
| 18279 | {.AsmStrOffset: 15470, .AliasCondStart: 5874, .NumOperands: 4, .NumConds: 7 }, |
| 18280 | // AArch64::ST2Twov4s_POST - 912 |
| 18281 | {.AsmStrOffset: 15490, .AliasCondStart: 5881, .NumOperands: 4, .NumConds: 7 }, |
| 18282 | // AArch64::ST2Twov8b_POST - 913 |
| 18283 | {.AsmStrOffset: 15510, .AliasCondStart: 5888, .NumOperands: 4, .NumConds: 7 }, |
| 18284 | // AArch64::ST2Twov8h_POST - 914 |
| 18285 | {.AsmStrOffset: 15530, .AliasCondStart: 5895, .NumOperands: 4, .NumConds: 7 }, |
| 18286 | // AArch64::ST2W_IMM - 915 |
| 18287 | {.AsmStrOffset: 15550, .AliasCondStart: 5902, .NumOperands: 4, .NumConds: 8 }, |
| 18288 | // AArch64::ST2i16_POST - 916 |
| 18289 | {.AsmStrOffset: 15572, .AliasCondStart: 5910, .NumOperands: 5, .NumConds: 8 }, |
| 18290 | // AArch64::ST2i32_POST - 917 |
| 18291 | {.AsmStrOffset: 15595, .AliasCondStart: 5918, .NumOperands: 5, .NumConds: 8 }, |
| 18292 | // AArch64::ST2i64_POST - 918 |
| 18293 | {.AsmStrOffset: 15618, .AliasCondStart: 5926, .NumOperands: 5, .NumConds: 8 }, |
| 18294 | // AArch64::ST2i8_POST - 919 |
| 18295 | {.AsmStrOffset: 15642, .AliasCondStart: 5934, .NumOperands: 5, .NumConds: 8 }, |
| 18296 | // AArch64::ST3B_IMM - 920 |
| 18297 | {.AsmStrOffset: 15665, .AliasCondStart: 5942, .NumOperands: 4, .NumConds: 8 }, |
| 18298 | // AArch64::ST3D_IMM - 921 |
| 18299 | {.AsmStrOffset: 15687, .AliasCondStart: 5950, .NumOperands: 4, .NumConds: 8 }, |
| 18300 | // AArch64::ST3H_IMM - 922 |
| 18301 | {.AsmStrOffset: 15709, .AliasCondStart: 5958, .NumOperands: 4, .NumConds: 8 }, |
| 18302 | // AArch64::ST3Q_IMM - 923 |
| 18303 | {.AsmStrOffset: 15731, .AliasCondStart: 5966, .NumOperands: 4, .NumConds: 8 }, |
| 18304 | // AArch64::ST3Threev16b_POST - 924 |
| 18305 | {.AsmStrOffset: 15753, .AliasCondStart: 5974, .NumOperands: 4, .NumConds: 7 }, |
| 18306 | // AArch64::ST3Threev2d_POST - 925 |
| 18307 | {.AsmStrOffset: 15773, .AliasCondStart: 5981, .NumOperands: 4, .NumConds: 7 }, |
| 18308 | // AArch64::ST3Threev2s_POST - 926 |
| 18309 | {.AsmStrOffset: 15793, .AliasCondStart: 5988, .NumOperands: 4, .NumConds: 7 }, |
| 18310 | // AArch64::ST3Threev4h_POST - 927 |
| 18311 | {.AsmStrOffset: 15813, .AliasCondStart: 5995, .NumOperands: 4, .NumConds: 7 }, |
| 18312 | // AArch64::ST3Threev4s_POST - 928 |
| 18313 | {.AsmStrOffset: 15833, .AliasCondStart: 6002, .NumOperands: 4, .NumConds: 7 }, |
| 18314 | // AArch64::ST3Threev8b_POST - 929 |
| 18315 | {.AsmStrOffset: 15853, .AliasCondStart: 6009, .NumOperands: 4, .NumConds: 7 }, |
| 18316 | // AArch64::ST3Threev8h_POST - 930 |
| 18317 | {.AsmStrOffset: 15873, .AliasCondStart: 6016, .NumOperands: 4, .NumConds: 7 }, |
| 18318 | // AArch64::ST3W_IMM - 931 |
| 18319 | {.AsmStrOffset: 15893, .AliasCondStart: 6023, .NumOperands: 4, .NumConds: 8 }, |
| 18320 | // AArch64::ST3i16_POST - 932 |
| 18321 | {.AsmStrOffset: 15915, .AliasCondStart: 6031, .NumOperands: 5, .NumConds: 8 }, |
| 18322 | // AArch64::ST3i32_POST - 933 |
| 18323 | {.AsmStrOffset: 15938, .AliasCondStart: 6039, .NumOperands: 5, .NumConds: 8 }, |
| 18324 | // AArch64::ST3i64_POST - 934 |
| 18325 | {.AsmStrOffset: 15962, .AliasCondStart: 6047, .NumOperands: 5, .NumConds: 8 }, |
| 18326 | // AArch64::ST3i8_POST - 935 |
| 18327 | {.AsmStrOffset: 15986, .AliasCondStart: 6055, .NumOperands: 5, .NumConds: 8 }, |
| 18328 | // AArch64::ST4B_IMM - 936 |
| 18329 | {.AsmStrOffset: 16009, .AliasCondStart: 6063, .NumOperands: 4, .NumConds: 8 }, |
| 18330 | // AArch64::ST4D_IMM - 937 |
| 18331 | {.AsmStrOffset: 16031, .AliasCondStart: 6071, .NumOperands: 4, .NumConds: 8 }, |
| 18332 | // AArch64::ST4Fourv16b_POST - 938 |
| 18333 | {.AsmStrOffset: 16053, .AliasCondStart: 6079, .NumOperands: 4, .NumConds: 7 }, |
| 18334 | // AArch64::ST4Fourv2d_POST - 939 |
| 18335 | {.AsmStrOffset: 16073, .AliasCondStart: 6086, .NumOperands: 4, .NumConds: 7 }, |
| 18336 | // AArch64::ST4Fourv2s_POST - 940 |
| 18337 | {.AsmStrOffset: 16093, .AliasCondStart: 6093, .NumOperands: 4, .NumConds: 7 }, |
| 18338 | // AArch64::ST4Fourv4h_POST - 941 |
| 18339 | {.AsmStrOffset: 16113, .AliasCondStart: 6100, .NumOperands: 4, .NumConds: 7 }, |
| 18340 | // AArch64::ST4Fourv4s_POST - 942 |
| 18341 | {.AsmStrOffset: 16133, .AliasCondStart: 6107, .NumOperands: 4, .NumConds: 7 }, |
| 18342 | // AArch64::ST4Fourv8b_POST - 943 |
| 18343 | {.AsmStrOffset: 16153, .AliasCondStart: 6114, .NumOperands: 4, .NumConds: 7 }, |
| 18344 | // AArch64::ST4Fourv8h_POST - 944 |
| 18345 | {.AsmStrOffset: 16173, .AliasCondStart: 6121, .NumOperands: 4, .NumConds: 7 }, |
| 18346 | // AArch64::ST4H_IMM - 945 |
| 18347 | {.AsmStrOffset: 16193, .AliasCondStart: 6128, .NumOperands: 4, .NumConds: 8 }, |
| 18348 | // AArch64::ST4Q_IMM - 946 |
| 18349 | {.AsmStrOffset: 16215, .AliasCondStart: 6136, .NumOperands: 4, .NumConds: 8 }, |
| 18350 | // AArch64::ST4W_IMM - 947 |
| 18351 | {.AsmStrOffset: 16237, .AliasCondStart: 6144, .NumOperands: 4, .NumConds: 8 }, |
| 18352 | // AArch64::ST4i16_POST - 948 |
| 18353 | {.AsmStrOffset: 16259, .AliasCondStart: 6152, .NumOperands: 5, .NumConds: 8 }, |
| 18354 | // AArch64::ST4i32_POST - 949 |
| 18355 | {.AsmStrOffset: 16282, .AliasCondStart: 6160, .NumOperands: 5, .NumConds: 8 }, |
| 18356 | // AArch64::ST4i64_POST - 950 |
| 18357 | {.AsmStrOffset: 16306, .AliasCondStart: 6168, .NumOperands: 5, .NumConds: 8 }, |
| 18358 | // AArch64::ST4i8_POST - 951 |
| 18359 | {.AsmStrOffset: 16330, .AliasCondStart: 6176, .NumOperands: 5, .NumConds: 8 }, |
| 18360 | // AArch64::STGPi - 952 |
| 18361 | {.AsmStrOffset: 16353, .AliasCondStart: 6184, .NumOperands: 4, .NumConds: 7 }, |
| 18362 | // AArch64::STGi - 953 |
| 18363 | {.AsmStrOffset: 16371, .AliasCondStart: 6191, .NumOperands: 3, .NumConds: 6 }, |
| 18364 | // AArch64::STLPi - 954 |
| 18365 | {.AsmStrOffset: 16384, .AliasCondStart: 6197, .NumOperands: 3, .NumConds: 6 }, |
| 18366 | // AArch64::STLURBi - 955 |
| 18367 | {.AsmStrOffset: 16402, .AliasCondStart: 6203, .NumOperands: 3, .NumConds: 6 }, |
| 18368 | // AArch64::STLURHi - 956 |
| 18369 | {.AsmStrOffset: 16418, .AliasCondStart: 6209, .NumOperands: 3, .NumConds: 6 }, |
| 18370 | // AArch64::STLURWi - 957 |
| 18371 | {.AsmStrOffset: 16434, .AliasCondStart: 6215, .NumOperands: 3, .NumConds: 6 }, |
| 18372 | // AArch64::STLURXi - 958 |
| 18373 | {.AsmStrOffset: 16434, .AliasCondStart: 6221, .NumOperands: 3, .NumConds: 6 }, |
| 18374 | // AArch64::STLURbi - 959 |
| 18375 | {.AsmStrOffset: 16434, .AliasCondStart: 6227, .NumOperands: 3, .NumConds: 9 }, |
| 18376 | // AArch64::STLURdi - 960 |
| 18377 | {.AsmStrOffset: 16434, .AliasCondStart: 6236, .NumOperands: 3, .NumConds: 9 }, |
| 18378 | // AArch64::STLURhi - 961 |
| 18379 | {.AsmStrOffset: 16434, .AliasCondStart: 6245, .NumOperands: 3, .NumConds: 9 }, |
| 18380 | // AArch64::STLURqi - 962 |
| 18381 | {.AsmStrOffset: 16434, .AliasCondStart: 6254, .NumOperands: 3, .NumConds: 9 }, |
| 18382 | // AArch64::STLURsi - 963 |
| 18383 | {.AsmStrOffset: 16434, .AliasCondStart: 6263, .NumOperands: 3, .NumConds: 9 }, |
| 18384 | // AArch64::STNPDi - 964 |
| 18385 | {.AsmStrOffset: 16449, .AliasCondStart: 6272, .NumOperands: 4, .NumConds: 7 }, |
| 18386 | // AArch64::STNPQi - 965 |
| 18387 | {.AsmStrOffset: 16449, .AliasCondStart: 6279, .NumOperands: 4, .NumConds: 7 }, |
| 18388 | // AArch64::STNPSi - 966 |
| 18389 | {.AsmStrOffset: 16449, .AliasCondStart: 6286, .NumOperands: 4, .NumConds: 7 }, |
| 18390 | // AArch64::STNPWi - 967 |
| 18391 | {.AsmStrOffset: 16449, .AliasCondStart: 6293, .NumOperands: 4, .NumConds: 4 }, |
| 18392 | // AArch64::STNPXi - 968 |
| 18393 | {.AsmStrOffset: 16449, .AliasCondStart: 6297, .NumOperands: 4, .NumConds: 4 }, |
| 18394 | // AArch64::STNT1B_2Z_IMM - 969 |
| 18395 | {.AsmStrOffset: 16467, .AliasCondStart: 6301, .NumOperands: 4, .NumConds: 8 }, |
| 18396 | // AArch64::STNT1B_2Z_STRIDED_IMM - 970 |
| 18397 | {.AsmStrOffset: 16491, .AliasCondStart: 6309, .NumOperands: 4, .NumConds: 7 }, |
| 18398 | // AArch64::STNT1B_4Z_IMM - 971 |
| 18399 | {.AsmStrOffset: 16467, .AliasCondStart: 6316, .NumOperands: 4, .NumConds: 8 }, |
| 18400 | // AArch64::STNT1B_4Z_STRIDED_IMM - 972 |
| 18401 | {.AsmStrOffset: 16515, .AliasCondStart: 6324, .NumOperands: 4, .NumConds: 7 }, |
| 18402 | // AArch64::STNT1B_ZRI - 973 |
| 18403 | {.AsmStrOffset: 16539, .AliasCondStart: 6331, .NumOperands: 4, .NumConds: 8 }, |
| 18404 | // AArch64::STNT1B_ZZR_D - 974 |
| 18405 | {.AsmStrOffset: 16563, .AliasCondStart: 6339, .NumOperands: 4, .NumConds: 7 }, |
| 18406 | // AArch64::STNT1B_ZZR_S - 975 |
| 18407 | {.AsmStrOffset: 16589, .AliasCondStart: 6346, .NumOperands: 4, .NumConds: 7 }, |
| 18408 | // AArch64::STNT1D_2Z_IMM - 976 |
| 18409 | {.AsmStrOffset: 16615, .AliasCondStart: 6353, .NumOperands: 4, .NumConds: 8 }, |
| 18410 | // AArch64::STNT1D_2Z_STRIDED_IMM - 977 |
| 18411 | {.AsmStrOffset: 16639, .AliasCondStart: 6361, .NumOperands: 4, .NumConds: 7 }, |
| 18412 | // AArch64::STNT1D_4Z_IMM - 978 |
| 18413 | {.AsmStrOffset: 16615, .AliasCondStart: 6368, .NumOperands: 4, .NumConds: 8 }, |
| 18414 | // AArch64::STNT1D_4Z_STRIDED_IMM - 979 |
| 18415 | {.AsmStrOffset: 16639, .AliasCondStart: 6376, .NumOperands: 4, .NumConds: 7 }, |
| 18416 | // AArch64::STNT1D_ZRI - 980 |
| 18417 | {.AsmStrOffset: 16663, .AliasCondStart: 6383, .NumOperands: 4, .NumConds: 8 }, |
| 18418 | // AArch64::STNT1D_ZZR_D - 981 |
| 18419 | {.AsmStrOffset: 16687, .AliasCondStart: 6391, .NumOperands: 4, .NumConds: 7 }, |
| 18420 | // AArch64::STNT1H_2Z_IMM - 982 |
| 18421 | {.AsmStrOffset: 16713, .AliasCondStart: 6398, .NumOperands: 4, .NumConds: 8 }, |
| 18422 | // AArch64::STNT1H_2Z_STRIDED_IMM - 983 |
| 18423 | {.AsmStrOffset: 16737, .AliasCondStart: 6406, .NumOperands: 4, .NumConds: 7 }, |
| 18424 | // AArch64::STNT1H_4Z_IMM - 984 |
| 18425 | {.AsmStrOffset: 16713, .AliasCondStart: 6413, .NumOperands: 4, .NumConds: 8 }, |
| 18426 | // AArch64::STNT1H_4Z_STRIDED_IMM - 985 |
| 18427 | {.AsmStrOffset: 16761, .AliasCondStart: 6421, .NumOperands: 4, .NumConds: 7 }, |
| 18428 | // AArch64::STNT1H_ZRI - 986 |
| 18429 | {.AsmStrOffset: 16785, .AliasCondStart: 6428, .NumOperands: 4, .NumConds: 8 }, |
| 18430 | // AArch64::STNT1H_ZZR_D - 987 |
| 18431 | {.AsmStrOffset: 16809, .AliasCondStart: 6436, .NumOperands: 4, .NumConds: 7 }, |
| 18432 | // AArch64::STNT1H_ZZR_S - 988 |
| 18433 | {.AsmStrOffset: 16835, .AliasCondStart: 6443, .NumOperands: 4, .NumConds: 7 }, |
| 18434 | // AArch64::STNT1W_2Z_IMM - 989 |
| 18435 | {.AsmStrOffset: 16861, .AliasCondStart: 6450, .NumOperands: 4, .NumConds: 8 }, |
| 18436 | // AArch64::STNT1W_2Z_STRIDED_IMM - 990 |
| 18437 | {.AsmStrOffset: 16885, .AliasCondStart: 6458, .NumOperands: 4, .NumConds: 7 }, |
| 18438 | // AArch64::STNT1W_4Z_IMM - 991 |
| 18439 | {.AsmStrOffset: 16861, .AliasCondStart: 6465, .NumOperands: 4, .NumConds: 8 }, |
| 18440 | // AArch64::STNT1W_4Z_STRIDED_IMM - 992 |
| 18441 | {.AsmStrOffset: 16885, .AliasCondStart: 6473, .NumOperands: 4, .NumConds: 7 }, |
| 18442 | // AArch64::STNT1W_ZRI - 993 |
| 18443 | {.AsmStrOffset: 16909, .AliasCondStart: 6480, .NumOperands: 4, .NumConds: 8 }, |
| 18444 | // AArch64::STNT1W_ZZR_D - 994 |
| 18445 | {.AsmStrOffset: 16933, .AliasCondStart: 6488, .NumOperands: 4, .NumConds: 7 }, |
| 18446 | // AArch64::STNT1W_ZZR_S - 995 |
| 18447 | {.AsmStrOffset: 16959, .AliasCondStart: 6495, .NumOperands: 4, .NumConds: 7 }, |
| 18448 | // AArch64::STPDi - 996 |
| 18449 | {.AsmStrOffset: 16985, .AliasCondStart: 6502, .NumOperands: 4, .NumConds: 7 }, |
| 18450 | // AArch64::STPQi - 997 |
| 18451 | {.AsmStrOffset: 16985, .AliasCondStart: 6509, .NumOperands: 4, .NumConds: 7 }, |
| 18452 | // AArch64::STPSi - 998 |
| 18453 | {.AsmStrOffset: 16985, .AliasCondStart: 6516, .NumOperands: 4, .NumConds: 7 }, |
| 18454 | // AArch64::STPWi - 999 |
| 18455 | {.AsmStrOffset: 16985, .AliasCondStart: 6523, .NumOperands: 4, .NumConds: 4 }, |
| 18456 | // AArch64::STPXi - 1000 |
| 18457 | {.AsmStrOffset: 16985, .AliasCondStart: 6527, .NumOperands: 4, .NumConds: 4 }, |
| 18458 | // AArch64::STRBBroX - 1001 |
| 18459 | {.AsmStrOffset: 17002, .AliasCondStart: 6531, .NumOperands: 5, .NumConds: 5 }, |
| 18460 | // AArch64::STRBBui - 1002 |
| 18461 | {.AsmStrOffset: 17020, .AliasCondStart: 6536, .NumOperands: 3, .NumConds: 3 }, |
| 18462 | // AArch64::STRBroX - 1003 |
| 18463 | {.AsmStrOffset: 17034, .AliasCondStart: 6539, .NumOperands: 5, .NumConds: 8 }, |
| 18464 | // AArch64::STRBui - 1004 |
| 18465 | {.AsmStrOffset: 17051, .AliasCondStart: 6547, .NumOperands: 3, .NumConds: 6 }, |
| 18466 | // AArch64::STRDroX - 1005 |
| 18467 | {.AsmStrOffset: 17034, .AliasCondStart: 6553, .NumOperands: 5, .NumConds: 8 }, |
| 18468 | // AArch64::STRDui - 1006 |
| 18469 | {.AsmStrOffset: 17051, .AliasCondStart: 6561, .NumOperands: 3, .NumConds: 6 }, |
| 18470 | // AArch64::STRHHroX - 1007 |
| 18471 | {.AsmStrOffset: 17064, .AliasCondStart: 6567, .NumOperands: 5, .NumConds: 5 }, |
| 18472 | // AArch64::STRHHui - 1008 |
| 18473 | {.AsmStrOffset: 17082, .AliasCondStart: 6572, .NumOperands: 3, .NumConds: 3 }, |
| 18474 | // AArch64::STRHroX - 1009 |
| 18475 | {.AsmStrOffset: 17034, .AliasCondStart: 6575, .NumOperands: 5, .NumConds: 8 }, |
| 18476 | // AArch64::STRHui - 1010 |
| 18477 | {.AsmStrOffset: 17051, .AliasCondStart: 6583, .NumOperands: 3, .NumConds: 6 }, |
| 18478 | // AArch64::STRQroX - 1011 |
| 18479 | {.AsmStrOffset: 17034, .AliasCondStart: 6589, .NumOperands: 5, .NumConds: 8 }, |
| 18480 | // AArch64::STRQui - 1012 |
| 18481 | {.AsmStrOffset: 17051, .AliasCondStart: 6597, .NumOperands: 3, .NumConds: 6 }, |
| 18482 | // AArch64::STRSroX - 1013 |
| 18483 | {.AsmStrOffset: 17034, .AliasCondStart: 6603, .NumOperands: 5, .NumConds: 8 }, |
| 18484 | // AArch64::STRSui - 1014 |
| 18485 | {.AsmStrOffset: 17051, .AliasCondStart: 6611, .NumOperands: 3, .NumConds: 6 }, |
| 18486 | // AArch64::STRWroX - 1015 |
| 18487 | {.AsmStrOffset: 17034, .AliasCondStart: 6617, .NumOperands: 5, .NumConds: 5 }, |
| 18488 | // AArch64::STRWui - 1016 |
| 18489 | {.AsmStrOffset: 17051, .AliasCondStart: 6622, .NumOperands: 3, .NumConds: 3 }, |
| 18490 | // AArch64::STRXroX - 1017 |
| 18491 | {.AsmStrOffset: 17034, .AliasCondStart: 6625, .NumOperands: 5, .NumConds: 5 }, |
| 18492 | // AArch64::STRXui - 1018 |
| 18493 | {.AsmStrOffset: 17051, .AliasCondStart: 6630, .NumOperands: 3, .NumConds: 3 }, |
| 18494 | // AArch64::STR_PXI - 1019 |
| 18495 | {.AsmStrOffset: 17096, .AliasCondStart: 6633, .NumOperands: 3, .NumConds: 7 }, |
| 18496 | // AArch64::STR_ZA - 1020 |
| 18497 | {.AsmStrOffset: 17111, .AliasCondStart: 6640, .NumOperands: 5, .NumConds: 8 }, |
| 18498 | // AArch64::STR_ZXI - 1021 |
| 18499 | {.AsmStrOffset: 17096, .AliasCondStart: 6648, .NumOperands: 3, .NumConds: 7 }, |
| 18500 | // AArch64::STTNPQi - 1022 |
| 18501 | {.AsmStrOffset: 17136, .AliasCondStart: 6655, .NumOperands: 4, .NumConds: 10 }, |
| 18502 | // AArch64::STTNPXi - 1023 |
| 18503 | {.AsmStrOffset: 17136, .AliasCondStart: 6665, .NumOperands: 4, .NumConds: 7 }, |
| 18504 | // AArch64::STTPQi - 1024 |
| 18505 | {.AsmStrOffset: 17155, .AliasCondStart: 6672, .NumOperands: 4, .NumConds: 10 }, |
| 18506 | // AArch64::STTPi - 1025 |
| 18507 | {.AsmStrOffset: 17155, .AliasCondStart: 6682, .NumOperands: 4, .NumConds: 7 }, |
| 18508 | // AArch64::STTRBi - 1026 |
| 18509 | {.AsmStrOffset: 17173, .AliasCondStart: 6689, .NumOperands: 3, .NumConds: 3 }, |
| 18510 | // AArch64::STTRHi - 1027 |
| 18511 | {.AsmStrOffset: 17188, .AliasCondStart: 6692, .NumOperands: 3, .NumConds: 3 }, |
| 18512 | // AArch64::STTRWi - 1028 |
| 18513 | {.AsmStrOffset: 17203, .AliasCondStart: 6695, .NumOperands: 3, .NumConds: 3 }, |
| 18514 | // AArch64::STTRXi - 1029 |
| 18515 | {.AsmStrOffset: 17203, .AliasCondStart: 6698, .NumOperands: 3, .NumConds: 3 }, |
| 18516 | // AArch64::STURBBi - 1030 |
| 18517 | {.AsmStrOffset: 17217, .AliasCondStart: 6701, .NumOperands: 3, .NumConds: 3 }, |
| 18518 | // AArch64::STURBi - 1031 |
| 18519 | {.AsmStrOffset: 17232, .AliasCondStart: 6704, .NumOperands: 3, .NumConds: 6 }, |
| 18520 | // AArch64::STURDi - 1032 |
| 18521 | {.AsmStrOffset: 17232, .AliasCondStart: 6710, .NumOperands: 3, .NumConds: 6 }, |
| 18522 | // AArch64::STURHHi - 1033 |
| 18523 | {.AsmStrOffset: 17246, .AliasCondStart: 6716, .NumOperands: 3, .NumConds: 3 }, |
| 18524 | // AArch64::STURHi - 1034 |
| 18525 | {.AsmStrOffset: 17232, .AliasCondStart: 6719, .NumOperands: 3, .NumConds: 6 }, |
| 18526 | // AArch64::STURQi - 1035 |
| 18527 | {.AsmStrOffset: 17232, .AliasCondStart: 6725, .NumOperands: 3, .NumConds: 6 }, |
| 18528 | // AArch64::STURSi - 1036 |
| 18529 | {.AsmStrOffset: 17232, .AliasCondStart: 6731, .NumOperands: 3, .NumConds: 6 }, |
| 18530 | // AArch64::STURWi - 1037 |
| 18531 | {.AsmStrOffset: 17232, .AliasCondStart: 6737, .NumOperands: 3, .NumConds: 3 }, |
| 18532 | // AArch64::STURXi - 1038 |
| 18533 | {.AsmStrOffset: 17232, .AliasCondStart: 6740, .NumOperands: 3, .NumConds: 3 }, |
| 18534 | // AArch64::STZ2Gi - 1039 |
| 18535 | {.AsmStrOffset: 17261, .AliasCondStart: 6743, .NumOperands: 3, .NumConds: 6 }, |
| 18536 | // AArch64::STZGi - 1040 |
| 18537 | {.AsmStrOffset: 17276, .AliasCondStart: 6749, .NumOperands: 3, .NumConds: 6 }, |
| 18538 | // AArch64::SUBPT_shift - 1041 |
| 18539 | {.AsmStrOffset: 17290, .AliasCondStart: 6755, .NumOperands: 4, .NumConds: 7 }, |
| 18540 | // AArch64::SUBSWri - 1042 |
| 18541 | {.AsmStrOffset: 17307, .AliasCondStart: 6762, .NumOperands: 4, .NumConds: 2 }, |
| 18542 | // AArch64::SUBSWrs - 1043 |
| 18543 | {.AsmStrOffset: 17320, .AliasCondStart: 6764, .NumOperands: 4, .NumConds: 4 }, |
| 18544 | {.AsmStrOffset: 17331, .AliasCondStart: 6768, .NumOperands: 4, .NumConds: 3 }, |
| 18545 | {.AsmStrOffset: 17346, .AliasCondStart: 6771, .NumOperands: 4, .NumConds: 4 }, |
| 18546 | {.AsmStrOffset: 17358, .AliasCondStart: 6775, .NumOperands: 4, .NumConds: 3 }, |
| 18547 | {.AsmStrOffset: 17374, .AliasCondStart: 6778, .NumOperands: 4, .NumConds: 4 }, |
| 18548 | // AArch64::SUBSWrx - 1048 |
| 18549 | {.AsmStrOffset: 17320, .AliasCondStart: 6782, .NumOperands: 4, .NumConds: 4 }, |
| 18550 | {.AsmStrOffset: 17390, .AliasCondStart: 6786, .NumOperands: 4, .NumConds: 3 }, |
| 18551 | {.AsmStrOffset: 17374, .AliasCondStart: 6789, .NumOperands: 4, .NumConds: 4 }, |
| 18552 | // AArch64::SUBSXri - 1051 |
| 18553 | {.AsmStrOffset: 17307, .AliasCondStart: 6793, .NumOperands: 4, .NumConds: 2 }, |
| 18554 | // AArch64::SUBSXrs - 1052 |
| 18555 | {.AsmStrOffset: 17320, .AliasCondStart: 6795, .NumOperands: 4, .NumConds: 4 }, |
| 18556 | {.AsmStrOffset: 17331, .AliasCondStart: 6799, .NumOperands: 4, .NumConds: 3 }, |
| 18557 | {.AsmStrOffset: 17346, .AliasCondStart: 6802, .NumOperands: 4, .NumConds: 4 }, |
| 18558 | {.AsmStrOffset: 17358, .AliasCondStart: 6806, .NumOperands: 4, .NumConds: 3 }, |
| 18559 | {.AsmStrOffset: 17374, .AliasCondStart: 6809, .NumOperands: 4, .NumConds: 4 }, |
| 18560 | // AArch64::SUBSXrx - 1057 |
| 18561 | {.AsmStrOffset: 17390, .AliasCondStart: 6813, .NumOperands: 4, .NumConds: 3 }, |
| 18562 | // AArch64::SUBSXrx64 - 1058 |
| 18563 | {.AsmStrOffset: 17320, .AliasCondStart: 6816, .NumOperands: 4, .NumConds: 4 }, |
| 18564 | {.AsmStrOffset: 17390, .AliasCondStart: 6820, .NumOperands: 4, .NumConds: 3 }, |
| 18565 | {.AsmStrOffset: 17374, .AliasCondStart: 6823, .NumOperands: 4, .NumConds: 4 }, |
| 18566 | // AArch64::SUBWrs - 1061 |
| 18567 | {.AsmStrOffset: 17405, .AliasCondStart: 6827, .NumOperands: 4, .NumConds: 4 }, |
| 18568 | {.AsmStrOffset: 17416, .AliasCondStart: 6831, .NumOperands: 4, .NumConds: 3 }, |
| 18569 | {.AsmStrOffset: 17431, .AliasCondStart: 6834, .NumOperands: 4, .NumConds: 4 }, |
| 18570 | // AArch64::SUBWrx - 1064 |
| 18571 | {.AsmStrOffset: 17431, .AliasCondStart: 6838, .NumOperands: 4, .NumConds: 4 }, |
| 18572 | {.AsmStrOffset: 17431, .AliasCondStart: 6842, .NumOperands: 4, .NumConds: 4 }, |
| 18573 | // AArch64::SUBXrs - 1066 |
| 18574 | {.AsmStrOffset: 17405, .AliasCondStart: 6846, .NumOperands: 4, .NumConds: 4 }, |
| 18575 | {.AsmStrOffset: 17416, .AliasCondStart: 6850, .NumOperands: 4, .NumConds: 3 }, |
| 18576 | {.AsmStrOffset: 17431, .AliasCondStart: 6853, .NumOperands: 4, .NumConds: 4 }, |
| 18577 | // AArch64::SUBXrx64 - 1069 |
| 18578 | {.AsmStrOffset: 17431, .AliasCondStart: 6857, .NumOperands: 4, .NumConds: 4 }, |
| 18579 | {.AsmStrOffset: 17431, .AliasCondStart: 6861, .NumOperands: 4, .NumConds: 4 }, |
| 18580 | // AArch64::SYSPxt_XZR - 1071 |
| 18581 | {.AsmStrOffset: 17446, .AliasCondStart: 6865, .NumOperands: 5, .NumConds: 5 }, |
| 18582 | // AArch64::SYSxt - 1072 |
| 18583 | {.AsmStrOffset: 17470, .AliasCondStart: 6870, .NumOperands: 5, .NumConds: 5 }, |
| 18584 | {.AsmStrOffset: 17478, .AliasCondStart: 6875, .NumOperands: 5, .NumConds: 8 }, |
| 18585 | {.AsmStrOffset: 17487, .AliasCondStart: 6883, .NumOperands: 5, .NumConds: 8 }, |
| 18586 | {.AsmStrOffset: 17495, .AliasCondStart: 6891, .NumOperands: 5, .NumConds: 8 }, |
| 18587 | {.AsmStrOffset: 17504, .AliasCondStart: 6899, .NumOperands: 5, .NumConds: 5 }, |
| 18588 | // AArch64::TCHANGEBri - 1077 |
| 18589 | {.AsmStrOffset: 17527, .AliasCondStart: 6904, .NumOperands: 3, .NumConds: 6 }, |
| 18590 | // AArch64::TCHANGEBrr - 1078 |
| 18591 | {.AsmStrOffset: 17545, .AliasCondStart: 6910, .NumOperands: 3, .NumConds: 6 }, |
| 18592 | // AArch64::TCHANGEFri - 1079 |
| 18593 | {.AsmStrOffset: 17561, .AliasCondStart: 6916, .NumOperands: 3, .NumConds: 6 }, |
| 18594 | // AArch64::TCHANGEFrr - 1080 |
| 18595 | {.AsmStrOffset: 17579, .AliasCondStart: 6922, .NumOperands: 3, .NumConds: 6 }, |
| 18596 | // AArch64::TENTER - 1081 |
| 18597 | {.AsmStrOffset: 17595, .AliasCondStart: 6928, .NumOperands: 2, .NumConds: 5 }, |
| 18598 | // AArch64::TEXIT - 1082 |
| 18599 | {.AsmStrOffset: 17607, .AliasCondStart: 6933, .NumOperands: 1, .NumConds: 4 }, |
| 18600 | // AArch64::TFLTNZ - 1083 |
| 18601 | {.AsmStrOffset: 17613, .AliasCondStart: 6937, .NumOperands: 3, .NumConds: 6 }, |
| 18602 | // AArch64::TFLTZ - 1084 |
| 18603 | {.AsmStrOffset: 17633, .AliasCondStart: 6943, .NumOperands: 3, .NumConds: 6 }, |
| 18604 | // AArch64::UBFMWri - 1085 |
| 18605 | {.AsmStrOffset: 17652, .AliasCondStart: 6949, .NumOperands: 4, .NumConds: 4 }, |
| 18606 | {.AsmStrOffset: 17667, .AliasCondStart: 6953, .NumOperands: 4, .NumConds: 4 }, |
| 18607 | {.AsmStrOffset: 17679, .AliasCondStart: 6957, .NumOperands: 4, .NumConds: 4 }, |
| 18608 | // AArch64::UBFMXri - 1088 |
| 18609 | {.AsmStrOffset: 17652, .AliasCondStart: 6961, .NumOperands: 4, .NumConds: 4 }, |
| 18610 | {.AsmStrOffset: 17667, .AliasCondStart: 6965, .NumOperands: 4, .NumConds: 4 }, |
| 18611 | {.AsmStrOffset: 17679, .AliasCondStart: 6969, .NumOperands: 4, .NumConds: 4 }, |
| 18612 | {.AsmStrOffset: 17691, .AliasCondStart: 6973, .NumOperands: 4, .NumConds: 4 }, |
| 18613 | // AArch64::UMADDLrrr - 1092 |
| 18614 | {.AsmStrOffset: 17703, .AliasCondStart: 6977, .NumOperands: 4, .NumConds: 4 }, |
| 18615 | // AArch64::UMOVvi32 - 1093 |
| 18616 | {.AsmStrOffset: 17720, .AliasCondStart: 6981, .NumOperands: 3, .NumConds: 5 }, |
| 18617 | // AArch64::UMOVvi32_idx0 - 1094 |
| 18618 | {.AsmStrOffset: 17720, .AliasCondStart: 6986, .NumOperands: 3, .NumConds: 5 }, |
| 18619 | // AArch64::UMOVvi64 - 1095 |
| 18620 | {.AsmStrOffset: 17739, .AliasCondStart: 6991, .NumOperands: 3, .NumConds: 5 }, |
| 18621 | // AArch64::UMOVvi64_idx0 - 1096 |
| 18622 | {.AsmStrOffset: 17739, .AliasCondStart: 6996, .NumOperands: 3, .NumConds: 5 }, |
| 18623 | // AArch64::UMSUBLrrr - 1097 |
| 18624 | {.AsmStrOffset: 17758, .AliasCondStart: 7001, .NumOperands: 4, .NumConds: 4 }, |
| 18625 | // AArch64::UQDECB_WPiI - 1098 |
| 18626 | {.AsmStrOffset: 17776, .AliasCondStart: 7005, .NumOperands: 4, .NumConds: 8 }, |
| 18627 | {.AsmStrOffset: 17786, .AliasCondStart: 7013, .NumOperands: 4, .NumConds: 8 }, |
| 18628 | // AArch64::UQDECB_XPiI - 1100 |
| 18629 | {.AsmStrOffset: 17776, .AliasCondStart: 7021, .NumOperands: 4, .NumConds: 8 }, |
| 18630 | {.AsmStrOffset: 17786, .AliasCondStart: 7029, .NumOperands: 4, .NumConds: 8 }, |
| 18631 | // AArch64::UQDECD_WPiI - 1102 |
| 18632 | {.AsmStrOffset: 17802, .AliasCondStart: 7037, .NumOperands: 4, .NumConds: 8 }, |
| 18633 | {.AsmStrOffset: 17812, .AliasCondStart: 7045, .NumOperands: 4, .NumConds: 8 }, |
| 18634 | // AArch64::UQDECD_XPiI - 1104 |
| 18635 | {.AsmStrOffset: 17802, .AliasCondStart: 7053, .NumOperands: 4, .NumConds: 8 }, |
| 18636 | {.AsmStrOffset: 17812, .AliasCondStart: 7061, .NumOperands: 4, .NumConds: 8 }, |
| 18637 | // AArch64::UQDECD_ZPiI - 1106 |
| 18638 | {.AsmStrOffset: 17828, .AliasCondStart: 7069, .NumOperands: 4, .NumConds: 8 }, |
| 18639 | {.AsmStrOffset: 17840, .AliasCondStart: 7077, .NumOperands: 4, .NumConds: 8 }, |
| 18640 | // AArch64::UQDECH_WPiI - 1108 |
| 18641 | {.AsmStrOffset: 17858, .AliasCondStart: 7085, .NumOperands: 4, .NumConds: 8 }, |
| 18642 | {.AsmStrOffset: 17868, .AliasCondStart: 7093, .NumOperands: 4, .NumConds: 8 }, |
| 18643 | // AArch64::UQDECH_XPiI - 1110 |
| 18644 | {.AsmStrOffset: 17858, .AliasCondStart: 7101, .NumOperands: 4, .NumConds: 8 }, |
| 18645 | {.AsmStrOffset: 17868, .AliasCondStart: 7109, .NumOperands: 4, .NumConds: 8 }, |
| 18646 | // AArch64::UQDECH_ZPiI - 1112 |
| 18647 | {.AsmStrOffset: 17884, .AliasCondStart: 7117, .NumOperands: 4, .NumConds: 8 }, |
| 18648 | {.AsmStrOffset: 17896, .AliasCondStart: 7125, .NumOperands: 4, .NumConds: 8 }, |
| 18649 | // AArch64::UQDECW_WPiI - 1114 |
| 18650 | {.AsmStrOffset: 17914, .AliasCondStart: 7133, .NumOperands: 4, .NumConds: 8 }, |
| 18651 | {.AsmStrOffset: 17924, .AliasCondStart: 7141, .NumOperands: 4, .NumConds: 8 }, |
| 18652 | // AArch64::UQDECW_XPiI - 1116 |
| 18653 | {.AsmStrOffset: 17914, .AliasCondStart: 7149, .NumOperands: 4, .NumConds: 8 }, |
| 18654 | {.AsmStrOffset: 17924, .AliasCondStart: 7157, .NumOperands: 4, .NumConds: 8 }, |
| 18655 | // AArch64::UQDECW_ZPiI - 1118 |
| 18656 | {.AsmStrOffset: 17940, .AliasCondStart: 7165, .NumOperands: 4, .NumConds: 8 }, |
| 18657 | {.AsmStrOffset: 17952, .AliasCondStart: 7173, .NumOperands: 4, .NumConds: 8 }, |
| 18658 | // AArch64::UQINCB_WPiI - 1120 |
| 18659 | {.AsmStrOffset: 17970, .AliasCondStart: 7181, .NumOperands: 4, .NumConds: 8 }, |
| 18660 | {.AsmStrOffset: 17980, .AliasCondStart: 7189, .NumOperands: 4, .NumConds: 8 }, |
| 18661 | // AArch64::UQINCB_XPiI - 1122 |
| 18662 | {.AsmStrOffset: 17970, .AliasCondStart: 7197, .NumOperands: 4, .NumConds: 8 }, |
| 18663 | {.AsmStrOffset: 17980, .AliasCondStart: 7205, .NumOperands: 4, .NumConds: 8 }, |
| 18664 | // AArch64::UQINCD_WPiI - 1124 |
| 18665 | {.AsmStrOffset: 17996, .AliasCondStart: 7213, .NumOperands: 4, .NumConds: 8 }, |
| 18666 | {.AsmStrOffset: 18006, .AliasCondStart: 7221, .NumOperands: 4, .NumConds: 8 }, |
| 18667 | // AArch64::UQINCD_XPiI - 1126 |
| 18668 | {.AsmStrOffset: 17996, .AliasCondStart: 7229, .NumOperands: 4, .NumConds: 8 }, |
| 18669 | {.AsmStrOffset: 18006, .AliasCondStart: 7237, .NumOperands: 4, .NumConds: 8 }, |
| 18670 | // AArch64::UQINCD_ZPiI - 1128 |
| 18671 | {.AsmStrOffset: 18022, .AliasCondStart: 7245, .NumOperands: 4, .NumConds: 8 }, |
| 18672 | {.AsmStrOffset: 18034, .AliasCondStart: 7253, .NumOperands: 4, .NumConds: 8 }, |
| 18673 | // AArch64::UQINCH_WPiI - 1130 |
| 18674 | {.AsmStrOffset: 18052, .AliasCondStart: 7261, .NumOperands: 4, .NumConds: 8 }, |
| 18675 | {.AsmStrOffset: 18062, .AliasCondStart: 7269, .NumOperands: 4, .NumConds: 8 }, |
| 18676 | // AArch64::UQINCH_XPiI - 1132 |
| 18677 | {.AsmStrOffset: 18052, .AliasCondStart: 7277, .NumOperands: 4, .NumConds: 8 }, |
| 18678 | {.AsmStrOffset: 18062, .AliasCondStart: 7285, .NumOperands: 4, .NumConds: 8 }, |
| 18679 | // AArch64::UQINCH_ZPiI - 1134 |
| 18680 | {.AsmStrOffset: 18078, .AliasCondStart: 7293, .NumOperands: 4, .NumConds: 8 }, |
| 18681 | {.AsmStrOffset: 18090, .AliasCondStart: 7301, .NumOperands: 4, .NumConds: 8 }, |
| 18682 | // AArch64::UQINCW_WPiI - 1136 |
| 18683 | {.AsmStrOffset: 18108, .AliasCondStart: 7309, .NumOperands: 4, .NumConds: 8 }, |
| 18684 | {.AsmStrOffset: 18118, .AliasCondStart: 7317, .NumOperands: 4, .NumConds: 8 }, |
| 18685 | // AArch64::UQINCW_XPiI - 1138 |
| 18686 | {.AsmStrOffset: 18108, .AliasCondStart: 7325, .NumOperands: 4, .NumConds: 8 }, |
| 18687 | {.AsmStrOffset: 18118, .AliasCondStart: 7333, .NumOperands: 4, .NumConds: 8 }, |
| 18688 | // AArch64::UQINCW_ZPiI - 1140 |
| 18689 | {.AsmStrOffset: 18134, .AliasCondStart: 7341, .NumOperands: 4, .NumConds: 8 }, |
| 18690 | {.AsmStrOffset: 18146, .AliasCondStart: 7349, .NumOperands: 4, .NumConds: 8 }, |
| 18691 | // AArch64::XPACLRI - 1142 |
| 18692 | {.AsmStrOffset: 18164, .AliasCondStart: 7357, .NumOperands: 0, .NumConds: 3 }, |
| 18693 | // AArch64::ZERO_M - 1143 |
| 18694 | {.AsmStrOffset: 18172, .AliasCondStart: 7360, .NumOperands: 1, .NumConds: 4 }, |
| 18695 | {.AsmStrOffset: 18182, .AliasCondStart: 7364, .NumOperands: 1, .NumConds: 4 }, |
| 18696 | {.AsmStrOffset: 18195, .AliasCondStart: 7368, .NumOperands: 1, .NumConds: 4 }, |
| 18697 | {.AsmStrOffset: 18208, .AliasCondStart: 7372, .NumOperands: 1, .NumConds: 4 }, |
| 18698 | {.AsmStrOffset: 18221, .AliasCondStart: 7376, .NumOperands: 1, .NumConds: 4 }, |
| 18699 | {.AsmStrOffset: 18234, .AliasCondStart: 7380, .NumOperands: 1, .NumConds: 4 }, |
| 18700 | {.AsmStrOffset: 18247, .AliasCondStart: 7384, .NumOperands: 1, .NumConds: 4 }, |
| 18701 | {.AsmStrOffset: 18260, .AliasCondStart: 7388, .NumOperands: 1, .NumConds: 4 }, |
| 18702 | {.AsmStrOffset: 18279, .AliasCondStart: 7392, .NumOperands: 1, .NumConds: 4 }, |
| 18703 | {.AsmStrOffset: 18298, .AliasCondStart: 7396, .NumOperands: 1, .NumConds: 4 }, |
| 18704 | {.AsmStrOffset: 18317, .AliasCondStart: 7400, .NumOperands: 1, .NumConds: 4 }, |
| 18705 | {.AsmStrOffset: 18336, .AliasCondStart: 7404, .NumOperands: 1, .NumConds: 4 }, |
| 18706 | {.AsmStrOffset: 18361, .AliasCondStart: 7408, .NumOperands: 1, .NumConds: 4 }, |
| 18707 | {.AsmStrOffset: 18386, .AliasCondStart: 7412, .NumOperands: 1, .NumConds: 4 }, |
| 18708 | {.AsmStrOffset: 18411, .AliasCondStart: 7416, .NumOperands: 1, .NumConds: 4 }, |
| 18709 | }; |
| 18710 | |
| 18711 | static const AliasPatternCond Conds[] = { |
| 18712 | // (ADDPT_shift GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0) - 0 |
| 18713 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 18714 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 18715 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18716 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18717 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18718 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCPA}, |
| 18719 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18720 | // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 7 |
| 18721 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 18722 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 18723 | // (ADDSWrs WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 9 |
| 18724 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 18725 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18726 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18727 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18728 | // (ADDSWrs WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, arith_shift32:$sh)) - 13 |
| 18729 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 18730 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18732 | // (ADDSWrs GPR32:$dst, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 16 |
| 18733 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18734 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18735 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18736 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18737 | // (ADDSWrx WZR, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 20 |
| 18738 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 18739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 18740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18741 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 18742 | // (ADDSWrx WZR, GPR32sp:$src1, (arith_extended_reg32_i32 GPR32:$src2, arith_extend:$sh)) - 24 |
| 18743 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 18744 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 18745 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18746 | // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 27 |
| 18747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 18749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18750 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 18751 | // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 31 |
| 18752 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 18753 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 18754 | // (ADDSXrs XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 33 |
| 18755 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 18756 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18758 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18759 | // (ADDSXrs XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, arith_shift64:$sh)) - 37 |
| 18760 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 18761 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18762 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18763 | // (ADDSXrs GPR64:$dst, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 40 |
| 18764 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18765 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18767 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18768 | // (ADDSXrx XZR, GPR64sp:$src1, (arith_extended_reg32_i64 GPR32:$src2, arith_extend:$sh)) - 44 |
| 18769 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 18770 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 18771 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18772 | // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 47 |
| 18773 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 18774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 18775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18776 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 18777 | // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 51 |
| 18778 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 18779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 18780 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18781 | // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 54 |
| 18782 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 18784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18785 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 18786 | // (ADDWri GPR32sponly:$dst, GPR32sp:$src, (addsub_shifted_imm32 0, 0)) - 58 |
| 18787 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 18788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 18789 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18790 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18791 | // (ADDWri GPR32sp:$dst, GPR32sponly:$src, (addsub_shifted_imm32 0, 0)) - 62 |
| 18792 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 18793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 18794 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18795 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18796 | // (ADDWrs GPR32:$dst, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 66 |
| 18797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18800 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18801 | // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 70 |
| 18802 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 18803 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 18804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18805 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 18806 | // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 74 |
| 18807 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 18808 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 18809 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18810 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 18811 | // (ADDXri GPR64sponly:$dst, GPR64sp:$src, (addsub_shifted_imm64 0, 0)) - 78 |
| 18812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 18813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 18814 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18815 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18816 | // (ADDXri GPR64sp:$dst, GPR64sponly:$src, (addsub_shifted_imm64 0, 0)) - 82 |
| 18817 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 18818 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 18819 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18820 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18821 | // (ADDXrs GPR64:$dst, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 86 |
| 18822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18823 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18824 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18825 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18826 | // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 90 |
| 18827 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 18828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 18829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18830 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 18831 | // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 94 |
| 18832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 18833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 18834 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18835 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 18836 | // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 98 |
| 18837 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 18838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18839 | // (ANDSWrs WZR, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 100 |
| 18840 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 18841 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18843 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18844 | // (ANDSWrs WZR, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, logical_shift32:$sh)) - 104 |
| 18845 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 18846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18848 | // (ANDSWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 107 |
| 18849 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18850 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18851 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18852 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18853 | // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 111 |
| 18854 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 18855 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18856 | // (ANDSXrs XZR, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 113 |
| 18857 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 18858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18859 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18860 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18861 | // (ANDSXrs XZR, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, logical_shift64:$sh)) - 117 |
| 18862 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 18863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18865 | // (ANDSXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 120 |
| 18866 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18867 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18868 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18869 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18870 | // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 124 |
| 18871 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 18872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 18873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 18874 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 2}, |
| 18875 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18876 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 18877 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 18878 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18879 | // (ANDWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 132 |
| 18880 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18881 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18882 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18883 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18884 | // (ANDXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 136 |
| 18885 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18887 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18888 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18889 | // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 140 |
| 18890 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 18891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 18892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 18893 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 2}, |
| 18894 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18895 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 18896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 18897 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18898 | // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 148 |
| 18899 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 18900 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 18901 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 18902 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18903 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 18904 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 18905 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18906 | // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 155 |
| 18907 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 18908 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 18909 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 18910 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18911 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 18912 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 18913 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18914 | // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 162 |
| 18915 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 18916 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 18917 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 18918 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18919 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 18920 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 18921 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18922 | // (AUTIA1716) - 169 |
| 18923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 18925 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18926 | // (AUTIASP) - 172 |
| 18927 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18928 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 18929 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18930 | // (AUTIAZ) - 175 |
| 18931 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 18933 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18934 | // (AUTIB1716) - 178 |
| 18935 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18936 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 18937 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18938 | // (AUTIBSP) - 181 |
| 18939 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18940 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 18941 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18942 | // (AUTIBZ) - 184 |
| 18943 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18944 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 18945 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18946 | // (BICSWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 187 |
| 18947 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18948 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18949 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18950 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18951 | // (BICSXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 191 |
| 18952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18955 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18956 | // (BICWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 195 |
| 18957 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18958 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 18960 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18961 | // (BICXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 199 |
| 18962 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18963 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18964 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18965 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 18966 | // (CHKFEAT) - 203 |
| 18967 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18968 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCHK}, |
| 18969 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18970 | // (CLREX 15) - 206 |
| 18971 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 18972 | // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 207 |
| 18973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18974 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 18975 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 18976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 18978 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 18979 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18980 | // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 214 |
| 18981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18982 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 18983 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 18984 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18985 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 18986 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 18987 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18988 | // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 221 |
| 18989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18990 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 18991 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 18992 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 18993 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 18994 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 18995 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 18996 | // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 228 |
| 18997 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 18998 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 18999 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19001 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19002 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19003 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19004 | // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 235 |
| 19005 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19006 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 19007 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19008 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19009 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19011 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19012 | // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 242 |
| 19013 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19014 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19015 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19016 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19017 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19018 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19019 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19020 | // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 249 |
| 19021 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19022 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 19023 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19026 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19027 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19028 | // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 256 |
| 19029 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19030 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19031 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19034 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19035 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19036 | // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 263 |
| 19037 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19038 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19039 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19041 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19042 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19043 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19044 | // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 270 |
| 19045 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19046 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19047 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19051 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19052 | // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 277 |
| 19053 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19054 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19055 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19056 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19057 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19059 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19060 | // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 284 |
| 19061 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19062 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19065 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19066 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19067 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19068 | // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 291 |
| 19069 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19070 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19071 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19072 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 19073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19074 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19075 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19076 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19077 | // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 299 |
| 19078 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19079 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19080 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19081 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 19082 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19083 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19084 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19085 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19086 | // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 307 |
| 19087 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19088 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19089 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 19091 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19092 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19093 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19094 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19095 | // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 315 |
| 19096 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19097 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19098 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19099 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 19100 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19101 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19102 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19103 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19104 | // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 323 |
| 19105 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19106 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19107 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19108 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 19109 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19112 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19113 | // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 331 |
| 19114 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19115 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19116 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19117 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 19118 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19121 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19122 | // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 339 |
| 19123 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19124 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19126 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 19127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19128 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19129 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19130 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19131 | // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 347 |
| 19132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19133 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19134 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19135 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 19136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19137 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19138 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19139 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19140 | // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 355 |
| 19141 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19142 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19143 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19146 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19147 | // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 361 |
| 19148 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19149 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19150 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19151 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19153 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19154 | // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 367 |
| 19155 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19156 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19157 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19160 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19161 | // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 373 |
| 19162 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19163 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19164 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19165 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19167 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19168 | // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 379 |
| 19169 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19170 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 19171 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 19172 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19173 | // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 383 |
| 19174 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19175 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19176 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19177 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19178 | // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 387 |
| 19179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19180 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 19181 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 19182 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19183 | // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 391 |
| 19184 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19185 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19186 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19187 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19188 | // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 395 |
| 19189 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19190 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 19191 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 19192 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19193 | // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 399 |
| 19194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19196 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19197 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19198 | // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 403 |
| 19199 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19200 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 19201 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 19202 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19203 | // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 407 |
| 19204 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19205 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19206 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19207 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19208 | // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 411 |
| 19209 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19211 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19212 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19213 | // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 415 |
| 19214 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19215 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19216 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19217 | {.Kind: AliasPatternCond::K_Custom, .Value: 4}, |
| 19218 | // (DCPS1 0) - 419 |
| 19219 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19220 | // (DCPS2 0) - 420 |
| 19221 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19222 | // (DCPS3 0) - 421 |
| 19223 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19224 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19225 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureEL3}, |
| 19226 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19227 | // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 425 |
| 19228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19229 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19230 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 19231 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19233 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19234 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19235 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19236 | // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 433 |
| 19237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19238 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19239 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19240 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19241 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19242 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19243 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19244 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19245 | // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 441 |
| 19246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19247 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19248 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 19249 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19250 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19251 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19252 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19253 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19254 | // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 449 |
| 19255 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19256 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19257 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19258 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19259 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19260 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19261 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19262 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19263 | // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 457 |
| 19264 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19265 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19266 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 19267 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19268 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19269 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19270 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19271 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19272 | // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 465 |
| 19273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19274 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19275 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19276 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19277 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19278 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19279 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19280 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19281 | // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 473 |
| 19282 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19283 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19284 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 19285 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19286 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19287 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19288 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19289 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19290 | // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 481 |
| 19291 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19292 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19293 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19294 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19295 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19296 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19297 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19298 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19299 | // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 489 |
| 19300 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19301 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19302 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 19303 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19304 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19305 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19306 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19307 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19308 | // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 497 |
| 19309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19310 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19311 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19312 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19313 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19314 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19315 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19316 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19317 | // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 505 |
| 19318 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19319 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19320 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 19321 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19323 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19324 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19325 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19326 | // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 513 |
| 19327 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19328 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19329 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19330 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19331 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19332 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19333 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19334 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19335 | // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 521 |
| 19336 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19337 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19338 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 19339 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19340 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19343 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19344 | // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 529 |
| 19345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19346 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19347 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19348 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19349 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19350 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19351 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19352 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19353 | // (DSB 0) - 537 |
| 19354 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19355 | // (DSB 4) - 538 |
| 19356 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 19357 | // (DSB { 1, 1, 0, 0 }) - 539 |
| 19358 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(12)}, |
| 19359 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19360 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::HasV8_0rOps}, |
| 19361 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19362 | // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 543 |
| 19363 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19364 | {.Kind: AliasPatternCond::K_Custom, .Value: 5}, |
| 19365 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19366 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19367 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19368 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19369 | // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 549 |
| 19370 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19371 | {.Kind: AliasPatternCond::K_Custom, .Value: 6}, |
| 19372 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19373 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19374 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19375 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19376 | // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 555 |
| 19377 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19378 | {.Kind: AliasPatternCond::K_Custom, .Value: 7}, |
| 19379 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19380 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19381 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19382 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19383 | // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 561 |
| 19384 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19385 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 19386 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19387 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19388 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19389 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19390 | // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 567 |
| 19391 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19392 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 19393 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19395 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19396 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19397 | // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 573 |
| 19398 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19399 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 19400 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19401 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19402 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19403 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19404 | // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 579 |
| 19405 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19406 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19407 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19408 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19409 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19410 | // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 584 |
| 19411 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19412 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19413 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19414 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19415 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19416 | // (DUP_ZI_D ZPR64:$Zd, (cpy_imm8_opt_lsl_i64 0, 0)) - 589 |
| 19417 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19418 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19419 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19420 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19421 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19422 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19423 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19424 | // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 596 |
| 19425 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19426 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19427 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19428 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19429 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19430 | // (DUP_ZI_H ZPR16:$Zd, (cpy_imm8_opt_lsl_i16 0, 0)) - 601 |
| 19431 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19432 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19433 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19434 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19435 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19436 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19437 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19438 | // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 608 |
| 19439 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19441 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19442 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19443 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19444 | // (DUP_ZI_S ZPR32:$Zd, (cpy_imm8_opt_lsl_i32 0, 0)) - 613 |
| 19445 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19446 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19447 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19448 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19449 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19450 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19451 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19452 | // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 620 |
| 19453 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19454 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 19455 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19456 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19457 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19458 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19459 | // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 626 |
| 19460 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19461 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 19462 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19463 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19464 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19465 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19466 | // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 632 |
| 19467 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19468 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 19469 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19470 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19471 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19472 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19473 | // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 638 |
| 19474 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19475 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 19476 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19477 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19478 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19479 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19480 | // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 644 |
| 19481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19482 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19483 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19484 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19485 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19486 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19487 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19488 | // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 651 |
| 19489 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19491 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19492 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19493 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19494 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19495 | // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 657 |
| 19496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19497 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19498 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19499 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19500 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19501 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19502 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19503 | // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 664 |
| 19504 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19505 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19506 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19507 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19508 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19509 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19510 | // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 670 |
| 19511 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19512 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19513 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19515 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19516 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19517 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19518 | // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 677 |
| 19519 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19520 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19521 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19522 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19523 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19524 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19525 | // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 683 |
| 19526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19528 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19529 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19530 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19531 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19532 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19533 | // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 690 |
| 19534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19535 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19536 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19537 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19538 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19539 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19540 | // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 696 |
| 19541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19543 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19544 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19545 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19546 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19547 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19548 | // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 703 |
| 19549 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19551 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19552 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19553 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19554 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19555 | // (EONWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 709 |
| 19556 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19557 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19558 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19559 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19560 | // (EONXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 713 |
| 19561 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19563 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19564 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19565 | // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 717 |
| 19566 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19568 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19569 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19570 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19571 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19572 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19573 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19574 | // (EORWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 725 |
| 19575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19577 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19578 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19579 | // (EORXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 729 |
| 19580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19582 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19583 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19584 | // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 733 |
| 19585 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19587 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19588 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19589 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19591 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19592 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19593 | // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 741 |
| 19594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19595 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19596 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 19597 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19598 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19600 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19601 | // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 748 |
| 19602 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19603 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19604 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 19605 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19606 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19607 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19608 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19609 | // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 755 |
| 19610 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19611 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19612 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 19613 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19614 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19615 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19616 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19617 | // (EXTRACT_ZPMXI_H_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 762 |
| 19618 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19619 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19620 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 19622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19623 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19624 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19625 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19626 | // (EXTRACT_ZPMXI_H_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 770 |
| 19627 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19628 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19629 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 19631 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19632 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19633 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19634 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19635 | // (EXTRACT_ZPMXI_H_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 778 |
| 19636 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19637 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19638 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19639 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 19640 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19641 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19642 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19643 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19644 | // (EXTRACT_ZPMXI_H_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpH128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 786 |
| 19645 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19646 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19647 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19648 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 19649 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19650 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19651 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19652 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19653 | // (EXTRACT_ZPMXI_H_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 794 |
| 19654 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19655 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19656 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19657 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 19658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19659 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19660 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19661 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19662 | // (EXTRACT_ZPMXI_V_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 802 |
| 19663 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19664 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19665 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19666 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 19667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19668 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19669 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19670 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19671 | // (EXTRACT_ZPMXI_V_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 810 |
| 19672 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19673 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19674 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19675 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 19676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19677 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19678 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19679 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19680 | // (EXTRACT_ZPMXI_V_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 818 |
| 19681 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19682 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19683 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 19685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19686 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19687 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19688 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19689 | // (EXTRACT_ZPMXI_V_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpV128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 826 |
| 19690 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19691 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19692 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19693 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 19694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19695 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19696 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19697 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19698 | // (EXTRACT_ZPMXI_V_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 834 |
| 19699 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19700 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19701 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19702 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 19703 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 19704 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19705 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19706 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19707 | // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 842 |
| 19708 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19709 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 19710 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19711 | {.Kind: AliasPatternCond::K_Custom, .Value: 8}, |
| 19712 | // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 846 |
| 19713 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19714 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 19715 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 19716 | // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 849 |
| 19717 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19718 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19719 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19721 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19722 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19723 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19724 | // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 856 |
| 19725 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19726 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19727 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19728 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19729 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19730 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19731 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19732 | // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 863 |
| 19733 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19734 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 19735 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 19736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19737 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19738 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19739 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19740 | // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 870 |
| 19741 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19742 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19745 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19746 | // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 875 |
| 19747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19748 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19749 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19750 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19751 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19752 | // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 880 |
| 19753 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19754 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19755 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19756 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 19757 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19758 | // (GCSPOPM XZR) - 885 |
| 19759 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 19760 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19761 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureGCS}, |
| 19762 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19763 | // (GLD1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 889 |
| 19764 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19765 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19767 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19768 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19769 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19770 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19771 | // (GLD1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 896 |
| 19772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19773 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19775 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19776 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19777 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19778 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19779 | // (GLD1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 903 |
| 19780 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19782 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19783 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19784 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19785 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19786 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19787 | // (GLD1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 910 |
| 19788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19789 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19790 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19791 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19792 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19793 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19794 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19795 | // (GLD1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 917 |
| 19796 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19799 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19800 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19802 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19803 | // (GLD1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 924 |
| 19804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19805 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19807 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 19808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19809 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 19810 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19811 | // (GLD1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 931 |
| 19812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19814 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19815 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19816 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19817 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19818 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19819 | // (GLD1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 938 |
| 19820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19823 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19826 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19827 | // (GLD1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 945 |
| 19828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19830 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19831 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19832 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19833 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19834 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19835 | // (GLD1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 952 |
| 19836 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19837 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19839 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19840 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19841 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19842 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19843 | // (GLD1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 959 |
| 19844 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19845 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19847 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19848 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19849 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19850 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19851 | // (GLD1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 966 |
| 19852 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19853 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19855 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19856 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19857 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19858 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19859 | // (GLD1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 973 |
| 19860 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19861 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19862 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19863 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19864 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19865 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19866 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19867 | // (GLDFF1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 980 |
| 19868 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19869 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19870 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19871 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19872 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19873 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19874 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19875 | // (GLDFF1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 987 |
| 19876 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19877 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19878 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19879 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19880 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19881 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19882 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19883 | // (GLDFF1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 994 |
| 19884 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19885 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19887 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19888 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19889 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19890 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19891 | // (GLDFF1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1001 |
| 19892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19895 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19898 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19899 | // (GLDFF1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1008 |
| 19900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19903 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19904 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19906 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19907 | // (GLDFF1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1015 |
| 19908 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19911 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19912 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19913 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19914 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19915 | // (GLDFF1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1022 |
| 19916 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19917 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19919 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19920 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19921 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19922 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19923 | // (GLDFF1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1029 |
| 19924 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19925 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19927 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19928 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19929 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19930 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19931 | // (GLDFF1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1036 |
| 19932 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19933 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19935 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19936 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19937 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19938 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19939 | // (GLDFF1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1043 |
| 19940 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19941 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19943 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19944 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19945 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19946 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19947 | // (GLDFF1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1050 |
| 19948 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19949 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19950 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19951 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19952 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19953 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19954 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19955 | // (GLDFF1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1057 |
| 19956 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19957 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 19958 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 19959 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 19960 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19961 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 19962 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19963 | // (HINT 1) - 1064 |
| 19964 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 19965 | // (HINT 2) - 1065 |
| 19966 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 19967 | // (HINT 3) - 1066 |
| 19968 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 19969 | // (HINT 4) - 1067 |
| 19970 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 19971 | // (HINT 5) - 1068 |
| 19972 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 19973 | // (HINT 6) - 1069 |
| 19974 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 19975 | // (HINT 16) - 1070 |
| 19976 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 19977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 19978 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRAS}, |
| 19979 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 19980 | // (HINT 20) - 1074 |
| 19981 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(20)}, |
| 19982 | // (HINT 48) - 1075 |
| 19983 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(48)}, |
| 19984 | // (HINT 49) - 1076 |
| 19985 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(49)}, |
| 19986 | // (HINT 50) - 1077 |
| 19987 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(50)}, |
| 19988 | // (HINT 51) - 1078 |
| 19989 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(51)}, |
| 19990 | // (HINT 52) - 1079 |
| 19991 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(52)}, |
| 19992 | // (HINT 54) - 1080 |
| 19993 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(54)}, |
| 19994 | // (HINT 55) - 1081 |
| 19995 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(55)}, |
| 19996 | // (HINT 56) - 1082 |
| 19997 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(56)}, |
| 19998 | // (HINT 32) - 1083 |
| 19999 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(32)}, |
| 20000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20001 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBTIE}, |
| 20002 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20003 | // (HINT 32) - 1087 |
| 20004 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(32)}, |
| 20005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20006 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBranchTargetId}, |
| 20007 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20008 | // (HINT 34) - 1091 |
| 20009 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(34)}, |
| 20010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20011 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBranchTargetId}, |
| 20012 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20013 | // (HINT 36) - 1095 |
| 20014 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(36)}, |
| 20015 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20016 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBranchTargetId}, |
| 20017 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20018 | // (HINT 38) - 1099 |
| 20019 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(38)}, |
| 20020 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20021 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBranchTargetId}, |
| 20022 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20023 | // (HINT 17) - 1103 |
| 20024 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(17)}, |
| 20025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20026 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSPE}, |
| 20027 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20028 | // (HINT 18) - 1107 |
| 20029 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(18)}, |
| 20030 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureTRACEV8_4}, |
| 20032 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20033 | // (HINT 19) - 1111 |
| 20034 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(19)}, |
| 20035 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20036 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureGCS}, |
| 20037 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20038 | // (HINT 22) - 1115 |
| 20039 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(22)}, |
| 20040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20041 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCLRBHB}, |
| 20042 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20043 | // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1119 |
| 20044 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 20045 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20046 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 20047 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20049 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20051 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20052 | // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1127 |
| 20053 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 20054 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20055 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20056 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20057 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20059 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20060 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20061 | // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1135 |
| 20062 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 20063 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20064 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 20065 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20066 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20067 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20068 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20069 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20070 | // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1143 |
| 20071 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 20072 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20073 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20074 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20075 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20076 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20077 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20078 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20079 | // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1151 |
| 20080 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20081 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20082 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 20083 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20084 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20087 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20088 | // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 1159 |
| 20089 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20090 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20091 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20092 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20093 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20094 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20096 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20097 | // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1167 |
| 20098 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 20099 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20100 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 20101 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20102 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20103 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20104 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20105 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20106 | // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1175 |
| 20107 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 20108 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20109 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20110 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20112 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20114 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20115 | // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1183 |
| 20116 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20117 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20118 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 20119 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20122 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20123 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20124 | // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 1191 |
| 20125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20126 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20127 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20128 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20129 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20130 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20132 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20133 | // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1199 |
| 20134 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 20135 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20136 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 20137 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20138 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20139 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20140 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20141 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20142 | // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1207 |
| 20143 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 20144 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20145 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20146 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20147 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20148 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20149 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20150 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20151 | // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1215 |
| 20152 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20153 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20154 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 20155 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20156 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20157 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20159 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20160 | // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 1223 |
| 20161 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20162 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20163 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20164 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 20165 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20167 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20168 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20169 | // (INSERT_MXIPZ_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1231 |
| 20170 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 20171 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20172 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20173 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20174 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20175 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20176 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20177 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20178 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20179 | // (INSERT_MXIPZ_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1240 |
| 20180 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 20181 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20182 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20183 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20184 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20185 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20186 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20187 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20188 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20189 | // (INSERT_MXIPZ_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1249 |
| 20190 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 20191 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20192 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20193 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20196 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20197 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20198 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20199 | // (INSERT_MXIPZ_H_Q TileVectorOpH128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1258 |
| 20200 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 20201 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20202 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20203 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20204 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20205 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20206 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20207 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20208 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20209 | // (INSERT_MXIPZ_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1267 |
| 20210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 20211 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20212 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20213 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20214 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20215 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20216 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20217 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20218 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20219 | // (INSERT_MXIPZ_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1276 |
| 20220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 20221 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20222 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20223 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20224 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20225 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20226 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20227 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20228 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20229 | // (INSERT_MXIPZ_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1285 |
| 20230 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 20231 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20232 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20233 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20236 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20237 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20238 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20239 | // (INSERT_MXIPZ_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1294 |
| 20240 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 20241 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20242 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20243 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20245 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20246 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20247 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20248 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20249 | // (INSERT_MXIPZ_V_Q TileVectorOpV128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1303 |
| 20250 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 20251 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20253 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20254 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20255 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20256 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20257 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20258 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20259 | // (INSERT_MXIPZ_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1312 |
| 20260 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 20261 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20262 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 20263 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20264 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20265 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20266 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20267 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20268 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20269 | // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 1321 |
| 20270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20271 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20272 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 20274 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20275 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20276 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20277 | // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 1328 |
| 20278 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20279 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20280 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20281 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20284 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20285 | // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 1335 |
| 20286 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20287 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20288 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20289 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 20290 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20291 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20292 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20293 | // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 1342 |
| 20294 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20295 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20296 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20297 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20298 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20299 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20300 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20301 | // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 1349 |
| 20302 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20303 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20304 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20305 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 20306 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20307 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20308 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20309 | // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 1356 |
| 20310 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20311 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20312 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20313 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20314 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20315 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20316 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20317 | // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 1363 |
| 20318 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20319 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20320 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20321 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 20322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20323 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20324 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20325 | // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 1370 |
| 20326 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20327 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20328 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20330 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20331 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20332 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20333 | // (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 1377 |
| 20334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20335 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20336 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20337 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20338 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 20339 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20340 | // (ISB 15) - 1383 |
| 20341 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 20342 | // (LD1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1384 |
| 20343 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 20344 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20346 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20347 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20348 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20349 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 20350 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20351 | // (LD1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1392 |
| 20352 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 20353 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20355 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20356 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20357 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20358 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20359 | // (LD1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1399 |
| 20360 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 20361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20362 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20363 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20364 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20365 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20366 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 20367 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20368 | // (LD1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1407 |
| 20369 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 20370 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20371 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20372 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20373 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20374 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20375 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20376 | // (LD1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1414 |
| 20377 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20378 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20379 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20380 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20381 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20382 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20383 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20384 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20385 | // (LD1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1422 |
| 20386 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20387 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20389 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20390 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20391 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20392 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20393 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20394 | // (LD1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1430 |
| 20395 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20396 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20397 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20398 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20399 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20400 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20401 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20402 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20403 | // (LD1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1438 |
| 20404 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20405 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20406 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20407 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20408 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20409 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20410 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20411 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20412 | // (LD1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1446 |
| 20413 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 20414 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20415 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20416 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20417 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20418 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20419 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 20420 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20421 | // (LD1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1454 |
| 20422 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 20423 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20424 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20425 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20426 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20427 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20428 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20429 | // (LD1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1461 |
| 20430 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 20431 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20432 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20433 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20434 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20435 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20436 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 20437 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20438 | // (LD1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1469 |
| 20439 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 20440 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20441 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20442 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20443 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20444 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20445 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20446 | // (LD1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1476 |
| 20447 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20448 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20449 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20450 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20453 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20454 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20455 | // (LD1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1484 |
| 20456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20457 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20458 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20459 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20460 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20461 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 20462 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20463 | // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1491 |
| 20464 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20465 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 20466 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20467 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20468 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20469 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20470 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20471 | // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1498 |
| 20472 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20473 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 20474 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20475 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20476 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20477 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20478 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20479 | // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1505 |
| 20480 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 20482 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20483 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20484 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20485 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20486 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20487 | // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1512 |
| 20488 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20489 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 20490 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20491 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20492 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20493 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20494 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20495 | // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1519 |
| 20496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20497 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 20498 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20499 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20500 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20501 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20502 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20503 | // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1526 |
| 20504 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20505 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 20506 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20507 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20508 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20509 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20510 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20511 | // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1533 |
| 20512 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20513 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 20514 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20515 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20516 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20517 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20518 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20519 | // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1540 |
| 20520 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20521 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 20522 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20523 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20524 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20525 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20526 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20527 | // (LD1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1547 |
| 20528 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 20529 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20530 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20531 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20532 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20533 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20534 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 20535 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20536 | // (LD1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1555 |
| 20537 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 20538 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20539 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20540 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20541 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20542 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20543 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20544 | // (LD1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1562 |
| 20545 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 20546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20547 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20548 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20549 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20550 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20551 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 20552 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20553 | // (LD1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1570 |
| 20554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 20555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 20556 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20557 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20558 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20559 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 20560 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20561 | // (LD1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1577 |
| 20562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20563 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20564 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20565 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20566 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20567 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20568 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20569 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20570 | // (LD1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1585 |
| 20571 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20572 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20573 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20574 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20575 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20576 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20577 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20578 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20579 | // (LD1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1593 |
| 20580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20582 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20583 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20584 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20585 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20586 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20587 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20588 | // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1601 |
| 20589 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20590 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20591 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20592 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20593 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20594 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20595 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20596 | // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1608 |
| 20597 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20598 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 20599 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20600 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20601 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20602 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20603 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20604 | // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1615 |
| 20605 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20606 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20607 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20608 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20609 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20610 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20611 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20612 | // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1622 |
| 20613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20614 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 20615 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20616 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20617 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20618 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20619 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20620 | // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1629 |
| 20621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 20623 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20624 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20625 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20626 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20627 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20628 | // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1636 |
| 20629 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20631 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20632 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20633 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20634 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20635 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20636 | // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1643 |
| 20637 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20638 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 20639 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20640 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20641 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20642 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20643 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20644 | // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1650 |
| 20645 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20646 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20647 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20648 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20649 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20650 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20651 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20652 | // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1657 |
| 20653 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20654 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20655 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20656 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20657 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20658 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20659 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20660 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20661 | // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1665 |
| 20662 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20663 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20664 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20665 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20666 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20667 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20668 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20669 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20670 | // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1673 |
| 20671 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20672 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20673 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20674 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20675 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20676 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20677 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20678 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20679 | // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1681 |
| 20680 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20681 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20682 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20683 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20684 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20685 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20686 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20687 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20688 | // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1689 |
| 20689 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20690 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20691 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20692 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20693 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20694 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20695 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20696 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20697 | // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1697 |
| 20698 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20699 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20700 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20701 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20702 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20703 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20704 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20705 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20706 | // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1705 |
| 20707 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20708 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20709 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20710 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20711 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20712 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20713 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20714 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20715 | // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1713 |
| 20716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20717 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20718 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20719 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20721 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20722 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20723 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20724 | // (LD1RO_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1721 |
| 20725 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20726 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20727 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20728 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20729 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20730 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20731 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20732 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20733 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 20734 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20735 | // (LD1RO_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1731 |
| 20736 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20737 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20738 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20739 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20740 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20741 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20742 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 20745 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20746 | // (LD1RO_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1741 |
| 20747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20750 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20751 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20752 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20753 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20754 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20755 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 20756 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20757 | // (LD1RO_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1751 |
| 20758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20759 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20760 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20761 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20763 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20764 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20765 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20766 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMatMulFP64}, |
| 20767 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20768 | // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1761 |
| 20769 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20770 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20771 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20772 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20773 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20774 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20775 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20776 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20777 | // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1769 |
| 20778 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20780 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20781 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20782 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20783 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20784 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20785 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20786 | // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1777 |
| 20787 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20789 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20790 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20791 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20792 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20793 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20794 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20795 | // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1785 |
| 20796 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20799 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20800 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20802 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20803 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20804 | // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1793 |
| 20805 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20807 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20808 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20809 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20810 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20811 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20812 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20813 | // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1801 |
| 20814 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20815 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20816 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20817 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20818 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20819 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20820 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20821 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20822 | // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1809 |
| 20823 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20824 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20825 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20826 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20827 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20828 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20829 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20830 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20831 | // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1817 |
| 20832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20834 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20835 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20836 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20837 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20838 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20839 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20840 | // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1825 |
| 20841 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20843 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20844 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20845 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20846 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20847 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20848 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20849 | // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1833 |
| 20850 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20851 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20852 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20853 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20854 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20855 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20856 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20857 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20858 | // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1841 |
| 20859 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20860 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20861 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20862 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20863 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20864 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20865 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20866 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20867 | // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1849 |
| 20868 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20869 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20870 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20871 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20872 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20873 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20874 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20875 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20876 | // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1857 |
| 20877 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20878 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20879 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20880 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20881 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20882 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20883 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20884 | // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1864 |
| 20885 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 20887 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20888 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20889 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20890 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20891 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20892 | // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1871 |
| 20893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20895 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20896 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20898 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20899 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20900 | // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1878 |
| 20901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 20903 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20904 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20907 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20908 | // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1885 |
| 20909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 20911 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20912 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20913 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20914 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20915 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20916 | // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1892 |
| 20917 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20919 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20920 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20921 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20922 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20923 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20924 | // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1899 |
| 20925 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 20927 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20928 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20929 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20930 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20931 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20932 | // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1906 |
| 20933 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 20935 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20936 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20937 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20938 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 20939 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20940 | // (LD1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1913 |
| 20941 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20943 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20944 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20945 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20946 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20947 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20948 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20949 | // (LD1SB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1921 |
| 20950 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20951 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20953 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20954 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20955 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20956 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20957 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20958 | // (LD1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1929 |
| 20959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20961 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20962 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20963 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20964 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20965 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20966 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20967 | // (LD1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1937 |
| 20968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20969 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20970 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20971 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20972 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20973 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20974 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20975 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20976 | // (LD1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1945 |
| 20977 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20978 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20979 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20980 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20981 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20982 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20983 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20984 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20985 | // (LD1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1953 |
| 20986 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 20987 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 20988 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20989 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 20990 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 20991 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 20992 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 20993 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 20994 | // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1961 |
| 20995 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 20996 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 20997 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 20998 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 20999 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21001 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21002 | // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1968 |
| 21003 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21004 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21005 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21006 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21007 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21008 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21009 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21010 | // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1975 |
| 21011 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21012 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21013 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21014 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21015 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21016 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21017 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21018 | // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1982 |
| 21019 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21020 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21021 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21022 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21023 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21024 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21025 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21026 | // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1989 |
| 21027 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21028 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21029 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21030 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21033 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21034 | // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1996 |
| 21035 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21037 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21038 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21041 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21042 | // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2003 |
| 21043 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21044 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21045 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21046 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21047 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21049 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21050 | // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2010 |
| 21051 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21052 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21053 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21054 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21055 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21056 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21057 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21058 | // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2017 |
| 21059 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21060 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21061 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21062 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21065 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21066 | // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 2024 |
| 21067 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21069 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21070 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21073 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21074 | // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2031 |
| 21075 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21076 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21077 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21078 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21079 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21081 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21082 | // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2038 |
| 21083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21085 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21086 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21087 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21088 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21089 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21090 | // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2045 |
| 21091 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21092 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21093 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21094 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21096 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21097 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21098 | // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2052 |
| 21099 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21100 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21101 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21102 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21103 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21104 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21105 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21106 | // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2059 |
| 21107 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21108 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21109 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21110 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21112 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21113 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21114 | // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2066 |
| 21115 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21116 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21117 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21118 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21121 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21122 | // (LD1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2073 |
| 21123 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 21124 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 21125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21126 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21128 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 21129 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 21130 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21131 | // (LD1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2081 |
| 21132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 21133 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 21134 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21135 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21137 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 21138 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21139 | // (LD1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2088 |
| 21140 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 21141 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 21142 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21143 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 21146 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 21147 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21148 | // (LD1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2096 |
| 21149 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 21150 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 21151 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21152 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21153 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21154 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 21155 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21156 | // (LD1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2103 |
| 21157 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 21158 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21159 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21160 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21161 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21163 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21164 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21165 | // (LD1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2111 |
| 21166 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 21167 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21168 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21169 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21170 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21171 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21172 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21173 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21174 | // (LD1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2119 |
| 21175 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 21176 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21177 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21178 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21179 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 21181 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21182 | // (LD1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2126 |
| 21183 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 21184 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21185 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21186 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21187 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21188 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21191 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21192 | // (LD1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2135 |
| 21193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 21194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21195 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21196 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21197 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21198 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21199 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21200 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21201 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21202 | // (LD1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2144 |
| 21203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 21204 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21205 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21206 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21207 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21208 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21209 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21210 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21211 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21212 | // (LD1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2153 |
| 21213 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 21214 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21215 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21216 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21217 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21218 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21219 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21220 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21221 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21222 | // (LD1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2162 |
| 21223 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 21224 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21225 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21226 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21228 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21229 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21231 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21232 | // (LD1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2171 |
| 21233 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 21234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21235 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21236 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21238 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21240 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21241 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21242 | // (LD1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2180 |
| 21243 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 21244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21245 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21247 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21248 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21249 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21250 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21251 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21252 | // (LD1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2189 |
| 21253 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 21254 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21255 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21257 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21258 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21259 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21260 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21261 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21262 | // (LD1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2198 |
| 21263 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 21264 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21265 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21266 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21268 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21269 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21270 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21271 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21272 | // (LD1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2207 |
| 21273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 21274 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 21275 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21276 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21277 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21278 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21279 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21280 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21281 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21282 | // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 2216 |
| 21283 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21284 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 21285 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21286 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21287 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21288 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21289 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21290 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21291 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21292 | // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 2225 |
| 21293 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21294 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 21295 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21296 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21297 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21298 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21299 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21300 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21301 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21302 | // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 2234 |
| 21303 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21304 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 21305 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21306 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21307 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21308 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21309 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21310 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21311 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21312 | // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 2243 |
| 21313 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 21315 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21316 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21317 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21318 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21319 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21320 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21321 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21322 | // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2252 |
| 21323 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 21324 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21325 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21326 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21327 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21328 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21329 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21330 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21331 | // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2260 |
| 21332 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 21333 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21335 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21336 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21337 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21338 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21339 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21340 | // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2268 |
| 21341 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 21342 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21343 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21344 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21345 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21346 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21347 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21348 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21349 | // (LD2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2276 |
| 21350 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 21351 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21352 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21353 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21354 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21355 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 21356 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 21357 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21358 | // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2284 |
| 21359 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21360 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21361 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21362 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21363 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21364 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21365 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21366 | // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 2291 |
| 21367 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21368 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21369 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21370 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21371 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21372 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21373 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21374 | // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2298 |
| 21375 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21376 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21377 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21378 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21379 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21380 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21381 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21382 | // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2305 |
| 21383 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21384 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21385 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21386 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21387 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21388 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21389 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21390 | // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2312 |
| 21391 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21392 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21393 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21394 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21395 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21396 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21397 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21398 | // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2319 |
| 21399 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21400 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21401 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21402 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21403 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21404 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21405 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21406 | // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2326 |
| 21407 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21408 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21409 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21410 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21411 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21412 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21413 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21414 | // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2333 |
| 21415 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21416 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21417 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21418 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21419 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21420 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21421 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21422 | // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2340 |
| 21423 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21424 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21425 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21426 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21427 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21428 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21429 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21430 | // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2347 |
| 21431 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21432 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21433 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21434 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21435 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21436 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21437 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21438 | // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2354 |
| 21439 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21440 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21441 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21442 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21443 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21444 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21445 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21446 | // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2361 |
| 21447 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21448 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21449 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21450 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21453 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21454 | // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2368 |
| 21455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21457 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21458 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21460 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21461 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21462 | // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2375 |
| 21463 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21464 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 21465 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21466 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21467 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21468 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21469 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21470 | // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2382 |
| 21471 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21472 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21473 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21474 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21475 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21476 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21477 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21478 | // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2389 |
| 21479 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 21480 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21482 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21483 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21484 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21485 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21486 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21487 | // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 2397 |
| 21488 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21489 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21490 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21491 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21492 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21493 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21494 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21495 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21496 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21497 | // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 2406 |
| 21498 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21499 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21500 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21501 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21502 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21503 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21504 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21505 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21506 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21507 | // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 2415 |
| 21508 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21509 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21510 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21511 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21512 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21513 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21515 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21516 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21517 | // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 2424 |
| 21518 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21519 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 21520 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21521 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21522 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21523 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21524 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21525 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21526 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21527 | // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2433 |
| 21528 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 21529 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21530 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21531 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21532 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21533 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21534 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21535 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21536 | // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2441 |
| 21537 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 21538 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21539 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21540 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21541 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21542 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21543 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21544 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21545 | // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2449 |
| 21546 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 21547 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21548 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21549 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21550 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21551 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21552 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21553 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21554 | // (LD3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2457 |
| 21555 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 21556 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21557 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21558 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21559 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21560 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 21561 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 21562 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21563 | // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2465 |
| 21564 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21565 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21566 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21567 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21568 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21569 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21570 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21571 | // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 2472 |
| 21572 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21573 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21574 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21575 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21576 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21577 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21578 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21579 | // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2479 |
| 21580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21582 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21583 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21584 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21585 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21586 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21587 | // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2486 |
| 21588 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21589 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21590 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21591 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21592 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21593 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21594 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21595 | // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2493 |
| 21596 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21597 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21598 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21599 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21600 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21601 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21602 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21603 | // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2500 |
| 21604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21605 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21606 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21607 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21608 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21609 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21610 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21611 | // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2507 |
| 21612 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21613 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21614 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21615 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21616 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21617 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21618 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21619 | // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2514 |
| 21620 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21622 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21623 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21624 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21625 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21626 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21627 | // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2521 |
| 21628 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21629 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21630 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21631 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21632 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21633 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21634 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21635 | // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2528 |
| 21636 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21637 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21638 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21639 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21640 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21641 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21642 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21643 | // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2535 |
| 21644 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21645 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21646 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21647 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21648 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21649 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21650 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21651 | // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2542 |
| 21652 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21653 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21654 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21655 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21656 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21657 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21658 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21659 | // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2549 |
| 21660 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21661 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21662 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21663 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21664 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21665 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21666 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21667 | // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2556 |
| 21668 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21669 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 21670 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21671 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21672 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21673 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21674 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21675 | // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2563 |
| 21676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21677 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21678 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21679 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21682 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21683 | // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2570 |
| 21684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 21685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21686 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21687 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21688 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21689 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21690 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21691 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21692 | // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 2578 |
| 21693 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21695 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21696 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21697 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21698 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21699 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21700 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21701 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21702 | // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 2587 |
| 21703 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21704 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21705 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21706 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21707 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21708 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21709 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21710 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21711 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21712 | // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 2596 |
| 21713 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21714 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21715 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21716 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21717 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21718 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21719 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21721 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21722 | // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 2605 |
| 21723 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21724 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 21725 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21726 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21727 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21728 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21729 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21730 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21731 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21732 | // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2614 |
| 21733 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 21734 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21735 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21736 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21737 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21738 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21739 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21740 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21741 | // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2622 |
| 21742 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 21743 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21744 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21745 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21746 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21747 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21748 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21749 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21750 | // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2630 |
| 21751 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21752 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21753 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21754 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21755 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21756 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21757 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21758 | // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2637 |
| 21759 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21760 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21761 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21762 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21763 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21764 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21765 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21766 | // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2644 |
| 21767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21768 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 21769 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21770 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21771 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21772 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21773 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21774 | // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2651 |
| 21775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21776 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 21777 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21778 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21779 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21780 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21781 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21782 | // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2658 |
| 21783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21785 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21786 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21787 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21788 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21789 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21790 | // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2665 |
| 21791 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21792 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 21793 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21794 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21795 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21796 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21797 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21798 | // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2672 |
| 21799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21800 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21801 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21802 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21803 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21804 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21805 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21806 | // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2679 |
| 21807 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 21808 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21809 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21810 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21811 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21812 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21813 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21814 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21815 | // (LD4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2687 |
| 21816 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 21817 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21818 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21819 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21820 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21821 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 21822 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 21823 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21824 | // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2695 |
| 21825 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21826 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21827 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21828 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21829 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21830 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21831 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21832 | // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 2702 |
| 21833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21834 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 21835 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21836 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21837 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21838 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21839 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21840 | // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2709 |
| 21841 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21843 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21844 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21845 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21846 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21847 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21848 | // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2716 |
| 21849 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21850 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 21851 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21852 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21853 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21854 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21855 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21856 | // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2723 |
| 21857 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 21859 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21860 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21862 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21863 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21864 | // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2730 |
| 21865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21866 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21867 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21868 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21869 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21870 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21871 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21872 | // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2737 |
| 21873 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21874 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 21875 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21876 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21877 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21878 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21879 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21880 | // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2744 |
| 21881 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21882 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21883 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21884 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21885 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21886 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21887 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21888 | // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2751 |
| 21889 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 21890 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 21891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21892 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 21893 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21894 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 21895 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 21896 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21897 | // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 2759 |
| 21898 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21899 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21900 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21901 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21902 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21903 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21904 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21906 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21907 | // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 2768 |
| 21908 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21910 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21911 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21912 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21913 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21914 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21915 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21916 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21917 | // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 2777 |
| 21918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21920 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21921 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21922 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21923 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21924 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21925 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21926 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21927 | // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 2786 |
| 21928 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 21930 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21931 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21932 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 21933 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21934 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21935 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 21936 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21937 | // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2795 |
| 21938 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 21939 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 21940 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21941 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21942 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 21943 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21944 | // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2801 |
| 21945 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 21946 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 21947 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21949 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 21950 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21951 | // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2807 |
| 21952 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 21953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 21954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21955 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21956 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 21957 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21958 | // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2813 |
| 21959 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 21960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 21961 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21962 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21963 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 21964 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21965 | // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2819 |
| 21966 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 21967 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 21968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21970 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 21971 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21972 | // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2825 |
| 21973 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21974 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 21975 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21976 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21977 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 21978 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21979 | // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2831 |
| 21980 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 21981 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 21982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21983 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21984 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 21985 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21986 | // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2837 |
| 21987 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 21988 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 21989 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21990 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21991 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 21992 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 21993 | // (LDAPPi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn) - 2843 |
| 21994 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 21995 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 21996 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 21997 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 21998 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSCP}, |
| 21999 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22000 | // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2849 |
| 22001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22002 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22003 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 22006 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22007 | // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2855 |
| 22008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22010 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22011 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22012 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 22013 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22014 | // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2861 |
| 22015 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22016 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22017 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22018 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22019 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 22020 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22021 | // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2867 |
| 22022 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22023 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22024 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22026 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 22027 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22028 | // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2873 |
| 22029 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22030 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22031 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22032 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22033 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 22034 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22035 | // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2879 |
| 22036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22037 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22038 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 22041 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22042 | // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2885 |
| 22043 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22044 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22045 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22046 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22047 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 22048 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22049 | // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2891 |
| 22050 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22051 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22052 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22053 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22054 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 22055 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22056 | // (LDAPURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 2897 |
| 22057 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 22058 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22059 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22060 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22061 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 22062 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 22065 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22066 | // (LDAPURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 2906 |
| 22067 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 22068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22069 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22070 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 22072 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22074 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 22075 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22076 | // (LDAPURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 2915 |
| 22077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 22078 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22079 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22081 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 22082 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22083 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22084 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 22085 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22086 | // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 2924 |
| 22087 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22088 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22089 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22090 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22091 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 22092 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22093 | // (LDAPURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 2930 |
| 22094 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 22095 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22096 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22097 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22098 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 22099 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22100 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22101 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 22102 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22103 | // (LDAPURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 2939 |
| 22104 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 22105 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22106 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22107 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22108 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 22109 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 22112 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22113 | // (LDAPi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn) - 2948 |
| 22114 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22115 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22116 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22117 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22118 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSCP}, |
| 22119 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22120 | // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2954 |
| 22121 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22122 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22123 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22124 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22125 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22126 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22127 | // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2960 |
| 22128 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22129 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22130 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22132 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22133 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22134 | // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2966 |
| 22135 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22136 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22137 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22138 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22139 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22140 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22141 | // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2972 |
| 22142 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22143 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22144 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22146 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22147 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22148 | // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2978 |
| 22149 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22150 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22151 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22153 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22154 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22155 | // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2984 |
| 22156 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22157 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22158 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22160 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22161 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22162 | // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2990 |
| 22163 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22164 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22165 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22167 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22168 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22169 | // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2996 |
| 22170 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22172 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22173 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22174 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22175 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22176 | // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3002 |
| 22177 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22178 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22181 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22182 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22183 | // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3008 |
| 22184 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22185 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22186 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22187 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22188 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22189 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22190 | // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3014 |
| 22191 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22192 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22193 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22194 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22195 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22196 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22197 | // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3020 |
| 22198 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22199 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22200 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22201 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22202 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22203 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22204 | // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3026 |
| 22205 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22206 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22207 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22208 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22209 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22210 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22211 | // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3032 |
| 22212 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22213 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22214 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22216 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22217 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22218 | // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3038 |
| 22219 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 22220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22221 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22224 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22225 | // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3044 |
| 22226 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22229 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22230 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 22231 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22232 | // (LDFF1B Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3050 |
| 22233 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22234 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22236 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22237 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22238 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22239 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22240 | // (LDFF1B_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3057 |
| 22241 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22242 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22243 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22244 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22245 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22246 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22247 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22248 | // (LDFF1B_H Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3064 |
| 22249 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22250 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22251 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22252 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22253 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22254 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22255 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22256 | // (LDFF1B_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3071 |
| 22257 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22258 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22259 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22260 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22261 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22262 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22263 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22264 | // (LDFF1D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3078 |
| 22265 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22266 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22268 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22269 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22270 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22271 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22272 | // (LDFF1H Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3085 |
| 22273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22274 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22275 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22276 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22277 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22278 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22279 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22280 | // (LDFF1H_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3092 |
| 22281 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22282 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22283 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22284 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22285 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22286 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22287 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22288 | // (LDFF1H_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3099 |
| 22289 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22290 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22291 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22292 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22293 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22294 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22295 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22296 | // (LDFF1SB_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3106 |
| 22297 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22298 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22299 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22300 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22301 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22302 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22303 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22304 | // (LDFF1SB_H Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3113 |
| 22305 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22306 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22307 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22308 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22309 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22310 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22311 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22312 | // (LDFF1SB_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3120 |
| 22313 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22316 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22317 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22318 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22319 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22320 | // (LDFF1SH_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3127 |
| 22321 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22322 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22323 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22324 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22325 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22326 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22327 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22328 | // (LDFF1SH_S Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3134 |
| 22329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22331 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22332 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22333 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22334 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22335 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22336 | // (LDFF1SW_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3141 |
| 22337 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22338 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22340 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22343 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22344 | // (LDFF1W Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3148 |
| 22345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22348 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22349 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22350 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22351 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22352 | // (LDFF1W_D Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3155 |
| 22353 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22355 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22356 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22357 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22358 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22359 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22360 | // (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 3162 |
| 22361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22362 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 22363 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22364 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22365 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22366 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 22367 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22368 | // (LDNF1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3169 |
| 22369 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22370 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22371 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22372 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22373 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22374 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22375 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22376 | // (LDNF1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3176 |
| 22377 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22378 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22379 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22380 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22381 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22382 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22383 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22384 | // (LDNF1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3183 |
| 22385 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22386 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22387 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22388 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22389 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22390 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22391 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22392 | // (LDNF1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3190 |
| 22393 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22394 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22395 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22396 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22397 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22398 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22399 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22400 | // (LDNF1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3197 |
| 22401 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22402 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22403 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22404 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22405 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22406 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22407 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22408 | // (LDNF1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3204 |
| 22409 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22410 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22411 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22412 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22413 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22414 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22415 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22416 | // (LDNF1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3211 |
| 22417 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22418 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22419 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22420 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22421 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22422 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22423 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22424 | // (LDNF1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3218 |
| 22425 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22426 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22427 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22428 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22429 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22430 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22431 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22432 | // (LDNF1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3225 |
| 22433 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22434 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22435 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22436 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22437 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22438 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22439 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22440 | // (LDNF1SB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3232 |
| 22441 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22442 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22443 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22444 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22445 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22446 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22447 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22448 | // (LDNF1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3239 |
| 22449 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22450 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22451 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22452 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22453 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22454 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22455 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22456 | // (LDNF1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3246 |
| 22457 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22458 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22459 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22460 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22461 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22462 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22463 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22464 | // (LDNF1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3253 |
| 22465 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22466 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22467 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22468 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22469 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22470 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22471 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22472 | // (LDNF1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3260 |
| 22473 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22474 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22475 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22476 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22477 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22478 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22479 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22480 | // (LDNF1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3267 |
| 22481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22482 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22483 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22484 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22485 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22486 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22487 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22488 | // (LDNF1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3274 |
| 22489 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22491 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22492 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22493 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22494 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22495 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22496 | // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3281 |
| 22497 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 22498 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 22499 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22500 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22501 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22502 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22503 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22504 | // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3288 |
| 22505 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 22506 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 22507 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22508 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22509 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22510 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22511 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22512 | // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3295 |
| 22513 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 22514 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 22515 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22516 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22517 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22518 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22519 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22520 | // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3302 |
| 22521 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22522 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22523 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22524 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22525 | // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3306 |
| 22526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22528 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22529 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22530 | // (LDNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3310 |
| 22531 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 22532 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22533 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22534 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22535 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22536 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22537 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 22538 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22539 | // (LDNT1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3318 |
| 22540 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 22541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22543 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22544 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22545 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22546 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22547 | // (LDNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3325 |
| 22548 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 22549 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22551 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22552 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22553 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22554 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 22555 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22556 | // (LDNT1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3333 |
| 22557 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 22558 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22559 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22560 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22561 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22562 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22563 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22564 | // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3340 |
| 22565 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22566 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22568 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22569 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22570 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22571 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 22572 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22573 | // (LDNT1B_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3348 |
| 22574 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22577 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22578 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22579 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22580 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22581 | // (LDNT1B_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3355 |
| 22582 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22583 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22584 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22585 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22586 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22587 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22588 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22589 | // (LDNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3362 |
| 22590 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 22591 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22592 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22593 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22594 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22595 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22596 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 22597 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22598 | // (LDNT1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3370 |
| 22599 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 22600 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22601 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22602 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22603 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22604 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22605 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22606 | // (LDNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3377 |
| 22607 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 22608 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22609 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22610 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22611 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22612 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22613 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 22614 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22615 | // (LDNT1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3385 |
| 22616 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 22617 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22618 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22619 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22620 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22621 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22622 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22623 | // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3392 |
| 22624 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22625 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22626 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22627 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22628 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22629 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22630 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 22631 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22632 | // (LDNT1D_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3400 |
| 22633 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22634 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22635 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22636 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22637 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22638 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22639 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22640 | // (LDNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3407 |
| 22641 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 22642 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22643 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22644 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22645 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22647 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 22648 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22649 | // (LDNT1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3415 |
| 22650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 22651 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22652 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22653 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22655 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22656 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22657 | // (LDNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3422 |
| 22658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 22659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22660 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22661 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22662 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22663 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22664 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 22665 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22666 | // (LDNT1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3430 |
| 22667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 22668 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22669 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22670 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22671 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22672 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22673 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22674 | // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3437 |
| 22675 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22677 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22678 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22679 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22680 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 22682 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22683 | // (LDNT1H_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3445 |
| 22684 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22686 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22687 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22688 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22689 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22690 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22691 | // (LDNT1H_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3452 |
| 22692 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22693 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22695 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22696 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22697 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22698 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22699 | // (LDNT1SB_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3459 |
| 22700 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22701 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22702 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22703 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22704 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22705 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22706 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22707 | // (LDNT1SB_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3466 |
| 22708 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22709 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22710 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22711 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22712 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22713 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22714 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22715 | // (LDNT1SH_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3473 |
| 22716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22717 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22718 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22719 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22721 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22722 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22723 | // (LDNT1SH_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3480 |
| 22724 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22725 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22726 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22727 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22728 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22729 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22730 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22731 | // (LDNT1SW_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3487 |
| 22732 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22733 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22734 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22735 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22737 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22738 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22739 | // (LDNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3494 |
| 22740 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 22741 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22742 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22743 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22745 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22746 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 22747 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22748 | // (LDNT1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3502 |
| 22749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 22750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22751 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22752 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22753 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22754 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22755 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22756 | // (LDNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3509 |
| 22757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 22758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22759 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22760 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22761 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22763 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 22764 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22765 | // (LDNT1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3517 |
| 22766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 22767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 22768 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22769 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22770 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22771 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 22772 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22773 | // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3524 |
| 22774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22776 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22777 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22778 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22779 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 22780 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 22781 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22782 | // (LDNT1W_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3532 |
| 22783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22785 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22786 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22787 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22788 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22789 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22790 | // (LDNT1W_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3539 |
| 22791 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22792 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 22793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 22794 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 22795 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22796 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 22797 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22798 | // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3546 |
| 22799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 22800 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 22801 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22802 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22803 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22804 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22805 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22806 | // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3553 |
| 22807 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 22808 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 22809 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22810 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22811 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22812 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22813 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22814 | // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3560 |
| 22815 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22816 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22817 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22818 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22819 | // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3564 |
| 22820 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 22821 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 22822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22823 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22824 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22826 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22827 | // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3571 |
| 22828 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22830 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22831 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22832 | // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3575 |
| 22833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22834 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22835 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22836 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22837 | // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3579 |
| 22838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22839 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22840 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22841 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 22843 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22844 | // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3585 |
| 22845 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22846 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22847 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22848 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22849 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 22850 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22851 | // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 3591 |
| 22852 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22853 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22855 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22856 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22857 | // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 3596 |
| 22858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22859 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22860 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22861 | // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 3599 |
| 22862 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 22863 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22865 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22866 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22867 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22868 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22869 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22870 | // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3607 |
| 22871 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 22872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22873 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22874 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22875 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22876 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22877 | // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 3613 |
| 22878 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 22879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22880 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22881 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22882 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22883 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22884 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22885 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22886 | // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3621 |
| 22887 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 22888 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22889 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22890 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22891 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22892 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22893 | // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 3627 |
| 22894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22895 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22896 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22897 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22898 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22899 | // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 3632 |
| 22900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22902 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22903 | // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 3635 |
| 22904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 22905 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22906 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22907 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22908 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22909 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22910 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22911 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22912 | // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3643 |
| 22913 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 22914 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22915 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22916 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22917 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22918 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22919 | // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend128 0, 0)) - 3649 |
| 22920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 22921 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22922 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22923 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22924 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22925 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22926 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22927 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22928 | // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3657 |
| 22929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 22930 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22931 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22933 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22934 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22935 | // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 3663 |
| 22936 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22937 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22938 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22939 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22940 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22941 | // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3668 |
| 22942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22943 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22944 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22945 | // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 3671 |
| 22946 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22947 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22948 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22949 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22950 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22951 | // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3676 |
| 22952 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22953 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22954 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22955 | // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 3679 |
| 22956 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22957 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22958 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22959 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22960 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22961 | // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3684 |
| 22962 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 22963 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22964 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22965 | // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 3687 |
| 22966 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22967 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22969 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22970 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22971 | // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3692 |
| 22972 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22974 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22975 | // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 3695 |
| 22976 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22977 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22978 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22979 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22980 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22981 | // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 3700 |
| 22982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22983 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22984 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22985 | // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 3703 |
| 22986 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 22987 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22988 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 22989 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22990 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22991 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22992 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 22993 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 22994 | // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3711 |
| 22995 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 22996 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 22997 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 22998 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 22999 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 23000 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23001 | // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 3717 |
| 23002 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23003 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23004 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23005 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23006 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23007 | // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3722 |
| 23008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23010 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23011 | // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 3725 |
| 23012 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23013 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23014 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23015 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23016 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23017 | // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 3730 |
| 23018 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23019 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23020 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23021 | // (LDR_PXI PPRorPNRAny:$Pt, GPR64sp:$Rn, 0) - 3733 |
| 23022 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRorPNRRegClassID}, |
| 23023 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23024 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23025 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23026 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 23027 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 23028 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23029 | // (LDR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 3740 |
| 23030 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 23031 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23032 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23033 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23034 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23035 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23036 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 23037 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23038 | // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 3748 |
| 23039 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 23040 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23041 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23042 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23043 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 23044 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 23045 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23046 | // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3755 |
| 23047 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23048 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23049 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23050 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23051 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23052 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23053 | // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3761 |
| 23054 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23055 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23056 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23057 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23058 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23059 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23060 | // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3767 |
| 23061 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23062 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23063 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23065 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23066 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23067 | // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3773 |
| 23068 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23069 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23070 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23073 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23074 | // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3779 |
| 23075 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23076 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23078 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23079 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23080 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23081 | // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3785 |
| 23082 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23085 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23086 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23087 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23088 | // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3791 |
| 23089 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23090 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23091 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23092 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23093 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23094 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23095 | // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3797 |
| 23096 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23097 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23098 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23099 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23100 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23101 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23102 | // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3803 |
| 23103 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23104 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23105 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23106 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23107 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23108 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23109 | // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3809 |
| 23110 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23111 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23112 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23114 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23115 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23116 | // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3815 |
| 23117 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23118 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23119 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23122 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23123 | // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3821 |
| 23124 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23125 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23126 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23128 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23129 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23130 | // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3827 |
| 23131 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23133 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23134 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23135 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23136 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23137 | // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3833 |
| 23138 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23139 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23140 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23141 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23142 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23143 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23144 | // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3839 |
| 23145 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23146 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23147 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23148 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23149 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23150 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23151 | // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3845 |
| 23152 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23153 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23154 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23155 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23156 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23157 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23158 | // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3851 |
| 23159 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23160 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23161 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23163 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23164 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23165 | // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3857 |
| 23166 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23167 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23168 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23169 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23170 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23171 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23172 | // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3863 |
| 23173 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23174 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23175 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23176 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23177 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23178 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23179 | // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3869 |
| 23180 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23181 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23182 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23184 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23185 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23186 | // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3875 |
| 23187 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23188 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23189 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23191 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23192 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23193 | // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3881 |
| 23194 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23196 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23197 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23198 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23199 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23200 | // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3887 |
| 23201 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23202 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23204 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23205 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23206 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23207 | // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3893 |
| 23208 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23209 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23210 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23211 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23212 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23213 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23214 | // (LDTADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3899 |
| 23215 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23216 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23217 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23218 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23219 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23220 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23221 | // (LDTADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3905 |
| 23222 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23223 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23224 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23225 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23226 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23227 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23228 | // (LDTADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3911 |
| 23229 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23230 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23231 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23233 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23234 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23235 | // (LDTADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3917 |
| 23236 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23238 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23240 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23241 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23242 | // (LDTCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3923 |
| 23243 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23245 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23246 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23247 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23248 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23249 | // (LDTCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3929 |
| 23250 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23251 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23253 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23254 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23255 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23256 | // (LDTCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3935 |
| 23257 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23258 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23259 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23260 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23261 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23262 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23263 | // (LDTCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3941 |
| 23264 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23265 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23266 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23267 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23268 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23269 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23270 | // (LDTNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3947 |
| 23271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 23272 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 23273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23274 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23275 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23276 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23277 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23278 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23279 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 23280 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23281 | // (LDTNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3957 |
| 23282 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23283 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23284 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23285 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23286 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23287 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23288 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23289 | // (LDTPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3964 |
| 23290 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 23291 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 23292 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23293 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23294 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23295 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23296 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23297 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23298 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 23299 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23300 | // (LDTPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3974 |
| 23301 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23302 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23303 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23304 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23305 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23306 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23307 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23308 | // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3981 |
| 23309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23310 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23311 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23312 | // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3984 |
| 23313 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23315 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23316 | // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3987 |
| 23317 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23318 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23319 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23320 | // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3990 |
| 23321 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23322 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23323 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23324 | // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3993 |
| 23325 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23326 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23327 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23328 | // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3996 |
| 23329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23331 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23332 | // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 3999 |
| 23333 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23335 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23336 | // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4002 |
| 23337 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23338 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23339 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23340 | // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4005 |
| 23341 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23342 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23343 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23344 | // (LDTSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4008 |
| 23345 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23348 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23349 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23350 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23351 | // (LDTSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4014 |
| 23352 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23353 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23354 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23355 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23356 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23357 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23358 | // (LDTSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4020 |
| 23359 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23360 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23362 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23363 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23364 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23365 | // (LDTSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4026 |
| 23366 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23367 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23368 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23369 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23370 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 23371 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23372 | // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 4032 |
| 23373 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23374 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23375 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23376 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23377 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23378 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23379 | // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 4038 |
| 23380 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23381 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23382 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23383 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23384 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23385 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23386 | // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 4044 |
| 23387 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23389 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23390 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23391 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23392 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23393 | // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 4050 |
| 23394 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23395 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23396 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23397 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23398 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23399 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23400 | // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4056 |
| 23401 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23402 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23403 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23404 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23405 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23406 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23407 | // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4062 |
| 23408 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23409 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23410 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23411 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23412 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23413 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23414 | // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4068 |
| 23415 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23416 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23417 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23418 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23419 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23420 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23421 | // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4074 |
| 23422 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23423 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23424 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23425 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23426 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23427 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23428 | // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 4080 |
| 23429 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23430 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23431 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23433 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23434 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23435 | // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 4086 |
| 23436 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23437 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23438 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23439 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23441 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23442 | // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 4092 |
| 23443 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23444 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23445 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23446 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23447 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23448 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23449 | // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 4098 |
| 23450 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23451 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23452 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23453 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23454 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23455 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23456 | // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4104 |
| 23457 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23458 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23459 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23460 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23461 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23462 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23463 | // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4110 |
| 23464 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23465 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23466 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23467 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23468 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23469 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23470 | // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 4116 |
| 23471 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23472 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23473 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23474 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23475 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23476 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23477 | // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 4122 |
| 23478 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23479 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23480 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23481 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23482 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSE}, |
| 23483 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23484 | // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 4128 |
| 23485 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23486 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23487 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23488 | // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 4131 |
| 23489 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 23490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23491 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23492 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23493 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 23494 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23495 | // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 4137 |
| 23496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 23497 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23498 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23499 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23500 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 23501 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23502 | // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 4143 |
| 23503 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23504 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23505 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23506 | // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 4146 |
| 23507 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 23508 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23509 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23510 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23511 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 23512 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23513 | // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 4152 |
| 23514 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 23515 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23516 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23517 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23518 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 23519 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23520 | // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4158 |
| 23521 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23522 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23523 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23524 | // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4161 |
| 23525 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23527 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23528 | // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4164 |
| 23529 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23530 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23531 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23532 | // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4167 |
| 23533 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23535 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23536 | // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 4170 |
| 23537 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23538 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23539 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23540 | // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 4173 |
| 23541 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 23542 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23543 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23544 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23545 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 23546 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23547 | // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4179 |
| 23548 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23549 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23550 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23551 | // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 4182 |
| 23552 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23553 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 23554 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23555 | // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 4185 |
| 23556 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23557 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23558 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23559 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23560 | // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 4189 |
| 23561 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23563 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23564 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23565 | // (MOVA_2ZMXI_H_B ZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 4193 |
| 23566 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 23568 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23569 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23570 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23571 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23572 | // (MOVA_2ZMXI_H_D ZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 4199 |
| 23573 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23574 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 23575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23576 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23577 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23578 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23579 | // (MOVA_2ZMXI_H_H ZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 4205 |
| 23580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23581 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 23582 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23583 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23584 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23585 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23586 | // (MOVA_2ZMXI_H_S ZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 4211 |
| 23587 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23588 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 23589 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23591 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23592 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23593 | // (MOVA_2ZMXI_V_B ZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 4217 |
| 23594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 23596 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23597 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23598 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23599 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23600 | // (MOVA_2ZMXI_V_D ZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 4223 |
| 23601 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23602 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 23603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23604 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23605 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23606 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23607 | // (MOVA_2ZMXI_V_H ZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 4229 |
| 23608 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23609 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 23610 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23611 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23612 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23613 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23614 | // (MOVA_2ZMXI_V_S ZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 4235 |
| 23615 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23616 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 23617 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23618 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23619 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23620 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23621 | // (MOVA_4ZMXI_H_B ZZZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4241 |
| 23622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23623 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 23624 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23625 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23626 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23627 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23628 | // (MOVA_4ZMXI_H_D ZZZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4247 |
| 23629 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 23631 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23632 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23633 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23634 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23635 | // (MOVA_4ZMXI_H_H ZZZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4253 |
| 23636 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23637 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 23638 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23639 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23640 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23641 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23642 | // (MOVA_4ZMXI_H_S ZZZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4259 |
| 23643 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23644 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 23645 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23646 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23647 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23648 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23649 | // (MOVA_4ZMXI_V_B ZZZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4265 |
| 23650 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23651 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 23652 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23653 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23654 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23655 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23656 | // (MOVA_4ZMXI_V_D ZZZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4271 |
| 23657 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23658 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 23659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23660 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23661 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23662 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23663 | // (MOVA_4ZMXI_V_H ZZZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4277 |
| 23664 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23665 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 23666 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23667 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23668 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23669 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23670 | // (MOVA_4ZMXI_V_S ZZZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4283 |
| 23671 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23672 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 23673 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23674 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23675 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23676 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23677 | // (MOVA_MXI2Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4289 |
| 23678 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 23679 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23680 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23681 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23682 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23683 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23684 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23685 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23686 | // (MOVA_MXI2Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4297 |
| 23687 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 23688 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23689 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23690 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23691 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23692 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23693 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23694 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23695 | // (MOVA_MXI2Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4305 |
| 23696 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 23697 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23698 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23699 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23700 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23701 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23702 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23703 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23704 | // (MOVA_MXI2Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4313 |
| 23705 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 23706 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23707 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23708 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23709 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23710 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23711 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23712 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23713 | // (MOVA_MXI2Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4321 |
| 23714 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 23715 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23717 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23718 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23719 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23721 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23722 | // (MOVA_MXI2Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4329 |
| 23723 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 23724 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23725 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23726 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23727 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23728 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23729 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23730 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23731 | // (MOVA_MXI2Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4337 |
| 23732 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 23733 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23734 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23735 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23736 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23737 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23738 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23739 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23740 | // (MOVA_MXI2Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4345 |
| 23741 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 23742 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23743 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23744 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23745 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23746 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23747 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23748 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23749 | // (MOVA_MXI4Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4353 |
| 23750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 23751 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23752 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23753 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23754 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23755 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23756 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23757 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23758 | // (MOVA_MXI4Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4361 |
| 23759 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 23760 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23761 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23762 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23763 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23764 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23765 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23766 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23767 | // (MOVA_MXI4Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4369 |
| 23768 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 23769 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23770 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23771 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23773 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23774 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23775 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23776 | // (MOVA_MXI4Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4377 |
| 23777 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 23778 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23780 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23782 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23783 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23784 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23785 | // (MOVA_MXI4Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4385 |
| 23786 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 23787 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23789 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23790 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23791 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23792 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23793 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23794 | // (MOVA_MXI4Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4393 |
| 23795 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 23796 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23798 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23800 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23802 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23803 | // (MOVA_MXI4Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4401 |
| 23804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 23805 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23807 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23808 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23809 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23810 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23811 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23812 | // (MOVA_MXI4Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4409 |
| 23813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 23814 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23815 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 23816 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23817 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23818 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23819 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23820 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23821 | // (MOVA_VG2_2ZMXI ZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4417 |
| 23822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23823 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 23824 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 23825 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23826 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23827 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23828 | // (MOVA_VG2_MXI2Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZ_d_mul_r:$Zn) - 4423 |
| 23829 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 23830 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23831 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 23832 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 23834 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23836 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23837 | // (MOVA_VG4_4ZMXI ZZZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4431 |
| 23838 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23839 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 23840 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 23841 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23842 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23843 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23844 | // (MOVA_VG4_MXI4Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZZZ_d_mul_r:$Zn) - 4437 |
| 23845 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 23846 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23847 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| 23848 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23849 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 23850 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23851 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 23852 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23853 | // (MOVT_TIZ ZTR:$ZTt, 0, ZPRAny:$Zt) - 4445 |
| 23854 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZTRRegClassID}, |
| 23855 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23856 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 23857 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23858 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME_LUTv2}, |
| 23859 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23860 | // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 1 }) - 4451 |
| 23861 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 23862 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 23863 | // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 1 }) - 4453 |
| 23864 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 23865 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 23866 | // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 1 }) - 4455 |
| 23867 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 23868 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 23869 | // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 0 }) - 4457 |
| 23870 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 23871 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23872 | // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 0 }) - 4459 |
| 23873 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 23874 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23875 | // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 0 }) - 4461 |
| 23876 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 23877 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23878 | // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 4463 |
| 23879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23880 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23881 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23882 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23883 | // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 4467 |
| 23884 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23885 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23887 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23888 | // (NOP) - 4471 |
| 23889 | // (NOTv16i8 V128:$Vd, V128:$Vn) - 4471 |
| 23890 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 23891 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 23892 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23893 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 23894 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23895 | // (NOTv8i8 V64:$Vd, V64:$Vn) - 4476 |
| 23896 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 23897 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 23898 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23899 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 23900 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23901 | // (ORNWrs GPR32:$Wd, WZR, (logical_shifted_reg32 GPR32:$Wm, 0)) - 4481 |
| 23902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23903 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23904 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23905 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23906 | // (ORNWrs GPR32:$Wd, WZR, (logical_shifted_reg32 GPR32:$Wm, logical_shift32:$sh)) - 4485 |
| 23907 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23908 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23910 | // (ORNWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 4488 |
| 23911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23913 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23914 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23915 | // (ORNXrs GPR64:$Xd, XZR, (logical_shifted_reg64 GPR64:$Xm, 0)) - 4492 |
| 23916 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23917 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23919 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23920 | // (ORNXrs GPR64:$Xd, XZR, (logical_shifted_reg64 GPR64:$Xm, logical_shift64:$sh)) - 4496 |
| 23921 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23922 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23923 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23924 | // (ORNXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 4499 |
| 23925 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23928 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23929 | // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4503 |
| 23930 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 23931 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 23932 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 23933 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 23934 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23935 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 23936 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 23937 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23938 | // (ORRWrs GPR32:$dst, WZR, (logical_shifted_reg32 GPR32:$src, 0)) - 4511 |
| 23939 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23940 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 23941 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23942 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23943 | // (ORRWrs GPR32:$dst, GPR32:$src1, (logical_shifted_reg32 GPR32:$src2, 0)) - 4515 |
| 23944 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23945 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23946 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 23947 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23948 | // (ORRXrs GPR64:$dst, XZR, (logical_shifted_reg64 GPR64:$src, 0)) - 4519 |
| 23949 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23950 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 23951 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23952 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23953 | // (ORRXrs GPR64:$dst, GPR64:$src1, (logical_shifted_reg64 GPR64:$src2, 0)) - 4523 |
| 23954 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23955 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23956 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 23957 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 23958 | // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4527 |
| 23959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 23960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 23961 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 23962 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 23963 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23964 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 23965 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 23966 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23967 | // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 4535 |
| 23968 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 23969 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23970 | {.Kind: AliasPatternCond::K_Custom, .Value: 1}, |
| 23971 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23972 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 23973 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 23974 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23975 | // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 4542 |
| 23976 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 23977 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23978 | {.Kind: AliasPatternCond::K_Custom, .Value: 2}, |
| 23979 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23980 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 23981 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 23982 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23983 | // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 4549 |
| 23984 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 23985 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 23986 | {.Kind: AliasPatternCond::K_Custom, .Value: 3}, |
| 23987 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23988 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 23989 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 23990 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23991 | // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 4556 |
| 23992 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 23993 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 23994 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 23995 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 23996 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 23997 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 23998 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 23999 | // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 4563 |
| 24000 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 24001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 24002 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 24003 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24005 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24006 | // (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 4569 |
| 24007 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 24008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 24009 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 1}, |
| 24010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24011 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24012 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24013 | // (PACIA1716) - 4575 |
| 24014 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24015 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 24016 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24017 | // (PACIASP) - 4578 |
| 24018 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24019 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 24020 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24021 | // (PACIAZ) - 4581 |
| 24022 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24023 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 24024 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24025 | // (PACIB1716) - 4584 |
| 24026 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24027 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 24028 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24029 | // (PACIBSP) - 4587 |
| 24030 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 24032 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24033 | // (PACIBZ) - 4590 |
| 24034 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24035 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 24036 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24037 | // (PACM) - 4593 |
| 24038 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuthLR}, |
| 24040 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24041 | // (PMOV_PZI_B PPR8:$Pd, ZPRAny:$Zn, 0) - 4596 |
| 24042 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24043 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24044 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24045 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24046 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 24047 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 24048 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24049 | // (PMOV_ZIP_B ZPRAny:$Zd, 0, PPR8:$Pn) - 4603 |
| 24050 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24051 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24052 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24053 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24054 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24055 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 24056 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 24057 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24058 | // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4611 |
| 24059 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24060 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24061 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24062 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24065 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24066 | // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4618 |
| 24067 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24069 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24070 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24074 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24075 | // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4626 |
| 24076 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24078 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24079 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24081 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24082 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24083 | // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4633 |
| 24084 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24085 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24086 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24087 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24088 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24089 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24090 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24091 | // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4640 |
| 24092 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24093 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24094 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24095 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24096 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24097 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24098 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24099 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24100 | // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4648 |
| 24101 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24102 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24103 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24104 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24105 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24106 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24107 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24108 | // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4655 |
| 24109 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24110 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24111 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24112 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24113 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24114 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24115 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24116 | // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4662 |
| 24117 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24118 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24119 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24120 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24121 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24122 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24123 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24124 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24125 | // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4670 |
| 24126 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24127 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24128 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24129 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24130 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24132 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24133 | // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 4677 |
| 24134 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24135 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24136 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24137 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24138 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24139 | // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 4682 |
| 24140 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24141 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24142 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24143 | // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 4685 |
| 24144 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24145 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24146 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24147 | // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4688 |
| 24148 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24149 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24150 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24151 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24153 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24154 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24155 | // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4695 |
| 24156 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24157 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24158 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24159 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24160 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24161 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24163 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24164 | // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4703 |
| 24165 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24166 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24167 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24168 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24169 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24170 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24171 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24172 | // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4710 |
| 24173 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24174 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24175 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24176 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24177 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24178 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24179 | // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4716 |
| 24180 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24181 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24182 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24184 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24185 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24186 | // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4722 |
| 24187 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24188 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24191 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24192 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24193 | // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4728 |
| 24194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24195 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24196 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24197 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24198 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24199 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24200 | // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4734 |
| 24201 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24202 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24203 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24204 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24205 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24206 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24207 | // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4740 |
| 24208 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24209 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24210 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24211 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24212 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24213 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24214 | // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4746 |
| 24215 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24216 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24217 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24218 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24219 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24220 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24221 | // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4752 |
| 24222 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24223 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24224 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24225 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24226 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24227 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24228 | // (RET LR) - 4758 |
| 24229 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::LR}, |
| 24230 | // (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 4759 |
| 24231 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24232 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 24233 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24234 | // (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 4762 |
| 24235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24236 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24238 | // (SBCWr GPR32:$dst, WZR, GPR32:$src) - 4765 |
| 24239 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24240 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 24241 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24242 | // (SBCXr GPR64:$dst, XZR, GPR64:$src) - 4768 |
| 24243 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24244 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24245 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24246 | // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 4771 |
| 24247 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24248 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24249 | {.Kind: AliasPatternCond::K_Custom, .Value: 8}, |
| 24250 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24251 | // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 4775 |
| 24252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24253 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24254 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24255 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 24256 | // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 4779 |
| 24257 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24258 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24259 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24260 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 24261 | // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 4783 |
| 24262 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24263 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24264 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24265 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(63)}, |
| 24266 | // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 4787 |
| 24267 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24268 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24269 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24270 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 24271 | // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 4791 |
| 24272 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24274 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24275 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 24276 | // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 4795 |
| 24277 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24278 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24279 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24280 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24281 | // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 4799 |
| 24282 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24283 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24284 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24285 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 24286 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24287 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24288 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24289 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24290 | // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 4807 |
| 24291 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24292 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24293 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24294 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 24295 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24296 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24297 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24298 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24299 | // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 4815 |
| 24300 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24301 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24302 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24303 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 24304 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24305 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24306 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24307 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24308 | // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 4823 |
| 24309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24310 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24311 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24312 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 24313 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24314 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24315 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24316 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24317 | // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 4831 |
| 24318 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24319 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRRegClassID}, |
| 24320 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24321 | {.Kind: AliasPatternCond::K_TiedReg, .Value: 0}, |
| 24322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24323 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24324 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24325 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24326 | // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4839 |
| 24327 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24328 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24330 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24331 | // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4843 |
| 24332 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24333 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24334 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 24335 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24336 | // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4847 |
| 24337 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24338 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24339 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24340 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24343 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24344 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24345 | // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4855 |
| 24346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24347 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24348 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24349 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24350 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24351 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24352 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24353 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24354 | // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4863 |
| 24355 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24356 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24357 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24358 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24359 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24360 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24361 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24362 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24363 | // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4871 |
| 24364 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24365 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24366 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24367 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24368 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24369 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24370 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24371 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24372 | // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4879 |
| 24373 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24374 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24375 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24376 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24377 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24378 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24379 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24380 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24381 | // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4887 |
| 24382 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24383 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24384 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24385 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24386 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24387 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24388 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24389 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24390 | // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4895 |
| 24391 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24392 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24393 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24394 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24395 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24396 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24397 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24398 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24399 | // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4903 |
| 24400 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24401 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24402 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24403 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24404 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24405 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24406 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24407 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24408 | // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4911 |
| 24409 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24410 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24411 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24412 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24413 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24414 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24415 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24416 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24417 | // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4919 |
| 24418 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24419 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24420 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24421 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24422 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24423 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24424 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24425 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24426 | // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4927 |
| 24427 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24428 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24429 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24430 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24431 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24432 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24433 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24434 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24435 | // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4935 |
| 24436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24437 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24438 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24439 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24440 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24441 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24442 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24443 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24444 | // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4943 |
| 24445 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24446 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24447 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24448 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24449 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24450 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24452 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24453 | // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4951 |
| 24454 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24456 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24457 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24458 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24460 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24461 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24462 | // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4959 |
| 24463 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24464 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24465 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24466 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24467 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24468 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24469 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24470 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24471 | // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4967 |
| 24472 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24473 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24474 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24475 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24476 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24477 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24478 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24479 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24480 | // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4975 |
| 24481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24482 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24483 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24484 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24485 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24486 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24487 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24488 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24489 | // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4983 |
| 24490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24491 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24492 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24493 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24494 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24495 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24496 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24497 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24498 | // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4991 |
| 24499 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24500 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24501 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24502 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24503 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24504 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24505 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24506 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24507 | // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4999 |
| 24508 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24509 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24510 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24511 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24512 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24513 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24515 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24516 | // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 5007 |
| 24517 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24518 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24519 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24520 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24521 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24522 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24523 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24524 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24525 | // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 5015 |
| 24526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24527 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24528 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24529 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24530 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24531 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24532 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24533 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24534 | // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5023 |
| 24535 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24536 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24537 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24538 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24539 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24540 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24541 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24542 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24543 | // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5031 |
| 24544 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24545 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24546 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24547 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24548 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24549 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24550 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24551 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24552 | // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5039 |
| 24553 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24555 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24556 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24557 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24558 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24559 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24560 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24561 | // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5047 |
| 24562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24563 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24564 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24565 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24566 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24567 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24568 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24569 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24570 | // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5055 |
| 24571 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24572 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24573 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24574 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24575 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24576 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24577 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24578 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24579 | // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5063 |
| 24580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24581 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24582 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24583 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24584 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24585 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24586 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24587 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24588 | // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5071 |
| 24589 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24590 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24591 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24592 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24593 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24594 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24595 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24596 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24597 | // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5079 |
| 24598 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24599 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24600 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24601 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24602 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24603 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24604 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24605 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24606 | // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 5087 |
| 24607 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24608 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24609 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24610 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24611 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24612 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24613 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24614 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24615 | // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 5095 |
| 24616 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24617 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24618 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24619 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24620 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24621 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24622 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24623 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24624 | // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5103 |
| 24625 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24626 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24627 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24628 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24629 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24630 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24631 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24632 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24633 | // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5111 |
| 24634 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24635 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24636 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24637 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24638 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24639 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24640 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24641 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24642 | // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5119 |
| 24643 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24644 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24645 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24646 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24647 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24648 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24649 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24650 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24651 | // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5127 |
| 24652 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24653 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24654 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24655 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24656 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24657 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24658 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24659 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24660 | // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 5135 |
| 24661 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24662 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24663 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24664 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24665 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24666 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24667 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24668 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24669 | // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 5143 |
| 24670 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24671 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24672 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24673 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24674 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24675 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24676 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24677 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24678 | // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5151 |
| 24679 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24680 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24681 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24682 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24683 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24684 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24685 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24686 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24687 | // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5159 |
| 24688 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24689 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24690 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24691 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24692 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24693 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24694 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24695 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24696 | // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5167 |
| 24697 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24698 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24699 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24700 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24701 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24702 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24703 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24704 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24705 | // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5175 |
| 24706 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24707 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 24708 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24709 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24710 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24711 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24712 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24713 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24714 | // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 5183 |
| 24715 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24716 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24717 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 24718 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24719 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24720 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24721 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24722 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24723 | // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 5191 |
| 24724 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24725 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24726 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24727 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 24728 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24729 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24730 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24731 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24732 | // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5199 |
| 24733 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24734 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24735 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24736 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24737 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24738 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24739 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24740 | // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5206 |
| 24741 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24742 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24743 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24744 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24745 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24746 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24747 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24748 | // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5213 |
| 24749 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24750 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24751 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24752 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24753 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24754 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24755 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24756 | // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5220 |
| 24757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24759 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24760 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24761 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24762 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24763 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24764 | // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5227 |
| 24765 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24766 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24768 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24769 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24770 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24771 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24772 | // (SST1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 5234 |
| 24773 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24774 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24775 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24776 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24777 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24778 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 24779 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24780 | // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5241 |
| 24781 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24782 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24784 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24785 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24786 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24787 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24788 | // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5248 |
| 24789 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24790 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24791 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24792 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24793 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24794 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24795 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24796 | // (ST1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5255 |
| 24797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 24798 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24800 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24802 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24803 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 24804 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24805 | // (ST1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5263 |
| 24806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 24807 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24808 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24809 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24810 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24811 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24812 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24813 | // (ST1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5270 |
| 24814 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 24815 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24816 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24817 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24818 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24819 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24820 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 24821 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24822 | // (ST1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5278 |
| 24823 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 24824 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24825 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24826 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24827 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24828 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24829 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24830 | // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5285 |
| 24831 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24833 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24834 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24835 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24836 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24837 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24838 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24839 | // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5293 |
| 24840 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24841 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24842 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24843 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24844 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24845 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24846 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24847 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24848 | // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5301 |
| 24849 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24850 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24851 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24852 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24853 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24854 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24855 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24856 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24857 | // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5309 |
| 24858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24859 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24860 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24861 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24862 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24863 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24864 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24865 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24866 | // (ST1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5317 |
| 24867 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 24868 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24869 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24870 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24871 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24872 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24873 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 24874 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24875 | // (ST1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5325 |
| 24876 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 24877 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24878 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24879 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24880 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24881 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24882 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24883 | // (ST1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5332 |
| 24884 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 24885 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24887 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24888 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24889 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24890 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 24891 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24892 | // (ST1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5340 |
| 24893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 24894 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24895 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24896 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24897 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24898 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24899 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24900 | // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5347 |
| 24901 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24902 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24903 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24904 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 24907 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 24908 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24909 | // (ST1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5355 |
| 24910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 24911 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 24912 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24913 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24914 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24915 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 24916 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24917 | // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 5362 |
| 24918 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 24920 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24921 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24922 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24924 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24925 | // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 5369 |
| 24926 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24927 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 24928 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24929 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24930 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24931 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24932 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24933 | // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 5376 |
| 24934 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24935 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 24936 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24937 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24938 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24939 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24940 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24941 | // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 5383 |
| 24942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24943 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 24944 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24945 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24946 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24947 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24948 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24949 | // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 5390 |
| 24950 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24951 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 24952 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24953 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24954 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24955 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24956 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24957 | // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 5397 |
| 24958 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 24960 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24961 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24962 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24963 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24964 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24965 | // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 5404 |
| 24966 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24967 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 24968 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24969 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24970 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24971 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24972 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24973 | // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 5411 |
| 24974 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24975 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 24976 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 24977 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 24978 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24979 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 24980 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24981 | // (ST1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5418 |
| 24982 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 24983 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24984 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24985 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24986 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24987 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24988 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 24989 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24990 | // (ST1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5426 |
| 24991 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 24992 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 24993 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 24994 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 24995 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 24996 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 24997 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 24998 | // (ST1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5433 |
| 24999 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 25000 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 25001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25002 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25003 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 25005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 25006 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25007 | // (ST1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5441 |
| 25008 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 25009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 25010 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25011 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25012 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25013 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 25014 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25015 | // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5448 |
| 25016 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 25017 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25018 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25019 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25020 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25021 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25022 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25023 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25024 | // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5456 |
| 25025 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 25026 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25027 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25028 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25029 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25030 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25032 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25033 | // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5464 |
| 25034 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 25035 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25037 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25038 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25040 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25041 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25042 | // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 5472 |
| 25043 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25044 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25045 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25046 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25047 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25049 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25050 | // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 5479 |
| 25051 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25052 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 25053 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25054 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25055 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25056 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25057 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25058 | // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 5486 |
| 25059 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25060 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25061 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25062 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25065 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25066 | // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 5493 |
| 25067 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 25069 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25070 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25071 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25073 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25074 | // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 5500 |
| 25075 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25076 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 25077 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25078 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25079 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25081 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25082 | // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 5507 |
| 25083 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25084 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25085 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25086 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25087 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25088 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25089 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25090 | // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 5514 |
| 25091 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25092 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 25093 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25094 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25095 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25096 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25097 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25098 | // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 5521 |
| 25099 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25100 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25101 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25102 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25103 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25104 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25105 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25106 | // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5528 |
| 25107 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25108 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25109 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25110 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25111 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25112 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25113 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25114 | // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 5535 |
| 25115 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25116 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 25117 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25118 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25120 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25121 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25122 | // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5542 |
| 25123 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25124 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25125 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25126 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25128 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25129 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25130 | // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5549 |
| 25131 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25132 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 25133 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25134 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25135 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25137 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25138 | // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5556 |
| 25139 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25140 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 25141 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25142 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25143 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25145 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25146 | // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 5563 |
| 25147 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25148 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25149 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25150 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25151 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25152 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25153 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25154 | // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 5570 |
| 25155 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25156 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 25157 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25158 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25159 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25160 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25161 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25162 | // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 5577 |
| 25163 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25164 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25165 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25166 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25167 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25168 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25169 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25170 | // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5584 |
| 25171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25172 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25173 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25174 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25175 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25176 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25177 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25178 | // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 5591 |
| 25179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25180 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 25181 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25182 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25184 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25185 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25186 | // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5598 |
| 25187 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25188 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25189 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25190 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25191 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25192 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25193 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25194 | // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5605 |
| 25195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25196 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 25197 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25198 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25199 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25200 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25201 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25202 | // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5612 |
| 25203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25204 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 25205 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25206 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25207 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25208 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25209 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25210 | // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5619 |
| 25211 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25212 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25213 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25214 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25216 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25217 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25218 | // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5626 |
| 25219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 25221 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25222 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25224 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25225 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25226 | // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5633 |
| 25227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25229 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25230 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25233 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25234 | // (ST1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5640 |
| 25235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 25236 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 25237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25238 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25239 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25240 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 25241 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 25242 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25243 | // (ST1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5648 |
| 25244 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 25245 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 25246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25247 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25248 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25249 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 25250 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25251 | // (ST1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5655 |
| 25252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 25253 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 25254 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25255 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25256 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25257 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 25258 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 25259 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25260 | // (ST1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5663 |
| 25261 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 25262 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 25263 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25264 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25265 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25266 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 25267 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25268 | // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5670 |
| 25269 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 25270 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25272 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25273 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25274 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25275 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25276 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25277 | // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5678 |
| 25278 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 25279 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25281 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25284 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25285 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25286 | // (ST1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5686 |
| 25287 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 25288 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25289 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25290 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25291 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25292 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 25293 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25294 | // (ST1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5693 |
| 25295 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 25296 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25297 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25298 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25299 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25300 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25301 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25302 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25303 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25304 | // (ST1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5702 |
| 25305 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 25306 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25307 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25308 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25309 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25310 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25311 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25312 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25313 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25314 | // (ST1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5711 |
| 25315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 25316 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25317 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25318 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25319 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25320 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25321 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25322 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25323 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25324 | // (ST1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5720 |
| 25325 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 25326 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25327 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25328 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25330 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25331 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25332 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25333 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25334 | // (ST1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5729 |
| 25335 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 25336 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25337 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25338 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25340 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25343 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25344 | // (ST1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5738 |
| 25345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR8RegClassID}, |
| 25346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25347 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25348 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25349 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25350 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25351 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25352 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25353 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25354 | // (ST1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5747 |
| 25355 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR64RegClassID}, |
| 25356 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25357 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25358 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25359 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25360 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25361 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25362 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25363 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25364 | // (ST1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5756 |
| 25365 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR16RegClassID}, |
| 25366 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25367 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25368 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25369 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25370 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25371 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25372 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25373 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25374 | // (ST1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5765 |
| 25375 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR128RegClassID}, |
| 25376 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25377 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25378 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25379 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25380 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25381 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25382 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25383 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25384 | // (ST1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5774 |
| 25385 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPR32RegClassID}, |
| 25386 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 25387 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25388 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25389 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25390 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25391 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25392 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25393 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25394 | // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 5783 |
| 25395 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25396 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25397 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25398 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25399 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25400 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25401 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25402 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25403 | // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 5791 |
| 25404 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25405 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25406 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25407 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25408 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25409 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25410 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25411 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25412 | // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 5799 |
| 25413 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25414 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25415 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25416 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25417 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25418 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25419 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25420 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25421 | // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 5807 |
| 25422 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25423 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25424 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25425 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25426 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25427 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25428 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25429 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25430 | // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5815 |
| 25431 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 25432 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25433 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25434 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25435 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25436 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25437 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25438 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25439 | // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5823 |
| 25440 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 25441 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25442 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25443 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25444 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25445 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25446 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25447 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25448 | // (ST2Gi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 5831 |
| 25449 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25450 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25451 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25453 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 25454 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25455 | // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5837 |
| 25456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 25457 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25458 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25459 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25460 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25461 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25462 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25463 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25464 | // (ST2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5845 |
| 25465 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 25466 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25467 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25468 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25469 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25470 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 25471 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 25472 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25473 | // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5853 |
| 25474 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25475 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25476 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25477 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25478 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25479 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25480 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25481 | // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5860 |
| 25482 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25483 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25484 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25485 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25486 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25487 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25488 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25489 | // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5867 |
| 25490 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25491 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 25492 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25493 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25494 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25495 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25496 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25497 | // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5874 |
| 25498 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25499 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 25500 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25501 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25502 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25503 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25504 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25505 | // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5881 |
| 25506 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25507 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25508 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25509 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25510 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25511 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25512 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25513 | // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5888 |
| 25514 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25515 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDRegClassID}, |
| 25516 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25517 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25518 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25519 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25520 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25521 | // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5895 |
| 25522 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25523 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25524 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25525 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25526 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25527 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25528 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25529 | // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5902 |
| 25530 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2RegClassID}, |
| 25531 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25532 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25533 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25534 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25535 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25536 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25537 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25538 | // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 5910 |
| 25539 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25540 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25541 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25542 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25543 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25544 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25545 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25546 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25547 | // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 5918 |
| 25548 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25549 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25550 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25551 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25552 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25553 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25554 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25555 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25556 | // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 5926 |
| 25557 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25558 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25559 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25560 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25561 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25562 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25563 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25564 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25565 | // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 5934 |
| 25566 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQRegClassID}, |
| 25568 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25569 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25570 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25571 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25572 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25573 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25574 | // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5942 |
| 25575 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 25576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25577 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25578 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25579 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25580 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25581 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25582 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25583 | // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5950 |
| 25584 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 25585 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25586 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25587 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25588 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25589 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25590 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25591 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25592 | // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5958 |
| 25593 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 25594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25595 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25596 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25597 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25598 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25599 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25600 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25601 | // (ST3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5966 |
| 25602 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 25603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25604 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25605 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25606 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25607 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 25608 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 25609 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25610 | // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5974 |
| 25611 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25612 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25613 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25614 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25615 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25616 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25617 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25618 | // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5981 |
| 25619 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25620 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25621 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25622 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25623 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25624 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25625 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25626 | // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5988 |
| 25627 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25628 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 25629 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25630 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25631 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25632 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25633 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25634 | // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5995 |
| 25635 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25636 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 25637 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25638 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25639 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25640 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25641 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25642 | // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 6002 |
| 25643 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25644 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25645 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25646 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25647 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25648 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25649 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25650 | // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 6009 |
| 25651 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25652 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDRegClassID}, |
| 25653 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25654 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25655 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25656 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25657 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25658 | // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 6016 |
| 25659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25660 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25661 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25662 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25663 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25664 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25665 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25666 | // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6023 |
| 25667 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR3RegClassID}, |
| 25668 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25669 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25670 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25671 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25672 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25673 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25674 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25675 | // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 6031 |
| 25676 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25677 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25678 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25679 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25680 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25681 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25682 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25683 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25684 | // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 6039 |
| 25685 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25686 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25687 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25688 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25689 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25690 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25691 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25692 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25693 | // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 6047 |
| 25694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25695 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25696 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25697 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25698 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25699 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25700 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25701 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25702 | // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 6055 |
| 25703 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25704 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQRegClassID}, |
| 25705 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25706 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25707 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25708 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25709 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25710 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25711 | // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6063 |
| 25712 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 25713 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25714 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25715 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25716 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25717 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25718 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25719 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25720 | // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6071 |
| 25721 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 25722 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25723 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25724 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25725 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25726 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25727 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25728 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25729 | // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 6079 |
| 25730 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25731 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 25732 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25733 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25734 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25735 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25736 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25737 | // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 6086 |
| 25738 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25739 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 25740 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25741 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25742 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25744 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25745 | // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 6093 |
| 25746 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 25748 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25749 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25750 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25751 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25752 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25753 | // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 6100 |
| 25754 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25755 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 25756 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25757 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25758 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25759 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25760 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25761 | // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 6107 |
| 25762 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25763 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 25764 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25765 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25766 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25767 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25768 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25769 | // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 6114 |
| 25770 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25771 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::DDDDRegClassID}, |
| 25772 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25773 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25774 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25775 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25776 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25777 | // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 6121 |
| 25778 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25779 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 25780 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25781 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25782 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25783 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25784 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25785 | // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6128 |
| 25786 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 25787 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25789 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25790 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25791 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25792 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25793 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25794 | // (ST4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6136 |
| 25795 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 25796 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25797 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25798 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25799 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25800 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2p1}, |
| 25801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 25802 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25803 | // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6144 |
| 25804 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4RegClassID}, |
| 25805 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 25806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25807 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25809 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 25810 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 25811 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25812 | // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 6152 |
| 25813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25814 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 25815 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25816 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25817 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25818 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25819 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25820 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25821 | // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 6160 |
| 25822 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25823 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 25824 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25825 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25826 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25827 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25828 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25829 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25830 | // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 6168 |
| 25831 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25832 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 25833 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25834 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25835 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25836 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25837 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25838 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25839 | // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 6176 |
| 25840 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25841 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::QQQQRegClassID}, |
| 25842 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25843 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 25844 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 25845 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25846 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25847 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25848 | // (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6184 |
| 25849 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25850 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25851 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25852 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25853 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25854 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 25855 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25856 | // (STGi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6191 |
| 25857 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25858 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25859 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25860 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25861 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 25862 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25863 | // (STLPi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn) - 6197 |
| 25864 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25865 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25866 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25867 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25868 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSCP}, |
| 25869 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25870 | // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 6203 |
| 25871 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25872 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25873 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25874 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25875 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 25876 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25877 | // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 6209 |
| 25878 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25880 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25881 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25882 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 25883 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25884 | // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 6215 |
| 25885 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25886 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25887 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25888 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25889 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 25890 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25891 | // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 6221 |
| 25892 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25893 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25894 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25895 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25896 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC_IMMO}, |
| 25897 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25898 | // (STLURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 6227 |
| 25899 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 25900 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25901 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25902 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25903 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 25904 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25905 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25906 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25907 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25908 | // (STLURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 6236 |
| 25909 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 25910 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25911 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25912 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25913 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 25914 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25915 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25916 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25917 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25918 | // (STLURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 6245 |
| 25919 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 25920 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25921 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25922 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25923 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 25924 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25925 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25926 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25927 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25928 | // (STLURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 6254 |
| 25929 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25930 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25931 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25932 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25933 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 25934 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25935 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25936 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25937 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25938 | // (STLURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 6263 |
| 25939 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 25940 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25941 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25942 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25943 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureRCPC3}, |
| 25944 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25945 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25946 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 25947 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25948 | // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6272 |
| 25949 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 25950 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 25951 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25952 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25953 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25954 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 25955 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25956 | // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6279 |
| 25957 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25958 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 25959 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25960 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25961 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25962 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 25963 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25964 | // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6286 |
| 25965 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 25966 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 25967 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25968 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25969 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25970 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 25971 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25972 | // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6293 |
| 25973 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25974 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 25975 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25976 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25977 | // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6297 |
| 25978 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25979 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 25980 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25981 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25982 | // (STNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6301 |
| 25983 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 25984 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 25985 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25986 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25987 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25988 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 25989 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 25990 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25991 | // (STNT1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6309 |
| 25992 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 25993 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 25994 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 25995 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 25996 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 25997 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 25998 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 25999 | // (STNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6316 |
| 26000 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 26001 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26002 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26003 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26004 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26005 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26006 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 26007 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26008 | // (STNT1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6324 |
| 26009 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 26010 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26011 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26012 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26013 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26014 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26015 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26016 | // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6331 |
| 26017 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26018 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26019 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26020 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26021 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26022 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26023 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26024 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26025 | // (STNT1B_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6339 |
| 26026 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26027 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26028 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26029 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26030 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26031 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 26032 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26033 | // (STNT1B_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6346 |
| 26034 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26035 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26036 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26037 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26038 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26039 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 26040 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26041 | // (STNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6353 |
| 26042 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 26043 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26044 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26045 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26046 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26047 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26048 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 26049 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26050 | // (STNT1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6361 |
| 26051 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 26052 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26053 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26054 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26055 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26056 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26057 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26058 | // (STNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6368 |
| 26059 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 26060 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26061 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26062 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26065 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 26066 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26067 | // (STNT1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6376 |
| 26068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 26069 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26070 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26071 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26074 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26075 | // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6383 |
| 26076 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26078 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26079 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26080 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26081 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26082 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26083 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26084 | // (STNT1D_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6391 |
| 26085 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26086 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26087 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26088 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26089 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26090 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 26091 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26092 | // (STNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6398 |
| 26093 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 26094 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26095 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26096 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26097 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26098 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26099 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 26100 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26101 | // (STNT1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6406 |
| 26102 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 26103 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26104 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26105 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26106 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26107 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26108 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26109 | // (STNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6413 |
| 26110 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 26111 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26112 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26113 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26114 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26115 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26116 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 26117 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26118 | // (STNT1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6421 |
| 26119 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 26120 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26121 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26122 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26123 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26124 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26125 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26126 | // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6428 |
| 26127 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26128 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26129 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26130 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26131 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26132 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26133 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26134 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26135 | // (STNT1H_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6436 |
| 26136 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26137 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26138 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26139 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26140 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26141 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 26142 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26143 | // (STNT1H_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6443 |
| 26144 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26145 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26146 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26147 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26148 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26149 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 26150 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26151 | // (STNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6450 |
| 26152 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2Mul2RegClassID}, |
| 26153 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26154 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26155 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26156 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26157 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26158 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 26159 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26160 | // (STNT1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6458 |
| 26161 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR2StridedRegClassID}, |
| 26162 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26163 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26164 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26165 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26166 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26167 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26168 | // (STNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6465 |
| 26169 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4Mul4RegClassID}, |
| 26170 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26171 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26172 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26173 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26174 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26175 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2p1}, |
| 26176 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26177 | // (STNT1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6473 |
| 26178 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPR4StridedRegClassID}, |
| 26179 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PNR_p8to15RegClassID}, |
| 26180 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26181 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26182 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26183 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME2}, |
| 26184 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26185 | // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6480 |
| 26186 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26187 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26188 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26189 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26191 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26192 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26193 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26194 | // (STNT1W_ZZR_D Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6488 |
| 26195 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26196 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26197 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26198 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26199 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26200 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 26201 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26202 | // (STNT1W_ZZR_S Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6495 |
| 26203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26204 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPR_3bRegClassID}, |
| 26205 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26206 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26207 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26208 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE2}, |
| 26209 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26210 | // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6502 |
| 26211 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 26212 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 26213 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26214 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26215 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26216 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26217 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26218 | // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6509 |
| 26219 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26220 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26221 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26222 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26224 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26225 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26226 | // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6516 |
| 26227 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 26228 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 26229 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26230 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26231 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26233 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26234 | // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6523 |
| 26235 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26236 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26237 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26238 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26239 | // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6527 |
| 26240 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26241 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26242 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26243 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26244 | // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 6531 |
| 26245 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26246 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26247 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26248 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26249 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26250 | // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6536 |
| 26251 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26252 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26253 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26254 | // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend8 0, 0)) - 6539 |
| 26255 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 26256 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26257 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26258 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26259 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26260 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26261 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26262 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26263 | // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6547 |
| 26264 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 26265 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26266 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26267 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26268 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26269 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26270 | // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 6553 |
| 26271 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 26272 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26273 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26274 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26275 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26276 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26277 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26278 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26279 | // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6561 |
| 26280 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 26281 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26282 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26284 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26285 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26286 | // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 6567 |
| 26287 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26288 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26289 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26290 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26291 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26292 | // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6572 |
| 26293 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26294 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26295 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26296 | // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend16 0, 0)) - 6575 |
| 26297 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 26298 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26299 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26300 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26301 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26302 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26303 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26304 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26305 | // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6583 |
| 26306 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 26307 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26308 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26309 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26310 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26311 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26312 | // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend128 0, 0)) - 6589 |
| 26313 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26314 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26315 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26316 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26317 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26318 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26319 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26320 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26321 | // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6597 |
| 26322 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26323 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26324 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26325 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26326 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26327 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26328 | // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 6603 |
| 26329 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 26330 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26331 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26332 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26333 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26334 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26335 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26336 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26337 | // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6611 |
| 26338 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 26339 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26340 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26341 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26342 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26343 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26344 | // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend32 0, 0)) - 6617 |
| 26345 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26346 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26347 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26348 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26349 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26350 | // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6622 |
| 26351 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26352 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26353 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26354 | // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ro_Xextend64 0, 0)) - 6625 |
| 26355 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26356 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26357 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26358 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26359 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26360 | // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 6630 |
| 26361 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26362 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26363 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26364 | // (STR_PXI PPRorPNRAny:$Pt, GPR64sp:$Rn, 0) - 6633 |
| 26365 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::PPRorPNRRegClassID}, |
| 26366 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26367 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26368 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26369 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26370 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26371 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26372 | // (STR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 6640 |
| 26373 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MPRRegClassID}, |
| 26374 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| 26375 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26376 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26377 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26378 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26379 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26380 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26381 | // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 6648 |
| 26382 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26383 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26384 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26385 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26386 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26387 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26388 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26389 | // (STTNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6655 |
| 26390 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26391 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26392 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26393 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26394 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26395 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 26396 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26397 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26398 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 26399 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26400 | // (STTNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6665 |
| 26401 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26402 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26403 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26404 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26405 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26406 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 26407 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26408 | // (STTPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6672 |
| 26409 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26410 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26411 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26412 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26413 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26414 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 26415 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26416 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26417 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 26418 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26419 | // (STTPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6682 |
| 26420 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26421 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26422 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26423 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26424 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26425 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureLSUI}, |
| 26426 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26427 | // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 6689 |
| 26428 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26429 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26430 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26431 | // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 6692 |
| 26432 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26433 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26434 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26435 | // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 6695 |
| 26436 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26437 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26438 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26439 | // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 6698 |
| 26440 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26441 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26442 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26443 | // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6701 |
| 26444 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26445 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26446 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26447 | // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6704 |
| 26448 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR8RegClassID}, |
| 26449 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26450 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26451 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26452 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26453 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26454 | // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6710 |
| 26455 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR64RegClassID}, |
| 26456 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26457 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26458 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26459 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26460 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26461 | // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6716 |
| 26462 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26463 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26464 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26465 | // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6719 |
| 26466 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR16RegClassID}, |
| 26467 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26468 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26469 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26470 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26471 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26472 | // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6725 |
| 26473 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26474 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26475 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26476 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26477 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26478 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26479 | // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6731 |
| 26480 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR32RegClassID}, |
| 26481 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26482 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26483 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26484 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureFPARMv8}, |
| 26485 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26486 | // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6737 |
| 26487 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26488 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26489 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26490 | // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 6740 |
| 26491 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26492 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26493 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26494 | // (STZ2Gi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6743 |
| 26495 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26496 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26497 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26498 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26499 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 26500 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26501 | // (STZGi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6749 |
| 26502 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26503 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26504 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26505 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26506 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureMTE}, |
| 26507 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26508 | // (SUBPT_shift GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0) - 6755 |
| 26509 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26510 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26511 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26512 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26513 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26514 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCPA}, |
| 26515 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26516 | // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 6762 |
| 26517 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26518 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26519 | // (SUBSWrs WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 6764 |
| 26520 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26521 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26522 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26523 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26524 | // (SUBSWrs WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, arith_shift32:$sh)) - 6768 |
| 26525 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26526 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26527 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26528 | // (SUBSWrs GPR32:$dst, WZR, (arith_shifted_reg32 GPR32:$src, 0)) - 6771 |
| 26529 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26530 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26531 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26532 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26533 | // (SUBSWrs GPR32:$dst, WZR, (arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)) - 6775 |
| 26534 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26535 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26536 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26537 | // (SUBSWrs GPR32:$dst, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 6778 |
| 26538 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26539 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26540 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26541 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26542 | // (SUBSWrx WZR, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 6782 |
| 26543 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26544 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 26545 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26546 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 26547 | // (SUBSWrx WZR, GPR32sp:$src1, (arith_extended_reg32_i32 GPR32:$src2, arith_extend:$sh)) - 6786 |
| 26548 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26549 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26550 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26551 | // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 6789 |
| 26552 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26553 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 26554 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26555 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 26556 | // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 6793 |
| 26557 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26558 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26559 | // (SUBSXrs XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 6795 |
| 26560 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26561 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26562 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26563 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26564 | // (SUBSXrs XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, arith_shift64:$sh)) - 6799 |
| 26565 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26566 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26567 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26568 | // (SUBSXrs GPR64:$dst, XZR, (arith_shifted_reg64 GPR64:$src, 0)) - 6802 |
| 26569 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26570 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26571 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26572 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26573 | // (SUBSXrs GPR64:$dst, XZR, (arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)) - 6806 |
| 26574 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26575 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26576 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26577 | // (SUBSXrs GPR64:$dst, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 6809 |
| 26578 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26579 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26580 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26581 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26582 | // (SUBSXrx XZR, GPR64sp:$src1, (arith_extended_reg32_i64 GPR32:$src2, arith_extend:$sh)) - 6813 |
| 26583 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26584 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26585 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26586 | // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 6816 |
| 26587 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26588 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 26589 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26590 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 26591 | // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 6820 |
| 26592 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26593 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26594 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26595 | // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6823 |
| 26596 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26597 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 26598 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26599 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 26600 | // (SUBWrs GPR32:$dst, WZR, (arith_shifted_reg32 GPR32:$src, 0)) - 6827 |
| 26601 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26602 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26603 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26604 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26605 | // (SUBWrs GPR32:$dst, WZR, (arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)) - 6831 |
| 26606 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26607 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::WZR}, |
| 26608 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26609 | // (SUBWrs GPR32:$dst, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)) - 6834 |
| 26610 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26611 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26612 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26613 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26614 | // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 6838 |
| 26615 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 26616 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26617 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26618 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 26619 | // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, (arith_extended_reg32_i32 GPR32:$src2, 16)) - 6842 |
| 26620 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32spRegClassID}, |
| 26621 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32sponlyRegClassID}, |
| 26622 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26623 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(16)}, |
| 26624 | // (SUBXrs GPR64:$dst, XZR, (arith_shifted_reg64 GPR64:$src, 0)) - 6846 |
| 26625 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26626 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26627 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26628 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26629 | // (SUBXrs GPR64:$dst, XZR, (arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)) - 6850 |
| 26630 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26631 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26632 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26633 | // (SUBXrs GPR64:$dst, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)) - 6853 |
| 26634 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26635 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26636 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26637 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26638 | // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 6857 |
| 26639 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 26640 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26641 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26642 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 26643 | // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6861 |
| 26644 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64spRegClassID}, |
| 26645 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64sponlyRegClassID}, |
| 26646 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26647 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(24)}, |
| 26648 | // (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 6865 |
| 26649 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26650 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26651 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26652 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26653 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26654 | // (SYSxt 6, 7, 0, 0, GPR64:$Xt) - 6870 |
| 26655 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(6)}, |
| 26656 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 26657 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26658 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26659 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26660 | // (SYSxt 1, 7, 2, 4, XZR) - 6875 |
| 26661 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26662 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 26663 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 26664 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(4)}, |
| 26665 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26666 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26667 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBRBE}, |
| 26668 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26669 | // (SYSxt 1, 7, 2, 5, XZR) - 6883 |
| 26670 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26671 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 26672 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 26673 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(5)}, |
| 26674 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26675 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26676 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureBRBE}, |
| 26677 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26678 | // (SYSxt 3, 7, 2, 7, GPR64:$Rt) - 6891 |
| 26679 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(3)}, |
| 26680 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 26681 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(2)}, |
| 26682 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 26683 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26684 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26685 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureITE}, |
| 26686 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26687 | // (SYSxt timm32_0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, timm32_0_7:$op2, XZR) - 6899 |
| 26688 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26689 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26690 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26691 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26692 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26693 | // (TCHANGEBri GPR64:$Xd, imm0_127:$imm, 0) - 6904 |
| 26694 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26695 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26696 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26697 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26698 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureS1POE2}, |
| 26699 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26700 | // (TCHANGEBrr GPR64:$Xd, GPR64:$Xn, 0) - 6910 |
| 26701 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26702 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26703 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26704 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26705 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureS1POE2}, |
| 26706 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26707 | // (TCHANGEFri GPR64:$Xd, imm0_127:$imm, 0) - 6916 |
| 26708 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26709 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26710 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26711 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26712 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureS1POE2}, |
| 26713 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26714 | // (TCHANGEFrr GPR64:$Xd, GPR64:$Xn, 0) - 6922 |
| 26715 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26716 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26717 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26718 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26719 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureS1POE2}, |
| 26720 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26721 | // (TENTER imm0_127:$imm, 0) - 6928 |
| 26722 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26723 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26724 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26725 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureTEV}, |
| 26726 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26727 | // (TEXIT 0) - 6933 |
| 26728 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26729 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26730 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureTEV}, |
| 26731 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26732 | // (TFLTNZ imm0_3:$reason, GPR64as32:$Rt, imm0_31:$imm) - 6937 |
| 26733 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26734 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26735 | {.Kind: AliasPatternCond::K_Custom, .Value: 8}, |
| 26736 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26737 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCFLT}, |
| 26738 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26739 | // (TFLTZ imm0_3:$reason, GPR64as32:$Rt, imm0_31:$imm) - 6943 |
| 26740 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26741 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26742 | {.Kind: AliasPatternCond::K_Custom, .Value: 8}, |
| 26743 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26744 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureCFLT}, |
| 26745 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26746 | // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 6949 |
| 26747 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26748 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26749 | {.Kind: AliasPatternCond::K_Custom, .Value: 8}, |
| 26750 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26751 | // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 6953 |
| 26752 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26753 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26754 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26755 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 26756 | // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 6957 |
| 26757 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26758 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26759 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26760 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 26761 | // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 6961 |
| 26762 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26763 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26764 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26765 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(63)}, |
| 26766 | // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 6965 |
| 26767 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26768 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26769 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26770 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(7)}, |
| 26771 | // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 6969 |
| 26772 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26773 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26774 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26775 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(15)}, |
| 26776 | // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 6973 |
| 26777 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26778 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26779 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(0)}, |
| 26780 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26781 | // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 6977 |
| 26782 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26783 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26784 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26785 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26786 | // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 6981 |
| 26787 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26788 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26789 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26790 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 26791 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26792 | // (UMOVvi32_idx0 GPR32:$dst, V128:$src, VectorIndex0:$idx) - 6986 |
| 26793 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26794 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26795 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26796 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 26797 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26798 | // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 6991 |
| 26799 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26800 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26801 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26802 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 26803 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26804 | // (UMOVvi64_idx0 GPR64:$dst, V128:$src, VectorIndex0:$idx) - 6996 |
| 26805 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26806 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::FPR128RegClassID}, |
| 26807 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26808 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureNEON}, |
| 26809 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26810 | // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 7001 |
| 26811 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26812 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26813 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26814 | {.Kind: AliasPatternCond::K_Reg, .Value: AArch64::XZR}, |
| 26815 | // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7005 |
| 26816 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26817 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26818 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26819 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26820 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26821 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26822 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26823 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26824 | // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7013 |
| 26825 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26826 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26827 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26828 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26829 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26830 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26831 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26832 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26833 | // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7021 |
| 26834 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26835 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26836 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26837 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26838 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26839 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26840 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26841 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26842 | // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7029 |
| 26843 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26844 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26845 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26846 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26847 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26848 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26849 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26850 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26851 | // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7037 |
| 26852 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26853 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26854 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26855 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26856 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26857 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26858 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26859 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26860 | // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7045 |
| 26861 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26862 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26863 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26864 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26865 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26866 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26867 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26868 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26869 | // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7053 |
| 26870 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26871 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26872 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26873 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26874 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26875 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26876 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26877 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26878 | // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7061 |
| 26879 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26880 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26881 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26882 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26883 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26884 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26885 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26886 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26887 | // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7069 |
| 26888 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26889 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26890 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26891 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26892 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26893 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26894 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26895 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26896 | // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 7077 |
| 26897 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26898 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26899 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26900 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26901 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26902 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26903 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26904 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26905 | // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7085 |
| 26906 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26907 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26908 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26909 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26910 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26911 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26912 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26913 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26914 | // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7093 |
| 26915 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26916 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26917 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26918 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26919 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26920 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26921 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26922 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26923 | // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7101 |
| 26924 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26925 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26926 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26927 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26928 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26929 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26930 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26931 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26932 | // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7109 |
| 26933 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26934 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26935 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26936 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26937 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26938 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26939 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26940 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26941 | // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7117 |
| 26942 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26943 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26944 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26945 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26946 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26947 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26948 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26949 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26950 | // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 7125 |
| 26951 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26952 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26953 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26954 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26955 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26956 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26957 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26958 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26959 | // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7133 |
| 26960 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26961 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26962 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26963 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26964 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26965 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26966 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26967 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26968 | // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7141 |
| 26969 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 26970 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26971 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26972 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26973 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26974 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26975 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26976 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26977 | // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7149 |
| 26978 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26979 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26980 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26981 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26982 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26983 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26984 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26985 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26986 | // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7157 |
| 26987 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 26988 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26989 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26990 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 26991 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 26992 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 26993 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 26994 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 26995 | // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7165 |
| 26996 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 26997 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 26998 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 26999 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27000 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27001 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27002 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27003 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27004 | // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 7173 |
| 27005 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27006 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27007 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27008 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27009 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27010 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27011 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27012 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27013 | // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7181 |
| 27014 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27015 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27016 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27017 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27018 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27019 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27020 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27021 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27022 | // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7189 |
| 27023 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27024 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27025 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27026 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27027 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27028 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27029 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27030 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27031 | // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7197 |
| 27032 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27033 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27034 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27035 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27036 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27037 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27038 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27039 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27040 | // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7205 |
| 27041 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27042 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27043 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27044 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27045 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27046 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27047 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27048 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27049 | // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7213 |
| 27050 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27051 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27052 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27053 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27054 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27055 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27056 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27057 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27058 | // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7221 |
| 27059 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27060 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27061 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27062 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27063 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27064 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27065 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27066 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27067 | // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7229 |
| 27068 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27069 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27070 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27071 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27072 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27073 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27074 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27075 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27076 | // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7237 |
| 27077 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27078 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27079 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27080 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27081 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27082 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27083 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27084 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27085 | // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7245 |
| 27086 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27087 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27088 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27089 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27090 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27091 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27092 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27093 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27094 | // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 7253 |
| 27095 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27096 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27097 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27098 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27099 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27100 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27101 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27102 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27103 | // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7261 |
| 27104 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27105 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27106 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27107 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27108 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27109 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27110 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27111 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27112 | // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7269 |
| 27113 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27114 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27115 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27116 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27117 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27118 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27119 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27120 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27121 | // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7277 |
| 27122 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27123 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27124 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27125 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27126 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27127 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27128 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27129 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27130 | // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7285 |
| 27131 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27132 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27133 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27134 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27135 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27136 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27137 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27138 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27139 | // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7293 |
| 27140 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27141 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27142 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27143 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27144 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27145 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27146 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27147 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27148 | // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 7301 |
| 27149 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27150 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27151 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27152 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27153 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27154 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27155 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27156 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27157 | // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7309 |
| 27158 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27159 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27160 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27161 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27162 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27163 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27164 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27165 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27166 | // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7317 |
| 27167 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR32RegClassID}, |
| 27168 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27169 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27170 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27171 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27172 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27173 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27174 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27175 | // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7325 |
| 27176 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27177 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27178 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27179 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27180 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27181 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27182 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27183 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27184 | // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7333 |
| 27185 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::GPR64RegClassID}, |
| 27186 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27187 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27188 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27189 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27190 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27191 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27192 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27193 | // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7341 |
| 27194 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27195 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27196 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(31)}, |
| 27197 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27198 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27199 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27200 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27201 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27202 | // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 7349 |
| 27203 | {.Kind: AliasPatternCond::K_RegClass, .Value: AArch64::ZPRRegClassID}, |
| 27204 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27205 | {.Kind: AliasPatternCond::K_Ignore, .Value: 0}, |
| 27206 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(1)}, |
| 27207 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27208 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSVE}, |
| 27209 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27210 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27211 | // (XPACLRI) - 7357 |
| 27212 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27213 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeaturePAuth}, |
| 27214 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27215 | // (ZERO_M { 1, 1, 1, 1, 1, 1, 1, 1 }) - 7360 |
| 27216 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(255)}, |
| 27217 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27218 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27219 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27220 | // (ZERO_M { 0, 1, 0, 1, 0, 1, 0, 1 }) - 7364 |
| 27221 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(85)}, |
| 27222 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27223 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27224 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27225 | // (ZERO_M { 1, 0, 1, 0, 1, 0, 1, 0 }) - 7368 |
| 27226 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(170)}, |
| 27227 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27228 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27229 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27230 | // (ZERO_M { 0, 0, 0, 1, 0, 0, 0, 1 }) - 7372 |
| 27231 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(17)}, |
| 27232 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27233 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27234 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27235 | // (ZERO_M { 0, 0, 1, 0, 0, 0, 1, 0 }) - 7376 |
| 27236 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(34)}, |
| 27237 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27238 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27239 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27240 | // (ZERO_M { 0, 1, 0, 0, 0, 1, 0, 0 }) - 7380 |
| 27241 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(68)}, |
| 27242 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27243 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27244 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27245 | // (ZERO_M { 1, 0, 0, 0, 1, 0, 0, 0 }) - 7384 |
| 27246 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(136)}, |
| 27247 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27248 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27249 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27250 | // (ZERO_M { 0, 0, 1, 1, 0, 0, 1, 1 }) - 7388 |
| 27251 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(51)}, |
| 27252 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27253 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27254 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27255 | // (ZERO_M { 1, 0, 0, 1, 1, 0, 0, 1 }) - 7392 |
| 27256 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(153)}, |
| 27257 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27258 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27259 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27260 | // (ZERO_M { 0, 1, 1, 0, 0, 1, 1, 0 }) - 7396 |
| 27261 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(102)}, |
| 27262 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27263 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27264 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27265 | // (ZERO_M { 1, 1, 0, 0, 1, 1, 0, 0 }) - 7400 |
| 27266 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(204)}, |
| 27267 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27268 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27269 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27270 | // (ZERO_M { 0, 1, 1, 1, 0, 1, 1, 1 }) - 7404 |
| 27271 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(119)}, |
| 27272 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27273 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27274 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27275 | // (ZERO_M { 1, 0, 1, 1, 1, 0, 1, 1 }) - 7408 |
| 27276 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(187)}, |
| 27277 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27278 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27279 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27280 | // (ZERO_M { 1, 1, 0, 1, 1, 1, 0, 1 }) - 7412 |
| 27281 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(221)}, |
| 27282 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27283 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27284 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27285 | // (ZERO_M { 1, 1, 1, 0, 1, 1, 1, 0 }) - 7416 |
| 27286 | {.Kind: AliasPatternCond::K_Imm, .Value: uint32_t(238)}, |
| 27287 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureAll}, |
| 27288 | {.Kind: AliasPatternCond::K_OrFeature, .Value: AArch64::FeatureSME}, |
| 27289 | {.Kind: AliasPatternCond::K_EndOrFeatures, .Value: 0}, |
| 27290 | }; |
| 27291 | |
| 27292 | static const char AsmStrings[] = |
| 27293 | /* 0 */ "addpt $\x01, $\x02, $\x03\0" |
| 27294 | /* 17 */ "cmn $\x02, $\xFF\x03\x01\0" |
| 27295 | /* 30 */ "cmn $\x02, $\x03\0" |
| 27296 | /* 41 */ "cmn $\x02, $\x03$\xFF\x04\x02\0" |
| 27297 | /* 56 */ "adds $\x01, $\x02, $\x03\0" |
| 27298 | /* 72 */ "cmn $\x02, $\x03$\xFF\x04\x03\0" |
| 27299 | /* 87 */ "mov $\x01, $\x02\0" |
| 27300 | /* 98 */ "add $\x01, $\x02, $\x03\0" |
| 27301 | /* 113 */ "tst $\x02, $\xFF\x03\x04\0" |
| 27302 | /* 126 */ "tst $\x02, $\x03\0" |
| 27303 | /* 137 */ "tst $\x02, $\x03$\xFF\x04\x02\0" |
| 27304 | /* 152 */ "ands $\x01, $\x02, $\x03\0" |
| 27305 | /* 168 */ "tst $\x02, $\xFF\x03\x05\0" |
| 27306 | /* 181 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 27307 | /* 205 */ "and $\x01, $\x02, $\x03\0" |
| 27308 | /* 220 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 27309 | /* 243 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| 27310 | /* 264 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| 27311 | /* 285 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| 27312 | /* 306 */ "autia1716\0" |
| 27313 | /* 316 */ "autiasp\0" |
| 27314 | /* 324 */ "autiaz\0" |
| 27315 | /* 331 */ "autib1716\0" |
| 27316 | /* 341 */ "autibsp\0" |
| 27317 | /* 349 */ "autibz\0" |
| 27318 | /* 356 */ "bics $\x01, $\x02, $\x03\0" |
| 27319 | /* 372 */ "bic $\x01, $\x02, $\x03\0" |
| 27320 | /* 387 */ "chkfeat x16\0" |
| 27321 | /* 399 */ "clrex\0" |
| 27322 | /* 405 */ "cntb $\x01\0" |
| 27323 | /* 413 */ "cntb $\x01, $\xFF\x02\x0E\0" |
| 27324 | /* 427 */ "cntd $\x01\0" |
| 27325 | /* 435 */ "cntd $\x01, $\xFF\x02\x0E\0" |
| 27326 | /* 449 */ "cnth $\x01\0" |
| 27327 | /* 457 */ "cnth $\x01, $\xFF\x02\x0E\0" |
| 27328 | /* 471 */ "cntw $\x01\0" |
| 27329 | /* 479 */ "cntw $\x01, $\xFF\x02\x0E\0" |
| 27330 | /* 493 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0" |
| 27331 | /* 516 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0" |
| 27332 | /* 539 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0" |
| 27333 | /* 562 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0" |
| 27334 | /* 585 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0" |
| 27335 | /* 606 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0" |
| 27336 | /* 627 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0" |
| 27337 | /* 648 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0" |
| 27338 | /* 669 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0" |
| 27339 | /* 692 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0" |
| 27340 | /* 715 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0" |
| 27341 | /* 738 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0" |
| 27342 | /* 761 */ "cset $\x01, $\xFF\x04\x14\0" |
| 27343 | /* 775 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0" |
| 27344 | /* 793 */ "csetm $\x01, $\xFF\x04\x14\0" |
| 27345 | /* 808 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0" |
| 27346 | /* 826 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0" |
| 27347 | /* 844 */ "dcps1\0" |
| 27348 | /* 850 */ "dcps2\0" |
| 27349 | /* 856 */ "dcps3\0" |
| 27350 | /* 862 */ "decb $\x01\0" |
| 27351 | /* 870 */ "decb $\x01, $\xFF\x03\x0E\0" |
| 27352 | /* 884 */ "decd $\x01\0" |
| 27353 | /* 892 */ "decd $\x01, $\xFF\x03\x0E\0" |
| 27354 | /* 906 */ "decd $\xFF\x01\x10\0" |
| 27355 | /* 916 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 27356 | /* 932 */ "dech $\x01\0" |
| 27357 | /* 940 */ "dech $\x01, $\xFF\x03\x0E\0" |
| 27358 | /* 954 */ "dech $\xFF\x01\x09\0" |
| 27359 | /* 964 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 27360 | /* 980 */ "decw $\x01\0" |
| 27361 | /* 988 */ "decw $\x01, $\xFF\x03\x0E\0" |
| 27362 | /* 1002 */ "decw $\xFF\x01\x0B\0" |
| 27363 | /* 1012 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 27364 | /* 1028 */ "ssbb\0" |
| 27365 | /* 1033 */ "pssbb\0" |
| 27366 | /* 1039 */ "dfb\0" |
| 27367 | /* 1043 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0" |
| 27368 | /* 1058 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0" |
| 27369 | /* 1073 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0" |
| 27370 | /* 1088 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0" |
| 27371 | /* 1104 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0" |
| 27372 | /* 1120 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0" |
| 27373 | /* 1136 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0" |
| 27374 | /* 1151 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0" |
| 27375 | /* 1166 */ "fmov $\xFF\x01\x10, #0.0\0" |
| 27376 | /* 1182 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0" |
| 27377 | /* 1197 */ "fmov $\xFF\x01\x09, #0.0\0" |
| 27378 | /* 1213 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0" |
| 27379 | /* 1228 */ "fmov $\xFF\x01\x0B, #0.0\0" |
| 27380 | /* 1244 */ "mov $\xFF\x01\x06, $\x02\0" |
| 27381 | /* 1257 */ "mov $\xFF\x01\x10, $\x02\0" |
| 27382 | /* 1270 */ "mov $\xFF\x01\x09, $\x02\0" |
| 27383 | /* 1283 */ "mov $\xFF\x01\x0B, $\x02\0" |
| 27384 | /* 1296 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0" |
| 27385 | /* 1311 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0" |
| 27386 | /* 1330 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0" |
| 27387 | /* 1345 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0" |
| 27388 | /* 1364 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0" |
| 27389 | /* 1379 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0" |
| 27390 | /* 1398 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0" |
| 27391 | /* 1413 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0" |
| 27392 | /* 1432 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0" |
| 27393 | /* 1447 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0" |
| 27394 | /* 1466 */ "eon $\x01, $\x02, $\x03\0" |
| 27395 | /* 1481 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 27396 | /* 1505 */ "eor $\x01, $\x02, $\x03\0" |
| 27397 | /* 1520 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| 27398 | /* 1543 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| 27399 | /* 1564 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| 27400 | /* 1585 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| 27401 | /* 1606 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 27402 | /* 1639 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 27403 | /* 1672 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 27404 | /* 1705 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 27405 | /* 1738 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| 27406 | /* 1771 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 27407 | /* 1804 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 27408 | /* 1837 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 27409 | /* 1870 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 27410 | /* 1903 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| 27411 | /* 1936 */ "ror $\x01, $\x02, $\x04\0" |
| 27412 | /* 1951 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| 27413 | /* 1975 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| 27414 | /* 1999 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| 27415 | /* 2023 */ "fmov $\xFF\x01\x10, $\xFF\x02\x22\0" |
| 27416 | /* 2039 */ "fmov $\xFF\x01\x09, $\xFF\x02\x22\0" |
| 27417 | /* 2055 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x22\0" |
| 27418 | /* 2071 */ "gcspopm\0" |
| 27419 | /* 2079 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27420 | /* 2105 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27421 | /* 2131 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27422 | /* 2157 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27423 | /* 2183 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27424 | /* 2209 */ "ld1q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27425 | /* 2235 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27426 | /* 2262 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27427 | /* 2289 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27428 | /* 2316 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27429 | /* 2343 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27430 | /* 2370 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27431 | /* 2396 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27432 | /* 2422 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27433 | /* 2450 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27434 | /* 2478 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27435 | /* 2506 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27436 | /* 2534 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27437 | /* 2562 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27438 | /* 2591 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27439 | /* 2620 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27440 | /* 2649 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27441 | /* 2678 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27442 | /* 2707 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27443 | /* 2735 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27444 | /* 2763 */ "yield\0" |
| 27445 | /* 2769 */ "wfe\0" |
| 27446 | /* 2773 */ "wfi\0" |
| 27447 | /* 2777 */ "sev\0" |
| 27448 | /* 2781 */ "sevl\0" |
| 27449 | /* 2786 */ "dgh\0" |
| 27450 | /* 2790 */ "esb\0" |
| 27451 | /* 2794 */ "csdb\0" |
| 27452 | /* 2799 */ "stshh keep\0" |
| 27453 | /* 2810 */ "stshh strm\0" |
| 27454 | /* 2821 */ "shuh\0" |
| 27455 | /* 2826 */ "shuh ph\0" |
| 27456 | /* 2834 */ "stcph\0" |
| 27457 | /* 2840 */ "srls\0" |
| 27458 | /* 2845 */ "srls stshstrm\0" |
| 27459 | /* 2859 */ "slbnd\0" |
| 27460 | /* 2865 */ "bti r\0" |
| 27461 | /* 2871 */ "bti\0" |
| 27462 | /* 2875 */ "bti c\0" |
| 27463 | /* 2881 */ "bti j\0" |
| 27464 | /* 2887 */ "bti jc\0" |
| 27465 | /* 2894 */ "psb csync\0" |
| 27466 | /* 2904 */ "tsb csync\0" |
| 27467 | /* 2914 */ "gcsb dsync\0" |
| 27468 | /* 2925 */ "clrbhb\0" |
| 27469 | /* 2932 */ "incb $\x01\0" |
| 27470 | /* 2940 */ "incb $\x01, $\xFF\x03\x0E\0" |
| 27471 | /* 2954 */ "incd $\x01\0" |
| 27472 | /* 2962 */ "incd $\x01, $\xFF\x03\x0E\0" |
| 27473 | /* 2976 */ "incd $\xFF\x01\x10\0" |
| 27474 | /* 2986 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 27475 | /* 3002 */ "inch $\x01\0" |
| 27476 | /* 3010 */ "inch $\x01, $\xFF\x03\x0E\0" |
| 27477 | /* 3024 */ "inch $\xFF\x01\x09\0" |
| 27478 | /* 3034 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 27479 | /* 3050 */ "incw $\x01\0" |
| 27480 | /* 3058 */ "incw $\x01, $\xFF\x03\x0E\0" |
| 27481 | /* 3072 */ "incw $\xFF\x01\x0B\0" |
| 27482 | /* 3082 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 27483 | /* 3098 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0" |
| 27484 | /* 3131 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0" |
| 27485 | /* 3164 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0" |
| 27486 | /* 3197 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0" |
| 27487 | /* 3230 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0" |
| 27488 | /* 3263 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0" |
| 27489 | /* 3296 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0" |
| 27490 | /* 3329 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0" |
| 27491 | /* 3362 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0" |
| 27492 | /* 3395 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0" |
| 27493 | /* 3428 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04\0" |
| 27494 | /* 3447 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19\0" |
| 27495 | /* 3474 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04\0" |
| 27496 | /* 3493 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19\0" |
| 27497 | /* 3520 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04\0" |
| 27498 | /* 3539 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19\0" |
| 27499 | /* 3566 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04\0" |
| 27500 | /* 3585 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19\0" |
| 27501 | /* 3612 */ "irg $\x01, $\x02\0" |
| 27502 | /* 3623 */ "isb\0" |
| 27503 | /* 3627 */ "ld1b $\xFF\x01\x26, $\xFF\x02\x27/z, [$\x03]\0" |
| 27504 | /* 3651 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x27/z, [$\x03]\0" |
| 27505 | /* 3675 */ "ld1b $\xFF\x01\x26, $\xFF\x02\x27/z, [$\x03]\0" |
| 27506 | /* 3699 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27507 | /* 3723 */ "ld1b $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27508 | /* 3747 */ "ld1b $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27509 | /* 3771 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27510 | /* 3795 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x27/z, [$\x03]\0" |
| 27511 | /* 3819 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x27/z, [$\x03]\0" |
| 27512 | /* 3843 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27513 | /* 3867 */ "ld1d $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 27514 | /* 3891 */ "ld1 $\xFF\x02\x2A, [$\x01], #64\0" |
| 27515 | /* 3911 */ "ld1 $\xFF\x02\x2B, [$\x01], #32\0" |
| 27516 | /* 3931 */ "ld1 $\xFF\x02\x2C, [$\x01], #64\0" |
| 27517 | /* 3951 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0" |
| 27518 | /* 3971 */ "ld1 $\xFF\x02\x2E, [$\x01], #32\0" |
| 27519 | /* 3991 */ "ld1 $\xFF\x02\x2F, [$\x01], #64\0" |
| 27520 | /* 4011 */ "ld1 $\xFF\x02\x30, [$\x01], #32\0" |
| 27521 | /* 4031 */ "ld1 $\xFF\x02\x31, [$\x01], #64\0" |
| 27522 | /* 4051 */ "ld1h $\xFF\x01\x29, $\xFF\x02\x27/z, [$\x03]\0" |
| 27523 | /* 4075 */ "ld1h $\xFF\x01\x32, $\xFF\x02\x27/z, [$\x03]\0" |
| 27524 | /* 4099 */ "ld1h $\xFF\x01\x29, $\xFF\x02\x27/z, [$\x03]\0" |
| 27525 | /* 4123 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27526 | /* 4147 */ "ld1h $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27527 | /* 4171 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27528 | /* 4195 */ "ld1 $\xFF\x02\x2A, [$\x01], #16\0" |
| 27529 | /* 4215 */ "ld1 $\xFF\x02\x2B, [$\x01], #8\0" |
| 27530 | /* 4234 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0" |
| 27531 | /* 4254 */ "ld1 $\xFF\x02\x2D, [$\x01], #8\0" |
| 27532 | /* 4273 */ "ld1 $\xFF\x02\x2E, [$\x01], #8\0" |
| 27533 | /* 4292 */ "ld1 $\xFF\x02\x2F, [$\x01], #16\0" |
| 27534 | /* 4312 */ "ld1 $\xFF\x02\x30, [$\x01], #8\0" |
| 27535 | /* 4331 */ "ld1 $\xFF\x02\x31, [$\x01], #16\0" |
| 27536 | /* 4351 */ "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27537 | /* 4376 */ "ld1rb $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27538 | /* 4401 */ "ld1rb $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27539 | /* 4426 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27540 | /* 4451 */ "ld1rd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27541 | /* 4476 */ "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27542 | /* 4501 */ "ld1rh $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27543 | /* 4526 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27544 | /* 4551 */ "ld1rob $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27545 | /* 4577 */ "ld1rod $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27546 | /* 4603 */ "ld1roh $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27547 | /* 4629 */ "ld1row $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27548 | /* 4655 */ "ld1rqb $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27549 | /* 4681 */ "ld1rqd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27550 | /* 4707 */ "ld1rqh $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27551 | /* 4733 */ "ld1rqw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27552 | /* 4759 */ "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27553 | /* 4785 */ "ld1rsb $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27554 | /* 4811 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27555 | /* 4837 */ "ld1rsh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27556 | /* 4863 */ "ld1rsh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27557 | /* 4889 */ "ld1rsw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27558 | /* 4915 */ "ld1rw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27559 | /* 4940 */ "ld1rw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27560 | /* 4965 */ "ld1r $\xFF\x02\x2A, [$\x01], #1\0" |
| 27561 | /* 4985 */ "ld1r $\xFF\x02\x2B, [$\x01], #8\0" |
| 27562 | /* 5005 */ "ld1r $\xFF\x02\x2C, [$\x01], #8\0" |
| 27563 | /* 5025 */ "ld1r $\xFF\x02\x2D, [$\x01], #4\0" |
| 27564 | /* 5045 */ "ld1r $\xFF\x02\x2E, [$\x01], #2\0" |
| 27565 | /* 5065 */ "ld1r $\xFF\x02\x2F, [$\x01], #4\0" |
| 27566 | /* 5085 */ "ld1r $\xFF\x02\x30, [$\x01], #1\0" |
| 27567 | /* 5105 */ "ld1r $\xFF\x02\x31, [$\x01], #2\0" |
| 27568 | /* 5125 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27569 | /* 5150 */ "ld1sb $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27570 | /* 5175 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27571 | /* 5200 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27572 | /* 5225 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27573 | /* 5250 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27574 | /* 5275 */ "ld1 $\xFF\x02\x2A, [$\x01], #48\0" |
| 27575 | /* 5295 */ "ld1 $\xFF\x02\x2B, [$\x01], #24\0" |
| 27576 | /* 5315 */ "ld1 $\xFF\x02\x2C, [$\x01], #48\0" |
| 27577 | /* 5335 */ "ld1 $\xFF\x02\x2D, [$\x01], #24\0" |
| 27578 | /* 5355 */ "ld1 $\xFF\x02\x2E, [$\x01], #24\0" |
| 27579 | /* 5375 */ "ld1 $\xFF\x02\x2F, [$\x01], #48\0" |
| 27580 | /* 5395 */ "ld1 $\xFF\x02\x30, [$\x01], #24\0" |
| 27581 | /* 5415 */ "ld1 $\xFF\x02\x31, [$\x01], #48\0" |
| 27582 | /* 5435 */ "ld1 $\xFF\x02\x2A, [$\x01], #32\0" |
| 27583 | /* 5455 */ "ld1 $\xFF\x02\x2B, [$\x01], #16\0" |
| 27584 | /* 5475 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0" |
| 27585 | /* 5495 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0" |
| 27586 | /* 5515 */ "ld1 $\xFF\x02\x2E, [$\x01], #16\0" |
| 27587 | /* 5535 */ "ld1 $\xFF\x02\x2F, [$\x01], #32\0" |
| 27588 | /* 5555 */ "ld1 $\xFF\x02\x30, [$\x01], #16\0" |
| 27589 | /* 5575 */ "ld1 $\xFF\x02\x31, [$\x01], #32\0" |
| 27590 | /* 5595 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x27/z, [$\x03]\0" |
| 27591 | /* 5619 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x27/z, [$\x03]\0" |
| 27592 | /* 5643 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27593 | /* 5667 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27594 | /* 5691 */ "ld1w $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 27595 | /* 5715 */ "ld1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27596 | /* 5751 */ "ld1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27597 | /* 5787 */ "ld1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27598 | /* 5823 */ "ld1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27599 | /* 5859 */ "ld1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27600 | /* 5895 */ "ld1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27601 | /* 5931 */ "ld1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27602 | /* 5967 */ "ld1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27603 | /* 6003 */ "ld1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27604 | /* 6039 */ "ld1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| 27605 | /* 6075 */ "ld1 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #2\0" |
| 27606 | /* 6098 */ "ld1 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #4\0" |
| 27607 | /* 6121 */ "ld1 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #8\0" |
| 27608 | /* 6144 */ "ld1 $\xFF\x02\x28$\xFF\x04\x19, [$\x01], #1\0" |
| 27609 | /* 6167 */ "ld2b $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27610 | /* 6191 */ "ld2d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27611 | /* 6215 */ "ld2h $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27612 | /* 6239 */ "ld2q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 27613 | /* 6263 */ "ld2r $\xFF\x02\x2A, [$\x01], #2\0" |
| 27614 | /* 6283 */ "ld2r $\xFF\x02\x2B, [$\x01], #16\0" |
| 27615 | /* 6304 */ "ld2r $\xFF\x02\x2C, [$\x01], #16\0" |
| 27616 | /* 6325 */ "ld2r $\xFF\x02\x2D, [$\x01], #8\0" |
| 27617 | /* 6345 */ "ld2r $\xFF\x02\x2E, [$\x01], #4\0" |
| 27618 | /* 6365 */ "ld2r $\xFF\x02\x2F, [$\x01], #8\0" |
| 27619 | /* 6385 */ "ld2r $\xFF\x02\x30, [$\x01], #2\0" |
| 27620 | /* 6405 */ "ld2r $\xFF\x02\x31, [$\x01], #4\0" |
| 27621 | /* 6425 */ "ld2 $\xFF\x02\x2A, [$\x01], #32\0" |
| 27622 | /* 6445 */ "ld2 $\xFF\x02\x2C, [$\x01], #32\0" |
| 27623 | /* 6465 */ "ld2 $\xFF\x02\x2D, [$\x01], #16\0" |
| 27624 | /* 6485 */ "ld2 $\xFF\x02\x2E, [$\x01], #16\0" |
| 27625 | /* 6505 */ "ld2 $\xFF\x02\x2F, [$\x01], #32\0" |
| 27626 | /* 6525 */ "ld2 $\xFF\x02\x30, [$\x01], #16\0" |
| 27627 | /* 6545 */ "ld2 $\xFF\x02\x31, [$\x01], #32\0" |
| 27628 | /* 6565 */ "ld2w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27629 | /* 6589 */ "ld2 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #4\0" |
| 27630 | /* 6612 */ "ld2 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #8\0" |
| 27631 | /* 6635 */ "ld2 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #16\0" |
| 27632 | /* 6659 */ "ld2 $\xFF\x02\x28$\xFF\x04\x19, [$\x01], #2\0" |
| 27633 | /* 6682 */ "ld3b $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27634 | /* 6706 */ "ld3d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27635 | /* 6730 */ "ld3h $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27636 | /* 6754 */ "ld3q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 27637 | /* 6778 */ "ld3r $\xFF\x02\x2A, [$\x01], #3\0" |
| 27638 | /* 6798 */ "ld3r $\xFF\x02\x2B, [$\x01], #24\0" |
| 27639 | /* 6819 */ "ld3r $\xFF\x02\x2C, [$\x01], #24\0" |
| 27640 | /* 6840 */ "ld3r $\xFF\x02\x2D, [$\x01], #12\0" |
| 27641 | /* 6861 */ "ld3r $\xFF\x02\x2E, [$\x01], #6\0" |
| 27642 | /* 6881 */ "ld3r $\xFF\x02\x2F, [$\x01], #12\0" |
| 27643 | /* 6902 */ "ld3r $\xFF\x02\x30, [$\x01], #3\0" |
| 27644 | /* 6922 */ "ld3r $\xFF\x02\x31, [$\x01], #6\0" |
| 27645 | /* 6942 */ "ld3 $\xFF\x02\x2A, [$\x01], #48\0" |
| 27646 | /* 6962 */ "ld3 $\xFF\x02\x2C, [$\x01], #48\0" |
| 27647 | /* 6982 */ "ld3 $\xFF\x02\x2D, [$\x01], #24\0" |
| 27648 | /* 7002 */ "ld3 $\xFF\x02\x2E, [$\x01], #24\0" |
| 27649 | /* 7022 */ "ld3 $\xFF\x02\x2F, [$\x01], #48\0" |
| 27650 | /* 7042 */ "ld3 $\xFF\x02\x30, [$\x01], #24\0" |
| 27651 | /* 7062 */ "ld3 $\xFF\x02\x31, [$\x01], #48\0" |
| 27652 | /* 7082 */ "ld3w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27653 | /* 7106 */ "ld3 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #6\0" |
| 27654 | /* 7129 */ "ld3 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #12\0" |
| 27655 | /* 7153 */ "ld3 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #24\0" |
| 27656 | /* 7177 */ "ld3 $\xFF\x02\x28$\xFF\x04\x19, [$\x01], #3\0" |
| 27657 | /* 7200 */ "ld4b $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27658 | /* 7224 */ "ld4d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27659 | /* 7248 */ "ld4 $\xFF\x02\x2A, [$\x01], #64\0" |
| 27660 | /* 7268 */ "ld4 $\xFF\x02\x2C, [$\x01], #64\0" |
| 27661 | /* 7288 */ "ld4 $\xFF\x02\x2D, [$\x01], #32\0" |
| 27662 | /* 7308 */ "ld4 $\xFF\x02\x2E, [$\x01], #32\0" |
| 27663 | /* 7328 */ "ld4 $\xFF\x02\x2F, [$\x01], #64\0" |
| 27664 | /* 7348 */ "ld4 $\xFF\x02\x30, [$\x01], #32\0" |
| 27665 | /* 7368 */ "ld4 $\xFF\x02\x31, [$\x01], #64\0" |
| 27666 | /* 7388 */ "ld4h $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27667 | /* 7412 */ "ld4q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| 27668 | /* 7436 */ "ld4r $\xFF\x02\x2A, [$\x01], #4\0" |
| 27669 | /* 7456 */ "ld4r $\xFF\x02\x2B, [$\x01], #32\0" |
| 27670 | /* 7477 */ "ld4r $\xFF\x02\x2C, [$\x01], #32\0" |
| 27671 | /* 7498 */ "ld4r $\xFF\x02\x2D, [$\x01], #16\0" |
| 27672 | /* 7519 */ "ld4r $\xFF\x02\x2E, [$\x01], #8\0" |
| 27673 | /* 7539 */ "ld4r $\xFF\x02\x2F, [$\x01], #16\0" |
| 27674 | /* 7560 */ "ld4r $\xFF\x02\x30, [$\x01], #4\0" |
| 27675 | /* 7580 */ "ld4r $\xFF\x02\x31, [$\x01], #8\0" |
| 27676 | /* 7600 */ "ld4w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27677 | /* 7624 */ "ld4 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #8\0" |
| 27678 | /* 7647 */ "ld4 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #16\0" |
| 27679 | /* 7671 */ "ld4 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #32\0" |
| 27680 | /* 7695 */ "ld4 $\xFF\x02\x28$\xFF\x04\x19, [$\x01], #4\0" |
| 27681 | /* 7718 */ "staddb $\x02, [$\x03]\0" |
| 27682 | /* 7734 */ "staddh $\x02, [$\x03]\0" |
| 27683 | /* 7750 */ "staddlb $\x02, [$\x03]\0" |
| 27684 | /* 7767 */ "staddlh $\x02, [$\x03]\0" |
| 27685 | /* 7784 */ "staddl $\x02, [$\x03]\0" |
| 27686 | /* 7800 */ "stadd $\x02, [$\x03]\0" |
| 27687 | /* 7815 */ "ldapp $\x01, $\x02, [$\x03]\0" |
| 27688 | /* 7834 */ "ldapurb $\x01, [$\x02]\0" |
| 27689 | /* 7851 */ "ldapurh $\x01, [$\x02]\0" |
| 27690 | /* 7868 */ "ldapursb $\x01, [$\x02]\0" |
| 27691 | /* 7886 */ "ldapursh $\x01, [$\x02]\0" |
| 27692 | /* 7904 */ "ldapursw $\x01, [$\x02]\0" |
| 27693 | /* 7922 */ "ldapur $\x01, [$\x02]\0" |
| 27694 | /* 7938 */ "ldap $\x01, $\x02, [$\x03]\0" |
| 27695 | /* 7956 */ "stclrb $\x02, [$\x03]\0" |
| 27696 | /* 7972 */ "stclrh $\x02, [$\x03]\0" |
| 27697 | /* 7988 */ "stclrlb $\x02, [$\x03]\0" |
| 27698 | /* 8005 */ "stclrlh $\x02, [$\x03]\0" |
| 27699 | /* 8022 */ "stclrl $\x02, [$\x03]\0" |
| 27700 | /* 8038 */ "stclr $\x02, [$\x03]\0" |
| 27701 | /* 8053 */ "steorb $\x02, [$\x03]\0" |
| 27702 | /* 8069 */ "steorh $\x02, [$\x03]\0" |
| 27703 | /* 8085 */ "steorlb $\x02, [$\x03]\0" |
| 27704 | /* 8102 */ "steorlh $\x02, [$\x03]\0" |
| 27705 | /* 8119 */ "steorl $\x02, [$\x03]\0" |
| 27706 | /* 8135 */ "steor $\x02, [$\x03]\0" |
| 27707 | /* 8150 */ "ldff1b $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27708 | /* 8176 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27709 | /* 8202 */ "ldff1b $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27710 | /* 8228 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27711 | /* 8254 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27712 | /* 8280 */ "ldff1h $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27713 | /* 8306 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27714 | /* 8332 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27715 | /* 8358 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27716 | /* 8385 */ "ldff1sb $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27717 | /* 8412 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27718 | /* 8439 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27719 | /* 8466 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27720 | /* 8493 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27721 | /* 8520 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27722 | /* 8546 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27723 | /* 8572 */ "ldg $\x01, [$\x03]\0" |
| 27724 | /* 8585 */ "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27725 | /* 8611 */ "ldnf1b $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27726 | /* 8637 */ "ldnf1b $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27727 | /* 8663 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27728 | /* 8689 */ "ldnf1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27729 | /* 8715 */ "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27730 | /* 8741 */ "ldnf1h $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27731 | /* 8767 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27732 | /* 8793 */ "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27733 | /* 8820 */ "ldnf1sb $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27734 | /* 8847 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27735 | /* 8874 */ "ldnf1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27736 | /* 8901 */ "ldnf1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27737 | /* 8928 */ "ldnf1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27738 | /* 8955 */ "ldnf1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27739 | /* 8981 */ "ldnf1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27740 | /* 9007 */ "ldnp $\x01, $\x02, [$\x03]\0" |
| 27741 | /* 9025 */ "ldnt1b $\xFF\x01\x26, $\xFF\x02\x27/z, [$\x03]\0" |
| 27742 | /* 9051 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x27/z, [$\x03]\0" |
| 27743 | /* 9077 */ "ldnt1b $\xFF\x01\x26, $\xFF\x02\x27/z, [$\x03]\0" |
| 27744 | /* 9103 */ "ldnt1b $\xFF\x01\x26, $\xFF\x02\x07/z, [$\x03]\0" |
| 27745 | /* 9129 */ "ldnt1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27746 | /* 9157 */ "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27747 | /* 9185 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x27/z, [$\x03]\0" |
| 27748 | /* 9211 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x27/z, [$\x03]\0" |
| 27749 | /* 9237 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| 27750 | /* 9263 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27751 | /* 9291 */ "ldnt1h $\xFF\x01\x29, $\xFF\x02\x27/z, [$\x03]\0" |
| 27752 | /* 9317 */ "ldnt1h $\xFF\x01\x32, $\xFF\x02\x27/z, [$\x03]\0" |
| 27753 | /* 9343 */ "ldnt1h $\xFF\x01\x29, $\xFF\x02\x27/z, [$\x03]\0" |
| 27754 | /* 9369 */ "ldnt1h $\xFF\x01\x29, $\xFF\x02\x07/z, [$\x03]\0" |
| 27755 | /* 9395 */ "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27756 | /* 9423 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27757 | /* 9451 */ "ldnt1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27758 | /* 9480 */ "ldnt1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27759 | /* 9509 */ "ldnt1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27760 | /* 9538 */ "ldnt1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27761 | /* 9567 */ "ldnt1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27762 | /* 9596 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x27/z, [$\x03]\0" |
| 27763 | /* 9622 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x27/z, [$\x03]\0" |
| 27764 | /* 9648 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| 27765 | /* 9674 */ "ldnt1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| 27766 | /* 9702 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| 27767 | /* 9730 */ "ldp $\x01, $\x02, [$\x03]\0" |
| 27768 | /* 9747 */ "ldpsw $\x01, $\x02, [$\x03]\0" |
| 27769 | /* 9766 */ "ldraa $\x01, [$\x02]\0" |
| 27770 | /* 9781 */ "ldrab $\x01, [$\x02]\0" |
| 27771 | /* 9796 */ "ldrb $\x01, [$\x02, $\x03]\0" |
| 27772 | /* 9814 */ "ldrb $\x01, [$\x02]\0" |
| 27773 | /* 9828 */ "ldr $\x01, [$\x02, $\x03]\0" |
| 27774 | /* 9845 */ "ldr $\x01, [$\x02]\0" |
| 27775 | /* 9858 */ "ldrh $\x01, [$\x02, $\x03]\0" |
| 27776 | /* 9876 */ "ldrh $\x01, [$\x02]\0" |
| 27777 | /* 9890 */ "ldrsb $\x01, [$\x02, $\x03]\0" |
| 27778 | /* 9909 */ "ldrsb $\x01, [$\x02]\0" |
| 27779 | /* 9924 */ "ldrsh $\x01, [$\x02, $\x03]\0" |
| 27780 | /* 9943 */ "ldrsh $\x01, [$\x02]\0" |
| 27781 | /* 9958 */ "ldrsw $\x01, [$\x02, $\x03]\0" |
| 27782 | /* 9977 */ "ldrsw $\x01, [$\x02]\0" |
| 27783 | /* 9992 */ "ldr $\xFF\x01\x07, [$\x02]\0" |
| 27784 | /* 10007 */ "ldr $\xFF\x01\x35[$\x02, $\xFF\x03\x20], [$\x04]\0" |
| 27785 | /* 10032 */ "stsetb $\x02, [$\x03]\0" |
| 27786 | /* 10048 */ "stseth $\x02, [$\x03]\0" |
| 27787 | /* 10064 */ "stsetlb $\x02, [$\x03]\0" |
| 27788 | /* 10081 */ "stsetlh $\x02, [$\x03]\0" |
| 27789 | /* 10098 */ "stsetl $\x02, [$\x03]\0" |
| 27790 | /* 10114 */ "stset $\x02, [$\x03]\0" |
| 27791 | /* 10129 */ "stsmaxb $\x02, [$\x03]\0" |
| 27792 | /* 10146 */ "stsmaxh $\x02, [$\x03]\0" |
| 27793 | /* 10163 */ "stsmaxlb $\x02, [$\x03]\0" |
| 27794 | /* 10181 */ "stsmaxlh $\x02, [$\x03]\0" |
| 27795 | /* 10199 */ "stsmaxl $\x02, [$\x03]\0" |
| 27796 | /* 10216 */ "stsmax $\x02, [$\x03]\0" |
| 27797 | /* 10232 */ "stsminb $\x02, [$\x03]\0" |
| 27798 | /* 10249 */ "stsminh $\x02, [$\x03]\0" |
| 27799 | /* 10266 */ "stsminlb $\x02, [$\x03]\0" |
| 27800 | /* 10284 */ "stsminlh $\x02, [$\x03]\0" |
| 27801 | /* 10302 */ "stsminl $\x02, [$\x03]\0" |
| 27802 | /* 10319 */ "stsmin $\x02, [$\x03]\0" |
| 27803 | /* 10335 */ "sttaddl $\x02, [$\x03]\0" |
| 27804 | /* 10352 */ "sttadd $\x02, [$\x03]\0" |
| 27805 | /* 10368 */ "sttclrl $\x02, [$\x03]\0" |
| 27806 | /* 10385 */ "sttclr $\x02, [$\x03]\0" |
| 27807 | /* 10401 */ "ldtnp $\x01, $\x02, [$\x03]\0" |
| 27808 | /* 10420 */ "ldtp $\x01, $\x02, [$\x03]\0" |
| 27809 | /* 10438 */ "ldtrb $\x01, [$\x02]\0" |
| 27810 | /* 10453 */ "ldtrh $\x01, [$\x02]\0" |
| 27811 | /* 10468 */ "ldtrsb $\x01, [$\x02]\0" |
| 27812 | /* 10484 */ "ldtrsh $\x01, [$\x02]\0" |
| 27813 | /* 10500 */ "ldtrsw $\x01, [$\x02]\0" |
| 27814 | /* 10516 */ "ldtr $\x01, [$\x02]\0" |
| 27815 | /* 10530 */ "sttsetl $\x02, [$\x03]\0" |
| 27816 | /* 10547 */ "sttset $\x02, [$\x03]\0" |
| 27817 | /* 10563 */ "stumaxb $\x02, [$\x03]\0" |
| 27818 | /* 10580 */ "stumaxh $\x02, [$\x03]\0" |
| 27819 | /* 10597 */ "stumaxlb $\x02, [$\x03]\0" |
| 27820 | /* 10615 */ "stumaxlh $\x02, [$\x03]\0" |
| 27821 | /* 10633 */ "stumaxl $\x02, [$\x03]\0" |
| 27822 | /* 10650 */ "stumax $\x02, [$\x03]\0" |
| 27823 | /* 10666 */ "stuminb $\x02, [$\x03]\0" |
| 27824 | /* 10683 */ "stuminh $\x02, [$\x03]\0" |
| 27825 | /* 10700 */ "stuminlb $\x02, [$\x03]\0" |
| 27826 | /* 10718 */ "stuminlh $\x02, [$\x03]\0" |
| 27827 | /* 10736 */ "stuminl $\x02, [$\x03]\0" |
| 27828 | /* 10753 */ "stumin $\x02, [$\x03]\0" |
| 27829 | /* 10769 */ "ldurb $\x01, [$\x02]\0" |
| 27830 | /* 10784 */ "ldur $\x01, [$\x02]\0" |
| 27831 | /* 10798 */ "ldurh $\x01, [$\x02]\0" |
| 27832 | /* 10813 */ "ldursb $\x01, [$\x02]\0" |
| 27833 | /* 10829 */ "ldursh $\x01, [$\x02]\0" |
| 27834 | /* 10845 */ "ldursw $\x01, [$\x02]\0" |
| 27835 | /* 10861 */ "mul $\x01, $\x02, $\x03\0" |
| 27836 | /* 10876 */ "mov $\xFF\x01\x26, $\xFF\x02\x1F[$\x03, $\xFF\x04\x36]\0" |
| 27837 | /* 10901 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x36]\0" |
| 27838 | /* 10926 */ "mov $\xFF\x01\x29, $\xFF\x02\x1F[$\x03, $\xFF\x04\x36]\0" |
| 27839 | /* 10951 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x36]\0" |
| 27840 | /* 10976 */ "mov $\xFF\x01\x26, $\xFF\x02\x21[$\x03, $\xFF\x04\x36]\0" |
| 27841 | /* 11001 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x36]\0" |
| 27842 | /* 11026 */ "mov $\xFF\x01\x29, $\xFF\x02\x21[$\x03, $\xFF\x04\x36]\0" |
| 27843 | /* 11051 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x36]\0" |
| 27844 | /* 11076 */ "mov $\xFF\x01\x26, $\xFF\x02\x1F[$\x03, $\xFF\x04\x37]\0" |
| 27845 | /* 11101 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x37]\0" |
| 27846 | /* 11126 */ "mov $\xFF\x01\x29, $\xFF\x02\x1F[$\x03, $\xFF\x04\x37]\0" |
| 27847 | /* 11151 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x37]\0" |
| 27848 | /* 11176 */ "mov $\xFF\x01\x26, $\xFF\x02\x21[$\x03, $\xFF\x04\x37]\0" |
| 27849 | /* 11201 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x37]\0" |
| 27850 | /* 11226 */ "mov $\xFF\x01\x29, $\xFF\x02\x21[$\x03, $\xFF\x04\x37]\0" |
| 27851 | /* 11251 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x37]\0" |
| 27852 | /* 11276 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x36], $\xFF\x05\x26\0" |
| 27853 | /* 11301 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x36], $\xFF\x05\x23\0" |
| 27854 | /* 11326 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x36], $\xFF\x05\x29\0" |
| 27855 | /* 11351 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x36], $\xFF\x05\x24\0" |
| 27856 | /* 11376 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x36], $\xFF\x05\x26\0" |
| 27857 | /* 11401 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x36], $\xFF\x05\x23\0" |
| 27858 | /* 11426 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x36], $\xFF\x05\x29\0" |
| 27859 | /* 11451 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x36], $\xFF\x05\x24\0" |
| 27860 | /* 11476 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x37], $\xFF\x05\x26\0" |
| 27861 | /* 11501 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x37], $\xFF\x05\x23\0" |
| 27862 | /* 11526 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x37], $\xFF\x05\x29\0" |
| 27863 | /* 11551 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x37], $\xFF\x05\x24\0" |
| 27864 | /* 11576 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x37], $\xFF\x05\x26\0" |
| 27865 | /* 11601 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x37], $\xFF\x05\x23\0" |
| 27866 | /* 11626 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x37], $\xFF\x05\x29\0" |
| 27867 | /* 11651 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x37], $\xFF\x05\x24\0" |
| 27868 | /* 11676 */ "mov $\xFF\x01\x23, $\xFF\x02\x38[$\x03, $\xFF\x04\x20, vgx2]\0" |
| 27869 | /* 11707 */ "mov $\xFF\x01\x38[$\x03, $\xFF\x04\x20, vgx2], $\xFF\x05\x23\0" |
| 27870 | /* 11738 */ "mov $\xFF\x01\x23, $\xFF\x02\x38[$\x03, $\xFF\x04\x20, vgx4]\0" |
| 27871 | /* 11769 */ "mov $\xFF\x01\x38[$\x03, $\xFF\x04\x20, vgx4], $\xFF\x05\x23\0" |
| 27872 | /* 11800 */ "movt $\x01, $\xFF\x03\x07\0" |
| 27873 | /* 11814 */ "smstart\0" |
| 27874 | /* 11822 */ "smstart sm\0" |
| 27875 | /* 11833 */ "smstart za\0" |
| 27876 | /* 11844 */ "smstop\0" |
| 27877 | /* 11851 */ "smstop sm\0" |
| 27878 | /* 11861 */ "smstop za\0" |
| 27879 | /* 11871 */ "mneg $\x01, $\x02, $\x03\0" |
| 27880 | /* 11887 */ "nop\0" |
| 27881 | /* 11891 */ "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0" |
| 27882 | /* 11914 */ "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0" |
| 27883 | /* 11935 */ "mvn $\x01, $\x03\0" |
| 27884 | /* 11946 */ "mvn $\x01, $\x03$\xFF\x04\x02\0" |
| 27885 | /* 11961 */ "orn $\x01, $\x02, $\x03\0" |
| 27886 | /* 11976 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0" |
| 27887 | /* 11992 */ "mov $\x01, $\x03\0" |
| 27888 | /* 12003 */ "orr $\x01, $\x02, $\x03\0" |
| 27889 | /* 12018 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0" |
| 27890 | /* 12033 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| 27891 | /* 12054 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| 27892 | /* 12075 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| 27893 | /* 12096 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0" |
| 27894 | /* 12111 */ "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0" |
| 27895 | /* 12134 */ "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0" |
| 27896 | /* 12155 */ "pacia1716\0" |
| 27897 | /* 12165 */ "paciasp\0" |
| 27898 | /* 12173 */ "paciaz\0" |
| 27899 | /* 12180 */ "pacib1716\0" |
| 27900 | /* 12190 */ "pacibsp\0" |
| 27901 | /* 12198 */ "pacibz\0" |
| 27902 | /* 12205 */ "pacm\0" |
| 27903 | /* 12210 */ "pmov $\xFF\x01\x06, $\xFF\x02\x07\0" |
| 27904 | /* 12226 */ "pmov $\xFF\x01\x07, $\xFF\x04\x06\0" |
| 27905 | /* 12242 */ "prfb $\xFF\x01\x3A, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 27906 | /* 12266 */ "prfb $\xFF\x01\x3A, $\xFF\x02\x07, [$\x03]\0" |
| 27907 | /* 12288 */ "prfb $\xFF\x01\x3A, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 27908 | /* 12312 */ "prfd $\xFF\x01\x3A, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 27909 | /* 12336 */ "prfd $\xFF\x01\x3A, $\xFF\x02\x07, [$\x03]\0" |
| 27910 | /* 12358 */ "prfd $\xFF\x01\x3A, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 27911 | /* 12382 */ "prfh $\xFF\x01\x3A, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 27912 | /* 12406 */ "prfh $\xFF\x01\x3A, $\xFF\x02\x07, [$\x03]\0" |
| 27913 | /* 12428 */ "prfh $\xFF\x01\x3A, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 27914 | /* 12452 */ "prfm $\xFF\x01\x3B, [$\x02, $\x03]\0" |
| 27915 | /* 12472 */ "prfm $\xFF\x01\x3B, [$\x02]\0" |
| 27916 | /* 12488 */ "prfum $\xFF\x01\x3B, [$\x02]\0" |
| 27917 | /* 12505 */ "prfw $\xFF\x01\x3A, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 27918 | /* 12529 */ "prfw $\xFF\x01\x3A, $\xFF\x02\x07, [$\x03]\0" |
| 27919 | /* 12551 */ "prfw $\xFF\x01\x3A, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 27920 | /* 12575 */ "ptrues $\xFF\x01\x06\0" |
| 27921 | /* 12587 */ "ptrues $\xFF\x01\x10\0" |
| 27922 | /* 12599 */ "ptrues $\xFF\x01\x09\0" |
| 27923 | /* 12611 */ "ptrues $\xFF\x01\x0B\0" |
| 27924 | /* 12623 */ "ptrue $\xFF\x01\x06\0" |
| 27925 | /* 12634 */ "ptrue $\xFF\x01\x10\0" |
| 27926 | /* 12645 */ "ptrue $\xFF\x01\x09\0" |
| 27927 | /* 12656 */ "ptrue $\xFF\x01\x0B\0" |
| 27928 | /* 12667 */ "ret\0" |
| 27929 | /* 12671 */ "ngcs $\x01, $\x03\0" |
| 27930 | /* 12683 */ "ngc $\x01, $\x03\0" |
| 27931 | /* 12694 */ "asr $\x01, $\x02, $\x03\0" |
| 27932 | /* 12709 */ "sxtb $\x01, $\x02\0" |
| 27933 | /* 12721 */ "sxth $\x01, $\x02\0" |
| 27934 | /* 12733 */ "sxtw $\x01, $\x02\0" |
| 27935 | /* 12745 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0" |
| 27936 | /* 12768 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0" |
| 27937 | /* 12791 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0" |
| 27938 | /* 12814 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0" |
| 27939 | /* 12837 */ "smull $\x01, $\x02, $\x03\0" |
| 27940 | /* 12854 */ "smnegl $\x01, $\x02, $\x03\0" |
| 27941 | /* 12872 */ "sqdecb $\x01\0" |
| 27942 | /* 12882 */ "sqdecb $\x01, $\xFF\x03\x0E\0" |
| 27943 | /* 12898 */ "sqdecb $\x01, $\xFF\x02\x3C\0" |
| 27944 | /* 12914 */ "sqdecb $\x01, $\xFF\x02\x3C, $\xFF\x03\x0E\0" |
| 27945 | /* 12936 */ "sqdecd $\x01\0" |
| 27946 | /* 12946 */ "sqdecd $\x01, $\xFF\x03\x0E\0" |
| 27947 | /* 12962 */ "sqdecd $\x01, $\xFF\x02\x3C\0" |
| 27948 | /* 12978 */ "sqdecd $\x01, $\xFF\x02\x3C, $\xFF\x03\x0E\0" |
| 27949 | /* 13000 */ "sqdecd $\xFF\x01\x10\0" |
| 27950 | /* 13012 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 27951 | /* 13030 */ "sqdech $\x01\0" |
| 27952 | /* 13040 */ "sqdech $\x01, $\xFF\x03\x0E\0" |
| 27953 | /* 13056 */ "sqdech $\x01, $\xFF\x02\x3C\0" |
| 27954 | /* 13072 */ "sqdech $\x01, $\xFF\x02\x3C, $\xFF\x03\x0E\0" |
| 27955 | /* 13094 */ "sqdech $\xFF\x01\x09\0" |
| 27956 | /* 13106 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 27957 | /* 13124 */ "sqdecw $\x01\0" |
| 27958 | /* 13134 */ "sqdecw $\x01, $\xFF\x03\x0E\0" |
| 27959 | /* 13150 */ "sqdecw $\x01, $\xFF\x02\x3C\0" |
| 27960 | /* 13166 */ "sqdecw $\x01, $\xFF\x02\x3C, $\xFF\x03\x0E\0" |
| 27961 | /* 13188 */ "sqdecw $\xFF\x01\x0B\0" |
| 27962 | /* 13200 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 27963 | /* 13218 */ "sqincb $\x01\0" |
| 27964 | /* 13228 */ "sqincb $\x01, $\xFF\x03\x0E\0" |
| 27965 | /* 13244 */ "sqincb $\x01, $\xFF\x02\x3C\0" |
| 27966 | /* 13260 */ "sqincb $\x01, $\xFF\x02\x3C, $\xFF\x03\x0E\0" |
| 27967 | /* 13282 */ "sqincd $\x01\0" |
| 27968 | /* 13292 */ "sqincd $\x01, $\xFF\x03\x0E\0" |
| 27969 | /* 13308 */ "sqincd $\x01, $\xFF\x02\x3C\0" |
| 27970 | /* 13324 */ "sqincd $\x01, $\xFF\x02\x3C, $\xFF\x03\x0E\0" |
| 27971 | /* 13346 */ "sqincd $\xFF\x01\x10\0" |
| 27972 | /* 13358 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 27973 | /* 13376 */ "sqinch $\x01\0" |
| 27974 | /* 13386 */ "sqinch $\x01, $\xFF\x03\x0E\0" |
| 27975 | /* 13402 */ "sqinch $\x01, $\xFF\x02\x3C\0" |
| 27976 | /* 13418 */ "sqinch $\x01, $\xFF\x02\x3C, $\xFF\x03\x0E\0" |
| 27977 | /* 13440 */ "sqinch $\xFF\x01\x09\0" |
| 27978 | /* 13452 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 27979 | /* 13470 */ "sqincw $\x01\0" |
| 27980 | /* 13480 */ "sqincw $\x01, $\xFF\x03\x0E\0" |
| 27981 | /* 13496 */ "sqincw $\x01, $\xFF\x02\x3C\0" |
| 27982 | /* 13512 */ "sqincw $\x01, $\xFF\x02\x3C, $\xFF\x03\x0E\0" |
| 27983 | /* 13534 */ "sqincw $\xFF\x01\x0B\0" |
| 27984 | /* 13546 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 27985 | /* 13564 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 27986 | /* 13588 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 27987 | /* 13612 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 27988 | /* 13636 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 27989 | /* 13660 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 27990 | /* 13684 */ "st1q $\xFF\x01\x25, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 27991 | /* 13708 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 27992 | /* 13732 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 27993 | /* 13756 */ "st1b $\xFF\x01\x26, $\xFF\x02\x27, [$\x03]\0" |
| 27994 | /* 13778 */ "st1b $\xFF\x01\x28, $\xFF\x02\x27, [$\x03]\0" |
| 27995 | /* 13800 */ "st1b $\xFF\x01\x26, $\xFF\x02\x27, [$\x03]\0" |
| 27996 | /* 13822 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 27997 | /* 13844 */ "st1b $\xFF\x01\x29, $\xFF\x02\x07, [$\x03]\0" |
| 27998 | /* 13866 */ "st1b $\xFF\x01\x26, $\xFF\x02\x07, [$\x03]\0" |
| 27999 | /* 13888 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 28000 | /* 13910 */ "st1d $\xFF\x01\x23, $\xFF\x02\x27, [$\x03]\0" |
| 28001 | /* 13932 */ "st1d $\xFF\x01\x23, $\xFF\x02\x27, [$\x03]\0" |
| 28002 | /* 13954 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 28003 | /* 13976 */ "st1d $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 28004 | /* 13998 */ "st1 $\xFF\x02\x2A, [$\x01], #64\0" |
| 28005 | /* 14018 */ "st1 $\xFF\x02\x2B, [$\x01], #32\0" |
| 28006 | /* 14038 */ "st1 $\xFF\x02\x2C, [$\x01], #64\0" |
| 28007 | /* 14058 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0" |
| 28008 | /* 14078 */ "st1 $\xFF\x02\x2E, [$\x01], #32\0" |
| 28009 | /* 14098 */ "st1 $\xFF\x02\x2F, [$\x01], #64\0" |
| 28010 | /* 14118 */ "st1 $\xFF\x02\x30, [$\x01], #32\0" |
| 28011 | /* 14138 */ "st1 $\xFF\x02\x31, [$\x01], #64\0" |
| 28012 | /* 14158 */ "st1h $\xFF\x01\x29, $\xFF\x02\x27, [$\x03]\0" |
| 28013 | /* 14180 */ "st1h $\xFF\x01\x32, $\xFF\x02\x27, [$\x03]\0" |
| 28014 | /* 14202 */ "st1h $\xFF\x01\x29, $\xFF\x02\x27, [$\x03]\0" |
| 28015 | /* 14224 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 28016 | /* 14246 */ "st1h $\xFF\x01\x29, $\xFF\x02\x07, [$\x03]\0" |
| 28017 | /* 14268 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 28018 | /* 14290 */ "st1 $\xFF\x02\x2A, [$\x01], #16\0" |
| 28019 | /* 14310 */ "st1 $\xFF\x02\x2B, [$\x01], #8\0" |
| 28020 | /* 14329 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0" |
| 28021 | /* 14349 */ "st1 $\xFF\x02\x2D, [$\x01], #8\0" |
| 28022 | /* 14368 */ "st1 $\xFF\x02\x2E, [$\x01], #8\0" |
| 28023 | /* 14387 */ "st1 $\xFF\x02\x2F, [$\x01], #16\0" |
| 28024 | /* 14407 */ "st1 $\xFF\x02\x30, [$\x01], #8\0" |
| 28025 | /* 14426 */ "st1 $\xFF\x02\x31, [$\x01], #16\0" |
| 28026 | /* 14446 */ "st1 $\xFF\x02\x2A, [$\x01], #48\0" |
| 28027 | /* 14466 */ "st1 $\xFF\x02\x2B, [$\x01], #24\0" |
| 28028 | /* 14486 */ "st1 $\xFF\x02\x2C, [$\x01], #48\0" |
| 28029 | /* 14506 */ "st1 $\xFF\x02\x2D, [$\x01], #24\0" |
| 28030 | /* 14526 */ "st1 $\xFF\x02\x2E, [$\x01], #24\0" |
| 28031 | /* 14546 */ "st1 $\xFF\x02\x2F, [$\x01], #48\0" |
| 28032 | /* 14566 */ "st1 $\xFF\x02\x30, [$\x01], #24\0" |
| 28033 | /* 14586 */ "st1 $\xFF\x02\x31, [$\x01], #48\0" |
| 28034 | /* 14606 */ "st1 $\xFF\x02\x2A, [$\x01], #32\0" |
| 28035 | /* 14626 */ "st1 $\xFF\x02\x2B, [$\x01], #16\0" |
| 28036 | /* 14646 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0" |
| 28037 | /* 14666 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0" |
| 28038 | /* 14686 */ "st1 $\xFF\x02\x2E, [$\x01], #16\0" |
| 28039 | /* 14706 */ "st1 $\xFF\x02\x2F, [$\x01], #32\0" |
| 28040 | /* 14726 */ "st1 $\xFF\x02\x30, [$\x01], #16\0" |
| 28041 | /* 14746 */ "st1 $\xFF\x02\x31, [$\x01], #32\0" |
| 28042 | /* 14766 */ "st1w $\xFF\x01\x24, $\xFF\x02\x27, [$\x03]\0" |
| 28043 | /* 14788 */ "st1w $\xFF\x01\x24, $\xFF\x02\x27, [$\x03]\0" |
| 28044 | /* 14810 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 28045 | /* 14832 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 28046 | /* 14854 */ "st1w $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 28047 | /* 14876 */ "st1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28048 | /* 14910 */ "st1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28049 | /* 14944 */ "st1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28050 | /* 14978 */ "st1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28051 | /* 15012 */ "st1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28052 | /* 15046 */ "st1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28053 | /* 15080 */ "st1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28054 | /* 15114 */ "st1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28055 | /* 15148 */ "st1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28056 | /* 15182 */ "st1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| 28057 | /* 15216 */ "st1 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #2\0" |
| 28058 | /* 15239 */ "st1 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #4\0" |
| 28059 | /* 15262 */ "st1 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #8\0" |
| 28060 | /* 15285 */ "st1 $\xFF\x02\x28$\xFF\x03\x19, [$\x01], #1\0" |
| 28061 | /* 15308 */ "st2b $\xFF\x01\x26, $\xFF\x02\x07, [$\x03]\0" |
| 28062 | /* 15330 */ "st2d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 28063 | /* 15352 */ "st2g $\x01, [$\x02]\0" |
| 28064 | /* 15366 */ "st2h $\xFF\x01\x29, $\xFF\x02\x07, [$\x03]\0" |
| 28065 | /* 15388 */ "st2q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 28066 | /* 15410 */ "st2 $\xFF\x02\x2A, [$\x01], #32\0" |
| 28067 | /* 15430 */ "st2 $\xFF\x02\x2C, [$\x01], #32\0" |
| 28068 | /* 15450 */ "st2 $\xFF\x02\x2D, [$\x01], #16\0" |
| 28069 | /* 15470 */ "st2 $\xFF\x02\x2E, [$\x01], #16\0" |
| 28070 | /* 15490 */ "st2 $\xFF\x02\x2F, [$\x01], #32\0" |
| 28071 | /* 15510 */ "st2 $\xFF\x02\x30, [$\x01], #16\0" |
| 28072 | /* 15530 */ "st2 $\xFF\x02\x31, [$\x01], #32\0" |
| 28073 | /* 15550 */ "st2w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 28074 | /* 15572 */ "st2 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #4\0" |
| 28075 | /* 15595 */ "st2 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #8\0" |
| 28076 | /* 15618 */ "st2 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #16\0" |
| 28077 | /* 15642 */ "st2 $\xFF\x02\x28$\xFF\x03\x19, [$\x01], #2\0" |
| 28078 | /* 15665 */ "st3b $\xFF\x01\x26, $\xFF\x02\x07, [$\x03]\0" |
| 28079 | /* 15687 */ "st3d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 28080 | /* 15709 */ "st3h $\xFF\x01\x29, $\xFF\x02\x07, [$\x03]\0" |
| 28081 | /* 15731 */ "st3q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 28082 | /* 15753 */ "st3 $\xFF\x02\x2A, [$\x01], #48\0" |
| 28083 | /* 15773 */ "st3 $\xFF\x02\x2C, [$\x01], #48\0" |
| 28084 | /* 15793 */ "st3 $\xFF\x02\x2D, [$\x01], #24\0" |
| 28085 | /* 15813 */ "st3 $\xFF\x02\x2E, [$\x01], #24\0" |
| 28086 | /* 15833 */ "st3 $\xFF\x02\x2F, [$\x01], #48\0" |
| 28087 | /* 15853 */ "st3 $\xFF\x02\x30, [$\x01], #24\0" |
| 28088 | /* 15873 */ "st3 $\xFF\x02\x31, [$\x01], #48\0" |
| 28089 | /* 15893 */ "st3w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 28090 | /* 15915 */ "st3 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #6\0" |
| 28091 | /* 15938 */ "st3 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #12\0" |
| 28092 | /* 15962 */ "st3 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #24\0" |
| 28093 | /* 15986 */ "st3 $\xFF\x02\x28$\xFF\x03\x19, [$\x01], #3\0" |
| 28094 | /* 16009 */ "st4b $\xFF\x01\x26, $\xFF\x02\x07, [$\x03]\0" |
| 28095 | /* 16031 */ "st4d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 28096 | /* 16053 */ "st4 $\xFF\x02\x2A, [$\x01], #64\0" |
| 28097 | /* 16073 */ "st4 $\xFF\x02\x2C, [$\x01], #64\0" |
| 28098 | /* 16093 */ "st4 $\xFF\x02\x2D, [$\x01], #32\0" |
| 28099 | /* 16113 */ "st4 $\xFF\x02\x2E, [$\x01], #32\0" |
| 28100 | /* 16133 */ "st4 $\xFF\x02\x2F, [$\x01], #64\0" |
| 28101 | /* 16153 */ "st4 $\xFF\x02\x30, [$\x01], #32\0" |
| 28102 | /* 16173 */ "st4 $\xFF\x02\x31, [$\x01], #64\0" |
| 28103 | /* 16193 */ "st4h $\xFF\x01\x29, $\xFF\x02\x07, [$\x03]\0" |
| 28104 | /* 16215 */ "st4q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| 28105 | /* 16237 */ "st4w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 28106 | /* 16259 */ "st4 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #8\0" |
| 28107 | /* 16282 */ "st4 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #16\0" |
| 28108 | /* 16306 */ "st4 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #32\0" |
| 28109 | /* 16330 */ "st4 $\xFF\x02\x28$\xFF\x03\x19, [$\x01], #4\0" |
| 28110 | /* 16353 */ "stgp $\x01, $\x02, [$\x03]\0" |
| 28111 | /* 16371 */ "stg $\x01, [$\x02]\0" |
| 28112 | /* 16384 */ "stlp $\x01, $\x02, [$\x03]\0" |
| 28113 | /* 16402 */ "stlurb $\x01, [$\x02]\0" |
| 28114 | /* 16418 */ "stlurh $\x01, [$\x02]\0" |
| 28115 | /* 16434 */ "stlur $\x01, [$\x02]\0" |
| 28116 | /* 16449 */ "stnp $\x01, $\x02, [$\x03]\0" |
| 28117 | /* 16467 */ "stnt1b $\xFF\x01\x26, $\xFF\x02\x27, [$\x03]\0" |
| 28118 | /* 16491 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x27, [$\x03]\0" |
| 28119 | /* 16515 */ "stnt1b $\xFF\x01\x26, $\xFF\x02\x27, [$\x03]\0" |
| 28120 | /* 16539 */ "stnt1b $\xFF\x01\x26, $\xFF\x02\x07, [$\x03]\0" |
| 28121 | /* 16563 */ "stnt1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 28122 | /* 16589 */ "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 28123 | /* 16615 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x27, [$\x03]\0" |
| 28124 | /* 16639 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x27, [$\x03]\0" |
| 28125 | /* 16663 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| 28126 | /* 16687 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 28127 | /* 16713 */ "stnt1h $\xFF\x01\x29, $\xFF\x02\x27, [$\x03]\0" |
| 28128 | /* 16737 */ "stnt1h $\xFF\x01\x32, $\xFF\x02\x27, [$\x03]\0" |
| 28129 | /* 16761 */ "stnt1h $\xFF\x01\x29, $\xFF\x02\x27, [$\x03]\0" |
| 28130 | /* 16785 */ "stnt1h $\xFF\x01\x29, $\xFF\x02\x07, [$\x03]\0" |
| 28131 | /* 16809 */ "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 28132 | /* 16835 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 28133 | /* 16861 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x27, [$\x03]\0" |
| 28134 | /* 16885 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x27, [$\x03]\0" |
| 28135 | /* 16909 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| 28136 | /* 16933 */ "stnt1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| 28137 | /* 16959 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| 28138 | /* 16985 */ "stp $\x01, $\x02, [$\x03]\0" |
| 28139 | /* 17002 */ "strb $\x01, [$\x02, $\x03]\0" |
| 28140 | /* 17020 */ "strb $\x01, [$\x02]\0" |
| 28141 | /* 17034 */ "str $\x01, [$\x02, $\x03]\0" |
| 28142 | /* 17051 */ "str $\x01, [$\x02]\0" |
| 28143 | /* 17064 */ "strh $\x01, [$\x02, $\x03]\0" |
| 28144 | /* 17082 */ "strh $\x01, [$\x02]\0" |
| 28145 | /* 17096 */ "str $\xFF\x01\x07, [$\x02]\0" |
| 28146 | /* 17111 */ "str $\xFF\x01\x35[$\x02, $\xFF\x03\x20], [$\x04]\0" |
| 28147 | /* 17136 */ "sttnp $\x01, $\x02, [$\x03]\0" |
| 28148 | /* 17155 */ "sttp $\x01, $\x02, [$\x03]\0" |
| 28149 | /* 17173 */ "sttrb $\x01, [$\x02]\0" |
| 28150 | /* 17188 */ "sttrh $\x01, [$\x02]\0" |
| 28151 | /* 17203 */ "sttr $\x01, [$\x02]\0" |
| 28152 | /* 17217 */ "sturb $\x01, [$\x02]\0" |
| 28153 | /* 17232 */ "stur $\x01, [$\x02]\0" |
| 28154 | /* 17246 */ "sturh $\x01, [$\x02]\0" |
| 28155 | /* 17261 */ "stz2g $\x01, [$\x02]\0" |
| 28156 | /* 17276 */ "stzg $\x01, [$\x02]\0" |
| 28157 | /* 17290 */ "subpt $\x01, $\x02, $\x03\0" |
| 28158 | /* 17307 */ "cmp $\x02, $\xFF\x03\x01\0" |
| 28159 | /* 17320 */ "cmp $\x02, $\x03\0" |
| 28160 | /* 17331 */ "cmp $\x02, $\x03$\xFF\x04\x02\0" |
| 28161 | /* 17346 */ "negs $\x01, $\x03\0" |
| 28162 | /* 17358 */ "negs $\x01, $\x03$\xFF\x04\x02\0" |
| 28163 | /* 17374 */ "subs $\x01, $\x02, $\x03\0" |
| 28164 | /* 17390 */ "cmp $\x02, $\x03$\xFF\x04\x03\0" |
| 28165 | /* 17405 */ "neg $\x01, $\x03\0" |
| 28166 | /* 17416 */ "neg $\x01, $\x03$\xFF\x04\x02\0" |
| 28167 | /* 17431 */ "sub $\x01, $\x02, $\x03\0" |
| 28168 | /* 17446 */ "sysp $\x01, $\xFF\x02\x3D, $\xFF\x03\x3D, $\x04\0" |
| 28169 | /* 17470 */ "apas $\x05\0" |
| 28170 | /* 17478 */ "brb iall\0" |
| 28171 | /* 17487 */ "brb inj\0" |
| 28172 | /* 17495 */ "trcit $\x05\0" |
| 28173 | /* 17504 */ "sys $\x01, $\xFF\x02\x3D, $\xFF\x03\x3D, $\x04\0" |
| 28174 | /* 17527 */ "tchangeb $\x01, $\xFF\x02\x0D\0" |
| 28175 | /* 17545 */ "tchangeb $\x01, $\x02\0" |
| 28176 | /* 17561 */ "tchangef $\x01, $\xFF\x02\x0D\0" |
| 28177 | /* 17579 */ "tchangef $\x01, $\x02\0" |
| 28178 | /* 17595 */ "tenter $\xFF\x01\x0D\0" |
| 28179 | /* 17607 */ "texit\0" |
| 28180 | /* 17613 */ "tfltnz $\x01, $\xFF\x02\x3C, $\x03\0" |
| 28181 | /* 17633 */ "tfltz $\x01, $\xFF\x02\x3C, $\x03\0" |
| 28182 | /* 17652 */ "lsr $\x01, $\x02, $\x03\0" |
| 28183 | /* 17667 */ "uxtb $\x01, $\x02\0" |
| 28184 | /* 17679 */ "uxth $\x01, $\x02\0" |
| 28185 | /* 17691 */ "uxtw $\x01, $\x02\0" |
| 28186 | /* 17703 */ "umull $\x01, $\x02, $\x03\0" |
| 28187 | /* 17720 */ "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19\0" |
| 28188 | /* 17739 */ "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19\0" |
| 28189 | /* 17758 */ "umnegl $\x01, $\x02, $\x03\0" |
| 28190 | /* 17776 */ "uqdecb $\x01\0" |
| 28191 | /* 17786 */ "uqdecb $\x01, $\xFF\x03\x0E\0" |
| 28192 | /* 17802 */ "uqdecd $\x01\0" |
| 28193 | /* 17812 */ "uqdecd $\x01, $\xFF\x03\x0E\0" |
| 28194 | /* 17828 */ "uqdecd $\xFF\x01\x10\0" |
| 28195 | /* 17840 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 28196 | /* 17858 */ "uqdech $\x01\0" |
| 28197 | /* 17868 */ "uqdech $\x01, $\xFF\x03\x0E\0" |
| 28198 | /* 17884 */ "uqdech $\xFF\x01\x09\0" |
| 28199 | /* 17896 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 28200 | /* 17914 */ "uqdecw $\x01\0" |
| 28201 | /* 17924 */ "uqdecw $\x01, $\xFF\x03\x0E\0" |
| 28202 | /* 17940 */ "uqdecw $\xFF\x01\x0B\0" |
| 28203 | /* 17952 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 28204 | /* 17970 */ "uqincb $\x01\0" |
| 28205 | /* 17980 */ "uqincb $\x01, $\xFF\x03\x0E\0" |
| 28206 | /* 17996 */ "uqincd $\x01\0" |
| 28207 | /* 18006 */ "uqincd $\x01, $\xFF\x03\x0E\0" |
| 28208 | /* 18022 */ "uqincd $\xFF\x01\x10\0" |
| 28209 | /* 18034 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| 28210 | /* 18052 */ "uqinch $\x01\0" |
| 28211 | /* 18062 */ "uqinch $\x01, $\xFF\x03\x0E\0" |
| 28212 | /* 18078 */ "uqinch $\xFF\x01\x09\0" |
| 28213 | /* 18090 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| 28214 | /* 18108 */ "uqincw $\x01\0" |
| 28215 | /* 18118 */ "uqincw $\x01, $\xFF\x03\x0E\0" |
| 28216 | /* 18134 */ "uqincw $\xFF\x01\x0B\0" |
| 28217 | /* 18146 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| 28218 | /* 18164 */ "xpaclri\0" |
| 28219 | /* 18172 */ "zero {za}\0" |
| 28220 | /* 18182 */ "zero {za0.h}\0" |
| 28221 | /* 18195 */ "zero {za1.h}\0" |
| 28222 | /* 18208 */ "zero {za0.s}\0" |
| 28223 | /* 18221 */ "zero {za1.s}\0" |
| 28224 | /* 18234 */ "zero {za2.s}\0" |
| 28225 | /* 18247 */ "zero {za3.s}\0" |
| 28226 | /* 18260 */ "zero {za0.s,za1.s}\0" |
| 28227 | /* 18279 */ "zero {za0.s,za3.s}\0" |
| 28228 | /* 18298 */ "zero {za1.s,za2.s}\0" |
| 28229 | /* 18317 */ "zero {za2.s,za3.s}\0" |
| 28230 | /* 18336 */ "zero {za0.s,za1.s,za2.s}\0" |
| 28231 | /* 18361 */ "zero {za0.s,za1.s,za3.s}\0" |
| 28232 | /* 18386 */ "zero {za0.s,za2.s,za3.s}\0" |
| 28233 | /* 18411 */ "zero {za1.s,za2.s,za3.s}\0" |
| 28234 | ; |
| 28235 | |
| 28236 | #ifndef NDEBUG |
| 28237 | static struct SortCheck { |
| 28238 | SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| 28239 | assert(std::is_sorted( |
| 28240 | OpToPatterns.begin(), OpToPatterns.end(), |
| 28241 | [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| 28242 | return L.Opcode < R.Opcode; |
| 28243 | }) && |
| 28244 | "tablegen failed to sort opcode patterns"); |
| 28245 | } |
| 28246 | } sortCheckVar(OpToPatterns); |
| 28247 | #endif |
| 28248 | |
| 28249 | AliasMatchingData M { |
| 28250 | .OpToPatterns: ArrayRef(OpToPatterns), |
| 28251 | .Patterns: ArrayRef(Patterns), |
| 28252 | .PatternConds: ArrayRef(Conds), |
| 28253 | .AsmStrings: StringRef(AsmStrings, std::size(AsmStrings)), |
| 28254 | .ValidateMCOperand: &AArch64InstPrinterValidateMCOperand, |
| 28255 | }; |
| 28256 | const char *AsmString = matchAliasPatterns(MI, STI: &STI, M); |
| 28257 | if (!AsmString) return false; |
| 28258 | |
| 28259 | unsigned I = 0; |
| 28260 | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| 28261 | AsmString[I] != '$' && AsmString[I] != '\0') |
| 28262 | ++I; |
| 28263 | OS << '\t' << StringRef(AsmString, I); |
| 28264 | if (AsmString[I] != '\0') { |
| 28265 | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| 28266 | OS << '\t'; |
| 28267 | ++I; |
| 28268 | } |
| 28269 | do { |
| 28270 | if (AsmString[I] == '$') { |
| 28271 | ++I; |
| 28272 | if (AsmString[I] == (char)0xff) { |
| 28273 | ++I; |
| 28274 | int OpIdx = AsmString[I++] - 1; |
| 28275 | int PrintMethodIdx = AsmString[I++] - 1; |
| 28276 | printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, O&: OS); |
| 28277 | } else |
| 28278 | printOperand(MI, OpNo: unsigned(AsmString[I++]) - 1, STI, O&: OS); |
| 28279 | } else { |
| 28280 | OS << AsmString[I++]; |
| 28281 | } |
| 28282 | } while (AsmString[I] != '\0'); |
| 28283 | } |
| 28284 | |
| 28285 | return true; |
| 28286 | } |
| 28287 | |
| 28288 | void AArch64InstPrinter::printCustomAliasOperand( |
| 28289 | const MCInst *MI, uint64_t Address, unsigned OpIdx, |
| 28290 | unsigned PrintMethodIdx, |
| 28291 | const MCSubtargetInfo &STI, |
| 28292 | raw_ostream &OS) { |
| 28293 | switch (PrintMethodIdx) { |
| 28294 | default: |
| 28295 | llvm_unreachable("Unknown PrintMethod kind"); |
| 28296 | break; |
| 28297 | case 0: |
| 28298 | printAddSubImm(MI, OpNum: OpIdx, STI, O&: OS); |
| 28299 | break; |
| 28300 | case 1: |
| 28301 | printShifter(MI, OpNum: OpIdx, STI, O&: OS); |
| 28302 | break; |
| 28303 | case 2: |
| 28304 | printArithExtend(MI, OpNum: OpIdx, STI, O&: OS); |
| 28305 | break; |
| 28306 | case 3: |
| 28307 | printLogicalImm<int32_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28308 | break; |
| 28309 | case 4: |
| 28310 | printLogicalImm<int64_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28311 | break; |
| 28312 | case 5: |
| 28313 | printSVERegOp<'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28314 | break; |
| 28315 | case 6: |
| 28316 | printSVERegOp<>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28317 | break; |
| 28318 | case 7: |
| 28319 | printLogicalImm<int8_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28320 | break; |
| 28321 | case 8: |
| 28322 | printSVERegOp<'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28323 | break; |
| 28324 | case 9: |
| 28325 | printLogicalImm<int16_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28326 | break; |
| 28327 | case 10: |
| 28328 | printSVERegOp<'s'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28329 | break; |
| 28330 | case 11: |
| 28331 | printVRegOperand(MI, OpNo: OpIdx, STI, O&: OS); |
| 28332 | break; |
| 28333 | case 12: |
| 28334 | printImm(MI, OpNo: OpIdx, STI, O&: OS); |
| 28335 | break; |
| 28336 | case 13: |
| 28337 | printSVEPattern(MI, OpNum: OpIdx, STI, O&: OS); |
| 28338 | break; |
| 28339 | case 14: |
| 28340 | printImm8OptLsl<int8_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28341 | break; |
| 28342 | case 15: |
| 28343 | printSVERegOp<'d'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28344 | break; |
| 28345 | case 16: |
| 28346 | printImm8OptLsl<int64_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28347 | break; |
| 28348 | case 17: |
| 28349 | printImm8OptLsl<int16_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28350 | break; |
| 28351 | case 18: |
| 28352 | printImm8OptLsl<int32_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28353 | break; |
| 28354 | case 19: |
| 28355 | printInverseCondCode(MI, OpNum: OpIdx, STI, O&: OS); |
| 28356 | break; |
| 28357 | case 20: |
| 28358 | printSVELogicalImm<int16_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28359 | break; |
| 28360 | case 21: |
| 28361 | printSVELogicalImm<int32_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28362 | break; |
| 28363 | case 22: |
| 28364 | printSVELogicalImm<int64_t>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28365 | break; |
| 28366 | case 23: |
| 28367 | printZPRasFPR<8>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28368 | break; |
| 28369 | case 24: |
| 28370 | printVectorIndex(MI, OpNum: OpIdx, STI, O&: OS); |
| 28371 | break; |
| 28372 | case 25: |
| 28373 | printZPRasFPR<64>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28374 | break; |
| 28375 | case 26: |
| 28376 | printZPRasFPR<16>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28377 | break; |
| 28378 | case 27: |
| 28379 | printSVERegOp<'q'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28380 | break; |
| 28381 | case 28: |
| 28382 | printZPRasFPR<128>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28383 | break; |
| 28384 | case 29: |
| 28385 | printZPRasFPR<32>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28386 | break; |
| 28387 | case 30: |
| 28388 | printMatrixTileVector<0>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28389 | break; |
| 28390 | case 31: |
| 28391 | printMatrixIndex(MI, OpNum: OpIdx, STI, O&: OS); |
| 28392 | break; |
| 28393 | case 32: |
| 28394 | printMatrixTileVector<1>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28395 | break; |
| 28396 | case 33: |
| 28397 | printFPImmOperand(MI, OpNum: OpIdx, STI, O&: OS); |
| 28398 | break; |
| 28399 | case 34: |
| 28400 | printTypedVectorList<0,'d'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28401 | break; |
| 28402 | case 35: |
| 28403 | printTypedVectorList<0,'s'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28404 | break; |
| 28405 | case 36: |
| 28406 | printTypedVectorList<0,'q'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28407 | break; |
| 28408 | case 37: |
| 28409 | printTypedVectorList<0,'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28410 | break; |
| 28411 | case 38: |
| 28412 | printPredicateAsCounter<0>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28413 | break; |
| 28414 | case 39: |
| 28415 | printTypedVectorList<0, 'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28416 | break; |
| 28417 | case 40: |
| 28418 | printTypedVectorList<0,'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28419 | break; |
| 28420 | case 41: |
| 28421 | printTypedVectorList<16, 'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28422 | break; |
| 28423 | case 42: |
| 28424 | printTypedVectorList<1, 'd'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28425 | break; |
| 28426 | case 43: |
| 28427 | printTypedVectorList<2, 'd'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28428 | break; |
| 28429 | case 44: |
| 28430 | printTypedVectorList<2, 's'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28431 | break; |
| 28432 | case 45: |
| 28433 | printTypedVectorList<4, 'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28434 | break; |
| 28435 | case 46: |
| 28436 | printTypedVectorList<4, 's'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28437 | break; |
| 28438 | case 47: |
| 28439 | printTypedVectorList<8, 'b'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28440 | break; |
| 28441 | case 48: |
| 28442 | printTypedVectorList<8, 'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28443 | break; |
| 28444 | case 49: |
| 28445 | printTypedVectorList<0, 'h'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28446 | break; |
| 28447 | case 50: |
| 28448 | printTypedVectorList<0, 's'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28449 | break; |
| 28450 | case 51: |
| 28451 | printTypedVectorList<0, 'd'>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28452 | break; |
| 28453 | case 52: |
| 28454 | printMatrix<0>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28455 | break; |
| 28456 | case 53: |
| 28457 | printImmRangeScale<2, 1>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28458 | break; |
| 28459 | case 54: |
| 28460 | printImmRangeScale<4, 3>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28461 | break; |
| 28462 | case 55: |
| 28463 | printMatrix<64>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28464 | break; |
| 28465 | case 56: |
| 28466 | printImmHex(MI, OpNo: OpIdx, STI, O&: OS); |
| 28467 | break; |
| 28468 | case 57: |
| 28469 | printPrefetchOp<true>(MI, OpNum: OpIdx, STI, O&: OS); |
| 28470 | break; |
| 28471 | case 58: |
| 28472 | printPrefetchOp(MI, OpNum: OpIdx, STI, O&: OS); |
| 28473 | break; |
| 28474 | case 59: |
| 28475 | printGPR64as32(MI, OpNum: OpIdx, STI, O&: OS); |
| 28476 | break; |
| 28477 | case 60: |
| 28478 | printSysCROperand(MI, OpNo: OpIdx, STI, O&: OS); |
| 28479 | break; |
| 28480 | } |
| 28481 | } |
| 28482 | |
| 28483 | static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp, |
| 28484 | const MCSubtargetInfo &STI, |
| 28485 | unsigned PredicateIndex) { |
| 28486 | switch (PredicateIndex) { |
| 28487 | default: |
| 28488 | llvm_unreachable("Unknown MCOperandPredicate kind"); |
| 28489 | break; |
| 28490 | case 1: { |
| 28491 | |
| 28492 | if (!MCOp.isImm()) |
| 28493 | return false; |
| 28494 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 28495 | return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Imm: Val); |
| 28496 | |
| 28497 | } |
| 28498 | case 2: { |
| 28499 | |
| 28500 | if (!MCOp.isImm()) |
| 28501 | return false; |
| 28502 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 28503 | return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Imm: Val); |
| 28504 | |
| 28505 | } |
| 28506 | case 3: { |
| 28507 | |
| 28508 | if (!MCOp.isImm()) |
| 28509 | return false; |
| 28510 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 28511 | return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Imm: Val); |
| 28512 | |
| 28513 | } |
| 28514 | case 4: { |
| 28515 | |
| 28516 | return MCOp.isImm() && |
| 28517 | MCOp.getImm() != AArch64CC::AL && |
| 28518 | MCOp.getImm() != AArch64CC::NV; |
| 28519 | |
| 28520 | } |
| 28521 | case 5: { |
| 28522 | |
| 28523 | if (!MCOp.isImm()) |
| 28524 | return false; |
| 28525 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 28526 | return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Imm: Val) && |
| 28527 | AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Imm: Val); |
| 28528 | |
| 28529 | } |
| 28530 | case 6: { |
| 28531 | |
| 28532 | if (!MCOp.isImm()) |
| 28533 | return false; |
| 28534 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 28535 | return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Imm: Val) && |
| 28536 | AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Imm: Val); |
| 28537 | |
| 28538 | } |
| 28539 | case 7: { |
| 28540 | |
| 28541 | if (!MCOp.isImm()) |
| 28542 | return false; |
| 28543 | int64_t Val = AArch64_AM::decodeLogicalImmediate(val: MCOp.getImm(), regSize: 64); |
| 28544 | return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Imm: Val) && |
| 28545 | AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Imm: Val); |
| 28546 | |
| 28547 | } |
| 28548 | case 8: { |
| 28549 | return MCOp.isImm() && isUInt<5>(x: MCOp.getImm()); |
| 28550 | } |
| 28551 | } |
| 28552 | } |
| 28553 | |
| 28554 | #endif // PRINT_ALIAS_INSTR |
| 28555 |
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