1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<29, 428, 739, 54, 13, 19> HexagonMCRegisterClassStorage;
12
13static const MVT::SimpleValueType HexagonVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
16 /* 10 */ MVT::i64, MVT::Other,
17 /* 12 */ MVT::v64i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
18 /* 17 */ MVT::v128i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
19 /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
20 /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
21 /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v32f16, MVT::v32bf16, MVT::v16f32, MVT::Other,
22 /* 40 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v64f16, MVT::v64bf16, MVT::v32f32, MVT::Other,
23 /* 47 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v128f16, MVT::v128bf16, MVT::v64f32, MVT::Other,
24 /* 54 */ MVT::Untyped, MVT::Other,
25};
26
27#ifdef __GNUC__
28#pragma GCC diagnostic push
29#pragma GCC diagnostic ignored "-Woverlength-strings"
30#endif
31static constexpr char HexagonSubRegIndexStrings[] = {
32 /* 0 */ "vsub_fake\000"
33 /* 10 */ "isub_hi\000"
34 /* 18 */ "wsub_hi_then_vsub_hi\000"
35 /* 39 */ "wsub_hi\000"
36 /* 47 */ "isub_lo\000"
37 /* 55 */ "wsub_hi_then_vsub_lo\000"
38 /* 76 */ "wsub_lo\000"
39 /* 84 */ "subreg_overflow\000"
40};
41#ifdef __GNUC__
42#pragma GCC diagnostic pop
43#endif
44
45
46static constexpr uint32_t HexagonSubRegIndexNameOffsets[] = {
47 10,
48 47,
49 84,
50 0,
51 31,
52 68,
53 39,
54 76,
55 18,
56 55,
57};
58
59static const TargetRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRangeTable[] = {
60 { .Offset: 4294967295, .Size: 4294967295 },
61 { .Offset: 32, .Size: 32 }, // isub_hi
62 { .Offset: 0, .Size: 32 }, // isub_lo
63 { .Offset: 0, .Size: 1 }, // subreg_overflow
64 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_fake
65 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_hi
66 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_lo
67 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi
68 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_lo
69 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_hi
70 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_lo
71 { .Offset: 4294967295, .Size: 4294967295 },
72 { .Offset: 32, .Size: 32 }, // isub_hi
73 { .Offset: 0, .Size: 32 }, // isub_lo
74 { .Offset: 0, .Size: 1 }, // subreg_overflow
75 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_fake
76 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_hi
77 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_lo
78 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi
79 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_lo
80 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_hi
81 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_lo
82 { .Offset: 4294967295, .Size: 4294967295 },
83 { .Offset: 32, .Size: 32 }, // isub_hi
84 { .Offset: 0, .Size: 32 }, // isub_lo
85 { .Offset: 0, .Size: 1 }, // subreg_overflow
86 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_fake
87 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_hi
88 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_lo
89 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi
90 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_lo
91 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_hi
92 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_lo
93};
94
95
96static const LaneBitmask HexagonSubRegIndexLaneMaskTable[] = {
97 LaneBitmask::getAll(),
98 LaneBitmask(0x0000000000000001), // isub_hi
99 LaneBitmask(0x0000000000000002), // isub_lo
100 LaneBitmask(0x0000000000000004), // subreg_overflow
101 LaneBitmask(0x0000000000000008), // vsub_fake
102 LaneBitmask(0x0000000000000010), // vsub_hi
103 LaneBitmask(0x0000000000000020), // vsub_lo
104 LaneBitmask(0x00000000000000C0), // wsub_hi
105 LaneBitmask(0x0000000000000030), // wsub_lo
106 LaneBitmask(0x0000000000000040), // wsub_hi_then_vsub_hi
107 LaneBitmask(0x0000000000000080), // wsub_hi_then_vsub_lo
108 };
109
110
111
112static const TargetRegisterInfo::RegClassInfo HexagonRegClassInfos[] = {
113 // Mode = 0 (DefaultMode)
114 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*HexagonVTLists+*/.VTListOffset: 0 }, // UsrBits
115 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // SysRegs
116 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GuestRegs
117 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 22 }, // IntRegs
118 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs
119 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // IntRegsLow8
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 2 }, // PredRegs
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // ModRegs
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V65Regs
128 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // SysRegs64
129 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 27 }, // DoubleRegs
130 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GuestRegs64
131 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // VectRegRev
132 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64
133 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
134 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
135 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
136 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
137 { .RegSize: 64, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 12 }, // HvxQR
138 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR
139 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR_and_V65Regs
140 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR
141 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR_with_wsub_lo
142 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 54 }, // HvxVQR
143 // Mode = 1 (Hvx64)
144 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*HexagonVTLists+*/.VTListOffset: 0 }, // UsrBits
145 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // SysRegs
146 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GuestRegs
147 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 22 }, // IntRegs
148 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs
149 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
150 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs
151 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // IntRegsLow8
152 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
153 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 2 }, // PredRegs
154 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
155 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // ModRegs
156 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
157 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V65Regs
158 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // SysRegs64
159 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 27 }, // DoubleRegs
160 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GuestRegs64
161 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // VectRegRev
162 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64
163 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
164 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
165 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
166 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
167 { .RegSize: 64, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 12 }, // HvxQR
168 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR
169 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR_and_V65Regs
170 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR
171 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR_with_wsub_lo
172 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 54 }, // HvxVQR
173 // Mode = 2 (Hvx128)
174 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*HexagonVTLists+*/.VTListOffset: 0 }, // UsrBits
175 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // SysRegs
176 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GuestRegs
177 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 22 }, // IntRegs
178 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs
179 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
180 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs
181 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // IntRegsLow8
182 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
183 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 2 }, // PredRegs
184 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
185 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // ModRegs
186 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
187 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V65Regs
188 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // SysRegs64
189 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 27 }, // DoubleRegs
190 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GuestRegs64
191 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // VectRegRev
192 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64
193 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
194 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
195 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
196 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
197 { .RegSize: 128, .SpillSize: 1024, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 17 }, // HvxQR
198 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxVR
199 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxVR_and_V65Regs
200 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 47 }, // HvxWR
201 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 47 }, // HvxWR_with_wsub_lo
202 { .RegSize: 4096, .SpillSize: 4096, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 54 }, // HvxVQR
203};
204
205static const uint8_t HexagonCostPerUseTable[] = {
2060, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
207
208
209static const bool HexagonInAllocatableClassTable[] = {
210false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
211
212
213static const TargetRegisterInfoDesc HexagonRegInfoDesc = { // Extra Descriptors
214.CostPerUse: HexagonCostPerUseTable, .NumCosts: 1, .InAllocatableClass: HexagonInAllocatableClassTable};
215
216unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
217 static const uint8_t RowMap[10] = {
218 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
219 };
220 static const uint8_t Rows[2][10] = {
221 { 0, 0, 0, 0, Hexagon::wsub_hi_then_vsub_hi, Hexagon::wsub_hi_then_vsub_lo, 0, 0, 0, 0, },
222 { 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, },
223 };
224
225 --IdxA; assert(IdxA < 10); (void) IdxA;
226 --IdxB; assert(IdxB < 10);
227 return Rows[RowMap[IdxA]][IdxB];
228}
229
230unsigned HexagonGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
231 static const uint8_t Table[10][10] = {
232 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, },
233 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, },
234 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, },
235 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, },
236 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, },
237 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, },
238 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, },
239 { 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, },
240 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, },
241 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, },
242 };
243
244 --IdxA; assert(IdxA < 10);
245 --IdxB; assert(IdxB < 10);
246 return Table[IdxA][IdxB];
247 }
248
249 struct MaskRolOp {
250 LaneBitmask Mask;
251 uint8_t RotateLeft;
252 };
253 static const MaskRolOp LaneMaskComposeSequences[] = {
254 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
255 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
256 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
257 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
258 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
259 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
260 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 12
261 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 7 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 14
262 };
263 static const uint8_t CompositeSequences[] = {
264 0, // to isub_hi
265 2, // to isub_lo
266 4, // to subreg_overflow
267 6, // to vsub_fake
268 8, // to vsub_hi
269 10, // to vsub_lo
270 4, // to wsub_hi
271 0, // to wsub_lo
272 12, // to wsub_hi_then_vsub_hi
273 14 // to wsub_hi_then_vsub_lo
274 };
275
276LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
277 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
278 LaneBitmask Result;
279 for (const MaskRolOp *Ops =
280 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
281 Ops->Mask.any(); ++Ops) {
282 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
283 if (unsigned S = Ops->RotateLeft)
284 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
285 else
286 Result |= LaneBitmask(M);
287 }
288 return Result;
289}
290
291LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
292 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
293 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
294 LaneBitmask Result;
295 for (const MaskRolOp *Ops =
296 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
297 Ops->Mask.any(); ++Ops) {
298 LaneBitmask::Type M = LaneMask.getAsInteger();
299 if (unsigned S = Ops->RotateLeft)
300 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
301 else
302 Result |= LaneBitmask(M);
303 }
304 return Result;
305}
306
307const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
308 static constexpr uint8_t Table[29][10] = {
309 { // UsrBits
310 0, // isub_hi
311 0, // isub_lo
312 0, // subreg_overflow
313 0, // vsub_fake
314 0, // vsub_hi
315 0, // vsub_lo
316 0, // wsub_hi
317 0, // wsub_lo
318 0, // wsub_hi_then_vsub_hi
319 0, // wsub_hi_then_vsub_lo
320 },
321 { // SysRegs
322 0, // isub_hi
323 0, // isub_lo
324 0, // subreg_overflow
325 0, // vsub_fake
326 0, // vsub_hi
327 0, // vsub_lo
328 0, // wsub_hi
329 0, // wsub_lo
330 0, // wsub_hi_then_vsub_hi
331 0, // wsub_hi_then_vsub_lo
332 },
333 { // GuestRegs
334 0, // isub_hi
335 0, // isub_lo
336 0, // subreg_overflow
337 0, // vsub_fake
338 0, // vsub_hi
339 0, // vsub_lo
340 0, // wsub_hi
341 0, // wsub_lo
342 0, // wsub_hi_then_vsub_hi
343 0, // wsub_hi_then_vsub_lo
344 },
345 { // IntRegs
346 0, // isub_hi
347 0, // isub_lo
348 0, // subreg_overflow
349 0, // vsub_fake
350 0, // vsub_hi
351 0, // vsub_lo
352 0, // wsub_hi
353 0, // wsub_lo
354 0, // wsub_hi_then_vsub_hi
355 0, // wsub_hi_then_vsub_lo
356 },
357 { // CtrRegs
358 0, // isub_hi
359 0, // isub_lo
360 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
361 0, // vsub_fake
362 0, // vsub_hi
363 0, // vsub_lo
364 0, // wsub_hi
365 0, // wsub_lo
366 0, // wsub_hi_then_vsub_hi
367 0, // wsub_hi_then_vsub_lo
368 },
369 { // GeneralSubRegs
370 0, // isub_hi
371 0, // isub_lo
372 0, // subreg_overflow
373 0, // vsub_fake
374 0, // vsub_hi
375 0, // vsub_lo
376 0, // wsub_hi
377 0, // wsub_lo
378 0, // wsub_hi_then_vsub_hi
379 0, // wsub_hi_then_vsub_lo
380 },
381 { // V62Regs
382 11, // isub_hi -> V62Regs_with_isub_hi
383 11, // isub_lo -> V62Regs_with_isub_hi
384 0, // subreg_overflow
385 0, // vsub_fake
386 0, // vsub_hi
387 0, // vsub_lo
388 0, // wsub_hi
389 0, // wsub_lo
390 0, // wsub_hi_then_vsub_hi
391 0, // wsub_hi_then_vsub_lo
392 },
393 { // IntRegsLow8
394 0, // isub_hi
395 0, // isub_lo
396 0, // subreg_overflow
397 0, // vsub_fake
398 0, // vsub_hi
399 0, // vsub_lo
400 0, // wsub_hi
401 0, // wsub_lo
402 0, // wsub_hi_then_vsub_hi
403 0, // wsub_hi_then_vsub_lo
404 },
405 { // CtrRegs_and_V62Regs
406 0, // isub_hi
407 0, // isub_lo
408 0, // subreg_overflow
409 0, // vsub_fake
410 0, // vsub_hi
411 0, // vsub_lo
412 0, // wsub_hi
413 0, // wsub_lo
414 0, // wsub_hi_then_vsub_hi
415 0, // wsub_hi_then_vsub_lo
416 },
417 { // PredRegs
418 0, // isub_hi
419 0, // isub_lo
420 0, // subreg_overflow
421 0, // vsub_fake
422 0, // vsub_hi
423 0, // vsub_lo
424 0, // wsub_hi
425 0, // wsub_lo
426 0, // wsub_hi_then_vsub_hi
427 0, // wsub_hi_then_vsub_lo
428 },
429 { // V62Regs_with_isub_hi
430 11, // isub_hi -> V62Regs_with_isub_hi
431 11, // isub_lo -> V62Regs_with_isub_hi
432 0, // subreg_overflow
433 0, // vsub_fake
434 0, // vsub_hi
435 0, // vsub_lo
436 0, // wsub_hi
437 0, // wsub_lo
438 0, // wsub_hi_then_vsub_hi
439 0, // wsub_hi_then_vsub_lo
440 },
441 { // ModRegs
442 0, // isub_hi
443 0, // isub_lo
444 0, // subreg_overflow
445 0, // vsub_fake
446 0, // vsub_hi
447 0, // vsub_lo
448 0, // wsub_hi
449 0, // wsub_lo
450 0, // wsub_hi_then_vsub_hi
451 0, // wsub_hi_then_vsub_lo
452 },
453 { // CtrRegs_with_subreg_overflow
454 0, // isub_hi
455 0, // isub_lo
456 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
457 0, // vsub_fake
458 0, // vsub_hi
459 0, // vsub_lo
460 0, // wsub_hi
461 0, // wsub_lo
462 0, // wsub_hi_then_vsub_hi
463 0, // wsub_hi_then_vsub_lo
464 },
465 { // V65Regs
466 0, // isub_hi
467 0, // isub_lo
468 0, // subreg_overflow
469 0, // vsub_fake
470 0, // vsub_hi
471 0, // vsub_lo
472 0, // wsub_hi
473 0, // wsub_lo
474 0, // wsub_hi_then_vsub_hi
475 0, // wsub_hi_then_vsub_lo
476 },
477 { // SysRegs64
478 15, // isub_hi -> SysRegs64
479 15, // isub_lo -> SysRegs64
480 0, // subreg_overflow
481 0, // vsub_fake
482 0, // vsub_hi
483 0, // vsub_lo
484 0, // wsub_hi
485 0, // wsub_lo
486 0, // wsub_hi_then_vsub_hi
487 0, // wsub_hi_then_vsub_lo
488 },
489 { // DoubleRegs
490 16, // isub_hi -> DoubleRegs
491 16, // isub_lo -> DoubleRegs
492 0, // subreg_overflow
493 0, // vsub_fake
494 0, // vsub_hi
495 0, // vsub_lo
496 0, // wsub_hi
497 0, // wsub_lo
498 0, // wsub_hi_then_vsub_hi
499 0, // wsub_hi_then_vsub_lo
500 },
501 { // GuestRegs64
502 17, // isub_hi -> GuestRegs64
503 17, // isub_lo -> GuestRegs64
504 0, // subreg_overflow
505 0, // vsub_fake
506 0, // vsub_hi
507 0, // vsub_lo
508 0, // wsub_hi
509 0, // wsub_lo
510 0, // wsub_hi_then_vsub_hi
511 0, // wsub_hi_then_vsub_lo
512 },
513 { // VectRegRev
514 0, // isub_hi
515 0, // isub_lo
516 0, // subreg_overflow
517 18, // vsub_fake -> VectRegRev
518 18, // vsub_hi -> VectRegRev
519 18, // vsub_lo -> VectRegRev
520 0, // wsub_hi
521 18, // wsub_lo -> VectRegRev
522 0, // wsub_hi_then_vsub_hi
523 0, // wsub_hi_then_vsub_lo
524 },
525 { // CtrRegs64
526 19, // isub_hi -> CtrRegs64
527 19, // isub_lo -> CtrRegs64
528 0, // subreg_overflow
529 0, // vsub_fake
530 0, // vsub_hi
531 0, // vsub_lo
532 0, // wsub_hi
533 0, // wsub_lo
534 0, // wsub_hi_then_vsub_hi
535 0, // wsub_hi_then_vsub_lo
536 },
537 { // GeneralDoubleLow8Regs
538 20, // isub_hi -> GeneralDoubleLow8Regs
539 20, // isub_lo -> GeneralDoubleLow8Regs
540 0, // subreg_overflow
541 0, // vsub_fake
542 0, // vsub_hi
543 0, // vsub_lo
544 0, // wsub_hi
545 0, // wsub_lo
546 0, // wsub_hi_then_vsub_hi
547 0, // wsub_hi_then_vsub_lo
548 },
549 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
550 21, // isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
551 21, // isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
552 0, // subreg_overflow
553 0, // vsub_fake
554 0, // vsub_hi
555 0, // vsub_lo
556 0, // wsub_hi
557 0, // wsub_lo
558 0, // wsub_hi_then_vsub_hi
559 0, // wsub_hi_then_vsub_lo
560 },
561 { // CtrRegs64_and_V62Regs
562 22, // isub_hi -> CtrRegs64_and_V62Regs
563 22, // isub_lo -> CtrRegs64_and_V62Regs
564 0, // subreg_overflow
565 0, // vsub_fake
566 0, // vsub_hi
567 0, // vsub_lo
568 0, // wsub_hi
569 0, // wsub_lo
570 0, // wsub_hi_then_vsub_hi
571 0, // wsub_hi_then_vsub_lo
572 },
573 { // CtrRegs64_with_isub_hi_in_ModRegs
574 23, // isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
575 23, // isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
576 0, // subreg_overflow
577 0, // vsub_fake
578 0, // vsub_hi
579 0, // vsub_lo
580 0, // wsub_hi
581 0, // wsub_lo
582 0, // wsub_hi_then_vsub_hi
583 0, // wsub_hi_then_vsub_lo
584 },
585 { // HvxQR
586 0, // isub_hi
587 0, // isub_lo
588 0, // subreg_overflow
589 0, // vsub_fake
590 0, // vsub_hi
591 0, // vsub_lo
592 0, // wsub_hi
593 0, // wsub_lo
594 0, // wsub_hi_then_vsub_hi
595 0, // wsub_hi_then_vsub_lo
596 },
597 { // HvxVR
598 0, // isub_hi
599 0, // isub_lo
600 0, // subreg_overflow
601 0, // vsub_fake
602 0, // vsub_hi
603 0, // vsub_lo
604 0, // wsub_hi
605 0, // wsub_lo
606 0, // wsub_hi_then_vsub_hi
607 0, // wsub_hi_then_vsub_lo
608 },
609 { // HvxVR_and_V65Regs
610 0, // isub_hi
611 0, // isub_lo
612 0, // subreg_overflow
613 0, // vsub_fake
614 0, // vsub_hi
615 0, // vsub_lo
616 0, // wsub_hi
617 0, // wsub_lo
618 0, // wsub_hi_then_vsub_hi
619 0, // wsub_hi_then_vsub_lo
620 },
621 { // HvxWR
622 0, // isub_hi
623 0, // isub_lo
624 0, // subreg_overflow
625 0, // vsub_fake
626 27, // vsub_hi -> HvxWR
627 27, // vsub_lo -> HvxWR
628 0, // wsub_hi
629 28, // wsub_lo -> HvxWR_with_wsub_lo
630 0, // wsub_hi_then_vsub_hi
631 0, // wsub_hi_then_vsub_lo
632 },
633 { // HvxWR_with_wsub_lo
634 0, // isub_hi
635 0, // isub_lo
636 0, // subreg_overflow
637 28, // vsub_fake -> HvxWR_with_wsub_lo
638 28, // vsub_hi -> HvxWR_with_wsub_lo
639 28, // vsub_lo -> HvxWR_with_wsub_lo
640 0, // wsub_hi
641 28, // wsub_lo -> HvxWR_with_wsub_lo
642 0, // wsub_hi_then_vsub_hi
643 0, // wsub_hi_then_vsub_lo
644 },
645 { // HvxVQR
646 0, // isub_hi
647 0, // isub_lo
648 0, // subreg_overflow
649 0, // vsub_fake
650 29, // vsub_hi -> HvxVQR
651 29, // vsub_lo -> HvxVQR
652 29, // wsub_hi -> HvxVQR
653 29, // wsub_lo -> HvxVQR
654 29, // wsub_hi_then_vsub_hi -> HvxVQR
655 29, // wsub_hi_then_vsub_lo -> HvxVQR
656 },
657
658 };
659 assert(RC && "Missing regclass");
660 if (!Idx) return RC;
661 --Idx;
662 assert(Idx < 10 && "Bad subreg");
663 unsigned TV = Table[RC->getID()][Idx];
664 return TV ? getRegClass(i: TV - 1) : nullptr;
665}const TargetRegisterClass *HexagonGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
666 static constexpr uint8_t Table[29][10] = {
667 { // UsrBits
668 0, // UsrBits:isub_hi
669 0, // UsrBits:isub_lo
670 0, // UsrBits:subreg_overflow
671 0, // UsrBits:vsub_fake
672 0, // UsrBits:vsub_hi
673 0, // UsrBits:vsub_lo
674 0, // UsrBits:wsub_hi
675 0, // UsrBits:wsub_lo
676 0, // UsrBits:wsub_hi_then_vsub_hi
677 0, // UsrBits:wsub_hi_then_vsub_lo
678 },
679 { // SysRegs
680 0, // SysRegs:isub_hi
681 0, // SysRegs:isub_lo
682 0, // SysRegs:subreg_overflow
683 0, // SysRegs:vsub_fake
684 0, // SysRegs:vsub_hi
685 0, // SysRegs:vsub_lo
686 0, // SysRegs:wsub_hi
687 0, // SysRegs:wsub_lo
688 0, // SysRegs:wsub_hi_then_vsub_hi
689 0, // SysRegs:wsub_hi_then_vsub_lo
690 },
691 { // GuestRegs
692 0, // GuestRegs:isub_hi
693 0, // GuestRegs:isub_lo
694 0, // GuestRegs:subreg_overflow
695 0, // GuestRegs:vsub_fake
696 0, // GuestRegs:vsub_hi
697 0, // GuestRegs:vsub_lo
698 0, // GuestRegs:wsub_hi
699 0, // GuestRegs:wsub_lo
700 0, // GuestRegs:wsub_hi_then_vsub_hi
701 0, // GuestRegs:wsub_hi_then_vsub_lo
702 },
703 { // IntRegs
704 0, // IntRegs:isub_hi
705 0, // IntRegs:isub_lo
706 0, // IntRegs:subreg_overflow
707 0, // IntRegs:vsub_fake
708 0, // IntRegs:vsub_hi
709 0, // IntRegs:vsub_lo
710 0, // IntRegs:wsub_hi
711 0, // IntRegs:wsub_lo
712 0, // IntRegs:wsub_hi_then_vsub_hi
713 0, // IntRegs:wsub_hi_then_vsub_lo
714 },
715 { // CtrRegs
716 0, // CtrRegs:isub_hi
717 0, // CtrRegs:isub_lo
718 1, // CtrRegs:subreg_overflow -> UsrBits
719 0, // CtrRegs:vsub_fake
720 0, // CtrRegs:vsub_hi
721 0, // CtrRegs:vsub_lo
722 0, // CtrRegs:wsub_hi
723 0, // CtrRegs:wsub_lo
724 0, // CtrRegs:wsub_hi_then_vsub_hi
725 0, // CtrRegs:wsub_hi_then_vsub_lo
726 },
727 { // GeneralSubRegs
728 0, // GeneralSubRegs:isub_hi
729 0, // GeneralSubRegs:isub_lo
730 0, // GeneralSubRegs:subreg_overflow
731 0, // GeneralSubRegs:vsub_fake
732 0, // GeneralSubRegs:vsub_hi
733 0, // GeneralSubRegs:vsub_lo
734 0, // GeneralSubRegs:wsub_hi
735 0, // GeneralSubRegs:wsub_lo
736 0, // GeneralSubRegs:wsub_hi_then_vsub_hi
737 0, // GeneralSubRegs:wsub_hi_then_vsub_lo
738 },
739 { // V62Regs
740 9, // V62Regs:isub_hi -> CtrRegs_and_V62Regs
741 9, // V62Regs:isub_lo -> CtrRegs_and_V62Regs
742 0, // V62Regs:subreg_overflow
743 0, // V62Regs:vsub_fake
744 0, // V62Regs:vsub_hi
745 0, // V62Regs:vsub_lo
746 0, // V62Regs:wsub_hi
747 0, // V62Regs:wsub_lo
748 0, // V62Regs:wsub_hi_then_vsub_hi
749 0, // V62Regs:wsub_hi_then_vsub_lo
750 },
751 { // IntRegsLow8
752 0, // IntRegsLow8:isub_hi
753 0, // IntRegsLow8:isub_lo
754 0, // IntRegsLow8:subreg_overflow
755 0, // IntRegsLow8:vsub_fake
756 0, // IntRegsLow8:vsub_hi
757 0, // IntRegsLow8:vsub_lo
758 0, // IntRegsLow8:wsub_hi
759 0, // IntRegsLow8:wsub_lo
760 0, // IntRegsLow8:wsub_hi_then_vsub_hi
761 0, // IntRegsLow8:wsub_hi_then_vsub_lo
762 },
763 { // CtrRegs_and_V62Regs
764 0, // CtrRegs_and_V62Regs:isub_hi
765 0, // CtrRegs_and_V62Regs:isub_lo
766 0, // CtrRegs_and_V62Regs:subreg_overflow
767 0, // CtrRegs_and_V62Regs:vsub_fake
768 0, // CtrRegs_and_V62Regs:vsub_hi
769 0, // CtrRegs_and_V62Regs:vsub_lo
770 0, // CtrRegs_and_V62Regs:wsub_hi
771 0, // CtrRegs_and_V62Regs:wsub_lo
772 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_hi
773 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_lo
774 },
775 { // PredRegs
776 0, // PredRegs:isub_hi
777 0, // PredRegs:isub_lo
778 0, // PredRegs:subreg_overflow
779 0, // PredRegs:vsub_fake
780 0, // PredRegs:vsub_hi
781 0, // PredRegs:vsub_lo
782 0, // PredRegs:wsub_hi
783 0, // PredRegs:wsub_lo
784 0, // PredRegs:wsub_hi_then_vsub_hi
785 0, // PredRegs:wsub_hi_then_vsub_lo
786 },
787 { // V62Regs_with_isub_hi
788 9, // V62Regs_with_isub_hi:isub_hi -> CtrRegs_and_V62Regs
789 9, // V62Regs_with_isub_hi:isub_lo -> CtrRegs_and_V62Regs
790 0, // V62Regs_with_isub_hi:subreg_overflow
791 0, // V62Regs_with_isub_hi:vsub_fake
792 0, // V62Regs_with_isub_hi:vsub_hi
793 0, // V62Regs_with_isub_hi:vsub_lo
794 0, // V62Regs_with_isub_hi:wsub_hi
795 0, // V62Regs_with_isub_hi:wsub_lo
796 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_hi
797 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_lo
798 },
799 { // ModRegs
800 0, // ModRegs:isub_hi
801 0, // ModRegs:isub_lo
802 0, // ModRegs:subreg_overflow
803 0, // ModRegs:vsub_fake
804 0, // ModRegs:vsub_hi
805 0, // ModRegs:vsub_lo
806 0, // ModRegs:wsub_hi
807 0, // ModRegs:wsub_lo
808 0, // ModRegs:wsub_hi_then_vsub_hi
809 0, // ModRegs:wsub_hi_then_vsub_lo
810 },
811 { // CtrRegs_with_subreg_overflow
812 0, // CtrRegs_with_subreg_overflow:isub_hi
813 0, // CtrRegs_with_subreg_overflow:isub_lo
814 1, // CtrRegs_with_subreg_overflow:subreg_overflow -> UsrBits
815 0, // CtrRegs_with_subreg_overflow:vsub_fake
816 0, // CtrRegs_with_subreg_overflow:vsub_hi
817 0, // CtrRegs_with_subreg_overflow:vsub_lo
818 0, // CtrRegs_with_subreg_overflow:wsub_hi
819 0, // CtrRegs_with_subreg_overflow:wsub_lo
820 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_hi
821 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_lo
822 },
823 { // V65Regs
824 0, // V65Regs:isub_hi
825 0, // V65Regs:isub_lo
826 0, // V65Regs:subreg_overflow
827 0, // V65Regs:vsub_fake
828 0, // V65Regs:vsub_hi
829 0, // V65Regs:vsub_lo
830 0, // V65Regs:wsub_hi
831 0, // V65Regs:wsub_lo
832 0, // V65Regs:wsub_hi_then_vsub_hi
833 0, // V65Regs:wsub_hi_then_vsub_lo
834 },
835 { // SysRegs64
836 2, // SysRegs64:isub_hi -> SysRegs
837 2, // SysRegs64:isub_lo -> SysRegs
838 0, // SysRegs64:subreg_overflow
839 0, // SysRegs64:vsub_fake
840 0, // SysRegs64:vsub_hi
841 0, // SysRegs64:vsub_lo
842 0, // SysRegs64:wsub_hi
843 0, // SysRegs64:wsub_lo
844 0, // SysRegs64:wsub_hi_then_vsub_hi
845 0, // SysRegs64:wsub_hi_then_vsub_lo
846 },
847 { // DoubleRegs
848 4, // DoubleRegs:isub_hi -> IntRegs
849 4, // DoubleRegs:isub_lo -> IntRegs
850 0, // DoubleRegs:subreg_overflow
851 0, // DoubleRegs:vsub_fake
852 0, // DoubleRegs:vsub_hi
853 0, // DoubleRegs:vsub_lo
854 0, // DoubleRegs:wsub_hi
855 0, // DoubleRegs:wsub_lo
856 0, // DoubleRegs:wsub_hi_then_vsub_hi
857 0, // DoubleRegs:wsub_hi_then_vsub_lo
858 },
859 { // GuestRegs64
860 3, // GuestRegs64:isub_hi -> GuestRegs
861 3, // GuestRegs64:isub_lo -> GuestRegs
862 0, // GuestRegs64:subreg_overflow
863 0, // GuestRegs64:vsub_fake
864 0, // GuestRegs64:vsub_hi
865 0, // GuestRegs64:vsub_lo
866 0, // GuestRegs64:wsub_hi
867 0, // GuestRegs64:wsub_lo
868 0, // GuestRegs64:wsub_hi_then_vsub_hi
869 0, // GuestRegs64:wsub_hi_then_vsub_lo
870 },
871 { // VectRegRev
872 0, // VectRegRev:isub_hi
873 0, // VectRegRev:isub_lo
874 0, // VectRegRev:subreg_overflow
875 0, // VectRegRev:vsub_fake
876 25, // VectRegRev:vsub_hi -> HvxVR
877 25, // VectRegRev:vsub_lo -> HvxVR
878 0, // VectRegRev:wsub_hi
879 27, // VectRegRev:wsub_lo -> HvxWR
880 0, // VectRegRev:wsub_hi_then_vsub_hi
881 0, // VectRegRev:wsub_hi_then_vsub_lo
882 },
883 { // CtrRegs64
884 5, // CtrRegs64:isub_hi -> CtrRegs
885 5, // CtrRegs64:isub_lo -> CtrRegs
886 0, // CtrRegs64:subreg_overflow
887 0, // CtrRegs64:vsub_fake
888 0, // CtrRegs64:vsub_hi
889 0, // CtrRegs64:vsub_lo
890 0, // CtrRegs64:wsub_hi
891 0, // CtrRegs64:wsub_lo
892 0, // CtrRegs64:wsub_hi_then_vsub_hi
893 0, // CtrRegs64:wsub_hi_then_vsub_lo
894 },
895 { // GeneralDoubleLow8Regs
896 6, // GeneralDoubleLow8Regs:isub_hi -> GeneralSubRegs
897 6, // GeneralDoubleLow8Regs:isub_lo -> GeneralSubRegs
898 0, // GeneralDoubleLow8Regs:subreg_overflow
899 0, // GeneralDoubleLow8Regs:vsub_fake
900 0, // GeneralDoubleLow8Regs:vsub_hi
901 0, // GeneralDoubleLow8Regs:vsub_lo
902 0, // GeneralDoubleLow8Regs:wsub_hi
903 0, // GeneralDoubleLow8Regs:wsub_lo
904 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_hi
905 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_lo
906 },
907 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
908 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_hi -> IntRegsLow8
909 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_lo -> IntRegsLow8
910 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:subreg_overflow
911 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_fake
912 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_hi
913 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_lo
914 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi
915 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_lo
916 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_hi
917 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_lo
918 },
919 { // CtrRegs64_and_V62Regs
920 9, // CtrRegs64_and_V62Regs:isub_hi -> CtrRegs_and_V62Regs
921 9, // CtrRegs64_and_V62Regs:isub_lo -> CtrRegs_and_V62Regs
922 0, // CtrRegs64_and_V62Regs:subreg_overflow
923 0, // CtrRegs64_and_V62Regs:vsub_fake
924 0, // CtrRegs64_and_V62Regs:vsub_hi
925 0, // CtrRegs64_and_V62Regs:vsub_lo
926 0, // CtrRegs64_and_V62Regs:wsub_hi
927 0, // CtrRegs64_and_V62Regs:wsub_lo
928 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_hi
929 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_lo
930 },
931 { // CtrRegs64_with_isub_hi_in_ModRegs
932 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_hi -> ModRegs
933 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_lo -> ModRegs
934 0, // CtrRegs64_with_isub_hi_in_ModRegs:subreg_overflow
935 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_fake
936 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_hi
937 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_lo
938 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi
939 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_lo
940 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_hi
941 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_lo
942 },
943 { // HvxQR
944 0, // HvxQR:isub_hi
945 0, // HvxQR:isub_lo
946 0, // HvxQR:subreg_overflow
947 0, // HvxQR:vsub_fake
948 0, // HvxQR:vsub_hi
949 0, // HvxQR:vsub_lo
950 0, // HvxQR:wsub_hi
951 0, // HvxQR:wsub_lo
952 0, // HvxQR:wsub_hi_then_vsub_hi
953 0, // HvxQR:wsub_hi_then_vsub_lo
954 },
955 { // HvxVR
956 0, // HvxVR:isub_hi
957 0, // HvxVR:isub_lo
958 0, // HvxVR:subreg_overflow
959 0, // HvxVR:vsub_fake
960 0, // HvxVR:vsub_hi
961 0, // HvxVR:vsub_lo
962 0, // HvxVR:wsub_hi
963 0, // HvxVR:wsub_lo
964 0, // HvxVR:wsub_hi_then_vsub_hi
965 0, // HvxVR:wsub_hi_then_vsub_lo
966 },
967 { // HvxVR_and_V65Regs
968 0, // HvxVR_and_V65Regs:isub_hi
969 0, // HvxVR_and_V65Regs:isub_lo
970 0, // HvxVR_and_V65Regs:subreg_overflow
971 0, // HvxVR_and_V65Regs:vsub_fake
972 0, // HvxVR_and_V65Regs:vsub_hi
973 0, // HvxVR_and_V65Regs:vsub_lo
974 0, // HvxVR_and_V65Regs:wsub_hi
975 0, // HvxVR_and_V65Regs:wsub_lo
976 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_hi
977 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_lo
978 },
979 { // HvxWR
980 0, // HvxWR:isub_hi
981 0, // HvxWR:isub_lo
982 0, // HvxWR:subreg_overflow
983 0, // HvxWR:vsub_fake
984 25, // HvxWR:vsub_hi -> HvxVR
985 25, // HvxWR:vsub_lo -> HvxVR
986 0, // HvxWR:wsub_hi
987 27, // HvxWR:wsub_lo -> HvxWR
988 0, // HvxWR:wsub_hi_then_vsub_hi
989 0, // HvxWR:wsub_hi_then_vsub_lo
990 },
991 { // HvxWR_with_wsub_lo
992 0, // HvxWR_with_wsub_lo:isub_hi
993 0, // HvxWR_with_wsub_lo:isub_lo
994 0, // HvxWR_with_wsub_lo:subreg_overflow
995 0, // HvxWR_with_wsub_lo:vsub_fake
996 25, // HvxWR_with_wsub_lo:vsub_hi -> HvxVR
997 25, // HvxWR_with_wsub_lo:vsub_lo -> HvxVR
998 0, // HvxWR_with_wsub_lo:wsub_hi
999 27, // HvxWR_with_wsub_lo:wsub_lo -> HvxWR
1000 0, // HvxWR_with_wsub_lo:wsub_hi_then_vsub_hi
1001 0, // HvxWR_with_wsub_lo:wsub_hi_then_vsub_lo
1002 },
1003 { // HvxVQR
1004 0, // HvxVQR:isub_hi
1005 0, // HvxVQR:isub_lo
1006 0, // HvxVQR:subreg_overflow
1007 0, // HvxVQR:vsub_fake
1008 25, // HvxVQR:vsub_hi -> HvxVR
1009 25, // HvxVQR:vsub_lo -> HvxVR
1010 27, // HvxVQR:wsub_hi -> HvxWR
1011 27, // HvxVQR:wsub_lo -> HvxWR
1012 25, // HvxVQR:wsub_hi_then_vsub_hi -> HvxVR
1013 25, // HvxVQR:wsub_hi_then_vsub_lo -> HvxVR
1014 },
1015
1016 };
1017 assert(RC && "Missing regclass");
1018 if (!Idx) return RC;
1019 --Idx;
1020 assert(Idx < 10 && "Bad subreg");
1021 unsigned TV = Table[RC->getID()][Idx];
1022 return TV ? getRegClass(i: TV - 1) : nullptr;
1023}/// Get the weight in units of pressure for this register class.
1024const RegClassWeight &HexagonGenRegisterInfo::
1025getRegClassWeight(const TargetRegisterClass *RC) const {
1026 static const RegClassWeight RCWeightTable[] = {
1027 {.RegWeight: 0, .WeightLimit: 0}, // UsrBits
1028 {.RegWeight: 0, .WeightLimit: 0}, // SysRegs
1029 {.RegWeight: 0, .WeightLimit: 0}, // GuestRegs
1030 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
1031 {.RegWeight: 0, .WeightLimit: 6}, // CtrRegs
1032 {.RegWeight: 1, .WeightLimit: 16}, // GeneralSubRegs
1033 {.RegWeight: 0, .WeightLimit: 0}, // V62Regs
1034 {.RegWeight: 1, .WeightLimit: 8}, // IntRegsLow8
1035 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs_and_V62Regs
1036 {.RegWeight: 2, .WeightLimit: 8}, // PredRegs
1037 {.RegWeight: 0, .WeightLimit: 0}, // V62Regs_with_isub_hi
1038 {.RegWeight: 1, .WeightLimit: 2}, // ModRegs
1039 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs_with_subreg_overflow
1040 {.RegWeight: 1, .WeightLimit: 1}, // V65Regs
1041 {.RegWeight: 0, .WeightLimit: 0}, // SysRegs64
1042 {.RegWeight: 2, .WeightLimit: 32}, // DoubleRegs
1043 {.RegWeight: 0, .WeightLimit: 0}, // GuestRegs64
1044 {.RegWeight: 2, .WeightLimit: 32}, // VectRegRev
1045 {.RegWeight: 0, .WeightLimit: 6}, // CtrRegs64
1046 {.RegWeight: 2, .WeightLimit: 16}, // GeneralDoubleLow8Regs
1047 {.RegWeight: 2, .WeightLimit: 8}, // DoubleRegs_with_isub_hi_in_IntRegsLow8
1048 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs64_and_V62Regs
1049 {.RegWeight: 2, .WeightLimit: 2}, // CtrRegs64_with_isub_hi_in_ModRegs
1050 {.RegWeight: 1, .WeightLimit: 4}, // HvxQR
1051 {.RegWeight: 1, .WeightLimit: 33}, // HvxVR
1052 {.RegWeight: 1, .WeightLimit: 1}, // HvxVR_and_V65Regs
1053 {.RegWeight: 2, .WeightLimit: 32}, // HvxWR
1054 {.RegWeight: 2, .WeightLimit: 32}, // HvxWR_with_wsub_lo
1055 {.RegWeight: 4, .WeightLimit: 32}, // HvxVQR
1056 };
1057 return RCWeightTable[RC->getID()];
1058}
1059
1060/// Get the weight in units of pressure for this register unit.
1061unsigned HexagonGenRegisterInfo::
1062getRegUnitWeight(MCRegUnit RegUnit) const {
1063 assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
1064 // All register units have unit weight.
1065 return 1;
1066}
1067
1068
1069// Get the number of dimensions of register pressure.
1070unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
1071 return 8;
1072}
1073
1074// Get the name of this register unit pressure set.
1075const char *HexagonGenRegisterInfo::
1076getRegPressureSetName(unsigned Idx) const {
1077 static const char *PressureNameTable[] = {
1078 "HvxVR_and_V65Regs",
1079 "ModRegs",
1080 "HvxQR",
1081 "IntRegsLow8",
1082 "PredRegs",
1083 "GeneralSubRegs",
1084 "IntRegs",
1085 "HvxVR",
1086 };
1087 return PressureNameTable[Idx];
1088}
1089
1090// Get the register unit pressure limit for this dimension.
1091// This limit must be adjusted dynamically for reserved registers.
1092unsigned HexagonGenRegisterInfo::
1093getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1094 static const uint8_t PressureLimitTable[] = {
1095 1, // 0: HvxVR_and_V65Regs
1096 2, // 1: ModRegs
1097 4, // 2: HvxQR
1098 8, // 3: IntRegsLow8
1099 8, // 4: PredRegs
1100 16, // 5: GeneralSubRegs
1101 32, // 6: IntRegs
1102 33, // 7: HvxVR
1103 };
1104 return PressureLimitTable[Idx];
1105}
1106
1107/// Table of pressure sets per register class or unit.
1108static const int RCSetsTable[] = {
1109 /* 0 */ 1, -1,
1110 /* 2 */ 2, -1,
1111 /* 4 */ 4, -1,
1112 /* 6 */ 3, 5, 6, -1,
1113 /* 10 */ 0, 7, -1,
1114};
1115
1116/// Get the dimensions of register pressure impacted by this register class.
1117/// Returns a -1 terminated array of pressure set IDs
1118const int *HexagonGenRegisterInfo::
1119getRegClassPressureSets(const TargetRegisterClass *RC) const {
1120 static const uint8_t RCSetStartTable[] = {
1121 1,1,1,8,1,7,1,6,1,4,1,0,1,1,1,8,1,11,1,7,6,1,1,2,11,10,11,11,11,};
1122 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1123}
1124
1125/// Get the dimensions of register pressure impacted by this register unit.
1126/// Returns a -1 terminated array of pressure set IDs
1127const int *HexagonGenRegisterInfo::
1128getRegUnitPressureSets(MCRegUnit RegUnit) const {
1129 assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
1130 static const uint8_t RUSetStartTable[] = {
1131 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,4,4,4,4,4,4,4,4,1,1,1,1,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
1132 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1133}
1134
1135
1136// Register to minimal register class mapping
1137
1138const TargetRegisterClass *HexagonGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
1139 static const uint16_t InvalidRegClassID = UINT16_MAX;
1140
1141 static const uint16_t Mapping[398] = {
1142 InvalidRegClassID, // NoRegister
1143 Hexagon::SysRegsRegClassID, // BADVA
1144 Hexagon::SysRegsRegClassID, // CCR
1145 Hexagon::SysRegsRegClassID, // CFGBASE
1146 Hexagon::CtrRegs64RegClassID, // CS
1147 Hexagon::SysRegsRegClassID, // DIAG
1148 Hexagon::SysRegsRegClassID, // ELR
1149 Hexagon::SysRegsRegClassID, // EVB
1150 Hexagon::CtrRegs_and_V62RegsRegClassID, // FRAMEKEY
1151 Hexagon::CtrRegs_and_V62RegsRegClassID, // FRAMELIMIT
1152 Hexagon::GuestRegsRegClassID, // GELR
1153 Hexagon::GuestRegsRegClassID, // GOSP
1154 Hexagon::CtrRegsRegClassID, // GP
1155 Hexagon::GuestRegsRegClassID, // GPCYCLEHI
1156 Hexagon::GuestRegsRegClassID, // GPCYCLELO
1157 Hexagon::GuestRegsRegClassID, // GSR
1158 Hexagon::SysRegsRegClassID, // HTID
1159 Hexagon::SysRegsRegClassID, // IMASK
1160 Hexagon::SysRegsRegClassID, // ISDBEN
1161 Hexagon::SysRegsRegClassID, // ISDBGPR
1162 Hexagon::SysRegsRegClassID, // ISDBMBXIN
1163 Hexagon::SysRegsRegClassID, // ISDBMBXOUT
1164 Hexagon::SysRegsRegClassID, // ISDBST
1165 Hexagon::SysRegsRegClassID, // MODECTL
1166 Hexagon::CtrRegsRegClassID, // PC
1167 Hexagon::SysRegsRegClassID, // PCYCLEHI
1168 Hexagon::SysRegsRegClassID, // PCYCLELO
1169 Hexagon::CtrRegs64_and_V62RegsRegClassID, // PKTCOUNT
1170 Hexagon::CtrRegs_and_V62RegsRegClassID, // PKTCOUNTHI
1171 Hexagon::CtrRegs_and_V62RegsRegClassID, // PKTCOUNTLO
1172 Hexagon::SysRegsRegClassID, // PMUCFG
1173 Hexagon::SysRegsRegClassID, // PMUEVTCFG
1174 Hexagon::SysRegsRegClassID, // REV
1175 Hexagon::SysRegsRegClassID, // SSR
1176 Hexagon::SysRegsRegClassID, // STID
1177 Hexagon::SysRegsRegClassID, // SYSCFG
1178 Hexagon::CtrRegsRegClassID, // UGP
1179 Hexagon::CtrRegs64RegClassID, // UPCYCLE
1180 Hexagon::CtrRegsRegClassID, // UPCYCLEHI
1181 Hexagon::CtrRegsRegClassID, // UPCYCLELO
1182 Hexagon::CtrRegs_with_subreg_overflowRegClassID, // USR
1183 Hexagon::UsrBitsRegClassID, // USR_OVF
1184 Hexagon::CtrRegs64_and_V62RegsRegClassID, // UTIMER
1185 Hexagon::CtrRegs_and_V62RegsRegClassID, // UTIMERHI
1186 Hexagon::CtrRegs_and_V62RegsRegClassID, // UTIMERLO
1187 Hexagon::SysRegsRegClassID, // VID
1188 Hexagon::HvxVR_and_V65RegsRegClassID, // VTMP
1189 Hexagon::SysRegsRegClassID, // BADVA0
1190 Hexagon::SysRegsRegClassID, // BADVA1
1191 Hexagon::SysRegsRegClassID, // BRKPTCFG0
1192 Hexagon::SysRegsRegClassID, // BRKPTCFG1
1193 Hexagon::SysRegsRegClassID, // BRKPTPC0
1194 Hexagon::SysRegsRegClassID, // BRKPTPC1
1195 Hexagon::CtrRegsRegClassID, // C5
1196 Hexagon::CtrRegsRegClassID, // C8
1197 Hexagon::CtrRegsRegClassID, // CS0
1198 Hexagon::CtrRegsRegClassID, // CS1
1199 Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, // D0
1200 Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, // D1
1201 Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, // D2
1202 Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, // D3
1203 Hexagon::DoubleRegsRegClassID, // D4
1204 Hexagon::DoubleRegsRegClassID, // D5
1205 Hexagon::DoubleRegsRegClassID, // D6
1206 Hexagon::DoubleRegsRegClassID, // D7
1207 Hexagon::GeneralDoubleLow8RegsRegClassID, // D8
1208 Hexagon::GeneralDoubleLow8RegsRegClassID, // D9
1209 Hexagon::GeneralDoubleLow8RegsRegClassID, // D10
1210 Hexagon::GeneralDoubleLow8RegsRegClassID, // D11
1211 Hexagon::DoubleRegsRegClassID, // D12
1212 Hexagon::DoubleRegsRegClassID, // D13
1213 Hexagon::DoubleRegsRegClassID, // D14
1214 Hexagon::DoubleRegsRegClassID, // D15
1215 Hexagon::GuestRegsRegClassID, // G3
1216 Hexagon::GuestRegsRegClassID, // G4
1217 Hexagon::GuestRegsRegClassID, // G5
1218 Hexagon::GuestRegsRegClassID, // G6
1219 Hexagon::GuestRegsRegClassID, // G7
1220 Hexagon::GuestRegsRegClassID, // G8
1221 Hexagon::GuestRegsRegClassID, // G9
1222 Hexagon::GuestRegsRegClassID, // G10
1223 Hexagon::GuestRegsRegClassID, // G11
1224 Hexagon::GuestRegsRegClassID, // G12
1225 Hexagon::GuestRegsRegClassID, // G13
1226 Hexagon::GuestRegsRegClassID, // G14
1227 Hexagon::GuestRegsRegClassID, // G15
1228 Hexagon::GuestRegsRegClassID, // G20
1229 Hexagon::GuestRegsRegClassID, // G21
1230 Hexagon::GuestRegsRegClassID, // G22
1231 Hexagon::GuestRegsRegClassID, // G23
1232 Hexagon::GuestRegsRegClassID, // G30
1233 Hexagon::GuestRegsRegClassID, // G31
1234 Hexagon::GuestRegsRegClassID, // GPMUCNT0
1235 Hexagon::GuestRegsRegClassID, // GPMUCNT1
1236 Hexagon::GuestRegsRegClassID, // GPMUCNT2
1237 Hexagon::GuestRegsRegClassID, // GPMUCNT3
1238 Hexagon::GuestRegsRegClassID, // GPMUCNT4
1239 Hexagon::GuestRegsRegClassID, // GPMUCNT5
1240 Hexagon::GuestRegsRegClassID, // GPMUCNT6
1241 Hexagon::GuestRegsRegClassID, // GPMUCNT7
1242 Hexagon::SysRegsRegClassID, // ISDBCFG0
1243 Hexagon::SysRegsRegClassID, // ISDBCFG1
1244 Hexagon::CtrRegsRegClassID, // LC0
1245 Hexagon::CtrRegsRegClassID, // LC1
1246 Hexagon::ModRegsRegClassID, // M0
1247 Hexagon::ModRegsRegClassID, // M1
1248 Hexagon::PredRegsRegClassID, // P0
1249 Hexagon::PredRegsRegClassID, // P1
1250 Hexagon::PredRegsRegClassID, // P2
1251 Hexagon::PredRegsRegClassID, // P3
1252 Hexagon::SysRegsRegClassID, // PMUCNT0
1253 Hexagon::SysRegsRegClassID, // PMUCNT1
1254 Hexagon::SysRegsRegClassID, // PMUCNT2
1255 Hexagon::SysRegsRegClassID, // PMUCNT3
1256 Hexagon::HvxQRRegClassID, // Q0
1257 Hexagon::HvxQRRegClassID, // Q1
1258 Hexagon::HvxQRRegClassID, // Q2
1259 Hexagon::HvxQRRegClassID, // Q3
1260 Hexagon::IntRegsLow8RegClassID, // R0
1261 Hexagon::IntRegsLow8RegClassID, // R1
1262 Hexagon::IntRegsLow8RegClassID, // R2
1263 Hexagon::IntRegsLow8RegClassID, // R3
1264 Hexagon::IntRegsLow8RegClassID, // R4
1265 Hexagon::IntRegsLow8RegClassID, // R5
1266 Hexagon::IntRegsLow8RegClassID, // R6
1267 Hexagon::IntRegsLow8RegClassID, // R7
1268 Hexagon::IntRegsRegClassID, // R8
1269 Hexagon::IntRegsRegClassID, // R9
1270 Hexagon::IntRegsRegClassID, // R10
1271 Hexagon::IntRegsRegClassID, // R11
1272 Hexagon::IntRegsRegClassID, // R12
1273 Hexagon::IntRegsRegClassID, // R13
1274 Hexagon::IntRegsRegClassID, // R14
1275 Hexagon::IntRegsRegClassID, // R15
1276 Hexagon::GeneralSubRegsRegClassID, // R16
1277 Hexagon::GeneralSubRegsRegClassID, // R17
1278 Hexagon::GeneralSubRegsRegClassID, // R18
1279 Hexagon::GeneralSubRegsRegClassID, // R19
1280 Hexagon::GeneralSubRegsRegClassID, // R20
1281 Hexagon::GeneralSubRegsRegClassID, // R21
1282 Hexagon::GeneralSubRegsRegClassID, // R22
1283 Hexagon::GeneralSubRegsRegClassID, // R23
1284 Hexagon::IntRegsRegClassID, // R24
1285 Hexagon::IntRegsRegClassID, // R25
1286 Hexagon::IntRegsRegClassID, // R26
1287 Hexagon::IntRegsRegClassID, // R27
1288 Hexagon::IntRegsRegClassID, // R28
1289 Hexagon::IntRegsRegClassID, // R29
1290 Hexagon::IntRegsRegClassID, // R30
1291 Hexagon::IntRegsRegClassID, // R31
1292 Hexagon::SysRegsRegClassID, // S11
1293 Hexagon::SysRegsRegClassID, // S12
1294 Hexagon::SysRegsRegClassID, // S13
1295 Hexagon::SysRegsRegClassID, // S14
1296 Hexagon::SysRegsRegClassID, // S15
1297 Hexagon::SysRegsRegClassID, // S19
1298 Hexagon::SysRegsRegClassID, // S20
1299 Hexagon::SysRegsRegClassID, // S22
1300 Hexagon::SysRegsRegClassID, // S23
1301 Hexagon::SysRegsRegClassID, // S24
1302 Hexagon::SysRegsRegClassID, // S25
1303 Hexagon::SysRegsRegClassID, // S26
1304 Hexagon::SysRegsRegClassID, // S35
1305 Hexagon::SysRegsRegClassID, // S44
1306 Hexagon::SysRegsRegClassID, // S45
1307 Hexagon::SysRegsRegClassID, // S46
1308 Hexagon::SysRegsRegClassID, // S47
1309 Hexagon::SysRegsRegClassID, // S54
1310 Hexagon::SysRegsRegClassID, // S55
1311 Hexagon::SysRegsRegClassID, // S56
1312 Hexagon::SysRegsRegClassID, // S57
1313 Hexagon::SysRegsRegClassID, // S58
1314 Hexagon::SysRegsRegClassID, // S59
1315 Hexagon::SysRegsRegClassID, // S60
1316 Hexagon::SysRegsRegClassID, // S61
1317 Hexagon::SysRegsRegClassID, // S62
1318 Hexagon::SysRegsRegClassID, // S63
1319 Hexagon::SysRegsRegClassID, // S64
1320 Hexagon::SysRegsRegClassID, // S65
1321 Hexagon::SysRegsRegClassID, // S66
1322 Hexagon::SysRegsRegClassID, // S67
1323 Hexagon::SysRegsRegClassID, // S68
1324 Hexagon::SysRegsRegClassID, // S69
1325 Hexagon::SysRegsRegClassID, // S70
1326 Hexagon::SysRegsRegClassID, // S71
1327 Hexagon::SysRegsRegClassID, // S72
1328 Hexagon::SysRegsRegClassID, // S73
1329 Hexagon::SysRegsRegClassID, // S74
1330 Hexagon::SysRegsRegClassID, // S75
1331 Hexagon::SysRegsRegClassID, // S76
1332 Hexagon::SysRegsRegClassID, // S77
1333 Hexagon::SysRegsRegClassID, // S78
1334 Hexagon::SysRegsRegClassID, // S79
1335 Hexagon::SysRegsRegClassID, // S80
1336 Hexagon::CtrRegsRegClassID, // SA0
1337 Hexagon::CtrRegsRegClassID, // SA1
1338 Hexagon::SysRegsRegClassID, // SGP0
1339 Hexagon::SysRegsRegClassID, // SGP1
1340 Hexagon::HvxVRRegClassID, // V0
1341 Hexagon::HvxVRRegClassID, // V1
1342 Hexagon::HvxVRRegClassID, // V2
1343 Hexagon::HvxVRRegClassID, // V3
1344 Hexagon::HvxVRRegClassID, // V4
1345 Hexagon::HvxVRRegClassID, // V5
1346 Hexagon::HvxVRRegClassID, // V6
1347 Hexagon::HvxVRRegClassID, // V7
1348 Hexagon::HvxVRRegClassID, // V8
1349 Hexagon::HvxVRRegClassID, // V9
1350 Hexagon::HvxVRRegClassID, // V10
1351 Hexagon::HvxVRRegClassID, // V11
1352 Hexagon::HvxVRRegClassID, // V12
1353 Hexagon::HvxVRRegClassID, // V13
1354 Hexagon::HvxVRRegClassID, // V14
1355 Hexagon::HvxVRRegClassID, // V15
1356 Hexagon::HvxVRRegClassID, // V16
1357 Hexagon::HvxVRRegClassID, // V17
1358 Hexagon::HvxVRRegClassID, // V18
1359 Hexagon::HvxVRRegClassID, // V19
1360 Hexagon::HvxVRRegClassID, // V20
1361 Hexagon::HvxVRRegClassID, // V21
1362 Hexagon::HvxVRRegClassID, // V22
1363 Hexagon::HvxVRRegClassID, // V23
1364 Hexagon::HvxVRRegClassID, // V24
1365 Hexagon::HvxVRRegClassID, // V25
1366 Hexagon::HvxVRRegClassID, // V26
1367 Hexagon::HvxVRRegClassID, // V27
1368 Hexagon::HvxVRRegClassID, // V28
1369 Hexagon::HvxVRRegClassID, // V29
1370 Hexagon::HvxVRRegClassID, // V30
1371 Hexagon::HvxVRRegClassID, // V31
1372 InvalidRegClassID, // VF0
1373 InvalidRegClassID, // VF1
1374 InvalidRegClassID, // VF2
1375 InvalidRegClassID, // VF3
1376 InvalidRegClassID, // VF4
1377 InvalidRegClassID, // VF5
1378 InvalidRegClassID, // VF6
1379 InvalidRegClassID, // VF7
1380 InvalidRegClassID, // VF8
1381 InvalidRegClassID, // VF9
1382 InvalidRegClassID, // VF10
1383 InvalidRegClassID, // VF11
1384 InvalidRegClassID, // VF12
1385 InvalidRegClassID, // VF13
1386 InvalidRegClassID, // VF14
1387 InvalidRegClassID, // VF15
1388 InvalidRegClassID, // VF16
1389 InvalidRegClassID, // VF17
1390 InvalidRegClassID, // VF18
1391 InvalidRegClassID, // VF19
1392 InvalidRegClassID, // VF20
1393 InvalidRegClassID, // VF21
1394 InvalidRegClassID, // VF22
1395 InvalidRegClassID, // VF23
1396 InvalidRegClassID, // VF24
1397 InvalidRegClassID, // VF25
1398 InvalidRegClassID, // VF26
1399 InvalidRegClassID, // VF27
1400 InvalidRegClassID, // VF28
1401 InvalidRegClassID, // VF29
1402 InvalidRegClassID, // VF30
1403 InvalidRegClassID, // VF31
1404 InvalidRegClassID, // VFR0
1405 InvalidRegClassID, // VFR1
1406 InvalidRegClassID, // VFR2
1407 InvalidRegClassID, // VFR3
1408 InvalidRegClassID, // VFR4
1409 InvalidRegClassID, // VFR5
1410 InvalidRegClassID, // VFR6
1411 InvalidRegClassID, // VFR7
1412 InvalidRegClassID, // VFR8
1413 InvalidRegClassID, // VFR9
1414 InvalidRegClassID, // VFR10
1415 InvalidRegClassID, // VFR11
1416 InvalidRegClassID, // VFR12
1417 InvalidRegClassID, // VFR13
1418 InvalidRegClassID, // VFR14
1419 InvalidRegClassID, // VFR15
1420 InvalidRegClassID, // VFR16
1421 InvalidRegClassID, // VFR17
1422 InvalidRegClassID, // VFR18
1423 InvalidRegClassID, // VFR19
1424 InvalidRegClassID, // VFR20
1425 InvalidRegClassID, // VFR21
1426 InvalidRegClassID, // VFR22
1427 InvalidRegClassID, // VFR23
1428 InvalidRegClassID, // VFR24
1429 InvalidRegClassID, // VFR25
1430 InvalidRegClassID, // VFR26
1431 InvalidRegClassID, // VFR27
1432 InvalidRegClassID, // VFR28
1433 InvalidRegClassID, // VFR29
1434 InvalidRegClassID, // VFR30
1435 InvalidRegClassID, // VFR31
1436 Hexagon::HvxVQRRegClassID, // VQ0
1437 Hexagon::HvxVQRRegClassID, // VQ1
1438 Hexagon::HvxVQRRegClassID, // VQ2
1439 Hexagon::HvxVQRRegClassID, // VQ3
1440 Hexagon::HvxVQRRegClassID, // VQ4
1441 Hexagon::HvxVQRRegClassID, // VQ5
1442 Hexagon::HvxVQRRegClassID, // VQ6
1443 Hexagon::HvxVQRRegClassID, // VQ7
1444 Hexagon::HvxWRRegClassID, // W0
1445 Hexagon::HvxWRRegClassID, // W1
1446 Hexagon::HvxWRRegClassID, // W2
1447 Hexagon::HvxWRRegClassID, // W3
1448 Hexagon::HvxWRRegClassID, // W4
1449 Hexagon::HvxWRRegClassID, // W5
1450 Hexagon::HvxWRRegClassID, // W6
1451 Hexagon::HvxWRRegClassID, // W7
1452 Hexagon::HvxWRRegClassID, // W8
1453 Hexagon::HvxWRRegClassID, // W9
1454 Hexagon::HvxWRRegClassID, // W10
1455 Hexagon::HvxWRRegClassID, // W11
1456 Hexagon::HvxWRRegClassID, // W12
1457 Hexagon::HvxWRRegClassID, // W13
1458 Hexagon::HvxWRRegClassID, // W14
1459 Hexagon::HvxWRRegClassID, // W15
1460 Hexagon::HvxWR_with_wsub_loRegClassID, // WR0
1461 Hexagon::HvxWR_with_wsub_loRegClassID, // WR1
1462 Hexagon::HvxWR_with_wsub_loRegClassID, // WR2
1463 Hexagon::HvxWR_with_wsub_loRegClassID, // WR3
1464 Hexagon::HvxWR_with_wsub_loRegClassID, // WR4
1465 Hexagon::HvxWR_with_wsub_loRegClassID, // WR5
1466 Hexagon::HvxWR_with_wsub_loRegClassID, // WR6
1467 Hexagon::HvxWR_with_wsub_loRegClassID, // WR7
1468 Hexagon::HvxWR_with_wsub_loRegClassID, // WR8
1469 Hexagon::HvxWR_with_wsub_loRegClassID, // WR9
1470 Hexagon::HvxWR_with_wsub_loRegClassID, // WR10
1471 Hexagon::HvxWR_with_wsub_loRegClassID, // WR11
1472 Hexagon::HvxWR_with_wsub_loRegClassID, // WR12
1473 Hexagon::HvxWR_with_wsub_loRegClassID, // WR13
1474 Hexagon::HvxWR_with_wsub_loRegClassID, // WR14
1475 Hexagon::HvxWR_with_wsub_loRegClassID, // WR15
1476 Hexagon::CtrRegs64RegClassID, // C1_0
1477 Hexagon::CtrRegs64RegClassID, // C3_2
1478 Hexagon::CtrRegs64RegClassID, // C5_4
1479 Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClassID, // C7_6
1480 Hexagon::CtrRegs64RegClassID, // C9_8
1481 Hexagon::CtrRegs64RegClassID, // C11_10
1482 Hexagon::CtrRegs64_and_V62RegsRegClassID, // C17_16
1483 Hexagon::GuestRegs64RegClassID, // G1_0
1484 Hexagon::GuestRegs64RegClassID, // G3_2
1485 Hexagon::GuestRegs64RegClassID, // G5_4
1486 Hexagon::GuestRegs64RegClassID, // G7_6
1487 Hexagon::GuestRegs64RegClassID, // G9_8
1488 Hexagon::GuestRegs64RegClassID, // G11_10
1489 Hexagon::GuestRegs64RegClassID, // G13_12
1490 Hexagon::GuestRegs64RegClassID, // G15_14
1491 Hexagon::GuestRegs64RegClassID, // G17_16
1492 Hexagon::GuestRegs64RegClassID, // G19_18
1493 Hexagon::GuestRegs64RegClassID, // G21_20
1494 Hexagon::GuestRegs64RegClassID, // G23_22
1495 Hexagon::GuestRegs64RegClassID, // G25_24
1496 Hexagon::GuestRegs64RegClassID, // G27_26
1497 Hexagon::GuestRegs64RegClassID, // G29_28
1498 Hexagon::GuestRegs64RegClassID, // G31_30
1499 Hexagon::CtrRegsRegClassID, // P3_0
1500 Hexagon::SysRegs64RegClassID, // S3_2
1501 Hexagon::SysRegs64RegClassID, // S5_4
1502 Hexagon::SysRegs64RegClassID, // S7_6
1503 Hexagon::SysRegs64RegClassID, // S9_8
1504 Hexagon::SysRegs64RegClassID, // S11_10
1505 Hexagon::SysRegs64RegClassID, // S13_12
1506 Hexagon::SysRegs64RegClassID, // S15_14
1507 Hexagon::SysRegs64RegClassID, // S17_16
1508 Hexagon::SysRegs64RegClassID, // S19_18
1509 Hexagon::SysRegs64RegClassID, // S21_20
1510 Hexagon::SysRegs64RegClassID, // S23_22
1511 Hexagon::SysRegs64RegClassID, // S25_24
1512 Hexagon::SysRegs64RegClassID, // S27_26
1513 Hexagon::SysRegs64RegClassID, // S29_28
1514 Hexagon::SysRegs64RegClassID, // S31_30
1515 Hexagon::SysRegs64RegClassID, // S33_32
1516 Hexagon::SysRegs64RegClassID, // S35_34
1517 Hexagon::SysRegs64RegClassID, // S37_36
1518 Hexagon::SysRegs64RegClassID, // S39_38
1519 Hexagon::SysRegs64RegClassID, // S41_40
1520 Hexagon::SysRegs64RegClassID, // S43_42
1521 Hexagon::SysRegs64RegClassID, // S45_44
1522 Hexagon::SysRegs64RegClassID, // S47_46
1523 Hexagon::SysRegs64RegClassID, // S49_48
1524 Hexagon::SysRegs64RegClassID, // S51_50
1525 Hexagon::SysRegs64RegClassID, // S53_52
1526 Hexagon::SysRegs64RegClassID, // S55_54
1527 Hexagon::SysRegs64RegClassID, // S57_56
1528 Hexagon::SysRegs64RegClassID, // S59_58
1529 Hexagon::SysRegs64RegClassID, // S61_60
1530 Hexagon::SysRegs64RegClassID, // S63_62
1531 Hexagon::SysRegs64RegClassID, // S65_64
1532 Hexagon::SysRegs64RegClassID, // S67_66
1533 Hexagon::SysRegs64RegClassID, // S69_68
1534 Hexagon::SysRegs64RegClassID, // S71_70
1535 Hexagon::SysRegs64RegClassID, // S73_72
1536 Hexagon::SysRegs64RegClassID, // S75_74
1537 Hexagon::SysRegs64RegClassID, // S77_76
1538 Hexagon::SysRegs64RegClassID, // S79_78
1539 Hexagon::SysRegs64RegClassID, // SGP1_0
1540 };
1541
1542 assert(Reg < ArrayRef(Mapping).size());
1543 unsigned RCID = Mapping[Reg.id()];
1544 if (RCID == InvalidRegClassID)
1545 return nullptr;
1546 return &HexagonMCRegisterClassStorage.Classes[RCID];
1547}
1548extern const MCRegisterDesc HexagonRegDesc[];
1549extern const int16_t HexagonRegDiffLists[];
1550extern const LaneBitmask HexagonLaneMaskLists[];
1551extern const char HexagonRegStrings[];
1552extern const char HexagonRegClassStrings[];
1553extern const MCPhysReg HexagonRegUnitRoots[][2];
1554extern const uint16_t HexagonSubRegIdxLists[];
1555extern const uint16_t HexagonRegEncodingTable[];
1556// Hexagon Dwarf<->LLVM register mappings.
1557extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
1558extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;
1559
1560extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
1561extern const unsigned HexagonEHFlavour0Dwarf2LSize;
1562
1563extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
1564extern const unsigned HexagonDwarfFlavour0L2DwarfSize;
1565
1566extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
1567extern const unsigned HexagonEHFlavour0L2DwarfSize;
1568
1569
1570HexagonGenRegisterInfo::
1571HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1572 unsigned PC, unsigned HwMode)
1573 : TargetRegisterInfo(&HexagonRegInfoDesc,
1574 HexagonSubRegIndexStrings, HexagonSubRegIndexNameOffsets,
1575 HexagonSubRegIdxRangeTable, HexagonSubRegIndexLaneMaskTable,
1576
1577 LaneBitmask(0xFFFFFFFFFFFFFFFB), HexagonRegClassInfos, HexagonVTLists, HwMode) {
1578 InitMCRegisterInfo(D: HexagonRegDesc, NR: 398, RA, PC,
1579 C: &getHexagonMCRegisterClass(RC: 0), NC: 29, RURoots: HexagonRegUnitRoots, NRU: 278, DL: HexagonRegDiffLists,
1580 RUMS: HexagonLaneMaskLists, Strings: HexagonRegStrings, ClassStrings: HexagonRegClassStrings, SubIndices: HexagonSubRegIdxLists, NumIndices: 11,
1581 RET: HexagonRegEncodingTable, RUI: nullptr);
1582
1583 switch (DwarfFlavour) {
1584 default:
1585 llvm_unreachable("Unknown DWARF flavour");
1586 case 0:
1587 mapDwarfRegsToLLVMRegs(Map: HexagonDwarfFlavour0Dwarf2L, Size: HexagonDwarfFlavour0Dwarf2LSize, isEH: false);
1588 break;
1589 }
1590 switch (EHFlavour) {
1591 default:
1592 llvm_unreachable("Unknown DWARF flavour");
1593 case 0:
1594 mapDwarfRegsToLLVMRegs(Map: HexagonEHFlavour0Dwarf2L, Size: HexagonEHFlavour0Dwarf2LSize, isEH: true);
1595 break;
1596 }
1597 switch (DwarfFlavour) {
1598 default:
1599 llvm_unreachable("Unknown DWARF flavour");
1600 case 0:
1601 mapLLVMRegsToDwarfRegs(Map: HexagonDwarfFlavour0L2Dwarf, Size: HexagonDwarfFlavour0L2DwarfSize, isEH: false);
1602 break;
1603 }
1604 switch (EHFlavour) {
1605 default:
1606 llvm_unreachable("Unknown DWARF flavour");
1607 case 0:
1608 mapLLVMRegsToDwarfRegs(Map: HexagonEHFlavour0L2Dwarf, Size: HexagonEHFlavour0L2DwarfSize, isEH: true);
1609 break;
1610 }
1611}
1612
1613static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
1614static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x00000000, 0x0000007e, 0x00000000, 0x0003ffc0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
1615
1616
1617ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
1618 static const uint32_t *const Masks[] = {
1619 HexagonCSR_RegMask,
1620 };
1621 return ArrayRef(Masks);
1622}
1623
1624bool HexagonGenRegisterInfo::
1625isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1626 return
1627 false;
1628}
1629
1630bool HexagonGenRegisterInfo::
1631isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1632 return
1633 false;
1634}
1635
1636bool HexagonGenRegisterInfo::
1637isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1638 return
1639 false;
1640}
1641
1642bool HexagonGenRegisterInfo::
1643isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1644 return
1645 false;
1646}
1647
1648bool HexagonGenRegisterInfo::
1649isConstantPhysReg(MCRegister PhysReg) const {
1650 return
1651 false;
1652}
1653
1654ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
1655 static const char *Names[] = {
1656 "HexagonCSR",
1657 };
1658 return ArrayRef(Names);
1659}
1660
1661const HexagonFrameLowering *
1662HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1663 return static_cast<const HexagonFrameLowering *>(
1664 MF.getSubtarget().getFrameLowering());
1665}
1666
1667
1668} // namespace llvm
1669