1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass HexagonMCRegisterClasses[];
12
13static const MVT::SimpleValueType HexagonVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
16 /* 10 */ MVT::i64, MVT::Other,
17 /* 12 */ MVT::v64i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
18 /* 17 */ MVT::v128i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
19 /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
20 /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
21 /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v32f16, MVT::v32bf16, MVT::v16f32, MVT::Other,
22 /* 40 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v64f16, MVT::v64bf16, MVT::v32f32, MVT::Other,
23 /* 47 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v128f16, MVT::v128bf16, MVT::v64f32, MVT::Other,
24 /* 54 */ MVT::Untyped, MVT::Other,
25};
26
27#ifdef __GNUC__
28#pragma GCC diagnostic push
29#pragma GCC diagnostic ignored "-Woverlength-strings"
30#endif
31static constexpr char HexagonSubRegIndexStrings[] = {
32 /* 0 */ "wsub_hi_then_vsub_fake\000"
33 /* 23 */ "isub_hi\000"
34 /* 31 */ "wsub_hi_then_vsub_hi\000"
35 /* 52 */ "wsub_hi\000"
36 /* 60 */ "isub_lo\000"
37 /* 68 */ "wsub_hi_then_vsub_lo\000"
38 /* 89 */ "wsub_lo\000"
39 /* 97 */ "subreg_overflow\000"
40};
41#ifdef __GNUC__
42#pragma GCC diagnostic pop
43#endif
44
45
46static constexpr uint32_t HexagonSubRegIndexNameOffsets[] = {
47 23,
48 60,
49 97,
50 13,
51 44,
52 81,
53 52,
54 89,
55 0,
56 31,
57 68,
58};
59
60static const TargetRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRangeTable[] = {
61 { .Offset: 4294967295, .Size: 4294967295 },
62 { .Offset: 32, .Size: 32 }, // isub_hi
63 { .Offset: 0, .Size: 32 }, // isub_lo
64 { .Offset: 0, .Size: 1 }, // subreg_overflow
65 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_fake
66 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_hi
67 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_lo
68 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi
69 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_lo
70 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_fake
71 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_hi
72 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_lo
73 { .Offset: 4294967295, .Size: 4294967295 },
74 { .Offset: 32, .Size: 32 }, // isub_hi
75 { .Offset: 0, .Size: 32 }, // isub_lo
76 { .Offset: 0, .Size: 1 }, // subreg_overflow
77 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_fake
78 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_hi
79 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_lo
80 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi
81 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_lo
82 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_fake
83 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_hi
84 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_lo
85 { .Offset: 4294967295, .Size: 4294967295 },
86 { .Offset: 32, .Size: 32 }, // isub_hi
87 { .Offset: 0, .Size: 32 }, // isub_lo
88 { .Offset: 0, .Size: 1 }, // subreg_overflow
89 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_fake
90 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_hi
91 { .Offset: 4294967295, .Size: 4294967295 }, // vsub_lo
92 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi
93 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_lo
94 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_fake
95 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_hi
96 { .Offset: 4294967295, .Size: 4294967295 }, // wsub_hi_then_vsub_lo
97};
98
99
100static const LaneBitmask HexagonSubRegIndexLaneMaskTable[] = {
101 LaneBitmask::getAll(),
102 LaneBitmask(0x0000000000000001), // isub_hi
103 LaneBitmask(0x0000000000000002), // isub_lo
104 LaneBitmask(0x0000000000000004), // subreg_overflow
105 LaneBitmask(0x0000000000000008), // vsub_fake
106 LaneBitmask(0x0000000000000010), // vsub_hi
107 LaneBitmask(0x0000000000000020), // vsub_lo
108 LaneBitmask(0x00000000000001C0), // wsub_hi
109 LaneBitmask(0x0000000000000038), // wsub_lo
110 LaneBitmask(0x0000000000000040), // wsub_hi_then_vsub_fake
111 LaneBitmask(0x0000000000000080), // wsub_hi_then_vsub_hi
112 LaneBitmask(0x0000000000000100), // wsub_hi_then_vsub_lo
113 };
114
115
116
117static const TargetRegisterInfo::RegClassInfo HexagonRegClassInfos[] = {
118 // Mode = 0 (DefaultMode)
119 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*HexagonVTLists+*/.VTListOffset: 0 }, // UsrBits
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // SysRegs
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GuestRegs
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 22 }, // IntRegs
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // IntRegsLow8
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
128 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 2 }, // PredRegs
129 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
130 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // ModRegs
131 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
132 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V65Regs
133 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // SysRegs64
134 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 27 }, // DoubleRegs
135 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GuestRegs64
136 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // VectRegRev
137 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64
138 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
139 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
140 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
141 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
142 { .RegSize: 64, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 12 }, // HvxQR
143 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR
144 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR_and_V65Regs
145 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR
146 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR_and_VectRegRev
147 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 54 }, // HvxVQR
148 // Mode = 1 (Hvx64)
149 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*HexagonVTLists+*/.VTListOffset: 0 }, // UsrBits
150 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // SysRegs
151 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GuestRegs
152 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 22 }, // IntRegs
153 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs
154 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
155 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs
156 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // IntRegsLow8
157 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
158 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 2 }, // PredRegs
159 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
160 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // ModRegs
161 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
162 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V65Regs
163 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // SysRegs64
164 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 27 }, // DoubleRegs
165 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GuestRegs64
166 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // VectRegRev
167 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64
168 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
169 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
170 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
171 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
172 { .RegSize: 64, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 12 }, // HvxQR
173 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR
174 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR_and_V65Regs
175 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR
176 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR_and_VectRegRev
177 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 54 }, // HvxVQR
178 // Mode = 2 (Hvx128)
179 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*HexagonVTLists+*/.VTListOffset: 0 }, // UsrBits
180 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // SysRegs
181 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GuestRegs
182 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 22 }, // IntRegs
183 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs
184 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
185 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs
186 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // IntRegsLow8
187 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
188 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 2 }, // PredRegs
189 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
190 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // ModRegs
191 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
192 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V65Regs
193 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // SysRegs64
194 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 27 }, // DoubleRegs
195 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GuestRegs64
196 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // VectRegRev
197 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64
198 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
199 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
200 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
201 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
202 { .RegSize: 128, .SpillSize: 1024, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 17 }, // HvxQR
203 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxVR
204 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxVR_and_V65Regs
205 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 47 }, // HvxWR
206 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 47 }, // HvxWR_and_VectRegRev
207 { .RegSize: 4096, .SpillSize: 4096, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 54 }, // HvxVQR
208};
209static const uint32_t UsrBitsSubClassMask[] = {
210 0x00000001,
211 0x00001000, // subreg_overflow
212};
213
214static const uint32_t SysRegsSubClassMask[] = {
215 0x00000002,
216 0x00004000, // isub_hi
217 0x00004000, // isub_lo
218};
219
220static const uint32_t GuestRegsSubClassMask[] = {
221 0x00000004,
222 0x00010000, // isub_hi
223 0x00010000, // isub_lo
224};
225
226static const uint32_t IntRegsSubClassMask[] = {
227 0x000000a8,
228 0x00188000, // isub_hi
229 0x00188000, // isub_lo
230};
231
232static const uint32_t CtrRegsSubClassMask[] = {
233 0x00001910,
234 0x00640400, // isub_hi
235 0x00640400, // isub_lo
236};
237
238static const uint32_t GeneralSubRegsSubClassMask[] = {
239 0x000000a0,
240 0x00180000, // isub_hi
241 0x00180000, // isub_lo
242};
243
244static const uint32_t V62RegsSubClassMask[] = {
245 0x00200540,
246 0x00200400, // isub_hi
247 0x00200400, // isub_lo
248};
249
250static const uint32_t IntRegsLow8SubClassMask[] = {
251 0x00000080,
252 0x00100000, // isub_hi
253 0x00100000, // isub_lo
254};
255
256static const uint32_t CtrRegs_and_V62RegsSubClassMask[] = {
257 0x00000100,
258 0x00200400, // isub_hi
259 0x00200400, // isub_lo
260};
261
262static const uint32_t PredRegsSubClassMask[] = {
263 0x00000200,
264};
265
266static const uint32_t V62Regs_with_isub_hiSubClassMask[] = {
267 0x00200400,
268};
269
270static const uint32_t ModRegsSubClassMask[] = {
271 0x00000800,
272 0x00400000, // isub_hi
273 0x00400000, // isub_lo
274};
275
276static const uint32_t CtrRegs_with_subreg_overflowSubClassMask[] = {
277 0x00001000,
278};
279
280static const uint32_t V65RegsSubClassMask[] = {
281 0x02002000,
282};
283
284static const uint32_t SysRegs64SubClassMask[] = {
285 0x00004000,
286};
287
288static const uint32_t DoubleRegsSubClassMask[] = {
289 0x00188000,
290};
291
292static const uint32_t GuestRegs64SubClassMask[] = {
293 0x00010000,
294};
295
296static const uint32_t VectRegRevSubClassMask[] = {
297 0x08020000,
298};
299
300static const uint32_t CtrRegs64SubClassMask[] = {
301 0x00640000,
302};
303
304static const uint32_t GeneralDoubleLow8RegsSubClassMask[] = {
305 0x00180000,
306};
307
308static const uint32_t DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask[] = {
309 0x00100000,
310};
311
312static const uint32_t CtrRegs64_and_V62RegsSubClassMask[] = {
313 0x00200000,
314};
315
316static const uint32_t CtrRegs64_with_isub_hi_in_ModRegsSubClassMask[] = {
317 0x00400000,
318};
319
320static const uint32_t HvxQRSubClassMask[] = {
321 0x00800000,
322};
323
324static const uint32_t HvxVRSubClassMask[] = {
325 0x03000000,
326 0x1c020000, // vsub_hi
327 0x1c020000, // vsub_lo
328 0x10000000, // wsub_hi_then_vsub_hi
329 0x10000000, // wsub_hi_then_vsub_lo
330};
331
332static const uint32_t HvxVR_and_V65RegsSubClassMask[] = {
333 0x02000000,
334};
335
336static const uint32_t HvxWRSubClassMask[] = {
337 0x0c000000,
338 0x10000000, // wsub_hi
339 0x10000000, // wsub_lo
340};
341
342static const uint32_t HvxWR_and_VectRegRevSubClassMask[] = {
343 0x08000000,
344};
345
346static const uint32_t HvxVQRSubClassMask[] = {
347 0x10000000,
348};
349
350static const uint16_t SuperRegIdxSeqs[] = {
351 /* 0 */ 1, 2, 0,
352 /* 3 */ 3, 0,
353 /* 5 */ 7, 8, 0,
354 /* 8 */ 5, 6, 10, 11, 0,
355};
356
357static unsigned const GeneralSubRegsSuperclasses[] = {
358 Hexagon::IntRegsRegClassID,
359};
360
361static unsigned const IntRegsLow8Superclasses[] = {
362 Hexagon::IntRegsRegClassID,
363 Hexagon::GeneralSubRegsRegClassID,
364};
365
366static unsigned const CtrRegs_and_V62RegsSuperclasses[] = {
367 Hexagon::CtrRegsRegClassID,
368 Hexagon::V62RegsRegClassID,
369};
370
371static unsigned const V62Regs_with_isub_hiSuperclasses[] = {
372 Hexagon::V62RegsRegClassID,
373};
374
375static unsigned const ModRegsSuperclasses[] = {
376 Hexagon::CtrRegsRegClassID,
377};
378
379static unsigned const CtrRegs_with_subreg_overflowSuperclasses[] = {
380 Hexagon::CtrRegsRegClassID,
381};
382
383static unsigned const GeneralDoubleLow8RegsSuperclasses[] = {
384 Hexagon::DoubleRegsRegClassID,
385};
386
387static unsigned const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
388 Hexagon::DoubleRegsRegClassID,
389 Hexagon::GeneralDoubleLow8RegsRegClassID,
390};
391
392static unsigned const CtrRegs64_and_V62RegsSuperclasses[] = {
393 Hexagon::V62RegsRegClassID,
394 Hexagon::V62Regs_with_isub_hiRegClassID,
395 Hexagon::CtrRegs64RegClassID,
396};
397
398static unsigned const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
399 Hexagon::CtrRegs64RegClassID,
400};
401
402static unsigned const HvxVR_and_V65RegsSuperclasses[] = {
403 Hexagon::V65RegsRegClassID,
404 Hexagon::HvxVRRegClassID,
405};
406
407static unsigned const HvxWR_and_VectRegRevSuperclasses[] = {
408 Hexagon::VectRegRevRegClassID,
409 Hexagon::HvxWRRegClassID,
410};
411
412namespace Hexagon {
413
414// Register class instances.
415 extern const TargetRegisterClass UsrBitsRegClass = {
416 .MC: &HexagonMCRegisterClasses[UsrBitsRegClassID],
417 .SubClassMask: UsrBitsSubClassMask,
418 .SuperRegIndices: SuperRegIdxSeqs + 3,
419 .LaneMask: LaneBitmask(0x0000000000000001),
420 .AllocationPriority: 0,
421 .GlobalPriority: false,
422 .TSFlags: 0x00, /* TSFlags */
423 .SpillStackID: 0, /* SpillStackID */
424 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
425 .CoveredBySubRegs: false, /* CoveredBySubRegs */
426 .SuperClasses: nullptr, .SuperClassesSize: 0,
427 .OrderFunc: nullptr
428 };
429
430 extern const TargetRegisterClass SysRegsRegClass = {
431 .MC: &HexagonMCRegisterClasses[SysRegsRegClassID],
432 .SubClassMask: SysRegsSubClassMask,
433 .SuperRegIndices: SuperRegIdxSeqs + 0,
434 .LaneMask: LaneBitmask(0x0000000000000001),
435 .AllocationPriority: 0,
436 .GlobalPriority: false,
437 .TSFlags: 0x00, /* TSFlags */
438 .SpillStackID: 0, /* SpillStackID */
439 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
440 .CoveredBySubRegs: false, /* CoveredBySubRegs */
441 .SuperClasses: nullptr, .SuperClassesSize: 0,
442 .OrderFunc: nullptr
443 };
444
445 extern const TargetRegisterClass GuestRegsRegClass = {
446 .MC: &HexagonMCRegisterClasses[GuestRegsRegClassID],
447 .SubClassMask: GuestRegsSubClassMask,
448 .SuperRegIndices: SuperRegIdxSeqs + 0,
449 .LaneMask: LaneBitmask(0x0000000000000001),
450 .AllocationPriority: 0,
451 .GlobalPriority: false,
452 .TSFlags: 0x00, /* TSFlags */
453 .SpillStackID: 0, /* SpillStackID */
454 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
455 .CoveredBySubRegs: false, /* CoveredBySubRegs */
456 .SuperClasses: nullptr, .SuperClassesSize: 0,
457 .OrderFunc: nullptr
458 };
459
460 extern const TargetRegisterClass IntRegsRegClass = {
461 .MC: &HexagonMCRegisterClasses[IntRegsRegClassID],
462 .SubClassMask: IntRegsSubClassMask,
463 .SuperRegIndices: SuperRegIdxSeqs + 0,
464 .LaneMask: LaneBitmask(0x0000000000000001),
465 .AllocationPriority: 0,
466 .GlobalPriority: false,
467 .TSFlags: 0x00, /* TSFlags */
468 .SpillStackID: 0, /* SpillStackID */
469 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
470 .CoveredBySubRegs: false, /* CoveredBySubRegs */
471 .SuperClasses: nullptr, .SuperClassesSize: 0,
472 .OrderFunc: nullptr
473 };
474
475 extern const TargetRegisterClass CtrRegsRegClass = {
476 .MC: &HexagonMCRegisterClasses[CtrRegsRegClassID],
477 .SubClassMask: CtrRegsSubClassMask,
478 .SuperRegIndices: SuperRegIdxSeqs + 0,
479 .LaneMask: LaneBitmask(0x0000000000000004),
480 .AllocationPriority: 0,
481 .GlobalPriority: false,
482 .TSFlags: 0x00, /* TSFlags */
483 .SpillStackID: 0, /* SpillStackID */
484 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
485 .CoveredBySubRegs: false, /* CoveredBySubRegs */
486 .SuperClasses: nullptr, .SuperClassesSize: 0,
487 .OrderFunc: nullptr
488 };
489
490 extern const TargetRegisterClass GeneralSubRegsRegClass = {
491 .MC: &HexagonMCRegisterClasses[GeneralSubRegsRegClassID],
492 .SubClassMask: GeneralSubRegsSubClassMask,
493 .SuperRegIndices: SuperRegIdxSeqs + 0,
494 .LaneMask: LaneBitmask(0x0000000000000001),
495 .AllocationPriority: 0,
496 .GlobalPriority: false,
497 .TSFlags: 0x00, /* TSFlags */
498 .SpillStackID: 0, /* SpillStackID */
499 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
500 .CoveredBySubRegs: false, /* CoveredBySubRegs */
501 .SuperClasses: GeneralSubRegsSuperclasses, .SuperClassesSize: 1,
502 .OrderFunc: nullptr
503 };
504
505 extern const TargetRegisterClass V62RegsRegClass = {
506 .MC: &HexagonMCRegisterClasses[V62RegsRegClassID],
507 .SubClassMask: V62RegsSubClassMask,
508 .SuperRegIndices: SuperRegIdxSeqs + 0,
509 .LaneMask: LaneBitmask(0x0000000000000003),
510 .AllocationPriority: 0,
511 .GlobalPriority: false,
512 .TSFlags: 0x00, /* TSFlags */
513 .SpillStackID: 0, /* SpillStackID */
514 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
515 .CoveredBySubRegs: false, /* CoveredBySubRegs */
516 .SuperClasses: nullptr, .SuperClassesSize: 0,
517 .OrderFunc: nullptr
518 };
519
520 extern const TargetRegisterClass IntRegsLow8RegClass = {
521 .MC: &HexagonMCRegisterClasses[IntRegsLow8RegClassID],
522 .SubClassMask: IntRegsLow8SubClassMask,
523 .SuperRegIndices: SuperRegIdxSeqs + 0,
524 .LaneMask: LaneBitmask(0x0000000000000001),
525 .AllocationPriority: 0,
526 .GlobalPriority: false,
527 .TSFlags: 0x00, /* TSFlags */
528 .SpillStackID: 0, /* SpillStackID */
529 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
530 .CoveredBySubRegs: false, /* CoveredBySubRegs */
531 .SuperClasses: IntRegsLow8Superclasses, .SuperClassesSize: 2,
532 .OrderFunc: nullptr
533 };
534
535 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
536 .MC: &HexagonMCRegisterClasses[CtrRegs_and_V62RegsRegClassID],
537 .SubClassMask: CtrRegs_and_V62RegsSubClassMask,
538 .SuperRegIndices: SuperRegIdxSeqs + 0,
539 .LaneMask: LaneBitmask(0x0000000000000001),
540 .AllocationPriority: 0,
541 .GlobalPriority: false,
542 .TSFlags: 0x00, /* TSFlags */
543 .SpillStackID: 0, /* SpillStackID */
544 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
545 .CoveredBySubRegs: false, /* CoveredBySubRegs */
546 .SuperClasses: CtrRegs_and_V62RegsSuperclasses, .SuperClassesSize: 2,
547 .OrderFunc: nullptr
548 };
549
550 extern const TargetRegisterClass PredRegsRegClass = {
551 .MC: &HexagonMCRegisterClasses[PredRegsRegClassID],
552 .SubClassMask: PredRegsSubClassMask,
553 .SuperRegIndices: SuperRegIdxSeqs + 2,
554 .LaneMask: LaneBitmask(0x0000000000000001),
555 .AllocationPriority: 0,
556 .GlobalPriority: false,
557 .TSFlags: 0x00, /* TSFlags */
558 .SpillStackID: 0, /* SpillStackID */
559 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
560 .CoveredBySubRegs: false, /* CoveredBySubRegs */
561 .SuperClasses: nullptr, .SuperClassesSize: 0,
562 .OrderFunc: nullptr
563 };
564
565 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
566 .MC: &HexagonMCRegisterClasses[V62Regs_with_isub_hiRegClassID],
567 .SubClassMask: V62Regs_with_isub_hiSubClassMask,
568 .SuperRegIndices: SuperRegIdxSeqs + 2,
569 .LaneMask: LaneBitmask(0x0000000000000003),
570 .AllocationPriority: 0,
571 .GlobalPriority: false,
572 .TSFlags: 0x00, /* TSFlags */
573 .SpillStackID: 0, /* SpillStackID */
574 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
575 .CoveredBySubRegs: true, /* CoveredBySubRegs */
576 .SuperClasses: V62Regs_with_isub_hiSuperclasses, .SuperClassesSize: 1,
577 .OrderFunc: nullptr
578 };
579
580 extern const TargetRegisterClass ModRegsRegClass = {
581 .MC: &HexagonMCRegisterClasses[ModRegsRegClassID],
582 .SubClassMask: ModRegsSubClassMask,
583 .SuperRegIndices: SuperRegIdxSeqs + 0,
584 .LaneMask: LaneBitmask(0x0000000000000001),
585 .AllocationPriority: 0,
586 .GlobalPriority: false,
587 .TSFlags: 0x00, /* TSFlags */
588 .SpillStackID: 0, /* SpillStackID */
589 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
590 .CoveredBySubRegs: false, /* CoveredBySubRegs */
591 .SuperClasses: ModRegsSuperclasses, .SuperClassesSize: 1,
592 .OrderFunc: nullptr
593 };
594
595 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
596 .MC: &HexagonMCRegisterClasses[CtrRegs_with_subreg_overflowRegClassID],
597 .SubClassMask: CtrRegs_with_subreg_overflowSubClassMask,
598 .SuperRegIndices: SuperRegIdxSeqs + 2,
599 .LaneMask: LaneBitmask(0x0000000000000004),
600 .AllocationPriority: 0,
601 .GlobalPriority: false,
602 .TSFlags: 0x00, /* TSFlags */
603 .SpillStackID: 0, /* SpillStackID */
604 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
605 .CoveredBySubRegs: false, /* CoveredBySubRegs */
606 .SuperClasses: CtrRegs_with_subreg_overflowSuperclasses, .SuperClassesSize: 1,
607 .OrderFunc: nullptr
608 };
609
610 extern const TargetRegisterClass V65RegsRegClass = {
611 .MC: &HexagonMCRegisterClasses[V65RegsRegClassID],
612 .SubClassMask: V65RegsSubClassMask,
613 .SuperRegIndices: SuperRegIdxSeqs + 2,
614 .LaneMask: LaneBitmask(0x0000000000000001),
615 .AllocationPriority: 0,
616 .GlobalPriority: false,
617 .TSFlags: 0x00, /* TSFlags */
618 .SpillStackID: 0, /* SpillStackID */
619 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
620 .CoveredBySubRegs: false, /* CoveredBySubRegs */
621 .SuperClasses: nullptr, .SuperClassesSize: 0,
622 .OrderFunc: nullptr
623 };
624
625 extern const TargetRegisterClass SysRegs64RegClass = {
626 .MC: &HexagonMCRegisterClasses[SysRegs64RegClassID],
627 .SubClassMask: SysRegs64SubClassMask,
628 .SuperRegIndices: SuperRegIdxSeqs + 2,
629 .LaneMask: LaneBitmask(0x0000000000000003),
630 .AllocationPriority: 0,
631 .GlobalPriority: false,
632 .TSFlags: 0x00, /* TSFlags */
633 .SpillStackID: 0, /* SpillStackID */
634 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
635 .CoveredBySubRegs: true, /* CoveredBySubRegs */
636 .SuperClasses: nullptr, .SuperClassesSize: 0,
637 .OrderFunc: nullptr
638 };
639
640 extern const TargetRegisterClass DoubleRegsRegClass = {
641 .MC: &HexagonMCRegisterClasses[DoubleRegsRegClassID],
642 .SubClassMask: DoubleRegsSubClassMask,
643 .SuperRegIndices: SuperRegIdxSeqs + 2,
644 .LaneMask: LaneBitmask(0x0000000000000003),
645 .AllocationPriority: 0,
646 .GlobalPriority: false,
647 .TSFlags: 0x00, /* TSFlags */
648 .SpillStackID: 0, /* SpillStackID */
649 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
650 .CoveredBySubRegs: true, /* CoveredBySubRegs */
651 .SuperClasses: nullptr, .SuperClassesSize: 0,
652 .OrderFunc: nullptr
653 };
654
655 extern const TargetRegisterClass GuestRegs64RegClass = {
656 .MC: &HexagonMCRegisterClasses[GuestRegs64RegClassID],
657 .SubClassMask: GuestRegs64SubClassMask,
658 .SuperRegIndices: SuperRegIdxSeqs + 2,
659 .LaneMask: LaneBitmask(0x0000000000000003),
660 .AllocationPriority: 0,
661 .GlobalPriority: false,
662 .TSFlags: 0x00, /* TSFlags */
663 .SpillStackID: 0, /* SpillStackID */
664 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
665 .CoveredBySubRegs: true, /* CoveredBySubRegs */
666 .SuperClasses: nullptr, .SuperClassesSize: 0,
667 .OrderFunc: nullptr
668 };
669
670 extern const TargetRegisterClass VectRegRevRegClass = {
671 .MC: &HexagonMCRegisterClasses[VectRegRevRegClassID],
672 .SubClassMask: VectRegRevSubClassMask,
673 .SuperRegIndices: SuperRegIdxSeqs + 2,
674 .LaneMask: LaneBitmask(0x0000000000000038),
675 .AllocationPriority: 0,
676 .GlobalPriority: false,
677 .TSFlags: 0x00, /* TSFlags */
678 .SpillStackID: 0, /* SpillStackID */
679 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
680 .CoveredBySubRegs: true, /* CoveredBySubRegs */
681 .SuperClasses: nullptr, .SuperClassesSize: 0,
682 .OrderFunc: nullptr
683 };
684
685 extern const TargetRegisterClass CtrRegs64RegClass = {
686 .MC: &HexagonMCRegisterClasses[CtrRegs64RegClassID],
687 .SubClassMask: CtrRegs64SubClassMask,
688 .SuperRegIndices: SuperRegIdxSeqs + 2,
689 .LaneMask: LaneBitmask(0x0000000000000003),
690 .AllocationPriority: 0,
691 .GlobalPriority: false,
692 .TSFlags: 0x00, /* TSFlags */
693 .SpillStackID: 0, /* SpillStackID */
694 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
695 .CoveredBySubRegs: true, /* CoveredBySubRegs */
696 .SuperClasses: nullptr, .SuperClassesSize: 0,
697 .OrderFunc: nullptr
698 };
699
700 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
701 .MC: &HexagonMCRegisterClasses[GeneralDoubleLow8RegsRegClassID],
702 .SubClassMask: GeneralDoubleLow8RegsSubClassMask,
703 .SuperRegIndices: SuperRegIdxSeqs + 2,
704 .LaneMask: LaneBitmask(0x0000000000000003),
705 .AllocationPriority: 0,
706 .GlobalPriority: false,
707 .TSFlags: 0x00, /* TSFlags */
708 .SpillStackID: 0, /* SpillStackID */
709 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
710 .CoveredBySubRegs: true, /* CoveredBySubRegs */
711 .SuperClasses: GeneralDoubleLow8RegsSuperclasses, .SuperClassesSize: 1,
712 .OrderFunc: nullptr
713 };
714
715 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
716 .MC: &HexagonMCRegisterClasses[DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID],
717 .SubClassMask: DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask,
718 .SuperRegIndices: SuperRegIdxSeqs + 2,
719 .LaneMask: LaneBitmask(0x0000000000000003),
720 .AllocationPriority: 0,
721 .GlobalPriority: false,
722 .TSFlags: 0x00, /* TSFlags */
723 .SpillStackID: 0, /* SpillStackID */
724 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
725 .CoveredBySubRegs: true, /* CoveredBySubRegs */
726 .SuperClasses: DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses, .SuperClassesSize: 2,
727 .OrderFunc: nullptr
728 };
729
730 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
731 .MC: &HexagonMCRegisterClasses[CtrRegs64_and_V62RegsRegClassID],
732 .SubClassMask: CtrRegs64_and_V62RegsSubClassMask,
733 .SuperRegIndices: SuperRegIdxSeqs + 2,
734 .LaneMask: LaneBitmask(0x0000000000000003),
735 .AllocationPriority: 0,
736 .GlobalPriority: false,
737 .TSFlags: 0x00, /* TSFlags */
738 .SpillStackID: 0, /* SpillStackID */
739 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
740 .CoveredBySubRegs: true, /* CoveredBySubRegs */
741 .SuperClasses: CtrRegs64_and_V62RegsSuperclasses, .SuperClassesSize: 3,
742 .OrderFunc: nullptr
743 };
744
745 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
746 .MC: &HexagonMCRegisterClasses[CtrRegs64_with_isub_hi_in_ModRegsRegClassID],
747 .SubClassMask: CtrRegs64_with_isub_hi_in_ModRegsSubClassMask,
748 .SuperRegIndices: SuperRegIdxSeqs + 2,
749 .LaneMask: LaneBitmask(0x0000000000000003),
750 .AllocationPriority: 0,
751 .GlobalPriority: false,
752 .TSFlags: 0x00, /* TSFlags */
753 .SpillStackID: 0, /* SpillStackID */
754 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
755 .CoveredBySubRegs: true, /* CoveredBySubRegs */
756 .SuperClasses: CtrRegs64_with_isub_hi_in_ModRegsSuperclasses, .SuperClassesSize: 1,
757 .OrderFunc: nullptr
758 };
759
760 extern const TargetRegisterClass HvxQRRegClass = {
761 .MC: &HexagonMCRegisterClasses[HvxQRRegClassID],
762 .SubClassMask: HvxQRSubClassMask,
763 .SuperRegIndices: SuperRegIdxSeqs + 2,
764 .LaneMask: LaneBitmask(0x0000000000000001),
765 .AllocationPriority: 0,
766 .GlobalPriority: false,
767 .TSFlags: 0x00, /* TSFlags */
768 .SpillStackID: 0, /* SpillStackID */
769 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
770 .CoveredBySubRegs: false, /* CoveredBySubRegs */
771 .SuperClasses: nullptr, .SuperClassesSize: 0,
772 .OrderFunc: nullptr
773 };
774
775 extern const TargetRegisterClass HvxVRRegClass = {
776 .MC: &HexagonMCRegisterClasses[HvxVRRegClassID],
777 .SubClassMask: HvxVRSubClassMask,
778 .SuperRegIndices: SuperRegIdxSeqs + 8,
779 .LaneMask: LaneBitmask(0x0000000000000001),
780 .AllocationPriority: 0,
781 .GlobalPriority: false,
782 .TSFlags: 0x00, /* TSFlags */
783 .SpillStackID: 0, /* SpillStackID */
784 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
785 .CoveredBySubRegs: false, /* CoveredBySubRegs */
786 .SuperClasses: nullptr, .SuperClassesSize: 0,
787 .OrderFunc: nullptr
788 };
789
790 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
791 .MC: &HexagonMCRegisterClasses[HvxVR_and_V65RegsRegClassID],
792 .SubClassMask: HvxVR_and_V65RegsSubClassMask,
793 .SuperRegIndices: SuperRegIdxSeqs + 2,
794 .LaneMask: LaneBitmask(0x0000000000000001),
795 .AllocationPriority: 0,
796 .GlobalPriority: false,
797 .TSFlags: 0x00, /* TSFlags */
798 .SpillStackID: 0, /* SpillStackID */
799 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
800 .CoveredBySubRegs: false, /* CoveredBySubRegs */
801 .SuperClasses: HvxVR_and_V65RegsSuperclasses, .SuperClassesSize: 2,
802 .OrderFunc: nullptr
803 };
804
805 extern const TargetRegisterClass HvxWRRegClass = {
806 .MC: &HexagonMCRegisterClasses[HvxWRRegClassID],
807 .SubClassMask: HvxWRSubClassMask,
808 .SuperRegIndices: SuperRegIdxSeqs + 5,
809 .LaneMask: LaneBitmask(0x0000000000000038),
810 .AllocationPriority: 0,
811 .GlobalPriority: false,
812 .TSFlags: 0x00, /* TSFlags */
813 .SpillStackID: 0, /* SpillStackID */
814 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
815 .CoveredBySubRegs: true, /* CoveredBySubRegs */
816 .SuperClasses: nullptr, .SuperClassesSize: 0,
817 .OrderFunc: nullptr
818 };
819
820 extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass = {
821 .MC: &HexagonMCRegisterClasses[HvxWR_and_VectRegRevRegClassID],
822 .SubClassMask: HvxWR_and_VectRegRevSubClassMask,
823 .SuperRegIndices: SuperRegIdxSeqs + 2,
824 .LaneMask: LaneBitmask(0x0000000000000038),
825 .AllocationPriority: 0,
826 .GlobalPriority: false,
827 .TSFlags: 0x00, /* TSFlags */
828 .SpillStackID: 0, /* SpillStackID */
829 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
830 .CoveredBySubRegs: true, /* CoveredBySubRegs */
831 .SuperClasses: HvxWR_and_VectRegRevSuperclasses, .SuperClassesSize: 2,
832 .OrderFunc: nullptr
833 };
834
835 extern const TargetRegisterClass HvxVQRRegClass = {
836 .MC: &HexagonMCRegisterClasses[HvxVQRRegClassID],
837 .SubClassMask: HvxVQRSubClassMask,
838 .SuperRegIndices: SuperRegIdxSeqs + 2,
839 .LaneMask: LaneBitmask(0x00000000000001F8),
840 .AllocationPriority: 0,
841 .GlobalPriority: false,
842 .TSFlags: 0x00, /* TSFlags */
843 .SpillStackID: 0, /* SpillStackID */
844 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
845 .CoveredBySubRegs: true, /* CoveredBySubRegs */
846 .SuperClasses: nullptr, .SuperClassesSize: 0,
847 .OrderFunc: nullptr
848 };
849
850
851} // namespace Hexagon
852static const TargetRegisterClass *const HexagonRegisterClasses[] = {
853 &Hexagon::UsrBitsRegClass,
854 &Hexagon::SysRegsRegClass,
855 &Hexagon::GuestRegsRegClass,
856 &Hexagon::IntRegsRegClass,
857 &Hexagon::CtrRegsRegClass,
858 &Hexagon::GeneralSubRegsRegClass,
859 &Hexagon::V62RegsRegClass,
860 &Hexagon::IntRegsLow8RegClass,
861 &Hexagon::CtrRegs_and_V62RegsRegClass,
862 &Hexagon::PredRegsRegClass,
863 &Hexagon::V62Regs_with_isub_hiRegClass,
864 &Hexagon::ModRegsRegClass,
865 &Hexagon::CtrRegs_with_subreg_overflowRegClass,
866 &Hexagon::V65RegsRegClass,
867 &Hexagon::SysRegs64RegClass,
868 &Hexagon::DoubleRegsRegClass,
869 &Hexagon::GuestRegs64RegClass,
870 &Hexagon::VectRegRevRegClass,
871 &Hexagon::CtrRegs64RegClass,
872 &Hexagon::GeneralDoubleLow8RegsRegClass,
873 &Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass,
874 &Hexagon::CtrRegs64_and_V62RegsRegClass,
875 &Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClass,
876 &Hexagon::HvxQRRegClass,
877 &Hexagon::HvxVRRegClass,
878 &Hexagon::HvxVR_and_V65RegsRegClass,
879 &Hexagon::HvxWRRegClass,
880 &Hexagon::HvxWR_and_VectRegRevRegClass,
881 &Hexagon::HvxVQRRegClass,
882 };
883
884static const uint8_t HexagonCostPerUseTable[] = {
8850, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
886
887
888static const bool HexagonInAllocatableClassTable[] = {
889false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
890
891
892static const TargetRegisterInfoDesc HexagonRegInfoDesc = { // Extra Descriptors
893.CostPerUse: HexagonCostPerUseTable, .NumCosts: 1, .InAllocatableClass: HexagonInAllocatableClassTable};
894
895unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
896 static const uint8_t RowMap[11] = {
897 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
898 };
899 static const uint8_t Rows[2][11] = {
900 { 0, 0, 0, Hexagon::wsub_hi_then_vsub_fake, Hexagon::wsub_hi_then_vsub_hi, Hexagon::wsub_hi_then_vsub_lo, 0, 0, 0, 0, 0, },
901 { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
902 };
903
904 --IdxA; assert(IdxA < 11); (void) IdxA;
905 --IdxB; assert(IdxB < 11);
906 return Rows[RowMap[IdxA]][IdxB];
907}
908
909unsigned HexagonGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
910 static const uint8_t Table[11][11] = {
911 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
912 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
913 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
914 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
915 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
916 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
917 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
918 { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
919 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
920 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
921 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
922 };
923
924 --IdxA; assert(IdxA < 11);
925 --IdxB; assert(IdxB < 11);
926 return Table[IdxA][IdxB];
927 }
928
929 struct MaskRolOp {
930 LaneBitmask Mask;
931 uint8_t RotateLeft;
932 };
933 static const MaskRolOp LaneMaskComposeSequences[] = {
934 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
935 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
936 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
937 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
938 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
939 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
940 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 12
941 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 7 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 14
942 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 8 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 16
943 };
944 static const uint8_t CompositeSequences[] = {
945 0, // to isub_hi
946 2, // to isub_lo
947 4, // to subreg_overflow
948 6, // to vsub_fake
949 8, // to vsub_hi
950 10, // to vsub_lo
951 6, // to wsub_hi
952 0, // to wsub_lo
953 12, // to wsub_hi_then_vsub_fake
954 14, // to wsub_hi_then_vsub_hi
955 16 // to wsub_hi_then_vsub_lo
956 };
957
958LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
959 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
960 LaneBitmask Result;
961 for (const MaskRolOp *Ops =
962 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
963 Ops->Mask.any(); ++Ops) {
964 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
965 if (unsigned S = Ops->RotateLeft)
966 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
967 else
968 Result |= LaneBitmask(M);
969 }
970 return Result;
971}
972
973LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
974 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
975 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
976 LaneBitmask Result;
977 for (const MaskRolOp *Ops =
978 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
979 Ops->Mask.any(); ++Ops) {
980 LaneBitmask::Type M = LaneMask.getAsInteger();
981 if (unsigned S = Ops->RotateLeft)
982 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
983 else
984 Result |= LaneBitmask(M);
985 }
986 return Result;
987}
988
989const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
990 static constexpr uint8_t Table[29][11] = {
991 { // UsrBits
992 0, // isub_hi
993 0, // isub_lo
994 0, // subreg_overflow
995 0, // vsub_fake
996 0, // vsub_hi
997 0, // vsub_lo
998 0, // wsub_hi
999 0, // wsub_lo
1000 0, // wsub_hi_then_vsub_fake
1001 0, // wsub_hi_then_vsub_hi
1002 0, // wsub_hi_then_vsub_lo
1003 },
1004 { // SysRegs
1005 0, // isub_hi
1006 0, // isub_lo
1007 0, // subreg_overflow
1008 0, // vsub_fake
1009 0, // vsub_hi
1010 0, // vsub_lo
1011 0, // wsub_hi
1012 0, // wsub_lo
1013 0, // wsub_hi_then_vsub_fake
1014 0, // wsub_hi_then_vsub_hi
1015 0, // wsub_hi_then_vsub_lo
1016 },
1017 { // GuestRegs
1018 0, // isub_hi
1019 0, // isub_lo
1020 0, // subreg_overflow
1021 0, // vsub_fake
1022 0, // vsub_hi
1023 0, // vsub_lo
1024 0, // wsub_hi
1025 0, // wsub_lo
1026 0, // wsub_hi_then_vsub_fake
1027 0, // wsub_hi_then_vsub_hi
1028 0, // wsub_hi_then_vsub_lo
1029 },
1030 { // IntRegs
1031 0, // isub_hi
1032 0, // isub_lo
1033 0, // subreg_overflow
1034 0, // vsub_fake
1035 0, // vsub_hi
1036 0, // vsub_lo
1037 0, // wsub_hi
1038 0, // wsub_lo
1039 0, // wsub_hi_then_vsub_fake
1040 0, // wsub_hi_then_vsub_hi
1041 0, // wsub_hi_then_vsub_lo
1042 },
1043 { // CtrRegs
1044 0, // isub_hi
1045 0, // isub_lo
1046 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
1047 0, // vsub_fake
1048 0, // vsub_hi
1049 0, // vsub_lo
1050 0, // wsub_hi
1051 0, // wsub_lo
1052 0, // wsub_hi_then_vsub_fake
1053 0, // wsub_hi_then_vsub_hi
1054 0, // wsub_hi_then_vsub_lo
1055 },
1056 { // GeneralSubRegs
1057 0, // isub_hi
1058 0, // isub_lo
1059 0, // subreg_overflow
1060 0, // vsub_fake
1061 0, // vsub_hi
1062 0, // vsub_lo
1063 0, // wsub_hi
1064 0, // wsub_lo
1065 0, // wsub_hi_then_vsub_fake
1066 0, // wsub_hi_then_vsub_hi
1067 0, // wsub_hi_then_vsub_lo
1068 },
1069 { // V62Regs
1070 11, // isub_hi -> V62Regs_with_isub_hi
1071 11, // isub_lo -> V62Regs_with_isub_hi
1072 0, // subreg_overflow
1073 0, // vsub_fake
1074 0, // vsub_hi
1075 0, // vsub_lo
1076 0, // wsub_hi
1077 0, // wsub_lo
1078 0, // wsub_hi_then_vsub_fake
1079 0, // wsub_hi_then_vsub_hi
1080 0, // wsub_hi_then_vsub_lo
1081 },
1082 { // IntRegsLow8
1083 0, // isub_hi
1084 0, // isub_lo
1085 0, // subreg_overflow
1086 0, // vsub_fake
1087 0, // vsub_hi
1088 0, // vsub_lo
1089 0, // wsub_hi
1090 0, // wsub_lo
1091 0, // wsub_hi_then_vsub_fake
1092 0, // wsub_hi_then_vsub_hi
1093 0, // wsub_hi_then_vsub_lo
1094 },
1095 { // CtrRegs_and_V62Regs
1096 0, // isub_hi
1097 0, // isub_lo
1098 0, // subreg_overflow
1099 0, // vsub_fake
1100 0, // vsub_hi
1101 0, // vsub_lo
1102 0, // wsub_hi
1103 0, // wsub_lo
1104 0, // wsub_hi_then_vsub_fake
1105 0, // wsub_hi_then_vsub_hi
1106 0, // wsub_hi_then_vsub_lo
1107 },
1108 { // PredRegs
1109 0, // isub_hi
1110 0, // isub_lo
1111 0, // subreg_overflow
1112 0, // vsub_fake
1113 0, // vsub_hi
1114 0, // vsub_lo
1115 0, // wsub_hi
1116 0, // wsub_lo
1117 0, // wsub_hi_then_vsub_fake
1118 0, // wsub_hi_then_vsub_hi
1119 0, // wsub_hi_then_vsub_lo
1120 },
1121 { // V62Regs_with_isub_hi
1122 11, // isub_hi -> V62Regs_with_isub_hi
1123 11, // isub_lo -> V62Regs_with_isub_hi
1124 0, // subreg_overflow
1125 0, // vsub_fake
1126 0, // vsub_hi
1127 0, // vsub_lo
1128 0, // wsub_hi
1129 0, // wsub_lo
1130 0, // wsub_hi_then_vsub_fake
1131 0, // wsub_hi_then_vsub_hi
1132 0, // wsub_hi_then_vsub_lo
1133 },
1134 { // ModRegs
1135 0, // isub_hi
1136 0, // isub_lo
1137 0, // subreg_overflow
1138 0, // vsub_fake
1139 0, // vsub_hi
1140 0, // vsub_lo
1141 0, // wsub_hi
1142 0, // wsub_lo
1143 0, // wsub_hi_then_vsub_fake
1144 0, // wsub_hi_then_vsub_hi
1145 0, // wsub_hi_then_vsub_lo
1146 },
1147 { // CtrRegs_with_subreg_overflow
1148 0, // isub_hi
1149 0, // isub_lo
1150 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
1151 0, // vsub_fake
1152 0, // vsub_hi
1153 0, // vsub_lo
1154 0, // wsub_hi
1155 0, // wsub_lo
1156 0, // wsub_hi_then_vsub_fake
1157 0, // wsub_hi_then_vsub_hi
1158 0, // wsub_hi_then_vsub_lo
1159 },
1160 { // V65Regs
1161 0, // isub_hi
1162 0, // isub_lo
1163 0, // subreg_overflow
1164 0, // vsub_fake
1165 0, // vsub_hi
1166 0, // vsub_lo
1167 0, // wsub_hi
1168 0, // wsub_lo
1169 0, // wsub_hi_then_vsub_fake
1170 0, // wsub_hi_then_vsub_hi
1171 0, // wsub_hi_then_vsub_lo
1172 },
1173 { // SysRegs64
1174 15, // isub_hi -> SysRegs64
1175 15, // isub_lo -> SysRegs64
1176 0, // subreg_overflow
1177 0, // vsub_fake
1178 0, // vsub_hi
1179 0, // vsub_lo
1180 0, // wsub_hi
1181 0, // wsub_lo
1182 0, // wsub_hi_then_vsub_fake
1183 0, // wsub_hi_then_vsub_hi
1184 0, // wsub_hi_then_vsub_lo
1185 },
1186 { // DoubleRegs
1187 16, // isub_hi -> DoubleRegs
1188 16, // isub_lo -> DoubleRegs
1189 0, // subreg_overflow
1190 0, // vsub_fake
1191 0, // vsub_hi
1192 0, // vsub_lo
1193 0, // wsub_hi
1194 0, // wsub_lo
1195 0, // wsub_hi_then_vsub_fake
1196 0, // wsub_hi_then_vsub_hi
1197 0, // wsub_hi_then_vsub_lo
1198 },
1199 { // GuestRegs64
1200 17, // isub_hi -> GuestRegs64
1201 17, // isub_lo -> GuestRegs64
1202 0, // subreg_overflow
1203 0, // vsub_fake
1204 0, // vsub_hi
1205 0, // vsub_lo
1206 0, // wsub_hi
1207 0, // wsub_lo
1208 0, // wsub_hi_then_vsub_fake
1209 0, // wsub_hi_then_vsub_hi
1210 0, // wsub_hi_then_vsub_lo
1211 },
1212 { // VectRegRev
1213 0, // isub_hi
1214 0, // isub_lo
1215 0, // subreg_overflow
1216 18, // vsub_fake -> VectRegRev
1217 18, // vsub_hi -> VectRegRev
1218 18, // vsub_lo -> VectRegRev
1219 0, // wsub_hi
1220 0, // wsub_lo
1221 0, // wsub_hi_then_vsub_fake
1222 0, // wsub_hi_then_vsub_hi
1223 0, // wsub_hi_then_vsub_lo
1224 },
1225 { // CtrRegs64
1226 19, // isub_hi -> CtrRegs64
1227 19, // isub_lo -> CtrRegs64
1228 0, // subreg_overflow
1229 0, // vsub_fake
1230 0, // vsub_hi
1231 0, // vsub_lo
1232 0, // wsub_hi
1233 0, // wsub_lo
1234 0, // wsub_hi_then_vsub_fake
1235 0, // wsub_hi_then_vsub_hi
1236 0, // wsub_hi_then_vsub_lo
1237 },
1238 { // GeneralDoubleLow8Regs
1239 20, // isub_hi -> GeneralDoubleLow8Regs
1240 20, // isub_lo -> GeneralDoubleLow8Regs
1241 0, // subreg_overflow
1242 0, // vsub_fake
1243 0, // vsub_hi
1244 0, // vsub_lo
1245 0, // wsub_hi
1246 0, // wsub_lo
1247 0, // wsub_hi_then_vsub_fake
1248 0, // wsub_hi_then_vsub_hi
1249 0, // wsub_hi_then_vsub_lo
1250 },
1251 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
1252 21, // isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
1253 21, // isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
1254 0, // subreg_overflow
1255 0, // vsub_fake
1256 0, // vsub_hi
1257 0, // vsub_lo
1258 0, // wsub_hi
1259 0, // wsub_lo
1260 0, // wsub_hi_then_vsub_fake
1261 0, // wsub_hi_then_vsub_hi
1262 0, // wsub_hi_then_vsub_lo
1263 },
1264 { // CtrRegs64_and_V62Regs
1265 22, // isub_hi -> CtrRegs64_and_V62Regs
1266 22, // isub_lo -> CtrRegs64_and_V62Regs
1267 0, // subreg_overflow
1268 0, // vsub_fake
1269 0, // vsub_hi
1270 0, // vsub_lo
1271 0, // wsub_hi
1272 0, // wsub_lo
1273 0, // wsub_hi_then_vsub_fake
1274 0, // wsub_hi_then_vsub_hi
1275 0, // wsub_hi_then_vsub_lo
1276 },
1277 { // CtrRegs64_with_isub_hi_in_ModRegs
1278 23, // isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
1279 23, // isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
1280 0, // subreg_overflow
1281 0, // vsub_fake
1282 0, // vsub_hi
1283 0, // vsub_lo
1284 0, // wsub_hi
1285 0, // wsub_lo
1286 0, // wsub_hi_then_vsub_fake
1287 0, // wsub_hi_then_vsub_hi
1288 0, // wsub_hi_then_vsub_lo
1289 },
1290 { // HvxQR
1291 0, // isub_hi
1292 0, // isub_lo
1293 0, // subreg_overflow
1294 0, // vsub_fake
1295 0, // vsub_hi
1296 0, // vsub_lo
1297 0, // wsub_hi
1298 0, // wsub_lo
1299 0, // wsub_hi_then_vsub_fake
1300 0, // wsub_hi_then_vsub_hi
1301 0, // wsub_hi_then_vsub_lo
1302 },
1303 { // HvxVR
1304 0, // isub_hi
1305 0, // isub_lo
1306 0, // subreg_overflow
1307 0, // vsub_fake
1308 0, // vsub_hi
1309 0, // vsub_lo
1310 0, // wsub_hi
1311 0, // wsub_lo
1312 0, // wsub_hi_then_vsub_fake
1313 0, // wsub_hi_then_vsub_hi
1314 0, // wsub_hi_then_vsub_lo
1315 },
1316 { // HvxVR_and_V65Regs
1317 0, // isub_hi
1318 0, // isub_lo
1319 0, // subreg_overflow
1320 0, // vsub_fake
1321 0, // vsub_hi
1322 0, // vsub_lo
1323 0, // wsub_hi
1324 0, // wsub_lo
1325 0, // wsub_hi_then_vsub_fake
1326 0, // wsub_hi_then_vsub_hi
1327 0, // wsub_hi_then_vsub_lo
1328 },
1329 { // HvxWR
1330 0, // isub_hi
1331 0, // isub_lo
1332 0, // subreg_overflow
1333 27, // vsub_fake -> HvxWR
1334 27, // vsub_hi -> HvxWR
1335 27, // vsub_lo -> HvxWR
1336 0, // wsub_hi
1337 0, // wsub_lo
1338 0, // wsub_hi_then_vsub_fake
1339 0, // wsub_hi_then_vsub_hi
1340 0, // wsub_hi_then_vsub_lo
1341 },
1342 { // HvxWR_and_VectRegRev
1343 0, // isub_hi
1344 0, // isub_lo
1345 0, // subreg_overflow
1346 28, // vsub_fake -> HvxWR_and_VectRegRev
1347 28, // vsub_hi -> HvxWR_and_VectRegRev
1348 28, // vsub_lo -> HvxWR_and_VectRegRev
1349 0, // wsub_hi
1350 0, // wsub_lo
1351 0, // wsub_hi_then_vsub_fake
1352 0, // wsub_hi_then_vsub_hi
1353 0, // wsub_hi_then_vsub_lo
1354 },
1355 { // HvxVQR
1356 0, // isub_hi
1357 0, // isub_lo
1358 0, // subreg_overflow
1359 29, // vsub_fake -> HvxVQR
1360 29, // vsub_hi -> HvxVQR
1361 29, // vsub_lo -> HvxVQR
1362 29, // wsub_hi -> HvxVQR
1363 29, // wsub_lo -> HvxVQR
1364 29, // wsub_hi_then_vsub_fake -> HvxVQR
1365 29, // wsub_hi_then_vsub_hi -> HvxVQR
1366 29, // wsub_hi_then_vsub_lo -> HvxVQR
1367 },
1368
1369 };
1370 assert(RC && "Missing regclass");
1371 if (!Idx) return RC;
1372 --Idx;
1373 assert(Idx < 11 && "Bad subreg");
1374 unsigned TV = Table[RC->getID()][Idx];
1375 return TV ? getRegClass(i: TV - 1) : nullptr;
1376}const TargetRegisterClass *HexagonGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1377 static constexpr uint8_t Table[29][11] = {
1378 { // UsrBits
1379 0, // UsrBits:isub_hi
1380 0, // UsrBits:isub_lo
1381 0, // UsrBits:subreg_overflow
1382 0, // UsrBits:vsub_fake
1383 0, // UsrBits:vsub_hi
1384 0, // UsrBits:vsub_lo
1385 0, // UsrBits:wsub_hi
1386 0, // UsrBits:wsub_lo
1387 0, // UsrBits:wsub_hi_then_vsub_fake
1388 0, // UsrBits:wsub_hi_then_vsub_hi
1389 0, // UsrBits:wsub_hi_then_vsub_lo
1390 },
1391 { // SysRegs
1392 0, // SysRegs:isub_hi
1393 0, // SysRegs:isub_lo
1394 0, // SysRegs:subreg_overflow
1395 0, // SysRegs:vsub_fake
1396 0, // SysRegs:vsub_hi
1397 0, // SysRegs:vsub_lo
1398 0, // SysRegs:wsub_hi
1399 0, // SysRegs:wsub_lo
1400 0, // SysRegs:wsub_hi_then_vsub_fake
1401 0, // SysRegs:wsub_hi_then_vsub_hi
1402 0, // SysRegs:wsub_hi_then_vsub_lo
1403 },
1404 { // GuestRegs
1405 0, // GuestRegs:isub_hi
1406 0, // GuestRegs:isub_lo
1407 0, // GuestRegs:subreg_overflow
1408 0, // GuestRegs:vsub_fake
1409 0, // GuestRegs:vsub_hi
1410 0, // GuestRegs:vsub_lo
1411 0, // GuestRegs:wsub_hi
1412 0, // GuestRegs:wsub_lo
1413 0, // GuestRegs:wsub_hi_then_vsub_fake
1414 0, // GuestRegs:wsub_hi_then_vsub_hi
1415 0, // GuestRegs:wsub_hi_then_vsub_lo
1416 },
1417 { // IntRegs
1418 0, // IntRegs:isub_hi
1419 0, // IntRegs:isub_lo
1420 0, // IntRegs:subreg_overflow
1421 0, // IntRegs:vsub_fake
1422 0, // IntRegs:vsub_hi
1423 0, // IntRegs:vsub_lo
1424 0, // IntRegs:wsub_hi
1425 0, // IntRegs:wsub_lo
1426 0, // IntRegs:wsub_hi_then_vsub_fake
1427 0, // IntRegs:wsub_hi_then_vsub_hi
1428 0, // IntRegs:wsub_hi_then_vsub_lo
1429 },
1430 { // CtrRegs
1431 0, // CtrRegs:isub_hi
1432 0, // CtrRegs:isub_lo
1433 1, // CtrRegs:subreg_overflow -> UsrBits
1434 0, // CtrRegs:vsub_fake
1435 0, // CtrRegs:vsub_hi
1436 0, // CtrRegs:vsub_lo
1437 0, // CtrRegs:wsub_hi
1438 0, // CtrRegs:wsub_lo
1439 0, // CtrRegs:wsub_hi_then_vsub_fake
1440 0, // CtrRegs:wsub_hi_then_vsub_hi
1441 0, // CtrRegs:wsub_hi_then_vsub_lo
1442 },
1443 { // GeneralSubRegs
1444 0, // GeneralSubRegs:isub_hi
1445 0, // GeneralSubRegs:isub_lo
1446 0, // GeneralSubRegs:subreg_overflow
1447 0, // GeneralSubRegs:vsub_fake
1448 0, // GeneralSubRegs:vsub_hi
1449 0, // GeneralSubRegs:vsub_lo
1450 0, // GeneralSubRegs:wsub_hi
1451 0, // GeneralSubRegs:wsub_lo
1452 0, // GeneralSubRegs:wsub_hi_then_vsub_fake
1453 0, // GeneralSubRegs:wsub_hi_then_vsub_hi
1454 0, // GeneralSubRegs:wsub_hi_then_vsub_lo
1455 },
1456 { // V62Regs
1457 9, // V62Regs:isub_hi -> CtrRegs_and_V62Regs
1458 9, // V62Regs:isub_lo -> CtrRegs_and_V62Regs
1459 0, // V62Regs:subreg_overflow
1460 0, // V62Regs:vsub_fake
1461 0, // V62Regs:vsub_hi
1462 0, // V62Regs:vsub_lo
1463 0, // V62Regs:wsub_hi
1464 0, // V62Regs:wsub_lo
1465 0, // V62Regs:wsub_hi_then_vsub_fake
1466 0, // V62Regs:wsub_hi_then_vsub_hi
1467 0, // V62Regs:wsub_hi_then_vsub_lo
1468 },
1469 { // IntRegsLow8
1470 0, // IntRegsLow8:isub_hi
1471 0, // IntRegsLow8:isub_lo
1472 0, // IntRegsLow8:subreg_overflow
1473 0, // IntRegsLow8:vsub_fake
1474 0, // IntRegsLow8:vsub_hi
1475 0, // IntRegsLow8:vsub_lo
1476 0, // IntRegsLow8:wsub_hi
1477 0, // IntRegsLow8:wsub_lo
1478 0, // IntRegsLow8:wsub_hi_then_vsub_fake
1479 0, // IntRegsLow8:wsub_hi_then_vsub_hi
1480 0, // IntRegsLow8:wsub_hi_then_vsub_lo
1481 },
1482 { // CtrRegs_and_V62Regs
1483 0, // CtrRegs_and_V62Regs:isub_hi
1484 0, // CtrRegs_and_V62Regs:isub_lo
1485 0, // CtrRegs_and_V62Regs:subreg_overflow
1486 0, // CtrRegs_and_V62Regs:vsub_fake
1487 0, // CtrRegs_and_V62Regs:vsub_hi
1488 0, // CtrRegs_and_V62Regs:vsub_lo
1489 0, // CtrRegs_and_V62Regs:wsub_hi
1490 0, // CtrRegs_and_V62Regs:wsub_lo
1491 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_fake
1492 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_hi
1493 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_lo
1494 },
1495 { // PredRegs
1496 0, // PredRegs:isub_hi
1497 0, // PredRegs:isub_lo
1498 0, // PredRegs:subreg_overflow
1499 0, // PredRegs:vsub_fake
1500 0, // PredRegs:vsub_hi
1501 0, // PredRegs:vsub_lo
1502 0, // PredRegs:wsub_hi
1503 0, // PredRegs:wsub_lo
1504 0, // PredRegs:wsub_hi_then_vsub_fake
1505 0, // PredRegs:wsub_hi_then_vsub_hi
1506 0, // PredRegs:wsub_hi_then_vsub_lo
1507 },
1508 { // V62Regs_with_isub_hi
1509 9, // V62Regs_with_isub_hi:isub_hi -> CtrRegs_and_V62Regs
1510 9, // V62Regs_with_isub_hi:isub_lo -> CtrRegs_and_V62Regs
1511 0, // V62Regs_with_isub_hi:subreg_overflow
1512 0, // V62Regs_with_isub_hi:vsub_fake
1513 0, // V62Regs_with_isub_hi:vsub_hi
1514 0, // V62Regs_with_isub_hi:vsub_lo
1515 0, // V62Regs_with_isub_hi:wsub_hi
1516 0, // V62Regs_with_isub_hi:wsub_lo
1517 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_fake
1518 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_hi
1519 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_lo
1520 },
1521 { // ModRegs
1522 0, // ModRegs:isub_hi
1523 0, // ModRegs:isub_lo
1524 0, // ModRegs:subreg_overflow
1525 0, // ModRegs:vsub_fake
1526 0, // ModRegs:vsub_hi
1527 0, // ModRegs:vsub_lo
1528 0, // ModRegs:wsub_hi
1529 0, // ModRegs:wsub_lo
1530 0, // ModRegs:wsub_hi_then_vsub_fake
1531 0, // ModRegs:wsub_hi_then_vsub_hi
1532 0, // ModRegs:wsub_hi_then_vsub_lo
1533 },
1534 { // CtrRegs_with_subreg_overflow
1535 0, // CtrRegs_with_subreg_overflow:isub_hi
1536 0, // CtrRegs_with_subreg_overflow:isub_lo
1537 1, // CtrRegs_with_subreg_overflow:subreg_overflow -> UsrBits
1538 0, // CtrRegs_with_subreg_overflow:vsub_fake
1539 0, // CtrRegs_with_subreg_overflow:vsub_hi
1540 0, // CtrRegs_with_subreg_overflow:vsub_lo
1541 0, // CtrRegs_with_subreg_overflow:wsub_hi
1542 0, // CtrRegs_with_subreg_overflow:wsub_lo
1543 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_fake
1544 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_hi
1545 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_lo
1546 },
1547 { // V65Regs
1548 0, // V65Regs:isub_hi
1549 0, // V65Regs:isub_lo
1550 0, // V65Regs:subreg_overflow
1551 0, // V65Regs:vsub_fake
1552 0, // V65Regs:vsub_hi
1553 0, // V65Regs:vsub_lo
1554 0, // V65Regs:wsub_hi
1555 0, // V65Regs:wsub_lo
1556 0, // V65Regs:wsub_hi_then_vsub_fake
1557 0, // V65Regs:wsub_hi_then_vsub_hi
1558 0, // V65Regs:wsub_hi_then_vsub_lo
1559 },
1560 { // SysRegs64
1561 2, // SysRegs64:isub_hi -> SysRegs
1562 2, // SysRegs64:isub_lo -> SysRegs
1563 0, // SysRegs64:subreg_overflow
1564 0, // SysRegs64:vsub_fake
1565 0, // SysRegs64:vsub_hi
1566 0, // SysRegs64:vsub_lo
1567 0, // SysRegs64:wsub_hi
1568 0, // SysRegs64:wsub_lo
1569 0, // SysRegs64:wsub_hi_then_vsub_fake
1570 0, // SysRegs64:wsub_hi_then_vsub_hi
1571 0, // SysRegs64:wsub_hi_then_vsub_lo
1572 },
1573 { // DoubleRegs
1574 4, // DoubleRegs:isub_hi -> IntRegs
1575 4, // DoubleRegs:isub_lo -> IntRegs
1576 0, // DoubleRegs:subreg_overflow
1577 0, // DoubleRegs:vsub_fake
1578 0, // DoubleRegs:vsub_hi
1579 0, // DoubleRegs:vsub_lo
1580 0, // DoubleRegs:wsub_hi
1581 0, // DoubleRegs:wsub_lo
1582 0, // DoubleRegs:wsub_hi_then_vsub_fake
1583 0, // DoubleRegs:wsub_hi_then_vsub_hi
1584 0, // DoubleRegs:wsub_hi_then_vsub_lo
1585 },
1586 { // GuestRegs64
1587 3, // GuestRegs64:isub_hi -> GuestRegs
1588 3, // GuestRegs64:isub_lo -> GuestRegs
1589 0, // GuestRegs64:subreg_overflow
1590 0, // GuestRegs64:vsub_fake
1591 0, // GuestRegs64:vsub_hi
1592 0, // GuestRegs64:vsub_lo
1593 0, // GuestRegs64:wsub_hi
1594 0, // GuestRegs64:wsub_lo
1595 0, // GuestRegs64:wsub_hi_then_vsub_fake
1596 0, // GuestRegs64:wsub_hi_then_vsub_hi
1597 0, // GuestRegs64:wsub_hi_then_vsub_lo
1598 },
1599 { // VectRegRev
1600 0, // VectRegRev:isub_hi
1601 0, // VectRegRev:isub_lo
1602 0, // VectRegRev:subreg_overflow
1603 0, // VectRegRev:vsub_fake
1604 25, // VectRegRev:vsub_hi -> HvxVR
1605 25, // VectRegRev:vsub_lo -> HvxVR
1606 0, // VectRegRev:wsub_hi
1607 0, // VectRegRev:wsub_lo
1608 0, // VectRegRev:wsub_hi_then_vsub_fake
1609 0, // VectRegRev:wsub_hi_then_vsub_hi
1610 0, // VectRegRev:wsub_hi_then_vsub_lo
1611 },
1612 { // CtrRegs64
1613 5, // CtrRegs64:isub_hi -> CtrRegs
1614 5, // CtrRegs64:isub_lo -> CtrRegs
1615 0, // CtrRegs64:subreg_overflow
1616 0, // CtrRegs64:vsub_fake
1617 0, // CtrRegs64:vsub_hi
1618 0, // CtrRegs64:vsub_lo
1619 0, // CtrRegs64:wsub_hi
1620 0, // CtrRegs64:wsub_lo
1621 0, // CtrRegs64:wsub_hi_then_vsub_fake
1622 0, // CtrRegs64:wsub_hi_then_vsub_hi
1623 0, // CtrRegs64:wsub_hi_then_vsub_lo
1624 },
1625 { // GeneralDoubleLow8Regs
1626 6, // GeneralDoubleLow8Regs:isub_hi -> GeneralSubRegs
1627 6, // GeneralDoubleLow8Regs:isub_lo -> GeneralSubRegs
1628 0, // GeneralDoubleLow8Regs:subreg_overflow
1629 0, // GeneralDoubleLow8Regs:vsub_fake
1630 0, // GeneralDoubleLow8Regs:vsub_hi
1631 0, // GeneralDoubleLow8Regs:vsub_lo
1632 0, // GeneralDoubleLow8Regs:wsub_hi
1633 0, // GeneralDoubleLow8Regs:wsub_lo
1634 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_fake
1635 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_hi
1636 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_lo
1637 },
1638 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
1639 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_hi -> IntRegsLow8
1640 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_lo -> IntRegsLow8
1641 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:subreg_overflow
1642 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_fake
1643 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_hi
1644 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_lo
1645 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi
1646 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_lo
1647 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_fake
1648 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_hi
1649 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_lo
1650 },
1651 { // CtrRegs64_and_V62Regs
1652 9, // CtrRegs64_and_V62Regs:isub_hi -> CtrRegs_and_V62Regs
1653 9, // CtrRegs64_and_V62Regs:isub_lo -> CtrRegs_and_V62Regs
1654 0, // CtrRegs64_and_V62Regs:subreg_overflow
1655 0, // CtrRegs64_and_V62Regs:vsub_fake
1656 0, // CtrRegs64_and_V62Regs:vsub_hi
1657 0, // CtrRegs64_and_V62Regs:vsub_lo
1658 0, // CtrRegs64_and_V62Regs:wsub_hi
1659 0, // CtrRegs64_and_V62Regs:wsub_lo
1660 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_fake
1661 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_hi
1662 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_lo
1663 },
1664 { // CtrRegs64_with_isub_hi_in_ModRegs
1665 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_hi -> ModRegs
1666 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_lo -> ModRegs
1667 0, // CtrRegs64_with_isub_hi_in_ModRegs:subreg_overflow
1668 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_fake
1669 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_hi
1670 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_lo
1671 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi
1672 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_lo
1673 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_fake
1674 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_hi
1675 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_lo
1676 },
1677 { // HvxQR
1678 0, // HvxQR:isub_hi
1679 0, // HvxQR:isub_lo
1680 0, // HvxQR:subreg_overflow
1681 0, // HvxQR:vsub_fake
1682 0, // HvxQR:vsub_hi
1683 0, // HvxQR:vsub_lo
1684 0, // HvxQR:wsub_hi
1685 0, // HvxQR:wsub_lo
1686 0, // HvxQR:wsub_hi_then_vsub_fake
1687 0, // HvxQR:wsub_hi_then_vsub_hi
1688 0, // HvxQR:wsub_hi_then_vsub_lo
1689 },
1690 { // HvxVR
1691 0, // HvxVR:isub_hi
1692 0, // HvxVR:isub_lo
1693 0, // HvxVR:subreg_overflow
1694 0, // HvxVR:vsub_fake
1695 0, // HvxVR:vsub_hi
1696 0, // HvxVR:vsub_lo
1697 0, // HvxVR:wsub_hi
1698 0, // HvxVR:wsub_lo
1699 0, // HvxVR:wsub_hi_then_vsub_fake
1700 0, // HvxVR:wsub_hi_then_vsub_hi
1701 0, // HvxVR:wsub_hi_then_vsub_lo
1702 },
1703 { // HvxVR_and_V65Regs
1704 0, // HvxVR_and_V65Regs:isub_hi
1705 0, // HvxVR_and_V65Regs:isub_lo
1706 0, // HvxVR_and_V65Regs:subreg_overflow
1707 0, // HvxVR_and_V65Regs:vsub_fake
1708 0, // HvxVR_and_V65Regs:vsub_hi
1709 0, // HvxVR_and_V65Regs:vsub_lo
1710 0, // HvxVR_and_V65Regs:wsub_hi
1711 0, // HvxVR_and_V65Regs:wsub_lo
1712 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_fake
1713 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_hi
1714 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_lo
1715 },
1716 { // HvxWR
1717 0, // HvxWR:isub_hi
1718 0, // HvxWR:isub_lo
1719 0, // HvxWR:subreg_overflow
1720 0, // HvxWR:vsub_fake
1721 25, // HvxWR:vsub_hi -> HvxVR
1722 25, // HvxWR:vsub_lo -> HvxVR
1723 0, // HvxWR:wsub_hi
1724 0, // HvxWR:wsub_lo
1725 0, // HvxWR:wsub_hi_then_vsub_fake
1726 0, // HvxWR:wsub_hi_then_vsub_hi
1727 0, // HvxWR:wsub_hi_then_vsub_lo
1728 },
1729 { // HvxWR_and_VectRegRev
1730 0, // HvxWR_and_VectRegRev:isub_hi
1731 0, // HvxWR_and_VectRegRev:isub_lo
1732 0, // HvxWR_and_VectRegRev:subreg_overflow
1733 0, // HvxWR_and_VectRegRev:vsub_fake
1734 25, // HvxWR_and_VectRegRev:vsub_hi -> HvxVR
1735 25, // HvxWR_and_VectRegRev:vsub_lo -> HvxVR
1736 0, // HvxWR_and_VectRegRev:wsub_hi
1737 0, // HvxWR_and_VectRegRev:wsub_lo
1738 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_fake
1739 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_hi
1740 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_lo
1741 },
1742 { // HvxVQR
1743 0, // HvxVQR:isub_hi
1744 0, // HvxVQR:isub_lo
1745 0, // HvxVQR:subreg_overflow
1746 0, // HvxVQR:vsub_fake
1747 25, // HvxVQR:vsub_hi -> HvxVR
1748 25, // HvxVQR:vsub_lo -> HvxVR
1749 27, // HvxVQR:wsub_hi -> HvxWR
1750 27, // HvxVQR:wsub_lo -> HvxWR
1751 0, // HvxVQR:wsub_hi_then_vsub_fake
1752 25, // HvxVQR:wsub_hi_then_vsub_hi -> HvxVR
1753 25, // HvxVQR:wsub_hi_then_vsub_lo -> HvxVR
1754 },
1755
1756 };
1757 assert(RC && "Missing regclass");
1758 if (!Idx) return RC;
1759 --Idx;
1760 assert(Idx < 11 && "Bad subreg");
1761 unsigned TV = Table[RC->getID()][Idx];
1762 return TV ? getRegClass(i: TV - 1) : nullptr;
1763}/// Get the weight in units of pressure for this register class.
1764const RegClassWeight &HexagonGenRegisterInfo::
1765getRegClassWeight(const TargetRegisterClass *RC) const {
1766 static const RegClassWeight RCWeightTable[] = {
1767 {.RegWeight: 0, .WeightLimit: 0}, // UsrBits
1768 {.RegWeight: 0, .WeightLimit: 0}, // SysRegs
1769 {.RegWeight: 0, .WeightLimit: 0}, // GuestRegs
1770 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
1771 {.RegWeight: 0, .WeightLimit: 6}, // CtrRegs
1772 {.RegWeight: 1, .WeightLimit: 16}, // GeneralSubRegs
1773 {.RegWeight: 0, .WeightLimit: 0}, // V62Regs
1774 {.RegWeight: 1, .WeightLimit: 8}, // IntRegsLow8
1775 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs_and_V62Regs
1776 {.RegWeight: 2, .WeightLimit: 8}, // PredRegs
1777 {.RegWeight: 0, .WeightLimit: 0}, // V62Regs_with_isub_hi
1778 {.RegWeight: 1, .WeightLimit: 2}, // ModRegs
1779 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs_with_subreg_overflow
1780 {.RegWeight: 1, .WeightLimit: 1}, // V65Regs
1781 {.RegWeight: 0, .WeightLimit: 0}, // SysRegs64
1782 {.RegWeight: 2, .WeightLimit: 32}, // DoubleRegs
1783 {.RegWeight: 0, .WeightLimit: 0}, // GuestRegs64
1784 {.RegWeight: 2, .WeightLimit: 32}, // VectRegRev
1785 {.RegWeight: 0, .WeightLimit: 6}, // CtrRegs64
1786 {.RegWeight: 2, .WeightLimit: 16}, // GeneralDoubleLow8Regs
1787 {.RegWeight: 2, .WeightLimit: 8}, // DoubleRegs_with_isub_hi_in_IntRegsLow8
1788 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs64_and_V62Regs
1789 {.RegWeight: 2, .WeightLimit: 2}, // CtrRegs64_with_isub_hi_in_ModRegs
1790 {.RegWeight: 1, .WeightLimit: 4}, // HvxQR
1791 {.RegWeight: 1, .WeightLimit: 33}, // HvxVR
1792 {.RegWeight: 1, .WeightLimit: 1}, // HvxVR_and_V65Regs
1793 {.RegWeight: 2, .WeightLimit: 32}, // HvxWR
1794 {.RegWeight: 2, .WeightLimit: 32}, // HvxWR_and_VectRegRev
1795 {.RegWeight: 4, .WeightLimit: 32}, // HvxVQR
1796 };
1797 return RCWeightTable[RC->getID()];
1798}
1799
1800/// Get the weight in units of pressure for this register unit.
1801unsigned HexagonGenRegisterInfo::
1802getRegUnitWeight(MCRegUnit RegUnit) const {
1803 assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
1804 // All register units have unit weight.
1805 return 1;
1806}
1807
1808
1809// Get the number of dimensions of register pressure.
1810unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
1811 return 8;
1812}
1813
1814// Get the name of this register unit pressure set.
1815const char *HexagonGenRegisterInfo::
1816getRegPressureSetName(unsigned Idx) const {
1817 static const char *PressureNameTable[] = {
1818 "HvxVR_and_V65Regs",
1819 "ModRegs",
1820 "HvxQR",
1821 "IntRegsLow8",
1822 "PredRegs",
1823 "GeneralSubRegs",
1824 "IntRegs",
1825 "HvxVR",
1826 };
1827 return PressureNameTable[Idx];
1828}
1829
1830// Get the register unit pressure limit for this dimension.
1831// This limit must be adjusted dynamically for reserved registers.
1832unsigned HexagonGenRegisterInfo::
1833getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1834 static const uint8_t PressureLimitTable[] = {
1835 1, // 0: HvxVR_and_V65Regs
1836 2, // 1: ModRegs
1837 4, // 2: HvxQR
1838 8, // 3: IntRegsLow8
1839 8, // 4: PredRegs
1840 16, // 5: GeneralSubRegs
1841 32, // 6: IntRegs
1842 33, // 7: HvxVR
1843 };
1844 return PressureLimitTable[Idx];
1845}
1846
1847/// Table of pressure sets per register class or unit.
1848static const int RCSetsTable[] = {
1849 /* 0 */ 1, -1,
1850 /* 2 */ 2, -1,
1851 /* 4 */ 4, -1,
1852 /* 6 */ 3, 5, 6, -1,
1853 /* 10 */ 0, 7, -1,
1854};
1855
1856/// Get the dimensions of register pressure impacted by this register class.
1857/// Returns a -1 terminated array of pressure set IDs
1858const int *HexagonGenRegisterInfo::
1859getRegClassPressureSets(const TargetRegisterClass *RC) const {
1860 static const uint8_t RCSetStartTable[] = {
1861 1,1,1,8,1,7,1,6,1,4,1,0,1,1,1,8,1,11,1,7,6,1,1,2,11,10,11,11,11,};
1862 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1863}
1864
1865/// Get the dimensions of register pressure impacted by this register unit.
1866/// Returns a -1 terminated array of pressure set IDs
1867const int *HexagonGenRegisterInfo::
1868getRegUnitPressureSets(MCRegUnit RegUnit) const {
1869 assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
1870 static const uint8_t RUSetStartTable[] = {
1871 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,4,4,4,4,4,4,4,4,1,1,1,1,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
1872 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1873}
1874
1875
1876// Register to minimal register class mapping
1877
1878const TargetRegisterClass *HexagonGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
1879 static const uint16_t InvalidRegClassID = UINT16_MAX;
1880
1881 static const uint16_t Mapping[398] = {
1882 InvalidRegClassID, // NoRegister
1883 Hexagon::SysRegsRegClassID, // BADVA
1884 Hexagon::SysRegsRegClassID, // CCR
1885 Hexagon::SysRegsRegClassID, // CFGBASE
1886 Hexagon::CtrRegs64RegClassID, // CS
1887 Hexagon::SysRegsRegClassID, // DIAG
1888 Hexagon::SysRegsRegClassID, // ELR
1889 Hexagon::SysRegsRegClassID, // EVB
1890 Hexagon::CtrRegs_and_V62RegsRegClassID, // FRAMEKEY
1891 Hexagon::CtrRegs_and_V62RegsRegClassID, // FRAMELIMIT
1892 Hexagon::GuestRegsRegClassID, // GELR
1893 Hexagon::GuestRegsRegClassID, // GOSP
1894 Hexagon::CtrRegsRegClassID, // GP
1895 Hexagon::GuestRegsRegClassID, // GPCYCLEHI
1896 Hexagon::GuestRegsRegClassID, // GPCYCLELO
1897 Hexagon::GuestRegsRegClassID, // GSR
1898 Hexagon::SysRegsRegClassID, // HTID
1899 Hexagon::SysRegsRegClassID, // IMASK
1900 Hexagon::SysRegsRegClassID, // ISDBEN
1901 Hexagon::SysRegsRegClassID, // ISDBGPR
1902 Hexagon::SysRegsRegClassID, // ISDBMBXIN
1903 Hexagon::SysRegsRegClassID, // ISDBMBXOUT
1904 Hexagon::SysRegsRegClassID, // ISDBST
1905 Hexagon::SysRegsRegClassID, // MODECTL
1906 Hexagon::CtrRegsRegClassID, // PC
1907 Hexagon::SysRegsRegClassID, // PCYCLEHI
1908 Hexagon::SysRegsRegClassID, // PCYCLELO
1909 Hexagon::CtrRegs64_and_V62RegsRegClassID, // PKTCOUNT
1910 Hexagon::CtrRegs_and_V62RegsRegClassID, // PKTCOUNTHI
1911 Hexagon::CtrRegs_and_V62RegsRegClassID, // PKTCOUNTLO
1912 Hexagon::SysRegsRegClassID, // PMUCFG
1913 Hexagon::SysRegsRegClassID, // PMUEVTCFG
1914 Hexagon::SysRegsRegClassID, // REV
1915 Hexagon::SysRegsRegClassID, // SSR
1916 Hexagon::SysRegsRegClassID, // STID
1917 Hexagon::SysRegsRegClassID, // SYSCFG
1918 Hexagon::CtrRegsRegClassID, // UGP
1919 Hexagon::CtrRegs64RegClassID, // UPCYCLE
1920 Hexagon::CtrRegsRegClassID, // UPCYCLEHI
1921 Hexagon::CtrRegsRegClassID, // UPCYCLELO
1922 Hexagon::CtrRegs_with_subreg_overflowRegClassID, // USR
1923 Hexagon::UsrBitsRegClassID, // USR_OVF
1924 Hexagon::CtrRegs64_and_V62RegsRegClassID, // UTIMER
1925 Hexagon::CtrRegs_and_V62RegsRegClassID, // UTIMERHI
1926 Hexagon::CtrRegs_and_V62RegsRegClassID, // UTIMERLO
1927 Hexagon::SysRegsRegClassID, // VID
1928 Hexagon::HvxVR_and_V65RegsRegClassID, // VTMP
1929 Hexagon::SysRegsRegClassID, // BADVA0
1930 Hexagon::SysRegsRegClassID, // BADVA1
1931 Hexagon::SysRegsRegClassID, // BRKPTCFG0
1932 Hexagon::SysRegsRegClassID, // BRKPTCFG1
1933 Hexagon::SysRegsRegClassID, // BRKPTPC0
1934 Hexagon::SysRegsRegClassID, // BRKPTPC1
1935 Hexagon::CtrRegsRegClassID, // C5
1936 Hexagon::CtrRegsRegClassID, // C8
1937 Hexagon::CtrRegsRegClassID, // CS0
1938 Hexagon::CtrRegsRegClassID, // CS1
1939 Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, // D0
1940 Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, // D1
1941 Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, // D2
1942 Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, // D3
1943 Hexagon::DoubleRegsRegClassID, // D4
1944 Hexagon::DoubleRegsRegClassID, // D5
1945 Hexagon::DoubleRegsRegClassID, // D6
1946 Hexagon::DoubleRegsRegClassID, // D7
1947 Hexagon::GeneralDoubleLow8RegsRegClassID, // D8
1948 Hexagon::GeneralDoubleLow8RegsRegClassID, // D9
1949 Hexagon::GeneralDoubleLow8RegsRegClassID, // D10
1950 Hexagon::GeneralDoubleLow8RegsRegClassID, // D11
1951 Hexagon::DoubleRegsRegClassID, // D12
1952 Hexagon::DoubleRegsRegClassID, // D13
1953 Hexagon::DoubleRegsRegClassID, // D14
1954 Hexagon::DoubleRegsRegClassID, // D15
1955 Hexagon::GuestRegsRegClassID, // G3
1956 Hexagon::GuestRegsRegClassID, // G4
1957 Hexagon::GuestRegsRegClassID, // G5
1958 Hexagon::GuestRegsRegClassID, // G6
1959 Hexagon::GuestRegsRegClassID, // G7
1960 Hexagon::GuestRegsRegClassID, // G8
1961 Hexagon::GuestRegsRegClassID, // G9
1962 Hexagon::GuestRegsRegClassID, // G10
1963 Hexagon::GuestRegsRegClassID, // G11
1964 Hexagon::GuestRegsRegClassID, // G12
1965 Hexagon::GuestRegsRegClassID, // G13
1966 Hexagon::GuestRegsRegClassID, // G14
1967 Hexagon::GuestRegsRegClassID, // G15
1968 Hexagon::GuestRegsRegClassID, // G20
1969 Hexagon::GuestRegsRegClassID, // G21
1970 Hexagon::GuestRegsRegClassID, // G22
1971 Hexagon::GuestRegsRegClassID, // G23
1972 Hexagon::GuestRegsRegClassID, // G30
1973 Hexagon::GuestRegsRegClassID, // G31
1974 Hexagon::GuestRegsRegClassID, // GPMUCNT0
1975 Hexagon::GuestRegsRegClassID, // GPMUCNT1
1976 Hexagon::GuestRegsRegClassID, // GPMUCNT2
1977 Hexagon::GuestRegsRegClassID, // GPMUCNT3
1978 Hexagon::GuestRegsRegClassID, // GPMUCNT4
1979 Hexagon::GuestRegsRegClassID, // GPMUCNT5
1980 Hexagon::GuestRegsRegClassID, // GPMUCNT6
1981 Hexagon::GuestRegsRegClassID, // GPMUCNT7
1982 Hexagon::SysRegsRegClassID, // ISDBCFG0
1983 Hexagon::SysRegsRegClassID, // ISDBCFG1
1984 Hexagon::CtrRegsRegClassID, // LC0
1985 Hexagon::CtrRegsRegClassID, // LC1
1986 Hexagon::ModRegsRegClassID, // M0
1987 Hexagon::ModRegsRegClassID, // M1
1988 Hexagon::PredRegsRegClassID, // P0
1989 Hexagon::PredRegsRegClassID, // P1
1990 Hexagon::PredRegsRegClassID, // P2
1991 Hexagon::PredRegsRegClassID, // P3
1992 Hexagon::SysRegsRegClassID, // PMUCNT0
1993 Hexagon::SysRegsRegClassID, // PMUCNT1
1994 Hexagon::SysRegsRegClassID, // PMUCNT2
1995 Hexagon::SysRegsRegClassID, // PMUCNT3
1996 Hexagon::HvxQRRegClassID, // Q0
1997 Hexagon::HvxQRRegClassID, // Q1
1998 Hexagon::HvxQRRegClassID, // Q2
1999 Hexagon::HvxQRRegClassID, // Q3
2000 Hexagon::IntRegsLow8RegClassID, // R0
2001 Hexagon::IntRegsLow8RegClassID, // R1
2002 Hexagon::IntRegsLow8RegClassID, // R2
2003 Hexagon::IntRegsLow8RegClassID, // R3
2004 Hexagon::IntRegsLow8RegClassID, // R4
2005 Hexagon::IntRegsLow8RegClassID, // R5
2006 Hexagon::IntRegsLow8RegClassID, // R6
2007 Hexagon::IntRegsLow8RegClassID, // R7
2008 Hexagon::IntRegsRegClassID, // R8
2009 Hexagon::IntRegsRegClassID, // R9
2010 Hexagon::IntRegsRegClassID, // R10
2011 Hexagon::IntRegsRegClassID, // R11
2012 Hexagon::IntRegsRegClassID, // R12
2013 Hexagon::IntRegsRegClassID, // R13
2014 Hexagon::IntRegsRegClassID, // R14
2015 Hexagon::IntRegsRegClassID, // R15
2016 Hexagon::GeneralSubRegsRegClassID, // R16
2017 Hexagon::GeneralSubRegsRegClassID, // R17
2018 Hexagon::GeneralSubRegsRegClassID, // R18
2019 Hexagon::GeneralSubRegsRegClassID, // R19
2020 Hexagon::GeneralSubRegsRegClassID, // R20
2021 Hexagon::GeneralSubRegsRegClassID, // R21
2022 Hexagon::GeneralSubRegsRegClassID, // R22
2023 Hexagon::GeneralSubRegsRegClassID, // R23
2024 Hexagon::IntRegsRegClassID, // R24
2025 Hexagon::IntRegsRegClassID, // R25
2026 Hexagon::IntRegsRegClassID, // R26
2027 Hexagon::IntRegsRegClassID, // R27
2028 Hexagon::IntRegsRegClassID, // R28
2029 Hexagon::IntRegsRegClassID, // R29
2030 Hexagon::IntRegsRegClassID, // R30
2031 Hexagon::IntRegsRegClassID, // R31
2032 Hexagon::SysRegsRegClassID, // S11
2033 Hexagon::SysRegsRegClassID, // S12
2034 Hexagon::SysRegsRegClassID, // S13
2035 Hexagon::SysRegsRegClassID, // S14
2036 Hexagon::SysRegsRegClassID, // S15
2037 Hexagon::SysRegsRegClassID, // S19
2038 Hexagon::SysRegsRegClassID, // S20
2039 Hexagon::SysRegsRegClassID, // S22
2040 Hexagon::SysRegsRegClassID, // S23
2041 Hexagon::SysRegsRegClassID, // S24
2042 Hexagon::SysRegsRegClassID, // S25
2043 Hexagon::SysRegsRegClassID, // S26
2044 Hexagon::SysRegsRegClassID, // S35
2045 Hexagon::SysRegsRegClassID, // S44
2046 Hexagon::SysRegsRegClassID, // S45
2047 Hexagon::SysRegsRegClassID, // S46
2048 Hexagon::SysRegsRegClassID, // S47
2049 Hexagon::SysRegsRegClassID, // S54
2050 Hexagon::SysRegsRegClassID, // S55
2051 Hexagon::SysRegsRegClassID, // S56
2052 Hexagon::SysRegsRegClassID, // S57
2053 Hexagon::SysRegsRegClassID, // S58
2054 Hexagon::SysRegsRegClassID, // S59
2055 Hexagon::SysRegsRegClassID, // S60
2056 Hexagon::SysRegsRegClassID, // S61
2057 Hexagon::SysRegsRegClassID, // S62
2058 Hexagon::SysRegsRegClassID, // S63
2059 Hexagon::SysRegsRegClassID, // S64
2060 Hexagon::SysRegsRegClassID, // S65
2061 Hexagon::SysRegsRegClassID, // S66
2062 Hexagon::SysRegsRegClassID, // S67
2063 Hexagon::SysRegsRegClassID, // S68
2064 Hexagon::SysRegsRegClassID, // S69
2065 Hexagon::SysRegsRegClassID, // S70
2066 Hexagon::SysRegsRegClassID, // S71
2067 Hexagon::SysRegsRegClassID, // S72
2068 Hexagon::SysRegsRegClassID, // S73
2069 Hexagon::SysRegsRegClassID, // S74
2070 Hexagon::SysRegsRegClassID, // S75
2071 Hexagon::SysRegsRegClassID, // S76
2072 Hexagon::SysRegsRegClassID, // S77
2073 Hexagon::SysRegsRegClassID, // S78
2074 Hexagon::SysRegsRegClassID, // S79
2075 Hexagon::SysRegsRegClassID, // S80
2076 Hexagon::CtrRegsRegClassID, // SA0
2077 Hexagon::CtrRegsRegClassID, // SA1
2078 Hexagon::SysRegsRegClassID, // SGP0
2079 Hexagon::SysRegsRegClassID, // SGP1
2080 Hexagon::HvxVRRegClassID, // V0
2081 Hexagon::HvxVRRegClassID, // V1
2082 Hexagon::HvxVRRegClassID, // V2
2083 Hexagon::HvxVRRegClassID, // V3
2084 Hexagon::HvxVRRegClassID, // V4
2085 Hexagon::HvxVRRegClassID, // V5
2086 Hexagon::HvxVRRegClassID, // V6
2087 Hexagon::HvxVRRegClassID, // V7
2088 Hexagon::HvxVRRegClassID, // V8
2089 Hexagon::HvxVRRegClassID, // V9
2090 Hexagon::HvxVRRegClassID, // V10
2091 Hexagon::HvxVRRegClassID, // V11
2092 Hexagon::HvxVRRegClassID, // V12
2093 Hexagon::HvxVRRegClassID, // V13
2094 Hexagon::HvxVRRegClassID, // V14
2095 Hexagon::HvxVRRegClassID, // V15
2096 Hexagon::HvxVRRegClassID, // V16
2097 Hexagon::HvxVRRegClassID, // V17
2098 Hexagon::HvxVRRegClassID, // V18
2099 Hexagon::HvxVRRegClassID, // V19
2100 Hexagon::HvxVRRegClassID, // V20
2101 Hexagon::HvxVRRegClassID, // V21
2102 Hexagon::HvxVRRegClassID, // V22
2103 Hexagon::HvxVRRegClassID, // V23
2104 Hexagon::HvxVRRegClassID, // V24
2105 Hexagon::HvxVRRegClassID, // V25
2106 Hexagon::HvxVRRegClassID, // V26
2107 Hexagon::HvxVRRegClassID, // V27
2108 Hexagon::HvxVRRegClassID, // V28
2109 Hexagon::HvxVRRegClassID, // V29
2110 Hexagon::HvxVRRegClassID, // V30
2111 Hexagon::HvxVRRegClassID, // V31
2112 InvalidRegClassID, // VF0
2113 InvalidRegClassID, // VF1
2114 InvalidRegClassID, // VF2
2115 InvalidRegClassID, // VF3
2116 InvalidRegClassID, // VF4
2117 InvalidRegClassID, // VF5
2118 InvalidRegClassID, // VF6
2119 InvalidRegClassID, // VF7
2120 InvalidRegClassID, // VF8
2121 InvalidRegClassID, // VF9
2122 InvalidRegClassID, // VF10
2123 InvalidRegClassID, // VF11
2124 InvalidRegClassID, // VF12
2125 InvalidRegClassID, // VF13
2126 InvalidRegClassID, // VF14
2127 InvalidRegClassID, // VF15
2128 InvalidRegClassID, // VF16
2129 InvalidRegClassID, // VF17
2130 InvalidRegClassID, // VF18
2131 InvalidRegClassID, // VF19
2132 InvalidRegClassID, // VF20
2133 InvalidRegClassID, // VF21
2134 InvalidRegClassID, // VF22
2135 InvalidRegClassID, // VF23
2136 InvalidRegClassID, // VF24
2137 InvalidRegClassID, // VF25
2138 InvalidRegClassID, // VF26
2139 InvalidRegClassID, // VF27
2140 InvalidRegClassID, // VF28
2141 InvalidRegClassID, // VF29
2142 InvalidRegClassID, // VF30
2143 InvalidRegClassID, // VF31
2144 InvalidRegClassID, // VFR0
2145 InvalidRegClassID, // VFR1
2146 InvalidRegClassID, // VFR2
2147 InvalidRegClassID, // VFR3
2148 InvalidRegClassID, // VFR4
2149 InvalidRegClassID, // VFR5
2150 InvalidRegClassID, // VFR6
2151 InvalidRegClassID, // VFR7
2152 InvalidRegClassID, // VFR8
2153 InvalidRegClassID, // VFR9
2154 InvalidRegClassID, // VFR10
2155 InvalidRegClassID, // VFR11
2156 InvalidRegClassID, // VFR12
2157 InvalidRegClassID, // VFR13
2158 InvalidRegClassID, // VFR14
2159 InvalidRegClassID, // VFR15
2160 InvalidRegClassID, // VFR16
2161 InvalidRegClassID, // VFR17
2162 InvalidRegClassID, // VFR18
2163 InvalidRegClassID, // VFR19
2164 InvalidRegClassID, // VFR20
2165 InvalidRegClassID, // VFR21
2166 InvalidRegClassID, // VFR22
2167 InvalidRegClassID, // VFR23
2168 InvalidRegClassID, // VFR24
2169 InvalidRegClassID, // VFR25
2170 InvalidRegClassID, // VFR26
2171 InvalidRegClassID, // VFR27
2172 InvalidRegClassID, // VFR28
2173 InvalidRegClassID, // VFR29
2174 InvalidRegClassID, // VFR30
2175 InvalidRegClassID, // VFR31
2176 Hexagon::HvxVQRRegClassID, // VQ0
2177 Hexagon::HvxVQRRegClassID, // VQ1
2178 Hexagon::HvxVQRRegClassID, // VQ2
2179 Hexagon::HvxVQRRegClassID, // VQ3
2180 Hexagon::HvxVQRRegClassID, // VQ4
2181 Hexagon::HvxVQRRegClassID, // VQ5
2182 Hexagon::HvxVQRRegClassID, // VQ6
2183 Hexagon::HvxVQRRegClassID, // VQ7
2184 Hexagon::HvxWRRegClassID, // W0
2185 Hexagon::HvxWRRegClassID, // W1
2186 Hexagon::HvxWRRegClassID, // W2
2187 Hexagon::HvxWRRegClassID, // W3
2188 Hexagon::HvxWRRegClassID, // W4
2189 Hexagon::HvxWRRegClassID, // W5
2190 Hexagon::HvxWRRegClassID, // W6
2191 Hexagon::HvxWRRegClassID, // W7
2192 Hexagon::HvxWRRegClassID, // W8
2193 Hexagon::HvxWRRegClassID, // W9
2194 Hexagon::HvxWRRegClassID, // W10
2195 Hexagon::HvxWRRegClassID, // W11
2196 Hexagon::HvxWRRegClassID, // W12
2197 Hexagon::HvxWRRegClassID, // W13
2198 Hexagon::HvxWRRegClassID, // W14
2199 Hexagon::HvxWRRegClassID, // W15
2200 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR0
2201 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR1
2202 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR2
2203 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR3
2204 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR4
2205 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR5
2206 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR6
2207 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR7
2208 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR8
2209 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR9
2210 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR10
2211 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR11
2212 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR12
2213 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR13
2214 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR14
2215 Hexagon::HvxWR_and_VectRegRevRegClassID, // WR15
2216 Hexagon::CtrRegs64RegClassID, // C1_0
2217 Hexagon::CtrRegs64RegClassID, // C3_2
2218 Hexagon::CtrRegs64RegClassID, // C5_4
2219 Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClassID, // C7_6
2220 Hexagon::CtrRegs64RegClassID, // C9_8
2221 Hexagon::CtrRegs64RegClassID, // C11_10
2222 Hexagon::CtrRegs64_and_V62RegsRegClassID, // C17_16
2223 Hexagon::GuestRegs64RegClassID, // G1_0
2224 Hexagon::GuestRegs64RegClassID, // G3_2
2225 Hexagon::GuestRegs64RegClassID, // G5_4
2226 Hexagon::GuestRegs64RegClassID, // G7_6
2227 Hexagon::GuestRegs64RegClassID, // G9_8
2228 Hexagon::GuestRegs64RegClassID, // G11_10
2229 Hexagon::GuestRegs64RegClassID, // G13_12
2230 Hexagon::GuestRegs64RegClassID, // G15_14
2231 Hexagon::GuestRegs64RegClassID, // G17_16
2232 Hexagon::GuestRegs64RegClassID, // G19_18
2233 Hexagon::GuestRegs64RegClassID, // G21_20
2234 Hexagon::GuestRegs64RegClassID, // G23_22
2235 Hexagon::GuestRegs64RegClassID, // G25_24
2236 Hexagon::GuestRegs64RegClassID, // G27_26
2237 Hexagon::GuestRegs64RegClassID, // G29_28
2238 Hexagon::GuestRegs64RegClassID, // G31_30
2239 Hexagon::CtrRegsRegClassID, // P3_0
2240 Hexagon::SysRegs64RegClassID, // S3_2
2241 Hexagon::SysRegs64RegClassID, // S5_4
2242 Hexagon::SysRegs64RegClassID, // S7_6
2243 Hexagon::SysRegs64RegClassID, // S9_8
2244 Hexagon::SysRegs64RegClassID, // S11_10
2245 Hexagon::SysRegs64RegClassID, // S13_12
2246 Hexagon::SysRegs64RegClassID, // S15_14
2247 Hexagon::SysRegs64RegClassID, // S17_16
2248 Hexagon::SysRegs64RegClassID, // S19_18
2249 Hexagon::SysRegs64RegClassID, // S21_20
2250 Hexagon::SysRegs64RegClassID, // S23_22
2251 Hexagon::SysRegs64RegClassID, // S25_24
2252 Hexagon::SysRegs64RegClassID, // S27_26
2253 Hexagon::SysRegs64RegClassID, // S29_28
2254 Hexagon::SysRegs64RegClassID, // S31_30
2255 Hexagon::SysRegs64RegClassID, // S33_32
2256 Hexagon::SysRegs64RegClassID, // S35_34
2257 Hexagon::SysRegs64RegClassID, // S37_36
2258 Hexagon::SysRegs64RegClassID, // S39_38
2259 Hexagon::SysRegs64RegClassID, // S41_40
2260 Hexagon::SysRegs64RegClassID, // S43_42
2261 Hexagon::SysRegs64RegClassID, // S45_44
2262 Hexagon::SysRegs64RegClassID, // S47_46
2263 Hexagon::SysRegs64RegClassID, // S49_48
2264 Hexagon::SysRegs64RegClassID, // S51_50
2265 Hexagon::SysRegs64RegClassID, // S53_52
2266 Hexagon::SysRegs64RegClassID, // S55_54
2267 Hexagon::SysRegs64RegClassID, // S57_56
2268 Hexagon::SysRegs64RegClassID, // S59_58
2269 Hexagon::SysRegs64RegClassID, // S61_60
2270 Hexagon::SysRegs64RegClassID, // S63_62
2271 Hexagon::SysRegs64RegClassID, // S65_64
2272 Hexagon::SysRegs64RegClassID, // S67_66
2273 Hexagon::SysRegs64RegClassID, // S69_68
2274 Hexagon::SysRegs64RegClassID, // S71_70
2275 Hexagon::SysRegs64RegClassID, // S73_72
2276 Hexagon::SysRegs64RegClassID, // S75_74
2277 Hexagon::SysRegs64RegClassID, // S77_76
2278 Hexagon::SysRegs64RegClassID, // S79_78
2279 Hexagon::SysRegs64RegClassID, // SGP1_0
2280 };
2281
2282 assert(Reg < ArrayRef(Mapping).size());
2283 unsigned RCID = Mapping[Reg.id()];
2284 if (RCID == InvalidRegClassID)
2285 return nullptr;
2286 return HexagonRegisterClasses[RCID];
2287}
2288extern const MCRegisterDesc HexagonRegDesc[];
2289extern const int16_t HexagonRegDiffLists[];
2290extern const LaneBitmask HexagonLaneMaskLists[];
2291extern const char HexagonRegStrings[];
2292extern const char HexagonRegClassStrings[];
2293extern const MCPhysReg HexagonRegUnitRoots[][2];
2294extern const uint16_t HexagonSubRegIdxLists[];
2295extern const uint16_t HexagonRegEncodingTable[];
2296// Hexagon Dwarf<->LLVM register mappings.
2297extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
2298extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;
2299
2300extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
2301extern const unsigned HexagonEHFlavour0Dwarf2LSize;
2302
2303extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
2304extern const unsigned HexagonDwarfFlavour0L2DwarfSize;
2305
2306extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
2307extern const unsigned HexagonEHFlavour0L2DwarfSize;
2308
2309
2310HexagonGenRegisterInfo::
2311HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2312 unsigned PC, unsigned HwMode)
2313 : TargetRegisterInfo(&HexagonRegInfoDesc, HexagonRegisterClasses,
2314 HexagonSubRegIndexStrings, HexagonSubRegIndexNameOffsets,
2315 HexagonSubRegIdxRangeTable, HexagonSubRegIndexLaneMaskTable,
2316
2317 LaneBitmask(0xFFFFFFFFFFFFFFFB), HexagonRegClassInfos, HexagonVTLists, HwMode) {
2318 InitMCRegisterInfo(D: HexagonRegDesc, NR: 398, RA, PC,
2319 C: HexagonMCRegisterClasses, NC: 29, RURoots: HexagonRegUnitRoots, NRU: 278, DL: HexagonRegDiffLists,
2320 RUMS: HexagonLaneMaskLists, Strings: HexagonRegStrings, ClassStrings: HexagonRegClassStrings, SubIndices: HexagonSubRegIdxLists, NumIndices: 12,
2321 RET: HexagonRegEncodingTable, RUI: nullptr);
2322
2323 switch (DwarfFlavour) {
2324 default:
2325 llvm_unreachable("Unknown DWARF flavour");
2326 case 0:
2327 mapDwarfRegsToLLVMRegs(Map: HexagonDwarfFlavour0Dwarf2L, Size: HexagonDwarfFlavour0Dwarf2LSize, isEH: false);
2328 break;
2329 }
2330 switch (EHFlavour) {
2331 default:
2332 llvm_unreachable("Unknown DWARF flavour");
2333 case 0:
2334 mapDwarfRegsToLLVMRegs(Map: HexagonEHFlavour0Dwarf2L, Size: HexagonEHFlavour0Dwarf2LSize, isEH: true);
2335 break;
2336 }
2337 switch (DwarfFlavour) {
2338 default:
2339 llvm_unreachable("Unknown DWARF flavour");
2340 case 0:
2341 mapLLVMRegsToDwarfRegs(Map: HexagonDwarfFlavour0L2Dwarf, Size: HexagonDwarfFlavour0L2DwarfSize, isEH: false);
2342 break;
2343 }
2344 switch (EHFlavour) {
2345 default:
2346 llvm_unreachable("Unknown DWARF flavour");
2347 case 0:
2348 mapLLVMRegsToDwarfRegs(Map: HexagonEHFlavour0L2Dwarf, Size: HexagonEHFlavour0L2DwarfSize, isEH: true);
2349 break;
2350 }
2351}
2352
2353static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
2354static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x00000000, 0x0000007e, 0x00000000, 0x0003ffc0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
2355
2356
2357ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
2358 static const uint32_t *const Masks[] = {
2359 HexagonCSR_RegMask,
2360 };
2361 return ArrayRef(Masks);
2362}
2363
2364bool HexagonGenRegisterInfo::
2365isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2366 return
2367 false;
2368}
2369
2370bool HexagonGenRegisterInfo::
2371isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
2372 return
2373 false;
2374}
2375
2376bool HexagonGenRegisterInfo::
2377isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2378 return
2379 false;
2380}
2381
2382bool HexagonGenRegisterInfo::
2383isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2384 return
2385 false;
2386}
2387
2388bool HexagonGenRegisterInfo::
2389isConstantPhysReg(MCRegister PhysReg) const {
2390 return
2391 false;
2392}
2393
2394ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
2395 static const char *Names[] = {
2396 "HexagonCSR",
2397 };
2398 return ArrayRef(Names);
2399}
2400
2401const HexagonFrameLowering *
2402HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2403 return static_cast<const HexagonFrameLowering *>(
2404 MF.getSubtarget().getFrameLowering());
2405}
2406
2407
2408} // namespace llvm
2409