1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass HexagonMCRegisterClasses[];
12
13static const MVT::SimpleValueType HexagonVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
16 /* 10 */ MVT::i64, MVT::Other,
17 /* 12 */ MVT::v64i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
18 /* 17 */ MVT::v128i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
19 /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
20 /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
21 /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v32f16, MVT::v32bf16, MVT::v16f32, MVT::Other,
22 /* 40 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v64f16, MVT::v64bf16, MVT::v32f32, MVT::Other,
23 /* 47 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v128f16, MVT::v128bf16, MVT::v64f32, MVT::Other,
24 /* 54 */ MVT::Untyped, MVT::Other,
25};
26
27#ifdef __GNUC__
28#pragma GCC diagnostic push
29#pragma GCC diagnostic ignored "-Woverlength-strings"
30#endif
31static constexpr char HexagonSubRegIndexStrings[] = {
32 /* 0 */ "wsub_hi_then_vsub_fake\000"
33 /* 23 */ "isub_hi\000"
34 /* 31 */ "wsub_hi_then_vsub_hi\000"
35 /* 52 */ "wsub_hi\000"
36 /* 60 */ "isub_lo\000"
37 /* 68 */ "wsub_hi_then_vsub_lo\000"
38 /* 89 */ "wsub_lo\000"
39 /* 97 */ "subreg_overflow\000"
40};
41#ifdef __GNUC__
42#pragma GCC diagnostic pop
43#endif
44
45
46static constexpr uint32_t HexagonSubRegIndexNameOffsets[] = {
47 23,
48 60,
49 97,
50 13,
51 44,
52 81,
53 52,
54 89,
55 0,
56 31,
57 68,
58};
59
60static const TargetRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRangeTable[] = {
61 { .Offset: 65535, .Size: 65535 },
62 { .Offset: 32, .Size: 32 }, // isub_hi
63 { .Offset: 0, .Size: 32 }, // isub_lo
64 { .Offset: 0, .Size: 1 }, // subreg_overflow
65 { .Offset: 65535, .Size: 65535 }, // vsub_fake
66 { .Offset: 65535, .Size: 65535 }, // vsub_hi
67 { .Offset: 65535, .Size: 65535 }, // vsub_lo
68 { .Offset: 65535, .Size: 65535 }, // wsub_hi
69 { .Offset: 65535, .Size: 65535 }, // wsub_lo
70 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_fake
71 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_hi
72 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_lo
73 { .Offset: 65535, .Size: 65535 },
74 { .Offset: 32, .Size: 32 }, // isub_hi
75 { .Offset: 0, .Size: 32 }, // isub_lo
76 { .Offset: 0, .Size: 1 }, // subreg_overflow
77 { .Offset: 65535, .Size: 65535 }, // vsub_fake
78 { .Offset: 65535, .Size: 65535 }, // vsub_hi
79 { .Offset: 65535, .Size: 65535 }, // vsub_lo
80 { .Offset: 65535, .Size: 65535 }, // wsub_hi
81 { .Offset: 65535, .Size: 65535 }, // wsub_lo
82 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_fake
83 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_hi
84 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_lo
85 { .Offset: 65535, .Size: 65535 },
86 { .Offset: 32, .Size: 32 }, // isub_hi
87 { .Offset: 0, .Size: 32 }, // isub_lo
88 { .Offset: 0, .Size: 1 }, // subreg_overflow
89 { .Offset: 65535, .Size: 65535 }, // vsub_fake
90 { .Offset: 65535, .Size: 65535 }, // vsub_hi
91 { .Offset: 65535, .Size: 65535 }, // vsub_lo
92 { .Offset: 65535, .Size: 65535 }, // wsub_hi
93 { .Offset: 65535, .Size: 65535 }, // wsub_lo
94 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_fake
95 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_hi
96 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_lo
97};
98
99
100static const LaneBitmask HexagonSubRegIndexLaneMaskTable[] = {
101 LaneBitmask::getAll(),
102 LaneBitmask(0x0000000000000001), // isub_hi
103 LaneBitmask(0x0000000000000002), // isub_lo
104 LaneBitmask(0x0000000000000004), // subreg_overflow
105 LaneBitmask(0x0000000000000008), // vsub_fake
106 LaneBitmask(0x0000000000000010), // vsub_hi
107 LaneBitmask(0x0000000000000020), // vsub_lo
108 LaneBitmask(0x00000000000001C0), // wsub_hi
109 LaneBitmask(0x0000000000000038), // wsub_lo
110 LaneBitmask(0x0000000000000040), // wsub_hi_then_vsub_fake
111 LaneBitmask(0x0000000000000080), // wsub_hi_then_vsub_hi
112 LaneBitmask(0x0000000000000100), // wsub_hi_then_vsub_lo
113 };
114
115
116
117static const TargetRegisterInfo::RegClassInfo HexagonRegClassInfos[] = {
118 // Mode = 0 (DefaultMode)
119 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*HexagonVTLists+*/.VTListOffset: 0 }, // UsrBits
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // SysRegs
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GuestRegs
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 22 }, // IntRegs
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // IntRegsLow8
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
128 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 2 }, // PredRegs
129 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
130 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // ModRegs
131 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
132 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V65Regs
133 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // SysRegs64
134 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 27 }, // DoubleRegs
135 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GuestRegs64
136 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // VectRegRev
137 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64
138 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
139 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
140 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
141 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
142 { .RegSize: 64, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 12 }, // HvxQR
143 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR
144 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR_and_V65Regs
145 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR
146 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR_and_VectRegRev
147 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 54 }, // HvxVQR
148 // Mode = 1 (Hvx64)
149 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*HexagonVTLists+*/.VTListOffset: 0 }, // UsrBits
150 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // SysRegs
151 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GuestRegs
152 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 22 }, // IntRegs
153 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs
154 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
155 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs
156 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // IntRegsLow8
157 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
158 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 2 }, // PredRegs
159 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
160 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // ModRegs
161 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
162 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V65Regs
163 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // SysRegs64
164 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 27 }, // DoubleRegs
165 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GuestRegs64
166 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // VectRegRev
167 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64
168 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
169 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
170 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
171 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
172 { .RegSize: 64, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 12 }, // HvxQR
173 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR
174 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 33 }, // HvxVR_and_V65Regs
175 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR
176 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxWR_and_VectRegRev
177 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 512, /*HexagonVTLists+*/.VTListOffset: 54 }, // HvxVQR
178 // Mode = 2 (Hvx128)
179 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*HexagonVTLists+*/.VTListOffset: 0 }, // UsrBits
180 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // SysRegs
181 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GuestRegs
182 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 22 }, // IntRegs
183 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs
184 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
185 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs
186 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // IntRegsLow8
187 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
188 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 2 }, // PredRegs
189 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
190 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // ModRegs
191 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
192 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*HexagonVTLists+*/.VTListOffset: 8 }, // V65Regs
193 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // SysRegs64
194 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 27 }, // DoubleRegs
195 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GuestRegs64
196 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // VectRegRev
197 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64
198 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
199 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
200 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
201 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*HexagonVTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
202 { .RegSize: 128, .SpillSize: 1024, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 17 }, // HvxQR
203 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxVR
204 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 40 }, // HvxVR_and_V65Regs
205 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 47 }, // HvxWR
206 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 47 }, // HvxWR_and_VectRegRev
207 { .RegSize: 4096, .SpillSize: 4096, .SpillAlignment: 1024, /*HexagonVTLists+*/.VTListOffset: 54 }, // HvxVQR
208};
209static const uint32_t UsrBitsSubClassMask[] = {
210 0x00000001,
211 0x00001000, // subreg_overflow
212};
213
214static const uint32_t SysRegsSubClassMask[] = {
215 0x00000002,
216 0x00004000, // isub_hi
217 0x00004000, // isub_lo
218};
219
220static const uint32_t GuestRegsSubClassMask[] = {
221 0x00000004,
222 0x00010000, // isub_hi
223 0x00010000, // isub_lo
224};
225
226static const uint32_t IntRegsSubClassMask[] = {
227 0x000000a8,
228 0x00188000, // isub_hi
229 0x00188000, // isub_lo
230};
231
232static const uint32_t CtrRegsSubClassMask[] = {
233 0x00001910,
234 0x00640400, // isub_hi
235 0x00640400, // isub_lo
236};
237
238static const uint32_t GeneralSubRegsSubClassMask[] = {
239 0x000000a0,
240 0x00180000, // isub_hi
241 0x00180000, // isub_lo
242};
243
244static const uint32_t V62RegsSubClassMask[] = {
245 0x00200540,
246 0x00200400, // isub_hi
247 0x00200400, // isub_lo
248};
249
250static const uint32_t IntRegsLow8SubClassMask[] = {
251 0x00000080,
252 0x00100000, // isub_hi
253 0x00100000, // isub_lo
254};
255
256static const uint32_t CtrRegs_and_V62RegsSubClassMask[] = {
257 0x00000100,
258 0x00200400, // isub_hi
259 0x00200400, // isub_lo
260};
261
262static const uint32_t PredRegsSubClassMask[] = {
263 0x00000200,
264};
265
266static const uint32_t V62Regs_with_isub_hiSubClassMask[] = {
267 0x00200400,
268};
269
270static const uint32_t ModRegsSubClassMask[] = {
271 0x00000800,
272 0x00400000, // isub_hi
273 0x00400000, // isub_lo
274};
275
276static const uint32_t CtrRegs_with_subreg_overflowSubClassMask[] = {
277 0x00001000,
278};
279
280static const uint32_t V65RegsSubClassMask[] = {
281 0x02002000,
282};
283
284static const uint32_t SysRegs64SubClassMask[] = {
285 0x00004000,
286};
287
288static const uint32_t DoubleRegsSubClassMask[] = {
289 0x00188000,
290};
291
292static const uint32_t GuestRegs64SubClassMask[] = {
293 0x00010000,
294};
295
296static const uint32_t VectRegRevSubClassMask[] = {
297 0x08020000,
298};
299
300static const uint32_t CtrRegs64SubClassMask[] = {
301 0x00640000,
302};
303
304static const uint32_t GeneralDoubleLow8RegsSubClassMask[] = {
305 0x00180000,
306};
307
308static const uint32_t DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask[] = {
309 0x00100000,
310};
311
312static const uint32_t CtrRegs64_and_V62RegsSubClassMask[] = {
313 0x00200000,
314};
315
316static const uint32_t CtrRegs64_with_isub_hi_in_ModRegsSubClassMask[] = {
317 0x00400000,
318};
319
320static const uint32_t HvxQRSubClassMask[] = {
321 0x00800000,
322};
323
324static const uint32_t HvxVRSubClassMask[] = {
325 0x03000000,
326 0x1c020000, // vsub_hi
327 0x1c020000, // vsub_lo
328 0x10000000, // wsub_hi_then_vsub_hi
329 0x10000000, // wsub_hi_then_vsub_lo
330};
331
332static const uint32_t HvxVR_and_V65RegsSubClassMask[] = {
333 0x02000000,
334};
335
336static const uint32_t HvxWRSubClassMask[] = {
337 0x0c000000,
338 0x10000000, // wsub_hi
339 0x10000000, // wsub_lo
340};
341
342static const uint32_t HvxWR_and_VectRegRevSubClassMask[] = {
343 0x08000000,
344};
345
346static const uint32_t HvxVQRSubClassMask[] = {
347 0x10000000,
348};
349
350static const uint16_t SuperRegIdxSeqs[] = {
351 /* 0 */ 1, 2, 0,
352 /* 3 */ 3, 0,
353 /* 5 */ 7, 8, 0,
354 /* 8 */ 5, 6, 10, 11, 0,
355};
356
357static unsigned const GeneralSubRegsSuperclasses[] = {
358 Hexagon::IntRegsRegClassID,
359};
360
361static unsigned const IntRegsLow8Superclasses[] = {
362 Hexagon::IntRegsRegClassID,
363 Hexagon::GeneralSubRegsRegClassID,
364};
365
366static unsigned const CtrRegs_and_V62RegsSuperclasses[] = {
367 Hexagon::CtrRegsRegClassID,
368 Hexagon::V62RegsRegClassID,
369};
370
371static unsigned const V62Regs_with_isub_hiSuperclasses[] = {
372 Hexagon::V62RegsRegClassID,
373};
374
375static unsigned const ModRegsSuperclasses[] = {
376 Hexagon::CtrRegsRegClassID,
377};
378
379static unsigned const CtrRegs_with_subreg_overflowSuperclasses[] = {
380 Hexagon::CtrRegsRegClassID,
381};
382
383static unsigned const GeneralDoubleLow8RegsSuperclasses[] = {
384 Hexagon::DoubleRegsRegClassID,
385};
386
387static unsigned const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
388 Hexagon::DoubleRegsRegClassID,
389 Hexagon::GeneralDoubleLow8RegsRegClassID,
390};
391
392static unsigned const CtrRegs64_and_V62RegsSuperclasses[] = {
393 Hexagon::V62RegsRegClassID,
394 Hexagon::V62Regs_with_isub_hiRegClassID,
395 Hexagon::CtrRegs64RegClassID,
396};
397
398static unsigned const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
399 Hexagon::CtrRegs64RegClassID,
400};
401
402static unsigned const HvxVR_and_V65RegsSuperclasses[] = {
403 Hexagon::V65RegsRegClassID,
404 Hexagon::HvxVRRegClassID,
405};
406
407static unsigned const HvxWR_and_VectRegRevSuperclasses[] = {
408 Hexagon::VectRegRevRegClassID,
409 Hexagon::HvxWRRegClassID,
410};
411
412namespace Hexagon {
413
414// Register class instances.
415 extern const TargetRegisterClass UsrBitsRegClass = {
416 .MC: &HexagonMCRegisterClasses[UsrBitsRegClassID],
417 .SubClassMask: UsrBitsSubClassMask,
418 .SuperRegIndices: SuperRegIdxSeqs + 3,
419 .LaneMask: LaneBitmask(0x0000000000000001),
420 .AllocationPriority: 0,
421 .GlobalPriority: false,
422 .TSFlags: 0x00, /* TSFlags */
423 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
424 .CoveredBySubRegs: false, /* CoveredBySubRegs */
425 .SuperClasses: nullptr, .SuperClassesSize: 0,
426 .OrderFunc: nullptr
427 };
428
429 extern const TargetRegisterClass SysRegsRegClass = {
430 .MC: &HexagonMCRegisterClasses[SysRegsRegClassID],
431 .SubClassMask: SysRegsSubClassMask,
432 .SuperRegIndices: SuperRegIdxSeqs + 0,
433 .LaneMask: LaneBitmask(0x0000000000000001),
434 .AllocationPriority: 0,
435 .GlobalPriority: false,
436 .TSFlags: 0x00, /* TSFlags */
437 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
438 .CoveredBySubRegs: false, /* CoveredBySubRegs */
439 .SuperClasses: nullptr, .SuperClassesSize: 0,
440 .OrderFunc: nullptr
441 };
442
443 extern const TargetRegisterClass GuestRegsRegClass = {
444 .MC: &HexagonMCRegisterClasses[GuestRegsRegClassID],
445 .SubClassMask: GuestRegsSubClassMask,
446 .SuperRegIndices: SuperRegIdxSeqs + 0,
447 .LaneMask: LaneBitmask(0x0000000000000001),
448 .AllocationPriority: 0,
449 .GlobalPriority: false,
450 .TSFlags: 0x00, /* TSFlags */
451 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
452 .CoveredBySubRegs: false, /* CoveredBySubRegs */
453 .SuperClasses: nullptr, .SuperClassesSize: 0,
454 .OrderFunc: nullptr
455 };
456
457 extern const TargetRegisterClass IntRegsRegClass = {
458 .MC: &HexagonMCRegisterClasses[IntRegsRegClassID],
459 .SubClassMask: IntRegsSubClassMask,
460 .SuperRegIndices: SuperRegIdxSeqs + 0,
461 .LaneMask: LaneBitmask(0x0000000000000001),
462 .AllocationPriority: 0,
463 .GlobalPriority: false,
464 .TSFlags: 0x00, /* TSFlags */
465 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
466 .CoveredBySubRegs: false, /* CoveredBySubRegs */
467 .SuperClasses: nullptr, .SuperClassesSize: 0,
468 .OrderFunc: nullptr
469 };
470
471 extern const TargetRegisterClass CtrRegsRegClass = {
472 .MC: &HexagonMCRegisterClasses[CtrRegsRegClassID],
473 .SubClassMask: CtrRegsSubClassMask,
474 .SuperRegIndices: SuperRegIdxSeqs + 0,
475 .LaneMask: LaneBitmask(0x0000000000000004),
476 .AllocationPriority: 0,
477 .GlobalPriority: false,
478 .TSFlags: 0x00, /* TSFlags */
479 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
480 .CoveredBySubRegs: false, /* CoveredBySubRegs */
481 .SuperClasses: nullptr, .SuperClassesSize: 0,
482 .OrderFunc: nullptr
483 };
484
485 extern const TargetRegisterClass GeneralSubRegsRegClass = {
486 .MC: &HexagonMCRegisterClasses[GeneralSubRegsRegClassID],
487 .SubClassMask: GeneralSubRegsSubClassMask,
488 .SuperRegIndices: SuperRegIdxSeqs + 0,
489 .LaneMask: LaneBitmask(0x0000000000000001),
490 .AllocationPriority: 0,
491 .GlobalPriority: false,
492 .TSFlags: 0x00, /* TSFlags */
493 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
494 .CoveredBySubRegs: false, /* CoveredBySubRegs */
495 .SuperClasses: GeneralSubRegsSuperclasses, .SuperClassesSize: 1,
496 .OrderFunc: nullptr
497 };
498
499 extern const TargetRegisterClass V62RegsRegClass = {
500 .MC: &HexagonMCRegisterClasses[V62RegsRegClassID],
501 .SubClassMask: V62RegsSubClassMask,
502 .SuperRegIndices: SuperRegIdxSeqs + 0,
503 .LaneMask: LaneBitmask(0x0000000000000003),
504 .AllocationPriority: 0,
505 .GlobalPriority: false,
506 .TSFlags: 0x00, /* TSFlags */
507 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
508 .CoveredBySubRegs: false, /* CoveredBySubRegs */
509 .SuperClasses: nullptr, .SuperClassesSize: 0,
510 .OrderFunc: nullptr
511 };
512
513 extern const TargetRegisterClass IntRegsLow8RegClass = {
514 .MC: &HexagonMCRegisterClasses[IntRegsLow8RegClassID],
515 .SubClassMask: IntRegsLow8SubClassMask,
516 .SuperRegIndices: SuperRegIdxSeqs + 0,
517 .LaneMask: LaneBitmask(0x0000000000000001),
518 .AllocationPriority: 0,
519 .GlobalPriority: false,
520 .TSFlags: 0x00, /* TSFlags */
521 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
522 .CoveredBySubRegs: false, /* CoveredBySubRegs */
523 .SuperClasses: IntRegsLow8Superclasses, .SuperClassesSize: 2,
524 .OrderFunc: nullptr
525 };
526
527 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
528 .MC: &HexagonMCRegisterClasses[CtrRegs_and_V62RegsRegClassID],
529 .SubClassMask: CtrRegs_and_V62RegsSubClassMask,
530 .SuperRegIndices: SuperRegIdxSeqs + 0,
531 .LaneMask: LaneBitmask(0x0000000000000001),
532 .AllocationPriority: 0,
533 .GlobalPriority: false,
534 .TSFlags: 0x00, /* TSFlags */
535 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
536 .CoveredBySubRegs: false, /* CoveredBySubRegs */
537 .SuperClasses: CtrRegs_and_V62RegsSuperclasses, .SuperClassesSize: 2,
538 .OrderFunc: nullptr
539 };
540
541 extern const TargetRegisterClass PredRegsRegClass = {
542 .MC: &HexagonMCRegisterClasses[PredRegsRegClassID],
543 .SubClassMask: PredRegsSubClassMask,
544 .SuperRegIndices: SuperRegIdxSeqs + 2,
545 .LaneMask: LaneBitmask(0x0000000000000001),
546 .AllocationPriority: 0,
547 .GlobalPriority: false,
548 .TSFlags: 0x00, /* TSFlags */
549 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
550 .CoveredBySubRegs: false, /* CoveredBySubRegs */
551 .SuperClasses: nullptr, .SuperClassesSize: 0,
552 .OrderFunc: nullptr
553 };
554
555 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
556 .MC: &HexagonMCRegisterClasses[V62Regs_with_isub_hiRegClassID],
557 .SubClassMask: V62Regs_with_isub_hiSubClassMask,
558 .SuperRegIndices: SuperRegIdxSeqs + 2,
559 .LaneMask: LaneBitmask(0x0000000000000003),
560 .AllocationPriority: 0,
561 .GlobalPriority: false,
562 .TSFlags: 0x00, /* TSFlags */
563 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
564 .CoveredBySubRegs: true, /* CoveredBySubRegs */
565 .SuperClasses: V62Regs_with_isub_hiSuperclasses, .SuperClassesSize: 1,
566 .OrderFunc: nullptr
567 };
568
569 extern const TargetRegisterClass ModRegsRegClass = {
570 .MC: &HexagonMCRegisterClasses[ModRegsRegClassID],
571 .SubClassMask: ModRegsSubClassMask,
572 .SuperRegIndices: SuperRegIdxSeqs + 0,
573 .LaneMask: LaneBitmask(0x0000000000000001),
574 .AllocationPriority: 0,
575 .GlobalPriority: false,
576 .TSFlags: 0x00, /* TSFlags */
577 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
578 .CoveredBySubRegs: false, /* CoveredBySubRegs */
579 .SuperClasses: ModRegsSuperclasses, .SuperClassesSize: 1,
580 .OrderFunc: nullptr
581 };
582
583 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
584 .MC: &HexagonMCRegisterClasses[CtrRegs_with_subreg_overflowRegClassID],
585 .SubClassMask: CtrRegs_with_subreg_overflowSubClassMask,
586 .SuperRegIndices: SuperRegIdxSeqs + 2,
587 .LaneMask: LaneBitmask(0x0000000000000004),
588 .AllocationPriority: 0,
589 .GlobalPriority: false,
590 .TSFlags: 0x00, /* TSFlags */
591 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
592 .CoveredBySubRegs: false, /* CoveredBySubRegs */
593 .SuperClasses: CtrRegs_with_subreg_overflowSuperclasses, .SuperClassesSize: 1,
594 .OrderFunc: nullptr
595 };
596
597 extern const TargetRegisterClass V65RegsRegClass = {
598 .MC: &HexagonMCRegisterClasses[V65RegsRegClassID],
599 .SubClassMask: V65RegsSubClassMask,
600 .SuperRegIndices: SuperRegIdxSeqs + 2,
601 .LaneMask: LaneBitmask(0x0000000000000001),
602 .AllocationPriority: 0,
603 .GlobalPriority: false,
604 .TSFlags: 0x00, /* TSFlags */
605 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
606 .CoveredBySubRegs: false, /* CoveredBySubRegs */
607 .SuperClasses: nullptr, .SuperClassesSize: 0,
608 .OrderFunc: nullptr
609 };
610
611 extern const TargetRegisterClass SysRegs64RegClass = {
612 .MC: &HexagonMCRegisterClasses[SysRegs64RegClassID],
613 .SubClassMask: SysRegs64SubClassMask,
614 .SuperRegIndices: SuperRegIdxSeqs + 2,
615 .LaneMask: LaneBitmask(0x0000000000000003),
616 .AllocationPriority: 0,
617 .GlobalPriority: false,
618 .TSFlags: 0x00, /* TSFlags */
619 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
620 .CoveredBySubRegs: true, /* CoveredBySubRegs */
621 .SuperClasses: nullptr, .SuperClassesSize: 0,
622 .OrderFunc: nullptr
623 };
624
625 extern const TargetRegisterClass DoubleRegsRegClass = {
626 .MC: &HexagonMCRegisterClasses[DoubleRegsRegClassID],
627 .SubClassMask: DoubleRegsSubClassMask,
628 .SuperRegIndices: SuperRegIdxSeqs + 2,
629 .LaneMask: LaneBitmask(0x0000000000000003),
630 .AllocationPriority: 0,
631 .GlobalPriority: false,
632 .TSFlags: 0x00, /* TSFlags */
633 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
634 .CoveredBySubRegs: true, /* CoveredBySubRegs */
635 .SuperClasses: nullptr, .SuperClassesSize: 0,
636 .OrderFunc: nullptr
637 };
638
639 extern const TargetRegisterClass GuestRegs64RegClass = {
640 .MC: &HexagonMCRegisterClasses[GuestRegs64RegClassID],
641 .SubClassMask: GuestRegs64SubClassMask,
642 .SuperRegIndices: SuperRegIdxSeqs + 2,
643 .LaneMask: LaneBitmask(0x0000000000000003),
644 .AllocationPriority: 0,
645 .GlobalPriority: false,
646 .TSFlags: 0x00, /* TSFlags */
647 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
648 .CoveredBySubRegs: true, /* CoveredBySubRegs */
649 .SuperClasses: nullptr, .SuperClassesSize: 0,
650 .OrderFunc: nullptr
651 };
652
653 extern const TargetRegisterClass VectRegRevRegClass = {
654 .MC: &HexagonMCRegisterClasses[VectRegRevRegClassID],
655 .SubClassMask: VectRegRevSubClassMask,
656 .SuperRegIndices: SuperRegIdxSeqs + 2,
657 .LaneMask: LaneBitmask(0x0000000000000038),
658 .AllocationPriority: 0,
659 .GlobalPriority: false,
660 .TSFlags: 0x00, /* TSFlags */
661 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
662 .CoveredBySubRegs: true, /* CoveredBySubRegs */
663 .SuperClasses: nullptr, .SuperClassesSize: 0,
664 .OrderFunc: nullptr
665 };
666
667 extern const TargetRegisterClass CtrRegs64RegClass = {
668 .MC: &HexagonMCRegisterClasses[CtrRegs64RegClassID],
669 .SubClassMask: CtrRegs64SubClassMask,
670 .SuperRegIndices: SuperRegIdxSeqs + 2,
671 .LaneMask: LaneBitmask(0x0000000000000003),
672 .AllocationPriority: 0,
673 .GlobalPriority: false,
674 .TSFlags: 0x00, /* TSFlags */
675 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
676 .CoveredBySubRegs: true, /* CoveredBySubRegs */
677 .SuperClasses: nullptr, .SuperClassesSize: 0,
678 .OrderFunc: nullptr
679 };
680
681 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
682 .MC: &HexagonMCRegisterClasses[GeneralDoubleLow8RegsRegClassID],
683 .SubClassMask: GeneralDoubleLow8RegsSubClassMask,
684 .SuperRegIndices: SuperRegIdxSeqs + 2,
685 .LaneMask: LaneBitmask(0x0000000000000003),
686 .AllocationPriority: 0,
687 .GlobalPriority: false,
688 .TSFlags: 0x00, /* TSFlags */
689 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
690 .CoveredBySubRegs: true, /* CoveredBySubRegs */
691 .SuperClasses: GeneralDoubleLow8RegsSuperclasses, .SuperClassesSize: 1,
692 .OrderFunc: nullptr
693 };
694
695 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
696 .MC: &HexagonMCRegisterClasses[DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID],
697 .SubClassMask: DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask,
698 .SuperRegIndices: SuperRegIdxSeqs + 2,
699 .LaneMask: LaneBitmask(0x0000000000000003),
700 .AllocationPriority: 0,
701 .GlobalPriority: false,
702 .TSFlags: 0x00, /* TSFlags */
703 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
704 .CoveredBySubRegs: true, /* CoveredBySubRegs */
705 .SuperClasses: DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses, .SuperClassesSize: 2,
706 .OrderFunc: nullptr
707 };
708
709 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
710 .MC: &HexagonMCRegisterClasses[CtrRegs64_and_V62RegsRegClassID],
711 .SubClassMask: CtrRegs64_and_V62RegsSubClassMask,
712 .SuperRegIndices: SuperRegIdxSeqs + 2,
713 .LaneMask: LaneBitmask(0x0000000000000003),
714 .AllocationPriority: 0,
715 .GlobalPriority: false,
716 .TSFlags: 0x00, /* TSFlags */
717 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
718 .CoveredBySubRegs: true, /* CoveredBySubRegs */
719 .SuperClasses: CtrRegs64_and_V62RegsSuperclasses, .SuperClassesSize: 3,
720 .OrderFunc: nullptr
721 };
722
723 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
724 .MC: &HexagonMCRegisterClasses[CtrRegs64_with_isub_hi_in_ModRegsRegClassID],
725 .SubClassMask: CtrRegs64_with_isub_hi_in_ModRegsSubClassMask,
726 .SuperRegIndices: SuperRegIdxSeqs + 2,
727 .LaneMask: LaneBitmask(0x0000000000000003),
728 .AllocationPriority: 0,
729 .GlobalPriority: false,
730 .TSFlags: 0x00, /* TSFlags */
731 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
732 .CoveredBySubRegs: true, /* CoveredBySubRegs */
733 .SuperClasses: CtrRegs64_with_isub_hi_in_ModRegsSuperclasses, .SuperClassesSize: 1,
734 .OrderFunc: nullptr
735 };
736
737 extern const TargetRegisterClass HvxQRRegClass = {
738 .MC: &HexagonMCRegisterClasses[HvxQRRegClassID],
739 .SubClassMask: HvxQRSubClassMask,
740 .SuperRegIndices: SuperRegIdxSeqs + 2,
741 .LaneMask: LaneBitmask(0x0000000000000001),
742 .AllocationPriority: 0,
743 .GlobalPriority: false,
744 .TSFlags: 0x00, /* TSFlags */
745 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
746 .CoveredBySubRegs: false, /* CoveredBySubRegs */
747 .SuperClasses: nullptr, .SuperClassesSize: 0,
748 .OrderFunc: nullptr
749 };
750
751 extern const TargetRegisterClass HvxVRRegClass = {
752 .MC: &HexagonMCRegisterClasses[HvxVRRegClassID],
753 .SubClassMask: HvxVRSubClassMask,
754 .SuperRegIndices: SuperRegIdxSeqs + 8,
755 .LaneMask: LaneBitmask(0x0000000000000001),
756 .AllocationPriority: 0,
757 .GlobalPriority: false,
758 .TSFlags: 0x00, /* TSFlags */
759 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
760 .CoveredBySubRegs: false, /* CoveredBySubRegs */
761 .SuperClasses: nullptr, .SuperClassesSize: 0,
762 .OrderFunc: nullptr
763 };
764
765 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
766 .MC: &HexagonMCRegisterClasses[HvxVR_and_V65RegsRegClassID],
767 .SubClassMask: HvxVR_and_V65RegsSubClassMask,
768 .SuperRegIndices: SuperRegIdxSeqs + 2,
769 .LaneMask: LaneBitmask(0x0000000000000001),
770 .AllocationPriority: 0,
771 .GlobalPriority: false,
772 .TSFlags: 0x00, /* TSFlags */
773 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
774 .CoveredBySubRegs: false, /* CoveredBySubRegs */
775 .SuperClasses: HvxVR_and_V65RegsSuperclasses, .SuperClassesSize: 2,
776 .OrderFunc: nullptr
777 };
778
779 extern const TargetRegisterClass HvxWRRegClass = {
780 .MC: &HexagonMCRegisterClasses[HvxWRRegClassID],
781 .SubClassMask: HvxWRSubClassMask,
782 .SuperRegIndices: SuperRegIdxSeqs + 5,
783 .LaneMask: LaneBitmask(0x0000000000000038),
784 .AllocationPriority: 0,
785 .GlobalPriority: false,
786 .TSFlags: 0x00, /* TSFlags */
787 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
788 .CoveredBySubRegs: true, /* CoveredBySubRegs */
789 .SuperClasses: nullptr, .SuperClassesSize: 0,
790 .OrderFunc: nullptr
791 };
792
793 extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass = {
794 .MC: &HexagonMCRegisterClasses[HvxWR_and_VectRegRevRegClassID],
795 .SubClassMask: HvxWR_and_VectRegRevSubClassMask,
796 .SuperRegIndices: SuperRegIdxSeqs + 2,
797 .LaneMask: LaneBitmask(0x0000000000000038),
798 .AllocationPriority: 0,
799 .GlobalPriority: false,
800 .TSFlags: 0x00, /* TSFlags */
801 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
802 .CoveredBySubRegs: true, /* CoveredBySubRegs */
803 .SuperClasses: HvxWR_and_VectRegRevSuperclasses, .SuperClassesSize: 2,
804 .OrderFunc: nullptr
805 };
806
807 extern const TargetRegisterClass HvxVQRRegClass = {
808 .MC: &HexagonMCRegisterClasses[HvxVQRRegClassID],
809 .SubClassMask: HvxVQRSubClassMask,
810 .SuperRegIndices: SuperRegIdxSeqs + 2,
811 .LaneMask: LaneBitmask(0x00000000000001F8),
812 .AllocationPriority: 0,
813 .GlobalPriority: false,
814 .TSFlags: 0x00, /* TSFlags */
815 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
816 .CoveredBySubRegs: true, /* CoveredBySubRegs */
817 .SuperClasses: nullptr, .SuperClassesSize: 0,
818 .OrderFunc: nullptr
819 };
820
821
822} // namespace Hexagon
823static const TargetRegisterClass *const HexagonRegisterClasses[] = {
824 &Hexagon::UsrBitsRegClass,
825 &Hexagon::SysRegsRegClass,
826 &Hexagon::GuestRegsRegClass,
827 &Hexagon::IntRegsRegClass,
828 &Hexagon::CtrRegsRegClass,
829 &Hexagon::GeneralSubRegsRegClass,
830 &Hexagon::V62RegsRegClass,
831 &Hexagon::IntRegsLow8RegClass,
832 &Hexagon::CtrRegs_and_V62RegsRegClass,
833 &Hexagon::PredRegsRegClass,
834 &Hexagon::V62Regs_with_isub_hiRegClass,
835 &Hexagon::ModRegsRegClass,
836 &Hexagon::CtrRegs_with_subreg_overflowRegClass,
837 &Hexagon::V65RegsRegClass,
838 &Hexagon::SysRegs64RegClass,
839 &Hexagon::DoubleRegsRegClass,
840 &Hexagon::GuestRegs64RegClass,
841 &Hexagon::VectRegRevRegClass,
842 &Hexagon::CtrRegs64RegClass,
843 &Hexagon::GeneralDoubleLow8RegsRegClass,
844 &Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass,
845 &Hexagon::CtrRegs64_and_V62RegsRegClass,
846 &Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClass,
847 &Hexagon::HvxQRRegClass,
848 &Hexagon::HvxVRRegClass,
849 &Hexagon::HvxVR_and_V65RegsRegClass,
850 &Hexagon::HvxWRRegClass,
851 &Hexagon::HvxWR_and_VectRegRevRegClass,
852 &Hexagon::HvxVQRRegClass,
853 };
854
855static const uint8_t HexagonCostPerUseTable[] = {
8560, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
857
858
859static const bool HexagonInAllocatableClassTable[] = {
860false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
861
862
863static const TargetRegisterInfoDesc HexagonRegInfoDesc = { // Extra Descriptors
864.CostPerUse: HexagonCostPerUseTable, .NumCosts: 1, .InAllocatableClass: HexagonInAllocatableClassTable};
865
866unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
867 static const uint8_t RowMap[11] = {
868 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
869 };
870 static const uint8_t Rows[2][11] = {
871 { 0, 0, 0, Hexagon::wsub_hi_then_vsub_fake, Hexagon::wsub_hi_then_vsub_hi, Hexagon::wsub_hi_then_vsub_lo, 0, 0, 0, 0, 0, },
872 { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
873 };
874
875 --IdxA; assert(IdxA < 11); (void) IdxA;
876 --IdxB; assert(IdxB < 11);
877 return Rows[RowMap[IdxA]][IdxB];
878}
879
880unsigned HexagonGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
881 static const uint8_t Table[11][11] = {
882 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
883 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
884 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
885 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
886 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
887 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
888 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
889 { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
890 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
891 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
892 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
893 };
894
895 --IdxA; assert(IdxA < 11);
896 --IdxB; assert(IdxB < 11);
897 return Table[IdxA][IdxB];
898 }
899
900 struct MaskRolOp {
901 LaneBitmask Mask;
902 uint8_t RotateLeft;
903 };
904 static const MaskRolOp LaneMaskComposeSequences[] = {
905 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
906 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
907 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
908 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
909 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
910 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
911 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 12
912 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 7 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 14
913 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 8 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 16
914 };
915 static const uint8_t CompositeSequences[] = {
916 0, // to isub_hi
917 2, // to isub_lo
918 4, // to subreg_overflow
919 6, // to vsub_fake
920 8, // to vsub_hi
921 10, // to vsub_lo
922 6, // to wsub_hi
923 0, // to wsub_lo
924 12, // to wsub_hi_then_vsub_fake
925 14, // to wsub_hi_then_vsub_hi
926 16 // to wsub_hi_then_vsub_lo
927 };
928
929LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
930 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
931 LaneBitmask Result;
932 for (const MaskRolOp *Ops =
933 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
934 Ops->Mask.any(); ++Ops) {
935 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
936 if (unsigned S = Ops->RotateLeft)
937 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
938 else
939 Result |= LaneBitmask(M);
940 }
941 return Result;
942}
943
944LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
945 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
946 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
947 LaneBitmask Result;
948 for (const MaskRolOp *Ops =
949 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
950 Ops->Mask.any(); ++Ops) {
951 LaneBitmask::Type M = LaneMask.getAsInteger();
952 if (unsigned S = Ops->RotateLeft)
953 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
954 else
955 Result |= LaneBitmask(M);
956 }
957 return Result;
958}
959
960const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
961 static constexpr uint8_t Table[29][11] = {
962 { // UsrBits
963 0, // isub_hi
964 0, // isub_lo
965 0, // subreg_overflow
966 0, // vsub_fake
967 0, // vsub_hi
968 0, // vsub_lo
969 0, // wsub_hi
970 0, // wsub_lo
971 0, // wsub_hi_then_vsub_fake
972 0, // wsub_hi_then_vsub_hi
973 0, // wsub_hi_then_vsub_lo
974 },
975 { // SysRegs
976 0, // isub_hi
977 0, // isub_lo
978 0, // subreg_overflow
979 0, // vsub_fake
980 0, // vsub_hi
981 0, // vsub_lo
982 0, // wsub_hi
983 0, // wsub_lo
984 0, // wsub_hi_then_vsub_fake
985 0, // wsub_hi_then_vsub_hi
986 0, // wsub_hi_then_vsub_lo
987 },
988 { // GuestRegs
989 0, // isub_hi
990 0, // isub_lo
991 0, // subreg_overflow
992 0, // vsub_fake
993 0, // vsub_hi
994 0, // vsub_lo
995 0, // wsub_hi
996 0, // wsub_lo
997 0, // wsub_hi_then_vsub_fake
998 0, // wsub_hi_then_vsub_hi
999 0, // wsub_hi_then_vsub_lo
1000 },
1001 { // IntRegs
1002 0, // isub_hi
1003 0, // isub_lo
1004 0, // subreg_overflow
1005 0, // vsub_fake
1006 0, // vsub_hi
1007 0, // vsub_lo
1008 0, // wsub_hi
1009 0, // wsub_lo
1010 0, // wsub_hi_then_vsub_fake
1011 0, // wsub_hi_then_vsub_hi
1012 0, // wsub_hi_then_vsub_lo
1013 },
1014 { // CtrRegs
1015 0, // isub_hi
1016 0, // isub_lo
1017 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
1018 0, // vsub_fake
1019 0, // vsub_hi
1020 0, // vsub_lo
1021 0, // wsub_hi
1022 0, // wsub_lo
1023 0, // wsub_hi_then_vsub_fake
1024 0, // wsub_hi_then_vsub_hi
1025 0, // wsub_hi_then_vsub_lo
1026 },
1027 { // GeneralSubRegs
1028 0, // isub_hi
1029 0, // isub_lo
1030 0, // subreg_overflow
1031 0, // vsub_fake
1032 0, // vsub_hi
1033 0, // vsub_lo
1034 0, // wsub_hi
1035 0, // wsub_lo
1036 0, // wsub_hi_then_vsub_fake
1037 0, // wsub_hi_then_vsub_hi
1038 0, // wsub_hi_then_vsub_lo
1039 },
1040 { // V62Regs
1041 11, // isub_hi -> V62Regs_with_isub_hi
1042 11, // isub_lo -> V62Regs_with_isub_hi
1043 0, // subreg_overflow
1044 0, // vsub_fake
1045 0, // vsub_hi
1046 0, // vsub_lo
1047 0, // wsub_hi
1048 0, // wsub_lo
1049 0, // wsub_hi_then_vsub_fake
1050 0, // wsub_hi_then_vsub_hi
1051 0, // wsub_hi_then_vsub_lo
1052 },
1053 { // IntRegsLow8
1054 0, // isub_hi
1055 0, // isub_lo
1056 0, // subreg_overflow
1057 0, // vsub_fake
1058 0, // vsub_hi
1059 0, // vsub_lo
1060 0, // wsub_hi
1061 0, // wsub_lo
1062 0, // wsub_hi_then_vsub_fake
1063 0, // wsub_hi_then_vsub_hi
1064 0, // wsub_hi_then_vsub_lo
1065 },
1066 { // CtrRegs_and_V62Regs
1067 0, // isub_hi
1068 0, // isub_lo
1069 0, // subreg_overflow
1070 0, // vsub_fake
1071 0, // vsub_hi
1072 0, // vsub_lo
1073 0, // wsub_hi
1074 0, // wsub_lo
1075 0, // wsub_hi_then_vsub_fake
1076 0, // wsub_hi_then_vsub_hi
1077 0, // wsub_hi_then_vsub_lo
1078 },
1079 { // PredRegs
1080 0, // isub_hi
1081 0, // isub_lo
1082 0, // subreg_overflow
1083 0, // vsub_fake
1084 0, // vsub_hi
1085 0, // vsub_lo
1086 0, // wsub_hi
1087 0, // wsub_lo
1088 0, // wsub_hi_then_vsub_fake
1089 0, // wsub_hi_then_vsub_hi
1090 0, // wsub_hi_then_vsub_lo
1091 },
1092 { // V62Regs_with_isub_hi
1093 11, // isub_hi -> V62Regs_with_isub_hi
1094 11, // isub_lo -> V62Regs_with_isub_hi
1095 0, // subreg_overflow
1096 0, // vsub_fake
1097 0, // vsub_hi
1098 0, // vsub_lo
1099 0, // wsub_hi
1100 0, // wsub_lo
1101 0, // wsub_hi_then_vsub_fake
1102 0, // wsub_hi_then_vsub_hi
1103 0, // wsub_hi_then_vsub_lo
1104 },
1105 { // ModRegs
1106 0, // isub_hi
1107 0, // isub_lo
1108 0, // subreg_overflow
1109 0, // vsub_fake
1110 0, // vsub_hi
1111 0, // vsub_lo
1112 0, // wsub_hi
1113 0, // wsub_lo
1114 0, // wsub_hi_then_vsub_fake
1115 0, // wsub_hi_then_vsub_hi
1116 0, // wsub_hi_then_vsub_lo
1117 },
1118 { // CtrRegs_with_subreg_overflow
1119 0, // isub_hi
1120 0, // isub_lo
1121 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
1122 0, // vsub_fake
1123 0, // vsub_hi
1124 0, // vsub_lo
1125 0, // wsub_hi
1126 0, // wsub_lo
1127 0, // wsub_hi_then_vsub_fake
1128 0, // wsub_hi_then_vsub_hi
1129 0, // wsub_hi_then_vsub_lo
1130 },
1131 { // V65Regs
1132 0, // isub_hi
1133 0, // isub_lo
1134 0, // subreg_overflow
1135 0, // vsub_fake
1136 0, // vsub_hi
1137 0, // vsub_lo
1138 0, // wsub_hi
1139 0, // wsub_lo
1140 0, // wsub_hi_then_vsub_fake
1141 0, // wsub_hi_then_vsub_hi
1142 0, // wsub_hi_then_vsub_lo
1143 },
1144 { // SysRegs64
1145 15, // isub_hi -> SysRegs64
1146 15, // isub_lo -> SysRegs64
1147 0, // subreg_overflow
1148 0, // vsub_fake
1149 0, // vsub_hi
1150 0, // vsub_lo
1151 0, // wsub_hi
1152 0, // wsub_lo
1153 0, // wsub_hi_then_vsub_fake
1154 0, // wsub_hi_then_vsub_hi
1155 0, // wsub_hi_then_vsub_lo
1156 },
1157 { // DoubleRegs
1158 16, // isub_hi -> DoubleRegs
1159 16, // isub_lo -> DoubleRegs
1160 0, // subreg_overflow
1161 0, // vsub_fake
1162 0, // vsub_hi
1163 0, // vsub_lo
1164 0, // wsub_hi
1165 0, // wsub_lo
1166 0, // wsub_hi_then_vsub_fake
1167 0, // wsub_hi_then_vsub_hi
1168 0, // wsub_hi_then_vsub_lo
1169 },
1170 { // GuestRegs64
1171 17, // isub_hi -> GuestRegs64
1172 17, // isub_lo -> GuestRegs64
1173 0, // subreg_overflow
1174 0, // vsub_fake
1175 0, // vsub_hi
1176 0, // vsub_lo
1177 0, // wsub_hi
1178 0, // wsub_lo
1179 0, // wsub_hi_then_vsub_fake
1180 0, // wsub_hi_then_vsub_hi
1181 0, // wsub_hi_then_vsub_lo
1182 },
1183 { // VectRegRev
1184 0, // isub_hi
1185 0, // isub_lo
1186 0, // subreg_overflow
1187 18, // vsub_fake -> VectRegRev
1188 18, // vsub_hi -> VectRegRev
1189 18, // vsub_lo -> VectRegRev
1190 0, // wsub_hi
1191 0, // wsub_lo
1192 0, // wsub_hi_then_vsub_fake
1193 0, // wsub_hi_then_vsub_hi
1194 0, // wsub_hi_then_vsub_lo
1195 },
1196 { // CtrRegs64
1197 19, // isub_hi -> CtrRegs64
1198 19, // isub_lo -> CtrRegs64
1199 0, // subreg_overflow
1200 0, // vsub_fake
1201 0, // vsub_hi
1202 0, // vsub_lo
1203 0, // wsub_hi
1204 0, // wsub_lo
1205 0, // wsub_hi_then_vsub_fake
1206 0, // wsub_hi_then_vsub_hi
1207 0, // wsub_hi_then_vsub_lo
1208 },
1209 { // GeneralDoubleLow8Regs
1210 20, // isub_hi -> GeneralDoubleLow8Regs
1211 20, // isub_lo -> GeneralDoubleLow8Regs
1212 0, // subreg_overflow
1213 0, // vsub_fake
1214 0, // vsub_hi
1215 0, // vsub_lo
1216 0, // wsub_hi
1217 0, // wsub_lo
1218 0, // wsub_hi_then_vsub_fake
1219 0, // wsub_hi_then_vsub_hi
1220 0, // wsub_hi_then_vsub_lo
1221 },
1222 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
1223 21, // isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
1224 21, // isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
1225 0, // subreg_overflow
1226 0, // vsub_fake
1227 0, // vsub_hi
1228 0, // vsub_lo
1229 0, // wsub_hi
1230 0, // wsub_lo
1231 0, // wsub_hi_then_vsub_fake
1232 0, // wsub_hi_then_vsub_hi
1233 0, // wsub_hi_then_vsub_lo
1234 },
1235 { // CtrRegs64_and_V62Regs
1236 22, // isub_hi -> CtrRegs64_and_V62Regs
1237 22, // isub_lo -> CtrRegs64_and_V62Regs
1238 0, // subreg_overflow
1239 0, // vsub_fake
1240 0, // vsub_hi
1241 0, // vsub_lo
1242 0, // wsub_hi
1243 0, // wsub_lo
1244 0, // wsub_hi_then_vsub_fake
1245 0, // wsub_hi_then_vsub_hi
1246 0, // wsub_hi_then_vsub_lo
1247 },
1248 { // CtrRegs64_with_isub_hi_in_ModRegs
1249 23, // isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
1250 23, // isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
1251 0, // subreg_overflow
1252 0, // vsub_fake
1253 0, // vsub_hi
1254 0, // vsub_lo
1255 0, // wsub_hi
1256 0, // wsub_lo
1257 0, // wsub_hi_then_vsub_fake
1258 0, // wsub_hi_then_vsub_hi
1259 0, // wsub_hi_then_vsub_lo
1260 },
1261 { // HvxQR
1262 0, // isub_hi
1263 0, // isub_lo
1264 0, // subreg_overflow
1265 0, // vsub_fake
1266 0, // vsub_hi
1267 0, // vsub_lo
1268 0, // wsub_hi
1269 0, // wsub_lo
1270 0, // wsub_hi_then_vsub_fake
1271 0, // wsub_hi_then_vsub_hi
1272 0, // wsub_hi_then_vsub_lo
1273 },
1274 { // HvxVR
1275 0, // isub_hi
1276 0, // isub_lo
1277 0, // subreg_overflow
1278 0, // vsub_fake
1279 0, // vsub_hi
1280 0, // vsub_lo
1281 0, // wsub_hi
1282 0, // wsub_lo
1283 0, // wsub_hi_then_vsub_fake
1284 0, // wsub_hi_then_vsub_hi
1285 0, // wsub_hi_then_vsub_lo
1286 },
1287 { // HvxVR_and_V65Regs
1288 0, // isub_hi
1289 0, // isub_lo
1290 0, // subreg_overflow
1291 0, // vsub_fake
1292 0, // vsub_hi
1293 0, // vsub_lo
1294 0, // wsub_hi
1295 0, // wsub_lo
1296 0, // wsub_hi_then_vsub_fake
1297 0, // wsub_hi_then_vsub_hi
1298 0, // wsub_hi_then_vsub_lo
1299 },
1300 { // HvxWR
1301 0, // isub_hi
1302 0, // isub_lo
1303 0, // subreg_overflow
1304 27, // vsub_fake -> HvxWR
1305 27, // vsub_hi -> HvxWR
1306 27, // vsub_lo -> HvxWR
1307 0, // wsub_hi
1308 0, // wsub_lo
1309 0, // wsub_hi_then_vsub_fake
1310 0, // wsub_hi_then_vsub_hi
1311 0, // wsub_hi_then_vsub_lo
1312 },
1313 { // HvxWR_and_VectRegRev
1314 0, // isub_hi
1315 0, // isub_lo
1316 0, // subreg_overflow
1317 28, // vsub_fake -> HvxWR_and_VectRegRev
1318 28, // vsub_hi -> HvxWR_and_VectRegRev
1319 28, // vsub_lo -> HvxWR_and_VectRegRev
1320 0, // wsub_hi
1321 0, // wsub_lo
1322 0, // wsub_hi_then_vsub_fake
1323 0, // wsub_hi_then_vsub_hi
1324 0, // wsub_hi_then_vsub_lo
1325 },
1326 { // HvxVQR
1327 0, // isub_hi
1328 0, // isub_lo
1329 0, // subreg_overflow
1330 29, // vsub_fake -> HvxVQR
1331 29, // vsub_hi -> HvxVQR
1332 29, // vsub_lo -> HvxVQR
1333 29, // wsub_hi -> HvxVQR
1334 29, // wsub_lo -> HvxVQR
1335 29, // wsub_hi_then_vsub_fake -> HvxVQR
1336 29, // wsub_hi_then_vsub_hi -> HvxVQR
1337 29, // wsub_hi_then_vsub_lo -> HvxVQR
1338 },
1339
1340 };
1341 assert(RC && "Missing regclass");
1342 if (!Idx) return RC;
1343 --Idx;
1344 assert(Idx < 11 && "Bad subreg");
1345 unsigned TV = Table[RC->getID()][Idx];
1346 return TV ? getRegClass(i: TV - 1) : nullptr;
1347}const TargetRegisterClass *HexagonGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1348 static constexpr uint8_t Table[29][11] = {
1349 { // UsrBits
1350 0, // UsrBits:isub_hi
1351 0, // UsrBits:isub_lo
1352 0, // UsrBits:subreg_overflow
1353 0, // UsrBits:vsub_fake
1354 0, // UsrBits:vsub_hi
1355 0, // UsrBits:vsub_lo
1356 0, // UsrBits:wsub_hi
1357 0, // UsrBits:wsub_lo
1358 0, // UsrBits:wsub_hi_then_vsub_fake
1359 0, // UsrBits:wsub_hi_then_vsub_hi
1360 0, // UsrBits:wsub_hi_then_vsub_lo
1361 },
1362 { // SysRegs
1363 0, // SysRegs:isub_hi
1364 0, // SysRegs:isub_lo
1365 0, // SysRegs:subreg_overflow
1366 0, // SysRegs:vsub_fake
1367 0, // SysRegs:vsub_hi
1368 0, // SysRegs:vsub_lo
1369 0, // SysRegs:wsub_hi
1370 0, // SysRegs:wsub_lo
1371 0, // SysRegs:wsub_hi_then_vsub_fake
1372 0, // SysRegs:wsub_hi_then_vsub_hi
1373 0, // SysRegs:wsub_hi_then_vsub_lo
1374 },
1375 { // GuestRegs
1376 0, // GuestRegs:isub_hi
1377 0, // GuestRegs:isub_lo
1378 0, // GuestRegs:subreg_overflow
1379 0, // GuestRegs:vsub_fake
1380 0, // GuestRegs:vsub_hi
1381 0, // GuestRegs:vsub_lo
1382 0, // GuestRegs:wsub_hi
1383 0, // GuestRegs:wsub_lo
1384 0, // GuestRegs:wsub_hi_then_vsub_fake
1385 0, // GuestRegs:wsub_hi_then_vsub_hi
1386 0, // GuestRegs:wsub_hi_then_vsub_lo
1387 },
1388 { // IntRegs
1389 0, // IntRegs:isub_hi
1390 0, // IntRegs:isub_lo
1391 0, // IntRegs:subreg_overflow
1392 0, // IntRegs:vsub_fake
1393 0, // IntRegs:vsub_hi
1394 0, // IntRegs:vsub_lo
1395 0, // IntRegs:wsub_hi
1396 0, // IntRegs:wsub_lo
1397 0, // IntRegs:wsub_hi_then_vsub_fake
1398 0, // IntRegs:wsub_hi_then_vsub_hi
1399 0, // IntRegs:wsub_hi_then_vsub_lo
1400 },
1401 { // CtrRegs
1402 0, // CtrRegs:isub_hi
1403 0, // CtrRegs:isub_lo
1404 1, // CtrRegs:subreg_overflow -> UsrBits
1405 0, // CtrRegs:vsub_fake
1406 0, // CtrRegs:vsub_hi
1407 0, // CtrRegs:vsub_lo
1408 0, // CtrRegs:wsub_hi
1409 0, // CtrRegs:wsub_lo
1410 0, // CtrRegs:wsub_hi_then_vsub_fake
1411 0, // CtrRegs:wsub_hi_then_vsub_hi
1412 0, // CtrRegs:wsub_hi_then_vsub_lo
1413 },
1414 { // GeneralSubRegs
1415 0, // GeneralSubRegs:isub_hi
1416 0, // GeneralSubRegs:isub_lo
1417 0, // GeneralSubRegs:subreg_overflow
1418 0, // GeneralSubRegs:vsub_fake
1419 0, // GeneralSubRegs:vsub_hi
1420 0, // GeneralSubRegs:vsub_lo
1421 0, // GeneralSubRegs:wsub_hi
1422 0, // GeneralSubRegs:wsub_lo
1423 0, // GeneralSubRegs:wsub_hi_then_vsub_fake
1424 0, // GeneralSubRegs:wsub_hi_then_vsub_hi
1425 0, // GeneralSubRegs:wsub_hi_then_vsub_lo
1426 },
1427 { // V62Regs
1428 9, // V62Regs:isub_hi -> CtrRegs_and_V62Regs
1429 9, // V62Regs:isub_lo -> CtrRegs_and_V62Regs
1430 0, // V62Regs:subreg_overflow
1431 0, // V62Regs:vsub_fake
1432 0, // V62Regs:vsub_hi
1433 0, // V62Regs:vsub_lo
1434 0, // V62Regs:wsub_hi
1435 0, // V62Regs:wsub_lo
1436 0, // V62Regs:wsub_hi_then_vsub_fake
1437 0, // V62Regs:wsub_hi_then_vsub_hi
1438 0, // V62Regs:wsub_hi_then_vsub_lo
1439 },
1440 { // IntRegsLow8
1441 0, // IntRegsLow8:isub_hi
1442 0, // IntRegsLow8:isub_lo
1443 0, // IntRegsLow8:subreg_overflow
1444 0, // IntRegsLow8:vsub_fake
1445 0, // IntRegsLow8:vsub_hi
1446 0, // IntRegsLow8:vsub_lo
1447 0, // IntRegsLow8:wsub_hi
1448 0, // IntRegsLow8:wsub_lo
1449 0, // IntRegsLow8:wsub_hi_then_vsub_fake
1450 0, // IntRegsLow8:wsub_hi_then_vsub_hi
1451 0, // IntRegsLow8:wsub_hi_then_vsub_lo
1452 },
1453 { // CtrRegs_and_V62Regs
1454 0, // CtrRegs_and_V62Regs:isub_hi
1455 0, // CtrRegs_and_V62Regs:isub_lo
1456 0, // CtrRegs_and_V62Regs:subreg_overflow
1457 0, // CtrRegs_and_V62Regs:vsub_fake
1458 0, // CtrRegs_and_V62Regs:vsub_hi
1459 0, // CtrRegs_and_V62Regs:vsub_lo
1460 0, // CtrRegs_and_V62Regs:wsub_hi
1461 0, // CtrRegs_and_V62Regs:wsub_lo
1462 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_fake
1463 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_hi
1464 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_lo
1465 },
1466 { // PredRegs
1467 0, // PredRegs:isub_hi
1468 0, // PredRegs:isub_lo
1469 0, // PredRegs:subreg_overflow
1470 0, // PredRegs:vsub_fake
1471 0, // PredRegs:vsub_hi
1472 0, // PredRegs:vsub_lo
1473 0, // PredRegs:wsub_hi
1474 0, // PredRegs:wsub_lo
1475 0, // PredRegs:wsub_hi_then_vsub_fake
1476 0, // PredRegs:wsub_hi_then_vsub_hi
1477 0, // PredRegs:wsub_hi_then_vsub_lo
1478 },
1479 { // V62Regs_with_isub_hi
1480 9, // V62Regs_with_isub_hi:isub_hi -> CtrRegs_and_V62Regs
1481 9, // V62Regs_with_isub_hi:isub_lo -> CtrRegs_and_V62Regs
1482 0, // V62Regs_with_isub_hi:subreg_overflow
1483 0, // V62Regs_with_isub_hi:vsub_fake
1484 0, // V62Regs_with_isub_hi:vsub_hi
1485 0, // V62Regs_with_isub_hi:vsub_lo
1486 0, // V62Regs_with_isub_hi:wsub_hi
1487 0, // V62Regs_with_isub_hi:wsub_lo
1488 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_fake
1489 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_hi
1490 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_lo
1491 },
1492 { // ModRegs
1493 0, // ModRegs:isub_hi
1494 0, // ModRegs:isub_lo
1495 0, // ModRegs:subreg_overflow
1496 0, // ModRegs:vsub_fake
1497 0, // ModRegs:vsub_hi
1498 0, // ModRegs:vsub_lo
1499 0, // ModRegs:wsub_hi
1500 0, // ModRegs:wsub_lo
1501 0, // ModRegs:wsub_hi_then_vsub_fake
1502 0, // ModRegs:wsub_hi_then_vsub_hi
1503 0, // ModRegs:wsub_hi_then_vsub_lo
1504 },
1505 { // CtrRegs_with_subreg_overflow
1506 0, // CtrRegs_with_subreg_overflow:isub_hi
1507 0, // CtrRegs_with_subreg_overflow:isub_lo
1508 1, // CtrRegs_with_subreg_overflow:subreg_overflow -> UsrBits
1509 0, // CtrRegs_with_subreg_overflow:vsub_fake
1510 0, // CtrRegs_with_subreg_overflow:vsub_hi
1511 0, // CtrRegs_with_subreg_overflow:vsub_lo
1512 0, // CtrRegs_with_subreg_overflow:wsub_hi
1513 0, // CtrRegs_with_subreg_overflow:wsub_lo
1514 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_fake
1515 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_hi
1516 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_lo
1517 },
1518 { // V65Regs
1519 0, // V65Regs:isub_hi
1520 0, // V65Regs:isub_lo
1521 0, // V65Regs:subreg_overflow
1522 0, // V65Regs:vsub_fake
1523 0, // V65Regs:vsub_hi
1524 0, // V65Regs:vsub_lo
1525 0, // V65Regs:wsub_hi
1526 0, // V65Regs:wsub_lo
1527 0, // V65Regs:wsub_hi_then_vsub_fake
1528 0, // V65Regs:wsub_hi_then_vsub_hi
1529 0, // V65Regs:wsub_hi_then_vsub_lo
1530 },
1531 { // SysRegs64
1532 2, // SysRegs64:isub_hi -> SysRegs
1533 2, // SysRegs64:isub_lo -> SysRegs
1534 0, // SysRegs64:subreg_overflow
1535 0, // SysRegs64:vsub_fake
1536 0, // SysRegs64:vsub_hi
1537 0, // SysRegs64:vsub_lo
1538 0, // SysRegs64:wsub_hi
1539 0, // SysRegs64:wsub_lo
1540 0, // SysRegs64:wsub_hi_then_vsub_fake
1541 0, // SysRegs64:wsub_hi_then_vsub_hi
1542 0, // SysRegs64:wsub_hi_then_vsub_lo
1543 },
1544 { // DoubleRegs
1545 4, // DoubleRegs:isub_hi -> IntRegs
1546 4, // DoubleRegs:isub_lo -> IntRegs
1547 0, // DoubleRegs:subreg_overflow
1548 0, // DoubleRegs:vsub_fake
1549 0, // DoubleRegs:vsub_hi
1550 0, // DoubleRegs:vsub_lo
1551 0, // DoubleRegs:wsub_hi
1552 0, // DoubleRegs:wsub_lo
1553 0, // DoubleRegs:wsub_hi_then_vsub_fake
1554 0, // DoubleRegs:wsub_hi_then_vsub_hi
1555 0, // DoubleRegs:wsub_hi_then_vsub_lo
1556 },
1557 { // GuestRegs64
1558 3, // GuestRegs64:isub_hi -> GuestRegs
1559 3, // GuestRegs64:isub_lo -> GuestRegs
1560 0, // GuestRegs64:subreg_overflow
1561 0, // GuestRegs64:vsub_fake
1562 0, // GuestRegs64:vsub_hi
1563 0, // GuestRegs64:vsub_lo
1564 0, // GuestRegs64:wsub_hi
1565 0, // GuestRegs64:wsub_lo
1566 0, // GuestRegs64:wsub_hi_then_vsub_fake
1567 0, // GuestRegs64:wsub_hi_then_vsub_hi
1568 0, // GuestRegs64:wsub_hi_then_vsub_lo
1569 },
1570 { // VectRegRev
1571 0, // VectRegRev:isub_hi
1572 0, // VectRegRev:isub_lo
1573 0, // VectRegRev:subreg_overflow
1574 0, // VectRegRev:vsub_fake
1575 25, // VectRegRev:vsub_hi -> HvxVR
1576 25, // VectRegRev:vsub_lo -> HvxVR
1577 0, // VectRegRev:wsub_hi
1578 0, // VectRegRev:wsub_lo
1579 0, // VectRegRev:wsub_hi_then_vsub_fake
1580 0, // VectRegRev:wsub_hi_then_vsub_hi
1581 0, // VectRegRev:wsub_hi_then_vsub_lo
1582 },
1583 { // CtrRegs64
1584 5, // CtrRegs64:isub_hi -> CtrRegs
1585 5, // CtrRegs64:isub_lo -> CtrRegs
1586 0, // CtrRegs64:subreg_overflow
1587 0, // CtrRegs64:vsub_fake
1588 0, // CtrRegs64:vsub_hi
1589 0, // CtrRegs64:vsub_lo
1590 0, // CtrRegs64:wsub_hi
1591 0, // CtrRegs64:wsub_lo
1592 0, // CtrRegs64:wsub_hi_then_vsub_fake
1593 0, // CtrRegs64:wsub_hi_then_vsub_hi
1594 0, // CtrRegs64:wsub_hi_then_vsub_lo
1595 },
1596 { // GeneralDoubleLow8Regs
1597 6, // GeneralDoubleLow8Regs:isub_hi -> GeneralSubRegs
1598 6, // GeneralDoubleLow8Regs:isub_lo -> GeneralSubRegs
1599 0, // GeneralDoubleLow8Regs:subreg_overflow
1600 0, // GeneralDoubleLow8Regs:vsub_fake
1601 0, // GeneralDoubleLow8Regs:vsub_hi
1602 0, // GeneralDoubleLow8Regs:vsub_lo
1603 0, // GeneralDoubleLow8Regs:wsub_hi
1604 0, // GeneralDoubleLow8Regs:wsub_lo
1605 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_fake
1606 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_hi
1607 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_lo
1608 },
1609 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
1610 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_hi -> IntRegsLow8
1611 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_lo -> IntRegsLow8
1612 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:subreg_overflow
1613 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_fake
1614 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_hi
1615 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_lo
1616 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi
1617 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_lo
1618 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_fake
1619 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_hi
1620 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_lo
1621 },
1622 { // CtrRegs64_and_V62Regs
1623 9, // CtrRegs64_and_V62Regs:isub_hi -> CtrRegs_and_V62Regs
1624 9, // CtrRegs64_and_V62Regs:isub_lo -> CtrRegs_and_V62Regs
1625 0, // CtrRegs64_and_V62Regs:subreg_overflow
1626 0, // CtrRegs64_and_V62Regs:vsub_fake
1627 0, // CtrRegs64_and_V62Regs:vsub_hi
1628 0, // CtrRegs64_and_V62Regs:vsub_lo
1629 0, // CtrRegs64_and_V62Regs:wsub_hi
1630 0, // CtrRegs64_and_V62Regs:wsub_lo
1631 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_fake
1632 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_hi
1633 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_lo
1634 },
1635 { // CtrRegs64_with_isub_hi_in_ModRegs
1636 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_hi -> ModRegs
1637 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_lo -> ModRegs
1638 0, // CtrRegs64_with_isub_hi_in_ModRegs:subreg_overflow
1639 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_fake
1640 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_hi
1641 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_lo
1642 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi
1643 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_lo
1644 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_fake
1645 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_hi
1646 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_lo
1647 },
1648 { // HvxQR
1649 0, // HvxQR:isub_hi
1650 0, // HvxQR:isub_lo
1651 0, // HvxQR:subreg_overflow
1652 0, // HvxQR:vsub_fake
1653 0, // HvxQR:vsub_hi
1654 0, // HvxQR:vsub_lo
1655 0, // HvxQR:wsub_hi
1656 0, // HvxQR:wsub_lo
1657 0, // HvxQR:wsub_hi_then_vsub_fake
1658 0, // HvxQR:wsub_hi_then_vsub_hi
1659 0, // HvxQR:wsub_hi_then_vsub_lo
1660 },
1661 { // HvxVR
1662 0, // HvxVR:isub_hi
1663 0, // HvxVR:isub_lo
1664 0, // HvxVR:subreg_overflow
1665 0, // HvxVR:vsub_fake
1666 0, // HvxVR:vsub_hi
1667 0, // HvxVR:vsub_lo
1668 0, // HvxVR:wsub_hi
1669 0, // HvxVR:wsub_lo
1670 0, // HvxVR:wsub_hi_then_vsub_fake
1671 0, // HvxVR:wsub_hi_then_vsub_hi
1672 0, // HvxVR:wsub_hi_then_vsub_lo
1673 },
1674 { // HvxVR_and_V65Regs
1675 0, // HvxVR_and_V65Regs:isub_hi
1676 0, // HvxVR_and_V65Regs:isub_lo
1677 0, // HvxVR_and_V65Regs:subreg_overflow
1678 0, // HvxVR_and_V65Regs:vsub_fake
1679 0, // HvxVR_and_V65Regs:vsub_hi
1680 0, // HvxVR_and_V65Regs:vsub_lo
1681 0, // HvxVR_and_V65Regs:wsub_hi
1682 0, // HvxVR_and_V65Regs:wsub_lo
1683 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_fake
1684 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_hi
1685 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_lo
1686 },
1687 { // HvxWR
1688 0, // HvxWR:isub_hi
1689 0, // HvxWR:isub_lo
1690 0, // HvxWR:subreg_overflow
1691 0, // HvxWR:vsub_fake
1692 25, // HvxWR:vsub_hi -> HvxVR
1693 25, // HvxWR:vsub_lo -> HvxVR
1694 0, // HvxWR:wsub_hi
1695 0, // HvxWR:wsub_lo
1696 0, // HvxWR:wsub_hi_then_vsub_fake
1697 0, // HvxWR:wsub_hi_then_vsub_hi
1698 0, // HvxWR:wsub_hi_then_vsub_lo
1699 },
1700 { // HvxWR_and_VectRegRev
1701 0, // HvxWR_and_VectRegRev:isub_hi
1702 0, // HvxWR_and_VectRegRev:isub_lo
1703 0, // HvxWR_and_VectRegRev:subreg_overflow
1704 0, // HvxWR_and_VectRegRev:vsub_fake
1705 25, // HvxWR_and_VectRegRev:vsub_hi -> HvxVR
1706 25, // HvxWR_and_VectRegRev:vsub_lo -> HvxVR
1707 0, // HvxWR_and_VectRegRev:wsub_hi
1708 0, // HvxWR_and_VectRegRev:wsub_lo
1709 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_fake
1710 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_hi
1711 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_lo
1712 },
1713 { // HvxVQR
1714 0, // HvxVQR:isub_hi
1715 0, // HvxVQR:isub_lo
1716 0, // HvxVQR:subreg_overflow
1717 0, // HvxVQR:vsub_fake
1718 25, // HvxVQR:vsub_hi -> HvxVR
1719 25, // HvxVQR:vsub_lo -> HvxVR
1720 27, // HvxVQR:wsub_hi -> HvxWR
1721 27, // HvxVQR:wsub_lo -> HvxWR
1722 0, // HvxVQR:wsub_hi_then_vsub_fake
1723 25, // HvxVQR:wsub_hi_then_vsub_hi -> HvxVR
1724 25, // HvxVQR:wsub_hi_then_vsub_lo -> HvxVR
1725 },
1726
1727 };
1728 assert(RC && "Missing regclass");
1729 if (!Idx) return RC;
1730 --Idx;
1731 assert(Idx < 11 && "Bad subreg");
1732 unsigned TV = Table[RC->getID()][Idx];
1733 return TV ? getRegClass(i: TV - 1) : nullptr;
1734}/// Get the weight in units of pressure for this register class.
1735const RegClassWeight &HexagonGenRegisterInfo::
1736getRegClassWeight(const TargetRegisterClass *RC) const {
1737 static const RegClassWeight RCWeightTable[] = {
1738 {.RegWeight: 0, .WeightLimit: 0}, // UsrBits
1739 {.RegWeight: 0, .WeightLimit: 0}, // SysRegs
1740 {.RegWeight: 0, .WeightLimit: 0}, // GuestRegs
1741 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
1742 {.RegWeight: 0, .WeightLimit: 6}, // CtrRegs
1743 {.RegWeight: 1, .WeightLimit: 16}, // GeneralSubRegs
1744 {.RegWeight: 0, .WeightLimit: 0}, // V62Regs
1745 {.RegWeight: 1, .WeightLimit: 8}, // IntRegsLow8
1746 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs_and_V62Regs
1747 {.RegWeight: 2, .WeightLimit: 8}, // PredRegs
1748 {.RegWeight: 0, .WeightLimit: 0}, // V62Regs_with_isub_hi
1749 {.RegWeight: 1, .WeightLimit: 2}, // ModRegs
1750 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs_with_subreg_overflow
1751 {.RegWeight: 1, .WeightLimit: 1}, // V65Regs
1752 {.RegWeight: 0, .WeightLimit: 0}, // SysRegs64
1753 {.RegWeight: 2, .WeightLimit: 32}, // DoubleRegs
1754 {.RegWeight: 0, .WeightLimit: 0}, // GuestRegs64
1755 {.RegWeight: 2, .WeightLimit: 32}, // VectRegRev
1756 {.RegWeight: 0, .WeightLimit: 6}, // CtrRegs64
1757 {.RegWeight: 2, .WeightLimit: 16}, // GeneralDoubleLow8Regs
1758 {.RegWeight: 2, .WeightLimit: 8}, // DoubleRegs_with_isub_hi_in_IntRegsLow8
1759 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs64_and_V62Regs
1760 {.RegWeight: 2, .WeightLimit: 2}, // CtrRegs64_with_isub_hi_in_ModRegs
1761 {.RegWeight: 1, .WeightLimit: 4}, // HvxQR
1762 {.RegWeight: 1, .WeightLimit: 33}, // HvxVR
1763 {.RegWeight: 1, .WeightLimit: 1}, // HvxVR_and_V65Regs
1764 {.RegWeight: 2, .WeightLimit: 32}, // HvxWR
1765 {.RegWeight: 2, .WeightLimit: 32}, // HvxWR_and_VectRegRev
1766 {.RegWeight: 4, .WeightLimit: 32}, // HvxVQR
1767 };
1768 return RCWeightTable[RC->getID()];
1769}
1770
1771/// Get the weight in units of pressure for this register unit.
1772unsigned HexagonGenRegisterInfo::
1773getRegUnitWeight(MCRegUnit RegUnit) const {
1774 assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
1775 // All register units have unit weight.
1776 return 1;
1777}
1778
1779
1780// Get the number of dimensions of register pressure.
1781unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
1782 return 8;
1783}
1784
1785// Get the name of this register unit pressure set.
1786const char *HexagonGenRegisterInfo::
1787getRegPressureSetName(unsigned Idx) const {
1788 static const char *PressureNameTable[] = {
1789 "HvxVR_and_V65Regs",
1790 "ModRegs",
1791 "HvxQR",
1792 "IntRegsLow8",
1793 "PredRegs",
1794 "GeneralSubRegs",
1795 "IntRegs",
1796 "HvxVR",
1797 };
1798 return PressureNameTable[Idx];
1799}
1800
1801// Get the register unit pressure limit for this dimension.
1802// This limit must be adjusted dynamically for reserved registers.
1803unsigned HexagonGenRegisterInfo::
1804getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1805 static const uint8_t PressureLimitTable[] = {
1806 1, // 0: HvxVR_and_V65Regs
1807 2, // 1: ModRegs
1808 4, // 2: HvxQR
1809 8, // 3: IntRegsLow8
1810 8, // 4: PredRegs
1811 16, // 5: GeneralSubRegs
1812 32, // 6: IntRegs
1813 33, // 7: HvxVR
1814 };
1815 return PressureLimitTable[Idx];
1816}
1817
1818/// Table of pressure sets per register class or unit.
1819static const int RCSetsTable[] = {
1820 /* 0 */ 1, -1,
1821 /* 2 */ 2, -1,
1822 /* 4 */ 4, -1,
1823 /* 6 */ 3, 5, 6, -1,
1824 /* 10 */ 0, 7, -1,
1825};
1826
1827/// Get the dimensions of register pressure impacted by this register class.
1828/// Returns a -1 terminated array of pressure set IDs
1829const int *HexagonGenRegisterInfo::
1830getRegClassPressureSets(const TargetRegisterClass *RC) const {
1831 static const uint8_t RCSetStartTable[] = {
1832 1,1,1,8,1,7,1,6,1,4,1,0,1,1,1,8,1,11,1,7,6,1,1,2,11,10,11,11,11,};
1833 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1834}
1835
1836/// Get the dimensions of register pressure impacted by this register unit.
1837/// Returns a -1 terminated array of pressure set IDs
1838const int *HexagonGenRegisterInfo::
1839getRegUnitPressureSets(MCRegUnit RegUnit) const {
1840 assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
1841 static const uint8_t RUSetStartTable[] = {
1842 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,4,4,4,4,4,4,4,4,1,1,1,1,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
1843 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1844}
1845
1846extern const MCRegisterDesc HexagonRegDesc[];
1847extern const int16_t HexagonRegDiffLists[];
1848extern const LaneBitmask HexagonLaneMaskLists[];
1849extern const char HexagonRegStrings[];
1850extern const char HexagonRegClassStrings[];
1851extern const MCPhysReg HexagonRegUnitRoots[][2];
1852extern const uint16_t HexagonSubRegIdxLists[];
1853extern const uint16_t HexagonRegEncodingTable[];
1854// Hexagon Dwarf<->LLVM register mappings.
1855extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
1856extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;
1857
1858extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
1859extern const unsigned HexagonEHFlavour0Dwarf2LSize;
1860
1861extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
1862extern const unsigned HexagonDwarfFlavour0L2DwarfSize;
1863
1864extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
1865extern const unsigned HexagonEHFlavour0L2DwarfSize;
1866
1867
1868HexagonGenRegisterInfo::
1869HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1870 unsigned PC, unsigned HwMode)
1871 : TargetRegisterInfo(&HexagonRegInfoDesc, HexagonRegisterClasses,
1872 HexagonSubRegIndexStrings, HexagonSubRegIndexNameOffsets,
1873 HexagonSubRegIdxRangeTable, HexagonSubRegIndexLaneMaskTable,
1874
1875 LaneBitmask(0xFFFFFFFFFFFFFFFB), HexagonRegClassInfos, HexagonVTLists, HwMode) {
1876 InitMCRegisterInfo(D: HexagonRegDesc, NR: 398, RA, PC,
1877 C: HexagonMCRegisterClasses, NC: 29, RURoots: HexagonRegUnitRoots, NRU: 278, DL: HexagonRegDiffLists,
1878 RUMS: HexagonLaneMaskLists, Strings: HexagonRegStrings, ClassStrings: HexagonRegClassStrings, SubIndices: HexagonSubRegIdxLists, NumIndices: 12,
1879 RET: HexagonRegEncodingTable, RUI: nullptr);
1880
1881 switch (DwarfFlavour) {
1882 default:
1883 llvm_unreachable("Unknown DWARF flavour");
1884 case 0:
1885 mapDwarfRegsToLLVMRegs(Map: HexagonDwarfFlavour0Dwarf2L, Size: HexagonDwarfFlavour0Dwarf2LSize, isEH: false);
1886 break;
1887 }
1888 switch (EHFlavour) {
1889 default:
1890 llvm_unreachable("Unknown DWARF flavour");
1891 case 0:
1892 mapDwarfRegsToLLVMRegs(Map: HexagonEHFlavour0Dwarf2L, Size: HexagonEHFlavour0Dwarf2LSize, isEH: true);
1893 break;
1894 }
1895 switch (DwarfFlavour) {
1896 default:
1897 llvm_unreachable("Unknown DWARF flavour");
1898 case 0:
1899 mapLLVMRegsToDwarfRegs(Map: HexagonDwarfFlavour0L2Dwarf, Size: HexagonDwarfFlavour0L2DwarfSize, isEH: false);
1900 break;
1901 }
1902 switch (EHFlavour) {
1903 default:
1904 llvm_unreachable("Unknown DWARF flavour");
1905 case 0:
1906 mapLLVMRegsToDwarfRegs(Map: HexagonEHFlavour0L2Dwarf, Size: HexagonEHFlavour0L2DwarfSize, isEH: true);
1907 break;
1908 }
1909}
1910
1911static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
1912static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x00000000, 0x0000007e, 0x00000000, 0x0003ffc0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
1913
1914
1915ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
1916 static const uint32_t *const Masks[] = {
1917 HexagonCSR_RegMask,
1918 };
1919 return ArrayRef(Masks);
1920}
1921
1922bool HexagonGenRegisterInfo::
1923isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1924 return
1925 false;
1926}
1927
1928bool HexagonGenRegisterInfo::
1929isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1930 return
1931 false;
1932}
1933
1934bool HexagonGenRegisterInfo::
1935isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1936 return
1937 false;
1938}
1939
1940bool HexagonGenRegisterInfo::
1941isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1942 return
1943 false;
1944}
1945
1946bool HexagonGenRegisterInfo::
1947isConstantPhysReg(MCRegister PhysReg) const {
1948 return
1949 false;
1950}
1951
1952ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
1953 static const char *Names[] = {
1954 "HexagonCSR",
1955 };
1956 return ArrayRef(Names);
1957}
1958
1959const HexagonFrameLowering *
1960HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1961 return static_cast<const HexagonFrameLowering *>(
1962 MF.getSubtarget().getFrameLowering());
1963}
1964
1965
1966} // namespace llvm
1967