1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass HexagonMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
16 /* 10 */ MVT::i64, MVT::Other,
17 /* 12 */ MVT::v64i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
18 /* 17 */ MVT::v128i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
19 /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
20 /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
21 /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v32f16, MVT::v32bf16, MVT::v16f32, MVT::Other,
22 /* 40 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v64f16, MVT::v64bf16, MVT::v32f32, MVT::Other,
23 /* 47 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v128f16, MVT::v128bf16, MVT::v64f32, MVT::Other,
24 /* 54 */ MVT::Untyped, MVT::Other,
25};
26
27static const char *SubRegIndexNameTable[] = { "isub_hi", "isub_lo", "subreg_overflow", "vsub_fake", "vsub_hi", "vsub_lo", "wsub_hi", "wsub_lo", "wsub_hi_then_vsub_fake", "wsub_hi_then_vsub_hi", "wsub_hi_then_vsub_lo", "" };
28
29static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
30 { .Offset: 65535, .Size: 65535 },
31 { .Offset: 32, .Size: 32 }, // isub_hi
32 { .Offset: 0, .Size: 32 }, // isub_lo
33 { .Offset: 0, .Size: 1 }, // subreg_overflow
34 { .Offset: 65535, .Size: 65535 }, // vsub_fake
35 { .Offset: 65535, .Size: 65535 }, // vsub_hi
36 { .Offset: 65535, .Size: 65535 }, // vsub_lo
37 { .Offset: 65535, .Size: 65535 }, // wsub_hi
38 { .Offset: 65535, .Size: 65535 }, // wsub_lo
39 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_fake
40 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_hi
41 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_lo
42 { .Offset: 65535, .Size: 65535 },
43 { .Offset: 32, .Size: 32 }, // isub_hi
44 { .Offset: 0, .Size: 32 }, // isub_lo
45 { .Offset: 0, .Size: 1 }, // subreg_overflow
46 { .Offset: 65535, .Size: 65535 }, // vsub_fake
47 { .Offset: 65535, .Size: 65535 }, // vsub_hi
48 { .Offset: 65535, .Size: 65535 }, // vsub_lo
49 { .Offset: 65535, .Size: 65535 }, // wsub_hi
50 { .Offset: 65535, .Size: 65535 }, // wsub_lo
51 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_fake
52 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_hi
53 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_lo
54 { .Offset: 65535, .Size: 65535 },
55 { .Offset: 32, .Size: 32 }, // isub_hi
56 { .Offset: 0, .Size: 32 }, // isub_lo
57 { .Offset: 0, .Size: 1 }, // subreg_overflow
58 { .Offset: 65535, .Size: 65535 }, // vsub_fake
59 { .Offset: 65535, .Size: 65535 }, // vsub_hi
60 { .Offset: 65535, .Size: 65535 }, // vsub_lo
61 { .Offset: 65535, .Size: 65535 }, // wsub_hi
62 { .Offset: 65535, .Size: 65535 }, // wsub_lo
63 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_fake
64 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_hi
65 { .Offset: 65535, .Size: 65535 }, // wsub_hi_then_vsub_lo
66};
67
68
69static const LaneBitmask SubRegIndexLaneMaskTable[] = {
70 LaneBitmask::getAll(),
71 LaneBitmask(0x0000000000000001), // isub_hi
72 LaneBitmask(0x0000000000000002), // isub_lo
73 LaneBitmask(0x0000000000000004), // subreg_overflow
74 LaneBitmask(0x0000000000000008), // vsub_fake
75 LaneBitmask(0x0000000000000010), // vsub_hi
76 LaneBitmask(0x0000000000000020), // vsub_lo
77 LaneBitmask(0x00000000000001C0), // wsub_hi
78 LaneBitmask(0x0000000000000038), // wsub_lo
79 LaneBitmask(0x0000000000000040), // wsub_hi_then_vsub_fake
80 LaneBitmask(0x0000000000000080), // wsub_hi_then_vsub_hi
81 LaneBitmask(0x0000000000000100), // wsub_hi_then_vsub_lo
82 };
83
84
85
86static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
87 // Mode = 0 (Default)
88 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 0 }, // UsrBits
89 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // SysRegs
90 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // GuestRegs
91 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 22 }, // IntRegs
92 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // CtrRegs
93 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
94 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // V62Regs
95 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // IntRegsLow8
96 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
97 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // PredRegs
98 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
99 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // ModRegs
100 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // V65Regs
102 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // SysRegs64
103 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 27 }, // DoubleRegs
104 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // GuestRegs64
105 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // VectRegRev
106 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // CtrRegs64
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
110 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
111 { .RegSize: 64, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 12 }, // HvxQR
112 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 33 }, // HvxVR
113 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 33 }, // HvxVR_and_V65Regs
114 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 40 }, // HvxWR
115 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 40 }, // HvxWR_and_VectRegRev
116 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 54 }, // HvxVQR
117 // Mode = 1 (Hvx64)
118 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 0 }, // UsrBits
119 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // SysRegs
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // GuestRegs
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 22 }, // IntRegs
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // CtrRegs
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // V62Regs
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // IntRegsLow8
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // PredRegs
128 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
129 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // ModRegs
130 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
131 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // V65Regs
132 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // SysRegs64
133 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 27 }, // DoubleRegs
134 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // GuestRegs64
135 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // VectRegRev
136 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // CtrRegs64
137 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
138 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
139 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
140 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
141 { .RegSize: 64, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 12 }, // HvxQR
142 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 33 }, // HvxVR
143 { .RegSize: 512, .SpillSize: 512, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 33 }, // HvxVR_and_V65Regs
144 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 40 }, // HvxWR
145 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 40 }, // HvxWR_and_VectRegRev
146 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 512, /*VTLists+*/.VTListOffset: 54 }, // HvxVQR
147 // Mode = 2 (Hvx128)
148 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 0 }, // UsrBits
149 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // SysRegs
150 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // GuestRegs
151 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 22 }, // IntRegs
152 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // CtrRegs
153 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // GeneralSubRegs
154 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // V62Regs
155 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // IntRegsLow8
156 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // CtrRegs_and_V62Regs
157 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // PredRegs
158 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // V62Regs_with_isub_hi
159 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // ModRegs
160 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // CtrRegs_with_subreg_overflow
161 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 8 }, // V65Regs
162 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // SysRegs64
163 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 27 }, // DoubleRegs
164 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // GuestRegs64
165 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // VectRegRev
166 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // CtrRegs64
167 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // GeneralDoubleLow8Regs
168 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
169 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // CtrRegs64_and_V62Regs
170 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 10 }, // CtrRegs64_with_isub_hi_in_ModRegs
171 { .RegSize: 128, .SpillSize: 1024, .SpillAlignment: 1024, /*VTLists+*/.VTListOffset: 17 }, // HvxQR
172 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 1024, /*VTLists+*/.VTListOffset: 40 }, // HvxVR
173 { .RegSize: 1024, .SpillSize: 1024, .SpillAlignment: 1024, /*VTLists+*/.VTListOffset: 40 }, // HvxVR_and_V65Regs
174 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 1024, /*VTLists+*/.VTListOffset: 47 }, // HvxWR
175 { .RegSize: 2048, .SpillSize: 2048, .SpillAlignment: 1024, /*VTLists+*/.VTListOffset: 47 }, // HvxWR_and_VectRegRev
176 { .RegSize: 4096, .SpillSize: 4096, .SpillAlignment: 1024, /*VTLists+*/.VTListOffset: 54 }, // HvxVQR
177};
178static const uint32_t UsrBitsSubClassMask[] = {
179 0x00000001,
180 0x00001000, // subreg_overflow
181};
182
183static const uint32_t SysRegsSubClassMask[] = {
184 0x00000002,
185 0x00004000, // isub_hi
186 0x00004000, // isub_lo
187};
188
189static const uint32_t GuestRegsSubClassMask[] = {
190 0x00000004,
191 0x00010000, // isub_hi
192 0x00010000, // isub_lo
193};
194
195static const uint32_t IntRegsSubClassMask[] = {
196 0x000000a8,
197 0x00188000, // isub_hi
198 0x00188000, // isub_lo
199};
200
201static const uint32_t CtrRegsSubClassMask[] = {
202 0x00001910,
203 0x00640400, // isub_hi
204 0x00640400, // isub_lo
205};
206
207static const uint32_t GeneralSubRegsSubClassMask[] = {
208 0x000000a0,
209 0x00180000, // isub_hi
210 0x00180000, // isub_lo
211};
212
213static const uint32_t V62RegsSubClassMask[] = {
214 0x00200540,
215 0x00200400, // isub_hi
216 0x00200400, // isub_lo
217};
218
219static const uint32_t IntRegsLow8SubClassMask[] = {
220 0x00000080,
221 0x00100000, // isub_hi
222 0x00100000, // isub_lo
223};
224
225static const uint32_t CtrRegs_and_V62RegsSubClassMask[] = {
226 0x00000100,
227 0x00200400, // isub_hi
228 0x00200400, // isub_lo
229};
230
231static const uint32_t PredRegsSubClassMask[] = {
232 0x00000200,
233};
234
235static const uint32_t V62Regs_with_isub_hiSubClassMask[] = {
236 0x00200400,
237};
238
239static const uint32_t ModRegsSubClassMask[] = {
240 0x00000800,
241 0x00400000, // isub_hi
242 0x00400000, // isub_lo
243};
244
245static const uint32_t CtrRegs_with_subreg_overflowSubClassMask[] = {
246 0x00001000,
247};
248
249static const uint32_t V65RegsSubClassMask[] = {
250 0x02002000,
251};
252
253static const uint32_t SysRegs64SubClassMask[] = {
254 0x00004000,
255};
256
257static const uint32_t DoubleRegsSubClassMask[] = {
258 0x00188000,
259};
260
261static const uint32_t GuestRegs64SubClassMask[] = {
262 0x00010000,
263};
264
265static const uint32_t VectRegRevSubClassMask[] = {
266 0x08020000,
267};
268
269static const uint32_t CtrRegs64SubClassMask[] = {
270 0x00640000,
271};
272
273static const uint32_t GeneralDoubleLow8RegsSubClassMask[] = {
274 0x00180000,
275};
276
277static const uint32_t DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask[] = {
278 0x00100000,
279};
280
281static const uint32_t CtrRegs64_and_V62RegsSubClassMask[] = {
282 0x00200000,
283};
284
285static const uint32_t CtrRegs64_with_isub_hi_in_ModRegsSubClassMask[] = {
286 0x00400000,
287};
288
289static const uint32_t HvxQRSubClassMask[] = {
290 0x00800000,
291};
292
293static const uint32_t HvxVRSubClassMask[] = {
294 0x03000000,
295 0x1c020000, // vsub_hi
296 0x1c020000, // vsub_lo
297 0x10000000, // wsub_hi_then_vsub_hi
298 0x10000000, // wsub_hi_then_vsub_lo
299};
300
301static const uint32_t HvxVR_and_V65RegsSubClassMask[] = {
302 0x02000000,
303};
304
305static const uint32_t HvxWRSubClassMask[] = {
306 0x0c000000,
307 0x10000000, // wsub_hi
308 0x10000000, // wsub_lo
309};
310
311static const uint32_t HvxWR_and_VectRegRevSubClassMask[] = {
312 0x08000000,
313};
314
315static const uint32_t HvxVQRSubClassMask[] = {
316 0x10000000,
317};
318
319static const uint16_t SuperRegIdxSeqs[] = {
320 /* 0 */ 1, 2, 0,
321 /* 3 */ 3, 0,
322 /* 5 */ 7, 8, 0,
323 /* 8 */ 5, 6, 10, 11, 0,
324};
325
326static unsigned const GeneralSubRegsSuperclasses[] = {
327 Hexagon::IntRegsRegClassID,
328};
329
330static unsigned const IntRegsLow8Superclasses[] = {
331 Hexagon::IntRegsRegClassID,
332 Hexagon::GeneralSubRegsRegClassID,
333};
334
335static unsigned const CtrRegs_and_V62RegsSuperclasses[] = {
336 Hexagon::CtrRegsRegClassID,
337 Hexagon::V62RegsRegClassID,
338};
339
340static unsigned const V62Regs_with_isub_hiSuperclasses[] = {
341 Hexagon::V62RegsRegClassID,
342};
343
344static unsigned const ModRegsSuperclasses[] = {
345 Hexagon::CtrRegsRegClassID,
346};
347
348static unsigned const CtrRegs_with_subreg_overflowSuperclasses[] = {
349 Hexagon::CtrRegsRegClassID,
350};
351
352static unsigned const GeneralDoubleLow8RegsSuperclasses[] = {
353 Hexagon::DoubleRegsRegClassID,
354};
355
356static unsigned const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
357 Hexagon::DoubleRegsRegClassID,
358 Hexagon::GeneralDoubleLow8RegsRegClassID,
359};
360
361static unsigned const CtrRegs64_and_V62RegsSuperclasses[] = {
362 Hexagon::V62RegsRegClassID,
363 Hexagon::V62Regs_with_isub_hiRegClassID,
364 Hexagon::CtrRegs64RegClassID,
365};
366
367static unsigned const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
368 Hexagon::CtrRegs64RegClassID,
369};
370
371static unsigned const HvxVR_and_V65RegsSuperclasses[] = {
372 Hexagon::V65RegsRegClassID,
373 Hexagon::HvxVRRegClassID,
374};
375
376static unsigned const HvxWR_and_VectRegRevSuperclasses[] = {
377 Hexagon::VectRegRevRegClassID,
378 Hexagon::HvxWRRegClassID,
379};
380
381
382namespace Hexagon { // Register class instances
383 extern const TargetRegisterClass UsrBitsRegClass = {
384 .MC: &HexagonMCRegisterClasses[UsrBitsRegClassID],
385 .SubClassMask: UsrBitsSubClassMask,
386 .SuperRegIndices: SuperRegIdxSeqs + 3,
387 .LaneMask: LaneBitmask(0x0000000000000001),
388 .AllocationPriority: 0,
389 .GlobalPriority: false,
390 .TSFlags: 0x00, /* TSFlags */
391 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
392 .CoveredBySubRegs: false, /* CoveredBySubRegs */
393 .SuperClasses: nullptr, .SuperClassesSize: 0,
394 .OrderFunc: nullptr
395 };
396
397 extern const TargetRegisterClass SysRegsRegClass = {
398 .MC: &HexagonMCRegisterClasses[SysRegsRegClassID],
399 .SubClassMask: SysRegsSubClassMask,
400 .SuperRegIndices: SuperRegIdxSeqs + 0,
401 .LaneMask: LaneBitmask(0x0000000000000001),
402 .AllocationPriority: 0,
403 .GlobalPriority: false,
404 .TSFlags: 0x00, /* TSFlags */
405 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
406 .CoveredBySubRegs: false, /* CoveredBySubRegs */
407 .SuperClasses: nullptr, .SuperClassesSize: 0,
408 .OrderFunc: nullptr
409 };
410
411 extern const TargetRegisterClass GuestRegsRegClass = {
412 .MC: &HexagonMCRegisterClasses[GuestRegsRegClassID],
413 .SubClassMask: GuestRegsSubClassMask,
414 .SuperRegIndices: SuperRegIdxSeqs + 0,
415 .LaneMask: LaneBitmask(0x0000000000000001),
416 .AllocationPriority: 0,
417 .GlobalPriority: false,
418 .TSFlags: 0x00, /* TSFlags */
419 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
420 .CoveredBySubRegs: false, /* CoveredBySubRegs */
421 .SuperClasses: nullptr, .SuperClassesSize: 0,
422 .OrderFunc: nullptr
423 };
424
425 extern const TargetRegisterClass IntRegsRegClass = {
426 .MC: &HexagonMCRegisterClasses[IntRegsRegClassID],
427 .SubClassMask: IntRegsSubClassMask,
428 .SuperRegIndices: SuperRegIdxSeqs + 0,
429 .LaneMask: LaneBitmask(0x0000000000000001),
430 .AllocationPriority: 0,
431 .GlobalPriority: false,
432 .TSFlags: 0x00, /* TSFlags */
433 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
434 .CoveredBySubRegs: false, /* CoveredBySubRegs */
435 .SuperClasses: nullptr, .SuperClassesSize: 0,
436 .OrderFunc: nullptr
437 };
438
439 extern const TargetRegisterClass CtrRegsRegClass = {
440 .MC: &HexagonMCRegisterClasses[CtrRegsRegClassID],
441 .SubClassMask: CtrRegsSubClassMask,
442 .SuperRegIndices: SuperRegIdxSeqs + 0,
443 .LaneMask: LaneBitmask(0x0000000000000004),
444 .AllocationPriority: 0,
445 .GlobalPriority: false,
446 .TSFlags: 0x00, /* TSFlags */
447 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
448 .CoveredBySubRegs: false, /* CoveredBySubRegs */
449 .SuperClasses: nullptr, .SuperClassesSize: 0,
450 .OrderFunc: nullptr
451 };
452
453 extern const TargetRegisterClass GeneralSubRegsRegClass = {
454 .MC: &HexagonMCRegisterClasses[GeneralSubRegsRegClassID],
455 .SubClassMask: GeneralSubRegsSubClassMask,
456 .SuperRegIndices: SuperRegIdxSeqs + 0,
457 .LaneMask: LaneBitmask(0x0000000000000001),
458 .AllocationPriority: 0,
459 .GlobalPriority: false,
460 .TSFlags: 0x00, /* TSFlags */
461 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
462 .CoveredBySubRegs: false, /* CoveredBySubRegs */
463 .SuperClasses: GeneralSubRegsSuperclasses, .SuperClassesSize: 1,
464 .OrderFunc: nullptr
465 };
466
467 extern const TargetRegisterClass V62RegsRegClass = {
468 .MC: &HexagonMCRegisterClasses[V62RegsRegClassID],
469 .SubClassMask: V62RegsSubClassMask,
470 .SuperRegIndices: SuperRegIdxSeqs + 0,
471 .LaneMask: LaneBitmask(0x0000000000000003),
472 .AllocationPriority: 0,
473 .GlobalPriority: false,
474 .TSFlags: 0x00, /* TSFlags */
475 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
476 .CoveredBySubRegs: false, /* CoveredBySubRegs */
477 .SuperClasses: nullptr, .SuperClassesSize: 0,
478 .OrderFunc: nullptr
479 };
480
481 extern const TargetRegisterClass IntRegsLow8RegClass = {
482 .MC: &HexagonMCRegisterClasses[IntRegsLow8RegClassID],
483 .SubClassMask: IntRegsLow8SubClassMask,
484 .SuperRegIndices: SuperRegIdxSeqs + 0,
485 .LaneMask: LaneBitmask(0x0000000000000001),
486 .AllocationPriority: 0,
487 .GlobalPriority: false,
488 .TSFlags: 0x00, /* TSFlags */
489 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
490 .CoveredBySubRegs: false, /* CoveredBySubRegs */
491 .SuperClasses: IntRegsLow8Superclasses, .SuperClassesSize: 2,
492 .OrderFunc: nullptr
493 };
494
495 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
496 .MC: &HexagonMCRegisterClasses[CtrRegs_and_V62RegsRegClassID],
497 .SubClassMask: CtrRegs_and_V62RegsSubClassMask,
498 .SuperRegIndices: SuperRegIdxSeqs + 0,
499 .LaneMask: LaneBitmask(0x0000000000000001),
500 .AllocationPriority: 0,
501 .GlobalPriority: false,
502 .TSFlags: 0x00, /* TSFlags */
503 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
504 .CoveredBySubRegs: false, /* CoveredBySubRegs */
505 .SuperClasses: CtrRegs_and_V62RegsSuperclasses, .SuperClassesSize: 2,
506 .OrderFunc: nullptr
507 };
508
509 extern const TargetRegisterClass PredRegsRegClass = {
510 .MC: &HexagonMCRegisterClasses[PredRegsRegClassID],
511 .SubClassMask: PredRegsSubClassMask,
512 .SuperRegIndices: SuperRegIdxSeqs + 2,
513 .LaneMask: LaneBitmask(0x0000000000000001),
514 .AllocationPriority: 0,
515 .GlobalPriority: false,
516 .TSFlags: 0x00, /* TSFlags */
517 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
518 .CoveredBySubRegs: false, /* CoveredBySubRegs */
519 .SuperClasses: nullptr, .SuperClassesSize: 0,
520 .OrderFunc: nullptr
521 };
522
523 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
524 .MC: &HexagonMCRegisterClasses[V62Regs_with_isub_hiRegClassID],
525 .SubClassMask: V62Regs_with_isub_hiSubClassMask,
526 .SuperRegIndices: SuperRegIdxSeqs + 2,
527 .LaneMask: LaneBitmask(0x0000000000000003),
528 .AllocationPriority: 0,
529 .GlobalPriority: false,
530 .TSFlags: 0x00, /* TSFlags */
531 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
532 .CoveredBySubRegs: true, /* CoveredBySubRegs */
533 .SuperClasses: V62Regs_with_isub_hiSuperclasses, .SuperClassesSize: 1,
534 .OrderFunc: nullptr
535 };
536
537 extern const TargetRegisterClass ModRegsRegClass = {
538 .MC: &HexagonMCRegisterClasses[ModRegsRegClassID],
539 .SubClassMask: ModRegsSubClassMask,
540 .SuperRegIndices: SuperRegIdxSeqs + 0,
541 .LaneMask: LaneBitmask(0x0000000000000001),
542 .AllocationPriority: 0,
543 .GlobalPriority: false,
544 .TSFlags: 0x00, /* TSFlags */
545 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
546 .CoveredBySubRegs: false, /* CoveredBySubRegs */
547 .SuperClasses: ModRegsSuperclasses, .SuperClassesSize: 1,
548 .OrderFunc: nullptr
549 };
550
551 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
552 .MC: &HexagonMCRegisterClasses[CtrRegs_with_subreg_overflowRegClassID],
553 .SubClassMask: CtrRegs_with_subreg_overflowSubClassMask,
554 .SuperRegIndices: SuperRegIdxSeqs + 2,
555 .LaneMask: LaneBitmask(0x0000000000000004),
556 .AllocationPriority: 0,
557 .GlobalPriority: false,
558 .TSFlags: 0x00, /* TSFlags */
559 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
560 .CoveredBySubRegs: false, /* CoveredBySubRegs */
561 .SuperClasses: CtrRegs_with_subreg_overflowSuperclasses, .SuperClassesSize: 1,
562 .OrderFunc: nullptr
563 };
564
565 extern const TargetRegisterClass V65RegsRegClass = {
566 .MC: &HexagonMCRegisterClasses[V65RegsRegClassID],
567 .SubClassMask: V65RegsSubClassMask,
568 .SuperRegIndices: SuperRegIdxSeqs + 2,
569 .LaneMask: LaneBitmask(0x0000000000000001),
570 .AllocationPriority: 0,
571 .GlobalPriority: false,
572 .TSFlags: 0x00, /* TSFlags */
573 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
574 .CoveredBySubRegs: false, /* CoveredBySubRegs */
575 .SuperClasses: nullptr, .SuperClassesSize: 0,
576 .OrderFunc: nullptr
577 };
578
579 extern const TargetRegisterClass SysRegs64RegClass = {
580 .MC: &HexagonMCRegisterClasses[SysRegs64RegClassID],
581 .SubClassMask: SysRegs64SubClassMask,
582 .SuperRegIndices: SuperRegIdxSeqs + 2,
583 .LaneMask: LaneBitmask(0x0000000000000003),
584 .AllocationPriority: 0,
585 .GlobalPriority: false,
586 .TSFlags: 0x00, /* TSFlags */
587 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
588 .CoveredBySubRegs: true, /* CoveredBySubRegs */
589 .SuperClasses: nullptr, .SuperClassesSize: 0,
590 .OrderFunc: nullptr
591 };
592
593 extern const TargetRegisterClass DoubleRegsRegClass = {
594 .MC: &HexagonMCRegisterClasses[DoubleRegsRegClassID],
595 .SubClassMask: DoubleRegsSubClassMask,
596 .SuperRegIndices: SuperRegIdxSeqs + 2,
597 .LaneMask: LaneBitmask(0x0000000000000003),
598 .AllocationPriority: 0,
599 .GlobalPriority: false,
600 .TSFlags: 0x00, /* TSFlags */
601 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
602 .CoveredBySubRegs: true, /* CoveredBySubRegs */
603 .SuperClasses: nullptr, .SuperClassesSize: 0,
604 .OrderFunc: nullptr
605 };
606
607 extern const TargetRegisterClass GuestRegs64RegClass = {
608 .MC: &HexagonMCRegisterClasses[GuestRegs64RegClassID],
609 .SubClassMask: GuestRegs64SubClassMask,
610 .SuperRegIndices: SuperRegIdxSeqs + 2,
611 .LaneMask: LaneBitmask(0x0000000000000003),
612 .AllocationPriority: 0,
613 .GlobalPriority: false,
614 .TSFlags: 0x00, /* TSFlags */
615 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
616 .CoveredBySubRegs: true, /* CoveredBySubRegs */
617 .SuperClasses: nullptr, .SuperClassesSize: 0,
618 .OrderFunc: nullptr
619 };
620
621 extern const TargetRegisterClass VectRegRevRegClass = {
622 .MC: &HexagonMCRegisterClasses[VectRegRevRegClassID],
623 .SubClassMask: VectRegRevSubClassMask,
624 .SuperRegIndices: SuperRegIdxSeqs + 2,
625 .LaneMask: LaneBitmask(0x0000000000000038),
626 .AllocationPriority: 0,
627 .GlobalPriority: false,
628 .TSFlags: 0x00, /* TSFlags */
629 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
630 .CoveredBySubRegs: true, /* CoveredBySubRegs */
631 .SuperClasses: nullptr, .SuperClassesSize: 0,
632 .OrderFunc: nullptr
633 };
634
635 extern const TargetRegisterClass CtrRegs64RegClass = {
636 .MC: &HexagonMCRegisterClasses[CtrRegs64RegClassID],
637 .SubClassMask: CtrRegs64SubClassMask,
638 .SuperRegIndices: SuperRegIdxSeqs + 2,
639 .LaneMask: LaneBitmask(0x0000000000000003),
640 .AllocationPriority: 0,
641 .GlobalPriority: false,
642 .TSFlags: 0x00, /* TSFlags */
643 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
644 .CoveredBySubRegs: true, /* CoveredBySubRegs */
645 .SuperClasses: nullptr, .SuperClassesSize: 0,
646 .OrderFunc: nullptr
647 };
648
649 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
650 .MC: &HexagonMCRegisterClasses[GeneralDoubleLow8RegsRegClassID],
651 .SubClassMask: GeneralDoubleLow8RegsSubClassMask,
652 .SuperRegIndices: SuperRegIdxSeqs + 2,
653 .LaneMask: LaneBitmask(0x0000000000000003),
654 .AllocationPriority: 0,
655 .GlobalPriority: false,
656 .TSFlags: 0x00, /* TSFlags */
657 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
658 .CoveredBySubRegs: true, /* CoveredBySubRegs */
659 .SuperClasses: GeneralDoubleLow8RegsSuperclasses, .SuperClassesSize: 1,
660 .OrderFunc: nullptr
661 };
662
663 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
664 .MC: &HexagonMCRegisterClasses[DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID],
665 .SubClassMask: DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask,
666 .SuperRegIndices: SuperRegIdxSeqs + 2,
667 .LaneMask: LaneBitmask(0x0000000000000003),
668 .AllocationPriority: 0,
669 .GlobalPriority: false,
670 .TSFlags: 0x00, /* TSFlags */
671 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
672 .CoveredBySubRegs: true, /* CoveredBySubRegs */
673 .SuperClasses: DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses, .SuperClassesSize: 2,
674 .OrderFunc: nullptr
675 };
676
677 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
678 .MC: &HexagonMCRegisterClasses[CtrRegs64_and_V62RegsRegClassID],
679 .SubClassMask: CtrRegs64_and_V62RegsSubClassMask,
680 .SuperRegIndices: SuperRegIdxSeqs + 2,
681 .LaneMask: LaneBitmask(0x0000000000000003),
682 .AllocationPriority: 0,
683 .GlobalPriority: false,
684 .TSFlags: 0x00, /* TSFlags */
685 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
686 .CoveredBySubRegs: true, /* CoveredBySubRegs */
687 .SuperClasses: CtrRegs64_and_V62RegsSuperclasses, .SuperClassesSize: 3,
688 .OrderFunc: nullptr
689 };
690
691 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
692 .MC: &HexagonMCRegisterClasses[CtrRegs64_with_isub_hi_in_ModRegsRegClassID],
693 .SubClassMask: CtrRegs64_with_isub_hi_in_ModRegsSubClassMask,
694 .SuperRegIndices: SuperRegIdxSeqs + 2,
695 .LaneMask: LaneBitmask(0x0000000000000003),
696 .AllocationPriority: 0,
697 .GlobalPriority: false,
698 .TSFlags: 0x00, /* TSFlags */
699 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
700 .CoveredBySubRegs: true, /* CoveredBySubRegs */
701 .SuperClasses: CtrRegs64_with_isub_hi_in_ModRegsSuperclasses, .SuperClassesSize: 1,
702 .OrderFunc: nullptr
703 };
704
705 extern const TargetRegisterClass HvxQRRegClass = {
706 .MC: &HexagonMCRegisterClasses[HvxQRRegClassID],
707 .SubClassMask: HvxQRSubClassMask,
708 .SuperRegIndices: SuperRegIdxSeqs + 2,
709 .LaneMask: LaneBitmask(0x0000000000000001),
710 .AllocationPriority: 0,
711 .GlobalPriority: false,
712 .TSFlags: 0x00, /* TSFlags */
713 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
714 .CoveredBySubRegs: false, /* CoveredBySubRegs */
715 .SuperClasses: nullptr, .SuperClassesSize: 0,
716 .OrderFunc: nullptr
717 };
718
719 extern const TargetRegisterClass HvxVRRegClass = {
720 .MC: &HexagonMCRegisterClasses[HvxVRRegClassID],
721 .SubClassMask: HvxVRSubClassMask,
722 .SuperRegIndices: SuperRegIdxSeqs + 8,
723 .LaneMask: LaneBitmask(0x0000000000000001),
724 .AllocationPriority: 0,
725 .GlobalPriority: false,
726 .TSFlags: 0x00, /* TSFlags */
727 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
728 .CoveredBySubRegs: false, /* CoveredBySubRegs */
729 .SuperClasses: nullptr, .SuperClassesSize: 0,
730 .OrderFunc: nullptr
731 };
732
733 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
734 .MC: &HexagonMCRegisterClasses[HvxVR_and_V65RegsRegClassID],
735 .SubClassMask: HvxVR_and_V65RegsSubClassMask,
736 .SuperRegIndices: SuperRegIdxSeqs + 2,
737 .LaneMask: LaneBitmask(0x0000000000000001),
738 .AllocationPriority: 0,
739 .GlobalPriority: false,
740 .TSFlags: 0x00, /* TSFlags */
741 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
742 .CoveredBySubRegs: false, /* CoveredBySubRegs */
743 .SuperClasses: HvxVR_and_V65RegsSuperclasses, .SuperClassesSize: 2,
744 .OrderFunc: nullptr
745 };
746
747 extern const TargetRegisterClass HvxWRRegClass = {
748 .MC: &HexagonMCRegisterClasses[HvxWRRegClassID],
749 .SubClassMask: HvxWRSubClassMask,
750 .SuperRegIndices: SuperRegIdxSeqs + 5,
751 .LaneMask: LaneBitmask(0x0000000000000038),
752 .AllocationPriority: 0,
753 .GlobalPriority: false,
754 .TSFlags: 0x00, /* TSFlags */
755 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
756 .CoveredBySubRegs: true, /* CoveredBySubRegs */
757 .SuperClasses: nullptr, .SuperClassesSize: 0,
758 .OrderFunc: nullptr
759 };
760
761 extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass = {
762 .MC: &HexagonMCRegisterClasses[HvxWR_and_VectRegRevRegClassID],
763 .SubClassMask: HvxWR_and_VectRegRevSubClassMask,
764 .SuperRegIndices: SuperRegIdxSeqs + 2,
765 .LaneMask: LaneBitmask(0x0000000000000038),
766 .AllocationPriority: 0,
767 .GlobalPriority: false,
768 .TSFlags: 0x00, /* TSFlags */
769 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
770 .CoveredBySubRegs: true, /* CoveredBySubRegs */
771 .SuperClasses: HvxWR_and_VectRegRevSuperclasses, .SuperClassesSize: 2,
772 .OrderFunc: nullptr
773 };
774
775 extern const TargetRegisterClass HvxVQRRegClass = {
776 .MC: &HexagonMCRegisterClasses[HvxVQRRegClassID],
777 .SubClassMask: HvxVQRSubClassMask,
778 .SuperRegIndices: SuperRegIdxSeqs + 2,
779 .LaneMask: LaneBitmask(0x00000000000001F8),
780 .AllocationPriority: 0,
781 .GlobalPriority: false,
782 .TSFlags: 0x00, /* TSFlags */
783 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
784 .CoveredBySubRegs: true, /* CoveredBySubRegs */
785 .SuperClasses: nullptr, .SuperClassesSize: 0,
786 .OrderFunc: nullptr
787 };
788
789} // end namespace Hexagon
790
791namespace {
792 const TargetRegisterClass *const RegisterClasses[] = {
793 &Hexagon::UsrBitsRegClass,
794 &Hexagon::SysRegsRegClass,
795 &Hexagon::GuestRegsRegClass,
796 &Hexagon::IntRegsRegClass,
797 &Hexagon::CtrRegsRegClass,
798 &Hexagon::GeneralSubRegsRegClass,
799 &Hexagon::V62RegsRegClass,
800 &Hexagon::IntRegsLow8RegClass,
801 &Hexagon::CtrRegs_and_V62RegsRegClass,
802 &Hexagon::PredRegsRegClass,
803 &Hexagon::V62Regs_with_isub_hiRegClass,
804 &Hexagon::ModRegsRegClass,
805 &Hexagon::CtrRegs_with_subreg_overflowRegClass,
806 &Hexagon::V65RegsRegClass,
807 &Hexagon::SysRegs64RegClass,
808 &Hexagon::DoubleRegsRegClass,
809 &Hexagon::GuestRegs64RegClass,
810 &Hexagon::VectRegRevRegClass,
811 &Hexagon::CtrRegs64RegClass,
812 &Hexagon::GeneralDoubleLow8RegsRegClass,
813 &Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass,
814 &Hexagon::CtrRegs64_and_V62RegsRegClass,
815 &Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClass,
816 &Hexagon::HvxQRRegClass,
817 &Hexagon::HvxVRRegClass,
818 &Hexagon::HvxVR_and_V65RegsRegClass,
819 &Hexagon::HvxWRRegClass,
820 &Hexagon::HvxWR_and_VectRegRevRegClass,
821 &Hexagon::HvxVQRRegClass,
822 };
823} // end anonymous namespace
824
825static const uint8_t CostPerUseTable[] = {
8260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
827
828
829static const bool InAllocatableClassTable[] = {
830false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
831
832
833static const TargetRegisterInfoDesc HexagonRegInfoDesc = { // Extra Descriptors
834.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
835
836unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
837 static const uint8_t RowMap[11] = {
838 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
839 };
840 static const uint8_t Rows[2][11] = {
841 { 0, 0, 0, Hexagon::wsub_hi_then_vsub_fake, Hexagon::wsub_hi_then_vsub_hi, Hexagon::wsub_hi_then_vsub_lo, 0, 0, 0, 0, 0, },
842 { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
843 };
844
845 --IdxA; assert(IdxA < 11); (void) IdxA;
846 --IdxB; assert(IdxB < 11);
847 return Rows[RowMap[IdxA]][IdxB];
848}
849
850unsigned HexagonGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
851 static const uint8_t Table[11][11] = {
852 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
853 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
854 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
855 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
856 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
857 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
858 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
859 { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
860 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
861 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
862 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
863 };
864
865 --IdxA; assert(IdxA < 11);
866 --IdxB; assert(IdxB < 11);
867 return Table[IdxA][IdxB];
868 }
869
870 struct MaskRolOp {
871 LaneBitmask Mask;
872 uint8_t RotateLeft;
873 };
874 static const MaskRolOp LaneMaskComposeSequences[] = {
875 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
876 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
877 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
878 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
879 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
880 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
881 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 12
882 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 7 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 14
883 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 8 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 16
884 };
885 static const uint8_t CompositeSequences[] = {
886 0, // to isub_hi
887 2, // to isub_lo
888 4, // to subreg_overflow
889 6, // to vsub_fake
890 8, // to vsub_hi
891 10, // to vsub_lo
892 6, // to wsub_hi
893 0, // to wsub_lo
894 12, // to wsub_hi_then_vsub_fake
895 14, // to wsub_hi_then_vsub_hi
896 16 // to wsub_hi_then_vsub_lo
897 };
898
899LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
900 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
901 LaneBitmask Result;
902 for (const MaskRolOp *Ops =
903 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
904 Ops->Mask.any(); ++Ops) {
905 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
906 if (unsigned S = Ops->RotateLeft)
907 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
908 else
909 Result |= LaneBitmask(M);
910 }
911 return Result;
912}
913
914LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
915 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
916 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
917 LaneBitmask Result;
918 for (const MaskRolOp *Ops =
919 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
920 Ops->Mask.any(); ++Ops) {
921 LaneBitmask::Type M = LaneMask.getAsInteger();
922 if (unsigned S = Ops->RotateLeft)
923 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
924 else
925 Result |= LaneBitmask(M);
926 }
927 return Result;
928}
929
930const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
931 static const uint8_t Table[29][11] = {
932 { // UsrBits
933 0, // isub_hi
934 0, // isub_lo
935 0, // subreg_overflow
936 0, // vsub_fake
937 0, // vsub_hi
938 0, // vsub_lo
939 0, // wsub_hi
940 0, // wsub_lo
941 0, // wsub_hi_then_vsub_fake
942 0, // wsub_hi_then_vsub_hi
943 0, // wsub_hi_then_vsub_lo
944 },
945 { // SysRegs
946 0, // isub_hi
947 0, // isub_lo
948 0, // subreg_overflow
949 0, // vsub_fake
950 0, // vsub_hi
951 0, // vsub_lo
952 0, // wsub_hi
953 0, // wsub_lo
954 0, // wsub_hi_then_vsub_fake
955 0, // wsub_hi_then_vsub_hi
956 0, // wsub_hi_then_vsub_lo
957 },
958 { // GuestRegs
959 0, // isub_hi
960 0, // isub_lo
961 0, // subreg_overflow
962 0, // vsub_fake
963 0, // vsub_hi
964 0, // vsub_lo
965 0, // wsub_hi
966 0, // wsub_lo
967 0, // wsub_hi_then_vsub_fake
968 0, // wsub_hi_then_vsub_hi
969 0, // wsub_hi_then_vsub_lo
970 },
971 { // IntRegs
972 0, // isub_hi
973 0, // isub_lo
974 0, // subreg_overflow
975 0, // vsub_fake
976 0, // vsub_hi
977 0, // vsub_lo
978 0, // wsub_hi
979 0, // wsub_lo
980 0, // wsub_hi_then_vsub_fake
981 0, // wsub_hi_then_vsub_hi
982 0, // wsub_hi_then_vsub_lo
983 },
984 { // CtrRegs
985 0, // isub_hi
986 0, // isub_lo
987 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
988 0, // vsub_fake
989 0, // vsub_hi
990 0, // vsub_lo
991 0, // wsub_hi
992 0, // wsub_lo
993 0, // wsub_hi_then_vsub_fake
994 0, // wsub_hi_then_vsub_hi
995 0, // wsub_hi_then_vsub_lo
996 },
997 { // GeneralSubRegs
998 0, // isub_hi
999 0, // isub_lo
1000 0, // subreg_overflow
1001 0, // vsub_fake
1002 0, // vsub_hi
1003 0, // vsub_lo
1004 0, // wsub_hi
1005 0, // wsub_lo
1006 0, // wsub_hi_then_vsub_fake
1007 0, // wsub_hi_then_vsub_hi
1008 0, // wsub_hi_then_vsub_lo
1009 },
1010 { // V62Regs
1011 11, // isub_hi -> V62Regs_with_isub_hi
1012 11, // isub_lo -> V62Regs_with_isub_hi
1013 0, // subreg_overflow
1014 0, // vsub_fake
1015 0, // vsub_hi
1016 0, // vsub_lo
1017 0, // wsub_hi
1018 0, // wsub_lo
1019 0, // wsub_hi_then_vsub_fake
1020 0, // wsub_hi_then_vsub_hi
1021 0, // wsub_hi_then_vsub_lo
1022 },
1023 { // IntRegsLow8
1024 0, // isub_hi
1025 0, // isub_lo
1026 0, // subreg_overflow
1027 0, // vsub_fake
1028 0, // vsub_hi
1029 0, // vsub_lo
1030 0, // wsub_hi
1031 0, // wsub_lo
1032 0, // wsub_hi_then_vsub_fake
1033 0, // wsub_hi_then_vsub_hi
1034 0, // wsub_hi_then_vsub_lo
1035 },
1036 { // CtrRegs_and_V62Regs
1037 0, // isub_hi
1038 0, // isub_lo
1039 0, // subreg_overflow
1040 0, // vsub_fake
1041 0, // vsub_hi
1042 0, // vsub_lo
1043 0, // wsub_hi
1044 0, // wsub_lo
1045 0, // wsub_hi_then_vsub_fake
1046 0, // wsub_hi_then_vsub_hi
1047 0, // wsub_hi_then_vsub_lo
1048 },
1049 { // PredRegs
1050 0, // isub_hi
1051 0, // isub_lo
1052 0, // subreg_overflow
1053 0, // vsub_fake
1054 0, // vsub_hi
1055 0, // vsub_lo
1056 0, // wsub_hi
1057 0, // wsub_lo
1058 0, // wsub_hi_then_vsub_fake
1059 0, // wsub_hi_then_vsub_hi
1060 0, // wsub_hi_then_vsub_lo
1061 },
1062 { // V62Regs_with_isub_hi
1063 11, // isub_hi -> V62Regs_with_isub_hi
1064 11, // isub_lo -> V62Regs_with_isub_hi
1065 0, // subreg_overflow
1066 0, // vsub_fake
1067 0, // vsub_hi
1068 0, // vsub_lo
1069 0, // wsub_hi
1070 0, // wsub_lo
1071 0, // wsub_hi_then_vsub_fake
1072 0, // wsub_hi_then_vsub_hi
1073 0, // wsub_hi_then_vsub_lo
1074 },
1075 { // ModRegs
1076 0, // isub_hi
1077 0, // isub_lo
1078 0, // subreg_overflow
1079 0, // vsub_fake
1080 0, // vsub_hi
1081 0, // vsub_lo
1082 0, // wsub_hi
1083 0, // wsub_lo
1084 0, // wsub_hi_then_vsub_fake
1085 0, // wsub_hi_then_vsub_hi
1086 0, // wsub_hi_then_vsub_lo
1087 },
1088 { // CtrRegs_with_subreg_overflow
1089 0, // isub_hi
1090 0, // isub_lo
1091 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
1092 0, // vsub_fake
1093 0, // vsub_hi
1094 0, // vsub_lo
1095 0, // wsub_hi
1096 0, // wsub_lo
1097 0, // wsub_hi_then_vsub_fake
1098 0, // wsub_hi_then_vsub_hi
1099 0, // wsub_hi_then_vsub_lo
1100 },
1101 { // V65Regs
1102 0, // isub_hi
1103 0, // isub_lo
1104 0, // subreg_overflow
1105 0, // vsub_fake
1106 0, // vsub_hi
1107 0, // vsub_lo
1108 0, // wsub_hi
1109 0, // wsub_lo
1110 0, // wsub_hi_then_vsub_fake
1111 0, // wsub_hi_then_vsub_hi
1112 0, // wsub_hi_then_vsub_lo
1113 },
1114 { // SysRegs64
1115 15, // isub_hi -> SysRegs64
1116 15, // isub_lo -> SysRegs64
1117 0, // subreg_overflow
1118 0, // vsub_fake
1119 0, // vsub_hi
1120 0, // vsub_lo
1121 0, // wsub_hi
1122 0, // wsub_lo
1123 0, // wsub_hi_then_vsub_fake
1124 0, // wsub_hi_then_vsub_hi
1125 0, // wsub_hi_then_vsub_lo
1126 },
1127 { // DoubleRegs
1128 16, // isub_hi -> DoubleRegs
1129 16, // isub_lo -> DoubleRegs
1130 0, // subreg_overflow
1131 0, // vsub_fake
1132 0, // vsub_hi
1133 0, // vsub_lo
1134 0, // wsub_hi
1135 0, // wsub_lo
1136 0, // wsub_hi_then_vsub_fake
1137 0, // wsub_hi_then_vsub_hi
1138 0, // wsub_hi_then_vsub_lo
1139 },
1140 { // GuestRegs64
1141 17, // isub_hi -> GuestRegs64
1142 17, // isub_lo -> GuestRegs64
1143 0, // subreg_overflow
1144 0, // vsub_fake
1145 0, // vsub_hi
1146 0, // vsub_lo
1147 0, // wsub_hi
1148 0, // wsub_lo
1149 0, // wsub_hi_then_vsub_fake
1150 0, // wsub_hi_then_vsub_hi
1151 0, // wsub_hi_then_vsub_lo
1152 },
1153 { // VectRegRev
1154 0, // isub_hi
1155 0, // isub_lo
1156 0, // subreg_overflow
1157 18, // vsub_fake -> VectRegRev
1158 18, // vsub_hi -> VectRegRev
1159 18, // vsub_lo -> VectRegRev
1160 0, // wsub_hi
1161 0, // wsub_lo
1162 0, // wsub_hi_then_vsub_fake
1163 0, // wsub_hi_then_vsub_hi
1164 0, // wsub_hi_then_vsub_lo
1165 },
1166 { // CtrRegs64
1167 19, // isub_hi -> CtrRegs64
1168 19, // isub_lo -> CtrRegs64
1169 0, // subreg_overflow
1170 0, // vsub_fake
1171 0, // vsub_hi
1172 0, // vsub_lo
1173 0, // wsub_hi
1174 0, // wsub_lo
1175 0, // wsub_hi_then_vsub_fake
1176 0, // wsub_hi_then_vsub_hi
1177 0, // wsub_hi_then_vsub_lo
1178 },
1179 { // GeneralDoubleLow8Regs
1180 20, // isub_hi -> GeneralDoubleLow8Regs
1181 20, // isub_lo -> GeneralDoubleLow8Regs
1182 0, // subreg_overflow
1183 0, // vsub_fake
1184 0, // vsub_hi
1185 0, // vsub_lo
1186 0, // wsub_hi
1187 0, // wsub_lo
1188 0, // wsub_hi_then_vsub_fake
1189 0, // wsub_hi_then_vsub_hi
1190 0, // wsub_hi_then_vsub_lo
1191 },
1192 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
1193 21, // isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
1194 21, // isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
1195 0, // subreg_overflow
1196 0, // vsub_fake
1197 0, // vsub_hi
1198 0, // vsub_lo
1199 0, // wsub_hi
1200 0, // wsub_lo
1201 0, // wsub_hi_then_vsub_fake
1202 0, // wsub_hi_then_vsub_hi
1203 0, // wsub_hi_then_vsub_lo
1204 },
1205 { // CtrRegs64_and_V62Regs
1206 22, // isub_hi -> CtrRegs64_and_V62Regs
1207 22, // isub_lo -> CtrRegs64_and_V62Regs
1208 0, // subreg_overflow
1209 0, // vsub_fake
1210 0, // vsub_hi
1211 0, // vsub_lo
1212 0, // wsub_hi
1213 0, // wsub_lo
1214 0, // wsub_hi_then_vsub_fake
1215 0, // wsub_hi_then_vsub_hi
1216 0, // wsub_hi_then_vsub_lo
1217 },
1218 { // CtrRegs64_with_isub_hi_in_ModRegs
1219 23, // isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
1220 23, // isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
1221 0, // subreg_overflow
1222 0, // vsub_fake
1223 0, // vsub_hi
1224 0, // vsub_lo
1225 0, // wsub_hi
1226 0, // wsub_lo
1227 0, // wsub_hi_then_vsub_fake
1228 0, // wsub_hi_then_vsub_hi
1229 0, // wsub_hi_then_vsub_lo
1230 },
1231 { // HvxQR
1232 0, // isub_hi
1233 0, // isub_lo
1234 0, // subreg_overflow
1235 0, // vsub_fake
1236 0, // vsub_hi
1237 0, // vsub_lo
1238 0, // wsub_hi
1239 0, // wsub_lo
1240 0, // wsub_hi_then_vsub_fake
1241 0, // wsub_hi_then_vsub_hi
1242 0, // wsub_hi_then_vsub_lo
1243 },
1244 { // HvxVR
1245 0, // isub_hi
1246 0, // isub_lo
1247 0, // subreg_overflow
1248 0, // vsub_fake
1249 0, // vsub_hi
1250 0, // vsub_lo
1251 0, // wsub_hi
1252 0, // wsub_lo
1253 0, // wsub_hi_then_vsub_fake
1254 0, // wsub_hi_then_vsub_hi
1255 0, // wsub_hi_then_vsub_lo
1256 },
1257 { // HvxVR_and_V65Regs
1258 0, // isub_hi
1259 0, // isub_lo
1260 0, // subreg_overflow
1261 0, // vsub_fake
1262 0, // vsub_hi
1263 0, // vsub_lo
1264 0, // wsub_hi
1265 0, // wsub_lo
1266 0, // wsub_hi_then_vsub_fake
1267 0, // wsub_hi_then_vsub_hi
1268 0, // wsub_hi_then_vsub_lo
1269 },
1270 { // HvxWR
1271 0, // isub_hi
1272 0, // isub_lo
1273 0, // subreg_overflow
1274 27, // vsub_fake -> HvxWR
1275 27, // vsub_hi -> HvxWR
1276 27, // vsub_lo -> HvxWR
1277 0, // wsub_hi
1278 0, // wsub_lo
1279 0, // wsub_hi_then_vsub_fake
1280 0, // wsub_hi_then_vsub_hi
1281 0, // wsub_hi_then_vsub_lo
1282 },
1283 { // HvxWR_and_VectRegRev
1284 0, // isub_hi
1285 0, // isub_lo
1286 0, // subreg_overflow
1287 28, // vsub_fake -> HvxWR_and_VectRegRev
1288 28, // vsub_hi -> HvxWR_and_VectRegRev
1289 28, // vsub_lo -> HvxWR_and_VectRegRev
1290 0, // wsub_hi
1291 0, // wsub_lo
1292 0, // wsub_hi_then_vsub_fake
1293 0, // wsub_hi_then_vsub_hi
1294 0, // wsub_hi_then_vsub_lo
1295 },
1296 { // HvxVQR
1297 0, // isub_hi
1298 0, // isub_lo
1299 0, // subreg_overflow
1300 29, // vsub_fake -> HvxVQR
1301 29, // vsub_hi -> HvxVQR
1302 29, // vsub_lo -> HvxVQR
1303 29, // wsub_hi -> HvxVQR
1304 29, // wsub_lo -> HvxVQR
1305 29, // wsub_hi_then_vsub_fake -> HvxVQR
1306 29, // wsub_hi_then_vsub_hi -> HvxVQR
1307 29, // wsub_hi_then_vsub_lo -> HvxVQR
1308 },
1309 };
1310 assert(RC && "Missing regclass");
1311 if (!Idx) return RC;
1312 --Idx;
1313 assert(Idx < 11 && "Bad subreg");
1314 unsigned TV = Table[RC->getID()][Idx];
1315 return TV ? getRegClass(i: TV - 1) : nullptr;
1316}
1317
1318const TargetRegisterClass *HexagonGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1319 static const uint8_t Table[29][11] = {
1320 { // UsrBits
1321 0, // UsrBits:isub_hi
1322 0, // UsrBits:isub_lo
1323 0, // UsrBits:subreg_overflow
1324 0, // UsrBits:vsub_fake
1325 0, // UsrBits:vsub_hi
1326 0, // UsrBits:vsub_lo
1327 0, // UsrBits:wsub_hi
1328 0, // UsrBits:wsub_lo
1329 0, // UsrBits:wsub_hi_then_vsub_fake
1330 0, // UsrBits:wsub_hi_then_vsub_hi
1331 0, // UsrBits:wsub_hi_then_vsub_lo
1332 },
1333 { // SysRegs
1334 0, // SysRegs:isub_hi
1335 0, // SysRegs:isub_lo
1336 0, // SysRegs:subreg_overflow
1337 0, // SysRegs:vsub_fake
1338 0, // SysRegs:vsub_hi
1339 0, // SysRegs:vsub_lo
1340 0, // SysRegs:wsub_hi
1341 0, // SysRegs:wsub_lo
1342 0, // SysRegs:wsub_hi_then_vsub_fake
1343 0, // SysRegs:wsub_hi_then_vsub_hi
1344 0, // SysRegs:wsub_hi_then_vsub_lo
1345 },
1346 { // GuestRegs
1347 0, // GuestRegs:isub_hi
1348 0, // GuestRegs:isub_lo
1349 0, // GuestRegs:subreg_overflow
1350 0, // GuestRegs:vsub_fake
1351 0, // GuestRegs:vsub_hi
1352 0, // GuestRegs:vsub_lo
1353 0, // GuestRegs:wsub_hi
1354 0, // GuestRegs:wsub_lo
1355 0, // GuestRegs:wsub_hi_then_vsub_fake
1356 0, // GuestRegs:wsub_hi_then_vsub_hi
1357 0, // GuestRegs:wsub_hi_then_vsub_lo
1358 },
1359 { // IntRegs
1360 0, // IntRegs:isub_hi
1361 0, // IntRegs:isub_lo
1362 0, // IntRegs:subreg_overflow
1363 0, // IntRegs:vsub_fake
1364 0, // IntRegs:vsub_hi
1365 0, // IntRegs:vsub_lo
1366 0, // IntRegs:wsub_hi
1367 0, // IntRegs:wsub_lo
1368 0, // IntRegs:wsub_hi_then_vsub_fake
1369 0, // IntRegs:wsub_hi_then_vsub_hi
1370 0, // IntRegs:wsub_hi_then_vsub_lo
1371 },
1372 { // CtrRegs
1373 0, // CtrRegs:isub_hi
1374 0, // CtrRegs:isub_lo
1375 1, // CtrRegs:subreg_overflow -> UsrBits
1376 0, // CtrRegs:vsub_fake
1377 0, // CtrRegs:vsub_hi
1378 0, // CtrRegs:vsub_lo
1379 0, // CtrRegs:wsub_hi
1380 0, // CtrRegs:wsub_lo
1381 0, // CtrRegs:wsub_hi_then_vsub_fake
1382 0, // CtrRegs:wsub_hi_then_vsub_hi
1383 0, // CtrRegs:wsub_hi_then_vsub_lo
1384 },
1385 { // GeneralSubRegs
1386 0, // GeneralSubRegs:isub_hi
1387 0, // GeneralSubRegs:isub_lo
1388 0, // GeneralSubRegs:subreg_overflow
1389 0, // GeneralSubRegs:vsub_fake
1390 0, // GeneralSubRegs:vsub_hi
1391 0, // GeneralSubRegs:vsub_lo
1392 0, // GeneralSubRegs:wsub_hi
1393 0, // GeneralSubRegs:wsub_lo
1394 0, // GeneralSubRegs:wsub_hi_then_vsub_fake
1395 0, // GeneralSubRegs:wsub_hi_then_vsub_hi
1396 0, // GeneralSubRegs:wsub_hi_then_vsub_lo
1397 },
1398 { // V62Regs
1399 9, // V62Regs:isub_hi -> CtrRegs_and_V62Regs
1400 9, // V62Regs:isub_lo -> CtrRegs_and_V62Regs
1401 0, // V62Regs:subreg_overflow
1402 0, // V62Regs:vsub_fake
1403 0, // V62Regs:vsub_hi
1404 0, // V62Regs:vsub_lo
1405 0, // V62Regs:wsub_hi
1406 0, // V62Regs:wsub_lo
1407 0, // V62Regs:wsub_hi_then_vsub_fake
1408 0, // V62Regs:wsub_hi_then_vsub_hi
1409 0, // V62Regs:wsub_hi_then_vsub_lo
1410 },
1411 { // IntRegsLow8
1412 0, // IntRegsLow8:isub_hi
1413 0, // IntRegsLow8:isub_lo
1414 0, // IntRegsLow8:subreg_overflow
1415 0, // IntRegsLow8:vsub_fake
1416 0, // IntRegsLow8:vsub_hi
1417 0, // IntRegsLow8:vsub_lo
1418 0, // IntRegsLow8:wsub_hi
1419 0, // IntRegsLow8:wsub_lo
1420 0, // IntRegsLow8:wsub_hi_then_vsub_fake
1421 0, // IntRegsLow8:wsub_hi_then_vsub_hi
1422 0, // IntRegsLow8:wsub_hi_then_vsub_lo
1423 },
1424 { // CtrRegs_and_V62Regs
1425 0, // CtrRegs_and_V62Regs:isub_hi
1426 0, // CtrRegs_and_V62Regs:isub_lo
1427 0, // CtrRegs_and_V62Regs:subreg_overflow
1428 0, // CtrRegs_and_V62Regs:vsub_fake
1429 0, // CtrRegs_and_V62Regs:vsub_hi
1430 0, // CtrRegs_and_V62Regs:vsub_lo
1431 0, // CtrRegs_and_V62Regs:wsub_hi
1432 0, // CtrRegs_and_V62Regs:wsub_lo
1433 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_fake
1434 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_hi
1435 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_lo
1436 },
1437 { // PredRegs
1438 0, // PredRegs:isub_hi
1439 0, // PredRegs:isub_lo
1440 0, // PredRegs:subreg_overflow
1441 0, // PredRegs:vsub_fake
1442 0, // PredRegs:vsub_hi
1443 0, // PredRegs:vsub_lo
1444 0, // PredRegs:wsub_hi
1445 0, // PredRegs:wsub_lo
1446 0, // PredRegs:wsub_hi_then_vsub_fake
1447 0, // PredRegs:wsub_hi_then_vsub_hi
1448 0, // PredRegs:wsub_hi_then_vsub_lo
1449 },
1450 { // V62Regs_with_isub_hi
1451 9, // V62Regs_with_isub_hi:isub_hi -> CtrRegs_and_V62Regs
1452 9, // V62Regs_with_isub_hi:isub_lo -> CtrRegs_and_V62Regs
1453 0, // V62Regs_with_isub_hi:subreg_overflow
1454 0, // V62Regs_with_isub_hi:vsub_fake
1455 0, // V62Regs_with_isub_hi:vsub_hi
1456 0, // V62Regs_with_isub_hi:vsub_lo
1457 0, // V62Regs_with_isub_hi:wsub_hi
1458 0, // V62Regs_with_isub_hi:wsub_lo
1459 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_fake
1460 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_hi
1461 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_lo
1462 },
1463 { // ModRegs
1464 0, // ModRegs:isub_hi
1465 0, // ModRegs:isub_lo
1466 0, // ModRegs:subreg_overflow
1467 0, // ModRegs:vsub_fake
1468 0, // ModRegs:vsub_hi
1469 0, // ModRegs:vsub_lo
1470 0, // ModRegs:wsub_hi
1471 0, // ModRegs:wsub_lo
1472 0, // ModRegs:wsub_hi_then_vsub_fake
1473 0, // ModRegs:wsub_hi_then_vsub_hi
1474 0, // ModRegs:wsub_hi_then_vsub_lo
1475 },
1476 { // CtrRegs_with_subreg_overflow
1477 0, // CtrRegs_with_subreg_overflow:isub_hi
1478 0, // CtrRegs_with_subreg_overflow:isub_lo
1479 1, // CtrRegs_with_subreg_overflow:subreg_overflow -> UsrBits
1480 0, // CtrRegs_with_subreg_overflow:vsub_fake
1481 0, // CtrRegs_with_subreg_overflow:vsub_hi
1482 0, // CtrRegs_with_subreg_overflow:vsub_lo
1483 0, // CtrRegs_with_subreg_overflow:wsub_hi
1484 0, // CtrRegs_with_subreg_overflow:wsub_lo
1485 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_fake
1486 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_hi
1487 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_lo
1488 },
1489 { // V65Regs
1490 0, // V65Regs:isub_hi
1491 0, // V65Regs:isub_lo
1492 0, // V65Regs:subreg_overflow
1493 0, // V65Regs:vsub_fake
1494 0, // V65Regs:vsub_hi
1495 0, // V65Regs:vsub_lo
1496 0, // V65Regs:wsub_hi
1497 0, // V65Regs:wsub_lo
1498 0, // V65Regs:wsub_hi_then_vsub_fake
1499 0, // V65Regs:wsub_hi_then_vsub_hi
1500 0, // V65Regs:wsub_hi_then_vsub_lo
1501 },
1502 { // SysRegs64
1503 2, // SysRegs64:isub_hi -> SysRegs
1504 2, // SysRegs64:isub_lo -> SysRegs
1505 0, // SysRegs64:subreg_overflow
1506 0, // SysRegs64:vsub_fake
1507 0, // SysRegs64:vsub_hi
1508 0, // SysRegs64:vsub_lo
1509 0, // SysRegs64:wsub_hi
1510 0, // SysRegs64:wsub_lo
1511 0, // SysRegs64:wsub_hi_then_vsub_fake
1512 0, // SysRegs64:wsub_hi_then_vsub_hi
1513 0, // SysRegs64:wsub_hi_then_vsub_lo
1514 },
1515 { // DoubleRegs
1516 4, // DoubleRegs:isub_hi -> IntRegs
1517 4, // DoubleRegs:isub_lo -> IntRegs
1518 0, // DoubleRegs:subreg_overflow
1519 0, // DoubleRegs:vsub_fake
1520 0, // DoubleRegs:vsub_hi
1521 0, // DoubleRegs:vsub_lo
1522 0, // DoubleRegs:wsub_hi
1523 0, // DoubleRegs:wsub_lo
1524 0, // DoubleRegs:wsub_hi_then_vsub_fake
1525 0, // DoubleRegs:wsub_hi_then_vsub_hi
1526 0, // DoubleRegs:wsub_hi_then_vsub_lo
1527 },
1528 { // GuestRegs64
1529 3, // GuestRegs64:isub_hi -> GuestRegs
1530 3, // GuestRegs64:isub_lo -> GuestRegs
1531 0, // GuestRegs64:subreg_overflow
1532 0, // GuestRegs64:vsub_fake
1533 0, // GuestRegs64:vsub_hi
1534 0, // GuestRegs64:vsub_lo
1535 0, // GuestRegs64:wsub_hi
1536 0, // GuestRegs64:wsub_lo
1537 0, // GuestRegs64:wsub_hi_then_vsub_fake
1538 0, // GuestRegs64:wsub_hi_then_vsub_hi
1539 0, // GuestRegs64:wsub_hi_then_vsub_lo
1540 },
1541 { // VectRegRev
1542 0, // VectRegRev:isub_hi
1543 0, // VectRegRev:isub_lo
1544 0, // VectRegRev:subreg_overflow
1545 0, // VectRegRev:vsub_fake
1546 25, // VectRegRev:vsub_hi -> HvxVR
1547 25, // VectRegRev:vsub_lo -> HvxVR
1548 0, // VectRegRev:wsub_hi
1549 0, // VectRegRev:wsub_lo
1550 0, // VectRegRev:wsub_hi_then_vsub_fake
1551 0, // VectRegRev:wsub_hi_then_vsub_hi
1552 0, // VectRegRev:wsub_hi_then_vsub_lo
1553 },
1554 { // CtrRegs64
1555 5, // CtrRegs64:isub_hi -> CtrRegs
1556 5, // CtrRegs64:isub_lo -> CtrRegs
1557 0, // CtrRegs64:subreg_overflow
1558 0, // CtrRegs64:vsub_fake
1559 0, // CtrRegs64:vsub_hi
1560 0, // CtrRegs64:vsub_lo
1561 0, // CtrRegs64:wsub_hi
1562 0, // CtrRegs64:wsub_lo
1563 0, // CtrRegs64:wsub_hi_then_vsub_fake
1564 0, // CtrRegs64:wsub_hi_then_vsub_hi
1565 0, // CtrRegs64:wsub_hi_then_vsub_lo
1566 },
1567 { // GeneralDoubleLow8Regs
1568 6, // GeneralDoubleLow8Regs:isub_hi -> GeneralSubRegs
1569 6, // GeneralDoubleLow8Regs:isub_lo -> GeneralSubRegs
1570 0, // GeneralDoubleLow8Regs:subreg_overflow
1571 0, // GeneralDoubleLow8Regs:vsub_fake
1572 0, // GeneralDoubleLow8Regs:vsub_hi
1573 0, // GeneralDoubleLow8Regs:vsub_lo
1574 0, // GeneralDoubleLow8Regs:wsub_hi
1575 0, // GeneralDoubleLow8Regs:wsub_lo
1576 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_fake
1577 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_hi
1578 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_lo
1579 },
1580 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
1581 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_hi -> IntRegsLow8
1582 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_lo -> IntRegsLow8
1583 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:subreg_overflow
1584 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_fake
1585 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_hi
1586 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_lo
1587 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi
1588 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_lo
1589 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_fake
1590 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_hi
1591 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_lo
1592 },
1593 { // CtrRegs64_and_V62Regs
1594 9, // CtrRegs64_and_V62Regs:isub_hi -> CtrRegs_and_V62Regs
1595 9, // CtrRegs64_and_V62Regs:isub_lo -> CtrRegs_and_V62Regs
1596 0, // CtrRegs64_and_V62Regs:subreg_overflow
1597 0, // CtrRegs64_and_V62Regs:vsub_fake
1598 0, // CtrRegs64_and_V62Regs:vsub_hi
1599 0, // CtrRegs64_and_V62Regs:vsub_lo
1600 0, // CtrRegs64_and_V62Regs:wsub_hi
1601 0, // CtrRegs64_and_V62Regs:wsub_lo
1602 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_fake
1603 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_hi
1604 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_lo
1605 },
1606 { // CtrRegs64_with_isub_hi_in_ModRegs
1607 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_hi -> ModRegs
1608 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_lo -> ModRegs
1609 0, // CtrRegs64_with_isub_hi_in_ModRegs:subreg_overflow
1610 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_fake
1611 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_hi
1612 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_lo
1613 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi
1614 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_lo
1615 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_fake
1616 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_hi
1617 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_lo
1618 },
1619 { // HvxQR
1620 0, // HvxQR:isub_hi
1621 0, // HvxQR:isub_lo
1622 0, // HvxQR:subreg_overflow
1623 0, // HvxQR:vsub_fake
1624 0, // HvxQR:vsub_hi
1625 0, // HvxQR:vsub_lo
1626 0, // HvxQR:wsub_hi
1627 0, // HvxQR:wsub_lo
1628 0, // HvxQR:wsub_hi_then_vsub_fake
1629 0, // HvxQR:wsub_hi_then_vsub_hi
1630 0, // HvxQR:wsub_hi_then_vsub_lo
1631 },
1632 { // HvxVR
1633 0, // HvxVR:isub_hi
1634 0, // HvxVR:isub_lo
1635 0, // HvxVR:subreg_overflow
1636 0, // HvxVR:vsub_fake
1637 0, // HvxVR:vsub_hi
1638 0, // HvxVR:vsub_lo
1639 0, // HvxVR:wsub_hi
1640 0, // HvxVR:wsub_lo
1641 0, // HvxVR:wsub_hi_then_vsub_fake
1642 0, // HvxVR:wsub_hi_then_vsub_hi
1643 0, // HvxVR:wsub_hi_then_vsub_lo
1644 },
1645 { // HvxVR_and_V65Regs
1646 0, // HvxVR_and_V65Regs:isub_hi
1647 0, // HvxVR_and_V65Regs:isub_lo
1648 0, // HvxVR_and_V65Regs:subreg_overflow
1649 0, // HvxVR_and_V65Regs:vsub_fake
1650 0, // HvxVR_and_V65Regs:vsub_hi
1651 0, // HvxVR_and_V65Regs:vsub_lo
1652 0, // HvxVR_and_V65Regs:wsub_hi
1653 0, // HvxVR_and_V65Regs:wsub_lo
1654 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_fake
1655 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_hi
1656 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_lo
1657 },
1658 { // HvxWR
1659 0, // HvxWR:isub_hi
1660 0, // HvxWR:isub_lo
1661 0, // HvxWR:subreg_overflow
1662 0, // HvxWR:vsub_fake
1663 25, // HvxWR:vsub_hi -> HvxVR
1664 25, // HvxWR:vsub_lo -> HvxVR
1665 0, // HvxWR:wsub_hi
1666 0, // HvxWR:wsub_lo
1667 0, // HvxWR:wsub_hi_then_vsub_fake
1668 0, // HvxWR:wsub_hi_then_vsub_hi
1669 0, // HvxWR:wsub_hi_then_vsub_lo
1670 },
1671 { // HvxWR_and_VectRegRev
1672 0, // HvxWR_and_VectRegRev:isub_hi
1673 0, // HvxWR_and_VectRegRev:isub_lo
1674 0, // HvxWR_and_VectRegRev:subreg_overflow
1675 0, // HvxWR_and_VectRegRev:vsub_fake
1676 25, // HvxWR_and_VectRegRev:vsub_hi -> HvxVR
1677 25, // HvxWR_and_VectRegRev:vsub_lo -> HvxVR
1678 0, // HvxWR_and_VectRegRev:wsub_hi
1679 0, // HvxWR_and_VectRegRev:wsub_lo
1680 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_fake
1681 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_hi
1682 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_lo
1683 },
1684 { // HvxVQR
1685 0, // HvxVQR:isub_hi
1686 0, // HvxVQR:isub_lo
1687 0, // HvxVQR:subreg_overflow
1688 0, // HvxVQR:vsub_fake
1689 25, // HvxVQR:vsub_hi -> HvxVR
1690 25, // HvxVQR:vsub_lo -> HvxVR
1691 27, // HvxVQR:wsub_hi -> HvxWR
1692 27, // HvxVQR:wsub_lo -> HvxWR
1693 0, // HvxVQR:wsub_hi_then_vsub_fake
1694 25, // HvxVQR:wsub_hi_then_vsub_hi -> HvxVR
1695 25, // HvxVQR:wsub_hi_then_vsub_lo -> HvxVR
1696 },
1697 };
1698 assert(RC && "Missing regclass");
1699 if (!Idx) return RC;
1700 --Idx;
1701 assert(Idx < 11 && "Bad subreg");
1702 unsigned TV = Table[RC->getID()][Idx];
1703 return TV ? getRegClass(i: TV - 1) : nullptr;
1704}
1705
1706/// Get the weight in units of pressure for this register class.
1707const RegClassWeight &HexagonGenRegisterInfo::
1708getRegClassWeight(const TargetRegisterClass *RC) const {
1709 static const RegClassWeight RCWeightTable[] = {
1710 {.RegWeight: 0, .WeightLimit: 0}, // UsrBits
1711 {.RegWeight: 0, .WeightLimit: 0}, // SysRegs
1712 {.RegWeight: 0, .WeightLimit: 0}, // GuestRegs
1713 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
1714 {.RegWeight: 0, .WeightLimit: 6}, // CtrRegs
1715 {.RegWeight: 1, .WeightLimit: 16}, // GeneralSubRegs
1716 {.RegWeight: 0, .WeightLimit: 0}, // V62Regs
1717 {.RegWeight: 1, .WeightLimit: 8}, // IntRegsLow8
1718 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs_and_V62Regs
1719 {.RegWeight: 2, .WeightLimit: 8}, // PredRegs
1720 {.RegWeight: 0, .WeightLimit: 0}, // V62Regs_with_isub_hi
1721 {.RegWeight: 1, .WeightLimit: 2}, // ModRegs
1722 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs_with_subreg_overflow
1723 {.RegWeight: 1, .WeightLimit: 1}, // V65Regs
1724 {.RegWeight: 0, .WeightLimit: 0}, // SysRegs64
1725 {.RegWeight: 2, .WeightLimit: 32}, // DoubleRegs
1726 {.RegWeight: 0, .WeightLimit: 0}, // GuestRegs64
1727 {.RegWeight: 2, .WeightLimit: 32}, // VectRegRev
1728 {.RegWeight: 0, .WeightLimit: 6}, // CtrRegs64
1729 {.RegWeight: 2, .WeightLimit: 16}, // GeneralDoubleLow8Regs
1730 {.RegWeight: 2, .WeightLimit: 8}, // DoubleRegs_with_isub_hi_in_IntRegsLow8
1731 {.RegWeight: 0, .WeightLimit: 0}, // CtrRegs64_and_V62Regs
1732 {.RegWeight: 2, .WeightLimit: 2}, // CtrRegs64_with_isub_hi_in_ModRegs
1733 {.RegWeight: 1, .WeightLimit: 4}, // HvxQR
1734 {.RegWeight: 1, .WeightLimit: 33}, // HvxVR
1735 {.RegWeight: 1, .WeightLimit: 1}, // HvxVR_and_V65Regs
1736 {.RegWeight: 2, .WeightLimit: 32}, // HvxWR
1737 {.RegWeight: 2, .WeightLimit: 32}, // HvxWR_and_VectRegRev
1738 {.RegWeight: 4, .WeightLimit: 32}, // HvxVQR
1739 };
1740 return RCWeightTable[RC->getID()];
1741}
1742
1743/// Get the weight in units of pressure for this register unit.
1744unsigned HexagonGenRegisterInfo::
1745getRegUnitWeight(MCRegUnit RegUnit) const {
1746 assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
1747 // All register units have unit weight.
1748 return 1;
1749}
1750
1751
1752// Get the number of dimensions of register pressure.
1753unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
1754 return 8;
1755}
1756
1757// Get the name of this register unit pressure set.
1758const char *HexagonGenRegisterInfo::
1759getRegPressureSetName(unsigned Idx) const {
1760 static const char *PressureNameTable[] = {
1761 "HvxVR_and_V65Regs",
1762 "ModRegs",
1763 "HvxQR",
1764 "IntRegsLow8",
1765 "PredRegs",
1766 "GeneralSubRegs",
1767 "IntRegs",
1768 "HvxVR",
1769 };
1770 return PressureNameTable[Idx];
1771}
1772
1773// Get the register unit pressure limit for this dimension.
1774// This limit must be adjusted dynamically for reserved registers.
1775unsigned HexagonGenRegisterInfo::
1776getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1777 static const uint8_t PressureLimitTable[] = {
1778 1, // 0: HvxVR_and_V65Regs
1779 2, // 1: ModRegs
1780 4, // 2: HvxQR
1781 8, // 3: IntRegsLow8
1782 8, // 4: PredRegs
1783 16, // 5: GeneralSubRegs
1784 32, // 6: IntRegs
1785 33, // 7: HvxVR
1786 };
1787 return PressureLimitTable[Idx];
1788}
1789
1790/// Table of pressure sets per register class or unit.
1791static const int RCSetsTable[] = {
1792 /* 0 */ 1, -1,
1793 /* 2 */ 2, -1,
1794 /* 4 */ 4, -1,
1795 /* 6 */ 3, 5, 6, -1,
1796 /* 10 */ 0, 7, -1,
1797};
1798
1799/// Get the dimensions of register pressure impacted by this register class.
1800/// Returns a -1 terminated array of pressure set IDs
1801const int *HexagonGenRegisterInfo::
1802getRegClassPressureSets(const TargetRegisterClass *RC) const {
1803 static const uint8_t RCSetStartTable[] = {
1804 1,1,1,8,1,7,1,6,1,4,1,0,1,1,1,8,1,11,1,7,6,1,1,2,11,10,11,11,11,};
1805 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1806}
1807
1808/// Get the dimensions of register pressure impacted by this register unit.
1809/// Returns a -1 terminated array of pressure set IDs
1810const int *HexagonGenRegisterInfo::
1811getRegUnitPressureSets(MCRegUnit RegUnit) const {
1812 assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
1813 static const uint8_t RUSetStartTable[] = {
1814 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,4,4,4,4,4,4,4,4,1,1,1,1,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
1815 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1816}
1817
1818extern const MCRegisterDesc HexagonRegDesc[];
1819extern const int16_t HexagonRegDiffLists[];
1820extern const LaneBitmask HexagonLaneMaskLists[];
1821extern const char HexagonRegStrings[];
1822extern const char HexagonRegClassStrings[];
1823extern const MCPhysReg HexagonRegUnitRoots[][2];
1824extern const uint16_t HexagonSubRegIdxLists[];
1825extern const uint16_t HexagonRegEncodingTable[];
1826// Hexagon Dwarf<->LLVM register mappings.
1827extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
1828extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;
1829
1830extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
1831extern const unsigned HexagonEHFlavour0Dwarf2LSize;
1832
1833extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
1834extern const unsigned HexagonDwarfFlavour0L2DwarfSize;
1835
1836extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
1837extern const unsigned HexagonEHFlavour0L2DwarfSize;
1838
1839HexagonGenRegisterInfo::
1840HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1841 unsigned PC, unsigned HwMode)
1842 : TargetRegisterInfo(&HexagonRegInfoDesc, RegisterClasses, RegisterClasses+29,
1843 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
1844 LaneBitmask(0xFFFFFFFFFFFFFFFB), RegClassInfos, VTLists, HwMode) {
1845 InitMCRegisterInfo(D: HexagonRegDesc, NR: 398, RA, PC,
1846 C: HexagonMCRegisterClasses, NC: 29,
1847 RURoots: HexagonRegUnitRoots,
1848 NRU: 278,
1849 DL: HexagonRegDiffLists,
1850 RUMS: HexagonLaneMaskLists,
1851 Strings: HexagonRegStrings,
1852 ClassStrings: HexagonRegClassStrings,
1853 SubIndices: HexagonSubRegIdxLists,
1854 NumIndices: 12,
1855 RET: HexagonRegEncodingTable);
1856
1857 switch (DwarfFlavour) {
1858 default:
1859 llvm_unreachable("Unknown DWARF flavour");
1860 case 0:
1861 mapDwarfRegsToLLVMRegs(Map: HexagonDwarfFlavour0Dwarf2L, Size: HexagonDwarfFlavour0Dwarf2LSize, isEH: false);
1862 break;
1863 }
1864 switch (EHFlavour) {
1865 default:
1866 llvm_unreachable("Unknown DWARF flavour");
1867 case 0:
1868 mapDwarfRegsToLLVMRegs(Map: HexagonEHFlavour0Dwarf2L, Size: HexagonEHFlavour0Dwarf2LSize, isEH: true);
1869 break;
1870 }
1871 switch (DwarfFlavour) {
1872 default:
1873 llvm_unreachable("Unknown DWARF flavour");
1874 case 0:
1875 mapLLVMRegsToDwarfRegs(Map: HexagonDwarfFlavour0L2Dwarf, Size: HexagonDwarfFlavour0L2DwarfSize, isEH: false);
1876 break;
1877 }
1878 switch (EHFlavour) {
1879 default:
1880 llvm_unreachable("Unknown DWARF flavour");
1881 case 0:
1882 mapLLVMRegsToDwarfRegs(Map: HexagonEHFlavour0L2Dwarf, Size: HexagonEHFlavour0L2DwarfSize, isEH: true);
1883 break;
1884 }
1885}
1886
1887static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
1888static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x00000000, 0x0000007e, 0x00000000, 0x0003ffc0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
1889
1890
1891ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
1892 static const uint32_t *const Masks[] = {
1893 HexagonCSR_RegMask,
1894 };
1895 return ArrayRef(Masks);
1896}
1897
1898bool HexagonGenRegisterInfo::
1899isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1900 return
1901 false;
1902}
1903
1904bool HexagonGenRegisterInfo::
1905isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1906 return
1907 false;
1908}
1909
1910bool HexagonGenRegisterInfo::
1911isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1912 return
1913 false;
1914}
1915
1916bool HexagonGenRegisterInfo::
1917isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1918 return
1919 false;
1920}
1921
1922bool HexagonGenRegisterInfo::
1923isConstantPhysReg(MCRegister PhysReg) const {
1924 return
1925 false;
1926}
1927
1928ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
1929 static const char *Names[] = {
1930 "HexagonCSR",
1931 };
1932 return ArrayRef(Names);
1933}
1934
1935const HexagonFrameLowering *
1936HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1937 return static_cast<const HexagonFrameLowering *>(
1938 MF.getSubtarget().getFrameLowering());
1939}
1940
1941} // end namespace llvm
1942
1943