1//===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Hexagon implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonRegisterInfo.h"
15#include "HexagonFrameLowering.h"
16#include "HexagonMachineFunctionInfo.h"
17#include "HexagonSubtarget.h"
18#include "llvm/ADT/BitVector.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallSet.h"
21#include "llvm/CodeGen/LiveIntervals.h"
22#include "llvm/CodeGen/LiveRegUnits.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/PseudoSourceValue.h"
28#include "llvm/CodeGen/RegisterScavenging.h"
29#include "llvm/CodeGen/TargetInstrInfo.h"
30#include "llvm/IR/Function.h"
31#include "llvm/IR/Type.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36#include "llvm/Target/TargetOptions.h"
37
38#define GET_REGINFO_TARGET_DESC
39#include "HexagonGenRegisterInfo.inc"
40
41using namespace llvm;
42
43static cl::opt<unsigned> FrameIndexSearchRange(
44 "hexagon-frame-index-search-range", cl::init(Val: 32), cl::Hidden,
45 cl::desc("Limit on instruction search range in frame index elimination"));
46
47static cl::opt<unsigned> FrameIndexReuseLimit(
48 "hexagon-frame-index-reuse-limit", cl::init(Val: ~0), cl::Hidden,
49 cl::desc("Limit on the number of reused registers in frame index "
50 "elimination"));
51
52HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode)
53 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
54 0/*PC*/, HwMode) {}
55
56bool HexagonRegisterInfo::isGlobalReg(MCPhysReg Reg) const {
57 switch (Reg) {
58 case Hexagon::R29:
59 case Hexagon::R30:
60 case Hexagon::R31:
61 return true;
62 }
63 return false;
64}
65
66bool HexagonRegisterInfo::isFakeReg(MCPhysReg Reg) const {
67 // VF0-VF31 are fake registers used as sub-registers in HVX vector pairs
68 if (Reg >= Hexagon::VF0 && Reg <= Hexagon::VF31)
69 return true;
70 // VFR0-VFR31 are fake registers used for reversed vector pairs
71 if (Reg >= Hexagon::VFR0 && Reg <= Hexagon::VFR31)
72 return true;
73 return false;
74}
75
76bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(Register R) const {
77 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
78 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
79}
80
81const MCPhysReg *
82HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF,
83 const TargetRegisterClass *RC) const {
84 using namespace Hexagon;
85
86 static const MCPhysReg Int32[] = {
87 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
88 };
89 static const MCPhysReg Int64[] = {
90 D0, D1, D2, D3, D4, D5, D6, D7, 0
91 };
92 static const MCPhysReg Pred[] = {
93 P0, P1, P2, P3, 0
94 };
95 static const MCPhysReg VecSgl[] = {
96 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
97 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
98 V28, V29, V30, V31, 0
99 };
100 static const MCPhysReg VecDbl[] = {
101 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
102 };
103 static const MCPhysReg VecPred[] = {
104 Q0, Q1, Q2, Q3, 0
105 };
106
107 switch (RC->getID()) {
108 case IntRegsRegClassID:
109 return Int32;
110 case DoubleRegsRegClassID:
111 return Int64;
112 case PredRegsRegClassID:
113 return Pred;
114 case HvxVRRegClassID:
115 return VecSgl;
116 case HvxWRRegClassID:
117 return VecDbl;
118 case HvxQRRegClassID:
119 return VecPred;
120 default:
121 break;
122 }
123
124 static const MCPhysReg Empty[] = { 0 };
125#ifndef NDEBUG
126 dbgs() << "Register class: " << getRegClassName(RC) << "\n";
127#endif
128 llvm_unreachable("Unexpected register class");
129 return Empty;
130}
131
132
133const MCPhysReg *
134HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
135 static const MCPhysReg CalleeSavedRegsV3[] = {
136 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
137 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
138 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
139 };
140
141 // Functions that contain a call to __builtin_eh_return also save the first 4
142 // parameter registers.
143 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
144 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
145 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
146 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
147 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
148 };
149
150 bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
151
152 return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
153}
154
155
156const uint32_t *HexagonRegisterInfo::getCallPreservedMask(
157 const MachineFunction &MF, CallingConv::ID) const {
158 return HexagonCSR_RegMask;
159}
160
161BitVector
162HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
163 BitVector Reserved = getBaseReservedRegs(MF);
164 if (Register AP = computeStackAlignBaseRegister(MF, BaseReservedRegs: Reserved)) {
165 Reserved.set(AP);
166 markSuperRegs(RegisterSet&: Reserved, Reg: AP);
167 }
168 return Reserved;
169}
170
171Register HexagonRegisterInfo::computeStackAlignBaseRegister(
172 const MachineFunction &MF) const {
173 return computeStackAlignBaseRegister(MF, BaseReservedRegs: getBaseReservedRegs(MF));
174}
175
176Register HexagonRegisterInfo::computeStackAlignBaseRegister(
177 const MachineFunction &MF, const BitVector &BaseReservedRegs) const {
178 auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
179 if (!HFI.needsAligna(MF))
180 return Register();
181
182 // Reserve the first non-volatile register.
183 Register AP;
184 for (const MCPhysReg *R = getCalleeSavedRegs(MF: &MF); *R; ++R) {
185 if (BaseReservedRegs[*R])
186 continue;
187 AP = *R;
188 break;
189 }
190 assert(AP.isValid() && "Couldn't reserve stack align register");
191 return AP;
192}
193
194BitVector
195HexagonRegisterInfo::getBaseReservedRegs(const MachineFunction &MF) const {
196 BitVector Reserved(getNumRegs());
197 Reserved.set(Hexagon::R29);
198 Reserved.set(Hexagon::R30);
199 Reserved.set(Hexagon::R31);
200 Reserved.set(Hexagon::VTMP);
201
202 // Guest registers.
203 Reserved.set(Hexagon::GELR); // G0
204 Reserved.set(Hexagon::GSR); // G1
205 Reserved.set(Hexagon::GOSP); // G2
206 Reserved.set(Hexagon::G3); // G3
207
208 // Control registers.
209 Reserved.set(Hexagon::SA0); // C0
210 Reserved.set(Hexagon::LC0); // C1
211 Reserved.set(Hexagon::SA1); // C2
212 Reserved.set(Hexagon::LC1); // C3
213 Reserved.set(Hexagon::P3_0); // C4
214 Reserved.set(Hexagon::USR); // C8
215 Reserved.set(Hexagon::PC); // C9
216 Reserved.set(Hexagon::UGP); // C10
217 Reserved.set(Hexagon::GP); // C11
218 Reserved.set(Hexagon::CS0); // C12
219 Reserved.set(Hexagon::CS1); // C13
220 Reserved.set(Hexagon::UPCYCLELO); // C14
221 Reserved.set(Hexagon::UPCYCLEHI); // C15
222 Reserved.set(Hexagon::FRAMELIMIT); // C16
223 Reserved.set(Hexagon::FRAMEKEY); // C17
224 Reserved.set(Hexagon::PKTCOUNTLO); // C18
225 Reserved.set(Hexagon::PKTCOUNTHI); // C19
226 Reserved.set(Hexagon::UTIMERLO); // C30
227 Reserved.set(Hexagon::UTIMERHI); // C31
228 // Out of the control registers, only C8 is explicitly defined in
229 // HexagonRegisterInfo.td. If others are defined, make sure to add
230 // them here as well.
231 Reserved.set(Hexagon::C8);
232 Reserved.set(Hexagon::USR_OVF);
233
234 // Leveraging these registers will require more work to recognize
235 // the new semantics posed, Hi/LoVec patterns, etc.
236 // Note well: if enabled, they should be restricted to only
237 // where `HST.useHVXOps() && HST.hasV67Ops()` is true.
238 for (auto Reg : Hexagon_MC::GetVectRegRev())
239 Reserved.set(Reg);
240
241 static const MCPhysReg RRegs[] = {
242 Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, Hexagon::R10,
243 Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, Hexagon::R15,
244 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20,
245 Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25,
246 Hexagon::R26, Hexagon::R27, Hexagon::R28};
247 for (MCPhysReg Reg : RRegs)
248 if (MF.getSubtarget().isRegisterReservedByUser(R: Reg))
249 Reserved.set(Reg);
250
251 for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(Prev: x))
252 markSuperRegs(RegisterSet&: Reserved, Reg: x);
253
254 return Reserved;
255}
256
257bool HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
258 int SPAdj, unsigned FIOp,
259 RegScavenger *RS) const {
260 static unsigned ReuseCount = 0;
261 //
262 // Hexagon_TODO: Do we need to enforce this for Hexagon?
263 assert(SPAdj == 0 && "Unexpected");
264
265 MachineInstr &MI = *II;
266 MachineBasicBlock &MB = *MI.getParent();
267 MachineFunction &MF = *MB.getParent();
268 auto &HST = MF.getSubtarget<HexagonSubtarget>();
269 auto &HII = *HST.getInstrInfo();
270 auto &HFI = *HST.getFrameLowering();
271
272 Register BP;
273 int FI = MI.getOperand(i: FIOp).getIndex();
274 // Select the base pointer (BP) and calculate the actual offset from BP
275 // to the beginning of the object at index FI.
276 int Offset = HFI.getFrameIndexReference(MF, FI, FrameReg&: BP).getFixed();
277 // Add the offset from the instruction.
278 int RealOffset = Offset + MI.getOperand(i: FIOp+1).getImm();
279
280 unsigned Opc = MI.getOpcode();
281 switch (Opc) {
282 case Hexagon::PS_fia:
283 MI.setDesc(HII.get(Opcode: Hexagon::A2_addi));
284 MI.getOperand(i: FIOp).ChangeToImmediate(ImmVal: RealOffset);
285 MI.removeOperand(OpNo: FIOp+1);
286 return false;
287 case Hexagon::PS_fi:
288 // Set up the instruction for updating below.
289 MI.setDesc(HII.get(Opcode: Hexagon::A2_addi));
290 break;
291 }
292
293 if (!HII.isValidOffset(Opcode: Opc, Offset: RealOffset, TRI: this)) {
294 // If the offset is not valid, calculate the address in a temporary
295 // register and use it with offset 0.
296 int InstOffset = 0;
297 // The actual base register (BP) is typically shared between many
298 // instructions where frame indices are being replaced. In scalar
299 // instructions the offset range is large, and the need for an extra
300 // add instruction is infrequent. Vector loads/stores, however, have
301 // a much smaller offset range: [-8, 7), or #s4. In those cases it
302 // makes sense to "standardize" the immediate in the "addi" instruction
303 // so that multiple loads/stores could be based on it.
304 bool IsPair = false;
305 switch (MI.getOpcode()) {
306 // All of these instructions have the same format: base+#s4.
307 case Hexagon::PS_vloadrw_ai:
308 case Hexagon::PS_vloadrw_nt_ai:
309 case Hexagon::PS_vstorerw_ai:
310 case Hexagon::PS_vstorerw_nt_ai:
311 IsPair = true;
312 [[fallthrough]];
313 case Hexagon::PS_vloadrv_ai:
314 case Hexagon::PS_vloadrv_nt_ai:
315 case Hexagon::PS_vstorerv_ai:
316 case Hexagon::PS_vstorerv_nt_ai:
317 case Hexagon::V6_vL32b_ai:
318 case Hexagon::V6_vS32b_ai: {
319 unsigned HwLen = HST.getVectorLength();
320 if (RealOffset % HwLen == 0) {
321 int VecOffset = RealOffset / HwLen;
322 // Rewrite the offset as "base + [-8, 7)".
323 VecOffset += 8;
324 // Pairs are expanded into two instructions: make sure that both
325 // can use the same base (i.e. VecOffset+1 is not a different
326 // multiple of 16 than VecOffset).
327 if (!IsPair || (VecOffset + 1) % 16 != 0) {
328 RealOffset = (VecOffset & -16) * HwLen;
329 InstOffset = (VecOffset % 16 - 8) * HwLen;
330 }
331 }
332 }
333 }
334
335 // Search backwards in the block for "Reg = A2_addi BP, RealOffset".
336 // This will give us a chance to avoid creating a new register.
337 Register ReuseBP;
338
339 if (ReuseCount < FrameIndexReuseLimit) {
340 unsigned SearchCount = 0, SearchRange = FrameIndexSearchRange;
341 SmallSet<Register,2> SeenVRegs;
342 bool PassedCall = false;
343 LiveRegUnits Defs(*this), Uses(*this);
344
345 for (auto I = std::next(x: II.getReverse()), E = MB.rend(); I != E; ++I) {
346 if (SearchCount == SearchRange)
347 break;
348 ++SearchCount;
349 const MachineInstr &BI = *I;
350 LiveRegUnits::accumulateUsedDefed(MI: BI, ModifiedRegUnits&: Defs, UsedRegUnits&: Uses, TRI: this);
351 PassedCall |= BI.isCall();
352 for (const MachineOperand &Op : BI.operands()) {
353 if (SeenVRegs.size() > 1)
354 break;
355 if (Op.isReg() && Op.getReg().isVirtual())
356 SeenVRegs.insert(V: Op.getReg());
357 }
358 if (BI.getOpcode() != Hexagon::A2_addi)
359 continue;
360 if (BI.getOperand(i: 1).getReg() != BP)
361 continue;
362 const auto &Op2 = BI.getOperand(i: 2);
363 if (!Op2.isImm() || Op2.getImm() != RealOffset)
364 continue;
365
366 Register R = BI.getOperand(i: 0).getReg();
367 if (R.isPhysical()) {
368 if (Defs.available(Reg: R))
369 ReuseBP = R;
370 } else if (R.isVirtual()) {
371 // Extending a range of a virtual register can be dangerous,
372 // since the scavenger will need to find a physical register
373 // for it. Avoid extending the range past a function call,
374 // and avoid overlapping it with another virtual register.
375 if (!PassedCall && SeenVRegs.size() <= 1)
376 ReuseBP = R;
377 }
378 break;
379 }
380 if (ReuseBP)
381 ++ReuseCount;
382 }
383
384 auto &MRI = MF.getRegInfo();
385 if (!ReuseBP) {
386 ReuseBP = MRI.createVirtualRegister(RegClass: &Hexagon::IntRegsRegClass);
387 const DebugLoc &DL = MI.getDebugLoc();
388 BuildMI(BB&: MB, I: II, MIMD: DL, MCID: HII.get(Opcode: Hexagon::A2_addi), DestReg: ReuseBP)
389 .addReg(RegNo: BP)
390 .addImm(Val: RealOffset);
391 }
392 BP = ReuseBP;
393 RealOffset = InstOffset;
394 }
395
396 MI.getOperand(i: FIOp).ChangeToRegister(Reg: BP, isDef: false, isImp: false, isKill: false);
397 MI.getOperand(i: FIOp+1).ChangeToImmediate(ImmVal: RealOffset);
398 return false;
399}
400
401
402bool HexagonRegisterInfo::shouldCoalesce(MachineInstr *MI,
403 const TargetRegisterClass *SrcRC, unsigned SubReg,
404 const TargetRegisterClass *DstRC, unsigned DstSubReg,
405 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
406 // Coalescing will extend the live interval of the destination register.
407 // If the destination register is a vector pair, avoid introducing function
408 // calls into the interval, since it could result in a spilling of a pair
409 // instead of a single vector.
410 MachineFunction &MF = *MI->getParent()->getParent();
411 const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
412 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
413 return true;
414 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
415 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
416 if (!SmallSrc && !SmallDst)
417 return true;
418
419 Register DstReg = MI->getOperand(i: 0).getReg();
420 Register SrcReg = MI->getOperand(i: 1).getReg();
421 const SlotIndexes &Indexes = *LIS.getSlotIndexes();
422 auto HasCall = [&Indexes] (const LiveInterval::Segment &S) {
423 for (SlotIndex I = S.start.getBaseIndex(), E = S.end.getBaseIndex();
424 I != E; I = I.getNextIndex()) {
425 if (const MachineInstr *MI = Indexes.getInstructionFromIndex(index: I))
426 if (MI->isCall())
427 return true;
428 }
429 return false;
430 };
431
432 if (SmallSrc == SmallDst) {
433 // Both must be true, because the case for both being false was
434 // checked earlier. Both registers will be coalesced into a register
435 // of a wider class (HvxWR), and we don't want its live range to
436 // span over calls.
437 return !any_of(Range&: LIS.getInterval(Reg: DstReg), P: HasCall) &&
438 !any_of(Range&: LIS.getInterval(Reg: SrcReg), P: HasCall);
439 }
440
441 // If one register is large (HvxWR) and the other is small (HvxVR), then
442 // coalescing is ok if the large is already live across a function call,
443 // or if the small one is not.
444 Register SmallReg = SmallSrc ? SrcReg : DstReg;
445 Register LargeReg = SmallSrc ? DstReg : SrcReg;
446 return any_of(Range&: LIS.getInterval(Reg: LargeReg), P: HasCall) ||
447 !any_of(Range&: LIS.getInterval(Reg: SmallReg), P: HasCall);
448}
449
450
451Register HexagonRegisterInfo::getFrameRegister(const MachineFunction
452 &MF) const {
453 const HexagonFrameLowering *TFI = getFrameLowering(MF);
454 if (TFI->hasFP(MF))
455 return getFrameRegister();
456 return getStackRegister();
457}
458
459
460Register HexagonRegisterInfo::getFrameRegister() const {
461 return Hexagon::R30;
462}
463
464
465Register HexagonRegisterInfo::getStackRegister() const {
466 return Hexagon::R29;
467}
468
469
470unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
471 const TargetRegisterClass &RC, unsigned GenIdx) const {
472 assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
473
474 static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
475 static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
476 static const unsigned WSub[] = { Hexagon::wsub_lo, Hexagon::wsub_hi };
477
478 switch (RC.getID()) {
479 case Hexagon::CtrRegs64RegClassID:
480 case Hexagon::DoubleRegsRegClassID:
481 return ISub[GenIdx];
482 case Hexagon::HvxWRRegClassID:
483 return VSub[GenIdx];
484 case Hexagon::HvxVQRRegClassID:
485 return WSub[GenIdx];
486 }
487
488 if (!RC.superclasses().empty())
489 return getHexagonSubRegIndex(RC: *getRegClass(i: *RC.superclasses().begin()),
490 GenIdx);
491
492 llvm_unreachable("Invalid register class");
493}
494
495bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF)
496 const {
497 return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
498}
499
500const TargetRegisterClass *
501HexagonRegisterInfo::getPointerRegClass(unsigned Kind) const {
502 return &Hexagon::IntRegsRegClass;
503}
504