1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass LoongArchMCRegisterClasses[];
12
13static const MVT::SimpleValueType LoongArchVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::f64, MVT::Other,
18 /* 8 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::Other,
19 /* 15 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
20};
21
22#ifdef __GNUC__
23#pragma GCC diagnostic push
24#pragma GCC diagnostic ignored "-Woverlength-strings"
25#endif
26static constexpr char LoongArchSubRegIndexStrings[] = {
27 /* 0 */ "sub_32\000"
28 /* 7 */ "sub_64\000"
29 /* 14 */ "sub_128\000"
30};
31#ifdef __GNUC__
32#pragma GCC diagnostic pop
33#endif
34
35
36static constexpr uint32_t LoongArchSubRegIndexNameOffsets[] = {
37 0,
38 7,
39 14,
40};
41
42static const TargetRegisterInfo::SubRegCoveredBits LoongArchSubRegIdxRangeTable[] = {
43 { .Offset: 4294967295, .Size: 4294967295 },
44 { .Offset: 0, .Size: 32 }, // sub_32
45 { .Offset: 0, .Size: 64 }, // sub_64
46 { .Offset: 0, .Size: 128 }, // sub_128
47 { .Offset: 4294967295, .Size: 4294967295 },
48 { .Offset: 0, .Size: 32 }, // sub_32
49 { .Offset: 0, .Size: 64 }, // sub_64
50 { .Offset: 0, .Size: 128 }, // sub_128
51};
52
53
54static const LaneBitmask LoongArchSubRegIndexLaneMaskTable[] = {
55 LaneBitmask::getAll(),
56 LaneBitmask(0x0000000000000001), // sub_32
57 LaneBitmask(0x0000000000000001), // sub_64
58 LaneBitmask(0x0000000000000001), // sub_128
59 };
60
61
62
63static const TargetRegisterInfo::RegClassInfo LoongArchRegClassInfos[] = {
64 // Mode = 0 (DefaultMode)
65 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 4 }, // FPR32
66 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // GPR
67 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // GPRJR
68 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // GPRNoR0R1
69 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // GPRT
70 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // CFR
71 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // FCSR
72 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // SCR
73 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 6 }, // FPR64
74 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*LoongArchVTLists+*/.VTListOffset: 8 }, // LSX128
75 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*LoongArchVTLists+*/.VTListOffset: 15 }, // LASX256
76 // Mode = 1 (LA64)
77 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 4 }, // FPR32
78 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // GPR
79 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // GPRJR
80 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // GPRNoR0R1
81 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // GPRT
82 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // CFR
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // FCSR
84 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // SCR
85 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 6 }, // FPR64
86 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*LoongArchVTLists+*/.VTListOffset: 8 }, // LSX128
87 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*LoongArchVTLists+*/.VTListOffset: 15 }, // LASX256
88};
89static const uint32_t FPR32SubClassMask[] = {
90 0x00000001,
91 0x00000700, // sub_32
92};
93
94static const uint32_t GPRSubClassMask[] = {
95 0x0000001e,
96};
97
98static const uint32_t GPRJRSubClassMask[] = {
99 0x0000001c,
100};
101
102static const uint32_t GPRNoR0R1SubClassMask[] = {
103 0x00000018,
104};
105
106static const uint32_t GPRTSubClassMask[] = {
107 0x00000010,
108};
109
110static const uint32_t CFRSubClassMask[] = {
111 0x00000020,
112};
113
114static const uint32_t FCSRSubClassMask[] = {
115 0x00000040,
116};
117
118static const uint32_t SCRSubClassMask[] = {
119 0x00000080,
120};
121
122static const uint32_t FPR64SubClassMask[] = {
123 0x00000100,
124 0x00000600, // sub_64
125};
126
127static const uint32_t LSX128SubClassMask[] = {
128 0x00000200,
129 0x00000400, // sub_128
130};
131
132static const uint32_t LASX256SubClassMask[] = {
133 0x00000400,
134};
135
136static const uint16_t SuperRegIdxSeqs[] = {
137 /* 0 */ 1, 0,
138 /* 2 */ 2, 0,
139 /* 4 */ 3, 0,
140};
141
142static unsigned const GPRJRSuperclasses[] = {
143 LoongArch::GPRRegClassID,
144};
145
146static unsigned const GPRNoR0R1Superclasses[] = {
147 LoongArch::GPRRegClassID,
148 LoongArch::GPRJRRegClassID,
149};
150
151static unsigned const GPRTSuperclasses[] = {
152 LoongArch::GPRRegClassID,
153 LoongArch::GPRJRRegClassID,
154 LoongArch::GPRNoR0R1RegClassID,
155};
156
157namespace LoongArch {
158
159// Register class instances.
160 extern const TargetRegisterClass FPR32RegClass = {
161 .MC: &LoongArchMCRegisterClasses[FPR32RegClassID],
162 .SubClassMask: FPR32SubClassMask,
163 .SuperRegIndices: SuperRegIdxSeqs + 0,
164 .LaneMask: LaneBitmask(0x0000000000000001),
165 .AllocationPriority: 0,
166 .GlobalPriority: false,
167 .TSFlags: 0x00, /* TSFlags */
168 .SpillStackID: 0, /* SpillStackID */
169 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
170 .CoveredBySubRegs: false, /* CoveredBySubRegs */
171 .SuperClasses: nullptr, .SuperClassesSize: 0,
172 .OrderFunc: nullptr
173 };
174
175 extern const TargetRegisterClass GPRRegClass = {
176 .MC: &LoongArchMCRegisterClasses[GPRRegClassID],
177 .SubClassMask: GPRSubClassMask,
178 .SuperRegIndices: SuperRegIdxSeqs + 1,
179 .LaneMask: LaneBitmask(0x0000000000000001),
180 .AllocationPriority: 0,
181 .GlobalPriority: false,
182 .TSFlags: 0x00, /* TSFlags */
183 .SpillStackID: 0, /* SpillStackID */
184 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
185 .CoveredBySubRegs: false, /* CoveredBySubRegs */
186 .SuperClasses: nullptr, .SuperClassesSize: 0,
187 .OrderFunc: nullptr
188 };
189
190 extern const TargetRegisterClass GPRJRRegClass = {
191 .MC: &LoongArchMCRegisterClasses[GPRJRRegClassID],
192 .SubClassMask: GPRJRSubClassMask,
193 .SuperRegIndices: SuperRegIdxSeqs + 1,
194 .LaneMask: LaneBitmask(0x0000000000000001),
195 .AllocationPriority: 0,
196 .GlobalPriority: false,
197 .TSFlags: 0x00, /* TSFlags */
198 .SpillStackID: 0, /* SpillStackID */
199 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
200 .CoveredBySubRegs: false, /* CoveredBySubRegs */
201 .SuperClasses: GPRJRSuperclasses, .SuperClassesSize: 1,
202 .OrderFunc: nullptr
203 };
204
205 extern const TargetRegisterClass GPRNoR0R1RegClass = {
206 .MC: &LoongArchMCRegisterClasses[GPRNoR0R1RegClassID],
207 .SubClassMask: GPRNoR0R1SubClassMask,
208 .SuperRegIndices: SuperRegIdxSeqs + 1,
209 .LaneMask: LaneBitmask(0x0000000000000001),
210 .AllocationPriority: 0,
211 .GlobalPriority: false,
212 .TSFlags: 0x00, /* TSFlags */
213 .SpillStackID: 0, /* SpillStackID */
214 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
215 .CoveredBySubRegs: false, /* CoveredBySubRegs */
216 .SuperClasses: GPRNoR0R1Superclasses, .SuperClassesSize: 2,
217 .OrderFunc: nullptr
218 };
219
220 extern const TargetRegisterClass GPRTRegClass = {
221 .MC: &LoongArchMCRegisterClasses[GPRTRegClassID],
222 .SubClassMask: GPRTSubClassMask,
223 .SuperRegIndices: SuperRegIdxSeqs + 1,
224 .LaneMask: LaneBitmask(0x0000000000000001),
225 .AllocationPriority: 0,
226 .GlobalPriority: false,
227 .TSFlags: 0x00, /* TSFlags */
228 .SpillStackID: 0, /* SpillStackID */
229 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
230 .CoveredBySubRegs: false, /* CoveredBySubRegs */
231 .SuperClasses: GPRTSuperclasses, .SuperClassesSize: 3,
232 .OrderFunc: nullptr
233 };
234
235 extern const TargetRegisterClass CFRRegClass = {
236 .MC: &LoongArchMCRegisterClasses[CFRRegClassID],
237 .SubClassMask: CFRSubClassMask,
238 .SuperRegIndices: SuperRegIdxSeqs + 1,
239 .LaneMask: LaneBitmask(0x0000000000000001),
240 .AllocationPriority: 0,
241 .GlobalPriority: false,
242 .TSFlags: 0x00, /* TSFlags */
243 .SpillStackID: 0, /* SpillStackID */
244 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
245 .CoveredBySubRegs: false, /* CoveredBySubRegs */
246 .SuperClasses: nullptr, .SuperClassesSize: 0,
247 .OrderFunc: nullptr
248 };
249
250 extern const TargetRegisterClass FCSRRegClass = {
251 .MC: &LoongArchMCRegisterClasses[FCSRRegClassID],
252 .SubClassMask: FCSRSubClassMask,
253 .SuperRegIndices: SuperRegIdxSeqs + 1,
254 .LaneMask: LaneBitmask(0x0000000000000001),
255 .AllocationPriority: 0,
256 .GlobalPriority: false,
257 .TSFlags: 0x00, /* TSFlags */
258 .SpillStackID: 0, /* SpillStackID */
259 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
260 .CoveredBySubRegs: false, /* CoveredBySubRegs */
261 .SuperClasses: nullptr, .SuperClassesSize: 0,
262 .OrderFunc: nullptr
263 };
264
265 extern const TargetRegisterClass SCRRegClass = {
266 .MC: &LoongArchMCRegisterClasses[SCRRegClassID],
267 .SubClassMask: SCRSubClassMask,
268 .SuperRegIndices: SuperRegIdxSeqs + 1,
269 .LaneMask: LaneBitmask(0x0000000000000001),
270 .AllocationPriority: 0,
271 .GlobalPriority: false,
272 .TSFlags: 0x00, /* TSFlags */
273 .SpillStackID: 0, /* SpillStackID */
274 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
275 .CoveredBySubRegs: false, /* CoveredBySubRegs */
276 .SuperClasses: nullptr, .SuperClassesSize: 0,
277 .OrderFunc: nullptr
278 };
279
280 extern const TargetRegisterClass FPR64RegClass = {
281 .MC: &LoongArchMCRegisterClasses[FPR64RegClassID],
282 .SubClassMask: FPR64SubClassMask,
283 .SuperRegIndices: SuperRegIdxSeqs + 2,
284 .LaneMask: LaneBitmask(0x0000000000000001),
285 .AllocationPriority: 0,
286 .GlobalPriority: false,
287 .TSFlags: 0x00, /* TSFlags */
288 .SpillStackID: 0, /* SpillStackID */
289 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
290 .CoveredBySubRegs: false, /* CoveredBySubRegs */
291 .SuperClasses: nullptr, .SuperClassesSize: 0,
292 .OrderFunc: nullptr
293 };
294
295 extern const TargetRegisterClass LSX128RegClass = {
296 .MC: &LoongArchMCRegisterClasses[LSX128RegClassID],
297 .SubClassMask: LSX128SubClassMask,
298 .SuperRegIndices: SuperRegIdxSeqs + 4,
299 .LaneMask: LaneBitmask(0x0000000000000001),
300 .AllocationPriority: 0,
301 .GlobalPriority: false,
302 .TSFlags: 0x00, /* TSFlags */
303 .SpillStackID: 0, /* SpillStackID */
304 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
305 .CoveredBySubRegs: false, /* CoveredBySubRegs */
306 .SuperClasses: nullptr, .SuperClassesSize: 0,
307 .OrderFunc: nullptr
308 };
309
310 extern const TargetRegisterClass LASX256RegClass = {
311 .MC: &LoongArchMCRegisterClasses[LASX256RegClassID],
312 .SubClassMask: LASX256SubClassMask,
313 .SuperRegIndices: SuperRegIdxSeqs + 1,
314 .LaneMask: LaneBitmask(0x0000000000000001),
315 .AllocationPriority: 0,
316 .GlobalPriority: false,
317 .TSFlags: 0x00, /* TSFlags */
318 .SpillStackID: 0, /* SpillStackID */
319 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
320 .CoveredBySubRegs: false, /* CoveredBySubRegs */
321 .SuperClasses: nullptr, .SuperClassesSize: 0,
322 .OrderFunc: nullptr
323 };
324
325
326} // namespace LoongArch
327static const TargetRegisterClass *const LoongArchRegisterClasses[] = {
328 &LoongArch::FPR32RegClass,
329 &LoongArch::GPRRegClass,
330 &LoongArch::GPRJRRegClass,
331 &LoongArch::GPRNoR0R1RegClass,
332 &LoongArch::GPRTRegClass,
333 &LoongArch::CFRRegClass,
334 &LoongArch::FCSRRegClass,
335 &LoongArch::SCRRegClass,
336 &LoongArch::FPR64RegClass,
337 &LoongArch::LSX128RegClass,
338 &LoongArch::LASX256RegClass,
339 };
340
341static const uint8_t LoongArchCostPerUseTable[] = {
3420, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
343
344
345static const bool LoongArchInAllocatableClassTable[] = {
346false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
347
348
349static const TargetRegisterInfoDesc LoongArchRegInfoDesc = { // Extra Descriptors
350.CostPerUse: LoongArchCostPerUseTable, .NumCosts: 1, .InAllocatableClass: LoongArchInAllocatableClassTable};
351
352unsigned LoongArchGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
353 static const uint8_t Rows[1][3] = {
354 { LoongArch::sub_32, LoongArch::sub_64, 0, },
355 };
356
357 --IdxA; assert(IdxA < 3); (void) IdxA;
358 --IdxB; assert(IdxB < 3);
359 return Rows[0][IdxB];
360}
361
362unsigned LoongArchGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
363 static const uint8_t Table[3][3] = {
364 { LoongArch::sub_32, LoongArch::sub_64, 0, },
365 { LoongArch::sub_32, LoongArch::sub_64, 0, },
366 { LoongArch::sub_32, LoongArch::sub_64, 0, },
367 };
368
369 --IdxA; assert(IdxA < 3);
370 --IdxB; assert(IdxB < 3);
371 return Table[IdxA][IdxB];
372 }
373
374 struct MaskRolOp {
375 LaneBitmask Mask;
376 uint8_t RotateLeft;
377 };
378 static const MaskRolOp LaneMaskComposeSequences[] = {
379 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
380 };
381 static const uint8_t CompositeSequences[] = {
382 0, // to sub_32
383 0, // to sub_64
384 0 // to sub_128
385 };
386
387LaneBitmask LoongArchGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
388 --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
389 LaneBitmask Result;
390 for (const MaskRolOp *Ops =
391 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
392 Ops->Mask.any(); ++Ops) {
393 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
394 if (unsigned S = Ops->RotateLeft)
395 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
396 else
397 Result |= LaneBitmask(M);
398 }
399 return Result;
400}
401
402LaneBitmask LoongArchGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
403 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
404 --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
405 LaneBitmask Result;
406 for (const MaskRolOp *Ops =
407 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
408 Ops->Mask.any(); ++Ops) {
409 LaneBitmask::Type M = LaneMask.getAsInteger();
410 if (unsigned S = Ops->RotateLeft)
411 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
412 else
413 Result |= LaneBitmask(M);
414 }
415 return Result;
416}
417
418const TargetRegisterClass *LoongArchGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
419 static constexpr uint8_t Table[11][3] = {
420 { // FPR32
421 0, // sub_32
422 0, // sub_64
423 0, // sub_128
424 },
425 { // GPR
426 0, // sub_32
427 0, // sub_64
428 0, // sub_128
429 },
430 { // GPRJR
431 0, // sub_32
432 0, // sub_64
433 0, // sub_128
434 },
435 { // GPRNoR0R1
436 0, // sub_32
437 0, // sub_64
438 0, // sub_128
439 },
440 { // GPRT
441 0, // sub_32
442 0, // sub_64
443 0, // sub_128
444 },
445 { // CFR
446 0, // sub_32
447 0, // sub_64
448 0, // sub_128
449 },
450 { // FCSR
451 0, // sub_32
452 0, // sub_64
453 0, // sub_128
454 },
455 { // SCR
456 0, // sub_32
457 0, // sub_64
458 0, // sub_128
459 },
460 { // FPR64
461 9, // sub_32 -> FPR64
462 0, // sub_64
463 0, // sub_128
464 },
465 { // LSX128
466 10, // sub_32 -> LSX128
467 10, // sub_64 -> LSX128
468 0, // sub_128
469 },
470 { // LASX256
471 11, // sub_32 -> LASX256
472 11, // sub_64 -> LASX256
473 11, // sub_128 -> LASX256
474 },
475
476 };
477 assert(RC && "Missing regclass");
478 if (!Idx) return RC;
479 --Idx;
480 assert(Idx < 3 && "Bad subreg");
481 unsigned TV = Table[RC->getID()][Idx];
482 return TV ? getRegClass(i: TV - 1) : nullptr;
483}const TargetRegisterClass *LoongArchGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
484 static constexpr uint8_t Table[11][3] = {
485 { // FPR32
486 0, // FPR32:sub_32
487 0, // FPR32:sub_64
488 0, // FPR32:sub_128
489 },
490 { // GPR
491 0, // GPR:sub_32
492 0, // GPR:sub_64
493 0, // GPR:sub_128
494 },
495 { // GPRJR
496 0, // GPRJR:sub_32
497 0, // GPRJR:sub_64
498 0, // GPRJR:sub_128
499 },
500 { // GPRNoR0R1
501 0, // GPRNoR0R1:sub_32
502 0, // GPRNoR0R1:sub_64
503 0, // GPRNoR0R1:sub_128
504 },
505 { // GPRT
506 0, // GPRT:sub_32
507 0, // GPRT:sub_64
508 0, // GPRT:sub_128
509 },
510 { // CFR
511 0, // CFR:sub_32
512 0, // CFR:sub_64
513 0, // CFR:sub_128
514 },
515 { // FCSR
516 0, // FCSR:sub_32
517 0, // FCSR:sub_64
518 0, // FCSR:sub_128
519 },
520 { // SCR
521 0, // SCR:sub_32
522 0, // SCR:sub_64
523 0, // SCR:sub_128
524 },
525 { // FPR64
526 1, // FPR64:sub_32 -> FPR32
527 0, // FPR64:sub_64
528 0, // FPR64:sub_128
529 },
530 { // LSX128
531 1, // LSX128:sub_32 -> FPR32
532 9, // LSX128:sub_64 -> FPR64
533 0, // LSX128:sub_128
534 },
535 { // LASX256
536 1, // LASX256:sub_32 -> FPR32
537 9, // LASX256:sub_64 -> FPR64
538 10, // LASX256:sub_128 -> LSX128
539 },
540
541 };
542 assert(RC && "Missing regclass");
543 if (!Idx) return RC;
544 --Idx;
545 assert(Idx < 3 && "Bad subreg");
546 unsigned TV = Table[RC->getID()][Idx];
547 return TV ? getRegClass(i: TV - 1) : nullptr;
548}/// Get the weight in units of pressure for this register class.
549const RegClassWeight &LoongArchGenRegisterInfo::
550getRegClassWeight(const TargetRegisterClass *RC) const {
551 static const RegClassWeight RCWeightTable[] = {
552 {.RegWeight: 1, .WeightLimit: 32}, // FPR32
553 {.RegWeight: 1, .WeightLimit: 32}, // GPR
554 {.RegWeight: 1, .WeightLimit: 31}, // GPRJR
555 {.RegWeight: 1, .WeightLimit: 30}, // GPRNoR0R1
556 {.RegWeight: 1, .WeightLimit: 17}, // GPRT
557 {.RegWeight: 1, .WeightLimit: 8}, // CFR
558 {.RegWeight: 0, .WeightLimit: 0}, // FCSR
559 {.RegWeight: 0, .WeightLimit: 0}, // SCR
560 {.RegWeight: 1, .WeightLimit: 32}, // FPR64
561 {.RegWeight: 1, .WeightLimit: 32}, // LSX128
562 {.RegWeight: 1, .WeightLimit: 32}, // LASX256
563 };
564 return RCWeightTable[RC->getID()];
565}
566
567/// Get the weight in units of pressure for this register unit.
568unsigned LoongArchGenRegisterInfo::
569getRegUnitWeight(MCRegUnit RegUnit) const {
570 assert(static_cast<unsigned>(RegUnit) < 80 && "invalid register unit");
571 // All register units have unit weight.
572 return 1;
573}
574
575
576// Get the number of dimensions of register pressure.
577unsigned LoongArchGenRegisterInfo::getNumRegPressureSets() const {
578 return 4;
579}
580
581// Get the name of this register unit pressure set.
582const char *LoongArchGenRegisterInfo::
583getRegPressureSetName(unsigned Idx) const {
584 static const char *PressureNameTable[] = {
585 "CFR",
586 "GPRT",
587 "FPR32",
588 "GPR",
589 };
590 return PressureNameTable[Idx];
591}
592
593// Get the register unit pressure limit for this dimension.
594// This limit must be adjusted dynamically for reserved registers.
595unsigned LoongArchGenRegisterInfo::
596getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
597 static const uint8_t PressureLimitTable[] = {
598 8, // 0: CFR
599 17, // 1: GPRT
600 32, // 2: FPR32
601 32, // 3: GPR
602 };
603 return PressureLimitTable[Idx];
604}
605
606/// Table of pressure sets per register class or unit.
607static const int RCSetsTable[] = {
608 /* 0 */ 0, -1,
609 /* 2 */ 2, -1,
610 /* 4 */ 1, 3, -1,
611};
612
613/// Get the dimensions of register pressure impacted by this register class.
614/// Returns a -1 terminated array of pressure set IDs
615const int *LoongArchGenRegisterInfo::
616getRegClassPressureSets(const TargetRegisterClass *RC) const {
617 static const uint8_t RCSetStartTable[] = {
618 2,5,5,5,4,0,1,1,2,2,2,};
619 return &RCSetsTable[RCSetStartTable[RC->getID()]];
620}
621
622/// Get the dimensions of register pressure impacted by this register unit.
623/// Returns a -1 terminated array of pressure set IDs
624const int *LoongArchGenRegisterInfo::
625getRegUnitPressureSets(MCRegUnit RegUnit) const {
626 assert(static_cast<unsigned>(RegUnit) < 80 && "invalid register unit");
627 static const uint8_t RUSetStartTable[] = {
628 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,1,1,1,1,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,1,1,1,1,};
629 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
630}
631
632
633// Register to minimal register class mapping
634
635const TargetRegisterClass *LoongArchGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
636 static const uint16_t InvalidRegClassID = UINT16_MAX;
637
638 static const uint16_t Mapping[177] = {
639 InvalidRegClassID, // NoRegister
640 LoongArch::FPR32RegClassID, // F0
641 LoongArch::FPR32RegClassID, // F1
642 LoongArch::FPR32RegClassID, // F2
643 LoongArch::FPR32RegClassID, // F3
644 LoongArch::FPR32RegClassID, // F4
645 LoongArch::FPR32RegClassID, // F5
646 LoongArch::FPR32RegClassID, // F6
647 LoongArch::FPR32RegClassID, // F7
648 LoongArch::FPR32RegClassID, // F8
649 LoongArch::FPR32RegClassID, // F9
650 LoongArch::FPR32RegClassID, // F10
651 LoongArch::FPR32RegClassID, // F11
652 LoongArch::FPR32RegClassID, // F12
653 LoongArch::FPR32RegClassID, // F13
654 LoongArch::FPR32RegClassID, // F14
655 LoongArch::FPR32RegClassID, // F15
656 LoongArch::FPR32RegClassID, // F16
657 LoongArch::FPR32RegClassID, // F17
658 LoongArch::FPR32RegClassID, // F18
659 LoongArch::FPR32RegClassID, // F19
660 LoongArch::FPR32RegClassID, // F20
661 LoongArch::FPR32RegClassID, // F21
662 LoongArch::FPR32RegClassID, // F22
663 LoongArch::FPR32RegClassID, // F23
664 LoongArch::FPR32RegClassID, // F24
665 LoongArch::FPR32RegClassID, // F25
666 LoongArch::FPR32RegClassID, // F26
667 LoongArch::FPR32RegClassID, // F27
668 LoongArch::FPR32RegClassID, // F28
669 LoongArch::FPR32RegClassID, // F29
670 LoongArch::FPR32RegClassID, // F30
671 LoongArch::FPR32RegClassID, // F31
672 LoongArch::CFRRegClassID, // FCC0
673 LoongArch::CFRRegClassID, // FCC1
674 LoongArch::CFRRegClassID, // FCC2
675 LoongArch::CFRRegClassID, // FCC3
676 LoongArch::CFRRegClassID, // FCC4
677 LoongArch::CFRRegClassID, // FCC5
678 LoongArch::CFRRegClassID, // FCC6
679 LoongArch::CFRRegClassID, // FCC7
680 LoongArch::FCSRRegClassID, // FCSR0
681 LoongArch::FCSRRegClassID, // FCSR1
682 LoongArch::FCSRRegClassID, // FCSR2
683 LoongArch::FCSRRegClassID, // FCSR3
684 LoongArch::GPRJRRegClassID, // R0
685 LoongArch::GPRRegClassID, // R1
686 LoongArch::GPRNoR0R1RegClassID, // R2
687 LoongArch::GPRNoR0R1RegClassID, // R3
688 LoongArch::GPRTRegClassID, // R4
689 LoongArch::GPRTRegClassID, // R5
690 LoongArch::GPRTRegClassID, // R6
691 LoongArch::GPRTRegClassID, // R7
692 LoongArch::GPRTRegClassID, // R8
693 LoongArch::GPRTRegClassID, // R9
694 LoongArch::GPRTRegClassID, // R10
695 LoongArch::GPRTRegClassID, // R11
696 LoongArch::GPRTRegClassID, // R12
697 LoongArch::GPRTRegClassID, // R13
698 LoongArch::GPRTRegClassID, // R14
699 LoongArch::GPRTRegClassID, // R15
700 LoongArch::GPRTRegClassID, // R16
701 LoongArch::GPRTRegClassID, // R17
702 LoongArch::GPRTRegClassID, // R18
703 LoongArch::GPRTRegClassID, // R19
704 LoongArch::GPRTRegClassID, // R20
705 LoongArch::GPRNoR0R1RegClassID, // R21
706 LoongArch::GPRNoR0R1RegClassID, // R22
707 LoongArch::GPRNoR0R1RegClassID, // R23
708 LoongArch::GPRNoR0R1RegClassID, // R24
709 LoongArch::GPRNoR0R1RegClassID, // R25
710 LoongArch::GPRNoR0R1RegClassID, // R26
711 LoongArch::GPRNoR0R1RegClassID, // R27
712 LoongArch::GPRNoR0R1RegClassID, // R28
713 LoongArch::GPRNoR0R1RegClassID, // R29
714 LoongArch::GPRNoR0R1RegClassID, // R30
715 LoongArch::GPRNoR0R1RegClassID, // R31
716 LoongArch::SCRRegClassID, // SCR0
717 LoongArch::SCRRegClassID, // SCR1
718 LoongArch::SCRRegClassID, // SCR2
719 LoongArch::SCRRegClassID, // SCR3
720 LoongArch::LSX128RegClassID, // VR0
721 LoongArch::LSX128RegClassID, // VR1
722 LoongArch::LSX128RegClassID, // VR2
723 LoongArch::LSX128RegClassID, // VR3
724 LoongArch::LSX128RegClassID, // VR4
725 LoongArch::LSX128RegClassID, // VR5
726 LoongArch::LSX128RegClassID, // VR6
727 LoongArch::LSX128RegClassID, // VR7
728 LoongArch::LSX128RegClassID, // VR8
729 LoongArch::LSX128RegClassID, // VR9
730 LoongArch::LSX128RegClassID, // VR10
731 LoongArch::LSX128RegClassID, // VR11
732 LoongArch::LSX128RegClassID, // VR12
733 LoongArch::LSX128RegClassID, // VR13
734 LoongArch::LSX128RegClassID, // VR14
735 LoongArch::LSX128RegClassID, // VR15
736 LoongArch::LSX128RegClassID, // VR16
737 LoongArch::LSX128RegClassID, // VR17
738 LoongArch::LSX128RegClassID, // VR18
739 LoongArch::LSX128RegClassID, // VR19
740 LoongArch::LSX128RegClassID, // VR20
741 LoongArch::LSX128RegClassID, // VR21
742 LoongArch::LSX128RegClassID, // VR22
743 LoongArch::LSX128RegClassID, // VR23
744 LoongArch::LSX128RegClassID, // VR24
745 LoongArch::LSX128RegClassID, // VR25
746 LoongArch::LSX128RegClassID, // VR26
747 LoongArch::LSX128RegClassID, // VR27
748 LoongArch::LSX128RegClassID, // VR28
749 LoongArch::LSX128RegClassID, // VR29
750 LoongArch::LSX128RegClassID, // VR30
751 LoongArch::LSX128RegClassID, // VR31
752 LoongArch::LASX256RegClassID, // XR0
753 LoongArch::LASX256RegClassID, // XR1
754 LoongArch::LASX256RegClassID, // XR2
755 LoongArch::LASX256RegClassID, // XR3
756 LoongArch::LASX256RegClassID, // XR4
757 LoongArch::LASX256RegClassID, // XR5
758 LoongArch::LASX256RegClassID, // XR6
759 LoongArch::LASX256RegClassID, // XR7
760 LoongArch::LASX256RegClassID, // XR8
761 LoongArch::LASX256RegClassID, // XR9
762 LoongArch::LASX256RegClassID, // XR10
763 LoongArch::LASX256RegClassID, // XR11
764 LoongArch::LASX256RegClassID, // XR12
765 LoongArch::LASX256RegClassID, // XR13
766 LoongArch::LASX256RegClassID, // XR14
767 LoongArch::LASX256RegClassID, // XR15
768 LoongArch::LASX256RegClassID, // XR16
769 LoongArch::LASX256RegClassID, // XR17
770 LoongArch::LASX256RegClassID, // XR18
771 LoongArch::LASX256RegClassID, // XR19
772 LoongArch::LASX256RegClassID, // XR20
773 LoongArch::LASX256RegClassID, // XR21
774 LoongArch::LASX256RegClassID, // XR22
775 LoongArch::LASX256RegClassID, // XR23
776 LoongArch::LASX256RegClassID, // XR24
777 LoongArch::LASX256RegClassID, // XR25
778 LoongArch::LASX256RegClassID, // XR26
779 LoongArch::LASX256RegClassID, // XR27
780 LoongArch::LASX256RegClassID, // XR28
781 LoongArch::LASX256RegClassID, // XR29
782 LoongArch::LASX256RegClassID, // XR30
783 LoongArch::LASX256RegClassID, // XR31
784 LoongArch::FPR64RegClassID, // F0_64
785 LoongArch::FPR64RegClassID, // F1_64
786 LoongArch::FPR64RegClassID, // F2_64
787 LoongArch::FPR64RegClassID, // F3_64
788 LoongArch::FPR64RegClassID, // F4_64
789 LoongArch::FPR64RegClassID, // F5_64
790 LoongArch::FPR64RegClassID, // F6_64
791 LoongArch::FPR64RegClassID, // F7_64
792 LoongArch::FPR64RegClassID, // F8_64
793 LoongArch::FPR64RegClassID, // F9_64
794 LoongArch::FPR64RegClassID, // F10_64
795 LoongArch::FPR64RegClassID, // F11_64
796 LoongArch::FPR64RegClassID, // F12_64
797 LoongArch::FPR64RegClassID, // F13_64
798 LoongArch::FPR64RegClassID, // F14_64
799 LoongArch::FPR64RegClassID, // F15_64
800 LoongArch::FPR64RegClassID, // F16_64
801 LoongArch::FPR64RegClassID, // F17_64
802 LoongArch::FPR64RegClassID, // F18_64
803 LoongArch::FPR64RegClassID, // F19_64
804 LoongArch::FPR64RegClassID, // F20_64
805 LoongArch::FPR64RegClassID, // F21_64
806 LoongArch::FPR64RegClassID, // F22_64
807 LoongArch::FPR64RegClassID, // F23_64
808 LoongArch::FPR64RegClassID, // F24_64
809 LoongArch::FPR64RegClassID, // F25_64
810 LoongArch::FPR64RegClassID, // F26_64
811 LoongArch::FPR64RegClassID, // F27_64
812 LoongArch::FPR64RegClassID, // F28_64
813 LoongArch::FPR64RegClassID, // F29_64
814 LoongArch::FPR64RegClassID, // F30_64
815 LoongArch::FPR64RegClassID, // F31_64
816 };
817
818 assert(Reg < ArrayRef(Mapping).size());
819 unsigned RCID = Mapping[Reg.id()];
820 if (RCID == InvalidRegClassID)
821 return nullptr;
822 return LoongArchRegisterClasses[RCID];
823}
824extern const MCRegisterDesc LoongArchRegDesc[];
825extern const int16_t LoongArchRegDiffLists[];
826extern const LaneBitmask LoongArchLaneMaskLists[];
827extern const char LoongArchRegStrings[];
828extern const char LoongArchRegClassStrings[];
829extern const MCPhysReg LoongArchRegUnitRoots[][2];
830extern const uint16_t LoongArchSubRegIdxLists[];
831extern const uint16_t LoongArchRegEncodingTable[];
832// LoongArch Dwarf<->LLVM register mappings.
833extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[];
834extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize;
835
836extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[];
837extern const unsigned LoongArchEHFlavour0Dwarf2LSize;
838
839extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[];
840extern const unsigned LoongArchDwarfFlavour0L2DwarfSize;
841
842extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[];
843extern const unsigned LoongArchEHFlavour0L2DwarfSize;
844
845
846LoongArchGenRegisterInfo::
847LoongArchGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
848 unsigned PC, unsigned HwMode)
849 : TargetRegisterInfo(&LoongArchRegInfoDesc, LoongArchRegisterClasses,
850 LoongArchSubRegIndexStrings, LoongArchSubRegIndexNameOffsets,
851 LoongArchSubRegIdxRangeTable, LoongArchSubRegIndexLaneMaskTable,
852
853 LaneBitmask(0xFFFFFFFFFFFFFFFE), LoongArchRegClassInfos, LoongArchVTLists, HwMode) {
854 InitMCRegisterInfo(D: LoongArchRegDesc, NR: 177, RA, PC,
855 C: LoongArchMCRegisterClasses, NC: 11, RURoots: LoongArchRegUnitRoots, NRU: 80, DL: LoongArchRegDiffLists,
856 RUMS: LoongArchLaneMaskLists, Strings: LoongArchRegStrings, ClassStrings: LoongArchRegClassStrings, SubIndices: LoongArchSubRegIdxLists, NumIndices: 4,
857 RET: LoongArchRegEncodingTable, RUI: nullptr);
858
859 switch (DwarfFlavour) {
860 default:
861 llvm_unreachable("Unknown DWARF flavour");
862 case 0:
863 mapDwarfRegsToLLVMRegs(Map: LoongArchDwarfFlavour0Dwarf2L, Size: LoongArchDwarfFlavour0Dwarf2LSize, isEH: false);
864 break;
865 }
866 switch (EHFlavour) {
867 default:
868 llvm_unreachable("Unknown DWARF flavour");
869 case 0:
870 mapDwarfRegsToLLVMRegs(Map: LoongArchEHFlavour0Dwarf2L, Size: LoongArchEHFlavour0Dwarf2LSize, isEH: true);
871 break;
872 }
873 switch (DwarfFlavour) {
874 default:
875 llvm_unreachable("Unknown DWARF flavour");
876 case 0:
877 mapLLVMRegsToDwarfRegs(Map: LoongArchDwarfFlavour0L2Dwarf, Size: LoongArchDwarfFlavour0L2DwarfSize, isEH: false);
878 break;
879 }
880 switch (EHFlavour) {
881 default:
882 llvm_unreachable("Unknown DWARF flavour");
883 case 0:
884 mapLLVMRegsToDwarfRegs(Map: LoongArchEHFlavour0L2Dwarf, Size: LoongArchEHFlavour0L2DwarfSize, isEH: true);
885 break;
886 }
887}
888
889static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64, 0 };
890static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x0001fe00, };
891static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31, 0 };
892static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
893static const MCPhysReg CSR_ILP32S_LP64S_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, 0 };
894static const uint32_t CSR_ILP32S_LP64S_RegMask[] = { 0x00000000, 0x00006000, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
895static const MCPhysReg CSR_MostRegs_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, 0 };
896static const uint32_t CSR_MostRegs_RegMask[] = { 0x00000000, 0xe1fe6000, 0x00001ff9, 0x00000000, 0x00000000, 0x00000000, };
897static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
898static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
899static const MCPhysReg CSR_NoneRegs_SaveList[] = { LoongArch::R1, LoongArch::R22, 0 };
900static const uint32_t CSR_NoneRegs_RegMask[] = { 0x00000000, 0x00006000, 0x00000008, 0x00000000, 0x00000000, 0x00000000, };
901
902
903ArrayRef<const uint32_t *> LoongArchGenRegisterInfo::getRegMasks() const {
904 static const uint32_t *const Masks[] = {
905 CSR_ILP32D_LP64D_RegMask,
906 CSR_ILP32F_LP64F_RegMask,
907 CSR_ILP32S_LP64S_RegMask,
908 CSR_MostRegs_RegMask,
909 CSR_NoRegs_RegMask,
910 CSR_NoneRegs_RegMask,
911 };
912 return ArrayRef(Masks);
913}
914
915bool LoongArchGenRegisterInfo::
916isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
917 return
918 false;
919}
920
921bool LoongArchGenRegisterInfo::
922isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
923 return
924 false;
925}
926
927bool LoongArchGenRegisterInfo::
928isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
929 return
930 false;
931}
932
933bool LoongArchGenRegisterInfo::
934isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
935 return
936 false;
937}
938
939bool LoongArchGenRegisterInfo::
940isConstantPhysReg(MCRegister PhysReg) const {
941 return
942 PhysReg == LoongArch::R0 ||
943 false;
944}
945
946ArrayRef<const char *> LoongArchGenRegisterInfo::getRegMaskNames() const {
947 static const char *Names[] = {
948 "CSR_ILP32D_LP64D",
949 "CSR_ILP32F_LP64F",
950 "CSR_ILP32S_LP64S",
951 "CSR_MostRegs",
952 "CSR_NoRegs",
953 "CSR_NoneRegs",
954 };
955 return ArrayRef(Names);
956}
957
958const LoongArchFrameLowering *
959LoongArchGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
960 return static_cast<const LoongArchFrameLowering *>(
961 MF.getSubtarget().getFrameLowering());
962}
963
964
965} // namespace llvm
966