1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<11, 254, 124, 14, 6, 6> LoongArchMCRegisterClassStorage;
12
13static const MVT::SimpleValueType LoongArchVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::f64, MVT::Other,
18 /* 8 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::Other,
19 /* 15 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
20};
21
22#ifdef __GNUC__
23#pragma GCC diagnostic push
24#pragma GCC diagnostic ignored "-Woverlength-strings"
25#endif
26static constexpr char LoongArchSubRegIndexStrings[] = {
27 /* 0 */ "sub_32\000"
28 /* 7 */ "sub_64\000"
29 /* 14 */ "sub_128\000"
30};
31#ifdef __GNUC__
32#pragma GCC diagnostic pop
33#endif
34
35
36static constexpr uint32_t LoongArchSubRegIndexNameOffsets[] = {
37 0,
38 7,
39 14,
40};
41
42static const TargetRegisterInfo::SubRegCoveredBits LoongArchSubRegIdxRangeTable[] = {
43 { .Offset: 4294967295, .Size: 4294967295 },
44 { .Offset: 0, .Size: 32 }, // sub_32
45 { .Offset: 0, .Size: 64 }, // sub_64
46 { .Offset: 0, .Size: 128 }, // sub_128
47 { .Offset: 4294967295, .Size: 4294967295 },
48 { .Offset: 0, .Size: 32 }, // sub_32
49 { .Offset: 0, .Size: 64 }, // sub_64
50 { .Offset: 0, .Size: 128 }, // sub_128
51};
52
53
54static const LaneBitmask LoongArchSubRegIndexLaneMaskTable[] = {
55 LaneBitmask::getAll(),
56 LaneBitmask(0x0000000000000001), // sub_32
57 LaneBitmask(0x0000000000000001), // sub_64
58 LaneBitmask(0x0000000000000001), // sub_128
59 };
60
61
62
63static const TargetRegisterInfo::RegClassInfo LoongArchRegClassInfos[] = {
64 // Mode = 0 (DefaultMode)
65 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 4 }, // FPR32
66 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // GPR
67 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // GPRJR
68 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // GPRNoR0R1
69 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // GPRT
70 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // CFR
71 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // FCSR
72 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // SCR
73 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 6 }, // FPR64
74 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*LoongArchVTLists+*/.VTListOffset: 8 }, // LSX128
75 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*LoongArchVTLists+*/.VTListOffset: 15 }, // LASX256
76 // Mode = 1 (LA64)
77 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 4 }, // FPR32
78 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // GPR
79 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // GPRJR
80 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // GPRNoR0R1
81 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // GPRT
82 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // CFR
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*LoongArchVTLists+*/.VTListOffset: 0 }, // FCSR
84 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 2 }, // SCR
85 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*LoongArchVTLists+*/.VTListOffset: 6 }, // FPR64
86 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*LoongArchVTLists+*/.VTListOffset: 8 }, // LSX128
87 { .RegSize: 256, .SpillSize: 256, .SpillAlignment: 256, /*LoongArchVTLists+*/.VTListOffset: 15 }, // LASX256
88};
89
90static const uint8_t LoongArchCostPerUseTable[] = {
910, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
92
93
94static const bool LoongArchInAllocatableClassTable[] = {
95false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
96
97
98static const TargetRegisterInfoDesc LoongArchRegInfoDesc = { // Extra Descriptors
99.CostPerUse: LoongArchCostPerUseTable, .NumCosts: 1, .InAllocatableClass: LoongArchInAllocatableClassTable};
100
101unsigned LoongArchGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
102 static const uint8_t Rows[1][3] = {
103 { LoongArch::sub_32, LoongArch::sub_64, 0, },
104 };
105
106 --IdxA; assert(IdxA < 3); (void) IdxA;
107 --IdxB; assert(IdxB < 3);
108 return Rows[0][IdxB];
109}
110
111unsigned LoongArchGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
112 static const uint8_t Table[3][3] = {
113 { LoongArch::sub_32, LoongArch::sub_64, 0, },
114 { LoongArch::sub_32, LoongArch::sub_64, 0, },
115 { LoongArch::sub_32, LoongArch::sub_64, 0, },
116 };
117
118 --IdxA; assert(IdxA < 3);
119 --IdxB; assert(IdxB < 3);
120 return Table[IdxA][IdxB];
121 }
122
123 struct MaskRolOp {
124 LaneBitmask Mask;
125 uint8_t RotateLeft;
126 };
127 static const MaskRolOp LaneMaskComposeSequences[] = {
128 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
129 };
130 static const uint8_t CompositeSequences[] = {
131 0, // to sub_32
132 0, // to sub_64
133 0 // to sub_128
134 };
135
136LaneBitmask LoongArchGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
137 --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
138 LaneBitmask Result;
139 for (const MaskRolOp *Ops =
140 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
141 Ops->Mask.any(); ++Ops) {
142 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
143 if (unsigned S = Ops->RotateLeft)
144 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
145 else
146 Result |= LaneBitmask(M);
147 }
148 return Result;
149}
150
151LaneBitmask LoongArchGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
152 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
153 --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
154 LaneBitmask Result;
155 for (const MaskRolOp *Ops =
156 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
157 Ops->Mask.any(); ++Ops) {
158 LaneBitmask::Type M = LaneMask.getAsInteger();
159 if (unsigned S = Ops->RotateLeft)
160 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
161 else
162 Result |= LaneBitmask(M);
163 }
164 return Result;
165}
166
167const TargetRegisterClass *LoongArchGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
168 static constexpr uint8_t Table[11][3] = {
169 { // FPR32
170 0, // sub_32
171 0, // sub_64
172 0, // sub_128
173 },
174 { // GPR
175 0, // sub_32
176 0, // sub_64
177 0, // sub_128
178 },
179 { // GPRJR
180 0, // sub_32
181 0, // sub_64
182 0, // sub_128
183 },
184 { // GPRNoR0R1
185 0, // sub_32
186 0, // sub_64
187 0, // sub_128
188 },
189 { // GPRT
190 0, // sub_32
191 0, // sub_64
192 0, // sub_128
193 },
194 { // CFR
195 0, // sub_32
196 0, // sub_64
197 0, // sub_128
198 },
199 { // FCSR
200 0, // sub_32
201 0, // sub_64
202 0, // sub_128
203 },
204 { // SCR
205 0, // sub_32
206 0, // sub_64
207 0, // sub_128
208 },
209 { // FPR64
210 9, // sub_32 -> FPR64
211 0, // sub_64
212 0, // sub_128
213 },
214 { // LSX128
215 10, // sub_32 -> LSX128
216 10, // sub_64 -> LSX128
217 0, // sub_128
218 },
219 { // LASX256
220 11, // sub_32 -> LASX256
221 11, // sub_64 -> LASX256
222 11, // sub_128 -> LASX256
223 },
224
225 };
226 assert(RC && "Missing regclass");
227 if (!Idx) return RC;
228 --Idx;
229 assert(Idx < 3 && "Bad subreg");
230 unsigned TV = Table[RC->getID()][Idx];
231 return TV ? getRegClass(i: TV - 1) : nullptr;
232}const TargetRegisterClass *LoongArchGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
233 static constexpr uint8_t Table[11][3] = {
234 { // FPR32
235 0, // FPR32:sub_32
236 0, // FPR32:sub_64
237 0, // FPR32:sub_128
238 },
239 { // GPR
240 0, // GPR:sub_32
241 0, // GPR:sub_64
242 0, // GPR:sub_128
243 },
244 { // GPRJR
245 0, // GPRJR:sub_32
246 0, // GPRJR:sub_64
247 0, // GPRJR:sub_128
248 },
249 { // GPRNoR0R1
250 0, // GPRNoR0R1:sub_32
251 0, // GPRNoR0R1:sub_64
252 0, // GPRNoR0R1:sub_128
253 },
254 { // GPRT
255 0, // GPRT:sub_32
256 0, // GPRT:sub_64
257 0, // GPRT:sub_128
258 },
259 { // CFR
260 0, // CFR:sub_32
261 0, // CFR:sub_64
262 0, // CFR:sub_128
263 },
264 { // FCSR
265 0, // FCSR:sub_32
266 0, // FCSR:sub_64
267 0, // FCSR:sub_128
268 },
269 { // SCR
270 0, // SCR:sub_32
271 0, // SCR:sub_64
272 0, // SCR:sub_128
273 },
274 { // FPR64
275 1, // FPR64:sub_32 -> FPR32
276 0, // FPR64:sub_64
277 0, // FPR64:sub_128
278 },
279 { // LSX128
280 1, // LSX128:sub_32 -> FPR32
281 9, // LSX128:sub_64 -> FPR64
282 0, // LSX128:sub_128
283 },
284 { // LASX256
285 1, // LASX256:sub_32 -> FPR32
286 9, // LASX256:sub_64 -> FPR64
287 10, // LASX256:sub_128 -> LSX128
288 },
289
290 };
291 assert(RC && "Missing regclass");
292 if (!Idx) return RC;
293 --Idx;
294 assert(Idx < 3 && "Bad subreg");
295 unsigned TV = Table[RC->getID()][Idx];
296 return TV ? getRegClass(i: TV - 1) : nullptr;
297}/// Get the weight in units of pressure for this register class.
298const RegClassWeight &LoongArchGenRegisterInfo::
299getRegClassWeight(const TargetRegisterClass *RC) const {
300 static const RegClassWeight RCWeightTable[] = {
301 {.RegWeight: 1, .WeightLimit: 32}, // FPR32
302 {.RegWeight: 1, .WeightLimit: 32}, // GPR
303 {.RegWeight: 1, .WeightLimit: 31}, // GPRJR
304 {.RegWeight: 1, .WeightLimit: 30}, // GPRNoR0R1
305 {.RegWeight: 1, .WeightLimit: 17}, // GPRT
306 {.RegWeight: 1, .WeightLimit: 8}, // CFR
307 {.RegWeight: 0, .WeightLimit: 0}, // FCSR
308 {.RegWeight: 0, .WeightLimit: 0}, // SCR
309 {.RegWeight: 1, .WeightLimit: 32}, // FPR64
310 {.RegWeight: 1, .WeightLimit: 32}, // LSX128
311 {.RegWeight: 1, .WeightLimit: 32}, // LASX256
312 };
313 return RCWeightTable[RC->getID()];
314}
315
316/// Get the weight in units of pressure for this register unit.
317unsigned LoongArchGenRegisterInfo::
318getRegUnitWeight(MCRegUnit RegUnit) const {
319 assert(static_cast<unsigned>(RegUnit) < 80 && "invalid register unit");
320 // All register units have unit weight.
321 return 1;
322}
323
324
325// Get the number of dimensions of register pressure.
326unsigned LoongArchGenRegisterInfo::getNumRegPressureSets() const {
327 return 4;
328}
329
330// Get the name of this register unit pressure set.
331const char *LoongArchGenRegisterInfo::
332getRegPressureSetName(unsigned Idx) const {
333 static const char *PressureNameTable[] = {
334 "CFR",
335 "GPRT",
336 "FPR32",
337 "GPR",
338 };
339 return PressureNameTable[Idx];
340}
341
342// Get the register unit pressure limit for this dimension.
343// This limit must be adjusted dynamically for reserved registers.
344unsigned LoongArchGenRegisterInfo::
345getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
346 static const uint8_t PressureLimitTable[] = {
347 8, // 0: CFR
348 17, // 1: GPRT
349 32, // 2: FPR32
350 32, // 3: GPR
351 };
352 return PressureLimitTable[Idx];
353}
354
355/// Table of pressure sets per register class or unit.
356static const int RCSetsTable[] = {
357 /* 0 */ 0, -1,
358 /* 2 */ 2, -1,
359 /* 4 */ 1, 3, -1,
360};
361
362/// Get the dimensions of register pressure impacted by this register class.
363/// Returns a -1 terminated array of pressure set IDs
364const int *LoongArchGenRegisterInfo::
365getRegClassPressureSets(const TargetRegisterClass *RC) const {
366 static const uint8_t RCSetStartTable[] = {
367 2,5,5,5,4,0,1,1,2,2,2,};
368 return &RCSetsTable[RCSetStartTable[RC->getID()]];
369}
370
371/// Get the dimensions of register pressure impacted by this register unit.
372/// Returns a -1 terminated array of pressure set IDs
373const int *LoongArchGenRegisterInfo::
374getRegUnitPressureSets(MCRegUnit RegUnit) const {
375 assert(static_cast<unsigned>(RegUnit) < 80 && "invalid register unit");
376 static const uint8_t RUSetStartTable[] = {
377 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,1,1,1,1,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,1,1,1,1,};
378 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
379}
380
381
382// Register to minimal register class mapping
383
384const TargetRegisterClass *LoongArchGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
385 static const uint16_t InvalidRegClassID = UINT16_MAX;
386
387 static const uint16_t Mapping[177] = {
388 InvalidRegClassID, // NoRegister
389 LoongArch::FPR32RegClassID, // F0
390 LoongArch::FPR32RegClassID, // F1
391 LoongArch::FPR32RegClassID, // F2
392 LoongArch::FPR32RegClassID, // F3
393 LoongArch::FPR32RegClassID, // F4
394 LoongArch::FPR32RegClassID, // F5
395 LoongArch::FPR32RegClassID, // F6
396 LoongArch::FPR32RegClassID, // F7
397 LoongArch::FPR32RegClassID, // F8
398 LoongArch::FPR32RegClassID, // F9
399 LoongArch::FPR32RegClassID, // F10
400 LoongArch::FPR32RegClassID, // F11
401 LoongArch::FPR32RegClassID, // F12
402 LoongArch::FPR32RegClassID, // F13
403 LoongArch::FPR32RegClassID, // F14
404 LoongArch::FPR32RegClassID, // F15
405 LoongArch::FPR32RegClassID, // F16
406 LoongArch::FPR32RegClassID, // F17
407 LoongArch::FPR32RegClassID, // F18
408 LoongArch::FPR32RegClassID, // F19
409 LoongArch::FPR32RegClassID, // F20
410 LoongArch::FPR32RegClassID, // F21
411 LoongArch::FPR32RegClassID, // F22
412 LoongArch::FPR32RegClassID, // F23
413 LoongArch::FPR32RegClassID, // F24
414 LoongArch::FPR32RegClassID, // F25
415 LoongArch::FPR32RegClassID, // F26
416 LoongArch::FPR32RegClassID, // F27
417 LoongArch::FPR32RegClassID, // F28
418 LoongArch::FPR32RegClassID, // F29
419 LoongArch::FPR32RegClassID, // F30
420 LoongArch::FPR32RegClassID, // F31
421 LoongArch::CFRRegClassID, // FCC0
422 LoongArch::CFRRegClassID, // FCC1
423 LoongArch::CFRRegClassID, // FCC2
424 LoongArch::CFRRegClassID, // FCC3
425 LoongArch::CFRRegClassID, // FCC4
426 LoongArch::CFRRegClassID, // FCC5
427 LoongArch::CFRRegClassID, // FCC6
428 LoongArch::CFRRegClassID, // FCC7
429 LoongArch::FCSRRegClassID, // FCSR0
430 LoongArch::FCSRRegClassID, // FCSR1
431 LoongArch::FCSRRegClassID, // FCSR2
432 LoongArch::FCSRRegClassID, // FCSR3
433 LoongArch::GPRJRRegClassID, // R0
434 LoongArch::GPRRegClassID, // R1
435 LoongArch::GPRNoR0R1RegClassID, // R2
436 LoongArch::GPRNoR0R1RegClassID, // R3
437 LoongArch::GPRTRegClassID, // R4
438 LoongArch::GPRTRegClassID, // R5
439 LoongArch::GPRTRegClassID, // R6
440 LoongArch::GPRTRegClassID, // R7
441 LoongArch::GPRTRegClassID, // R8
442 LoongArch::GPRTRegClassID, // R9
443 LoongArch::GPRTRegClassID, // R10
444 LoongArch::GPRTRegClassID, // R11
445 LoongArch::GPRTRegClassID, // R12
446 LoongArch::GPRTRegClassID, // R13
447 LoongArch::GPRTRegClassID, // R14
448 LoongArch::GPRTRegClassID, // R15
449 LoongArch::GPRTRegClassID, // R16
450 LoongArch::GPRTRegClassID, // R17
451 LoongArch::GPRTRegClassID, // R18
452 LoongArch::GPRTRegClassID, // R19
453 LoongArch::GPRTRegClassID, // R20
454 LoongArch::GPRNoR0R1RegClassID, // R21
455 LoongArch::GPRNoR0R1RegClassID, // R22
456 LoongArch::GPRNoR0R1RegClassID, // R23
457 LoongArch::GPRNoR0R1RegClassID, // R24
458 LoongArch::GPRNoR0R1RegClassID, // R25
459 LoongArch::GPRNoR0R1RegClassID, // R26
460 LoongArch::GPRNoR0R1RegClassID, // R27
461 LoongArch::GPRNoR0R1RegClassID, // R28
462 LoongArch::GPRNoR0R1RegClassID, // R29
463 LoongArch::GPRNoR0R1RegClassID, // R30
464 LoongArch::GPRNoR0R1RegClassID, // R31
465 LoongArch::SCRRegClassID, // SCR0
466 LoongArch::SCRRegClassID, // SCR1
467 LoongArch::SCRRegClassID, // SCR2
468 LoongArch::SCRRegClassID, // SCR3
469 LoongArch::LSX128RegClassID, // VR0
470 LoongArch::LSX128RegClassID, // VR1
471 LoongArch::LSX128RegClassID, // VR2
472 LoongArch::LSX128RegClassID, // VR3
473 LoongArch::LSX128RegClassID, // VR4
474 LoongArch::LSX128RegClassID, // VR5
475 LoongArch::LSX128RegClassID, // VR6
476 LoongArch::LSX128RegClassID, // VR7
477 LoongArch::LSX128RegClassID, // VR8
478 LoongArch::LSX128RegClassID, // VR9
479 LoongArch::LSX128RegClassID, // VR10
480 LoongArch::LSX128RegClassID, // VR11
481 LoongArch::LSX128RegClassID, // VR12
482 LoongArch::LSX128RegClassID, // VR13
483 LoongArch::LSX128RegClassID, // VR14
484 LoongArch::LSX128RegClassID, // VR15
485 LoongArch::LSX128RegClassID, // VR16
486 LoongArch::LSX128RegClassID, // VR17
487 LoongArch::LSX128RegClassID, // VR18
488 LoongArch::LSX128RegClassID, // VR19
489 LoongArch::LSX128RegClassID, // VR20
490 LoongArch::LSX128RegClassID, // VR21
491 LoongArch::LSX128RegClassID, // VR22
492 LoongArch::LSX128RegClassID, // VR23
493 LoongArch::LSX128RegClassID, // VR24
494 LoongArch::LSX128RegClassID, // VR25
495 LoongArch::LSX128RegClassID, // VR26
496 LoongArch::LSX128RegClassID, // VR27
497 LoongArch::LSX128RegClassID, // VR28
498 LoongArch::LSX128RegClassID, // VR29
499 LoongArch::LSX128RegClassID, // VR30
500 LoongArch::LSX128RegClassID, // VR31
501 LoongArch::LASX256RegClassID, // XR0
502 LoongArch::LASX256RegClassID, // XR1
503 LoongArch::LASX256RegClassID, // XR2
504 LoongArch::LASX256RegClassID, // XR3
505 LoongArch::LASX256RegClassID, // XR4
506 LoongArch::LASX256RegClassID, // XR5
507 LoongArch::LASX256RegClassID, // XR6
508 LoongArch::LASX256RegClassID, // XR7
509 LoongArch::LASX256RegClassID, // XR8
510 LoongArch::LASX256RegClassID, // XR9
511 LoongArch::LASX256RegClassID, // XR10
512 LoongArch::LASX256RegClassID, // XR11
513 LoongArch::LASX256RegClassID, // XR12
514 LoongArch::LASX256RegClassID, // XR13
515 LoongArch::LASX256RegClassID, // XR14
516 LoongArch::LASX256RegClassID, // XR15
517 LoongArch::LASX256RegClassID, // XR16
518 LoongArch::LASX256RegClassID, // XR17
519 LoongArch::LASX256RegClassID, // XR18
520 LoongArch::LASX256RegClassID, // XR19
521 LoongArch::LASX256RegClassID, // XR20
522 LoongArch::LASX256RegClassID, // XR21
523 LoongArch::LASX256RegClassID, // XR22
524 LoongArch::LASX256RegClassID, // XR23
525 LoongArch::LASX256RegClassID, // XR24
526 LoongArch::LASX256RegClassID, // XR25
527 LoongArch::LASX256RegClassID, // XR26
528 LoongArch::LASX256RegClassID, // XR27
529 LoongArch::LASX256RegClassID, // XR28
530 LoongArch::LASX256RegClassID, // XR29
531 LoongArch::LASX256RegClassID, // XR30
532 LoongArch::LASX256RegClassID, // XR31
533 LoongArch::FPR64RegClassID, // F0_64
534 LoongArch::FPR64RegClassID, // F1_64
535 LoongArch::FPR64RegClassID, // F2_64
536 LoongArch::FPR64RegClassID, // F3_64
537 LoongArch::FPR64RegClassID, // F4_64
538 LoongArch::FPR64RegClassID, // F5_64
539 LoongArch::FPR64RegClassID, // F6_64
540 LoongArch::FPR64RegClassID, // F7_64
541 LoongArch::FPR64RegClassID, // F8_64
542 LoongArch::FPR64RegClassID, // F9_64
543 LoongArch::FPR64RegClassID, // F10_64
544 LoongArch::FPR64RegClassID, // F11_64
545 LoongArch::FPR64RegClassID, // F12_64
546 LoongArch::FPR64RegClassID, // F13_64
547 LoongArch::FPR64RegClassID, // F14_64
548 LoongArch::FPR64RegClassID, // F15_64
549 LoongArch::FPR64RegClassID, // F16_64
550 LoongArch::FPR64RegClassID, // F17_64
551 LoongArch::FPR64RegClassID, // F18_64
552 LoongArch::FPR64RegClassID, // F19_64
553 LoongArch::FPR64RegClassID, // F20_64
554 LoongArch::FPR64RegClassID, // F21_64
555 LoongArch::FPR64RegClassID, // F22_64
556 LoongArch::FPR64RegClassID, // F23_64
557 LoongArch::FPR64RegClassID, // F24_64
558 LoongArch::FPR64RegClassID, // F25_64
559 LoongArch::FPR64RegClassID, // F26_64
560 LoongArch::FPR64RegClassID, // F27_64
561 LoongArch::FPR64RegClassID, // F28_64
562 LoongArch::FPR64RegClassID, // F29_64
563 LoongArch::FPR64RegClassID, // F30_64
564 LoongArch::FPR64RegClassID, // F31_64
565 };
566
567 assert(Reg < ArrayRef(Mapping).size());
568 unsigned RCID = Mapping[Reg.id()];
569 if (RCID == InvalidRegClassID)
570 return nullptr;
571 return &LoongArchMCRegisterClassStorage.Classes[RCID];
572}
573extern const MCRegisterDesc LoongArchRegDesc[];
574extern const int16_t LoongArchRegDiffLists[];
575extern const LaneBitmask LoongArchLaneMaskLists[];
576extern const char LoongArchRegStrings[];
577extern const char LoongArchRegClassStrings[];
578extern const MCPhysReg LoongArchRegUnitRoots[][2];
579extern const uint16_t LoongArchSubRegIdxLists[];
580extern const uint16_t LoongArchRegEncodingTable[];
581// LoongArch Dwarf<->LLVM register mappings.
582extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[];
583extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize;
584
585extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[];
586extern const unsigned LoongArchEHFlavour0Dwarf2LSize;
587
588extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[];
589extern const unsigned LoongArchDwarfFlavour0L2DwarfSize;
590
591extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[];
592extern const unsigned LoongArchEHFlavour0L2DwarfSize;
593
594
595LoongArchGenRegisterInfo::
596LoongArchGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
597 unsigned PC, unsigned HwMode)
598 : TargetRegisterInfo(&LoongArchRegInfoDesc,
599 LoongArchSubRegIndexStrings, LoongArchSubRegIndexNameOffsets,
600 LoongArchSubRegIdxRangeTable, LoongArchSubRegIndexLaneMaskTable,
601
602 LaneBitmask(0xFFFFFFFFFFFFFFFE), LoongArchRegClassInfos, LoongArchVTLists, HwMode) {
603 InitMCRegisterInfo(D: LoongArchRegDesc, NR: 177, RA, PC,
604 C: &getLoongArchMCRegisterClass(RC: 0), NC: 11, RURoots: LoongArchRegUnitRoots, NRU: 80, DL: LoongArchRegDiffLists,
605 RUMS: LoongArchLaneMaskLists, Strings: LoongArchRegStrings, ClassStrings: LoongArchRegClassStrings, SubIndices: LoongArchSubRegIdxLists, NumIndices: 4,
606 RET: LoongArchRegEncodingTable, RUI: nullptr);
607
608 switch (DwarfFlavour) {
609 default:
610 llvm_unreachable("Unknown DWARF flavour");
611 case 0:
612 mapDwarfRegsToLLVMRegs(Map: LoongArchDwarfFlavour0Dwarf2L, Size: LoongArchDwarfFlavour0Dwarf2LSize, isEH: false);
613 break;
614 }
615 switch (EHFlavour) {
616 default:
617 llvm_unreachable("Unknown DWARF flavour");
618 case 0:
619 mapDwarfRegsToLLVMRegs(Map: LoongArchEHFlavour0Dwarf2L, Size: LoongArchEHFlavour0Dwarf2LSize, isEH: true);
620 break;
621 }
622 switch (DwarfFlavour) {
623 default:
624 llvm_unreachable("Unknown DWARF flavour");
625 case 0:
626 mapLLVMRegsToDwarfRegs(Map: LoongArchDwarfFlavour0L2Dwarf, Size: LoongArchDwarfFlavour0L2DwarfSize, isEH: false);
627 break;
628 }
629 switch (EHFlavour) {
630 default:
631 llvm_unreachable("Unknown DWARF flavour");
632 case 0:
633 mapLLVMRegsToDwarfRegs(Map: LoongArchEHFlavour0L2Dwarf, Size: LoongArchEHFlavour0L2DwarfSize, isEH: true);
634 break;
635 }
636}
637
638static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64, 0 };
639static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x0001fe00, };
640static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31, 0 };
641static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
642static const MCPhysReg CSR_ILP32S_LP64S_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, 0 };
643static const uint32_t CSR_ILP32S_LP64S_RegMask[] = { 0x00000000, 0x00006000, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
644static const MCPhysReg CSR_MostRegs_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, 0 };
645static const uint32_t CSR_MostRegs_RegMask[] = { 0x00000000, 0xe1fe6000, 0x00001ff9, 0x00000000, 0x00000000, 0x00000000, };
646static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
647static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
648static const MCPhysReg CSR_NoneRegs_SaveList[] = { LoongArch::R1, LoongArch::R22, 0 };
649static const uint32_t CSR_NoneRegs_RegMask[] = { 0x00000000, 0x00006000, 0x00000008, 0x00000000, 0x00000000, 0x00000000, };
650
651
652ArrayRef<const uint32_t *> LoongArchGenRegisterInfo::getRegMasks() const {
653 static const uint32_t *const Masks[] = {
654 CSR_ILP32D_LP64D_RegMask,
655 CSR_ILP32F_LP64F_RegMask,
656 CSR_ILP32S_LP64S_RegMask,
657 CSR_MostRegs_RegMask,
658 CSR_NoRegs_RegMask,
659 CSR_NoneRegs_RegMask,
660 };
661 return ArrayRef(Masks);
662}
663
664bool LoongArchGenRegisterInfo::
665isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
666 return
667 false;
668}
669
670bool LoongArchGenRegisterInfo::
671isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
672 return
673 false;
674}
675
676bool LoongArchGenRegisterInfo::
677isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
678 return
679 false;
680}
681
682bool LoongArchGenRegisterInfo::
683isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
684 return
685 false;
686}
687
688bool LoongArchGenRegisterInfo::
689isConstantPhysReg(MCRegister PhysReg) const {
690 return
691 PhysReg == LoongArch::R0 ||
692 false;
693}
694
695ArrayRef<const char *> LoongArchGenRegisterInfo::getRegMaskNames() const {
696 static const char *Names[] = {
697 "CSR_ILP32D_LP64D",
698 "CSR_ILP32F_LP64F",
699 "CSR_ILP32S_LP64S",
700 "CSR_MostRegs",
701 "CSR_NoRegs",
702 "CSR_NoneRegs",
703 };
704 return ArrayRef(Names);
705}
706
707const LoongArchFrameLowering *
708LoongArchGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
709 return static_cast<const LoongArchFrameLowering *>(
710 MF.getSubtarget().getFrameLowering());
711}
712
713
714} // namespace llvm
715