1//===- LoongArchRegisterInfo.cpp - LoongArch Register Information -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "LoongArchRegisterInfo.h"
15#include "LoongArch.h"
16#include "LoongArchInstrInfo.h"
17#include "LoongArchSubtarget.h"
18#include "MCTargetDesc/LoongArchBaseInfo.h"
19#include "MCTargetDesc/LoongArchMCTargetDesc.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/RegisterScavenging.h"
24#include "llvm/CodeGen/TargetFrameLowering.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27
28using namespace llvm;
29
30#define GET_REGINFO_TARGET_DESC
31#include "LoongArchGenRegisterInfo.inc"
32
33LoongArchRegisterInfo::LoongArchRegisterInfo(unsigned HwMode)
34 : LoongArchGenRegisterInfo(LoongArch::R1, /*DwarfFlavour*/ 0,
35 /*EHFlavor*/ 0,
36 /*PC*/ 0, HwMode) {}
37
38const MCPhysReg *
39LoongArchRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
40 auto &Subtarget = MF->getSubtarget<LoongArchSubtarget>();
41 auto CC = MF->getFunction().getCallingConv();
42
43 if (CC == CallingConv::GHC)
44 return CSR_NoRegs_SaveList;
45 if (CC == CallingConv::PreserveNone)
46 return CSR_NoneRegs_SaveList;
47 if (CC == CallingConv::PreserveMost)
48 return CSR_MostRegs_SaveList;
49 switch (Subtarget.getTargetABI()) {
50 default:
51 llvm_unreachable("Unrecognized ABI");
52 case LoongArchABI::ABI_ILP32S:
53 case LoongArchABI::ABI_LP64S:
54 return CSR_ILP32S_LP64S_SaveList;
55 case LoongArchABI::ABI_ILP32F:
56 case LoongArchABI::ABI_LP64F:
57 return CSR_ILP32F_LP64F_SaveList;
58 case LoongArchABI::ABI_ILP32D:
59 case LoongArchABI::ABI_LP64D:
60 return CSR_ILP32D_LP64D_SaveList;
61 }
62}
63
64const uint32_t *
65LoongArchRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
66 CallingConv::ID CC) const {
67 auto &Subtarget = MF.getSubtarget<LoongArchSubtarget>();
68
69 if (CC == CallingConv::GHC)
70 return CSR_NoRegs_RegMask;
71 if (CC == CallingConv::PreserveNone)
72 return CSR_NoneRegs_RegMask;
73 if (CC == CallingConv::PreserveMost)
74 return CSR_MostRegs_RegMask;
75 switch (Subtarget.getTargetABI()) {
76 default:
77 llvm_unreachable("Unrecognized ABI");
78 case LoongArchABI::ABI_ILP32S:
79 case LoongArchABI::ABI_LP64S:
80 return CSR_ILP32S_LP64S_RegMask;
81 case LoongArchABI::ABI_ILP32F:
82 case LoongArchABI::ABI_LP64F:
83 return CSR_ILP32F_LP64F_RegMask;
84 case LoongArchABI::ABI_ILP32D:
85 case LoongArchABI::ABI_LP64D:
86 return CSR_ILP32D_LP64D_RegMask;
87 }
88}
89
90const uint32_t *LoongArchRegisterInfo::getNoPreservedMask() const {
91 return CSR_NoRegs_RegMask;
92}
93
94BitVector
95LoongArchRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
96 const LoongArchFrameLowering *TFI = getFrameLowering(MF);
97 BitVector Reserved(getNumRegs());
98
99 // Use markSuperRegs to ensure any register aliases are also reserved
100 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R0); // zero
101 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R2); // tp
102 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R3); // sp
103 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R21); // non-allocatable
104 if (TFI->hasFP(MF))
105 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R22); // fp
106 // Reserve the base register if we need to realign the stack and allocate
107 // variable-sized objects at runtime.
108 if (TFI->hasBP(MF))
109 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArchABI::getBPReg()); // bp
110
111 assert(checkAllSuperRegsMarked(Reserved));
112 return Reserved;
113}
114
115Register
116LoongArchRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
117 const TargetFrameLowering *TFI = getFrameLowering(MF);
118 return TFI->hasFP(MF) ? LoongArch::R22 : LoongArch::R3;
119}
120
121bool LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
122 int SPAdj,
123 unsigned FIOperandNum,
124 RegScavenger *RS) const {
125 // TODO: this implementation is a temporary placeholder which does just
126 // enough to allow other aspects of code generation to be tested.
127
128 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
129
130 MachineInstr &MI = *II;
131 assert(MI.getOperand(FIOperandNum + 1).isImm() &&
132 "Unexpected FI-consuming insn");
133
134 MachineBasicBlock &MBB = *MI.getParent();
135 MachineFunction &MF = *MI.getParent()->getParent();
136 MachineRegisterInfo &MRI = MF.getRegInfo();
137 const LoongArchSubtarget &STI = MF.getSubtarget<LoongArchSubtarget>();
138 const LoongArchInstrInfo *TII = STI.getInstrInfo();
139 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
140 DebugLoc DL = MI.getDebugLoc();
141 bool IsLA64 = STI.is64Bit();
142 unsigned MIOpc = MI.getOpcode();
143
144 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
145 Register FrameReg;
146 StackOffset Offset =
147 TFI->getFrameIndexReference(MF, FI: FrameIndex, FrameReg) +
148 StackOffset::getFixed(Fixed: MI.getOperand(i: FIOperandNum + 1).getImm());
149
150 bool FrameRegIsKill = false;
151
152 int FixedOffset = Offset.getFixed();
153 bool OffsetLegal = true;
154
155 // Handle offsets that exceed the immediate range of the instruction.
156 switch (MIOpc) {
157 case LoongArch::VSTELM_B:
158 case LoongArch::XVSTELM_B:
159 OffsetLegal = isInt<8>(x: FixedOffset);
160 break;
161 case LoongArch::VSTELM_H:
162 case LoongArch::XVSTELM_H:
163 OffsetLegal = isShiftedInt<8, 1>(x: FixedOffset);
164 break;
165 case LoongArch::VSTELM_W:
166 case LoongArch::XVSTELM_W:
167 OffsetLegal = isShiftedInt<8, 2>(x: FixedOffset);
168 break;
169 case LoongArch::VSTELM_D:
170 case LoongArch::XVSTELM_D:
171 OffsetLegal = isShiftedInt<8, 3>(x: FixedOffset);
172 break;
173 }
174
175 if (!OffsetLegal && isInt<12>(x: FixedOffset)) {
176 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
177
178 // The offset fits in si12 but is not legal for the instruction,
179 // so use only one scratch register instead.
180 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
181 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Addi), DestReg: ScratchReg)
182 .addReg(RegNo: FrameReg)
183 .addImm(Val: FixedOffset);
184 Offset = StackOffset::getFixed(Fixed: 0);
185 FrameReg = ScratchReg;
186 FrameRegIsKill = true;
187 }
188
189 if (!isInt<12>(x: FixedOffset)) {
190 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
191 unsigned Add = IsLA64 ? LoongArch::ADD_D : LoongArch::ADD_W;
192
193 // The offset won't fit in an immediate, so use a scratch register instead.
194 // Modify Offset and FrameReg appropriately.
195 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
196 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val: Offset.getFixed());
197 if (MIOpc == Addi) {
198 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Add), DestReg: MI.getOperand(i: 0).getReg())
199 .addReg(RegNo: FrameReg)
200 .addReg(RegNo: ScratchReg, Flags: RegState::Kill);
201 MI.eraseFromParent();
202 return true;
203 }
204 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Add), DestReg: ScratchReg)
205 .addReg(RegNo: FrameReg)
206 .addReg(RegNo: ScratchReg, Flags: RegState::Kill);
207 Offset = StackOffset::getFixed(Fixed: 0);
208 FrameReg = ScratchReg;
209 FrameRegIsKill = true;
210 }
211
212 // Spill CFRs.
213 if (MIOpc == LoongArch::PseudoST_CFR) {
214 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
215 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: LoongArch::MOVCF2GR), DestReg: ScratchReg)
216 .add(MO: MI.getOperand(i: 0));
217 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: IsLA64 ? LoongArch::ST_D : LoongArch::ST_W))
218 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
219 .addReg(RegNo: FrameReg)
220 .addImm(Val: Offset.getFixed());
221 MI.eraseFromParent();
222 return true;
223 }
224
225 // Reload CFRs.
226 if (MIOpc == LoongArch::PseudoLD_CFR) {
227 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
228 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: IsLA64 ? LoongArch::LD_D : LoongArch::LD_W),
229 DestReg: ScratchReg)
230 .addReg(RegNo: FrameReg)
231 .addImm(Val: Offset.getFixed());
232 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: LoongArch::MOVGR2CF))
233 .add(MO: MI.getOperand(i: 0))
234 .addReg(RegNo: ScratchReg, Flags: RegState::Kill);
235 MI.eraseFromParent();
236 return true;
237 }
238
239 MI.getOperand(i: FIOperandNum)
240 .ChangeToRegister(Reg: FrameReg, isDef: false, isImp: false, isKill: FrameRegIsKill);
241 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset.getFixed());
242 return false;
243}
244
245bool LoongArchRegisterInfo::canRealignStack(const MachineFunction &MF) const {
246 if (!TargetRegisterInfo::canRealignStack(MF))
247 return false;
248
249 const MachineRegisterInfo *MRI = &MF.getRegInfo();
250 const LoongArchFrameLowering *TFI = getFrameLowering(MF);
251
252 // Stack realignment requires a frame pointer. If we already started
253 // register allocation with frame pointer elimination, it is too late now.
254 if (!MRI->canReserveReg(PhysReg: LoongArch::R22))
255 return false;
256
257 // We may also need a base pointer if there are dynamic allocas or stack
258 // pointer adjustments around calls.
259 if (TFI->hasReservedCallFrame(MF))
260 return true;
261
262 // A base pointer is required and allowed. Check that it isn't too late to
263 // reserve it.
264 return MRI->canReserveReg(PhysReg: LoongArchABI::getBPReg());
265}
266