1//===- LoongArchRegisterInfo.cpp - LoongArch Register Information -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "LoongArchRegisterInfo.h"
15#include "LoongArch.h"
16#include "LoongArchInstrInfo.h"
17#include "LoongArchSubtarget.h"
18#include "MCTargetDesc/LoongArchBaseInfo.h"
19#include "MCTargetDesc/LoongArchMCTargetDesc.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/RegisterScavenging.h"
24#include "llvm/CodeGen/TargetFrameLowering.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27
28using namespace llvm;
29
30#define GET_REGINFO_TARGET_DESC
31#include "LoongArchGenRegisterInfo.inc"
32
33LoongArchRegisterInfo::LoongArchRegisterInfo(unsigned HwMode)
34 : LoongArchGenRegisterInfo(LoongArch::R1, /*DwarfFlavour*/ 0,
35 /*EHFlavor*/ 0,
36 /*PC*/ 0, HwMode) {}
37
38const MCPhysReg *
39LoongArchRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
40 auto &Subtarget = MF->getSubtarget<LoongArchSubtarget>();
41 auto CC = MF->getFunction().getCallingConv();
42
43 if (CC == CallingConv::GHC)
44 return CSR_NoRegs_SaveList;
45 if (CC == CallingConv::PreserveNone)
46 return CSR_NoneRegs_SaveList;
47 if (CC == CallingConv::PreserveMost)
48 return CSR_MostRegs_SaveList;
49 switch (Subtarget.getTargetABI()) {
50 default:
51 llvm_unreachable("Unrecognized ABI");
52 case LoongArchABI::ABI_ILP32S:
53 case LoongArchABI::ABI_LP64S:
54 return CSR_ILP32S_LP64S_SaveList;
55 case LoongArchABI::ABI_ILP32F:
56 case LoongArchABI::ABI_LP64F:
57 return CSR_ILP32F_LP64F_SaveList;
58 case LoongArchABI::ABI_ILP32D:
59 case LoongArchABI::ABI_LP64D:
60 return CSR_ILP32D_LP64D_SaveList;
61 }
62}
63
64const uint32_t *
65LoongArchRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
66 CallingConv::ID CC) const {
67 auto &Subtarget = MF.getSubtarget<LoongArchSubtarget>();
68
69 if (CC == CallingConv::GHC)
70 return CSR_NoRegs_RegMask;
71 if (CC == CallingConv::PreserveNone)
72 return CSR_NoneRegs_RegMask;
73 if (CC == CallingConv::PreserveMost)
74 return CSR_MostRegs_RegMask;
75 switch (Subtarget.getTargetABI()) {
76 default:
77 llvm_unreachable("Unrecognized ABI");
78 case LoongArchABI::ABI_ILP32S:
79 case LoongArchABI::ABI_LP64S:
80 return CSR_ILP32S_LP64S_RegMask;
81 case LoongArchABI::ABI_ILP32F:
82 case LoongArchABI::ABI_LP64F:
83 return CSR_ILP32F_LP64F_RegMask;
84 case LoongArchABI::ABI_ILP32D:
85 case LoongArchABI::ABI_LP64D:
86 return CSR_ILP32D_LP64D_RegMask;
87 }
88}
89
90const uint32_t *LoongArchRegisterInfo::getNoPreservedMask() const {
91 return CSR_NoRegs_RegMask;
92}
93
94BitVector
95LoongArchRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
96 const LoongArchFrameLowering *TFI = getFrameLowering(MF);
97 BitVector Reserved(getNumRegs());
98
99 // Use markSuperRegs to ensure any register aliases are also reserved
100 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R0); // zero
101 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R2); // tp
102 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R3); // sp
103 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R21); // non-allocatable
104 if (TFI->hasFP(MF))
105 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R22); // fp
106 // Reserve the base register if we need to realign the stack and allocate
107 // variable-sized objects at runtime.
108 if (TFI->hasBP(MF))
109 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArchABI::getBPReg()); // bp
110
111 assert(checkAllSuperRegsMarked(Reserved));
112 return Reserved;
113}
114
115Register
116LoongArchRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
117 const TargetFrameLowering *TFI = getFrameLowering(MF);
118 return TFI->hasFP(MF) ? LoongArch::R22 : LoongArch::R3;
119}
120
121bool LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
122 int SPAdj,
123 unsigned FIOperandNum,
124 RegScavenger *RS) const {
125 // TODO: this implementation is a temporary placeholder which does just
126 // enough to allow other aspects of code generation to be tested.
127
128 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
129
130 MachineInstr &MI = *II;
131 assert(MI.getOperand(FIOperandNum + 1).isImm() &&
132 "Unexpected FI-consuming insn");
133
134 MachineBasicBlock &MBB = *MI.getParent();
135 MachineFunction &MF = *MI.getParent()->getParent();
136 MachineRegisterInfo &MRI = MF.getRegInfo();
137 const LoongArchSubtarget &STI = MF.getSubtarget<LoongArchSubtarget>();
138 const LoongArchInstrInfo *TII = STI.getInstrInfo();
139 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
140 DebugLoc DL = MI.getDebugLoc();
141 bool IsLA64 = STI.is64Bit();
142 unsigned MIOpc = MI.getOpcode();
143
144 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
145 Register FrameReg;
146 StackOffset Offset =
147 TFI->getFrameIndexReference(MF, FI: FrameIndex, FrameReg) +
148 StackOffset::getFixed(Fixed: MI.getOperand(i: FIOperandNum + 1).getImm());
149
150 bool FrameRegIsKill = false;
151
152 int FixedOffset = Offset.getFixed();
153 bool OffsetLegal = true;
154 // True only when the instruction's immediate field is si12.
155 bool HasSimm12Field = false;
156 // Replace ld/st with ldptr/stptr if possible.
157 unsigned PtrOpc = 0;
158
159 switch (MIOpc) {
160 case LoongArch::LDPTR_W:
161 case LoongArch::LDPTR_D:
162 case LoongArch::STPTR_W:
163 case LoongArch::STPTR_D:
164 PtrOpc = MIOpc;
165 break;
166 case LoongArch::LD_W:
167 HasSimm12Field = true;
168 PtrOpc = LoongArch::LDPTR_W;
169 break;
170 case LoongArch::LD_D:
171 HasSimm12Field = true;
172 PtrOpc = LoongArch::LDPTR_D;
173 break;
174 case LoongArch::ST_W:
175 HasSimm12Field = true;
176 PtrOpc = LoongArch::STPTR_W;
177 break;
178 case LoongArch::ST_D:
179 HasSimm12Field = true;
180 PtrOpc = LoongArch::STPTR_D;
181 break;
182 case LoongArch::LD_B:
183 case LoongArch::LD_H:
184 case LoongArch::LD_BU:
185 case LoongArch::LD_HU:
186 case LoongArch::LD_WU:
187 case LoongArch::ST_B:
188 case LoongArch::ST_H:
189 case LoongArch::FLD_S:
190 case LoongArch::FLD_D:
191 case LoongArch::FST_S:
192 case LoongArch::FST_D:
193 case LoongArch::VLD:
194 case LoongArch::VST:
195 case LoongArch::XVLD:
196 case LoongArch::XVST:
197 case LoongArch::VLDREPL_B:
198 case LoongArch::XVLDREPL_B:
199 HasSimm12Field = true;
200 break;
201 }
202
203 // Handle offsets that exceed the immediate range of the instruction.
204 switch (MIOpc) {
205 case LoongArch::VSTELM_B:
206 case LoongArch::XVSTELM_B:
207 OffsetLegal = isInt<8>(x: FixedOffset);
208 break;
209 case LoongArch::VSTELM_H:
210 case LoongArch::XVSTELM_H:
211 OffsetLegal = isShiftedInt<8, 1>(x: FixedOffset);
212 break;
213 case LoongArch::VSTELM_W:
214 case LoongArch::XVSTELM_W:
215 OffsetLegal = isShiftedInt<8, 2>(x: FixedOffset);
216 break;
217 case LoongArch::VSTELM_D:
218 case LoongArch::XVSTELM_D:
219 OffsetLegal = isShiftedInt<8, 3>(x: FixedOffset);
220 break;
221 }
222
223 if (!OffsetLegal && isInt<12>(x: FixedOffset)) {
224 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
225
226 // The offset fits in si12 but is not legal for the instruction,
227 // so use only one scratch register instead.
228 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
229 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Addi), DestReg: ScratchReg)
230 .addReg(RegNo: FrameReg)
231 .addImm(Val: FixedOffset);
232 Offset = StackOffset::getFixed(Fixed: 0);
233 FrameReg = ScratchReg;
234 FrameRegIsKill = true;
235 }
236
237 // If the offset doesn't fit the si12 field of ld/st but does fit
238 // the si14 << 2 field of ldptr/stptr, replace with the latter one.
239 if (IsLA64 && !isInt<12>(x: FixedOffset) && isShiftedInt<14, 2>(x: FixedOffset)) {
240 if (PtrOpc) {
241 MI.setDesc(TII->get(Opcode: PtrOpc));
242 MI.getOperand(i: FIOperandNum)
243 .ChangeToRegister(Reg: FrameReg, isDef: false, isImp: false, isKill: FrameRegIsKill);
244 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: FixedOffset);
245 return false;
246 }
247 }
248
249 if (!isInt<12>(x: FixedOffset)) {
250 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
251 unsigned Add = IsLA64 ? LoongArch::ADD_D : LoongArch::ADD_W;
252 int64_t Val = FixedOffset;
253 // Keep the old behaviour of materializing the whole offset for instructions
254 // do not have simm12 field or ADDI due to it will be replaced.
255 int64_t Lo12 = !HasSimm12Field ? 0 : SignExtend64<12>(x: Val);
256 uint64_t HiVal = (uint64_t)Val - (uint64_t)Lo12;
257
258 // The offset won't fit in an immediate, so use a scratch register instead.
259 // Modify Offset and FrameReg appropriately.
260 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
261 // Move lower 12-bit of offset into original instruction.
262 Offset = StackOffset::getFixed(Fixed: Lo12);
263
264 if (HasSimm12Field && isShiftedInt<20, 12>(x: HiVal)) {
265 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: LoongArch::PseudoAddUpperImm), DestReg: ScratchReg)
266 .addReg(RegNo: FrameReg)
267 .addImm(Val: static_cast<int64_t>(HiVal) >> 12);
268 } else {
269 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val: HiVal);
270 if (MIOpc == Addi) {
271 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Add), DestReg: MI.getOperand(i: 0).getReg())
272 .addReg(RegNo: FrameReg)
273 .addReg(RegNo: ScratchReg, Flags: RegState::Kill);
274 MI.eraseFromParent();
275 return true;
276 }
277 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Add), DestReg: ScratchReg)
278 .addReg(RegNo: FrameReg)
279 .addReg(RegNo: ScratchReg, Flags: RegState::Kill);
280 }
281 FrameReg = ScratchReg;
282 FrameRegIsKill = true;
283 }
284
285 // Spill CFRs.
286 if (MIOpc == LoongArch::PseudoST_CFR) {
287 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
288 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: LoongArch::MOVCF2GR), DestReg: ScratchReg)
289 .add(MO: MI.getOperand(i: 0));
290 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: IsLA64 ? LoongArch::ST_D : LoongArch::ST_W))
291 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
292 .addReg(RegNo: FrameReg)
293 .addImm(Val: Offset.getFixed());
294 MI.eraseFromParent();
295 return true;
296 }
297
298 // Reload CFRs.
299 if (MIOpc == LoongArch::PseudoLD_CFR) {
300 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
301 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: IsLA64 ? LoongArch::LD_D : LoongArch::LD_W),
302 DestReg: ScratchReg)
303 .addReg(RegNo: FrameReg)
304 .addImm(Val: Offset.getFixed());
305 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: LoongArch::MOVGR2CF))
306 .add(MO: MI.getOperand(i: 0))
307 .addReg(RegNo: ScratchReg, Flags: RegState::Kill);
308 MI.eraseFromParent();
309 return true;
310 }
311
312 MI.getOperand(i: FIOperandNum)
313 .ChangeToRegister(Reg: FrameReg, isDef: false, isImp: false, isKill: FrameRegIsKill);
314 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset.getFixed());
315 return false;
316}
317
318bool LoongArchRegisterInfo::canRealignStack(const MachineFunction &MF) const {
319 if (!TargetRegisterInfo::canRealignStack(MF))
320 return false;
321
322 const MachineRegisterInfo *MRI = &MF.getRegInfo();
323 const LoongArchFrameLowering *TFI = getFrameLowering(MF);
324
325 // Stack realignment requires a frame pointer. If we already started
326 // register allocation with frame pointer elimination, it is too late now.
327 if (!MRI->canReserveReg(PhysReg: LoongArch::R22))
328 return false;
329
330 // We may also need a base pointer if there are dynamic allocas or stack
331 // pointer adjustments around calls.
332 if (TFI->hasReservedCallFrame(MF))
333 return true;
334
335 // A base pointer is required and allowed. Check that it isn't too late to
336 // reserve it.
337 return MRI->canReserveReg(PhysReg: LoongArchABI::getBPReg());
338}
339