1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SparcMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i32, MVT::i64, MVT::Other,
17 /* 7 */ MVT::f32, MVT::Other,
18 /* 9 */ MVT::f64, MVT::Other,
19 /* 11 */ MVT::f128, MVT::Other,
20 /* 13 */ MVT::v2i32, MVT::Other,
21};
22
23static const char *SubRegIndexNameTable[] = { "sub_even", "sub_even64", "sub_odd", "sub_odd64", "sub_odd64_then_sub_even", "sub_odd64_then_sub_odd", "" };
24
25static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
26 { .Offset: 65535, .Size: 65535 },
27 { .Offset: 0, .Size: 32 }, // sub_even
28 { .Offset: 0, .Size: 64 }, // sub_even64
29 { .Offset: 32, .Size: 32 }, // sub_odd
30 { .Offset: 64, .Size: 64 }, // sub_odd64
31 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
32 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
33 { .Offset: 65535, .Size: 65535 },
34 { .Offset: 0, .Size: 32 }, // sub_even
35 { .Offset: 0, .Size: 64 }, // sub_even64
36 { .Offset: 32, .Size: 32 }, // sub_odd
37 { .Offset: 64, .Size: 64 }, // sub_odd64
38 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
39 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
40};
41
42
43static const LaneBitmask SubRegIndexLaneMaskTable[] = {
44 LaneBitmask::getAll(),
45 LaneBitmask(0x0000000000000001), // sub_even
46 LaneBitmask(0x0000000000000003), // sub_even64
47 LaneBitmask(0x0000000000000002), // sub_odd
48 LaneBitmask(0x000000000000000C), // sub_odd64
49 LaneBitmask(0x0000000000000004), // sub_odd64_then_sub_even
50 LaneBitmask(0x0000000000000008), // sub_odd64_then_sub_odd
51 };
52
53
54
55static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
56 // Mode = 0 (Default)
57 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*VTLists+*/.VTListOffset: 0 }, // FCCRegs
58 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // ASRRegs
59 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CoprocRegs
60 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 7 }, // FPRegs
61 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // IntRegs
62 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
63 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
64 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 9 }, // DFPRegs
65 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs
66 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // PRRegs
67 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // CoprocPair
68 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair
69 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 9 }, // LowDFPRegs
70 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
71 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
72 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
73 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
74 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
75 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // QFPRegs
76 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // LowQFPRegs
77 // Mode = 1 (SPARC64)
78 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*VTLists+*/.VTListOffset: 0 }, // FCCRegs
79 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // ASRRegs
80 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CoprocRegs
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 7 }, // FPRegs
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // IntRegs
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
84 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
85 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 9 }, // DFPRegs
86 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs
87 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // PRRegs
88 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // CoprocPair
89 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair
90 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 9 }, // LowDFPRegs
91 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
92 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
93 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
94 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
95 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
96 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // QFPRegs
97 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // LowQFPRegs
98};
99static const uint32_t FCCRegsSubClassMask[] = {
100 0x00000001,
101};
102
103static const uint32_t ASRRegsSubClassMask[] = {
104 0x00020002,
105};
106
107static const uint32_t CoprocRegsSubClassMask[] = {
108 0x00000004,
109 0x00000400, // sub_even
110 0x00000400, // sub_odd
111};
112
113static const uint32_t FPRegsSubClassMask[] = {
114 0x00000008,
115 0x00081000, // sub_even
116 0x00081000, // sub_odd
117 0x00080000, // sub_odd64_then_sub_even
118 0x00080000, // sub_odd64_then_sub_odd
119};
120
121static const uint32_t IntRegsSubClassMask[] = {
122 0x00006170,
123 0x00018800, // sub_even
124 0x00018800, // sub_odd
125};
126
127static const uint32_t GPRIncomingArgSubClassMask[] = {
128 0x00002020,
129 0x00008000, // sub_even
130 0x00008000, // sub_odd
131};
132
133static const uint32_t GPROutgoingArgSubClassMask[] = {
134 0x00004040,
135 0x00010000, // sub_even
136 0x00010000, // sub_odd
137};
138
139static const uint32_t DFPRegsSubClassMask[] = {
140 0x00001080,
141 0x000c0000, // sub_even64
142 0x000c0000, // sub_odd64
143};
144
145static const uint32_t I64RegsSubClassMask[] = {
146 0x00006100,
147 0x00018800, // sub_even
148 0x00018800, // sub_odd
149};
150
151static const uint32_t PRRegsSubClassMask[] = {
152 0x00020200,
153};
154
155static const uint32_t CoprocPairSubClassMask[] = {
156 0x00000400,
157};
158
159static const uint32_t IntPairSubClassMask[] = {
160 0x00018800,
161};
162
163static const uint32_t LowDFPRegsSubClassMask[] = {
164 0x00001000,
165 0x00080000, // sub_even64
166 0x00080000, // sub_odd64
167};
168
169static const uint32_t I64Regs_and_GPRIncomingArgSubClassMask[] = {
170 0x00002000,
171 0x00008000, // sub_even
172 0x00008000, // sub_odd
173};
174
175static const uint32_t I64Regs_and_GPROutgoingArgSubClassMask[] = {
176 0x00004000,
177 0x00010000, // sub_even
178 0x00010000, // sub_odd
179};
180
181static const uint32_t IntPair_with_sub_even_in_GPRIncomingArgSubClassMask[] = {
182 0x00008000,
183};
184
185static const uint32_t IntPair_with_sub_even_in_GPROutgoingArgSubClassMask[] = {
186 0x00010000,
187};
188
189static const uint32_t PRRegs_and_ASRRegsSubClassMask[] = {
190 0x00020000,
191};
192
193static const uint32_t QFPRegsSubClassMask[] = {
194 0x000c0000,
195};
196
197static const uint32_t LowQFPRegsSubClassMask[] = {
198 0x00080000,
199};
200
201static const uint16_t SuperRegIdxSeqs[] = {
202 /* 0 */ 1, 3, 0,
203 /* 3 */ 2, 4, 0,
204 /* 6 */ 1, 3, 5, 6, 0,
205};
206
207static unsigned const GPRIncomingArgSuperclasses[] = {
208 SP::IntRegsRegClassID,
209};
210
211static unsigned const GPROutgoingArgSuperclasses[] = {
212 SP::IntRegsRegClassID,
213};
214
215static unsigned const I64RegsSuperclasses[] = {
216 SP::IntRegsRegClassID,
217};
218
219static unsigned const LowDFPRegsSuperclasses[] = {
220 SP::DFPRegsRegClassID,
221};
222
223static unsigned const I64Regs_and_GPRIncomingArgSuperclasses[] = {
224 SP::IntRegsRegClassID,
225 SP::GPRIncomingArgRegClassID,
226 SP::I64RegsRegClassID,
227};
228
229static unsigned const I64Regs_and_GPROutgoingArgSuperclasses[] = {
230 SP::IntRegsRegClassID,
231 SP::GPROutgoingArgRegClassID,
232 SP::I64RegsRegClassID,
233};
234
235static unsigned const IntPair_with_sub_even_in_GPRIncomingArgSuperclasses[] = {
236 SP::IntPairRegClassID,
237};
238
239static unsigned const IntPair_with_sub_even_in_GPROutgoingArgSuperclasses[] = {
240 SP::IntPairRegClassID,
241};
242
243static unsigned const PRRegs_and_ASRRegsSuperclasses[] = {
244 SP::ASRRegsRegClassID,
245 SP::PRRegsRegClassID,
246};
247
248static unsigned const LowQFPRegsSuperclasses[] = {
249 SP::QFPRegsRegClassID,
250};
251
252
253namespace SP { // Register class instances
254 extern const TargetRegisterClass FCCRegsRegClass = {
255 .MC: &SparcMCRegisterClasses[FCCRegsRegClassID],
256 .SubClassMask: FCCRegsSubClassMask,
257 .SuperRegIndices: SuperRegIdxSeqs + 2,
258 .LaneMask: LaneBitmask(0x0000000000000001),
259 .AllocationPriority: 0,
260 .GlobalPriority: false,
261 .TSFlags: 0x00, /* TSFlags */
262 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
263 .CoveredBySubRegs: false, /* CoveredBySubRegs */
264 .SuperClasses: nullptr, .SuperClassesSize: 0,
265 .OrderFunc: nullptr
266 };
267
268 extern const TargetRegisterClass ASRRegsRegClass = {
269 .MC: &SparcMCRegisterClasses[ASRRegsRegClassID],
270 .SubClassMask: ASRRegsSubClassMask,
271 .SuperRegIndices: SuperRegIdxSeqs + 2,
272 .LaneMask: LaneBitmask(0x0000000000000001),
273 .AllocationPriority: 0,
274 .GlobalPriority: false,
275 .TSFlags: 0x00, /* TSFlags */
276 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
277 .CoveredBySubRegs: false, /* CoveredBySubRegs */
278 .SuperClasses: nullptr, .SuperClassesSize: 0,
279 .OrderFunc: nullptr
280 };
281
282 extern const TargetRegisterClass CoprocRegsRegClass = {
283 .MC: &SparcMCRegisterClasses[CoprocRegsRegClassID],
284 .SubClassMask: CoprocRegsSubClassMask,
285 .SuperRegIndices: SuperRegIdxSeqs + 0,
286 .LaneMask: LaneBitmask(0x0000000000000001),
287 .AllocationPriority: 0,
288 .GlobalPriority: false,
289 .TSFlags: 0x00, /* TSFlags */
290 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
291 .CoveredBySubRegs: false, /* CoveredBySubRegs */
292 .SuperClasses: nullptr, .SuperClassesSize: 0,
293 .OrderFunc: nullptr
294 };
295
296 extern const TargetRegisterClass FPRegsRegClass = {
297 .MC: &SparcMCRegisterClasses[FPRegsRegClassID],
298 .SubClassMask: FPRegsSubClassMask,
299 .SuperRegIndices: SuperRegIdxSeqs + 6,
300 .LaneMask: LaneBitmask(0x0000000000000001),
301 .AllocationPriority: 0,
302 .GlobalPriority: false,
303 .TSFlags: 0x00, /* TSFlags */
304 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
305 .CoveredBySubRegs: false, /* CoveredBySubRegs */
306 .SuperClasses: nullptr, .SuperClassesSize: 0,
307 .OrderFunc: nullptr
308 };
309
310 extern const TargetRegisterClass IntRegsRegClass = {
311 .MC: &SparcMCRegisterClasses[IntRegsRegClassID],
312 .SubClassMask: IntRegsSubClassMask,
313 .SuperRegIndices: SuperRegIdxSeqs + 0,
314 .LaneMask: LaneBitmask(0x0000000000000001),
315 .AllocationPriority: 0,
316 .GlobalPriority: false,
317 .TSFlags: 0x00, /* TSFlags */
318 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
319 .CoveredBySubRegs: false, /* CoveredBySubRegs */
320 .SuperClasses: nullptr, .SuperClassesSize: 0,
321 .OrderFunc: nullptr
322 };
323
324 extern const TargetRegisterClass GPRIncomingArgRegClass = {
325 .MC: &SparcMCRegisterClasses[GPRIncomingArgRegClassID],
326 .SubClassMask: GPRIncomingArgSubClassMask,
327 .SuperRegIndices: SuperRegIdxSeqs + 0,
328 .LaneMask: LaneBitmask(0x0000000000000001),
329 .AllocationPriority: 0,
330 .GlobalPriority: false,
331 .TSFlags: 0x00, /* TSFlags */
332 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
333 .CoveredBySubRegs: false, /* CoveredBySubRegs */
334 .SuperClasses: GPRIncomingArgSuperclasses, .SuperClassesSize: 1,
335 .OrderFunc: nullptr
336 };
337
338 extern const TargetRegisterClass GPROutgoingArgRegClass = {
339 .MC: &SparcMCRegisterClasses[GPROutgoingArgRegClassID],
340 .SubClassMask: GPROutgoingArgSubClassMask,
341 .SuperRegIndices: SuperRegIdxSeqs + 0,
342 .LaneMask: LaneBitmask(0x0000000000000001),
343 .AllocationPriority: 0,
344 .GlobalPriority: false,
345 .TSFlags: 0x00, /* TSFlags */
346 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
347 .CoveredBySubRegs: false, /* CoveredBySubRegs */
348 .SuperClasses: GPROutgoingArgSuperclasses, .SuperClassesSize: 1,
349 .OrderFunc: nullptr
350 };
351
352 extern const TargetRegisterClass DFPRegsRegClass = {
353 .MC: &SparcMCRegisterClasses[DFPRegsRegClassID],
354 .SubClassMask: DFPRegsSubClassMask,
355 .SuperRegIndices: SuperRegIdxSeqs + 3,
356 .LaneMask: LaneBitmask(0x0000000000000003),
357 .AllocationPriority: 0,
358 .GlobalPriority: false,
359 .TSFlags: 0x00, /* TSFlags */
360 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
361 .CoveredBySubRegs: false, /* CoveredBySubRegs */
362 .SuperClasses: nullptr, .SuperClassesSize: 0,
363 .OrderFunc: nullptr
364 };
365
366 extern const TargetRegisterClass I64RegsRegClass = {
367 .MC: &SparcMCRegisterClasses[I64RegsRegClassID],
368 .SubClassMask: I64RegsSubClassMask,
369 .SuperRegIndices: SuperRegIdxSeqs + 0,
370 .LaneMask: LaneBitmask(0x0000000000000001),
371 .AllocationPriority: 0,
372 .GlobalPriority: false,
373 .TSFlags: 0x00, /* TSFlags */
374 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
375 .CoveredBySubRegs: false, /* CoveredBySubRegs */
376 .SuperClasses: I64RegsSuperclasses, .SuperClassesSize: 1,
377 .OrderFunc: nullptr
378 };
379
380 extern const TargetRegisterClass PRRegsRegClass = {
381 .MC: &SparcMCRegisterClasses[PRRegsRegClassID],
382 .SubClassMask: PRRegsSubClassMask,
383 .SuperRegIndices: SuperRegIdxSeqs + 2,
384 .LaneMask: LaneBitmask(0x0000000000000001),
385 .AllocationPriority: 0,
386 .GlobalPriority: false,
387 .TSFlags: 0x00, /* TSFlags */
388 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
389 .CoveredBySubRegs: false, /* CoveredBySubRegs */
390 .SuperClasses: nullptr, .SuperClassesSize: 0,
391 .OrderFunc: nullptr
392 };
393
394 extern const TargetRegisterClass CoprocPairRegClass = {
395 .MC: &SparcMCRegisterClasses[CoprocPairRegClassID],
396 .SubClassMask: CoprocPairSubClassMask,
397 .SuperRegIndices: SuperRegIdxSeqs + 2,
398 .LaneMask: LaneBitmask(0x0000000000000003),
399 .AllocationPriority: 0,
400 .GlobalPriority: false,
401 .TSFlags: 0x00, /* TSFlags */
402 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
403 .CoveredBySubRegs: true, /* CoveredBySubRegs */
404 .SuperClasses: nullptr, .SuperClassesSize: 0,
405 .OrderFunc: nullptr
406 };
407
408 extern const TargetRegisterClass IntPairRegClass = {
409 .MC: &SparcMCRegisterClasses[IntPairRegClassID],
410 .SubClassMask: IntPairSubClassMask,
411 .SuperRegIndices: SuperRegIdxSeqs + 2,
412 .LaneMask: LaneBitmask(0x0000000000000003),
413 .AllocationPriority: 0,
414 .GlobalPriority: false,
415 .TSFlags: 0x00, /* TSFlags */
416 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
417 .CoveredBySubRegs: true, /* CoveredBySubRegs */
418 .SuperClasses: nullptr, .SuperClassesSize: 0,
419 .OrderFunc: nullptr
420 };
421
422 extern const TargetRegisterClass LowDFPRegsRegClass = {
423 .MC: &SparcMCRegisterClasses[LowDFPRegsRegClassID],
424 .SubClassMask: LowDFPRegsSubClassMask,
425 .SuperRegIndices: SuperRegIdxSeqs + 3,
426 .LaneMask: LaneBitmask(0x0000000000000003),
427 .AllocationPriority: 0,
428 .GlobalPriority: false,
429 .TSFlags: 0x00, /* TSFlags */
430 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
431 .CoveredBySubRegs: true, /* CoveredBySubRegs */
432 .SuperClasses: LowDFPRegsSuperclasses, .SuperClassesSize: 1,
433 .OrderFunc: nullptr
434 };
435
436 extern const TargetRegisterClass I64Regs_and_GPRIncomingArgRegClass = {
437 .MC: &SparcMCRegisterClasses[I64Regs_and_GPRIncomingArgRegClassID],
438 .SubClassMask: I64Regs_and_GPRIncomingArgSubClassMask,
439 .SuperRegIndices: SuperRegIdxSeqs + 0,
440 .LaneMask: LaneBitmask(0x0000000000000001),
441 .AllocationPriority: 0,
442 .GlobalPriority: false,
443 .TSFlags: 0x00, /* TSFlags */
444 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
445 .CoveredBySubRegs: false, /* CoveredBySubRegs */
446 .SuperClasses: I64Regs_and_GPRIncomingArgSuperclasses, .SuperClassesSize: 3,
447 .OrderFunc: nullptr
448 };
449
450 extern const TargetRegisterClass I64Regs_and_GPROutgoingArgRegClass = {
451 .MC: &SparcMCRegisterClasses[I64Regs_and_GPROutgoingArgRegClassID],
452 .SubClassMask: I64Regs_and_GPROutgoingArgSubClassMask,
453 .SuperRegIndices: SuperRegIdxSeqs + 0,
454 .LaneMask: LaneBitmask(0x0000000000000001),
455 .AllocationPriority: 0,
456 .GlobalPriority: false,
457 .TSFlags: 0x00, /* TSFlags */
458 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
459 .CoveredBySubRegs: false, /* CoveredBySubRegs */
460 .SuperClasses: I64Regs_and_GPROutgoingArgSuperclasses, .SuperClassesSize: 3,
461 .OrderFunc: nullptr
462 };
463
464 extern const TargetRegisterClass IntPair_with_sub_even_in_GPRIncomingArgRegClass = {
465 .MC: &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPRIncomingArgRegClassID],
466 .SubClassMask: IntPair_with_sub_even_in_GPRIncomingArgSubClassMask,
467 .SuperRegIndices: SuperRegIdxSeqs + 2,
468 .LaneMask: LaneBitmask(0x0000000000000003),
469 .AllocationPriority: 0,
470 .GlobalPriority: false,
471 .TSFlags: 0x00, /* TSFlags */
472 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
473 .CoveredBySubRegs: true, /* CoveredBySubRegs */
474 .SuperClasses: IntPair_with_sub_even_in_GPRIncomingArgSuperclasses, .SuperClassesSize: 1,
475 .OrderFunc: nullptr
476 };
477
478 extern const TargetRegisterClass IntPair_with_sub_even_in_GPROutgoingArgRegClass = {
479 .MC: &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPROutgoingArgRegClassID],
480 .SubClassMask: IntPair_with_sub_even_in_GPROutgoingArgSubClassMask,
481 .SuperRegIndices: SuperRegIdxSeqs + 2,
482 .LaneMask: LaneBitmask(0x0000000000000003),
483 .AllocationPriority: 0,
484 .GlobalPriority: false,
485 .TSFlags: 0x00, /* TSFlags */
486 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
487 .CoveredBySubRegs: true, /* CoveredBySubRegs */
488 .SuperClasses: IntPair_with_sub_even_in_GPROutgoingArgSuperclasses, .SuperClassesSize: 1,
489 .OrderFunc: nullptr
490 };
491
492 extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass = {
493 .MC: &SparcMCRegisterClasses[PRRegs_and_ASRRegsRegClassID],
494 .SubClassMask: PRRegs_and_ASRRegsSubClassMask,
495 .SuperRegIndices: SuperRegIdxSeqs + 2,
496 .LaneMask: LaneBitmask(0x0000000000000001),
497 .AllocationPriority: 0,
498 .GlobalPriority: false,
499 .TSFlags: 0x00, /* TSFlags */
500 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
501 .CoveredBySubRegs: false, /* CoveredBySubRegs */
502 .SuperClasses: PRRegs_and_ASRRegsSuperclasses, .SuperClassesSize: 2,
503 .OrderFunc: nullptr
504 };
505
506 extern const TargetRegisterClass QFPRegsRegClass = {
507 .MC: &SparcMCRegisterClasses[QFPRegsRegClassID],
508 .SubClassMask: QFPRegsSubClassMask,
509 .SuperRegIndices: SuperRegIdxSeqs + 2,
510 .LaneMask: LaneBitmask(0x000000000000000F),
511 .AllocationPriority: 0,
512 .GlobalPriority: false,
513 .TSFlags: 0x00, /* TSFlags */
514 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
515 .CoveredBySubRegs: true, /* CoveredBySubRegs */
516 .SuperClasses: nullptr, .SuperClassesSize: 0,
517 .OrderFunc: nullptr
518 };
519
520 extern const TargetRegisterClass LowQFPRegsRegClass = {
521 .MC: &SparcMCRegisterClasses[LowQFPRegsRegClassID],
522 .SubClassMask: LowQFPRegsSubClassMask,
523 .SuperRegIndices: SuperRegIdxSeqs + 2,
524 .LaneMask: LaneBitmask(0x000000000000000F),
525 .AllocationPriority: 0,
526 .GlobalPriority: false,
527 .TSFlags: 0x00, /* TSFlags */
528 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
529 .CoveredBySubRegs: true, /* CoveredBySubRegs */
530 .SuperClasses: LowQFPRegsSuperclasses, .SuperClassesSize: 1,
531 .OrderFunc: nullptr
532 };
533
534} // end namespace SP
535
536namespace {
537 const TargetRegisterClass *const RegisterClasses[] = {
538 &SP::FCCRegsRegClass,
539 &SP::ASRRegsRegClass,
540 &SP::CoprocRegsRegClass,
541 &SP::FPRegsRegClass,
542 &SP::IntRegsRegClass,
543 &SP::GPRIncomingArgRegClass,
544 &SP::GPROutgoingArgRegClass,
545 &SP::DFPRegsRegClass,
546 &SP::I64RegsRegClass,
547 &SP::PRRegsRegClass,
548 &SP::CoprocPairRegClass,
549 &SP::IntPairRegClass,
550 &SP::LowDFPRegsRegClass,
551 &SP::I64Regs_and_GPRIncomingArgRegClass,
552 &SP::I64Regs_and_GPROutgoingArgRegClass,
553 &SP::IntPair_with_sub_even_in_GPRIncomingArgRegClass,
554 &SP::IntPair_with_sub_even_in_GPROutgoingArgRegClass,
555 &SP::PRRegs_and_ASRRegsRegClass,
556 &SP::QFPRegsRegClass,
557 &SP::LowQFPRegsRegClass,
558 };
559} // end anonymous namespace
560
561static const uint8_t CostPerUseTable[] = {
5620, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
563
564
565static const bool InAllocatableClassTable[] = {
566false, true, true, true, false, false, true, false, false, true, false, true, true, false, true, true, false, true, true, true, true, true, true, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
567
568
569static const TargetRegisterInfoDesc SparcRegInfoDesc = { // Extra Descriptors
570.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
571
572unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
573 static const uint8_t RowMap[6] = {
574 0, 0, 0, 1, 0, 0,
575 };
576 static const uint8_t Rows[2][6] = {
577 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
578 { SP::sub_odd64_then_sub_even, 0, SP::sub_odd64_then_sub_odd, 0, 0, 0, },
579 };
580
581 --IdxA; assert(IdxA < 6); (void) IdxA;
582 --IdxB; assert(IdxB < 6);
583 return Rows[RowMap[IdxA]][IdxB];
584}
585
586unsigned SparcGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
587 static const uint8_t Table[6][6] = {
588 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
589 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
590 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
591 { 0, 0, 0, 0, SP::sub_even, SP::sub_odd, },
592 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
593 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
594 };
595
596 --IdxA; assert(IdxA < 6);
597 --IdxB; assert(IdxB < 6);
598 return Table[IdxA][IdxB];
599 }
600
601 struct MaskRolOp {
602 LaneBitmask Mask;
603 uint8_t RotateLeft;
604 };
605 static const MaskRolOp LaneMaskComposeSequences[] = {
606 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
607 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
608 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
609 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 6
610 };
611 static const uint8_t CompositeSequences[] = {
612 0, // to sub_even
613 0, // to sub_even64
614 2, // to sub_odd
615 4, // to sub_odd64
616 4, // to sub_odd64_then_sub_even
617 6 // to sub_odd64_then_sub_odd
618 };
619
620LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
621 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
622 LaneBitmask Result;
623 for (const MaskRolOp *Ops =
624 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
625 Ops->Mask.any(); ++Ops) {
626 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
627 if (unsigned S = Ops->RotateLeft)
628 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
629 else
630 Result |= LaneBitmask(M);
631 }
632 return Result;
633}
634
635LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
636 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
637 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
638 LaneBitmask Result;
639 for (const MaskRolOp *Ops =
640 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
641 Ops->Mask.any(); ++Ops) {
642 LaneBitmask::Type M = LaneMask.getAsInteger();
643 if (unsigned S = Ops->RotateLeft)
644 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
645 else
646 Result |= LaneBitmask(M);
647 }
648 return Result;
649}
650
651const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
652 static const uint8_t Table[20][6] = {
653 { // FCCRegs
654 0, // sub_even
655 0, // sub_even64
656 0, // sub_odd
657 0, // sub_odd64
658 0, // sub_odd64_then_sub_even
659 0, // sub_odd64_then_sub_odd
660 },
661 { // ASRRegs
662 0, // sub_even
663 0, // sub_even64
664 0, // sub_odd
665 0, // sub_odd64
666 0, // sub_odd64_then_sub_even
667 0, // sub_odd64_then_sub_odd
668 },
669 { // CoprocRegs
670 0, // sub_even
671 0, // sub_even64
672 0, // sub_odd
673 0, // sub_odd64
674 0, // sub_odd64_then_sub_even
675 0, // sub_odd64_then_sub_odd
676 },
677 { // FPRegs
678 0, // sub_even
679 0, // sub_even64
680 0, // sub_odd
681 0, // sub_odd64
682 0, // sub_odd64_then_sub_even
683 0, // sub_odd64_then_sub_odd
684 },
685 { // IntRegs
686 0, // sub_even
687 0, // sub_even64
688 0, // sub_odd
689 0, // sub_odd64
690 0, // sub_odd64_then_sub_even
691 0, // sub_odd64_then_sub_odd
692 },
693 { // GPRIncomingArg
694 0, // sub_even
695 0, // sub_even64
696 0, // sub_odd
697 0, // sub_odd64
698 0, // sub_odd64_then_sub_even
699 0, // sub_odd64_then_sub_odd
700 },
701 { // GPROutgoingArg
702 0, // sub_even
703 0, // sub_even64
704 0, // sub_odd
705 0, // sub_odd64
706 0, // sub_odd64_then_sub_even
707 0, // sub_odd64_then_sub_odd
708 },
709 { // DFPRegs
710 13, // sub_even -> LowDFPRegs
711 0, // sub_even64
712 13, // sub_odd -> LowDFPRegs
713 0, // sub_odd64
714 0, // sub_odd64_then_sub_even
715 0, // sub_odd64_then_sub_odd
716 },
717 { // I64Regs
718 0, // sub_even
719 0, // sub_even64
720 0, // sub_odd
721 0, // sub_odd64
722 0, // sub_odd64_then_sub_even
723 0, // sub_odd64_then_sub_odd
724 },
725 { // PRRegs
726 0, // sub_even
727 0, // sub_even64
728 0, // sub_odd
729 0, // sub_odd64
730 0, // sub_odd64_then_sub_even
731 0, // sub_odd64_then_sub_odd
732 },
733 { // CoprocPair
734 11, // sub_even -> CoprocPair
735 0, // sub_even64
736 11, // sub_odd -> CoprocPair
737 0, // sub_odd64
738 0, // sub_odd64_then_sub_even
739 0, // sub_odd64_then_sub_odd
740 },
741 { // IntPair
742 12, // sub_even -> IntPair
743 0, // sub_even64
744 12, // sub_odd -> IntPair
745 0, // sub_odd64
746 0, // sub_odd64_then_sub_even
747 0, // sub_odd64_then_sub_odd
748 },
749 { // LowDFPRegs
750 13, // sub_even -> LowDFPRegs
751 0, // sub_even64
752 13, // sub_odd -> LowDFPRegs
753 0, // sub_odd64
754 0, // sub_odd64_then_sub_even
755 0, // sub_odd64_then_sub_odd
756 },
757 { // I64Regs_and_GPRIncomingArg
758 0, // sub_even
759 0, // sub_even64
760 0, // sub_odd
761 0, // sub_odd64
762 0, // sub_odd64_then_sub_even
763 0, // sub_odd64_then_sub_odd
764 },
765 { // I64Regs_and_GPROutgoingArg
766 0, // sub_even
767 0, // sub_even64
768 0, // sub_odd
769 0, // sub_odd64
770 0, // sub_odd64_then_sub_even
771 0, // sub_odd64_then_sub_odd
772 },
773 { // IntPair_with_sub_even_in_GPRIncomingArg
774 16, // sub_even -> IntPair_with_sub_even_in_GPRIncomingArg
775 0, // sub_even64
776 16, // sub_odd -> IntPair_with_sub_even_in_GPRIncomingArg
777 0, // sub_odd64
778 0, // sub_odd64_then_sub_even
779 0, // sub_odd64_then_sub_odd
780 },
781 { // IntPair_with_sub_even_in_GPROutgoingArg
782 17, // sub_even -> IntPair_with_sub_even_in_GPROutgoingArg
783 0, // sub_even64
784 17, // sub_odd -> IntPair_with_sub_even_in_GPROutgoingArg
785 0, // sub_odd64
786 0, // sub_odd64_then_sub_even
787 0, // sub_odd64_then_sub_odd
788 },
789 { // PRRegs_and_ASRRegs
790 0, // sub_even
791 0, // sub_even64
792 0, // sub_odd
793 0, // sub_odd64
794 0, // sub_odd64_then_sub_even
795 0, // sub_odd64_then_sub_odd
796 },
797 { // QFPRegs
798 20, // sub_even -> LowQFPRegs
799 19, // sub_even64 -> QFPRegs
800 20, // sub_odd -> LowQFPRegs
801 19, // sub_odd64 -> QFPRegs
802 20, // sub_odd64_then_sub_even -> LowQFPRegs
803 20, // sub_odd64_then_sub_odd -> LowQFPRegs
804 },
805 { // LowQFPRegs
806 20, // sub_even -> LowQFPRegs
807 20, // sub_even64 -> LowQFPRegs
808 20, // sub_odd -> LowQFPRegs
809 20, // sub_odd64 -> LowQFPRegs
810 20, // sub_odd64_then_sub_even -> LowQFPRegs
811 20, // sub_odd64_then_sub_odd -> LowQFPRegs
812 },
813 };
814 assert(RC && "Missing regclass");
815 if (!Idx) return RC;
816 --Idx;
817 assert(Idx < 6 && "Bad subreg");
818 unsigned TV = Table[RC->getID()][Idx];
819 return TV ? getRegClass(i: TV - 1) : nullptr;
820}
821
822const TargetRegisterClass *SparcGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
823 static const uint8_t Table[20][6] = {
824 { // FCCRegs
825 0, // FCCRegs:sub_even
826 0, // FCCRegs:sub_even64
827 0, // FCCRegs:sub_odd
828 0, // FCCRegs:sub_odd64
829 0, // FCCRegs:sub_odd64_then_sub_even
830 0, // FCCRegs:sub_odd64_then_sub_odd
831 },
832 { // ASRRegs
833 0, // ASRRegs:sub_even
834 0, // ASRRegs:sub_even64
835 0, // ASRRegs:sub_odd
836 0, // ASRRegs:sub_odd64
837 0, // ASRRegs:sub_odd64_then_sub_even
838 0, // ASRRegs:sub_odd64_then_sub_odd
839 },
840 { // CoprocRegs
841 0, // CoprocRegs:sub_even
842 0, // CoprocRegs:sub_even64
843 0, // CoprocRegs:sub_odd
844 0, // CoprocRegs:sub_odd64
845 0, // CoprocRegs:sub_odd64_then_sub_even
846 0, // CoprocRegs:sub_odd64_then_sub_odd
847 },
848 { // FPRegs
849 0, // FPRegs:sub_even
850 0, // FPRegs:sub_even64
851 0, // FPRegs:sub_odd
852 0, // FPRegs:sub_odd64
853 0, // FPRegs:sub_odd64_then_sub_even
854 0, // FPRegs:sub_odd64_then_sub_odd
855 },
856 { // IntRegs
857 0, // IntRegs:sub_even
858 0, // IntRegs:sub_even64
859 0, // IntRegs:sub_odd
860 0, // IntRegs:sub_odd64
861 0, // IntRegs:sub_odd64_then_sub_even
862 0, // IntRegs:sub_odd64_then_sub_odd
863 },
864 { // GPRIncomingArg
865 0, // GPRIncomingArg:sub_even
866 0, // GPRIncomingArg:sub_even64
867 0, // GPRIncomingArg:sub_odd
868 0, // GPRIncomingArg:sub_odd64
869 0, // GPRIncomingArg:sub_odd64_then_sub_even
870 0, // GPRIncomingArg:sub_odd64_then_sub_odd
871 },
872 { // GPROutgoingArg
873 0, // GPROutgoingArg:sub_even
874 0, // GPROutgoingArg:sub_even64
875 0, // GPROutgoingArg:sub_odd
876 0, // GPROutgoingArg:sub_odd64
877 0, // GPROutgoingArg:sub_odd64_then_sub_even
878 0, // GPROutgoingArg:sub_odd64_then_sub_odd
879 },
880 { // DFPRegs
881 4, // DFPRegs:sub_even -> FPRegs
882 0, // DFPRegs:sub_even64
883 4, // DFPRegs:sub_odd -> FPRegs
884 0, // DFPRegs:sub_odd64
885 0, // DFPRegs:sub_odd64_then_sub_even
886 0, // DFPRegs:sub_odd64_then_sub_odd
887 },
888 { // I64Regs
889 0, // I64Regs:sub_even
890 0, // I64Regs:sub_even64
891 0, // I64Regs:sub_odd
892 0, // I64Regs:sub_odd64
893 0, // I64Regs:sub_odd64_then_sub_even
894 0, // I64Regs:sub_odd64_then_sub_odd
895 },
896 { // PRRegs
897 0, // PRRegs:sub_even
898 0, // PRRegs:sub_even64
899 0, // PRRegs:sub_odd
900 0, // PRRegs:sub_odd64
901 0, // PRRegs:sub_odd64_then_sub_even
902 0, // PRRegs:sub_odd64_then_sub_odd
903 },
904 { // CoprocPair
905 3, // CoprocPair:sub_even -> CoprocRegs
906 0, // CoprocPair:sub_even64
907 3, // CoprocPair:sub_odd -> CoprocRegs
908 0, // CoprocPair:sub_odd64
909 0, // CoprocPair:sub_odd64_then_sub_even
910 0, // CoprocPair:sub_odd64_then_sub_odd
911 },
912 { // IntPair
913 9, // IntPair:sub_even -> I64Regs
914 0, // IntPair:sub_even64
915 9, // IntPair:sub_odd -> I64Regs
916 0, // IntPair:sub_odd64
917 0, // IntPair:sub_odd64_then_sub_even
918 0, // IntPair:sub_odd64_then_sub_odd
919 },
920 { // LowDFPRegs
921 4, // LowDFPRegs:sub_even -> FPRegs
922 0, // LowDFPRegs:sub_even64
923 4, // LowDFPRegs:sub_odd -> FPRegs
924 0, // LowDFPRegs:sub_odd64
925 0, // LowDFPRegs:sub_odd64_then_sub_even
926 0, // LowDFPRegs:sub_odd64_then_sub_odd
927 },
928 { // I64Regs_and_GPRIncomingArg
929 0, // I64Regs_and_GPRIncomingArg:sub_even
930 0, // I64Regs_and_GPRIncomingArg:sub_even64
931 0, // I64Regs_and_GPRIncomingArg:sub_odd
932 0, // I64Regs_and_GPRIncomingArg:sub_odd64
933 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_even
934 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_odd
935 },
936 { // I64Regs_and_GPROutgoingArg
937 0, // I64Regs_and_GPROutgoingArg:sub_even
938 0, // I64Regs_and_GPROutgoingArg:sub_even64
939 0, // I64Regs_and_GPROutgoingArg:sub_odd
940 0, // I64Regs_and_GPROutgoingArg:sub_odd64
941 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_even
942 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_odd
943 },
944 { // IntPair_with_sub_even_in_GPRIncomingArg
945 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even -> I64Regs_and_GPRIncomingArg
946 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even64
947 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd -> I64Regs_and_GPRIncomingArg
948 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64
949 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_even
950 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_odd
951 },
952 { // IntPair_with_sub_even_in_GPROutgoingArg
953 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even -> I64Regs_and_GPROutgoingArg
954 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even64
955 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd -> I64Regs_and_GPROutgoingArg
956 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64
957 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_even
958 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_odd
959 },
960 { // PRRegs_and_ASRRegs
961 0, // PRRegs_and_ASRRegs:sub_even
962 0, // PRRegs_and_ASRRegs:sub_even64
963 0, // PRRegs_and_ASRRegs:sub_odd
964 0, // PRRegs_and_ASRRegs:sub_odd64
965 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_even
966 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_odd
967 },
968 { // QFPRegs
969 4, // QFPRegs:sub_even -> FPRegs
970 8, // QFPRegs:sub_even64 -> DFPRegs
971 4, // QFPRegs:sub_odd -> FPRegs
972 8, // QFPRegs:sub_odd64 -> DFPRegs
973 4, // QFPRegs:sub_odd64_then_sub_even -> FPRegs
974 4, // QFPRegs:sub_odd64_then_sub_odd -> FPRegs
975 },
976 { // LowQFPRegs
977 4, // LowQFPRegs:sub_even -> FPRegs
978 13, // LowQFPRegs:sub_even64 -> LowDFPRegs
979 4, // LowQFPRegs:sub_odd -> FPRegs
980 13, // LowQFPRegs:sub_odd64 -> LowDFPRegs
981 4, // LowQFPRegs:sub_odd64_then_sub_even -> FPRegs
982 4, // LowQFPRegs:sub_odd64_then_sub_odd -> FPRegs
983 },
984 };
985 assert(RC && "Missing regclass");
986 if (!Idx) return RC;
987 --Idx;
988 assert(Idx < 6 && "Bad subreg");
989 unsigned TV = Table[RC->getID()][Idx];
990 return TV ? getRegClass(i: TV - 1) : nullptr;
991}
992
993/// Get the weight in units of pressure for this register class.
994const RegClassWeight &SparcGenRegisterInfo::
995getRegClassWeight(const TargetRegisterClass *RC) const {
996 static const RegClassWeight RCWeightTable[] = {
997 {.RegWeight: 1, .WeightLimit: 4}, // FCCRegs
998 {.RegWeight: 1, .WeightLimit: 1}, // ASRRegs
999 {.RegWeight: 0, .WeightLimit: 0}, // CoprocRegs
1000 {.RegWeight: 1, .WeightLimit: 32}, // FPRegs
1001 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
1002 {.RegWeight: 1, .WeightLimit: 6}, // GPRIncomingArg
1003 {.RegWeight: 1, .WeightLimit: 6}, // GPROutgoingArg
1004 {.RegWeight: 2, .WeightLimit: 64}, // DFPRegs
1005 {.RegWeight: 1, .WeightLimit: 32}, // I64Regs
1006 {.RegWeight: 1, .WeightLimit: 17}, // PRRegs
1007 {.RegWeight: 0, .WeightLimit: 0}, // CoprocPair
1008 {.RegWeight: 2, .WeightLimit: 32}, // IntPair
1009 {.RegWeight: 2, .WeightLimit: 32}, // LowDFPRegs
1010 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPRIncomingArg
1011 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPROutgoingArg
1012 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPRIncomingArg
1013 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPROutgoingArg
1014 {.RegWeight: 1, .WeightLimit: 1}, // PRRegs_and_ASRRegs
1015 {.RegWeight: 4, .WeightLimit: 64}, // QFPRegs
1016 {.RegWeight: 4, .WeightLimit: 32}, // LowQFPRegs
1017 };
1018 return RCWeightTable[RC->getID()];
1019}
1020
1021/// Get the weight in units of pressure for this register unit.
1022unsigned SparcGenRegisterInfo::
1023getRegUnitWeight(MCRegUnit RegUnit) const {
1024 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
1025 static const uint8_t RUWeightTable[] = {
1026 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
1027 return RUWeightTable[static_cast<unsigned>(RegUnit)];
1028}
1029
1030
1031// Get the number of dimensions of register pressure.
1032unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
1033 return 8;
1034}
1035
1036// Get the name of this register unit pressure set.
1037const char *SparcGenRegisterInfo::
1038getRegPressureSetName(unsigned Idx) const {
1039 static const char *PressureNameTable[] = {
1040 "PRRegs_and_ASRRegs",
1041 "FCCRegs",
1042 "GPRIncomingArg",
1043 "GPROutgoingArg",
1044 "PRRegs",
1045 "FPRegs",
1046 "IntRegs",
1047 "DFPRegs",
1048 };
1049 return PressureNameTable[Idx];
1050}
1051
1052// Get the register unit pressure limit for this dimension.
1053// This limit must be adjusted dynamically for reserved registers.
1054unsigned SparcGenRegisterInfo::
1055getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1056 static const uint8_t PressureLimitTable[] = {
1057 1, // 0: PRRegs_and_ASRRegs
1058 4, // 1: FCCRegs
1059 6, // 2: GPRIncomingArg
1060 6, // 3: GPROutgoingArg
1061 17, // 4: PRRegs
1062 32, // 5: FPRegs
1063 32, // 6: IntRegs
1064 64, // 7: DFPRegs
1065 };
1066 return PressureLimitTable[Idx];
1067}
1068
1069/// Table of pressure sets per register class or unit.
1070static const int RCSetsTable[] = {
1071 /* 0 */ 1, -1,
1072 /* 2 */ 0, 4, -1,
1073 /* 5 */ 2, 6, -1,
1074 /* 8 */ 3, 6, -1,
1075 /* 11 */ 5, 7, -1,
1076};
1077
1078/// Get the dimensions of register pressure impacted by this register class.
1079/// Returns a -1 terminated array of pressure set IDs
1080const int *SparcGenRegisterInfo::
1081getRegClassPressureSets(const TargetRegisterClass *RC) const {
1082 static const uint8_t RCSetStartTable[] = {
1083 0,1,1,11,6,5,8,12,6,3,1,6,11,5,8,5,8,2,12,11,};
1084 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1085}
1086
1087/// Get the dimensions of register pressure impacted by this register unit.
1088/// Returns a -1 terminated array of pressure set IDs
1089const int *SparcGenRegisterInfo::
1090getRegUnitPressureSets(MCRegUnit RegUnit) const {
1091 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
1092 static const uint8_t RUSetStartTable[] = {
1093 3,3,3,1,1,3,1,1,3,1,3,3,1,3,3,1,2,3,3,3,3,3,3,1,3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,0,0,0,0,6,6,6,6,6,6,6,6,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,8,8,8,8,8,8,6,6,};
1094 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1095}
1096
1097extern const MCRegisterDesc SparcRegDesc[];
1098extern const int16_t SparcRegDiffLists[];
1099extern const LaneBitmask SparcLaneMaskLists[];
1100extern const char SparcRegStrings[];
1101extern const char SparcRegClassStrings[];
1102extern const MCPhysReg SparcRegUnitRoots[][2];
1103extern const uint16_t SparcSubRegIdxLists[];
1104extern const uint16_t SparcRegEncodingTable[];
1105// SP Dwarf<->LLVM register mappings.
1106extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
1107extern const unsigned SPDwarfFlavour0Dwarf2LSize;
1108
1109extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
1110extern const unsigned SPEHFlavour0Dwarf2LSize;
1111
1112extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
1113extern const unsigned SPDwarfFlavour0L2DwarfSize;
1114
1115extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
1116extern const unsigned SPEHFlavour0L2DwarfSize;
1117
1118SparcGenRegisterInfo::
1119SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1120 unsigned PC, unsigned HwMode)
1121 : TargetRegisterInfo(&SparcRegInfoDesc, RegisterClasses, RegisterClasses+20,
1122 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
1123 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
1124 InitMCRegisterInfo(D: SparcRegDesc, NR: 238, RA, PC,
1125 C: SparcMCRegisterClasses, NC: 20,
1126 RURoots: SparcRegUnitRoots,
1127 NRU: 173,
1128 DL: SparcRegDiffLists,
1129 RUMS: SparcLaneMaskLists,
1130 Strings: SparcRegStrings,
1131 ClassStrings: SparcRegClassStrings,
1132 SubIndices: SparcSubRegIdxLists,
1133 NumIndices: 7,
1134 RET: SparcRegEncodingTable);
1135
1136 switch (DwarfFlavour) {
1137 default:
1138 llvm_unreachable("Unknown DWARF flavour");
1139 case 0:
1140 mapDwarfRegsToLLVMRegs(Map: SPDwarfFlavour0Dwarf2L, Size: SPDwarfFlavour0Dwarf2LSize, isEH: false);
1141 break;
1142 }
1143 switch (EHFlavour) {
1144 default:
1145 llvm_unreachable("Unknown DWARF flavour");
1146 case 0:
1147 mapDwarfRegsToLLVMRegs(Map: SPEHFlavour0Dwarf2L, Size: SPEHFlavour0Dwarf2LSize, isEH: true);
1148 break;
1149 }
1150 switch (DwarfFlavour) {
1151 default:
1152 llvm_unreachable("Unknown DWARF flavour");
1153 case 0:
1154 mapLLVMRegsToDwarfRegs(Map: SPDwarfFlavour0L2Dwarf, Size: SPDwarfFlavour0L2DwarfSize, isEH: false);
1155 break;
1156 }
1157 switch (EHFlavour) {
1158 default:
1159 llvm_unreachable("Unknown DWARF flavour");
1160 case 0:
1161 mapLLVMRegsToDwarfRegs(Map: SPEHFlavour0L2Dwarf, Size: SPEHFlavour0L2DwarfSize, isEH: true);
1162 break;
1163 }
1164}
1165
1166static const MCPhysReg CSR_SaveList[] = { 0 };
1167static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x103fffc0, 0x00000000, 0x000003fc, };
1168static const MCPhysReg RTCSR_SaveList[] = { 0 };
1169static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00003000, 0x00000000, 0x00000020, };
1170
1171
1172ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
1173 static const uint32_t *const Masks[] = {
1174 CSR_RegMask,
1175 RTCSR_RegMask,
1176 };
1177 return ArrayRef(Masks);
1178}
1179
1180bool SparcGenRegisterInfo::
1181isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1182 return
1183 false;
1184}
1185
1186bool SparcGenRegisterInfo::
1187isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1188 return
1189 false;
1190}
1191
1192bool SparcGenRegisterInfo::
1193isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1194 return
1195 false;
1196}
1197
1198bool SparcGenRegisterInfo::
1199isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1200 return
1201 false;
1202}
1203
1204bool SparcGenRegisterInfo::
1205isConstantPhysReg(MCRegister PhysReg) const {
1206 return
1207 PhysReg == SP::G0 ||
1208 false;
1209}
1210
1211ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
1212 static const char *Names[] = {
1213 "CSR",
1214 "RTCSR",
1215 };
1216 return ArrayRef(Names);
1217}
1218
1219const SparcFrameLowering *
1220SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1221 return static_cast<const SparcFrameLowering *>(
1222 MF.getSubtarget().getFrameLowering());
1223}
1224
1225} // end namespace llvm
1226
1227