1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SparcMCRegisterClasses[];
12
13static const MVT::SimpleValueType SparcVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i32, MVT::i64, MVT::Other,
17 /* 7 */ MVT::f32, MVT::Other,
18 /* 9 */ MVT::f64, MVT::Other,
19 /* 11 */ MVT::f128, MVT::Other,
20 /* 13 */ MVT::v2i32, MVT::Other,
21};
22
23#ifdef __GNUC__
24#pragma GCC diagnostic push
25#pragma GCC diagnostic ignored "-Woverlength-strings"
26#endif
27static constexpr char SparcSubRegIndexStrings[] = {
28 /* 0 */ "sub_odd64\000"
29 /* 10 */ "sub_even64\000"
30 /* 21 */ "sub_odd64_then_sub_odd\000"
31 /* 44 */ "sub_odd64_then_sub_even\000"
32};
33#ifdef __GNUC__
34#pragma GCC diagnostic pop
35#endif
36
37
38static constexpr uint32_t SparcSubRegIndexNameOffsets[] = {
39 59,
40 10,
41 36,
42 0,
43 44,
44 21,
45};
46
47static const TargetRegisterInfo::SubRegCoveredBits SparcSubRegIdxRangeTable[] = {
48 { .Offset: 4294967295, .Size: 4294967295 },
49 { .Offset: 0, .Size: 32 }, // sub_even
50 { .Offset: 0, .Size: 64 }, // sub_even64
51 { .Offset: 32, .Size: 32 }, // sub_odd
52 { .Offset: 64, .Size: 64 }, // sub_odd64
53 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
54 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
55 { .Offset: 4294967295, .Size: 4294967295 },
56 { .Offset: 0, .Size: 32 }, // sub_even
57 { .Offset: 0, .Size: 64 }, // sub_even64
58 { .Offset: 32, .Size: 32 }, // sub_odd
59 { .Offset: 64, .Size: 64 }, // sub_odd64
60 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
61 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
62};
63
64
65static const LaneBitmask SparcSubRegIndexLaneMaskTable[] = {
66 LaneBitmask::getAll(),
67 LaneBitmask(0x0000000000000001), // sub_even
68 LaneBitmask(0x0000000000000003), // sub_even64
69 LaneBitmask(0x0000000000000002), // sub_odd
70 LaneBitmask(0x000000000000000C), // sub_odd64
71 LaneBitmask(0x0000000000000004), // sub_odd64_then_sub_even
72 LaneBitmask(0x0000000000000008), // sub_odd64_then_sub_odd
73 };
74
75
76
77static const TargetRegisterInfo::RegClassInfo SparcRegClassInfos[] = {
78 // Mode = 0 (DefaultMode)
79 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*SparcVTLists+*/.VTListOffset: 0 }, // FCCRegs
80 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // ASRRegs
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // CoprocRegs
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 7 }, // FPRegs
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // IntRegs
84 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
85 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
86 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // DFPRegs
87 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs
88 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs
89 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // CoprocPair
90 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair
91 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // LowDFPRegs
92 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
93 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
94 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
95 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
96 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
97 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // QFPRegs
98 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // LowQFPRegs
99 // Mode = 1 (SPARC64)
100 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*SparcVTLists+*/.VTListOffset: 0 }, // FCCRegs
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // ASRRegs
102 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // CoprocRegs
103 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 7 }, // FPRegs
104 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // IntRegs
105 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
106 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // DFPRegs
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs
110 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // CoprocPair
111 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair
112 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // LowDFPRegs
113 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
114 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
115 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
116 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
117 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
118 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // QFPRegs
119 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // LowQFPRegs
120};
121static const uint32_t FCCRegsSubClassMask[] = {
122 0x00000001,
123};
124
125static const uint32_t ASRRegsSubClassMask[] = {
126 0x00020002,
127};
128
129static const uint32_t CoprocRegsSubClassMask[] = {
130 0x00000004,
131 0x00000400, // sub_even
132 0x00000400, // sub_odd
133};
134
135static const uint32_t FPRegsSubClassMask[] = {
136 0x00000008,
137 0x00081000, // sub_even
138 0x00081000, // sub_odd
139 0x00080000, // sub_odd64_then_sub_even
140 0x00080000, // sub_odd64_then_sub_odd
141};
142
143static const uint32_t IntRegsSubClassMask[] = {
144 0x00006170,
145 0x00018800, // sub_even
146 0x00018800, // sub_odd
147};
148
149static const uint32_t GPRIncomingArgSubClassMask[] = {
150 0x00002020,
151 0x00008000, // sub_even
152 0x00008000, // sub_odd
153};
154
155static const uint32_t GPROutgoingArgSubClassMask[] = {
156 0x00004040,
157 0x00010000, // sub_even
158 0x00010000, // sub_odd
159};
160
161static const uint32_t DFPRegsSubClassMask[] = {
162 0x00001080,
163 0x000c0000, // sub_even64
164 0x000c0000, // sub_odd64
165};
166
167static const uint32_t I64RegsSubClassMask[] = {
168 0x00006100,
169 0x00018800, // sub_even
170 0x00018800, // sub_odd
171};
172
173static const uint32_t PRRegsSubClassMask[] = {
174 0x00020200,
175};
176
177static const uint32_t CoprocPairSubClassMask[] = {
178 0x00000400,
179};
180
181static const uint32_t IntPairSubClassMask[] = {
182 0x00018800,
183};
184
185static const uint32_t LowDFPRegsSubClassMask[] = {
186 0x00001000,
187 0x00080000, // sub_even64
188 0x00080000, // sub_odd64
189};
190
191static const uint32_t I64Regs_and_GPRIncomingArgSubClassMask[] = {
192 0x00002000,
193 0x00008000, // sub_even
194 0x00008000, // sub_odd
195};
196
197static const uint32_t I64Regs_and_GPROutgoingArgSubClassMask[] = {
198 0x00004000,
199 0x00010000, // sub_even
200 0x00010000, // sub_odd
201};
202
203static const uint32_t IntPair_with_sub_even_in_GPRIncomingArgSubClassMask[] = {
204 0x00008000,
205};
206
207static const uint32_t IntPair_with_sub_even_in_GPROutgoingArgSubClassMask[] = {
208 0x00010000,
209};
210
211static const uint32_t PRRegs_and_ASRRegsSubClassMask[] = {
212 0x00020000,
213};
214
215static const uint32_t QFPRegsSubClassMask[] = {
216 0x000c0000,
217};
218
219static const uint32_t LowQFPRegsSubClassMask[] = {
220 0x00080000,
221};
222
223static const uint16_t SuperRegIdxSeqs[] = {
224 /* 0 */ 1, 3, 0,
225 /* 3 */ 2, 4, 0,
226 /* 6 */ 1, 3, 5, 6, 0,
227};
228
229static unsigned const GPRIncomingArgSuperclasses[] = {
230 SP::IntRegsRegClassID,
231};
232
233static unsigned const GPROutgoingArgSuperclasses[] = {
234 SP::IntRegsRegClassID,
235};
236
237static unsigned const I64RegsSuperclasses[] = {
238 SP::IntRegsRegClassID,
239};
240
241static unsigned const LowDFPRegsSuperclasses[] = {
242 SP::DFPRegsRegClassID,
243};
244
245static unsigned const I64Regs_and_GPRIncomingArgSuperclasses[] = {
246 SP::IntRegsRegClassID,
247 SP::GPRIncomingArgRegClassID,
248 SP::I64RegsRegClassID,
249};
250
251static unsigned const I64Regs_and_GPROutgoingArgSuperclasses[] = {
252 SP::IntRegsRegClassID,
253 SP::GPROutgoingArgRegClassID,
254 SP::I64RegsRegClassID,
255};
256
257static unsigned const IntPair_with_sub_even_in_GPRIncomingArgSuperclasses[] = {
258 SP::IntPairRegClassID,
259};
260
261static unsigned const IntPair_with_sub_even_in_GPROutgoingArgSuperclasses[] = {
262 SP::IntPairRegClassID,
263};
264
265static unsigned const PRRegs_and_ASRRegsSuperclasses[] = {
266 SP::ASRRegsRegClassID,
267 SP::PRRegsRegClassID,
268};
269
270static unsigned const LowQFPRegsSuperclasses[] = {
271 SP::QFPRegsRegClassID,
272};
273
274namespace SP {
275
276// Register class instances.
277 extern const TargetRegisterClass FCCRegsRegClass = {
278 .MC: &SparcMCRegisterClasses[FCCRegsRegClassID],
279 .SubClassMask: FCCRegsSubClassMask,
280 .SuperRegIndices: SuperRegIdxSeqs + 2,
281 .LaneMask: LaneBitmask(0x0000000000000001),
282 .AllocationPriority: 0,
283 .GlobalPriority: false,
284 .TSFlags: 0x00, /* TSFlags */
285 .SpillStackID: 0, /* SpillStackID */
286 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
287 .CoveredBySubRegs: false, /* CoveredBySubRegs */
288 .SuperClasses: nullptr, .SuperClassesSize: 0,
289 .OrderFunc: nullptr
290 };
291
292 extern const TargetRegisterClass ASRRegsRegClass = {
293 .MC: &SparcMCRegisterClasses[ASRRegsRegClassID],
294 .SubClassMask: ASRRegsSubClassMask,
295 .SuperRegIndices: SuperRegIdxSeqs + 2,
296 .LaneMask: LaneBitmask(0x0000000000000001),
297 .AllocationPriority: 0,
298 .GlobalPriority: false,
299 .TSFlags: 0x00, /* TSFlags */
300 .SpillStackID: 0, /* SpillStackID */
301 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
302 .CoveredBySubRegs: false, /* CoveredBySubRegs */
303 .SuperClasses: nullptr, .SuperClassesSize: 0,
304 .OrderFunc: nullptr
305 };
306
307 extern const TargetRegisterClass CoprocRegsRegClass = {
308 .MC: &SparcMCRegisterClasses[CoprocRegsRegClassID],
309 .SubClassMask: CoprocRegsSubClassMask,
310 .SuperRegIndices: SuperRegIdxSeqs + 0,
311 .LaneMask: LaneBitmask(0x0000000000000001),
312 .AllocationPriority: 0,
313 .GlobalPriority: false,
314 .TSFlags: 0x00, /* TSFlags */
315 .SpillStackID: 0, /* SpillStackID */
316 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
317 .CoveredBySubRegs: false, /* CoveredBySubRegs */
318 .SuperClasses: nullptr, .SuperClassesSize: 0,
319 .OrderFunc: nullptr
320 };
321
322 extern const TargetRegisterClass FPRegsRegClass = {
323 .MC: &SparcMCRegisterClasses[FPRegsRegClassID],
324 .SubClassMask: FPRegsSubClassMask,
325 .SuperRegIndices: SuperRegIdxSeqs + 6,
326 .LaneMask: LaneBitmask(0x0000000000000001),
327 .AllocationPriority: 0,
328 .GlobalPriority: false,
329 .TSFlags: 0x00, /* TSFlags */
330 .SpillStackID: 0, /* SpillStackID */
331 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
332 .CoveredBySubRegs: false, /* CoveredBySubRegs */
333 .SuperClasses: nullptr, .SuperClassesSize: 0,
334 .OrderFunc: nullptr
335 };
336
337 extern const TargetRegisterClass IntRegsRegClass = {
338 .MC: &SparcMCRegisterClasses[IntRegsRegClassID],
339 .SubClassMask: IntRegsSubClassMask,
340 .SuperRegIndices: SuperRegIdxSeqs + 0,
341 .LaneMask: LaneBitmask(0x0000000000000001),
342 .AllocationPriority: 0,
343 .GlobalPriority: false,
344 .TSFlags: 0x00, /* TSFlags */
345 .SpillStackID: 0, /* SpillStackID */
346 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
347 .CoveredBySubRegs: false, /* CoveredBySubRegs */
348 .SuperClasses: nullptr, .SuperClassesSize: 0,
349 .OrderFunc: nullptr
350 };
351
352 extern const TargetRegisterClass GPRIncomingArgRegClass = {
353 .MC: &SparcMCRegisterClasses[GPRIncomingArgRegClassID],
354 .SubClassMask: GPRIncomingArgSubClassMask,
355 .SuperRegIndices: SuperRegIdxSeqs + 0,
356 .LaneMask: LaneBitmask(0x0000000000000001),
357 .AllocationPriority: 0,
358 .GlobalPriority: false,
359 .TSFlags: 0x00, /* TSFlags */
360 .SpillStackID: 0, /* SpillStackID */
361 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
362 .CoveredBySubRegs: false, /* CoveredBySubRegs */
363 .SuperClasses: GPRIncomingArgSuperclasses, .SuperClassesSize: 1,
364 .OrderFunc: nullptr
365 };
366
367 extern const TargetRegisterClass GPROutgoingArgRegClass = {
368 .MC: &SparcMCRegisterClasses[GPROutgoingArgRegClassID],
369 .SubClassMask: GPROutgoingArgSubClassMask,
370 .SuperRegIndices: SuperRegIdxSeqs + 0,
371 .LaneMask: LaneBitmask(0x0000000000000001),
372 .AllocationPriority: 0,
373 .GlobalPriority: false,
374 .TSFlags: 0x00, /* TSFlags */
375 .SpillStackID: 0, /* SpillStackID */
376 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
377 .CoveredBySubRegs: false, /* CoveredBySubRegs */
378 .SuperClasses: GPROutgoingArgSuperclasses, .SuperClassesSize: 1,
379 .OrderFunc: nullptr
380 };
381
382 extern const TargetRegisterClass DFPRegsRegClass = {
383 .MC: &SparcMCRegisterClasses[DFPRegsRegClassID],
384 .SubClassMask: DFPRegsSubClassMask,
385 .SuperRegIndices: SuperRegIdxSeqs + 3,
386 .LaneMask: LaneBitmask(0x0000000000000003),
387 .AllocationPriority: 0,
388 .GlobalPriority: false,
389 .TSFlags: 0x00, /* TSFlags */
390 .SpillStackID: 0, /* SpillStackID */
391 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
392 .CoveredBySubRegs: false, /* CoveredBySubRegs */
393 .SuperClasses: nullptr, .SuperClassesSize: 0,
394 .OrderFunc: nullptr
395 };
396
397 extern const TargetRegisterClass I64RegsRegClass = {
398 .MC: &SparcMCRegisterClasses[I64RegsRegClassID],
399 .SubClassMask: I64RegsSubClassMask,
400 .SuperRegIndices: SuperRegIdxSeqs + 0,
401 .LaneMask: LaneBitmask(0x0000000000000001),
402 .AllocationPriority: 0,
403 .GlobalPriority: false,
404 .TSFlags: 0x00, /* TSFlags */
405 .SpillStackID: 0, /* SpillStackID */
406 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
407 .CoveredBySubRegs: false, /* CoveredBySubRegs */
408 .SuperClasses: I64RegsSuperclasses, .SuperClassesSize: 1,
409 .OrderFunc: nullptr
410 };
411
412 extern const TargetRegisterClass PRRegsRegClass = {
413 .MC: &SparcMCRegisterClasses[PRRegsRegClassID],
414 .SubClassMask: PRRegsSubClassMask,
415 .SuperRegIndices: SuperRegIdxSeqs + 2,
416 .LaneMask: LaneBitmask(0x0000000000000001),
417 .AllocationPriority: 0,
418 .GlobalPriority: false,
419 .TSFlags: 0x00, /* TSFlags */
420 .SpillStackID: 0, /* SpillStackID */
421 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
422 .CoveredBySubRegs: false, /* CoveredBySubRegs */
423 .SuperClasses: nullptr, .SuperClassesSize: 0,
424 .OrderFunc: nullptr
425 };
426
427 extern const TargetRegisterClass CoprocPairRegClass = {
428 .MC: &SparcMCRegisterClasses[CoprocPairRegClassID],
429 .SubClassMask: CoprocPairSubClassMask,
430 .SuperRegIndices: SuperRegIdxSeqs + 2,
431 .LaneMask: LaneBitmask(0x0000000000000003),
432 .AllocationPriority: 0,
433 .GlobalPriority: false,
434 .TSFlags: 0x00, /* TSFlags */
435 .SpillStackID: 0, /* SpillStackID */
436 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
437 .CoveredBySubRegs: true, /* CoveredBySubRegs */
438 .SuperClasses: nullptr, .SuperClassesSize: 0,
439 .OrderFunc: nullptr
440 };
441
442 extern const TargetRegisterClass IntPairRegClass = {
443 .MC: &SparcMCRegisterClasses[IntPairRegClassID],
444 .SubClassMask: IntPairSubClassMask,
445 .SuperRegIndices: SuperRegIdxSeqs + 2,
446 .LaneMask: LaneBitmask(0x0000000000000003),
447 .AllocationPriority: 0,
448 .GlobalPriority: false,
449 .TSFlags: 0x00, /* TSFlags */
450 .SpillStackID: 0, /* SpillStackID */
451 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
452 .CoveredBySubRegs: true, /* CoveredBySubRegs */
453 .SuperClasses: nullptr, .SuperClassesSize: 0,
454 .OrderFunc: nullptr
455 };
456
457 extern const TargetRegisterClass LowDFPRegsRegClass = {
458 .MC: &SparcMCRegisterClasses[LowDFPRegsRegClassID],
459 .SubClassMask: LowDFPRegsSubClassMask,
460 .SuperRegIndices: SuperRegIdxSeqs + 3,
461 .LaneMask: LaneBitmask(0x0000000000000003),
462 .AllocationPriority: 0,
463 .GlobalPriority: false,
464 .TSFlags: 0x00, /* TSFlags */
465 .SpillStackID: 0, /* SpillStackID */
466 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
467 .CoveredBySubRegs: true, /* CoveredBySubRegs */
468 .SuperClasses: LowDFPRegsSuperclasses, .SuperClassesSize: 1,
469 .OrderFunc: nullptr
470 };
471
472 extern const TargetRegisterClass I64Regs_and_GPRIncomingArgRegClass = {
473 .MC: &SparcMCRegisterClasses[I64Regs_and_GPRIncomingArgRegClassID],
474 .SubClassMask: I64Regs_and_GPRIncomingArgSubClassMask,
475 .SuperRegIndices: SuperRegIdxSeqs + 0,
476 .LaneMask: LaneBitmask(0x0000000000000001),
477 .AllocationPriority: 0,
478 .GlobalPriority: false,
479 .TSFlags: 0x00, /* TSFlags */
480 .SpillStackID: 0, /* SpillStackID */
481 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
482 .CoveredBySubRegs: false, /* CoveredBySubRegs */
483 .SuperClasses: I64Regs_and_GPRIncomingArgSuperclasses, .SuperClassesSize: 3,
484 .OrderFunc: nullptr
485 };
486
487 extern const TargetRegisterClass I64Regs_and_GPROutgoingArgRegClass = {
488 .MC: &SparcMCRegisterClasses[I64Regs_and_GPROutgoingArgRegClassID],
489 .SubClassMask: I64Regs_and_GPROutgoingArgSubClassMask,
490 .SuperRegIndices: SuperRegIdxSeqs + 0,
491 .LaneMask: LaneBitmask(0x0000000000000001),
492 .AllocationPriority: 0,
493 .GlobalPriority: false,
494 .TSFlags: 0x00, /* TSFlags */
495 .SpillStackID: 0, /* SpillStackID */
496 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
497 .CoveredBySubRegs: false, /* CoveredBySubRegs */
498 .SuperClasses: I64Regs_and_GPROutgoingArgSuperclasses, .SuperClassesSize: 3,
499 .OrderFunc: nullptr
500 };
501
502 extern const TargetRegisterClass IntPair_with_sub_even_in_GPRIncomingArgRegClass = {
503 .MC: &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPRIncomingArgRegClassID],
504 .SubClassMask: IntPair_with_sub_even_in_GPRIncomingArgSubClassMask,
505 .SuperRegIndices: SuperRegIdxSeqs + 2,
506 .LaneMask: LaneBitmask(0x0000000000000003),
507 .AllocationPriority: 0,
508 .GlobalPriority: false,
509 .TSFlags: 0x00, /* TSFlags */
510 .SpillStackID: 0, /* SpillStackID */
511 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
512 .CoveredBySubRegs: true, /* CoveredBySubRegs */
513 .SuperClasses: IntPair_with_sub_even_in_GPRIncomingArgSuperclasses, .SuperClassesSize: 1,
514 .OrderFunc: nullptr
515 };
516
517 extern const TargetRegisterClass IntPair_with_sub_even_in_GPROutgoingArgRegClass = {
518 .MC: &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPROutgoingArgRegClassID],
519 .SubClassMask: IntPair_with_sub_even_in_GPROutgoingArgSubClassMask,
520 .SuperRegIndices: SuperRegIdxSeqs + 2,
521 .LaneMask: LaneBitmask(0x0000000000000003),
522 .AllocationPriority: 0,
523 .GlobalPriority: false,
524 .TSFlags: 0x00, /* TSFlags */
525 .SpillStackID: 0, /* SpillStackID */
526 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
527 .CoveredBySubRegs: true, /* CoveredBySubRegs */
528 .SuperClasses: IntPair_with_sub_even_in_GPROutgoingArgSuperclasses, .SuperClassesSize: 1,
529 .OrderFunc: nullptr
530 };
531
532 extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass = {
533 .MC: &SparcMCRegisterClasses[PRRegs_and_ASRRegsRegClassID],
534 .SubClassMask: PRRegs_and_ASRRegsSubClassMask,
535 .SuperRegIndices: SuperRegIdxSeqs + 2,
536 .LaneMask: LaneBitmask(0x0000000000000001),
537 .AllocationPriority: 0,
538 .GlobalPriority: false,
539 .TSFlags: 0x00, /* TSFlags */
540 .SpillStackID: 0, /* SpillStackID */
541 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
542 .CoveredBySubRegs: false, /* CoveredBySubRegs */
543 .SuperClasses: PRRegs_and_ASRRegsSuperclasses, .SuperClassesSize: 2,
544 .OrderFunc: nullptr
545 };
546
547 extern const TargetRegisterClass QFPRegsRegClass = {
548 .MC: &SparcMCRegisterClasses[QFPRegsRegClassID],
549 .SubClassMask: QFPRegsSubClassMask,
550 .SuperRegIndices: SuperRegIdxSeqs + 2,
551 .LaneMask: LaneBitmask(0x000000000000000F),
552 .AllocationPriority: 0,
553 .GlobalPriority: false,
554 .TSFlags: 0x00, /* TSFlags */
555 .SpillStackID: 0, /* SpillStackID */
556 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
557 .CoveredBySubRegs: true, /* CoveredBySubRegs */
558 .SuperClasses: nullptr, .SuperClassesSize: 0,
559 .OrderFunc: nullptr
560 };
561
562 extern const TargetRegisterClass LowQFPRegsRegClass = {
563 .MC: &SparcMCRegisterClasses[LowQFPRegsRegClassID],
564 .SubClassMask: LowQFPRegsSubClassMask,
565 .SuperRegIndices: SuperRegIdxSeqs + 2,
566 .LaneMask: LaneBitmask(0x000000000000000F),
567 .AllocationPriority: 0,
568 .GlobalPriority: false,
569 .TSFlags: 0x00, /* TSFlags */
570 .SpillStackID: 0, /* SpillStackID */
571 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
572 .CoveredBySubRegs: true, /* CoveredBySubRegs */
573 .SuperClasses: LowQFPRegsSuperclasses, .SuperClassesSize: 1,
574 .OrderFunc: nullptr
575 };
576
577
578} // namespace SP
579static const TargetRegisterClass *const SparcRegisterClasses[] = {
580 &SP::FCCRegsRegClass,
581 &SP::ASRRegsRegClass,
582 &SP::CoprocRegsRegClass,
583 &SP::FPRegsRegClass,
584 &SP::IntRegsRegClass,
585 &SP::GPRIncomingArgRegClass,
586 &SP::GPROutgoingArgRegClass,
587 &SP::DFPRegsRegClass,
588 &SP::I64RegsRegClass,
589 &SP::PRRegsRegClass,
590 &SP::CoprocPairRegClass,
591 &SP::IntPairRegClass,
592 &SP::LowDFPRegsRegClass,
593 &SP::I64Regs_and_GPRIncomingArgRegClass,
594 &SP::I64Regs_and_GPROutgoingArgRegClass,
595 &SP::IntPair_with_sub_even_in_GPRIncomingArgRegClass,
596 &SP::IntPair_with_sub_even_in_GPROutgoingArgRegClass,
597 &SP::PRRegs_and_ASRRegsRegClass,
598 &SP::QFPRegsRegClass,
599 &SP::LowQFPRegsRegClass,
600 };
601
602static const uint8_t SparcCostPerUseTable[] = {
6030, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
604
605
606static const bool SparcInAllocatableClassTable[] = {
607false, true, true, true, false, false, true, false, false, true, false, true, true, false, true, true, false, true, true, true, true, true, true, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
608
609
610static const TargetRegisterInfoDesc SparcRegInfoDesc = { // Extra Descriptors
611.CostPerUse: SparcCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SparcInAllocatableClassTable};
612
613unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
614 static const uint8_t RowMap[6] = {
615 0, 0, 0, 1, 0, 0,
616 };
617 static const uint8_t Rows[2][6] = {
618 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
619 { SP::sub_odd64_then_sub_even, 0, SP::sub_odd64_then_sub_odd, 0, 0, 0, },
620 };
621
622 --IdxA; assert(IdxA < 6); (void) IdxA;
623 --IdxB; assert(IdxB < 6);
624 return Rows[RowMap[IdxA]][IdxB];
625}
626
627unsigned SparcGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
628 static const uint8_t Table[6][6] = {
629 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
630 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
631 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
632 { 0, 0, 0, 0, SP::sub_even, SP::sub_odd, },
633 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
634 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
635 };
636
637 --IdxA; assert(IdxA < 6);
638 --IdxB; assert(IdxB < 6);
639 return Table[IdxA][IdxB];
640 }
641
642 struct MaskRolOp {
643 LaneBitmask Mask;
644 uint8_t RotateLeft;
645 };
646 static const MaskRolOp LaneMaskComposeSequences[] = {
647 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
648 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
649 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
650 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 6
651 };
652 static const uint8_t CompositeSequences[] = {
653 0, // to sub_even
654 0, // to sub_even64
655 2, // to sub_odd
656 4, // to sub_odd64
657 4, // to sub_odd64_then_sub_even
658 6 // to sub_odd64_then_sub_odd
659 };
660
661LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
662 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
663 LaneBitmask Result;
664 for (const MaskRolOp *Ops =
665 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
666 Ops->Mask.any(); ++Ops) {
667 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
668 if (unsigned S = Ops->RotateLeft)
669 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
670 else
671 Result |= LaneBitmask(M);
672 }
673 return Result;
674}
675
676LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
677 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
678 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
679 LaneBitmask Result;
680 for (const MaskRolOp *Ops =
681 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
682 Ops->Mask.any(); ++Ops) {
683 LaneBitmask::Type M = LaneMask.getAsInteger();
684 if (unsigned S = Ops->RotateLeft)
685 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
686 else
687 Result |= LaneBitmask(M);
688 }
689 return Result;
690}
691
692const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
693 static constexpr uint8_t Table[20][6] = {
694 { // FCCRegs
695 0, // sub_even
696 0, // sub_even64
697 0, // sub_odd
698 0, // sub_odd64
699 0, // sub_odd64_then_sub_even
700 0, // sub_odd64_then_sub_odd
701 },
702 { // ASRRegs
703 0, // sub_even
704 0, // sub_even64
705 0, // sub_odd
706 0, // sub_odd64
707 0, // sub_odd64_then_sub_even
708 0, // sub_odd64_then_sub_odd
709 },
710 { // CoprocRegs
711 0, // sub_even
712 0, // sub_even64
713 0, // sub_odd
714 0, // sub_odd64
715 0, // sub_odd64_then_sub_even
716 0, // sub_odd64_then_sub_odd
717 },
718 { // FPRegs
719 0, // sub_even
720 0, // sub_even64
721 0, // sub_odd
722 0, // sub_odd64
723 0, // sub_odd64_then_sub_even
724 0, // sub_odd64_then_sub_odd
725 },
726 { // IntRegs
727 0, // sub_even
728 0, // sub_even64
729 0, // sub_odd
730 0, // sub_odd64
731 0, // sub_odd64_then_sub_even
732 0, // sub_odd64_then_sub_odd
733 },
734 { // GPRIncomingArg
735 0, // sub_even
736 0, // sub_even64
737 0, // sub_odd
738 0, // sub_odd64
739 0, // sub_odd64_then_sub_even
740 0, // sub_odd64_then_sub_odd
741 },
742 { // GPROutgoingArg
743 0, // sub_even
744 0, // sub_even64
745 0, // sub_odd
746 0, // sub_odd64
747 0, // sub_odd64_then_sub_even
748 0, // sub_odd64_then_sub_odd
749 },
750 { // DFPRegs
751 13, // sub_even -> LowDFPRegs
752 0, // sub_even64
753 13, // sub_odd -> LowDFPRegs
754 0, // sub_odd64
755 0, // sub_odd64_then_sub_even
756 0, // sub_odd64_then_sub_odd
757 },
758 { // I64Regs
759 0, // sub_even
760 0, // sub_even64
761 0, // sub_odd
762 0, // sub_odd64
763 0, // sub_odd64_then_sub_even
764 0, // sub_odd64_then_sub_odd
765 },
766 { // PRRegs
767 0, // sub_even
768 0, // sub_even64
769 0, // sub_odd
770 0, // sub_odd64
771 0, // sub_odd64_then_sub_even
772 0, // sub_odd64_then_sub_odd
773 },
774 { // CoprocPair
775 11, // sub_even -> CoprocPair
776 0, // sub_even64
777 11, // sub_odd -> CoprocPair
778 0, // sub_odd64
779 0, // sub_odd64_then_sub_even
780 0, // sub_odd64_then_sub_odd
781 },
782 { // IntPair
783 12, // sub_even -> IntPair
784 0, // sub_even64
785 12, // sub_odd -> IntPair
786 0, // sub_odd64
787 0, // sub_odd64_then_sub_even
788 0, // sub_odd64_then_sub_odd
789 },
790 { // LowDFPRegs
791 13, // sub_even -> LowDFPRegs
792 0, // sub_even64
793 13, // sub_odd -> LowDFPRegs
794 0, // sub_odd64
795 0, // sub_odd64_then_sub_even
796 0, // sub_odd64_then_sub_odd
797 },
798 { // I64Regs_and_GPRIncomingArg
799 0, // sub_even
800 0, // sub_even64
801 0, // sub_odd
802 0, // sub_odd64
803 0, // sub_odd64_then_sub_even
804 0, // sub_odd64_then_sub_odd
805 },
806 { // I64Regs_and_GPROutgoingArg
807 0, // sub_even
808 0, // sub_even64
809 0, // sub_odd
810 0, // sub_odd64
811 0, // sub_odd64_then_sub_even
812 0, // sub_odd64_then_sub_odd
813 },
814 { // IntPair_with_sub_even_in_GPRIncomingArg
815 16, // sub_even -> IntPair_with_sub_even_in_GPRIncomingArg
816 0, // sub_even64
817 16, // sub_odd -> IntPair_with_sub_even_in_GPRIncomingArg
818 0, // sub_odd64
819 0, // sub_odd64_then_sub_even
820 0, // sub_odd64_then_sub_odd
821 },
822 { // IntPair_with_sub_even_in_GPROutgoingArg
823 17, // sub_even -> IntPair_with_sub_even_in_GPROutgoingArg
824 0, // sub_even64
825 17, // sub_odd -> IntPair_with_sub_even_in_GPROutgoingArg
826 0, // sub_odd64
827 0, // sub_odd64_then_sub_even
828 0, // sub_odd64_then_sub_odd
829 },
830 { // PRRegs_and_ASRRegs
831 0, // sub_even
832 0, // sub_even64
833 0, // sub_odd
834 0, // sub_odd64
835 0, // sub_odd64_then_sub_even
836 0, // sub_odd64_then_sub_odd
837 },
838 { // QFPRegs
839 20, // sub_even -> LowQFPRegs
840 19, // sub_even64 -> QFPRegs
841 20, // sub_odd -> LowQFPRegs
842 19, // sub_odd64 -> QFPRegs
843 20, // sub_odd64_then_sub_even -> LowQFPRegs
844 20, // sub_odd64_then_sub_odd -> LowQFPRegs
845 },
846 { // LowQFPRegs
847 20, // sub_even -> LowQFPRegs
848 20, // sub_even64 -> LowQFPRegs
849 20, // sub_odd -> LowQFPRegs
850 20, // sub_odd64 -> LowQFPRegs
851 20, // sub_odd64_then_sub_even -> LowQFPRegs
852 20, // sub_odd64_then_sub_odd -> LowQFPRegs
853 },
854
855 };
856 assert(RC && "Missing regclass");
857 if (!Idx) return RC;
858 --Idx;
859 assert(Idx < 6 && "Bad subreg");
860 unsigned TV = Table[RC->getID()][Idx];
861 return TV ? getRegClass(i: TV - 1) : nullptr;
862}const TargetRegisterClass *SparcGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
863 static constexpr uint8_t Table[20][6] = {
864 { // FCCRegs
865 0, // FCCRegs:sub_even
866 0, // FCCRegs:sub_even64
867 0, // FCCRegs:sub_odd
868 0, // FCCRegs:sub_odd64
869 0, // FCCRegs:sub_odd64_then_sub_even
870 0, // FCCRegs:sub_odd64_then_sub_odd
871 },
872 { // ASRRegs
873 0, // ASRRegs:sub_even
874 0, // ASRRegs:sub_even64
875 0, // ASRRegs:sub_odd
876 0, // ASRRegs:sub_odd64
877 0, // ASRRegs:sub_odd64_then_sub_even
878 0, // ASRRegs:sub_odd64_then_sub_odd
879 },
880 { // CoprocRegs
881 0, // CoprocRegs:sub_even
882 0, // CoprocRegs:sub_even64
883 0, // CoprocRegs:sub_odd
884 0, // CoprocRegs:sub_odd64
885 0, // CoprocRegs:sub_odd64_then_sub_even
886 0, // CoprocRegs:sub_odd64_then_sub_odd
887 },
888 { // FPRegs
889 0, // FPRegs:sub_even
890 0, // FPRegs:sub_even64
891 0, // FPRegs:sub_odd
892 0, // FPRegs:sub_odd64
893 0, // FPRegs:sub_odd64_then_sub_even
894 0, // FPRegs:sub_odd64_then_sub_odd
895 },
896 { // IntRegs
897 0, // IntRegs:sub_even
898 0, // IntRegs:sub_even64
899 0, // IntRegs:sub_odd
900 0, // IntRegs:sub_odd64
901 0, // IntRegs:sub_odd64_then_sub_even
902 0, // IntRegs:sub_odd64_then_sub_odd
903 },
904 { // GPRIncomingArg
905 0, // GPRIncomingArg:sub_even
906 0, // GPRIncomingArg:sub_even64
907 0, // GPRIncomingArg:sub_odd
908 0, // GPRIncomingArg:sub_odd64
909 0, // GPRIncomingArg:sub_odd64_then_sub_even
910 0, // GPRIncomingArg:sub_odd64_then_sub_odd
911 },
912 { // GPROutgoingArg
913 0, // GPROutgoingArg:sub_even
914 0, // GPROutgoingArg:sub_even64
915 0, // GPROutgoingArg:sub_odd
916 0, // GPROutgoingArg:sub_odd64
917 0, // GPROutgoingArg:sub_odd64_then_sub_even
918 0, // GPROutgoingArg:sub_odd64_then_sub_odd
919 },
920 { // DFPRegs
921 4, // DFPRegs:sub_even -> FPRegs
922 0, // DFPRegs:sub_even64
923 4, // DFPRegs:sub_odd -> FPRegs
924 0, // DFPRegs:sub_odd64
925 0, // DFPRegs:sub_odd64_then_sub_even
926 0, // DFPRegs:sub_odd64_then_sub_odd
927 },
928 { // I64Regs
929 0, // I64Regs:sub_even
930 0, // I64Regs:sub_even64
931 0, // I64Regs:sub_odd
932 0, // I64Regs:sub_odd64
933 0, // I64Regs:sub_odd64_then_sub_even
934 0, // I64Regs:sub_odd64_then_sub_odd
935 },
936 { // PRRegs
937 0, // PRRegs:sub_even
938 0, // PRRegs:sub_even64
939 0, // PRRegs:sub_odd
940 0, // PRRegs:sub_odd64
941 0, // PRRegs:sub_odd64_then_sub_even
942 0, // PRRegs:sub_odd64_then_sub_odd
943 },
944 { // CoprocPair
945 3, // CoprocPair:sub_even -> CoprocRegs
946 0, // CoprocPair:sub_even64
947 3, // CoprocPair:sub_odd -> CoprocRegs
948 0, // CoprocPair:sub_odd64
949 0, // CoprocPair:sub_odd64_then_sub_even
950 0, // CoprocPair:sub_odd64_then_sub_odd
951 },
952 { // IntPair
953 9, // IntPair:sub_even -> I64Regs
954 0, // IntPair:sub_even64
955 9, // IntPair:sub_odd -> I64Regs
956 0, // IntPair:sub_odd64
957 0, // IntPair:sub_odd64_then_sub_even
958 0, // IntPair:sub_odd64_then_sub_odd
959 },
960 { // LowDFPRegs
961 4, // LowDFPRegs:sub_even -> FPRegs
962 0, // LowDFPRegs:sub_even64
963 4, // LowDFPRegs:sub_odd -> FPRegs
964 0, // LowDFPRegs:sub_odd64
965 0, // LowDFPRegs:sub_odd64_then_sub_even
966 0, // LowDFPRegs:sub_odd64_then_sub_odd
967 },
968 { // I64Regs_and_GPRIncomingArg
969 0, // I64Regs_and_GPRIncomingArg:sub_even
970 0, // I64Regs_and_GPRIncomingArg:sub_even64
971 0, // I64Regs_and_GPRIncomingArg:sub_odd
972 0, // I64Regs_and_GPRIncomingArg:sub_odd64
973 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_even
974 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_odd
975 },
976 { // I64Regs_and_GPROutgoingArg
977 0, // I64Regs_and_GPROutgoingArg:sub_even
978 0, // I64Regs_and_GPROutgoingArg:sub_even64
979 0, // I64Regs_and_GPROutgoingArg:sub_odd
980 0, // I64Regs_and_GPROutgoingArg:sub_odd64
981 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_even
982 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_odd
983 },
984 { // IntPair_with_sub_even_in_GPRIncomingArg
985 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even -> I64Regs_and_GPRIncomingArg
986 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even64
987 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd -> I64Regs_and_GPRIncomingArg
988 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64
989 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_even
990 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_odd
991 },
992 { // IntPair_with_sub_even_in_GPROutgoingArg
993 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even -> I64Regs_and_GPROutgoingArg
994 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even64
995 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd -> I64Regs_and_GPROutgoingArg
996 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64
997 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_even
998 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_odd
999 },
1000 { // PRRegs_and_ASRRegs
1001 0, // PRRegs_and_ASRRegs:sub_even
1002 0, // PRRegs_and_ASRRegs:sub_even64
1003 0, // PRRegs_and_ASRRegs:sub_odd
1004 0, // PRRegs_and_ASRRegs:sub_odd64
1005 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_even
1006 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_odd
1007 },
1008 { // QFPRegs
1009 4, // QFPRegs:sub_even -> FPRegs
1010 8, // QFPRegs:sub_even64 -> DFPRegs
1011 4, // QFPRegs:sub_odd -> FPRegs
1012 8, // QFPRegs:sub_odd64 -> DFPRegs
1013 4, // QFPRegs:sub_odd64_then_sub_even -> FPRegs
1014 4, // QFPRegs:sub_odd64_then_sub_odd -> FPRegs
1015 },
1016 { // LowQFPRegs
1017 4, // LowQFPRegs:sub_even -> FPRegs
1018 13, // LowQFPRegs:sub_even64 -> LowDFPRegs
1019 4, // LowQFPRegs:sub_odd -> FPRegs
1020 13, // LowQFPRegs:sub_odd64 -> LowDFPRegs
1021 4, // LowQFPRegs:sub_odd64_then_sub_even -> FPRegs
1022 4, // LowQFPRegs:sub_odd64_then_sub_odd -> FPRegs
1023 },
1024
1025 };
1026 assert(RC && "Missing regclass");
1027 if (!Idx) return RC;
1028 --Idx;
1029 assert(Idx < 6 && "Bad subreg");
1030 unsigned TV = Table[RC->getID()][Idx];
1031 return TV ? getRegClass(i: TV - 1) : nullptr;
1032}/// Get the weight in units of pressure for this register class.
1033const RegClassWeight &SparcGenRegisterInfo::
1034getRegClassWeight(const TargetRegisterClass *RC) const {
1035 static const RegClassWeight RCWeightTable[] = {
1036 {.RegWeight: 1, .WeightLimit: 4}, // FCCRegs
1037 {.RegWeight: 1, .WeightLimit: 1}, // ASRRegs
1038 {.RegWeight: 0, .WeightLimit: 0}, // CoprocRegs
1039 {.RegWeight: 1, .WeightLimit: 32}, // FPRegs
1040 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
1041 {.RegWeight: 1, .WeightLimit: 6}, // GPRIncomingArg
1042 {.RegWeight: 1, .WeightLimit: 6}, // GPROutgoingArg
1043 {.RegWeight: 2, .WeightLimit: 64}, // DFPRegs
1044 {.RegWeight: 1, .WeightLimit: 32}, // I64Regs
1045 {.RegWeight: 1, .WeightLimit: 17}, // PRRegs
1046 {.RegWeight: 0, .WeightLimit: 0}, // CoprocPair
1047 {.RegWeight: 2, .WeightLimit: 32}, // IntPair
1048 {.RegWeight: 2, .WeightLimit: 32}, // LowDFPRegs
1049 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPRIncomingArg
1050 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPROutgoingArg
1051 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPRIncomingArg
1052 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPROutgoingArg
1053 {.RegWeight: 1, .WeightLimit: 1}, // PRRegs_and_ASRRegs
1054 {.RegWeight: 4, .WeightLimit: 64}, // QFPRegs
1055 {.RegWeight: 4, .WeightLimit: 32}, // LowQFPRegs
1056 };
1057 return RCWeightTable[RC->getID()];
1058}
1059
1060/// Get the weight in units of pressure for this register unit.
1061unsigned SparcGenRegisterInfo::
1062getRegUnitWeight(MCRegUnit RegUnit) const {
1063 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
1064 static const uint8_t RUWeightTable[] = {
1065 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
1066 return RUWeightTable[static_cast<unsigned>(RegUnit)];
1067}
1068
1069
1070// Get the number of dimensions of register pressure.
1071unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
1072 return 8;
1073}
1074
1075// Get the name of this register unit pressure set.
1076const char *SparcGenRegisterInfo::
1077getRegPressureSetName(unsigned Idx) const {
1078 static const char *PressureNameTable[] = {
1079 "PRRegs_and_ASRRegs",
1080 "FCCRegs",
1081 "GPRIncomingArg",
1082 "GPROutgoingArg",
1083 "PRRegs",
1084 "FPRegs",
1085 "IntRegs",
1086 "DFPRegs",
1087 };
1088 return PressureNameTable[Idx];
1089}
1090
1091// Get the register unit pressure limit for this dimension.
1092// This limit must be adjusted dynamically for reserved registers.
1093unsigned SparcGenRegisterInfo::
1094getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1095 static const uint8_t PressureLimitTable[] = {
1096 1, // 0: PRRegs_and_ASRRegs
1097 4, // 1: FCCRegs
1098 6, // 2: GPRIncomingArg
1099 6, // 3: GPROutgoingArg
1100 17, // 4: PRRegs
1101 32, // 5: FPRegs
1102 32, // 6: IntRegs
1103 64, // 7: DFPRegs
1104 };
1105 return PressureLimitTable[Idx];
1106}
1107
1108/// Table of pressure sets per register class or unit.
1109static const int RCSetsTable[] = {
1110 /* 0 */ 1, -1,
1111 /* 2 */ 0, 4, -1,
1112 /* 5 */ 2, 6, -1,
1113 /* 8 */ 3, 6, -1,
1114 /* 11 */ 5, 7, -1,
1115};
1116
1117/// Get the dimensions of register pressure impacted by this register class.
1118/// Returns a -1 terminated array of pressure set IDs
1119const int *SparcGenRegisterInfo::
1120getRegClassPressureSets(const TargetRegisterClass *RC) const {
1121 static const uint8_t RCSetStartTable[] = {
1122 0,1,1,11,6,5,8,12,6,3,1,6,11,5,8,5,8,2,12,11,};
1123 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1124}
1125
1126/// Get the dimensions of register pressure impacted by this register unit.
1127/// Returns a -1 terminated array of pressure set IDs
1128const int *SparcGenRegisterInfo::
1129getRegUnitPressureSets(MCRegUnit RegUnit) const {
1130 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
1131 static const uint8_t RUSetStartTable[] = {
1132 3,3,3,1,1,3,1,1,3,1,3,3,1,3,3,1,2,3,3,3,3,3,3,1,3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,0,0,0,0,6,6,6,6,6,6,6,6,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,8,8,8,8,8,8,6,6,};
1133 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1134}
1135
1136
1137// Register to minimal register class mapping
1138
1139const TargetRegisterClass *SparcGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
1140 static const uint16_t InvalidRegClassID = UINT16_MAX;
1141
1142 static const uint16_t Mapping[238] = {
1143 InvalidRegClassID, // NoRegister
1144 SP::PRRegsRegClassID, // CANRESTORE
1145 SP::PRRegsRegClassID, // CANSAVE
1146 SP::PRRegsRegClassID, // CLEANWIN
1147 InvalidRegClassID, // CPQ
1148 InvalidRegClassID, // CPSR
1149 SP::PRRegsRegClassID, // CWP
1150 InvalidRegClassID, // FQ
1151 InvalidRegClassID, // FSR
1152 SP::PRRegsRegClassID, // GL
1153 InvalidRegClassID, // ICC
1154 SP::PRRegsRegClassID, // OTHERWIN
1155 SP::PRRegsRegClassID, // PIL
1156 InvalidRegClassID, // PSR
1157 SP::PRRegsRegClassID, // PSTATE
1158 SP::PRRegsRegClassID, // TBA
1159 InvalidRegClassID, // TBR
1160 SP::PRRegs_and_ASRRegsRegClassID, // TICK
1161 SP::PRRegsRegClassID, // TL
1162 SP::PRRegsRegClassID, // TNPC
1163 SP::PRRegsRegClassID, // TPC
1164 SP::PRRegsRegClassID, // TSTATE
1165 SP::PRRegsRegClassID, // TT
1166 SP::PRRegsRegClassID, // VER
1167 InvalidRegClassID, // WIM
1168 SP::PRRegsRegClassID, // WSTATE
1169 SP::ASRRegsRegClassID, // Y
1170 SP::ASRRegsRegClassID, // ASR1
1171 SP::ASRRegsRegClassID, // ASR2
1172 SP::ASRRegsRegClassID, // ASR3
1173 SP::ASRRegsRegClassID, // ASR4
1174 SP::ASRRegsRegClassID, // ASR5
1175 SP::ASRRegsRegClassID, // ASR6
1176 SP::ASRRegsRegClassID, // ASR7
1177 SP::ASRRegsRegClassID, // ASR8
1178 SP::ASRRegsRegClassID, // ASR9
1179 SP::ASRRegsRegClassID, // ASR10
1180 SP::ASRRegsRegClassID, // ASR11
1181 SP::ASRRegsRegClassID, // ASR12
1182 SP::ASRRegsRegClassID, // ASR13
1183 SP::ASRRegsRegClassID, // ASR14
1184 SP::ASRRegsRegClassID, // ASR15
1185 SP::ASRRegsRegClassID, // ASR16
1186 SP::ASRRegsRegClassID, // ASR17
1187 SP::ASRRegsRegClassID, // ASR18
1188 SP::ASRRegsRegClassID, // ASR19
1189 SP::ASRRegsRegClassID, // ASR20
1190 SP::ASRRegsRegClassID, // ASR21
1191 SP::ASRRegsRegClassID, // ASR22
1192 SP::ASRRegsRegClassID, // ASR23
1193 SP::ASRRegsRegClassID, // ASR24
1194 SP::ASRRegsRegClassID, // ASR25
1195 SP::ASRRegsRegClassID, // ASR26
1196 SP::ASRRegsRegClassID, // ASR27
1197 SP::ASRRegsRegClassID, // ASR28
1198 SP::ASRRegsRegClassID, // ASR29
1199 SP::ASRRegsRegClassID, // ASR30
1200 SP::ASRRegsRegClassID, // ASR31
1201 SP::CoprocRegsRegClassID, // C0
1202 SP::CoprocRegsRegClassID, // C1
1203 SP::CoprocRegsRegClassID, // C2
1204 SP::CoprocRegsRegClassID, // C3
1205 SP::CoprocRegsRegClassID, // C4
1206 SP::CoprocRegsRegClassID, // C5
1207 SP::CoprocRegsRegClassID, // C6
1208 SP::CoprocRegsRegClassID, // C7
1209 SP::CoprocRegsRegClassID, // C8
1210 SP::CoprocRegsRegClassID, // C9
1211 SP::CoprocRegsRegClassID, // C10
1212 SP::CoprocRegsRegClassID, // C11
1213 SP::CoprocRegsRegClassID, // C12
1214 SP::CoprocRegsRegClassID, // C13
1215 SP::CoprocRegsRegClassID, // C14
1216 SP::CoprocRegsRegClassID, // C15
1217 SP::CoprocRegsRegClassID, // C16
1218 SP::CoprocRegsRegClassID, // C17
1219 SP::CoprocRegsRegClassID, // C18
1220 SP::CoprocRegsRegClassID, // C19
1221 SP::CoprocRegsRegClassID, // C20
1222 SP::CoprocRegsRegClassID, // C21
1223 SP::CoprocRegsRegClassID, // C22
1224 SP::CoprocRegsRegClassID, // C23
1225 SP::CoprocRegsRegClassID, // C24
1226 SP::CoprocRegsRegClassID, // C25
1227 SP::CoprocRegsRegClassID, // C26
1228 SP::CoprocRegsRegClassID, // C27
1229 SP::CoprocRegsRegClassID, // C28
1230 SP::CoprocRegsRegClassID, // C29
1231 SP::CoprocRegsRegClassID, // C30
1232 SP::CoprocRegsRegClassID, // C31
1233 SP::LowDFPRegsRegClassID, // D0
1234 SP::LowDFPRegsRegClassID, // D1
1235 SP::LowDFPRegsRegClassID, // D2
1236 SP::LowDFPRegsRegClassID, // D3
1237 SP::LowDFPRegsRegClassID, // D4
1238 SP::LowDFPRegsRegClassID, // D5
1239 SP::LowDFPRegsRegClassID, // D6
1240 SP::LowDFPRegsRegClassID, // D7
1241 SP::LowDFPRegsRegClassID, // D8
1242 SP::LowDFPRegsRegClassID, // D9
1243 SP::LowDFPRegsRegClassID, // D10
1244 SP::LowDFPRegsRegClassID, // D11
1245 SP::LowDFPRegsRegClassID, // D12
1246 SP::LowDFPRegsRegClassID, // D13
1247 SP::LowDFPRegsRegClassID, // D14
1248 SP::LowDFPRegsRegClassID, // D15
1249 SP::DFPRegsRegClassID, // D16
1250 SP::DFPRegsRegClassID, // D17
1251 SP::DFPRegsRegClassID, // D18
1252 SP::DFPRegsRegClassID, // D19
1253 SP::DFPRegsRegClassID, // D20
1254 SP::DFPRegsRegClassID, // D21
1255 SP::DFPRegsRegClassID, // D22
1256 SP::DFPRegsRegClassID, // D23
1257 SP::DFPRegsRegClassID, // D24
1258 SP::DFPRegsRegClassID, // D25
1259 SP::DFPRegsRegClassID, // D26
1260 SP::DFPRegsRegClassID, // D27
1261 SP::DFPRegsRegClassID, // D28
1262 SP::DFPRegsRegClassID, // D29
1263 SP::DFPRegsRegClassID, // D30
1264 SP::DFPRegsRegClassID, // D31
1265 SP::FPRegsRegClassID, // F0
1266 SP::FPRegsRegClassID, // F1
1267 SP::FPRegsRegClassID, // F2
1268 SP::FPRegsRegClassID, // F3
1269 SP::FPRegsRegClassID, // F4
1270 SP::FPRegsRegClassID, // F5
1271 SP::FPRegsRegClassID, // F6
1272 SP::FPRegsRegClassID, // F7
1273 SP::FPRegsRegClassID, // F8
1274 SP::FPRegsRegClassID, // F9
1275 SP::FPRegsRegClassID, // F10
1276 SP::FPRegsRegClassID, // F11
1277 SP::FPRegsRegClassID, // F12
1278 SP::FPRegsRegClassID, // F13
1279 SP::FPRegsRegClassID, // F14
1280 SP::FPRegsRegClassID, // F15
1281 SP::FPRegsRegClassID, // F16
1282 SP::FPRegsRegClassID, // F17
1283 SP::FPRegsRegClassID, // F18
1284 SP::FPRegsRegClassID, // F19
1285 SP::FPRegsRegClassID, // F20
1286 SP::FPRegsRegClassID, // F21
1287 SP::FPRegsRegClassID, // F22
1288 SP::FPRegsRegClassID, // F23
1289 SP::FPRegsRegClassID, // F24
1290 SP::FPRegsRegClassID, // F25
1291 SP::FPRegsRegClassID, // F26
1292 SP::FPRegsRegClassID, // F27
1293 SP::FPRegsRegClassID, // F28
1294 SP::FPRegsRegClassID, // F29
1295 SP::FPRegsRegClassID, // F30
1296 SP::FPRegsRegClassID, // F31
1297 SP::FCCRegsRegClassID, // FCC0
1298 SP::FCCRegsRegClassID, // FCC1
1299 SP::FCCRegsRegClassID, // FCC2
1300 SP::FCCRegsRegClassID, // FCC3
1301 SP::I64RegsRegClassID, // G0
1302 SP::I64RegsRegClassID, // G1
1303 SP::I64RegsRegClassID, // G2
1304 SP::I64RegsRegClassID, // G3
1305 SP::I64RegsRegClassID, // G4
1306 SP::I64RegsRegClassID, // G5
1307 SP::I64RegsRegClassID, // G6
1308 SP::I64RegsRegClassID, // G7
1309 SP::I64Regs_and_GPRIncomingArgRegClassID, // I0
1310 SP::I64Regs_and_GPRIncomingArgRegClassID, // I1
1311 SP::I64Regs_and_GPRIncomingArgRegClassID, // I2
1312 SP::I64Regs_and_GPRIncomingArgRegClassID, // I3
1313 SP::I64Regs_and_GPRIncomingArgRegClassID, // I4
1314 SP::I64Regs_and_GPRIncomingArgRegClassID, // I5
1315 SP::I64RegsRegClassID, // I6
1316 SP::I64RegsRegClassID, // I7
1317 SP::I64RegsRegClassID, // L0
1318 SP::I64RegsRegClassID, // L1
1319 SP::I64RegsRegClassID, // L2
1320 SP::I64RegsRegClassID, // L3
1321 SP::I64RegsRegClassID, // L4
1322 SP::I64RegsRegClassID, // L5
1323 SP::I64RegsRegClassID, // L6
1324 SP::I64RegsRegClassID, // L7
1325 SP::I64Regs_and_GPROutgoingArgRegClassID, // O0
1326 SP::I64Regs_and_GPROutgoingArgRegClassID, // O1
1327 SP::I64Regs_and_GPROutgoingArgRegClassID, // O2
1328 SP::I64Regs_and_GPROutgoingArgRegClassID, // O3
1329 SP::I64Regs_and_GPROutgoingArgRegClassID, // O4
1330 SP::I64Regs_and_GPROutgoingArgRegClassID, // O5
1331 SP::I64RegsRegClassID, // O6
1332 SP::I64RegsRegClassID, // O7
1333 SP::LowQFPRegsRegClassID, // Q0
1334 SP::LowQFPRegsRegClassID, // Q1
1335 SP::LowQFPRegsRegClassID, // Q2
1336 SP::LowQFPRegsRegClassID, // Q3
1337 SP::LowQFPRegsRegClassID, // Q4
1338 SP::LowQFPRegsRegClassID, // Q5
1339 SP::LowQFPRegsRegClassID, // Q6
1340 SP::LowQFPRegsRegClassID, // Q7
1341 SP::QFPRegsRegClassID, // Q8
1342 SP::QFPRegsRegClassID, // Q9
1343 SP::QFPRegsRegClassID, // Q10
1344 SP::QFPRegsRegClassID, // Q11
1345 SP::QFPRegsRegClassID, // Q12
1346 SP::QFPRegsRegClassID, // Q13
1347 SP::QFPRegsRegClassID, // Q14
1348 SP::QFPRegsRegClassID, // Q15
1349 SP::CoprocPairRegClassID, // C0_C1
1350 SP::CoprocPairRegClassID, // C2_C3
1351 SP::CoprocPairRegClassID, // C4_C5
1352 SP::CoprocPairRegClassID, // C6_C7
1353 SP::CoprocPairRegClassID, // C8_C9
1354 SP::CoprocPairRegClassID, // C10_C11
1355 SP::CoprocPairRegClassID, // C12_C13
1356 SP::CoprocPairRegClassID, // C14_C15
1357 SP::CoprocPairRegClassID, // C16_C17
1358 SP::CoprocPairRegClassID, // C18_C19
1359 SP::CoprocPairRegClassID, // C20_C21
1360 SP::CoprocPairRegClassID, // C22_C23
1361 SP::CoprocPairRegClassID, // C24_C25
1362 SP::CoprocPairRegClassID, // C26_C27
1363 SP::CoprocPairRegClassID, // C28_C29
1364 SP::CoprocPairRegClassID, // C30_C31
1365 SP::IntPairRegClassID, // G0_G1
1366 SP::IntPairRegClassID, // G2_G3
1367 SP::IntPairRegClassID, // G4_G5
1368 SP::IntPairRegClassID, // G6_G7
1369 SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, // I0_I1
1370 SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, // I2_I3
1371 SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, // I4_I5
1372 SP::IntPairRegClassID, // I6_I7
1373 SP::IntPairRegClassID, // L0_L1
1374 SP::IntPairRegClassID, // L2_L3
1375 SP::IntPairRegClassID, // L4_L5
1376 SP::IntPairRegClassID, // L6_L7
1377 SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, // O0_O1
1378 SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, // O2_O3
1379 SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, // O4_O5
1380 SP::IntPairRegClassID, // O6_O7
1381 };
1382
1383 assert(Reg < ArrayRef(Mapping).size());
1384 unsigned RCID = Mapping[Reg.id()];
1385 if (RCID == InvalidRegClassID)
1386 return nullptr;
1387 return SparcRegisterClasses[RCID];
1388}
1389extern const MCRegisterDesc SparcRegDesc[];
1390extern const int16_t SparcRegDiffLists[];
1391extern const LaneBitmask SparcLaneMaskLists[];
1392extern const char SparcRegStrings[];
1393extern const char SparcRegClassStrings[];
1394extern const MCPhysReg SparcRegUnitRoots[][2];
1395extern const uint16_t SparcSubRegIdxLists[];
1396extern const uint16_t SparcRegEncodingTable[];
1397// SP Dwarf<->LLVM register mappings.
1398extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
1399extern const unsigned SPDwarfFlavour0Dwarf2LSize;
1400
1401extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
1402extern const unsigned SPEHFlavour0Dwarf2LSize;
1403
1404extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
1405extern const unsigned SPDwarfFlavour0L2DwarfSize;
1406
1407extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
1408extern const unsigned SPEHFlavour0L2DwarfSize;
1409
1410
1411SparcGenRegisterInfo::
1412SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1413 unsigned PC, unsigned HwMode)
1414 : TargetRegisterInfo(&SparcRegInfoDesc, SparcRegisterClasses,
1415 SparcSubRegIndexStrings, SparcSubRegIndexNameOffsets,
1416 SparcSubRegIdxRangeTable, SparcSubRegIndexLaneMaskTable,
1417
1418 LaneBitmask(0xFFFFFFFFFFFFFFFF), SparcRegClassInfos, SparcVTLists, HwMode) {
1419 InitMCRegisterInfo(D: SparcRegDesc, NR: 238, RA, PC,
1420 C: SparcMCRegisterClasses, NC: 20, RURoots: SparcRegUnitRoots, NRU: 173, DL: SparcRegDiffLists,
1421 RUMS: SparcLaneMaskLists, Strings: SparcRegStrings, ClassStrings: SparcRegClassStrings, SubIndices: SparcSubRegIdxLists, NumIndices: 7,
1422 RET: SparcRegEncodingTable, RUI: nullptr);
1423
1424 switch (DwarfFlavour) {
1425 default:
1426 llvm_unreachable("Unknown DWARF flavour");
1427 case 0:
1428 mapDwarfRegsToLLVMRegs(Map: SPDwarfFlavour0Dwarf2L, Size: SPDwarfFlavour0Dwarf2LSize, isEH: false);
1429 break;
1430 }
1431 switch (EHFlavour) {
1432 default:
1433 llvm_unreachable("Unknown DWARF flavour");
1434 case 0:
1435 mapDwarfRegsToLLVMRegs(Map: SPEHFlavour0Dwarf2L, Size: SPEHFlavour0Dwarf2LSize, isEH: true);
1436 break;
1437 }
1438 switch (DwarfFlavour) {
1439 default:
1440 llvm_unreachable("Unknown DWARF flavour");
1441 case 0:
1442 mapLLVMRegsToDwarfRegs(Map: SPDwarfFlavour0L2Dwarf, Size: SPDwarfFlavour0L2DwarfSize, isEH: false);
1443 break;
1444 }
1445 switch (EHFlavour) {
1446 default:
1447 llvm_unreachable("Unknown DWARF flavour");
1448 case 0:
1449 mapLLVMRegsToDwarfRegs(Map: SPEHFlavour0L2Dwarf, Size: SPEHFlavour0L2DwarfSize, isEH: true);
1450 break;
1451 }
1452}
1453
1454static const MCPhysReg CSR_SaveList[] = { 0 };
1455static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x103fffc0, 0x00000000, 0x000003fc, };
1456static const MCPhysReg RTCSR_SaveList[] = { 0 };
1457static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00003000, 0x00000000, 0x00000020, };
1458
1459
1460ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
1461 static const uint32_t *const Masks[] = {
1462 CSR_RegMask,
1463 RTCSR_RegMask,
1464 };
1465 return ArrayRef(Masks);
1466}
1467
1468bool SparcGenRegisterInfo::
1469isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1470 return
1471 false;
1472}
1473
1474bool SparcGenRegisterInfo::
1475isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1476 return
1477 false;
1478}
1479
1480bool SparcGenRegisterInfo::
1481isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1482 return
1483 false;
1484}
1485
1486bool SparcGenRegisterInfo::
1487isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1488 return
1489 false;
1490}
1491
1492bool SparcGenRegisterInfo::
1493isConstantPhysReg(MCRegister PhysReg) const {
1494 return
1495 PhysReg == SP::G0 ||
1496 false;
1497}
1498
1499ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
1500 static const char *Names[] = {
1501 "CSR",
1502 "RTCSR",
1503 };
1504 return ArrayRef(Names);
1505}
1506
1507const SparcFrameLowering *
1508SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1509 return static_cast<const SparcFrameLowering *>(
1510 MF.getSubtarget().getFrameLowering());
1511}
1512
1513
1514} // namespace llvm
1515