1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SparcMCRegisterClasses[];
12
13static const MVT::SimpleValueType SparcVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i32, MVT::i64, MVT::Other,
17 /* 7 */ MVT::f32, MVT::Other,
18 /* 9 */ MVT::f64, MVT::Other,
19 /* 11 */ MVT::f128, MVT::Other,
20 /* 13 */ MVT::v2i32, MVT::Other,
21};
22
23#ifdef __GNUC__
24#pragma GCC diagnostic push
25#pragma GCC diagnostic ignored "-Woverlength-strings"
26#endif
27static constexpr char SparcSubRegIndexStrings[] = {
28 /* 0 */ "sub_odd64\000"
29 /* 10 */ "sub_even64\000"
30 /* 21 */ "sub_odd64_then_sub_odd\000"
31 /* 44 */ "sub_odd64_then_sub_even\000"
32};
33#ifdef __GNUC__
34#pragma GCC diagnostic pop
35#endif
36
37
38static constexpr uint32_t SparcSubRegIndexNameOffsets[] = {
39 59,
40 10,
41 36,
42 0,
43 44,
44 21,
45};
46
47static const TargetRegisterInfo::SubRegCoveredBits SparcSubRegIdxRangeTable[] = {
48 { .Offset: 65535, .Size: 65535 },
49 { .Offset: 0, .Size: 32 }, // sub_even
50 { .Offset: 0, .Size: 64 }, // sub_even64
51 { .Offset: 32, .Size: 32 }, // sub_odd
52 { .Offset: 64, .Size: 64 }, // sub_odd64
53 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
54 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
55 { .Offset: 65535, .Size: 65535 },
56 { .Offset: 0, .Size: 32 }, // sub_even
57 { .Offset: 0, .Size: 64 }, // sub_even64
58 { .Offset: 32, .Size: 32 }, // sub_odd
59 { .Offset: 64, .Size: 64 }, // sub_odd64
60 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
61 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
62};
63
64
65static const LaneBitmask SparcSubRegIndexLaneMaskTable[] = {
66 LaneBitmask::getAll(),
67 LaneBitmask(0x0000000000000001), // sub_even
68 LaneBitmask(0x0000000000000003), // sub_even64
69 LaneBitmask(0x0000000000000002), // sub_odd
70 LaneBitmask(0x000000000000000C), // sub_odd64
71 LaneBitmask(0x0000000000000004), // sub_odd64_then_sub_even
72 LaneBitmask(0x0000000000000008), // sub_odd64_then_sub_odd
73 };
74
75
76
77static const TargetRegisterInfo::RegClassInfo SparcRegClassInfos[] = {
78 // Mode = 0 (DefaultMode)
79 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*SparcVTLists+*/.VTListOffset: 0 }, // FCCRegs
80 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // ASRRegs
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // CoprocRegs
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 7 }, // FPRegs
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // IntRegs
84 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
85 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
86 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // DFPRegs
87 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs
88 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs
89 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // CoprocPair
90 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair
91 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // LowDFPRegs
92 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
93 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
94 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
95 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
96 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
97 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // QFPRegs
98 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // LowQFPRegs
99 // Mode = 1 (SPARC64)
100 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*SparcVTLists+*/.VTListOffset: 0 }, // FCCRegs
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // ASRRegs
102 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // CoprocRegs
103 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 7 }, // FPRegs
104 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // IntRegs
105 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
106 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // DFPRegs
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs
110 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // CoprocPair
111 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair
112 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // LowDFPRegs
113 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
114 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
115 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
116 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
117 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
118 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // QFPRegs
119 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // LowQFPRegs
120};
121static const uint32_t FCCRegsSubClassMask[] = {
122 0x00000001,
123};
124
125static const uint32_t ASRRegsSubClassMask[] = {
126 0x00020002,
127};
128
129static const uint32_t CoprocRegsSubClassMask[] = {
130 0x00000004,
131 0x00000400, // sub_even
132 0x00000400, // sub_odd
133};
134
135static const uint32_t FPRegsSubClassMask[] = {
136 0x00000008,
137 0x00081000, // sub_even
138 0x00081000, // sub_odd
139 0x00080000, // sub_odd64_then_sub_even
140 0x00080000, // sub_odd64_then_sub_odd
141};
142
143static const uint32_t IntRegsSubClassMask[] = {
144 0x00006170,
145 0x00018800, // sub_even
146 0x00018800, // sub_odd
147};
148
149static const uint32_t GPRIncomingArgSubClassMask[] = {
150 0x00002020,
151 0x00008000, // sub_even
152 0x00008000, // sub_odd
153};
154
155static const uint32_t GPROutgoingArgSubClassMask[] = {
156 0x00004040,
157 0x00010000, // sub_even
158 0x00010000, // sub_odd
159};
160
161static const uint32_t DFPRegsSubClassMask[] = {
162 0x00001080,
163 0x000c0000, // sub_even64
164 0x000c0000, // sub_odd64
165};
166
167static const uint32_t I64RegsSubClassMask[] = {
168 0x00006100,
169 0x00018800, // sub_even
170 0x00018800, // sub_odd
171};
172
173static const uint32_t PRRegsSubClassMask[] = {
174 0x00020200,
175};
176
177static const uint32_t CoprocPairSubClassMask[] = {
178 0x00000400,
179};
180
181static const uint32_t IntPairSubClassMask[] = {
182 0x00018800,
183};
184
185static const uint32_t LowDFPRegsSubClassMask[] = {
186 0x00001000,
187 0x00080000, // sub_even64
188 0x00080000, // sub_odd64
189};
190
191static const uint32_t I64Regs_and_GPRIncomingArgSubClassMask[] = {
192 0x00002000,
193 0x00008000, // sub_even
194 0x00008000, // sub_odd
195};
196
197static const uint32_t I64Regs_and_GPROutgoingArgSubClassMask[] = {
198 0x00004000,
199 0x00010000, // sub_even
200 0x00010000, // sub_odd
201};
202
203static const uint32_t IntPair_with_sub_even_in_GPRIncomingArgSubClassMask[] = {
204 0x00008000,
205};
206
207static const uint32_t IntPair_with_sub_even_in_GPROutgoingArgSubClassMask[] = {
208 0x00010000,
209};
210
211static const uint32_t PRRegs_and_ASRRegsSubClassMask[] = {
212 0x00020000,
213};
214
215static const uint32_t QFPRegsSubClassMask[] = {
216 0x000c0000,
217};
218
219static const uint32_t LowQFPRegsSubClassMask[] = {
220 0x00080000,
221};
222
223static const uint16_t SuperRegIdxSeqs[] = {
224 /* 0 */ 1, 3, 0,
225 /* 3 */ 2, 4, 0,
226 /* 6 */ 1, 3, 5, 6, 0,
227};
228
229static unsigned const GPRIncomingArgSuperclasses[] = {
230 SP::IntRegsRegClassID,
231};
232
233static unsigned const GPROutgoingArgSuperclasses[] = {
234 SP::IntRegsRegClassID,
235};
236
237static unsigned const I64RegsSuperclasses[] = {
238 SP::IntRegsRegClassID,
239};
240
241static unsigned const LowDFPRegsSuperclasses[] = {
242 SP::DFPRegsRegClassID,
243};
244
245static unsigned const I64Regs_and_GPRIncomingArgSuperclasses[] = {
246 SP::IntRegsRegClassID,
247 SP::GPRIncomingArgRegClassID,
248 SP::I64RegsRegClassID,
249};
250
251static unsigned const I64Regs_and_GPROutgoingArgSuperclasses[] = {
252 SP::IntRegsRegClassID,
253 SP::GPROutgoingArgRegClassID,
254 SP::I64RegsRegClassID,
255};
256
257static unsigned const IntPair_with_sub_even_in_GPRIncomingArgSuperclasses[] = {
258 SP::IntPairRegClassID,
259};
260
261static unsigned const IntPair_with_sub_even_in_GPROutgoingArgSuperclasses[] = {
262 SP::IntPairRegClassID,
263};
264
265static unsigned const PRRegs_and_ASRRegsSuperclasses[] = {
266 SP::ASRRegsRegClassID,
267 SP::PRRegsRegClassID,
268};
269
270static unsigned const LowQFPRegsSuperclasses[] = {
271 SP::QFPRegsRegClassID,
272};
273
274namespace SP {
275
276// Register class instances.
277 extern const TargetRegisterClass FCCRegsRegClass = {
278 .MC: &SparcMCRegisterClasses[FCCRegsRegClassID],
279 .SubClassMask: FCCRegsSubClassMask,
280 .SuperRegIndices: SuperRegIdxSeqs + 2,
281 .LaneMask: LaneBitmask(0x0000000000000001),
282 .AllocationPriority: 0,
283 .GlobalPriority: false,
284 .TSFlags: 0x00, /* TSFlags */
285 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
286 .CoveredBySubRegs: false, /* CoveredBySubRegs */
287 .SuperClasses: nullptr, .SuperClassesSize: 0,
288 .OrderFunc: nullptr
289 };
290
291 extern const TargetRegisterClass ASRRegsRegClass = {
292 .MC: &SparcMCRegisterClasses[ASRRegsRegClassID],
293 .SubClassMask: ASRRegsSubClassMask,
294 .SuperRegIndices: SuperRegIdxSeqs + 2,
295 .LaneMask: LaneBitmask(0x0000000000000001),
296 .AllocationPriority: 0,
297 .GlobalPriority: false,
298 .TSFlags: 0x00, /* TSFlags */
299 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
300 .CoveredBySubRegs: false, /* CoveredBySubRegs */
301 .SuperClasses: nullptr, .SuperClassesSize: 0,
302 .OrderFunc: nullptr
303 };
304
305 extern const TargetRegisterClass CoprocRegsRegClass = {
306 .MC: &SparcMCRegisterClasses[CoprocRegsRegClassID],
307 .SubClassMask: CoprocRegsSubClassMask,
308 .SuperRegIndices: SuperRegIdxSeqs + 0,
309 .LaneMask: LaneBitmask(0x0000000000000001),
310 .AllocationPriority: 0,
311 .GlobalPriority: false,
312 .TSFlags: 0x00, /* TSFlags */
313 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
314 .CoveredBySubRegs: false, /* CoveredBySubRegs */
315 .SuperClasses: nullptr, .SuperClassesSize: 0,
316 .OrderFunc: nullptr
317 };
318
319 extern const TargetRegisterClass FPRegsRegClass = {
320 .MC: &SparcMCRegisterClasses[FPRegsRegClassID],
321 .SubClassMask: FPRegsSubClassMask,
322 .SuperRegIndices: SuperRegIdxSeqs + 6,
323 .LaneMask: LaneBitmask(0x0000000000000001),
324 .AllocationPriority: 0,
325 .GlobalPriority: false,
326 .TSFlags: 0x00, /* TSFlags */
327 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
328 .CoveredBySubRegs: false, /* CoveredBySubRegs */
329 .SuperClasses: nullptr, .SuperClassesSize: 0,
330 .OrderFunc: nullptr
331 };
332
333 extern const TargetRegisterClass IntRegsRegClass = {
334 .MC: &SparcMCRegisterClasses[IntRegsRegClassID],
335 .SubClassMask: IntRegsSubClassMask,
336 .SuperRegIndices: SuperRegIdxSeqs + 0,
337 .LaneMask: LaneBitmask(0x0000000000000001),
338 .AllocationPriority: 0,
339 .GlobalPriority: false,
340 .TSFlags: 0x00, /* TSFlags */
341 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
342 .CoveredBySubRegs: false, /* CoveredBySubRegs */
343 .SuperClasses: nullptr, .SuperClassesSize: 0,
344 .OrderFunc: nullptr
345 };
346
347 extern const TargetRegisterClass GPRIncomingArgRegClass = {
348 .MC: &SparcMCRegisterClasses[GPRIncomingArgRegClassID],
349 .SubClassMask: GPRIncomingArgSubClassMask,
350 .SuperRegIndices: SuperRegIdxSeqs + 0,
351 .LaneMask: LaneBitmask(0x0000000000000001),
352 .AllocationPriority: 0,
353 .GlobalPriority: false,
354 .TSFlags: 0x00, /* TSFlags */
355 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
356 .CoveredBySubRegs: false, /* CoveredBySubRegs */
357 .SuperClasses: GPRIncomingArgSuperclasses, .SuperClassesSize: 1,
358 .OrderFunc: nullptr
359 };
360
361 extern const TargetRegisterClass GPROutgoingArgRegClass = {
362 .MC: &SparcMCRegisterClasses[GPROutgoingArgRegClassID],
363 .SubClassMask: GPROutgoingArgSubClassMask,
364 .SuperRegIndices: SuperRegIdxSeqs + 0,
365 .LaneMask: LaneBitmask(0x0000000000000001),
366 .AllocationPriority: 0,
367 .GlobalPriority: false,
368 .TSFlags: 0x00, /* TSFlags */
369 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
370 .CoveredBySubRegs: false, /* CoveredBySubRegs */
371 .SuperClasses: GPROutgoingArgSuperclasses, .SuperClassesSize: 1,
372 .OrderFunc: nullptr
373 };
374
375 extern const TargetRegisterClass DFPRegsRegClass = {
376 .MC: &SparcMCRegisterClasses[DFPRegsRegClassID],
377 .SubClassMask: DFPRegsSubClassMask,
378 .SuperRegIndices: SuperRegIdxSeqs + 3,
379 .LaneMask: LaneBitmask(0x0000000000000003),
380 .AllocationPriority: 0,
381 .GlobalPriority: false,
382 .TSFlags: 0x00, /* TSFlags */
383 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
384 .CoveredBySubRegs: false, /* CoveredBySubRegs */
385 .SuperClasses: nullptr, .SuperClassesSize: 0,
386 .OrderFunc: nullptr
387 };
388
389 extern const TargetRegisterClass I64RegsRegClass = {
390 .MC: &SparcMCRegisterClasses[I64RegsRegClassID],
391 .SubClassMask: I64RegsSubClassMask,
392 .SuperRegIndices: SuperRegIdxSeqs + 0,
393 .LaneMask: LaneBitmask(0x0000000000000001),
394 .AllocationPriority: 0,
395 .GlobalPriority: false,
396 .TSFlags: 0x00, /* TSFlags */
397 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
398 .CoveredBySubRegs: false, /* CoveredBySubRegs */
399 .SuperClasses: I64RegsSuperclasses, .SuperClassesSize: 1,
400 .OrderFunc: nullptr
401 };
402
403 extern const TargetRegisterClass PRRegsRegClass = {
404 .MC: &SparcMCRegisterClasses[PRRegsRegClassID],
405 .SubClassMask: PRRegsSubClassMask,
406 .SuperRegIndices: SuperRegIdxSeqs + 2,
407 .LaneMask: LaneBitmask(0x0000000000000001),
408 .AllocationPriority: 0,
409 .GlobalPriority: false,
410 .TSFlags: 0x00, /* TSFlags */
411 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
412 .CoveredBySubRegs: false, /* CoveredBySubRegs */
413 .SuperClasses: nullptr, .SuperClassesSize: 0,
414 .OrderFunc: nullptr
415 };
416
417 extern const TargetRegisterClass CoprocPairRegClass = {
418 .MC: &SparcMCRegisterClasses[CoprocPairRegClassID],
419 .SubClassMask: CoprocPairSubClassMask,
420 .SuperRegIndices: SuperRegIdxSeqs + 2,
421 .LaneMask: LaneBitmask(0x0000000000000003),
422 .AllocationPriority: 0,
423 .GlobalPriority: false,
424 .TSFlags: 0x00, /* TSFlags */
425 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
426 .CoveredBySubRegs: true, /* CoveredBySubRegs */
427 .SuperClasses: nullptr, .SuperClassesSize: 0,
428 .OrderFunc: nullptr
429 };
430
431 extern const TargetRegisterClass IntPairRegClass = {
432 .MC: &SparcMCRegisterClasses[IntPairRegClassID],
433 .SubClassMask: IntPairSubClassMask,
434 .SuperRegIndices: SuperRegIdxSeqs + 2,
435 .LaneMask: LaneBitmask(0x0000000000000003),
436 .AllocationPriority: 0,
437 .GlobalPriority: false,
438 .TSFlags: 0x00, /* TSFlags */
439 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
440 .CoveredBySubRegs: true, /* CoveredBySubRegs */
441 .SuperClasses: nullptr, .SuperClassesSize: 0,
442 .OrderFunc: nullptr
443 };
444
445 extern const TargetRegisterClass LowDFPRegsRegClass = {
446 .MC: &SparcMCRegisterClasses[LowDFPRegsRegClassID],
447 .SubClassMask: LowDFPRegsSubClassMask,
448 .SuperRegIndices: SuperRegIdxSeqs + 3,
449 .LaneMask: LaneBitmask(0x0000000000000003),
450 .AllocationPriority: 0,
451 .GlobalPriority: false,
452 .TSFlags: 0x00, /* TSFlags */
453 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
454 .CoveredBySubRegs: true, /* CoveredBySubRegs */
455 .SuperClasses: LowDFPRegsSuperclasses, .SuperClassesSize: 1,
456 .OrderFunc: nullptr
457 };
458
459 extern const TargetRegisterClass I64Regs_and_GPRIncomingArgRegClass = {
460 .MC: &SparcMCRegisterClasses[I64Regs_and_GPRIncomingArgRegClassID],
461 .SubClassMask: I64Regs_and_GPRIncomingArgSubClassMask,
462 .SuperRegIndices: SuperRegIdxSeqs + 0,
463 .LaneMask: LaneBitmask(0x0000000000000001),
464 .AllocationPriority: 0,
465 .GlobalPriority: false,
466 .TSFlags: 0x00, /* TSFlags */
467 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
468 .CoveredBySubRegs: false, /* CoveredBySubRegs */
469 .SuperClasses: I64Regs_and_GPRIncomingArgSuperclasses, .SuperClassesSize: 3,
470 .OrderFunc: nullptr
471 };
472
473 extern const TargetRegisterClass I64Regs_and_GPROutgoingArgRegClass = {
474 .MC: &SparcMCRegisterClasses[I64Regs_and_GPROutgoingArgRegClassID],
475 .SubClassMask: I64Regs_and_GPROutgoingArgSubClassMask,
476 .SuperRegIndices: SuperRegIdxSeqs + 0,
477 .LaneMask: LaneBitmask(0x0000000000000001),
478 .AllocationPriority: 0,
479 .GlobalPriority: false,
480 .TSFlags: 0x00, /* TSFlags */
481 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
482 .CoveredBySubRegs: false, /* CoveredBySubRegs */
483 .SuperClasses: I64Regs_and_GPROutgoingArgSuperclasses, .SuperClassesSize: 3,
484 .OrderFunc: nullptr
485 };
486
487 extern const TargetRegisterClass IntPair_with_sub_even_in_GPRIncomingArgRegClass = {
488 .MC: &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPRIncomingArgRegClassID],
489 .SubClassMask: IntPair_with_sub_even_in_GPRIncomingArgSubClassMask,
490 .SuperRegIndices: SuperRegIdxSeqs + 2,
491 .LaneMask: LaneBitmask(0x0000000000000003),
492 .AllocationPriority: 0,
493 .GlobalPriority: false,
494 .TSFlags: 0x00, /* TSFlags */
495 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
496 .CoveredBySubRegs: true, /* CoveredBySubRegs */
497 .SuperClasses: IntPair_with_sub_even_in_GPRIncomingArgSuperclasses, .SuperClassesSize: 1,
498 .OrderFunc: nullptr
499 };
500
501 extern const TargetRegisterClass IntPair_with_sub_even_in_GPROutgoingArgRegClass = {
502 .MC: &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPROutgoingArgRegClassID],
503 .SubClassMask: IntPair_with_sub_even_in_GPROutgoingArgSubClassMask,
504 .SuperRegIndices: SuperRegIdxSeqs + 2,
505 .LaneMask: LaneBitmask(0x0000000000000003),
506 .AllocationPriority: 0,
507 .GlobalPriority: false,
508 .TSFlags: 0x00, /* TSFlags */
509 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
510 .CoveredBySubRegs: true, /* CoveredBySubRegs */
511 .SuperClasses: IntPair_with_sub_even_in_GPROutgoingArgSuperclasses, .SuperClassesSize: 1,
512 .OrderFunc: nullptr
513 };
514
515 extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass = {
516 .MC: &SparcMCRegisterClasses[PRRegs_and_ASRRegsRegClassID],
517 .SubClassMask: PRRegs_and_ASRRegsSubClassMask,
518 .SuperRegIndices: SuperRegIdxSeqs + 2,
519 .LaneMask: LaneBitmask(0x0000000000000001),
520 .AllocationPriority: 0,
521 .GlobalPriority: false,
522 .TSFlags: 0x00, /* TSFlags */
523 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
524 .CoveredBySubRegs: false, /* CoveredBySubRegs */
525 .SuperClasses: PRRegs_and_ASRRegsSuperclasses, .SuperClassesSize: 2,
526 .OrderFunc: nullptr
527 };
528
529 extern const TargetRegisterClass QFPRegsRegClass = {
530 .MC: &SparcMCRegisterClasses[QFPRegsRegClassID],
531 .SubClassMask: QFPRegsSubClassMask,
532 .SuperRegIndices: SuperRegIdxSeqs + 2,
533 .LaneMask: LaneBitmask(0x000000000000000F),
534 .AllocationPriority: 0,
535 .GlobalPriority: false,
536 .TSFlags: 0x00, /* TSFlags */
537 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
538 .CoveredBySubRegs: true, /* CoveredBySubRegs */
539 .SuperClasses: nullptr, .SuperClassesSize: 0,
540 .OrderFunc: nullptr
541 };
542
543 extern const TargetRegisterClass LowQFPRegsRegClass = {
544 .MC: &SparcMCRegisterClasses[LowQFPRegsRegClassID],
545 .SubClassMask: LowQFPRegsSubClassMask,
546 .SuperRegIndices: SuperRegIdxSeqs + 2,
547 .LaneMask: LaneBitmask(0x000000000000000F),
548 .AllocationPriority: 0,
549 .GlobalPriority: false,
550 .TSFlags: 0x00, /* TSFlags */
551 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
552 .CoveredBySubRegs: true, /* CoveredBySubRegs */
553 .SuperClasses: LowQFPRegsSuperclasses, .SuperClassesSize: 1,
554 .OrderFunc: nullptr
555 };
556
557
558} // namespace SP
559static const TargetRegisterClass *const SparcRegisterClasses[] = {
560 &SP::FCCRegsRegClass,
561 &SP::ASRRegsRegClass,
562 &SP::CoprocRegsRegClass,
563 &SP::FPRegsRegClass,
564 &SP::IntRegsRegClass,
565 &SP::GPRIncomingArgRegClass,
566 &SP::GPROutgoingArgRegClass,
567 &SP::DFPRegsRegClass,
568 &SP::I64RegsRegClass,
569 &SP::PRRegsRegClass,
570 &SP::CoprocPairRegClass,
571 &SP::IntPairRegClass,
572 &SP::LowDFPRegsRegClass,
573 &SP::I64Regs_and_GPRIncomingArgRegClass,
574 &SP::I64Regs_and_GPROutgoingArgRegClass,
575 &SP::IntPair_with_sub_even_in_GPRIncomingArgRegClass,
576 &SP::IntPair_with_sub_even_in_GPROutgoingArgRegClass,
577 &SP::PRRegs_and_ASRRegsRegClass,
578 &SP::QFPRegsRegClass,
579 &SP::LowQFPRegsRegClass,
580 };
581
582static const uint8_t SparcCostPerUseTable[] = {
5830, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
584
585
586static const bool SparcInAllocatableClassTable[] = {
587false, true, true, true, false, false, true, false, false, true, false, true, true, false, true, true, false, true, true, true, true, true, true, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
588
589
590static const TargetRegisterInfoDesc SparcRegInfoDesc = { // Extra Descriptors
591.CostPerUse: SparcCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SparcInAllocatableClassTable};
592
593unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
594 static const uint8_t RowMap[6] = {
595 0, 0, 0, 1, 0, 0,
596 };
597 static const uint8_t Rows[2][6] = {
598 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
599 { SP::sub_odd64_then_sub_even, 0, SP::sub_odd64_then_sub_odd, 0, 0, 0, },
600 };
601
602 --IdxA; assert(IdxA < 6); (void) IdxA;
603 --IdxB; assert(IdxB < 6);
604 return Rows[RowMap[IdxA]][IdxB];
605}
606
607unsigned SparcGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
608 static const uint8_t Table[6][6] = {
609 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
610 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
611 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
612 { 0, 0, 0, 0, SP::sub_even, SP::sub_odd, },
613 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
614 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
615 };
616
617 --IdxA; assert(IdxA < 6);
618 --IdxB; assert(IdxB < 6);
619 return Table[IdxA][IdxB];
620 }
621
622 struct MaskRolOp {
623 LaneBitmask Mask;
624 uint8_t RotateLeft;
625 };
626 static const MaskRolOp LaneMaskComposeSequences[] = {
627 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
628 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
629 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
630 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 6
631 };
632 static const uint8_t CompositeSequences[] = {
633 0, // to sub_even
634 0, // to sub_even64
635 2, // to sub_odd
636 4, // to sub_odd64
637 4, // to sub_odd64_then_sub_even
638 6 // to sub_odd64_then_sub_odd
639 };
640
641LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
642 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
643 LaneBitmask Result;
644 for (const MaskRolOp *Ops =
645 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
646 Ops->Mask.any(); ++Ops) {
647 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
648 if (unsigned S = Ops->RotateLeft)
649 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
650 else
651 Result |= LaneBitmask(M);
652 }
653 return Result;
654}
655
656LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
657 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
658 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
659 LaneBitmask Result;
660 for (const MaskRolOp *Ops =
661 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
662 Ops->Mask.any(); ++Ops) {
663 LaneBitmask::Type M = LaneMask.getAsInteger();
664 if (unsigned S = Ops->RotateLeft)
665 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
666 else
667 Result |= LaneBitmask(M);
668 }
669 return Result;
670}
671
672const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
673 static constexpr uint8_t Table[20][6] = {
674 { // FCCRegs
675 0, // sub_even
676 0, // sub_even64
677 0, // sub_odd
678 0, // sub_odd64
679 0, // sub_odd64_then_sub_even
680 0, // sub_odd64_then_sub_odd
681 },
682 { // ASRRegs
683 0, // sub_even
684 0, // sub_even64
685 0, // sub_odd
686 0, // sub_odd64
687 0, // sub_odd64_then_sub_even
688 0, // sub_odd64_then_sub_odd
689 },
690 { // CoprocRegs
691 0, // sub_even
692 0, // sub_even64
693 0, // sub_odd
694 0, // sub_odd64
695 0, // sub_odd64_then_sub_even
696 0, // sub_odd64_then_sub_odd
697 },
698 { // FPRegs
699 0, // sub_even
700 0, // sub_even64
701 0, // sub_odd
702 0, // sub_odd64
703 0, // sub_odd64_then_sub_even
704 0, // sub_odd64_then_sub_odd
705 },
706 { // IntRegs
707 0, // sub_even
708 0, // sub_even64
709 0, // sub_odd
710 0, // sub_odd64
711 0, // sub_odd64_then_sub_even
712 0, // sub_odd64_then_sub_odd
713 },
714 { // GPRIncomingArg
715 0, // sub_even
716 0, // sub_even64
717 0, // sub_odd
718 0, // sub_odd64
719 0, // sub_odd64_then_sub_even
720 0, // sub_odd64_then_sub_odd
721 },
722 { // GPROutgoingArg
723 0, // sub_even
724 0, // sub_even64
725 0, // sub_odd
726 0, // sub_odd64
727 0, // sub_odd64_then_sub_even
728 0, // sub_odd64_then_sub_odd
729 },
730 { // DFPRegs
731 13, // sub_even -> LowDFPRegs
732 0, // sub_even64
733 13, // sub_odd -> LowDFPRegs
734 0, // sub_odd64
735 0, // sub_odd64_then_sub_even
736 0, // sub_odd64_then_sub_odd
737 },
738 { // I64Regs
739 0, // sub_even
740 0, // sub_even64
741 0, // sub_odd
742 0, // sub_odd64
743 0, // sub_odd64_then_sub_even
744 0, // sub_odd64_then_sub_odd
745 },
746 { // PRRegs
747 0, // sub_even
748 0, // sub_even64
749 0, // sub_odd
750 0, // sub_odd64
751 0, // sub_odd64_then_sub_even
752 0, // sub_odd64_then_sub_odd
753 },
754 { // CoprocPair
755 11, // sub_even -> CoprocPair
756 0, // sub_even64
757 11, // sub_odd -> CoprocPair
758 0, // sub_odd64
759 0, // sub_odd64_then_sub_even
760 0, // sub_odd64_then_sub_odd
761 },
762 { // IntPair
763 12, // sub_even -> IntPair
764 0, // sub_even64
765 12, // sub_odd -> IntPair
766 0, // sub_odd64
767 0, // sub_odd64_then_sub_even
768 0, // sub_odd64_then_sub_odd
769 },
770 { // LowDFPRegs
771 13, // sub_even -> LowDFPRegs
772 0, // sub_even64
773 13, // sub_odd -> LowDFPRegs
774 0, // sub_odd64
775 0, // sub_odd64_then_sub_even
776 0, // sub_odd64_then_sub_odd
777 },
778 { // I64Regs_and_GPRIncomingArg
779 0, // sub_even
780 0, // sub_even64
781 0, // sub_odd
782 0, // sub_odd64
783 0, // sub_odd64_then_sub_even
784 0, // sub_odd64_then_sub_odd
785 },
786 { // I64Regs_and_GPROutgoingArg
787 0, // sub_even
788 0, // sub_even64
789 0, // sub_odd
790 0, // sub_odd64
791 0, // sub_odd64_then_sub_even
792 0, // sub_odd64_then_sub_odd
793 },
794 { // IntPair_with_sub_even_in_GPRIncomingArg
795 16, // sub_even -> IntPair_with_sub_even_in_GPRIncomingArg
796 0, // sub_even64
797 16, // sub_odd -> IntPair_with_sub_even_in_GPRIncomingArg
798 0, // sub_odd64
799 0, // sub_odd64_then_sub_even
800 0, // sub_odd64_then_sub_odd
801 },
802 { // IntPair_with_sub_even_in_GPROutgoingArg
803 17, // sub_even -> IntPair_with_sub_even_in_GPROutgoingArg
804 0, // sub_even64
805 17, // sub_odd -> IntPair_with_sub_even_in_GPROutgoingArg
806 0, // sub_odd64
807 0, // sub_odd64_then_sub_even
808 0, // sub_odd64_then_sub_odd
809 },
810 { // PRRegs_and_ASRRegs
811 0, // sub_even
812 0, // sub_even64
813 0, // sub_odd
814 0, // sub_odd64
815 0, // sub_odd64_then_sub_even
816 0, // sub_odd64_then_sub_odd
817 },
818 { // QFPRegs
819 20, // sub_even -> LowQFPRegs
820 19, // sub_even64 -> QFPRegs
821 20, // sub_odd -> LowQFPRegs
822 19, // sub_odd64 -> QFPRegs
823 20, // sub_odd64_then_sub_even -> LowQFPRegs
824 20, // sub_odd64_then_sub_odd -> LowQFPRegs
825 },
826 { // LowQFPRegs
827 20, // sub_even -> LowQFPRegs
828 20, // sub_even64 -> LowQFPRegs
829 20, // sub_odd -> LowQFPRegs
830 20, // sub_odd64 -> LowQFPRegs
831 20, // sub_odd64_then_sub_even -> LowQFPRegs
832 20, // sub_odd64_then_sub_odd -> LowQFPRegs
833 },
834
835 };
836 assert(RC && "Missing regclass");
837 if (!Idx) return RC;
838 --Idx;
839 assert(Idx < 6 && "Bad subreg");
840 unsigned TV = Table[RC->getID()][Idx];
841 return TV ? getRegClass(i: TV - 1) : nullptr;
842}const TargetRegisterClass *SparcGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
843 static constexpr uint8_t Table[20][6] = {
844 { // FCCRegs
845 0, // FCCRegs:sub_even
846 0, // FCCRegs:sub_even64
847 0, // FCCRegs:sub_odd
848 0, // FCCRegs:sub_odd64
849 0, // FCCRegs:sub_odd64_then_sub_even
850 0, // FCCRegs:sub_odd64_then_sub_odd
851 },
852 { // ASRRegs
853 0, // ASRRegs:sub_even
854 0, // ASRRegs:sub_even64
855 0, // ASRRegs:sub_odd
856 0, // ASRRegs:sub_odd64
857 0, // ASRRegs:sub_odd64_then_sub_even
858 0, // ASRRegs:sub_odd64_then_sub_odd
859 },
860 { // CoprocRegs
861 0, // CoprocRegs:sub_even
862 0, // CoprocRegs:sub_even64
863 0, // CoprocRegs:sub_odd
864 0, // CoprocRegs:sub_odd64
865 0, // CoprocRegs:sub_odd64_then_sub_even
866 0, // CoprocRegs:sub_odd64_then_sub_odd
867 },
868 { // FPRegs
869 0, // FPRegs:sub_even
870 0, // FPRegs:sub_even64
871 0, // FPRegs:sub_odd
872 0, // FPRegs:sub_odd64
873 0, // FPRegs:sub_odd64_then_sub_even
874 0, // FPRegs:sub_odd64_then_sub_odd
875 },
876 { // IntRegs
877 0, // IntRegs:sub_even
878 0, // IntRegs:sub_even64
879 0, // IntRegs:sub_odd
880 0, // IntRegs:sub_odd64
881 0, // IntRegs:sub_odd64_then_sub_even
882 0, // IntRegs:sub_odd64_then_sub_odd
883 },
884 { // GPRIncomingArg
885 0, // GPRIncomingArg:sub_even
886 0, // GPRIncomingArg:sub_even64
887 0, // GPRIncomingArg:sub_odd
888 0, // GPRIncomingArg:sub_odd64
889 0, // GPRIncomingArg:sub_odd64_then_sub_even
890 0, // GPRIncomingArg:sub_odd64_then_sub_odd
891 },
892 { // GPROutgoingArg
893 0, // GPROutgoingArg:sub_even
894 0, // GPROutgoingArg:sub_even64
895 0, // GPROutgoingArg:sub_odd
896 0, // GPROutgoingArg:sub_odd64
897 0, // GPROutgoingArg:sub_odd64_then_sub_even
898 0, // GPROutgoingArg:sub_odd64_then_sub_odd
899 },
900 { // DFPRegs
901 4, // DFPRegs:sub_even -> FPRegs
902 0, // DFPRegs:sub_even64
903 4, // DFPRegs:sub_odd -> FPRegs
904 0, // DFPRegs:sub_odd64
905 0, // DFPRegs:sub_odd64_then_sub_even
906 0, // DFPRegs:sub_odd64_then_sub_odd
907 },
908 { // I64Regs
909 0, // I64Regs:sub_even
910 0, // I64Regs:sub_even64
911 0, // I64Regs:sub_odd
912 0, // I64Regs:sub_odd64
913 0, // I64Regs:sub_odd64_then_sub_even
914 0, // I64Regs:sub_odd64_then_sub_odd
915 },
916 { // PRRegs
917 0, // PRRegs:sub_even
918 0, // PRRegs:sub_even64
919 0, // PRRegs:sub_odd
920 0, // PRRegs:sub_odd64
921 0, // PRRegs:sub_odd64_then_sub_even
922 0, // PRRegs:sub_odd64_then_sub_odd
923 },
924 { // CoprocPair
925 3, // CoprocPair:sub_even -> CoprocRegs
926 0, // CoprocPair:sub_even64
927 3, // CoprocPair:sub_odd -> CoprocRegs
928 0, // CoprocPair:sub_odd64
929 0, // CoprocPair:sub_odd64_then_sub_even
930 0, // CoprocPair:sub_odd64_then_sub_odd
931 },
932 { // IntPair
933 9, // IntPair:sub_even -> I64Regs
934 0, // IntPair:sub_even64
935 9, // IntPair:sub_odd -> I64Regs
936 0, // IntPair:sub_odd64
937 0, // IntPair:sub_odd64_then_sub_even
938 0, // IntPair:sub_odd64_then_sub_odd
939 },
940 { // LowDFPRegs
941 4, // LowDFPRegs:sub_even -> FPRegs
942 0, // LowDFPRegs:sub_even64
943 4, // LowDFPRegs:sub_odd -> FPRegs
944 0, // LowDFPRegs:sub_odd64
945 0, // LowDFPRegs:sub_odd64_then_sub_even
946 0, // LowDFPRegs:sub_odd64_then_sub_odd
947 },
948 { // I64Regs_and_GPRIncomingArg
949 0, // I64Regs_and_GPRIncomingArg:sub_even
950 0, // I64Regs_and_GPRIncomingArg:sub_even64
951 0, // I64Regs_and_GPRIncomingArg:sub_odd
952 0, // I64Regs_and_GPRIncomingArg:sub_odd64
953 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_even
954 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_odd
955 },
956 { // I64Regs_and_GPROutgoingArg
957 0, // I64Regs_and_GPROutgoingArg:sub_even
958 0, // I64Regs_and_GPROutgoingArg:sub_even64
959 0, // I64Regs_and_GPROutgoingArg:sub_odd
960 0, // I64Regs_and_GPROutgoingArg:sub_odd64
961 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_even
962 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_odd
963 },
964 { // IntPair_with_sub_even_in_GPRIncomingArg
965 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even -> I64Regs_and_GPRIncomingArg
966 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even64
967 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd -> I64Regs_and_GPRIncomingArg
968 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64
969 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_even
970 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_odd
971 },
972 { // IntPair_with_sub_even_in_GPROutgoingArg
973 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even -> I64Regs_and_GPROutgoingArg
974 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even64
975 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd -> I64Regs_and_GPROutgoingArg
976 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64
977 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_even
978 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_odd
979 },
980 { // PRRegs_and_ASRRegs
981 0, // PRRegs_and_ASRRegs:sub_even
982 0, // PRRegs_and_ASRRegs:sub_even64
983 0, // PRRegs_and_ASRRegs:sub_odd
984 0, // PRRegs_and_ASRRegs:sub_odd64
985 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_even
986 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_odd
987 },
988 { // QFPRegs
989 4, // QFPRegs:sub_even -> FPRegs
990 8, // QFPRegs:sub_even64 -> DFPRegs
991 4, // QFPRegs:sub_odd -> FPRegs
992 8, // QFPRegs:sub_odd64 -> DFPRegs
993 4, // QFPRegs:sub_odd64_then_sub_even -> FPRegs
994 4, // QFPRegs:sub_odd64_then_sub_odd -> FPRegs
995 },
996 { // LowQFPRegs
997 4, // LowQFPRegs:sub_even -> FPRegs
998 13, // LowQFPRegs:sub_even64 -> LowDFPRegs
999 4, // LowQFPRegs:sub_odd -> FPRegs
1000 13, // LowQFPRegs:sub_odd64 -> LowDFPRegs
1001 4, // LowQFPRegs:sub_odd64_then_sub_even -> FPRegs
1002 4, // LowQFPRegs:sub_odd64_then_sub_odd -> FPRegs
1003 },
1004
1005 };
1006 assert(RC && "Missing regclass");
1007 if (!Idx) return RC;
1008 --Idx;
1009 assert(Idx < 6 && "Bad subreg");
1010 unsigned TV = Table[RC->getID()][Idx];
1011 return TV ? getRegClass(i: TV - 1) : nullptr;
1012}/// Get the weight in units of pressure for this register class.
1013const RegClassWeight &SparcGenRegisterInfo::
1014getRegClassWeight(const TargetRegisterClass *RC) const {
1015 static const RegClassWeight RCWeightTable[] = {
1016 {.RegWeight: 1, .WeightLimit: 4}, // FCCRegs
1017 {.RegWeight: 1, .WeightLimit: 1}, // ASRRegs
1018 {.RegWeight: 0, .WeightLimit: 0}, // CoprocRegs
1019 {.RegWeight: 1, .WeightLimit: 32}, // FPRegs
1020 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
1021 {.RegWeight: 1, .WeightLimit: 6}, // GPRIncomingArg
1022 {.RegWeight: 1, .WeightLimit: 6}, // GPROutgoingArg
1023 {.RegWeight: 2, .WeightLimit: 64}, // DFPRegs
1024 {.RegWeight: 1, .WeightLimit: 32}, // I64Regs
1025 {.RegWeight: 1, .WeightLimit: 17}, // PRRegs
1026 {.RegWeight: 0, .WeightLimit: 0}, // CoprocPair
1027 {.RegWeight: 2, .WeightLimit: 32}, // IntPair
1028 {.RegWeight: 2, .WeightLimit: 32}, // LowDFPRegs
1029 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPRIncomingArg
1030 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPROutgoingArg
1031 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPRIncomingArg
1032 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPROutgoingArg
1033 {.RegWeight: 1, .WeightLimit: 1}, // PRRegs_and_ASRRegs
1034 {.RegWeight: 4, .WeightLimit: 64}, // QFPRegs
1035 {.RegWeight: 4, .WeightLimit: 32}, // LowQFPRegs
1036 };
1037 return RCWeightTable[RC->getID()];
1038}
1039
1040/// Get the weight in units of pressure for this register unit.
1041unsigned SparcGenRegisterInfo::
1042getRegUnitWeight(MCRegUnit RegUnit) const {
1043 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
1044 static const uint8_t RUWeightTable[] = {
1045 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
1046 return RUWeightTable[static_cast<unsigned>(RegUnit)];
1047}
1048
1049
1050// Get the number of dimensions of register pressure.
1051unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
1052 return 8;
1053}
1054
1055// Get the name of this register unit pressure set.
1056const char *SparcGenRegisterInfo::
1057getRegPressureSetName(unsigned Idx) const {
1058 static const char *PressureNameTable[] = {
1059 "PRRegs_and_ASRRegs",
1060 "FCCRegs",
1061 "GPRIncomingArg",
1062 "GPROutgoingArg",
1063 "PRRegs",
1064 "FPRegs",
1065 "IntRegs",
1066 "DFPRegs",
1067 };
1068 return PressureNameTable[Idx];
1069}
1070
1071// Get the register unit pressure limit for this dimension.
1072// This limit must be adjusted dynamically for reserved registers.
1073unsigned SparcGenRegisterInfo::
1074getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1075 static const uint8_t PressureLimitTable[] = {
1076 1, // 0: PRRegs_and_ASRRegs
1077 4, // 1: FCCRegs
1078 6, // 2: GPRIncomingArg
1079 6, // 3: GPROutgoingArg
1080 17, // 4: PRRegs
1081 32, // 5: FPRegs
1082 32, // 6: IntRegs
1083 64, // 7: DFPRegs
1084 };
1085 return PressureLimitTable[Idx];
1086}
1087
1088/// Table of pressure sets per register class or unit.
1089static const int RCSetsTable[] = {
1090 /* 0 */ 1, -1,
1091 /* 2 */ 0, 4, -1,
1092 /* 5 */ 2, 6, -1,
1093 /* 8 */ 3, 6, -1,
1094 /* 11 */ 5, 7, -1,
1095};
1096
1097/// Get the dimensions of register pressure impacted by this register class.
1098/// Returns a -1 terminated array of pressure set IDs
1099const int *SparcGenRegisterInfo::
1100getRegClassPressureSets(const TargetRegisterClass *RC) const {
1101 static const uint8_t RCSetStartTable[] = {
1102 0,1,1,11,6,5,8,12,6,3,1,6,11,5,8,5,8,2,12,11,};
1103 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1104}
1105
1106/// Get the dimensions of register pressure impacted by this register unit.
1107/// Returns a -1 terminated array of pressure set IDs
1108const int *SparcGenRegisterInfo::
1109getRegUnitPressureSets(MCRegUnit RegUnit) const {
1110 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
1111 static const uint8_t RUSetStartTable[] = {
1112 3,3,3,1,1,3,1,1,3,1,3,3,1,3,3,1,2,3,3,3,3,3,3,1,3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,0,0,0,0,6,6,6,6,6,6,6,6,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,8,8,8,8,8,8,6,6,};
1113 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1114}
1115
1116extern const MCRegisterDesc SparcRegDesc[];
1117extern const int16_t SparcRegDiffLists[];
1118extern const LaneBitmask SparcLaneMaskLists[];
1119extern const char SparcRegStrings[];
1120extern const char SparcRegClassStrings[];
1121extern const MCPhysReg SparcRegUnitRoots[][2];
1122extern const uint16_t SparcSubRegIdxLists[];
1123extern const uint16_t SparcRegEncodingTable[];
1124// SP Dwarf<->LLVM register mappings.
1125extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
1126extern const unsigned SPDwarfFlavour0Dwarf2LSize;
1127
1128extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
1129extern const unsigned SPEHFlavour0Dwarf2LSize;
1130
1131extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
1132extern const unsigned SPDwarfFlavour0L2DwarfSize;
1133
1134extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
1135extern const unsigned SPEHFlavour0L2DwarfSize;
1136
1137
1138SparcGenRegisterInfo::
1139SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1140 unsigned PC, unsigned HwMode)
1141 : TargetRegisterInfo(&SparcRegInfoDesc, SparcRegisterClasses,
1142 SparcSubRegIndexStrings, SparcSubRegIndexNameOffsets,
1143 SparcSubRegIdxRangeTable, SparcSubRegIndexLaneMaskTable,
1144
1145 LaneBitmask(0xFFFFFFFFFFFFFFFF), SparcRegClassInfos, SparcVTLists, HwMode) {
1146 InitMCRegisterInfo(D: SparcRegDesc, NR: 238, RA, PC,
1147 C: SparcMCRegisterClasses, NC: 20, RURoots: SparcRegUnitRoots, NRU: 173, DL: SparcRegDiffLists,
1148 RUMS: SparcLaneMaskLists, Strings: SparcRegStrings, ClassStrings: SparcRegClassStrings, SubIndices: SparcSubRegIdxLists, NumIndices: 7,
1149 RET: SparcRegEncodingTable, RUI: nullptr);
1150
1151 switch (DwarfFlavour) {
1152 default:
1153 llvm_unreachable("Unknown DWARF flavour");
1154 case 0:
1155 mapDwarfRegsToLLVMRegs(Map: SPDwarfFlavour0Dwarf2L, Size: SPDwarfFlavour0Dwarf2LSize, isEH: false);
1156 break;
1157 }
1158 switch (EHFlavour) {
1159 default:
1160 llvm_unreachable("Unknown DWARF flavour");
1161 case 0:
1162 mapDwarfRegsToLLVMRegs(Map: SPEHFlavour0Dwarf2L, Size: SPEHFlavour0Dwarf2LSize, isEH: true);
1163 break;
1164 }
1165 switch (DwarfFlavour) {
1166 default:
1167 llvm_unreachable("Unknown DWARF flavour");
1168 case 0:
1169 mapLLVMRegsToDwarfRegs(Map: SPDwarfFlavour0L2Dwarf, Size: SPDwarfFlavour0L2DwarfSize, isEH: false);
1170 break;
1171 }
1172 switch (EHFlavour) {
1173 default:
1174 llvm_unreachable("Unknown DWARF flavour");
1175 case 0:
1176 mapLLVMRegsToDwarfRegs(Map: SPEHFlavour0L2Dwarf, Size: SPEHFlavour0L2DwarfSize, isEH: true);
1177 break;
1178 }
1179}
1180
1181static const MCPhysReg CSR_SaveList[] = { 0 };
1182static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x103fffc0, 0x00000000, 0x000003fc, };
1183static const MCPhysReg RTCSR_SaveList[] = { 0 };
1184static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00003000, 0x00000000, 0x00000020, };
1185
1186
1187ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
1188 static const uint32_t *const Masks[] = {
1189 CSR_RegMask,
1190 RTCSR_RegMask,
1191 };
1192 return ArrayRef(Masks);
1193}
1194
1195bool SparcGenRegisterInfo::
1196isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1197 return
1198 false;
1199}
1200
1201bool SparcGenRegisterInfo::
1202isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1203 return
1204 false;
1205}
1206
1207bool SparcGenRegisterInfo::
1208isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1209 return
1210 false;
1211}
1212
1213bool SparcGenRegisterInfo::
1214isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1215 return
1216 false;
1217}
1218
1219bool SparcGenRegisterInfo::
1220isConstantPhysReg(MCRegister PhysReg) const {
1221 return
1222 PhysReg == SP::G0 ||
1223 false;
1224}
1225
1226ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
1227 static const char *Names[] = {
1228 "CSR",
1229 "RTCSR",
1230 };
1231 return ArrayRef(Names);
1232}
1233
1234const SparcFrameLowering *
1235SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1236 return static_cast<const SparcFrameLowering *>(
1237 MF.getSubtarget().getFrameLowering());
1238}
1239
1240
1241} // namespace llvm
1242