1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<20, 317, 405, 42, 11, 15> SparcMCRegisterClassStorage;
12
13static const MVT::SimpleValueType SparcVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i32, MVT::i64, MVT::Other,
17 /* 7 */ MVT::f32, MVT::Other,
18 /* 9 */ MVT::f64, MVT::Other,
19 /* 11 */ MVT::f128, MVT::Other,
20 /* 13 */ MVT::v2i32, MVT::Other,
21};
22
23#ifdef __GNUC__
24#pragma GCC diagnostic push
25#pragma GCC diagnostic ignored "-Woverlength-strings"
26#endif
27static constexpr char SparcSubRegIndexStrings[] = {
28 /* 0 */ "sub_odd64\000"
29 /* 10 */ "sub_even64\000"
30 /* 21 */ "sub_odd64_then_sub_odd\000"
31 /* 44 */ "sub_odd64_then_sub_even\000"
32};
33#ifdef __GNUC__
34#pragma GCC diagnostic pop
35#endif
36
37
38static constexpr uint32_t SparcSubRegIndexNameOffsets[] = {
39 59,
40 10,
41 36,
42 0,
43 44,
44 21,
45};
46
47static const TargetRegisterInfo::SubRegCoveredBits SparcSubRegIdxRangeTable[] = {
48 { .Offset: 4294967295, .Size: 4294967295 },
49 { .Offset: 0, .Size: 32 }, // sub_even
50 { .Offset: 0, .Size: 64 }, // sub_even64
51 { .Offset: 32, .Size: 32 }, // sub_odd
52 { .Offset: 64, .Size: 64 }, // sub_odd64
53 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
54 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
55 { .Offset: 4294967295, .Size: 4294967295 },
56 { .Offset: 0, .Size: 32 }, // sub_even
57 { .Offset: 0, .Size: 64 }, // sub_even64
58 { .Offset: 32, .Size: 32 }, // sub_odd
59 { .Offset: 64, .Size: 64 }, // sub_odd64
60 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
61 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
62};
63
64
65static const LaneBitmask SparcSubRegIndexLaneMaskTable[] = {
66 LaneBitmask::getAll(),
67 LaneBitmask(0x0000000000000001), // sub_even
68 LaneBitmask(0x0000000000000003), // sub_even64
69 LaneBitmask(0x0000000000000002), // sub_odd
70 LaneBitmask(0x000000000000000C), // sub_odd64
71 LaneBitmask(0x0000000000000004), // sub_odd64_then_sub_even
72 LaneBitmask(0x0000000000000008), // sub_odd64_then_sub_odd
73 };
74
75
76
77static const TargetRegisterInfo::RegClassInfo SparcRegClassInfos[] = {
78 // Mode = 0 (DefaultMode)
79 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*SparcVTLists+*/.VTListOffset: 0 }, // FCCRegs
80 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // ASRRegs
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // CoprocRegs
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 7 }, // FPRegs
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // IntRegs
84 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
85 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
86 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // DFPRegs
87 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs
88 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs
89 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // CoprocPair
90 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair
91 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // LowDFPRegs
92 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
93 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
94 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
95 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
96 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
97 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // QFPRegs
98 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // LowQFPRegs
99 // Mode = 1 (SPARC64)
100 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*SparcVTLists+*/.VTListOffset: 0 }, // FCCRegs
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // ASRRegs
102 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // CoprocRegs
103 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 7 }, // FPRegs
104 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // IntRegs
105 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
106 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // DFPRegs
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs
110 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // CoprocPair
111 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair
112 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // LowDFPRegs
113 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
114 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
115 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
116 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
117 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
118 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // QFPRegs
119 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // LowQFPRegs
120};
121
122static const uint8_t SparcCostPerUseTable[] = {
1230, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
124
125
126static const bool SparcInAllocatableClassTable[] = {
127false, true, true, true, false, false, true, false, false, true, false, true, true, false, true, true, false, true, true, true, true, true, true, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
128
129
130static const TargetRegisterInfoDesc SparcRegInfoDesc = { // Extra Descriptors
131.CostPerUse: SparcCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SparcInAllocatableClassTable};
132
133unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
134 static const uint8_t RowMap[6] = {
135 0, 0, 0, 1, 0, 0,
136 };
137 static const uint8_t Rows[2][6] = {
138 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
139 { SP::sub_odd64_then_sub_even, 0, SP::sub_odd64_then_sub_odd, 0, 0, 0, },
140 };
141
142 --IdxA; assert(IdxA < 6); (void) IdxA;
143 --IdxB; assert(IdxB < 6);
144 return Rows[RowMap[IdxA]][IdxB];
145}
146
147unsigned SparcGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
148 static const uint8_t Table[6][6] = {
149 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
150 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
151 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
152 { 0, 0, 0, 0, SP::sub_even, SP::sub_odd, },
153 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
154 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
155 };
156
157 --IdxA; assert(IdxA < 6);
158 --IdxB; assert(IdxB < 6);
159 return Table[IdxA][IdxB];
160 }
161
162 struct MaskRolOp {
163 LaneBitmask Mask;
164 uint8_t RotateLeft;
165 };
166 static const MaskRolOp LaneMaskComposeSequences[] = {
167 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
168 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
169 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
170 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 6
171 };
172 static const uint8_t CompositeSequences[] = {
173 0, // to sub_even
174 0, // to sub_even64
175 2, // to sub_odd
176 4, // to sub_odd64
177 4, // to sub_odd64_then_sub_even
178 6 // to sub_odd64_then_sub_odd
179 };
180
181LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
182 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
183 LaneBitmask Result;
184 for (const MaskRolOp *Ops =
185 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
186 Ops->Mask.any(); ++Ops) {
187 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
188 if (unsigned S = Ops->RotateLeft)
189 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
190 else
191 Result |= LaneBitmask(M);
192 }
193 return Result;
194}
195
196LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
197 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
198 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
199 LaneBitmask Result;
200 for (const MaskRolOp *Ops =
201 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
202 Ops->Mask.any(); ++Ops) {
203 LaneBitmask::Type M = LaneMask.getAsInteger();
204 if (unsigned S = Ops->RotateLeft)
205 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
206 else
207 Result |= LaneBitmask(M);
208 }
209 return Result;
210}
211
212const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
213 static constexpr uint8_t Table[20][6] = {
214 { // FCCRegs
215 0, // sub_even
216 0, // sub_even64
217 0, // sub_odd
218 0, // sub_odd64
219 0, // sub_odd64_then_sub_even
220 0, // sub_odd64_then_sub_odd
221 },
222 { // ASRRegs
223 0, // sub_even
224 0, // sub_even64
225 0, // sub_odd
226 0, // sub_odd64
227 0, // sub_odd64_then_sub_even
228 0, // sub_odd64_then_sub_odd
229 },
230 { // CoprocRegs
231 0, // sub_even
232 0, // sub_even64
233 0, // sub_odd
234 0, // sub_odd64
235 0, // sub_odd64_then_sub_even
236 0, // sub_odd64_then_sub_odd
237 },
238 { // FPRegs
239 0, // sub_even
240 0, // sub_even64
241 0, // sub_odd
242 0, // sub_odd64
243 0, // sub_odd64_then_sub_even
244 0, // sub_odd64_then_sub_odd
245 },
246 { // IntRegs
247 0, // sub_even
248 0, // sub_even64
249 0, // sub_odd
250 0, // sub_odd64
251 0, // sub_odd64_then_sub_even
252 0, // sub_odd64_then_sub_odd
253 },
254 { // GPRIncomingArg
255 0, // sub_even
256 0, // sub_even64
257 0, // sub_odd
258 0, // sub_odd64
259 0, // sub_odd64_then_sub_even
260 0, // sub_odd64_then_sub_odd
261 },
262 { // GPROutgoingArg
263 0, // sub_even
264 0, // sub_even64
265 0, // sub_odd
266 0, // sub_odd64
267 0, // sub_odd64_then_sub_even
268 0, // sub_odd64_then_sub_odd
269 },
270 { // DFPRegs
271 13, // sub_even -> LowDFPRegs
272 0, // sub_even64
273 13, // sub_odd -> LowDFPRegs
274 0, // sub_odd64
275 0, // sub_odd64_then_sub_even
276 0, // sub_odd64_then_sub_odd
277 },
278 { // I64Regs
279 0, // sub_even
280 0, // sub_even64
281 0, // sub_odd
282 0, // sub_odd64
283 0, // sub_odd64_then_sub_even
284 0, // sub_odd64_then_sub_odd
285 },
286 { // PRRegs
287 0, // sub_even
288 0, // sub_even64
289 0, // sub_odd
290 0, // sub_odd64
291 0, // sub_odd64_then_sub_even
292 0, // sub_odd64_then_sub_odd
293 },
294 { // CoprocPair
295 11, // sub_even -> CoprocPair
296 0, // sub_even64
297 11, // sub_odd -> CoprocPair
298 0, // sub_odd64
299 0, // sub_odd64_then_sub_even
300 0, // sub_odd64_then_sub_odd
301 },
302 { // IntPair
303 12, // sub_even -> IntPair
304 0, // sub_even64
305 12, // sub_odd -> IntPair
306 0, // sub_odd64
307 0, // sub_odd64_then_sub_even
308 0, // sub_odd64_then_sub_odd
309 },
310 { // LowDFPRegs
311 13, // sub_even -> LowDFPRegs
312 0, // sub_even64
313 13, // sub_odd -> LowDFPRegs
314 0, // sub_odd64
315 0, // sub_odd64_then_sub_even
316 0, // sub_odd64_then_sub_odd
317 },
318 { // I64Regs_and_GPRIncomingArg
319 0, // sub_even
320 0, // sub_even64
321 0, // sub_odd
322 0, // sub_odd64
323 0, // sub_odd64_then_sub_even
324 0, // sub_odd64_then_sub_odd
325 },
326 { // I64Regs_and_GPROutgoingArg
327 0, // sub_even
328 0, // sub_even64
329 0, // sub_odd
330 0, // sub_odd64
331 0, // sub_odd64_then_sub_even
332 0, // sub_odd64_then_sub_odd
333 },
334 { // IntPair_with_sub_even_in_GPRIncomingArg
335 16, // sub_even -> IntPair_with_sub_even_in_GPRIncomingArg
336 0, // sub_even64
337 16, // sub_odd -> IntPair_with_sub_even_in_GPRIncomingArg
338 0, // sub_odd64
339 0, // sub_odd64_then_sub_even
340 0, // sub_odd64_then_sub_odd
341 },
342 { // IntPair_with_sub_even_in_GPROutgoingArg
343 17, // sub_even -> IntPair_with_sub_even_in_GPROutgoingArg
344 0, // sub_even64
345 17, // sub_odd -> IntPair_with_sub_even_in_GPROutgoingArg
346 0, // sub_odd64
347 0, // sub_odd64_then_sub_even
348 0, // sub_odd64_then_sub_odd
349 },
350 { // PRRegs_and_ASRRegs
351 0, // sub_even
352 0, // sub_even64
353 0, // sub_odd
354 0, // sub_odd64
355 0, // sub_odd64_then_sub_even
356 0, // sub_odd64_then_sub_odd
357 },
358 { // QFPRegs
359 20, // sub_even -> LowQFPRegs
360 19, // sub_even64 -> QFPRegs
361 20, // sub_odd -> LowQFPRegs
362 19, // sub_odd64 -> QFPRegs
363 20, // sub_odd64_then_sub_even -> LowQFPRegs
364 20, // sub_odd64_then_sub_odd -> LowQFPRegs
365 },
366 { // LowQFPRegs
367 20, // sub_even -> LowQFPRegs
368 20, // sub_even64 -> LowQFPRegs
369 20, // sub_odd -> LowQFPRegs
370 20, // sub_odd64 -> LowQFPRegs
371 20, // sub_odd64_then_sub_even -> LowQFPRegs
372 20, // sub_odd64_then_sub_odd -> LowQFPRegs
373 },
374
375 };
376 assert(RC && "Missing regclass");
377 if (!Idx) return RC;
378 --Idx;
379 assert(Idx < 6 && "Bad subreg");
380 unsigned TV = Table[RC->getID()][Idx];
381 return TV ? getRegClass(i: TV - 1) : nullptr;
382}const TargetRegisterClass *SparcGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
383 static constexpr uint8_t Table[20][6] = {
384 { // FCCRegs
385 0, // FCCRegs:sub_even
386 0, // FCCRegs:sub_even64
387 0, // FCCRegs:sub_odd
388 0, // FCCRegs:sub_odd64
389 0, // FCCRegs:sub_odd64_then_sub_even
390 0, // FCCRegs:sub_odd64_then_sub_odd
391 },
392 { // ASRRegs
393 0, // ASRRegs:sub_even
394 0, // ASRRegs:sub_even64
395 0, // ASRRegs:sub_odd
396 0, // ASRRegs:sub_odd64
397 0, // ASRRegs:sub_odd64_then_sub_even
398 0, // ASRRegs:sub_odd64_then_sub_odd
399 },
400 { // CoprocRegs
401 0, // CoprocRegs:sub_even
402 0, // CoprocRegs:sub_even64
403 0, // CoprocRegs:sub_odd
404 0, // CoprocRegs:sub_odd64
405 0, // CoprocRegs:sub_odd64_then_sub_even
406 0, // CoprocRegs:sub_odd64_then_sub_odd
407 },
408 { // FPRegs
409 0, // FPRegs:sub_even
410 0, // FPRegs:sub_even64
411 0, // FPRegs:sub_odd
412 0, // FPRegs:sub_odd64
413 0, // FPRegs:sub_odd64_then_sub_even
414 0, // FPRegs:sub_odd64_then_sub_odd
415 },
416 { // IntRegs
417 0, // IntRegs:sub_even
418 0, // IntRegs:sub_even64
419 0, // IntRegs:sub_odd
420 0, // IntRegs:sub_odd64
421 0, // IntRegs:sub_odd64_then_sub_even
422 0, // IntRegs:sub_odd64_then_sub_odd
423 },
424 { // GPRIncomingArg
425 0, // GPRIncomingArg:sub_even
426 0, // GPRIncomingArg:sub_even64
427 0, // GPRIncomingArg:sub_odd
428 0, // GPRIncomingArg:sub_odd64
429 0, // GPRIncomingArg:sub_odd64_then_sub_even
430 0, // GPRIncomingArg:sub_odd64_then_sub_odd
431 },
432 { // GPROutgoingArg
433 0, // GPROutgoingArg:sub_even
434 0, // GPROutgoingArg:sub_even64
435 0, // GPROutgoingArg:sub_odd
436 0, // GPROutgoingArg:sub_odd64
437 0, // GPROutgoingArg:sub_odd64_then_sub_even
438 0, // GPROutgoingArg:sub_odd64_then_sub_odd
439 },
440 { // DFPRegs
441 4, // DFPRegs:sub_even -> FPRegs
442 0, // DFPRegs:sub_even64
443 4, // DFPRegs:sub_odd -> FPRegs
444 0, // DFPRegs:sub_odd64
445 0, // DFPRegs:sub_odd64_then_sub_even
446 0, // DFPRegs:sub_odd64_then_sub_odd
447 },
448 { // I64Regs
449 0, // I64Regs:sub_even
450 0, // I64Regs:sub_even64
451 0, // I64Regs:sub_odd
452 0, // I64Regs:sub_odd64
453 0, // I64Regs:sub_odd64_then_sub_even
454 0, // I64Regs:sub_odd64_then_sub_odd
455 },
456 { // PRRegs
457 0, // PRRegs:sub_even
458 0, // PRRegs:sub_even64
459 0, // PRRegs:sub_odd
460 0, // PRRegs:sub_odd64
461 0, // PRRegs:sub_odd64_then_sub_even
462 0, // PRRegs:sub_odd64_then_sub_odd
463 },
464 { // CoprocPair
465 3, // CoprocPair:sub_even -> CoprocRegs
466 0, // CoprocPair:sub_even64
467 3, // CoprocPair:sub_odd -> CoprocRegs
468 0, // CoprocPair:sub_odd64
469 0, // CoprocPair:sub_odd64_then_sub_even
470 0, // CoprocPair:sub_odd64_then_sub_odd
471 },
472 { // IntPair
473 9, // IntPair:sub_even -> I64Regs
474 0, // IntPair:sub_even64
475 9, // IntPair:sub_odd -> I64Regs
476 0, // IntPair:sub_odd64
477 0, // IntPair:sub_odd64_then_sub_even
478 0, // IntPair:sub_odd64_then_sub_odd
479 },
480 { // LowDFPRegs
481 4, // LowDFPRegs:sub_even -> FPRegs
482 0, // LowDFPRegs:sub_even64
483 4, // LowDFPRegs:sub_odd -> FPRegs
484 0, // LowDFPRegs:sub_odd64
485 0, // LowDFPRegs:sub_odd64_then_sub_even
486 0, // LowDFPRegs:sub_odd64_then_sub_odd
487 },
488 { // I64Regs_and_GPRIncomingArg
489 0, // I64Regs_and_GPRIncomingArg:sub_even
490 0, // I64Regs_and_GPRIncomingArg:sub_even64
491 0, // I64Regs_and_GPRIncomingArg:sub_odd
492 0, // I64Regs_and_GPRIncomingArg:sub_odd64
493 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_even
494 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_odd
495 },
496 { // I64Regs_and_GPROutgoingArg
497 0, // I64Regs_and_GPROutgoingArg:sub_even
498 0, // I64Regs_and_GPROutgoingArg:sub_even64
499 0, // I64Regs_and_GPROutgoingArg:sub_odd
500 0, // I64Regs_and_GPROutgoingArg:sub_odd64
501 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_even
502 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_odd
503 },
504 { // IntPair_with_sub_even_in_GPRIncomingArg
505 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even -> I64Regs_and_GPRIncomingArg
506 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even64
507 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd -> I64Regs_and_GPRIncomingArg
508 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64
509 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_even
510 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_odd
511 },
512 { // IntPair_with_sub_even_in_GPROutgoingArg
513 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even -> I64Regs_and_GPROutgoingArg
514 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even64
515 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd -> I64Regs_and_GPROutgoingArg
516 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64
517 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_even
518 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_odd
519 },
520 { // PRRegs_and_ASRRegs
521 0, // PRRegs_and_ASRRegs:sub_even
522 0, // PRRegs_and_ASRRegs:sub_even64
523 0, // PRRegs_and_ASRRegs:sub_odd
524 0, // PRRegs_and_ASRRegs:sub_odd64
525 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_even
526 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_odd
527 },
528 { // QFPRegs
529 4, // QFPRegs:sub_even -> FPRegs
530 8, // QFPRegs:sub_even64 -> DFPRegs
531 4, // QFPRegs:sub_odd -> FPRegs
532 8, // QFPRegs:sub_odd64 -> DFPRegs
533 4, // QFPRegs:sub_odd64_then_sub_even -> FPRegs
534 4, // QFPRegs:sub_odd64_then_sub_odd -> FPRegs
535 },
536 { // LowQFPRegs
537 4, // LowQFPRegs:sub_even -> FPRegs
538 13, // LowQFPRegs:sub_even64 -> LowDFPRegs
539 4, // LowQFPRegs:sub_odd -> FPRegs
540 13, // LowQFPRegs:sub_odd64 -> LowDFPRegs
541 4, // LowQFPRegs:sub_odd64_then_sub_even -> FPRegs
542 4, // LowQFPRegs:sub_odd64_then_sub_odd -> FPRegs
543 },
544
545 };
546 assert(RC && "Missing regclass");
547 if (!Idx) return RC;
548 --Idx;
549 assert(Idx < 6 && "Bad subreg");
550 unsigned TV = Table[RC->getID()][Idx];
551 return TV ? getRegClass(i: TV - 1) : nullptr;
552}/// Get the weight in units of pressure for this register class.
553const RegClassWeight &SparcGenRegisterInfo::
554getRegClassWeight(const TargetRegisterClass *RC) const {
555 static const RegClassWeight RCWeightTable[] = {
556 {.RegWeight: 1, .WeightLimit: 4}, // FCCRegs
557 {.RegWeight: 1, .WeightLimit: 1}, // ASRRegs
558 {.RegWeight: 0, .WeightLimit: 0}, // CoprocRegs
559 {.RegWeight: 1, .WeightLimit: 32}, // FPRegs
560 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
561 {.RegWeight: 1, .WeightLimit: 6}, // GPRIncomingArg
562 {.RegWeight: 1, .WeightLimit: 6}, // GPROutgoingArg
563 {.RegWeight: 2, .WeightLimit: 64}, // DFPRegs
564 {.RegWeight: 1, .WeightLimit: 32}, // I64Regs
565 {.RegWeight: 1, .WeightLimit: 17}, // PRRegs
566 {.RegWeight: 0, .WeightLimit: 0}, // CoprocPair
567 {.RegWeight: 2, .WeightLimit: 32}, // IntPair
568 {.RegWeight: 2, .WeightLimit: 32}, // LowDFPRegs
569 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPRIncomingArg
570 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPROutgoingArg
571 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPRIncomingArg
572 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPROutgoingArg
573 {.RegWeight: 1, .WeightLimit: 1}, // PRRegs_and_ASRRegs
574 {.RegWeight: 4, .WeightLimit: 64}, // QFPRegs
575 {.RegWeight: 4, .WeightLimit: 32}, // LowQFPRegs
576 };
577 return RCWeightTable[RC->getID()];
578}
579
580/// Get the weight in units of pressure for this register unit.
581unsigned SparcGenRegisterInfo::
582getRegUnitWeight(MCRegUnit RegUnit) const {
583 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
584 static const uint8_t RUWeightTable[] = {
585 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
586 return RUWeightTable[static_cast<unsigned>(RegUnit)];
587}
588
589
590// Get the number of dimensions of register pressure.
591unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
592 return 8;
593}
594
595// Get the name of this register unit pressure set.
596const char *SparcGenRegisterInfo::
597getRegPressureSetName(unsigned Idx) const {
598 static const char *PressureNameTable[] = {
599 "PRRegs_and_ASRRegs",
600 "FCCRegs",
601 "GPRIncomingArg",
602 "GPROutgoingArg",
603 "PRRegs",
604 "FPRegs",
605 "IntRegs",
606 "DFPRegs",
607 };
608 return PressureNameTable[Idx];
609}
610
611// Get the register unit pressure limit for this dimension.
612// This limit must be adjusted dynamically for reserved registers.
613unsigned SparcGenRegisterInfo::
614getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
615 static const uint8_t PressureLimitTable[] = {
616 1, // 0: PRRegs_and_ASRRegs
617 4, // 1: FCCRegs
618 6, // 2: GPRIncomingArg
619 6, // 3: GPROutgoingArg
620 17, // 4: PRRegs
621 32, // 5: FPRegs
622 32, // 6: IntRegs
623 64, // 7: DFPRegs
624 };
625 return PressureLimitTable[Idx];
626}
627
628/// Table of pressure sets per register class or unit.
629static const int RCSetsTable[] = {
630 /* 0 */ 1, -1,
631 /* 2 */ 0, 4, -1,
632 /* 5 */ 2, 6, -1,
633 /* 8 */ 3, 6, -1,
634 /* 11 */ 5, 7, -1,
635};
636
637/// Get the dimensions of register pressure impacted by this register class.
638/// Returns a -1 terminated array of pressure set IDs
639const int *SparcGenRegisterInfo::
640getRegClassPressureSets(const TargetRegisterClass *RC) const {
641 static const uint8_t RCSetStartTable[] = {
642 0,1,1,11,6,5,8,12,6,3,1,6,11,5,8,5,8,2,12,11,};
643 return &RCSetsTable[RCSetStartTable[RC->getID()]];
644}
645
646/// Get the dimensions of register pressure impacted by this register unit.
647/// Returns a -1 terminated array of pressure set IDs
648const int *SparcGenRegisterInfo::
649getRegUnitPressureSets(MCRegUnit RegUnit) const {
650 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
651 static const uint8_t RUSetStartTable[] = {
652 3,3,3,1,1,3,1,1,3,1,3,3,1,3,3,1,2,3,3,3,3,3,3,1,3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,0,0,0,0,6,6,6,6,6,6,6,6,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,8,8,8,8,8,8,6,6,};
653 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
654}
655
656
657// Register to minimal register class mapping
658
659const TargetRegisterClass *SparcGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
660 static const uint16_t InvalidRegClassID = UINT16_MAX;
661
662 static const uint16_t Mapping[238] = {
663 InvalidRegClassID, // NoRegister
664 SP::PRRegsRegClassID, // CANRESTORE
665 SP::PRRegsRegClassID, // CANSAVE
666 SP::PRRegsRegClassID, // CLEANWIN
667 InvalidRegClassID, // CPQ
668 InvalidRegClassID, // CPSR
669 SP::PRRegsRegClassID, // CWP
670 InvalidRegClassID, // FQ
671 InvalidRegClassID, // FSR
672 SP::PRRegsRegClassID, // GL
673 InvalidRegClassID, // ICC
674 SP::PRRegsRegClassID, // OTHERWIN
675 SP::PRRegsRegClassID, // PIL
676 InvalidRegClassID, // PSR
677 SP::PRRegsRegClassID, // PSTATE
678 SP::PRRegsRegClassID, // TBA
679 InvalidRegClassID, // TBR
680 SP::PRRegs_and_ASRRegsRegClassID, // TICK
681 SP::PRRegsRegClassID, // TL
682 SP::PRRegsRegClassID, // TNPC
683 SP::PRRegsRegClassID, // TPC
684 SP::PRRegsRegClassID, // TSTATE
685 SP::PRRegsRegClassID, // TT
686 SP::PRRegsRegClassID, // VER
687 InvalidRegClassID, // WIM
688 SP::PRRegsRegClassID, // WSTATE
689 SP::ASRRegsRegClassID, // Y
690 SP::ASRRegsRegClassID, // ASR1
691 SP::ASRRegsRegClassID, // ASR2
692 SP::ASRRegsRegClassID, // ASR3
693 SP::ASRRegsRegClassID, // ASR4
694 SP::ASRRegsRegClassID, // ASR5
695 SP::ASRRegsRegClassID, // ASR6
696 SP::ASRRegsRegClassID, // ASR7
697 SP::ASRRegsRegClassID, // ASR8
698 SP::ASRRegsRegClassID, // ASR9
699 SP::ASRRegsRegClassID, // ASR10
700 SP::ASRRegsRegClassID, // ASR11
701 SP::ASRRegsRegClassID, // ASR12
702 SP::ASRRegsRegClassID, // ASR13
703 SP::ASRRegsRegClassID, // ASR14
704 SP::ASRRegsRegClassID, // ASR15
705 SP::ASRRegsRegClassID, // ASR16
706 SP::ASRRegsRegClassID, // ASR17
707 SP::ASRRegsRegClassID, // ASR18
708 SP::ASRRegsRegClassID, // ASR19
709 SP::ASRRegsRegClassID, // ASR20
710 SP::ASRRegsRegClassID, // ASR21
711 SP::ASRRegsRegClassID, // ASR22
712 SP::ASRRegsRegClassID, // ASR23
713 SP::ASRRegsRegClassID, // ASR24
714 SP::ASRRegsRegClassID, // ASR25
715 SP::ASRRegsRegClassID, // ASR26
716 SP::ASRRegsRegClassID, // ASR27
717 SP::ASRRegsRegClassID, // ASR28
718 SP::ASRRegsRegClassID, // ASR29
719 SP::ASRRegsRegClassID, // ASR30
720 SP::ASRRegsRegClassID, // ASR31
721 SP::CoprocRegsRegClassID, // C0
722 SP::CoprocRegsRegClassID, // C1
723 SP::CoprocRegsRegClassID, // C2
724 SP::CoprocRegsRegClassID, // C3
725 SP::CoprocRegsRegClassID, // C4
726 SP::CoprocRegsRegClassID, // C5
727 SP::CoprocRegsRegClassID, // C6
728 SP::CoprocRegsRegClassID, // C7
729 SP::CoprocRegsRegClassID, // C8
730 SP::CoprocRegsRegClassID, // C9
731 SP::CoprocRegsRegClassID, // C10
732 SP::CoprocRegsRegClassID, // C11
733 SP::CoprocRegsRegClassID, // C12
734 SP::CoprocRegsRegClassID, // C13
735 SP::CoprocRegsRegClassID, // C14
736 SP::CoprocRegsRegClassID, // C15
737 SP::CoprocRegsRegClassID, // C16
738 SP::CoprocRegsRegClassID, // C17
739 SP::CoprocRegsRegClassID, // C18
740 SP::CoprocRegsRegClassID, // C19
741 SP::CoprocRegsRegClassID, // C20
742 SP::CoprocRegsRegClassID, // C21
743 SP::CoprocRegsRegClassID, // C22
744 SP::CoprocRegsRegClassID, // C23
745 SP::CoprocRegsRegClassID, // C24
746 SP::CoprocRegsRegClassID, // C25
747 SP::CoprocRegsRegClassID, // C26
748 SP::CoprocRegsRegClassID, // C27
749 SP::CoprocRegsRegClassID, // C28
750 SP::CoprocRegsRegClassID, // C29
751 SP::CoprocRegsRegClassID, // C30
752 SP::CoprocRegsRegClassID, // C31
753 SP::LowDFPRegsRegClassID, // D0
754 SP::LowDFPRegsRegClassID, // D1
755 SP::LowDFPRegsRegClassID, // D2
756 SP::LowDFPRegsRegClassID, // D3
757 SP::LowDFPRegsRegClassID, // D4
758 SP::LowDFPRegsRegClassID, // D5
759 SP::LowDFPRegsRegClassID, // D6
760 SP::LowDFPRegsRegClassID, // D7
761 SP::LowDFPRegsRegClassID, // D8
762 SP::LowDFPRegsRegClassID, // D9
763 SP::LowDFPRegsRegClassID, // D10
764 SP::LowDFPRegsRegClassID, // D11
765 SP::LowDFPRegsRegClassID, // D12
766 SP::LowDFPRegsRegClassID, // D13
767 SP::LowDFPRegsRegClassID, // D14
768 SP::LowDFPRegsRegClassID, // D15
769 SP::DFPRegsRegClassID, // D16
770 SP::DFPRegsRegClassID, // D17
771 SP::DFPRegsRegClassID, // D18
772 SP::DFPRegsRegClassID, // D19
773 SP::DFPRegsRegClassID, // D20
774 SP::DFPRegsRegClassID, // D21
775 SP::DFPRegsRegClassID, // D22
776 SP::DFPRegsRegClassID, // D23
777 SP::DFPRegsRegClassID, // D24
778 SP::DFPRegsRegClassID, // D25
779 SP::DFPRegsRegClassID, // D26
780 SP::DFPRegsRegClassID, // D27
781 SP::DFPRegsRegClassID, // D28
782 SP::DFPRegsRegClassID, // D29
783 SP::DFPRegsRegClassID, // D30
784 SP::DFPRegsRegClassID, // D31
785 SP::FPRegsRegClassID, // F0
786 SP::FPRegsRegClassID, // F1
787 SP::FPRegsRegClassID, // F2
788 SP::FPRegsRegClassID, // F3
789 SP::FPRegsRegClassID, // F4
790 SP::FPRegsRegClassID, // F5
791 SP::FPRegsRegClassID, // F6
792 SP::FPRegsRegClassID, // F7
793 SP::FPRegsRegClassID, // F8
794 SP::FPRegsRegClassID, // F9
795 SP::FPRegsRegClassID, // F10
796 SP::FPRegsRegClassID, // F11
797 SP::FPRegsRegClassID, // F12
798 SP::FPRegsRegClassID, // F13
799 SP::FPRegsRegClassID, // F14
800 SP::FPRegsRegClassID, // F15
801 SP::FPRegsRegClassID, // F16
802 SP::FPRegsRegClassID, // F17
803 SP::FPRegsRegClassID, // F18
804 SP::FPRegsRegClassID, // F19
805 SP::FPRegsRegClassID, // F20
806 SP::FPRegsRegClassID, // F21
807 SP::FPRegsRegClassID, // F22
808 SP::FPRegsRegClassID, // F23
809 SP::FPRegsRegClassID, // F24
810 SP::FPRegsRegClassID, // F25
811 SP::FPRegsRegClassID, // F26
812 SP::FPRegsRegClassID, // F27
813 SP::FPRegsRegClassID, // F28
814 SP::FPRegsRegClassID, // F29
815 SP::FPRegsRegClassID, // F30
816 SP::FPRegsRegClassID, // F31
817 SP::FCCRegsRegClassID, // FCC0
818 SP::FCCRegsRegClassID, // FCC1
819 SP::FCCRegsRegClassID, // FCC2
820 SP::FCCRegsRegClassID, // FCC3
821 SP::I64RegsRegClassID, // G0
822 SP::I64RegsRegClassID, // G1
823 SP::I64RegsRegClassID, // G2
824 SP::I64RegsRegClassID, // G3
825 SP::I64RegsRegClassID, // G4
826 SP::I64RegsRegClassID, // G5
827 SP::I64RegsRegClassID, // G6
828 SP::I64RegsRegClassID, // G7
829 SP::I64Regs_and_GPRIncomingArgRegClassID, // I0
830 SP::I64Regs_and_GPRIncomingArgRegClassID, // I1
831 SP::I64Regs_and_GPRIncomingArgRegClassID, // I2
832 SP::I64Regs_and_GPRIncomingArgRegClassID, // I3
833 SP::I64Regs_and_GPRIncomingArgRegClassID, // I4
834 SP::I64Regs_and_GPRIncomingArgRegClassID, // I5
835 SP::I64RegsRegClassID, // I6
836 SP::I64RegsRegClassID, // I7
837 SP::I64RegsRegClassID, // L0
838 SP::I64RegsRegClassID, // L1
839 SP::I64RegsRegClassID, // L2
840 SP::I64RegsRegClassID, // L3
841 SP::I64RegsRegClassID, // L4
842 SP::I64RegsRegClassID, // L5
843 SP::I64RegsRegClassID, // L6
844 SP::I64RegsRegClassID, // L7
845 SP::I64Regs_and_GPROutgoingArgRegClassID, // O0
846 SP::I64Regs_and_GPROutgoingArgRegClassID, // O1
847 SP::I64Regs_and_GPROutgoingArgRegClassID, // O2
848 SP::I64Regs_and_GPROutgoingArgRegClassID, // O3
849 SP::I64Regs_and_GPROutgoingArgRegClassID, // O4
850 SP::I64Regs_and_GPROutgoingArgRegClassID, // O5
851 SP::I64RegsRegClassID, // O6
852 SP::I64RegsRegClassID, // O7
853 SP::LowQFPRegsRegClassID, // Q0
854 SP::LowQFPRegsRegClassID, // Q1
855 SP::LowQFPRegsRegClassID, // Q2
856 SP::LowQFPRegsRegClassID, // Q3
857 SP::LowQFPRegsRegClassID, // Q4
858 SP::LowQFPRegsRegClassID, // Q5
859 SP::LowQFPRegsRegClassID, // Q6
860 SP::LowQFPRegsRegClassID, // Q7
861 SP::QFPRegsRegClassID, // Q8
862 SP::QFPRegsRegClassID, // Q9
863 SP::QFPRegsRegClassID, // Q10
864 SP::QFPRegsRegClassID, // Q11
865 SP::QFPRegsRegClassID, // Q12
866 SP::QFPRegsRegClassID, // Q13
867 SP::QFPRegsRegClassID, // Q14
868 SP::QFPRegsRegClassID, // Q15
869 SP::CoprocPairRegClassID, // C0_C1
870 SP::CoprocPairRegClassID, // C2_C3
871 SP::CoprocPairRegClassID, // C4_C5
872 SP::CoprocPairRegClassID, // C6_C7
873 SP::CoprocPairRegClassID, // C8_C9
874 SP::CoprocPairRegClassID, // C10_C11
875 SP::CoprocPairRegClassID, // C12_C13
876 SP::CoprocPairRegClassID, // C14_C15
877 SP::CoprocPairRegClassID, // C16_C17
878 SP::CoprocPairRegClassID, // C18_C19
879 SP::CoprocPairRegClassID, // C20_C21
880 SP::CoprocPairRegClassID, // C22_C23
881 SP::CoprocPairRegClassID, // C24_C25
882 SP::CoprocPairRegClassID, // C26_C27
883 SP::CoprocPairRegClassID, // C28_C29
884 SP::CoprocPairRegClassID, // C30_C31
885 SP::IntPairRegClassID, // G0_G1
886 SP::IntPairRegClassID, // G2_G3
887 SP::IntPairRegClassID, // G4_G5
888 SP::IntPairRegClassID, // G6_G7
889 SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, // I0_I1
890 SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, // I2_I3
891 SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, // I4_I5
892 SP::IntPairRegClassID, // I6_I7
893 SP::IntPairRegClassID, // L0_L1
894 SP::IntPairRegClassID, // L2_L3
895 SP::IntPairRegClassID, // L4_L5
896 SP::IntPairRegClassID, // L6_L7
897 SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, // O0_O1
898 SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, // O2_O3
899 SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, // O4_O5
900 SP::IntPairRegClassID, // O6_O7
901 };
902
903 assert(Reg < ArrayRef(Mapping).size());
904 unsigned RCID = Mapping[Reg.id()];
905 if (RCID == InvalidRegClassID)
906 return nullptr;
907 return &SparcMCRegisterClassStorage.Classes[RCID];
908}
909extern const MCRegisterDesc SparcRegDesc[];
910extern const int16_t SparcRegDiffLists[];
911extern const LaneBitmask SparcLaneMaskLists[];
912extern const char SparcRegStrings[];
913extern const char SparcRegClassStrings[];
914extern const MCPhysReg SparcRegUnitRoots[][2];
915extern const uint16_t SparcSubRegIdxLists[];
916extern const uint16_t SparcRegEncodingTable[];
917// SP Dwarf<->LLVM register mappings.
918extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
919extern const unsigned SPDwarfFlavour0Dwarf2LSize;
920
921extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
922extern const unsigned SPEHFlavour0Dwarf2LSize;
923
924extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
925extern const unsigned SPDwarfFlavour0L2DwarfSize;
926
927extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
928extern const unsigned SPEHFlavour0L2DwarfSize;
929
930
931SparcGenRegisterInfo::
932SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
933 unsigned PC, unsigned HwMode)
934 : TargetRegisterInfo(&SparcRegInfoDesc,
935 SparcSubRegIndexStrings, SparcSubRegIndexNameOffsets,
936 SparcSubRegIdxRangeTable, SparcSubRegIndexLaneMaskTable,
937
938 LaneBitmask(0xFFFFFFFFFFFFFFFF), SparcRegClassInfos, SparcVTLists, HwMode) {
939 InitMCRegisterInfo(D: SparcRegDesc, NR: 238, RA, PC,
940 C: &getSparcMCRegisterClass(RC: 0), NC: 20, RURoots: SparcRegUnitRoots, NRU: 173, DL: SparcRegDiffLists,
941 RUMS: SparcLaneMaskLists, Strings: SparcRegStrings, ClassStrings: SparcRegClassStrings, SubIndices: SparcSubRegIdxLists, NumIndices: 7,
942 RET: SparcRegEncodingTable, RUI: nullptr);
943
944 switch (DwarfFlavour) {
945 default:
946 llvm_unreachable("Unknown DWARF flavour");
947 case 0:
948 mapDwarfRegsToLLVMRegs(Map: SPDwarfFlavour0Dwarf2L, Size: SPDwarfFlavour0Dwarf2LSize, isEH: false);
949 break;
950 }
951 switch (EHFlavour) {
952 default:
953 llvm_unreachable("Unknown DWARF flavour");
954 case 0:
955 mapDwarfRegsToLLVMRegs(Map: SPEHFlavour0Dwarf2L, Size: SPEHFlavour0Dwarf2LSize, isEH: true);
956 break;
957 }
958 switch (DwarfFlavour) {
959 default:
960 llvm_unreachable("Unknown DWARF flavour");
961 case 0:
962 mapLLVMRegsToDwarfRegs(Map: SPDwarfFlavour0L2Dwarf, Size: SPDwarfFlavour0L2DwarfSize, isEH: false);
963 break;
964 }
965 switch (EHFlavour) {
966 default:
967 llvm_unreachable("Unknown DWARF flavour");
968 case 0:
969 mapLLVMRegsToDwarfRegs(Map: SPEHFlavour0L2Dwarf, Size: SPEHFlavour0L2DwarfSize, isEH: true);
970 break;
971 }
972}
973
974static const MCPhysReg CSR_SaveList[] = { 0 };
975static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x103fffc0, 0x00000000, 0x000003fc, };
976static const MCPhysReg RTCSR_SaveList[] = { 0 };
977static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00003000, 0x00000000, 0x00000020, };
978
979
980ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
981 static const uint32_t *const Masks[] = {
982 CSR_RegMask,
983 RTCSR_RegMask,
984 };
985 return ArrayRef(Masks);
986}
987
988bool SparcGenRegisterInfo::
989isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
990 return
991 false;
992}
993
994bool SparcGenRegisterInfo::
995isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
996 return
997 false;
998}
999
1000bool SparcGenRegisterInfo::
1001isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1002 return
1003 false;
1004}
1005
1006bool SparcGenRegisterInfo::
1007isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1008 return
1009 false;
1010}
1011
1012bool SparcGenRegisterInfo::
1013isConstantPhysReg(MCRegister PhysReg) const {
1014 return
1015 PhysReg == SP::G0 ||
1016 false;
1017}
1018
1019ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
1020 static const char *Names[] = {
1021 "CSR",
1022 "RTCSR",
1023 };
1024 return ArrayRef(Names);
1025}
1026
1027const SparcFrameLowering *
1028SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1029 return static_cast<const SparcFrameLowering *>(
1030 MF.getSubtarget().getFrameLowering());
1031}
1032
1033
1034} // namespace llvm
1035