1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<20, 317, 47, 42, 11, 15> SparcMCRegisterClassStorage;
12
13static const MVT::SimpleValueType SparcVTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i32, MVT::i64, MVT::Other,
17 /* 7 */ MVT::f32, MVT::Other,
18 /* 9 */ MVT::f64, MVT::Other,
19 /* 11 */ MVT::f128, MVT::Other,
20 /* 13 */ MVT::v2i32, MVT::Other,
21};
22
23#ifdef __GNUC__
24#pragma GCC diagnostic push
25#pragma GCC diagnostic ignored "-Woverlength-strings"
26#endif
27static constexpr char SparcSubRegIndexStrings[] = {
28 /* 0 */ "sub_odd64\000"
29 /* 10 */ "sub_even64\000"
30 /* 21 */ "sub_odd64_then_sub_odd\000"
31 /* 44 */ "sub_odd64_then_sub_even\000"
32};
33#ifdef __GNUC__
34#pragma GCC diagnostic pop
35#endif
36
37
38static constexpr uint32_t SparcSubRegIndexNameOffsets[] = {
39 59,
40 10,
41 36,
42 0,
43 44,
44 21,
45};
46
47static const TargetRegisterInfo::SubRegCoveredBits SparcSubRegIdxRangeTable[] = {
48 { .Offset: 4294967295, .Size: 4294967295 },
49 { .Offset: 0, .Size: 32 }, // sub_even
50 { .Offset: 0, .Size: 64 }, // sub_even64
51 { .Offset: 32, .Size: 32 }, // sub_odd
52 { .Offset: 64, .Size: 64 }, // sub_odd64
53 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
54 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
55 { .Offset: 4294967295, .Size: 4294967295 },
56 { .Offset: 0, .Size: 32 }, // sub_even
57 { .Offset: 0, .Size: 64 }, // sub_even64
58 { .Offset: 32, .Size: 32 }, // sub_odd
59 { .Offset: 64, .Size: 64 }, // sub_odd64
60 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
61 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
62};
63
64
65static const LaneBitmask SparcSubRegIndexLaneMaskTable[] = {
66 LaneBitmask::getAll(),
67 LaneBitmask(0x0000000000000001), // sub_even
68 LaneBitmask(0x0000000000000003), // sub_even64
69 LaneBitmask(0x0000000000000002), // sub_odd
70 LaneBitmask(0x000000000000000C), // sub_odd64
71 LaneBitmask(0x0000000000000004), // sub_odd64_then_sub_even
72 LaneBitmask(0x0000000000000008), // sub_odd64_then_sub_odd
73 };
74
75
76
77static const TargetRegisterInfo::RegClassInfo SparcRegClassInfos[] = {
78 // Mode = 0 (DefaultMode)
79 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*SparcVTLists+*/.VTListOffset: 0 }, // FCCRegs
80 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // ASRRegs
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // CoprocRegs
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 7 }, // FPRegs
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // IntRegs
84 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
85 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
86 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // DFPRegs
87 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs
88 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs
89 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // CoprocPair
90 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair
91 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // LowDFPRegs
92 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
93 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
94 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
95 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
96 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
97 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // QFPRegs
98 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // LowQFPRegs
99 // Mode = 1 (SPARC64)
100 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*SparcVTLists+*/.VTListOffset: 0 }, // FCCRegs
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // ASRRegs
102 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 2 }, // CoprocRegs
103 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 7 }, // FPRegs
104 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // IntRegs
105 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
106 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*SparcVTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // DFPRegs
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs
110 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // CoprocPair
111 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair
112 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 9 }, // LowDFPRegs
113 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
114 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
115 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
116 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
117 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*SparcVTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
118 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // QFPRegs
119 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*SparcVTLists+*/.VTListOffset: 11 }, // LowQFPRegs
120};
121
122static const uint8_t SparcCostPerUseTable[] = {
1230, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
124
125
126static const bool SparcInAllocatableClassTable[] = {
127false, true, true, true, false, false, true, false, false, true, false, true, true, false, true, true, false, true, true, true, true, true, true, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
128
129
130static const TargetRegisterInfoDesc SparcRegInfoDesc = { // Extra Descriptors
131.CostPerUse: SparcCostPerUseTable, .NumCosts: 1, .InAllocatableClass: SparcInAllocatableClassTable};
132
133unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
134 static const uint8_t RowMap[6] = {
135 0, 0, 0, 1, 0, 0,
136 };
137 static const uint8_t Rows[2][6] = {
138 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
139 { SP::sub_odd64_then_sub_even, 0, SP::sub_odd64_then_sub_odd, 0, 0, 0, },
140 };
141
142 --IdxA; assert(IdxA < 6); (void) IdxA;
143 --IdxB; assert(IdxB < 6);
144 return Rows[RowMap[IdxA]][IdxB];
145}
146
147unsigned SparcGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
148 static const uint8_t Table[6][6] = {
149 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
150 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
151 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
152 { 0, 0, 0, 0, SP::sub_even, SP::sub_odd, },
153 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
154 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
155 };
156
157 --IdxA; assert(IdxA < 6);
158 --IdxB; assert(IdxB < 6);
159 return Table[IdxA][IdxB];
160 }
161
162 struct MaskRolOp {
163 LaneBitmask Mask;
164 uint8_t RotateLeft;
165 };
166 static const MaskRolOp LaneMaskComposeSequences[] = {
167 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
168 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
169 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
170 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 6
171 };
172 static const uint8_t CompositeSequences[] = {
173 0, // to sub_even
174 0, // to sub_even64
175 2, // to sub_odd
176 4, // to sub_odd64
177 4, // to sub_odd64_then_sub_even
178 6 // to sub_odd64_then_sub_odd
179 };
180
181LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
182 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
183 LaneBitmask Result;
184 for (const MaskRolOp *Ops =
185 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
186 Ops->Mask.any(); ++Ops) {
187 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
188 if (unsigned S = Ops->RotateLeft)
189 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
190 else
191 Result |= LaneBitmask(M);
192 }
193 return Result;
194}
195
196LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
197 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
198 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
199 LaneBitmask Result;
200 for (const MaskRolOp *Ops =
201 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
202 Ops->Mask.any(); ++Ops) {
203 LaneBitmask::Type M = LaneMask.getAsInteger();
204 if (unsigned S = Ops->RotateLeft)
205 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
206 else
207 Result |= LaneBitmask(M);
208 }
209 return Result;
210}
211
212const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
213 static constexpr uint8_t Table[20][6] = {
214 { // FCCRegs
215 0, // sub_even
216 0, // sub_even64
217 0, // sub_odd
218 0, // sub_odd64
219 0, // sub_odd64_then_sub_even
220 0, // sub_odd64_then_sub_odd
221 },
222 { // ASRRegs
223 0, // sub_even
224 0, // sub_even64
225 0, // sub_odd
226 0, // sub_odd64
227 0, // sub_odd64_then_sub_even
228 0, // sub_odd64_then_sub_odd
229 },
230 { // CoprocRegs
231 0, // sub_even
232 0, // sub_even64
233 0, // sub_odd
234 0, // sub_odd64
235 0, // sub_odd64_then_sub_even
236 0, // sub_odd64_then_sub_odd
237 },
238 { // FPRegs
239 0, // sub_even
240 0, // sub_even64
241 0, // sub_odd
242 0, // sub_odd64
243 0, // sub_odd64_then_sub_even
244 0, // sub_odd64_then_sub_odd
245 },
246 { // IntRegs
247 0, // sub_even
248 0, // sub_even64
249 0, // sub_odd
250 0, // sub_odd64
251 0, // sub_odd64_then_sub_even
252 0, // sub_odd64_then_sub_odd
253 },
254 { // GPRIncomingArg
255 0, // sub_even
256 0, // sub_even64
257 0, // sub_odd
258 0, // sub_odd64
259 0, // sub_odd64_then_sub_even
260 0, // sub_odd64_then_sub_odd
261 },
262 { // GPROutgoingArg
263 0, // sub_even
264 0, // sub_even64
265 0, // sub_odd
266 0, // sub_odd64
267 0, // sub_odd64_then_sub_even
268 0, // sub_odd64_then_sub_odd
269 },
270 { // DFPRegs
271 13, // sub_even -> LowDFPRegs
272 0, // sub_even64
273 13, // sub_odd -> LowDFPRegs
274 0, // sub_odd64
275 0, // sub_odd64_then_sub_even
276 0, // sub_odd64_then_sub_odd
277 },
278 { // I64Regs
279 0, // sub_even
280 0, // sub_even64
281 0, // sub_odd
282 0, // sub_odd64
283 0, // sub_odd64_then_sub_even
284 0, // sub_odd64_then_sub_odd
285 },
286 { // PRRegs
287 0, // sub_even
288 0, // sub_even64
289 0, // sub_odd
290 0, // sub_odd64
291 0, // sub_odd64_then_sub_even
292 0, // sub_odd64_then_sub_odd
293 },
294 { // CoprocPair
295 11, // sub_even -> CoprocPair
296 0, // sub_even64
297 11, // sub_odd -> CoprocPair
298 0, // sub_odd64
299 0, // sub_odd64_then_sub_even
300 0, // sub_odd64_then_sub_odd
301 },
302 { // IntPair
303 12, // sub_even -> IntPair
304 0, // sub_even64
305 12, // sub_odd -> IntPair
306 0, // sub_odd64
307 0, // sub_odd64_then_sub_even
308 0, // sub_odd64_then_sub_odd
309 },
310 { // LowDFPRegs
311 13, // sub_even -> LowDFPRegs
312 0, // sub_even64
313 13, // sub_odd -> LowDFPRegs
314 0, // sub_odd64
315 0, // sub_odd64_then_sub_even
316 0, // sub_odd64_then_sub_odd
317 },
318 { // I64Regs_and_GPRIncomingArg
319 0, // sub_even
320 0, // sub_even64
321 0, // sub_odd
322 0, // sub_odd64
323 0, // sub_odd64_then_sub_even
324 0, // sub_odd64_then_sub_odd
325 },
326 { // I64Regs_and_GPROutgoingArg
327 0, // sub_even
328 0, // sub_even64
329 0, // sub_odd
330 0, // sub_odd64
331 0, // sub_odd64_then_sub_even
332 0, // sub_odd64_then_sub_odd
333 },
334 { // IntPair_with_sub_even_in_GPRIncomingArg
335 16, // sub_even -> IntPair_with_sub_even_in_GPRIncomingArg
336 0, // sub_even64
337 16, // sub_odd -> IntPair_with_sub_even_in_GPRIncomingArg
338 0, // sub_odd64
339 0, // sub_odd64_then_sub_even
340 0, // sub_odd64_then_sub_odd
341 },
342 { // IntPair_with_sub_even_in_GPROutgoingArg
343 17, // sub_even -> IntPair_with_sub_even_in_GPROutgoingArg
344 0, // sub_even64
345 17, // sub_odd -> IntPair_with_sub_even_in_GPROutgoingArg
346 0, // sub_odd64
347 0, // sub_odd64_then_sub_even
348 0, // sub_odd64_then_sub_odd
349 },
350 { // PRRegs_and_ASRRegs
351 0, // sub_even
352 0, // sub_even64
353 0, // sub_odd
354 0, // sub_odd64
355 0, // sub_odd64_then_sub_even
356 0, // sub_odd64_then_sub_odd
357 },
358 { // QFPRegs
359 20, // sub_even -> LowQFPRegs
360 19, // sub_even64 -> QFPRegs
361 20, // sub_odd -> LowQFPRegs
362 19, // sub_odd64 -> QFPRegs
363 20, // sub_odd64_then_sub_even -> LowQFPRegs
364 20, // sub_odd64_then_sub_odd -> LowQFPRegs
365 },
366 { // LowQFPRegs
367 20, // sub_even -> LowQFPRegs
368 20, // sub_even64 -> LowQFPRegs
369 20, // sub_odd -> LowQFPRegs
370 20, // sub_odd64 -> LowQFPRegs
371 20, // sub_odd64_then_sub_even -> LowQFPRegs
372 20, // sub_odd64_then_sub_odd -> LowQFPRegs
373 },
374
375 };
376 assert(RC && "Missing regclass");
377 if (!Idx) return RC;
378 --Idx;
379 assert(Idx < 6 && "Bad subreg");
380 unsigned TV = Table[RC->getID()][Idx];
381 return TV ? getRegClass(i: TV - 1) : nullptr;
382}const TargetRegisterClass *SparcGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
383 static constexpr uint8_t Table[20][6] = {
384 { // FCCRegs
385 0, // FCCRegs:sub_even
386 0, // FCCRegs:sub_even64
387 0, // FCCRegs:sub_odd
388 0, // FCCRegs:sub_odd64
389 0, // FCCRegs:sub_odd64_then_sub_even
390 0, // FCCRegs:sub_odd64_then_sub_odd
391 },
392 { // ASRRegs
393 0, // ASRRegs:sub_even
394 0, // ASRRegs:sub_even64
395 0, // ASRRegs:sub_odd
396 0, // ASRRegs:sub_odd64
397 0, // ASRRegs:sub_odd64_then_sub_even
398 0, // ASRRegs:sub_odd64_then_sub_odd
399 },
400 { // CoprocRegs
401 0, // CoprocRegs:sub_even
402 0, // CoprocRegs:sub_even64
403 0, // CoprocRegs:sub_odd
404 0, // CoprocRegs:sub_odd64
405 0, // CoprocRegs:sub_odd64_then_sub_even
406 0, // CoprocRegs:sub_odd64_then_sub_odd
407 },
408 { // FPRegs
409 0, // FPRegs:sub_even
410 0, // FPRegs:sub_even64
411 0, // FPRegs:sub_odd
412 0, // FPRegs:sub_odd64
413 0, // FPRegs:sub_odd64_then_sub_even
414 0, // FPRegs:sub_odd64_then_sub_odd
415 },
416 { // IntRegs
417 0, // IntRegs:sub_even
418 0, // IntRegs:sub_even64
419 0, // IntRegs:sub_odd
420 0, // IntRegs:sub_odd64
421 0, // IntRegs:sub_odd64_then_sub_even
422 0, // IntRegs:sub_odd64_then_sub_odd
423 },
424 { // GPRIncomingArg
425 0, // GPRIncomingArg:sub_even
426 0, // GPRIncomingArg:sub_even64
427 0, // GPRIncomingArg:sub_odd
428 0, // GPRIncomingArg:sub_odd64
429 0, // GPRIncomingArg:sub_odd64_then_sub_even
430 0, // GPRIncomingArg:sub_odd64_then_sub_odd
431 },
432 { // GPROutgoingArg
433 0, // GPROutgoingArg:sub_even
434 0, // GPROutgoingArg:sub_even64
435 0, // GPROutgoingArg:sub_odd
436 0, // GPROutgoingArg:sub_odd64
437 0, // GPROutgoingArg:sub_odd64_then_sub_even
438 0, // GPROutgoingArg:sub_odd64_then_sub_odd
439 },
440 { // DFPRegs
441 4, // DFPRegs:sub_even -> FPRegs
442 0, // DFPRegs:sub_even64
443 4, // DFPRegs:sub_odd -> FPRegs
444 0, // DFPRegs:sub_odd64
445 0, // DFPRegs:sub_odd64_then_sub_even
446 0, // DFPRegs:sub_odd64_then_sub_odd
447 },
448 { // I64Regs
449 0, // I64Regs:sub_even
450 0, // I64Regs:sub_even64
451 0, // I64Regs:sub_odd
452 0, // I64Regs:sub_odd64
453 0, // I64Regs:sub_odd64_then_sub_even
454 0, // I64Regs:sub_odd64_then_sub_odd
455 },
456 { // PRRegs
457 0, // PRRegs:sub_even
458 0, // PRRegs:sub_even64
459 0, // PRRegs:sub_odd
460 0, // PRRegs:sub_odd64
461 0, // PRRegs:sub_odd64_then_sub_even
462 0, // PRRegs:sub_odd64_then_sub_odd
463 },
464 { // CoprocPair
465 3, // CoprocPair:sub_even -> CoprocRegs
466 0, // CoprocPair:sub_even64
467 3, // CoprocPair:sub_odd -> CoprocRegs
468 0, // CoprocPair:sub_odd64
469 0, // CoprocPair:sub_odd64_then_sub_even
470 0, // CoprocPair:sub_odd64_then_sub_odd
471 },
472 { // IntPair
473 9, // IntPair:sub_even -> I64Regs
474 0, // IntPair:sub_even64
475 9, // IntPair:sub_odd -> I64Regs
476 0, // IntPair:sub_odd64
477 0, // IntPair:sub_odd64_then_sub_even
478 0, // IntPair:sub_odd64_then_sub_odd
479 },
480 { // LowDFPRegs
481 4, // LowDFPRegs:sub_even -> FPRegs
482 0, // LowDFPRegs:sub_even64
483 4, // LowDFPRegs:sub_odd -> FPRegs
484 0, // LowDFPRegs:sub_odd64
485 0, // LowDFPRegs:sub_odd64_then_sub_even
486 0, // LowDFPRegs:sub_odd64_then_sub_odd
487 },
488 { // I64Regs_and_GPRIncomingArg
489 0, // I64Regs_and_GPRIncomingArg:sub_even
490 0, // I64Regs_and_GPRIncomingArg:sub_even64
491 0, // I64Regs_and_GPRIncomingArg:sub_odd
492 0, // I64Regs_and_GPRIncomingArg:sub_odd64
493 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_even
494 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_odd
495 },
496 { // I64Regs_and_GPROutgoingArg
497 0, // I64Regs_and_GPROutgoingArg:sub_even
498 0, // I64Regs_and_GPROutgoingArg:sub_even64
499 0, // I64Regs_and_GPROutgoingArg:sub_odd
500 0, // I64Regs_and_GPROutgoingArg:sub_odd64
501 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_even
502 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_odd
503 },
504 { // IntPair_with_sub_even_in_GPRIncomingArg
505 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even -> I64Regs_and_GPRIncomingArg
506 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even64
507 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd -> I64Regs_and_GPRIncomingArg
508 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64
509 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_even
510 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_odd
511 },
512 { // IntPair_with_sub_even_in_GPROutgoingArg
513 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even -> I64Regs_and_GPROutgoingArg
514 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even64
515 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd -> I64Regs_and_GPROutgoingArg
516 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64
517 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_even
518 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_odd
519 },
520 { // PRRegs_and_ASRRegs
521 0, // PRRegs_and_ASRRegs:sub_even
522 0, // PRRegs_and_ASRRegs:sub_even64
523 0, // PRRegs_and_ASRRegs:sub_odd
524 0, // PRRegs_and_ASRRegs:sub_odd64
525 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_even
526 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_odd
527 },
528 { // QFPRegs
529 4, // QFPRegs:sub_even -> FPRegs
530 8, // QFPRegs:sub_even64 -> DFPRegs
531 4, // QFPRegs:sub_odd -> FPRegs
532 8, // QFPRegs:sub_odd64 -> DFPRegs
533 4, // QFPRegs:sub_odd64_then_sub_even -> FPRegs
534 4, // QFPRegs:sub_odd64_then_sub_odd -> FPRegs
535 },
536 { // LowQFPRegs
537 4, // LowQFPRegs:sub_even -> FPRegs
538 13, // LowQFPRegs:sub_even64 -> LowDFPRegs
539 4, // LowQFPRegs:sub_odd -> FPRegs
540 13, // LowQFPRegs:sub_odd64 -> LowDFPRegs
541 4, // LowQFPRegs:sub_odd64_then_sub_even -> FPRegs
542 4, // LowQFPRegs:sub_odd64_then_sub_odd -> FPRegs
543 },
544
545 };
546 assert(RC && "Missing regclass");
547 if (!Idx) return RC;
548 --Idx;
549 assert(Idx < 6 && "Bad subreg");
550 unsigned TV = Table[RC->getID()][Idx];
551 return TV ? getRegClass(i: TV - 1) : nullptr;
552}/// Get the weight in units of pressure for this register class.
553const RegClassWeight &SparcGenRegisterInfo::
554getRegClassWeight(const TargetRegisterClass *RC) const {
555 static const RegClassWeight RCWeightTable[] = {
556 {.RegWeight: 1, .WeightLimit: 4}, // FCCRegs
557 {.RegWeight: 1, .WeightLimit: 1}, // ASRRegs
558 {.RegWeight: 0, .WeightLimit: 0}, // CoprocRegs
559 {.RegWeight: 1, .WeightLimit: 32}, // FPRegs
560 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
561 {.RegWeight: 1, .WeightLimit: 6}, // GPRIncomingArg
562 {.RegWeight: 1, .WeightLimit: 6}, // GPROutgoingArg
563 {.RegWeight: 2, .WeightLimit: 64}, // DFPRegs
564 {.RegWeight: 1, .WeightLimit: 32}, // I64Regs
565 {.RegWeight: 1, .WeightLimit: 17}, // PRRegs
566 {.RegWeight: 0, .WeightLimit: 0}, // CoprocPair
567 {.RegWeight: 2, .WeightLimit: 32}, // IntPair
568 {.RegWeight: 2, .WeightLimit: 32}, // LowDFPRegs
569 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPRIncomingArg
570 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPROutgoingArg
571 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPRIncomingArg
572 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPROutgoingArg
573 {.RegWeight: 1, .WeightLimit: 1}, // PRRegs_and_ASRRegs
574 {.RegWeight: 4, .WeightLimit: 64}, // QFPRegs
575 {.RegWeight: 4, .WeightLimit: 32}, // LowQFPRegs
576 };
577 return RCWeightTable[RC->getID()];
578}
579
580/// Get the weight in units of pressure for this register unit.
581unsigned SparcGenRegisterInfo::
582getRegUnitWeight(MCRegUnit RegUnit) const {
583 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
584 static const uint8_t RUWeightTable[] = {
585 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
586 return RUWeightTable[static_cast<unsigned>(RegUnit)];
587}
588
589
590// Get the number of dimensions of register pressure.
591unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
592 return 8;
593}
594
595// Get the name of this register unit pressure set.
596const char *SparcGenRegisterInfo::
597getRegPressureSetName(unsigned Idx) const {
598 static const char *PressureNameTable[] = {
599 "PRRegs_and_ASRRegs",
600 "FCCRegs",
601 "GPRIncomingArg",
602 "GPROutgoingArg",
603 "PRRegs",
604 "FPRegs",
605 "IntRegs",
606 "DFPRegs",
607 };
608 return PressureNameTable[Idx];
609}
610
611// Get the register unit pressure limit for this dimension.
612// This limit must be adjusted dynamically for reserved registers.
613unsigned SparcGenRegisterInfo::
614getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
615 static const uint8_t PressureLimitTable[] = {
616 1, // 0: PRRegs_and_ASRRegs
617 4, // 1: FCCRegs
618 6, // 2: GPRIncomingArg
619 6, // 3: GPROutgoingArg
620 17, // 4: PRRegs
621 32, // 5: FPRegs
622 32, // 6: IntRegs
623 64, // 7: DFPRegs
624 };
625 return PressureLimitTable[Idx];
626}
627
628/// Get the register class for this pressure set with the largest
629/// `RegClassWeight::WeightLimit`.
630const TargetRegisterClass *SparcGenRegisterInfo::
631getLargestRegClassForRegPressureSet(unsigned Idx) const {
632 static const uint8_t PSetRegClassTable[] = {
633 SP::PRRegs_and_ASRRegsRegClassID, // 0: PRRegs_and_ASRRegs
634 SP::FCCRegsRegClassID, // 1: FCCRegs
635 SP::GPRIncomingArgRegClassID, // 2: GPRIncomingArg
636 SP::GPROutgoingArgRegClassID, // 3: GPROutgoingArg
637 SP::PRRegsRegClassID, // 4: PRRegs
638 SP::FPRegsRegClassID, // 5: FPRegs
639 SP::IntRegsRegClassID, // 6: IntRegs
640 SP::DFPRegsRegClassID, // 7: DFPRegs
641 };
642 return getRegClass(i: PSetRegClassTable[Idx]);
643}
644
645/// Table of pressure sets per register class or unit.
646static const int RCSetsTable[] = {
647 /* 0 */ 1, -1,
648 /* 2 */ 0, 4, -1,
649 /* 5 */ 2, 6, -1,
650 /* 8 */ 3, 6, -1,
651 /* 11 */ 5, 7, -1,
652};
653
654/// Get the dimensions of register pressure impacted by this register class.
655/// Returns a -1 terminated array of pressure set IDs
656const int *SparcGenRegisterInfo::
657getRegClassPressureSets(const TargetRegisterClass *RC) const {
658 static const uint8_t RCSetStartTable[] = {
659 0,1,1,11,6,5,8,12,6,3,1,6,11,5,8,5,8,2,12,11,};
660 return &RCSetsTable[RCSetStartTable[RC->getID()]];
661}
662
663/// Get the dimensions of register pressure impacted by this register unit.
664/// Returns a -1 terminated array of pressure set IDs
665const int *SparcGenRegisterInfo::
666getRegUnitPressureSets(MCRegUnit RegUnit) const {
667 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
668 static const uint8_t RUSetStartTable[] = {
669 3,3,3,1,1,3,1,1,3,1,3,3,1,3,3,1,2,3,3,3,3,3,3,1,3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,0,0,0,0,6,6,6,6,6,6,6,6,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,8,8,8,8,8,8,6,6,};
670 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
671}
672
673
674// Register to minimal register class mapping
675
676const TargetRegisterClass *SparcGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
677 static const uint16_t InvalidRegClassID = UINT16_MAX;
678
679 static const uint16_t Mapping[238] = {
680 InvalidRegClassID, // NoRegister
681 SP::PRRegsRegClassID, // CANRESTORE
682 SP::PRRegsRegClassID, // CANSAVE
683 SP::PRRegsRegClassID, // CLEANWIN
684 InvalidRegClassID, // CPQ
685 InvalidRegClassID, // CPSR
686 SP::PRRegsRegClassID, // CWP
687 InvalidRegClassID, // FQ
688 InvalidRegClassID, // FSR
689 SP::PRRegsRegClassID, // GL
690 InvalidRegClassID, // ICC
691 SP::PRRegsRegClassID, // OTHERWIN
692 SP::PRRegsRegClassID, // PIL
693 InvalidRegClassID, // PSR
694 SP::PRRegsRegClassID, // PSTATE
695 SP::PRRegsRegClassID, // TBA
696 InvalidRegClassID, // TBR
697 SP::PRRegs_and_ASRRegsRegClassID, // TICK
698 SP::PRRegsRegClassID, // TL
699 SP::PRRegsRegClassID, // TNPC
700 SP::PRRegsRegClassID, // TPC
701 SP::PRRegsRegClassID, // TSTATE
702 SP::PRRegsRegClassID, // TT
703 SP::PRRegsRegClassID, // VER
704 InvalidRegClassID, // WIM
705 SP::PRRegsRegClassID, // WSTATE
706 SP::ASRRegsRegClassID, // Y
707 SP::ASRRegsRegClassID, // ASR1
708 SP::ASRRegsRegClassID, // ASR2
709 SP::ASRRegsRegClassID, // ASR3
710 SP::ASRRegsRegClassID, // ASR4
711 SP::ASRRegsRegClassID, // ASR5
712 SP::ASRRegsRegClassID, // ASR6
713 SP::ASRRegsRegClassID, // ASR7
714 SP::ASRRegsRegClassID, // ASR8
715 SP::ASRRegsRegClassID, // ASR9
716 SP::ASRRegsRegClassID, // ASR10
717 SP::ASRRegsRegClassID, // ASR11
718 SP::ASRRegsRegClassID, // ASR12
719 SP::ASRRegsRegClassID, // ASR13
720 SP::ASRRegsRegClassID, // ASR14
721 SP::ASRRegsRegClassID, // ASR15
722 SP::ASRRegsRegClassID, // ASR16
723 SP::ASRRegsRegClassID, // ASR17
724 SP::ASRRegsRegClassID, // ASR18
725 SP::ASRRegsRegClassID, // ASR19
726 SP::ASRRegsRegClassID, // ASR20
727 SP::ASRRegsRegClassID, // ASR21
728 SP::ASRRegsRegClassID, // ASR22
729 SP::ASRRegsRegClassID, // ASR23
730 SP::ASRRegsRegClassID, // ASR24
731 SP::ASRRegsRegClassID, // ASR25
732 SP::ASRRegsRegClassID, // ASR26
733 SP::ASRRegsRegClassID, // ASR27
734 SP::ASRRegsRegClassID, // ASR28
735 SP::ASRRegsRegClassID, // ASR29
736 SP::ASRRegsRegClassID, // ASR30
737 SP::ASRRegsRegClassID, // ASR31
738 SP::CoprocRegsRegClassID, // C0
739 SP::CoprocRegsRegClassID, // C1
740 SP::CoprocRegsRegClassID, // C2
741 SP::CoprocRegsRegClassID, // C3
742 SP::CoprocRegsRegClassID, // C4
743 SP::CoprocRegsRegClassID, // C5
744 SP::CoprocRegsRegClassID, // C6
745 SP::CoprocRegsRegClassID, // C7
746 SP::CoprocRegsRegClassID, // C8
747 SP::CoprocRegsRegClassID, // C9
748 SP::CoprocRegsRegClassID, // C10
749 SP::CoprocRegsRegClassID, // C11
750 SP::CoprocRegsRegClassID, // C12
751 SP::CoprocRegsRegClassID, // C13
752 SP::CoprocRegsRegClassID, // C14
753 SP::CoprocRegsRegClassID, // C15
754 SP::CoprocRegsRegClassID, // C16
755 SP::CoprocRegsRegClassID, // C17
756 SP::CoprocRegsRegClassID, // C18
757 SP::CoprocRegsRegClassID, // C19
758 SP::CoprocRegsRegClassID, // C20
759 SP::CoprocRegsRegClassID, // C21
760 SP::CoprocRegsRegClassID, // C22
761 SP::CoprocRegsRegClassID, // C23
762 SP::CoprocRegsRegClassID, // C24
763 SP::CoprocRegsRegClassID, // C25
764 SP::CoprocRegsRegClassID, // C26
765 SP::CoprocRegsRegClassID, // C27
766 SP::CoprocRegsRegClassID, // C28
767 SP::CoprocRegsRegClassID, // C29
768 SP::CoprocRegsRegClassID, // C30
769 SP::CoprocRegsRegClassID, // C31
770 SP::LowDFPRegsRegClassID, // D0
771 SP::LowDFPRegsRegClassID, // D1
772 SP::LowDFPRegsRegClassID, // D2
773 SP::LowDFPRegsRegClassID, // D3
774 SP::LowDFPRegsRegClassID, // D4
775 SP::LowDFPRegsRegClassID, // D5
776 SP::LowDFPRegsRegClassID, // D6
777 SP::LowDFPRegsRegClassID, // D7
778 SP::LowDFPRegsRegClassID, // D8
779 SP::LowDFPRegsRegClassID, // D9
780 SP::LowDFPRegsRegClassID, // D10
781 SP::LowDFPRegsRegClassID, // D11
782 SP::LowDFPRegsRegClassID, // D12
783 SP::LowDFPRegsRegClassID, // D13
784 SP::LowDFPRegsRegClassID, // D14
785 SP::LowDFPRegsRegClassID, // D15
786 SP::DFPRegsRegClassID, // D16
787 SP::DFPRegsRegClassID, // D17
788 SP::DFPRegsRegClassID, // D18
789 SP::DFPRegsRegClassID, // D19
790 SP::DFPRegsRegClassID, // D20
791 SP::DFPRegsRegClassID, // D21
792 SP::DFPRegsRegClassID, // D22
793 SP::DFPRegsRegClassID, // D23
794 SP::DFPRegsRegClassID, // D24
795 SP::DFPRegsRegClassID, // D25
796 SP::DFPRegsRegClassID, // D26
797 SP::DFPRegsRegClassID, // D27
798 SP::DFPRegsRegClassID, // D28
799 SP::DFPRegsRegClassID, // D29
800 SP::DFPRegsRegClassID, // D30
801 SP::DFPRegsRegClassID, // D31
802 SP::FPRegsRegClassID, // F0
803 SP::FPRegsRegClassID, // F1
804 SP::FPRegsRegClassID, // F2
805 SP::FPRegsRegClassID, // F3
806 SP::FPRegsRegClassID, // F4
807 SP::FPRegsRegClassID, // F5
808 SP::FPRegsRegClassID, // F6
809 SP::FPRegsRegClassID, // F7
810 SP::FPRegsRegClassID, // F8
811 SP::FPRegsRegClassID, // F9
812 SP::FPRegsRegClassID, // F10
813 SP::FPRegsRegClassID, // F11
814 SP::FPRegsRegClassID, // F12
815 SP::FPRegsRegClassID, // F13
816 SP::FPRegsRegClassID, // F14
817 SP::FPRegsRegClassID, // F15
818 SP::FPRegsRegClassID, // F16
819 SP::FPRegsRegClassID, // F17
820 SP::FPRegsRegClassID, // F18
821 SP::FPRegsRegClassID, // F19
822 SP::FPRegsRegClassID, // F20
823 SP::FPRegsRegClassID, // F21
824 SP::FPRegsRegClassID, // F22
825 SP::FPRegsRegClassID, // F23
826 SP::FPRegsRegClassID, // F24
827 SP::FPRegsRegClassID, // F25
828 SP::FPRegsRegClassID, // F26
829 SP::FPRegsRegClassID, // F27
830 SP::FPRegsRegClassID, // F28
831 SP::FPRegsRegClassID, // F29
832 SP::FPRegsRegClassID, // F30
833 SP::FPRegsRegClassID, // F31
834 SP::FCCRegsRegClassID, // FCC0
835 SP::FCCRegsRegClassID, // FCC1
836 SP::FCCRegsRegClassID, // FCC2
837 SP::FCCRegsRegClassID, // FCC3
838 SP::I64RegsRegClassID, // G0
839 SP::I64RegsRegClassID, // G1
840 SP::I64RegsRegClassID, // G2
841 SP::I64RegsRegClassID, // G3
842 SP::I64RegsRegClassID, // G4
843 SP::I64RegsRegClassID, // G5
844 SP::I64RegsRegClassID, // G6
845 SP::I64RegsRegClassID, // G7
846 SP::I64Regs_and_GPRIncomingArgRegClassID, // I0
847 SP::I64Regs_and_GPRIncomingArgRegClassID, // I1
848 SP::I64Regs_and_GPRIncomingArgRegClassID, // I2
849 SP::I64Regs_and_GPRIncomingArgRegClassID, // I3
850 SP::I64Regs_and_GPRIncomingArgRegClassID, // I4
851 SP::I64Regs_and_GPRIncomingArgRegClassID, // I5
852 SP::I64RegsRegClassID, // I6
853 SP::I64RegsRegClassID, // I7
854 SP::I64RegsRegClassID, // L0
855 SP::I64RegsRegClassID, // L1
856 SP::I64RegsRegClassID, // L2
857 SP::I64RegsRegClassID, // L3
858 SP::I64RegsRegClassID, // L4
859 SP::I64RegsRegClassID, // L5
860 SP::I64RegsRegClassID, // L6
861 SP::I64RegsRegClassID, // L7
862 SP::I64Regs_and_GPROutgoingArgRegClassID, // O0
863 SP::I64Regs_and_GPROutgoingArgRegClassID, // O1
864 SP::I64Regs_and_GPROutgoingArgRegClassID, // O2
865 SP::I64Regs_and_GPROutgoingArgRegClassID, // O3
866 SP::I64Regs_and_GPROutgoingArgRegClassID, // O4
867 SP::I64Regs_and_GPROutgoingArgRegClassID, // O5
868 SP::I64RegsRegClassID, // O6
869 SP::I64RegsRegClassID, // O7
870 SP::LowQFPRegsRegClassID, // Q0
871 SP::LowQFPRegsRegClassID, // Q1
872 SP::LowQFPRegsRegClassID, // Q2
873 SP::LowQFPRegsRegClassID, // Q3
874 SP::LowQFPRegsRegClassID, // Q4
875 SP::LowQFPRegsRegClassID, // Q5
876 SP::LowQFPRegsRegClassID, // Q6
877 SP::LowQFPRegsRegClassID, // Q7
878 SP::QFPRegsRegClassID, // Q8
879 SP::QFPRegsRegClassID, // Q9
880 SP::QFPRegsRegClassID, // Q10
881 SP::QFPRegsRegClassID, // Q11
882 SP::QFPRegsRegClassID, // Q12
883 SP::QFPRegsRegClassID, // Q13
884 SP::QFPRegsRegClassID, // Q14
885 SP::QFPRegsRegClassID, // Q15
886 SP::CoprocPairRegClassID, // C0_C1
887 SP::CoprocPairRegClassID, // C2_C3
888 SP::CoprocPairRegClassID, // C4_C5
889 SP::CoprocPairRegClassID, // C6_C7
890 SP::CoprocPairRegClassID, // C8_C9
891 SP::CoprocPairRegClassID, // C10_C11
892 SP::CoprocPairRegClassID, // C12_C13
893 SP::CoprocPairRegClassID, // C14_C15
894 SP::CoprocPairRegClassID, // C16_C17
895 SP::CoprocPairRegClassID, // C18_C19
896 SP::CoprocPairRegClassID, // C20_C21
897 SP::CoprocPairRegClassID, // C22_C23
898 SP::CoprocPairRegClassID, // C24_C25
899 SP::CoprocPairRegClassID, // C26_C27
900 SP::CoprocPairRegClassID, // C28_C29
901 SP::CoprocPairRegClassID, // C30_C31
902 SP::IntPairRegClassID, // G0_G1
903 SP::IntPairRegClassID, // G2_G3
904 SP::IntPairRegClassID, // G4_G5
905 SP::IntPairRegClassID, // G6_G7
906 SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, // I0_I1
907 SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, // I2_I3
908 SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, // I4_I5
909 SP::IntPairRegClassID, // I6_I7
910 SP::IntPairRegClassID, // L0_L1
911 SP::IntPairRegClassID, // L2_L3
912 SP::IntPairRegClassID, // L4_L5
913 SP::IntPairRegClassID, // L6_L7
914 SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, // O0_O1
915 SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, // O2_O3
916 SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, // O4_O5
917 SP::IntPairRegClassID, // O6_O7
918 };
919
920 assert(Reg < ArrayRef(Mapping).size());
921 unsigned RCID = Mapping[Reg.id()];
922 if (RCID == InvalidRegClassID)
923 return nullptr;
924 return &SparcMCRegisterClassStorage.Classes[RCID];
925}
926extern const MCRegisterDesc SparcRegDesc[];
927extern const int16_t SparcRegDiffLists[];
928extern const LaneBitmask SparcLaneMaskLists[];
929extern const char SparcRegStrings[];
930extern const char SparcRegClassStrings[];
931extern const MCPhysReg SparcRegUnitRoots[][2];
932extern const uint16_t SparcSubRegIdxLists[];
933extern const uint16_t SparcRegEncodingTable[];
934// SP Dwarf<->LLVM register mappings.
935extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
936extern const unsigned SPDwarfFlavour0Dwarf2LSize;
937
938extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
939extern const unsigned SPEHFlavour0Dwarf2LSize;
940
941extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
942extern const unsigned SPDwarfFlavour0L2DwarfSize;
943
944extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
945extern const unsigned SPEHFlavour0L2DwarfSize;
946
947
948SparcGenRegisterInfo::
949SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
950 unsigned PC, unsigned HwMode)
951 : TargetRegisterInfo(&SparcRegInfoDesc,
952 SparcSubRegIndexStrings, SparcSubRegIndexNameOffsets,
953 SparcSubRegIdxRangeTable, SparcSubRegIndexLaneMaskTable,
954
955 LaneBitmask(0xFFFFFFFFFFFFFFFF), SparcRegClassInfos, SparcVTLists, HwMode) {
956 InitMCRegisterInfo(D: SparcRegDesc, NR: 238, RA, PC,
957 C: &getSparcMCRegisterClass(RC: 0), NC: 20, RURoots: SparcRegUnitRoots, NRU: 173, DL: SparcRegDiffLists,
958 RUMS: SparcLaneMaskLists, Strings: SparcRegStrings, ClassStrings: SparcRegClassStrings, SubIndices: SparcSubRegIdxLists, NumIndices: 7,
959 RET: SparcRegEncodingTable, RUI: nullptr);
960
961 switch (DwarfFlavour) {
962 default:
963 llvm_unreachable("Unknown DWARF flavour");
964 case 0:
965 mapDwarfRegsToLLVMRegs(Map: SPDwarfFlavour0Dwarf2L, Size: SPDwarfFlavour0Dwarf2LSize, isEH: false);
966 break;
967 }
968 switch (EHFlavour) {
969 default:
970 llvm_unreachable("Unknown DWARF flavour");
971 case 0:
972 mapDwarfRegsToLLVMRegs(Map: SPEHFlavour0Dwarf2L, Size: SPEHFlavour0Dwarf2LSize, isEH: true);
973 break;
974 }
975 switch (DwarfFlavour) {
976 default:
977 llvm_unreachable("Unknown DWARF flavour");
978 case 0:
979 mapLLVMRegsToDwarfRegs(Map: SPDwarfFlavour0L2Dwarf, Size: SPDwarfFlavour0L2DwarfSize, isEH: false);
980 break;
981 }
982 switch (EHFlavour) {
983 default:
984 llvm_unreachable("Unknown DWARF flavour");
985 case 0:
986 mapLLVMRegsToDwarfRegs(Map: SPEHFlavour0L2Dwarf, Size: SPEHFlavour0L2DwarfSize, isEH: true);
987 break;
988 }
989}
990
991static const MCPhysReg CSR_SaveList[] = { 0 };
992static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x103fffc0, 0x00000000, 0x000003fc, };
993static const MCPhysReg RTCSR_SaveList[] = { 0 };
994static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00003000, 0x00000000, 0x00000020, };
995
996
997ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
998 static const uint32_t *const Masks[] = {
999 CSR_RegMask,
1000 RTCSR_RegMask,
1001 };
1002 return ArrayRef(Masks);
1003}
1004
1005bool SparcGenRegisterInfo::
1006isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1007 return
1008 false;
1009}
1010
1011bool SparcGenRegisterInfo::
1012isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1013 return
1014 false;
1015}
1016
1017bool SparcGenRegisterInfo::
1018isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1019 return
1020 false;
1021}
1022
1023bool SparcGenRegisterInfo::
1024isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1025 return
1026 false;
1027}
1028
1029bool SparcGenRegisterInfo::
1030isConstantPhysReg(MCRegister PhysReg) const {
1031 return
1032 PhysReg == SP::G0 ||
1033 false;
1034}
1035
1036ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
1037 static const char *Names[] = {
1038 "CSR",
1039 "RTCSR",
1040 };
1041 return ArrayRef(Names);
1042}
1043
1044const SparcFrameLowering *
1045SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1046 return static_cast<const SparcFrameLowering *>(
1047 MF.getSubtarget().getFrameLowering());
1048}
1049
1050
1051} // namespace llvm
1052