1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass SparcMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i1, MVT::Other,
15 /* 2 */ MVT::i32, MVT::Other,
16 /* 4 */ MVT::i32, MVT::i64, MVT::Other,
17 /* 7 */ MVT::f32, MVT::Other,
18 /* 9 */ MVT::f64, MVT::Other,
19 /* 11 */ MVT::f128, MVT::Other,
20 /* 13 */ MVT::v2i32, MVT::Other,
21};
22
23#ifdef __GNUC__
24#pragma GCC diagnostic push
25#pragma GCC diagnostic ignored "-Woverlength-strings"
26#endif
27static constexpr char SparcSubRegIndexStrings[] = {
28 /* 0 */ "sub_odd64\000"
29 /* 10 */ "sub_even64\000"
30 /* 21 */ "sub_odd64_then_sub_odd\000"
31 /* 44 */ "sub_odd64_then_sub_even\000"
32};
33#ifdef __GNUC__
34#pragma GCC diagnostic pop
35#endif
36
37
38static constexpr uint32_t SparcSubRegIndexNameOffsets[] = {
39 59,
40 10,
41 36,
42 0,
43 44,
44 21,
45};
46
47static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
48 { .Offset: 65535, .Size: 65535 },
49 { .Offset: 0, .Size: 32 }, // sub_even
50 { .Offset: 0, .Size: 64 }, // sub_even64
51 { .Offset: 32, .Size: 32 }, // sub_odd
52 { .Offset: 64, .Size: 64 }, // sub_odd64
53 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
54 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
55 { .Offset: 65535, .Size: 65535 },
56 { .Offset: 0, .Size: 32 }, // sub_even
57 { .Offset: 0, .Size: 64 }, // sub_even64
58 { .Offset: 32, .Size: 32 }, // sub_odd
59 { .Offset: 64, .Size: 64 }, // sub_odd64
60 { .Offset: 64, .Size: 32 }, // sub_odd64_then_sub_even
61 { .Offset: 96, .Size: 32 }, // sub_odd64_then_sub_odd
62};
63
64
65static const LaneBitmask SubRegIndexLaneMaskTable[] = {
66 LaneBitmask::getAll(),
67 LaneBitmask(0x0000000000000001), // sub_even
68 LaneBitmask(0x0000000000000003), // sub_even64
69 LaneBitmask(0x0000000000000002), // sub_odd
70 LaneBitmask(0x000000000000000C), // sub_odd64
71 LaneBitmask(0x0000000000000004), // sub_odd64_then_sub_even
72 LaneBitmask(0x0000000000000008), // sub_odd64_then_sub_odd
73 };
74
75
76
77static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
78 // Mode = 0 (DefaultMode)
79 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*VTLists+*/.VTListOffset: 0 }, // FCCRegs
80 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // ASRRegs
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CoprocRegs
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 7 }, // FPRegs
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // IntRegs
84 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
85 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
86 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 9 }, // DFPRegs
87 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs
88 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // PRRegs
89 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // CoprocPair
90 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair
91 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 9 }, // LowDFPRegs
92 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
93 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
94 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
95 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
96 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
97 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // QFPRegs
98 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // LowQFPRegs
99 // Mode = 1 (SPARC64)
100 { .RegSize: 1, .SpillSize: 1, .SpillAlignment: 1, /*VTLists+*/.VTListOffset: 0 }, // FCCRegs
101 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // ASRRegs
102 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 2 }, // CoprocRegs
103 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 7 }, // FPRegs
104 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // IntRegs
105 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GPRIncomingArg
106 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // GPROutgoingArg
107 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 9 }, // DFPRegs
108 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs
109 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // PRRegs
110 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // CoprocPair
111 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair
112 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 9 }, // LowDFPRegs
113 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPRIncomingArg
114 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // I64Regs_and_GPROutgoingArg
115 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPRIncomingArg
116 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 13 }, // IntPair_with_sub_even_in_GPROutgoingArg
117 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 5 }, // PRRegs_and_ASRRegs
118 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // QFPRegs
119 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // LowQFPRegs
120};
121static const uint32_t FCCRegsSubClassMask[] = {
122 0x00000001,
123};
124
125static const uint32_t ASRRegsSubClassMask[] = {
126 0x00020002,
127};
128
129static const uint32_t CoprocRegsSubClassMask[] = {
130 0x00000004,
131 0x00000400, // sub_even
132 0x00000400, // sub_odd
133};
134
135static const uint32_t FPRegsSubClassMask[] = {
136 0x00000008,
137 0x00081000, // sub_even
138 0x00081000, // sub_odd
139 0x00080000, // sub_odd64_then_sub_even
140 0x00080000, // sub_odd64_then_sub_odd
141};
142
143static const uint32_t IntRegsSubClassMask[] = {
144 0x00006170,
145 0x00018800, // sub_even
146 0x00018800, // sub_odd
147};
148
149static const uint32_t GPRIncomingArgSubClassMask[] = {
150 0x00002020,
151 0x00008000, // sub_even
152 0x00008000, // sub_odd
153};
154
155static const uint32_t GPROutgoingArgSubClassMask[] = {
156 0x00004040,
157 0x00010000, // sub_even
158 0x00010000, // sub_odd
159};
160
161static const uint32_t DFPRegsSubClassMask[] = {
162 0x00001080,
163 0x000c0000, // sub_even64
164 0x000c0000, // sub_odd64
165};
166
167static const uint32_t I64RegsSubClassMask[] = {
168 0x00006100,
169 0x00018800, // sub_even
170 0x00018800, // sub_odd
171};
172
173static const uint32_t PRRegsSubClassMask[] = {
174 0x00020200,
175};
176
177static const uint32_t CoprocPairSubClassMask[] = {
178 0x00000400,
179};
180
181static const uint32_t IntPairSubClassMask[] = {
182 0x00018800,
183};
184
185static const uint32_t LowDFPRegsSubClassMask[] = {
186 0x00001000,
187 0x00080000, // sub_even64
188 0x00080000, // sub_odd64
189};
190
191static const uint32_t I64Regs_and_GPRIncomingArgSubClassMask[] = {
192 0x00002000,
193 0x00008000, // sub_even
194 0x00008000, // sub_odd
195};
196
197static const uint32_t I64Regs_and_GPROutgoingArgSubClassMask[] = {
198 0x00004000,
199 0x00010000, // sub_even
200 0x00010000, // sub_odd
201};
202
203static const uint32_t IntPair_with_sub_even_in_GPRIncomingArgSubClassMask[] = {
204 0x00008000,
205};
206
207static const uint32_t IntPair_with_sub_even_in_GPROutgoingArgSubClassMask[] = {
208 0x00010000,
209};
210
211static const uint32_t PRRegs_and_ASRRegsSubClassMask[] = {
212 0x00020000,
213};
214
215static const uint32_t QFPRegsSubClassMask[] = {
216 0x000c0000,
217};
218
219static const uint32_t LowQFPRegsSubClassMask[] = {
220 0x00080000,
221};
222
223static const uint16_t SuperRegIdxSeqs[] = {
224 /* 0 */ 1, 3, 0,
225 /* 3 */ 2, 4, 0,
226 /* 6 */ 1, 3, 5, 6, 0,
227};
228
229static unsigned const GPRIncomingArgSuperclasses[] = {
230 SP::IntRegsRegClassID,
231};
232
233static unsigned const GPROutgoingArgSuperclasses[] = {
234 SP::IntRegsRegClassID,
235};
236
237static unsigned const I64RegsSuperclasses[] = {
238 SP::IntRegsRegClassID,
239};
240
241static unsigned const LowDFPRegsSuperclasses[] = {
242 SP::DFPRegsRegClassID,
243};
244
245static unsigned const I64Regs_and_GPRIncomingArgSuperclasses[] = {
246 SP::IntRegsRegClassID,
247 SP::GPRIncomingArgRegClassID,
248 SP::I64RegsRegClassID,
249};
250
251static unsigned const I64Regs_and_GPROutgoingArgSuperclasses[] = {
252 SP::IntRegsRegClassID,
253 SP::GPROutgoingArgRegClassID,
254 SP::I64RegsRegClassID,
255};
256
257static unsigned const IntPair_with_sub_even_in_GPRIncomingArgSuperclasses[] = {
258 SP::IntPairRegClassID,
259};
260
261static unsigned const IntPair_with_sub_even_in_GPROutgoingArgSuperclasses[] = {
262 SP::IntPairRegClassID,
263};
264
265static unsigned const PRRegs_and_ASRRegsSuperclasses[] = {
266 SP::ASRRegsRegClassID,
267 SP::PRRegsRegClassID,
268};
269
270static unsigned const LowQFPRegsSuperclasses[] = {
271 SP::QFPRegsRegClassID,
272};
273
274namespace SP {
275
276// Register class instances
277 extern const TargetRegisterClass FCCRegsRegClass = {
278 .MC: &SparcMCRegisterClasses[FCCRegsRegClassID],
279 .SubClassMask: FCCRegsSubClassMask,
280 .SuperRegIndices: SuperRegIdxSeqs + 2,
281 .LaneMask: LaneBitmask(0x0000000000000001),
282 .AllocationPriority: 0,
283 .GlobalPriority: false,
284 .TSFlags: 0x00, /* TSFlags */
285 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
286 .CoveredBySubRegs: false, /* CoveredBySubRegs */
287 .SuperClasses: nullptr, .SuperClassesSize: 0,
288 .OrderFunc: nullptr
289 };
290
291 extern const TargetRegisterClass ASRRegsRegClass = {
292 .MC: &SparcMCRegisterClasses[ASRRegsRegClassID],
293 .SubClassMask: ASRRegsSubClassMask,
294 .SuperRegIndices: SuperRegIdxSeqs + 2,
295 .LaneMask: LaneBitmask(0x0000000000000001),
296 .AllocationPriority: 0,
297 .GlobalPriority: false,
298 .TSFlags: 0x00, /* TSFlags */
299 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
300 .CoveredBySubRegs: false, /* CoveredBySubRegs */
301 .SuperClasses: nullptr, .SuperClassesSize: 0,
302 .OrderFunc: nullptr
303 };
304
305 extern const TargetRegisterClass CoprocRegsRegClass = {
306 .MC: &SparcMCRegisterClasses[CoprocRegsRegClassID],
307 .SubClassMask: CoprocRegsSubClassMask,
308 .SuperRegIndices: SuperRegIdxSeqs + 0,
309 .LaneMask: LaneBitmask(0x0000000000000001),
310 .AllocationPriority: 0,
311 .GlobalPriority: false,
312 .TSFlags: 0x00, /* TSFlags */
313 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
314 .CoveredBySubRegs: false, /* CoveredBySubRegs */
315 .SuperClasses: nullptr, .SuperClassesSize: 0,
316 .OrderFunc: nullptr
317 };
318
319 extern const TargetRegisterClass FPRegsRegClass = {
320 .MC: &SparcMCRegisterClasses[FPRegsRegClassID],
321 .SubClassMask: FPRegsSubClassMask,
322 .SuperRegIndices: SuperRegIdxSeqs + 6,
323 .LaneMask: LaneBitmask(0x0000000000000001),
324 .AllocationPriority: 0,
325 .GlobalPriority: false,
326 .TSFlags: 0x00, /* TSFlags */
327 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
328 .CoveredBySubRegs: false, /* CoveredBySubRegs */
329 .SuperClasses: nullptr, .SuperClassesSize: 0,
330 .OrderFunc: nullptr
331 };
332
333 extern const TargetRegisterClass IntRegsRegClass = {
334 .MC: &SparcMCRegisterClasses[IntRegsRegClassID],
335 .SubClassMask: IntRegsSubClassMask,
336 .SuperRegIndices: SuperRegIdxSeqs + 0,
337 .LaneMask: LaneBitmask(0x0000000000000001),
338 .AllocationPriority: 0,
339 .GlobalPriority: false,
340 .TSFlags: 0x00, /* TSFlags */
341 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
342 .CoveredBySubRegs: false, /* CoveredBySubRegs */
343 .SuperClasses: nullptr, .SuperClassesSize: 0,
344 .OrderFunc: nullptr
345 };
346
347 extern const TargetRegisterClass GPRIncomingArgRegClass = {
348 .MC: &SparcMCRegisterClasses[GPRIncomingArgRegClassID],
349 .SubClassMask: GPRIncomingArgSubClassMask,
350 .SuperRegIndices: SuperRegIdxSeqs + 0,
351 .LaneMask: LaneBitmask(0x0000000000000001),
352 .AllocationPriority: 0,
353 .GlobalPriority: false,
354 .TSFlags: 0x00, /* TSFlags */
355 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
356 .CoveredBySubRegs: false, /* CoveredBySubRegs */
357 .SuperClasses: GPRIncomingArgSuperclasses, .SuperClassesSize: 1,
358 .OrderFunc: nullptr
359 };
360
361 extern const TargetRegisterClass GPROutgoingArgRegClass = {
362 .MC: &SparcMCRegisterClasses[GPROutgoingArgRegClassID],
363 .SubClassMask: GPROutgoingArgSubClassMask,
364 .SuperRegIndices: SuperRegIdxSeqs + 0,
365 .LaneMask: LaneBitmask(0x0000000000000001),
366 .AllocationPriority: 0,
367 .GlobalPriority: false,
368 .TSFlags: 0x00, /* TSFlags */
369 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
370 .CoveredBySubRegs: false, /* CoveredBySubRegs */
371 .SuperClasses: GPROutgoingArgSuperclasses, .SuperClassesSize: 1,
372 .OrderFunc: nullptr
373 };
374
375 extern const TargetRegisterClass DFPRegsRegClass = {
376 .MC: &SparcMCRegisterClasses[DFPRegsRegClassID],
377 .SubClassMask: DFPRegsSubClassMask,
378 .SuperRegIndices: SuperRegIdxSeqs + 3,
379 .LaneMask: LaneBitmask(0x0000000000000003),
380 .AllocationPriority: 0,
381 .GlobalPriority: false,
382 .TSFlags: 0x00, /* TSFlags */
383 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
384 .CoveredBySubRegs: false, /* CoveredBySubRegs */
385 .SuperClasses: nullptr, .SuperClassesSize: 0,
386 .OrderFunc: nullptr
387 };
388
389 extern const TargetRegisterClass I64RegsRegClass = {
390 .MC: &SparcMCRegisterClasses[I64RegsRegClassID],
391 .SubClassMask: I64RegsSubClassMask,
392 .SuperRegIndices: SuperRegIdxSeqs + 0,
393 .LaneMask: LaneBitmask(0x0000000000000001),
394 .AllocationPriority: 0,
395 .GlobalPriority: false,
396 .TSFlags: 0x00, /* TSFlags */
397 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
398 .CoveredBySubRegs: false, /* CoveredBySubRegs */
399 .SuperClasses: I64RegsSuperclasses, .SuperClassesSize: 1,
400 .OrderFunc: nullptr
401 };
402
403 extern const TargetRegisterClass PRRegsRegClass = {
404 .MC: &SparcMCRegisterClasses[PRRegsRegClassID],
405 .SubClassMask: PRRegsSubClassMask,
406 .SuperRegIndices: SuperRegIdxSeqs + 2,
407 .LaneMask: LaneBitmask(0x0000000000000001),
408 .AllocationPriority: 0,
409 .GlobalPriority: false,
410 .TSFlags: 0x00, /* TSFlags */
411 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
412 .CoveredBySubRegs: false, /* CoveredBySubRegs */
413 .SuperClasses: nullptr, .SuperClassesSize: 0,
414 .OrderFunc: nullptr
415 };
416
417 extern const TargetRegisterClass CoprocPairRegClass = {
418 .MC: &SparcMCRegisterClasses[CoprocPairRegClassID],
419 .SubClassMask: CoprocPairSubClassMask,
420 .SuperRegIndices: SuperRegIdxSeqs + 2,
421 .LaneMask: LaneBitmask(0x0000000000000003),
422 .AllocationPriority: 0,
423 .GlobalPriority: false,
424 .TSFlags: 0x00, /* TSFlags */
425 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
426 .CoveredBySubRegs: true, /* CoveredBySubRegs */
427 .SuperClasses: nullptr, .SuperClassesSize: 0,
428 .OrderFunc: nullptr
429 };
430
431 extern const TargetRegisterClass IntPairRegClass = {
432 .MC: &SparcMCRegisterClasses[IntPairRegClassID],
433 .SubClassMask: IntPairSubClassMask,
434 .SuperRegIndices: SuperRegIdxSeqs + 2,
435 .LaneMask: LaneBitmask(0x0000000000000003),
436 .AllocationPriority: 0,
437 .GlobalPriority: false,
438 .TSFlags: 0x00, /* TSFlags */
439 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
440 .CoveredBySubRegs: true, /* CoveredBySubRegs */
441 .SuperClasses: nullptr, .SuperClassesSize: 0,
442 .OrderFunc: nullptr
443 };
444
445 extern const TargetRegisterClass LowDFPRegsRegClass = {
446 .MC: &SparcMCRegisterClasses[LowDFPRegsRegClassID],
447 .SubClassMask: LowDFPRegsSubClassMask,
448 .SuperRegIndices: SuperRegIdxSeqs + 3,
449 .LaneMask: LaneBitmask(0x0000000000000003),
450 .AllocationPriority: 0,
451 .GlobalPriority: false,
452 .TSFlags: 0x00, /* TSFlags */
453 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
454 .CoveredBySubRegs: true, /* CoveredBySubRegs */
455 .SuperClasses: LowDFPRegsSuperclasses, .SuperClassesSize: 1,
456 .OrderFunc: nullptr
457 };
458
459 extern const TargetRegisterClass I64Regs_and_GPRIncomingArgRegClass = {
460 .MC: &SparcMCRegisterClasses[I64Regs_and_GPRIncomingArgRegClassID],
461 .SubClassMask: I64Regs_and_GPRIncomingArgSubClassMask,
462 .SuperRegIndices: SuperRegIdxSeqs + 0,
463 .LaneMask: LaneBitmask(0x0000000000000001),
464 .AllocationPriority: 0,
465 .GlobalPriority: false,
466 .TSFlags: 0x00, /* TSFlags */
467 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
468 .CoveredBySubRegs: false, /* CoveredBySubRegs */
469 .SuperClasses: I64Regs_and_GPRIncomingArgSuperclasses, .SuperClassesSize: 3,
470 .OrderFunc: nullptr
471 };
472
473 extern const TargetRegisterClass I64Regs_and_GPROutgoingArgRegClass = {
474 .MC: &SparcMCRegisterClasses[I64Regs_and_GPROutgoingArgRegClassID],
475 .SubClassMask: I64Regs_and_GPROutgoingArgSubClassMask,
476 .SuperRegIndices: SuperRegIdxSeqs + 0,
477 .LaneMask: LaneBitmask(0x0000000000000001),
478 .AllocationPriority: 0,
479 .GlobalPriority: false,
480 .TSFlags: 0x00, /* TSFlags */
481 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
482 .CoveredBySubRegs: false, /* CoveredBySubRegs */
483 .SuperClasses: I64Regs_and_GPROutgoingArgSuperclasses, .SuperClassesSize: 3,
484 .OrderFunc: nullptr
485 };
486
487 extern const TargetRegisterClass IntPair_with_sub_even_in_GPRIncomingArgRegClass = {
488 .MC: &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPRIncomingArgRegClassID],
489 .SubClassMask: IntPair_with_sub_even_in_GPRIncomingArgSubClassMask,
490 .SuperRegIndices: SuperRegIdxSeqs + 2,
491 .LaneMask: LaneBitmask(0x0000000000000003),
492 .AllocationPriority: 0,
493 .GlobalPriority: false,
494 .TSFlags: 0x00, /* TSFlags */
495 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
496 .CoveredBySubRegs: true, /* CoveredBySubRegs */
497 .SuperClasses: IntPair_with_sub_even_in_GPRIncomingArgSuperclasses, .SuperClassesSize: 1,
498 .OrderFunc: nullptr
499 };
500
501 extern const TargetRegisterClass IntPair_with_sub_even_in_GPROutgoingArgRegClass = {
502 .MC: &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPROutgoingArgRegClassID],
503 .SubClassMask: IntPair_with_sub_even_in_GPROutgoingArgSubClassMask,
504 .SuperRegIndices: SuperRegIdxSeqs + 2,
505 .LaneMask: LaneBitmask(0x0000000000000003),
506 .AllocationPriority: 0,
507 .GlobalPriority: false,
508 .TSFlags: 0x00, /* TSFlags */
509 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
510 .CoveredBySubRegs: true, /* CoveredBySubRegs */
511 .SuperClasses: IntPair_with_sub_even_in_GPROutgoingArgSuperclasses, .SuperClassesSize: 1,
512 .OrderFunc: nullptr
513 };
514
515 extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass = {
516 .MC: &SparcMCRegisterClasses[PRRegs_and_ASRRegsRegClassID],
517 .SubClassMask: PRRegs_and_ASRRegsSubClassMask,
518 .SuperRegIndices: SuperRegIdxSeqs + 2,
519 .LaneMask: LaneBitmask(0x0000000000000001),
520 .AllocationPriority: 0,
521 .GlobalPriority: false,
522 .TSFlags: 0x00, /* TSFlags */
523 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
524 .CoveredBySubRegs: false, /* CoveredBySubRegs */
525 .SuperClasses: PRRegs_and_ASRRegsSuperclasses, .SuperClassesSize: 2,
526 .OrderFunc: nullptr
527 };
528
529 extern const TargetRegisterClass QFPRegsRegClass = {
530 .MC: &SparcMCRegisterClasses[QFPRegsRegClassID],
531 .SubClassMask: QFPRegsSubClassMask,
532 .SuperRegIndices: SuperRegIdxSeqs + 2,
533 .LaneMask: LaneBitmask(0x000000000000000F),
534 .AllocationPriority: 0,
535 .GlobalPriority: false,
536 .TSFlags: 0x00, /* TSFlags */
537 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
538 .CoveredBySubRegs: true, /* CoveredBySubRegs */
539 .SuperClasses: nullptr, .SuperClassesSize: 0,
540 .OrderFunc: nullptr
541 };
542
543 extern const TargetRegisterClass LowQFPRegsRegClass = {
544 .MC: &SparcMCRegisterClasses[LowQFPRegsRegClassID],
545 .SubClassMask: LowQFPRegsSubClassMask,
546 .SuperRegIndices: SuperRegIdxSeqs + 2,
547 .LaneMask: LaneBitmask(0x000000000000000F),
548 .AllocationPriority: 0,
549 .GlobalPriority: false,
550 .TSFlags: 0x00, /* TSFlags */
551 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
552 .CoveredBySubRegs: true, /* CoveredBySubRegs */
553 .SuperClasses: LowQFPRegsSuperclasses, .SuperClassesSize: 1,
554 .OrderFunc: nullptr
555 };
556
557
558} // namespace SP
559namespace {
560
561 const TargetRegisterClass *const RegisterClasses[] = {
562 &SP::FCCRegsRegClass,
563 &SP::ASRRegsRegClass,
564 &SP::CoprocRegsRegClass,
565 &SP::FPRegsRegClass,
566 &SP::IntRegsRegClass,
567 &SP::GPRIncomingArgRegClass,
568 &SP::GPROutgoingArgRegClass,
569 &SP::DFPRegsRegClass,
570 &SP::I64RegsRegClass,
571 &SP::PRRegsRegClass,
572 &SP::CoprocPairRegClass,
573 &SP::IntPairRegClass,
574 &SP::LowDFPRegsRegClass,
575 &SP::I64Regs_and_GPRIncomingArgRegClass,
576 &SP::I64Regs_and_GPROutgoingArgRegClass,
577 &SP::IntPair_with_sub_even_in_GPRIncomingArgRegClass,
578 &SP::IntPair_with_sub_even_in_GPROutgoingArgRegClass,
579 &SP::PRRegs_and_ASRRegsRegClass,
580 &SP::QFPRegsRegClass,
581 &SP::LowQFPRegsRegClass,
582 };
583} // namespace
584
585static const uint8_t CostPerUseTable[] = {
5860, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
587
588
589static const bool InAllocatableClassTable[] = {
590false, true, true, true, false, false, true, false, false, true, false, true, true, false, true, true, false, true, true, true, true, true, true, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
591
592
593static const TargetRegisterInfoDesc SparcRegInfoDesc = { // Extra Descriptors
594.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
595
596unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
597 static const uint8_t RowMap[6] = {
598 0, 0, 0, 1, 0, 0,
599 };
600 static const uint8_t Rows[2][6] = {
601 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
602 { SP::sub_odd64_then_sub_even, 0, SP::sub_odd64_then_sub_odd, 0, 0, 0, },
603 };
604
605 --IdxA; assert(IdxA < 6); (void) IdxA;
606 --IdxB; assert(IdxB < 6);
607 return Rows[RowMap[IdxA]][IdxB];
608}
609
610unsigned SparcGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
611 static const uint8_t Table[6][6] = {
612 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
613 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
614 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
615 { 0, 0, 0, 0, SP::sub_even, SP::sub_odd, },
616 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
617 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
618 };
619
620 --IdxA; assert(IdxA < 6);
621 --IdxB; assert(IdxB < 6);
622 return Table[IdxA][IdxB];
623 }
624
625 struct MaskRolOp {
626 LaneBitmask Mask;
627 uint8_t RotateLeft;
628 };
629 static const MaskRolOp LaneMaskComposeSequences[] = {
630 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
631 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
632 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
633 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 6
634 };
635 static const uint8_t CompositeSequences[] = {
636 0, // to sub_even
637 0, // to sub_even64
638 2, // to sub_odd
639 4, // to sub_odd64
640 4, // to sub_odd64_then_sub_even
641 6 // to sub_odd64_then_sub_odd
642 };
643
644LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
645 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
646 LaneBitmask Result;
647 for (const MaskRolOp *Ops =
648 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
649 Ops->Mask.any(); ++Ops) {
650 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
651 if (unsigned S = Ops->RotateLeft)
652 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
653 else
654 Result |= LaneBitmask(M);
655 }
656 return Result;
657}
658
659LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
660 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
661 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
662 LaneBitmask Result;
663 for (const MaskRolOp *Ops =
664 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
665 Ops->Mask.any(); ++Ops) {
666 LaneBitmask::Type M = LaneMask.getAsInteger();
667 if (unsigned S = Ops->RotateLeft)
668 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
669 else
670 Result |= LaneBitmask(M);
671 }
672 return Result;
673}
674
675const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
676 static constexpr uint8_t Table[20][6] = {
677 { // FCCRegs
678 0, // sub_even
679 0, // sub_even64
680 0, // sub_odd
681 0, // sub_odd64
682 0, // sub_odd64_then_sub_even
683 0, // sub_odd64_then_sub_odd
684 },
685 { // ASRRegs
686 0, // sub_even
687 0, // sub_even64
688 0, // sub_odd
689 0, // sub_odd64
690 0, // sub_odd64_then_sub_even
691 0, // sub_odd64_then_sub_odd
692 },
693 { // CoprocRegs
694 0, // sub_even
695 0, // sub_even64
696 0, // sub_odd
697 0, // sub_odd64
698 0, // sub_odd64_then_sub_even
699 0, // sub_odd64_then_sub_odd
700 },
701 { // FPRegs
702 0, // sub_even
703 0, // sub_even64
704 0, // sub_odd
705 0, // sub_odd64
706 0, // sub_odd64_then_sub_even
707 0, // sub_odd64_then_sub_odd
708 },
709 { // IntRegs
710 0, // sub_even
711 0, // sub_even64
712 0, // sub_odd
713 0, // sub_odd64
714 0, // sub_odd64_then_sub_even
715 0, // sub_odd64_then_sub_odd
716 },
717 { // GPRIncomingArg
718 0, // sub_even
719 0, // sub_even64
720 0, // sub_odd
721 0, // sub_odd64
722 0, // sub_odd64_then_sub_even
723 0, // sub_odd64_then_sub_odd
724 },
725 { // GPROutgoingArg
726 0, // sub_even
727 0, // sub_even64
728 0, // sub_odd
729 0, // sub_odd64
730 0, // sub_odd64_then_sub_even
731 0, // sub_odd64_then_sub_odd
732 },
733 { // DFPRegs
734 13, // sub_even -> LowDFPRegs
735 0, // sub_even64
736 13, // sub_odd -> LowDFPRegs
737 0, // sub_odd64
738 0, // sub_odd64_then_sub_even
739 0, // sub_odd64_then_sub_odd
740 },
741 { // I64Regs
742 0, // sub_even
743 0, // sub_even64
744 0, // sub_odd
745 0, // sub_odd64
746 0, // sub_odd64_then_sub_even
747 0, // sub_odd64_then_sub_odd
748 },
749 { // PRRegs
750 0, // sub_even
751 0, // sub_even64
752 0, // sub_odd
753 0, // sub_odd64
754 0, // sub_odd64_then_sub_even
755 0, // sub_odd64_then_sub_odd
756 },
757 { // CoprocPair
758 11, // sub_even -> CoprocPair
759 0, // sub_even64
760 11, // sub_odd -> CoprocPair
761 0, // sub_odd64
762 0, // sub_odd64_then_sub_even
763 0, // sub_odd64_then_sub_odd
764 },
765 { // IntPair
766 12, // sub_even -> IntPair
767 0, // sub_even64
768 12, // sub_odd -> IntPair
769 0, // sub_odd64
770 0, // sub_odd64_then_sub_even
771 0, // sub_odd64_then_sub_odd
772 },
773 { // LowDFPRegs
774 13, // sub_even -> LowDFPRegs
775 0, // sub_even64
776 13, // sub_odd -> LowDFPRegs
777 0, // sub_odd64
778 0, // sub_odd64_then_sub_even
779 0, // sub_odd64_then_sub_odd
780 },
781 { // I64Regs_and_GPRIncomingArg
782 0, // sub_even
783 0, // sub_even64
784 0, // sub_odd
785 0, // sub_odd64
786 0, // sub_odd64_then_sub_even
787 0, // sub_odd64_then_sub_odd
788 },
789 { // I64Regs_and_GPROutgoingArg
790 0, // sub_even
791 0, // sub_even64
792 0, // sub_odd
793 0, // sub_odd64
794 0, // sub_odd64_then_sub_even
795 0, // sub_odd64_then_sub_odd
796 },
797 { // IntPair_with_sub_even_in_GPRIncomingArg
798 16, // sub_even -> IntPair_with_sub_even_in_GPRIncomingArg
799 0, // sub_even64
800 16, // sub_odd -> IntPair_with_sub_even_in_GPRIncomingArg
801 0, // sub_odd64
802 0, // sub_odd64_then_sub_even
803 0, // sub_odd64_then_sub_odd
804 },
805 { // IntPair_with_sub_even_in_GPROutgoingArg
806 17, // sub_even -> IntPair_with_sub_even_in_GPROutgoingArg
807 0, // sub_even64
808 17, // sub_odd -> IntPair_with_sub_even_in_GPROutgoingArg
809 0, // sub_odd64
810 0, // sub_odd64_then_sub_even
811 0, // sub_odd64_then_sub_odd
812 },
813 { // PRRegs_and_ASRRegs
814 0, // sub_even
815 0, // sub_even64
816 0, // sub_odd
817 0, // sub_odd64
818 0, // sub_odd64_then_sub_even
819 0, // sub_odd64_then_sub_odd
820 },
821 { // QFPRegs
822 20, // sub_even -> LowQFPRegs
823 19, // sub_even64 -> QFPRegs
824 20, // sub_odd -> LowQFPRegs
825 19, // sub_odd64 -> QFPRegs
826 20, // sub_odd64_then_sub_even -> LowQFPRegs
827 20, // sub_odd64_then_sub_odd -> LowQFPRegs
828 },
829 { // LowQFPRegs
830 20, // sub_even -> LowQFPRegs
831 20, // sub_even64 -> LowQFPRegs
832 20, // sub_odd -> LowQFPRegs
833 20, // sub_odd64 -> LowQFPRegs
834 20, // sub_odd64_then_sub_even -> LowQFPRegs
835 20, // sub_odd64_then_sub_odd -> LowQFPRegs
836 },
837
838 };
839 assert(RC && "Missing regclass");
840 if (!Idx) return RC;
841 --Idx;
842 assert(Idx < 6 && "Bad subreg");
843 unsigned TV = Table[RC->getID()][Idx];
844 return TV ? getRegClass(i: TV - 1) : nullptr;
845}const TargetRegisterClass *SparcGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
846 static constexpr uint8_t Table[20][6] = {
847 { // FCCRegs
848 0, // FCCRegs:sub_even
849 0, // FCCRegs:sub_even64
850 0, // FCCRegs:sub_odd
851 0, // FCCRegs:sub_odd64
852 0, // FCCRegs:sub_odd64_then_sub_even
853 0, // FCCRegs:sub_odd64_then_sub_odd
854 },
855 { // ASRRegs
856 0, // ASRRegs:sub_even
857 0, // ASRRegs:sub_even64
858 0, // ASRRegs:sub_odd
859 0, // ASRRegs:sub_odd64
860 0, // ASRRegs:sub_odd64_then_sub_even
861 0, // ASRRegs:sub_odd64_then_sub_odd
862 },
863 { // CoprocRegs
864 0, // CoprocRegs:sub_even
865 0, // CoprocRegs:sub_even64
866 0, // CoprocRegs:sub_odd
867 0, // CoprocRegs:sub_odd64
868 0, // CoprocRegs:sub_odd64_then_sub_even
869 0, // CoprocRegs:sub_odd64_then_sub_odd
870 },
871 { // FPRegs
872 0, // FPRegs:sub_even
873 0, // FPRegs:sub_even64
874 0, // FPRegs:sub_odd
875 0, // FPRegs:sub_odd64
876 0, // FPRegs:sub_odd64_then_sub_even
877 0, // FPRegs:sub_odd64_then_sub_odd
878 },
879 { // IntRegs
880 0, // IntRegs:sub_even
881 0, // IntRegs:sub_even64
882 0, // IntRegs:sub_odd
883 0, // IntRegs:sub_odd64
884 0, // IntRegs:sub_odd64_then_sub_even
885 0, // IntRegs:sub_odd64_then_sub_odd
886 },
887 { // GPRIncomingArg
888 0, // GPRIncomingArg:sub_even
889 0, // GPRIncomingArg:sub_even64
890 0, // GPRIncomingArg:sub_odd
891 0, // GPRIncomingArg:sub_odd64
892 0, // GPRIncomingArg:sub_odd64_then_sub_even
893 0, // GPRIncomingArg:sub_odd64_then_sub_odd
894 },
895 { // GPROutgoingArg
896 0, // GPROutgoingArg:sub_even
897 0, // GPROutgoingArg:sub_even64
898 0, // GPROutgoingArg:sub_odd
899 0, // GPROutgoingArg:sub_odd64
900 0, // GPROutgoingArg:sub_odd64_then_sub_even
901 0, // GPROutgoingArg:sub_odd64_then_sub_odd
902 },
903 { // DFPRegs
904 4, // DFPRegs:sub_even -> FPRegs
905 0, // DFPRegs:sub_even64
906 4, // DFPRegs:sub_odd -> FPRegs
907 0, // DFPRegs:sub_odd64
908 0, // DFPRegs:sub_odd64_then_sub_even
909 0, // DFPRegs:sub_odd64_then_sub_odd
910 },
911 { // I64Regs
912 0, // I64Regs:sub_even
913 0, // I64Regs:sub_even64
914 0, // I64Regs:sub_odd
915 0, // I64Regs:sub_odd64
916 0, // I64Regs:sub_odd64_then_sub_even
917 0, // I64Regs:sub_odd64_then_sub_odd
918 },
919 { // PRRegs
920 0, // PRRegs:sub_even
921 0, // PRRegs:sub_even64
922 0, // PRRegs:sub_odd
923 0, // PRRegs:sub_odd64
924 0, // PRRegs:sub_odd64_then_sub_even
925 0, // PRRegs:sub_odd64_then_sub_odd
926 },
927 { // CoprocPair
928 3, // CoprocPair:sub_even -> CoprocRegs
929 0, // CoprocPair:sub_even64
930 3, // CoprocPair:sub_odd -> CoprocRegs
931 0, // CoprocPair:sub_odd64
932 0, // CoprocPair:sub_odd64_then_sub_even
933 0, // CoprocPair:sub_odd64_then_sub_odd
934 },
935 { // IntPair
936 9, // IntPair:sub_even -> I64Regs
937 0, // IntPair:sub_even64
938 9, // IntPair:sub_odd -> I64Regs
939 0, // IntPair:sub_odd64
940 0, // IntPair:sub_odd64_then_sub_even
941 0, // IntPair:sub_odd64_then_sub_odd
942 },
943 { // LowDFPRegs
944 4, // LowDFPRegs:sub_even -> FPRegs
945 0, // LowDFPRegs:sub_even64
946 4, // LowDFPRegs:sub_odd -> FPRegs
947 0, // LowDFPRegs:sub_odd64
948 0, // LowDFPRegs:sub_odd64_then_sub_even
949 0, // LowDFPRegs:sub_odd64_then_sub_odd
950 },
951 { // I64Regs_and_GPRIncomingArg
952 0, // I64Regs_and_GPRIncomingArg:sub_even
953 0, // I64Regs_and_GPRIncomingArg:sub_even64
954 0, // I64Regs_and_GPRIncomingArg:sub_odd
955 0, // I64Regs_and_GPRIncomingArg:sub_odd64
956 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_even
957 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_odd
958 },
959 { // I64Regs_and_GPROutgoingArg
960 0, // I64Regs_and_GPROutgoingArg:sub_even
961 0, // I64Regs_and_GPROutgoingArg:sub_even64
962 0, // I64Regs_and_GPROutgoingArg:sub_odd
963 0, // I64Regs_and_GPROutgoingArg:sub_odd64
964 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_even
965 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_odd
966 },
967 { // IntPair_with_sub_even_in_GPRIncomingArg
968 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even -> I64Regs_and_GPRIncomingArg
969 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even64
970 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd -> I64Regs_and_GPRIncomingArg
971 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64
972 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_even
973 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_odd
974 },
975 { // IntPair_with_sub_even_in_GPROutgoingArg
976 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even -> I64Regs_and_GPROutgoingArg
977 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even64
978 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd -> I64Regs_and_GPROutgoingArg
979 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64
980 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_even
981 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_odd
982 },
983 { // PRRegs_and_ASRRegs
984 0, // PRRegs_and_ASRRegs:sub_even
985 0, // PRRegs_and_ASRRegs:sub_even64
986 0, // PRRegs_and_ASRRegs:sub_odd
987 0, // PRRegs_and_ASRRegs:sub_odd64
988 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_even
989 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_odd
990 },
991 { // QFPRegs
992 4, // QFPRegs:sub_even -> FPRegs
993 8, // QFPRegs:sub_even64 -> DFPRegs
994 4, // QFPRegs:sub_odd -> FPRegs
995 8, // QFPRegs:sub_odd64 -> DFPRegs
996 4, // QFPRegs:sub_odd64_then_sub_even -> FPRegs
997 4, // QFPRegs:sub_odd64_then_sub_odd -> FPRegs
998 },
999 { // LowQFPRegs
1000 4, // LowQFPRegs:sub_even -> FPRegs
1001 13, // LowQFPRegs:sub_even64 -> LowDFPRegs
1002 4, // LowQFPRegs:sub_odd -> FPRegs
1003 13, // LowQFPRegs:sub_odd64 -> LowDFPRegs
1004 4, // LowQFPRegs:sub_odd64_then_sub_even -> FPRegs
1005 4, // LowQFPRegs:sub_odd64_then_sub_odd -> FPRegs
1006 },
1007
1008 };
1009 assert(RC && "Missing regclass");
1010 if (!Idx) return RC;
1011 --Idx;
1012 assert(Idx < 6 && "Bad subreg");
1013 unsigned TV = Table[RC->getID()][Idx];
1014 return TV ? getRegClass(i: TV - 1) : nullptr;
1015}/// Get the weight in units of pressure for this register class.
1016const RegClassWeight &SparcGenRegisterInfo::
1017getRegClassWeight(const TargetRegisterClass *RC) const {
1018 static const RegClassWeight RCWeightTable[] = {
1019 {.RegWeight: 1, .WeightLimit: 4}, // FCCRegs
1020 {.RegWeight: 1, .WeightLimit: 1}, // ASRRegs
1021 {.RegWeight: 0, .WeightLimit: 0}, // CoprocRegs
1022 {.RegWeight: 1, .WeightLimit: 32}, // FPRegs
1023 {.RegWeight: 1, .WeightLimit: 32}, // IntRegs
1024 {.RegWeight: 1, .WeightLimit: 6}, // GPRIncomingArg
1025 {.RegWeight: 1, .WeightLimit: 6}, // GPROutgoingArg
1026 {.RegWeight: 2, .WeightLimit: 64}, // DFPRegs
1027 {.RegWeight: 1, .WeightLimit: 32}, // I64Regs
1028 {.RegWeight: 1, .WeightLimit: 17}, // PRRegs
1029 {.RegWeight: 0, .WeightLimit: 0}, // CoprocPair
1030 {.RegWeight: 2, .WeightLimit: 32}, // IntPair
1031 {.RegWeight: 2, .WeightLimit: 32}, // LowDFPRegs
1032 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPRIncomingArg
1033 {.RegWeight: 1, .WeightLimit: 6}, // I64Regs_and_GPROutgoingArg
1034 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPRIncomingArg
1035 {.RegWeight: 2, .WeightLimit: 6}, // IntPair_with_sub_even_in_GPROutgoingArg
1036 {.RegWeight: 1, .WeightLimit: 1}, // PRRegs_and_ASRRegs
1037 {.RegWeight: 4, .WeightLimit: 64}, // QFPRegs
1038 {.RegWeight: 4, .WeightLimit: 32}, // LowQFPRegs
1039 };
1040 return RCWeightTable[RC->getID()];
1041}
1042
1043/// Get the weight in units of pressure for this register unit.
1044unsigned SparcGenRegisterInfo::
1045getRegUnitWeight(MCRegUnit RegUnit) const {
1046 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
1047 static const uint8_t RUWeightTable[] = {
1048 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
1049 return RUWeightTable[static_cast<unsigned>(RegUnit)];
1050}
1051
1052
1053// Get the number of dimensions of register pressure.
1054unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
1055 return 8;
1056}
1057
1058// Get the name of this register unit pressure set.
1059const char *SparcGenRegisterInfo::
1060getRegPressureSetName(unsigned Idx) const {
1061 static const char *PressureNameTable[] = {
1062 "PRRegs_and_ASRRegs",
1063 "FCCRegs",
1064 "GPRIncomingArg",
1065 "GPROutgoingArg",
1066 "PRRegs",
1067 "FPRegs",
1068 "IntRegs",
1069 "DFPRegs",
1070 };
1071 return PressureNameTable[Idx];
1072}
1073
1074// Get the register unit pressure limit for this dimension.
1075// This limit must be adjusted dynamically for reserved registers.
1076unsigned SparcGenRegisterInfo::
1077getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
1078 static const uint8_t PressureLimitTable[] = {
1079 1, // 0: PRRegs_and_ASRRegs
1080 4, // 1: FCCRegs
1081 6, // 2: GPRIncomingArg
1082 6, // 3: GPROutgoingArg
1083 17, // 4: PRRegs
1084 32, // 5: FPRegs
1085 32, // 6: IntRegs
1086 64, // 7: DFPRegs
1087 };
1088 return PressureLimitTable[Idx];
1089}
1090
1091/// Table of pressure sets per register class or unit.
1092static const int RCSetsTable[] = {
1093 /* 0 */ 1, -1,
1094 /* 2 */ 0, 4, -1,
1095 /* 5 */ 2, 6, -1,
1096 /* 8 */ 3, 6, -1,
1097 /* 11 */ 5, 7, -1,
1098};
1099
1100/// Get the dimensions of register pressure impacted by this register class.
1101/// Returns a -1 terminated array of pressure set IDs
1102const int *SparcGenRegisterInfo::
1103getRegClassPressureSets(const TargetRegisterClass *RC) const {
1104 static const uint8_t RCSetStartTable[] = {
1105 0,1,1,11,6,5,8,12,6,3,1,6,11,5,8,5,8,2,12,11,};
1106 return &RCSetsTable[RCSetStartTable[RC->getID()]];
1107}
1108
1109/// Get the dimensions of register pressure impacted by this register unit.
1110/// Returns a -1 terminated array of pressure set IDs
1111const int *SparcGenRegisterInfo::
1112getRegUnitPressureSets(MCRegUnit RegUnit) const {
1113 assert(static_cast<unsigned>(RegUnit) < 173 && "invalid register unit");
1114 static const uint8_t RUSetStartTable[] = {
1115 3,3,3,1,1,3,1,1,3,1,3,3,1,3,3,1,2,3,3,3,3,3,3,1,3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,0,0,0,0,6,6,6,6,6,6,6,6,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,8,8,8,8,8,8,6,6,};
1116 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
1117}
1118
1119extern const MCRegisterDesc SparcRegDesc[];
1120extern const int16_t SparcRegDiffLists[];
1121extern const LaneBitmask SparcLaneMaskLists[];
1122extern const char SparcRegStrings[];
1123extern const char SparcRegClassStrings[];
1124extern const MCPhysReg SparcRegUnitRoots[][2];
1125extern const uint16_t SparcSubRegIdxLists[];
1126extern const uint16_t SparcRegEncodingTable[];
1127// SP Dwarf<->LLVM register mappings.
1128extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
1129extern const unsigned SPDwarfFlavour0Dwarf2LSize;
1130
1131extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
1132extern const unsigned SPEHFlavour0Dwarf2LSize;
1133
1134extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
1135extern const unsigned SPDwarfFlavour0L2DwarfSize;
1136
1137extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
1138extern const unsigned SPEHFlavour0L2DwarfSize;
1139
1140
1141SparcGenRegisterInfo::
1142SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
1143 unsigned PC, unsigned HwMode)
1144 : TargetRegisterInfo(&SparcRegInfoDesc, RegisterClasses, RegisterClasses+20,
1145 SparcSubRegIndexStrings, SparcSubRegIndexNameOffsets,
1146 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
1147
1148 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
1149 InitMCRegisterInfo(D: SparcRegDesc, NR: 238, RA, PC,
1150 C: SparcMCRegisterClasses, NC: 20,
1151 RURoots: SparcRegUnitRoots,
1152 NRU: 173,
1153 DL: SparcRegDiffLists,
1154 RUMS: SparcLaneMaskLists,
1155 Strings: SparcRegStrings,
1156 ClassStrings: SparcRegClassStrings,
1157 SubIndices: SparcSubRegIdxLists,
1158 NumIndices: 7,
1159 RET: SparcRegEncodingTable,
1160 RUI: nullptr);
1161
1162 switch (DwarfFlavour) {
1163 default:
1164 llvm_unreachable("Unknown DWARF flavour");
1165 case 0:
1166 mapDwarfRegsToLLVMRegs(Map: SPDwarfFlavour0Dwarf2L, Size: SPDwarfFlavour0Dwarf2LSize, isEH: false);
1167 break;
1168 }
1169 switch (EHFlavour) {
1170 default:
1171 llvm_unreachable("Unknown DWARF flavour");
1172 case 0:
1173 mapDwarfRegsToLLVMRegs(Map: SPEHFlavour0Dwarf2L, Size: SPEHFlavour0Dwarf2LSize, isEH: true);
1174 break;
1175 }
1176 switch (DwarfFlavour) {
1177 default:
1178 llvm_unreachable("Unknown DWARF flavour");
1179 case 0:
1180 mapLLVMRegsToDwarfRegs(Map: SPDwarfFlavour0L2Dwarf, Size: SPDwarfFlavour0L2DwarfSize, isEH: false);
1181 break;
1182 }
1183 switch (EHFlavour) {
1184 default:
1185 llvm_unreachable("Unknown DWARF flavour");
1186 case 0:
1187 mapLLVMRegsToDwarfRegs(Map: SPEHFlavour0L2Dwarf, Size: SPEHFlavour0L2DwarfSize, isEH: true);
1188 break;
1189 }
1190}
1191
1192static const MCPhysReg CSR_SaveList[] = { 0 };
1193static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x103fffc0, 0x00000000, 0x000003fc, };
1194static const MCPhysReg RTCSR_SaveList[] = { 0 };
1195static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00003000, 0x00000000, 0x00000020, };
1196
1197
1198ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
1199 static const uint32_t *const Masks[] = {
1200 CSR_RegMask,
1201 RTCSR_RegMask,
1202 };
1203 return ArrayRef(Masks);
1204}
1205
1206bool SparcGenRegisterInfo::
1207isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1208 return
1209 false;
1210}
1211
1212bool SparcGenRegisterInfo::
1213isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
1214 return
1215 false;
1216}
1217
1218bool SparcGenRegisterInfo::
1219isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1220 return
1221 false;
1222}
1223
1224bool SparcGenRegisterInfo::
1225isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
1226 return
1227 false;
1228}
1229
1230bool SparcGenRegisterInfo::
1231isConstantPhysReg(MCRegister PhysReg) const {
1232 return
1233 PhysReg == SP::G0 ||
1234 false;
1235}
1236
1237ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
1238 static const char *Names[] = {
1239 "CSR",
1240 "RTCSR",
1241 };
1242 return ArrayRef(Names);
1243}
1244
1245const SparcFrameLowering *
1246SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1247 return static_cast<const SparcFrameLowering *>(
1248 MF.getSubtarget().getFrameLowering());
1249}
1250
1251
1252} // namespace llvm
1253