1//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the SPARC implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SparcRegisterInfo.h"
14#include "Sparc.h"
15#include "SparcSubtarget.h"
16#include "llvm/ADT/BitVector.h"
17#include "llvm/CodeGen/MachineFrameInfo.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21#include "llvm/IR/Type.h"
22#include "llvm/Support/ErrorHandling.h"
23
24using namespace llvm;
25
26#define GET_REGINFO_TARGET_DESC
27#include "SparcGenRegisterInfo.inc"
28
29SparcRegisterInfo::SparcRegisterInfo(const SparcSubtarget &STI)
30 : SparcGenRegisterInfo(SP::O7), Is64Bit(STI.is64Bit()) {}
31
32const MCPhysReg*
33SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
34 return CSR_SaveList;
35}
36
37const uint32_t *
38SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
39 CallingConv::ID CC) const {
40 return CSR_RegMask;
41}
42
43const uint32_t*
44SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
45 return RTCSR_RegMask;
46}
47
48BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
49 BitVector Reserved(getNumRegs());
50 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
51 // FIXME: G1 reserved for now for large imm generation by frame code.
52 Reserved.set(SP::G1);
53
54 // G1-G4 can be used in applications.
55 if (Subtarget.getCLOpts().reserve_app_registers) {
56 Reserved.set(SP::G2);
57 Reserved.set(SP::G3);
58 Reserved.set(SP::G4);
59 }
60 // G5 is not reserved in 64 bit mode.
61 if (!Subtarget.is64Bit())
62 Reserved.set(SP::G5);
63
64 Reserved.set(SP::O6);
65 Reserved.set(SP::I6);
66 Reserved.set(SP::I7);
67 Reserved.set(SP::G0);
68 Reserved.set(SP::G6);
69 Reserved.set(SP::G7);
70
71 // Also reserve the register pair aliases covering the above
72 // registers, with the same conditions.
73 Reserved.set(SP::G0_G1);
74 if (Subtarget.getCLOpts().reserve_app_registers)
75 Reserved.set(SP::G2_G3);
76 if (Subtarget.getCLOpts().reserve_app_registers || !Subtarget.is64Bit())
77 Reserved.set(SP::G4_G5);
78
79 Reserved.set(SP::O6_O7);
80 Reserved.set(SP::I6_I7);
81 Reserved.set(SP::G6_G7);
82
83 // Unaliased double registers are not available in non-V9 targets.
84 if (!Subtarget.isV9()) {
85 for (unsigned n = 0; n != 16; ++n) {
86 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
87 Reserved.set(*AI);
88 }
89 }
90
91 // Reserve ASR1-ASR31
92 for (unsigned n = 0; n < 31; n++)
93 Reserved.set(SP::ASR1 + n);
94
95 for (TargetRegisterClass::iterator i = SP::IntRegsRegClass.begin();
96 i != SP::IntRegsRegClass.end(); ++i) {
97 if (MF.getSubtarget<SparcSubtarget>().isRegisterReserved(PhysReg: *i))
98 markSuperRegs(RegisterSet&: Reserved, Reg: *i);
99 }
100
101 assert(checkAllSuperRegsMarked(Reserved));
102 return Reserved;
103}
104
105bool SparcRegisterInfo::isReservedReg(const MachineFunction &MF,
106 MCRegister Reg) const {
107 return getReservedRegs(MF)[Reg];
108}
109
110static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II,
111 MachineInstr &MI, const DebugLoc &dl,
112 unsigned FIOperandNum, int Offset, unsigned FramePtr) {
113 // Replace frame index with a frame pointer reference.
114 if (Offset >= -4096 && Offset <= 4095) {
115 // If the offset is small enough to fit in the immediate field, directly
116 // encode it.
117 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: FramePtr, isDef: false);
118 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
119 return;
120 }
121
122 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
123
124 // FIXME: it would be better to scavenge a register here instead of
125 // reserving G1 all of the time.
126 if (Offset >= 0) {
127 // Emit nonnegaive immediates with sethi + or.
128 // sethi %hi(Offset), %g1
129 // add %g1, %fp, %g1
130 // Insert G1+%lo(offset) into the user.
131 BuildMI(BB&: *MI.getParent(), I: II, MIMD: dl, MCID: TII.get(Opcode: SP::SETHIi), DestReg: SP::G1)
132 .addImm(Val: HI22(imm: Offset));
133
134
135 // Emit G1 = G1 + I6
136 BuildMI(BB&: *MI.getParent(), I: II, MIMD: dl, MCID: TII.get(Opcode: SP::ADDrr), DestReg: SP::G1).addReg(RegNo: SP::G1)
137 .addReg(RegNo: FramePtr);
138 // Insert: G1+%lo(offset) into the user.
139 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: SP::G1, isDef: false);
140 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: LO10(imm: Offset));
141 return;
142 }
143
144 // Emit Negative numbers with sethi + xor
145 // sethi %hix(Offset), %g1
146 // xor %g1, %lox(offset), %g1
147 // add %g1, %fp, %g1
148 // Insert: G1 + 0 into the user.
149 BuildMI(BB&: *MI.getParent(), I: II, MIMD: dl, MCID: TII.get(Opcode: SP::SETHIi), DestReg: SP::G1)
150 .addImm(Val: HIX22(imm: Offset));
151 BuildMI(BB&: *MI.getParent(), I: II, MIMD: dl, MCID: TII.get(Opcode: SP::XORri), DestReg: SP::G1)
152 .addReg(RegNo: SP::G1).addImm(Val: LOX10(imm: Offset));
153
154 BuildMI(BB&: *MI.getParent(), I: II, MIMD: dl, MCID: TII.get(Opcode: SP::ADDrr), DestReg: SP::G1).addReg(RegNo: SP::G1)
155 .addReg(RegNo: FramePtr);
156 // Insert: G1+%lo(offset) into the user.
157 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: SP::G1, isDef: false);
158 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
159}
160
161
162bool
163SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
164 int SPAdj, unsigned FIOperandNum,
165 RegScavenger *RS) const {
166 assert(SPAdj == 0 && "Unexpected");
167
168 MachineInstr &MI = *II;
169 DebugLoc dl = MI.getDebugLoc();
170 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
171 MachineFunction &MF = *MI.getParent()->getParent();
172 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
173 const SparcFrameLowering *TFI = getFrameLowering(MF);
174
175 Register FrameReg;
176 int Offset;
177 Offset = TFI->getFrameIndexReference(MF, FI: FrameIndex, FrameReg).getFixed();
178
179 Offset += MI.getOperand(i: FIOperandNum + 1).getImm();
180
181 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
182 if (MI.getOpcode() == SP::STQFri) {
183 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
184 Register SrcReg = MI.getOperand(i: 2).getReg();
185 Register SrcEvenReg = getSubReg(Reg: SrcReg, Idx: SP::sub_even64);
186 Register SrcOddReg = getSubReg(Reg: SrcReg, Idx: SP::sub_odd64);
187 MachineInstr *StMI =
188 BuildMI(BB&: *MI.getParent(), I: II, MIMD: dl, MCID: TII.get(Opcode: SP::STDFri))
189 .addReg(RegNo: FrameReg).addImm(Val: 0).addReg(RegNo: SrcEvenReg);
190 replaceFI(MF, II: *StMI, MI&: *StMI, dl, FIOperandNum: 0, Offset, FramePtr: FrameReg);
191 MI.setDesc(TII.get(Opcode: SP::STDFri));
192 MI.getOperand(i: 2).setReg(SrcOddReg);
193 Offset += 8;
194 } else if (MI.getOpcode() == SP::LDQFri) {
195 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
196 Register DestReg = MI.getOperand(i: 0).getReg();
197 Register DestEvenReg = getSubReg(Reg: DestReg, Idx: SP::sub_even64);
198 Register DestOddReg = getSubReg(Reg: DestReg, Idx: SP::sub_odd64);
199 MachineInstr *LdMI =
200 BuildMI(BB&: *MI.getParent(), I: II, MIMD: dl, MCID: TII.get(Opcode: SP::LDDFri), DestReg: DestEvenReg)
201 .addReg(RegNo: FrameReg).addImm(Val: 0);
202 replaceFI(MF, II: *LdMI, MI&: *LdMI, dl, FIOperandNum: 1, Offset, FramePtr: FrameReg);
203
204 MI.setDesc(TII.get(Opcode: SP::LDDFri));
205 MI.getOperand(i: 0).setReg(DestOddReg);
206 Offset += 8;
207 }
208 }
209
210 replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr: FrameReg);
211 // replaceFI never removes II
212 return false;
213}
214
215Register SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
216 return SP::I6;
217}
218